[PATCH v3] arm64: defconfig: Enable GPIO and I2C configs for TI's J721e platform
Add configs to enable regulators that supply power to the SD card on TI's J721e platform. These regulators are controlled by either SoC gpios or gpios over i2c expander. Changes to vmlinux size: Before: text data bss dec hex filename 20219067 10875634 523924 31618625 1e27641 vmlinux After: text data bssdec hex filename 20228755 10880422 524628 31633805 1e2b18d vmlinux delta: 15180 (dec) Acked-by: Tero Kristo Signed-off-by: Faiz Abbas --- Changes in v3: Added changes to vmlinux size in commit message Changes in v2: Squashed changes into a single patch v2: https://lore.kernel.org/linux-arm-kernel/20201102183005.14174-1-faiz_ab...@ti.com/ v1: https://lore.kernel.org/linux-arm-kernel/20201002164535.9920-1-faiz_ab...@ti.com/ arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5cfe3cf6f2ac..bbf42faaddfe 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -438,6 +438,7 @@ CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OMAP=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_CCI=m @@ -497,6 +498,7 @@ CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MPC8XXX=y -- 2.17.1
[PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain
There are 4 instances of gpio modules in main domain:
gpio0, gpio2, gpio4 and gpio6
Groups are created to provide protection between different processor virtual
worlds. Each of these modules I/O pins are muxed within the group. Exactly
one module can be selected to control the corresponding pin by selecting it
in the pad mux configuration registers.
This group pins out 69 lines (5 banks).
Add DT modes for each module instance in the main domain.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 68 +++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 72d6496e88dd..c22ef2efa531 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -446,4 +446,72 @@
dr_mode = "otg";
};
};
+
+ main_gpio0: gpio@60 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0060 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <145>, <146>, <147>, <148>,
+<149>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio2: gpio@61 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0061 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <154>, <155>, <156>, <157>,
+<158>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio4: gpio@62 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0062 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <163>, <164>, <165>, <166>,
+<167>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 109 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio6: gpio@63 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0063 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <172>, <173>, <174>, <175>,
+<176>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 111 0>;
+ clock-names = "gpio";
+ };
};
--
2.17.1
[PATCH 0/3] Add gpio support for TI's J7200 platform
The following patches add gpio support for TI's J7200 platform. These patches were posted as a part of an older series but have now been split into three parts. The 3 parts add configs, gpios and MMC/SD related dts patches respectively. Older series is here: https://lore.kernel.org/linux-arm-kernel/20201001190541.6364-1-faiz_ab...@ti.com/ Series adding configs to arm64 defconfig is here: https://lore.kernel.org/linux-arm-kernel/20201102183005.14174-1-faiz_ab...@ti.com/ Faiz Abbas (3): arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules .../dts/ti/k3-j7200-common-proc-board.dts | 16 + arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 68 +++ .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 32 + 3 files changed, 116 insertions(+) -- 2.17.1
[PATCH 2/3] arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain
Similar to the gpio groups in main domain, there is one gpio group in
wakeup domain with 2 mdoules instances in it. The gpio group pins out
73 pins (5 banks). Add DT nodes for these 2 gpio module instances.
Signed-off-by: Faiz Abbas
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 32 +++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index eb2a78a53512..5ee64d4ee41f 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -107,6 +107,38 @@
ti,interrupt-ranges = <16 960 16>;
};
+ wkup_gpio0: gpio@4211 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x4211 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <73>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 113 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_gpio1: gpio@4210 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x4210 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <73>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "gpio";
+ };
+
mcu_navss: bus@2838 {
compatible = "simple-mfd";
#address-cells = <2>;
--
2.17.1
[PATCH 3/3] arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules
There are 6 gpio instances inside SoC with 2 groups as show below:
Group one: wkup_gpio0, wkup_gpio1
Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6
Only one instance from each group can be used at a time. So use main_gpio0
and wkup_gpio0 in current linux context and disable the rest of the nodes.
Signed-off-by: Faiz Abbas
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index ef03e7636b66..0bc4170225d5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -127,6 +127,22 @@
status = "disabled";
};
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
--
2.17.1
[PATCH v2] arm64: defconfig: Enable GPIO and I2C configs for TI's J721e platform
Add configs to help enable regulators that supply power to the SD card on TI's J721e platform. These regulators are controlled by either SoC gpios or gpios over i2c expander. Acked-by: Tero Kristo Signed-off-by: Faiz Abbas --- Changes in v2: Squashed changes into a single patch v1: https://lore.kernel.org/linux-arm-kernel/20201002164535.9920-1-faiz_ab...@ti.com/ arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5cfe3cf6f2ac..bbf42faaddfe 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -438,6 +438,7 @@ CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OMAP=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_CCI=m @@ -497,6 +498,7 @@ CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MPC8XXX=y -- 2.17.1
[PATCH] mmc: sdhci_am654: Fix module autoload
Add a MODULE_DEVICE_TABLE() entry so that the driver is autoloaded
when built as a module.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 2bce962bf7e4..a64ea143d185 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -739,6 +739,7 @@ static const struct of_device_id sdhci_am654_of_match[] = {
},
{ /* sentinel */ }
};
+MODULE_DEVICE_TABLE(of, sdhci_am654_of_match);
static int sdhci_am654_probe(struct platform_device *pdev)
{
--
2.17.1
Re: [PATCH 0/2] Enable GPIO and I2C configs for TI's J721e platform
Tero, On 08/10/20 2:49 pm, Tero Kristo wrote: > On 08/10/2020 11:59, Faiz Abbas wrote: >> Tero, >> >> On 06/10/20 6:40 pm, Tero Kristo wrote: >>> On 06/10/2020 16:03, Faiz Abbas wrote: >>>> Hi Tero, >>>> >>>> On 06/10/20 5:21 pm, Tero Kristo wrote: >>>>> On 02/10/2020 19:45, Faiz Abbas wrote: >>>>>> The following patches enable configs in the arm64 defconfig to support >>>>>> GPIO and I2C support on TI's J721e platform. >>>>>> >>>>>> Faiz Abbas (2): >>>>>> arm64: defconfig: Enable OMAP I2C driver >>>>>> arm64: defconfig: Enable DAVINCI_GPIO driver >>>>>> >>>>>> arch/arm64/configs/defconfig | 2 ++ >>>>>> 1 file changed, 2 insertions(+) >>>>>> >>>>> >>>>> Why are you enabling these? >>>>> >>>>> Are they required for booting the board? >>>>> >>>>> If not, they shall not be enabled, as it just clutters the arm64 >>>>> defconfig unnecessarily. >>>>> >>>> >>>> They are required because the SD card regulators need gpio over i2c >>>> expander and also >>>> soc gpio support to come up in UHS modes. >>> >>> Is that needed for boot support? If it is only needed with UHS cards, that >>> does not seem important enough for me. We can already boot the board via >>> other means. >> >> Without these configs, the regulator drivers keep EPROBE_DEFERing waiting >> for their gpio drivers >> to probe and SD card never comes up. This configuration happens before any >> UHS capabilities are detected. >> >> [ 1.326654] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc >> ret:-517 >> [ 1.333651] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc >> ret:-517 >> [ 1.340693] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 >> [ 1.489088] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc >> ret:-517 >> [ 1.496067] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc >> ret:-517 >> [ 1.510392] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 >> [ 1.543210] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc >> ret:-517 >> [ 1.550186] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc >> ret:-517 >> [ 1.568134] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 > > This happens because you have merged/enabled UHS support or? This sounds like > a regression as I haven't seen this happen before. > Thats right. The EPROBE_DEFERs will happen if my patches enabling UHS modes here are merged. I need to repost them for v5.11-rc1: https://lore.kernel.org/linux-arm-kernel/20201001190541.6364-1-faiz_ab...@ti.com/ Thanks, Faiz
Re: [PATCH 0/2] Enable GPIO and I2C configs for TI's J721e platform
Tero, On 06/10/20 6:40 pm, Tero Kristo wrote: > On 06/10/2020 16:03, Faiz Abbas wrote: >> Hi Tero, >> >> On 06/10/20 5:21 pm, Tero Kristo wrote: >>> On 02/10/2020 19:45, Faiz Abbas wrote: >>>> The following patches enable configs in the arm64 defconfig to support >>>> GPIO and I2C support on TI's J721e platform. >>>> >>>> Faiz Abbas (2): >>>> arm64: defconfig: Enable OMAP I2C driver >>>> arm64: defconfig: Enable DAVINCI_GPIO driver >>>> >>>> arch/arm64/configs/defconfig | 2 ++ >>>> 1 file changed, 2 insertions(+) >>>> >>> >>> Why are you enabling these? >>> >>> Are they required for booting the board? >>> >>> If not, they shall not be enabled, as it just clutters the arm64 defconfig >>> unnecessarily. >>> >> >> They are required because the SD card regulators need gpio over i2c expander >> and also >> soc gpio support to come up in UHS modes. > > Is that needed for boot support? If it is only needed with UHS cards, that > does not seem important enough for me. We can already boot the board via > other means. Without these configs, the regulator drivers keep EPROBE_DEFERing waiting for their gpio drivers to probe and SD card never comes up. This configuration happens before any UHS capabilities are detected. [1.326654] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc ret:-517 [1.333651] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc ret:-517 [1.340693] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 [1.489088] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc ret:-517 [1.496067] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc ret:-517 [1.510392] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 [1.543210] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vmmc ret:-517 [1.550186] sdhci-am654 4fb.sdhci: _devm_regulator_get id:vqmmc ret:-517 [1.568134] sdhci-am654 4fb.sdhci: sdhci_am654_probe ret:-517 Thanks, Faiz
Re: [PATCH 0/2] Enable GPIO and I2C configs for TI's J721e platform
Hi Tero, On 06/10/20 5:21 pm, Tero Kristo wrote: > On 02/10/2020 19:45, Faiz Abbas wrote: >> The following patches enable configs in the arm64 defconfig to support >> GPIO and I2C support on TI's J721e platform. >> >> Faiz Abbas (2): >> arm64: defconfig: Enable OMAP I2C driver >> arm64: defconfig: Enable DAVINCI_GPIO driver >> >> arch/arm64/configs/defconfig | 2 ++ >> 1 file changed, 2 insertions(+) >> > > Why are you enabling these? > > Are they required for booting the board? > > If not, they shall not be enabled, as it just clutters the arm64 defconfig > unnecessarily. > They are required because the SD card regulators need gpio over i2c expander and also soc gpio support to come up in UHS modes. But in general isn't any feature we add supposed to be enabled in the arm64 defconfig? Thanks, Faiz
Re: [PATCH 0/2] Enable GPIO and I2C configs for TI's J721e platform
Nishanth, On 02/10/20 10:32 pm, Nishanth Menon wrote: > On 22:15-20201002, Faiz Abbas wrote: >> The following patches enable configs in the arm64 defconfig to support >> GPIO and I2C support on TI's J721e platform. >> >> Faiz Abbas (2): >> arm64: defconfig: Enable OMAP I2C driver >> arm64: defconfig: Enable DAVINCI_GPIO driver >> >> arch/arm64/configs/defconfig | 2 ++ >> 1 file changed, 2 insertions(+) > > > Could we do an audit and make sure nothing else is missing - Say ALSA / > DRM or something else? I'm not aware of anything that might be missing. That said, I am not aware of every single config in every subsystem. IMO the various driver owners should be responsible for adding their configs to defconfig. > > And I don't really see the need to split these into individual patches, > maybe, take a hint from [1] > > > [1] > https://lore.kernel.org/linux-arm-kernel/20200630171500.11438-1-geert+rene...@glider.be/ > Sounds good. I'll squash into a single patch and repost. Thanks, Faiz
[PATCH 0/2] Enable GPIO and I2C configs for TI's J721e platform
The following patches enable configs in the arm64 defconfig to support GPIO and I2C support on TI's J721e platform. Faiz Abbas (2): arm64: defconfig: Enable OMAP I2C driver arm64: defconfig: Enable DAVINCI_GPIO driver arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1
[PATCH 2/2] arm64: defconfig: Enable DAVINCI_GPIO driver
Enable support for devices compatible with TI's davinci gpio controllers. Signed-off-by: Faiz Abbas --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0d5b81264fa1..c4b657644e33 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -497,6 +497,7 @@ CONFIG_PINCTRL_SDM845=y CONFIG_PINCTRL_SM8150=y CONFIG_PINCTRL_SM8250=y CONFIG_GPIO_ALTERA=m +CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_MB86S7X=y CONFIG_GPIO_MPC8XXX=y -- 2.17.1
[PATCH 1/2] arm64: defconfig: Enable OMAP I2C driver
Enable support for devices compatible with TI's OMAP I2C controllers. Signed-off-by: Faiz Abbas --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 55f9c35568bf..0d5b81264fa1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -437,6 +437,7 @@ CONFIG_I2C_IMX=y CONFIG_I2C_IMX_LPI2C=y CONFIG_I2C_MESON=y CONFIG_I2C_MV64XXX=y +CONFIG_I2C_OMAP=y CONFIG_I2C_OWL=y CONFIG_I2C_PXA=y CONFIG_I2C_QCOM_CCI=m -- 2.17.1
Re: [PATCH 0/8] Add support for UHS modes in TI's J721e and J7200 boards
Hi Nishanth, On 02/10/20 6:19 pm, Nishanth Menon wrote: > On 10:14-20201002, Faiz Abbas wrote: >> Hi Nishanth, >> >> On 02/10/20 12:43 am, Nishanth Menon wrote: >>> On 00:35-20201002, Faiz Abbas wrote: >>>> The following patches add support for UHS modes for TI's j721e and j7200 >>>> boards. >>>> >>>> Patches 1-3 add support for gpios to j7200-evm >>>> >>>> Patches 4-6 add support for voltage regulators for required by the >>>> SD card in both devices as well as enable UHS modes at 1.8V >>>> >>>> Patches 5-6 add some required configs to the arm64 defconfig. >>>> >>>> This series depends on driver patches adding tuning support here: >>>> https://lore.kernel.org/linux-arm-kernel/20200923105206.7988-1-faiz_ab...@ti.com/ >>>> >>>> Faiz Abbas (8): >>>> arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain >>>> arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain >>>> arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio >>>> modules >>>> arm64: dts: ti: k3-j721e-main: Add output tap delay values >>>> arm64: dts: ti: k3-j721e-common-proc-board: Add support SD card UHS >>>> modes >>>> arm64: dts: ti: k3-j7200-common-proc-board: Add support SD card UHS >>>> modes >>> >>> Split these up please! >> >> Into SD card UHS and gpio series? >> >>>> arm64: defconfig: Enable OMAP I2C driver >>>> arm64: defconfig: Enable DAVINCI_GPIO driver >>>> >>> >>> defconfig patches can be posted independent of dts patches, they go to >>> different branches. >> >> I was trying to follow Arnd's advice here: >> https://lore.kernel.org/linux-arm-kernel/CAK8P3a1JpCCCV-CVQj3+eMfWF+=4auhppv390tyj2pkn63_...@mail.gmail.com/ >> >> He says that defconfig patches can be sent at the same time as dts updates >> and maintainers can send those >> as separate pull requests. > > BTW, [1] your patches 7/8 and 8/8 never hit the mailing list, So, I am > commenting on the defconfig patches without actually seeing the patches, > and solely based on $subject in the cover letter. This is weird. They are there in my patches/ folder and I always do a "git send-email patches/* ..." Not sure why they didn't get sent. My last send-email command does have all the patches being sent: https://pastebin.ubuntu.com/p/VNWsrMcBZd/ > > The reason for my comment was that I think defconfig series could go > independent of the remaining series into 5.10, since they are not > related specifically to this series, they are probably needed even for > am654 and j721e nodes that already exist and was a miss that we didn't > enable. Tying that to this specific series didn't make sense to me. You're right that they are not tied to the series. > > But either way, we are way past rc7. I don't have enough time for > these patches to bake in -next to make it to 5.10 window. So, lets try > reposting this after rc1 tag is done so that I can send the defconfig > (separately for 5.10 window) and the dts staged towards 5.11 (and no, > I don't consider the dts patches as fixes - they are enabling the next > level of functionality). > Ok. I'll send only the defconfig patches in a new series and repost v2 of this at rc1. Thanks, Fai
Re: [PATCH 0/8] Add support for UHS modes in TI's J721e and J7200 boards
Hi Nishanth, On 02/10/20 12:43 am, Nishanth Menon wrote: > On 00:35-20201002, Faiz Abbas wrote: >> The following patches add support for UHS modes for TI's j721e and j7200 >> boards. >> >> Patches 1-3 add support for gpios to j7200-evm >> >> Patches 4-6 add support for voltage regulators for required by the >> SD card in both devices as well as enable UHS modes at 1.8V >> >> Patches 5-6 add some required configs to the arm64 defconfig. >> >> This series depends on driver patches adding tuning support here: >> https://lore.kernel.org/linux-arm-kernel/20200923105206.7988-1-faiz_ab...@ti.com/ >> >> Faiz Abbas (8): >> arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain >> arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain >> arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio >> modules >> arm64: dts: ti: k3-j721e-main: Add output tap delay values >> arm64: dts: ti: k3-j721e-common-proc-board: Add support SD card UHS >> modes >> arm64: dts: ti: k3-j7200-common-proc-board: Add support SD card UHS >> modes > > Split these up please! Into SD card UHS and gpio series? >> arm64: defconfig: Enable OMAP I2C driver >> arm64: defconfig: Enable DAVINCI_GPIO driver >> > > defconfig patches can be posted independent of dts patches, they go to > different branches. I was trying to follow Arnd's advice here: https://lore.kernel.org/linux-arm-kernel/CAK8P3a1JpCCCV-CVQj3+eMfWF+=4auhppv390tyj2pkn63_...@mail.gmail.com/ He says that defconfig patches can be sent at the same time as dts updates and maintainers can send those as separate pull requests. Thanks, Faiz
[PATCH 0/8] Add support for UHS modes in TI's J721e and J7200 boards
The following patches add support for UHS modes for TI's j721e and j7200 boards. Patches 1-3 add support for gpios to j7200-evm Patches 4-6 add support for voltage regulators for required by the SD card in both devices as well as enable UHS modes at 1.8V Patches 5-6 add some required configs to the arm64 defconfig. This series depends on driver patches adding tuning support here: https://lore.kernel.org/linux-arm-kernel/20200923105206.7988-1-faiz_ab...@ti.com/ Faiz Abbas (8): arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules arm64: dts: ti: k3-j721e-main: Add output tap delay values arm64: dts: ti: k3-j721e-common-proc-board: Add support SD card UHS modes arm64: dts: ti: k3-j7200-common-proc-board: Add support SD card UHS modes arm64: defconfig: Enable OMAP I2C driver arm64: defconfig: Enable DAVINCI_GPIO driver .../dts/ti/k3-j7200-common-proc-board.dts | 48 + arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 69 ++- .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 32 + .../dts/ti/k3-j721e-common-proc-board.dts | 35 +- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 22 -- arch/arm64/configs/defconfig | 2 + 6 files changed, 201 insertions(+), 7 deletions(-) -- 2.17.1
[PATCH 5/8] arm64: dts: ti: k3-j721e-common-proc-board: Add support SD card UHS modes
Add support for UHS modes for the SD card connected at sdhci1. This
involves adding regulators for voltage switching and power cycling the
SD card and removing the no-1-8-v property.
Signed-off-by: Faiz Abbas
---
.../dts/ti/k3-j721e-common-proc-board.dts | 35 ++-
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 --
2 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 52e121155563..0df9e6117b7c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -67,6 +67,31 @@
regulator-boot-on;
};
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ vin-supply = <&vsys_3v3>;
+ gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+ regulator-name = "tlv71033";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ vin-supply = <&vsys_5v0>;
+ gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
+
sound0: sound@0 {
compatible = "ti,j721e-cpb-audio";
model = "j721e-cpb";
@@ -106,7 +131,13 @@
>;
};
- main_usbss0_pins_default: main-usbss0-pins-default {
+ vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4)
SPI1_CS1.GPIO0_117 */
+ >;
+ };
+
+ main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS
*/
J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3)
MCAN1_RX.GPIO1_3 */
@@ -295,6 +326,8 @@
&main_sdhci1 {
/* SD/MMC */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv_alt>;
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 630b195cbc8a..a38d772b8356 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -1109,7 +1109,6 @@
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
- no-1-8-v;
};
main_sdhci2: sdhci@4f98000 {
@@ -1130,7 +1129,6 @@
ti,trm-icp = <0x8>;
ti,clkbuf-sel = <0x7>;
dma-coherent;
- no-1-8-v;
};
usbss0: cdns-usb@4104000 {
--
2.17.1
[PATCH 4/8] arm64: dts: ti: k3-j721e-main: Add output tap delay values
Add output tap delay values as given in the latest Data Manual[1]. [1] https://www.ti.com/lit/gpn/tda4vm Signed-off-by: Faiz Abbas --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index e2a96b2c423c..630b195cbc8a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -1081,7 +1081,11 @@ bus-width = <8>; mmc-hs400-1_8v; mmc-ddr-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0xf>; + ti,otap-del-sel-mmc-hs = <0xf>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x6>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; ti,strobe-sel = <0x77>; dma-coherent; @@ -1096,7 +1100,12 @@ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>; assigned-clocks = <&k3_clks 92 0>; assigned-clock-parents = <&k3_clks 92 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; @@ -1112,7 +1121,12 @@ clocks = <&k3_clks 93 0>, <&k3_clks 93 5>; assigned-clocks = <&k3_clks 93 0>; assigned-clock-parents = <&k3_clks 93 1>; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-sd-hs = <0xf>; + ti,otap-del-sel-sdr12 = <0xf>; + ti,otap-del-sel-sdr25 = <0xf>; + ti,otap-del-sel-sdr50 = <0xc>; + ti,otap-del-sel-ddr50 = <0xc>; ti,trm-icp = <0x8>; ti,clkbuf-sel = <0x7>; dma-coherent; -- 2.17.1
[PATCH 6/8] arm64: dts: ti: k3-j7200-common-proc-board: Add support SD card UHS modes
Add support for UHS modes for the SD card connected at sdhci1. This
involves adding regulators for voltage switching and power cycling the
SD card and removing the no-1-8-v property.
Signed-off-by: Faiz Abbas
---
.../dts/ti/k3-j7200-common-proc-board.dts | 32 +++
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 -
2 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 50d330245a42..02112c2a63e9 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -7,12 +7,36 @@
#include "k3-j7200-som-p0.dtsi"
#include
+#include
/ {
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x0280";
};
+
+ vdd_mmc1: fixedregulator-sd {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_mmc1";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ enable-active-high;
+ gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd_sd_dv";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd_sd_dv_pins_default>;
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
+ states = <180 0x0
+ 330 0x1>;
+ };
};
&wkup_pmx0 {
@@ -68,6 +92,12 @@
J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
>;
};
+
+ vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5)
SPI0_D1.GPIO0_55 */
+ >;
+ };
};
&wkup_uart0 {
@@ -196,6 +226,8 @@
&main_sdhci1 {
/* SD card */
+ vmmc-supply = <&vdd_mmc1>;
+ vqmmc-supply = <&vdd_sd_dv>;
pinctrl-0 = <&main_mmc1_pins_default>;
pinctrl-names = "default";
ti,driver-strength-ohm = <50>;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f21f22237e0f..7307a94f7f3e 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -392,7 +392,6 @@
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
- no-1-8-v;
dma-coherent;
};
--
2.17.1
[PATCH 1/8] arm64: dts: ti: k3-j7200-main: Add gpio nodes in main domain
There are 4 instances of gpio modules in main domain:
gpio0, gpio2, gpio4 and gpio6
Groups are created to provide protection between different processor virtual
worlds. Each of these modules I/O pins are muxed within the group. Exactly
one module can be selected to control the corresponding pin by selecting it
in the pad mux configuration registers.
This group pins out 69 lines (5 banks).
Add DT modes for each module instance in the main domain.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 68 +++
1 file changed, 68 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 4a4fcd24f852..f21f22237e0f 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -395,4 +395,72 @@
no-1-8-v;
dma-coherent;
};
+
+ main_gpio0: gpio@60 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0060 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <145>, <146>, <147>, <148>,
+<149>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 105 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio2: gpio@61 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0061 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <154>, <155>, <156>, <157>,
+<158>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 107 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio4: gpio@62 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0062 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <163>, <164>, <165>, <166>,
+<167>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 109 0>;
+ clock-names = "gpio";
+ };
+
+ main_gpio6: gpio@63 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x0063 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&main_gpio_intr>;
+ interrupts = <172>, <173>, <174>, <175>,
+<176>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <69>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 111 0>;
+ clock-names = "gpio";
+ };
};
--
2.17.1
[PATCH 2/8] arm64: dts: ti: k3-j7200: Add gpio nodes in wakeup domain
Similar to the gpio groups in main domain, there is one gpio group in
wakeup domain with 2 mdoules instances in it. The gpio group pins out
73 pins (5 banks). Add DT nodes for these 2 gpio module instances.
Signed-off-by: Faiz Abbas
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 32 +++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index eb2a78a53512..5ee64d4ee41f 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -107,6 +107,38 @@
ti,interrupt-ranges = <16 960 16>;
};
+ wkup_gpio0: gpio@4211 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x4211 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <73>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 113 0>;
+ clock-names = "gpio";
+ };
+
+ wkup_gpio1: gpio@4210 {
+ compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+ reg = <0x00 0x4210 0x00 0x100>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-parent = <&wkup_gpio_intr>;
+ interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ti,ngpio = <73>;
+ ti,davinci-gpio-unbanked = <0>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 114 0>;
+ clock-names = "gpio";
+ };
+
mcu_navss: bus@2838 {
compatible = "simple-mfd";
#address-cells = <2>;
--
2.17.1
[PATCH 3/8] arm64: dts: ti: k3-j7200-common-proc-board: Disable unused gpio modules
There are 6 gpio instances inside SoC with 2 groups as show below:
Group one: wkup_gpio0, wkup_gpio1
Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6
Only one instance from each group can be used at a time. So use main_gpio0
and wkup_gpio0 in current linux context and disable the rest of the nodes.
Signed-off-by: Faiz Abbas
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 1541311cecb4..50d330245a42 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -120,6 +120,22 @@
status = "disabled";
};
+&main_gpio2 {
+ status = "disabled";
+};
+
+&main_gpio4 {
+ status = "disabled";
+};
+
+&main_gpio6 {
+ status = "disabled";
+};
+
+&wkup_gpio1 {
+ status = "disabled";
+};
+
&mcu_cpsw {
pinctrl-names = "default";
pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
--
2.17.1
[PATCH v2 1/2] arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes
Add support for MMC/SD controller nodes present on TI's j7200 SoCs.
There are two nodes:
1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps)
2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps)
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f44f0b83d12a..e613f5d94281 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -310,4 +310,41 @@
clocks = <&k3_clks 193 1>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
+
+ main_sdhci0: mmc@4f8 {
+ compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
+ reg = <0x00 0x04f8 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
+ interrupts = ;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x0>;
+ ti,strobe-sel = <0x77>;
+ ti,trm-icp = <0x8>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ dma-coherent;
+ };
+
+ main_sdhci1: mmc@4fb {
+ compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
+ reg = <0x00 0x04fb 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
+ interrupts = ;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ no-1-8-v;
+ dma-coherent;
+ };
};
--
2.17.1
[PATCH v2 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1 is connected to the
micro SD slot.
Signed-off-by: Faiz Abbas
---
.../dts/ti/k3-j7200-common-proc-board.dts | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 03c8817e8745..794241ba74cb 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -28,6 +28,19 @@
J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3)
EXT_REFCLK1.I2C1_SDA */
>;
};
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+ >;
+ };
};
&wkup_uart0 {
@@ -112,3 +125,18 @@
#gpio-cells = <2>;
};
};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.17.1
[PATCH v2 0/2] Add support for MMC/SD on j7200-evm
The following patches add dt support for MMC/SD on TI's j7200-evm. Currently, eMMC support upto HS200 speed and SD card supports upto high speed speed mode. v2: Fixed node names to use mmc@* format Fixed reg address format to align with others in the file Faiz Abbas (2): arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card .../dts/ti/k3-j7200-common-proc-board.dts | 28 ++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++ 2 files changed, 65 insertions(+) -- 2.17.1
Re: [PATCH v2 0/2] J7200: Add I2C support
Hi, On 23/09/20 9:23 pm, Vignesh Raghavendra wrote: > Add I2C and I2C IO expanders nodes for J7200 > > v2: > Align reg address format with that of file's (s/0x0/0x00) > > Vignesh Raghavendra (2): > arm64: dts: ti: j7200: Add I2C nodes > arm64: dts: ti: k3-j7200-common-proc-board: Add I2C IO expanders > > .../dts/ti/k3-j7200-common-proc-board.dts | 49 > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 77 +++ > .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 33 > 3 files changed, 159 insertions(+) > Reviewed-by: Faiz Abbas Thanks, Faiz
[PATCH 6/6] mmc: sdhci_am654: Enable tuning for SDR50
According to the SW tuning App note[1], tuning is required for all UHS speed modes. Tuning for SDR50 is not enabled in Capabilities by default so enable it from the CTL_CFG registers. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 5af7638ad606..2bce962bf7e4 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -19,9 +19,11 @@ /* CTL_CFG Registers */ #define CTL_CFG_2 0x14 +#define CTL_CFG_3 0x18 #define SLOTTYPE_MASK GENMASK(31, 30) #define SLOTTYPE_EMBEDDED BIT(30) +#define TUNINGFORSDR50_MASKBIT(13) /* PHY Registers */ #define PHY_CTRL1 0x100 @@ -646,6 +648,10 @@ static int sdhci_am654_init(struct sdhci_host *host) regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2); + /* Enable tuning for SDR50 */ + regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, + TUNINGFORSDR50_MASK); + ret = sdhci_setup_host(host); if (ret) return ret; -- 2.17.1
[PATCH 5/6] mmc: sdhci_am654: Add support for software tuning
With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.
[1] https://www.ti.com/lit/pdf/spract9
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 41 ++
1 file changed, 41 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 1213b711e60a..5af7638ad606 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -396,7 +396,46 @@ static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host,
u32 intmask)
return 0;
}
+#define ITAP_MAX 32
+static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host,
+ u32 opcode)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host);
+ int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+ u32 itap;
+
+ /* Enable ITAPDLY */
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK,
+ 1 << ITAPDLYENA_SHIFT);
+
+ for (itap = 0; itap < ITAP_MAX; itap++) {
+ sdhci_am654_write_itapdly(sdhci_am654, itap);
+
+ cur_val = !mmc_send_tuning(host->mmc, opcode, NULL);
+ if (cur_val && !prev_val)
+ pass_window = itap;
+
+ if (!cur_val)
+ fail_len++;
+
+ prev_val = cur_val;
+ }
+ /*
+* Having determined the length of the failing window and start of
+* the passing window calculate the length of the passing window and
+* set the final value halfway through it considering the range as a
+* circular buffer
+*/
+ pass_len = ITAP_MAX - fail_len;
+ itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+ sdhci_am654_write_itapdly(sdhci_am654, itap);
+
+ return 0;
+}
+
static struct sdhci_ops sdhci_am654_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
@@ -426,6 +465,7 @@ static const struct sdhci_am654_driver_data
sdhci_am654_drvdata = {
};
static struct sdhci_ops sdhci_j721e_8bit_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
@@ -449,6 +489,7 @@ static const struct sdhci_am654_driver_data
sdhci_j721e_8bit_drvdata = {
};
static struct sdhci_ops sdhci_j721e_4bit_ops = {
+ .platform_execute_tuning = sdhci_am654_platform_execute_tuning,
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.set_uhs_signaling = sdhci_set_uhs_signaling,
--
2.17.1
[PATCH 3/6] mmc: sdhci_am654: Fix hard coded otap delay array size
Change hard coded array size value to depend on struct timing_data
array size.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index a4c6d9d80e88..9f3347bc3757 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -85,10 +85,30 @@ static struct regmap_config sdhci_am654_regmap_config = {
.fast_io = true,
};
+struct timing_data {
+ const char *binding;
+ u32 capability;
+};
+
+static const struct timing_data td[] = {
+ [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
+ [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
+ [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
+ [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
+ [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
+ [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
+ [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
+ MMC_CAP_UHS_SDR104},
+ [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
+ [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
+ [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
+ [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
+};
+
struct sdhci_am654_data {
struct regmap *base;
bool legacy_otapdly;
- int otap_del_sel[11];
+ int otap_del_sel[ARRAY_SIZE(td)];
int clkbuf_sel;
int trm_icp;
int drv_strength;
@@ -107,26 +127,6 @@ struct sdhci_am654_driver_data {
#define DLL_CALIB (1 << 4)
};
-struct timing_data {
- const char *binding;
- u32 capability;
-};
-
-static const struct timing_data td[] = {
- [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
- [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
- [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
- [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
- [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
- [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
- MMC_CAP_UHS_SDR104},
- [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
- [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
- [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
- [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
-};
-
static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock)
{
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
--
2.17.1
[PATCH 0/6] Add UHS mode support for TI's AM65x, J721e, J7200 boards
The following are driver and documentation patches to enable UHS modes for TI's AM65x, J721e, and J7200 boards. Device tree and defconfig patches will be sent in a separate series. With the complete set, the following maximum modes will be supported: am654x-evm,idk - SDR104, HS200 j721e-common-proc-board - DDR50, HS200 j7200-common-proc-board - DDR50, HS200 These patches mainly add support for the software tuning algorithm[1] needed for higher speed modes [1] [1] https://www.ti.com/lit/pdf/spract9 Faiz Abbas (6): dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller documentation to json schema dt-bindings: mmc: sdhci-am654: Add documentation for input tap delay mmc: sdhci_am654: Fix hard coded otap delay array size mmc: sdhci_am654: Add support for input tap delay mmc: sdhci_am654: Add support for software tuning mmc: sdhci_am654: Enable tuning for SDR50 .../devicetree/bindings/mmc/sdhci-am654.txt | 65 -- .../devicetree/bindings/mmc/sdhci-am654.yaml | 218 ++ drivers/mmc/host/sdhci_am654.c| 179 ++ 3 files changed, 358 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.txt create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.yaml -- 2.17.1
[PATCH 1/6] dt-bindings: mmc: sdhci-am654: Convert sdhci-am654 controller documentation to json schema
Convert sdhci-am654 documentation to yaml format. The new file
sdhci-am654.yaml will inherit from mmc-controller.yaml.
Signed-off-by: Faiz Abbas
---
.../devicetree/bindings/mmc/sdhci-am654.txt | 65 ---
.../devicetree/bindings/mmc/sdhci-am654.yaml | 175 ++
2 files changed, 175 insertions(+), 65 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.txt
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt
b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt
deleted file mode 100644
index b49cbfdd679f..
--- a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Device Tree Bindings for the SDHCI Controllers present on TI's AM654 SOCs
-
-The bindings follow the mmc[1], clock[2] and interrupt[3] bindings.
-Only deviations are documented here.
-
- [1] Documentation/devicetree/bindings/mmc/mmc.txt
- [2] Documentation/devicetree/bindings/clock/clock-bindings.txt
- [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Required Properties:
- - compatible: should be one of:
- "ti,am654-sdhci-5.1": SDHCI on AM654 device.
- "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device.
- "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device.
- "ti,j7200-sdhci-8bit": 8 bit SDHCI on J7200 device.
- "ti,j7200-sdhci-4bit": 4 bit SDHCI on J7200 device.
- - reg: Must be two entries.
- - The first should be the sdhci register space
- - The second should the subsystem/phy register space
- - clocks: Handles to the clock inputs.
- - clock-names: Tuple including "clk_xin" and "clk_ahb"
- - interrupts: Interrupt specifiers
- Output tap delay for each speed mode:
- - ti,otap-del-sel-legacy
- - ti,otap-del-sel-mmc-hs
- - ti,otap-del-sel-sd-hs
- - ti,otap-del-sel-sdr12
- - ti,otap-del-sel-sdr25
- - ti,otap-del-sel-sdr50
- - ti,otap-del-sel-sdr104
- - ti,otap-del-sel-ddr50
- - ti,otap-del-sel-ddr52
- - ti,otap-del-sel-hs200
- - ti,otap-del-sel-hs400
- These bindings must be provided otherwise the driver will disable the
- corresponding speed mode (i.e. all nodes must provide at least
-legacy)
-
-Optional Properties (Required for ti,am654-sdhci-5.1,
- ti,j721e-sdhci-8bit,
- ti,j7200-sdhci-8bit):
- - ti,trm-icp: DLL trim select
- - ti,driver-strength-ohm: driver strength in ohms.
- Valid values are 33, 40, 50, 66 and 100 ohms.
-Optional Properties:
- - ti,strobe-sel: strobe select delay for HS400 speed mode. Default
value: 0x0.
- - ti,clkbuf-sel: Clock Delay Buffer Select
-
-Example:
-
- sdhci0: sdhci@4f8 {
- compatible = "ti,am654-sdhci-5.1";
- reg = <0x0 0x4f8 0x0 0x260>, <0x0 0x4f9 0x0 0x134>;
- power-domains = <&k3_pds 47>;
- clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
- clock-names = "clk_ahb", "clk_xin";
- interrupts = ;
- sdhci-caps-mask = <0x8007 0x0>;
- mmc-ddr-1_8v;
- ti,otap-del-sel-legacy = <0x0>;
- ti,otap-del-sel-mmc-hs = <0x0>;
- ti,otap-del-sel-ddr52 = <0x5>;
- ti,otap-del-sel-hs200 = <0x5>;
- ti,otap-del-sel-hs400 = <0x0>;
- ti,trm-icp = <0x8>;
- };
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
new file mode 100644
index ..c222e057eca9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
@@ -0,0 +1,175 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#";
+$schema : "http://devicetree.org/meta-schemas/core.yaml#";
+
+title: TI AM654 MMC Controller
+
+maintainers:
+ - Ulf Hansson
+
+allOf:
+ - $ref: mmc-controller.yaml#
+
+properties:
+ compatible:
+enum:
+ - ti,am654-sdhci-5.1
+ - ti,j721e-sdhci-8bit
+ - ti,j721e-sdhci-4bit
+ - ti,j7200-sdhci-8bit
+ - ti,j721e-sdhci-4bit
+
+ reg:
+maxItems: 2
+
+ interrupts:
+maxItems: 1
+
+ power-domains:
+maxItems: 1
+
+ clocks:
+minItems: 1
+maxItems: 2
+description: Handles to input clocks
+
+ clock-names:
+minItems: 1
+maxItems: 2
+items
[PATCH 4/6] mmc: sdhci_am654: Add support for input tap delay
DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.
With this addition, make sure that DLL is always switched off at the
beginning of the set_clock() call to simplify configuration. This also
removes the need for the dll_on member in struct sdhci_am654_data.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 114 -
1 file changed, 84 insertions(+), 30 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 9f3347bc3757..1213b711e60a 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -66,6 +66,14 @@
#define RETRIM_MASKBIT(RETRIM_SHIFT)
#define SELDLYTXCLK_SHIFT 17
#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
+#define SELDLYRXCLK_SHIFT 16
+#define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT)
+#define ITAPDLYSEL_SHIFT 0
+#define ITAPDLYSEL_MASKGENMASK(4, 0)
+#define ITAPDLYENA_SHIFT 8
+#define ITAPDLYENA_MASKBIT(ITAPDLYENA_SHIFT)
+#define ITAPCHGWIN_SHIFT 9
+#define ITAPCHGWIN_MASKBIT(ITAPCHGWIN_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1
@@ -73,7 +81,7 @@
#define DRIVER_STRENGTH_100_OHM0x3
#define DRIVER_STRENGTH_40_OHM 0x4
-#define CLOCK_TOO_SLOW_HZ 40
+#define CLOCK_TOO_SLOW_HZ 5000
/* Command Queue Host Controller Interface Base address */
#define SDHCI_AM654_CQE_BASE_ADDR 0x200
@@ -86,33 +94,55 @@ static struct regmap_config sdhci_am654_regmap_config = {
};
struct timing_data {
- const char *binding;
+ const char *otap_binding;
+ const char *itap_binding;
u32 capability;
};
static const struct timing_data td[] = {
- [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0},
- [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED},
- [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED},
- [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12},
- [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25},
- [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50},
- [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
+ [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
+ "ti,itap-del-sel-legacy",
+ 0},
+ [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
+ "ti,itap-del-sel-mmc-hs",
+ MMC_CAP_MMC_HIGHSPEED},
+ [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
+ "ti,itap-del-sel-sd-hs",
+ MMC_CAP_SD_HIGHSPEED},
+ [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
+ "ti,itap-del-sel-sdr12",
+ MMC_CAP_UHS_SDR12},
+ [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
+ "ti,itap-del-sel-sdr25",
+ MMC_CAP_UHS_SDR25},
+ [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
+ NULL,
+ MMC_CAP_UHS_SDR50},
+ [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
+ NULL,
MMC_CAP_UHS_SDR104},
- [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50},
- [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR},
- [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200},
- [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400},
+ [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
+ NULL,
+ MMC_CAP_UHS_DDR50},
+ [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
+ "ti,itap-del-sel-ddr52",
+ MMC_CAP_DDR},
+ [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
+ NULL,
+ MMC_CAP2_HS200},
+ [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
+ NULL,
+ MMC_CAP2_HS400},
};
struct sdhci_am654_data {
struct regmap
[PATCH 2/6] dt-bindings: mmc: sdhci-am654: Add documentation for input tap delay
Add documentation for input tap delay bindings. Signed-off-by: Faiz Abbas --- .../devicetree/bindings/mmc/sdhci-am654.yaml | 43 +++ 1 file changed, 43 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml index c222e057eca9..ac79f3adf20b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml @@ -114,6 +114,46 @@ properties: minimum: 0 maximum: 0xf + # PHY input tap delays: + # Used to delay the data valid window and align it to the sampling clock for + # modes that don't support tuning + + ti,itap-del-sel-legacy: +description: Input tap delay for SD/MMC legacy timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + + ti,itap-del-sel-mmc-hs: +description: Input tap delay for MMC high speed timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + + ti,itap-del-sel-sd-hs: +description: Input tap delay for SD high speed timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + + ti,itap-del-sel-sdr12: +description: Input tap delay for SD UHS SDR12 timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + + ti,itap-del-sel-sdr25: +description: Input tap delay for SD UHS SDR25 timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + + ti,itap-del-sel-ddr52: +description: Input tap delay for MMC DDR52 timing +$ref: "/schemas/types.yaml#/definitions/uint32" +minimum: 0 +maximum: 0x1f + ti,trm-icp: description: DLL trim select $ref: "/schemas/types.yaml#/definitions/uint32" @@ -170,6 +210,9 @@ examples: ti,otap-del-sel-ddr52 = <0x5>; ti,otap-del-sel-hs200 = <0x5>; ti,otap-del-sel-hs400 = <0x0>; +ti,itap-del-sel-legacy = <0x10>; +ti,itap-del-sel-mmc-hs = <0xa>; +ti,itap-del-sel-ddr52 = <0x3>; ti,trm-icp = <0x8>; }; }; -- 2.17.1
[PATCH 0/2] Add support for MMC/SD on j7200-evm
The following patches add dt support for MMC/SD on TI's j7200-evm. Currently, eMMC support upto HS200 speed and SD card supports upto high speed speed mode. These patches depend on: Lokesh's initial support series https://patchwork.kernel.org/cover/11740039/ Vignesh's I2C support series https://lore.kernel.org/patchwork/cover/1282152/ Vignesh's Hyperflash series https://lore.kernel.org/patchwork/cover/1285326/ Faiz Abbas (2): arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card .../dts/ti/k3-j7200-common-proc-board.dts | 30 +++ arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++ 2 files changed, 67 insertions(+) -- 2.17.1
[PATCH 1/2] arm64: dts: ti: k3-j7200-main: Add support for MMC/SD controller nodes
Add support for MMC/SD controller nodes present on TI's j7200 SoCs.
There are two nodes:
1. sdhci0 (8 bit bus width, 200 MHz, HS200, 200 MBps)
2. sdhci1 (4 bit bus width, 50 MHz, HS, 25 MBps)
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 37 +++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 0a87fa3ea5f0..1702ac0bbf40 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -273,4 +273,41 @@
clocks = <&k3_clks 193 1>;
power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
};
+
+ main_sdhci0: sdhci@4f8 {
+ compatible = "ti,j7200-sdhci-8bit", "ti,j721e-sdhci-8bit";
+ reg = <0x0 0x04f8 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
+ interrupts = ;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-ddr52 = <0x6>;
+ ti,otap-del-sel-hs200 = <0x8>;
+ ti,otap-del-sel-hs400 = <0x0>;
+ ti,strobe-sel = <0x77>;
+ ti,trm-icp = <0x8>;
+ bus-width = <8>;
+ mmc-ddr-1_8v;
+ dma-coherent;
+ };
+
+ main_sdhci1: sdhci@4fb {
+ compatible = "ti,j7200-sdhci-4bit", "ti,j721e-sdhci-4bit";
+ reg = <0x0 0x04fb 0x0 0x260>, <0x0 0x4fb8000 0x0 0x134>;
+ interrupts = ;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0xf>;
+ ti,otap-del-sel-sdr25 = <0xf>;
+ ti,otap-del-sel-sdr50 = <0xc>;
+ ti,otap-del-sel-sdr104 = <0x5>;
+ ti,otap-del-sel-ddr50 = <0xc>;
+ no-1-8-v;
+ dma-coherent;
+ };
};
--
2.17.1
[PATCH 2/2] arm64: dts: ti: k3-j7200-common-proc-board: Add support for eMMC and SD card
Add support for the eMMC and SD card connected on the common
processor board
sdhci0 is connected to an eMMC while sdhci1 is connected to the
micro SD slot.
Signed-off-by: Faiz Abbas
---
.../dts/ti/k3-j7200-common-proc-board.dts | 28 +++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 26ad2e46009e..8e534ef8a3f5 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -28,6 +28,19 @@
J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3)
EXT_REFCLK1.I2C1_SDA */
>;
};
+
+ main_mmc1_pins_default: main-mmc1-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+ J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
+ >;
+ };
};
&wkup_uart0 {
@@ -111,3 +124,18 @@
#gpio-cells = <2>;
};
};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD card */
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ pinctrl-names = "default";
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
--
2.17.1
[PATCH v2] mmc: sdhci_am654: Add workaround for card detect debounce timer
There is a one time delay because of a card detect debounce timer in the
controller IP. This timer runs as soon as power is applied to the module
regardless of whether a card is present or not and any writes to
SDHCI_POWER_ON will return 0 before it expires. This timeout has been
measured to be about 1 second in am654x and j721e.
Write-and-read-back in a loop on SDHCI_POWER_ON for a maximum of
1.5 seconds to make sure that the controller actually powers on.
Signed-off-by: Faiz Abbas
---
v2: Use read_poll_timeout() standard macro
drivers/mmc/host/sdhci_am654.c | 24
1 file changed, 24 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index f9d24af12396..9a048c80dad4 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -6,6 +6,7 @@
*
*/
#include
+#include
#include
#include
#include
@@ -272,9 +273,19 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host
*host,
sdhci_set_clock(host, clock);
}
+static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg)
+{
+ writeb(val, host->ioaddr + reg);
+ usleep_range(1000, 1);
+ return readb(host->ioaddr + reg);
+}
+
+#define MAX_POWER_ON_TIMEOUT 150 /* us */
static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
{
unsigned char timing = host->mmc->ios.timing;
+ u8 pwr;
+ int ret;
if (reg == SDHCI_HOST_CONTROL) {
switch (timing) {
@@ -291,6 +302,19 @@ static void sdhci_am654_write_b(struct sdhci_host *host,
u8 val, int reg)
}
writeb(val, host->ioaddr + reg);
+ if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
+ /*
+* Power on will not happen until the card detect debounce
+* timer expires. Wait at least 1.5 seconds for the power on
+* bit to be set
+*/
+ ret = read_poll_timeout(sdhci_am654_write_power_on, pwr,
+ pwr & SDHCI_POWER_ON, 0,
+ MAX_POWER_ON_TIMEOUT, false, host, val,
+ reg);
+ if (ret)
+ dev_warn(mmc_dev(host->mmc), "Power on failed\n");
+ }
}
static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
--
2.17.1
[PATCH v2] can: m_can: Set device to software init mode before closing
There might be some requests pending in the buffer when the interface close sequence occurs. In some devices, these pending requests might lead to the module not shutting down properly when m_can_clk_stop() is called. Therefore, move the device to init state before potentially powering it down. Signed-off-by: Faiz Abbas --- changes since v1: Rebased to latest mainline drivers/net/can/m_can/m_can.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 02c5795b7393..d0c458f7f6e1 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1414,6 +1414,9 @@ static void m_can_stop(struct net_device *dev) /* disable all interrupts */ m_can_disable_all_interrupts(cdev); + /* Set init mode to disengage from the network */ + m_can_config_endisable(cdev, true); + /* set the state as STOPPED */ cdev->can.state = CAN_STATE_STOPPED; } -- 2.17.1
Re: [PATCH] dt-bindings: mmc: sdhci-am654: Document bindings for the host controllers on TI's J7200 devices
Hi Ulf, On 18/08/20 2:47 am, Rob Herring wrote: > On Sun, 02 Aug 2020 12:31:14 +0530, Faiz Abbas wrote: >> Add binding documentation for mmc host controllers present on >> TI's J7200 SOC >> >> Signed-off-by: Faiz Abbas >> --- >> Documentation/devicetree/bindings/mmc/sdhci-am654.txt | 6 +- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> > > Acked-by: Rob Herring > Can you pick this up now or should I rebase to latest? Thanks, Faiz
Re: [PATCH] mmc: sdhci_am654: Add workaround for card detect debounce timer
Re: [PATCH] mmc: sdhci_am654: Add workaround for card detect debounce timer
Hi Adrian,
On 05/08/20 1:44 pm, Adrian Hunter wrote:
> On 30/07/20 2:41 am, Faiz Abbas wrote:
>> There is a one time delay because of a card detect debounce timer in the
>> controller IP. This timer runs as soon as power is applied to the module
>> regardless of whether a card is present or not and any writes to
>> SDHCI_POWER_ON will return 0 before it expires. This timeout has been
>> measured to be about 1 second in am654x and j721e.
>>
>> Write-and-read-back in a loop on SDHCI_POWER_ON for a maximum of
>> 1.5 seconds to make sure that the controller actually powers on.
>>
>> Signed-off-by: Faiz Abbas
>> ---
>> drivers/mmc/host/sdhci_am654.c | 21 +
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
>> index 1718b9e8af63..55cff9de2f3e 100644
>> --- a/drivers/mmc/host/sdhci_am654.c
>> +++ b/drivers/mmc/host/sdhci_am654.c
>> @@ -272,6 +272,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host
>> *host,
>> sdhci_set_clock(host, clock);
>> }
>>
>> +#define MAX_POWER_ON_TIMEOUT1500 /* ms */
>> static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
>> {
>> unsigned char timing = host->mmc->ios.timing;
>> @@ -291,6 +292,26 @@ static void sdhci_am654_write_b(struct sdhci_host
>> *host, u8 val, int reg)
>> }
>>
>> writeb(val, host->ioaddr + reg);
>> +if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
>> +/*
>> + * Power on will not happen until the card detect debounce
>> + * timer expires. Wait at least 1.5 seconds for the power on
>> + * bit to be set
>> + */
>
> Can you use readb_poll_timeout() here?
>
The loop is write -> readback -> check for set bit -> write again and so on
until timeout
so poll_timeout() calls will not work.
Thanks,
Faiz
[PATCH] dt-bindings: mmc: sdhci-am654: Document bindings for the host controllers on TI's J7200 devices
Add binding documentation for mmc host controllers present on TI's J7200 SOC Signed-off-by: Faiz Abbas --- Documentation/devicetree/bindings/mmc/sdhci-am654.txt | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt index 6d202f4d9249..b49cbfdd679f 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -12,6 +12,8 @@ Required Properties: "ti,am654-sdhci-5.1": SDHCI on AM654 device. "ti,j721e-sdhci-8bit": 8 bit SDHCI on J721E device. "ti,j721e-sdhci-4bit": 4 bit SDHCI on J721E device. + "ti,j7200-sdhci-8bit": 8 bit SDHCI on J7200 device. + "ti,j7200-sdhci-4bit": 4 bit SDHCI on J7200 device. - reg: Must be two entries. - The first should be the sdhci register space - The second should the subsystem/phy register space @@ -33,7 +35,9 @@ Required Properties: These bindings must be provided otherwise the driver will disable the corresponding speed mode (i.e. all nodes must provide at least -legacy) -Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit): +Optional Properties (Required for ti,am654-sdhci-5.1, + ti,j721e-sdhci-8bit, + ti,j7200-sdhci-8bit): - ti,trm-icp: DLL trim select - ti,driver-strength-ohm: driver strength in ohms. Valid values are 33, 40, 50, 66 and 100 ohms. -- 2.17.1
[PATCH] mmc: sdhci_am654: Add workaround for card detect debounce timer
There is a one time delay because of a card detect debounce timer in the
controller IP. This timer runs as soon as power is applied to the module
regardless of whether a card is present or not and any writes to
SDHCI_POWER_ON will return 0 before it expires. This timeout has been
measured to be about 1 second in am654x and j721e.
Write-and-read-back in a loop on SDHCI_POWER_ON for a maximum of
1.5 seconds to make sure that the controller actually powers on.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 1718b9e8af63..55cff9de2f3e 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -272,6 +272,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host
*host,
sdhci_set_clock(host, clock);
}
+#define MAX_POWER_ON_TIMEOUT 1500 /* ms */
static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
{
unsigned char timing = host->mmc->ios.timing;
@@ -291,6 +292,26 @@ static void sdhci_am654_write_b(struct sdhci_host *host,
u8 val, int reg)
}
writeb(val, host->ioaddr + reg);
+ if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) {
+ /*
+* Power on will not happen until the card detect debounce
+* timer expires. Wait at least 1.5 seconds for the power on
+* bit to be set
+*/
+ ktime_t timeout = ktime_add_ms(ktime_get(),
+ MAX_POWER_ON_TIMEOUT);
+ do {
+ if (ktime_compare(ktime_get(), timeout) > 0) {
+ dev_warn(mmc_dev(host->mmc),
+"Power on failed\n");
+
+ return;
+ }
+
+ writeb(val, host->ioaddr + reg);
+ usleep_range(1000, 1);
+ } while (!(readb(host->ioaddr + reg) & SDHCI_POWER_ON));
+ }
}
static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode)
--
2.17.1
Re: [PATCH] can: m_can: Set device to software init mode before closing
Hi, On 16/07/20 9:53 am, Faiz Abbas wrote: > There might be some requests pending in the buffer when the > interface close sequence occurs. In some devices, these > pending requests might lead to the module not shutting down > properly when m_can_clk_stop() is called. > > Therefore, move the device to init state before potentially > powering it down. > > Signed-off-by: Faiz Abbas > --- > drivers/net/can/m_can/m_can.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c > index 02c5795b7393..d0c458f7f6e1 100644 > --- a/drivers/net/can/m_can/m_can.c > +++ b/drivers/net/can/m_can/m_can.c > @@ -1414,6 +1414,9 @@ static void m_can_stop(struct net_device *dev) > /* disable all interrupts */ > m_can_disable_all_interrupts(cdev); > > + /* Set init mode to disengage from the network */ > + m_can_config_endisable(cdev, true); > + > /* set the state as STOPPED */ > cdev->can.state = CAN_STATE_STOPPED; > } > Gentle ping. Thanks, Faiz
Re: [PATCH 7/7] arm64: defconfig: Enable AM654x SDHCI controller
Tero, On 17/07/20 6:39 pm, Arnd Bergmann wrote: > On Fri, Jul 17, 2020 at 1:20 PM Tero Kristo wrote: >> On 17/07/2020 11:38, Faiz Abbas wrote: >>> On 16/07/20 11:58 pm, Arnd Bergmann wrote: >>>> On Thu, Jul 16, 2020 at 3:25 PM Sekhar Nori wrote: >>>> I tend to ignore individual patches to the defconfig file unless >>>> they are sent to:s...@kernel.org. The best way to get them >>>> included is to have the platform maintainers pick up the >>>> changes and send them that way as a separate pull request >>>> at the same time as sending any DT updates. >>>> >>>> The MAINTAINERS file lists Tero and Nishanth as maintainers >>>> for the platform. If they want, I can apply this one directly, but in >>>> the future, send it to them. >>>> >>> >>> Thanks for clarifying Arnd. Tero, can you pick this up? >> >> Ok, this topic has been bit unclear for me also, but if you say I can >> pick the patches myself and send a pull request out, I can do that. > Patches 1-6 are being merged from mmc tree. You only need to pick up this patch. Thanks, Faiz
Re: [PATCH 7/7] arm64: defconfig: Enable AM654x SDHCI controller
Hi, On 16/07/20 11:58 pm, Arnd Bergmann wrote: > On Thu, Jul 16, 2020 at 3:25 PM Sekhar Nori wrote: >> >> On 7/16/20 5:49 PM, Faiz Abbas wrote: >>> Hi, >>> >>> On 19/06/20 6:28 pm, Faiz Abbas wrote: >>>> Enable CONFIG_SDHCI_AM654 to Support AM65x sdhci controller. >>>> >>>> Signed-off-by: Faiz Abbas >>>> --- >>>> arch/arm64/configs/defconfig | 1 + >>>> 1 file changed, 1 insertion(+) >>>> >>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig >>>> index 883e8bace3ed..40dd13e0adc5 100644 >>>> --- a/arch/arm64/configs/defconfig >>>> +++ b/arch/arm64/configs/defconfig >>>> @@ -731,6 +731,7 @@ CONFIG_MMC_DW_ROCKCHIP=y >>>> CONFIG_MMC_SUNXI=y >>>> CONFIG_MMC_BCM2835=y >>>> CONFIG_MMC_SDHCI_XENON=y >>>> +CONFIG_MMC_SDHCI_AM654=y >>>> CONFIG_MMC_OWL=y >>>> CONFIG_NEW_LEDS=y >>>> CONFIG_LEDS_CLASS=y >>>> >>> >>> Gentle ping. Will, Catalin, can this patch be picked up? >> >> From logs, Arnd has been picking up patches for this file. Looping in >> Arnd and ARM-SoC team. > > I tend to ignore individual patches to the defconfig file unless > they are sent to:s...@kernel.org. The best way to get them > included is to have the platform maintainers pick up the > changes and send them that way as a separate pull request > at the same time as sending any DT updates. > > The MAINTAINERS file lists Tero and Nishanth as maintainers > for the platform. If they want, I can apply this one directly, but in > the future, send it to them. > Thanks for clarifying Arnd. Tero, can you pick this up? Thanks, Faiz
Re: [PATCH 7/7] arm64: defconfig: Enable AM654x SDHCI controller
Hi, On 19/06/20 6:28 pm, Faiz Abbas wrote: > Enable CONFIG_SDHCI_AM654 to Support AM65x sdhci controller. > > Signed-off-by: Faiz Abbas > --- > arch/arm64/configs/defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig > index 883e8bace3ed..40dd13e0adc5 100644 > --- a/arch/arm64/configs/defconfig > +++ b/arch/arm64/configs/defconfig > @@ -731,6 +731,7 @@ CONFIG_MMC_DW_ROCKCHIP=y > CONFIG_MMC_SUNXI=y > CONFIG_MMC_BCM2835=y > CONFIG_MMC_SDHCI_XENON=y > +CONFIG_MMC_SDHCI_AM654=y > CONFIG_MMC_OWL=y > CONFIG_NEW_LEDS=y > CONFIG_LEDS_CLASS=y > Gentle ping. Will, Catalin, can this patch be picked up? Thanks, Faiz
[PATCH] can: m_can: Set device to software init mode before closing
There might be some requests pending in the buffer when the interface close sequence occurs. In some devices, these pending requests might lead to the module not shutting down properly when m_can_clk_stop() is called. Therefore, move the device to init state before potentially powering it down. Signed-off-by: Faiz Abbas --- drivers/net/can/m_can/m_can.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 02c5795b7393..d0c458f7f6e1 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -1414,6 +1414,9 @@ static void m_can_stop(struct net_device *dev) /* disable all interrupts */ m_can_disable_all_interrupts(cdev); + /* Set init mode to disengage from the network */ + m_can_config_endisable(cdev, true); + /* set the state as STOPPED */ cdev->can.state = CAN_STATE_STOPPED; } -- 2.17.1
[PATCH 2/2] arm64: dts: ti: k3-am654-base-board: Add support for SD card
With silicon revision 2.0, add support for SD card on the am65x-evm.
Boards with silicon revision 1.0 are susceptible to interface issues
because of erratas i2025 and i2026[1] and are recommended to disable
this node.
[1] Am654x Silicon Revision 1.0 errata: https://www.ti.com/lit/pdf/sprz452
Signed-off-by: Faiz Abbas
---
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 24 +++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 9fc7898a6a3b..84aeb4761ac0 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -167,6 +167,19 @@
>;
};
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27)
MMC1_CLK */
+ AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28)
MMC1_CMD */
+ AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28)
MMC1_DAT0 */
+ AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27)
MMC1_DAT1 */
+ AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26)
MMC1_DAT2 */
+ AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27)
MMC1_DAT3 */
+ AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24)
MMC1_SDCD */
+ AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */
+ >;
+ };
+
usb1_pins_default: usb1_pins_default {
pinctrl-single,pins = <
AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8)
USB1_DRVVBUS */
@@ -299,6 +312,17 @@
ti,driver-strength-ohm = <50>;
disable-wp;
};
+/*
+ * Because of erratas i2025 and i2026 for silicon revision 1.0, the
+ * SD card interface might fail. Boards with sr1.0 are recommended to
+ * disable sdhci1
+ */
+&sdhci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
&dwc3_1 {
status = "okay";
--
2.17.1
[PATCH 1/2] arm64: dts: ti: k3-am65-main: Add support for sdhci1
Add support for the 2nd SDHCI controller on TI's AM654x SoCs.
Although it supports upto SDR104 (100 MBps @ 200 MHz) speed mode,
only enable support upto High Speed (25 MBps @ 50 MHz) for now.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 24
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 3a4effee8fba..dfb429bed56d 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -259,6 +259,30 @@
dma-coherent;
};
+ sdhci1: sdhci@4fa {
+ compatible = "ti,am654-sdhci-5.1";
+ reg = <0x0 0x4fa 0x0 0x260>, <0x0 0x4fb 0x0 0x134>;
+ power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
+ clock-names = "clk_ahb", "clk_xin";
+ interrupts = ;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x7>;
+ ti,otap-del-sel-ddr50 = <0x4>;
+ ti,otap-del-sel-ddr52 = <0x4>;
+ ti,otap-del-sel-hs200 = <0x7>;
+ ti,clkbuf-sel = <0x7>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ dma-coherent;
+ no-1-8-v;
+ };
+
scm_conf: scm_conf@10 {
compatible = "syscon", "simple-mfd";
reg = <0 0x0010 0 0x1c000>;
--
2.17.1
[PATCH 0/2] Add support for SD card on on AM65x-evm
The following patches add support for SD card node in am654x-evm Because of fundamental interface issues (see patch 2 for details), SD card was never enabled for silicon revision 1.0 These issues have been fixed with SR2.0 but boards with SR1.0 are recommended to disable this node These patches depend on kernel patches for supporting silicon revision 2.0 posted here: https://patchwork.kernel.org/project/linux-mmc/list/?series=305565 The dependencies have been picked up and are in linux-next Faiz Abbas (2): arm64: dts: ti: k3-am65-main: Add support for sdhci1 arm64: dts: ti: k3-am654-base-board: Add support for SD card arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 24 +++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 24 +++ 2 files changed, 48 insertions(+) -- 2.17.1
Re: [PATCH 0/7] Add support for SD card in AM654x-evm
Hi, On 19/06/20 6:27 pm, Faiz Abbas wrote: > The following patches add driver support for SD card on the > am654x-evm. It only enables high speed mode with UHS mode > support coming in a future series. > > DTS support will be added in another series as well. > > Faiz Abbas (7): > dt-bindings: mmc: sdhci-am654: Add ti,clkbuf-sel binding > mmc: sdhci_am654: Add flag for PHY calibration > mmc: sdhci_am654: Add Support for SR2.0 > mmc: sdhci_am654: Fix conditions for enabling dll > mmc: sdhci_am654: Update delay chain configuration > mmc: sdhci_am654: Add support for clkbuf_sel property > arm64: defconfig: Enable AM654x SDHCI controller > > .../devicetree/bindings/mmc/sdhci-am654.txt | 1 + > arch/arm64/configs/defconfig | 1 + > drivers/mmc/host/sdhci_am654.c| 86 ++- > 3 files changed, 65 insertions(+), 23 deletions(-) > Gentle ping. Thanks, Faiz
[PATCH 1/7] dt-bindings: mmc: sdhci-am654: Add ti,clkbuf-sel binding
Add documentation for the clock buffer select phy property in the am654x and j721e 4 bit IP Signed-off-by: Faiz Abbas --- Documentation/devicetree/bindings/mmc/sdhci-am654.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt index c6ccecb9ae5a..6d202f4d9249 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -39,6 +39,7 @@ Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit): Valid values are 33, 40, 50, 66 and 100 ohms. Optional Properties: - ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0. + - ti,clkbuf-sel: Clock Delay Buffer Select Example: -- 2.17.1
[PATCH 6/7] mmc: sdhci_am654: Add support for clkbuf_sel property
Add support for writing new clkbuf_sel property for the J721e 4 bit IP.
Signed-off-by: Faiz Abbas
Signed-off-by: Sekhar Nori
---
drivers/mmc/host/sdhci_am654.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index f7535ee3a232..f9d24af12396 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -47,6 +47,8 @@
#define SEL100_MASKBIT(SEL100_SHIFT)
#define FREQSEL_SHIFT 8
#define FREQSEL_MASK GENMASK(10, 8)
+#define CLKBUFSEL_SHIFT0
+#define CLKBUFSEL_MASK GENMASK(2, 0)
#define DLL_TRIM_ICP_SHIFT 4
#define DLL_TRIM_ICP_MASK GENMASK(7, 4)
#define DR_TY_SHIFT20
@@ -86,6 +88,7 @@ struct sdhci_am654_data {
struct regmap *base;
bool legacy_otapdly;
int otap_del_sel[11];
+ int clkbuf_sel;
int trm_icp;
int drv_strength;
bool dll_on;
@@ -238,6 +241,9 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT);
}
+
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ sdhci_am654->clkbuf_sel);
}
static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
@@ -260,6 +266,9 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host
*host,
(otap_del_sel << OTAPDLYSEL_SHIFT);
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK,
+ sdhci_am654->clkbuf_sel);
+
sdhci_set_clock(host, clock);
}
@@ -582,6 +591,8 @@ static int sdhci_am654_get_of_property(struct
platform_device *pdev,
}
device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel);
+ device_property_read_u32(dev, "ti,clkbuf-sel",
+&sdhci_am654->clkbuf_sel);
sdhci_get_of_property(pdev);
--
2.17.1
[PATCH 4/7] mmc: sdhci_am654: Fix conditions for enabling dll
The clock > CLOCK_TOO_SLOW_HZ condition gating phy configuration
is only required because dll should not be enabled at too low a
clock frequency or too low timing. Make sure that this condition
only gates dll enablement.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 42 --
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 365eb2819dd9..8b0f69012d09 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -204,34 +204,32 @@ static void sdhci_am654_set_clock(struct sdhci_host
*host, unsigned int clock)
sdhci_set_clock(host, clock);
- if (clock > CLOCK_TOO_SLOW_HZ) {
- /* Setup DLL Output TAP delay */
- if (sdhci_am654->legacy_otapdly)
- otap_del_sel = sdhci_am654->otap_del_sel[0];
- else
- otap_del_sel = sdhci_am654->otap_del_sel[timing];
+ /* Setup DLL Output TAP delay */
+ if (sdhci_am654->legacy_otapdly)
+ otap_del_sel = sdhci_am654->otap_del_sel[0];
+ else
+ otap_del_sel = sdhci_am654->otap_del_sel[timing];
- otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
+ otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0;
- mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
- val = (otap_del_ena << OTAPDLYENA_SHIFT) |
- (otap_del_sel << OTAPDLYSEL_SHIFT);
+ mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
+ val = (otap_del_ena << OTAPDLYENA_SHIFT) |
+ (otap_del_sel << OTAPDLYSEL_SHIFT);
- /* Write to STRBSEL for HS400 speed mode */
- if (timing == MMC_TIMING_MMC_HS400) {
- if (sdhci_am654->flags & STRBSEL_4_BIT)
- mask |= STRBSEL_4BIT_MASK;
- else
- mask |= STRBSEL_8BIT_MASK;
+ /* Write to STRBSEL for HS400 speed mode */
+ if (timing == MMC_TIMING_MMC_HS400) {
+ if (sdhci_am654->flags & STRBSEL_4_BIT)
+ mask |= STRBSEL_4BIT_MASK;
+ else
+ mask |= STRBSEL_8BIT_MASK;
- val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
- }
+ val |= sdhci_am654->strb_sel << STRBSEL_SHIFT;
+ }
- regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
- if (timing > MMC_TIMING_UHS_SDR25)
- sdhci_am654_setup_dll(host, clock);
- }
+ if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ)
+ sdhci_am654_setup_dll(host, clock);
}
static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
--
2.17.1
[PATCH 2/7] mmc: sdhci_am654: Add flag for PHY calibration
Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag
to indicate the same.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 061b4398a4f1..85a05344f825 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -97,6 +97,7 @@ struct sdhci_am654_driver_data {
#define FREQSEL_2_BIT (1 << 1)
#define STRBSEL_4_BIT (1 << 2)
#define DLL_PRESENT(1 << 3)
+#define DLL_CALIB (1 << 4)
};
struct timing_data {
@@ -325,7 +326,8 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = {
static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
.pdata = &sdhci_am654_pdata,
- .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
+DLL_CALIB,
};
static struct sdhci_ops sdhci_j721e_8bit_ops = {
@@ -348,7 +350,7 @@ static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata
= {
static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = {
.pdata = &sdhci_j721e_8bit_pdata,
- .flags = DLL_PRESENT,
+ .flags = DLL_PRESENT | DLL_CALIB,
};
static struct sdhci_ops sdhci_j721e_4bit_ops = {
@@ -469,7 +471,7 @@ static int sdhci_am654_init(struct sdhci_host *host)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
- if (sdhci_am654->flags & DLL_PRESENT) {
+ if (sdhci_am654->flags & DLL_CALIB) {
regmap_read(sdhci_am654->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
--
2.17.1
[PATCH 0/7] Add support for SD card in AM654x-evm
The following patches add driver support for SD card on the am654x-evm. It only enables high speed mode with UHS mode support coming in a future series. DTS support will be added in another series as well. Faiz Abbas (7): dt-bindings: mmc: sdhci-am654: Add ti,clkbuf-sel binding mmc: sdhci_am654: Add flag for PHY calibration mmc: sdhci_am654: Add Support for SR2.0 mmc: sdhci_am654: Fix conditions for enabling dll mmc: sdhci_am654: Update delay chain configuration mmc: sdhci_am654: Add support for clkbuf_sel property arm64: defconfig: Enable AM654x SDHCI controller .../devicetree/bindings/mmc/sdhci-am654.txt | 1 + arch/arm64/configs/defconfig | 1 + drivers/mmc/host/sdhci_am654.c| 86 ++- 3 files changed, 65 insertions(+), 23 deletions(-) -- 2.17.1
[PATCH 5/7] mmc: sdhci_am654: Update delay chain configuration
For speed modes where DLL is not enabled write to TXDLYCLK to enable
transmitter delay chain mode.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 8b0f69012d09..f7535ee3a232 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -61,6 +61,8 @@
#define CALDONE_MASK BIT(CALDONE_SHIFT)
#define RETRIM_SHIFT 17
#define RETRIM_MASKBIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT 17
+#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT)
#define DRIVER_STRENGTH_50_OHM 0x0
#define DRIVER_STRENGTH_33_OHM 0x1
@@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
- if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ)
+ if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) {
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
+ SELDLYTXCLK_MASK, 0);
sdhci_am654_setup_dll(host, clock);
+ } else {
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
+ SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT);
+ }
}
static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host,
--
2.17.1
[PATCH 3/7] mmc: sdhci_am654: Add Support for SR2.0
Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the driver data and skip do DLL calibration if the revision is 1.0
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 85a05344f825..365eb2819dd9 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include "cqhci.h"
#include "sdhci-pltfm.h"
@@ -324,12 +325,17 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = {
.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
};
-static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
+static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = {
.pdata = &sdhci_am654_pdata,
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT |
DLL_CALIB,
};
+static const struct sdhci_am654_driver_data sdhci_am654_drvdata = {
+ .pdata = &sdhci_am654_pdata,
+ .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT,
+};
+
static struct sdhci_ops sdhci_j721e_8bit_ops = {
.get_max_clock = sdhci_pltfm_clk_get_max_clock,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
@@ -376,6 +382,14 @@ static const struct sdhci_am654_driver_data
sdhci_j721e_4bit_drvdata = {
.flags = IOMUX_PRESENT,
};
+static const struct soc_device_attribute sdhci_am654_devices[] = {
+ { .family = "AM65X",
+ .revision = "SR1.0",
+ .data = &sdhci_am654_sr1_drvdata
+ },
+ {/* sentinel */}
+};
+
static void sdhci_am654_dumpregs(struct mmc_host *mmc)
{
sdhci_dumpregs(mmc_priv(mmc));
@@ -587,6 +601,7 @@ static const struct of_device_id sdhci_am654_of_match[] = {
static int sdhci_am654_probe(struct platform_device *pdev)
{
const struct sdhci_am654_driver_data *drvdata;
+ const struct soc_device_attribute *soc;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_am654_data *sdhci_am654;
const struct of_device_id *match;
@@ -598,6 +613,12 @@ static int sdhci_am654_probe(struct platform_device *pdev)
match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node);
drvdata = match->data;
+
+ /* Update drvdata based on SoC revision */
+ soc = soc_device_match(sdhci_am654_devices);
+ if (soc && soc->data)
+ drvdata = soc->data;
+
host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654));
if (IS_ERR(host))
return PTR_ERR(host);
--
2.17.1
[PATCH 7/7] arm64: defconfig: Enable AM654x SDHCI controller
Enable CONFIG_SDHCI_AM654 to Support AM65x sdhci controller. Signed-off-by: Faiz Abbas --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 883e8bace3ed..40dd13e0adc5 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -731,6 +731,7 @@ CONFIG_MMC_DW_ROCKCHIP=y CONFIG_MMC_SUNXI=y CONFIG_MMC_BCM2835=y CONFIG_MMC_SDHCI_XENON=y +CONFIG_MMC_SDHCI_AM654=y CONFIG_MMC_OWL=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -- 2.17.1
Re: [PATCH v3] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
Hi, On 19/05/20 1:50 pm, Faiz Abbas wrote: > According to the latest AM65x Data Manual[1], a different output tap > delay value is optimum for a given speed mode. Update these values. > > [1] http://www.ti.com/lit/gpn/am6526 > > Signed-off-by: Faiz Abbas > --- > > v3: Updated values to the latest data manual revision > > v2: Updated to the latest mainline kernel > Can this patch be picked up? Thanks, Faiz
Re: [PATCH v2] arm: dts: Move am33xx and am43xx mmc nodes to sdhci-omap driver
Tony, On 15/05/20 3:04 pm, Faiz Abbas wrote: > Hi Tony, > > On 13/05/20 9:53 pm, Tony Lindgren wrote: >> * Faiz Abbas [200512 13:39]: >>> Move mmc nodes to be compatible with the sdhci-omap driver. The following >>> modifications are required for omap_hsmmc specific properties: >>> >>> ti,non-removable: convert to the generic mmc non-removable >>> ti,needs-special-reset: co-opted into the sdhci-omap driver >>> ti,dual-volt: removed. Legacy property not used in am335x or am43xx >>> ti,needs-special-hs-handling: removed. Legacy property not used in am335x >>> or am43xx >>> >>> Also since the sdhci-omap driver does not support runtime PM, explicitly >>> disable the mmc3 instance in the dtsi. >>> >>> Signed-off-by: Faiz Abbas >>> --- >>> >>> v2: Rebased to latest mainline where all kernel dependancies have been >>> merged. >>> >>> Suspend/Resume is now supported in the sdhci-omap driver. >> >> Great, thanks for updating it. >> >> Keerthy, care to test for am3 and am4? >> > > Suspend/resume on am43xx-gpevm is broken right now in mainline and the > regression looks > like it is caused by the display subsystem. I have reported this to Tomi and > its being investigated. > > Meanwhile I have tested this patch with display configs disabled and Keerthy's > suspend/resume tests pass on both am3 and am4. > Can this patch be picked up? I would really like this to be merged by v5.8 Thanks, Faiz
[PATCH v3] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Update these values. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas --- v3: Updated values to the latest data manual revision v2: Updated to the latest mainline kernel arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 11887c72f23a..056130a126f9 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -244,7 +244,17 @@ interrupts = ; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x7>; + ti,otap-del-sel-ddr50 = <0x5>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; dma-coherent; }; -- 2.17.1
Re: [PATCH v2] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
Hi Tero, On 15/05/20 3:44 pm, Tero Kristo wrote: > On 07/05/2020 21:15, Faiz Abbas wrote: >> According to the latest AM65x Data Manual[1], a different output tap >> delay value is optimum for a given speed mode. Update these values. >> >> [1] http://www.ti.com/lit/gpn/am6526 >> >> Signed-off-by: Faiz Abbas >> --- >> v2: Rebased to the latest mainline kernel >> >> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++- >> 1 file changed, 11 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> index 11887c72f23a..6cd9701e4ead 100644 >> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi >> @@ -244,7 +244,17 @@ >> interrupts = ; >> mmc-ddr-1_8v; >> mmc-hs200-1_8v; >> - ti,otap-del-sel = <0x2>; >> + ti,otap-del-sel-legacy = <0x0>; >> + ti,otap-del-sel-mmc-hs = <0x0>; >> + ti,otap-del-sel-sd-hs = <0x0>; >> + ti,otap-del-sel-sdr12 = <0x0>; >> + ti,otap-del-sel-sdr25 = <0x0>; >> + ti,otap-del-sel-sdr50 = <0x8>; >> + ti,otap-del-sel-sdr104 = <0x5>; > > Isn't this wrong? Doc claims the value for sdr104 should be 0x7? > Yes. There seems to be an update to the document since I last updated the value. Thanks for catching. I will post another version soon. Thanks, Faiz
Re: [PATCH v2] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
Tero, On 07/05/20 11:45 pm, Faiz Abbas wrote: > According to the latest AM65x Data Manual[1], a different output tap > delay value is optimum for a given speed mode. Update these values. > > [1] http://www.ti.com/lit/gpn/am6526 > > Signed-off-by: Faiz Abbas > --- > v2: Rebased to the latest mainline kernel > Gentle ping. Thanks, Faiz
Re: [PATCH v2] arm: dts: Move am33xx and am43xx mmc nodes to sdhci-omap driver
Hi Tony, On 13/05/20 9:53 pm, Tony Lindgren wrote: > * Faiz Abbas [200512 13:39]: >> Move mmc nodes to be compatible with the sdhci-omap driver. The following >> modifications are required for omap_hsmmc specific properties: >> >> ti,non-removable: convert to the generic mmc non-removable >> ti,needs-special-reset: co-opted into the sdhci-omap driver >> ti,dual-volt: removed. Legacy property not used in am335x or am43xx >> ti,needs-special-hs-handling: removed. Legacy property not used in am335x >> or am43xx >> >> Also since the sdhci-omap driver does not support runtime PM, explicitly >> disable the mmc3 instance in the dtsi. >> >> Signed-off-by: Faiz Abbas >> --- >> >> v2: Rebased to latest mainline where all kernel dependancies have been >> merged. >> >> Suspend/Resume is now supported in the sdhci-omap driver. > > Great, thanks for updating it. > > Keerthy, care to test for am3 and am4? > Suspend/resume on am43xx-gpevm is broken right now in mainline and the regression looks like it is caused by the display subsystem. I have reported this to Tomi and its being investigated. Meanwhile I have tested this patch with display configs disabled and Keerthy's suspend/resume tests pass on both am3 and am4. Thanks, Faiz
[PATCH v2] arm: dts: Move am33xx and am43xx mmc nodes to sdhci-omap driver
Move mmc nodes to be compatible with the sdhci-omap driver. The following
modifications are required for omap_hsmmc specific properties:
ti,non-removable: convert to the generic mmc non-removable
ti,needs-special-reset: co-opted into the sdhci-omap driver
ti,dual-volt: removed. Legacy property not used in am335x or am43xx
ti,needs-special-hs-handling: removed. Legacy property not used in am335x
or am43xx
Also since the sdhci-omap driver does not support runtime PM, explicitly
disable the mmc3 instance in the dtsi.
Signed-off-by: Faiz Abbas
---
v2: Rebased to latest mainline where all kernel dependancies have been merged.
Suspend/Resume is now supported in the sdhci-omap driver.
Tested on: am335x-evm, am335x-boneblack, am335x-sk, am335x-bone, am437x-idk,
am43xx-gp-evm, am43xx-epos-evm.
arch/arm/boot/dts/am335x-baltos.dtsi | 2 +-
arch/arm/boot/dts/am335x-boneblack-common.dtsi| 1 +
arch/arm/boot/dts/am335x-boneblack-wireless.dts | 1 -
arch/arm/boot/dts/am335x-boneblue.dts | 1 -
arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 1 -
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/am335x-evmsk.dts| 2 +-
arch/arm/boot/dts/am335x-lxm.dts | 2 +-
arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 2 +-
arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts| 2 +-
arch/arm/boot/dts/am335x-pepper.dts | 4 ++--
arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +-
arch/arm/boot/dts/am33xx-l4.dtsi | 6 ++
arch/arm/boot/dts/am33xx.dtsi | 3 ++-
arch/arm/boot/dts/am4372.dtsi | 3 ++-
arch/arm/boot/dts/am437x-cm-t43.dts | 2 +-
arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++--
arch/arm/boot/dts/am437x-l4.dtsi | 5 ++---
arch/arm/boot/dts/am437x-sk-evm.dts | 2 +-
19 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi
b/arch/arm/boot/dts/am335x-baltos.dtsi
index 05e7b5d4a95b..04f0b1227efe 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -369,7 +369,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
- ti,non-removable;
+ non-removable;
bus-width = <4>;
cap-power-off-card;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
index 91f93bc89716..dd932220a8bf 100644
--- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
@@ -22,6 +22,7 @@
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
+ non-removable;
};
&am33xx_pinmux {
diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 3124d94c0b3c..e07dd7979586 100644
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts
b/arch/arm/boot/dts/am335x-boneblue.dts
index 5811fb8d4fdf..83f9452c9cd3 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -367,7 +367,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 4092cd193b8a..609c8db687ec 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 68252dab32c3..a4fc6b168a85 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -743,8 +743,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlan_pins>;
- ti,non-removable;
- ti,needs-special-hs-handling;
+ non-removable;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/arch/arm/boot/dts/am3
[PATCH v2] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
According to the latest AM65x Data Manual[1], a different output tap delay value is optimum for a given speed mode. Update these values. [1] http://www.ti.com/lit/gpn/am6526 Signed-off-by: Faiz Abbas --- v2: Rebased to the latest mainline kernel arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index 11887c72f23a..6cd9701e4ead 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -244,7 +244,17 @@ interrupts = ; mmc-ddr-1_8v; mmc-hs200-1_8v; - ti,otap-del-sel = <0x2>; + ti,otap-del-sel-legacy = <0x0>; + ti,otap-del-sel-mmc-hs = <0x0>; + ti,otap-del-sel-sd-hs = <0x0>; + ti,otap-del-sel-sdr12 = <0x0>; + ti,otap-del-sel-sdr25 = <0x0>; + ti,otap-del-sel-sdr50 = <0x8>; + ti,otap-del-sel-sdr104 = <0x5>; + ti,otap-del-sel-ddr50 = <0x5>; + ti,otap-del-sel-ddr52 = <0x5>; + ti,otap-del-sel-hs200 = <0x5>; + ti,otap-del-sel-hs400 = <0x0>; ti,trm-icp = <0x8>; dma-coherent; }; -- 2.17.1
Re: [RFC] mmc: cqhci: commit descriptors before setting the doorbell
Hi Uffe,
On 18/10/19 4:28 PM, Ulf Hansson wrote:
> On Mon, 14 Oct 2019 at 20:37, Faiz Abbas wrote:
>>
>> Add a write memory barrier to make sure that descriptors are actually
>> written to memory before ringing the doorbell.
>>
>> Signed-off-by: Faiz Abbas
>
> Applied for fixes and by adding a stable tag, thanks!
>
> BTW, do you have a valid commit that it fixes?
>
You can add:
Fixes: a4080225f51d ("mmc: cqhci: support for command queue enabled host")
Thanks,
Faiz
Re: [RFC] mmc: cqhci: commit descriptors before setting the doorbell
Adrian,
On 16/10/19 5:46 PM, Faiz Abbas wrote:
> Adrian,
>
> On 15/10/19 7:15 PM, Adrian Hunter wrote:
>> On 15/10/19 10:55 AM, Faiz Abbas wrote:
>>> Hi,
>>>
>>> On 15/10/19 12:08 AM, Faiz Abbas wrote:
>>>> Add a write memory barrier to make sure that descriptors are actually
>>>> written to memory before ringing the doorbell.
>>>>
>>>> Signed-off-by: Faiz Abbas
>>>> ---
>>>>
>>>> This patch fixes a very infrequent ADMA error (1 out of 100 times) that
>>>> I have been seeing after enabling command queuing for J721e.
>>>> Also looking at memory-barriers.txt and this commit[1],
>>>> it looks like we should be doing this before any descriptor write
>>>> followed by a doorbell ring operation. It'll be nice if someone with more
>>>> expertise in memory barriers can comment.
>>>>
>>>> [1] ad1a1b9cd67a ("scsi: ufs: commit descriptors before setting the
>>>> doorbell")
>>>
>>> So I see that cqhci_readl/writel() use readl/writel_relaxed() which
>>> seems to be causing this issue. Should I just fix this by converting
>>> those to readl/writel with memory barriers instead?
>>
>> Perhaps we could do both changes i.e. add wmb() and convert to non-relaxed
>> readl/writel
>>
>
> readl is implemented as readl_relaxed(); __rmb();
> and
> writel is implemented as wmb(); writel_relaxed();
>
> I think another wmb() before writel will be redundant.
>
> Maybe this patch is good enough in itself.
>
Do you agree?
Thanks,
Faiz
Re: [RFC] mmc: cqhci: commit descriptors before setting the doorbell
Adrian,
On 15/10/19 7:15 PM, Adrian Hunter wrote:
> On 15/10/19 10:55 AM, Faiz Abbas wrote:
>> Hi,
>>
>> On 15/10/19 12:08 AM, Faiz Abbas wrote:
>>> Add a write memory barrier to make sure that descriptors are actually
>>> written to memory before ringing the doorbell.
>>>
>>> Signed-off-by: Faiz Abbas
>>> ---
>>>
>>> This patch fixes a very infrequent ADMA error (1 out of 100 times) that
>>> I have been seeing after enabling command queuing for J721e.
>>> Also looking at memory-barriers.txt and this commit[1],
>>> it looks like we should be doing this before any descriptor write
>>> followed by a doorbell ring operation. It'll be nice if someone with more
>>> expertise in memory barriers can comment.
>>>
>>> [1] ad1a1b9cd67a ("scsi: ufs: commit descriptors before setting the
>>> doorbell")
>>
>> So I see that cqhci_readl/writel() use readl/writel_relaxed() which
>> seems to be causing this issue. Should I just fix this by converting
>> those to readl/writel with memory barriers instead?
>
> Perhaps we could do both changes i.e. add wmb() and convert to non-relaxed
> readl/writel
>
readl is implemented as readl_relaxed(); __rmb();
and
writel is implemented as wmb(); writel_relaxed();
I think another wmb() before writel will be redundant.
Maybe this patch is good enough in itself.
Thanks,
Faiz
Re: [RFC] mmc: cqhci: commit descriptors before setting the doorbell
Hi,
On 15/10/19 12:08 AM, Faiz Abbas wrote:
> Add a write memory barrier to make sure that descriptors are actually
> written to memory before ringing the doorbell.
>
> Signed-off-by: Faiz Abbas
> ---
>
> This patch fixes a very infrequent ADMA error (1 out of 100 times) that
> I have been seeing after enabling command queuing for J721e.
> Also looking at memory-barriers.txt and this commit[1],
> it looks like we should be doing this before any descriptor write
> followed by a doorbell ring operation. It'll be nice if someone with more
> expertise in memory barriers can comment.
>
> [1] ad1a1b9cd67a ("scsi: ufs: commit descriptors before setting the
> doorbell")
So I see that cqhci_readl/writel() use readl/writel_relaxed() which
seems to be causing this issue. Should I just fix this by converting
those to readl/writel with memory barriers instead?
Thanks,
Faiz
[RFC] mmc: cqhci: commit descriptors before setting the doorbell
Add a write memory barrier to make sure that descriptors are actually
written to memory before ringing the doorbell.
Signed-off-by: Faiz Abbas
---
This patch fixes a very infrequent ADMA error (1 out of 100 times) that
I have been seeing after enabling command queuing for J721e.
Also looking at memory-barriers.txt and this commit[1],
it looks like we should be doing this before any descriptor write
followed by a doorbell ring operation. It'll be nice if someone with more
expertise in memory barriers can comment.
[1] ad1a1b9cd67a ("scsi: ufs: commit descriptors before setting the
doorbell")
drivers/mmc/host/cqhci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index f7bdae5354c3..5047f7343ffc 100644
--- a/drivers/mmc/host/cqhci.c
+++ b/drivers/mmc/host/cqhci.c
@@ -611,7 +611,8 @@ static int cqhci_request(struct mmc_host *mmc, struct
mmc_request *mrq)
cq_host->slot[tag].flags = 0;
cq_host->qcnt += 1;
-
+ /* Make sure descriptors are ready before ringing the doorbell */
+ wmb();
cqhci_writel(cq_host, 1 << tag, CQHCI_TDBR);
if (!(cqhci_readl(cq_host, CQHCI_TDBR) & (1 << tag)))
pr_debug("%s: cqhci: doorbell not set for tag %d\n",
--
2.19.2
[PATCH] mmc: sdhci-omap: Fix Tuning procedure for temperatures < -20C
According to the App note[1] detailing the tuning algorithm, for
temperatures < -20C, the initial tuning value should be min(largest
value in LPW - 24, ceil(13/16 ratio of LPW)). The largest value in
LPW is (max_window + 4 * (max_len - 1)) and not (max_window + 4 * max_len)
itself. Fix this implementation.
[1] http://www.ti.com/lit/an/spraca9b/spraca9b.pdf
Fixes: 961de0a856e3 ("mmc: sdhci-omap: Workaround errata regarding
SDR104/HS200 tuning failures (i929)")
Cc: sta...@vger.kernel.org
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci-omap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 41c2677c587f..083e7e053c95 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -372,7 +372,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc,
u32 opcode)
* on temperature
*/
if (temperature < -2)
- phase_delay = min(max_window + 4 * max_len - 24,
+ phase_delay = min(max_window + 4 * (max_len - 1) - 24,
max_window +
DIV_ROUND_UP(13 * max_len, 16) * 4);
else if (temperature < 2)
--
2.19.2
Re: [PATCH 0/2] Add Support for MMC/SD for J721e-base-board
Hi, On 19/09/19 9:02 PM, Faiz Abbas wrote: > The following are dts patches to add MMC/SD Support on TI's J721e base > board. > > Patches depend on Lokesh's gpio patches[1] and device exclusivity patches[2]. > > [1] https://patchwork.kernel.org/cover/11085643/ > [2] https://patchwork.kernel.org/cover/11051559/ > > Faiz Abbas (2): > arm64: dts: ti: j721e-main: Add SDHCI nodes > arm64: dts: ti: j721e-common-proc-board: Add Support for eMMC and SD > card > > .../dts/ti/k3-j721e-common-proc-board.dts | 34 + > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 50 +++ > 2 files changed, 84 insertions(+) > Gentle ping. Thanks, Faiz
[PATCH] arm64: dts: ti: k3-am654-base-board: Add disable-wp for mmc0
MMC0_SDWP is not connected to the card. Indicate this by adding a
disable-wp flag.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 1102b84f853d..143474119328 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -221,6 +221,7 @@
bus-width = <8>;
non-removable;
ti,driver-strength-ohm = <50>;
+ disable-wp;
};
&dwc3_1 {
--
2.19.2
[PATCH 2/2] arm64: dts: ti: j721e-common-proc-board: Add Support for eMMC and SD card
sdhci0 is connected to an eMMC and sdhci1 is connected to an SD card
slot. Add support for these nodes.
Signed-off-by: Faiz Abbas
---
.../dts/ti/k3-j721e-common-proc-board.dts | 34 +++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index d2894d55fbbe..3cfaa2c83ba6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -41,6 +41,20 @@
J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18)
EXTINTn.GPIO0_0 */
>;
};
+
+ main_mmc1_pins_default: main_mmc1_pins_default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
+ J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
+ J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+ J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
+ J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
+ J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
+ J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
+ J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
+ J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
+ >;
+ };
};
&wkup_pmx0 {
@@ -117,3 +131,23 @@
&wkup_gpio1 {
status = "disabled";
};
+
+&main_sdhci0 {
+ /* eMMC */
+ non-removable;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci1 {
+ /* SD/MMC */
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_mmc1_pins_default>;
+ ti,driver-strength-ohm = <50>;
+ disable-wp;
+};
+
+&main_sdhci2 {
+ /* Unused */
+ status = "disabled";
+};
--
2.19.2
[PATCH 1/2] arm64: dts: ti: j721e-main: Add SDHCI nodes
Add nodes for the 3 SDHCI instances present on TI's J721E device.
instance 0 supports HS400 (8 bit bus widht, DDR, 400 MBps)
while instances 1 and 2 support SDR104 (4 bit width, SDR, 100 MBps) as
their highest speed modes. Currently, only High speed (50 MHz clock) has
been enabled.
Signed-off-by: Faiz Abbas
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 50 +++
1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 199bc9a00b20..1650bbd10932 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -372,4 +372,54 @@
clocks = <&k3_clks 112 0>;
clock-names = "gpio";
};
+
+ main_sdhci0: sdhci@4f8 {
+ compatible = "ti,j721e-sdhci-8bit";
+ reg = <0x0 0x4f8 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
+ interrupts = ;
+ power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
+ assigned-clocks = <&k3_clks 91 1>;
+ assigned-clock-parents = <&k3_clks 91 2>;
+ bus-width = <8>;
+ mmc-hs400-1_8v;
+ mmc-ddr-1_8v;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ ti,strobe-sel = <0x77>;
+ dma-coherent;
+ };
+
+ main_sdhci1: sdhci@4fb {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x0 0x04fb 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
+ interrupts = ;
+ power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
+ assigned-clocks = <&k3_clks 92 0>;
+ assigned-clock-parents = <&k3_clks 92 1>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ ti,clkbuf-sel = <0x7>;
+ dma-coherent;
+ no-1-8-v;
+ };
+
+ main_sdhci2: sdhci@4f98000 {
+ compatible = "ti,j721e-sdhci-4bit";
+ reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f9 0x0 0x400>;
+ interrupts = ;
+ power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
+ assigned-clocks = <&k3_clks 93 0>;
+ assigned-clock-parents = <&k3_clks 93 1>;
+ ti,otap-del-sel = <0x2>;
+ ti,trm-icp = <0x8>;
+ ti,clkbuf-sel = <0x7>;
+ dma-coherent;
+ no-1-8-v;
+ };
};
--
2.19.2
[PATCH 0/2] Add Support for MMC/SD for J721e-base-board
The following are dts patches to add MMC/SD Support on TI's J721e base board. Patches depend on Lokesh's gpio patches[1] and device exclusivity patches[2]. [1] https://patchwork.kernel.org/cover/11085643/ [2] https://patchwork.kernel.org/cover/11051559/ Faiz Abbas (2): arm64: dts: ti: j721e-main: Add SDHCI nodes arm64: dts: ti: j721e-common-proc-board: Add Support for eMMC and SD card .../dts/ti/k3-j721e-common-proc-board.dts | 34 + arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 50 +++ 2 files changed, 84 insertions(+) -- 2.19.2
[PATCH] ARM: dts: dra74x: Fix iodelay configuration for mmc3
According to the latest am572x[1] and dra74x[2] data manuals, mmc3
default, hs, sdr12 and sdr25 modes use iodelay values given in
MMC3_MANUAL1. Set the MODE_SELECT bit for these so that manual mode is
selected and correct iodelay values can be configured.
[1] http://www.ti.com/lit/ds/symlink/am5728.pdf
[2] http://www.ti.com/lit/ds/symlink/dra746.pdf
Signed-off-by: Faiz Abbas
---
arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi | 50 +++
1 file changed, 25 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
index 28ebb4eb884a..214b9e6de2c3 100644
--- a/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
+++ b/arch/arm/boot/dts/dra74x-mmc-iodelay.dtsi
@@ -32,7 +32,7 @@
*
* Datamanual Revisions:
*
- * AM572x Silicon Revision 2.0: SPRS953B, Revised November 2016
+ * AM572x Silicon Revision 2.0: SPRS953F, Revised May 2019
* AM572x Silicon Revision 1.1: SPRS915R, Revised November 2016
*
*/
@@ -229,45 +229,45 @@
mmc3_pins_default: mmc3_pins_default {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_hs: mmc3_pins_hs {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
>;
};
mmc3_pins_sdr12: mmc3_pins_sdr12 {
pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_clk.mmc3_clk */
- DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
- DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
- DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
- DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
- DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP |
MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP |
MODE_SELECT | MUX_MODE0)) /* mm
Re: [PATCH v12 5/5] can: m_can: Fix checkpatch issues on existing code
Hi,
On 09/05/19 9:41 PM, Dan Murphy wrote:
> Fix checkpatch issues found during the m_can framework creation.
> The code the issues were in, was in untouched code and these
> changes should be done separately as to not be confused with the
> framework changes.
>
> Fix these 3 check issues:
> CHECK: Unnecessary parentheses around 'cdev->can.state !=
> CAN_STATE_ERROR_WARNING'
> if (psr & PSR_EW &&
> (cdev->can.state != CAN_STATE_ERROR_WARNING)) {
>
> CHECK: Unnecessary parentheses around 'cdev->can.state !=
> CAN_STATE_ERROR_PASSIVE'
> if ((psr & PSR_EP) &&
> (cdev->can.state != CAN_STATE_ERROR_PASSIVE)) {
>
> CHECK: Unnecessary parentheses around 'cdev->can.state != CAN_STATE_BUS_OFF'
> if ((psr & PSR_BO) &&
> (cdev->can.state != CAN_STATE_BUS_OFF)) {
>
> Signed-off-by: Dan Murphy
Acked-by: Faiz Abbas
Thanks,
Faiz
Re: [PATCH v12 2/5] can: m_can: Rename m_can_priv to m_can_classdev
Hi, On 09/05/19 9:41 PM, Dan Murphy wrote: > Rename the common m_can_priv class structure to > m_can_classdev as this is more descriptive. > > Acked-by: Wolfgang Grandegger > Signed-off-by: Dan Murphy Acked-by: Faiz Abbas Thanks, Faiz
Re: [PATCH v12 1/5] can: m_can: Create a m_can platform framework
Hi, On 09/05/19 9:41 PM, Dan Murphy wrote: > Create a m_can platform framework that peripheral > devices can register to and use common code and register sets. > The peripheral devices may provide read/write and configuration > support of the IP. > > Acked-by: Wolfgang Grandegger > Signed-off-by: Dan Murphy Acked-by: Faiz Abbas Thanks, Faiz
[PATCH] ARM: dts: am57xx: Disable voltage switching for SD card
If UHS speed modes are enabled, a compatible SD card switches down to
1.8V during enumeration. If after this a software reboot/crash takes
place and on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.
The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the
card). Because the beaglebone X15 (rev A,B and C), am57xx-idks and
am57xx-evms don't have this capability, disable voltage switching for
these boards.
The major effect of this is that the maximum supported speed
mode is now high speed(50 MHz) down from SDR104(200 MHz).
commit 88a748419b84 ("ARM: dts: am57xx-idk: Remove support for voltage
switching for SD card") did this only for idk boards. Do it for all
affected boards.
Signed-off-by: Faiz Abbas
---
arch/arm/boot/dts/am571x-idk.dts| 7 +--
arch/arm/boot/dts/am572x-idk.dts| 7 +--
arch/arm/boot/dts/am574x-idk.dts| 7 +--
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 1 +
arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts | 7 +--
arch/arm/boot/dts/am57xx-beagle-x15-revc.dts| 7 +--
6 files changed, 6 insertions(+), 30 deletions(-)
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index 66116ad3f9f4..0a043908215c 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -178,14 +178,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50",
"sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index 4f835222c266..8663a9416af6 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -19,14 +19,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50",
"sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_sdr12>;
- pinctrl-3 = <&mmc1_pins_sdr25>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>;
- pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};
&mmc2 {
diff --git a/arch/arm/boot/dts/am574x-idk.dts b/arch/arm/boot/dts/am574x-idk.dts
index dc5141c35610..7935d70874ce 100644
--- a/arch/arm/boot/dts/am574x-idk.dts
+++ b/arch/arm/boot/dts/am574x-idk.dts
@@ -24,14 +24,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50",
"sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default_no_clk_pu>;
pinctrl-1 = <&mmc1_pins_hs>;
- pinctrl-2 = <&mmc1_pins_default>;
- pinctrl-3 = <&mmc1_pins_hs>;
- pinctrl-4 = <&mmc1_pins_sdr50>;
- pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_conf>;
- pinctrl-6 = <&mmc1_pins_ddr50 &mmc1_iodelay_sdr104_conf>;
};
&mmc2 {
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 2341a56ebab9..0cdfd2853ba8 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -433,6 +433,7 @@
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ no-1-8-v;
};
&mmc2 {
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
index 5a77b334923d..34c69965821b 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-revb1.dts
@@ -19,14 +19,9 @@
};
&mmc1 {
- pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50",
"sdr104";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
Re: [PATCH v3 1/3] mmc: sdhci_am654: Fix SLOTTYPE write
Hi Sasha,
On 04/06/19 6:20 PM, Sasha Levin wrote:
> Hi,
>
> [This is an automated email]
>
> This commit has been processed because it contains a -stable tag.
> The stable tag indicates that it's relevant for the following trees: all
>
> The bot has tested the following trees: v5.1.6, v5.0.20, v4.19.47, v4.14.123,
> v4.9.180, v4.4.180.
>
> v5.1.6: Build OK!
> v5.0.20: Build OK!
Please apply it only to the above two releases. I guess this script
could detect that the file was not even present before this and not try
to apply to those.
> v4.19.47: Failed to apply! Possible dependencies:
> 06b23ca021c4 ("mmc: sdhci-of-arasan: Add a single data structure to
> incorporate pdata and soc_ctl_map")
> 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI
> driver")
> f0061fed1f8a ("mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY")
>
> v4.14.123: Failed to apply! Possible dependencies:
> 06b23ca021c4 ("mmc: sdhci-of-arasan: Add a single data structure to
> incorporate pdata and soc_ctl_map")
> 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI
> driver")
> 7d326930d352 ("mmc: sdhci-omap: Add OMAP SDHCI driver")
> 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for
> arasan,sdhci-5.1")
> f0061fed1f8a ("mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY")
>
> v4.9.180: Failed to apply! Possible dependencies:
> 06b23ca021c4 ("mmc: sdhci-of-arasan: Add a single data structure to
> incorporate pdata and soc_ctl_map")
> 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core
> functionality")
> 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI
> driver")
> 7d326930d352 ("mmc: sdhci-omap: Add OMAP SDHCI driver")
> 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for
> arasan,sdhci-5.1")
> d38dcad4e7b4 ("mmc: sdhci: Let drivers decide whether to use
> mmc_retune_needed() with pm")
> f0061fed1f8a ("mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY")
>
> v4.4.180: Failed to apply! Possible dependencies:
> 06b23ca021c4 ("mmc: sdhci-of-arasan: Add a single data structure to
> incorporate pdata and soc_ctl_map")
> 0c7fe32e847f ("mmc: sdhci-of-arasan: fix clk issue in
> sdhci_arasan_remove()")
> 278d09624eda ("mmc: sdhci-of-arasan: fix missing sdhci_pltfm_free for err
> handling")
> 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core
> functionality")
> 3ea4666e8d42 ("mmc: sdhci-of-arasan: Properly set corecfg_baseclkfreq on
> rk3399")
> 41fd4caeb00b ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI
> driver")
> 476bf3d62d5c ("mmc: sdhci-brcmstb: Add driver for Broadcom BRCMSTB SoCs")
> 5d9460d74ce5 ("mmc: sdhci-pic32: Add PIC32 SDHCI host controller driver")
> 7d326930d352 ("mmc: sdhci-omap: Add OMAP SDHCI driver")
> 802ac39a5566 ("mmc: sdhci-of-arasan: fix set_clock when a phy is
> supported")
> 84362d79f436 ("mmc: sdhci-of-arasan: Add CQHCI support for
> arasan,sdhci-5.1")
> 89211418cb71 ("mmc: sdhci-of-arasan: use sdhci_pltfm_init for private
> allocation")
> 91aa366109e8 ("mmc: sdhci-of-arasan: add phy support for sdhci-of-arasan")
> a05c84651145 ("mmc: sdhci-of-arasan: implement enhanced strobe callback")
> c390f2110adf ("mmc: sdhci-of-arasan: Add ability to export card clock")
> ca572f4636aa ("mmc: sdhci-of-arasan: Always power the PHY off/on when
> clock changes")
> f0061fed1f8a ("mmc: sdhci-of-arasan: Add Support for AM654 MMC and PHY")
>
>
> How should we proceed with this patch?
>
Thanks,
Faiz
[PATCH v3 0/3] Fix issues with phy configurations in am65x MMC driver
The following patches fix issues with phy configurations for sdhci_am654 driver. v3: Changed order of patches so that the first one can be applied easily to stable tree. v2: 1. Split patch 1 into 2 separate patches. 2. Improved patch descriptions. Faiz Abbas (3): mmc: sdhci_am654: Fix SLOTTYPE write mmc: sdhci_am654: Improve whitespace utilisation with regmap_*() calls mmc: sdhci_am654: Print error message if the DLL fails to lock drivers/mmc/host/sdhci_am654.c | 37 -- 1 file changed, 17 insertions(+), 20 deletions(-) -- 2.19.2
[PATCH v3 2/3] mmc: sdhci_am654: Improve whitespace utilisation with regmap_*() calls
Line wrapping with the regmap_*() functions is way more conservative
than required by the 80 character rule. Expand the function calls out to
use less number of lines.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 34 +-
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 3222ea4d584d..3c32d9fb6e1e 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -88,8 +88,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
int ret;
if (sdhci_am654->dll_on) {
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- ENDLL_MASK, 0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
sdhci_am654->dll_on = false;
}
@@ -101,8 +100,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
val = (1 << OTAPDLYENA_SHIFT) |
(sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
- regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
switch (clock) {
case 2:
sel50 = 0;
@@ -120,8 +118,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
/* Configure PHY DLL frequency */
mask = SEL50_MASK | SEL100_MASK;
val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
- regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
/* Configure DLL TRIM */
mask = DLL_TRIM_ICP_MASK;
val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
@@ -129,20 +126,17 @@ static void sdhci_am654_set_clock(struct sdhci_host
*host, unsigned int clock)
/* Configure DLL driver strength */
mask |= DR_TY_MASK;
val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
/* Enable DLL */
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- ENDLL_MASK, 0x1 << ENDLL_SHIFT);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
+ 0x1 << ENDLL_SHIFT);
/*
* Poll for DLL ready. Use a one second timeout.
* Works in all experiments done so far
*/
- ret = regmap_read_poll_timeout(sdhci_am654->base,
-PHY_STAT1, val,
-val & DLLRDY_MASK,
-1000, 100);
-
+ ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
+ val, val & DLLRDY_MASK, 1000,
+ 100);
sdhci_am654->dll_on = true;
}
}
@@ -208,8 +202,7 @@ static int sdhci_am654_init(struct sdhci_host *host)
/* Reset OTAP to default value */
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
- regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
- mask, 0x0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
regmap_read(sdhci_am654->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
@@ -223,15 +216,14 @@ static int sdhci_am654_init(struct sdhci_host *host)
}
/* Enable pins by setting IO mux to 0 */
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- IOMUX_ENABLE_MASK, 0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
/* Set slot type based on SD or eMMC */
if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
ctl_cfg_2 = SLOTTYPE_EMBEDDED;
- regmap_update_bits(sdhci_am654->base, CTL_CFG_2,
- SLOTTYPE_MASK, ctl_cfg_2);
+ regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK,
+ ctl_cfg_2);
return sdhci_add_host(host);
}
--
2.19.2
[PATCH v3 1/3] mmc: sdhci_am654: Fix SLOTTYPE write
In the call to regmap_update_bits() for SLOTTYPE, the mask and value fields are exchanged. Fix this. Signed-off-by: Faiz Abbas Cc: stable --- drivers/mmc/host/sdhci_am654.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index a91c0b45c48d..3222ea4d584d 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -231,7 +231,7 @@ static int sdhci_am654_init(struct sdhci_host *host) ctl_cfg_2 = SLOTTYPE_EMBEDDED; regmap_update_bits(sdhci_am654->base, CTL_CFG_2, - ctl_cfg_2, SLOTTYPE_MASK); + SLOTTYPE_MASK, ctl_cfg_2); return sdhci_add_host(host); } -- 2.19.2
[PATCH v3 3/3] mmc: sdhci_am654: Print error message if the DLL fails to lock
Print an error message and return if DLL fails to lock.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 3c32d9fb6e1e..d0b20780dd0f 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -137,6 +137,11 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
val, val & DLLRDY_MASK, 1000,
100);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
+ return;
+ }
+
sdhci_am654->dll_on = true;
}
}
--
2.19.2
Re: [PATCH v2 3/3] mmc: sdhci_am654: Fix SLOTTYPE write
Hi Adrian, On 10/05/19 11:28 AM, Adrian Hunter wrote: > On 10/05/19 6:42 AM, Faiz Abbas wrote: >> In the call to regmap_update_bits() for SLOTTYPE, the mask and value >> fields are exchanged. Fix this. This didn't have any affect on the >> driver because this was a NOP and it was taking the correct value from >> the bootloader. >> >> Cc: stable > > Except that it doesn't apply to stable because of patch 1. Maybe make this > the first patch. > Ok. Sending v3 with this as first patch. Thanks, Faiz
[PATCH v2 2/3] mmc: sdhci_am654: Print error message if the DLL fails to lock
Print an error message and return if DLL fails to lock.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index 337c24b8f4a8..3ff949925127 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -137,6 +137,11 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
val, val & DLLRDY_MASK, 1000,
100);
+ if (ret) {
+ dev_err(mmc_dev(host->mmc), "DLL failed to relock\n");
+ return;
+ }
+
sdhci_am654->dll_on = true;
}
}
--
2.19.2
[PATCH v2 0/3] Fix issues with phy configurations in am65x MMC driver
The following patches fix issues with phy configurations for sdhci_am654 driver. v2: 1. Split patch 1 into 2 separate patches. 2. Improved patch descriptions. Faiz Abbas (3): mmc: sdhci_am654: Improve line wrapping with regmap_*() calls mmc: sdhci_am654: Print error message if the DLL fails to lock mmc: sdhci_am654: Fix SLOTTYPE write drivers/mmc/host/sdhci_am654.c | 37 -- 1 file changed, 17 insertions(+), 20 deletions(-) -- 2.19.2
[PATCH v2 3/3] mmc: sdhci_am654: Fix SLOTTYPE write
In the call to regmap_update_bits() for SLOTTYPE, the mask and value fields are exchanged. Fix this. This didn't have any affect on the driver because this was a NOP and it was taking the correct value from the bootloader. Cc: stable Signed-off-by: Faiz Abbas --- drivers/mmc/host/sdhci_am654.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 3ff949925127..d0b20780dd0f 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -227,8 +227,8 @@ static int sdhci_am654_init(struct sdhci_host *host) if (host->mmc->caps & MMC_CAP_NONREMOVABLE) ctl_cfg_2 = SLOTTYPE_EMBEDDED; - regmap_update_bits(sdhci_am654->base, CTL_CFG_2, ctl_cfg_2, - SLOTTYPE_MASK); + regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, + ctl_cfg_2); return sdhci_add_host(host); } -- 2.19.2
[PATCH v2 1/3] mmc: sdhci_am654: Improve line wrapping with regmap_*() calls
Line wrapping with the regmap_*() functions is way more conservative
than required by the 80 character rule. Expand the function calls out to
use less number of lines.
Signed-off-by: Faiz Abbas
---
drivers/mmc/host/sdhci_am654.c | 34 +-
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index a91c0b45c48d..337c24b8f4a8 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -88,8 +88,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
int ret;
if (sdhci_am654->dll_on) {
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- ENDLL_MASK, 0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0);
sdhci_am654->dll_on = false;
}
@@ -101,8 +100,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
val = (1 << OTAPDLYENA_SHIFT) |
(sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT);
- regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val);
switch (clock) {
case 2:
sel50 = 0;
@@ -120,8 +118,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host,
unsigned int clock)
/* Configure PHY DLL frequency */
mask = SEL50_MASK | SEL100_MASK;
val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
- regmap_update_bits(sdhci_am654->base, PHY_CTRL5,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val);
/* Configure DLL TRIM */
mask = DLL_TRIM_ICP_MASK;
val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT;
@@ -129,20 +126,17 @@ static void sdhci_am654_set_clock(struct sdhci_host
*host, unsigned int clock)
/* Configure DLL driver strength */
mask |= DR_TY_MASK;
val |= sdhci_am654->drv_strength << DR_TY_SHIFT;
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- mask, val);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val);
/* Enable DLL */
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- ENDLL_MASK, 0x1 << ENDLL_SHIFT);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK,
+ 0x1 << ENDLL_SHIFT);
/*
* Poll for DLL ready. Use a one second timeout.
* Works in all experiments done so far
*/
- ret = regmap_read_poll_timeout(sdhci_am654->base,
-PHY_STAT1, val,
-val & DLLRDY_MASK,
-1000, 100);
-
+ ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1,
+ val, val & DLLRDY_MASK, 1000,
+ 100);
sdhci_am654->dll_on = true;
}
}
@@ -208,8 +202,7 @@ static int sdhci_am654_init(struct sdhci_host *host)
/* Reset OTAP to default value */
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
- regmap_update_bits(sdhci_am654->base, PHY_CTRL4,
- mask, 0x0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0);
regmap_read(sdhci_am654->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
@@ -223,15 +216,14 @@ static int sdhci_am654_init(struct sdhci_host *host)
}
/* Enable pins by setting IO mux to 0 */
- regmap_update_bits(sdhci_am654->base, PHY_CTRL1,
- IOMUX_ENABLE_MASK, 0);
+ regmap_update_bits(sdhci_am654->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
/* Set slot type based on SD or eMMC */
if (host->mmc->caps & MMC_CAP_NONREMOVABLE)
ctl_cfg_2 = SLOTTYPE_EMBEDDED;
- regmap_update_bits(sdhci_am654->base, CTL_CFG_2,
- ctl_cfg_2, SLOTTYPE_MASK);
+ regmap_update_bits(sdhci_am654->base, CTL_CFG_2, ctl_cfg_2,
+ SLOTTYPE_MASK);
return sdhci_add_host(host);
}
--
2.19.2
Re: [PATCH 1/2] mmc: sdhci_am654: Fix minor phy configurations
Hi Adrian, On 26/04/19 11:20 AM, Adrian Hunter wrote: > On 25/04/19 6:57 PM, Faiz Abbas wrote: >> Fix the following minor things: >> >> 1. Line wrapping with the regmap_*() functions is way more conservative >> than required by the 80 character rule. Expand the function calls out to >> use less number of lines. >> >> 2. Add an error message if the DLL fails to lock. > > Please make the white space changes a separate patch. > > Also I would prefer not to use "fix" in the subject unless the patch fixes > driver behaviour. > Ok. Two different patches. No "fix" in the subject. Sending v2. Thanks, Faiz
Re: [PATCH 2/2] mmc: sdhci_am654: Fix SLOTTYPE write
Hi Adrian, On 26/04/19 11:30 AM, Adrian Hunter wrote: > On 25/04/19 6:57 PM, Faiz Abbas wrote: >> In the call to regmap_update_bits() for SLOTTYPE, the mask and value >> fields are exchanged. Fix this. > > Could you also comment on whether this has any known effect on the driver. > This call was basically a NOP but it was the correct way around in u-boot so it was just taking that value instead. No effect that was known to me. Found this out just by inspection. Thanks, Faiz
Re: [PATCH] ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
Hi Tony, On 02/05/19 7:50 PM, Tony Lindgren wrote: > * Faiz Abbas [190502 01:48]: >> If UHS speed modes are enabled, a compatible SD card switches down to >> 1.8V during enumeration. If after this a software reboot/crash takes >> place and on-chip ROM tries to enumerate the SD card, the difference in >> IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card. >> >> The fix for this is to have support for power cycling the card in >> hardware (with a PORz/soft-reset line causing a power cycle of the >> card). Since am571x-, am572x- and am574x-idk don't have this >> capability, disable voltage switching for these boards. >> >> The major effect of this is that the maximum supported speed >> mode is now high speed(50 MHz) down from SDR104(200 MHz). > > This sounds a bit urgent, does it also need a stable tag or is > it safe to apply against any earlier kernels? > This should be good to apply on any previous releases. Thanks, Faiz
[PATCH] ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
If UHS speed modes are enabled, a compatible SD card switches down to
1.8V during enumeration. If after this a software reboot/crash takes
place and on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.
The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the
card). Since am571x-, am572x- and am574x-idk don't have this
capability, disable voltage switching for these boards.
The major effect of this is that the maximum supported speed
mode is now high speed(50 MHz) down from SDR104(200 MHz).
Signed-off-by: Faiz Abbas
---
arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi
b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index f7bd26458915..42e433da79ec 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -420,6 +420,7 @@
vqmmc-supply = <&ldo1_reg>;
bus-width = <4>;
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; /* gpio 219 */
+ no-1-8-v;
};
&mmc2 {
--
2.19.2
Re: [PATCH] ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
Hi Tony, On 30/04/19 9:24 PM, Tony Lindgren wrote: > Hi, > > * Faiz Abbas [190429 23:09]: >> Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest >> dra76x data manual[1]. >> >> Also this particular pinctrl-array is using spaces instead of tabs for >> spacing between the values and the comments. Fix this as well. > > Is this needed as a fix or can this wait? > This is a fix. The new iodelay values will have better marginality and should prevent issues in corner cases. Thanks, Faiz
