RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
> -Original Message-
> From: Bin Meng
> Sent: 16 December 2020 11:36
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> devicetree ; open list:GPIO SUBSYSTEM g...@vger.kernel.org>; broo...@kernel.org; Greg Kroah-Hartman
> ; Albert Ou ;
> lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; Thierry Reding
> ; and...@lunn.ch; Peter Korsgaard
> ; Paul Walmsley ( Sifive)
> ; Palmer Dabbelt ; Rob
> Herring ; Bartosz Golaszewski
> ; Linus Walleij
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> Hi Yash,
>
> On Wed, Dec 16, 2020 at 1:24 PM Yash Shah
> wrote:
> >
> > > -Original Message-
> > > From: Bin Meng
> > > Sent: 10 December 2020 19:05
> > > To: Yash Shah
> > > Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> > > p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel > > ker...@vger.kernel.org>; linux-riscv
> > > ;
> > > devicetree ; open list:GPIO SUBSYSTEM
> > > ; broo...@kernel.org; Greg
> > > Kroah-Hartman ; Albert Ou
> > > ; lee.jo...@linaro.org;
> > > u.kleine-koe...@pengutronix.de; Thierry Reding
> > > ; and...@lunn.ch; Peter Korsgaard
> > > ; Paul Walmsley ( Sifive)
> > > ; Palmer Dabbelt ;
> Rob
> > > Herring ; Bartosz Golaszewski
> > > ; Linus Walleij
> > >
> > > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the
> > > SiFive FU740-
> > > C000 SoC
> > >
> > > [External Email] Do not click links or attachments unless you
> > > recognize the sender and know the content is safe
> > >
> > > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah
> wrote:
> > > >
> > > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is
> > > > built
> > >
> > > FU740-C000 Soc
> > >
> > > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > > >
> > > > This file is expected to grow as more device drivers are added to
> > > > the kernel.
> > > >
> > > > Signed-off-by: Yash Shah
> > > > ---
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > > +
> > > > 1 file changed, 293 insertions(+) create mode 100644
> > > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > >
> > > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > new file mode 100644
> > > > index 000..eeb4f8c3
> > > > --- /dev/null
> > > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > > @@ -0,0 +1,293 @@
> >
> > ...
> >
> > > > + plic0: interrupt-controller@c00 {
> > > > + #interrupt-cells = <1>;
> > > > + #address-cells = <0>;
> > > > + compatible = "sifive,fu540-c000-plic",
> > > > + "sifive,plic-1.0.0";
> > >
> > > I don't see bindings updated for FU740 PLIC, like
> > > "sifive,fu740-c000-plic"?
> >
> > That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
>
> Are there any driver changes for the drivers that have an updated
> fu640-c000-* bindings? I don't see them in the linux-riscv list.
Yes, they will be posted soon.
- Yash
>
> >
> > ...
> >
> > > > + eth0: ethernet@1009 {
> > > > + compatible = "sifive,fu540-c000-gem";
> > >
> > > "sifive,fu740-c000-gem"?
> > >
> >
> > Same reason as above.
> >
> > Thanks for your review.
>
> Regards,
> Bin
Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
Hi Yash,
On Wed, Dec 16, 2020 at 1:24 PM Yash Shah wrote:
>
> > -Original Message-
> > From: Bin Meng
> > Sent: 10 December 2020 19:05
> > To: Yash Shah
> > Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> > p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel > ker...@vger.kernel.org>; linux-riscv ;
> > devicetree ; open list:GPIO SUBSYSTEM > g...@vger.kernel.org>; broo...@kernel.org; Greg Kroah-Hartman
> > ; Albert Ou ;
> > lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; Thierry Reding
> > ; and...@lunn.ch; Peter Korsgaard
> > ; Paul Walmsley ( Sifive)
> > ; Palmer Dabbelt ; Rob
> > Herring ; Bartosz Golaszewski
> > ; Linus Walleij
> > Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> > FU740-
> > C000 SoC
> >
> > [External Email] Do not click links or attachments unless you recognize the
> > sender and know the content is safe
> >
> > On Tue, Dec 8, 2020 at 3:06 PM Yash Shah wrote:
> > >
> > > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
> >
> > FU740-C000 Soc
> >
> > > around the SiFIve U7 Core Complex and a TileLink interconnect.
> > >
> > > This file is expected to grow as more device drivers are added to the
> > > kernel.
> > >
> > > Signed-off-by: Yash Shah
> > > ---
> > > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > > +
> > > 1 file changed, 293 insertions(+)
> > > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > >
> > > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > new file mode 100644
> > > index 000..eeb4f8c3
> > > --- /dev/null
> > > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > > @@ -0,0 +1,293 @@
>
> ...
>
> > > + plic0: interrupt-controller@c00 {
> > > + #interrupt-cells = <1>;
> > > + #address-cells = <0>;
> > > + compatible = "sifive,fu540-c000-plic",
> > > + "sifive,plic-1.0.0";
> >
> > I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
>
> That's because it is not required. There won't be any difference in driver
> code for FU740 plic.
Are there any driver changes for the drivers that have an updated
fu640-c000-* bindings? I don't see them in the linux-riscv list.
>
> ...
>
> > > + eth0: ethernet@1009 {
> > > + compatible = "sifive,fu540-c000-gem";
> >
> > "sifive,fu740-c000-gem"?
> >
>
> Same reason as above.
>
> Thanks for your review.
Regards,
Bin
RE: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
> -Original Message-
> From: Bin Meng
> Sent: 10 December 2020 19:05
> To: Yash Shah
> Cc: linux-...@vger.kernel.org; linux-ser...@vger.kernel.org; linux-
> p...@vger.kernel.org; linux-...@vger.kernel.org; linux-kernel ker...@vger.kernel.org>; linux-riscv ;
> devicetree ; open list:GPIO SUBSYSTEM g...@vger.kernel.org>; broo...@kernel.org; Greg Kroah-Hartman
> ; Albert Ou ;
> lee.jo...@linaro.org; u.kleine-koe...@pengutronix.de; Thierry Reding
> ; and...@lunn.ch; Peter Korsgaard
> ; Paul Walmsley ( Sifive)
> ; Palmer Dabbelt ; Rob
> Herring ; Bartosz Golaszewski
> ; Linus Walleij
> Subject: Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive
> FU740-
> C000 SoC
>
> [External Email] Do not click links or attachments unless you recognize the
> sender and know the content is safe
>
> On Tue, Dec 8, 2020 at 3:06 PM Yash Shah wrote:
> >
> > Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
>
> FU740-C000 Soc
>
> > around the SiFIve U7 Core Complex and a TileLink interconnect.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Yash Shah
> > ---
> > arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> > +
> > 1 file changed, 293 insertions(+)
> > create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > new file mode 100644
> > index 000..eeb4f8c3
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> > @@ -0,0 +1,293 @@
...
> > + plic0: interrupt-controller@c00 {
> > + #interrupt-cells = <1>;
> > + #address-cells = <0>;
> > + compatible = "sifive,fu540-c000-plic",
> > + "sifive,plic-1.0.0";
>
> I don't see bindings updated for FU740 PLIC, like "sifive,fu740-c000-plic"?
That's because it is not required. There won't be any difference in driver code
for FU740 plic.
...
> > + eth0: ethernet@1009 {
> > + compatible = "sifive,fu540-c000-gem";
>
> "sifive,fu740-c000-gem"?
>
Same reason as above.
Thanks for your review.
- Yash
> > + interrupt-parent = <&plic0>;
> > + interrupts = <55>;
> > + reg = <0x0 0x1009 0x0 0x2000>,
> > + <0x0 0x100a 0x0 0x1000>;
> > + local-mac-address = [00 00 00 00 00 00];
> > + clock-names = "pclk", "hclk";
> > + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> > +<&prci PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > + pwm0: pwm@1002 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x1002 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <44>, <45>, <46>, <47>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + pwm1: pwm@10021000 {
> > + compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
> > + reg = <0x0 0x10021000 0x0 0x1000>;
> > + interrupt-parent = <&plic0>;
> > + interrupts = <48>, <49>, <50>, <51>;
> > + clocks = <&prci PRCI_CLK_PCLK>;
> > + #pwm-cells = <3>;
> > + status = "disabled";
> > + };
> > + ccache: cache-controller@201 {
> > + compatible = "sifive,fu740-c000-ccache", "cache";
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > +
Re: [PATCH v2 7/9] riscv: dts: add initial support for the SiFive FU740-C000 SoC
On Tue, Dec 8, 2020 at 3:06 PM Yash Shah wrote:
>
> Add initial support for the SiFive FU540-C000 SoC. FU740-C000 is built
FU740-C000 Soc
> around the SiFIve U7 Core Complex and a TileLink interconnect.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Yash Shah
> ---
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 293
> +
> 1 file changed, 293 insertions(+)
> create mode 100644 arch/riscv/boot/dts/sifive/fu740-c000.dtsi
>
> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> new file mode 100644
> index 000..eeb4f8c3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
> @@ -0,0 +1,293 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020 SiFive, Inc */
> +
> +/dts-v1/;
> +
> +#include
> +
> +/ {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "sifive,fu740-c000", "sifive,fu740";
> +
> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + ethernet0 = ð0;
> + };
> +
> + chosen {
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cpu0: cpu@0 {
> + compatible = "sifive,bullet0", "riscv";
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <16384>;
> + next-level-cache = <&ccache>;
> + reg = <0x0>;
> + riscv,isa = "rv64imac";
> + status = "disabled";
> + cpu0_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu1: cpu@1 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x1>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu1_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu2: cpu@2 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + reg = <0x2>;
> + riscv,isa = "rv64imafdc";
> + tlb-split;
> + cpu2_intc: interrupt-controller {
> + #interrupt-cells = <1>;
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + };
> + };
> + cpu3: cpu@3 {
> + compatible = "sifive,bullet0", "riscv";
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <32768>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <128>;
> + i-cache-size = <32768>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> +
