Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thu, Mar 30, 2017 at 05:37:41PM +0200, Olliver Schinagl wrote: > Hey Jon, > > On March 30, 2017 3:42:19 PM CEST, Jon Hunterwrote: > > > >On 29/03/17 19:48, Olliver Schinagl wrote: > >> The tegra serial IP seems to be following the common layout and the > >> interrupt ID's match up nicely. Replace the magic values to match the > >> common serial_reg defines, with the addition of the Tegra unique End > >of > >> Data interrupt. > >> > >> Signed-off-by: Olliver Schinagl > >> --- > >> Note I do not own any tegra hardware and just noticed it while > >working on my > >> somewhat related previous patch, > >> "serial: Do not treat the IIR register as a bitfield" > >> > >> As such, this patch can only be applied after the aforementioned > >patch or the > >> iir variable will not have its mask applied yet. > > > >Nit-pick. If this is the case, then this should really be part of a > >patch series so it is obvious to everyone that this should only be > >applied after the other patch. > Yes, and it was, but I did not want to have the really big list of names in > this much smaller group. Ok, this is a mess, don't send me patches that need to be applied in a specific order, yet are not obviously linked together in a single series. How do you expect a maintainer to handle this type of stuff? You need to make it _OBVIOUS_ as to what I need to do here, otherwise I will get it wrong. I'm going to drop all of your patches from my queue and wait for a resend with the correct order, and ones that work properly, you can do better than this :) thanks, greg k-h
Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thu, Mar 30, 2017 at 05:37:41PM +0200, Olliver Schinagl wrote: > Hey Jon, > > On March 30, 2017 3:42:19 PM CEST, Jon Hunter wrote: > > > >On 29/03/17 19:48, Olliver Schinagl wrote: > >> The tegra serial IP seems to be following the common layout and the > >> interrupt ID's match up nicely. Replace the magic values to match the > >> common serial_reg defines, with the addition of the Tegra unique End > >of > >> Data interrupt. > >> > >> Signed-off-by: Olliver Schinagl > >> --- > >> Note I do not own any tegra hardware and just noticed it while > >working on my > >> somewhat related previous patch, > >> "serial: Do not treat the IIR register as a bitfield" > >> > >> As such, this patch can only be applied after the aforementioned > >patch or the > >> iir variable will not have its mask applied yet. > > > >Nit-pick. If this is the case, then this should really be part of a > >patch series so it is obvious to everyone that this should only be > >applied after the other patch. > Yes, and it was, but I did not want to have the really big list of names in > this much smaller group. Ok, this is a mess, don't send me patches that need to be applied in a specific order, yet are not obviously linked together in a single series. How do you expect a maintainer to handle this type of stuff? You need to make it _OBVIOUS_ as to what I need to do here, otherwise I will get it wrong. I'm going to drop all of your patches from my queue and wait for a resend with the correct order, and ones that work properly, you can do better than this :) thanks, greg k-h
Re: [PATCH] serial: tegra: Map the iir register to default defines
Hey Shadar, On 31-03-17 12:42, Shardar Mohammed wrote: On 31/03/17 11:07, Shardar Mohammed wrote: Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK; Per Olliver's original email did you pick up the other patch [0] before applying this because that does apply the mask. I mentioned to Olliver that this should really be a series, so it is clear that this patch is dependent upon the other. For UART_IIR_MASK macro, dependent patch is required if we add this required line. But here to fix the issue with the current patch above masking step is necessary. Yeah the other big patch adds this line (and does some other fixes to the tegra driver with regards to the UART_IIR_MASK). I did not make it a 'set' because the other patch has a big big list of names and touches a lot of serial devices. So both 'groups' would get a lot of noise. I'm sorry if this caused confusion. If you guys prefer, I'll turn it into a set. Again, sorry for the inconvenience, Olliver -Original Message- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl <oli...@schinagl.nl>; Greg Kroah-Hartman <gre...@linuxfoundation.org>; Jiri Slaby <jsl...@suse.com>; Stephen Warren <swar...@wwwdotorg.org>; Thierry Reding <thierry.red...@gmail.com>; Alexandre Courbot <gnu...@gmail.com> Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed <smoham...@nvidia.com> Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: The tegra serial IP seems to be following the common layout and the interrupt ID's match up nicely. Replace the magic values to match the common serial_reg defines, with the addition of the Tegra unique End of Data interrupt. Signed-off-by: Olliver Schinagl <oli...@schinagl.nl> --- Adding Shardar for verifications. Acked-by: Laxman Dewangan <ldewan...@nvidia.com> Furthermore does this ACK imply that you have reviewed the other patch this one is dependent upon? Yes dependent change looks fine, but I have not tested it. Cheers Jon [0] http://marc.info/?l=linux-serial=149081309627392=2 -- nvpublic
Re: [PATCH] serial: tegra: Map the iir register to default defines
Hey Shadar, On 31-03-17 12:42, Shardar Mohammed wrote: On 31/03/17 11:07, Shardar Mohammed wrote: Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK; Per Olliver's original email did you pick up the other patch [0] before applying this because that does apply the mask. I mentioned to Olliver that this should really be a series, so it is clear that this patch is dependent upon the other. For UART_IIR_MASK macro, dependent patch is required if we add this required line. But here to fix the issue with the current patch above masking step is necessary. Yeah the other big patch adds this line (and does some other fixes to the tegra driver with regards to the UART_IIR_MASK). I did not make it a 'set' because the other patch has a big big list of names and touches a lot of serial devices. So both 'groups' would get a lot of noise. I'm sorry if this caused confusion. If you guys prefer, I'll turn it into a set. Again, sorry for the inconvenience, Olliver -Original Message- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl ; Greg Kroah-Hartman ; Jiri Slaby ; Stephen Warren ; Thierry Reding ; Alexandre Courbot Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: The tegra serial IP seems to be following the common layout and the interrupt ID's match up nicely. Replace the magic values to match the common serial_reg defines, with the addition of the Tegra unique End of Data interrupt. Signed-off-by: Olliver Schinagl --- Adding Shardar for verifications. Acked-by: Laxman Dewangan Furthermore does this ACK imply that you have reviewed the other patch this one is dependent upon? Yes dependent change looks fine, but I have not tested it. Cheers Jon [0] http://marc.info/?l=linux-serial=149081309627392=2 -- nvpublic
RE: [PATCH] serial: tegra: Map the iir register to default defines
> On 31/03/17 11:07, Shardar Mohammed wrote: > > Verification failed on Tegra. > > Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR > register as on Tegra bit-6 is used for internal usage to know if FIFO mode is > enabled. > > while (1) { > > iir = tegra_uart_read(tup, UART_IIR); > > +iir &= UART_IIR_MASK; > > Per Olliver's original email did you pick up the other patch [0] before > applying > this because that does apply the mask. I mentioned to Olliver that this should > really be a series, so it is clear that this patch is dependent upon the > other. For UART_IIR_MASK macro, dependent patch is required if we add this required line. But here to fix the issue with the current patch above masking step is necessary. > > > -Original Message- > > From: Laxman Dewangan > > Sent: Thursday, March 30, 2017 3:48 PM > > To: Olliver Schinagl <oli...@schinagl.nl>; Greg Kroah-Hartman > > <gre...@linuxfoundation.org>; Jiri Slaby <jsl...@suse.com>; Stephen > > Warren <swar...@wwwdotorg.org>; Thierry Reding > > <thierry.red...@gmail.com>; Alexandre Courbot <gnu...@gmail.com> > > Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; > > linux-kernel@vger.kernel.org; Shardar Mohammed > <smoham...@nvidia.com> > > Subject: Re: [PATCH] serial: tegra: Map the iir register to default > > defines > > > > > > On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > >> The tegra serial IP seems to be following the common layout and the > >> interrupt ID's match up nicely. Replace the magic values to match the > >> common serial_reg defines, with the addition of the Tegra unique End > >> of Data interrupt. > >> > >> Signed-off-by: Olliver Schinagl <oli...@schinagl.nl> > >> --- > > > > Adding Shardar for verifications. > > > > Acked-by: Laxman Dewangan <ldewan...@nvidia.com> > > Furthermore does this ACK imply that you have reviewed the other patch this > one is dependent upon? > Yes dependent change looks fine, but I have not tested it. > Cheers > Jon > > [0] http://marc.info/?l=linux-serial=149081309627392=2 > > -- > nvpublic
RE: [PATCH] serial: tegra: Map the iir register to default defines
> On 31/03/17 11:07, Shardar Mohammed wrote: > > Verification failed on Tegra. > > Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR > register as on Tegra bit-6 is used for internal usage to know if FIFO mode is > enabled. > > while (1) { > > iir = tegra_uart_read(tup, UART_IIR); > > +iir &= UART_IIR_MASK; > > Per Olliver's original email did you pick up the other patch [0] before > applying > this because that does apply the mask. I mentioned to Olliver that this should > really be a series, so it is clear that this patch is dependent upon the > other. For UART_IIR_MASK macro, dependent patch is required if we add this required line. But here to fix the issue with the current patch above masking step is necessary. > > > -Original Message- > > From: Laxman Dewangan > > Sent: Thursday, March 30, 2017 3:48 PM > > To: Olliver Schinagl ; Greg Kroah-Hartman > > ; Jiri Slaby ; Stephen > > Warren ; Thierry Reding > > ; Alexandre Courbot > > Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; > > linux-kernel@vger.kernel.org; Shardar Mohammed > > > Subject: Re: [PATCH] serial: tegra: Map the iir register to default > > defines > > > > > > On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > >> The tegra serial IP seems to be following the common layout and the > >> interrupt ID's match up nicely. Replace the magic values to match the > >> common serial_reg defines, with the addition of the Tegra unique End > >> of Data interrupt. > >> > >> Signed-off-by: Olliver Schinagl > >> --- > > > > Adding Shardar for verifications. > > > > Acked-by: Laxman Dewangan > > Furthermore does this ACK imply that you have reviewed the other patch this > one is dependent upon? > Yes dependent change looks fine, but I have not tested it. > Cheers > Jon > > [0] http://marc.info/?l=linux-serial=149081309627392=2 > > -- > nvpublic
Re: [PATCH] serial: tegra: Map the iir register to default defines
On 31/03/17 11:07, Shardar Mohammed wrote: > Verification failed on Tegra. > Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR > register as on Tegra bit-6 is used for internal usage to know if FIFO mode is > enabled. > while (1) { > iir = tegra_uart_read(tup, UART_IIR); >+iir &= UART_IIR_MASK; Per Olliver's original email did you pick up the other patch [0] before applying this because that does apply the mask. I mentioned to Olliver that this should really be a series, so it is clear that this patch is dependent upon the other. > -Original Message- > From: Laxman Dewangan > Sent: Thursday, March 30, 2017 3:48 PM > To: Olliver Schinagl <oli...@schinagl.nl>; Greg Kroah-Hartman > <gre...@linuxfoundation.org>; Jiri Slaby <jsl...@suse.com>; Stephen Warren > <swar...@wwwdotorg.org>; Thierry Reding <thierry.red...@gmail.com>; Alexandre > Courbot <gnu...@gmail.com> > Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; > linux-kernel@vger.kernel.org; Shardar Mohammed <smoham...@nvidia.com> > Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines > > > On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: >> The tegra serial IP seems to be following the common layout and the >> interrupt ID's match up nicely. Replace the magic values to match the >> common serial_reg defines, with the addition of the Tegra unique End >> of Data interrupt. >> >> Signed-off-by: Olliver Schinagl <oli...@schinagl.nl> >> --- > > Adding Shardar for verifications. > > Acked-by: Laxman Dewangan <ldewan...@nvidia.com> Furthermore does this ACK imply that you have reviewed the other patch this one is dependent upon? Cheers Jon [0] http://marc.info/?l=linux-serial=149081309627392=2 -- nvpublic
Re: [PATCH] serial: tegra: Map the iir register to default defines
On 31/03/17 11:07, Shardar Mohammed wrote: > Verification failed on Tegra. > Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR > register as on Tegra bit-6 is used for internal usage to know if FIFO mode is > enabled. > while (1) { > iir = tegra_uart_read(tup, UART_IIR); >+iir &= UART_IIR_MASK; Per Olliver's original email did you pick up the other patch [0] before applying this because that does apply the mask. I mentioned to Olliver that this should really be a series, so it is clear that this patch is dependent upon the other. > -Original Message- > From: Laxman Dewangan > Sent: Thursday, March 30, 2017 3:48 PM > To: Olliver Schinagl ; Greg Kroah-Hartman > ; Jiri Slaby ; Stephen Warren > ; Thierry Reding ; Alexandre > Courbot > Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; > linux-kernel@vger.kernel.org; Shardar Mohammed > Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines > > > On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: >> The tegra serial IP seems to be following the common layout and the >> interrupt ID's match up nicely. Replace the magic values to match the >> common serial_reg defines, with the addition of the Tegra unique End >> of Data interrupt. >> >> Signed-off-by: Olliver Schinagl >> --- > > Adding Shardar for verifications. > > Acked-by: Laxman Dewangan Furthermore does this ACK imply that you have reviewed the other patch this one is dependent upon? Cheers Jon [0] http://marc.info/?l=linux-serial=149081309627392=2 -- nvpublic
RE: [PATCH] serial: tegra: Map the iir register to default defines
Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK; Thanks, Shardar -Original Message- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl <oli...@schinagl.nl>; Greg Kroah-Hartman <gre...@linuxfoundation.org>; Jiri Slaby <jsl...@suse.com>; Stephen Warren <swar...@wwwdotorg.org>; Thierry Reding <thierry.red...@gmail.com>; Alexandre Courbot <gnu...@gmail.com> Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed <smoham...@nvidia.com> Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End > of Data interrupt. > > Signed-off-by: Olliver Schinagl <oli...@schinagl.nl> > --- Adding Shardar for verifications. Acked-by: Laxman Dewangan <ldewan...@nvidia.com>
RE: [PATCH] serial: tegra: Map the iir register to default defines
Verification failed on Tegra. Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled. while (1) { iir = tegra_uart_read(tup, UART_IIR); +iir &= UART_IIR_MASK; Thanks, Shardar -Original Message- From: Laxman Dewangan Sent: Thursday, March 30, 2017 3:48 PM To: Olliver Schinagl ; Greg Kroah-Hartman ; Jiri Slaby ; Stephen Warren ; Thierry Reding ; Alexandre Courbot Cc: linux-ser...@vger.kernel.org; linux-te...@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End > of Data interrupt. > > Signed-off-by: Olliver Schinagl > --- Adding Shardar for verifications. Acked-by: Laxman Dewangan
Re: [PATCH] serial: tegra: Map the iir register to default defines
Hey Jon, On March 30, 2017 3:42:19 PM CEST, Jon Hunterwrote: > >On 29/03/17 19:48, Olliver Schinagl wrote: >> The tegra serial IP seems to be following the common layout and the >> interrupt ID's match up nicely. Replace the magic values to match the >> common serial_reg defines, with the addition of the Tegra unique End >of >> Data interrupt. >> >> Signed-off-by: Olliver Schinagl >> --- >> Note I do not own any tegra hardware and just noticed it while >working on my >> somewhat related previous patch, >> "serial: Do not treat the IIR register as a bitfield" >> >> As such, this patch can only be applied after the aforementioned >patch or the >> iir variable will not have its mask applied yet. > >Nit-pick. If this is the case, then this should really be part of a >patch series so it is obvious to everyone that this should only be >applied after the other patch. Yes, and it was, but I did not want to have the really big list of names in this much smaller group. > >Cheers >Jon -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
Re: [PATCH] serial: tegra: Map the iir register to default defines
Hey Jon, On March 30, 2017 3:42:19 PM CEST, Jon Hunter wrote: > >On 29/03/17 19:48, Olliver Schinagl wrote: >> The tegra serial IP seems to be following the common layout and the >> interrupt ID's match up nicely. Replace the magic values to match the >> common serial_reg defines, with the addition of the Tegra unique End >of >> Data interrupt. >> >> Signed-off-by: Olliver Schinagl >> --- >> Note I do not own any tegra hardware and just noticed it while >working on my >> somewhat related previous patch, >> "serial: Do not treat the IIR register as a bitfield" >> >> As such, this patch can only be applied after the aforementioned >patch or the >> iir variable will not have its mask applied yet. > >Nit-pick. If this is the case, then this should really be part of a >patch series so it is obvious to everyone that this should only be >applied after the other patch. Yes, and it was, but I did not want to have the really big list of names in this much smaller group. > >Cheers >Jon -- Sent from my Android device with K-9 Mail. Please excuse my brevity.
Re: [PATCH] serial: tegra: Map the iir register to default defines
On 29/03/17 19:48, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End of > Data interrupt. > > Signed-off-by: Olliver Schinagl> --- > Note I do not own any tegra hardware and just noticed it while working on my > somewhat related previous patch, > "serial: Do not treat the IIR register as a bitfield" > > As such, this patch can only be applied after the aforementioned patch or the > iir variable will not have its mask applied yet. Nit-pick. If this is the case, then this should really be part of a patch series so it is obvious to everyone that this should only be applied after the other patch. Cheers Jon -- nvpublic
Re: [PATCH] serial: tegra: Map the iir register to default defines
On 29/03/17 19:48, Olliver Schinagl wrote: > The tegra serial IP seems to be following the common layout and the > interrupt ID's match up nicely. Replace the magic values to match the > common serial_reg defines, with the addition of the Tegra unique End of > Data interrupt. > > Signed-off-by: Olliver Schinagl > --- > Note I do not own any tegra hardware and just noticed it while working on my > somewhat related previous patch, > "serial: Do not treat the IIR register as a bitfield" > > As such, this patch can only be applied after the aforementioned patch or the > iir variable will not have its mask applied yet. Nit-pick. If this is the case, then this should really be part of a patch series so it is obvious to everyone that this should only be applied after the other patch. Cheers Jon -- nvpublic
Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: The tegra serial IP seems to be following the common layout and the interrupt ID's match up nicely. Replace the magic values to match the common serial_reg defines, with the addition of the Tegra unique End of Data interrupt. Signed-off-by: Olliver Schinagl--- Adding Shardar for verifications. Acked-by: Laxman Dewangan
Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote: The tegra serial IP seems to be following the common layout and the interrupt ID's match up nicely. Replace the magic values to match the common serial_reg defines, with the addition of the Tegra unique End of Data interrupt. Signed-off-by: Olliver Schinagl --- Adding Shardar for verifications. Acked-by: Laxman Dewangan