Re: [PATCH 02/25] OMAP4: Redefine mandatory barriers for OMAP to include interconnect barriers.
On Wed, Sep 14, 2011 at 1:57 AM, Tony Lindgren wrote: > * Santosh Shilimkar [110904 06:22]: >> On OMAP4 SOC intecronnects has many write buffers in the async bridges >> and they can be drained only with stongly ordered accesses. > > This is not correct, strongly ordered access does not guarantee > anything here. If it fixes issues, it's because it makes the writes > to reach the device faster. Strongly ordered does not affect anything > outside ARM, so the bus access won't change. > > The only real fix here is to do a read back of the device in question > to guarantee the write got to the device. > >> There are two ports as below from MPU and both needs to be drained. >> - MPU --> L3 T2ASYNC FIFO >> - MPU --> DDR T2ASYNC FIFO >> >> Without the interconnect barriers, many issues have been observed >> leading to system freeze, CPU deadlocks, random crashes with >> register accesses, synchronization loss on initiators operating >> on both interconnect port simultaneously. > > We had these issues for omap3 too. Adding a few read backs solved > those kinds of issues. > No. Don't mix things. OMAP3 behaviour is a interconnect level and it was single interconnect channel. The issue here is a BUG in the asynchronous bridges and OMAp4 has two separate channels at interconnect level form MPU side as mentioned above. Both of these patches I have passed it through Russell and Caralin before including them here. Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/25] ARM: mm: Add strongly ordered descriptor support.
On Wed, Sep 14, 2011 at 1:53 AM, Tony Lindgren wrote: > * Santosh Shilimkar [110904 06:22]: >> On certain architectures, there might be a need to mark certain >> addresses with strongly ordered memory attributes to avoid ordering >> issues at the interconnect level. > > This is something Russell needs to look. > > You might want to also read the mailing list archives regarding the > strongly ordered access. > > Basically it still won't guarantee that the write gets to the > device, only a read back from the device in question guarantees > that at the bus level. > Russell has already seen this. I have sent this patches to Russell before adding them in the queue. This is different. There is a BUG in asynchronous bridges on OMAP44XX devices and that's the reason it' s needed. Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 13/25] OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extn
Tony, On Wed, Sep 14, 2011 at 2:06 AM, Tony Lindgren wrote: > * Santosh Shilimkar [110904 06:23]: >> OMAP WakeupGen is the interrupt controller extension used along >> with ARM GIC to wake the CPU out from low power states on >> external interrupts. >> >> The WakeupGen unit is responsible for generating wakeup event >> from the incoming interrupts and enable bits. It is implemented >> in MPU always ON power domain. During normal operation, >> WakeupGen delivers external interrupts directly to the GIC. > ... > >> + /* >> + * Override GIC architecture specific functions to add >> + * OMAP WakeupGen interrupt controller along with GIC >> + */ >> + gic_arch_extn.irq_mask = wakeupgen_mask; >> + gic_arch_extn.irq_unmask = wakeupgen_unmask; >> + gic_arch_extn.irq_set_wake = wakeupgen_set_wake; >> + gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; > > As I've commented before, there should not be any need to tweak > the wakeupgen registers for each interrupt during the runtime. > And I gave you all the reasons why it needs to be done this way. > AFAIK the wakeupgen registers only need to be armed every time > before entering idle. > No that doesn't work and it completely hacky approach. This problem is for all SOC's using A9 SMP and GIC and every soc has an architecture specific interrupt controller extension. And that was the reason the GIC arch_extn was proposed. It's just another IRQCHIP and works seamlessly being part of the framework. And it will also initialized with primary IRQCHIP( GIC). Regards Santosh -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCHv2 09/15] OMAP: DSS2: HDMI: implement detect()
Hi,
On Mon, Sep 12, 2011 at 10:16 PM, Rob Clark wrote:
> On Mon, Sep 12, 2011 at 8:24 AM, K, Mythri P wrote:
>>> +bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
>>> +{
>>> + int r;
>>> +
>>> + void __iomem *base = hdmi_core_sys_base(ip_data);
>>> +
>>> + /* HPD */
>>> + r = REG_GET(base, HDMI_CORE_SYS_SYS_STAT, 1, 1);
>>> +
>>> + return r == 1;
>>> +}
>>> +
>> For HPD the probe should also be on the core interrupt first , and the
>> detect should be dynamic, ie based on the cable connect and disconnect
>> event.So this approach for HPD is not really the way.
>> Also that should be based on the GPIO(63) , I am planning to push a
>> patch on that shortly.
>
>
> Fwiw, we do still need a dssdrv->detect() function from omapdrm
> driver.. if there is another way to implement that function, such as
> with a GPIO, that is great. But somehow or another we need the detect
> function. The implementation can always change later.
Yes we still need a detect , but the implementation would be different
, from the prior experience with the Hot-plug detection it wad found
that the interrupt based way to handle HPD was not the best ,but if
this is just to poll the status then it should be fine.
>
> BR,
> -R
>
Thanks and regards,
Mythri.
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Re: [PATCH 14/25] OMAP4: PM: Add CPUX OFF mode support
On Tue, Sep 13, 2011 at 11:03 PM, Kevin Hilman wrote:
> Santosh writes:
>
>> On Tuesday 13 September 2011 02:36 AM, Kevin Hilman wrote:
>>> Santosh Shilimkar writes:
>>>
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
retention (CSWR) is not supported by hardware design.
The CPUx OFF mode isn't supported on OMAP4430 ES1.0
CPUx sleep code is common for hotplug, suspend and CPUilde.
Signed-off-by: Santosh Shilimkar
Cc: Kevin Hilman
>>>
>>> [...]
>>>
@@ -38,6 +39,11 @@ void __iomem *omap4_get_scu_base(void)
void __cpuinit platform_secondary_init(unsigned int cpu)
{
+ /* Enable NS access to SMP bit for this CPU on EMU/HS devices */
+ if (cpu_is_omap443x()&& (omap_type() != OMAP2_DEVICE_TYPE_GP))
>>>
>>> A comment here about why this is 443x specific would be helpful.
>>>
>>> I see a comment in omap4_cpu_resume() that seems to indicate that SMP
>>> bit is accessible on 446x NS devices, but repeating that commen here
>>> would help future readability.
>>>
>> Ok. Will add comments here too. Was just trying to save some lines :)
>
> heh, this is a negative side-effect of people caring primarily about
> diffstat. :(
>
ya.
> One other comment on this patch. You need spaces around the '&&' above.
>
The original patch is fine for that. Some replies has eaten that space. My
Thunderbird email client is doing the same. :(
Regards
Santosh
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Re: [PATCH v2 5/6] iommu/intel: announce supported page sizes
On Wed, Sep 14, 2011 at 12:32 AM, David Woodhouse wrote: > On Tue, 2011-09-13 at 22:31 +0300, Ohad Ben-Cohen wrote: >> + * Traditionally the IOMMU core just handed us the mappings directly, >> + * after making sure the size is an order of a 4KB page and that the >> + * mapping has natural alignment. >> + * >> + * To retain this behavior, we currently advertise that we support >> + * all page sizes that are an order of 4KB. > > This is wrong. We do not support 4000-byte pages. We only support > 4096-byte pages. 4KiB, not 4kB. > > Please fix. Sure thing; I'll s/KB/KiB throughout the patch set. Do I have your ACK otherwise ? Thanks, Ohad. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v15 11/12] OMAP: dmtimer: extend spinlock to exported APIs
On Wed, Sep 14, 2011 at 4:45 AM, Tony Lindgren wrote:
> * Tarun Kanti DebBarma [110908 13:36]:
>> Since the exported APIs can be called from interrupt context
>> extend spinlock protection to some more relevant APIs to avoid
>> race condition.
>
> We should have locking for requesting and releasing a timer etc,
> but I don't see need for that for the timer specific functions.
Alright... I will remove locking from timer specific functions.
In that case we have extension of locks to just following two functions:
omap_dm_timer_request()
omap_dm_timer_request_specific()
So, I can modify the patch subject and description accordingly.
>
>> @@ -317,9 +317,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
>> void omap_dm_timer_start(struct omap_dm_timer *timer)
>> {
>> u32 l;
>> + unsigned long flags;
>>
>> omap_dm_timer_enable(timer);
>>
>> + spin_lock_irqsave(&dm_timer_lock, flags);
>> if (timer->loses_context) {
>> u32 ctx_loss_cnt_after =
>> timer->get_context_loss_count(&timer->pdev->dev);
>
> Here the caller already owns the timer being started. So there
> should never be multiple users for a single timer. If there are,
> then the caller should take care of locking.
Ok.
>
>> void omap_dm_timer_stop(struct omap_dm_timer *timer)
>> {
>> - unsigned long rate = 0;
>> + unsigned long rate = 0, flags;
>> struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
>> bool is_omap2 = true;
>>
>> + spin_lock_irqsave(&dm_timer_lock, flags);
>> if (pdata->needs_manual_reset)
>> is_omap2 = false;
>> else
>
> Here too.
Right.
>
>> @@ -389,8 +394,10 @@ void omap_dm_timer_set_load(struct omap_dm_timer
>> *timer, int autoreload,
>> unsigned int load)
>> {
>> u32 l;
>> + unsigned long flags;
>>
>> omap_dm_timer_enable(timer);
>> + spin_lock_irqsave(&dm_timer_lock, flags);
>> l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
>> if (autoreload)
>> l |= OMAP_TIMER_CTRL_AR;
>
> And here.
Ok.
>
>> @@ -412,9 +420,11 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer
>> *timer, int autoreload,
>> unsigned int load)
>> {
>> u32 l;
>> + unsigned long flags;
>>
>> omap_dm_timer_enable(timer);
>>
>> + spin_lock_irqsave(&dm_timer_lock, flags);
>> if (timer->loses_context) {
>> u32 ctx_loss_cnt_after =
>> timer->get_context_loss_count(&timer->pdev->dev);
>
> Not needed here either. And that's the case for all the other functions
> too.
Sure.
--
Tarun
>
> Regards,
>
> Tony
>
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Re: [PATCH v15 11/12] OMAP: dmtimer: extend spinlock to exported APIs
* Tarun Kanti DebBarma [110908 13:36]:
> Since the exported APIs can be called from interrupt context
> extend spinlock protection to some more relevant APIs to avoid
> race condition.
We should have locking for requesting and releasing a timer etc,
but I don't see need for that for the timer specific functions.
> @@ -317,9 +317,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
> void omap_dm_timer_start(struct omap_dm_timer *timer)
> {
> u32 l;
> + unsigned long flags;
>
> omap_dm_timer_enable(timer);
>
> + spin_lock_irqsave(&dm_timer_lock, flags);
> if (timer->loses_context) {
> u32 ctx_loss_cnt_after =
> timer->get_context_loss_count(&timer->pdev->dev);
Here the caller already owns the timer being started. So there
should never be multiple users for a single timer. If there are,
then the caller should take care of locking.
> void omap_dm_timer_stop(struct omap_dm_timer *timer)
> {
> - unsigned long rate = 0;
> + unsigned long rate = 0, flags;
> struct dmtimer_platform_data *pdata = timer->pdev->dev.platform_data;
> bool is_omap2 = true;
>
> + spin_lock_irqsave(&dm_timer_lock, flags);
> if (pdata->needs_manual_reset)
> is_omap2 = false;
> else
Here too.
> @@ -389,8 +394,10 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer,
> int autoreload,
> unsigned int load)
> {
> u32 l;
> + unsigned long flags;
>
> omap_dm_timer_enable(timer);
> + spin_lock_irqsave(&dm_timer_lock, flags);
> l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> if (autoreload)
> l |= OMAP_TIMER_CTRL_AR;
And here.
> @@ -412,9 +420,11 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer
> *timer, int autoreload,
> unsigned int load)
> {
> u32 l;
> + unsigned long flags;
>
> omap_dm_timer_enable(timer);
>
> + spin_lock_irqsave(&dm_timer_lock, flags);
> if (timer->loses_context) {
> u32 ctx_loss_cnt_after =
> timer->get_context_loss_count(&timer->pdev->dev);
Not needed here either. And that's the case for all the other functions
too.
Regards,
Tony
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Re: [PATCH v2 5/6] iommu/intel: announce supported page sizes
On Tue, 2011-09-13 at 22:31 +0300, Ohad Ben-Cohen wrote: > + * Traditionally the IOMMU core just handed us the mappings directly, > + * after making sure the size is an order of a 4KB page and that the > + * mapping has natural alignment. > + * > + * To retain this behavior, we currently advertise that we support > + * all page sizes that are an order of 4KB. This is wrong. We do not support 4000-byte pages. We only support 4096-byte pages. 4KiB, not 4kB. Please fix. -- dwmw2 smime.p7s Description: S/MIME cryptographic signature
[PATCH 5/6] OMAP3: id: remove duplicate code for testing SoC ES level
omap3_cpuinfo() contains essentially duplicated code from
omap3_check_revision(), just for the purpose of determining the chip ES level.
Set the cpu_rev char array pointer in omap3_check_revision() instead,
and drop the now-useless code from omap3_cpuinfo().
Signed-off-by: Paul Walmsley
---
arch/arm/mach-omap2/id.c | 80 +-
1 files changed, 23 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 18c3797..307e186 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -242,7 +242,7 @@ static void __init ti816x_check_features(void)
omap_features = OMAP3_HAS_NEON;
}
-static void __init omap3_check_revision(void)
+static void __init omap3_check_revision(const char **cpu_rev)
{
u32 cpuid, idcode;
u16 hawkeye;
@@ -259,6 +259,7 @@ static void __init omap3_check_revision(void)
if cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
omap_revision = OMAP3430_REV_ES1_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES1;
+ *cpu_rev = "1.0";
return;
}
@@ -280,18 +281,22 @@ static void __init omap3_check_revision(void)
case 1:
omap_revision = OMAP3430_REV_ES2_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+ *cpu_rev = "2.0";
break;
case 2:
omap_revision = OMAP3430_REV_ES2_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES2;
+ *cpu_rev = "2.1";
break;
case 3:
omap_revision = OMAP3430_REV_ES3_0;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
+ *cpu_rev = "3.0";
break;
case 4:
omap_revision = OMAP3430_REV_ES3_1;
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+ *cpu_rev = "3.1";
break;
case 7:
/* FALLTHROUGH */
@@ -301,6 +306,7 @@ static void __init omap3_check_revision(void)
/* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
+ *cpu_rev = "3.1.2";
}
break;
case 0xb868:
@@ -315,11 +321,13 @@ static void __init omap3_check_revision(void)
switch (rev) {
case 0:
omap_revision = OMAP3517_REV_ES1_0;
+ *cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = OMAP3517_REV_ES1_1;
+ *cpu_rev = "1.1";
}
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
@@ -330,16 +338,19 @@ static void __init omap3_check_revision(void)
switch(rev) {
case 0: /* Take care of early samples */
omap_revision = OMAP3630_REV_ES1_0;
+ *cpu_rev = "1.0";
break;
case 1:
omap_revision = OMAP3630_REV_ES1_1;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
+ *cpu_rev = "1.1";
break;
case 2:
/* FALLTHROUGH */
default:
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+ *cpu_rev = "1.2";
}
break;
case 0xb81e:
@@ -348,17 +359,21 @@ static void __init omap3_check_revision(void)
switch (rev) {
case 0:
omap_revision = TI8168_REV_ES1_0;
+ *cpu_rev = "1.0";
break;
case 1:
/* FALLTHROUGH */
default:
omap_revision = TI8168_REV_ES1_1;
+ *cpu_rev = "1.1";
+ break;
}
break;
default:
/* Unknown default to latest silicon rev as default */
- omap_revision = OMAP3630_REV_ES1_2;
+ omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+ *cpu_rev = "1.2";
pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
}
}
@@ -435,10 +450,9 @@ static void __init omap4_check_revision(void)
if (omap3_has_ ##feat())\
printk(#feat" ");
-static void __init omap3_cpuinfo(void)
+static void __init omap3_cpuinfo(const char *cpu_rev)
{
- u8 rev = GET_OMAP_RE
[PATCH 4/6] OMAP3: id: add fallthrough warning; fix some CodingStyle issues
Emit a warning to the console in omap3_check_revision() if that code
cannot determine what type of SoC the system is currently running on.
Remove some extra whitespace, remove some duplicate code, and
add an appropriate comment to a fallthrough case.
Signed-off-by: Paul Walmsley
Cc: Hemant Pedanekar
---
arch/arm/mach-omap2/id.c | 11 ++-
1 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 6810c52..18c3797 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -336,8 +336,9 @@ static void __init omap3_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP3630ES1_1;
break;
case 2:
+ /* FALLTHROUGH */
default:
- omap_revision = OMAP3630_REV_ES1_2;
+ omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
}
break;
@@ -349,16 +350,16 @@ static void __init omap3_check_revision(void)
omap_revision = TI8168_REV_ES1_0;
break;
case 1:
- omap_revision = TI8168_REV_ES1_1;
- break;
+ /* FALLTHROUGH */
default:
- omap_revision = TI8168_REV_ES1_1;
+ omap_revision = TI8168_REV_ES1_1;
}
break;
default:
- /* Unknown default to latest silicon rev as default*/
+ /* Unknown default to latest silicon rev as default */
omap_revision = OMAP3630_REV_ES1_2;
omap_chip.oc |= CHIP_IS_OMAP3630ES1_2;
+ pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
}
}
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[PATCH 6/6] OMAP2+: id: remove OMAP_REVBITS_* macros
The OMAP_REVBITS_* macros are just used as otherwise meaningless
aliases for the numbers zero through five, so remove these macros.
Signed-off-by: Paul Walmsley
---
arch/arm/plat-omap/include/plat/cpu.h | 33 ++---
1 files changed, 10 insertions(+), 23 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/cpu.h
b/arch/arm/plat-omap/include/plat/cpu.h
index 566975c..0ec90cf 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -60,19 +60,6 @@ struct omap_chip_id {
unsigned int omap_rev(void);
/*
- * Define CPU revision bits
- *
- * Verbose meaning of the revision bits may be different for a silicon
- * family. This difference can be handled separately.
- */
-#define OMAP_REVBITS_000x00
-#define OMAP_REVBITS_010x01
-#define OMAP_REVBITS_020x02
-#define OMAP_REVBITS_030x03
-#define OMAP_REVBITS_040x04
-#define OMAP_REVBITS_050x05
-
-/*
* Get the CPU revision for OMAP devices
*/
#define GET_OMAP_REVISION()((omap_rev() >> 8) & 0xff)
@@ -379,31 +366,31 @@ IS_OMAP_TYPE(3517, 0x3517)
/* Various silicon revisions for omap2 */
#define OMAP242X_CLASS 0x24200024
#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
-#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP2420_REV_ES2_0 (OMAP242X_CLASS | (0x1 << 8))
#define OMAP243X_CLASS 0x24300024
#define OMAP2430_REV_ES1_0 OMAP243X_CLASS
#define OMAP343X_CLASS 0x34300034
#define OMAP3430_REV_ES1_0 OMAP343X_CLASS
-#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (OMAP_REVBITS_02 << 8))
-#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (OMAP_REVBITS_03 << 8))
-#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (OMAP_REVBITS_04 << 8))
-#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (OMAP_REVBITS_05 << 8))
+#define OMAP3430_REV_ES2_0 (OMAP343X_CLASS | (0x1 << 8))
+#define OMAP3430_REV_ES2_1 (OMAP343X_CLASS | (0x2 << 8))
+#define OMAP3430_REV_ES3_0 (OMAP343X_CLASS | (0x3 << 8))
+#define OMAP3430_REV_ES3_1 (OMAP343X_CLASS | (0x4 << 8))
+#define OMAP3430_REV_ES3_1_2 (OMAP343X_CLASS | (0x5 << 8))
#define OMAP363X_CLASS 0x36300034
#define OMAP3630_REV_ES1_0 OMAP363X_CLASS
-#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
-#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
+#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (0x1 << 8))
+#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (0x2 << 8))
#define OMAP3517_CLASS 0x3517
#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
-#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (OMAP_REVBITS_01 << 8))
+#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (0x1 << 8))
#define TI816X_CLASS 0x81600034
#define TI8168_REV_ES1_0 TI816X_CLASS
-#define TI8168_REV_ES1_1 (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
+#define TI8168_REV_ES1_1 (TI816X_CLASS | (0x1 << 8))
#define OMAP443X_CLASS 0x44300044
#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
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[PATCH 2/6] OMAP3: id: remove useless strcpy()s
omap3_cpuinfo() is filled with useless strcpy() calls; remove them.
Signed-off-by: Paul Walmsley
Cc: Sanjeev Premi
---
arch/arm/mach-omap2/id.c | 48 +-
1 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 723e2f8..46bc2f9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -429,84 +429,80 @@ static void __init omap4_check_revision(void)
static void __init omap3_cpuinfo(void)
{
u8 rev = GET_OMAP_REVISION();
- char cpu_name[16], cpu_rev[16];
+ const char *cpu_name, *cpu_rev;
- /* OMAP3430 and OMAP3530 are assumed to be same.
+ /*
+* OMAP3430 and OMAP3530 are assumed to be same.
*
* OMAP3525, OMAP3515 and OMAP3503 can be detected only based
* on available features. Upon detection, update the CPU id
* and CPU class bits.
*/
if (cpu_is_omap3630()) {
- strcpy(cpu_name, "OMAP3630");
+ cpu_name = "OMAP3630";
} else if (cpu_is_omap3505()) {
- /*
-* AM35xx devices
-*/
- if (omap3_has_sgx())
- strcpy(cpu_name, "AM3517");
- else
- strcpy(cpu_name, "AM3505");
+ /* AM35xx devices */
+ cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
} else if (cpu_is_ti816x()) {
- strcpy(cpu_name, "TI816X");
+ cpu_name = "TI816X";
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
- strcpy(cpu_name, "OMAP3430/3530");
+ cpu_name = "OMAP3430/3530";
} else if (omap3_has_iva()) {
- strcpy(cpu_name, "OMAP3525");
+ cpu_name = "OMAP3525";
} else if (omap3_has_sgx()) {
- strcpy(cpu_name, "OMAP3515");
+ cpu_name = "OMAP3515";
} else {
- strcpy(cpu_name, "OMAP3503");
+ cpu_name = "OMAP3503";
}
if (cpu_is_omap3630() || cpu_is_ti816x()) {
switch (rev) {
case OMAP_REVBITS_00:
- strcpy(cpu_rev, "1.0");
+ cpu_rev = "1.0";
break;
case OMAP_REVBITS_01:
- strcpy(cpu_rev, "1.1");
+ cpu_rev = "1.1";
break;
case OMAP_REVBITS_02:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
- strcpy(cpu_rev, "1.2");
+ cpu_rev = "1.2";
}
} else if (cpu_is_omap3505() || cpu_is_omap3517()) {
switch (rev) {
case OMAP_REVBITS_00:
- strcpy(cpu_rev, "1.0");
+ cpu_rev = "1.0";
break;
case OMAP_REVBITS_01:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
- strcpy(cpu_rev, "1.1");
+ cpu_rev = "1.1";
}
} else {
switch (rev) {
case OMAP_REVBITS_00:
- strcpy(cpu_rev, "1.0");
+ cpu_rev = "1.0";
break;
case OMAP_REVBITS_01:
- strcpy(cpu_rev, "2.0");
+ cpu_rev = "2.0";
break;
case OMAP_REVBITS_02:
- strcpy(cpu_rev, "2.1");
+ cpu_rev = "2.1";
break;
case OMAP_REVBITS_03:
- strcpy(cpu_rev, "3.0");
+ cpu_rev = "3.0";
break;
case OMAP_REVBITS_04:
- strcpy(cpu_rev, "3.1");
+ cpu_rev = "3.1";
break;
case OMAP_REVBITS_05:
/* FALLTHROUGH */
default:
/* Use the latest known revision as default */
- strcpy(cpu_rev, "3.1.2");
+ cpu_rev = "3.1.2";
}
}
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[PATCH 3/6] OMAP3: id: use explicit omap_revision codes for 3505/3517 ES levels
Use explicit revision codes for OMAP/AM 3505/3517 ES levels, as the rest
of the OMAP2+ SoCs do in mach-omap2/cpu.c.
Signed-off-by: Paul Walmsley
Cc: Sanjeev Premi
---
arch/arm/mach-omap2/id.c | 10 +-
arch/arm/plat-omap/include/plat/cpu.h |3 ++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 46bc2f9..6810c52 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -312,7 +312,15 @@ static void __init omap3_check_revision(void)
*
* REVISIT: AM3505/AM3517 should have their own CHIP_IS
*/
- omap_revision = OMAP3517_REV(rev);
+ switch (rev) {
+ case 0:
+ omap_revision = OMAP3517_REV_ES1_0;
+ break;
+ case 1:
+ /* FALLTHROUGH */
+ default:
+ omap_revision = OMAP3517_REV_ES1_1;
+ }
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
case 0xb891:
diff --git a/arch/arm/plat-omap/include/plat/cpu.h
b/arch/arm/plat-omap/include/plat/cpu.h
index b6bd8f7..566975c 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -398,7 +398,8 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
#define OMAP3517_CLASS 0x3517
-#define OMAP3517_REV(v)(OMAP3517_CLASS | (v << 8))
+#define OMAP3517_REV_ES1_0 OMAP3517_CLASS
+#define OMAP3517_REV_ES1_1 (OMAP3517_CLASS | (OMAP_REVBITS_01 << 8))
#define TI816X_CLASS 0x81600034
#define TI8168_REV_ES1_0 TI816X_CLASS
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[PATCH 1/6] OMAP3: id: remove identification codes that only correspond to marketing names
The OMAP3505/AM3505 appears to be based on the same silicon as the
OMAP3517/AM3517, with some features disabled via eFuse bits. Follow
the same practice as OMAP3430 and identify these devices internally as
part of the OMAP3517/AM3517 family.
The OMAP3503/3515/3525/3530 chips appear to be based on the same silicon
as the OMAP3430, with some features disabled via eFuse bits. Identify
these devices internally as part of the OMAP3430 family.
Remove the old OMAP35XX_CLASS, which actually covered two very different
chip families. The OMAP3503/3515/3525/3530 chips will now be covered by
OMAP343X_CLASS, since the silicon appears to be identical. For the
OMAP3517/AM3517 family, create a new class, OMAP3517_CLASS.
Signed-off-by: Paul Walmsley
Cc: Sanjeev Premi
---
arch/arm/mach-omap2/id.c | 17 ++---
arch/arm/plat-omap/include/plat/cpu.h |9 ++---
2 files changed, 8 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 37efb86..723e2f8 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -304,14 +304,15 @@ static void __init omap3_check_revision(void)
}
break;
case 0xb868:
- /* Handle OMAP35xx/AM35xx devices
+ /*
+* Handle OMAP/AM 3505/3517 devices
*
-* Set the device to be OMAP3505 here. Actual device
+* Set the device to be OMAP3517 here. Actual device
* is identified later based on the features.
*
* REVISIT: AM3505/AM3517 should have their own CHIP_IS
*/
- omap_revision = OMAP3505_REV(rev);
+ omap_revision = OMAP3517_REV(rev);
omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
break;
case 0xb891:
@@ -442,26 +443,20 @@ static void __init omap3_cpuinfo(void)
/*
* AM35xx devices
*/
- if (omap3_has_sgx()) {
- omap_revision = OMAP3517_REV(rev);
+ if (omap3_has_sgx())
strcpy(cpu_name, "AM3517");
- } else {
- /* Already set in omap3_check_revision() */
+ else
strcpy(cpu_name, "AM3505");
- }
} else if (cpu_is_ti816x()) {
strcpy(cpu_name, "TI816X");
} else if (omap3_has_iva() && omap3_has_sgx()) {
/* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
strcpy(cpu_name, "OMAP3430/3530");
} else if (omap3_has_iva()) {
- omap_revision = OMAP3525_REV(rev);
strcpy(cpu_name, "OMAP3525");
} else if (omap3_has_sgx()) {
- omap_revision = OMAP3515_REV(rev);
strcpy(cpu_name, "OMAP3515");
} else {
- omap_revision = OMAP3503_REV(rev);
strcpy(cpu_name, "OMAP3503");
}
diff --git a/arch/arm/plat-omap/include/plat/cpu.h
b/arch/arm/plat-omap/include/plat/cpu.h
index 67b3d75..b6bd8f7 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -397,13 +397,8 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP3630_REV_ES1_1 (OMAP363X_CLASS | (OMAP_REVBITS_01 << 8))
#define OMAP3630_REV_ES1_2 (OMAP363X_CLASS | (OMAP_REVBITS_02 << 8))
-#define OMAP35XX_CLASS 0x3534
-#define OMAP3503_REV(v)(OMAP35XX_CLASS | (0x3503 << 16) | (v
<< 8))
-#define OMAP3515_REV(v)(OMAP35XX_CLASS | (0x3515 << 16) | (v
<< 8))
-#define OMAP3525_REV(v)(OMAP35XX_CLASS | (0x3525 << 16) | (v
<< 8))
-#define OMAP3530_REV(v)(OMAP35XX_CLASS | (0x3530 << 16) | (v
<< 8))
-#define OMAP3505_REV(v)(OMAP35XX_CLASS | (0x3505 << 16) | (v
<< 8))
-#define OMAP3517_REV(v)(OMAP35XX_CLASS | (0x3517 << 16) | (v
<< 8))
+#define OMAP3517_CLASS 0x3517
+#define OMAP3517_REV(v)(OMAP3517_CLASS | (v << 8))
#define TI816X_CLASS 0x81600034
#define TI8168_REV_ES1_0 TI816X_CLASS
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[PATCH 0/6] OMAP2+: id: cleanup for 3.2
Clean up the SoC detection code for some OMAP3 devices. The main goal is to make the AM3517 family detection code work like the rest of the OMAP3 SoCs, although this series does some other cleanup of this code at the same time. This patch series will be a prerequisite for the OMAP_CHIP removal series. Tested on an OMAP3530ES2 BeagleBoard C2 and a OMAP3730ES1 BeagleBoard A2. These are the only OMAP3 boards I have access to right now - testing welcomed from people with other OMAP3 families or ES levels. - Paul --- Paul Walmsley (6): OMAP3: id: remove identification codes that only correspond to marketing names OMAP3: id: remove useless strcpy()s OMAP3: id: use explicit omap_revision codes for 3505/3517 ES levels OMAP3: id: add fallthrough warning; fix some CodingStyle issues OMAP3: id: remove duplicate code for testing SoC ES level OMAP2+: id: remove OMAP_REVBITS_* macros arch/arm/mach-omap2/id.c | 134 - arch/arm/plat-omap/include/plat/cpu.h | 41 +++--- 2 files changed, 62 insertions(+), 113 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 13/25] OMAP4: PM: Add WakeupGen module as OMAP gic_arch_extn
* Santosh Shilimkar [110904 06:23]: > OMAP WakeupGen is the interrupt controller extension used along > with ARM GIC to wake the CPU out from low power states on > external interrupts. > > The WakeupGen unit is responsible for generating wakeup event > from the incoming interrupts and enable bits. It is implemented > in MPU always ON power domain. During normal operation, > WakeupGen delivers external interrupts directly to the GIC. ... > + /* > + * Override GIC architecture specific functions to add > + * OMAP WakeupGen interrupt controller along with GIC > + */ > + gic_arch_extn.irq_mask = wakeupgen_mask; > + gic_arch_extn.irq_unmask = wakeupgen_unmask; > + gic_arch_extn.irq_set_wake = wakeupgen_set_wake; > + gic_arch_extn.flags = IRQCHIP_MASK_ON_SUSPEND; As I've commented before, there should not be any need to tweak the wakeupgen registers for each interrupt during the runtime. AFAIK the wakeupgen registers only need to be armed every time before entering idle. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 02/25] OMAP4: Redefine mandatory barriers for OMAP to include interconnect barriers.
* Santosh Shilimkar [110904 06:22]: > On OMAP4 SOC intecronnects has many write buffers in the async bridges > and they can be drained only with stongly ordered accesses. This is not correct, strongly ordered access does not guarantee anything here. If it fixes issues, it's because it makes the writes to reach the device faster. Strongly ordered does not affect anything outside ARM, so the bus access won't change. The only real fix here is to do a read back of the device in question to guarantee the write got to the device. > There are two ports as below from MPU and both needs to be drained. > - MPU --> L3 T2ASYNC FIFO > - MPU --> DDR T2ASYNC FIFO > > Without the interconnect barriers, many issues have been observed > leading to system freeze, CPU deadlocks, random crashes with > register accesses, synchronization loss on initiators operating > on both interconnect port simultaneously. We had these issues for omap3 too. Adding a few read backs solved those kinds of issues. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 01/25] ARM: mm: Add strongly ordered descriptor support.
* Santosh Shilimkar [110904 06:22]: > On certain architectures, there might be a need to mark certain > addresses with strongly ordered memory attributes to avoid ordering > issues at the interconnect level. This is something Russell needs to look. You might want to also read the mailing list archives regarding the strongly ordered access. Basically it still won't guarantee that the write gets to the device, only a read back from the device in question guarantees that at the bus level. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 4/6] iommu/amd: announce supported page sizes
Let the IOMMU core know we support arbitrary page sizes (as long as
they're an order of 4KB).
This way the IOMMU core will retain the existing behavior we're used to;
it will let us map regions that:
- their size is an order of 4KB
- they are naturally aligned
Signed-off-by: Ohad Ben-Cohen
Cc: Joerg Roedel
---
drivers/iommu/amd_iommu.c | 21 -
1 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index a14f8dc..17fa0fc 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -2488,12 +2488,31 @@ static unsigned device_dma_ops_init(void)
}
/*
+ * This bitmap is used to advertise the page sizes our hardware support
+ * to the IOMMU core, which will then use this information to split
+ * physically contiguous memory regions it is mapping into page sizes
+ * that we support.
+ *
+ * Traditionally the IOMMU core just handed us the mappings directly,
+ * after making sure the size is an order of a 4KB page and that the
+ * mapping has natural alignment.
+ *
+ * To retain this behavior, we currently advertise that we support
+ * all page sizes that are an order of 4KB.
+ *
+ * If at some point we'd like to utilize the IOMMU core's new behavior,
+ * we could change this to advertise the real page sizes we support.
+ */
+static unsigned long amd_iommu_pgsizes = ~0xFFFUL;
+
+/*
* The function which clues the AMD IOMMU driver into dma_ops.
*/
void __init amd_iommu_init_api(void)
{
- register_iommu(&amd_iommu_ops);
+ register_iommu_pgsize(&amd_iommu_ops, &amd_iommu_pgsizes,
+ BITS_PER_LONG);
}
int __init amd_iommu_init_dma_ops(void)
--
1.7.4.1
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[PATCH v2 5/6] iommu/intel: announce supported page sizes
Let the IOMMU core know we support arbitrary page sizes (as long as
they're an order of 4KB).
This way the IOMMU core will retain the existing behavior we're used to;
it will let us map regions that:
- their size is an order of 4KB
- they are naturally aligned
Note: Intel IOMMU hardware doesn't support arbitrary page sizes,
but the driver does (it splits arbitrary-sized mappings into
the pages supported by the hardware).
To make everything simpler for now, though, this patch effectively tells
the IOMMU core to keep giving this driver the same memory regions it did
before, so nothing is changed as far as it's concerned.
Note: at this point, the page sizes announced remain static within the IOMMU
core. To correctly utilize the pgsize-splitting of the IOMMU core by
this driver, it seems that some core changes should still be done,
because Intel's IOMMU page size capabilities seem to have the potential
to be different between different DMA remapping devices.
Signed-off-by: Ohad Ben-Cohen
Cc: David Woodhouse
---
drivers/iommu/intel-iommu.c | 21 -
1 files changed, 20 insertions(+), 1 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index c621c98..333a9cb 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -3426,6 +3426,24 @@ static struct notifier_block device_nb = {
.notifier_call = device_notifier,
};
+/*
+ * This bitmap is used to advertise the page sizes our hardware support
+ * to the IOMMU core, which will then use this information to split
+ * physically contiguous memory regions it is mapping into page sizes
+ * that we support.
+ *
+ * Traditionally the IOMMU core just handed us the mappings directly,
+ * after making sure the size is an order of a 4KB page and that the
+ * mapping has natural alignment.
+ *
+ * To retain this behavior, we currently advertise that we support
+ * all page sizes that are an order of 4KB.
+ *
+ * If at some point we'd like to utilize the IOMMU core's new behavior,
+ * we could change this to advertise the real page sizes we support.
+ */
+static unsigned long intel_iommu_pgsizes = ~0xFFFUL;
+
int __init intel_iommu_init(void)
{
int ret = 0;
@@ -3486,7 +3504,8 @@ int __init intel_iommu_init(void)
init_iommu_pm_ops();
- register_iommu(&intel_iommu_ops);
+ register_iommu_pgsize(&intel_iommu_ops, &intel_iommu_pgsizes,
+ BITS_PER_LONG);
bus_register_notifier(&pci_bus_type, &device_nb);
--
1.7.4.1
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[PATCH v2 6/6] iommu/core: remove the temporary register_iommu_pgsize API
Now that all IOMMU drivers are converted to the new
register_iommu_pgsize() API, the old code can be removed, and
we can s/register_iommu_pgsize/register_iommu/.
Signed-off-by: Ohad Ben-Cohen
Cc: Joerg Roedel
Cc: David Woodhouse
Cc: David Brown
Cc: Stepan Moskovchenko
---
drivers/iommu/amd_iommu.c |3 +--
drivers/iommu/intel-iommu.c |3 +--
drivers/iommu/iommu.c | 34 +-
drivers/iommu/msm_iommu.c |2 +-
drivers/iommu/omap-iommu.c |2 +-
include/linux/iommu.h |5 ++---
6 files changed, 7 insertions(+), 42 deletions(-)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index 17fa0fc..5cdfa91 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -2511,8 +2511,7 @@ static unsigned long amd_iommu_pgsizes = ~0xFFFUL;
void __init amd_iommu_init_api(void)
{
- register_iommu_pgsize(&amd_iommu_ops, &amd_iommu_pgsizes,
- BITS_PER_LONG);
+ register_iommu(&amd_iommu_ops, &amd_iommu_pgsizes, BITS_PER_LONG);
}
int __init amd_iommu_init_dma_ops(void)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 333a9cb..a8c91a6 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -3504,8 +3504,7 @@ int __init intel_iommu_init(void)
init_iommu_pm_ops();
- register_iommu_pgsize(&intel_iommu_ops, &intel_iommu_pgsizes,
- BITS_PER_LONG);
+ register_iommu(&intel_iommu_ops, &intel_iommu_pgsizes, BITS_PER_LONG);
bus_register_notifier(&pci_bus_type, &device_nb);
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index c848f14..8bbd1aa 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -46,13 +46,8 @@ static unsigned int iommu_min_page_idx;
* @ops: iommu handlers
* @pgsize_bitmap: bitmap of page sizes supported by the hardware
* @nr_page_bits: size of @pgsize_bitmap (in bits)
- *
- * Note: this is a temporary function, which will be removed once
- * all IOMMU drivers are converted. The only reason it exists is to
- * allow splitting the pgsizes changes to several patches in order to ease
- * the review.
*/
-void register_iommu_pgsize(struct iommu_ops *ops, unsigned long *pgsize_bitmap,
+void register_iommu(struct iommu_ops *ops, unsigned long *pgsize_bitmap,
unsigned int nr_page_bits)
{
if (iommu_ops || iommu_pgsize_bitmap || !nr_page_bits)
@@ -67,33 +62,6 @@ void register_iommu_pgsize(struct iommu_ops *ops, unsigned
long *pgsize_bitmap,
iommu_min_pagesz = 1 << iommu_min_page_idx;
}
-/*
- * default pagesize bitmap, will be removed once all IOMMU drivers
- * are converted
- */
-static unsigned long default_iommu_pgsizes = ~0xFFFUL;
-
-void register_iommu(struct iommu_ops *ops)
-{
- if (iommu_ops)
- BUG();
-
- iommu_ops = ops;
-
- /*
-* set default pgsize values, which retain the existing
-* IOMMU API behavior: drivers will be called to map
-* regions that are sized/aligned to order of 4KB pages
-*/
- iommu_pgsize_bitmap = &default_iommu_pgsizes;
- iommu_nr_page_bits = BITS_PER_LONG;
-
- /* find the minimum page size and its index only once */
- iommu_min_page_idx = find_first_bit(iommu_pgsize_bitmap,
- iommu_nr_page_bits);
- iommu_min_pagesz = 1 << iommu_min_page_idx;
-}
-
bool iommu_found(void)
{
return iommu_ops != NULL;
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
index a4ed116..e59ced9 100644
--- a/drivers/iommu/msm_iommu.c
+++ b/drivers/iommu/msm_iommu.c
@@ -733,7 +733,7 @@ static int __init msm_iommu_init(void)
setup_iommu_tex_classes();
/* we're only using the first 25 bits of the pgsizes bitmap */
- register_iommu_pgsize(&msm_iommu_ops, &msm_iommu_pgsizes, 25);
+ register_iommu(&msm_iommu_ops, &msm_iommu_pgsizes, 25);
return 0;
}
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 403dd6a..3d8ad87 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1229,7 +1229,7 @@ static int __init omap_iommu_init(void)
iopte_cachep = p;
/* we're only using the first 25 bits of the pgsizes bitmap */
- register_iommu_pgsize(&omap_iommu_ops, &omap_iommu_pgsizes, 25);
+ register_iommu(&omap_iommu_ops, &omap_iommu_pgsizes, 25);
return platform_driver_register(&omap_iommu_driver);
}
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 1806956..297893f 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -60,9 +60,8 @@ struct iommu_ops {
#ifdef CONFIG_IOMMU_API
-extern void register_iommu(struct iommu_ops *ops);
-extern void register_iommu_pgsize(struct iommu_ops *ops,
- unsigned long *pgsize_bitmap, unsigned i
[PATCH v2 2/6] iommu/omap: announce supported page sizes
Let the IOMMU core know we support 4KB, 64KB, 1MB and 16MB page sizes.
This way the IOMMU core can split any arbitrary-sized physically
contiguous regions (that it needs to map) as needed.
Signed-off-by: Ohad Ben-Cohen
---
drivers/iommu/omap-iommu.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index 7e0188f..403dd6a 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -1202,6 +1202,9 @@ static int omap_iommu_domain_has_cap(struct iommu_domain
*domain,
return 0;
}
+/* bitmap of the page sizes supported by the OMAP IOMMU hardware */
+static unsigned long omap_iommu_pgsizes = SZ_4K | SZ_64K | SZ_1M | SZ_16M;
+
static struct iommu_ops omap_iommu_ops = {
.domain_init= omap_iommu_domain_init,
.domain_destroy = omap_iommu_domain_destroy,
@@ -1225,7 +1228,8 @@ static int __init omap_iommu_init(void)
return -ENOMEM;
iopte_cachep = p;
- register_iommu(&omap_iommu_ops);
+ /* we're only using the first 25 bits of the pgsizes bitmap */
+ register_iommu_pgsize(&omap_iommu_ops, &omap_iommu_pgsizes, 25);
return platform_driver_register(&omap_iommu_driver);
}
--
1.7.4.1
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[PATCH v2 3/6] iommu/msm: announce supported page sizes
Let the IOMMU core know we support 4KB, 64KB, 1MB and 16MB page sizes.
This way the IOMMU core can split any arbitrary-sized physically
contiguous regions (that it needs to map) as needed.
Signed-off-by: Ohad Ben-Cohen
Cc: David Brown
Cc: Stepan Moskovchenko
---
drivers/iommu/msm_iommu.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/drivers/iommu/msm_iommu.c b/drivers/iommu/msm_iommu.c
index d1733f6..a4ed116 100644
--- a/drivers/iommu/msm_iommu.c
+++ b/drivers/iommu/msm_iommu.c
@@ -676,6 +676,9 @@ fail:
return 0;
}
+/* bitmap of the page sizes currently supported */
+static unsigned long msm_iommu_pgsizes = SZ_4K | SZ_64K | SZ_1M | SZ_16M;
+
static struct iommu_ops msm_iommu_ops = {
.domain_init = msm_iommu_domain_init,
.domain_destroy = msm_iommu_domain_destroy,
@@ -728,7 +731,10 @@ static void __init setup_iommu_tex_classes(void)
static int __init msm_iommu_init(void)
{
setup_iommu_tex_classes();
- register_iommu(&msm_iommu_ops);
+
+ /* we're only using the first 25 bits of the pgsizes bitmap */
+ register_iommu_pgsize(&msm_iommu_ops, &msm_iommu_pgsizes, 25);
+
return 0;
}
--
1.7.4.1
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[PATCH v2 1/6] iommu/core: split mapping to page sizes as supported by the hardware
When mapping a memory region, split it to page sizes as supported
by the iommu hardware. Always prefer bigger pages, when possible,
in order to reduce the TLB pressure.
The logic to do that is now added to the IOMMU core, so neither the iommu
drivers themselves nor users of the IOMMU API have to duplicate it.
This allows a more lenient granularity of mappings; traditionally the
IOMMU API took 'order' (of a page) as a mapping size, and directly let
the low level iommu drivers handle the mapping, but now that the IOMMU
core can split arbitrary memory regions into pages, we can remove this
limitation, so users don't have to split those regions by themselves.
Currently the supported page sizes are advertised once and they then
remain static. That works well for OMAP (and seemingly MSM too) but
it would probably not fly with intel's hardware, where the page size
capabilities seem to have the potential to be different between
several DMA remapping devices. This limitation can be dealt with
later, if desired. For now, the existing IOMMU API behavior is retained
(see: "iommu/intel: announce supported page sizes").
As requested, register_iommu() isn't changed yet, so we can convert
the IOMMU drivers in subsequent patches, and after all the drivers
are converted, register_iommu will be changed (and the temporary
register_iommu_pgsize() will be removed).
Mainline users of the IOMMU API (kvm and omap-iovmm) are adopted
to send the mapping size in bytes instead of in page order.
Signed-off-by: Ohad Ben-Cohen
Cc: David Brown
Cc: David Woodhouse
Cc: Joerg Roedel
Cc: Stepan Moskovchenko
Cc: Hiroshi DOYU
Cc: Laurent Pinchart
Cc: k...@vger.kernel.org
---
v1->v2: keep old code around until all drivers are converted
drivers/iommu/iommu.c | 158 +---
drivers/iommu/omap-iovmm.c | 12 +---
include/linux/iommu.h |6 +-
virt/kvm/iommu.c |4 +-
4 files changed, 157 insertions(+), 23 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index c68ff29..c848f14 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -16,6 +16,8 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#define pr_fmt(fmt)"%s: " fmt, __func__
+
#include
#include
#include
@@ -23,15 +25,73 @@
#include
#include
#include
+#include
static struct iommu_ops *iommu_ops;
+/* bitmap of supported page sizes */
+static unsigned long *iommu_pgsize_bitmap;
+
+/* number of bits used to represent the supported pages */
+static unsigned int iommu_nr_page_bits;
+
+/* size of the smallest supported page (in bytes) */
+static unsigned int iommu_min_pagesz;
+
+/* bit number of the smallest supported page */
+static unsigned int iommu_min_page_idx;
+
+/**
+ * register_iommu() - register an IOMMU hardware
+ * @ops: iommu handlers
+ * @pgsize_bitmap: bitmap of page sizes supported by the hardware
+ * @nr_page_bits: size of @pgsize_bitmap (in bits)
+ *
+ * Note: this is a temporary function, which will be removed once
+ * all IOMMU drivers are converted. The only reason it exists is to
+ * allow splitting the pgsizes changes to several patches in order to ease
+ * the review.
+ */
+void register_iommu_pgsize(struct iommu_ops *ops, unsigned long *pgsize_bitmap,
+ unsigned int nr_page_bits)
+{
+ if (iommu_ops || iommu_pgsize_bitmap || !nr_page_bits)
+ BUG();
+
+ iommu_ops = ops;
+ iommu_pgsize_bitmap = pgsize_bitmap;
+ iommu_nr_page_bits = nr_page_bits;
+
+ /* find the minimum page size and its index only once */
+ iommu_min_page_idx = find_first_bit(pgsize_bitmap, nr_page_bits);
+ iommu_min_pagesz = 1 << iommu_min_page_idx;
+}
+
+/*
+ * default pagesize bitmap, will be removed once all IOMMU drivers
+ * are converted
+ */
+static unsigned long default_iommu_pgsizes = ~0xFFFUL;
+
void register_iommu(struct iommu_ops *ops)
{
if (iommu_ops)
BUG();
iommu_ops = ops;
+
+ /*
+* set default pgsize values, which retain the existing
+* IOMMU API behavior: drivers will be called to map
+* regions that are sized/aligned to order of 4KB pages
+*/
+ iommu_pgsize_bitmap = &default_iommu_pgsizes;
+ iommu_nr_page_bits = BITS_PER_LONG;
+
+ /* find the minimum page size and its index only once */
+ iommu_min_page_idx = find_first_bit(iommu_pgsize_bitmap,
+ iommu_nr_page_bits);
+ iommu_min_pagesz = 1 << iommu_min_page_idx;
}
bool iommu_found(void)
@@ -109,26 +169,104 @@ int iommu_domain_has_cap(struct iommu_domain *domain,
EXPORT_SYMBOL_GPL(iommu_domain_has_cap);
int iommu_map(struct iommu_domain *domain, unsigned long iova,
- phys_addr_t paddr, int gfp_order, int prot)
+ phys_addr_t paddr, size_t size, int prot)
{
- size_t size;
+ int ret = 0;
+
+
[PATCH v2 2/2] iommu/omap: migrate to the generic fault report mechanism
Start using the generic fault report mechanism, as provided by
the IOMMU core, and remove its now-redundant omap_iommu_set_isr API.
Currently we're only interested in letting upper layers know about the
fault, so in case the faulting device is a remote processor, they could
restart it.
Dynamic PTE/TLB loading is not supported.
Signed-off-by: Ohad Ben-Cohen
---
arch/arm/plat-omap/include/plat/iommu.h |3 +--
drivers/iommu/omap-iommu.c | 31 +++
2 files changed, 4 insertions(+), 30 deletions(-)
diff --git a/arch/arm/plat-omap/include/plat/iommu.h
b/arch/arm/plat-omap/include/plat/iommu.h
index 7f1df0e..a1d79ee 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -32,6 +32,7 @@ struct omap_iommu {
void __iomem*regbase;
struct device *dev;
void*isr_priv;
+ struct iommu_domain *domain;
unsigned intrefcount;
spinlock_t iommu_lock; /* global for this whole object */
@@ -48,8 +49,6 @@ struct omap_iommu {
struct list_headmmap;
struct mutexmmap_lock; /* protect mmap */
- int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs, void *priv);
-
void *ctx; /* iommu context: registres saved area */
u32 da_start;
u32 da_end;
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index bd5f606..7e0188f 100644
--- a/drivers/iommu/omap-iommu.c
+++ b/drivers/iommu/omap-iommu.c
@@ -775,6 +775,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
u32 da, errs;
u32 *iopgd, *iopte;
struct omap_iommu *obj = data;
+ struct iommu_domain *domain = obj->domain;
if (!obj->refcount)
return IRQ_NONE;
@@ -786,7 +787,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
return IRQ_HANDLED;
/* Fault callback or TLB/PTE Dynamic loading */
- if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
+ if (!report_iommu_fault(domain, obj->dev, da, 0))
return IRQ_HANDLED;
iommu_disable(obj);
@@ -904,33 +905,6 @@ static void omap_iommu_detach(struct omap_iommu *obj)
dev_dbg(obj->dev, "%s: %s\n", __func__, obj->name);
}
-int omap_iommu_set_isr(const char *name,
- int (*isr)(struct omap_iommu *obj, u32 da, u32 iommu_errs,
-void *priv),
- void *isr_priv)
-{
- struct device *dev;
- struct omap_iommu *obj;
-
- dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
-device_match_by_alias);
- if (!dev)
- return -ENODEV;
-
- obj = to_iommu(dev);
- spin_lock(&obj->iommu_lock);
- if (obj->refcount != 0) {
- spin_unlock(&obj->iommu_lock);
- return -EBUSY;
- }
- obj->isr = isr;
- obj->isr_priv = isr_priv;
- spin_unlock(&obj->iommu_lock);
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(omap_iommu_set_isr);
-
/*
* OMAP Device MMU(IOMMU) detection
*/
@@ -1115,6 +1089,7 @@ omap_iommu_attach_dev(struct iommu_domain *domain, struct
device *dev)
}
omap_domain->iommu_dev = oiommu;
+ oiommu->domain = domain;
out:
spin_unlock(&omap_domain->lock);
--
1.7.4.1
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[PATCH v2 1/2] iommu/core: add fault reporting mechanism
Add iommu fault report mechanism to the IOMMU API, so implementations
could report about mmu faults (translation errors, hardware errors,
etc..).
Fault reports can be used in several ways:
- mere logging
- reset the device that accessed the faulting address (may be necessary
in case the device is a remote processor for example)
- implement dynamic PTE/TLB loading
A dedicated iommu_set_fault_handler() API has been added to allow
users, who are interested to receive such reports, to provide
their handler.
Signed-off-by: Ohad Ben-Cohen
---
v1->v2: remove 'event' parameter
drivers/iommu/iommu.c | 13
include/linux/iommu.h | 51 +
2 files changed, 64 insertions(+), 0 deletions(-)
diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
index e61a9ba..c68ff29 100644
--- a/drivers/iommu/iommu.c
+++ b/drivers/iommu/iommu.c
@@ -40,6 +40,19 @@ bool iommu_found(void)
}
EXPORT_SYMBOL_GPL(iommu_found);
+/**
+ * iommu_domain_alloc() - set a fault handler for an iommu domain
+ * @domain: iommu domain
+ * @handler: fault handler
+ */
+void iommu_set_fault_handler(struct iommu_domain *domain,
+ iommu_fault_handler_t handler)
+{
+ BUG_ON(!domain);
+
+ domain->handler = handler;
+}
+
struct iommu_domain *iommu_domain_alloc(void)
{
struct iommu_domain *domain;
diff --git a/include/linux/iommu.h b/include/linux/iommu.h
index 9940319..d084e87 100644
--- a/include/linux/iommu.h
+++ b/include/linux/iommu.h
@@ -26,9 +26,18 @@
#define IOMMU_CACHE(4) /* DMA cache coherency */
struct device;
+struct iommu_domain;
+
+/* iommu fault flags */
+#define IOMMU_FAULT_READ 0x0
+#define IOMMU_FAULT_WRITE 0x1
+
+typedef int (*iommu_fault_handler_t)(struct iommu_domain *,
+ struct device *, unsigned long, int);
struct iommu_domain {
void *priv;
+ iommu_fault_handler_t handler;
};
#define IOMMU_CAP_CACHE_COHERENCY 0x1
@@ -67,6 +76,43 @@ extern phys_addr_t iommu_iova_to_phys(struct iommu_domain
*domain,
unsigned long iova);
extern int iommu_domain_has_cap(struct iommu_domain *domain,
unsigned long cap);
+extern void iommu_set_fault_handler(struct iommu_domain *domain,
+ iommu_fault_handler_t handler);
+
+/**
+ * report_iommu_fault() - report about an IOMMU fault to the IOMMU framework
+ * @domain: the iommu domain where the fault has happened
+ * @dev: the device where the fault has happened
+ * @iova: the faulting address
+ * @flags: mmu fault flags (e.g. IOMMU_FAULT_READ/IOMMU_FAULT_WRITE/...)
+ *
+ * This function should be called by the low-level IOMMU implementations
+ * whenever IOMMU faults happen, to allow high-level users, that are
+ * interested in such events, to know about them.
+ *
+ * This event may be useful for several possible use cases:
+ * - mere logging of the event
+ * - dynamic TLB/PTE loading
+ * - if restarting of the faulting device is required
+ *
+ * Returns 0 on success and an appropriate error code otherwise (if dynamic
+ * PTE/TLB loading will one day be supported, implementations will be able
+ * to tell whether it succeeded or not according to this return value).
+ */
+static inline int report_iommu_fault(struct iommu_domain *domain,
+ struct device *dev, unsigned long iova, int flags)
+{
+ int ret = 0;
+
+ /*
+* if upper layers showed interest and installed a fault handler,
+* invoke it.
+*/
+ if (domain->handler)
+ ret = domain->handler(domain, dev, iova, flags);
+
+ return ret;
+}
#else /* CONFIG_IOMMU_API */
@@ -123,6 +169,11 @@ static inline int domain_has_cap(struct iommu_domain
*domain,
return 0;
}
+static inline void iommu_set_fault_handler(struct iommu_domain *domain,
+ iommu_fault_handler_t handler)
+{
+}
+
#endif /* CONFIG_IOMMU_API */
#endif /* __LINUX_IOMMU_H */
--
1.7.4.1
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Re: [PATCH 1/4] AM3517 : support for suspend/resume
Hi Abhilash,
"Koyamangalath, Abhilash" writes:
> Hi
>
> On Wed, Aug 31, 2011 at 4:28 AM, Hilman, Kevin wrote:
>>
>> Abhilash K V writes:
>>
>>> 1. Patch to disable dynamic sleep (as it is not supported
>>>on AM35xx).
>>> 2. Imported the unique suspend/resume sequence for AM3517,
>>>contained in the new file arch/arm/mach-omap2/sleep3517.S.
>>> 3. Added omap3517_ to symbol-names in sleep3517.S which are common
>>>with sleep34xx.S, and added appropriate checks.
>>>
>>> There are still 3 caveats:
>>>
>>> 1. If "no_console_suspend" is enabled (via boot-args), the device
>>>doesnot resume but simply hangs.
>>> 2. Every second and subsequent attempt to suspend/resume prints this
>>> slow-path
>>>WARNING (for both uart1 and uart2), while resuming :
>>>[ 70.943939] omap_hwmod: uart1: idle state can only be entered from
>>>enabled state
>>> 3. Wakeup using the TSC2004 touch-screen controller is not supported.
>>>
>>> Signed-off-by: Ranjith Lohithakshan
>>> Reviewed-by: Vaibhav Hiremath
>>> Signed-off-by: Abhilash K V
>>
>> In addition to Russell's comments about using the latest code from
>> mainline, I have some comments below.
> [Abhilash K V] I have reworked the patch against the tip (as suggested by
> Russell).
> And I've incorporated all of Kevin's comments too.
Great, thanks!
> There is one "known" issue left which needs to be closed before I can submit
> v2 of this patch.
> With no_console_suspend, suspend to RAM hangs right now on AM3517, after
> the message:
> Disabling non-boot CPUs ...
> There is no error message or dump.
> I found that this crash is happening in a call to pr_warning(), from
> _omap_device_deactivate().
> The same code does not produce this issue on omap34xx due to this snippet
> from omap_sram_idle() :
> /* PER */
> if (per_next_state < PWRDM_POWER_ON) {
> per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
> omap_uart_prepare_idle(2);
> omap_uart_prepare_idle(3);
> omap2_gpio_prepare_for_idle(per_going_off);
> if (per_next_state == PWRDM_POWER_OFF)
> omap3_per_save_context();
> }
> /* CORE */
> if (core_next_state < PWRDM_POWER_ON) {
> omap_uart_prepare_idle(0);
> omap_uart_prepare_idle(1);
> if (core_next_state == PWRDM_POWER_OFF) {
> omap3_core_save_context();
> omap3_cm_save_context();
> }
> }
> This happens in preparation to the suspend operation (I,e. the WFI).
> As seen here, on 34xx the sequence in which the uarts are disabled is 2, 3, 0
> and 1.The console-uart, which is uart-1 here (starting from uart-0) is
> disabled last.
> For AM3517 EVM, the console-uart is uart-2 and this ought to be
> disabled at the last to prevent this crash from occurring.
There are several other OMAP3 platforms (n900, Beagle, etc.) where the
UART console is also UART2, so console ordering is not the problem.
The fact that that pr_warning is making it to the console suggests that
the console is not locked. In the idle path, we take the console lock
(using console_trylock(), just above the code you showed above.)
But during suspend, there was an assumption (by me[2]) that the console
would always be locked in the suspend path. During no_console_suspend,
it appears that is not the case.
Can you try the patch below[1] to see if that fixes your problem? I
think it should.
Kevin
[1]
>From 5b5a73101fcfa042d53828c017ee3149eae44b50 Mon Sep 17 00:00:00 2001
From: Kevin Hilman
Date: Tue, 13 Sep 2011 11:18:44 -0700
Subject: [PATCH] OMAP3: PM: fix UART handling when using no_console_suspend
During the idle/suspend path, we expect the console lock to be held so
that no console output is done during/after the UARTs are idled.
However, when using the no_console_suspend argument on the
command-line, the console driver does not take the console lock. This
allows the possibility of console activity after UARTs have been
disabled.
To fix, update the current is_suspending() to also check the
console_suspend_enabled flag.
NOTE: this is short-term workaround until the OMAP serial driver
is fully converted to use runtime PM.
Signed-off-by: Kevin Hilman
---
arch/arm/mach-omap2/pm34xx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7255d9b..c8cbd00 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -55,7 +55,7 @@
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
{
- return (suspend_state != PM_SUSPEND_ON);
+ return (suspend_state != PM_SUSPEND_ON) && console_suspend_enabled;
}
#else
static inline bool is_suspending(void)
--
1.7.6
[2]
commit e83df17f178360a8e7874441bca04a710c869e42
Autho
OMAP3505 revisions?
Hi Sanjeev Am looking at your commit 4cac6018, which touches arch/arm/mach-omap2/id.c. That commit implements SoC detection for the 3505 in a different way than the implementations for other OMAP2+ devices: it doesn't enumerate the possible TAP revisions for OMAP3505. The TRM doesn't seem to list those, either. And unfortunately that is blocking some of the omap_chip removal work. Could you send me a list of the possible revision values for the 3505/3517, along with mappings to ES levels, please? thanks - Paul -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 14/25] OMAP4: PM: Add CPUX OFF mode support
Santosh writes:
> On Tuesday 13 September 2011 02:36 AM, Kevin Hilman wrote:
>> Santosh Shilimkar writes:
>>
>>> This patch adds the CPU0 and CPU1 off mode support. CPUX close switch
>>> retention (CSWR) is not supported by hardware design.
>>>
>>> The CPUx OFF mode isn't supported on OMAP4430 ES1.0
>>>
>>> CPUx sleep code is common for hotplug, suspend and CPUilde.
>>>
>>> Signed-off-by: Santosh Shilimkar
>>> Cc: Kevin Hilman
>>
>> [...]
>>
>>> @@ -38,6 +39,11 @@ void __iomem *omap4_get_scu_base(void)
>>>
>>> void __cpuinit platform_secondary_init(unsigned int cpu)
>>> {
>>> + /* Enable NS access to SMP bit for this CPU on EMU/HS devices */
>>> + if (cpu_is_omap443x()&& (omap_type() != OMAP2_DEVICE_TYPE_GP))
>>
>> A comment here about why this is 443x specific would be helpful.
>>
>> I see a comment in omap4_cpu_resume() that seems to indicate that SMP
>> bit is accessible on 446x NS devices, but repeating that commen here
>> would help future readability.
>>
> Ok. Will add comments here too. Was just trying to save some lines :)
heh, this is a negative side-effect of people caring primarily about
diffstat. :(
One other comment on this patch. You need spaces around the '&&' above.
Kevin
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Re: [alsa-devel] [PATCH 0/3] ASoC: tpa6130a2: model handling cleanup
On Tue, 2011-09-13 at 13:27 +0100, Mark Brown wrote: > On Tue, Sep 13, 2011 at 03:11:41PM +0300, Péter Ujfalusi wrote: > > > Would you have time to take a look at this series (it got the Tested-by > > from > > Jarkko)? > > I'm fine with it, I'm waiting for Liam's review. Acked-by: Liam Girdwood -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/5 v8] mfd: omap: usb: Runtime PM support for EHCI and OHCI drivers
On Fri, Sep 9, 2011 at 10:02 PM, Munegowda, Keshava wrote: > On Thu, Aug 25, 2011 at 12:31 PM, Keshava Munegowda > wrote: >> From: Keshava Munegowda >> >> The Hwmod structures and Runtime PM features are implemented >> For EHCI and OHCI drivers of OMAP3 and OMAP4. >> The global suspend/resume of EHCI and OHCI >> is validated on OMAP3430 sdp board with these patches. >> >> these patches are rebased to kevin's pm branch and >> usbhs latest mainline kernel patches >> >> TODO: >> - Adding pad configurations to Hwmods >> - Aggressive clock cutting in usb bus suspends >> - Remote Wakeup implementation using irq-chaining >> >> >> Benoit Cousson (1): >> arm: omap: usb: ehci and ohci hwmod structures for omap4 >> >> Keshava Munegowda (4): >> arm: omap: usb: ehci and ohci hwmod structures for omap3 >> arm: omap: usb: register hwmods of usbhs >> arm: omap: usb: device name change for the clk names of usbhs >> mfd: omap: usb: Runtime PM support >> >> arch/arm/mach-omap2/clock3xxx_data.c | 26 +- >> arch/arm/mach-omap2/clock44xx_data.c | 10 +- >> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 281 +++ >> arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 247 ++ >> arch/arm/mach-omap2/usb-host.c | 114 ++--- >> arch/arm/plat-omap/include/plat/usb.h | 3 - >> drivers/mfd/omap-usb-host.c | 733 >> +++- >> drivers/usb/host/ehci-omap.c | 17 +- >> drivers/usb/host/ohci-omap3.c | 18 +- >> 9 files changed, 891 insertions(+), 558 deletions(-) >> >> > > Hi Benoit Cousson > please ack this series; I am waiting for your ack > to lineup this USBHS runtime pm adaptions. > > regards > keshava Hi Benoit Cousson please ack this series; kevin has already given review by for the Runtime pm adaptations; balbi has recommended for you ack ; so,I request please give you ack by so that sameo can take these patches from my git tree : git://gitorious.org/~kmg/mirrors/kmg-usbhs-pm.git regards keshava -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: musb crash on suspend
Cliff Brake gmail.com> writes: > > On Thu, Jul 28, 2011 at 5:05 PM, Cliff Brake gmail.com> wrote: > > My kernel config is: > > CONFIG_USB_MUSB_HDRC=y > # CONFIG_USB_MUSB_TUSB6010 is not set > CONFIG_USB_MUSB_OMAP2PLUS=y > # CONFIG_USB_MUSB_AM35X is not set > # CONFIG_USB_MUSB_HOST is not set > # CONFIG_USB_MUSB_PERIPHERAL is not set > CONFIG_USB_MUSB_OTG=y > CONFIG_USB_GADGET_MUSB_HDRC=y > CONFIG_USB_MUSB_HDRC_HCD=y > # CONFIG_MUSB_PIO_ONLY is not set > CONFIG_USB_INVENTRA_DMA=y > > Its interesting that if I plug a host cable into the port, then it > seems to suspend. Its only when a host cable is not plugged in (ID > pin is not grounded) that I get this crash. > > Cliff > Hi Cliff, I have the same problem as you. Did you ever fix the problem? I don't think it is working when you have the usb cable plugged in. You don't see the error because it doesn't really go into suspend mode when the cable is plugged in. You should see something like "core_domain failed to suspend error 1" when you resume from suspend. I found the error to be in musb_core.c, musb_save_context(), when executing this line: musb->context.power = musb_readb(musb_base, MUSB_POWER); I wonder if the memory is suspending before the USB can save the context. Thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 00/26] gpio/omap: driver cleanup and fixes
This series is continuation of cleanup of OMAP GPIO driver and fixes.
The cleanup include getting rid of cpu_is_* checks wherever possible,
use of gpio_bank list instead of static array, use of unique platform
specific value associated data member to OMAP platforms to avoid
cpu_is_* checks. The series also include PM runtime support.*
Baseline: git://gitorious.org/khilman/linux-omap-pm.git
Branch: for_3.2/gpio-cleanup
Commit: 8323374
Test Details:
- Compile tested for omap1_defconfig and omap2plus_defconfig.
- OMAP1710-H3: Bootup test.
- OMAP2430/SDP, OMAP3430/SDP, OMAP4430/SDP: Functional testing.
- PM Testing on OMAP3430-SDP: retention, off_mode, system_wide
suspend and gpio wakeup.
v7:
- Use pm_runtime_put() instead of pm_runtime_put_sync_suspend()
- Keep *_runtime_get/put*() outside spinlock
- Remove additional checking of conditions in _restore_context()
From:
if (bank->regs->set_dataout && bank->regs->clear_dataout)
...
To:
if (bank->regs->set_dataout)
...
- Use SET_RUNTIME_PM_OPS and SET_SYSTEM_SLEEP_PM_OPS macros
- In [PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle,
protect the bank data elements and register access using spinlock in
runtime_suspend/resume() callbacks.
This is because these callbacks run with interrupts enabled.
- Add dbclk aliases for all GPIO modules. Without this, GPIO modules were not
getting the correct clock handle to enable/disable debounec clock.
- Fix log comments on the following patches:
[PATCH 19/25] gpio/omap: cleanup prepare_for_idle and resume_after_idle
[PATCH 20/25] gpio/omap: skip operations in runtime callbacks
[PATCH 24/25] gpio/omap: restore OE only after setting the output level
v6:
- Save and restore debounce registers for proper driver operation.
- Restore interrupt enable after all configuration to avoid spurious interrupts.
- Restore dataout register before oe register.
- Restore dataout into dataout_set or dataout based upon the OMAP version.
- Change register name from wkup_status to wkup_en.
- Remove wrapper around omap_pm_get_dev_context_loss_count(). Use it directly.
Also, changed the signature of get_context_loss_count in pdata and bank
structure
from int to u32.
- Use 'context' instead of 'ctx' for clarity wherever it is used.
- Merged two patches into one which are related to bank_is_mpuio() modification.
- Use shift operator instead of following:
+ .irqctrl= OMAP_MPUIO_GPIO_INT_EDGE / 2,
- Remove redundant check from the following
+ if (bank_is_mpuio(bank)) {
+ if (bank->regs->wkup_status) <--- redundant check
+ mpuio_init(bank);
- Change subject of following patch
[PATCH v5 15/22] gpio/omap: use readl in irq_handler for all access
into
[PATCH 14/25] gpio/omap: remove unnecessary bit-masking for read access
- Fix multi-line comments in
[PATCH v5 20/22] gpio/omap: cleanup prepare_for_idle and resume_after_idle
v5:
- Reduce runtime callback overhead when *_get/put_sync() called from probe()
and *_gpio_request/free().
- Dynamic context save within functions where context is modified instead of
saving all context within a common function.
- Removed call to mpuio_init() from omap_gpio_mod_init(). Both the functions are
called once during initialization in *_gpio_probe().
Call to omap_gpio_mod_init() has been removed from omap_gpio_request() on the
first access to gpio bank. One time initialization looks sufficient.
- In *_gpio_irq_handler() use *_put_sync_suspend() instead of *_put_sync().
- Removed hardcoding of OMAP16xx sysconfig register value and instead defined an
associated constant.
- Removed *_get_sync() call from *_gpio_suspend() and *_put_sync() call from
*_gpio_resume(). They got wrongly slipped into the code.
- Removed following redundant zero allocated initialization from
mach-omap2/gpio.c
+ pdata->regs->irqctrl = 0;
+ pdata->regs->edgectrl1 = 0;
+ pdata->regs->edgectrl2 = 0;
- Removed following redundant code in gpio-omap.c
-#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
v4:
- since all accesses to registers are 4-byte aligned, removing special
checks and handling of 16 and 32-bit wide bank registers and instead
use 32-bit read/write access consistently.
- redundant usage of MOD_REG_BIT has been corrected and replaced with
_gpio_rmw().
- omap_gpio_mod_init() function has been simplified further using _gpio_rmw().
- sysconfig register offset specific to omap16xx has been removed along
with its usage.
- additional logic to skip from suspend/resume:
if (!bank->regs->wkup_status || !bank->suspend_wakeup)
return 0;
if (!bank->regs->wkup_status || !bank->saved_wakeup)
return 0;
- separated mpuio related changes into a different patch from the patch where
wakeup status register related changes are done.
- Incorrect replacement of !cpu_class_is_omap2() in gpio_irq_type()
corrected:
+ if (!bank->regs->leveldete
[PATCH v7 05/26] gpio/omap: handle save/restore context in GPIO driver
From: Charulatha V
Modify omap_gpio_prepare_for_idle() & omap_gpio_resume_after_idle() functions
to handle save context & restore context respectively in the OMAP GPIO driver
itself instead of calling these functions from pm specific files.
For this, in gpio_prepare_for_idle(), call *_get_context_loss_count() and in
gpio_resume_after_idle() call it again. If the count is different, do restore
context. The workaround_enabled flag is no more required and is removed.
Signed-off-by: Charulatha V
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |5 +-
arch/arm/mach-omap2/pm34xx.c | 14
arch/arm/plat-omap/include/plat/gpio.h |5 +-
drivers/gpio/gpio-omap.c | 131 ++--
4 files changed, 65 insertions(+), 90 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 9f3a007..6c6b1a7 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -23,6 +23,7 @@
#include
#include
+#include
#include "powerdomain.h"
@@ -63,7 +64,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->bank_width = dev_attr->bank_width;
pdata->dbck_flag = dev_attr->dbck_flag;
pdata->virtual_irq_start = IH_GPIO_BASE + 32 * (id - 1);
-
+#ifdef CONFIG_PM
+ pdata->get_context_loss_count = omap_pm_get_dev_context_loss_count;
+#endif
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata) {
pr_err("gpio%d: Memory allocation failed\n", id);
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 1915050..b33cf3d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -85,16 +85,6 @@ static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
static struct powerdomain *cam_pwrdm;
-static inline void omap3_per_save_context(void)
-{
- omap_gpio_save_context();
-}
-
-static inline void omap3_per_restore_context(void)
-{
- omap_gpio_restore_context();
-}
-
static void omap3_enable_io_chain(void)
{
int timeout = 0;
@@ -393,8 +383,6 @@ void omap_sram_idle(void)
omap_uart_prepare_idle(2);
omap_uart_prepare_idle(3);
omap2_gpio_prepare_for_idle(per_going_off);
- if (per_next_state == PWRDM_POWER_OFF)
- omap3_per_save_context();
}
/* CORE */
@@ -462,8 +450,6 @@ void omap_sram_idle(void)
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
omap2_gpio_resume_after_idle();
- if (per_prev_state == PWRDM_POWER_OFF)
- omap3_per_restore_context();
omap_uart_resume_idle(2);
omap_uart_resume_idle(3);
}
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 58d0bf2..2c06e43 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -201,14 +201,15 @@ struct omap_gpio_platform_data {
bool loses_context; /* whether the bank would ever lose context */
struct omap_gpio_reg_offs *regs;
+
+ /* Return context loss count due to PM states changing */
+ u32 (*get_context_loss_count)(struct device *dev);
};
extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
extern void omap_set_gpio_debounce_time(int gpio, int enable);
-extern void omap_gpio_save_context(void);
-extern void omap_gpio_restore_context(void);
/*-*/
/* Wrappers for "new style" GPIO calls, using the new infrastructure
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 62d2213..c3cf01f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -72,9 +72,11 @@ struct gpio_bank {
bool loses_context;
int stride;
u32 width;
+ u32 context_loss_count;
u16 id;
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
+ u32 (*get_context_loss_count)(struct device *dev);
struct omap_gpio_reg_offs *regs;
};
@@ -1179,6 +1181,7 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
bank->loses_context = pdata->loses_context;
+ bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1323,11 +1326,11 @@ static struct syscore_ops omap_gpio_syscore_ops = {
#ifdef CONFIG_ARCH_OMAP2PLUS
-static int workaround_enabled;
+static vo
[PATCH v7 26/26] gpio/omap: add dbclk aliases for all gpio modules
Unless the dbclk aliases are assigned, clk_get(bank->dev, "dbclk")
would not fetch the associated clock handle. As a result, we would
not be able to turn on/off the debounce clock. This was preventing
the gpio modules going to low power mode whenever dbclk is enabled.
Signed-off-by: Tarun Kanti DebBarma
---
arch/arm/mach-omap2/clock3xxx_data.c |6 ++
arch/arm/mach-omap2/clock44xx_data.c |6 ++
2 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c
b/arch/arm/mach-omap2/clock3xxx_data.c
index ffd55b1..7238ec1 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3462,6 +3462,12 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("musb-am35x", "fck", &hsotgusb_fck_am35xx,
CK_AM35XX),
CLK(NULL, "hecc_ck", &hecc_ck, CK_AM35XX),
CLK(NULL, "uart4_ick",&uart4_ick_am35xx, CK_AM35XX),
+ CLK("omap_gpio.1", "dbclk",&gpio1_dbck,CK_3XXX),
+ CLK("omap_gpio.2", "dbclk",&gpio2_dbck,CK_3XXX),
+ CLK("omap_gpio.3", "dbclk",&gpio3_dbck,CK_3XXX),
+ CLK("omap_gpio.4", "dbclk",&gpio4_dbck,CK_3XXX),
+ CLK("omap_gpio.5", "dbclk",&gpio5_dbck,CK_3XXX),
+ CLK("omap_gpio.6", "dbclk",&gpio6_dbck,CK_3XXX),
};
diff --git a/arch/arm/mach-omap2/clock44xx_data.c
b/arch/arm/mach-omap2/clock44xx_data.c
index 2af0e3f..4986069 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3363,6 +3363,12 @@ static struct omap_clk omap44xx_clks[] = {
CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck,
CK_443X),
CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck,
CK_443X),
CLK("omap_wdt", "ick", &dummy_ck,
CK_443X),
+ CLK("omap_gpio.1", "dbclk",&gpio1_dbclk, CK_443X),
+ CLK("omap_gpio.2", "dbclk",&gpio2_dbclk, CK_443X),
+ CLK("omap_gpio.3", "dbclk",&gpio3_dbclk, CK_443X),
+ CLK("omap_gpio.4", "dbclk",&gpio4_dbclk, CK_443X),
+ CLK("omap_gpio.5", "dbclk",&gpio5_dbclk, CK_443X),
+ CLK("omap_gpio.6", "dbclk",&gpio6_dbclk, CK_443X),
};
int __init omap4xxx_clk_init(void)
--
1.7.0.4
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[PATCH v7 03/26] gpio/omap: make gpio_context part of gpio_bank structure
From: Charulatha V
Currently gpio_context array used to save gpio bank's context, is used only for
OMAP3 architecture. Move gpio_context as part of gpio_bank structure so that it
can be specific to each gpio bank and can be used for any OMAP architecture
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 76 -
1 files changed, 34 insertions(+), 42 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 65fed50..62d2213 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -30,6 +30,19 @@
static LIST_HEAD(omap_gpio_list);
+struct gpio_regs {
+ u32 irqenable1;
+ u32 irqenable2;
+ u32 wake_en;
+ u32 ctrl;
+ u32 oe;
+ u32 leveldetect0;
+ u32 leveldetect1;
+ u32 risingdetect;
+ u32 fallingdetect;
+ u32 dataout;
+};
+
struct gpio_bank {
struct list_head node;
unsigned long pbase;
@@ -43,7 +56,7 @@ struct gpio_bank {
#endif
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
-
+ struct gpio_regs context;
u32 saved_datain;
u32 saved_fallingdetect;
u32 saved_risingdetect;
@@ -66,23 +79,6 @@ struct gpio_bank {
struct omap_gpio_reg_offs *regs;
};
-#ifdef CONFIG_ARCH_OMAP3
-struct omap3_gpio_regs {
- u32 irqenable1;
- u32 irqenable2;
- u32 wake_en;
- u32 ctrl;
- u32 oe;
- u32 leveldetect0;
- u32 leveldetect1;
- u32 risingdetect;
- u32 fallingdetect;
- u32 dataout;
-};
-
-static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
-#endif
-
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
@@ -1499,33 +1495,31 @@ void omap2_gpio_resume_after_idle(void)
void omap_gpio_save_context(void)
{
struct gpio_bank *bank;
- int i = 0;
list_for_each_entry(bank, &omap_gpio_list, node) {
- i++;
if (!bank->loses_context)
continue;
- gpio_context[i].irqenable1 =
+ bank->context.irqenable1 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
- gpio_context[i].irqenable2 =
+ bank->context.irqenable2 =
__raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
- gpio_context[i].wake_en =
+ bank->context.wake_en =
__raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
- gpio_context[i].ctrl =
+ bank->context.ctrl =
__raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
- gpio_context[i].oe =
+ bank->context.oe =
__raw_readl(bank->base + OMAP24XX_GPIO_OE);
- gpio_context[i].leveldetect0 =
+ bank->context.leveldetect0 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
- gpio_context[i].leveldetect1 =
+ bank->context.leveldetect1 =
__raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- gpio_context[i].risingdetect =
+ bank->context.risingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
- gpio_context[i].fallingdetect =
+ bank->context.fallingdetect =
__raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- gpio_context[i].dataout =
+ bank->context.dataout =
__raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
}
}
@@ -1533,33 +1527,31 @@ void omap_gpio_save_context(void)
void omap_gpio_restore_context(void)
{
struct gpio_bank *bank;
- int i = 0;
list_for_each_entry(bank, &omap_gpio_list, node) {
- i++;
if (!bank->loses_context)
continue;
- __raw_writel(gpio_context[i].irqenable1,
+ __raw_writel(bank->context.irqenable1,
bank->base + OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(gpio_context[i].irqenable2,
+ __raw_writel(bank->context.irqenable2,
bank->base + OMAP24XX_GPIO_IRQENABLE2);
- __raw_writel(gpio_context[i].wake_en,
+ __raw_writel(bank->context.wake_en,
bank->base + OMAP24XX_GPIO_WAKE_EN);
- __raw_writel(gpio_context[i].ctrl,
+ __raw_writel(bank->context.ctrl,
bank->base + OMAP24XX_GPIO_CTRL);
- __raw_writel(gpio_context[i].oe,
+ __raw_writel(bank->context.oe,
bank->base + OMAP24XX_GPIO_OE);
- __raw_writel(gpio_context[i].leveldetect0,
+ __
[PATCH v7 07/26] gpio/omap: avoid cpu checks during module ena/disable
From: Charulatha V
Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio
request/free.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |2 +
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c | 53 ++--
3 files changed, 26 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index a430fb1..72a640d 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -98,6 +98,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
+ pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
break;
case 2:
pdata->bank_type = METHOD_GPIO_44XX;
@@ -114,6 +115,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
+ pdata->regs->ctrl = OMAP4_GPIO_CTRL;
break;
default:
WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index a93adeb..eaa6de3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs {
u16 clr_irqenable;
u16 debounce;
u16 debounce_en;
+ u16 ctrl;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 090feb8..84cd934 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -83,6 +83,7 @@ struct gpio_bank {
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
+#define GPIO_MOD_CTRL_BIT BIT(0)
static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
{
@@ -577,22 +578,18 @@ static int omap_gpio_request(struct gpio_chip *chip,
unsigned offset)
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
}
#endif
- if (!cpu_class_is_omap1()) {
- if (!bank->mod_usage) {
- void __iomem *reg = bank->base;
- u32 ctrl;
-
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- reg += OMAP24XX_GPIO_CTRL;
- else if (cpu_is_omap44xx())
- reg += OMAP4_GPIO_CTRL;
- ctrl = __raw_readl(reg);
- /* Module is enabled, clocks are not gated */
- ctrl &= 0xFFFE;
- __raw_writel(ctrl, reg);
- }
- bank->mod_usage |= 1 << offset;
+ if (bank->regs->ctrl && !bank->mod_usage) {
+ void __iomem *reg = bank->base + bank->regs->ctrl;
+ u32 ctrl;
+
+ ctrl = __raw_readl(reg);
+ /* Module is enabled, clocks are not gated */
+ ctrl &= ~GPIO_MOD_CTRL_BIT;
+ __raw_writel(ctrl, reg);
}
+
+ bank->mod_usage |= 1 << offset;
+
spin_unlock_irqrestore(&bank->lock, flags);
return 0;
@@ -625,22 +622,18 @@ static void omap_gpio_free(struct gpio_chip *chip,
unsigned offset)
__raw_writel(1 << offset, reg);
}
#endif
- if (!cpu_class_is_omap1()) {
- bank->mod_usage &= ~(1 << offset);
- if (!bank->mod_usage) {
- void __iomem *reg = bank->base;
- u32 ctrl;
-
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- reg += OMAP24XX_GPIO_CTRL;
- else if (cpu_is_omap44xx())
- reg += OMAP4_GPIO_CTRL;
- ctrl = __raw_readl(reg);
- /* Module is disabled, clocks are gated */
- ctrl |= 1;
- __raw_writel(ctrl, reg);
- }
+ bank->mod_usage &= ~(1 << offset);
+
+ if (bank->regs->ctrl && !bank->mod_usage) {
+ void __iomem *reg = bank->base + bank->regs->ctrl;
+ u32 ctrl;
+
+ ctrl = __raw_readl(reg);
+ /* Module is disabled, clocks are gated */
+ ctrl |= GPIO_MOD_CTRL_BIT;
+ __raw_writel(ctrl, reg);
}
+
_reset_gpio(bank, bank->chip.base + offset);
spin_unlock_irqrestore(&bank->lock, flags);
}
--
1.7.0.4
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[PATCH v7 02/26] gpio/omap: use flag to identify wakeup domain
From: Charulatha V
In omap3, save/restore context is implemented for GPIO banks 2-6 as GPIO bank1
is in wakeup domain. Instead of identifying bank's power domain by bank id,
use 'loses_context' flag which is filled by pwrdm_can_ever_lose_context()
during dev_init.
For getting the powerdomain pointer, omap_hwmod_get_pwrdm() is used.
omap_device_get_pwrdm() could not be used as the pwrdm information needs to be
filled in pdata, whereas omap_device_get_pwrdm() could be used only after
omap_device_build() call.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |6 ++
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c | 13 ++---
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index fb162fd..9f3a007 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -24,6 +24,8 @@
#include
#include
+#include "powerdomain.h"
+
static struct omap_device_pm_latency omap_gpio_latency[] = {
[0] = {
.deactivate_func = omap_device_idle_hwmods,
@@ -39,6 +41,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
struct omap_gpio_dev_attr *dev_attr;
char *name = "omap_gpio";
int id;
+ struct powerdomain *pwrdm;
/*
* extract the device id from name field available in the
@@ -107,6 +110,9 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
return -EINVAL;
}
+ pwrdm = omap_hwmod_get_pwrdm(oh);
+ pdata->loses_context = pwrdm_can_ever_lose_context(pwrdm);
+
od = omap_device_build(name, id - 1, oh, pdata,
sizeof(*pdata), omap_gpio_latency,
ARRAY_SIZE(omap_gpio_latency),
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index dd330ed..58d0bf2 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -198,6 +198,7 @@ struct omap_gpio_platform_data {
int bank_width; /* GPIO bank width */
int bank_stride;/* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
+ bool loses_context; /* whether the bank would ever lose context */
struct omap_gpio_reg_offs *regs;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index fabe2c0..65fed50 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -56,6 +56,7 @@ struct gpio_bank {
u32 dbck_enable_mask;
struct device *dev;
bool dbck_flag;
+ bool loses_context;
int stride;
u32 width;
u16 id;
@@ -1181,7 +1182,7 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
-
+ bank->loses_context = pdata->loses_context;
bank->regs = pdata->regs;
if (bank->regs->set_dataout && bank->regs->clr_dataout)
@@ -1337,8 +1338,7 @@ void omap2_gpio_prepare_for_idle(int off_mode)
u32 l1 = 0, l2 = 0;
int j;
- /* TODO: Do not use cpu_is_omap34xx */
- if ((cpu_is_omap34xx()) && (bank->id == 0))
+ if (!bank->loses_context)
continue;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1405,8 +1405,7 @@ void omap2_gpio_resume_after_idle(void)
u32 l = 0, gen, gen0, gen1;
int j;
- /* TODO: Do not use cpu_is_omap34xx */
- if ((cpu_is_omap34xx()) && (bank->id == 0))
+ if (!bank->loses_context)
continue;
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
@@ -1505,7 +1504,7 @@ void omap_gpio_save_context(void)
list_for_each_entry(bank, &omap_gpio_list, node) {
i++;
- if (bank->id == 0)
+ if (!bank->loses_context)
continue;
gpio_context[i].irqenable1 =
@@ -1539,7 +1538,7 @@ void omap_gpio_restore_context(void)
list_for_each_entry(bank, &omap_gpio_list, node) {
i++;
- if (bank->id == 0)
+ if (!bank->loses_context)
continue;
__raw_writel(gpio_context[i].irqenable1,
--
1.7.0.4
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[PATCH v7 12/26] gpio/omap: cleanup omap_gpio_mod_init function
With register offsets now defined for respective OMAP versions we can get rid
of cpu_class_* checks. This function now has common initialization code for
all OMAP versions. Initialization specific to OMAP16xx has been moved within
omap16xx_gpio_init().
Signed-off-by: Tarun Kanti DebBarma
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio16xx.c | 35 +++-
drivers/gpio/gpio-omap.c | 71 +--
2 files changed, 51 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 46bb57a..86ac415 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -24,6 +24,9 @@
#define OMAP1610_GPIO4_BASE0xfffbbc00
#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
+/* smart idle, enable wakeup */
+#define SYSCONFIG_WORD 0x14
+
/* mpu gpio */
static struct __initdata resource omap16xx_mpu_gpio_resources[] = {
{
@@ -218,12 +221,42 @@ static struct __initdata platform_device *
omap16xx_gpio_dev[] = {
static int __init omap16xx_gpio_init(void)
{
int i;
+ void __iomem *base;
+ struct resource *res;
+ struct platform_device *pdev;
+ struct omap_gpio_platform_data *pdata;
if (!cpu_is_omap16xx())
return -EINVAL;
- for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
+ for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++) {
+ pdev = omap16xx_gpio_dev[i];
+ pdata = pdev->dev.platform_data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (unlikely(!res)) {
+ dev_err(&pdev->dev, "Invalid mem resource.\n");
+ return -ENODEV;
+ }
+
+ base = ioremap(res->start, resource_size(res));
+ if (unlikely(!base)) {
+ dev_err(&pdev->dev, "ioremap failed.\n");
+ return -ENOMEM;
+ }
+
+ __raw_writel(SYSCONFIG_WORD, base + OMAP1610_GPIO_SYSCONFIG);
+ iounmap(base);
+
+ /*
+* Enable system clock for GPIO module.
+* The CAM_CLK_CTRL *is* really the right place.
+*/
+ omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
+ ULPD_CAM_CLK_CTRL);
+
platform_device_register(omap16xx_gpio_dev[i]);
+ }
return 0;
}
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index e51804b..2a57d0b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -605,7 +605,6 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
if (!(isr & 1))
continue;
-#ifdef CONFIG_ARCH_OMAP1
/*
* Some chips can't respond to both rising and falling
* at the same time. If this irq was requested with
@@ -615,7 +614,6 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
*/
if (bank->toggle_mask & (1 << gpio_index))
_toggle_gpio_edge_triggering(bank, gpio_index);
-#endif
generic_handle_irq(gpio_irq);
}
@@ -893,62 +891,24 @@ static void __init omap_gpio_show_rev(struct gpio_bank
*bank)
*/
static struct lock_class_key gpio_lock_class;
-/* TODO: Cleanup cpu_is_* checks */
static void omap_gpio_mod_init(struct gpio_bank *bank)
{
- if (cpu_class_is_omap2()) {
- if (cpu_is_omap44xx()) {
- __raw_writel(0x, bank->base +
- OMAP4_GPIO_IRQSTATUSCLR0);
- __raw_writel(0x, bank->base +
-OMAP4_GPIO_DEBOUNCENABLE);
- /* Initialize interface clk ungated, module enabled */
- __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
- } else if (cpu_is_omap34xx()) {
- __raw_writel(0x, bank->base +
- OMAP24XX_GPIO_IRQENABLE1);
- __raw_writel(0x, bank->base +
- OMAP24XX_GPIO_IRQSTATUS1);
- __raw_writel(0x, bank->base +
- OMAP24XX_GPIO_DEBOUNCE_EN);
-
- /* Initialize interface clk ungated, module enabled */
- __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
- }
- } else if (cpu_class_is_omap1()) {
- if (bank_is_mpuio(bank)) {
- __raw_writew(0x, bank->base +
- OMAP_MPUIO_GPIO_MASKIT / b
[PATCH v7 16/26] gpio/omap: fix bankwidth for OMAP7xx MPUIO
From: Charulatha V
In all OMAP1 SoCs, the MPUIO bank width is 16 bits. But, in OMAP7xx,
it is wrongly initialised to 32. Fix this.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio7xx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 433491c..4771d6b 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_width = 32,
.is_mpuio = true,
+ .bank_width = 16,
.bank_stride= 2,
.regs = &omap7xx_mpuio_regs,
};
--
1.7.0.4
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[PATCH v7 10/26] gpio/omap: remove hardcoded offsets in context save/restore
It is not required to use hard-coded offsets any more in context save and
restore functions and instead use the generic offsets which have been correctly
initialized during device registration.
Signed-off-by: Tarun Kanti DebBarma
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |2 +
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c | 41 ++-
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 06fa913..5ce695c 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -94,6 +94,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->irqstatus = OMAP24XX_GPIO_IRQSTATUS1;
pdata->regs->irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2;
pdata->regs->irqenable = OMAP24XX_GPIO_IRQENABLE1;
+ pdata->regs->irqenable2 = OMAP24XX_GPIO_IRQENABLE2;
pdata->regs->set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1;
pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1;
pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
@@ -116,6 +117,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->irqstatus = OMAP4_GPIO_IRQSTATUS0;
pdata->regs->irqstatus2 = OMAP4_GPIO_IRQSTATUS1;
pdata->regs->irqenable = OMAP4_GPIO_IRQSTATUSSET0;
+ pdata->regs->irqenable2 = OMAP4_GPIO_IRQSTATUSSET1;
pdata->regs->set_irqenable = OMAP4_GPIO_IRQSTATUSSET0;
pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0;
pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 9590532..61865b4 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -184,6 +184,7 @@ struct omap_gpio_reg_offs {
u16 irqstatus;
u16 irqstatus2;
u16 irqenable;
+ u16 irqenable2;
u16 set_irqenable;
u16 clr_irqenable;
u16 debounce;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index d9bf7ac..9715cf2 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1371,45 +1371,42 @@ void omap2_gpio_resume_after_idle(void)
static void omap_gpio_save_context(struct gpio_bank *bank)
{
bank->context.irqenable1 =
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ __raw_readl(bank->base + bank->regs->irqenable);
bank->context.irqenable2 =
- __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ __raw_readl(bank->base + bank->regs->irqenable2);
bank->context.wake_en =
- __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
- bank->context.ctrl = __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
- bank->context.oe = __raw_readl(bank->base + OMAP24XX_GPIO_OE);
+ __raw_readl(bank->base + bank->regs->wkup_en);
+ bank->context.ctrl = __raw_readl(bank->base + bank->regs->ctrl);
+ bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
bank->context.leveldetect0 =
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
+ __raw_readl(bank->base + bank->regs->leveldetect0);
bank->context.leveldetect1 =
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+ __raw_readl(bank->base + bank->regs->leveldetect1);
bank->context.risingdetect =
- __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
+ __raw_readl(bank->base + bank->regs->risingdetect);
bank->context.fallingdetect =
- __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
- bank->context.dataout =
- __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
+ bank->context.dataout = __raw_readl(bank->base + bank->regs->dataout);
}
static void omap_gpio_restore_context(struct gpio_bank *bank)
{
__raw_writel(bank->context.irqenable1,
- bank->base + OMAP24XX_GPIO_IRQENABLE1);
+ bank->base + bank->regs->irqenable);
__raw_writel(bank->context.irqenable2,
- bank->base + OMAP24XX_GPIO_IRQENABLE2);
+ bank->base + bank->regs->irqenable2);
__raw_writel(bank->context.wake_en,
- bank->base + OMAP24XX_GPIO_WAKE_EN);
- __raw_writel(bank->context.ctrl, bank->base + OMAP24XX_GPIO_CTRL);
- __raw_writel(bank->context.oe, bank->base + OMAP24XX_GPIO_OE);
+ bank->base + bank->regs->wkup_en);
+ __raw_writel(bank->context.ctrl, bank->base +
[PATCH v7 14/26] gpio/omap: remove unnecessary bit-masking for read access
Remove un-necessary bit masking. Since the register are 4 byte aligned and readl would work as is. The 'enabled' mask is already taking care to mask for bank width. Signed-off-by: Charulatha V Signed-off-by: Tarun Kanti DebBarma Reviewed-by: Santosh Shilimkar --- drivers/gpio/gpio-omap.c |2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 876e387..d614c6d 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -571,8 +571,6 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) enabled = _get_gpio_irqbank_mask(bank); isr_saved = isr = __raw_readl(isr_reg) & enabled; - if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) - isr &= 0x; if (bank->level_mask) level_mask = bank->level_mask & enabled; -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 09/26] gpio/omap: use level/edge detect reg offsets
By adding level and edge detection register offsets and then initializing them
correctly according to OMAP versions during device registrations we can now
remove
lot of revision checks in these functions.
Signed-off-by: Tarun Kanti DebBarma
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |8 ++
arch/arm/plat-omap/include/plat/gpio.h |4 +
drivers/gpio/gpio-omap.c | 118 ++--
3 files changed, 48 insertions(+), 82 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index b1364b6..06fa913 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -100,6 +100,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
+ pdata->regs->leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0;
+ pdata->regs->leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1;
+ pdata->regs->risingdetect = OMAP24XX_GPIO_RISINGDETECT;
+ pdata->regs->fallingdetect = OMAP24XX_GPIO_FALLINGDETECT;
break;
case 2:
pdata->bank_type = METHOD_GPIO_44XX;
@@ -118,6 +122,10 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
pdata->regs->ctrl = OMAP4_GPIO_CTRL;
pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
+ pdata->regs->leveldetect0 = OMAP4_GPIO_LEVELDETECT0;
+ pdata->regs->leveldetect1 = OMAP4_GPIO_LEVELDETECT1;
+ pdata->regs->risingdetect = OMAP4_GPIO_RISINGDETECT;
+ pdata->regs->fallingdetect = OMAP4_GPIO_FALLINGDETECT;
break;
default:
WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 7ea1608..9590532 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -190,6 +190,10 @@ struct omap_gpio_reg_offs {
u16 debounce_en;
u16 ctrl;
u16 wkup_en;
+ u16 leveldetect0;
+ u16 leveldetect1;
+ u16 risingdetect;
+ u16 fallingdetect;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 82707e3..d9bf7ac 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -257,15 +257,9 @@ static inline void set_24xx_gpio_triggering(struct
gpio_bank *bank, int gpio,
bank->enabled_non_wakeup_gpios &= ~gpio_bit;
}
- if (cpu_is_omap44xx()) {
- bank->level_mask =
- __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
- __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
- } else {
- bank->level_mask =
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
- __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
- }
+ bank->level_mask =
+ __raw_readl(bank->base + bank->regs->leveldetect0) |
+ __raw_readl(bank->base + bank->regs->leveldetect1);
}
#endif
@@ -405,12 +399,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned
type)
if (type & ~IRQ_TYPE_SENSE_MASK)
return -EINVAL;
- /* OMAP1 allows only only edge triggering */
- if (!cpu_class_is_omap2()
- && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
+ bank = irq_data_get_irq_chip_data(d);
+
+ if (!bank->regs->leveldetect0 &&
+ (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
return -EINVAL;
- bank = irq_data_get_irq_chip_data(d);
spin_lock_irqsave(&bank->lock, flags);
retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
spin_unlock_irqrestore(&bank->lock, flags);
@@ -658,9 +652,8 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
isr &= 0x;
- if (cpu_class_is_omap2()) {
+ if (bank->level_mask)
level_mask = bank->level_mask & enabled;
- }
/* clear edge sensitive interrupts before handler(s) are
called so that we don't miss any interrupt occurred while
@@ -1269,40 +1262,18 @@ void omap2_gpio_prepare_for_idle(int off_mode)
if (!(bank->enabled_non_wakeup_gpios))
goto save_gpio_context;
- if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
- bank->saved_datain = __raw_readl(bank->base +
-
[PATCH v7 17/26] gpio/omap: use pm-runtime framework
Call runtime pm APIs pm_runtime_get_sync() and pm_runtime_put_sync()
for enabling/disabling clocks appropriately. Remove syscore_ops and
instead use SET_RUNTIME_PM_OPS macro.
Signed-off-by: Charulatha V
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 65 +
1 files changed, 42 insertions(+), 23 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 6efacea..b5be8b8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -21,6 +21,7 @@
#include
#include
#include
+#include
#include
#include
@@ -79,6 +80,8 @@ struct gpio_bank {
struct omap_gpio_reg_offs *regs;
};
+static void omap_gpio_mod_init(struct gpio_bank *bank);
+
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
#define GPIO_MOD_CTRL_BIT BIT(0)
@@ -478,8 +481,14 @@ static int omap_gpio_request(struct gpio_chip *chip,
unsigned offset)
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
unsigned long flags;
- spin_lock_irqsave(&bank->lock, flags);
+ /*
+* If this is the first gpio_request for the bank,
+* enable the bank module.
+*/
+ if (!bank->mod_usage)
+ pm_runtime_get_sync(bank->dev);
+ spin_lock_irqsave(&bank->lock, flags);
/* Set trigger to none. You need to enable the desired trigger with
* request_irq() or set_irq_type().
*/
@@ -535,6 +544,13 @@ static void omap_gpio_free(struct gpio_chip *chip,
unsigned offset)
_reset_gpio(bank, bank->chip.base + offset);
spin_unlock_irqrestore(&bank->lock, flags);
+
+ /*
+* If this is the last gpio to be freed in the bank,
+* disable the bank module.
+*/
+ if (!bank->mod_usage)
+ pm_runtime_put_sync(bank->dev);
}
/*
@@ -560,6 +576,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
bank = irq_get_handler_data(irq);
isr_reg = bank->base + bank->regs->irqstatus;
+ pm_runtime_get_sync(bank->dev);
if (WARN_ON(!isr_reg))
goto exit;
@@ -621,6 +638,7 @@ static void gpio_irq_handler(unsigned int irq, struct
irq_desc *desc)
exit:
if (!unmasked)
chained_irq_exit(chip, desc);
+ pm_runtime_put(bank->dev);
}
static void gpio_irq_shutdown(struct irq_data *d)
@@ -1027,6 +1045,7 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
}
pm_runtime_enable(bank->dev);
+ pm_runtime_irq_safe(bank->dev);
pm_runtime_get_sync(bank->dev);
if (bank->is_mpuio)
@@ -1036,6 +1055,8 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
omap_gpio_chip_init(bank);
omap_gpio_show_rev(bank);
+ pm_runtime_put_sync(bank->dev);
+
list_add_tail(&bank->node, &omap_gpio_list);
return ret;
@@ -1046,7 +1067,9 @@ err_exit:
return ret;
}
-static int omap_gpio_suspend(void)
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
+static int omap_gpio_suspend(struct device *dev)
{
struct gpio_bank *bank;
@@ -1064,12 +1087,13 @@ static int omap_gpio_suspend(void)
bank->saved_wakeup = __raw_readl(wake_status);
_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags);
+ pm_runtime_put_sync(dev);
}
return 0;
}
-static void omap_gpio_resume(void)
+static int omap_gpio_resume(struct device *dev)
{
struct gpio_bank *bank;
@@ -1078,20 +1102,17 @@ static void omap_gpio_resume(void)
unsigned long flags;
if (!bank->regs->wkup_en)
- return;
+ return 0;
+ pm_runtime_get_sync(dev);
spin_lock_irqsave(&bank->lock, flags);
_gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
spin_unlock_irqrestore(&bank->lock, flags);
}
-}
-static struct syscore_ops omap_gpio_syscore_ops = {
- .suspend= omap_gpio_suspend,
- .resume = omap_gpio_resume,
-};
+ return 0;
+}
-#ifdef CONFIG_ARCH_OMAP2PLUS
static void omap_gpio_save_context(struct gpio_bank *bank);
static void omap_gpio_restore_context(struct gpio_bank *bank);
@@ -1138,6 +1159,7 @@ save_gpio_context:
bank->get_context_loss_count(bank->dev);
omap_gpio_save_context(bank);
+ pm_runtime_put(bank->dev);
}
}
@@ -1153,6 +1175,8 @@ void omap2_gpio_resume_after_idle(void)
if (!bank->loses_context)
continue;
+ pm_runtime_get_sync(bank->dev);
+
for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
[PATCH v7 06/26] gpio/omap: make non-wakeup GPIO part of pdata
From: Charulatha V
Non-wakeup GPIOs are available only in OMAP2. Avoid cpu_is checks by making
non_wakeup_gpios as part of pdata.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/gpio.c |8
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c |8 +---
3 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 6c6b1a7..a430fb1 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -75,6 +75,14 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
switch (oh->class->rev) {
case 0:
+ if (id == 1)
+ /* non-wakeup GPIO pins for OMAP2 Bank1 */
+ pdata->non_wakeup_gpios = 0xe203ffc0;
+ else if (id == 2)
+ /* non-wakeup GPIO pins for OMAP2 Bank2 */
+ pdata->non_wakeup_gpios = 0x08700040;
+ /* fall through */
+
case 1:
pdata->bank_type = METHOD_GPIO_24XX;
pdata->regs->revision = OMAP24XX_GPIO_REVISION;
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 2c06e43..a93adeb 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -199,6 +199,7 @@ struct omap_gpio_platform_data {
int bank_stride;/* Only needed for omap1 MPUIO */
bool dbck_flag; /* dbck required or not - True for OMAP3&4 */
bool loses_context; /* whether the bank would ever lose context */
+ u32 non_wakeup_gpios;
struct omap_gpio_reg_offs *regs;
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c3cf01f..090feb8 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1021,13 +1021,6 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
/* Initialize interface clk ungated, module enabled */
__raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
- } else if (cpu_is_omap24xx()) {
- static const u32 non_wakeup_gpios[] = {
- 0xe203ffc0, 0x08700040
- };
- if (bank->id < ARRAY_SIZE(non_wakeup_gpios))
- bank->non_wakeup_gpios =
- non_wakeup_gpios[bank->id];
}
} else if (cpu_class_is_omap1()) {
if (bank_is_mpuio(bank)) {
@@ -1180,6 +1173,7 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
bank->dbck_flag = pdata->dbck_flag;
bank->stride = pdata->bank_stride;
bank->width = pdata->bank_width;
+ bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
bank->loses_context = pdata->loses_context;
bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
--
1.7.0.4
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[PATCH v7 01/26] gpio/omap: remove dependency on gpio_bank_count
From: Charulatha V
The gpio_bank_count is the count of number of GPIO devices in a SoC. Remove this
dependency from the driver by using list. Also remove the dependency on array of
pointers to gpio_bank struct of all GPIO devices.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio15xx.c |1 -
arch/arm/mach-omap1/gpio16xx.c |2 -
arch/arm/mach-omap1/gpio7xx.c |2 -
arch/arm/mach-omap2/gpio.c |1 -
arch/arm/plat-omap/include/plat/gpio.h |3 -
drivers/gpio/gpio-omap.c | 163
6 files changed, 80 insertions(+), 92 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 399da4c..f8c15ea 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -115,7 +115,6 @@ static int __init omap15xx_gpio_init(void)
platform_device_register(&omap15xx_mpu_gpio);
platform_device_register(&omap15xx_gpio);
- gpio_bank_count = 2;
return 0;
}
postcore_initcall(omap15xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 0f399bd..df4bb44 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -221,8 +221,6 @@ static int __init omap16xx_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(omap16xx_gpio_dev); i++)
platform_device_register(omap16xx_gpio_dev[i]);
- gpio_bank_count = ARRAY_SIZE(omap16xx_gpio_dev);
-
return 0;
}
postcore_initcall(omap16xx_gpio_init);
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 5ab63ea..923eaa1 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -282,8 +282,6 @@ static int __init omap7xx_gpio_init(void)
for (i = 0; i < ARRAY_SIZE(omap7xx_gpio_dev); i++)
platform_device_register(omap7xx_gpio_dev[i]);
- gpio_bank_count = ARRAY_SIZE(omap7xx_gpio_dev);
-
return 0;
}
postcore_initcall(omap7xx_gpio_init);
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 2765cdc..fb162fd 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -121,7 +121,6 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
omap_device_disable_idle_on_suspend(od);
- gpio_bank_count++;
return 0;
}
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 91e8de3..dd330ed 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -202,9 +202,6 @@ struct omap_gpio_platform_data {
struct omap_gpio_reg_offs *regs;
};
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-extern int gpio_bank_count;
-
extern void omap2_gpio_prepare_for_idle(int off_mode);
extern void omap2_gpio_resume_after_idle(void);
extern void omap_set_gpio_debounce(int gpio, int enable);
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index f0208a9..fabe2c0 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -28,7 +28,10 @@
#include
#include
+static LIST_HEAD(omap_gpio_list);
+
struct gpio_bank {
+ struct list_head node;
unsigned long pbase;
void __iomem *base;
u16 irq;
@@ -55,6 +58,7 @@ struct gpio_bank {
bool dbck_flag;
int stride;
u32 width;
+ u16 id;
void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
@@ -78,15 +82,6 @@ struct omap3_gpio_regs {
static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
#endif
-/*
- * TODO: Cleanup gpio_bank usage as it is having information
- * related to all instances of the device
- */
-static struct gpio_bank *gpio_bank;
-
-/* TODO: Analyze removing gpio_bank_count usage from driver code */
-int gpio_bank_count;
-
#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
@@ -869,9 +864,8 @@ static struct platform_device omap_mpuio_device = {
/* could list the /proc/iomem resources */
};
-static inline void mpuio_init(void)
+static inline void mpuio_init(struct gpio_bank *bank)
{
- struct gpio_bank *bank = &gpio_bank[0];
platform_set_drvdata(&omap_mpuio_device, bank);
if (platform_driver_register(&omap_mpuio_driver) == 0)
@@ -879,13 +873,13 @@ static inline void mpuio_init(void)
}
#else
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
#endif /* 16xx */
#else
#define bank_is_mpuio(bank)0
-static inline void mpuio_init(void) {}
+static inline void mpuio_init(struct gpio_bank *bank) {}
#endif
@@ -1007,20 +1001,8 @@ static void __init omap_gpio_show_rev(struct gpio_bank
*bank)
*/
static struct lock_class_key gpio_lock_class;
-static inline int init_gpio_info(struct platform_device *pdev)
-
[PATCH v7 04/26] gpio/omap: fix pwrdm_post_transition call sequence
From: Charulatha V
The context lost count is modified in omap_sram_idle() path when
pwrdm_post_transition() is called. But pwrdm_post_transition() is called
only after omap_gpio_resume_after_idle() is called. Correct this so that
context lost count is modified before calling omap_gpio_resume_after_idle().
This would be useful when OMAP GPIO save/restore context is called by
the OMAP GPIO driver itself.
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap2/pm34xx.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 7255d9b..1915050 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -363,7 +363,6 @@ void omap_sram_idle(void)
printk(KERN_ERR "Invalid mpu state in sram_idle\n");
return;
}
- pwrdm_pre_transition();
/* NEON control */
if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
@@ -386,6 +385,8 @@ void omap_sram_idle(void)
if (!console_trylock())
goto console_still_active;
+ pwrdm_pre_transition();
+
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
@@ -455,6 +456,8 @@ void omap_sram_idle(void)
}
omap3_intc_resume_idle();
+ pwrdm_post_transition();
+
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
@@ -478,8 +481,6 @@ console_still_active:
omap3_disable_io_chain();
}
- pwrdm_post_transition();
-
clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
}
--
1.7.0.4
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[PATCH v7 23/26] gpio/omap: enable irq at the end of all configuration in restore
From: Nishanth Menon
Setup the interrupt enable registers only after we have configured the
required edge and required configurations, not before, to prevent
spurious events as part of restore routine.
Signed-off-by: Nishanth Menon
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index a1aeeed..4687d6b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1310,10 +1310,6 @@ void omap2_gpio_resume_after_idle(void)
static void omap_gpio_restore_context(struct gpio_bank *bank)
{
- __raw_writel(bank->context.irqenable1,
- bank->base + bank->regs->irqenable);
- __raw_writel(bank->context.irqenable2,
- bank->base + bank->regs->irqenable2);
__raw_writel(bank->context.wake_en,
bank->base + bank->regs->wkup_en);
__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
@@ -1333,6 +1329,11 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
__raw_writel(bank->context.debounce_en,
bank->base + bank->regs->debounce_en);
}
+
+ __raw_writel(bank->context.irqenable1,
+ bank->base + bank->regs->irqenable);
+ __raw_writel(bank->context.irqenable2,
+ bank->base + bank->regs->irqenable2);
}
#else
#define omap_gpio_suspend NULL
--
1.7.0.4
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[PATCH v7 15/26] gpio/omap: remove bank->method & METHOD_* macros
From: Charulatha V
The only bank->type (method) used in the OMAP GPIO driver is MPUIO type as they
need to be handled separately. Identify the same using a flag and remove all
METHOD_* macros.
mpuio_init() function is defined under #ifdefs. It is required only in case
of MPUIO bank type and only when PM operations are supported by it.
This is applicable only in case of OMAP16xx SoC's MPUIO GPIO bank type.
For all the other cases it is a dummy function. Hence clean up the same
and remove all the OMAP SoC specific #ifdefs.
Signed-off-by: Charulatha V
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio15xx.c |3 +-
arch/arm/mach-omap1/gpio16xx.c |6 +
arch/arm/mach-omap1/gpio7xx.c |8 +--
arch/arm/mach-omap2/gpio.c |2 -
arch/arm/plat-omap/include/plat/gpio.h |8 +--
drivers/gpio/gpio-omap.c | 38 +--
6 files changed, 10 insertions(+), 55 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 950e467..634903e 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -47,7 +47,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
+ .is_mpuio = true,
.bank_width = 16,
.bank_stride= 1,
.regs = &omap15xx_mpuio_regs,
@@ -90,7 +90,6 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_1510,
.bank_width = 16,
.regs = &omap15xx_gpio_regs,
};
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 86ac415..1c5f90e 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -53,7 +53,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
+ .is_mpuio = true,
.bank_width = 16,
.bank_stride= 1,
.regs = &omap16xx_mpuio_regs,
@@ -100,7 +100,6 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@@ -130,7 +129,6 @@ static struct __initdata resource
omap16xx_gpio2_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio2_config = {
.virtual_irq_start = IH_GPIO_BASE + 16,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@@ -160,7 +158,6 @@ static struct __initdata resource
omap16xx_gpio3_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio3_config = {
.virtual_irq_start = IH_GPIO_BASE + 32,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
@@ -190,7 +187,6 @@ static struct __initdata resource
omap16xx_gpio4_resources[] = {
static struct __initdata omap_gpio_platform_data omap16xx_gpio4_config = {
.virtual_irq_start = IH_GPIO_BASE + 48,
- .bank_type = METHOD_GPIO_1610,
.bank_width = 16,
.regs = &omap16xx_gpio_regs,
};
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 207a23c..433491c 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -52,8 +52,8 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
.virtual_irq_start = IH_MPUIO_BASE,
- .bank_type = METHOD_MPUIO,
.bank_width = 32,
+ .is_mpuio = true,
.bank_stride= 2,
.regs = &omap7xx_mpuio_regs,
};
@@ -94,7 +94,6 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
.virtual_irq_start = IH_GPIO_BASE,
- .bank_type = METHOD_GPIO_7XX,
.bank_width = 32,
.regs = &omap7xx_gpio_regs,
};
@@ -124,7 +123,6 @
[PATCH v7 24/26] gpio/omap: restore OE only after setting the output level
From: Nishanth Menon
Setup the dataout register before restoring OE. This is to make
sure that we have valid data in dataout register which would be
made available in output pins as soon as OE is enabled. Else,
there is risk of unknown data getting out into gpio pins.
Signed-off-by: Nishanth Menon
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 4687d6b..165a598 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1313,7 +1313,6 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
__raw_writel(bank->context.wake_en,
bank->base + bank->regs->wkup_en);
__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
- __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
__raw_writel(bank->context.leveldetect0,
bank->base + bank->regs->leveldetect0);
__raw_writel(bank->context.leveldetect1,
@@ -1323,6 +1322,8 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
__raw_writel(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
+ __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
+
if (bank->dbck_enable_mask) {
__raw_writel(bank->context.debounce, bank->base +
bank->regs->debounce);
--
1.7.0.4
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[PATCH v7 25/26] gpio/omap: handle set_dataout reg capable IP on restore
From: Nishanth Menon
GPIO IP revisions such as those used in OMAP4 have a set_dataout
while the previous revisions used a single dataout register.
Depending on what is available restore the dataout settings
to the right register.
Signed-off-by: Nishanth Menon
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c |9 +++--
1 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 165a598..c597303 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1048,7 +1048,7 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
bank->get_context_loss_count = pdata->get_context_loss_count;
bank->regs = pdata->regs;
- if (bank->regs->set_dataout && bank->regs->clr_dataout)
+ if (bank->regs->set_dataout)
bank->set_dataout = _set_gpio_dataout_reg;
else
bank->set_dataout = _set_gpio_dataout_mask;
@@ -1321,7 +1321,12 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
bank->base + bank->regs->risingdetect);
__raw_writel(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
- __raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
+ if (bank->regs->set_dataout)
+ __raw_writel(bank->context.dataout,
+ bank->base + bank->regs->set_dataout);
+ else
+ __raw_writel(bank->context.dataout,
+ bank->base + bank->regs->dataout);
__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
if (bank->dbck_enable_mask) {
--
1.7.0.4
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[PATCH v7 21/26] gpio/omap: remove omap_gpio_save_context overhead
Context is now saved dynamically in respective functions whenever and
whichever registers are modified. This avoid overhead of saving all
registers context in the runtime suspend callback.
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 62 ++---
1 files changed, 36 insertions(+), 26 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 628e42f..c84f620 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -98,6 +98,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int
gpio, int is_input)
else
l &= ~(1 << gpio);
__raw_writel(l, reg);
+ bank->context.oe = l;
}
@@ -128,6 +129,7 @@ static void _set_gpio_dataout_mask(struct gpio_bank *bank,
int gpio, int enable)
else
l &= ~gpio_bit;
__raw_writel(l, reg);
+ bank->context.dataout = l;
}
static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
@@ -217,9 +219,20 @@ static inline void set_gpio_trigger(struct gpio_bank
*bank, int gpio,
_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
trigger & IRQ_TYPE_EDGE_FALLING);
- if (likely(!(bank->non_wakeup_gpios & gpio_bit)))
+ bank->context.leveldetect0 =
+ __raw_readl(bank->base + bank->regs->leveldetect0);
+ bank->context.leveldetect1 =
+ __raw_readl(bank->base + bank->regs->leveldetect1);
+ bank->context.risingdetect =
+ __raw_readl(bank->base + bank->regs->risingdetect);
+ bank->context.fallingdetect =
+ __raw_readl(bank->base + bank->regs->fallingdetect);
+ if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
_gpio_rmw(base, bank->regs->wkup_en, gpio_bit,
trigger != 0);
+ bank->context.wake_en =
+ __raw_readl(bank->base + bank->regs->wkup_en);
+ }
/* This part needs to be executed always for OMAP{34xx, 44xx} */
if (cpu_is_omap34xx() || cpu_is_omap44xx() ||
@@ -306,6 +319,8 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int
gpio, int trigger)
/* Enable wake-up during idle for dynamic tick */
_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
+ bank->context.wake_en =
+ __raw_readl(bank->base + bank->regs->wkup_en);
__raw_writel(l, reg);
}
return 0;
@@ -398,6 +413,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank,
int gpio_mask)
}
__raw_writel(l, reg);
+ bank->context.irqenable1 = l;
}
static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
@@ -418,6 +434,7 @@ static void _disable_gpio_irqbank(struct gpio_bank *bank,
int gpio_mask)
}
__raw_writel(l, reg);
+ bank->context.irqenable1 = l;
}
static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int
enable)
@@ -509,6 +526,7 @@ static int omap_gpio_request(struct gpio_chip *chip,
unsigned offset)
/* Module is enabled, clocks are not gated */
ctrl &= ~GPIO_MOD_CTRL_BIT;
__raw_writel(ctrl, reg);
+ bank->context.ctrl = ctrl;
}
bank->mod_usage |= 1 << offset;
@@ -526,9 +544,12 @@ static void omap_gpio_free(struct gpio_chip *chip,
unsigned offset)
spin_lock_irqsave(&bank->lock, flags);
- if (bank->regs->wkup_en)
+ if (bank->regs->wkup_en) {
/* Disable wake-up during idle for dynamic tick */
_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
+ bank->context.wake_en =
+ __raw_readl(bank->base + bank->regs->wkup_en);
+ }
bank->mod_usage &= ~(1 << offset);
@@ -540,6 +561,7 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned
offset)
/* Module is disabled, clocks are gated */
ctrl |= GPIO_MOD_CTRL_BIT;
__raw_writel(ctrl, reg);
+ bank->context.ctrl = ctrl;
}
_reset_gpio(bank, bank->chip.base + offset);
@@ -900,6 +922,8 @@ static void omap_gpio_mod_init(struct gpio_bank *bank)
bank->regs->irqenable_inv == false);
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
+ bank->context.irqenable1 =
+ __raw_readl(bank->base + bank->regs->irqenable);
}
static __init void
@@ -1087,6 +,7 @@ static int omap_gpio_suspend(struct device *dev)
spin_lock_irqsave(&bank->lock, flags);
bank->saved_wakeup = __raw_readl(wake_status);
_gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
+ bank->
[PATCH v7 22/26] gpio/omap: save and restore debounce registers
From: Nishanth Menon
GPIO debounce registers need to be saved and restored for proper functioning
of driver. To save the registers, we cannot cut the clock before the save,
hence move the clk disable after the save.
Signed-off-by: Nishanth Menon
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 10 ++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index c84f620..a1aeeed 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -42,6 +42,8 @@ struct gpio_regs {
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
+ u32 debounce;
+ u32 debounce_en;
};
struct gpio_bank {
@@ -202,6 +204,8 @@ static void _set_gpio_debounce(struct gpio_bank *bank,
unsigned gpio,
bank->dbck_enable_mask = val;
__raw_writel(val, reg);
+ bank->context.debounce = debounce;
+ bank->context.debounce_en = val;
}
static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
@@ -1323,6 +1327,12 @@ static void omap_gpio_restore_context(struct gpio_bank
*bank)
__raw_writel(bank->context.fallingdetect,
bank->base + bank->regs->fallingdetect);
__raw_writel(bank->context.dataout, bank->base + bank->regs->dataout);
+ if (bank->dbck_enable_mask) {
+ __raw_writel(bank->context.debounce, bank->base +
+ bank->regs->debounce);
+ __raw_writel(bank->context.debounce_en,
+ bank->base + bank->regs->debounce_en);
+ }
}
#else
#define omap_gpio_suspend NULL
--
1.7.0.4
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[PATCH v7 18/26] gpio/omap: optimize suspend and resume functions
There is no need to operate on all the banks every time the function is called.
Just operate on the current bank passed by the framework.
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 53 +
1 files changed, 25 insertions(+), 28 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index b5be8b8..6249b8f 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1044,6 +1044,8 @@ static int __devinit omap_gpio_probe(struct
platform_device *pdev)
goto err_free;
}
+ platform_set_drvdata(pdev, bank);
+
pm_runtime_enable(bank->dev);
pm_runtime_irq_safe(bank->dev);
pm_runtime_get_sync(bank->dev);
@@ -1071,44 +1073,39 @@ err_exit:
static int omap_gpio_suspend(struct device *dev)
{
- struct gpio_bank *bank;
-
- list_for_each_entry(bank, &omap_gpio_list, node) {
- void __iomem *base = bank->base;
- void __iomem *wake_status;
- unsigned long flags;
-
- if (!bank->regs->wkup_en)
- return 0;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ void __iomem *base = bank->base;
+ void __iomem *wake_status;
+ unsigned long flags;
- wake_status = bank->base + bank->regs->wkup_en;
+ if (!bank->regs->wkup_en || !bank->suspend_wakeup)
+ return 0;
- spin_lock_irqsave(&bank->lock, flags);
- bank->saved_wakeup = __raw_readl(wake_status);
- _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
- spin_unlock_irqrestore(&bank->lock, flags);
- pm_runtime_put_sync(dev);
- }
+ wake_status = bank->base + bank->regs->wkup_en;
+ spin_lock_irqsave(&bank->lock, flags);
+ bank->saved_wakeup = __raw_readl(wake_status);
+ _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
+ spin_unlock_irqrestore(&bank->lock, flags);
+ pm_runtime_put_sync(dev);
return 0;
}
static int omap_gpio_resume(struct device *dev)
{
- struct gpio_bank *bank;
-
- list_for_each_entry(bank, &omap_gpio_list, node) {
- void __iomem *base = bank->base;
- unsigned long flags;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ void __iomem *base = bank->base;
+ unsigned long flags;
- if (!bank->regs->wkup_en)
- return 0;
+ if (!bank->regs->wkup_en || !bank->saved_wakeup)
+ return 0;
- pm_runtime_get_sync(dev);
- spin_lock_irqsave(&bank->lock, flags);
- _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
- spin_unlock_irqrestore(&bank->lock, flags);
- }
+ pm_runtime_get_sync(dev);
+ spin_lock_irqsave(&bank->lock, flags);
+ _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
+ spin_unlock_irqrestore(&bank->lock, flags);
return 0;
}
--
1.7.0.4
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[PATCH v7 08/26] gpio/omap: further cleanup using wkup_en register
Wakeup enable register offset initialized according to OMAP versions
during device registration. Use this to avoid version checks.
Starting with OMAP4, legacy registers should not be used in combination
with the updated regsiters. Use wkup_en register consistently for
all SoCs wherever applicable.
Signed-off-by: Tarun Kanti DebBarma
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio16xx.c |1 +
arch/arm/mach-omap2/gpio.c |2 +
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c | 108 ++--
4 files changed, 23 insertions(+), 89 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index df4bb44..1eb47e2 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -89,6 +89,7 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.irqenable = OMAP1610_GPIO_IRQENABLE1,
.set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
.clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
+ .wkup_en= OMAP1610_GPIO_WAKEUPENABLE,
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 72a640d..b1364b6 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -99,6 +99,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL;
pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN;
pdata->regs->ctrl = OMAP24XX_GPIO_CTRL;
+ pdata->regs->wkup_en = OMAP24XX_GPIO_WAKE_EN;
break;
case 2:
pdata->bank_type = METHOD_GPIO_44XX;
@@ -116,6 +117,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void
*unused)
pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME;
pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE;
pdata->regs->ctrl = OMAP4_GPIO_CTRL;
+ pdata->regs->wkup_en = OMAP4_GPIO_IRQWAKEN0;
break;
default:
WARN(1, "Invalid gpio bank_type\n");
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index eaa6de3..7ea1608 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -189,6 +189,7 @@ struct omap_gpio_reg_offs {
u16 debounce;
u16 debounce_en;
u16 ctrl;
+ u16 wkup_en;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 84cd934..82707e3 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -50,10 +50,8 @@ struct gpio_bank {
u16 irq;
u16 virtual_irq_start;
int method;
-#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
u32 suspend_wakeup;
u32 saved_wakeup;
-#endif
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
struct gpio_regs context;
@@ -598,30 +596,15 @@ static int omap_gpio_request(struct gpio_chip *chip,
unsigned offset)
static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
{
struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
+ void __iomem *base = bank->base;
unsigned long flags;
spin_lock_irqsave(&bank->lock, flags);
-#ifdef CONFIG_ARCH_OMAP16XX
- if (bank->method == METHOD_GPIO_1610) {
- /* Disable wake-up during idle for dynamic tick */
- void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
- __raw_writel(1 << offset, reg);
- }
-#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
- if (bank->method == METHOD_GPIO_24XX) {
- /* Disable wake-up during idle for dynamic tick */
- void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
- __raw_writel(1 << offset, reg);
- }
-#endif
-#ifdef CONFIG_ARCH_OMAP4
- if (bank->method == METHOD_GPIO_44XX) {
+
+ if (bank->regs->wkup_en)
/* Disable wake-up during idle for dynamic tick */
- void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
- __raw_writel(1 << offset, reg);
- }
-#endif
+ _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
+
bank->mod_usage &= ~(1 << offset);
if (bank->regs->ctrl && !bank->mod_usage) {
@@ -1071,8 +1054,8 @@ omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int
irq_start,
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = gpio_irq_type;
- /* REVISIT: assuming only 16xx supports MPUIO wake events */
- if (cpu_is_omap16xx())
+
+ if (bank->regs->wkup_en)
ct->chip.
[PATCH v7 19/26] gpio/omap: cleanup prepare_for_idle and resume_after_idle
Since *_prepare_for_idle() and *_resume_after_idle() are called
with interrupts disabled they should be kept as simple as possible.
So, moving most of the stuff to *_runtime_suspend/resume() callbacks.
Signed-off-by: Tarun Kanti DebBarma
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
drivers/gpio/gpio-omap.c | 236 +
1 files changed, 131 insertions(+), 105 deletions(-)
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 6249b8f..8ec9f68 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -1114,135 +1114,157 @@ static int omap_gpio_resume(struct device *dev)
static void omap_gpio_save_context(struct gpio_bank *bank);
static void omap_gpio_restore_context(struct gpio_bank *bank);
-void omap2_gpio_prepare_for_idle(int off_mode)
+static int omap_gpio_runtime_suspend(struct device *dev)
{
- struct gpio_bank *bank;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ u32 l1 = 0, l2 = 0;
+ int j;
+ unsigned long flags;
- list_for_each_entry(bank, &omap_gpio_list, node) {
- u32 l1 = 0, l2 = 0;
- int j;
+ spin_lock_irqsave(&bank->lock, flags);
+ /*
+* If going to OFF, remove triggering for all
+* non-wakeup GPIOs. Otherwise spurious IRQs will be
+* generated. See OMAP2420 Errata item 1.101.
+*/
+ if (!(bank->enabled_non_wakeup_gpios))
+ goto save_gpio_context;
- if (!bank->loses_context)
- continue;
+ bank->saved_datain = __raw_readl(bank->base +
+ bank->regs->datain);
+ l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
+ l2 = __raw_readl(bank->base + bank->regs->risingdetect);
- for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
- clk_disable(bank->dbck);
+ bank->saved_fallingdetect = l1;
+ bank->saved_risingdetect = l2;
+ l1 &= ~bank->enabled_non_wakeup_gpios;
+ l2 &= ~bank->enabled_non_wakeup_gpios;
- if (!off_mode)
- continue;
+ __raw_writel(l1, bank->base + bank->regs->fallingdetect);
+ __raw_writel(l2, bank->base + bank->regs->risingdetect);
- /* If going to OFF, remove triggering for all
-* non-wakeup GPIOs. Otherwise spurious IRQs will be
-* generated. See OMAP2420 Errata item 1.101. */
- if (!(bank->enabled_non_wakeup_gpios))
- goto save_gpio_context;
+save_gpio_context:
+ if (bank->get_context_loss_count)
+ bank->context_loss_count =
+ bank->get_context_loss_count(bank->dev);
- bank->saved_datain = __raw_readl(bank->base +
- bank->regs->datain);
- l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
- l2 = __raw_readl(bank->base + bank->regs->risingdetect);
+ omap_gpio_save_context(bank);
+ for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+ clk_disable(bank->dbck);
+
+ spin_unlock_irqrestore(&bank->lock, flags);
+ return 0;
+}
- bank->saved_fallingdetect = l1;
- bank->saved_risingdetect = l2;
- l1 &= ~bank->enabled_non_wakeup_gpios;
- l2 &= ~bank->enabled_non_wakeup_gpios;
+static int omap_gpio_runtime_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct gpio_bank *bank = platform_get_drvdata(pdev);
+ u32 context_lost_cnt_after;
+ u32 l = 0, gen, gen0, gen1;
+ int j;
+ unsigned long flags;
- __raw_writel(l1, bank->base + bank->regs->fallingdetect);
- __raw_writel(l2, bank->base + bank->regs->risingdetect);
+ spin_lock_irqsave(&bank->lock, flags);
+ for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
+ clk_enable(bank->dbck);
-save_gpio_context:
- if (bank->get_context_loss_count)
- bank->context_loss_count =
- bank->get_context_loss_count(bank->dev);
+ if (bank->get_context_loss_count) {
+ context_lost_cnt_after =
+ bank->get_context_loss_count(bank->dev);
+ if (context_lost_cnt_after != bank->context_loss_count ||
+ !context_lost_cnt_after) {
+ omap_gpio_restore_context(bank);
+ } else {
+ spin_unlock_irqrestore(&bank->lock, flags);
+ return 0;
+ }
+ }
- omap_gpio_save_context(bank);
- pm_runtime_put(
[PATCH v7 20/26] gpio/omap: skip operations in runtime callbacks
The *_runtime_suspend/resume() callbacks perform basic operations necessary before/after turning off/on clocks using *_runtime_put/get*(). This happens when modules are fully initialized and functional. They don't have to be called during initialization. As we need the clocks to be turned on/off using *_runtime_get/put*() in *_probe() make sure we return from these callbacks during this time. Signed-off-by: Tarun Kanti DebBarma Reviewed-by: Santosh Shilimkar --- drivers/gpio/gpio-omap.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 8ec9f68..628e42f 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c @@ -1122,6 +1122,9 @@ static int omap_gpio_runtime_suspend(struct device *dev) int j; unsigned long flags; + if (!bank->mod_usage) + return 0; + spin_lock_irqsave(&bank->lock, flags); /* * If going to OFF, remove triggering for all @@ -1166,6 +1169,9 @@ static int omap_gpio_runtime_resume(struct device *dev) int j; unsigned long flags; + if (!bank->mod_usage) + return 0; + spin_lock_irqsave(&bank->lock, flags); for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_enable(bank->dbck); -- 1.7.0.4 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v7 11/26] gpio/omap: cleanup set_gpio_triggering function
Getting rid of ifdefs within the function by adding register offset intctrl
and associating OMAP_GPIO_INT_CONTROL in respective SoC specific files.
Also, use wkup_status register consistently instead of referring to wakeup
clear and wakeup set register offsets.
Signed-off-by: Charulatha V
Signed-off-by: Tarun Kanti DebBarma
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio15xx.c |2 +
arch/arm/mach-omap1/gpio16xx.c |3 +
arch/arm/mach-omap1/gpio7xx.c |2 +
arch/arm/plat-omap/include/plat/gpio.h |3 +
drivers/gpio/gpio-omap.c | 148
5 files changed, 46 insertions(+), 112 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index f8c15ea..2adfece 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -42,6 +42,7 @@ static struct omap_gpio_reg_offs omap15xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true,
+ .irqctrl= OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap15xx_mpu_gpio_config = {
@@ -83,6 +84,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.irqstatus = OMAP1510_GPIO_INT_STATUS,
.irqenable = OMAP1510_GPIO_INT_MASK,
.irqenable_inv = true,
+ .irqctrl= OMAP1510_GPIO_INT_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/mach-omap1/gpio16xx.c b/arch/arm/mach-omap1/gpio16xx.c
index 1eb47e2..46bb57a 100644
--- a/arch/arm/mach-omap1/gpio16xx.c
+++ b/arch/arm/mach-omap1/gpio16xx.c
@@ -45,6 +45,7 @@ static struct omap_gpio_reg_offs omap16xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT,
.irqenable = OMAP_MPUIO_GPIO_MASKIT,
.irqenable_inv = true,
+ .irqctrl= OMAP_MPUIO_GPIO_INT_EDGE,
};
static struct __initdata omap_gpio_platform_data omap16xx_mpu_gpio_config = {
@@ -90,6 +91,8 @@ static struct omap_gpio_reg_offs omap16xx_gpio_regs = {
.set_irqenable = OMAP1610_GPIO_SET_IRQENABLE1,
.clr_irqenable = OMAP1610_GPIO_CLEAR_IRQENABLE1,
.wkup_en= OMAP1610_GPIO_WAKEUPENABLE,
+ .edgectrl1 = OMAP1610_GPIO_EDGE_CTRL1,
+ .edgectrl2 = OMAP1610_GPIO_EDGE_CTRL2,
};
static struct __initdata omap_gpio_platform_data omap16xx_gpio1_config = {
diff --git a/arch/arm/mach-omap1/gpio7xx.c b/arch/arm/mach-omap1/gpio7xx.c
index 923eaa1..207a23c 100644
--- a/arch/arm/mach-omap1/gpio7xx.c
+++ b/arch/arm/mach-omap1/gpio7xx.c
@@ -47,6 +47,7 @@ static struct omap_gpio_reg_offs omap7xx_mpuio_regs = {
.irqstatus = OMAP_MPUIO_GPIO_INT / 2,
.irqenable = OMAP_MPUIO_GPIO_MASKIT / 2,
.irqenable_inv = true,
+ .irqctrl= OMAP_MPUIO_GPIO_INT_EDGE >> 1,
};
static struct __initdata omap_gpio_platform_data omap7xx_mpu_gpio_config = {
@@ -88,6 +89,7 @@ static struct omap_gpio_reg_offs omap7xx_gpio_regs = {
.irqstatus = OMAP7XX_GPIO_INT_STATUS,
.irqenable = OMAP7XX_GPIO_INT_MASK,
.irqenable_inv = true,
+ .irqctrl= OMAP7XX_GPIO_INT_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap7xx_gpio1_config = {
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 61865b4..92a6262 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -195,6 +195,9 @@ struct omap_gpio_reg_offs {
u16 leveldetect1;
u16 risingdetect;
u16 fallingdetect;
+ u16 irqctrl;
+ u16 edgectrl1;
+ u16 edgectrl2;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 9715cf2..e51804b 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -199,49 +199,25 @@ static void _set_gpio_debounce(struct gpio_bank *bank,
unsigned gpio,
__raw_writel(val, reg);
}
-#ifdef CONFIG_ARCH_OMAP2PLUS
-static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
+static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
int trigger)
{
void __iomem *base = bank->base;
u32 gpio_bit = 1 << gpio;
- if (cpu_is_omap44xx()) {
- _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit,
- trigger & IRQ_TYPE_LEVEL_LOW);
- _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit,
- trigger & IRQ_TYPE_LEVEL_HIGH);
- _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit,
- trigger & IRQ_TYPE_EDGE_RISING);
- _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit,
- trigger & IRQ_TYPE_EDGE_FALLING);
- } else {
-
[PATCH v7 13/26] gpio/omap: use pinctrl offset instead of macro
From: Charulatha V
Use regs->pinctrl field instead of using the macro OMAP1510_GPIO_PIN_CONTROL
Signed-off-by: Charulatha V
Reviewed-by: Santosh Shilimkar
---
arch/arm/mach-omap1/gpio15xx.c |1 +
arch/arm/plat-omap/include/plat/gpio.h |1 +
drivers/gpio/gpio-omap.c |8 +++-
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap1/gpio15xx.c b/arch/arm/mach-omap1/gpio15xx.c
index 2adfece..950e467 100644
--- a/arch/arm/mach-omap1/gpio15xx.c
+++ b/arch/arm/mach-omap1/gpio15xx.c
@@ -85,6 +85,7 @@ static struct omap_gpio_reg_offs omap15xx_gpio_regs = {
.irqenable = OMAP1510_GPIO_INT_MASK,
.irqenable_inv = true,
.irqctrl= OMAP1510_GPIO_INT_CONTROL,
+ .pinctrl= OMAP1510_GPIO_PIN_CONTROL,
};
static struct __initdata omap_gpio_platform_data omap15xx_gpio_config = {
diff --git a/arch/arm/plat-omap/include/plat/gpio.h
b/arch/arm/plat-omap/include/plat/gpio.h
index 92a6262..a4e5ef3 100644
--- a/arch/arm/plat-omap/include/plat/gpio.h
+++ b/arch/arm/plat-omap/include/plat/gpio.h
@@ -198,6 +198,7 @@ struct omap_gpio_reg_offs {
u16 irqctrl;
u16 edgectrl1;
u16 edgectrl2;
+ u16 pinctrl;
bool irqenable_inv;
};
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 2a57d0b..876e387 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -485,15 +485,13 @@ static int omap_gpio_request(struct gpio_chip *chip,
unsigned offset)
*/
_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
-#ifdef CONFIG_ARCH_OMAP15XX
- if (bank->method == METHOD_GPIO_1510) {
- void __iomem *reg;
+ if (bank->regs->pinctrl) {
+ void __iomem *reg = bank->base + bank->regs->pinctrl;
/* Claim the pin for MPU */
- reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
__raw_writel(__raw_readl(reg) | (1 << offset), reg);
}
-#endif
+
if (bank->regs->ctrl && !bank->mod_usage) {
void __iomem *reg = bank->base + bank->regs->ctrl;
u32 ctrl;
--
1.7.0.4
--
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Re: [PATCH 3/3] iommu/core: split mapping to page sizes as supported by the hardware
On Tue, Sep 13, 2011 at 1:44 PM, Roedel, Joerg wrote: > Not necessarily. You could implement this side-by-side with the old code > until all drivers are converted and remove the old code then. This keeps > bisectability. Ok. >> > Intel IOMMU does not support arbitrary page-sizes, afaik. >> >> It does; besides the usual 4K it has "super page sizes" support of >> 2MB, 1GB, 512GB and 1TB. > > But the value ~0xfffUL indicates support for 4k, 8k, 16k .. 2^63, no? Yes, I have done this intentionally, in order to retain the existing behavior for IOMMU drivers which are already capable of handling arbitrary page sizes (intel-iommu handles this in software, see hardware_largepage_caps() and the code that uses it). Long term, it might make more sense to remove hardware_largepage_caps() (and the logic around it) and instead just declare the real page sizes the hardware supports when calling register_iommu(), but I guess it's up to Intel guys. For now it's just safer to declare ~0xfffUL which really means: keep calling me with sizes and alignments that are an order of 4KB, just like you always did. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 0/3] ASoC: tpa6130a2: model handling cleanup
On Tue, Sep 13, 2011 at 03:11:41PM +0300, Péter Ujfalusi wrote: > Would you have time to take a look at this series (it got the Tested-by from > Jarkko)? I'm fine with it, I'm waiting for Liam's review. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [alsa-devel] [PATCH 0/3] ASoC: tpa6130a2: model handling cleanup
Hello Mark, Tony, On Tuesday 30 August 2011 13:39:51 Ujfalusi, Peter wrote: > Hello, > > Small cleanup for the tpa6130a2 driver for model handling: > Remove the model_id from platform_data, and use the device name/device_data > to distinguish between the supported models of TPA. Would you have time to take a look at this series (it got the Tested-by from Jarkko)? Thank you, Péter -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 1/4] AM3517 : support for suspend/resume
Hi
On Wed, Aug 31, 2011 at 4:28 AM, Hilman, Kevin wrote:
>
> Abhilash K V writes:
>
>> 1. Patch to disable dynamic sleep (as it is not supported
>>on AM35xx).
>> 2. Imported the unique suspend/resume sequence for AM3517,
>>contained in the new file arch/arm/mach-omap2/sleep3517.S.
>> 3. Added omap3517_ to symbol-names in sleep3517.S which are common
>>with sleep34xx.S, and added appropriate checks.
>>
>> There are still 3 caveats:
>>
>> 1. If "no_console_suspend" is enabled (via boot-args), the device
>>doesnot resume but simply hangs.
>> 2. Every second and subsequent attempt to suspend/resume prints this
>> slow-path
>>WARNING (for both uart1 and uart2), while resuming :
>>[ 70.943939] omap_hwmod: uart1: idle state can only be entered from
>>enabled state
>> 3. Wakeup using the TSC2004 touch-screen controller is not supported.
>>
>> Signed-off-by: Ranjith Lohithakshan
>> Reviewed-by: Vaibhav Hiremath
>> Signed-off-by: Abhilash K V
>
> In addition to Russell's comments about using the latest code from
> mainline, I have some comments below.
[Abhilash K V] I have reworked the patch against the tip (as suggested by
Russell).
And I've incorporated all of Kevin's comments too.
There is one "known" issue left which needs to be closed before I can submit v2
of this patch.
With no_console_suspend, suspend to RAM hangs right now on AM3517, after
the message:
Disabling non-boot CPUs ...
There is no error message or dump.
I found that this crash is happening in a call to pr_warning(), from
_omap_device_deactivate().
The same code does not produce this issue on omap34xx due to this snippet from
omap_sram_idle() :
/* PER */
if (per_next_state < PWRDM_POWER_ON) {
per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
omap_uart_prepare_idle(2);
omap_uart_prepare_idle(3);
omap2_gpio_prepare_for_idle(per_going_off);
if (per_next_state == PWRDM_POWER_OFF)
omap3_per_save_context();
}
/* CORE */
if (core_next_state < PWRDM_POWER_ON) {
omap_uart_prepare_idle(0);
omap_uart_prepare_idle(1);
if (core_next_state == PWRDM_POWER_OFF) {
omap3_core_save_context();
omap3_cm_save_context();
}
}
This happens in preparation to the suspend operation (I,e. the WFI).
As seen here, on 34xx the sequence in which the uarts are disabled is 2, 3, 0
and 1.The console-uart, which is uart-1 here (starting from uart-0) is disabled
last.
For AM3517 EVM, the console-uart is uart-2 and this ought to be disabled at the
last to prevent this crash from occurring.
So my suggestion is to use a console_uart flag to store the appropriate uart
no. for that platform rather than hard-code it and to ensure that this uart is
disabled at the last.
Another point that complicates matters is that uart-1 and uart-2 are in
different power domains (CORE and PER respectively) - so that would amount to
using the console-uart
no. to decide whether CORE or PER power-domains are disabled first.
Would this have any side-effects?
Is there a better way to go?
-Abhilash
>
>
>> ---
>> arch/arm/mach-omap2/Makefile|2 +-
>> arch/arm/mach-omap2/control.c |7 ++-
>> arch/arm/mach-omap2/control.h |1 +
>> arch/arm/mach-omap2/pm.h|4 +
>> arch/arm/mach-omap2/pm34xx.c| 18 -
>> arch/arm/mach-omap2/sleep3517.S | 144
>> +++
>> 6 files changed, 170 insertions(+), 6 deletions(-)
>> create mode 100644 arch/arm/mach-omap2/sleep3517.S
>>
>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>> index 46f5fbc..3fdf086 100644
>> --- a/arch/arm/mach-omap2/Makefile
>> +++ b/arch/arm/mach-omap2/Makefile
>> @@ -61,7 +61,7 @@ endif
>> ifeq ($(CONFIG_PM),y)
>> obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
>> obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
>> -obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o \
>> +obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o sleep3517.o \
>> cpuidle34xx.o
>> obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o
>> obj-$(CONFIG_PM_DEBUG) += pm-debug.o
>> diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
>> index da53ba3..7d2d8a8 100644
>> --- a/arch/arm/mach-omap2/control.c
>> +++ b/arch/arm/mach-omap2/control.c
>> @@ -284,10 +284,13 @@ void omap3_save_scratchpad_contents(void)
>>* The restore pointer is stored into the scratchpad.
>>*/
>> scratchpad_contents.boot_config_ptr = 0x0;
>> - if (cpu_is_omap3630())
>> + if (cpu_is_omap3505() || cpu_is_omap3517()) {
>> + scratchpad_contents.public_restore_ptr =
>> + virt_to_phys(omap3517_get_restore_pointer());
>
Re: [PATCH 3/3] iommu/core: split mapping to page sizes as supported by the hardware
On Tue, Sep 13, 2011 at 06:34:23AM -0400, Ohad Ben-Cohen wrote:
> Hi Joerg,
>
> On Tue, Sep 13, 2011 at 1:10 PM, Roedel, Joerg wrote:
> > Please split this patch into the core-change and patches for the
> > individual iommu-drivers and post this as a seperate patch-set.
>
> But we'll be breaking bisectibility this way, no?
Not necessarily. You could implement this side-by-side with the old code
until all drivers are converted and remove the old code then. This keeps
bisectability.
> > Intel IOMMU does not support arbitrary page-sizes, afaik.
>
> It does; besides the usual 4K it has "super page sizes" support of
> 2MB, 1GB, 512GB and 1TB.
But the value ~0xfffUL indicates support for 4k, 8k, 16k .. 2^63, no?
>
> >> + pr_debug("map: iova 0x%lx pa 0x%lx size 0x%lx\n", iova,
> >> + (unsigned long)paddr, size);
> >
> > Please keep the debug-code in a seperate patch in your dev-tree. No need
> > for it to be merged upstream.
>
> It's actually useful sometimes to have those around - it's off by
> default, and can be enabled only when needed (CONFIG_DYNAMIC_DEBUG).
>
> But I don't mind removing them.
Ah right, it is just debug, so I am fine keeping it.
Joerg
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Re: [PATCH 3/3] iommu/core: split mapping to page sizes as supported by the hardware
Hi Joerg,
On Tue, Sep 13, 2011 at 1:10 PM, Roedel, Joerg wrote:
> Please split this patch into the core-change and patches for the
> individual iommu-drivers and post this as a seperate patch-set.
But we'll be breaking bisectibility this way, no ?
> Intel IOMMU does not support arbitrary page-sizes, afaik.
It does; besides the usual 4K it has "super page sizes" support of
2MB, 1GB, 512GB and 1TB.
>> + pr_debug("map: iova 0x%lx pa 0x%lx size 0x%lx\n", iova,
>> + (unsigned long)paddr, size);
>
> Please keep the debug-code in a seperate patch in your dev-tree. No need
> for it to be merged upstream.
It's actually useful sometimes to have those around - it's off by
default, and can be enabled only when needed (CONFIG_DYNAMIC_DEBUG).
But I don't mind removing them.
Thanks,
Ohad.
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Re: [PATCH 1/3] iommu/core: add fault reporting mechanism
On Tue, Sep 13, 2011 at 1:00 PM, Roedel, Joerg wrote: > For now I think it is the best to remove this IOMMU_ERROR thing. It is > inherent to the function call already. When a real use-case comes up we > can easily add it later. I'm fine with this, will post an update. Thanks, Ohad. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 3/3] iommu/core: split mapping to page sizes as supported by the hardware
On Wed, Sep 07, 2011 at 02:53:24PM -0400, Ohad Ben-Cohen wrote:
> drivers/iommu/amd_iommu.c | 20 ++-
> drivers/iommu/intel-iommu.c | 20 ++-
> drivers/iommu/iommu.c | 129
> +++
> drivers/iommu/msm_iommu.c |8 ++-
> drivers/iommu/omap-iommu.c |6 ++-
> drivers/iommu/omap-iovmm.c | 12 +---
> include/linux/iommu.h |7 +-
> virt/kvm/iommu.c|4 +-
> 8 files changed, 176 insertions(+), 30 deletions(-)
Please split this patch into the core-change and patches for the
individual iommu-drivers and post this as a seperate patch-set.
>
> diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
> index a14f8dc..5cdfa91 100644
> --- a/drivers/iommu/amd_iommu.c
> +++ b/drivers/iommu/amd_iommu.c
> @@ -2488,12 +2488,30 @@ static unsigned device_dma_ops_init(void)
> }
>
> /*
> + * This bitmap is used to advertise the page sizes our hardware support
> + * to the IOMMU core, which will then use this information to split
> + * physically contiguous memory regions it is mapping into page sizes
> + * that we support.
> + *
> + * Traditionally the IOMMU core just handed us the mappings directly,
> + * after making sure the size is an order of a 4KB page and that the
> + * mapping has natural alignment.
> + *
> + * To retain this behavior, we currently advertise that we support
> + * all page sizes that are an order of 4KB.
> + *
> + * If at some point we'd like to utilize the IOMMU core's new behavior,
> + * we could change this to advertise the real page sizes we support.
> + */
> +static unsigned long amd_iommu_pgsizes = ~0xFFFUL;
> +
> +/*
> * The function which clues the AMD IOMMU driver into dma_ops.
> */
>
> void __init amd_iommu_init_api(void)
> {
> - register_iommu(&amd_iommu_ops);
> + register_iommu(&amd_iommu_ops, &amd_iommu_pgsizes, BITS_PER_LONG);
> }
>
> int __init amd_iommu_init_dma_ops(void)
> diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
> index c621c98..a8c91a6 100644
> --- a/drivers/iommu/intel-iommu.c
> +++ b/drivers/iommu/intel-iommu.c
> @@ -3426,6 +3426,24 @@ static struct notifier_block device_nb = {
> .notifier_call = device_notifier,
> };
>
> +/*
> + * This bitmap is used to advertise the page sizes our hardware support
> + * to the IOMMU core, which will then use this information to split
> + * physically contiguous memory regions it is mapping into page sizes
> + * that we support.
> + *
> + * Traditionally the IOMMU core just handed us the mappings directly,
> + * after making sure the size is an order of a 4KB page and that the
> + * mapping has natural alignment.
> + *
> + * To retain this behavior, we currently advertise that we support
> + * all page sizes that are an order of 4KB.
> + *
> + * If at some point we'd like to utilize the IOMMU core's new behavior,
> + * we could change this to advertise the real page sizes we support.
> + */
> +static unsigned long intel_iommu_pgsizes = ~0xFFFUL;
Intel IOMMU does not support arbitrary page-sizes, afaik.
> +
> int __init intel_iommu_init(void)
> {
> int ret = 0;
> @@ -3486,7 +3504,7 @@ int __init intel_iommu_init(void)
>
> init_iommu_pm_ops();
>
> - register_iommu(&intel_iommu_ops);
> + register_iommu(&intel_iommu_ops, &intel_iommu_pgsizes, BITS_PER_LONG);
>
> bus_register_notifier(&pci_bus_type, &device_nb);
>
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index c68ff29..e07ea03 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -16,6 +16,8 @@
> * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> */
>
> +#define pr_fmt(fmt)"%s: " fmt, __func__
> +
> #include
> #include
> #include
> @@ -23,15 +25,41 @@
> #include
> #include
> #include
> +#include
>
> static struct iommu_ops *iommu_ops;
>
> -void register_iommu(struct iommu_ops *ops)
> +/* bitmap of supported page sizes */
> +static unsigned long *iommu_pgsize_bitmap;
> +
> +/* number of bits used to represent the supported pages */
> +static unsigned int iommu_nr_page_bits;
> +
> +/* size of the smallest supported page (in bytes) */
> +static unsigned int iommu_min_pagesz;
> +
> +/* bit number of the smallest supported page */
> +static unsigned int iommu_min_page_idx;
> +
> +/**
> + * register_iommu() - register an IOMMU hardware
> + * @ops: iommu handlers
> + * @pgsize_bitmap: bitmap of page sizes supported by the hardware
> + * @nr_page_bits: size of @pgsize_bitmap (in bits)
> + */
> +void register_iommu(struct iommu_ops *ops, unsigned long *pgsize_bitmap,
> + unsigned int nr_page_bits)
> {
> - if (iommu_ops)
> + if (iommu_ops || iommu_pgsize_bitmap || !nr_page_bits)
> BUG();
>
> iommu_ops = ops;
> + iommu_pgsize_bitmap = pgsize_bitmap;
> + iommu_nr_page_bits = nr_page_bits;
> +
> + /* find the minimum
Re: [PATCH 1/3] iommu/core: add fault reporting mechanism
On Mon, Sep 12, 2011 at 12:21:13PM -0400, Ohad Ben-Cohen wrote: > On Mon, Sep 12, 2011 at 7:02 PM, Roedel, Joerg wrote: > > I still don't get the need for this. It would make sense to encode > > different types of faults, like page-faults or interrupt-faults. > > Right. > > > When I read the comment above it sounds more like you want to encode > > different error-levels, like recoverable and unrecoverable error. > > The exact meaning of these values need to be clarified. > > Well, we currently only need to say "something bad has happened". > > We don't need at this point to tell whether it's a hardware bug, > inconsistent data, missing page-table entries or whatnot, because we > don't expect the user (or the iommu core itself) to do anything about > it. Not that it's not possible though: a valid response one day would > be to fix the page-table or add a missing TLB (depending on the mode > the hardware is configured to) but this is not (yet?) implemented. So > a "general unrecoverable error" is enough at this point, but it's > certainly makes sense to allow drivers to provide additional types of > errors/faults - once they are implemented. But besides real faults all this can be handled in the iommu-driver itself, right? So there is no need to communicate other errors than page-faults up to the driver. For now I think it is the best to remove this IOMMU_ERROR thing. It is inherent to the function call already. When a real use-case comes up we can easily add it later. Joerg -- AMD Operating System Research Center Advanced Micro Devices GmbH Einsteinring 24 85609 Dornach General Managers: Alberto Bozzo, Andrew Bowd Registration: Dornach, Landkr. Muenchen; Registerger. Muenchen, HRB Nr. 43632 -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 1/2] omap: hsmmc: Normalize dma cleanup operations
On Tue, Sep 13, 2011 at 1:26 AM, Per Forlin wrote: > On 1 September 2011 21:05, Venkatraman S wrote: >> Reuse omap_hsmmc_dma_cleanup even for normal dma teardown in >> omap_hsmmc_dma_cb. Consolidate multiple points of dma unmap into a >> single location in post_req function, to prevent double unmapping. > It's optional to use pre_req() and post_req(). The SDIO framework > doesn't utilise these hooks. For instance this wont work together with > SDIO-wlan on the pandaboard. > If pre_req() has been issued it's fine to defer dma_unmap() until > post_req(). If pre_req() is not called the driver should call > dma_unmap() directly. > Thanks for the clarification. I'll redo the fix. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] DMAEngine: Define generic transfer request api
2011/9/13 Jassi Brar : > On 13 September 2011 13:16, Barry Song <21cn...@gmail.com> wrote: >>> if test pass, to the patch, and even for the moment, to the API's idea >>> Acked-by: Barry Song >> >> one issue i noticed is with a device_prep_dma_genxfer, i don't need >> device_prep_slave_sg any more, > Yeah, the damengine would need to adapt to the fact that these > interleaved tranfers could be Mem->Mem as well as Mem<->Dev > (even though yours could be only one type, but some dmacs could > do both). > >> How about: >> >> BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) && >> - !device->device_prep_dma_memcpy); >> + !device->device_prep_dma_memcpy && >> + !device->device_prep_dma_genxfer); >> >> BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && >> - !device->device_prep_slave_sg); >> + !device->device_prep_slave_sg && >> + !device->device_prep_dma_genxfer); >> > Seems ok, but please modify in a way you think is best and submit a patch > on top of this new api. Then it'll be easier to evaluate everything. i think it should be handled by this patch but not a new one. > > thanks. > -barry -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] DMAEngine: Define generic transfer request api
On 13 September 2011 13:16, Barry Song <21cn...@gmail.com> wrote: >> if test pass, to the patch, and even for the moment, to the API's idea >> Acked-by: Barry Song > > one issue i noticed is with a device_prep_dma_genxfer, i don't need > device_prep_slave_sg any more, Yeah, the damengine would need to adapt to the fact that these interleaved tranfers could be Mem->Mem as well as Mem<->Dev (even though yours could be only one type, but some dmacs could do both). > How about: > > BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) && > - !device->device_prep_dma_memcpy); > + !device->device_prep_dma_memcpy && > + !device->device_prep_dma_genxfer); > > BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) && > - !device->device_prep_slave_sg); > + !device->device_prep_slave_sg && > + !device->device_prep_dma_genxfer); > Seems ok, but please modify in a way you think is best and submit a patch on top of this new api. Then it'll be easier to evaluate everything. thanks. -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support
On Tuesday 13 September 2011 01:09 PM, Jean Pihet wrote:
Hi Santosh,
On Tue, Sep 13, 2011 at 7:37 AM, Santosh wrote:
On Tuesday 13 September 2011 12:22 AM, Kevin Hilman wrote:
[..]
static inline int omap4_finish_suspend(unsigned long cpu_state)
{}
This one should return 0, as I already pointed out in the comments for [14/25].
Taken care already.
Regards
Santosh
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Re: [PATCH] DMAEngine: Define generic transfer request api
2011/9/13 Barry Song <21cn...@gmail.com>:
> 2011/9/13 Jassi Brar :
>> On 12 September 2011 21:56, Barry Song <21cn...@gmail.com> wrote:
Define a new api that could be used for doing fancy data transfers
like interleaved to contiguous copy and vice-versa.
Traditional SG_list based transfers tend to be very inefficient in
such cases as where the interleave and chunk are only a few bytes,
which call for a very condensed api to convey pattern of the transfer.
This api supports all 4 variants of scatter-gather and contiguous transfer.
Besides, it could also represent common operations like
device_prep_dma_{cyclic, memset, memcpy}
and maybe some more that I am not sure of.
Of course, neither can this api help transfers that don't lend to DMA by
nature, i.e, scattered tiny read/writes with no periodic pattern.
Signed-off-by: Jassi Brar
>>>
>>> anyway, this API needs a real user to prove why it needs to exist.
>>>
>>> prima2 can be the 1st(?, 2nd if TI uses) user of this API. let's try
>>> to see what the driver will be with this api. Then we might figure out
>>> more about what it should be.
>>>
>> Did you discover any issue with the api?
>
> no until now, but i need to test as i said since there is nobody else
> has used it before. so i just hold the formal ACK for a moment.
>
>> Because only three days ago you said
>> {
>> Jassi, you might think my reply as an ACK to "[PATCH] DMAEngine:
>> Define generic transfer request api".
>> }
>
> if test pass, to the patch, and even for the moment, to the API's idea
> Acked-by: Barry Song
one issue i noticed is with a device_prep_dma_genxfer, i don't need
device_prep_slave_sg any more, then the validation check in
dma_async_device_register():
BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
!device->device_prep_slave_sg);
is wrong to me.
How about:
BUG_ON(dma_has_cap(DMA_MEMCPY, device->cap_mask) &&
- !device->device_prep_dma_memcpy);
+ !device->device_prep_dma_memcpy &&
+ !device->device_prep_dma_genxfer);
BUG_ON(dma_has_cap(DMA_SLAVE, device->cap_mask) &&
- !device->device_prep_slave_sg);
+ !device->device_prep_slave_sg &&
+ !device->device_prep_dma_genxfer);
>
>>
>> The api met your requirements easily not because I know them already,
>> but because I designed the api to be as generic as practically possible.
-barry
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Re: [PATCH 21/25] OMAP4: PM: Add MPUSS power domain OSWR support
Hi Santosh,
On Tue, Sep 13, 2011 at 7:37 AM, Santosh wrote:
> On Tuesday 13 September 2011 12:22 AM, Kevin Hilman wrote:
>>
>> Santosh Shilimkar writes:
>>
>>> This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS
>>> OSWR configuration is as below.
>>> - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained
>>>
>>> OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more
>>> anymore just like CORE power domain. The deepest state supported is OSWR.
>>> On OMAP4430 secure devices too, MPUSS off mode can't be used because of
>>> a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an
>>> independent state isn't supported on OMAP44XX devices.
>>>
>>> Ofcourse when MPUSS power domain transitions to OSWR along
>>> with device off mode, it eventually hits off state since memory
>>> contents are lost.
>>>
>>> Hence the MPUSS off mode independent state is not attempted without
>>> device off mode. All the necessary infrastructure code for MPUSS
>>> off mode is in place as part of this series.
>>>
>>> Signed-off-by: Santosh Shilimkar
>>> Cc: Kevin Hilman
>>
>> Compile failure for the !CONFIG_PM case:
>>
>> [...]
>>
>>> @@ -70,11 +71,18 @@ static inline int omap4_mpuss_init(void)
>>> {
>>> return 0;
>>> }
>>> -
>>> +static inline u32 omap4_mpuss_read_prev_context_state(void)
>>> +{
>>> + return 0;
>>> +}
>>
>> added here
>>
>>> static inline int omap4_finish_suspend(unsigned long cpu_state)
>>> {}
This one should return 0, as I already pointed out in the comments for [14/25].
Regards,
Jean
>>> static inline void omap4_cpu_resume(void)
>>> {}
>>> +static inline u32 omap4_mpuss_read_prev_context_state(void)
>>> +{
>>> + return 0;
>>> +}
>>
>> same thing added here
>>
> I noticed this yesterday and was planning to send a note on this
> patch. :(
> Have removed this already in the updated patches.
> Thanks for pointing it out.
>
> Regards
> Santosh
>
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RE: [PATCH 1/8] omap3evm: Enable regulators for camera interface
Hi,
>
> From: Laurent Pinchart [laurent.pinch...@ideasonboard.com]
> Sent: Thursday, September 08, 2011 10:21 PM
> To: Ravi, Deepthy
> Cc: linux-omap@vger.kernel.org; t...@atomide.com; li...@arm.linux.org.uk;
> linux-arm-ker...@lists.infradead.org; linux-ker...@vger.kernel.org;
> mche...@infradead.org; linux-me...@vger.kernel.org; g.liakhovet...@gmx.de;
> Hiremath, Vaibhav
> Subject: Re: [PATCH 1/8] omap3evm: Enable regulators for camera interface
>
> Hi,
>
> On Thursday 08 September 2011 15:33:51 Deepthy Ravi wrote:
>> From: Vaibhav Hiremath
>>
>> Enabled 1v8 and 2v8 regulator output, which is being used by
>> camera module.
>
> Thanks for the patch. Just one minor comment below.
>
>> Signed-off-by: Vaibhav Hiremath
>> Signed-off-by: Deepthy Ravi
>> ---
>> arch/arm/mach-omap2/board-omap3evm.c | 40
>> ++ 1 files changed, 40 insertions(+), 0
>> deletions(-)
>>
>> diff --git a/arch/arm/mach-omap2/board-omap3evm.c
>> b/arch/arm/mach-omap2/board-omap3evm.c index a1184b3..8333ee4 100644
>> --- a/arch/arm/mach-omap2/board-omap3evm.c
>> +++ b/arch/arm/mach-omap2/board-omap3evm.c
>> @@ -273,6 +273,44 @@ static struct omap_dss_board_info omap3_evm_dss_data =
>> { .default_device = &omap3_evm_lcd_device,
>> };
>>
>> +static struct regulator_consumer_supply omap3evm_vaux3_supply = {
>> + .supply = "cam_1v8",
>> +};
>> +
>> +static struct regulator_consumer_supply omap3evm_vaux4_supply = {
>> + .supply = "cam_2v8",
>> +};
>> +
>> +/* VAUX3 for CAM_1V8 */
>> +static struct regulator_init_data omap3evm_vaux3 = {
>> + .constraints = {
>> + .min_uV = 180,
>> + .max_uV = 180,
>> + .apply_uV = true,
>> + .valid_modes_mask = REGULATOR_MODE_NORMAL
>> + | REGULATOR_MODE_STANDBY,
>> + .valid_ops_mask = REGULATOR_CHANGE_MODE
>> + | REGULATOR_CHANGE_STATUS,
>> + },
>> + .num_consumer_supplies = 1,
>> + .consumer_supplies = &omap3evm_vaux3_supply,
>
> I might be wrong, but I think we're standardizing on using REGULATOR_SUPPLY
> arrays as described in commit 786b01a8c1db0c0decca55d660a2a3ebd7cfb26b
> ("cleanup regulator supply definitions in mach-omap2").
>
[Deepthy Ravi] Yes, you are right. I will modify it.
>> +};
>> +
>> +/* VAUX4 for CAM_2V8 */
>> +static struct regulator_init_data omap3evm_vaux4 = {
>> + .constraints = {
>> + .min_uV = 180,
>> + .max_uV = 180,
>> + .apply_uV = true,
>> + .valid_modes_mask = REGULATOR_MODE_NORMAL
>> + | REGULATOR_MODE_STANDBY,
>> + .valid_ops_mask = REGULATOR_CHANGE_MODE
>> + | REGULATOR_CHANGE_STATUS,
>> + },
>> + .num_consumer_supplies = 1,
>> + .consumer_supplies = &omap3evm_vaux4_supply,
>> +};
>> +
>> static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
>> REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
>> };
>> @@ -499,6 +537,8 @@ static struct twl4030_platform_data omap3evm_twldata =
>> { .vio= &omap3evm_vio,
>> .vmmc1 = &omap3evm_vmmc1,
>> .vsim = &omap3evm_vsim,
>> + .vaux3 = &omap3evm_vaux3,
>> + .vaux4 = &omap3evm_vaux4,
>> };
>>
>> static int __init omap3_evm_i2c_init(void)
>
> --
> Regards,
>
> Laurent Pinchart
>
Thanks,
Deepthy Ravi.
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