Re: [PATCH 0/3] ARM: dts: r8a779[014]: Use R-Car Gen 2 fallback binding for vin nodes

[Niklas Söderlund]

Hi Simon,

Thanks for your work.

On 2017-07-11 14:56:46 +0200, Simon Horman wrote:
> Use R-Car Gen 2 fallback binding for vind nodes in DT for r8a779[014] SoCs.
> 
> This has no run-time effect for the current driver as the initialisation
> sequence is the same for the SoC-specific binding for r8a779[014] and the
> fallback binding for R-Car Gen 2
> 
> This is consistent with existing compat string usage in vin nodes for the
> r8a779[23] SoCs.

For whole serries:

Acked-by: Niklas Söderlund 

> 
> Based on renesas-devel-20170711-v4.12
> 
> Simon Horman (3):
>   ARM: dts: r8a7790: Use R-Car Gen 2 fallback binding for vin nodes
>   ARM: dts: r8a7791: Use R-Car Gen 2 fallback binding for vin nodes
>   ARM: dts: r8a7794: Use R-Car Gen 2 fallback binding for vin nodes
> 
>  arch/arm/boot/dts/r8a7790.dtsi | 8 
>  arch/arm/boot/dts/r8a7791.dtsi | 6 +++---
>  arch/arm/boot/dts/r8a7794.dtsi | 4 ++--
>  3 files changed, 9 insertions(+), 9 deletions(-)
> 
> -- 
> 2.1.4
> 

-- 
Regards,
Niklas Söderlund

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

[kbuild test robot]

Hi Chris,

[auto build test ERROR on renesas/next]
[also build test ERROR on next-20170712]
[cannot apply to v4.12]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Chris-Paterson/Add-MMCIF0-support-for-r8a7743-iwg20m/20170713-042814
base:   https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git next
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget 
https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O 
~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/r8a7743-iwg20m.dtsi:40.1-5 Label or path pfc not 
>> found
   FATAL ERROR: Syntax error parsing input tree

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


.config.gz
Description: application/gzip

Re: [PATCH V3 8/8] clk: vc5: Add support for IDT VersaClock 5P49V6901

[Stephen Boyd]

On 07/09, Marek Vasut wrote:
> Update IDT VersaClock 5 driver to support IDT VersaClock 6 5P49V6901.
> This chip has two clock inputs (external XTAL or external CLKIN), four
> fractional dividers (FODs) and five clock outputs (four universal clock
> outputs and one reference clock output at OUT0_SELB_I2C).
> 
> Signed-off-by: Marek Vasut 
> Cc: Alexey Firago 
> Cc: Stephen Boyd 
> Cc: Michael Turquette 
> Cc: Laurent Pinchart 
> Cc: linux-renesas-soc@vger.kernel.org
> Tested-by: Laurent Pinchart 
> on Salvator-XS with the display LVDS output.
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH V3 3/8] clk: vc5: Do not warn about disabled output buffer input muxes

[Stephen Boyd]

On 07/09, Marek Vasut wrote:
> The output buffer input mux can be configured in either of three
> states -- disabled, input from FOD, input from previous output.
> If the output buffer input mux is set to disabled, the code in
> vc5_clk_out_get_parent() would consider this an invalid setting
> and warn about it, which is not necessarily the case.
> 
> In case the output buffer input mux is disabled, default to input
> from FOD to have some parent and don't print the warning.
> 
> Signed-off-by: Marek Vasut 
> Cc: Stephen Boyd 
> Cc: Alexey Firago 
> Cc: Michael Turquette 
> Cc: Laurent Pinchart 
> Cc: linux-renesas-soc@vger.kernel.org
> Tested-by: Laurent Pinchart 
> on Salvator-XS with the display LVDS output.
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH V3 1/8] clk: vc5: Prevent division by zero on unconfigured outputs

[Stephen Boyd]

On 07/09, Marek Vasut wrote:
> In case the initial values of the FOD registers are not configured in
> the OTP or by the bootloader, it is possible that the FOD registers
> will contain zeroes. The code in vc5_fod_recalc_rate() immediately
> feeds the FOD divider value obtained from the FOD registers into the
> div64_u64() and if the FOD divider value is zero, triggers division
> by zero exception.
> 
> Check if the FOD divider value is zero and return the frequency of
> the FOD output as 0 Hz if it is so. This prevents the division by
> zero exception.
> 
> Signed-off-by: Marek Vasut 
> Cc: Stephen Boyd 
> Cc: Alexey Firago 
> Cc: Michael Turquette 
> Cc: Laurent Pinchart 
> Cc: linux-renesas-soc@vger.kernel.org
> Tested-by: Laurent Pinchart 
> on Salvator-XS with the display LVDS output.
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Re: [PATCH V3 2/8] clk: vc5: Fix trivial typo

[Stephen Boyd]

On 07/09, Marek Vasut wrote:
> Fix trivial typo in vc5_clk_out_unprepare() , s/Enable/Disable/ .
> 
> Signed-off-by: Marek Vasut 
> Cc: Stephen Boyd 
> Cc: Alexey Firago 
> Cc: Michael Turquette 
> Cc: Laurent Pinchart 
> Cc: linux-renesas-soc@vger.kernel.org
> Tested-by: Laurent Pinchart 
> on Salvator-XS with the display LVDS output.
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

[PATCH] drm: rcar-du: Fix comments to comply with the kernel coding style

[Laurent Pinchart]

To avoid mixing comment styles when new comments complying with the
kernel coding style are introduced, fix all multiline comments in one
go.

Signed-off-by: Laurent Pinchart 
---
 drivers/gpu/drm/rcar-du/rcar_du_crtc.c| 24 --
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 21 ++--
 drivers/gpu/drm/rcar-du/rcar_du_group.c   | 18 -
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 18 -
 drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c | 12 ++---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c   | 42 ---
 drivers/gpu/drm/rcar-du/rcar_du_plane.h   |  3 ++-
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +++--
 8 files changed, 96 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c 
b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
index f131fc68cc46..a04802f7b2f1 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
@@ -168,7 +168,8 @@ static void rcar_du_crtc_set_display_timing(struct 
rcar_du_crtc *rcrtc)
u32 escr;
u32 div;
 
-   /* Compute the clock divisor and select the internal or external dot
+   /*
+* Compute the clock divisor and select the internal or external dot
 * clock based on the requested frequency.
 */
clk = clk_get_rate(rcrtc->clock);
@@ -261,12 +262,14 @@ void rcar_du_crtc_route_output(struct drm_crtc *crtc,
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
struct rcar_du_device *rcdu = rcrtc->group->dev;
 
-   /* Store the route from the CRTC output to the DU output. The DU will be
+   /*
+* Store the route from the CRTC output to the DU output. The DU will be
 * configured when starting the CRTC.
 */
rcrtc->outputs |= BIT(output);
 
-   /* Store RGB routing to DPAD0, the hardware will be configured when
+   /*
+* Store RGB routing to DPAD0, the hardware will be configured when
 * starting the CRTC.
 */
if (output == RCAR_DU_OUTPUT_DPAD0)
@@ -342,7 +345,8 @@ static void rcar_du_crtc_update_planes(struct rcar_du_crtc 
*rcrtc)
}
}
 
-   /* Update the planes to display timing and dot clock generator
+   /*
+* Update the planes to display timing and dot clock generator
 * associations.
 *
 * Updating the DPTSR register requires restarting the CRTC group,
@@ -450,7 +454,8 @@ static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
/* Start with all planes disabled. */
rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
 
-   /* Select master sync mode. This enables display operation in master
+   /*
+* Select master sync mode. This enables display operation in master
 * sync mode (with the HSYNC and VSYNC signals configured as outputs and
 * actively driven).
 */
@@ -478,7 +483,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
if (!rcrtc->started)
return;
 
-   /* Disable all planes and wait for the change to take effect. This is
+   /*
+* Disable all planes and wait for the change to take effect. This is
 * required as the DSnPR registers are updated on vblank, and no vblank
 * will occur once the CRTC is stopped. Disabling planes when starting
 * the CRTC thus wouldn't be enough as it would start scanning out
@@ -491,7 +497,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
drm_crtc_wait_one_vblank(crtc);
 
-   /* Disable vertical blanking interrupt reporting. We first need to wait
+   /*
+* Disable vertical blanking interrupt reporting. We first need to wait
 * for page flip completion before stopping the CRTC as userspace
 * expects page flips to eventually complete.
 */
@@ -502,7 +509,8 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
rcar_du_vsp_disable(rcrtc);
 
-   /* Select switch sync mode. This stops display operation and configures
+   /*
+* Select switch sync mode. This stops display operation and configures
 * the HSYNC and VSYNC signals as inputs.
 */
rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c 
b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index d6a0255181cc..b95437bccb3d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -39,7 +39,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info 
= {
.features = 0,
.num_crtcs = 2,
.routes = {
-   /* R8A7779 has two RGB outputs and one (currently unsupported)
+  

[PATCH 12/14] pinctrl: sh-pfc: r8a7796: Fix to delete MOD_SEL0 bit2 register definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the macro definitions of MOD_SEL0 bit2 register deleted.

This is a correction because MOD_SEL register specification for R8A7796
SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index e2c6a51..df33b9d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -471,7 +471,6 @@
 #define MOD_SEL0_7_6   FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) 
FM(SEL_DRIF0_2) F_(0, 0)
 #define MOD_SEL0_5 FM(SEL_CANFD0_0)FM(SEL_CANFD0_1)
 #define MOD_SEL0_4_3   FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) 
FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
-#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
 
 /* MOD_SEL1 */ /* 0 */ /* 1 */ 
/* 2 */ /* 3 */ /* 4 */ /* 5 */ 
/* 6 */ /* 7 */
 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) 
FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
@@ -540,7 +539,7 @@
 MOD_SEL0_5 MOD_SEL1_5 \
 MOD_SEL0_4_3   MOD_SEL1_4 \
MOD_SEL1_3 \
-MOD_SEL0_2 MOD_SEL1_2 \
+   MOD_SEL1_2 \
MOD_SEL1_1 \
MOD_SEL1_0  MOD_SEL2_0
 
-- 
1.9.1

[PATCH 13/14] pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment for FSO pins group

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes IPSR{12,17,18} and MOD_SEL0 pin assignment for FSO pins
group.

This is a correction because GPSR and IPSR register specification for
R8A7796 SoC was changed in R-Car Gen3 Hardware User's Manual Rev.0.54E.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 26 +++---
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index df33b9d..bac9b7fe 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -318,14 +318,14 @@
 #define IP11_31_28 FM(RX0) FM(HRX1_B)  F_(0, 0)
F_(0, 0)F_(0, 0)FM(TS_SCK0_C)   
FM(STP_ISCLK_0_C)   FM(RIF0_D0_B)   F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_3_0   FM(TX0) FM(HTX1_B)  F_(0, 0)
F_(0, 0)F_(0, 0)
FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C)  FM(RIF0_D1_B)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP12_7_4   FM(CTS0_N)  FM(HCTS1_N_B)   
FM(MSIOF1_SYNC_B)   F_(0, 0)F_(0, 0)
FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C)  FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C)  
FM(ADICS_SAMP)  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
-#define IP12_11_8  FM(RTS0_N_TANS) FM(HRTS1_N_B)   
FM(MSIOF1_SS1_B)FM(AUDIO_CLKA_B)FM(SCL2_A)  F_(0, 
0)FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A)   
FM(ADICHS1) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
+#define IP12_11_8  FM(RTS0_N_TANS) FM(HRTS1_N_B)   
FM(MSIOF1_SS1_B)FM(AUDIO_CLKA_B)FM(SCL2_A)  F_(0, 
0)FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0)
FM(ADICHS1) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP12_15_12 FM(RX1_A)   FM(HRX1_A)  F_(0, 0)
F_(0, 0)F_(0, 0)FM(TS_SDAT0_C)  
FM(STP_ISD_0_C) FM(RIF1_CLK_C)  F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_19_16 FM(TX1_A)   FM(HTX1_A)  F_(0, 0)
F_(0, 0)F_(0, 0)FM(TS_SDEN0_C)  
FM(STP_ISEN_0_C)FM(RIF1_D0_C)   F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP12_23_20 FM(CTS1_N)  FM(HCTS1_N_A)   
FM(MSIOF1_RXD_B)F_(0, 0)F_(0, 0)
FM(TS_SDEN1_C)  FM(STP_ISEN_1_C)FM(RIF1_D0_B)   F_(0, 0)
FM(ADIDATA) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A)   
FM(MSIOF1_TXD_B)F_(0, 0)F_(0, 0)
FM(TS_SDAT1_C)  FM(STP_ISD_1_C) FM(RIF1_D1_B)   F_(0, 0)
FM(ADICHS0) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP12_31_28 FM(SCK2)FM(SCIF_CLK_B)  
FM(MSIOF1_SCK_B)F_(0, 0)F_(0, 0)
FM(TS_SCK1_C)   FM(STP_ISCLK_1_C)   FM(RIF1_CLK_B)  F_(0, 0)
FM(ADICLK)  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
-#define IP13_3_0   FM(TX2_A)   F_(0, 0)F_(0, 0)
FM(SD2_CD_B)FM(SCL1_A)  F_(0, 0)
FM(FMCLK_A) FM(RIF1_D1_C)   F_(0, 0)FM(FSO_CFE_0_B) 
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP13_7_4   FM(RX2_A)   F_(0, 0)F_(0, 0)
FM(SD2_WP_B)FM(SDA1_A)  F_(0, 0)
FM(FMIN_A)  FM(RIF1_SYNC_C) F_(0, 0)FM(FSO_CFE_1_B) 
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_3_0   FM(TX2_A)   F_(0, 0)F_(0, 0)
FM(SD2_CD_B)FM(SCL1_A)  F_(0, 0)
FM(FMCLK_A) FM(RIF1_D1_C)   F_(0, 0)FM(FSO_CFE_0_N) 
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP13_7_4   FM(RX2_A)   F_(0, 0)F_(0, 0)
FM(SD2_WP_B)FM(SDA1_A)  F_(0, 0)
FM(FMIN_A)  FM(RIF1_SYNC_C) F_(0, 0)FM(FSO_CFE_1_N) 
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 

[PATCH 10/14] pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7 bit[15:12] register definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the macro definitions of FSCLKST pins function and IPSR7
bit[15:12] register deleted.

This is a correction because IPSR register specification for R8A7796 SoC
was changed in R-Car Gen3 Hardware User's Manual Rev.0.53E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 84f8f78..cec3a8a 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -278,7 +278,6 @@
 #define IP7_3_0FM(D13) FM(LCDOUT5) 
FM(MSIOF2_SS2_D)FM(TX4_C)   FM(VI4_DATA5_A) F_(0, 
0)FM(DU_DR5)  F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP7_7_4FM(D14) FM(LCDOUT6) 
FM(MSIOF3_SS1_A)FM(HRX3_C)  FM(VI4_DATA6_A) F_(0, 
0)FM(DU_DR6)  FM(SCL6_C)  F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP7_11_8   FM(D15) FM(LCDOUT7) 
FM(MSIOF3_SS2_A)FM(HTX3_C)  FM(VI4_DATA7_A) F_(0, 
0)FM(DU_DR7)  FM(SDA6_C)  F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP7_15_12  FM(FSCLKST) F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP7_19_16  FM(SD0_CLK) F_(0, 0)
FM(MSIOF1_SCK_E)F_(0, 0)F_(0, 0)F_(0, 
0)FM(STP_OPWM_0_B)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP7_23_20  FM(SD0_CMD) F_(0, 0)
FM(MSIOF1_SYNC_E)   F_(0, 0)F_(0, 0)F_(0, 
0)FM(STP_IVCXO27_0_B) F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP7_27_24  FM(SD0_DAT0)F_(0, 0)
FM(MSIOF1_RXD_E)F_(0, 0)F_(0, 0)
FM(TS_SCK0_B)   FM(STP_ISCLK_0_B)   F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
@@ -419,7 +418,7 @@
 FM(IP4_3_0)IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) 
IP6_3_0 FM(IP7_3_0) IP7_3_0 \
 FM(IP4_7_4)IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) 
IP6_7_4 FM(IP7_7_4) IP7_7_4 \
 FM(IP4_11_8)   IP4_11_8FM(IP5_11_8)IP5_11_8FM(IP6_11_8)
IP6_11_8FM(IP7_11_8)IP7_11_8 \
-FM(IP4_15_12)  IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   
IP6_15_12   FM(IP7_15_12)   IP7_15_12 \
+FM(IP4_15_12)  IP4_15_12   FM(IP5_15_12)   IP5_15_12   FM(IP6_15_12)   
IP6_15_12 \
 FM(IP4_19_16)  IP4_19_16   FM(IP5_19_16)   IP5_19_16   FM(IP6_19_16)   
IP6_19_16   FM(IP7_19_16)   IP7_19_16 \
 FM(IP4_23_20)  IP4_23_20   FM(IP5_23_20)   IP5_23_20   FM(IP6_23_20)   
IP6_23_20   FM(IP7_23_20)   IP7_23_20 \
 FM(IP4_27_24)  IP4_27_24   FM(IP5_27_24)   IP5_27_24   FM(IP6_27_24)   
IP6_27_24   FM(IP7_27_24)   IP7_27_24 \
@@ -990,8 +989,6 @@ enum {
PINMUX_IPSR_GPSR(IP7_11_8,  DU_DR7),
PINMUX_IPSR_MSEL(IP7_11_8,  SDA6_C, SEL_I2C6_2),
 
-   PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
-
PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E,   SEL_MSIOF1_4),
PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B,   SEL_SSP1_0_1),
@@ -4927,7 +4924,7 @@ enum {
IP7_27_24
IP7_23_20
IP7_19_16
-   IP7_15_12
+   /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
IP7_11_8
IP7_7_4
IP7_3_0 }
-- 
1.9.1

[PATCH 01/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using STP_ISEN_1_D

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of MOD_SEL1 bit[25:24]
value when STP_ISEN_1_D pin function is selected for IPSR17 bit[27:24].

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 98bf5d0..b2fb66f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1461,7 +1461,7 @@ enum {
PINMUX_IPSR_GPSR(IP17_27_24,AUDIO_CLKOUT_B),
PINMUX_IPSR_MSEL(IP17_27_24,SSI_SCK2_B, SEL_SSI_1),
PINMUX_IPSR_MSEL(IP17_27_24,TS_SDEN1_D, SEL_TSIF1_3),
-   PINMUX_IPSR_MSEL(IP17_27_24,STP_ISEN_1_D,   SEL_SSP1_1_2),
+   PINMUX_IPSR_MSEL(IP17_27_24,STP_ISEN_1_D,   SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24,STP_OPWM_0_E,   SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24,RIF3_D0_B,  SEL_DRIF3_1),
PINMUX_IPSR_MSEL(IP17_27_24,TCLK2_B,
SEL_TIMER_TMU_1),
-- 
1.9.1

[PATCH 08/14] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of IPSR register value
definitions for MSIOF3_{SS1,SS2}_E pins function.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 80007b9..866cbe4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -221,8 +221,8 @@
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   FM(A25) 
FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)
F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)  
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)FM(A24) 
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-- 
1.9.1

[PATCH 07/14] pinctrl: sh-pfc: r8a7796: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pin function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of IPSR register value
definitions for NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N} pins function.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 36 ++--
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 9a9094f..80007b9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -291,24 +291,24 @@
 #define IP8_23_20  FM(SD1_DAT1)FM(SD2_DAT5)
FM(MSIOF1_TXD_G)FM(NFDATA14_B)  F_(0, 0)
FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B)  F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP8_27_24  FM(SD1_DAT2)FM(SD2_DAT6)
FM(MSIOF1_SS1_G)FM(NFDATA15_B)  F_(0, 0)
FM(TS_SDAT1_B)  FM(STP_ISD_1_B) F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP8_31_28  FM(SD1_DAT3)FM(SD2_DAT7)
FM(MSIOF1_SS2_G)FM(NFRB_N_B)F_(0, 0)
FM(TS_SDEN1_B)  FM(STP_ISEN_1_B)F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
-#define IP9_3_0FM(SD2_CLK) F_(0, 0)F_(0, 
0)FM(NFDATA8) F_(0, 0)F_(0, 0)  
  F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)  
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_7_4FM(SD2_CMD) F_(0, 0)F_(0, 
0)FM(NFDATA9) F_(0, 0)F_(0, 0)  
  F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)  
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_11_8   FM(SD2_DAT0)F_(0, 0)F_(0, 0)
FM(NFDATA10)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_15_12  FM(SD2_DAT1)F_(0, 0)F_(0, 0)
FM(NFDATA11)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_19_16  FM(SD2_DAT2)F_(0, 0)F_(0, 0)
FM(NFDATA12)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_23_20  FM(SD2_DAT3)F_(0, 0)F_(0, 0)
FM(NFDATA13)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24  FM(SD2_DS)  F_(0, 0)F_(0, 0)
FM(NFALE)   F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)FM(SATA_DEVSLP_B)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_31_28  FM(SD3_CLK) F_(0, 0)F_(0, 0)
FM(NFWE_N)  F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_3_0   FM(SD3_CMD) F_(0, 0)F_(0, 0)
FM(NFRE_N)  F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_7_4   FM(SD3_DAT0)F_(0, 0)F_(0, 0)
FM(NFDATA0) F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP10_11_8  FM(SD3_DAT1)F_(0, 0)F_(0, 0)
FM(NFDATA1) 

[PATCH 06/14] pinctrl: sh-pfc: r8a7796: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of IPSR register value
definitions for FMCLK{_C,_D} and FMIN{_C,_D} pins function.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 467f32e..9a9094f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -367,8 +367,8 @@
 #define IP17_23_20 FM(USB1_OVC)F_(0, 0)
FM(MSIOF1_SS2_C)F_(0, 0)FM(SSI_WS1_A)   
FM(TS_SDAT0_E)  FM(STP_ISD_0_E) FM(FMIN_B)  FM(RIF2_SYNC_B) 
F_(0, 0)FM(REMOCON_B)   F_(0, 0)F_(0, 0) FM(HCTS2_N_C) F_(0, 0) 
F_(0, 0)
 #define IP17_27_24 FM(USB30_PWEN)  F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT_B)  FM(SSI_SCK2_B)  FM(TS_SDEN1_D)  
FM(STP_ISEN_1_D)FM(STP_OPWM_0_E)FM(RIF3_D0_B)   F_(0, 0)
FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
 #define IP17_31_28 FM(USB30_OVC)   F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B)   
FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D)  FM(STP_IVCXO27_0_E)FM(RIF3_D1_B)
F_(0, 0)FM(FSO_TOE_B)   FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
-#define IP18_3_0   FM(GP6_30)  F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  
FM(STP_ISEN_0_E)F_(0, 0)FM(RIF2_D0_B)   F_(0, 0)
FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
-#define IP18_7_4   FM(GP6_31)  F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B)   
FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)  F_(0, 0)FM(RIF2_D1_B)   
F_(0, 0)FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) 
F_(0, 0)
+#define IP18_3_0   FM(GP6_30)  F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B)  FM(TS_SDEN0_E)  
FM(STP_ISEN_0_E)F_(0, 0)FM(RIF2_D0_B)   F_(0, 0)
FM(FSO_CFE_0_A) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
+#define IP18_7_4   FM(GP6_31)  F_(0, 0)F_(0, 0)
FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B)   
FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E)  F_(0, 0)FM(RIF2_D1_B)   
F_(0, 0)FM(FSO_CFE_1_A) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) 
F_(0, 0)
 
 #define PINMUX_GPSR\
 \
-- 
1.9.1

[PATCH 09/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for TCLK{1,2}_{A,B} pins group

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes to set MOD_SEL2 bit19 when using TCLK2_A pin function is
selected for IPSR16 bit[23:20] or using TCLK2_B pin function is selected
for IPSR17 bit[27:24].

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 866cbe4..84f8f78 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1393,7 +1393,7 @@ enum {
PINMUX_IPSR_MSEL(IP16_23_20,STP_ISEN_1_A,   SEL_SSP1_1_0),
PINMUX_IPSR_MSEL(IP16_23_20,RIF1_D0_A,  SEL_DRIF1_0),
PINMUX_IPSR_MSEL(IP16_23_20,RIF3_D0_A,  SEL_DRIF3_0),
-   PINMUX_IPSR_MSEL(IP16_23_20,TCLK2_A,
SEL_TIMER_TMU_0),
+   PINMUX_IPSR_MSEL(IP16_23_20,TCLK2_A,
SEL_TIMER_TMU2_0),
 
PINMUX_IPSR_GPSR(IP16_27_24,SSI_SDATA8),
PINMUX_IPSR_MSEL(IP16_27_24,HRTS2_N_B,  SEL_HSCIF2_1),
@@ -1464,7 +1464,7 @@ enum {
PINMUX_IPSR_MSEL(IP17_27_24,STP_ISEN_1_D,   SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_27_24,STP_OPWM_0_E,   SEL_SSP1_0_4),
PINMUX_IPSR_MSEL(IP17_27_24,RIF3_D0_B,  SEL_DRIF3_1),
-   PINMUX_IPSR_MSEL(IP17_27_24,TCLK2_B,
SEL_TIMER_TMU_1),
+   PINMUX_IPSR_MSEL(IP17_27_24,TCLK2_B,
SEL_TIMER_TMU2_1),
PINMUX_IPSR_GPSR(IP17_27_24,TPU0TO0),
PINMUX_IPSR_MSEL(IP17_27_24,BPFCLK_C,   SEL_FM_2),
PINMUX_IPSR_MSEL(IP17_27_24,HRTS2_N_C,  SEL_HSCIF2_2),
-- 
1.9.1

[PATCH 11/14] pinctrl: sh-pfc: r8a7796: Fix to delete SATA_DEVSLP_B pins function definitions

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the macro definitions of SATA_DEVSLP_B pins function
deleted.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index cec3a8a..e2c6a51 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -296,7 +296,7 @@
 #define IP9_15_12  FM(SD2_DAT1)F_(0, 0)FM(NFDATA11)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_19_16  FM(SD2_DAT2)F_(0, 0)FM(NFDATA12)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_23_20  FM(SD2_DAT3)F_(0, 0)FM(NFDATA13)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP9_27_24  FM(SD2_DS)  F_(0, 0)FM(NFALE)   
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)FM(SATA_DEVSLP_B)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP9_27_24  FM(SD2_DS)  F_(0, 0)FM(NFALE)   
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)  
  F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP9_31_28  FM(SD3_CLK) F_(0, 0)FM(NFWE_N)  
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_3_0   FM(SD3_CMD) F_(0, 0)FM(NFRE_N)  
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP10_7_4   FM(SD3_DAT0)F_(0, 0)FM(NFDATA0) 
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-- 
1.9.1

[PATCH 02/14] pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E pin was selected

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes to set IPSR register when using MSIOF3_SS1_E pin function
is selected.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index b2fb66f..87f21d7b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -645,7 +645,7 @@ enum {
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B,  SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B,SEL_CANFD0_1),
-   PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E,   SEL_MSIOF3_4),
+   PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E,   SEL_MSIOF3_4),
 
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0,   IRQ2),
-- 
1.9.1

[PATCH 04/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI pins group

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes MOD_SEL1 bit20 and MOD_SEL2 bit20, bit21 pin assignment
for SSI pins group.

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 38 ++--
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 4d070c2..18c9c61 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -480,7 +480,7 @@
 #define MOD_SEL1_26FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0)FM(SEL_SSP1_1_1)
FM(SEL_SSP1_1_2)FM(SEL_SSP1_1_3)
 #define MOD_SEL1_23_22_21  FM(SEL_SSP1_0_0)FM(SEL_SSP1_0_1)
FM(SEL_SSP1_0_2)FM(SEL_SSP1_0_3)FM(SEL_SSP1_0_4)F_(0, 
0)F_(0, 0)F_(0, 0)
-#define MOD_SEL1_20FM(SEL_SSI_0)   FM(SEL_SSI_1)
+#define MOD_SEL1_20FM(SEL_SSI1_0)  FM(SEL_SSI1_1)
 #define MOD_SEL1_19FM(SEL_SPEED_PULSE_0)   FM(SEL_SPEED_PULSE_1)
 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0)   FM(SEL_SIMCARD_1)   
FM(SEL_SIMCARD_2)   FM(SEL_SIMCARD_3)
 #define MOD_SEL1_16FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
@@ -1230,7 +1230,7 @@ enum {
PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D,   SEL_MSIOF1_3),
PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A,   SEL_ADG_B_0),
-   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B,   SEL_SSI1_1),
PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D,  SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D,  SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
@@ -1238,14 +1238,14 @@ enum {
 
PINMUX_IPSR_GPSR(IP13_15_12,HRX0),
PINMUX_IPSR_MSEL(IP13_15_12,MSIOF1_RXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_15_12,SSI_SDATA2_B,   SEL_SSI2_1),
PINMUX_IPSR_MSEL(IP13_15_12,TS_SDEN0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_15_12,STP_ISEN_0_D,   SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_15_12,RIF0_D0_C,  SEL_DRIF0_2),
 
PINMUX_IPSR_GPSR(IP13_19_16,HTX0),
PINMUX_IPSR_MSEL(IP13_19_16,MSIOF1_TXD_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI_1),
+   PINMUX_IPSR_MSEL(IP13_19_16,SSI_SDATA9_B,   SEL_SSI9_1),
PINMUX_IPSR_MSEL(IP13_19_16,TS_SDAT0_D, SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_19_16,STP_ISD_0_D,SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_19_16,RIF0_D1_C,  SEL_DRIF0_2),
@@ -1253,7 +1253,7 @@ enum {
PINMUX_IPSR_GPSR(IP13_23_20,HCTS0_N),
PINMUX_IPSR_MSEL(IP13_23_20,RX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_23_20,MSIOF1_SYNC_D,  SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_23_20,SSI_SCK9_A, SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_23_20,TS_SPSYNC0_D,   SEL_TSIF0_3),
PINMUX_IPSR_MSEL(IP13_23_20,STP_ISSYNC_0_D, SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_23_20,RIF0_SYNC_C,SEL_DRIF0_2),
@@ -1262,7 +1262,7 @@ enum {
PINMUX_IPSR_GPSR(IP13_27_24,HRTS0_N),
PINMUX_IPSR_MSEL(IP13_27_24,TX2_B,  SEL_SCIF2_1),
PINMUX_IPSR_MSEL(IP13_27_24,MSIOF1_SS1_D,   SEL_MSIOF1_3),
-   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP13_27_24,SSI_WS9_A,  SEL_SSI9_0),
PINMUX_IPSR_MSEL(IP13_27_24,STP_IVCXO27_0_D,SEL_SSP1_0_3),
PINMUX_IPSR_MSEL(IP13_27_24,BPFCLK_A,   SEL_FM_0),
PINMUX_IPSR_GPSR(IP13_27_24,AUDIO_CLKOUT2_A),
@@ -1277,7 +1277,7 @@ enum {
PINMUX_IPSR_MSEL(IP14_3_0,  RX5_A,  SEL_SCIF5_0),
PINMUX_IPSR_MSEL(IP14_3_0,  NFWP_N_A,   SEL_NDF_0),
PINMUX_IPSR_MSEL(IP14_3_0,  AUDIO_CLKA_C,   SEL_ADG_A_2),
-   PINMUX_IPSR_MSEL(IP14_3_0,  SSI_SCK2_A, SEL_SSI_0),
+   PINMUX_IPSR_MSEL(IP14_3_0,  SSI_SCK2_A, 

[PATCH 05/14] pinctrl: sh-pfc: r8a7796: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment to MOD_SEL1 bit10

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes SCIF_CLK_{A,B} pin's MOD_SEL assignment from MOD_SEL1
bit11 to MOD_SEL1 bit10.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 18c9c61..467f32e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -488,7 +488,7 @@
 #define MOD_SEL1_13FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
 #define MOD_SEL1_12FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
 #define MOD_SEL1_11FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
-#define MOD_SEL1_10FM(SEL_SATA_0)  FM(SEL_SATA_1)
+#define MOD_SEL1_10FM(SEL_SCIF_0)  FM(SEL_SCIF_1)
 #define MOD_SEL1_9 FM(SEL_REMOCON_0)   FM(SEL_REMOCON_1)
 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
 #define MOD_SEL1_5 FM(SEL_PWM6_0)  FM(SEL_PWM6_1)
@@ -1205,7 +1205,7 @@ enum {
PINMUX_IPSR_GPSR(IP12_27_24,ADICHS0),
 
PINMUX_IPSR_GPSR(IP12_31_28,SCK2),
-   PINMUX_IPSR_MSEL(IP12_31_28,SCIF_CLK_B, SEL_SCIF1_1),
+   PINMUX_IPSR_MSEL(IP12_31_28,SCIF_CLK_B, SEL_SCIF_1),
PINMUX_IPSR_MSEL(IP12_31_28,MSIOF1_SCK_B,   SEL_MSIOF1_1),
PINMUX_IPSR_MSEL(IP12_31_28,TS_SCK1_C,  SEL_TSIF1_2),
PINMUX_IPSR_MSEL(IP12_31_28,STP_ISCLK_1_C,  SEL_SSP1_1_2),
@@ -1417,7 +1417,7 @@ enum {
PINMUX_IPSR_GPSR(IP17_3_0,  CC5_OSCOUT),
 
PINMUX_IPSR_MSEL(IP17_7_4,  AUDIO_CLKB_B,   SEL_ADG_B_1),
-   PINMUX_IPSR_MSEL(IP17_7_4,  SCIF_CLK_A, SEL_SCIF1_0),
+   PINMUX_IPSR_MSEL(IP17_7_4,  SCIF_CLK_A, SEL_SCIF_0),
PINMUX_IPSR_MSEL(IP17_7_4,  STP_IVCXO27_1_D,SEL_SSP1_1_3),
PINMUX_IPSR_MSEL(IP17_7_4,  REMOCON_A,  SEL_REMOCON_0),
PINMUX_IPSR_MSEL(IP17_7_4,  TCLK1_A,
SEL_TIMER_TMU_0),
-- 
1.9.1

[PATCH 03/14] pinctrl: sh-pfc: r8a7796: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A

[Yoshihiro Kaneko]

From: Takeshi Kihara 

This patch fixes the implementation incorrect of MOD_SEL2 bit26 value
when SCK5_A pin function is selected for IPSR16 bit[31:28].

This is a correction to the incorrect implementation of MOD_SEL register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
Signed-off-by: Yoshihiro Kaneko 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 87f21d7b..4d070c2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -1410,7 +1410,7 @@ enum {
PINMUX_IPSR_MSEL(IP16_31_28,SSI_WS1_B,  SEL_SSI_1),
PINMUX_IPSR_GPSR(IP16_31_28,SCK1),
PINMUX_IPSR_MSEL(IP16_31_28,STP_IVCXO27_1_A,SEL_SSP1_1_0),
-   PINMUX_IPSR_GPSR(IP16_31_28,SCK5_A),
+   PINMUX_IPSR_MSEL(IP16_31_28,SCK5_A, SEL_SCIF5_0),
 
/* IPSR17 */
PINMUX_IPSR_MSEL(IP17_3_0,  AUDIO_CLKA_A,   SEL_ADG_A_0),
-- 
1.9.1

[PATCH 00/14] pinctrl: sh-pfc: r8a7796: Fix pin assignment definitions

[Yoshihiro Kaneko]

This series fixes pin assignment definitions for R8A7796 SoC.
This series is based on the for-next branch of linux-pinctrl tree.

Takeshi Kihara (14):
  pinctrl: sh-pfc: r8a7796: Fix MOD_SEL1 bit[25:24] to 0x3 when using
STP_ISEN_1_D
  pinctrl: sh-pfc: r8a7796: Fix IPSR register setting when MSIOF3_SS1_E
pin was selected
  pinctrl: sh-pfc: r8a7796: Fix MOD_SEL2 bit26 to 0x0 when using SCK5_A
  pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for SSI
pins group
  pinctrl: sh-pfc: r8a7796: Fix SCIF_CLK_{A,B} pin's MOD_SEL assignment
to MOD_SEL1 bit10
  pinctrl: sh-pfc: r8a7796: Fix FMCLK{_C,_D} and FMIN{_C,_D} pin
function definitions
  pinctrl: sh-pfc: r8a7796: Fix NFDATA{0..13} and NF{ALE,CLE,WE_N,RE_N}
pin function definitions
  pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pins function
definitions
  pinctrl: sh-pfc: r8a7796: Fix MOD_SEL register pin assignment for
TCLK{1,2}_{A,B} pins group
  pinctrl: sh-pfc: r8a7796: Fix to delete FSCLKST pin and IPSR7
bit[15:12] register definitions
  pinctrl: sh-pfc: r8a7796: Fix to delete SATA_DEVSLP_B pins function
definitions
  pinctrl: sh-pfc: r8a7796: Fix to delete MOD_SEL0 bit2 register
definitions
  pinctrl: sh-pfc: r8a7796: Fix IPSR and MOD_SEL register pin assignment
for FSO pins group
  pinctrl: sh-pfc: r8a7796: Rename CS1# pin function definitions

 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 138 +--
 1 file changed, 65 insertions(+), 73 deletions(-)

-- 
1.9.1

Re: [PATCH] drm: rcar-du: Setup planes before enabling CRTC to avoid flicker

[Kieran Bingham]

Hi Laurent,

On 28/06/17 19:50, Laurent Pinchart wrote:
> Commit 52055bafa1ff ("drm: rcar-du: Move plane commit code from CRTC
> start to CRTC resume") changed the order of the plane commit and CRTC
> enable operations to accommodate the runtime PM requirements. However,
> this introduced corruption in the first displayed frame, as the CRTC is
> now enabled without any plane configured. On Gen2 hardware the first
> frame will be black and likely unnoticed, but on Gen3 hardware we end up
> starting the display before the VSP compositor, which is more
> noticeable.
> 
> To fix this, revert the order of the commit operations back, and handle
> runtime PM requirements in the CRTC .atomic_begin() and .atomic_enable()
> helper operation handlers.
> 
> Signed-off-by: Laurent Pinchart 

I only have code reduction or comment suggestions below - so either with or
without those changes, feel free to add my:

Reviewed-by: Kieran Bingham 

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 66 
> --
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.h |  4 +--
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c  |  2 +-
>  3 files changed, 43 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 6b5219ef0ad2..76cdb88b2b8e 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -448,14 +448,8 @@ static void rcar_du_crtc_wait_page_flip(struct 
> rcar_du_crtc *rcrtc)
>   * Start/Stop and Suspend/Resume
>   */
>  
> -static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
> +static void rcar_du_crtc_setup(struct rcar_du_crtc *rcrtc)
>  {
> - struct drm_crtc *crtc = >crtc;
> - bool interlaced;
> -
> - if (rcrtc->started)
> - return;
> -
>   /* Set display off and background to black */
>   rcar_du_crtc_write(rcrtc, DOOR, DOOR_RGB(0, 0, 0));
>   rcar_du_crtc_write(rcrtc, BPOR, BPOR_RGB(0, 0, 0));
> @@ -467,6 +461,18 @@ static void rcar_du_crtc_start(struct rcar_du_crtc 
> *rcrtc)
>   /* Start with all planes disabled. */
>   rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
>  
> + /* Enable the VSP compositor. */
> + if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
> + rcar_du_vsp_enable(rcrtc);
> +
> + /* Turn vertical blanking interrupt reporting on. */
> + drm_crtc_vblank_on(>crtc);
> +}
> +
> +static void rcar_du_crtc_start(struct rcar_du_crtc *rcrtc)
> +{
> + bool interlaced;
> +
>   /* Select master sync mode. This enables display operation in master

Are we close enough here to fix this multiline comment style ?
(Not worth doing unless the patch is respun for other reasons ...)

Actually - there are a lot in this file, so it would be better to do them all in
one hit/patch at a point of least conflicts ...


>* sync mode (with the HSYNC and VSYNC signals configured as outputs and
>* actively driven).
> @@ -477,24 +483,12 @@ static void rcar_du_crtc_start(struct rcar_du_crtc 
> *rcrtc)
>DSYSR_TVM_MASTER);
>  
>   rcar_du_group_start_stop(rcrtc->group, true);
> -
> - /* Enable the VSP compositor. */
> - if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
> - rcar_du_vsp_enable(rcrtc);
> -
> - /* Turn vertical blanking interrupt reporting back on. */
> - drm_crtc_vblank_on(crtc);
> -
> - rcrtc->started = true;
>  }
>  
>  static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>  {
>   struct drm_crtc *crtc = >crtc;
>  
> - if (!rcrtc->started)
> - return;
> -
>   /* Disable all planes and wait for the change to take effect. This is
>* required as the DSnPR registers are updated on vblank, and no vblank
>* will occur once the CRTC is stopped. Disabling planes when starting
> @@ -525,8 +519,6 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>   rcar_du_crtc_clr_set(rcrtc, DSYSR, DSYSR_TVM_MASK, DSYSR_TVM_SWITCH);
>  
>   rcar_du_group_start_stop(rcrtc->group, false);
> -
> - rcrtc->started = false;
>  }
>  
>  void rcar_du_crtc_suspend(struct rcar_du_crtc *rcrtc)
> @@ -546,12 +538,10 @@ void rcar_du_crtc_resume(struct rcar_du_crtc *rcrtc)
>   return;
>  
>   rcar_du_crtc_get(rcrtc);
> - rcar_du_crtc_start(rcrtc);
> + rcar_du_crtc_setup(rcrtc);

Every call to _setup is immediately prefixed by a call to _get()

Could the _get() be done in the _setup() for code reduction?

I'm entirely open to that not happening here as it might be preferred to keep
the _get() and _start() separate for style purposes.

>  
>   /* Commit the planes state. */
> - if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> - rcar_du_vsp_enable(rcrtc);
> - } else {
> + if 

Re: [PATCH v3] mmc: tmio-mmc: fix bad pointer math

[Wolfram Sang]

On Wed, Jul 12, 2017 at 08:40:01AM -0700, Chris Brandt wrote:
> The existing code gives an incorrect pointer value.
> The buffer pointer 'buf' was of type unsigned short *, and 'count' was a
> number in bytes. A cast of buf should have been used.
> 
> However, instead of casting, just change the code to use u32 pointers.
> 
> Reported-by: Dan Carpenter 
> Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port")
> Signed-off-by: Chris Brandt 
> Reviewed-by: Geert Uytterhoeven 

Acked-by: Wolfram Sang 



signature.asc
Description: PGP signature

[PATCH v3] mmc: tmio-mmc: fix bad pointer math

[Chris Brandt]

The existing code gives an incorrect pointer value.
The buffer pointer 'buf' was of type unsigned short *, and 'count' was a
number in bytes. A cast of buf should have been used.

However, instead of casting, just change the code to use u32 pointers.

Reported-by: Dan Carpenter 
Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port")
Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
---
v3:
 * Merged lines
 * Added Reviewed-by
v2:
 * Use u32 pointers instead of casting
---
 drivers/mmc/host/tmio_mmc_core.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 77e7b56a9099..db779732fd2e 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -415,30 +415,29 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host 
*host,
 * Transfer the data
 */
if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
-   u8 data[4] = { };
+   u32 data = 0;
+   u32 *buf32 = (u32 *)buf;
 
if (is_read)
-   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
+   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, buf32,
   count >> 2);
else
-   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
+   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, buf32,
count >> 2);
 
/* if count was multiple of 4 */
if (!(count & 0x3))
return;
 
-   buf8 = (u8 *)(buf + (count >> 2));
+   buf32 += count >> 2;
count %= 4;
 
if (is_read) {
-   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
-  (u32 *)data, 1);
-   memcpy(buf8, data, count);
+   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, , 1);
+   memcpy(buf32, , count);
} else {
-   memcpy(data, buf8, count);
-   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
-   (u32 *)data, 1);
+   memcpy(, buf32, count);
+   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, , 1);
}
 
return;
-- 
2.13.0

RE: [PATCH v2] mmc: tmio-mmc: fix bad pointer math

[Chris Brandt]

Hi Geert,

On Wednesday, July 12, 2017 1, Geert Uytterhoeven wrote:
> > Reported-by: Dan Carpenter 
> > Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port")
> > Signed-off-by: Chris Brandt 
> 
> Reviewed-by: Geert Uytterhoeven 


As always, thank you for your review.


> > if (is_read) {
> > sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
> > -  (u32 *)data, 1);
> > +  , 1);
> 
> I would use the opportunity to merge the two above lines, now they fit
> on a single line.
> 
> > +   memcpy(buf32, , count);
> > } else {
> > -   memcpy(data, buf8, count);
> > +   memcpy(, buf32, count);
> > sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
> > -   (u32 *)data, 1);
> > +   , 1);
> 
> Likewise.

Easy enough.

Done!


Thanks,
Chris

Re: Rebasing mmc/next

[Ulf Hansson]

On 20 June 2017 at 11:06, Geert Uytterhoeven  wrote:
> Hi Ulf,
>
> On Tue, Jun 20, 2017 at 10:07 AM, Ulf Hansson  wrote:
>> On 20 June 2017 at 09:17, Geert Uytterhoeven  wrote:
>>> It looks like you rebase mmc/next almost daily. Is there any specific reason
>>> for that?
>>
>> I don't do it daily, but often, yes. :-)
>
> A few years ago, I got bashed by Linus for rebasing the m68k "for-linus"
> branch on every -rc.

Perhaps something to be discussed a kernel/mainainer-summit, cause at
the moment I don't think there is given policy.

>
>>> I'm asking because I create a "renesas-drivers" tree on a regular basis
>>> (cfr. e.g. https://www.spinics.net/lists/linux-renesas-soc/msg15111.html).
>>> This tree is meant to ease development of platform support and drivers
>>> for Renesas ARM SoCs. It is created by merging (a) the for-next branches
>>> of various subsystem trees and (b) branches with driver code submitted
>>> or planned for submission to maintainers into the development branch of
>>> Simon Horman's renesas.git tree.
>>
>> If you are asking me to keep my next branch immutable, then please no,
>> I don't like to do that. Reason explained below.
>
> 100% immutable is not needed.
>
>> I don't have a problem to share specific renesas mmc branches with
>> you, if that helps?
>
> Hmm, that would be more work on your side. Plus communication overhead.

OK.

[...]

>
>> I am trying to understand the purpose of your renesas integration
>> tree, and why it's a problem for you to pick up my re-based branch?
>> Could you perhaps elaborate on this?
>
> The purpose is to make it easier for the upstream Renesas kernel team and
> associated testers to consume our work-in-progress.
>
> Hence I merge the for-next branches of selected subsystems, followed by
> topic branches with work-in-progress driver code.
>
> E.g. Simon had asked me to include
> git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git
> topic/sdhi-gen3-dma-2017
> That branch was based on your mmc/next.

I guess there are two other options to deal with this.

1) Don't merge my next branch, in case there is another branch based
on it. Instead, in this case, it will be Simon's responsibility of
re-basing his branch on top of mmc next, as to get the latest changes.
2) Base your WIP branches on top of some commit from Linus tree. Then
you can keep merging my next branch and any other "for-next" branch
that is often being re-based.

>
> But by the time I created the renesas-drivers release, mmc/next had been
> rebased.  Hence after merging the new mmc/next, I had to rebase his work:
> https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/sdhi-gen3-dma-2017-rebased1
>
> I hope this explains our problem.

Yeah, thanks for the explanation - and apologize for the delay.

Kind regards
Uffe

Re: [PATCH v2] mmc: tmio-mmc: fix bad pointer math

[Geert Uytterhoeven]

On Wed, Jul 12, 2017 at 3:27 PM, Chris Brandt  wrote:
> The existing code gives an incorrect pointer value.
> The buffer pointer 'buf' was of type unsigned short *, and 'count' was a
> number in bytes. A cast of buf should have been used.
>
> However,instead of casting, just change the code to use u32 pointers.
>
> Reported-by: Dan Carpenter 
> Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port")
> Signed-off-by: Chris Brandt 

Reviewed-by: Geert Uytterhoeven 

> --- a/drivers/mmc/host/tmio_mmc_core.c
> +++ b/drivers/mmc/host/tmio_mmc_core.c

> if (is_read) {
> sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
> -  (u32 *)data, 1);
> +  , 1);

I would use the opportunity to merge the two above lines, now they fit
on a single line.

> +   memcpy(buf32, , count);
> } else {
> -   memcpy(data, buf8, count);
> +   memcpy(, buf32, count);
> sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
> -   (u32 *)data, 1);
> +   , 1);

Likewise.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH] ARM: shmobile: rcar-gen2: Fix deadlock in regulator quirk

[Geert Uytterhoeven]

Simon Horman reported that Koelsch and Lager hang during boot, and
bisected this to commit 1c3c5eab171590f8 ("sched/core: Enable
might_sleep() and smp_processor_id() checks early").

The da9063/da9210 regulator quirk for R-Car Gen2 boards uses a bus
notifier, and unregisters the notifier when it is no longer needed.
However, a notifier must not be unregistered from within the call chain.

This bug went unnoticed, as blocking_notifier_chain_unregister() didn't
take the semaphore during early boot.  The aforementioned commit changed
that behavior, leading to a deadlock.

Fix this by removing the call to bus_unregister_notifier(), and keeping
local completion state instead.

Reported-by: Simon Horman 
Fixes: 663fbb52159cca6f ("ARM: shmobile: R-Car Gen2: Add da9063/da9210 
regulator quirk")
Signed-off-by: Geert Uytterhoeven 
---
 arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c 
b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
index 73e3adbc133096ec..44438f344dc80f9c 100644
--- a/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/regulator-quirk-rcar-gen2.c
@@ -67,8 +67,12 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 {
struct device *dev = data;
struct i2c_client *client;
+   static bool done;
u32 mon;
 
+   if (done)
+   return 0;
+
mon = ioread32(irqc + IRQC_MONITOR);
dev_dbg(dev, "%s: %ld, IRQC_MONITOR = 0x%x\n", __func__, action, mon);
if (mon & REGULATOR_IRQ_MASK)
@@ -99,7 +103,7 @@ static int regulator_quirk_notify(struct notifier_block *nb,
 remove:
dev_info(dev, "IRQ2 is not asserted, removing quirk\n");
 
-   bus_unregister_notifier(_bus_type, nb);
+   done = true;
iounmap(irqc);
return 0;
 }
-- 
2.7.4

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

[Kieran Bingham]

Hi Geert,

> Indeed.
> 
> BTW, the M3-W version also has unconnected USB3 and SATA connectors.

Thanks for the heads up :) - I've just put a post it note over those, +HDMI1-OUT
(or rather the text on the top lid) to prevent any confusion for me down the 
line.

--
Kieran

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

[Geert Uytterhoeven]

Hi Kieran,

On Wed, Jul 12, 2017 at 3:51 PM, Kieran Bingham
 wrote:
> Table 35.1 (in the DU datasheet) certainly shows that there is only an 
> HDMI-IF0
> on the M3, but it's amusing that (and I was confused by the fact that) my
> r8a7796 board (Salvator-X) still has the HDMI1 populated. Of course I presume
> this is populated to keep the boards the same but is not connected in the 
> chip.

Indeed.

BTW, the M3-W version also has unconnected USB3 and SATA connectors.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 2/2] drm: rcar-du: Add HDMI outputs to R8A7796 device description

[Kieran Bingham]

Hi Laurent,

This looks good to me.

Table 35.1 (in the DU datasheet) certainly shows that there is only an HDMI-IF0
on the M3, but it's amusing that (and I was confused by the fact that) my
r8a7796 board (Salvator-X) still has the HDMI1 populated. Of course I presume
this is populated to keep the boards the same but is not connected in the chip.

Anyway, that's irrelevant to this patch so ...

On 21/06/17 10:04, Laurent Pinchart wrote:
> Update the device description with the HDMI output.
> 
> Signed-off-by: Laurent Pinchart 

Reviewed-by: Kieran Bingham 

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 10 --
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index d6a0255181cc..fc0ae0947b8f 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -180,19 +180,25 @@ static const struct rcar_du_device_info 
> rcar_du_r8a7796_info = {
> | RCAR_DU_FEATURE_VSP1_SOURCE,
>   .num_crtcs = 3,
>   .routes = {
> - /* R8A7796 has one RGB output, one LVDS output and one
> -  * (currently unsupported) HDMI output.
> + /*
> +  * R8A7796 has one RGB output, one LVDS output and one HDMI
> +  * output.
>*/
>   [RCAR_DU_OUTPUT_DPAD0] = {
>   .possible_crtcs = BIT(2),
>   .port = 0,
>   },
> + [RCAR_DU_OUTPUT_HDMI0] = {
> + .possible_crtcs = BIT(1),
> + .port = 1,
> + },
>   [RCAR_DU_OUTPUT_LVDS0] = {
>   .possible_crtcs = BIT(0),
>   .port = 2,
>   },
>   },
>   .num_lvds = 1,
> + .dpll_ch =  BIT(1),
>  };
>  
>  static const struct of_device_id rcar_du_of_table[] = {
> 

[PATCH v2] mmc: tmio-mmc: fix bad pointer math

[Chris Brandt]

The existing code gives an incorrect pointer value.
The buffer pointer 'buf' was of type unsigned short *, and 'count' was a
number in bytes. A cast of buf should have been used.

However,instead of casting, just change the code to use u32 pointers.

Reported-by: Dan Carpenter 
Fixes: 8185e51f358a: ("mmc: tmio-mmc: add support for 32bit data port")
Signed-off-by: Chris Brandt 
---
v2:
 * Use u32 pointers instead of casting
---
 drivers/mmc/host/tmio_mmc_core.c | 17 +
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 77e7b56a9099..e4e35b6e2db5 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -415,30 +415,31 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host 
*host,
 * Transfer the data
 */
if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
-   u8 data[4] = { };
+   u32 data = 0;
+   u32 *buf32 = (u32 *)buf;
 
if (is_read)
-   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
+   sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, buf32,
   count >> 2);
else
-   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, (u32 *)buf,
+   sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, buf32,
count >> 2);
 
/* if count was multiple of 4 */
if (!(count & 0x3))
return;
 
-   buf8 = (u8 *)(buf + (count >> 2));
+   buf32 += count >> 2;
count %= 4;
 
if (is_read) {
sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT,
-  (u32 *)data, 1);
-   memcpy(buf8, data, count);
+  , 1);
+   memcpy(buf32, , count);
} else {
-   memcpy(data, buf8, count);
+   memcpy(, buf32, count);
sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT,
-   (u32 *)data, 1);
+   , 1);
}
 
return;
-- 
2.13.0

Re: [PATCH v2 2/3] drm: rcar-du: Fix planes to CRTC assignment when using the VSP

[Laurent Pinchart]

Hi Kieran,

On Wednesday 12 Jul 2017 11:30:19 Kieran Bingham wrote:
> On 11/07/17 23:29, Laurent Pinchart wrote:
> > The DU can compose the output of a VSP with other planes on Gen2
> > hardware, and of two VSPs on Gen3 hardware. Neither of these features
> > are supported by the driver, and the current implementation always
> > assigns planes to CRTCs the same way.
> > 
> > Simplify the implementation by configuring plane assignment when setting
> > up DU groups, instead of recomputing it for every atomic plane update.
> > This allows skipping the wait for vertical blanking when stopping a
> > CRTC, as there's no need to reconfigure plane assignment at that point.
> > 
> > Signed-off-by: Laurent Pinchart
> > 
> 
> Reviewed-by: Kieran Bingham 
> 
> > ---
> > 
> >  drivers/gpu/drm/rcar-du/rcar_du_crtc.c  | 31 ++-
> >  drivers/gpu/drm/rcar-du/rcar_du_group.c | 12 
> >  drivers/gpu/drm/rcar-du/rcar_du_kms.c   | 28 +---
> >  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 10 +-
> >  drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  9 -
> >  5 files changed, 46 insertions(+), 44 deletions(-)

[snip]

> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_group.c index
> > 00d5f470d377..d26b647207b8 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> > @@ -126,6 +126,18 @@ static void rcar_du_group_setup(struct rcar_du_group
> > *rgrp)> 
> > if (rcdu->info->gen >= 3)
> > rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | 
DEFR10_DEFE10);
> > 
> > +   if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> > +   /*
> > +* The CRTCs can compose the output of a VSP with other planes
> > +* on Gen2 hardware, and of two VSPs on Gen3 hardware. Neither
> > +* of these features are supported by the driver, so we 
hardcode
> > +* plane assignment to CRTCs when setting the group up to 
avoid
> > +* the need to restart then group when setting planes up.
> 
> Minor nits in comment:
> 
>   /restart then group/restart the group/
> 
> I would also possibly swap the final 'planes up' as 'up planes' if you
> update here anyway:
> 
> * so we hardcode plane assignment to CRTCs when setting the group up to
> avoid
> * the need to restart the group when setting up planes.
> 
> Up to you of course :)

Thanks, I've fixed both, and also replaced "setting the group up" with 
"setting up the group".

> > +*/
> > +   rcar_du_group_write(rgrp, DS1PR, 1);
> > +   rcar_du_group_write(rgrp, DS2PR, rcdu->info->gen >= 3 ? 3 : 
2);
> 
> whew ... that DS2PR indexing change from g2 to g3 looks annoying ... I had
> to write out the logic tables on paper to verify the change here from the
> previous code.

That's also how I wrote the code :-)

> > +   }
> > +
> > 
> > /*
> > 
> >  * Use DS1PR and DS2PR to configure planes priorities and connects the
> >  * superposition 0 to DU0 pins. DU1 pins will be configured 
dynamically.

-- 
Regards,

Laurent Pinchart

[PATCH] pinctrl: sh-pfc: r8a7791: Add missing mmc_data8_b pin group

[Geert Uytterhoeven]

Pins D6 and D7 of the MMC interface can be muxed to two different sets
of pins, but currently only one set is supported.
Add a pin group for the alternative set to fix this.

Signed-off-by: Geert Uytterhoeven 
---
To be queued in sh-pfc-for-v4.14.

 drivers/pinctrl/sh-pfc/pfc-r8a7791.c | 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 4c5ffbd75be77148..10bd35f8c894c58e 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -2589,6 +2589,17 @@ static const unsigned int mmc_data8_mux[] = {
MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
 };
+static const unsigned int mmc_data8_b_pins[] = {
+   /* D[0:7] */
+   RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
+   RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
+   RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
+   RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
+};
+static const unsigned int mmc_data8_b_mux[] = {
+   MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
+   MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
+};
 static const unsigned int mmc_ctrl_pins[] = {
/* CLK, CMD */
RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
@@ -4420,7 +4431,7 @@ static const unsigned int vin2_clk_mux[] = {
 };
 
 static const struct {
-   struct sh_pfc_pin_group common[341];
+   struct sh_pfc_pin_group common[342];
struct sh_pfc_pin_group r8a779x[9];
 } pinmux_groups = {
.common = {
@@ -4523,6 +4534,7 @@ static const struct {
SH_PFC_PIN_GROUP(mmc_data1),
SH_PFC_PIN_GROUP(mmc_data4),
SH_PFC_PIN_GROUP(mmc_data8),
+   SH_PFC_PIN_GROUP(mmc_data8_b),
SH_PFC_PIN_GROUP(mmc_ctrl),
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
@@ -4955,6 +4967,7 @@ static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_data4",
"mmc_data8",
+   "mmc_data8_b",
"mmc_ctrl",
 };
 
-- 
2.7.4

Re: [PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

[Geert Uytterhoeven]

Hi Chris,

On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson
 wrote:
> Define the iwg20m board dependent part of the MMCIF0 device node.
>
> Signed-off-by: Chris Paterson 
>
> diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi 
> b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> index 001ca91..ffce1b6 100644
> --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
> +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi

> + {
> +   mmcif0_pins: mmc {
> +   groups = "mmc_data8", "mmc_ctrl";

"mmc_data8" is not correct, as D6/D7 of the eMMC are not connected to GP6_28
resp. GP6_29, but to GP6_6 resp. GP6_7.
So it should be "mmc_data8_b".

Unfortunately the latter pin group isn't supported by the PFC driver yet.
Cooking a patch...

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 2/3] ARM: dts: r8a7743: Add MMCIF0 support

[Geert Uytterhoeven]

On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson
 wrote:
> Add the MMCIF0 device to the r8a7743 device tree.
>
> Signed-off-by: Chris Paterson 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

[Geert Uytterhoeven]

On Wed, Jul 12, 2017 at 12:03 PM, Chris Paterson
 wrote:
> Signed-off-by: Chris Paterson 

Reviewed-by: Geert Uytterhoeven 

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH v2 07/16] drm/rcar-du: Use new iterator macros, v2.

[Maarten Lankhorst]

Op 12-07-17 om 11:15 schreef Daniel Vetter:
> On Wed, Jul 12, 2017 at 10:13:35AM +0200, Maarten Lankhorst wrote:
>> for_each_obj_in_state is about to be removed, so use the correct new
>> iterator macros.
>>
>> Signed-off-by: Maarten Lankhorst 
>> Cc: Laurent Pinchart 
>> Cc: linux-renesas-soc@vger.kernel.org
> Looks correct, but I think Laurent has a patch to rework/remove this.
> Found something below anyway.
>
>> ---
>>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 41 
>> -
>>  1 file changed, 20 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c 
>> b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
>> index dcde6288da6c..dfd84e3c8c25 100644
>> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
>> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
>> @@ -51,12 +51,9 @@
>>   */
>>  
>>  static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane,
>> +const struct rcar_du_plane_state 
>> *cur_state,
>>  struct rcar_du_plane_state *new_state)
>>  {
>> -struct rcar_du_plane_state *cur_state;
>> -
>> -cur_state = to_rcar_plane_state(plane->plane.state);
>> -
>>  /* Lowering the number of planes doesn't strictly require reallocation
>>   * as the extra hardware plane will be freed when committing, but doing
>>   * so could lead to more fragmentation.
>> @@ -141,16 +138,17 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>>  unsigned int groups = 0;
>>  unsigned int i;
>>  struct drm_plane *drm_plane;
>> -struct drm_plane_state *drm_plane_state;
>> +struct drm_plane_state *old_drm_plane_state, *new_drm_plane_state;
>>  
>>  /* Check if hardware planes need to be reallocated. */
>> -for_each_plane_in_state(state, drm_plane, drm_plane_state, i) {
>> -struct rcar_du_plane_state *plane_state;
>> +for_each_oldnew_plane_in_state(state, drm_plane, old_drm_plane_state, 
>> new_drm_plane_state, i) {
>> +struct rcar_du_plane_state *old_plane_state, *new_plane_state;
>>  struct rcar_du_plane *plane;
>>  unsigned int index;
>>  
>>  plane = to_rcar_plane(drm_plane);
>> -plane_state = to_rcar_plane_state(drm_plane_state);
>> +old_plane_state = to_rcar_plane_state(old_drm_plane_state);
>> +new_plane_state = to_rcar_plane_state(new_drm_plane_state);
>>  
>>  dev_dbg(rcdu->dev, "%s: checking plane (%u,%tu)\n", __func__,
>>  plane->group->index, plane - plane->group->planes);
>> @@ -159,19 +157,19 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>>   * the full reallocation procedure. Just mark the hardware
>>   * plane(s) as freed.
>>   */
>> -if (!plane_state->format) {
>> +if (!new_plane_state->format) {
>>  dev_dbg(rcdu->dev, "%s: plane is being disabled\n",
>>  __func__);
>>  index = plane - plane->group->planes;
>>  group_freed_planes[plane->group->index] |= 1 << index;
>> -plane_state->hwindex = -1;
>> +new_plane_state->hwindex = -1;
>>  continue;
>>  }
>>  
>>  /* If the plane needs to be reallocated mark it as such, and
>>   * mark the hardware plane(s) as free.
>>   */
>> -if (rcar_du_plane_needs_realloc(plane, plane_state)) {
>> +if (rcar_du_plane_needs_realloc(plane, old_plane_state, 
>> new_plane_state)) {
>>  dev_dbg(rcdu->dev, "%s: plane needs reallocation\n",
>>  __func__);
>>  groups |= 1 << plane->group->index;
>> @@ -179,7 +177,7 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>>  
>>  index = plane - plane->group->planes;
>>  group_freed_planes[plane->group->index] |= 1 << index;
>> -plane_state->hwindex = -1;
>> +new_plane_state->hwindex = -1;
>>  }
>>  }
>>  
>> @@ -226,16 +224,16 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>>  continue;
>>  }
>>  
>> -plane_state = to_rcar_plane_state(plane->plane.state);
>> +new_plane_state = 
>> to_rcar_plane_state(plane->plane.state);
>>  used_planes |= rcar_du_plane_hwmask(plane_state);
>>  
>>  dev_dbg(rcdu->dev,
>>  "%s: plane (%u,%tu) uses %u hwplanes (index 
>> %d)\n",
>>  __func__, plane->group->index,
>>  plane - plane->group->planes,
>> -plane_state->format ?
>> -

[PATCH v2] ARM: shmobile: rcar-gen2: Add support for CPG/MSSR bindings

[Geert Uytterhoeven]

When using the new CPG/MSSR bindings, there is no longer a
"renesas,rcar-gen2-cpg-clocks" node, and the code to obtain the external
clock crystal frequency falls back to a default of 20 MHz.
While this is correct for all upstream R-Car Gen2 and RZ/G1 boards, this
is not necessarily the case for out-of-tree third party boards.

Add support for finding the external clock crystal oscillator on RZ/G1M,
and on R-Car H2, M2-W, and M2-N using the new CPG/MSSR bindings, through
the corresponding "renesas,r8a77xx-cpg-mssr" nodes.

Note that this is not needed on R-Car V2H and E2, and on RZ/G1E, as on
those SoCs the arch_timer and generic counter clock is derived from the
ZS clock instead.

Signed-off-by: Geert Uytterhoeven 
---
v2:
  - Drop RZ/G1E,
  - Add support for R-Car H2, M2-W, and M2-N.
---
 arch/arm/mach-shmobile/setup-rcar-gen2.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c 
b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index a54125cb509ca775..18b556835e474feb 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -30,17 +30,29 @@
 #include "common.h"
 #include "rcar-gen2.h"
 
+static const struct of_device_id cpg_matches[] __initconst = {
+   { .compatible = "renesas,rcar-gen2-cpg-clocks", },
+   { .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
+   { .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
+   { .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
+   { .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
+   { /* sentinel */ }
+};
+
 static unsigned int __init get_extal_freq(void)
 {
+   const struct of_device_id *match;
struct device_node *cpg, *extal;
u32 freq = 2000;
+   int idx = 0;
 
-   cpg = of_find_compatible_node(NULL, NULL,
- "renesas,rcar-gen2-cpg-clocks");
+   cpg = of_find_matching_node_and_match(NULL, cpg_matches, );
if (!cpg)
return freq;
 
-   extal = of_parse_phandle(cpg, "clocks", 0);
+   if (match->data)
+   idx = of_property_match_string(cpg, "clock-names", match->data);
+   extal = of_parse_phandle(cpg, "clocks", idx);
of_node_put(cpg);
if (!extal)
return freq;
-- 
2.7.4

[PATCH] arm64: dts: r8a7796: Add missing second pair of DMA names to MSIOF nodes

[Geert Uytterhoeven]

MSIOF0 and MSIOF1 are tied to two DMA controllers through two pairs of
DMA specifiers.  However, the second pair of corresponding DMA names was
missing.

Fixes: 80fab06e258da762 ("arm64: dts: r8a7796: Add all MSIOF nodes")
Signed-off-by: Geert Uytterhoeven 
---
 arch/arm64/boot/dts/renesas/r8a7796.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index c7bbb501ebe06826..f63f9107f453b5b7 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1000,7 +1000,7 @@
clocks = < CPG_MOD 211>;
dmas = < 0x41>, < 0x40>,
   < 0x41>, < 0x40>;
-   dma-names = "tx", "rx";
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < R8A7796_PD_ALWAYS_ON>;
resets = < 211>;
#address-cells = <1>;
@@ -1016,7 +1016,7 @@
clocks = < CPG_MOD 210>;
dmas = < 0x43>, < 0x42>,
   < 0x43>, < 0x42>;
-   dma-names = "tx", "rx";
+   dma-names = "tx", "rx", "tx", "rx";
power-domains = < R8A7796_PD_ALWAYS_ON>;
resets = < 210>;
#address-cells = <1>;
-- 
2.7.4

Re: [PATCH v2 1/3] drm: rcar-du: Use the VBK interrupt for vblank events

[Kieran Bingham]

Hi Laurent,

On 11/07/17 23:29, Laurent Pinchart wrote:
> When implementing support for interlaced modes, the driver switched from
> reporting vblank events on the vertical blanking (VBK) interrupt to the
> frame end interrupt (FRM). This incorrectly divided the reported refresh
> rate by two. Fix it by moving back to the VBK interrupt.
> 
> Fixes: 906eff7fcada ("drm: rcar-du: Implement support for interlaced modes")
> Signed-off-by: Laurent Pinchart 

Of course, this looks much more correct than the patch I submitted :-)

Reviewed-by: Kieran Bingham 

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 98cf446391dc..17fd1cd5212c 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -698,7 +698,7 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
>   status = rcar_du_crtc_read(rcrtc, DSSR);
>   rcar_du_crtc_write(rcrtc, DSRCR, status & DSRCR_MASK);
>  
> - if (status & DSSR_FRM) {
> + if (status & DSSR_VBK) {
>   drm_crtc_handle_vblank(>crtc);
>  
>   if (rcdu->info->gen < 3)
> 

[PATCH v3] arm64: dts: r8a7795: Add all MSIOF nodes

[Geert Uytterhoeven]

Add the device nodes for all MSIOF SPI controllers, incl. clocks, power
domain, dma, and reset properties.

Due to a hardware erratum on R-Car H3 ES1.x, using MSIOF for SPI is only
supported on ES2.0 and later.

Signed-off-by: Geert Uytterhoeven 
---
Tested on r8a7795/salvator-xs with MSIOF3(A) connected to a HD44780
character LCD through a pair of 74HCT595 shift registers.

v3:
  - Add resets properties,
  - Add family-specific compatible values,
  - Add link to second DMA controller for MSIOF[01],

v2:
  - Rebased,
  - Switch to final CPG/MSSR bindings,
  - Change one-line summary prefix to match current arm-soc practices.
---
 arch/arm64/boot/dts/renesas/r8a7795.dtsi | 62 
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi 
b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 6f5130766a212d6d..507d8ad07aaf9007 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -899,6 +899,68 @@
status = "disabled";
};
 
+   msiof0: spi@e6e9 {
+   compatible = "renesas,msiof-r8a7795",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6e9 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 211>;
+   dmas = < 0x41>, < 0x40>,
+  < 0x41>, < 0x40>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7795_PD_ALWAYS_ON>;
+   resets = < 211>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof1: spi@e6ea {
+   compatible = "renesas,msiof-r8a7795",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6ea 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 210>;
+   dmas = < 0x43>, < 0x42>,
+  < 0x43>, < 0x42>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7795_PD_ALWAYS_ON>;
+   resets = < 210>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof2: spi@e6c0 {
+   compatible = "renesas,msiof-r8a7795",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c0 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 209>;
+   dmas = < 0x45>, < 0x44>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A7795_PD_ALWAYS_ON>;
+   resets = < 209>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
+   msiof3: spi@e6c1 {
+   compatible = "renesas,msiof-r8a7795",
+"renesas,rcar-gen3-msiof";
+   reg = <0 0xe6c1 0 0x0064>;
+   interrupts = ;
+   clocks = < CPG_MOD 208>;
+   dmas = < 0x47>, < 0x46>;
+   dma-names = "tx", "rx";
+   power-domains = < R8A7795_PD_ALWAYS_ON>;
+   resets = < 208>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "disabled";
+   };
+
scif0: serial@e6e6 {
compatible = "renesas,scif-r8a7795",
 "renesas,rcar-gen3-scif", "renesas,scif";
-- 
2.7.4

[PATCH 1/5] pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function definitions

[Geert Uytterhoeven]

From: Takeshi Kihara 

This patch fixes the incorrect IPSR register value definitions for
MSIOF3_{SS1,SS2}_E pin functions.

This is a correction to the incorrect implementation of IPSR register pin
assignment of the specifications updated for R8A7795 ES2.0 SoC in R-Car
Gen3 Hardware User's Manual Rev.0.53E.

Fixes: b205914c8f822ef2 ("pinctrl: sh-pfc: r8a7795: Add support for R-Car H3 
ES2.0")
Signed-off-by: Takeshi Kihara 
[geert: Reword, update Fixes for upstream]
Signed-off-by: Geert Uytterhoeven 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index 1656295af2b0c3be..f27d80c0b2d0953f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -215,8 +215,8 @@
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)
FM(FSCLKST2_N_A) F_(0, 0)   F_(0, 0)F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) 
F_(0, 0)
 #define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   FM(A25) 
FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)
F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)  
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)FM(A24) 
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-- 
2.7.4

[PATCH 2/5] pinctrl: sh-pfc: r8a7795: Add MSIOF pins, groups and functions

[Geert Uytterhoeven]

Add pins, groups, and functions for MSIOF on R-Car H3 ES2.0.

Extracted from a big patch in the BSP by Takeshi Kihara, with
corrections for MSIOF3 SS1_E/SS2_E pins and SS2_E mux.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 912 +++
 1 file changed, 912 insertions(+)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
index f27d80c0b2d0953f..7df11d4e853aa2e0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7795.c
@@ -1744,6 +1744,704 @@ static const unsigned int du_disp_mux[] = {
DU_DISP_MARK,
 };
 
+/* - MSIOF0 - 
*/
+static const unsigned int msiof0_clk_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 17),
+};
+static const unsigned int msiof0_clk_mux[] = {
+   MSIOF0_SCK_MARK,
+};
+static const unsigned int msiof0_sync_pins[] = {
+   /* SYNC */
+   RCAR_GP_PIN(5, 18),
+};
+static const unsigned int msiof0_sync_mux[] = {
+   MSIOF0_SYNC_MARK,
+};
+static const unsigned int msiof0_ss1_pins[] = {
+   /* SS1 */
+   RCAR_GP_PIN(5, 19),
+};
+static const unsigned int msiof0_ss1_mux[] = {
+   MSIOF0_SS1_MARK,
+};
+static const unsigned int msiof0_ss2_pins[] = {
+   /* SS2 */
+   RCAR_GP_PIN(5, 21),
+};
+static const unsigned int msiof0_ss2_mux[] = {
+   MSIOF0_SS2_MARK,
+};
+static const unsigned int msiof0_txd_pins[] = {
+   /* TXD */
+   RCAR_GP_PIN(5, 20),
+};
+static const unsigned int msiof0_txd_mux[] = {
+   MSIOF0_TXD_MARK,
+};
+static const unsigned int msiof0_rxd_pins[] = {
+   /* RXD */
+   RCAR_GP_PIN(5, 22),
+};
+static const unsigned int msiof0_rxd_mux[] = {
+   MSIOF0_RXD_MARK,
+};
+/* - MSIOF1 - 
*/
+static const unsigned int msiof1_clk_a_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 8),
+};
+static const unsigned int msiof1_clk_a_mux[] = {
+   MSIOF1_SCK_A_MARK,
+};
+static const unsigned int msiof1_sync_a_pins[] = {
+   /* SYNC */
+   RCAR_GP_PIN(6, 9),
+};
+static const unsigned int msiof1_sync_a_mux[] = {
+   MSIOF1_SYNC_A_MARK,
+};
+static const unsigned int msiof1_ss1_a_pins[] = {
+   /* SS1 */
+   RCAR_GP_PIN(6, 5),
+};
+static const unsigned int msiof1_ss1_a_mux[] = {
+   MSIOF1_SS1_A_MARK,
+};
+static const unsigned int msiof1_ss2_a_pins[] = {
+   /* SS2 */
+   RCAR_GP_PIN(6, 6),
+};
+static const unsigned int msiof1_ss2_a_mux[] = {
+   MSIOF1_SS2_A_MARK,
+};
+static const unsigned int msiof1_txd_a_pins[] = {
+   /* TXD */
+   RCAR_GP_PIN(6, 7),
+};
+static const unsigned int msiof1_txd_a_mux[] = {
+   MSIOF1_TXD_A_MARK,
+};
+static const unsigned int msiof1_rxd_a_pins[] = {
+   /* RXD */
+   RCAR_GP_PIN(6, 10),
+};
+static const unsigned int msiof1_rxd_a_mux[] = {
+   MSIOF1_RXD_A_MARK,
+};
+static const unsigned int msiof1_clk_b_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(5, 9),
+};
+static const unsigned int msiof1_clk_b_mux[] = {
+   MSIOF1_SCK_B_MARK,
+};
+static const unsigned int msiof1_sync_b_pins[] = {
+   /* SYNC */
+   RCAR_GP_PIN(5, 3),
+};
+static const unsigned int msiof1_sync_b_mux[] = {
+   MSIOF1_SYNC_B_MARK,
+};
+static const unsigned int msiof1_ss1_b_pins[] = {
+   /* SS1 */
+   RCAR_GP_PIN(5, 4),
+};
+static const unsigned int msiof1_ss1_b_mux[] = {
+   MSIOF1_SS1_B_MARK,
+};
+static const unsigned int msiof1_ss2_b_pins[] = {
+   /* SS2 */
+   RCAR_GP_PIN(5, 0),
+};
+static const unsigned int msiof1_ss2_b_mux[] = {
+   MSIOF1_SS2_B_MARK,
+};
+static const unsigned int msiof1_txd_b_pins[] = {
+   /* TXD */
+   RCAR_GP_PIN(5, 8),
+};
+static const unsigned int msiof1_txd_b_mux[] = {
+   MSIOF1_TXD_B_MARK,
+};
+static const unsigned int msiof1_rxd_b_pins[] = {
+   /* RXD */
+   RCAR_GP_PIN(5, 7),
+};
+static const unsigned int msiof1_rxd_b_mux[] = {
+   MSIOF1_RXD_B_MARK,
+};
+static const unsigned int msiof1_clk_c_pins[] = {
+   /* SCK */
+   RCAR_GP_PIN(6, 17),
+};
+static const unsigned int msiof1_clk_c_mux[] = {
+   MSIOF1_SCK_C_MARK,
+};
+static const unsigned int msiof1_sync_c_pins[] = {
+   /* SYNC */
+   RCAR_GP_PIN(6, 18),
+};
+static const unsigned int msiof1_sync_c_mux[] = {
+   MSIOF1_SYNC_C_MARK,
+};
+static const unsigned int msiof1_ss1_c_pins[] = {
+   /* SS1 */
+   RCAR_GP_PIN(6, 21),
+};
+static const unsigned int msiof1_ss1_c_mux[] = {
+   MSIOF1_SS1_C_MARK,
+};
+static const unsigned int msiof1_ss2_c_pins[] = {
+   /* SS2 */
+   RCAR_GP_PIN(6, 27),
+};
+static const unsigned int msiof1_ss2_c_mux[] = {
+   MSIOF1_SS2_C_MARK,
+};
+static const unsigned int msiof1_txd_c_pins[] = {
+   /* TXD */
+   RCAR_GP_PIN(6, 20),
+};
+static const unsigned int msiof1_txd_c_mux[] = {
+   MSIOF1_TXD_C_MARK,

[PATCH 3/5] pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pin function definitions

[Geert Uytterhoeven]

From: Takeshi Kihara 

This patch fixes the incorrect IPSR register value definitions for
MSIOF3_{SS1,SS2}_E pin functions.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
[geert: Reword]
Signed-off-by: Geert Uytterhoeven 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 98bf5d0e078ec096..6fa1729d784e6df2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -221,8 +221,8 @@
 #define IP0_15_12  FM(AVB_LINK)F_(0, 0)
FM(MSIOF2_SCK_C)FM(TX4_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_19_16  FM(AVB_AVTP_MATCH_A)F_(0, 0)
FM(MSIOF2_RXD_C)FM(CTS4_N_A)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP0_23_20  FM(AVB_AVTP_CAPTURE_A)  F_(0, 0)
FM(MSIOF2_TXD_C)FM(RTS4_N_TANS_A)   F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 
0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_27_24  FM(IRQ0)FM(QPOLB)   F_(0, 0)
FM(DU_CDE)  FM(VI4_DATA0_B) FM(CAN0_TX_B)   
FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
+#define IP0_31_28  FM(IRQ1)FM(QPOLA)   F_(0, 0)
FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B)   
FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0)   F_(0, 0)
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_3_0FM(IRQ2)FM(QCPV_QDE)F_(0, 
0)FM(DU_EXODDF_DU_ODDF_DISP_CDE)  FM(VI4_DATA2_B) F_(0, 0)  
  F_(0, 0)FM(MSIOF3_SYNC_E) F_(0, 0)  FM(PWM3_B)
  F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_7_4FM(IRQ3)FM(QSTVB_QVE)   FM(A25) 
FM(DU_DOTCLKOUT1)   FM(VI4_DATA3_B) F_(0, 0)
F_(0, 0)FM(MSIOF3_SCK_E) F_(0, 0)   FM(PWM4_B)  
F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
 #define IP1_11_8   FM(IRQ4)FM(QSTH_QHS)FM(A24) 
FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0)F_(0, 
0)FM(MSIOF3_RXD_E) F_(0, 0)   FM(PWM5_B)  F_(0, 
0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
-- 
2.7.4

[PATCH 0/5] pinctrl: sh-pfc: r8a7795/r8a7796: MSIOF updates

[Geert Uytterhoeven]

Hi Linus, Laurent,

This patch series fixes MSIOF-related bugs in the R-Car H3 ES2.0 and M3-W
pin control drivers, and enables support for MSIOF on R-Car H3 ES2.0.

I plan to queue these up in sh-pfc-for-v4.14.

Thanks!

Geert Uytterhoeven (2):
  pinctrl: sh-pfc: r8a7795: Add MSIOF pins, groups and functions
  pinctrl: sh-pfc: r8a7796: Fix MSIOF3 SS2_E mux

Takeshi Kihara (3):
  pinctrl: sh-pfc: r8a7795: Fix MSIOF3_{SS1,SS2}_E pin function
definitions
  pinctrl: sh-pfc: r8a7796: Fix MSIOF3_{SS1,SS2}_E pin function
definitions
  pinctrl: sh-pfc: r8a7796: Fix IPSR setting for MSIOF3_SS1_E pin

 drivers/pinctrl/sh-pfc/pfc-r8a7795.c | 916 ++-
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c |   8 +-
 2 files changed, 918 insertions(+), 6 deletions(-)

-- 
2.7.4

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

[PATCH 5/5] pinctrl: sh-pfc: r8a7796: Fix MSIOF3 SS2_E mux

[Geert Uytterhoeven]

Fix a copy-and-paste bug in the MSIOF3 SS2_E mux array.

Fixes: 4753231cc9468390 ("pinctrl: sh-pfc: r8a7796: Add MSIOF pins, groups and 
functions")
Signed-off-by: Geert Uytterhoeven 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 0fd96f198b4dfae2..1ef8d90e48cef317 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -3082,7 +3082,7 @@ static const unsigned int msiof3_ss2_e_pins[] = {
RCAR_GP_PIN(2, 0),
 };
 static const unsigned int msiof3_ss2_e_mux[] = {
-   MSIOF3_SS1_E_MARK,
+   MSIOF3_SS2_E_MARK,
 };
 static const unsigned int msiof3_txd_e_pins[] = {
/* TXD */
-- 
2.7.4

[PATCH 4/5] pinctrl: sh-pfc: r8a7796: Fix IPSR setting for MSIOF3_SS1_E pin

[Geert Uytterhoeven]

From: Takeshi Kihara 

This patch fixes the IPSR register setting when the MSIOF3_SS1_E pin
function is selected.

This is a correction to the incorrect implementation of IPSR register
pin assignment for R8A7796 SoC specification of R-Car Gen3 Hardware
User's Manual Rev.0.51E or later.

Fixes: f9aece7344bd81ce ("pinctrl: sh-pfc: Initial R8A7796 PFC support")
Signed-off-by: Takeshi Kihara 
[geert: Reword]
Signed-off-by: Geert Uytterhoeven 
---
 drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c 
b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
index 6fa1729d784e6df2..0fd96f198b4dfae2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c
@@ -645,7 +645,7 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B,SEL_VIN4_1),
PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B,  SEL_RCAN0_1),
PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B,SEL_CANFD0_1),
-   PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E,   SEL_MSIOF3_4),
+   PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E,   SEL_MSIOF3_4),
 
/* IPSR1 */
PINMUX_IPSR_GPSR(IP1_3_0,   IRQ2),
-- 
2.7.4

Re: [PATCH v2 2/3] drm: rcar-du: Fix planes to CRTC assignment when using the VSP

[Kieran Bingham]

Hi Laurent,

Thanks for the patch

Only a minor nit on one comment, but aside from that,

On 11/07/17 23:29, Laurent Pinchart wrote:
> The DU can compose the output of a VSP with other planes on Gen2
> hardware, and of two VSPs on Gen3 hardware. Neither of these features
> are supported by the driver, and the current implementation always
> assigns planes to CRTCs the same way.
> 
> Simplify the implementation by configuring plane assignment when setting
> up DU groups, instead of recomputing it for every atomic plane update.
> This allows skipping the wait for vertical blanking when stopping a
> CRTC, as there's no need to reconfigure plane assignment at that point.
> 
> Signed-off-by: Laurent Pinchart 

Reviewed-by: Kieran Bingham 

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.c  | 31 ---
>  drivers/gpu/drm/rcar-du/rcar_du_group.c | 12 
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c   | 28 +---
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 10 +-
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c   |  9 -
>  5 files changed, 46 insertions(+), 44 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> index 17fd1cd5212c..413ab032afed 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c
> @@ -315,6 +315,10 @@ static void rcar_du_crtc_update_planes(struct 
> rcar_du_crtc *rcrtc)
>   unsigned int i;
>   u32 dspr = 0;
>  
> + /* Plane assignment is fixed when using the VSP. */
> + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
> + return;
> +
>   for (i = 0; i < rcrtc->group->num_planes; ++i) {
>   struct rcar_du_plane *plane = >group->planes[i];
>   unsigned int j;
> @@ -351,17 +355,6 @@ static void rcar_du_crtc_update_planes(struct 
> rcar_du_crtc *rcrtc)
>   }
>   }
>  
> - /* If VSP+DU integration is enabled the plane assignment is fixed. */
> - if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> - if (rcdu->info->gen < 3) {
> - dspr = (rcrtc->index % 2) + 1;
> - hwplanes = 1 << (rcrtc->index % 2);
> - } else {
> - dspr = (rcrtc->index % 2) ? 3 : 1;
> - hwplanes = 1 << ((rcrtc->index % 2) ? 2 : 0);
> - }
> - }
> -
>   /*
>* Update the planes to display timing and dot clock generator
>* associations.
> @@ -462,8 +455,13 @@ static void rcar_du_crtc_setup(struct rcar_du_crtc 
> *rcrtc)
>   rcar_du_crtc_set_display_timing(rcrtc);
>   rcar_du_group_set_routing(rcrtc->group);
>  
> - /* Start with all planes disabled. */
> - rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
> + /*
> +  * Start with all planes disabled, except when using the VSP in which
> +  * case the fixed plane assignment must not be modified.
> +  */
> + if (!rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
> + rcar_du_group_write(rcrtc->group,
> + rcrtc->index % 2 ? DS2PR : DS1PR, 0);
>  
>   /* Enable the VSP compositor. */
>   if (rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE))
> @@ -505,8 +503,11 @@ static void rcar_du_crtc_stop(struct rcar_du_crtc *rcrtc)
>* are stopped in one operation as we now wait for one vblank per CRTC.
>* Whether this can be improved needs to be researched.
>*/
> - rcar_du_group_write(rcrtc->group, rcrtc->index % 2 ? DS2PR : DS1PR, 0);
> - drm_crtc_wait_one_vblank(crtc);
> + if (!rcar_du_has(rcrtc->group->dev, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> + rcar_du_group_write(rcrtc->group,
> + rcrtc->index % 2 ? DS2PR : DS1PR, 0);
> + drm_crtc_wait_one_vblank(crtc);
> + }
>  
>   /*
>* Disable vertical blanking interrupt reporting. We first need to wait
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> index 00d5f470d377..d26b647207b8 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c
> @@ -126,6 +126,18 @@ static void rcar_du_group_setup(struct rcar_du_group 
> *rgrp)
>   if (rcdu->info->gen >= 3)
>   rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
>  
> + if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> + /*
> +  * The CRTCs can compose the output of a VSP with other planes
> +  * on Gen2 hardware, and of two VSPs on Gen3 hardware. Neither
> +  * of these features are supported by the driver, so we hardcode
> +  * plane assignment to CRTCs when setting the group up to avoid
> +  * the need to 

[PATCH] spi: sh-msiof: Limit minimum divider on R-Car Gen3

[Geert Uytterhoeven]

On R-Car Gen3 SoCs (excluding R-Car H3 ES1.x, which cannot be used for
SPI due to a hardware erratum), BRPS x BRDV = 1/1 is an invalid divider
setting.
Implement this limitation using an SoC/family-specific minimum divider.

Signed-off-by: Geert Uytterhoeven 
---
 drivers/spi/spi-sh-msiof.c | 32 +++-
 1 file changed, 23 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index c304c7167866d2db..0eb1e95834854fb6 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -38,6 +38,7 @@ struct sh_msiof_chipdata {
u16 tx_fifo_size;
u16 rx_fifo_size;
u16 master_flags;
+   u16 min_div;
 };
 
 struct sh_msiof_spi_priv {
@@ -49,6 +50,7 @@ struct sh_msiof_spi_priv {
struct completion done;
unsigned int tx_fifo_size;
unsigned int rx_fifo_size;
+   unsigned int min_div;
void *tx_dma_page;
void *rx_dma_page;
dma_addr_t tx_dma_addr;
@@ -261,6 +263,8 @@ static void sh_msiof_spi_set_clk_regs(struct 
sh_msiof_spi_priv *p,
if (!WARN_ON(!spi_hz || !parent_rate))
div = DIV_ROUND_UP(parent_rate, spi_hz);
 
+   div = max_t(unsigned long, div, p->min_div);
+
for (k = 0; k < ARRAY_SIZE(sh_msiof_spi_div_table); k++) {
brps = DIV_ROUND_UP(div, sh_msiof_spi_div_table[k].div);
/* SCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */
@@ -998,24 +1002,33 @@ static const struct sh_msiof_chipdata sh_data = {
.tx_fifo_size = 64,
.rx_fifo_size = 64,
.master_flags = 0,
+   .min_div = 1,
+};
+
+static const struct sh_msiof_chipdata rcar_gen2_data = {
+   .tx_fifo_size = 64,
+   .rx_fifo_size = 64,
+   .master_flags = SPI_MASTER_MUST_TX,
+   .min_div = 1,
 };
 
-static const struct sh_msiof_chipdata r8a779x_data = {
+static const struct sh_msiof_chipdata rcar_gen3_data = {
.tx_fifo_size = 64,
.rx_fifo_size = 64,
.master_flags = SPI_MASTER_MUST_TX,
+   .min_div = 2,
 };
 
 static const struct of_device_id sh_msiof_match[] = {
{ .compatible = "renesas,sh-mobile-msiof", .data = _data },
-   { .compatible = "renesas,msiof-r8a7790",   .data = _data },
-   { .compatible = "renesas,msiof-r8a7791",   .data = _data },
-   { .compatible = "renesas,msiof-r8a7792",   .data = _data },
-   { .compatible = "renesas,msiof-r8a7793",   .data = _data },
-   { .compatible = "renesas,msiof-r8a7794",   .data = _data },
-   { .compatible = "renesas,rcar-gen2-msiof", .data = _data },
-   { .compatible = "renesas,msiof-r8a7796",   .data = _data },
-   { .compatible = "renesas,rcar-gen3-msiof", .data = _data },
+   { .compatible = "renesas,msiof-r8a7790",   .data = _gen2_data },
+   { .compatible = "renesas,msiof-r8a7791",   .data = _gen2_data },
+   { .compatible = "renesas,msiof-r8a7792",   .data = _gen2_data },
+   { .compatible = "renesas,msiof-r8a7793",   .data = _gen2_data },
+   { .compatible = "renesas,msiof-r8a7794",   .data = _gen2_data },
+   { .compatible = "renesas,rcar-gen2-msiof", .data = _gen2_data },
+   { .compatible = "renesas,msiof-r8a7796",   .data = _gen3_data },
+   { .compatible = "renesas,rcar-gen3-msiof", .data = _gen3_data },
{ .compatible = "renesas,sh-msiof",.data = _data }, /* 
Deprecated */
{},
 };
@@ -1230,6 +1243,7 @@ static int sh_msiof_spi_probe(struct platform_device 
*pdev)
platform_set_drvdata(pdev, p);
p->master = master;
p->info = info;
+   p->min_div = chipdata->min_div;
 
init_completion(>done);
 
-- 
2.7.4

[PATCH v2] spi: sh-msiof: Add support for R-Car H3

[Geert Uytterhoeven]

Add support for MSIOF in r8a7795 (R-Car H3).
Due to a hardware erratum on R-Car H3 ES1.x, this is only supported on
ES2.0 and later.

No driver update is needed.

Signed-off-by: Geert Uytterhoeven 
---
v2:
  - Drop RFC status,
  - Rebased,
  - Drop matching on "renesas,msiof-r8a7795", as the driver started
matching against "renesas,rcar-gen3-msiof" in the mean time.
---
 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt 
b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 64ee489571c42f88..39e5ef7c5e71694e 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -6,6 +6,7 @@ Required properties:
 "renesas,msiof-r8a7792" (R-Car V2H)
 "renesas,msiof-r8a7793" (R-Car M2-N)
 "renesas,msiof-r8a7794" (R-Car E2)
+"renesas,msiof-r8a7795" (R-Car H3)
 "renesas,msiof-r8a7796" (R-Car M3-W)
 "renesas,msiof-sh73a0" (SH-Mobile AG5)
 "renesas,sh-mobile-msiof" (generic SH-Mobile 
compatibile device)
-- 
2.7.4

Re: [PATCH mmc/next v3 0/4] mmc: renesas_sdhi: add support for R-Car Gen3 SDHI DMAC

[Simon Horman]

On Tue, Jul 11, 2017 at 04:43:00PM +0200, Ulf Hansson wrote:
> On 21 June 2017 at 16:00, Simon Horman  wrote:
> > Hi,
> >
> > this series adds support for the internal DMAC used by r8a779[56] SoCs.
> > This is achieved by adding a new variant of the SDHI driver for this
> > DMA controller with compat strings for the r8a779[56] SoCs.
> > Compat strings for these SoCs are also removed from the existing SYS DMAC
> > variant of the SDHI driver.
> >
> > Based on mmc/next
> >
> > Headline performance boost: 9.5MB/s -> 39.7MB/s
> > Details below.
> >
> > Simon Horman (3):
> >   mmc: tmio, renesas-sdhi: add dataend to DMA ops
> >   mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC
> >   mmc: renesas-sdhi: remove gen3 support from SYS-DMAC driver
> >
> > Yoshihiro Shimoda (1):
> >   mmc: tmio, renesas-sdhi: add max_{segs,blk_count} to tmio_mmc_data
> >
> >  drivers/mmc/host/Kconfig  |  19 ++
> >  drivers/mmc/host/Makefile |   8 +-
> >  drivers/mmc/host/renesas_sdhi.h   |   2 +
> >  drivers/mmc/host/renesas_sdhi_core.c  |   2 +
> >  drivers/mmc/host/renesas_sdhi_internal_dmac.c | 271 
> > ++
> >  drivers/mmc/host/renesas_sdhi_sys_dmac.c  |  29 +--
> >  drivers/mmc/host/tmio_mmc.h   |   2 +
> >  drivers/mmc/host/tmio_mmc_core.c  |  16 +-
> >  include/linux/mfd/tmio.h  |   2 +
> >  9 files changed, 323 insertions(+), 28 deletions(-)
> >  create mode 100644 drivers/mmc/host/renesas_sdhi_internal_dmac.c
> 
> Thanks, applied patch 1->3 for next!

Great, thanks.

[PATCH 3/3] ARM: dts: iwg20m: Add MMCIF0 support

[Chris Paterson]

Define the iwg20m board dependent part of the MMCIF0 device node.

Signed-off-by: Chris Paterson 

diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi 
b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
index 001ca91..ffce1b6 100644
--- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
+++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi
@@ -22,8 +22,34 @@
device_type = "memory";
reg = <2 0x 0 0x2000>;
};
+
+   reg_3p3v: 3p3v {
+   compatible = "regulator-fixed";
+   regulator-name = "3P3V";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
 };
 
 _clk {
clock-frequency = <2000>;
 };
+
+ {
+   mmcif0_pins: mmc {
+   groups = "mmc_data8", "mmc_ctrl";
+   function = "mmc";
+   };
+};
+
+ {
+   pinctrl-0 = <_pins>;
+   pinctrl-names = "default";
+
+   vmmc-supply = <_3p3v>;
+   bus-width = <8>;
+   non-removable;
+   status = "okay";
+};
-- 
1.9.1

[PATCH 2/3] ARM: dts: r8a7743: Add MMCIF0 support

[Chris Paterson]

Add the MMCIF0 device to the r8a7743 device tree.

Signed-off-by: Chris Paterson 

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 0d02191..f62e858 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -641,6 +641,22 @@
#size-cells = <0>;
status = "disabled";
};
+
+   mmcif0: mmc@ee20 {
+   compatible = "renesas,mmcif-r8a7743",
+"renesas,sh-mmcif";
+   reg = <0 0xee20 0 0x80>;
+   interrupts = ;
+   clocks = < CPG_MOD 315>;
+   dmas = < 0xd1>, < 0xd2>,
+  < 0xd1>, < 0xd2>;
+   dma-names = "tx", "rx", "tx", "rx";
+   power-domains = < R8A7743_PD_ALWAYS_ON>;
+   resets = < 315>;
+   reg-io-width = <4>;
+   max-frequency = <9750>;
+   status = "disabled";
+   };
};
 
/* External root clock */
-- 
1.9.1

[PATCH 1/3] dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings

[Chris Paterson]

Signed-off-by: Chris Paterson 

diff --git a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt 
b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
index c32dc5a..703e18c 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,mmcif.txt
@@ -11,6 +11,7 @@ Required properties:
- "renesas,mmcif-r7s72100" for the MMCIF found in r7s72100 SoCs
- "renesas,mmcif-r8a73a4" for the MMCIF found in r8a73a4 SoCs
- "renesas,mmcif-r8a7740" for the MMCIF found in r8a7740 SoCs
+   - "renesas,mmcif-r8a7743" for the MMCIF found in r8a7743 SoCs
- "renesas,mmcif-r8a7778" for the MMCIF found in r8a7778 SoCs
- "renesas,mmcif-r8a7790" for the MMCIF found in r8a7790 SoCs
- "renesas,mmcif-r8a7791" for the MMCIF found in r8a7791 SoCs
@@ -21,7 +22,7 @@ Required properties:
 - interrupts: Some SoCs have only 1 shared interrupt, while others have either
   2 or 3 individual interrupts (error, int, card detect). Below is the number
   of interrupts for each SoC:
-1: r8a73a4, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
+1: r8a73a4, r8a7743, r8a7778, r8a7790, r8a7791, r8a7793, r8a7794
 2: r8a7740, sh73a0
 3: r7s72100
 
-- 
1.9.1

[PATCH 0/3] Add MMCIF0 support for r8a7743/iwg20m

[Chris Paterson]

This series adds MMCIF0 support for the r8a7743 SoC and the iWave-RZG1M-20M
Qseven SOM.

This series is based on renesas-devel-20170711-v4.12.

Chris Paterson (3):
  dt-bindings: mmc: sh_mmcif: Document r8a7743 DT bindings
  ARM: dts: r8a7743: Add MMCIF0 support
  ARM: dts: iwg20m: Add MMCIF0 support

 .../devicetree/bindings/mmc/renesas,mmcif.txt  |  3 ++-
 arch/arm/boot/dts/r8a7743-iwg20m.dtsi  | 26 ++
 arch/arm/boot/dts/r8a7743.dtsi | 16 +
 3 files changed, 44 insertions(+), 1 deletion(-)

-- 
1.9.1

Re: [PATCH 07/16] drm/rcar-du: Use new iterator macros

[Daniel Vetter]

On Wed, Jul 12, 2017 at 10:13:35AM +0200, Maarten Lankhorst wrote:
> for_each_obj_in_state is about to be removed, so use the correct new
> iterator macros.
> 
> Signed-off-by: Maarten Lankhorst 
> Cc: Laurent Pinchart 
> Cc: linux-renesas-soc@vger.kernel.org

Looks correct, but I think Laurent has a patch to rework/remove this.
Found something below anyway.

> ---
>  drivers/gpu/drm/rcar-du/rcar_du_plane.c | 41 
> -
>  1 file changed, 20 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c 
> b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> index dcde6288da6c..dfd84e3c8c25 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
> @@ -51,12 +51,9 @@
>   */
>  
>  static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane,
> + const struct rcar_du_plane_state 
> *cur_state,
>   struct rcar_du_plane_state *new_state)
>  {
> - struct rcar_du_plane_state *cur_state;
> -
> - cur_state = to_rcar_plane_state(plane->plane.state);
> -
>   /* Lowering the number of planes doesn't strictly require reallocation
>* as the extra hardware plane will be freed when committing, but doing
>* so could lead to more fragmentation.
> @@ -141,16 +138,17 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>   unsigned int groups = 0;
>   unsigned int i;
>   struct drm_plane *drm_plane;
> - struct drm_plane_state *drm_plane_state;
> + struct drm_plane_state *old_drm_plane_state, *new_drm_plane_state;
>  
>   /* Check if hardware planes need to be reallocated. */
> - for_each_plane_in_state(state, drm_plane, drm_plane_state, i) {
> - struct rcar_du_plane_state *plane_state;
> + for_each_oldnew_plane_in_state(state, drm_plane, old_drm_plane_state, 
> new_drm_plane_state, i) {
> + struct rcar_du_plane_state *old_plane_state, *new_plane_state;
>   struct rcar_du_plane *plane;
>   unsigned int index;
>  
>   plane = to_rcar_plane(drm_plane);
> - plane_state = to_rcar_plane_state(drm_plane_state);
> + old_plane_state = to_rcar_plane_state(old_drm_plane_state);
> + new_plane_state = to_rcar_plane_state(new_drm_plane_state);
>  
>   dev_dbg(rcdu->dev, "%s: checking plane (%u,%tu)\n", __func__,
>   plane->group->index, plane - plane->group->planes);
> @@ -159,19 +157,19 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>* the full reallocation procedure. Just mark the hardware
>* plane(s) as freed.
>*/
> - if (!plane_state->format) {
> + if (!new_plane_state->format) {
>   dev_dbg(rcdu->dev, "%s: plane is being disabled\n",
>   __func__);
>   index = plane - plane->group->planes;
>   group_freed_planes[plane->group->index] |= 1 << index;
> - plane_state->hwindex = -1;
> + new_plane_state->hwindex = -1;
>   continue;
>   }
>  
>   /* If the plane needs to be reallocated mark it as such, and
>* mark the hardware plane(s) as free.
>*/
> - if (rcar_du_plane_needs_realloc(plane, plane_state)) {
> + if (rcar_du_plane_needs_realloc(plane, old_plane_state, 
> new_plane_state)) {
>   dev_dbg(rcdu->dev, "%s: plane needs reallocation\n",
>   __func__);
>   groups |= 1 << plane->group->index;
> @@ -179,7 +177,7 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>  
>   index = plane - plane->group->planes;
>   group_freed_planes[plane->group->index] |= 1 << index;
> - plane_state->hwindex = -1;
> + new_plane_state->hwindex = -1;
>   }
>   }
>  
> @@ -226,16 +224,16 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
>   continue;
>   }
>  
> - plane_state = to_rcar_plane_state(plane->plane.state);
> + new_plane_state = 
> to_rcar_plane_state(plane->plane.state);
>   used_planes |= rcar_du_plane_hwmask(plane_state);
>  
>   dev_dbg(rcdu->dev,
>   "%s: plane (%u,%tu) uses %u hwplanes (index 
> %d)\n",
>   __func__, plane->group->index,
>   plane - plane->group->planes,
> - plane_state->format ?
> - plane_state->format->planes : 0,
> - 

Re: [PATCH v2 2/7] arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances

[Laurent Pinchart]

Hi Geert,

On Wednesday 12 Jul 2017 09:22:50 Geert Uytterhoeven wrote:
> On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart wrote:
> > The FCPs handle the interface between various IP cores and memory. Add
> > the instances related to the FDPs and VSP2s.
> > 
> > Signed-off-by: Laurent Pinchart
> > 
> > Reviewed-by: Geert Uytterhoeven 
> 
> Ah, the pitfalls of reposting patches 8 months later...
> 
> >  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 42
> >   1 file changed, 42 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> > b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index
> > 1f6710912045..28b0e2127021 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> > @@ -1440,6 +1440,48 @@
> > /* placeholder */
> > };
> > 
> > +   fcpf0: fcp@fe95 {
> > +   compatible = "renesas,fcpf";
> > +   reg = <0 0xfe95 0 0x200>;
> > +   clocks = < CPG_MOD 615>;
> > +   power-domains = < R8A7796_PD_A3VC>;
> 
> ... missing resets properties.

Oops :-/

Simon, can I send an incremental patch ?

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 0/2] R-Car H3 ES2.0 Salvator-X: Enable DU support in DT

[Laurent Pinchart]

Hi Simon,

On Wednesday 12 Jul 2017 07:56:15 Simon Horman wrote:
> On Wed, Jul 12, 2017 at 02:20:43AM +0300, Laurent Pinchart wrote:
> > On Tuesday 11 Jul 2017 11:16:17 Simon Horman wrote:
> >> On Mon, Jul 10, 2017 at 04:31:38PM +0300, Laurent Pinchart wrote:
> >>> On Monday 26 Jun 2017 19:29:28 Laurent Pinchart wrote:
>  Hello,
>  
>  This patch series enable DU support in DT for the R-Car H3 ES2.0
>  Salvator-X board. Patch 1/2 extends the DT bindings as needed, and
>  patch
>  2/2 then enables DU in the SoC DT.
>  
>  The patches are based on top of Simon's arm64-dt-for-v4.14 branch.
>  
>  Compared to v1
>  
>  - the VSP DT bindings have been extended in patch 1/2
>  - patch 2/2 has been updated accordingly
>  - patch "arm64: dts: r8a7795: salvator-x: Unify DU node between ES1.x
>  
>    and ES2.0" has been dropped
>  
>  Laurent Pinchart (2):
>    drm: rcar-du: Add a VSP channel index to the vsps DT property
>    arm64: dts: r8a7795: Add support for the DU
>   
>   .../devicetree/bindings/display/renesas,du.txt | 51 +++--
>   arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi   |  1 -
>   arch/arm64/boot/dts/renesas/r8a7795.dtsi   |  2 +
>   3 files changed, 32 insertions(+), 22 deletions(-)
> >>> 
> >>> Hi Simon,
> >>> 
> >>> Could you please pick this series for v4.14 ? I believe it has
> >>> received the necessary acks.
> >> 
> >> Hi Laurent,
> >> 
> >> sure, both patches applied for v4.14.
> > 
> > It looks like you've picked v2 instead of v2.1 for patch 2/2 :-/ Is it
> > possible to fix that ?
> 
> Sure, but I don't see v2.1. Could you repost it?

Strange. I've reposted the patch and CC'ed you.

-- 
Regards,

Laurent Pinchart

[RESEND] [PATCH v2.1 1/2] dt-bindings: display: rcar-du: Add a VSP channel index to the vsps DT property

[Laurent Pinchart]

On some R-Car SoCs a single VSP can serve multiple DU channels through
multiple LIF instances in the VSP. The current DT bindings don't support
specifying that kind of SoC integration scheme. Extend them with a VSP
channel index.

Backward compatibility can be ensured in drivers by checking the length
of the vsps property and setting the channel to 0 when the property
doesn't contain channel indices.

Signed-off-by: Laurent Pinchart 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Rob Herring 
---
 .../devicetree/bindings/display/renesas,du.txt | 51 +-
 1 file changed, 30 insertions(+), 21 deletions(-)

Changes since v2:

- Used proper prefix for subject line
- Fixed type in vsps property description
- Increase visibility in the vsps example

diff --git a/Documentation/devicetree/bindings/display/renesas,du.txt 
b/Documentation/devicetree/bindings/display/renesas,du.txt
index c6cb96a4fa93..4bbd1e9bf3be 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.txt
+++ b/Documentation/devicetree/bindings/display/renesas,du.txt
@@ -36,8 +36,10 @@ Required Properties:
   When supplied they must be named "dclkin.x" with "x" being the input
   clock numerical index.
 
-  - vsps: A list of phandles to the VSP nodes that handle the memory
-interfaces for the DU channels.
+  - vsps: A list of phandle and channel index tuples to the VSPs that handle
+the memory interfaces for the DU channels. The phandle identifies the VSP
+instance that serves the DU channel, and the channel index identifies the
+LIF instance in that VSP.
 
 Required nodes:
 
@@ -59,24 +61,24 @@ corresponding to each DU output.
  R8A7796 (M3-W)DPADHDMILVDS-
 
 
-Example: R8A7790 (R-Car H2) DU
+Example: R8A7795 (R-Car H3) ES2.0 DU
 
-   du: du@feb0 {
-   compatible = "renesas,du-r8a7790";
-   reg = <0 0xfeb0 0 0x7>,
- <0 0xfeb9 0 0x1c>,
- <0 0xfeb94000 0 0x1c>;
-   reg-names = "du", "lvds.0", "lvds.1";
-   interrupt-parent = <>;
-   interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
-<0 268 IRQ_TYPE_LEVEL_HIGH>,
-<0 269 IRQ_TYPE_LEVEL_HIGH>;
-   clocks = <_clks R8A7790_CLK_DU0>,
-<_clks R8A7790_CLK_DU1>,
-<_clks R8A7790_CLK_DU2>,
-<_clks R8A7790_CLK_LVDS0>,
-<_clks R8A7790_CLK_LVDS1>;
-   clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
+   du: display@feb0 {
+   compatible = "renesas,du-r8a7795";
+   reg = <0 0xfeb0 0 0x8>,
+ <0 0xfeb9 0 0x14>;
+   reg-names = "du", "lvds.0";
+   interrupts = ,
+,
+,
+;
+   clocks = < CPG_MOD 724>,
+< CPG_MOD 723>,
+< CPG_MOD 722>,
+< CPG_MOD 721>,
+< CPG_MOD 727>;
+   clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";
+   vsps = < 0>, < 0>, < 0>, < 1>;
 
ports {
#address-cells = <1>;
@@ -89,12 +91,19 @@ Example: R8A7790 (R-Car H2) DU
};
port@1 {
reg = <1>;
-   du_out_lvds0: endpoint {
+   du_out_hdmi0: endpoint {
+   remote-endpoint = <_hdmi0_in>;
};
};
port@2 {
reg = <2>;
-   du_out_lvds1: endpoint {
+   du_out_hdmi1: endpoint {
+   remote-endpoint = <_hdmi1_in>;
+   };
+   };
+   port@3 {
+   reg = <3>;
+   du_out_lvds0: endpoint {
};
};
};
-- 
Regards,

Laurent Pinchart

[PATCH 07/16] drm/rcar-du: Use new iterator macros

[Maarten Lankhorst]

for_each_obj_in_state is about to be removed, so use the correct new
iterator macros.

Signed-off-by: Maarten Lankhorst 
Cc: Laurent Pinchart 
Cc: linux-renesas-soc@vger.kernel.org
---
 drivers/gpu/drm/rcar-du/rcar_du_plane.c | 41 -
 1 file changed, 20 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.c 
b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
index dcde6288da6c..dfd84e3c8c25 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.c
@@ -51,12 +51,9 @@
  */
 
 static bool rcar_du_plane_needs_realloc(struct rcar_du_plane *plane,
+   const struct rcar_du_plane_state 
*cur_state,
struct rcar_du_plane_state *new_state)
 {
-   struct rcar_du_plane_state *cur_state;
-
-   cur_state = to_rcar_plane_state(plane->plane.state);
-
/* Lowering the number of planes doesn't strictly require reallocation
 * as the extra hardware plane will be freed when committing, but doing
 * so could lead to more fragmentation.
@@ -141,16 +138,17 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
unsigned int groups = 0;
unsigned int i;
struct drm_plane *drm_plane;
-   struct drm_plane_state *drm_plane_state;
+   struct drm_plane_state *old_drm_plane_state, *new_drm_plane_state;
 
/* Check if hardware planes need to be reallocated. */
-   for_each_plane_in_state(state, drm_plane, drm_plane_state, i) {
-   struct rcar_du_plane_state *plane_state;
+   for_each_oldnew_plane_in_state(state, drm_plane, old_drm_plane_state, 
new_drm_plane_state, i) {
+   struct rcar_du_plane_state *old_plane_state, *new_plane_state;
struct rcar_du_plane *plane;
unsigned int index;
 
plane = to_rcar_plane(drm_plane);
-   plane_state = to_rcar_plane_state(drm_plane_state);
+   old_plane_state = to_rcar_plane_state(old_drm_plane_state);
+   new_plane_state = to_rcar_plane_state(new_drm_plane_state);
 
dev_dbg(rcdu->dev, "%s: checking plane (%u,%tu)\n", __func__,
plane->group->index, plane - plane->group->planes);
@@ -159,19 +157,19 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
 * the full reallocation procedure. Just mark the hardware
 * plane(s) as freed.
 */
-   if (!plane_state->format) {
+   if (!new_plane_state->format) {
dev_dbg(rcdu->dev, "%s: plane is being disabled\n",
__func__);
index = plane - plane->group->planes;
group_freed_planes[plane->group->index] |= 1 << index;
-   plane_state->hwindex = -1;
+   new_plane_state->hwindex = -1;
continue;
}
 
/* If the plane needs to be reallocated mark it as such, and
 * mark the hardware plane(s) as free.
 */
-   if (rcar_du_plane_needs_realloc(plane, plane_state)) {
+   if (rcar_du_plane_needs_realloc(plane, old_plane_state, 
new_plane_state)) {
dev_dbg(rcdu->dev, "%s: plane needs reallocation\n",
__func__);
groups |= 1 << plane->group->index;
@@ -179,7 +177,7 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
 
index = plane - plane->group->planes;
group_freed_planes[plane->group->index] |= 1 << index;
-   plane_state->hwindex = -1;
+   new_plane_state->hwindex = -1;
}
}
 
@@ -226,16 +224,16 @@ int rcar_du_atomic_check_planes(struct drm_device *dev,
continue;
}
 
-   plane_state = to_rcar_plane_state(plane->plane.state);
+   new_plane_state = 
to_rcar_plane_state(plane->plane.state);
used_planes |= rcar_du_plane_hwmask(plane_state);
 
dev_dbg(rcdu->dev,
"%s: plane (%u,%tu) uses %u hwplanes (index 
%d)\n",
__func__, plane->group->index,
plane - plane->group->planes,
-   plane_state->format ?
-   plane_state->format->planes : 0,
-   plane_state->hwindex);
+   new_plane_state->format ?
+   new_plane_state->format->planes : 0,
+   new_plane_state->hwindex);
}
 

[PATCH] drm: shmobile: checking for NULL instead if IS_ERR()

[Dan Carpenter]

We changed from ioremap_nocache() to devm_ioremap_resource() so the
check needs to be changed from checking for NULL to checking for error
pointers.

Fixes: 16ad3b2ce8dd ("drm/shmobile: Use devm_* managed functions")
Signed-off-by: Dan Carpenter 

diff --git a/drivers/gpu/drm/shmobile/shmob_drm_drv.c 
b/drivers/gpu/drm/shmobile/shmob_drm_drv.c
index 800d1d2c435d..6bd777a3dc17 100644
--- a/drivers/gpu/drm/shmobile/shmob_drm_drv.c
+++ b/drivers/gpu/drm/shmobile/shmob_drm_drv.c
@@ -235,8 +235,8 @@ static int shmob_drm_probe(struct platform_device *pdev)
 
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sdev->mmio = devm_ioremap_resource(>dev, res);
-   if (sdev->mmio == NULL)
-   return -ENOMEM;
+   if (IS_ERR(sdev->mmio))
+   return PTR_ERR(sdev->mmio);
 
ret = shmob_drm_setup_clocks(sdev, pdata->clk_source);
if (ret < 0)

Re: [PATCH v2 3/7] arm64: dts: renesas: r8a7796: Add VSP instances

[Geert Uytterhoeven]

Hi Laurent, Simon,

On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart
 wrote:
> The r8a7796 has 5 VSP instances.
>
> Signed-off-by: Laurent Pinchart 
> Reviewed-by: Geert Uytterhoeven 

Ah, the pitfalls of reposting patches 8 months later...

> ---
>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 50 
> 
>  1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 28b0e2127021..ad9cd1c3199f 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -1447,6 +1447,16 @@
> power-domains = < R8A7796_PD_A3VC>;
> };
>
> +   vspb: vsp@fe96 {
> +   compatible = "renesas,vsp2";
> +   reg = <0 0xfe96 0 0x8000>;
> +   interrupts = ;
> +   clocks = < CPG_MOD 626>;
> +   power-domains = < R8A7796_PD_A3VC>;

... missing resets properties.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH v2 2/7] arm64: dts: renesas: r8a7796: Add FCPF and FCPV instances

[Geert Uytterhoeven]

Hi Laurent, Simon,

On Wed, Jun 21, 2017 at 11:31 AM, Laurent Pinchart
 wrote:
> The FCPs handle the interface between various IP cores and memory. Add
> the instances related to the FDPs and VSP2s.
>
> Signed-off-by: Laurent Pinchart 
> Reviewed-by: Geert Uytterhoeven 

Ah, the pitfalls of reposting patches 8 months later...

>  arch/arm64/boot/dts/renesas/r8a7796.dtsi | 42 
> 
>  1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi 
> b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> index 1f6710912045..28b0e2127021 100644
> --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
> @@ -1440,6 +1440,48 @@
> /* placeholder */
> };
>
> +   fcpf0: fcp@fe95 {
> +   compatible = "renesas,fcpf";
> +   reg = <0 0xfe95 0 0x200>;
> +   clocks = < CPG_MOD 615>;
> +   power-domains = < R8A7796_PD_A3VC>;

... missing resets properties.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH] mmc: tmio-mmc: fix bad pointer math

[Geert Uytterhoeven]

Hi Chris,

On Tue, Jul 11, 2017 at 9:37 PM, Chris Brandt  wrote:
> On Tuesday, July 11, 2017, Geert Uytterhoeven wrote:
>> > zeroing out the bottom 2 bits of count for out math.
>>
>> s/out/our/
>
> Thank you!
>
>> > -   buf8 = (u8 *)(buf + (count >> 2));
>> > +   buf8 = (u8 *)buf + (count & ~3);
>> > count %= 4;
>>
>> While correct, this is IMHO still difficult to understand for the casual
>> reader.
>>
>> Given the code before casts to "u32 *", and uses "count >>2", and the code
>> after also casts to "u32 *", what about getting rid of all casts like:
>>
>> u32 data = 0;
>> u32 *buf32 = buf;
>>
>> if (is_read)
>> sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, buf32,
>>count >> 2);
>> else
>> sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, buf32,
>> count >> 2);
>>
>> /* if count was multiple of 4 */
>> if (!(count & 0x3))
>> return;
>>
>> buf32 += count >> 2;
>> count %= 4;
>>
>> if (is_read) {
>> sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, , 1);
>> memcpy(buf32, , count);
>> } else {
>> memcpy(, buf32, count);
>> sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, , 1);
>> }
>>
>> return;
>> }
>>
>
> Good idea. I just tried it and it seems to work. I'll resend a patch.
>
>
>> u32 *buf32 = buf;
>
> GCC didn't like this line without casting buf to a u32 *. It threw an
> error, not just a warning. Go figure.

Sorry, the cast is indeed missing, as buf is not a void *.

> Question:
>> u32 data = 0;
>
> Any special reason why you are initializing this to 0

I think the original code did that, too. Hmm, I got mislead by the curly braces,
there's no "0" in between them.

It's also a bit safer to not write uninitialized data to the CTL_SD_DATA_PORT
register.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

Re: [PATCH/RFC] gpio: rcar: add gen[123] fallback compatibility strings

[Geert Uytterhoeven]

Hi Simon,

CC DT

On Wed, Jul 12, 2017 at 7:49 AM, Simon Horman  wrote:
> On Tue, Jul 11, 2017 at 07:59:31PM +0200, Geert Uytterhoeven wrote:
>> On Tue, Jul 11, 2017 at 2:38 PM, Simon Horman
>>  wrote:
>> > Add fallback compatibility string for R-Car Gen 1, 2 and 3.
>> >
>> > In the case of Renesas R-Car hardware we know that there are generations of
>> > SoCs, f.e. Gen 1 and 2. But beyond that its not clear what the relationship
>> > between IP blocks might be. For example, I believe that r8a7790 is older
>> > than r8a7791 but that doesn't imply that the latter is a descendant of the
>> > former or vice versa.
>> >
>> > We can, however, by examining the documentation and behaviour of the
>> > hardware at run-time observe that the current driver implementation appears
>> > to be compatible with the IP blocks on SoCs within a given generation.
>> >
>> > For the above reasons and convenience when enabling new SoCs a
>> > per-generation fallback compatibility string scheme being adopted for
>> > drivers for Renesas SoCs.
>> >
>> > Also deprecate renesas,gpio-rcar as its name is more generic than its
>> > implementation.
>> >
>> > Signed-off-by: Simon Horman 
>>
>> Reviewed-by: Geert Uytterhoeven 
>>
>> > ---
>> > Based on linux-gpio/for-next
>> > ---
>> >  .../devicetree/bindings/gpio/renesas,gpio-rcar.txt| 15 
>> > +++
>> >  drivers/gpio/gpio-rcar.c  | 10 ++
>> >  2 files changed, 21 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt 
>> > b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
>> > index 6826a371fb69..48634b01f1bf 100644
>> > --- a/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
>> > +++ b/Documentation/devicetree/bindings/gpio/renesas,gpio-rcar.txt
>> > @@ -2,7 +2,7 @@
>> >
>> >  Required Properties:
>> >
>> > -  - compatible: should contain one of the following.
>> > +  - compatible: should contain one or more of the following:
>> >  - "renesas,gpio-r8a7743": for R8A7743 (RZ/G1M) compatible GPIO 
>> > controller.
>> >  - "renesas,gpio-r8a7778": for R8A7778 (R-Mobile M1) compatible GPIO 
>> > controller.
>> >  - "renesas,gpio-r8a7779": for R8A7779 (R-Car H1) compatible GPIO 
>> > controller.
>> > @@ -13,7 +13,14 @@ Required Properties:
>> >  - "renesas,gpio-r8a7794": for R8A7794 (R-Car E2) compatible GPIO 
>> > controller.
>> >  - "renesas,gpio-r8a7795": for R8A7795 (R-Car H3) compatible GPIO 
>> > controller.
>> >  - "renesas,gpio-r8a7796": for R8A7796 (R-Car M3-W) compatible GPIO 
>> > controller.
>> > -- "renesas,gpio-rcar": for generic R-Car GPIO controller.
>> > +- "renesas,rcar-gen1-gpio": for a generic R-Car Gen1 GPIO controller.
>> > +- "renesas,rcar-gen2-gpio": for a generic R-Car Gen2 or RZ/G1 GPIO 
>> > controller.
>> > +- "renesas,rcar-gen3-gpio": for a generic R-Car Gen3 GPIO controller.
>> > +- "renesas,gpio-rcar": deprecated.
>> > +
>> > +When compatible with the generic version nodes must list the
>> > +SoC-specific version corresponding to the platform first followed by
>> > +the generic version.
>>
>> Besides for consistency, does it make sense to deprecate "renesas,gpio-rcar"
>> (which means R-Car Gen1) and introduce "renesas,rcar-gen1-gpio"?
>> It's not like new R-Car Gen1 SoCs will pop up anytime soon (do we want Linux
>> support for R-Car E1?).
>
> From my PoV the only advantage of that portion of the change is improving
> consistency. Perhaps it would be better to substitute it with something
> like this:
>
> - "renesas,gpio-rcar": for a generic R-Car Gen1 GPIO controller.

That sounds good to me. But other people may disagree.
Oh, no CC to the devicetree folks. Fixed.
Patch at https://patchwork.kernel.org/patch/9834611/

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds