[linux-sunxi] Re: [PATCH v4 0/5] simplefb: add clock handling code
On Sun, Nov 02, 2014 at 10:28:48AM -0500, jonsm...@gmail.com wrote: Simplefb is also being developed as a way of protecting the BIOS setup of the framebuffer past the boot process and out into use as a normal user space console. I in no way support this use. We have experienced decades of problems on the x86 with VGA and BIOSes that I do not wish to repeat in the ARM world. Oh wow. Luc Verhaegen, aka, the guy who made BIOS-free display drivers possible. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [RFC Patch 1/4] mfd: AXP20x: Add power supply bindings documentation
Hi Ezaul, On Tue, 04 November 2014 Ezaul Zillmer ezaulzill...@gmail.com wrote: Cubieboard2 + Kernel 3.18-rc3 [ 15.955655] axp20x-regulator axp20x-regulator: regulators node not found [ 15.962580] LDO1: 1300 mV [ 15.965732] LDO2: at 3000 mV [ 15.969120] LDO3: at 2275 mV [ 15.972314] LDO4: at 2800 mV [ 15.975700] LDO5: at 2800 mV [ 15.979075] DCDC2: at 1400 mV [ 15.982555] DCDC3: at 1250 mV [ 15.985706] axp20x 0-0034: AXP20X driver loaded What was missing for axp20x work of cubieboard2 dt? as poderiar do to run this drive? Not sure what patches, it at all you have on top of 3.18-rc3. As far as I know 3.18 should not have any AXP driver that's not already present in 3.17. The base AXP driver only includes power-off support and bits for regulators while the DT part of regulators is missing (at least for cubietruck). My patches, ideally combined with Carlo's patches from June or so I mentioned in introduction mail would include power supply and input driver for power button. The regulator DT entries are in some other patch (I think Maxime did have them in some of his trees - probably defining them causes too much trouble because all uses are not yet ready to explicitly use them). On DT side, on top of my patches, for cubieboard2 you might need to add the backup battery property if it has such a battery - I don't think the CB2 has a main battery connector but I might be wrong (I only have a cubietruck). Except for that a hwmon driver would be useful to cover some of the last bits of the AXP like temprature sensor and main voltage sensor. With that about all the features should be covered. Bruno -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH 3/6] phy: Add driver to support individual USB PHYs on sun9i
On Wed, Nov 5, 2014 at 1:03 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Tue, Nov 04, 2014 at 12:07:16PM +0800, Chen-Yu Tsai wrote:
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt | 34 +++
drivers/phy/Kconfig| 12 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-sun9i-usb.c| 227
+
4 files changed, 274 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
create mode 100644 drivers/phy/phy-sun9i-usb.c
diff --git a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
new file mode 100644
index 000..27a6067
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
@@ -0,0 +1,34 @@
+Allwinner sun9i USB PHY
+---
+
+Required properties:
+- compatible : should be one of
+ * allwinner,sun9i-a80-usb-phy
+- reg : a list of offset + length pairs
+- #phy-cells : from the generic phy bindings, must be 0
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names :
+ * phy for normal USB
+ * hsic_480M, hsic_12M for HSIC
Do you need all of them? phy and one of the hsic one?
It would be either phy or the hsic ones, depending on the
value of the phy_type property. I will make it clearer.
+- resets : a list of phandle + reset specifier pairs
+- reset-names :
+ * phy for normal USB
+ * hsic for HSIC
+- phy_type : hsic for HSIC usage;
+ other values or absence of this property indicates normal USB
+
+It is recommended to list all clocks and resets available.
+The driver will only use those matching the phy_type.
+
+Example:
+ usbphy1: phy@00a01800 {
+ compatible = allwinner,sun9i-a80-usb-phy;
+ reg = 0x00a01800 0x4;
+ clocks = usb_phy_clk 2, usb_phy_clk 10,
+usb_phy_clk 3;
+ clock-names = hsic_480M, hsic_12M, phy;
+ resets = usb_phy_clk 18, usb_phy_clk 19;
+ reset-names = hsic, phy;
+ status = disabled;
+ #phy-cells = 0;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..f5b7fbb 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -153,6 +153,18 @@ config PHY_SUN4I_USB
This driver controls the entire USB PHY block, both the USB OTG
parts, as well as the 2 regular USB 2 host PHYs.
+config PHY_SUN9I_USB
+ tristate Allwinner sun9i SoC USB PHY driver
+ depends on ARCH_SUNXI HAS_IOMEM OF
+ depends on RESET_CONTROLLER
+ select USB_PHY
+ select GENERIC_PHY
+ help
+ Enable this to support the transceiver that is part of Allwinner
+ sun9i SoCs.
+
+ This driver controls each individual USB 2 host PHY.
+
config PHY_SAMSUNG_USB2
tristate Samsung USB 2.0 PHY driver
depends on HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fc..c3977dc 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA)+= phy-exynos5250-sata.o
obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o
+obj-$(CONFIG_PHY_SUN9I_USB) += phy-sun9i-usb.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y+= phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2)+=
phy-exynos4210-usb2.o
diff --git a/drivers/phy/phy-sun9i-usb.c b/drivers/phy/phy-sun9i-usb.c
new file mode 100644
index 000..f9085d9
--- /dev/null
+++ b/drivers/phy/phy-sun9i-usb.c
@@ -0,0 +1,227 @@
+/*
+ * Allwinner sun9i USB phy driver
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ *
+ * Based on phy-sun9i.c from
I doubt this is the file you were thinking of :)
This is what happens when you do a global replace. :|
+ * Hans de Goede hdego...@redhat.com
+ *
+ * and code from
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public
Re: [linux-sunxi] [PATCH 3/6] phy: Add driver to support individual USB PHYs on sun9i
Hi,
On Tue, Nov 4, 2014 at 2:16 PM, Priit Laes pl...@plaes.org wrote:
On Tue, 2014-11-04 at 12:07 +0800, Chen-Yu Tsai wrote:
Unlike previous Allwinner SoCs, there is no central PHY control block
on the A80. Also, OTG support is completely split off into a
different
controller.
This adds a new driver to support the regular USB PHYs.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
.../devicetree/bindings/phy/sun9i-usb-phy.txt | 34 +++
drivers/phy/Kconfig| 12 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-sun9i-usb.c| 227
+
4 files changed, 274 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/sun9i-usb-
phy.txt
create mode 100644 drivers/phy/phy-sun9i-usb.c
diff --git a/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
new file mode 100644
index 000..27a6067
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt
@@ -0,0 +1,34 @@
+Allwinner sun9i USB PHY
+---
+
+Required properties:
+- compatible : should be one of
+ * allwinner,sun9i-a80-usb-phy
+- reg : a list of offset + length pairs
+- #phy-cells : from the generic phy bindings, must be 0
+- clocks : phandle + clock specifier for the phy clocks
+- clock-names :
+ * phy for normal USB
+ * hsic_480M, hsic_12M for HSIC
+- resets : a list of phandle + reset specifier pairs
+- reset-names :
+ * phy for normal USB
+ * hsic for HSIC
+- phy_type : hsic for HSIC usage;
+ other values or
absence of this property indicates normal USB
+
+It is recommended to list all clocks and resets available.
+The driver will only use those matching the phy_type.
+
+Example:
+ usbphy1: phy@00a01800 {
+ compatible = allwinner,sun9i-a80-usb-phy;
+ reg = 0x00a01800 0x4;
+ clocks = usb_phy_clk 2, usb_phy_clk 10,
+
usb_phy_clk 3;
+ clock-names = hsic_480M, hsic_12M, phy;
+ resets = usb_phy_clk 18, usb_phy_clk 19;
+ reset-names = hsic, phy;
+ status = disabled;
+ #phy-cells = 0;
+ };
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 2a436e6..f5b7fbb 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -153,6 +153,18 @@ config PHY_SUN4I_USB
This driver controls the entire USB PHY
block, both the USB OTG
parts, as well as the 2 regular USB 2 host
PHYs.
+config PHY_SUN9I_USB
+ tristate Allwinner sun9i SoC USB PHY driver
Adding 'A80' to the user visible data makes things a bit easier for
end users:
AllWinner sun9i (A80) SoC USB PHY driver
We explicitly left out A80 from the description of the MACH_SUN9I
Kconfig option. Keeping it the same here.
But I will add a few more patches to this series to enable this
by default in (sunxi and multiv7) defconfigs.
+ depends on ARCH_SUNXI HAS_IOMEM OF
+ depends on RESET_CONTROLLER
+ select USB_PHY
+ select GENERIC_PHY
+ help
+ Enable this to support the transceiver that
is part of Allwinner
+ sun9i SoCs.
And extra 'A80' here wouldn't hurt either.
+
+ This driver controls each individual USB 2
host PHY.
+
config PHY_SAMSUNG_USB2
tristate Samsung USB 2.0 PHY driver
depends on HAS_IOMEM
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c4590fc..c3977dc 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_TWL4030_USB) += phy-
twl4030-usb.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
+obj-$(CONFIG_PHY_SUN9I_USB)+= phy-sun9i-usb.o
obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
phy-exynos-usb2-y += phy-samsung-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-
usb2.o
diff --git a/drivers/phy/phy-sun9i-usb.c b/drivers/phy/phy-sun9i-
usb.c
new file mode 100644
index 000..f9085d9
--- /dev/null
+++ b/drivers/phy/phy-sun9i-usb.c
@@ -0,0 +1,227 @@
+/*
+ * Allwinner sun9i USB phy driver
+ *
+ * Copyright (C) 2014 Chen-Yu Tsai w...@csie.org
+ *
+ * Based on phy-sun9i.c from
+ * Hans de Goede hdego...@redhat.com
+ *
+ * and code from
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License as
published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
[linux-sunxi] Re: [PATCH 1/6] clk: sunxi: Add support for sun9i a80 usb clocks and resets
Hi Russell, On Tue, Nov 04, 2014 at 06:12:19PM +, Russell King - ARM Linux wrote: On Tue, Nov 04, 2014 at 12:07:14PM +0800, Chen-Yu Tsai wrote: + spin_lock_irqsave(data-lock, flags); + + reg = readl(data-reg); + writel(reg ~BIT(id), data-reg); + + spin_unlock_irqrestore(data-lock, flags); Don't we have generic support for atomic modification of register values? Hmm, we have it for ARM only - atomic_io_modify() and atomic_io_modify_relaxed(). I guess we should push for those to become cross-arch if we end up with generic drivers shared between other architectures. IIRC, the atomic MMIO accessors are doing exactly that, but with a global lock for all MMIO accesses, while here we protect a single register. I'm not really sure that sharing this spinlock across the whole system is worth it and scales that well. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [linux-sunxi] [PATCH 3/6] phy: Add driver to support individual USB PHYs on sun9i
On Tue, Nov 04, 2014 at 08:16:13AM +0200, Priit Laes wrote: --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -153,6 +153,18 @@ config PHY_SUN4I_USB This driver controls the entire USB PHY block, both the USB OTG parts, as well as the 2 regular USB 2 host PHYs. +config PHY_SUN9I_USB + tristate Allwinner sun9i SoC USB PHY driver Adding 'A80' to the user visible data makes things a bit easier for end users: AllWinner sun9i (A80) SoC USB PHY driver Until some new SoC part of the sun9i family comes up, and it will just add to the confusion. Plus, who the end user is for a Kconfig file? My guess is that it is a kernel developper, or at least someone with a good kernel experience. Such a person would know that the A80 is part of the sun9i family if it has some knowledge of the Allwinner SocS. And if they don't, A80 or sun9i or both won't make any kind of difference. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [PATCH 1/6] clk: sunxi: Add support for sun9i a80 usb clocks and resets
Hi,
On Wed, Nov 5, 2014 at 12:57 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Tue, Nov 04, 2014 at 12:07:14PM +0800, Chen-Yu Tsai wrote:
The USB controller/phy clocks and reset controls are in a separate
address block, unlike previous SoCs where they were in the clock
controller.
This patch copies the original gates clk functions used for usb
clocks into a separate file, and renames them to *_usb_*. Also
add a per-gate parent index, so we can set different parents for
each gate.
In time we may move the other usb clock drivers to this file.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
Documentation/devicetree/bindings/clock/sunxi.txt | 5 +
drivers/clk/sunxi/Makefile| 1 +
drivers/clk/sunxi/clk-usb.c | 192
++
3 files changed, 198 insertions(+)
create mode 100644 drivers/clk/sunxi/clk-usb.c
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt
b/Documentation/devicetree/bindings/clock/sunxi.txt
index 0455cb9..b953fe5 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -66,6 +66,8 @@ Required properties:
allwinner,sun4i-a10-usb-clk - for usb gates + resets on A10 / A20
allwinner,sun5i-a13-usb-clk - for usb gates + resets on A13
allwinner,sun6i-a31-usb-clk - for usb gates + resets on A31
+ allwinner,sun9i-a80-usb-mod-clk - for usb gates + resets on A80
+ allwinner,sun9i-a80-usb-phy-clk - for usb phy gates + resets on A80
Required properties for all clocks:
- reg : shall be the control register address for the clock.
@@ -82,6 +84,9 @@ Required properties for all clocks:
And allwinner,*-usb-clk clocks also require:
- reset-cells : shall be set to 1
+allwinner,sun9i-a80-usb-*-clk clocks require:
+- clocks : shall be the usb hci ahb1 gate and peripheral pll clocks
+
In this particular order, I assume?
Yes, I will make it clear.
For allwinner,sun7i-a20-gmac-clk, the parent clocks shall be fixed rate
dummy clocks at 25 MHz and 125 MHz, respectively. See example.
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index a66953c..f19ce54 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -8,6 +8,7 @@ obj-y += clk-a20-gmac.o
obj-y += clk-mod0.o
obj-y += clk-sun8i-mbus.o
obj-y += clk-sun9i-core.o
+obj-y += clk-usb.o
obj-$(CONFIG_MFD_SUN6I_PRCM) += \
clk-sun6i-ar100.o clk-sun6i-apb0.o clk-sun6i-apb0-gates.o \
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
new file mode 100644
index 000..d92ee36
--- /dev/null
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2013 Emilio López
+ *
+ * Emilio López emi...@elopez.com.ar
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include linux/clk-provider.h
+#include linux/clkdev.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/reset-controller.h
+#include linux/spinlock.h
+
+
+/**
+ * sunxi_usb_reset... - reset bits in usb clk registers handling
+ */
+
+struct usb_reset_data {
+ void __iomem*reg;
+ spinlock_t *lock;
+ struct reset_controller_dev rcdev;
+};
+
+static int sunxi_usb_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct usb_reset_data *data = container_of(rcdev,
+struct usb_reset_data,
+rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data-lock, flags);
+
+ reg = readl(data-reg);
+ writel(reg ~BIT(id), data-reg);
+
+ spin_unlock_irqrestore(data-lock, flags);
+
+ return 0;
+}
+
+static int sunxi_usb_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct usb_reset_data *data = container_of(rcdev,
+ struct usb_reset_data,
+ rcdev);
+ unsigned long flags;
+ u32 reg;
+
+ spin_lock_irqsave(data-lock, flags);
+
+ reg = readl(data-reg);
+ writel(reg | BIT(id), data-reg);
+
+ spin_unlock_irqrestore(data-lock, flags);
+
+ return 0;
+}
+
+static struct reset_control_ops sunxi_usb_reset_ops = {
+ .assert =
[linux-sunxi] Re: [PATCH 1/6] clk: sunxi: Add support for sun9i a80 usb clocks and resets
On Wed, Nov 05, 2014 at 06:02:35PM +0800, Chen-Yu Tsai wrote:
+static void __init sunxi_usb_clk_setup(struct device_node *node,
+const struct usb_clk_data *data,
+spinlock_t *lock)
+{
+ struct clk_onecell_data *clk_data;
+ struct usb_reset_data *reset_data;
+ const char *clk_parent;
+ const char *clk_name;
+ void __iomem *reg;
+ int qty;
+ int i = 0;
+ int j = 0;
+
+ reg = of_iomap(node, 0);
of_io_request_and_map?
OK. About that, any recommended naming style for the 3rd argument?
Maybe the driver name clk_sun9i_usb? Or just a generic name like
usb_clk?
I'm asking now as we'll likely be changing the existing drivers to
use it as well.
I don't really have a preference. Maybe the DT node name would be both
the easier and better solution.
[...]
+static void __init sun9i_a80_usb_mod_setup(struct device_node *node)
+{
+ /* AHB1 gate must be enabled to access registers */
+ struct clk *ahb = of_clk_get(node, 0);
+
+ WARN_ON(IS_ERR(ahb));
+ clk_prepare_enable(ahb);
H. That look off.
Why do you need the clock to be enabled all the time? Isn't the CCF
already taking care of enabling the parent clock whenever it needs to
access any register?
There are also resets in the same block. That and I couldn't get it
working without enabling the clock beforehand.
Ah, right.
What happens if you just enable and disable the clocks in the
reset_assert and reset_deassert right before and after accessing the
registers?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Description: Digital signature
[linux-sunxi] Re: [PATCH][RFC] Add standalone driver for the A20 Soc TP embedded temperature sensor
clabbe.montjoie wrote: For the temperature value, I cannot found any document on how to transform the raw value in °C. [...] Under heavy loads, the temperature of both sensors rise linearly. But based on a series of tests with and without heatsinks applied to the A20 I came to the conclusion that the values reported here must be already pre-calibrated. The base idle temperatures reported without an applied heatsink are way higher compared to the value of the very same A20 with heatsink: http://forum.lemaker.org/forum.php?mod=redirectgoto=findpostptid=8137pid=40817 Does anyone have a clue how the A20's CHOP_TEMP_EN register (according to the A20's user manual: Chop temperature calibration enable: 0: Disable, 1: Enable) can be read/set? -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [RFC Patch 1/4] mfd: AXP20x: Add power supply bindings documentation
*Hello Bruno Thank you for your attention sought some more docs just applying a patch and here is the result.* *add* *https://dev.openwrt.org/browser/trunk/target/linux/sunxi/patches-3.14/210-mfd-add-axp20x-pmic-driver.patch?rev=42463* *https://dev.openwrt.org/browser/trunk/target/linux/sunxi/patches-3.14/211-input-add-axp20x-power-enable-key-support.patch?rev=42463* *https://dev.openwrt.org/browser/trunk/target/linux/sunxi/patches-3.14/213-dt-sunxi-add-x-powers.patch?rev=42463* *https://dev.openwrt.org/browser/trunk/target/linux/sunxi/patches-3.14/214-1-dt-sun7i-add-axp209-to-cubieboard2.patch?rev=42463* *[ 15.962628] i2c /dev entries driver* *[ 15.975115] input: axp20x-pek as /devices/soc@01c0/1c2ac00.i2c/i2c-0/0-0034/axp20x-pek/input/input0* *[ 15.985426] LDO1: 1300 mV* *[ 15.988789] LDO2: 1800 -- 3300 mV at 3000 mV* *[ 15.993788] LDO3: 700 -- 3500 mV at 2275 mV* *[ 15.998416] LDO4: 1250 -- 3300 mV at 2800 mV* *[ 16.003440] LDO5: 1800 -- 3300 mV at 2800 mV* *[ 16.008406] DCDC2: 700 -- 2275 mV at 1400 mV* *[ 16.013377] DCDC3: 700 -- 3500 mV at 1250 mV* *[ 16.018005] axp20x 0-0034: AXP20X driver loaded* Thank´s -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 1/9] sun6i: Add new p2wi controller driver
Hi,
On 11/03/2014 04:59 PM, Chen-Yu Tsai wrote:
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede hdego...@redhat.com wrote:
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/p2wi.c| 117 +++
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +
arch/arm/include/asm/arch-sunxi/p2wi.h | 140
+
4 files changed, 261 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/p2wi.c
create mode 100644 arch/arm/include/asm/arch-sunxi/p2wi.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 82dbf76..b3a3601 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c
b/arch/arm/cpu/armv7/sunxi/p2wi.c
new file mode 100644
index 000..10df348
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -0,0 +1,117 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl oli...@schinagl.nl
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Berg Xing bergx...@allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/p2wi.h
+#include asm/arch/prcm.h
+#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg
*)SUNXI_P2WI_BASE;
+
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, p2wi-ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ p2wi-cc);
+}
+
+int p2wi_set_pmu_address(u8 slave_addr, u8 ctrl_reg, u8 init_data)
set_pmu_address is actually a misnomer. What it actually does is
write init_data to ctrl_reg on device found at slave_addr,
probably using I2C, with the sole purpose of putting the device
into P2WI mode (or RSB mode for later AXPs).
According to the docs/code we have, it is always writing 0x3e to
register 0x3e.
I've renamed this to p2wi_change_to_p2wi_mode for the next version
of this patch-set.
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg
*)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ p2wi-pm);
+
+ while ((readl(p2wi-pm) P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() tmo)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg
*)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(p2wi-status);
+ if (reg P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, p2wi-status); /* Clear status bits */
+ return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg
*)SUNXI_P2WI_BASE;
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), p2wi-dataddr0);
+
[linux-sunxi] Re: [PATCH 3/6] phy: Add driver to support individual USB PHYs on sun9i
Until some new SoC part of the sun9i family comes up, and it will just add to the confusion. Maybe, but then again maybe not. It depends whether such a new member ever shows up, and whether it has a hardware that's compatible enough that the code doesn't need to be changed (seems unlikely). Such a person would know that the A80 is part of the sun9i family if it has some knowledge of the Allwinner SocS. And if they don't, A80 or sun9i or both won't make any kind of difference. Actually, I'm fairly familiar with Allwinner's family of SoCs, but I kind of lost track of which Ann corresponds to which sunXi. If I got a board, all the documentation would tell me that it's got an A80 on board, but not that it has a sun9i thingy on board. So there's a good chance that a user knows A80 but not sun9i. And last I heard the sunXi designations are a bit unreliable since Allwinner renumbered them differently (is the A20 a sun7i or a sun8i). Stefan -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] Re: [PATCH 3/6] phy: Add driver to support individual USB PHYs on sun9i
Hi Stefan, Please keep me in Cc. On Wed, Nov 05, 2014 at 08:27:41AM -0500, Stefan Monnier wrote: Until some new SoC part of the sun9i family comes up, and it will just add to the confusion. Maybe, but then again maybe not. It depends whether such a new member ever shows up, and whether it has a hardware that's compatible enough that the code doesn't need to be changed (seems unlikely). Yeah, and in all cases, we won't be wrong. While if a new SoCs comes out which is part of the sun9i (let's say A842), you'll have to select an option that states that it is for the A80. The list will be confusing for the user and/or a pain to maintain for us. Such a person would know that the A80 is part of the sun9i family if it has some knowledge of the Allwinner SocS. And if they don't, A80 or sun9i or both won't make any kind of difference. Actually, I'm fairly familiar with Allwinner's family of SoCs, but I kind of lost track of which Ann corresponds to which sunXi. If I got a board, all the documentation would tell me that it's got an A80 on board, but not that it has a sun9i thingy on board. So there's a good chance that a user knows A80 but not sun9i. Good thing we do have a wiki page just for that then. http://linux-sunxi.org/Allwinner_SoC_Family#Comparison_table And last I heard the sunXi designations are a bit unreliable since Allwinner renumbered them differently (is the A20 a sun7i or a sun8i). It might have been both to Allwinner. It's always been sun7i for us. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
[linux-sunxi] Re: [RFC Patch 1/4] mfd: AXP20x: Add power supply bindings documentation
On Tue, Nov 04, 2014 at 10:08:27PM +0100, Bruno Prémont wrote: On Tue, 04 November 2014 Maxime Ripard maxime.rip...@free-electrons.com wrote: On Mon, Nov 03, 2014 at 09:02:44PM +0100, Bruno Prémont wrote: Doing something like this?: --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -126,9 +126,11 @@ interrupt-controller; #interrupt-cells = 1; - backup = 300 200; - battery.resistance = 100; - battery.capacity = 2000; + x-powers,backup = 300 200; I don't really remember what was that property used for. Would it make sense to put it into the battery node? The backup/rtc battery is completely distinct from main battery. It's presence is in no way related to that of the main battery, thus I would not put it into the same node. As all the information needed is included in the property I see no reason to move it into a separate node. Oh. So it is to model some button battery that might be here to keep the RTC state while the board is unpowered? How is that related to the PMIC? Maybe modeling as a fixed regulator would be more accurate. Maxime -- Maxime Ripard, Free Electrons Embedded Linux, Kernel and Android engineering http://free-electrons.com signature.asc Description: Digital signature
Re: [linux-sunxi] [RFC Patch 1/4] mfd: AXP20x: Add power supply bindings documentation
Op 5 nov. 2014, om 15:48 heeft Maxime Ripard maxime.rip...@free-electrons.com het volgende geschreven: On Tue, Nov 04, 2014 at 10:08:27PM +0100, Bruno Prémont wrote: On Tue, 04 November 2014 Maxime Ripard maxime.rip...@free-electrons.com wrote: On Mon, Nov 03, 2014 at 09:02:44PM +0100, Bruno Prémont wrote: Doing something like this?: --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -126,9 +126,11 @@ interrupt-controller; #interrupt-cells = 1; - backup = 300 200; - battery.resistance = 100; - battery.capacity = 2000; + x-powers,backup = 300 200; I don't really remember what was that property used for. Would it make sense to put it into the battery node? The backup/rtc battery is completely distinct from main battery. It's presence is in no way related to that of the main battery, thus I would not put it into the same node. As all the information needed is included in the property I see no reason to move it into a separate node. Oh. So it is to model some button battery that might be here to keep the RTC state while the board is unpowered? How is that related to the PMIC? Some PMICs can recharge it and detect it it's empty or not. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] [PATCH 1/2 3.4] Re-Enable symmetric multiprocessing for sun7i
From: Andreas Baierl ich...@imkreisrum.de Signed-off-by: Andreas Baierl ich...@imkreisrum.de --- arch/arm/configs/sun7i_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/sun7i_defconfig b/arch/arm/configs/sun7i_defconfig index be7fedb..ce17398 100644 --- a/arch/arm/configs/sun7i_defconfig +++ b/arch/arm/configs/sun7i_defconfig @@ -42,9 +42,11 @@ CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_CFQ_GROUP_IOSCHED=y CONFIG_ARCH_SUN7I=y -CONFIG_SWP_EMULATE=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y +CONFIG_SMP=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_NR_CPUS=2 CONFIG_PREEMPT=y CONFIG_AEABI=y CONFIG_HIGHMEM=y -- 2.1.1 -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] [PATCH 4/9] sun6i: Add cpucfg register definitions
Hi,
On 11/03/2014 05:05 PM, Chen-Yu Tsai wrote:
Hi,
On Mon, Nov 3, 2014 at 11:34 PM, Hans de Goede hdego...@redhat.com wrote:
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/include/asm/arch-sunxi/cpu.h| 5 +++
arch/arm/include/asm/arch-sunxi/cpucfg.h | 67
2 files changed, 72 insertions(+)
create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg.h
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 0de79a0..6258cce 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -70,7 +70,9 @@
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
+#ifndef CONFIG_MACH_SUN6I
#define SUNXI_CPUCFG_BASE 0x01c25c00
+#endif
Could we rename it SUN7I_CPUCFG_BASE? Since it is only used on sun7i.
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
@@ -111,6 +113,9 @@
#define SUNXI_AVG_BASE 0x01ea
#define SUNXI_PRCM_BASE0x01f01400
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_CPUCFG_BASE 0x01f01c00
+#endif
And this would be SUN6I_CPUCFG_BASE.
Yes, good idea, done.
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h
b/arch/arm/include/asm/arch-sunxi/cpucfg.h
new file mode 100644
index 000..e2a29cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg.h
sun6i_cpucfg.h?
cpucfg_sun6i.h to be consistent with dram_sun#i.h and clock_sun#i.h,
otherwise a good idea, done.
This might be better, considering the registers are different
for each different SoC.
Cheers
ChenYu
Regards,
Hans
@@ -0,0 +1,67 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#ifndef __ASSEMBLY__
+
+struct sunxi_cpucfg_reg {
+ u8 res0[0x40]; /* 0x000 */
+ u32 cpu0_rst; /* 0x040 */
+ u32 cpu0_ctrl; /* 0x044 */
+ u32 cpu0_status;/* 0x048 */
+ u8 res1[0x34]; /* 0x04c */
+ u32 cpu1_rst; /* 0x080 */
+ u32 cpu1_ctrl; /* 0x084 */
+ u32 cpu1_status;/* 0x088 */
+ u8 res2[0x34]; /* 0x08c */
+ u32 cpu2_rst; /* 0x0c0 */
+ u32 cpu2_ctrl; /* 0x0c4 */
+ u32 cpu2_status;/* 0x0c8 */
+ u8 res3[0x34]; /* 0x0cc */
+ u32 cpu3_rst; /* 0x100 */
+ u32 cpu3_ctrl; /* 0x104 */
+ u32 cpu3_status;/* 0x108 */
+ u8 res4[0x78]; /* 0x10c */
+ u32 gen_ctrl; /* 0x184 */
+ u32 l2_status; /* 0x188 */
+ u8 res5[0x4]; /* 0x18c */
+ u32 event_in; /* 0x190 */
+ u8 res6[0xc]; /* 0x194 */
+ u32 super_standy_flag; /* 0x1a0 */
+ u32 priv0; /* 0x1a4 */
+ u32 priv1; /* 0x1a8 */
+ u8 res7[0x54]; /* 0x1ac */
+ u32 idle_cnt0_low; /* 0x200 */
+ u32 idle_cnt0_high; /* 0x204 */
+ u32 idle_cnt0_ctrl; /* 0x208 */
+ u8 res8[0x4]; /* 0x20c */
+ u32 idle_cnt1_low; /* 0x210 */
+ u32 idle_cnt1_high; /* 0x214 */
+ u32 idle_cnt1_ctrl; /* 0x218 */
+ u8 res9[0x4]; /* 0x21c */
+ u32 idle_cnt2_low; /* 0x220 */
+ u32 idle_cnt2_high; /* 0x224 */
+ u32 idle_cnt2_ctrl; /* 0x228 */
+ u8 res10[0x4]; /* 0x22c */
+ u32 idle_cnt3_low; /* 0x230 */
+ u32 idle_cnt3_high; /* 0x234 */
+ u32 idle_cnt3_ctrl; /* 0x238 */
+ u8 res11[0x4]; /* 0x23c */
+ u32 idle_cnt4_low; /* 0x240 */
+ u32 idle_cnt4_high; /* 0x244 */
+ u32 idle_cnt4_ctrl; /* 0x248 */
+ u8 res12[0x34]; /* 0x24c */
+ u32 cnt64_ctrl; /* 0x280 */
+ u32 cnt64_low; /* 0x284 */
+ u32 cnt64_high; /* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
--
2.1.0
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Re: [linux-sunxi] [PATCH 5/9] sun4i: Rename dram files to dram_sun4i.x
Hi,
On 11/04/2014 05:23 AM, Julian Calaby wrote:
Hi Hans,
On Tue, Nov 4, 2014 at 2:34 AM, Hans de Goede hdego...@redhat.com wrote:
In preparation for adding sun6i dram support.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 6 +-
arch/arm/cpu/armv7/sunxi/dram.c | 750
---
arch/arm/cpu/armv7/sunxi/dram_sun4i.c| 750
+++
arch/arm/include/asm/arch-sunxi/dram.h | 171 +-
arch/arm/include/asm/arch-sunxi/dram_sun4i.h | 182 +++
5 files changed, 941 insertions(+), 918 deletions(-)
delete mode 100644 arch/arm/cpu/armv7/sunxi/dram.c
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun4i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun4i.h
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index 1945f75..9072e68 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -14,172 +14,13 @@
#include linux/types.h
-struct sunxi_dram_reg {
- u32 ccr;/* 0x00 controller configuration register */
- u32 dcr;/* 0x04 dram configuration register */
- u32 iocr; /* 0x08 i/o configuration register */
- u32 csr;/* 0x0c controller status register */
- u32 drr;/* 0x10 dram refresh register */
- u32 tpr0; /* 0x14 dram timing parameters register 0 */
- u32 tpr1; /* 0x18 dram timing parameters register 1 */
- u32 tpr2; /* 0x1c dram timing parameters register 2 */
- u32 gdllcr; /* 0x20 global dll control register */
- u8 res0[0x28];
- u32 rslr0; /* 0x4c rank system latency register */
- u32 rslr1; /* 0x50 rank system latency register */
- u8 res1[0x8];
- u32 rdgr0; /* 0x5c rank dqs gating register */
- u32 rdgr1; /* 0x60 rank dqs gating register */
- u8 res2[0x34];
- u32 odtcr; /* 0x98 odt configuration register */
- u32 dtr0; /* 0x9c data training register 0 */
- u32 dtr1; /* 0xa0 data training register 1 */
- u32 dtar; /* 0xa4 data training address register */
- u32 zqcr0; /* 0xa8 zq control register 0 */
- u32 zqcr1; /* 0xac zq control register 1 */
- u32 zqsr; /* 0xb0 zq status register */
- u32 idcr; /* 0xb4 initializaton delay configure reg */
- u8 res3[0x138];
- u32 mr; /* 0x1f0 mode register */
- u32 emr;/* 0x1f4 extended mode register */
- u32 emr2; /* 0x1f8 extended mode register */
- u32 emr3; /* 0x1fc extended mode register */
- u32 dllctr; /* 0x200 dll control register */
- u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */
- /* 0x208 dll control register 1(byte 1) */
- /* 0x20c dll control register 2(byte 2) */
- /* 0x210 dll control register 3(byte 3) */
- /* 0x214 dll control register 4(byte 4) */
- u32 dqtr0; /* 0x218 dq timing register */
- u32 dqtr1; /* 0x21c dq timing register */
- u32 dqtr2; /* 0x220 dq timing register */
- u32 dqtr3; /* 0x224 dq timing register */
- u32 dqstr; /* 0x228 dqs timing register */
- u32 dqsbtr; /* 0x22c dqsb timing register */
- u32 mcr;/* 0x230 mode configure register */
- u8 res[0x8];
- u32 ppwrsctl; /* 0x23c pad power save control */
- u32 apr;/* 0x240 arbiter period register */
- u32 pldtr; /* 0x244 priority level data threshold reg */
- u8 res5[0x8];
- u32 hpcr[32]; /* 0x250 host port configure register */
- u8 res6[0x10];
- u32 csel; /* 0x2e0 controller select register */
-};
-
-struct dram_para {
- u32 clock;
- u32 mbus_clock;
- u32 type;
- u32 rank_num;
- u32 density;
- u32 io_width;
- u32 bus_width;
- u32 cas;
- u32 zq;
- u32 odt_en;
- u32 size;
- u32 tpr0;
- u32 tpr1;
- u32 tpr2;
- u32 tpr3;
- u32 tpr4;
- u32 tpr5;
- u32 emr1;
- u32 emr2;
- u32 emr3;
- u32 dqs_gating_delay;
- u32 active_windowing;
-};
-
-#define DRAM_CCR_COMMAND_RATE_1T (0x1 5)
-#define DRAM_CCR_DQS_GATE (0x1 14)
-#define DRAM_CCR_DQS_DRIFT_COMP (0x1 17)
-#define DRAM_CCR_ITM_OFF (0x1 28)
-#define DRAM_CCR_DATA_TRAINING (0x1 30)
-#define DRAM_CCR_INIT (0x1 31)
-
-#define DRAM_MEMORY_TYPE_DDR1 1
-#define
[linux-sunxi] [PATCH v2 2/9] sun6i: Add basic axp221 driver
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses the AXP221 pmic for various voltages.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
---
board/sunxi/board.c| 26 +++
drivers/power/Kconfig | 47
drivers/power/Makefile | 1 +
drivers/power/axp221.c | 205 +
include/axp221.h | 42 ++
5 files changed, 321 insertions(+)
create mode 100644 drivers/power/axp221.c
create mode 100644 include/axp221.h
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 8d5d03e..ddb0acd 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -19,6 +19,9 @@
#ifdef CONFIG_AXP209_POWER
#include axp209.h
#endif
+#ifdef CONFIG_AXP221_POWER
+#include axp221.h
+#endif
#include asm/arch/clock.h
#include asm/arch/cpu.h
#include asm/arch/dram.h
@@ -173,6 +176,29 @@ void sunxi_board_init(void)
power_failed |= axp209_set_ldo3(2800);
power_failed |= axp209_set_ldo4(2800);
#endif
+#ifdef CONFIG_AXP221_POWER
+ power_failed = axp221_init();
+ power_failed |= axp221_set_dcdc1(3000);
+ power_failed |= axp221_set_dcdc2(1200);
+ power_failed |= axp221_set_dcdc3(1200);
+ power_failed |= axp221_set_dcdc4(1200);
+ power_failed |= axp221_set_dcdc5(1500);
+#if CONFIG_AXP221_DLDO1_VOLT != -1
+ power_failed |= axp221_set_dldo1(CONFIG_AXP221_DLDO1_VOLT);
+#endif
+#if CONFIG_AXP221_DLDO4_VOLT != -1
+ power_failed |= axp221_set_dldo4(CONFIG_AXP221_DLDO4_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO1_VOLT != -1
+ power_failed |= axp221_set_aldo1(CONFIG_AXP221_ALDO1_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO2_VOLT != -1
+ power_failed |= axp221_set_aldo2(CONFIG_AXP221_ALDO2_VOLT);
+#endif
+#if CONFIG_AXP221_ALDO3_VOLT != -1
+ power_failed |= axp221_set_aldo3(CONFIG_AXP221_ALDO3_VOLT);
+#endif
+#endif
printf(DRAM:);
ramsize = sunxi_dram_init();
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index e69de29..1ec7c0e 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -0,0 +1,47 @@
+config AXP221_POWER
+ boolean axp221 pmic support
+ depends on MACH_SUN6I
+ default y
+ ---help---
+ Say y here to enable support for the axp221 pmic found on most sun6i
+ (A31) boards.
+
+config AXP221_DLDO1_VOLT
+ int axp221 dldo1 voltage
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 dldo1 at, set to -1 to
+ disable dldo1.
+
+config AXP221_DLDO4_VOLT
+ int axp221 dldo4 voltage
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 dldo4 at, set to -1 to
+ disable dldo4.
+
+config AXP221_ALDO1_VOLT
+ int axp221 aldo1 voltage
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo1 at, set to -1 to
+ disable aldo1.
+
+config AXP221_ALDO2_VOLT
+ int axp221 aldo2 voltage
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo2 at, set to -1 to
+ disable aldo2.
+
+config AXP221_ALDO3_VOLT
+ int axp221 aldo3 voltage
+ depends on AXP221_POWER
+ default -1
+ ---help---
+ Set the voltage (mV) to program the axp221 aldo3 at, set to -1 to
+ disable aldo3.
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index dc64e4d..04bd996 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_AXP152_POWER) += axp152.o
obj-$(CONFIG_AXP209_POWER) += axp209.o
+obj-$(CONFIG_AXP221_POWER) += axp221.o
obj-$(CONFIG_EXYNOS_TMU) += exynos-tmu.o
obj-$(CONFIG_FTPMU010_POWER) += ftpmu010.o
obj-$(CONFIG_TPS6586X_POWER) += tps6586x.o
diff --git a/drivers/power/axp221.c b/drivers/power/axp221.c
new file mode 100644
index 000..f4dc72e
--- /dev/null
+++ b/drivers/power/axp221.c
@@ -0,0 +1,205 @@
+/*
+ * (C) Copyright 2013 Oliver Schinagl oli...@schinagl.nl
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/arch/p2wi.h
+#include axp221.h
+
+static u8 axp221_mvolt_to_cfg(int mvolt, int min, int max, int div)
+{
+ if (mvolt min)
+ mvolt = min;
+ else if (mvolt max)
+ mvolt = max;
+
+ return (mvolt - min) / div;
+}
+
+int axp221_set_dcdc1(unsigned int mvolt)
+{
+ int ret;
+ u8 cfg = axp221_mvolt_to_cfg(mvolt, 1600, 3400, 100);
+
+ ret = p2wi_write(AXP221_DCDC1_CTRL, cfg);
+ if (ret)
+ return ret;
+
+ ret = p2wi_read(AXP221_OUTPUT_CTRL2, cfg);
+ if (ret)
+ return ret;
+
+ cfg |= 1 7;
+ return p2wi_write(AXP221_OUTPUT_CTRL2, cfg);
+}
+
+int axp221_set_dcdc2(unsigned int mvolt)
+{
+ u8 cfg =
[linux-sunxi] [PATCH v2 3/9] sun6i: Add clock functions needed for SPL / DRAM init
Add clock_init_safe and clockset_pll5 functions, as these are needed for
SPL support resp. DRAM init (which is needed for SPL too).
Also add some extra clock register constant defines.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/clock_sun6i.c| 77 +++
arch/arm/include/asm/arch-sunxi/clock.h | 1 +
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 27 +-
arch/arm/include/asm/arch-sunxi/prcm.h| 1 +
include/configs/sun6i.h | 1 +
5 files changed, 106 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index 1eae976..16ab6f3 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -16,6 +16,33 @@
#include asm/arch/prcm.h
#include asm/arch/sys_proto.h
+#ifdef CONFIG_SPL_BUILD
+void clock_init_safe(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ struct sunxi_prcm_reg * const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ /* Set PLL ldo voltage without this PLL6 does not work properly */
+ clrsetbits_le32(prcm-pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_KEY);
+ clrsetbits_le32(prcm-pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
+ PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
+ PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
+ clrbits_le32(prcm-pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
+
+ clock_set_pll1(40800);
+
+ writel(AHB1_ABP1_DIV_DEFAULT, ccm-ahb1_apb1_div);
+
+ writel(PLL6_CFG_DEFAULT, ccm-pll6_cfg);
+
+ writel(MBUS_CLK_DEFAULT, ccm-mbus0_clk_cfg);
+ writel(MBUS_CLK_DEFAULT, ccm-mbus1_clk_cfg);
+}
+#endif
+
void clock_init_uart(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -65,6 +92,56 @@ int clock_twi_onoff(int port, int state)
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void clock_set_pll1(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int k = 1;
+ int m = 1;
+
+ if (clk 115200) {
+ k = 2;
+ } else if (clk 76800) {
+ k = 3;
+ m = 2;
+ }
+
+ /* Switch to 24MHz clock while changing PLL1 */
+ writel(AXI_DIV_3 AXI_DIV_SHIFT |
+ ATB_DIV_2 ATB_DIV_SHIFT |
+ CPU_CLK_SRC_OSC24M CPU_CLK_SRC_SHIFT,
+ ccm-cpu_axi_cfg);
+
+ /* PLL1 rate = 2400 * n * k / m */
+ writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
+ CCM_PLL1_CTRL_N(clk / (2400 * k / m)) |
+ CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), ccm-pll1_cfg);
+ sdelay(200);
+
+ /* Switch CPU to PLL1 */
+ writel(AXI_DIV_3 AXI_DIV_SHIFT |
+ ATB_DIV_2 ATB_DIV_SHIFT |
+ CPU_CLK_SRC_PLL1 CPU_CLK_SRC_SHIFT,
+ ccm-cpu_axi_cfg);
+}
+#endif
+
+void clock_set_pll5(unsigned int clk)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int k = 2;
+ const int m = 1;
+
+ /* PLL5 rate = 2400 * n * k / m */
+ writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
+ CCM_PLL5_CTRL_N(clk / (2400 * k / m)) |
+ CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), ccm-pll5_cfg);
+
+ udelay(5500);
+}
+
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
diff --git a/arch/arm/include/asm/arch-sunxi/clock.h
b/arch/arm/include/asm/arch-sunxi/clock.h
index 42382a8..b40c16b 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -25,6 +25,7 @@
int clock_init(void);
int clock_twi_onoff(int port, int state);
void clock_set_pll1(unsigned int hz);
+void clock_set_pll5(unsigned int hz);
unsigned int clock_get_pll5p(void);
unsigned int clock_get_pll6(void);
void clock_init_safe(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 1397b35..4992dbc 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -170,7 +170,17 @@ struct sunxi_ccm_reg {
#define CPU_CLK_SRC_OSC24M 1
#define CPU_CLK_SRC_PLL1 2
-#define PLL1_CFG_DEFAULT 0x90011b21
+#define CCM_PLL1_CTRL_M(n) n) - 1) 0x3) 0)
+#define CCM_PLL1_CTRL_K(n) n) - 1) 0x3) 4)
+#define CCM_PLL1_CTRL_N(n) n) - 1) 0x1f) 8)
+#define CCM_PLL1_CTRL_MAGIC(0x1 16)
+#define CCM_PLL1_CTRL_EN (0x1 31)
+
+#define CCM_PLL5_CTRL_M(n) n) - 1) 0x3) 0)
+#define CCM_PLL5_CTRL_K(n) n) - 1) 0x3) 4)
+#define CCM_PLL5_CTRL_N(n)
[linux-sunxi] [PATCH v2 7/9] sun6i: Poke magic sram controller register to avoid cache issues
Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/board.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 6c812fc..9b3e80c 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
+#if defined CONFIG_SPL_BUILD defined CONFIG_MACH_SUN6I
+ /* Magic (undocmented) value taken from boot0, without this DRAM
+* access gets messed up (seems cache related) */
+ setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
+#endif
#if !defined CONFIG_SPL_BUILD (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
--
2.1.0
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[linux-sunxi] [PATCH v2 4/9] sun6i: Add cpucfg register definitions
Not used atm, for future use (e.g. PSCI).
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/psci.S| 4 +-
arch/arm/include/asm/arch-sunxi/cpu.h | 3 +-
arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h | 67 ++
3 files changed, 71 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
diff --git a/arch/arm/cpu/armv7/sunxi/psci.S b/arch/arm/cpu/armv7/sunxi/psci.S
index 0084c81..b9ea78b 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.S
+++ b/arch/arm/cpu/armv7/sunxi/psci.S
@@ -87,8 +87,8 @@ psci_cpu_on:
str r2, [r0]
dsb
- movwr0, #(SUNXI_CPUCFG_BASE 0x)
- movtr0, #(SUNXI_CPUCFG_BASE 16)
+ movwr0, #(SUN7I_CPUCFG_BASE 0x)
+ movtr0, #(SUN7I_CPUCFG_BASE 16)
@ CPU mask
and r1, r1, #3 @ only care about first cluster
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 0de79a0..d34690e 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -70,7 +70,7 @@
#define SUNXI_TP_BASE 0x01c25000
#define SUNXI_PMU_BASE 0x01c25400
-#define SUNXI_CPUCFG_BASE 0x01c25c00
+#define SUN7I_CPUCFG_BASE 0x01c25c00
#define SUNXI_UART0_BASE 0x01c28000
#define SUNXI_UART1_BASE 0x01c28400
@@ -111,6 +111,7 @@
#define SUNXI_AVG_BASE 0x01ea
#define SUNXI_PRCM_BASE0x01f01400
+#define SUN6I_CPUCFG_BASE 0x01f01c00
#define SUNXI_R_UART_BASE 0x01f02800
#define SUNXI_R_PIO_BASE 0x01f02c00
#define SUNXI_P2WI_BASE0x01f03400
diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
new file mode 100644
index 000..e2a29cb
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpucfg_sun6i.h
@@ -0,0 +1,67 @@
+/*
+ * Sunxi A31 CPUCFG register definition.
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPUCFG_H
+#define _SUNXI_CPUCFG_H
+
+#ifndef __ASSEMBLY__
+
+struct sunxi_cpucfg_reg {
+ u8 res0[0x40]; /* 0x000 */
+ u32 cpu0_rst; /* 0x040 */
+ u32 cpu0_ctrl; /* 0x044 */
+ u32 cpu0_status;/* 0x048 */
+ u8 res1[0x34]; /* 0x04c */
+ u32 cpu1_rst; /* 0x080 */
+ u32 cpu1_ctrl; /* 0x084 */
+ u32 cpu1_status;/* 0x088 */
+ u8 res2[0x34]; /* 0x08c */
+ u32 cpu2_rst; /* 0x0c0 */
+ u32 cpu2_ctrl; /* 0x0c4 */
+ u32 cpu2_status;/* 0x0c8 */
+ u8 res3[0x34]; /* 0x0cc */
+ u32 cpu3_rst; /* 0x100 */
+ u32 cpu3_ctrl; /* 0x104 */
+ u32 cpu3_status;/* 0x108 */
+ u8 res4[0x78]; /* 0x10c */
+ u32 gen_ctrl; /* 0x184 */
+ u32 l2_status; /* 0x188 */
+ u8 res5[0x4]; /* 0x18c */
+ u32 event_in; /* 0x190 */
+ u8 res6[0xc]; /* 0x194 */
+ u32 super_standy_flag; /* 0x1a0 */
+ u32 priv0; /* 0x1a4 */
+ u32 priv1; /* 0x1a8 */
+ u8 res7[0x54]; /* 0x1ac */
+ u32 idle_cnt0_low; /* 0x200 */
+ u32 idle_cnt0_high; /* 0x204 */
+ u32 idle_cnt0_ctrl; /* 0x208 */
+ u8 res8[0x4]; /* 0x20c */
+ u32 idle_cnt1_low; /* 0x210 */
+ u32 idle_cnt1_high; /* 0x214 */
+ u32 idle_cnt1_ctrl; /* 0x218 */
+ u8 res9[0x4]; /* 0x21c */
+ u32 idle_cnt2_low; /* 0x220 */
+ u32 idle_cnt2_high; /* 0x224 */
+ u32 idle_cnt2_ctrl; /* 0x228 */
+ u8 res10[0x4]; /* 0x22c */
+ u32 idle_cnt3_low; /* 0x230 */
+ u32 idle_cnt3_high; /* 0x234 */
+ u32 idle_cnt3_ctrl; /* 0x238 */
+ u8 res11[0x4]; /* 0x23c */
+ u32 idle_cnt4_low; /* 0x240 */
+ u32 idle_cnt4_high; /* 0x244 */
+ u32 idle_cnt4_ctrl; /* 0x248 */
+ u8 res12[0x34]; /* 0x24c */
+ u32 cnt64_ctrl; /* 0x280 */
+ u32 cnt64_low; /* 0x284 */
+ u32 cnt64_high; /* 0x288 */
+};
+
+#endif /* __ASSEMBLY__ */
+#endif /* _SUNXI_CPUCFG_H */
--
2.1.0
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[linux-sunxi] [PATCH v2 6/9] sun6i: Add dram initialization code
Add full support for dram initialization, using a fixed clock and autodetection
of the memory organization (numbers of channels, bus-width, etc.).
This is based on dram_sun6i.c and dram.h from u-boot in the Allwinner A31 SDK,
extended with extra initialization sequences and the autodetect algorithm
from boot0.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile| 1 +
arch/arm/cpu/armv7/sunxi/dram_sun6i.c| 436 +++
arch/arm/include/asm/arch-sunxi/cpu.h| 8 +-
arch/arm/include/asm/arch-sunxi/dram.h | 4 +
arch/arm/include/asm/arch-sunxi/dram_sun6i.h | 359 ++
5 files changed, 805 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/armv7/sunxi/dram_sun6i.c
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun6i.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 48cca0b..3b6ae47 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -30,6 +30,7 @@ endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_MACH_SUN4I) += dram_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o
+obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o
obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o
ifdef CONFIG_SPL_FEL
obj-y += start.o
diff --git a/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
new file mode 100644
index 000..d28a07d
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/dram_sun6i.c
@@ -0,0 +1,436 @@
+/*
+ * Sun6i platform dram controller init.
+ *
+ * (C) Copyright 2007-2012
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Berg Xing bergx...@allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * (C) Copyright 2014 Hans de Goede hdego...@redhat.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/clock.h
+#include asm/arch/dram.h
+#include asm/arch/prcm.h
+
+/* DRAM clk zq defaults, maybe turn these into Kconfig options ? */
+#define DRAM_CLK_DEFAULT 31200
+#define DRAM_ZQ_DEFAULT 0x78
+
+struct dram_sun6i_para
+{
+ u8 bus_width;
+ u8 chan;
+ u8 rank;
+ u8 rows;
+ u16 page_size;
+};
+
+/*
+ * Wait up to 1s for value to be set in given part of reg.
+ */
+static void await_completion(u32 *reg, u32 mask, u32 val)
+{
+ unsigned long tmo = timer_get_us() + 100;
+
+ while ((readl(reg) mask) != val) {
+ if (timer_get_us() tmo)
+ panic(Timeout initialising DRAM\n);
+ }
+}
+
+static void mctl_sys_init(void)
+{
+ struct sunxi_ccm_reg * const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ const int dram_clk_div = 2;
+
+ clock_set_pll5(DRAM_CLK_DEFAULT * dram_clk_div);
+
+ clrsetbits_le32(ccm-dram_clk_cfg, CCM_DRAMCLK_CFG_DIV0_MASK,
+ CCM_DRAMCLK_CFG_DIV0(dram_clk_div) | CCM_DRAMCLK_CFG_RST |
+ CCM_DRAMCLK_CFG_UPD);
+ await_completion(ccm-dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
+
+ writel(MDFS_CLK_DEFAULT, ccm-mdfs_clk_cfg);
+
+ /* deassert mctl reset */
+ setbits_le32(ccm-ahb_reset0_cfg, 1 AHB_RESET_OFFSET_MCTL);
+
+ /* enable mctl clock */
+ setbits_le32(ccm-ahb_gate0, 1 AHB_GATE_OFFSET_MCTL);
+}
+
+static void mctl_dll_init(int ch_index, struct dram_sun6i_para *para)
+{
+ struct sunxi_mctl_phy_reg *mctl_phy;
+
+ if (ch_index == 0)
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
+ else
+ mctl_phy = (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY1_BASE;
+
+ /* disable + reset dlls */
+ writel(MCTL_DLLCR_DISABLE, mctl_phy-acdllcr);
+ writel(MCTL_DLLCR_DISABLE, mctl_phy-dx0dllcr);
+ writel(MCTL_DLLCR_DISABLE, mctl_phy-dx1dllcr);
+ if (para-bus_width == 32) {
+ writel(MCTL_DLLCR_DISABLE, mctl_phy-dx2dllcr);
+ writel(MCTL_DLLCR_DISABLE, mctl_phy-dx3dllcr);
+ }
+ udelay(2);
+
+ /* enable + reset dlls */
+ writel(0, mctl_phy-acdllcr);
+ writel(0, mctl_phy-dx0dllcr);
+ writel(0, mctl_phy-dx1dllcr);
+ if (para-bus_width == 32) {
+ writel(0, mctl_phy-dx2dllcr);
+ writel(0, mctl_phy-dx3dllcr);
+ }
+ udelay(22);
+
+ /* enable and release reset of dlls */
+ writel(MCTL_DLLCR_NRESET, mctl_phy-acdllcr);
+ writel(MCTL_DLLCR_NRESET, mctl_phy-dx0dllcr);
+ writel(MCTL_DLLCR_NRESET, mctl_phy-dx1dllcr);
+ if (para-bus_width == 32) {
+ writel(MCTL_DLLCR_NRESET, mctl_phy-dx2dllcr);
+ writel(MCTL_DLLCR_NRESET, mctl_phy-dx3dllcr);
+ }
+ udelay(22);
+}
+
+static bool mctl_rank_detect(u32 *gsr0, int rank)
+{
+ const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE rank;
+ const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR rank;
+
+ await_completion(gsr0,
[linux-sunxi] [PATCH v2 1/9] sun6i: Add new p2wi controller driver
From: Oliver Schinagl oli...@schinagl.nl
The A31 uses a new push-pull two wire interface, which features higher
transfer speeds (upto 6 MHz) in theory. While the hardware can burst 8
bytes each time, this driver will only see very little use and thus is
limited to single byte transmission only.
Signed-off-by: Oliver Schinagl oli...@schinagl.nl
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/p2wi.c| 117 +++
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +
arch/arm/include/asm/arch-sunxi/p2wi.h | 140 +
4 files changed, 261 insertions(+)
create mode 100644 arch/arm/cpu/armv7/sunxi/p2wi.c
create mode 100644 arch/arm/include/asm/arch-sunxi/p2wi.h
diff --git a/arch/arm/cpu/armv7/sunxi/Makefile
b/arch/arm/cpu/armv7/sunxi/Makefile
index 82dbf76..b3a3601 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,6 +13,7 @@ obj-y += clock.o
obj-y += pinmux.o
obj-$(CONFIG_MACH_SUN6I) += prcm.o
obj-$(CONFIG_MACH_SUN8I) += prcm.o
+obj-$(CONFIG_MACH_SUN6I) += p2wi.o
obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c
new file mode 100644
index 000..8d58955
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/p2wi.c
@@ -0,0 +1,117 @@
+/*
+ * Sunxi A31 Power Management Unit
+ *
+ * (C) Copyright 2013 Oliver Schinagl oli...@schinagl.nl
+ * http://linux-sunxi.org
+ *
+ * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
+ *
+ * (C) Copyright 2006-2013
+ * Allwinner Technology Co., Ltd. www.allwinnertech.com
+ * Berg Xing bergx...@allwinnertech.com
+ * Tom Cubie tangli...@allwinnertech.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include errno.h
+#include asm/io.h
+#include asm/arch/cpu.h
+#include asm/arch/gpio.h
+#include asm/arch/p2wi.h
+#include asm/arch/prcm.h
+#include asm/arch/clock.h
+#include asm/arch/sys_proto.h
+
+void p2wi_init(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+ /* Enable p2wi and PIO clk, and de-assert their resets */
+ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
+
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK);
+ sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA);
+
+ /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
+ writel(P2WI_CTRL_RESET, p2wi-ctrl);
+ sdelay(0x100);
+ writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
+ p2wi-cc);
+}
+
+int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+
+ writel(P2WI_PM_DEV_ADDR(slave_addr) |
+ P2WI_PM_CTRL_ADDR(ctrl_reg) |
+ P2WI_PM_INIT_DATA(init_data) |
+ P2WI_PM_INIT_SEND,
+ p2wi-pm);
+
+ while ((readl(p2wi-pm) P2WI_PM_INIT_SEND)) {
+ if (timer_get_us() tmo)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int p2wi_await_trans(void)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ unsigned long tmo = timer_get_us() + 100;
+ int ret;
+ u8 reg;
+
+ while (1) {
+ reg = readl(p2wi-status);
+ if (reg P2WI_STAT_TRANS_ERR) {
+ ret = -EIO;
+ break;
+ }
+ if (reg P2WI_STAT_TRANS_DONE) {
+ ret = 0;
+ break;
+ }
+ if (timer_get_us() tmo) {
+ ret = -ETIME;
+ break;
+ }
+ }
+ writel(reg, p2wi-status); /* Clear status bits */
+ return ret;
+}
+
+int p2wi_read(const u8 addr, u8 *data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+ int ret;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), p2wi-dataddr0);
+ writel(P2WI_DATA_NUM_BYTES(1) |
+ P2WI_DATA_NUM_BYTES_READ, p2wi-numbytes);
+ writel(P2WI_STAT_TRANS_DONE, p2wi-status);
+ writel(P2WI_CTRL_TRANS_START, p2wi-ctrl);
+
+ ret = p2wi_await_trans();
+
+ *data = readl(p2wi-data0) P2WI_DATA_BYTE_1_MASK;
+ return ret;
+}
+
+int p2wi_write(const u8 addr, u8 data)
+{
+ struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE;
+
+ writel(P2WI_DATADDR_BYTE_1(addr), p2wi-dataddr0);
+ writel(P2WI_DATA_BYTE_1(data), p2wi-data0);
+ writel(P2WI_DATA_NUM_BYTES(1), p2wi-numbytes);
+ writel(P2WI_STAT_TRANS_DONE, p2wi-status);
+
[linux-sunxi] Re: [PATCH 1/6] clk: sunxi: Add support for sun9i a80 usb clocks and resets
On Wed, Nov 5, 2014 at 6:09 PM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Wed, Nov 05, 2014 at 06:02:35PM +0800, Chen-Yu Tsai wrote:
+static void __init sunxi_usb_clk_setup(struct device_node *node,
+const struct usb_clk_data *data,
+spinlock_t *lock)
+{
+ struct clk_onecell_data *clk_data;
+ struct usb_reset_data *reset_data;
+ const char *clk_parent;
+ const char *clk_name;
+ void __iomem *reg;
+ int qty;
+ int i = 0;
+ int j = 0;
+
+ reg = of_iomap(node, 0);
of_io_request_and_map?
OK. About that, any recommended naming style for the 3rd argument?
Maybe the driver name clk_sun9i_usb? Or just a generic name like
usb_clk?
I'm asking now as we'll likely be changing the existing drivers to
use it as well.
I don't really have a preference. Maybe the DT node name would be both
the easier and better solution.
Using of_node_full_name() then.
[...]
+static void __init sun9i_a80_usb_mod_setup(struct device_node *node)
+{
+ /* AHB1 gate must be enabled to access registers */
+ struct clk *ahb = of_clk_get(node, 0);
+
+ WARN_ON(IS_ERR(ahb));
+ clk_prepare_enable(ahb);
H. That look off.
Why do you need the clock to be enabled all the time? Isn't the CCF
already taking care of enabling the parent clock whenever it needs to
access any register?
There are also resets in the same block. That and I couldn't get it
working without enabling the clock beforehand.
Ah, right.
What happens if you just enable and disable the clocks in the
reset_assert and reset_deassert right before and after accessing the
registers?
That doesn't work either. I forgot to mention that most of the clock
gates have the peripheral pll as their parent, not the ahb clock gate.
Since most of the clocks are special clocks @ 12M, 48M, or 480M, which
on previous SoCs were driven by PLL6 or another special PLL, it seems
to make sense to assume the same on A80 and set them this way.
ChenYu
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Re: [linux-sunxi] Re: [PATCH][RFC] Add standalone driver for the A20 Soc TP embedded temperature sensor
Am 05.11.2014 12:44 schrieb thomas.kai...@phg-online.de: clabbe.montjoie wrote: For the temperature value, I cannot found any document on how to transform the raw value in °C. [...] Under heavy loads, the temperature of both sensors rise linearly. But based on a series of tests with and without heatsinks applied to the A20 I came to the conclusion that the values reported here must be already pre-calibrated. The base idle temperatures reported without an applied heatsink are way higher compared to the value of the very same A20 with heatsink: http://forum.lemaker.org/forum.php?mod=redirectgoto=findpostptid=8137pid=40817 Does anyone have a clue how the A20's CHOP_TEMP_EN register (according to the A20's user manual: Chop temperature calibration enable: 0: Disable, 1: Enable) can be read/set? For read write access from user space you can try to use devmem2 with the address given in the user manual. http://manpages.ubuntu.com/manpages/natty/man1/devmem2.1.html Regards, Christian -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [linux-sunxi] A20 Booting without uboot
Hi, Ryong, You can use make menuconfig, and there will be a option of choosing wether to use arguments compiled in kernel, and you can alse specify the arguments to use. I have ever do this some time ago, and it boots correctly. Hope this be of help. Regards 2014-11-05 15:14 GMT+08:00 Ryang HaeDong ryanghaed...@gmail.com: Hi Jhon I used /linux/params file for kernel argument. console=ttyS0,115200 loglevel=9 root=/dev/nandb init=/init Also as you said I tried build a kernel with option Always use the default kernel command string And default kernel command string is equal to contents of params file. Unfortunately boot.axf doesn't load the stripped linux kernel directly. Please refer below log. [ 0.414] recovery key high 40, low 4 [ 0.421] show pic finish [ 0.421] load kernel start [ 0.624] load kernel successed [ 0.624] start address = 0x4a00 [ 0.626] ERR: display driver not open yet [ 0.630] jump to kernel Can you explain about compile a kernel with kernel argument built in? Kind Regards, -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 0/3] ARM: sun8i: Add DMA controller support
On Fri, Sep 26, 2014 at 11:06:01AM +0800, Chen-Yu Tsai wrote: On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote: Hi everyone, This is v2 of my sun8i DMA controller support series. This series adds support for the DMA controller found in the Allwinner A23 SoC. It is the same hardware as found in the A31 (sun6i) SoC. In addition to reduced physical channels and endpoints, the controller in the A23 requires an undocumented register to be toggled. That seems to allow memory bus access. This series is based on my earlier clk: sun6i: Unify AHB1 clock and fix rate calculation series, which removes the clock muxing calls from the sun6i-dma driver. The default PLL6 pre-divider for AHB1 on the A23 results in an exceedingly high clock rate for AHB1, and the system hangs. Also, on the A23, the dma controller happily works even when AHB1 is clocked from AXI. Patch 1 changes the channel count macros into runtime data binded to the DT compatible strings. It also gets rid of some hardcoded values in the interrupt handler. Patch 2 adds the channel number data for the A23 (sun8i), as well as the undocumented register quirk. Hi, Vinod, Any chance we can get patches 1 2 merged? You've already merged the prerequisite patch dmaengine: sun6i: Remove obsolete clk muxing code a few days ago, and patch 3 is already in arm-soc. Hi ChenYu, The patches look fine to me so I tried applying them but they fail to apply, can you please rebase these two and resend Thanks -- ~Vinod -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[linux-sunxi] Re: [PATCH v2 0/3] ARM: sun8i: Add DMA controller support
On Thu, Nov 6, 2014 at 3:11 PM, Vinod Koul vinod.k...@intel.com wrote: On Fri, Sep 26, 2014 at 11:06:01AM +0800, Chen-Yu Tsai wrote: On Thu, Sep 18, 2014 at 11:24 AM, Chen-Yu Tsai w...@csie.org wrote: Hi everyone, This is v2 of my sun8i DMA controller support series. This series adds support for the DMA controller found in the Allwinner A23 SoC. It is the same hardware as found in the A31 (sun6i) SoC. In addition to reduced physical channels and endpoints, the controller in the A23 requires an undocumented register to be toggled. That seems to allow memory bus access. This series is based on my earlier clk: sun6i: Unify AHB1 clock and fix rate calculation series, which removes the clock muxing calls from the sun6i-dma driver. The default PLL6 pre-divider for AHB1 on the A23 results in an exceedingly high clock rate for AHB1, and the system hangs. Also, on the A23, the dma controller happily works even when AHB1 is clocked from AXI. Patch 1 changes the channel count macros into runtime data binded to the DT compatible strings. It also gets rid of some hardcoded values in the interrupt handler. Patch 2 adds the channel number data for the A23 (sun8i), as well as the undocumented register quirk. Hi, Vinod, Any chance we can get patches 1 2 merged? You've already merged the prerequisite patch dmaengine: sun6i: Remove obsolete clk muxing code a few days ago, and patch 3 is already in arm-soc. Hi ChenYu, The patches look fine to me so I tried applying them but they fail to apply, can you please rebase these two and resend Hi Vinod, Could you publish an updated slave-dma/next branch? Currently I see it at v3.18-rc1. And the series rebases cleanly onto it with no differences. I'm guessing some of Maxime's cleanup work is the source of conflict. Thanks ChenYu -- You received this message because you are subscribed to the Google Groups linux-sunxi group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
