[linux-sunxi] Re: Hardware question, FPC connectors.

[Alexis Jeandet]

>
>
> Hi Jon,

As far as I know FPC connectors are single side.

Alexis.
 

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Re: [linux-sunxi] Is it possible to boot the A13 chip without DDR3 RAM?

[Alexis Jeandet]

Hi Rock Slate,

On Sunday, October 4, 2015 at 12:31:50 PM UTC+2, Rock Slate wrote:
>
> Hi Alexis,
>
> I am working on something extremely similar. What are you trying to do 
> with FPGA ? 
>
>
>>>
In my lab we plan to develop a kind of tablet with a A20 and a FPGA. Then 
this tablet would be used for different purposes, the first one is a 
magnetic sniffer with a 20 o 60 MHz ADC. 
The general idea of this project is to have a mobile and re-configurable 
test-bench/Oscilloscope/signal generator for our lab. Today we already have 
a strong background in soc design in FPGA around Gaisler's GRLIB and we 
designed a generic DMA controller for data acquisition. If we find an 
efficient way to connect the FPGA to the CPU this would make a really nice 
tool and the last step would be to make an interface to put ADCs DACs or 
anything you plan to connect to the FPGA inside a module like a game boy.
I got funding for this project and we may start working on it slowly this 
year and more next year.

Alexis.

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Re: [linux-sunxi] Is it possible to boot the A13 chip without DDR3 RAM?

[Alexis Jeandet]

Hi Jon,

On Monday, October 5, 2015 at 12:19:50 AM UTC+2, Jon Smirl wrote:
>
> On Sun, Oct 4, 2015 at 6:14 PM, jons...@gmail.com  <
> jons...@gmail.com > wrote: 
> > On Sun, Oct 4, 2015 at 4:26 AM, Alexis Jeandet  > wrote: 
> >> 
> >> Hi, 
> >> On Saturday, October 3, 2015 at 1:39:55 PM UTC+2, Jon Smirl wrote: 
> >>> 
> >>> On Sat, Oct 3, 2015 at 3:53 AM, Rock Slate  
> wrote: 
> >>> > Wow, that's a really detailed response. Thanks a lot for the 
> pointers. I 
> >>> > will definitely look into this and will let you know as I proceed. 
> >>> 
> >>> On other processors I have seen people attach SRAM to the LCD 
> >>> interface. That technique may be possible on Allwinner but it will 
> >>> need some investigation. 
> >>> 
> >>  I've seen the opposite, I'm interested if you have some links, it 
> would be 
> >> a good point to link FPGA to allwinner devices. 
> > 
> > I believe it works by putting the LCD controller into 8080 mode, then 
> > the LCD interface looks like an ISA bus. Normal SRAM has no problem 
> > attaching to the ISA bus. But I don't know if the Allwinner LCD 
> > controller supports 8080 mode on LCD panels. 
> > 
>
> The A10 says it supports 8080 mode for LCD panels. The display 
> controller section is missing from the A13 manual. 
>
>
In my understanding, the 8080 mode with LCD just uses a data bus and a 
CMD/DATA bit but no address bus. When we connect LCD to a memory controller 
in 8080 mode we connect the CMD/DATA bit to an address bit in order to 
automatically switch between DATA and CMD. It also allow to copy pixel 
buffers directly from RAM to LCD GRAM with DMA.

In this case I don't understand how to handle the SRAM address bus without 
additional logic. I should have missed something.
 
Alexis.

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Re: [linux-sunxi] Is it possible to boot the A13 chip without DDR3 RAM?

[Alexis Jeandet]

Hi,
On Saturday, October 3, 2015 at 1:39:55 PM UTC+2, Jon Smirl wrote:
>
> On Sat, Oct 3, 2015 at 3:53 AM, Rock Slate  > wrote: 
> > Wow, that's a really detailed response. Thanks a lot for the pointers. I 
> > will definitely look into this and will let you know as I proceed. 
>
> On other processors I have seen people attach SRAM to the LCD 
> interface. That technique may be possible on Allwinner but it will 
> need some investigation. 
>
>  I've seen the opposite, I'm interested if you have some links, it would 
be a good point to link FPGA to allwinner devices.

>
> > 
> > On Sat, Oct 3, 2015 at 1:16 PM, Siarhei Siamashka 
> > > wrote: 
> >> 
> >> > On Sat, Oct 3, 2015 at 12:32 PM, Rock Slate  > 
> >> > wrote: 
> >> > 
> >> > > Hi, 
> >> > > 
> >> > > Thanks for the reply. Both yes and no. The A13 comes in a nice 
> >> > > friendly 
> >> > > package which is easy to solder. However the FBGA on the DDR3 is 
> >> > > really a 
> >> > > nightmare. If not placed correctly, I would have to reball the chip 
> >> > > and 
> >> > > this is a little tough to do since I am not sure if I have the 
> right 
> >> > > experience for achieving this. 
> >> > > 
> >> > > However , I have some dedicated code which is really 
> small(something 
> >> > > like 
> >> > > toggling a few pins) to control another interface which I would 
> like 
> >> > > to do 
> >> > > even if the DDR does not work(signal integrity is also a problem , 
> >> > > even if 
> >> > > ODT is present). 
> >> 
> >> The DDR3 signal integrity also depends on the DRAM controller 
> >> configuration. And this configuration is done by software on 
> >> Allwinner A13: http://linux-sunxi.org/DDR_Calibration 
> >> 
> >> > > I dont want to put in another MCU just for this purpose. 
> >> > > 
> >> > > I was wondering if its possible to run the A13 without the DDRAM 
> being 
> >> > > configured. 
> >> 
> >> I have already answered this particular question. Yes, it is possible. 
> >> Your code and data can use a small amount of the on-chip SRAM (48KiB). 
> >> Moreover, that's how the bootloaders normally work. The boot ROM does 
> >> not normally initialize the DRAM on ARM devices, because there are no 
> >> DIMM modules with a nice standardized way to retrieve all the necessary 
> >> DRAM settings (from SPD). Instead the bootloader code does all this 
> >> board-specific configuration job on ARM devices. And bootloaders are 
> >> running in SRAM memory, or at least start executing there. 
> >> 
> >> > > Although I havent read the cortex A8 manual , I am assuming 
> >> > > that UBOOT at some level should be able to achieve what I want. 
> >> 
> >> Just take a look at the SPL part of U-Boot. It gets loaded into the 
> >> SRAM, runs from there, takes care of initializing the DRAM and then 
> >> loads the main part of U-Boot into the DRAM memory. 
> >> 
> >> > > It is also an interesting topic since I dont find many papers 
> >> > > detailing 
> >> > > how to use the ARM without external RAM apart from 
> >> > > http://www.coreboot.org/images/6/6c/LBCar.pdf so that I can use it 
> as 
> >> > > a 
> >> > > microcontroller in the initial stages of development. 
> >> 
> >> Is this paper really about ARM? It looks very much x86 to me. 
> >> 
> >> Please don't confuse the SRAM memory and CPU L1/L2 caches. You can 
> >> already use SRAM easily. It is more than enough for storing your code, 
> >> which is responsible for toggling a few pins. Moreover, if your DRAM 
> >> happens to be broken, guess how the U-Boot bootloader is able to print 
> >> an error message about this mishap on the UART serial console? 
> >> 
> >> As for the L2 cache, it has a much larger size than SRAM, but it is not 
> >> normally designed to be used instead of SRAM and DRAM. There might be a 
> >> way to configure it like this (I did not rule out this possibility 
> yet), 
> >> but the documentation needs to be checked (ARM Architecture Reference 
> >> Manual ARMv7-A and ARMv7-R edition): 
> >> 
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html 
> >> 
> >> -- 
> >> Best regards, 
> >> Siarhei Siamashka 
> > 
> > 
> > -- 
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>
>
>
> -- 
> Jon Smirl 
> jons...@gmail.com  
>

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Re: [linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

On Monday, August 31, 2015 at 9:38:29 PM UTC+2, CodeKipper wrote:
>
> On 31 August 2015 at 08:31, Andrea Venturi  > wrote: 
> > 
> > 
> > Il giorno domenica 30 agosto 2015 13:55:14 UTC+2, Alexis Jeandet ha 
> scritto: 
> >> 
> >> Hi Andrea, 
> >> 
> >> Indeed my song is mono, so that may explain the issue. 
> >> 
> > 
> > ok 
> > 
> >> 
> >> I also continued to investigate the code from Marcus, which if I 
> >> understood correctly, is based on your code. I got some successful 
> results 
> >> also with this code. I think that Marcus wanted to merge the two 
> structures 
> >> sunxi_priv and sunxi_i2s_info and remove the sunxi_iis instance. 
> > 
> > 
> > 
> > yes; the sunxi_iis is a leftover of the original legacy AW driver and 
> the 
> > useful fields should be folded into the "private" data structure of the 
> > relevant  alsa module. 
> > 
> >> 
> >> There is still some points I don't get yet, if I understand correctly 
> the 
> >> UDA is supposed to generate the sysclock with it's own PLL from bclk? 
> > 
> Hi All, 
> I've now joined the working i2s club...managed to get my uda1380 
> singing but there are a few quirks that I will need to look at. For 
> example my audio test file of choice doesn't output audio(it's 
> 44.1KHz) and skips through the file quickly.  If I play a 48KHz file I 
> get audio and then if I go back to the original audio file then it 
> works. It looks like none of the clock divisors are being set up 
> correctly..and I will check the logs tomorrow. I've also been able to 
> play 192KHz files but then if I play them again then it plays slow. 
> BR, 
> CK 
>
I saw this behaviour also, If you play 3 time the same file it will also 
work. First I thought it may come from the uda driver because of i2c 
registers cache but it seems ok. It looks like a problem with the order the 
things are done, maybe some register should be set in a different order on 
i2s side? In more elaborated datasheet you usually get some procedure to 
initialise the device and to configure it. 

> > 
> > IIRC it's a PLL from the "left right" clock (ie frame rate 44.1 or 48 
> KHz) 
> > and the proper UDA register is set when there's WSPLL=1 on device tree.. 
> > 
> >> 
> >> Then you have to set the multiplication factor on the UDA? For each 
> song? 
> > 
> > 
> > for earch sample rate.. 
> > 
> >> 
> >> Or you just set it to 256 or 128fs and then just focus on i2s 
> interface? 
> >> In this case 24 bits resolution wouldn't be possible? 
> > 
> > 
> > the bit clock is a multiple of the FS changing when you have different 
> bit 
> > resolutions. 
> > 
> >> 
> >> Don't understand yet what ALSA does exactly, and I didn't check what is 
> >> done on i2c side. 
> >> 
> >> Best regards, 
> >> Alexis. 
> > 
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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi,

I put this link here, it's a good aditionnal doc for alsa:
http://processors.wiki.ti.com/index.php/AM335x_Audio_Driver's_Guide

I was looking the uda code today and I wonder if the driver doesn't need 
some love also, I'm not totally sure that the I2c reg cache is correctly 
synchronised with the chip register. It may come from my alsa/pulseaudio 
setup but I need to tweak the volume some times and retry several times to 
play a file before I get correctly some sound. It looks like the chip isn't 
correctly configured after boot.

Alexis.
On Monday, August 31, 2015 at 8:31:44 AM UTC+2, Andrea Venturi wrote:
>
>
>
> Il giorno domenica 30 agosto 2015 13:55:14 UTC+2, Alexis Jeandet ha 
> scritto:
>>
>> Hi Andrea,
>>
>> Indeed my song is mono, so that may explain the issue.
>>
>>
> ok
>  
>
>> I also continued to investigate the code from Marcus, which if I 
>> understood correctly, is based on your code. I got some successful results 
>> also with this code. I think that Marcus wanted to merge the two structures 
>> sunxi_priv 
>> and sunxi_i2s_info and remove the sunxi_iis instance. 
>>
>
>
> yes; the sunxi_iis is a leftover of the original legacy AW driver and the 
> useful fields should be folded into the "private" data structure of the 
> relevant  alsa module.
>
I did this, and seems to work, sent this modifications to Marcus. 

>
>
>> There is still some points I don't get yet, if I understand correctly the 
>> UDA is supposed to generate the sysclock with it's own PLL from bclk? 
>>
>
> IIRC it's a PLL from the "left right" clock (ie frame rate 44.1 or 48 KHz) 
> and the proper UDA register is set when there's WSPLL=1 on device tree..
>
Yes I saw that, thanks for the clarification. 

>  
>
>> Then you have to set the multiplication factor on the UDA? For each song? 
>>
>
> for earch sample rate.. 
>  
>
>> Or you just set it to 256 or 128fs and then just focus on i2s interface? 
>> In this case 24 bits resolution wouldn't be possible? 
>>
>
> the bit clock is a multiple of the FS changing when you have different bit 
> resolutions.
>  
>
>> Don't understand yet what ALSA does exactly, and I didn't check what is 
>> done on i2c side.
>>
>> Best regards,
>> Alexis.
>>
>

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi Andrea,

Indeed my song is mono, so that may explain the issue.

I also continued to investigate the code from Marcus, which if I understood 
correctly, is based on your code. I got some successful results also with 
this code. I think that Marcus wanted to merge the two structures sunxi_priv 
and sunxi_i2s_info and remove the sunxi_iis instance. 

There is still some points I don't get yet, if I understand correctly the 
UDA is supposed to generate the sysclock with it's own PLL from bclk? Then 
you have to set the multiplication factor on the UDA? For each song? Or you 
just set it to 256 or 128fs and then just focus on i2s interface? In this 
case 24 bits resolution wouldn't be possible? Don't understand yet what 
ALSA does exactly, and I didn't check what is done on i2c side.

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi Andrea,

Good news! I can hear some sounds :). After some discussions with Marcus 
I've checked I2S pins with logic analyser, the data where at the output but 
really fast (340kS/s). I decided to replace the I2S driver from Marcus 
 repo  with your code(only 
sunxi-i2s.c plus sunxi.h). At least I can hear sound, it still refuse to 
play 32 bits wave file(with aply) and my sample is read at twice the 
speed(looks like mickey mouse) but it works! With the sample you provided 
it works at nominal speed, I think(not easy to say).
If you are interested here are the screenshots of what I saw with Marcus 
patch:
https://www.dropbox.com/s/t2cn38hl5aywwiz/Capture%20d%27%C3%A9cran%20de%202015-08-27%2014-18-08.png?dl=0

As a conclusion, on Marcus repo I2C works but something broke on I2S code.

Best regards,
Alexis.

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Re: [linux-sunxi] A20 touchscreen controller with mainline kernel?

[Alexis Jeandet]

One other mistake I did, the kernel need Event interface in input section, 
it wasn't enabled.

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Re: [linux-sunxi] A20 touchscreen controller with mainline kernel?

[Alexis Jeandet]

Hi Hans,

Thanks for your answer, I saw this after, it wasn't clear to me since no 
dts file use it. I will use it with TS from olimex which is resistive.
Once again I'm really impressed by the sunxi mainlining effort, it's far 
better than exynos chips...

Best regards,
Alexis.

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[linux-sunxi] A20 touchscreen controller with mainline kernel?

[Alexis Jeandet]

Hi,

I saw in drivers/input/touchscreen/sun4i-ts.c that A20 have a similar TC 
controller but at the end:
===
static const struct of_device_id sun4i_ts_of_match[] = {
{ .compatible = "allwinner,sun4i-a10-ts", },
{ .compatible = "allwinner,sun5i-a13-ts", },
{ .compatible = "allwinner,sun6i-a31-ts", },
{ /* sentinel */ }
};
===
Does that means that I can't load it on A20, is there any hack to use it on 
A20, then is there any dts entry to add, I'm quite lost?

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi Andrea,

I got slightly better results, I played with alsa and some GUI mixers like 
qashctl over ssh, now I can hear a click when playing a sound but, still no 
sound.

I also noticed that a 3 minutes sound is played in 5 seconds, here is my 
asound.conf to get the default output on sunxii2sdaiuda1:
=
pcm.!default {
type hw
card 1
device 0
}

ctl.!default {
type hw   
card 1
}


aplay also complains about 32 bits wav files, it says that this device is 
only compatible with 16bits signed data.
Have you seen similar behaviour?

Then last question, do you know if GUI mixers like qashctl read the dac 
config? If yes i means that the volume control works on my side. Anyway I 
can hear some clik in the headphone when playing with some parameters on 
qashctl.

Best reagards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Ok thanks for your answer, I don't any screen yet(I'm still waiting for the 
lime LCD ribbon) so I will play with alsa mixer later. For now I think it 
may be interesting to play in userspace with i2c and try to speak with the 
UDA, at least to see if it behaves as expected.

I also have a DSLogic analyser, if you need some captures, just tell me.

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Now I2C works :), I can see 2 sound cards in /proc/asound,
Here is the output of  sudo aplay -l :
 List of PLAYBACK Hardware Devices 
card 0: sunxicodec [sunxi-codec], device 0: CDC PCM Codec-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0
card 1: sunxii2sdaiuda1 [sunxi-i2s-dai-uda1380-hifi], device 0: sunxi
-i2s-dai-uda1380-hifi uda1380-hifi-0 []
  Subdevices: 1/1
  Subdevice #0: subdevice #0

I use this to switch from card 0 to 1
sudo  amixer -c 1 -- sset Master Playback 0dB

I play with this:
sudo aplay -vv someWaveFile.wav

But I still don't get any sound, any hint?

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi,

I did the connections today, it doesn't work yet here is the kernel output:

[1.603394] asoc-simple-card sound: uda1380-hifi <-> 1c22400.i2s mapping 
ok
[1.610467] uda1380-codec 1-0018: ASoC: mux Capture Mux has no paths
[1.616961] uda1380-codec 1-0018: ASoC: Failed to create Playback 
debugfs file
[1.624212] uda1380-codec 1-0018: ASoC: Failed to create Capture debugfs 
file
[1.631831] uda1380-codec 1-0018: uda1380_sync_cache: write to reg 0x1 
failed
[1.639054] uda1380-codec 1-0018: uda1380_sync_cache: write to reg 0x2 
failed
[1.646291] i2c i2c-1: mv64xxx_i2c_fsm: Ctlr Error -- state: 0x6, 
status: 0x38, addr: 0x18, flags: 0x0
[1.651912] ata1: SATA link down (SStatus 0 SControl 300)
[1.660989] uda1380-codec 1-0018: uda1380_sync_cache: write to reg 0x3 
failed
[1.681903] usb 1-1: new high-speed USB device number 2 using 
ehci-platform
[3.191912] cfg80211: Calling CRDA to update world regulatory domain
[3.661900] i2c i2c-1: mv64xxx: I2C bus locked, block: 1, time_left: 0
[3.668428] uda1380-codec 1-0018: uda1380_sync_cache: write to reg 0x4 
failed

looks like an i2c connection problem, my pinout is this one:
A20 Side|   UDA side
PB5 I2S0_MCLK  -> TXMCLK
PB6 I2S0_BCLK   -> TXCLK
PB7 I2S0_LRCK   -> TXWS
PB8 I2S0_D0   -> TXDA
PB12  I2S0_DI -> RXDA

PB18 I2C1_SCK -> SCL
PB19 I2C1_SDA-> SDA

I will try to look more in details tomorrow.

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

Hi Andrea, 

Thank you for your answer, I also got one from code keeper with a link to 
his git repo here. 

After some tweaks(uboot scripts and kernel config for systemd) I 
successfully booted his kernel.
Now I need to do some soldering to connect the uda board to the lime2, I 
will do that tomorrow and give some results.

Best regards,
Alexis.

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[linux-sunxi] Re: A20 mainline kernel questions

[Alexis Jeandet]

I received one answer by mail, init of lcd screen is done by u-boot, I 
found useful informations by looking in u-boot/configs/ folder and with 
some grep and looking tablets defconfig files. At least it works on my 
"no-name" a20 tablet I will try later on lime2, I didn't received the lcd 
cable yet.

useful options for lcd(in my case):
CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:18,pclk_khz:33000,le:45,ri:209,up:22,lo:22,hs:1,vs:1,sync:3,vmode:0"
CONFIG_VIDEO_LCD_POWER="PH8"
CONFIG_VIDEO_LCD_BL_EN="PH7"
CONFIG_VIDEO_LCD_BL_PWM="PB2"

Alexis.

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[linux-sunxi] A20 mainline kernel questions

[Alexis Jeandet]

Hi,

I wonder if I can and how to use a olinuxino lime 2 on LCD(via LVDS) with 
mainline kernel. I'm using fedora since it shows a good upstream policy(I 
feel) and I use it everywhere.
>From what I understand, for now u-boot is supposed to init the screen and 
then kernel just use simple-fb, is it correct? I just need to search on 
uboot side how to switch from hdmi to LCD?

Then would a UDA1380 work? I need to add sound. What I saw is that UDA 
driver exist but needs i2c bus so i need to tweak the dts file for lime2. 
Does somebody have some lights to give me on this topic?

I got really impress by the huge upstream effort done by the sunxi 
community! It's really nice to be able to boot a standard distrib and do 
kernel updates transparently, the graphic boot loader was also a big 
surprise for me!

Best regards,
Alexis.

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[linux-sunxi] Re: New firmware for GSL1680

[Alexis Jeandet]

Hi,

You can do it with readelf and dd, it's not straight forward, you need to 
find the symbol offset(table offset + symbol ofset) and size in the file 
then you dump it with dd.
I made a graphical tool to make this easier:
https://hephaistos.lpp.polytechnique.fr/redmine/projects/execut/wiki
You have the choice between sources, rpm for fedora and static Win32 exe.

Best regards,
Alexis.
On Monday, May 18, 2015 at 3:31:00 AM UTC+2, sergk...@gmail.com wrote:
>
> Hello.
>
> Could anyone share or describe the way how to extract it firmware for 
> GSL1680 on 8" with 800x1280?
>
> What I have - rooted Android and binaries of kenel module (driver) fw is 
> inside.
> Also I have original fw from Windows 8.1.
>
> More technical details for Linux Guru: I need assistance of extracting 
> from ELFfile .data segment declared their static (constant) values.
>
> Look at the objdump
>
> objdump -t gslx68x_ts.ko  | grep gsl_config
> 0140 g O .data035c gsl_config_data_id_gsl_customer
> 54a0 g O .data0800 
> gsl_config_data_id_I81_GSL3676B_8001280_OGS_SG
> 5ca0 g O .data0800 
> gsl_config_data_id_I802_GSL3676B_8001280_OGS_SG
> 64a0 g O .data0800 
> gsl_config_data_id_I802_GSL3676B_8001280_OGS_DZ
> 4ca0 g O .data0800 
> gsl_config_data_id_I100_GSL3692_1280800_GG_SG
> 44a0 g O .data0800 
> gsl_config_data_id_I89_GSL3676B_19201200_OGS_SG
> 34a0 g O .data0800 
> gsl_config_data_id_I71_GSL1686F_1024600_PG_XLL
> 24a0 g O .data0800 
> gsl_config_data_id_I86_GSL3676B_8001280_PG_FC
> 1ca0 g O .data0800 
> gsl_config_data_id_I86_GSL3676B_8001280_OGS_SG
> 2ca0 g O .data0800 
> gsl_config_data_id_I706_GSL1686_OGS_6001024_DZ_70F2
> 3ca0 g O .data0800 
> gsl_config_data_id_I89_GSL3676B_19201200_OGS_DZ
> 0ca0 g O .data0800 
> gsl_config_data_id_I101_GSL3692_1280800_GG_FC_FC101S123
> 14a0 g O .data0800 
> gsl_config_data_id_I86_GSL3676B_8001280_PG_FC_W
> 04a0 g O .data0800 
> gsl_config_data_id_I892_GSL3676B_8001280_OGS_SG
>
> objdump -x gslx68x_ts.ko | grep .data
>
> I am attaching linux driver module to this message. If it is needed 
> windows fw file - please let me know - I will send it too.
> PS: Suppose this helps to have more fw for new screen!
> RELOCATION RECORDS FOR [.data]:
> 0040 R_386_32  gsl_config_data_id_gsl_customer
> 0044 R_386_32  gsl_config_data_id_I81_GSL3676B_8001280_OGS_SG
> 0048 R_386_32  gsl_config_data_id_I802_GSL3676B_8001280_OGS_SG
> 004c R_386_32  gsl_config_data_id_I802_GSL3676B_8001280_OGS_DZ
> 0050 R_386_32  gsl_config_data_id_I100_GSL3692_1280800_GG_SG
> 0054 R_386_32  gsl_config_data_id_I89_GSL3676B_19201200_OGS_SG
> 0058 R_386_32  gsl_config_data_id_I71_GSL1686F_1024600_PG_XLL
> 005c R_386_32  gsl_config_data_id_I86_GSL3676B_8001280_PG_FC
> 0060 R_386_32  gsl_config_data_id_I86_GSL3676B_8001280_OGS_SG
> 0064 R_386_32  
> gsl_config_data_id_I706_GSL1686_OGS_6001024_DZ_70F2
> 0068 R_386_32  gsl_config_data_id_I89_GSL3676B_19201200_OGS_DZ
> 006c R_386_32  
> gsl_config_data_id_I101_GSL3692_1280800_GG_FC_FC101S123
> 0070 R_386_32  gsl_config_data_id_I86_GSL3676B_8001280_PG_FC_W
> 0074 R_386_32  gsl_config_data_id_I892_GSL3676B_8001280_OGS_SG
>
> Kind regards,
>   Serge Kolotylo.
>
>
>

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[linux-sunxi] Tool for elf files exploration

[Alexis Jeandet]

Hi,

I made a free(GPL) graphical tool to view and extract symbols or sections 
of an elf file. It may be useful for android firmware extraction(from 
kernel drivers) and other stuff. I hope it would help somebody. Feedback 
and contribution are welcome.

https://hephaistos.lpp.polytechnique.fr/redmine/projects/execut/wiki/Wiki

best regards,
Alexis.

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Re: [linux-sunxi] Device list contribution procedure

[Alexis Jeandet]

 Ok thank, I didn't find this page, I will try to do as much as I can, I'm 
actually trying to find a good kernel config, to get as much
 devices working as I can, in parallel I will try to fill a new Wiki entry 
for this device.

best regards,
Alexis. 

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[linux-sunxi] Device list contribution procedure

[Alexis Jeandet]

Hello everybody,

I bought an A20 tablet which doesn't seems to be listed in the wiki device 
list, I would be happy to contribute in any way to provide all the 
information about it, I took some PCB pictures, I started to list all the 
chip inside. 
At this point I can boot linux on it thank to Olimex OlinuXino-A20 image, 
I've started to extract android initialization info from the nanda.

The PCB is tagged as A70X1_V2.

What is the procedure to update the Wiki, who should I contact to give all 
the pictures, and others information? If you are interested.

Best regards,
Alexis.

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