[PATCH REPOST v5 2/3] powernv, cpufreq: cpufreq driver for powernv platform
From: Vaidyanathan Srinivasan sva...@linux.vnet.ibm.com Backend driver to dynamically set voltage and frequency on IBM POWER non-virtualized platforms. Power management SPRs are used to set the required PState. This driver works in conjunction with cpufreq governors like 'ondemand' to provide a demand based frequency and voltage setting on IBM POWER non-virtualized platforms. PState table is obtained from OPAL v3 firmware through device tree. powernv_cpufreq back-end driver would parse the relevant device-tree nodes and initialise the cpufreq subsystem on powernv platform. The code was originally written by sva...@linux.vnet.ibm.com. Over time it was modified to accomodate bug-fixes as well as updates to the the cpu-freq core. Relevant portions of the change logs corresponding to those modifications are noted below: * The policy-cpus needs to be populated in a hotplug-invariant manner instead of using cpu_sibling_mask() which varies with cpu-hotplug. This is because the cpufreq core code copies this content into policy-related_cpus mask which should not vary on cpu-hotplug. [Authored by srivatsa.b...@linux.vnet.ibm.com] * Create a helper routine that can return the cpu-frequency for the corresponding pstate_id. Also, cache the values of the pstate_max, pstate_min and pstate_nominal and nr_pstates in a static structure so that they can be reused in the future to perform any validations. [Authored by e...@linux.vnet.ibm.com] * Create a driver attribute named cpuinfo_nominal_freq which creates a sysfs read-only file named cpuinfo_nominal_freq. Export the frequency corresponding to the nominal_pstate through this interface. Nominal frequency is the highest non-turbo frequency for the platform. This is generally used for setting governor policies from user space for optimal energy efficiency. [Authored by e...@linux.vnet.ibm.com] * Implement a powernv_cpufreq_get(unsigned int cpu) method which will return the current operating frequency. Export this via the sysfs interface cpuinfo_cur_freq by setting powernv_cpufreq_driver.get to powernv_cpufreq_get(). [Authored by e...@linux.vnet.ibm.com] [Change log updated by e...@linux.vnet.ibm.com] Reviewed-by: Preeti U Murthy pre...@linux.vnet.ibm.com Signed-off-by: Vaidyanathan Srinivasan sva...@linux.vnet.ibm.com Signed-off-by: Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com Signed-off-by: Anton Blanchard an...@samba.org Signed-off-by: Gautham R. Shenoy e...@linux.vnet.ibm.com --- arch/powerpc/include/asm/reg.h| 4 + drivers/cpufreq/Kconfig.powerpc | 8 + drivers/cpufreq/Makefile | 1 + drivers/cpufreq/powernv-cpufreq.c | 342 ++ 4 files changed, 355 insertions(+) create mode 100644 drivers/cpufreq/powernv-cpufreq.c diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 1a36b8e..2189f8f 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -271,6 +271,10 @@ #define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */ #define SPRN_IC0x350 /* Virtual Instruction Count */ #define SPRN_VTB 0x351 /* Virtual Time Base */ +#define SPRN_PMICR 0x354 /* Power Management Idle Control Reg */ +#define SPRN_PMSR 0x355 /* Power Management Status Reg */ +#define SPRN_PMCR 0x374 /* Power Management Control Register */ + /* HFSCR and FSCR bit numbers are the same */ #define FSCR_TAR_LG8 /* Enable Target Address Register */ #define FSCR_EBB_LG7 /* Enable Event Based Branching */ diff --git a/drivers/cpufreq/Kconfig.powerpc b/drivers/cpufreq/Kconfig.powerpc index ca0021a..72564b7 100644 --- a/drivers/cpufreq/Kconfig.powerpc +++ b/drivers/cpufreq/Kconfig.powerpc @@ -54,3 +54,11 @@ config PPC_PASEMI_CPUFREQ help This adds the support for frequency switching on PA Semi PWRficient processors. + +config POWERNV_CPUFREQ + tristate CPU frequency scaling for IBM POWERNV platform + depends on PPC_POWERNV + default y + help +This adds support for CPU frequency switching on IBM POWERNV +platform diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile index 7494565..0dbb963 100644 --- a/drivers/cpufreq/Makefile +++ b/drivers/cpufreq/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_PPC_CORENET_CPUFREQ) += ppc-corenet-cpufreq.o obj-$(CONFIG_CPU_FREQ_PMAC)+= pmac32-cpufreq.o obj-$(CONFIG_CPU_FREQ_PMAC64) += pmac64-cpufreq.o obj-$(CONFIG_PPC_PASEMI_CPUFREQ) += pasemi-cpufreq.o +obj-$(CONFIG_POWERNV_CPUFREQ) += powernv-cpufreq.o ## # Other platform drivers diff --git a/drivers/cpufreq/powernv-cpufreq.c b/drivers/cpufreq/powernv-cpufreq.c new file mode 100644 index 000..e1e5197 --- /dev/null +++ b/drivers/cpufreq/powernv-cpufreq.c @@ -0,0 +1,342 @@
[PATCH REPOST v5 3/3] powernv, cpufreq: Use cpufreq_frequency_table.driver_data to store pstate ids
From: Gautham R. Shenoy e...@linux.vnet.ibm.com
The .driver_data field in the cpufreq_frequency_table was supposed to
be private to the drivers. However at some later point, it was being
used to indicate if the particular frequency in the table is the
BOOST_FREQUENCY. After patches [1] and [2], the .driver_data is once
again private to the driver. Thus we can safely use
cpufreq_frequency_table.driver_data to store pstate_ids instead of
having to maintain a separate array powernv_pstate_ids[] for this
purpose.
[1]:
Subject: cpufreq: don't print value of .driver_data from core
From : Viresh Kumar viresh.kumar@ linaro.org
url: http://marc.info/?l=linux-pmm=139601421504709w=2
[2]:
Subject: cpufreq: create another field .flags in cpufreq_frequency_table
From : Viresh Kumar viresh.ku...@linaro.org
url: http://marc.info/?l=linux-pmm=139601416804702w=2
Signed-off-by: Gautham R. Shenoy e...@linux.vnet.ibm.com
---
drivers/cpufreq/powernv-cpufreq.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/cpufreq/powernv-cpufreq.c
b/drivers/cpufreq/powernv-cpufreq.c
index e1e5197..9edccc6 100644
--- a/drivers/cpufreq/powernv-cpufreq.c
+++ b/drivers/cpufreq/powernv-cpufreq.c
@@ -33,7 +33,6 @@
#define POWERNV_MAX_PSTATES256
static struct cpufreq_frequency_table powernv_freqs[POWERNV_MAX_PSTATES+1];
-static int powernv_pstate_ids[POWERNV_MAX_PSTATES+1];
/*
* Note: The set of pstates consists of contiguous integers, the
@@ -112,7 +111,7 @@ static int init_powernv_pstates(void)
pr_debug(PState id %d freq %d MHz\n, id, freq);
powernv_freqs[i].frequency = freq * 1000; /* kHz */
- powernv_pstate_ids[i] = id;
+ powernv_freqs[i].driver_data = id;
}
/* End of list marker entry */
powernv_freqs[i].frequency = CPUFREQ_TABLE_END;
@@ -283,7 +282,7 @@ static int powernv_cpufreq_target_index(struct
cpufreq_policy *policy,
{
struct powernv_smp_call_data freq_data;
- freq_data.pstate_id = powernv_pstate_ids[new_index];
+ freq_data.pstate_id = powernv_freqs[new_index].driver_data;
/*
* Use smp_call_function to send IPI and execute the
--
1.8.3.1
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[PATCH REPOST v5 1/3] powernv, cpufreq: Select CPUFreq related Kconfig options for powernv
From: Gautham R. Shenoy e...@linux.vnet.ibm.com Enable CPUFreq for PowerNV. Select performance, powersave, userspace and ondemand governors. Choose ondemand to be the default governor. Signed-off-by: Gautham R. Shenoy e...@linux.vnet.ibm.com Signed-off-by: Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com --- arch/powerpc/configs/pseries_defconfig| 1 + arch/powerpc/configs/pseries_le_defconfig | 1 + arch/powerpc/platforms/powernv/Kconfig| 6 ++ 3 files changed, 8 insertions(+) diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 9ea8342b..a905063 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -306,3 +306,4 @@ CONFIG_KVM_BOOK3S_64=m CONFIG_KVM_BOOK3S_64_HV=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y diff --git a/arch/powerpc/configs/pseries_le_defconfig b/arch/powerpc/configs/pseries_le_defconfig index 3c84f9d..58e3dbf 100644 --- a/arch/powerpc/configs/pseries_le_defconfig +++ b/arch/powerpc/configs/pseries_le_defconfig @@ -301,3 +301,4 @@ CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_NX=y CONFIG_CRYPTO_DEV_NX_ENCRYPT=m +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig index 895e8a2..c252ee9 100644 --- a/arch/powerpc/platforms/powernv/Kconfig +++ b/arch/powerpc/platforms/powernv/Kconfig @@ -11,6 +11,12 @@ config PPC_POWERNV select PPC_UDBG_16550 select PPC_SCOM select ARCH_RANDOM + select CPU_FREQ + select CPU_FREQ_GOV_PERFORMANCE + select CPU_FREQ_GOV_POWERSAVE + select CPU_FREQ_GOV_USERSPACE + select CPU_FREQ_GOV_ONDEMAND + select CPU_FREQ_GOV_CONSERVATIVE default y config PPC_POWERNV_RTAS -- 1.8.3.1 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] Make the diu driver work without board level initilization
+ if (!diu_ops.set_pixel_clock) {
+ data-pixelclk_reg = of_iomap(np, 1);
+ if (!data-pixelclk_reg) {
+ dev_err(pdev-dev, Cannot map pixelclk registers,
please \
+ provide the diu_ops for pixclk setting
instead.\n);
The error message should be in one line if possible, or it will hard to
grep.
If cannot, should split it into two or more lines, like:
+dev_err(pdev-dev, Cannot map pixelclk registers,\n
+please provide the diu_ops for pixclk setting
instead.\n);
Thanks, This has been fixed in the update version, please help to review it at:
http://patchwork.ozlabs.org/patch/335225/
I forgot to add the V2 information in the subject in the update patch so this
may confuse the reviewer, sorry for that.
Best Regards,
Jason
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[PATCH 2/2] powerpc: Enable NO_BOOTMEM
Currently bootmem is just a wrapper around memblock. This gets rid of
the wrapper code just as other ARHC(es) did: x86, arm, etc.
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
arch/powerpc/Kconfig | 3 +++
arch/powerpc/mm/mem.c | 8
2 files changed, 11 insertions(+)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 957d3e5..2a2d4b3 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -471,6 +471,9 @@ config SYS_SUPPORTS_HUGETLBFS
source mm/Kconfig
+config NO_BOOTMEM
+ def_bool y
+
config ARCH_MEMORY_PROBE
def_bool y
depends on MEMORY_HOTPLUG
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index eaf5d1d8..d3e1d5f 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -187,10 +187,12 @@ EXPORT_SYMBOL_GPL(walk_system_ram_range);
#ifndef CONFIG_NEED_MULTIPLE_NODES
void __init do_init_bootmem(void)
{
+#ifndef CONFIG_NO_BOOTMEM
unsigned long start, bootmap_pages;
struct memblock_region *reg;
int boot_mapsize;
phys_addr_t _total_lowmem;
+#endif
phys_addr_t _lowmem_end_addr;
#ifndef CONFIG_HIGHMEM
@@ -203,6 +205,7 @@ void __init do_init_bootmem(void)
max_low_pfn = _lowmem_end_addr PAGE_SHIFT;
min_low_pfn = MEMORY_START PAGE_SHIFT;
+#ifndef CONFIG_NO_BOOTMEM
/*
* Find an area to use for the bootmem bitmap. Calculate the size of
* bitmap required as (Total Memory) / PAGE_SIZE / BITS_PER_BYTE.
@@ -214,12 +217,14 @@ void __init do_init_bootmem(void)
start = memblock_alloc(bootmap_pages PAGE_SHIFT, PAGE_SIZE);
boot_mapsize = init_bootmem_node(NODE_DATA(0), start PAGE_SHIFT,
min_low_pfn, max_low_pfn);
+#endif
/* Place all memblock_regions in the same node and merge contiguous
* memblock_regions
*/
memblock_set_node(0, (phys_addr_t)ULLONG_MAX, memblock.memory, 0);
+#ifndef CONFIG_NO_BOOTMEM
/* Add all physical memory to the bootmem map, mark each area
* present.
*/
@@ -234,11 +239,14 @@ void __init do_init_bootmem(void)
reserve_bootmem(reg-base, trunc_size, BOOTMEM_DEFAULT);
}
}
+#endif
/* XXX need to clip this if using highmem? */
sparse_memory_present_with_active_regions(0);
+#ifndef CONFIG_NO_BOOTMEM
init_bootmem_done = 1;
+#endif
}
/* mark pages that don't exist as nosave */
--
1.9.1
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[PATCH 1/2] bootmem/powerpc: Unify bootmem initialization
Unify the low/highmem code path from do_init_bootmem() by using (the)
lowmem related variables/parameters even when the low/highmem split
is not needed (64-bit) or configured. In such cases the lowmem
variables/parameters continue to observe the definition by referring
to memory directly mapped by the kernel
Signed-off-by: Emil Medve emilian.me...@freescale.com
---
arch/powerpc/mm/mem.c | 36
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index 32202c9..eaf5d1d8 100644
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -188,27 +188,31 @@ EXPORT_SYMBOL_GPL(walk_system_ram_range);
void __init do_init_bootmem(void)
{
unsigned long start, bootmap_pages;
- unsigned long total_pages;
struct memblock_region *reg;
int boot_mapsize;
+ phys_addr_t _total_lowmem;
+ phys_addr_t _lowmem_end_addr;
- max_low_pfn = max_pfn = memblock_end_of_DRAM() PAGE_SHIFT;
- total_pages = (memblock_end_of_DRAM() - memstart_addr) PAGE_SHIFT;
-#ifdef CONFIG_HIGHMEM
- total_pages = total_lowmem PAGE_SHIFT;
- max_low_pfn = lowmem_end_addr PAGE_SHIFT;
+#ifndef CONFIG_HIGHMEM
+ _lowmem_end_addr = memblock_end_of_DRAM();
+#else
+ _lowmem_end_addr = lowmem_end_addr;
#endif
+ max_pfn = memblock_end_of_DRAM() PAGE_SHIFT;
+ max_low_pfn = _lowmem_end_addr PAGE_SHIFT;
+ min_low_pfn = MEMORY_START PAGE_SHIFT;
+
/*
* Find an area to use for the bootmem bitmap. Calculate the size of
* bitmap required as (Total Memory) / PAGE_SIZE / BITS_PER_BYTE.
* Add 1 additional page in case the address isn't page-aligned.
*/
- bootmap_pages = bootmem_bootmap_pages(total_pages);
+ _total_lowmem = _lowmem_end_addr - memstart_addr;
+ bootmap_pages = bootmem_bootmap_pages(_total_lowmem PAGE_SHIFT);
start = memblock_alloc(bootmap_pages PAGE_SHIFT, PAGE_SIZE);
- min_low_pfn = MEMORY_START PAGE_SHIFT;
boot_mapsize = init_bootmem_node(NODE_DATA(0), start PAGE_SHIFT,
min_low_pfn, max_low_pfn);
/* Place all memblock_regions in the same node and merge contiguous
@@ -219,26 +223,18 @@ void __init do_init_bootmem(void)
/* Add all physical memory to the bootmem map, mark each area
* present.
*/
-#ifdef CONFIG_HIGHMEM
- free_bootmem_with_active_regions(0, lowmem_end_addr PAGE_SHIFT);
+ free_bootmem_with_active_regions(0, max_low_pfn);
/* reserve the sections we're already using */
for_each_memblock(reserved, reg) {
- unsigned long top = reg-base + reg-size - 1;
- if (top lowmem_end_addr)
+ if (reg-base + reg-size - 1 _lowmem_end_addr)
reserve_bootmem(reg-base, reg-size, BOOTMEM_DEFAULT);
- else if (reg-base lowmem_end_addr) {
- unsigned long trunc_size = lowmem_end_addr - reg-base;
+ else if (reg-base _lowmem_end_addr) {
+ unsigned long trunc_size = _lowmem_end_addr - reg-base;
reserve_bootmem(reg-base, trunc_size, BOOTMEM_DEFAULT);
}
}
-#else
- free_bootmem_with_active_regions(0, max_pfn);
- /* reserve the sections we're already using */
- for_each_memblock(reserved, reg)
- reserve_bootmem(reg-base, reg-size, BOOTMEM_DEFAULT);
-#endif
/* XXX need to clip this if using highmem? */
sparse_memory_present_with_active_regions(0);
--
1.9.1
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[PATCH] spi: add spi-lsb-first to devicetree
add optional property devicetree for SPI slave nodes
into devicetree so that LSB mode can be enabled by devicetree.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Documentation/devicetree/bindings/spi/spi-bus.txt | 4
drivers/spi/spi.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt
b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e5a4d1b..fdd9f15 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -55,11 +55,15 @@ contain the following properties.
chip select active high
- spi-3wire - (optional) Empty property indicating device requires
3-wire mode.
+- spi-lsb-first - (optional) Empty property indicating device requires
+ LSB first mode.
- spi-tx-bus-width - (optional) The bus width(number of data wires) that
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
used for MISO. Defaults to 1 if not present.
+- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+ used for MISO. Defaults to 1 if not present.
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 23756b0..0a20a90 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1050,6 +1050,8 @@ static void of_register_spi_devices(struct spi_master
*master)
spi-mode |= SPI_CS_HIGH;
if (of_find_property(nc, spi-3wire, NULL))
spi-mode |= SPI_3WIRE;
+ if (of_find_property(nc, spi-lsb-first, NULL))
+ spi-mode |= SPI_LSB_FIRST;
/* Device DUAL/QUAD mode */
if (!of_property_read_u32(nc, spi-tx-bus-width, value)) {
--
1.8.5
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Re: Build regressions/improvements in v3.14
On Tue, Apr 1, 2014 at 9:57 AM, Geert Uytterhoeven ge...@linux-m68k.org wrote:
JFYI, when comparing v3.14[1] to v3.14-rc8[3], the summaries are:
- build errors: +2/-10
+ error: No rule to make target include/config/auto.conf: = N/A
powerpc-randconfig
+ error: initramfs.c: undefined reference to `__stack_chk_guard':
= .init.text+0x1067)
x86_64-randconfig
[1] http://kisskb.ellerman.id.au/kisskb/head/7320/ (all 119 configs)
[3] http://kisskb.ellerman.id.au/kisskb/head/7303/ (all 119 configs)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
-- Linus Torval
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[PATCH] cpuidle: add freescale e500 family porcessors idle support
From: Wang Dongsheng dongsheng.w...@freescale.com
Add cpuidle support for e500 family, using cpuidle framework to
manage various low power modes. The new implementation will remain
compatible with original idle method.
I have done test about power consumption and latency. Cpuidle framework
will make CPU response time faster than original method, but power
consumption is higher than original method.
Power consumption:
The original method, power consumption is 10.51202 (W).
The cpuidle framework, power consumption is 10.5311 (W).
Latency:
The original method, avg latency is 6782 (us).
The cpuidle framework, avg latency is 6482 (us).
Initially, this supports PW10, PW20 and subsequent patches will support
DOZE/NAP and PH10, PH20.
Signed-off-by: Wang Dongsheng dongsheng.w...@freescale.com
diff --git a/arch/powerpc/include/asm/machdep.h
b/arch/powerpc/include/asm/machdep.h
index 5b6c03f..9301420 100644
--- a/arch/powerpc/include/asm/machdep.h
+++ b/arch/powerpc/include/asm/machdep.h
@@ -294,6 +294,15 @@ extern void power7_idle(void);
extern void ppc6xx_idle(void);
extern void book3e_idle(void);
+static inline void cpuidle_wait(void)
+{
+#ifdef CONFIG_PPC64
+ book3e_idle();
+#else
+ e500_idle();
+#endif
+}
+
/*
* ppc_md contains a copy of the machine description structure for the
* current platform. machine_id contains the initial address where the
diff --git a/arch/powerpc/kernel/sysfs.c b/arch/powerpc/kernel/sysfs.c
index 97e1dc9..edd193f 100644
--- a/arch/powerpc/kernel/sysfs.c
+++ b/arch/powerpc/kernel/sysfs.c
@@ -190,6 +190,9 @@ static ssize_t show_pw20_wait_time(struct device *dev,
return sprintf(buf, %llu\n, time 0 ? time : 0);
}
+#ifdef CONFIG_CPU_IDLE_E500
+u32 cpuidle_entry_bit;
+#endif
static void set_pw20_wait_entry_bit(void *val)
{
u32 *value = val;
@@ -204,7 +207,11 @@ static void set_pw20_wait_entry_bit(void *val)
/* set count */
pw20_idle |= ((MAX_BIT - *value) PWRMGTCR0_PW20_ENT_SHIFT);
+#ifdef CONFIG_CPU_IDLE_E500
+ cpuidle_entry_bit = *value;
+#else
mtspr(SPRN_PWRMGTCR0, pw20_idle);
+#endif
}
static ssize_t store_pw20_wait_time(struct device *dev,
diff --git a/drivers/cpuidle/Kconfig.powerpc b/drivers/cpuidle/Kconfig.powerpc
index 66c3a09..0949dbf 100644
--- a/drivers/cpuidle/Kconfig.powerpc
+++ b/drivers/cpuidle/Kconfig.powerpc
@@ -18,3 +18,10 @@ config POWERNV_CPUIDLE
help
Select this option to enable processor idle state management
through cpuidle subsystem.
+
+config CPU_IDLE_E500
+ bool CPU Idle Driver for E500 family processors
+ depends on CPU_IDLE
+ depends on FSL_SOC_BOOKE
+ help
+ Select this to enable cpuidle on e500 family processors.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index f71ae1b..7e6adea 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o
# POWERPC drivers
obj-$(CONFIG_PSERIES_CPUIDLE) += cpuidle-pseries.o
obj-$(CONFIG_POWERNV_CPUIDLE) += cpuidle-powernv.o
+obj-$(CONFIG_CPU_IDLE_E500)+= cpuidle-e500.o
diff --git a/drivers/cpuidle/cpuidle-e500.c b/drivers/cpuidle/cpuidle-e500.c
new file mode 100644
index 000..ddc0def
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-e500.c
@@ -0,0 +1,194 @@
+/*
+ * CPU Idle driver for Freescale PowerPC e500 family processors.
+ *
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * Author: Dongsheng Wang dongsheng.w...@freescale.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/cpu.h
+#include linux/cpuidle.h
+#include linux/init.h
+#include linux/kernel.h
+#include linux/notifier.h
+
+#include asm/cputable.h
+#include asm/machdep.h
+#include asm/mpc85xx.h
+
+static unsigned int max_idle_state;
+static struct cpuidle_state *cpuidle_state_table;
+
+struct cpuidle_driver e500_idle_driver = {
+ .name = e500_idle,
+ .owner = THIS_MODULE,
+};
+
+static void e500_cpuidle(void)
+{
+ if (cpuidle_idle_call())
+ cpuidle_wait();
+}
+
+static int pw10_enter(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ cpuidle_wait();
+ return index;
+}
+
+#define MAX_BIT63
+#define MIN_BIT1
+extern u32 cpuidle_entry_bit;
+static int pw20_enter(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv, int index)
+{
+ u32 pw20_idle;
+ u32 entry_bit;
+ pw20_idle = mfspr(SPRN_PWRMGTCR0);
+ if ((pw20_idle PWRMGTCR0_PW20_ENT) != PWRMGTCR0_PW20_ENT) {
+ pw20_idle = ~PWRMGTCR0_PW20_ENT;
+ entry_bit = MAX_BIT - cpuidle_entry_bit;
+ pw20_idle |= (entry_bit PWRMGTCR0_PW20_ENT_SHIFT);
+ mtspr(SPRN_PWRMGTCR0,
Re: [PATCH] spi: add spi-lsb-first to devicetree
Hi Zhao Qiang,
On Tue, Apr 01, 2014 at 03:55:31PM +0800, Zhao Qiang wrote:
add optional property devicetree for SPI slave nodes
into devicetree so that LSB mode can be enabled by devicetree.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
Documentation/devicetree/bindings/spi/spi-bus.txt | 4
drivers/spi/spi.c | 2 ++
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt
b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e5a4d1b..fdd9f15 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -55,11 +55,15 @@ contain the following properties.
chip select active high
- spi-3wire - (optional) Empty property indicating device requires
3-wire mode.
+- spi-lsb-first - (optional) Empty property indicating device requires
+ LSB first mode.
- spi-tx-bus-width - (optional) The bus width(number of data wires) that
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
used for MISO. Defaults to 1 if not present.
+- spi-rx-bus-width - (optional) The bus width(number of data wires) that
+ used for MISO. Defaults to 1 if not present.
Is this part intentionally here? It is not mentioned in the commit log, and
seems to merit a separate patch.
baruch
Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 23756b0..0a20a90 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1050,6 +1050,8 @@ static void of_register_spi_devices(struct spi_master
*master)
spi-mode |= SPI_CS_HIGH;
if (of_find_property(nc, spi-3wire, NULL))
spi-mode |= SPI_3WIRE;
+ if (of_find_property(nc, spi-lsb-first, NULL))
+ spi-mode |= SPI_LSB_FIRST;
/* Device DUAL/QUAD mode */
if (!of_property_read_u32(nc, spi-tx-bus-width, value)) {
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
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[PATCH v2] spi: add spi-lsb-first to devicetree
add optional property devicetree for SPI slave nodes
into devicetree so that LSB mode can be enabled by devicetree.
Signed-off-by: Zhao Qiang b45...@freescale.com
---
changs for v2:
- remove duplicate spi-rx-bus-width
Documentation/devicetree/bindings/spi/spi-bus.txt | 2 ++
drivers/spi/spi.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/spi/spi-bus.txt
b/Documentation/devicetree/bindings/spi/spi-bus.txt
index e5a4d1b..22d5740 100644
--- a/Documentation/devicetree/bindings/spi/spi-bus.txt
+++ b/Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -55,6 +55,8 @@ contain the following properties.
chip select active high
- spi-3wire - (optional) Empty property indicating device requires
3-wire mode.
+- spi-lsb-first - (optional) Empty property indicating device requires
+ LSB first mode.
- spi-tx-bus-width - (optional) The bus width(number of data wires) that
used for MOSI. Defaults to 1 if not present.
- spi-rx-bus-width - (optional) The bus width(number of data wires) that
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 23756b0..0a20a90 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1050,6 +1050,8 @@ static void of_register_spi_devices(struct spi_master
*master)
spi-mode |= SPI_CS_HIGH;
if (of_find_property(nc, spi-3wire, NULL))
spi-mode |= SPI_3WIRE;
+ if (of_find_property(nc, spi-lsb-first, NULL))
+ spi-mode |= SPI_LSB_FIRST;
/* Device DUAL/QUAD mode */
if (!of_property_read_u32(nc, spi-tx-bus-width, value)) {
--
1.8.5
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Re: [PATCH REPOST v5 1/3] powernv, cpufreq: Select CPUFreq related Kconfig options for powernv
On Tue, 2014-04-01 at 12:43 +0530, Gautham R. Shenoy wrote: From: Gautham R. Shenoy e...@linux.vnet.ibm.com Enable CPUFreq for PowerNV. Select performance, powersave, userspace and ondemand governors. Choose ondemand to be the default governor. Rafael, are you going to take these or should I send them to Linus ? (I'd rather you take them :-) Cheers, Ben. Signed-off-by: Gautham R. Shenoy e...@linux.vnet.ibm.com Signed-off-by: Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com --- arch/powerpc/configs/pseries_defconfig| 1 + arch/powerpc/configs/pseries_le_defconfig | 1 + arch/powerpc/platforms/powernv/Kconfig| 6 ++ 3 files changed, 8 insertions(+) diff --git a/arch/powerpc/configs/pseries_defconfig b/arch/powerpc/configs/pseries_defconfig index 9ea8342b..a905063 100644 --- a/arch/powerpc/configs/pseries_defconfig +++ b/arch/powerpc/configs/pseries_defconfig @@ -306,3 +306,4 @@ CONFIG_KVM_BOOK3S_64=m CONFIG_KVM_BOOK3S_64_HV=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y diff --git a/arch/powerpc/configs/pseries_le_defconfig b/arch/powerpc/configs/pseries_le_defconfig index 3c84f9d..58e3dbf 100644 --- a/arch/powerpc/configs/pseries_le_defconfig +++ b/arch/powerpc/configs/pseries_le_defconfig @@ -301,3 +301,4 @@ CONFIG_CRYPTO_LZO=m # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_DEV_NX=y CONFIG_CRYPTO_DEV_NX_ENCRYPT=m +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y diff --git a/arch/powerpc/platforms/powernv/Kconfig b/arch/powerpc/platforms/powernv/Kconfig index 895e8a2..c252ee9 100644 --- a/arch/powerpc/platforms/powernv/Kconfig +++ b/arch/powerpc/platforms/powernv/Kconfig @@ -11,6 +11,12 @@ config PPC_POWERNV select PPC_UDBG_16550 select PPC_SCOM select ARCH_RANDOM + select CPU_FREQ + select CPU_FREQ_GOV_PERFORMANCE + select CPU_FREQ_GOV_POWERSAVE + select CPU_FREQ_GOV_USERSPACE + select CPU_FREQ_GOV_ONDEMAND + select CPU_FREQ_GOV_CONSERVATIVE default y config PPC_POWERNV_RTAS ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC PATCH] powerpc/le: enable RTAS events support
On Mon, Mar 31, 2014 at 5:02 PM, Nathan Fontenot
nf...@linux.vnet.ibm.com wrote:
struct rtas_error_log {
- unsigned long version:8;/* Architectural version */
- unsigned long severity:3; /* Severity level of error */
- unsigned long disposition:2;/* Degree of recovery */
- unsigned long extended:1; /* extended log present? */
- unsigned long /* reserved */ :2;/* Reserved for future use */
- unsigned long initiator:4; /* Initiator of event */
- unsigned long target:4; /* Target of failed operation
*/
- unsigned long type:8; /* General event or error*/
- unsigned long extended_log_length:32; /* length in bytes */
- unsigned char buffer[1];/* Start of extended log */
+ /* Byte 0 */
+ uint8_t version;/* Architectural version */
+
+ /* Byte 1 */
+ uint8_t severity;
+ /*
+* XXX 3: Severity level of error
+*XX2: Degree of recovery
+* X 1: Extended log present?
+* XX 2: Reserved
+*/
+
+ /* Byte 2 */
+ uint8_t :8;
+ /*
+* 4: Initiator of event
+* 4: Target of failed operation
+*/
+ uint8_t type; /* General event or error*/
+ uint32_textended_log_length;/* length in bytes */
Now the bitfields are gone, things like the above can become __be32,
so we get extra type checking from sparse (make C=1).
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
-- Linus Torvalds
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Re: [PATCH bisect 0/2] ASoC: fsl_sai: Overwrite trigger()
On Tue, Apr 01, 2014 at 11:17:05AM +0800, Nicolin Chen wrote: * The patches are generated by using '-U2' because the default '-U3' would conflict the baseline without fsl_sai_isr patches. What are these fsi_sai_isr patches? signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH bisect 0/2] ASoC: fsl_sai: Overwrite trigger()
On Tue, Apr 01, 2014 at 12:04:12PM +0100, Mark Brown wrote: On Tue, Apr 01, 2014 at 11:17:05AM +0800, Nicolin Chen wrote: * The patches are generated by using '-U2' because the default '-U3' would conflict the baseline without fsl_sai_isr patches. What are these fsi_sai_isr patches? Ah..I should have mentioned the full patch name: e2681a1 ASoC: fsl_sai: Add isr to deal with error flag The patch conflicts against that asoc-3.15-4 tag at the fsl_sai.h because this isr patch added some new macros to it. Thank you, Nicolin Chen ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[RFC] powerpc, ptrace: Add few more ptrace request macros
This patch adds few more ptrace request macros expanding
the existing capability. These ptrace requests macros can
be classified into two categories.
(1) Transactional memory
/* TM special purpose registers */
PTRACE_GETTM_SPRREGS
PTRACE_SETTM_SPRREGS
/* Checkpointed GPR registers */
PTRACE_GETTM_CGPRREGS
PTRACE_SETTM_CGPRREGS
/* Checkpointed FPR registers */
PTRACE_GETTM_CFPRREGS
PTRACE_SETTM_CFPRREGS
/* Checkpointed VMX registers */
PTRACE_GETTM_CVMXREGS
PTRACE_SETTM_CVMXREGS
(2) Miscellaneous
/* TAR, PPR, DSCR registers */
PTRACE_GETMSCREGS
PTRACE_SETMSCREGS
This patch also adds mutliple new generic ELF core note sections in
this regard which can be listed as follows.
NT_PPC_TM_SPR /* Transactional memory specific registers */
NT_PPC_TM_CGPR /* Transactional memory checkpointed GPR */
NT_PPC_TM_CFPR /* Transactional memory checkpointed FPR */
NT_PPC_TM_CVMX /* Transactional memory checkpointed VMX */
NT_PPC_MISC /* Miscellaneous registers */
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/switch_to.h | 8 +
arch/powerpc/include/uapi/asm/ptrace.h | 61 +++
arch/powerpc/kernel/process.c | 24 ++
arch/powerpc/kernel/ptrace.c | 658 +++--
include/uapi/linux/elf.h | 5 +
5 files changed, 729 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/include/asm/switch_to.h
b/arch/powerpc/include/asm/switch_to.h
index 0e83e7d..73e2601 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -80,6 +80,14 @@ static inline void flush_spe_to_thread(struct task_struct *t)
}
#endif
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+extern void flush_tmreg_to_thread(struct task_struct *);
+#else
+static inline void flush_tmreg_to_thread(struct task_struct *t)
+{
+}
+#endif
+
static inline void clear_task_ebb(struct task_struct *t)
{
#ifdef CONFIG_PPC_BOOK3S_64
diff --git a/arch/powerpc/include/uapi/asm/ptrace.h
b/arch/powerpc/include/uapi/asm/ptrace.h
index 77d2ed3..fd962d6 100644
--- a/arch/powerpc/include/uapi/asm/ptrace.h
+++ b/arch/powerpc/include/uapi/asm/ptrace.h
@@ -190,6 +190,67 @@ struct pt_regs {
#define PPC_PTRACE_SETHWDEBUG 0x88
#define PPC_PTRACE_DELHWDEBUG 0x87
+/* Transactional memory registers */
+
+/*
+ * SPR
+ *
+ * struct data {
+ * u64 tm_tfhar;
+ * u64 tm_texasr;
+ * u64 tm_tfiar;
+ * unsigned long tm_orig_msr;
+ * u64 tm_tar;
+ * u64 tm_ppr;
+ * u64 tm_dscr;
+ * };
+ */
+#define PTRACE_GETTM_SPRREGS 0x70
+#define PTRACE_SETTM_SPRREGS 0x71
+
+/*
+ * Checkpointed GPR
+ *
+ * struct data {
+ * struct pt_regs ckpt_regs;
+ * };
+ */
+#define PTRACE_GETTM_CGPRREGS 0x72
+#define PTRACE_SETTM_CGPRREGS 0x73
+
+/*
+ * Checkpointed FPR
+ *
+ * struct data {
+ * u64 fpr[32];
+ * u64 fpscr;
+ * };
+ */
+#define PTRACE_GETTM_CFPRREGS 0x74
+#define PTRACE_SETTM_CFPRREGS 0x75
+
+/*
+ * Checkpointed VMX
+ *
+ * struct data {
+ * vector128 vr[32];
+ * vector128 vscr;
+ * unsigned long vrsave;
+ *};
+ */
+#define PTRACE_GETTM_CVMXREGS 0x76
+#define PTRACE_SETTM_CVMXREGS 0x77
+
+/* Miscellaneous registers */
+#define PTRACE_GETMSCREGS 0x78
+#define PTRACE_SETMSCREGS 0x79
+
+/*
+ * XXX: A note to application developers. The existing data layout
+ * of the above four ptrace requests can change when new registers
+ * are available for each category in forthcoming processors.
+ */
+
#ifndef __ASSEMBLY__
struct ppc_debug_info {
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index af064d2..e5dfd8e 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -673,6 +673,30 @@ static inline void __switch_to_tm(struct task_struct *prev)
}
}
+void flush_tmreg_to_thread(struct task_struct *tsk)
+{
+ /*
+* If task is not current, it should have been flushed
+* already to it's thread_struct during __switch_to().
+*/
+ if (tsk != current)
+ return;
+
+ preempt_disable();
+ if (tsk-thread.regs) {
+ /*
+* If we are still current, the TM state need to
+* be flushed to thread_struct as it will be still
+* present in the current cpu
+*/
+ if (MSR_TM_ACTIVE(tsk-thread.regs-msr)) {
+ __switch_to_tm(tsk);
+ tm_recheckpoint_new_task(tsk);
+ }
+ }
+ preempt_enable();
+}
+
/*
* This is called if we are on the way out to userspace and the
* TIF_RESTORE_TM flag is set. It checks if we need to reload
diff --git a/arch/powerpc/kernel/ptrace.c
[PATCH] ASoC: fsl_sai: Add imx6sx platform support
The next coming i.MX6 Solo X SoC also contains SAI module while we use
imp_pcm_init() for i.MX platform.
So this patch adds one compatible route for imx6sx and updates the DT
doc accordingly.
Signed-off-by: Nicolin Chen guangyu.c...@freescale.com
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 2 +-
sound/soc/fsl/fsl_sai.c | 12 ++--
sound/soc/fsl/fsl_sai.h | 1 +
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt
b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 98611a6..35c09fe 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -7,7 +7,7 @@ codec/DSP interfaces.
Required properties:
-- compatible: Compatible list, contains fsl,vf610-sai.
+- compatible: Compatible list, contains fsl,vf610-sai or fsl,imx6sx-sai.
- reg: Offset and length of the register set for the device.
- clocks: Must contain an entry for each entry in clock-names.
- clock-names : Must include the sai entry.
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index d64c33f..9ed6795 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -22,6 +22,7 @@
#include sound/pcm_params.h
#include fsl_sai.h
+#include imx-pcm.h
#define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
FSL_SAI_CSR_FEIE)
@@ -592,6 +593,9 @@ static int fsl_sai_probe(struct platform_device *pdev)
sai-pdev = pdev;
+ if (of_device_is_compatible(pdev-dev.of_node, fsl,imx6sx-sai))
+ sai-sai_on_imx = true;
+
sai-big_endian_regs = of_property_read_bool(np, big-endian-regs);
if (sai-big_endian_regs)
fsl_sai_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG;
@@ -634,12 +638,16 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (ret)
return ret;
- return devm_snd_dmaengine_pcm_register(pdev-dev, NULL,
- SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
+ if (sai-sai_on_imx)
+ return imx_pcm_dma_init(pdev);
+ else
+ return devm_snd_dmaengine_pcm_register(pdev-dev, NULL,
+ SND_DMAENGINE_PCM_FLAG_NO_RESIDUE);
}
static const struct of_device_id fsl_sai_ids[] = {
{ .compatible = fsl,vf610-sai, },
+ { .compatible = fsl,imx6sx-sai, },
{ /* sentinel */ }
};
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index be26d46..677670d 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -130,6 +130,7 @@ struct fsl_sai {
bool big_endian_regs;
bool big_endian_data;
bool is_dsp_mode;
+ bool sai_on_imx;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
--
1.8.4
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[PATCH 1/2] ASoC: fsl_sai: Add clock control for SAI
The SAI mainly has two clocks:
ipg_clock -- registers access for SoC or DMA to read and write.
sai_clock -- providing DAI format bit clock and frame clock.
Thus this patch adds these two clocks to the driver with their clock
controls and replaces the regmap clock 'sai_clock' with 'ipg_clock'.
Signed-off-by: Nicolin Chen guangyu.c...@freescale.com
---
.../devicetree/bindings/sound/fsl-sai.txt | 7 ++--
sound/soc/fsl/fsl_sai.c| 37 --
sound/soc/fsl/fsl_sai.h| 2 ++
3 files changed, 41 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt
b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 35c09fe..bad4453 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -11,5 +11,6 @@ Required properties:
- reg: Offset and length of the register set for the device.
- clocks: Must contain an entry for each entry in clock-names.
-- clock-names : Must include the sai entry.
+- clock-names : Must include the ipg for register access and sai for bit
+ clock and frame clock providing.
- dmas : Generic dma devicetree binding as described in
Documentation/devicetree/bindings/dma/dma.txt.
@@ -31,6 +32,6 @@ sai2: sai@40031000 {
pinctrl-names = default;
pinctrl-0 = pinctrl_sai2_1;
- clocks = clks VF610_CLK_SAI2;
- clock-names = sai;
+ clocks = clks VF610_CLK_SAI2, clks VF610_CLK_SAI2;
+ clock-names = ipg, sai;
dma-names = tx, rx;
dmas = edma0 0 VF610_EDMA_MUXID0_SAI2_TX,
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 3847d2a..2d749df 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -428,5 +428,18 @@ static int fsl_sai_startup(struct snd_pcm_substream
*substream,
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
- u32 reg;
+ struct device *dev = sai-pdev-dev;
+ u32 reg, ret;
+
+ ret = clk_prepare_enable(sai-ipg_clk);
+ if (ret) {
+ dev_err(dev, failed to prepare and enable ipg clock\n);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(sai-sai_clk);
+ if (ret) {
+ dev_err(dev, failed to prepare and enable sai clock\n);
+ goto err;
+ }
if (substream-stream == SNDRV_PCM_STREAM_PLAYBACK)
@@ -439,4 +452,9 @@ static int fsl_sai_startup(struct snd_pcm_substream
*substream,
return 0;
+
+err:
+ clk_disable_unprepare(sai-ipg_clk);
+
+ return ret;
}
@@ -454,4 +472,7 @@ static void fsl_sai_shutdown(struct snd_pcm_substream
*substream,
regmap_update_bits(sai-regmap, reg, FSL_SAI_CR3_TRCE,
~FSL_SAI_CR3_TRCE);
+
+ clk_disable_unprepare(sai-sai_clk);
+ clk_disable_unprepare(sai-ipg_clk);
}
@@ -609,5 +630,5 @@ static int fsl_sai_probe(struct platform_device *pdev)
sai-regmap = devm_regmap_init_mmio_clk(pdev-dev,
- sai, base, fsl_sai_regmap_config);
+ ipg, base, fsl_sai_regmap_config);
if (IS_ERR(sai-regmap)) {
dev_err(pdev-dev, regmap init failed\n);
@@ -615,4 +636,16 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
+ sai-ipg_clk = devm_clk_get(pdev-dev, ipg);
+ if (IS_ERR(sai-ipg_clk)) {
+ dev_err(pdev-dev, failed to get ipg clock\n);
+ return PTR_ERR(sai-ipg_clk);
+ }
+
+ sai-sai_clk = devm_clk_get(pdev-dev, sai);
+ if (IS_ERR(sai-sai_clk)) {
+ dev_err(pdev-dev, failed to get sai clock\n);
+ return PTR_ERR(sai-sai_clk);
+ }
+
irq = platform_get_irq(pdev, 0);
if (irq 0) {
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 677670d..cbaf114 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -127,4 +127,6 @@ struct fsl_sai {
struct platform_device *pdev;
struct regmap *regmap;
+ struct clk *ipg_clk;
+ struct clk *sai_clk;
bool big_endian_regs;
--
1.8.4
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[PATCH 0/2] Add ipg clock control to sai driver
This series of patches add ipg clock control to fsl_sai driver and updates the vf610.dtsi accordingly. @Shawn I'm not sure if VF610 currently does full works with SAI audio function. The PATCH-2 is based on broonie/for-next. Nicolin Chen (2): ASoC: fsl_sai: Add clock control for SAI ARM: dts: Add ipg clock for sai2 on VF610 platform .../devicetree/bindings/sound/fsl-sai.txt | 7 ++-- arch/arm/boot/dts/vf610.dtsi | 4 +-- sound/soc/fsl/fsl_sai.c| 37 -- sound/soc/fsl/fsl_sai.h| 2 ++ 4 files changed, 43 insertions(+), 7 deletions(-) -- 1.8.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH 2/2] ARM: dts: Add ipg clock for sai2 on VF610 platform
Since we added ipg clock to the DT binding, we should update the current SAI dts/dtsi so as not to break their functions. Signed-off-by: Nicolin Chen guangyu.c...@freescale.com --- arch/arm/boot/dts/vf610.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index d31ce1b..493c498 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -140,6 +140,6 @@ reg = 0x40031000 0x1000; interrupts = 0 86 0x04; - clocks = clks VF610_CLK_SAI2; - clock-names = sai; + clocks = clks VF610_CLK_SAI2, clks VF610_CLK_SAI2; + clock-names = ipg, sai; status = disabled; }; -- 1.8.4 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH bisect 1/2] ASoC: fsl_sai: Fix buggy configurations in trigger()
On Tue, Apr 01, 2014 at 11:17:06AM +0800, Nicolin Chen wrote: The current trigger() has two crucial problems: 1) The DMA request enabling operations (FSL_SAI_CSR_FRDE) for Tx and Rx are now totally exclusive: It would fail to run simultaneous Tx-Rx cases. 2) The TERE disabling operation depends on an incorrect condition -- active reference count that only gets increased in snd_pcm_open() and decreased in snd_pcm_close(): The TERE would never get cleared. Applied, thanks. signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH bisect 2/2] ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams
On Tue, Apr 01, 2014 at 11:17:07AM +0800, Nicolin Chen wrote: We only enable one side interrupt for each stream since over/underrun on the opposite stream would be resulted from what we previously did, enabling TERE but remaining FRDE disabled, even though the xrun on the opposite direction will not break the current stream. This still doesn't apply against fsl-sai (nor for-next). signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH bisect 2/2] ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams
On Tue, Apr 01, 2014 at 01:07:15PM +0100, Mark Brown wrote: On Tue, Apr 01, 2014 at 11:17:07AM +0800, Nicolin Chen wrote: We only enable one side interrupt for each stream since over/underrun on the opposite stream would be resulted from what we previously did, enabling TERE but remaining FRDE disabled, even though the xrun on the opposite direction will not break the current stream. This still doesn't apply against fsl-sai (nor for-next). Sir, I just rebased my for-next branch again and found that it's missing two applied patches: ASoC: fsl_sai: Add isr to deal with error flag and ASoC: fsl_sai: Improve fsl_sai_isr(), so that's why this PATCH-2 could not be applied against it as it needs the macro that's included in the patch ASoC: fsl_sai: Add isr to deal with error flag. What should I do now? Thank you, Nicolin ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] powerpc: Use 64k io pages when we never see an HEA
When we never get around to seeing an HEA ethernet adapter, there's
no point in restricting ourselves to 4k IO page size.
This speeds up IO maps when CONFIG_IBMEBUS is disabled.
Signed-off-by: Alexander Graf ag...@suse.de
---
arch/powerpc/mm/hash_utils_64.c | 21 ++---
1 file changed, 18 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index d766d6e..c0ef976 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -445,6 +445,20 @@ static void mmu_psize_set_default_penc(void)
mmu_psize_defs[bpsize].penc[apsize] = -1;
}
+static bool might_have_hea(void)
+{
+ /*
+* The HEA ethernet adapter requires awareness of the
+* GX bus. Without that awareness we can easily assume
+* we will never see an HEA ethernet device.
+*/
+#ifdef CONFIG_IBMEBUS
+ return true;
+#else
+ return false;
+#endif
+}
+
static void __init htab_init_page_sizes(void)
{
int rc;
@@ -499,10 +513,11 @@ static void __init htab_init_page_sizes(void)
mmu_linear_psize = MMU_PAGE_64K;
if (mmu_has_feature(MMU_FTR_CI_LARGE_PAGE)) {
/*
-* Don't use 64k pages for ioremap on pSeries, since
-* that would stop us accessing the HEA ethernet.
+* When running on pSeries using 64k pages for ioremap
+* would stop us accessing the HEA ethernet. So if we
+* have the chance of ever seeing one, stay at 4k.
*/
- if (!machine_is(pseries))
+ if (!might_have_hea() || !machine_is(pseries))
mmu_io_psize = MMU_PAGE_64K;
} else
mmu_ci_restrictions = 1;
--
1.8.1.4
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Re: [PATCH 15/33] powerpc: Fix ABIv2 issues with stack offsets in assembly code
Anton Blanchard wrote: diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S index 72ad055..01da956 100644 --- a/arch/powerpc/lib/memcpy_64.S +++ b/arch/powerpc/lib/memcpy_64.S @@ -12,7 +12,7 @@ .align 7 _GLOBAL(memcpy) BEGIN_FTR_SECTION - std r3,48(r1) /* save destination pointer for return value */ + std r3,STK_PARAM(R3)(r1)/* save destination pointer for return value */ FTR_SECTION_ELSE #ifndef SELFTEST b memcpy_power7 This chunk is rejected when applied to linux-3.14, because of the reference to SELTEST. The last three context lines should rather read: FTR_SECTION_ELSE b memcpy_power7 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY) Same issue with [PATCH 16/33] powerpc: Fix unsafe accesses to parameter area in ELFv2. Philippe ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH bisect 2/2] ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams
On Tue, Apr 01, 2014 at 09:21:57PM +0800, Nicolin Chen wrote: Sir, I just rebased my for-next branch again and found that it's missing two applied patches: ASoC: fsl_sai: Add isr to deal with error flag and ASoC: fsl_sai: Improve fsl_sai_isr(), so that's why this PATCH-2 could not be applied against it as it needs the macro that's included in the patch ASoC: fsl_sai: Add isr to deal with error flag. Ah, those dropped out of -next due to the merge window. I've applied your new patch now. signature.asc Description: Digital signature ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
On Tue, 2014-04-01 at 07:47 +0200, Alexander Graf wrote: Am 01.04.2014 um 01:03 schrieb Scott Wood scottw...@freescale.com: On Mon, 2014-03-31 at 15:41 +0200, Alexander Graf wrote: On 03/26/2014 10:17 PM, Scott Wood wrote: On Thu, 2014-02-20 at 18:30 +0200, Mihai Caraman wrote: +/* + * Another thread may rewrite the TLB entry in parallel, don't + * execute from the address if the execute permission is not set + */ What happens when another thread rewrites the TLB entry in parallel? Does tlbsx succeed? Does it fail? Do we see failure indicated somehow? Are the contents of the MAS registers consistent at this point or inconsistent? If another thread rewrites the TLB entry, then we use the new TLB entry, just as if it had raced in hardware. This check ensures that we don't execute from the new TLB entry if it doesn't have execute permissions (just as hardware would). What happens if the new TLB entry is valid and executable, and the instruction pointed to is valid, but doesn't trap (and thus we don't have emulation for it)? There has to be a good way to detect such a race and deal with it, no? How would you detect it? We don't get any information from the trap about what physical address the instruction was fetched from, or what the instruction was. Ah, this is a guest race where the guest modifies exactly the TLB in question. I see. Why would this ever happen in practice (in a case where we're not executing malicious code)? I don't know. It probably wouldn't. But it seems wrong to not check the exec bit. -Scott ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 4/4] KVM: PPC: Bookehv: Get vcpu's last instruction for emulation
On 04/01/2014 06:58 PM, Scott Wood wrote: On Tue, 2014-04-01 at 07:47 +0200, Alexander Graf wrote: Am 01.04.2014 um 01:03 schrieb Scott Wood scottw...@freescale.com: On Mon, 2014-03-31 at 15:41 +0200, Alexander Graf wrote: On 03/26/2014 10:17 PM, Scott Wood wrote: On Thu, 2014-02-20 at 18:30 +0200, Mihai Caraman wrote: +/* + * Another thread may rewrite the TLB entry in parallel, don't + * execute from the address if the execute permission is not set + */ What happens when another thread rewrites the TLB entry in parallel? Does tlbsx succeed? Does it fail? Do we see failure indicated somehow? Are the contents of the MAS registers consistent at this point or inconsistent? If another thread rewrites the TLB entry, then we use the new TLB entry, just as if it had raced in hardware. This check ensures that we don't execute from the new TLB entry if it doesn't have execute permissions (just as hardware would). What happens if the new TLB entry is valid and executable, and the instruction pointed to is valid, but doesn't trap (and thus we don't have emulation for it)? There has to be a good way to detect such a race and deal with it, no? How would you detect it? We don't get any information from the trap about what physical address the instruction was fetched from, or what the instruction was. Ah, this is a guest race where the guest modifies exactly the TLB in question. I see. Why would this ever happen in practice (in a case where we're not executing malicious code)? I don't know. It probably wouldn't. But it seems wrong to not check the exec bit. Right, I'm just saying that a program interrupt is not too bad of an answer in case the guest does something as stupid as this in kernel space :). It's definitely good practice to check for the exec bit. Alex ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/2] Make the diu driver work without board level initilization
On Tue, 2014-04-01 at 02:28 -0500, Jin Zhengxiong-R64188 wrote:
+ if (!diu_ops.set_pixel_clock) {
+ data-pixelclk_reg = of_iomap(np, 1);
+ if (!data-pixelclk_reg) {
+ dev_err(pdev-dev, Cannot map pixelclk registers,
please \
+ provide the diu_ops for pixclk setting
instead.\n);
The error message should be in one line if possible, or it will hard to
grep.
If cannot, should split it into two or more lines, like:
+ dev_err(pdev-dev, Cannot map pixelclk registers,\n
+ please provide the diu_ops for pixclk setting
instead.\n);
Thanks, This has been fixed in the update version, please help to review it
at:
http://patchwork.ozlabs.org/patch/335225/
I forgot to add the V2 information in the subject in the update patch so this
may confuse the reviewer, sorry for that.
It is not fixed in that patch (or did you link the wrong version?). You
should never use \ to continue a line in C, other than in macros.
Further, it is not permitted to wrap kernel output strings. This is an
exception to the 80-column rule. Checkpatch should have told you this.
-Scott
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Re: [PATCH 1/3] powerpc/fsl-booke: Add support for T2080/T2081 SoC
On Mon, 2014-03-03 at 17:50 +0800, Shengzhou Liu wrote:
+ corenet-cf@18000 {
+ compatible = fsl,corenet-cf;
+ reg = 0x18000 0x1000;
+ interrupts = 16 2 1 31;
+ fsl,ccf-num-csdids = 32;
+ fsl,ccf-num-snoopids = 32;
+ };
This is not compatible with fsl,corenet-cf.
+ clockgen: global-utilities@e1000 {
+ compatible = fsl,t2080-clockgen, fsl,qoriq-clockgen-2.0;
+ reg = 0xe1000 0x1000;
+ };
See Documentation/devicetree/bindings/clock/corenet-clock.txt
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ /*
+ * Temporarily add next-level-cache info in each cpu node so
+ * that uboot can do L2 cache fixup. This can be removed once
+ * u-boot can create cpu node with cache info.
+ */
Is there a reason why this is temporary? What do we gain from U-Boot
doing the fixup? Is U-Boot doing the rest of the fixup (adding ePAPR
properties to the L2 cache nodes)?
-Scott
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Re: [PATCH REPOST v5 1/3] powernv, cpufreq: Select CPUFreq related Kconfig options for powernv
On Tuesday, April 01, 2014 08:46:49 PM Benjamin Herrenschmidt wrote: On Tue, 2014-04-01 at 12:43 +0530, Gautham R. Shenoy wrote: From: Gautham R. Shenoy e...@linux.vnet.ibm.com Enable CPUFreq for PowerNV. Select performance, powersave, userspace and ondemand governors. Choose ondemand to be the default governor. Rafael, are you going to take these or should I send them to Linus ? (I'd rather you take them :-) I can do that, but the timing is pretty bad. How urgent are they? Rafael ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 2/3] powerpc/fsl-booke: Add initial T208x QDS board support
On Mon, 2014-03-03 at 17:50 +0800, Shengzhou Liu wrote:
+ dcsr: dcsr@f {
+ ranges = 0x 0xf 0x 0x01072000;
+ };
This is a very odd size -- where did it come from?
-Scott
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[git pull] Please pull powerpc.git merge branch
Hi Linus !
This time around, the powerpc merges are going to be a little bit
more complicated than usual.
This is the main pull request with most of the work for this merge
window. I will describe it a bit more further down.
There is some additional cpuidle driver work, however I haven't included
it in this tree as it depends on some work in tip/timer-core which
Thomas accidentally forgot to put in a topic branch. Since I didn't want
to carry all of that tip timer stuff in powerpc -next, I setup a
separate branch on top of Thomas tree with just that cpuidle driver in
it, and Stephen has been carrying that in next separately for a while
now. I'll send a separate pull request for it.
Additionally, two new pieces in this tree add users for a sysfs API
that Tejun and Greg have been deprecating in drivers-core-next.
Thankfully Greg reverted the patch that removes the old API so this
merge can happen cleanly, but once merged, I will send a patch adjusting
our new code to the new API so that Greg can send you the removal patch.
Now as for the content of this branch, we have a lot of perf work for
power8 new counters including support for our new nest counters
(also called 24x7) under pHyp (not natively yet).
We have new functionality when running under the OPAL firmware
(non-virtualized or KVM host), such as access to the firmware error logs
and service processor dumps, system parameters and sensors, along with
a hwmon driver for the latter.
There's also a bunch of bug fixes accross the board, some LE fixes,
and a nice set of selftests for validating our various types of
copy loops.
On the Freescale side, we see mostly new chip/board revisions, some
clock updates, better support for machine checks and debug exceptions,
etc...
Cheers,
Ben.
The following changes since commit a5b2cf5b1af424ee3dd9e3ce6d5cea18cb927e67:
powerpc: Align p_dyn, p_rela and p_st symbols (2014-03-07 13:50:19 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
for you to fetch changes up to cd427485357c0c4b99f69719251baacf25946e11:
Merge remote-tracking branch 'scott/next' into next (2014-03-24 10:26:10
+1100)
Aneesh Kumar K.V (2):
powerpc/mm: Make sure a local_irq_disable prevent a parallel THP split
powerpc/defconfigs: Enable THP in pseries defconfig
Anshuman Khandual (2):
powerpc/perf: Make some new raw event codes available in sysfs
powerpc/perf: Define perf_event_print_debug() to print PMU register values
Anton Blanchard (2):
powerpc: Use default set of netfilter modules
(CONFIG_NETFILTER_ADVANCED=n)
powerpc/compat: 32-bit little endian machine name is ppcle, not ppc
Benjamin Herrenschmidt (2):
powerpc/pseries: Don't try to register pseries cpu hotplug on non-pseries
Merge remote-tracking branch 'scott/next' into next
Benjamin Krill (1):
powerpc/book3e: Fix check for linear mapping in TLB miss handler
Brandon Stewart (1):
macintosh/adb: Fixed some coding style problems
Cody P Schafer (10):
sysfs: create bin_attributes under the requested group
powerpc: Add hvcalls for 24x7 and gpci (Get Performance Counter Info)
powerpc/perf: Add hv_gpci interface header
powerpc/perf: Add 24x7 interface headers
powerpc/perf: Add a shared interface to get gpci version and capabilities
powerpc/perf: Add macros for defining event fields formats
powerpc/perf: Add support for the hv gpci (get performance counter info)
interface
powerpc/perf: Add support for the hv 24x7 interface
powerpc/perf: Add kconfig option for hypervisor provided counters
powerpc/perf/hv_{gpci, 24x7}: Add documentation of device attributes
Greg Kurz (1):
powerpc/le: Big endian arguments for ppc_rtas()
Haren Myneni (2):
powerpc/pseries: Device tree should only be updated once after
suspend/migrate
powerpc/pseries: Update dynamic cache nodes for suspend/resume operation
Josh Boyer (1):
powerpc: Update ppc4xx maintainer
Li Zhong (1):
powerpc: Revert c6102609 and replace it with the correct fix for vio dma
mask setting
Luis Henriques (1):
powerpc/kconfig: Remove TSI108_BRIDGE duplicates
Mahesh Salgaonkar (2):
powerpc/book3s: Recover from MC in sapphire on SCOM read via MMIO.
powerpc/book3s: Fix CFAR clobbering issue in machine check handler.
Michael Ellerman (9):
selftests/powerpc: Import Anton's memcpy / copy_tofrom_user tests
powerpc: Add a cpu feature CPU_FTR_PMAO_BUG
powerpc/perf: Add lost exception workaround
powerpc/perf: Reject EBB events which specify a sample_type
powerpc/perf: Clean up the EBB hash defines a little
powerpc/perf: Avoid mutating event in power8_get_constraint()
powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBB
powerpc/perf: Enable BHRB access for EBB events
[git pull] Please pull powerpc.git next branch
Hi Linus !
This time around, the powerpc merges are going to be a little bit
more complicated than usual.
This is the main pull request with most of the work for this merge
window. I will describe it a bit more further down.
There is some additional cpuidle driver work, however I haven't included
it in this tree as it depends on some work in tip/timer-core which
Thomas accidentally forgot to put in a topic branch. Since I didn't want
to carry all of that tip timer stuff in powerpc -next, I setup a
separate branch on top of Thomas tree with just that cpuidle driver in
it, and Stephen has been carrying that in next separately for a while
now. I'll send a separate pull request for it.
Additionally, two new pieces in this tree add users for a sysfs API
that Tejun and Greg have been deprecating in drivers-core-next.
Thankfully Greg reverted the patch that removes the old API so this
merge can happen cleanly, but once merged, I will send a patch adjusting
our new code to the new API so that Greg can send you the removal patch.
Now as for the content of this branch, we have a lot of perf work for
power8 new counters including support for our new nest counters
(also called 24x7) under pHyp (not natively yet).
We have new functionality when running under the OPAL firmware
(non-virtualized or KVM host), such as access to the firmware error logs
and service processor dumps, system parameters and sensors, along with
a hwmon driver for the latter.
There's also a bunch of bug fixes accross the board, some LE fixes,
and a nice set of selftests for validating our various types of
copy loops.
On the Freescale side, we see mostly new chip/board revisions, some
clock updates, better support for machine checks and debug exceptions,
etc...
Cheers,
Ben.
The following changes since commit a5b2cf5b1af424ee3dd9e3ce6d5cea18cb927e67:
powerpc: Align p_dyn, p_rela and p_st symbols (2014-03-07 13:50:19 +1100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git next
for you to fetch changes up to cd427485357c0c4b99f69719251baacf25946e11:
Merge remote-tracking branch 'scott/next' into next (2014-03-24 10:26:10
+1100)
Aneesh Kumar K.V (2):
powerpc/mm: Make sure a local_irq_disable prevent a parallel THP split
powerpc/defconfigs: Enable THP in pseries defconfig
Anshuman Khandual (2):
powerpc/perf: Make some new raw event codes available in sysfs
powerpc/perf: Define perf_event_print_debug() to print PMU register values
Anton Blanchard (2):
powerpc: Use default set of netfilter modules
(CONFIG_NETFILTER_ADVANCED=n)
powerpc/compat: 32-bit little endian machine name is ppcle, not ppc
Benjamin Herrenschmidt (2):
powerpc/pseries: Don't try to register pseries cpu hotplug on non-pseries
Merge remote-tracking branch 'scott/next' into next
Benjamin Krill (1):
powerpc/book3e: Fix check for linear mapping in TLB miss handler
Brandon Stewart (1):
macintosh/adb: Fixed some coding style problems
Cody P Schafer (10):
sysfs: create bin_attributes under the requested group
powerpc: Add hvcalls for 24x7 and gpci (Get Performance Counter Info)
powerpc/perf: Add hv_gpci interface header
powerpc/perf: Add 24x7 interface headers
powerpc/perf: Add a shared interface to get gpci version and capabilities
powerpc/perf: Add macros for defining event fields formats
powerpc/perf: Add support for the hv gpci (get performance counter info)
interface
powerpc/perf: Add support for the hv 24x7 interface
powerpc/perf: Add kconfig option for hypervisor provided counters
powerpc/perf/hv_{gpci, 24x7}: Add documentation of device attributes
Greg Kurz (1):
powerpc/le: Big endian arguments for ppc_rtas()
Haren Myneni (2):
powerpc/pseries: Device tree should only be updated once after
suspend/migrate
powerpc/pseries: Update dynamic cache nodes for suspend/resume operation
Josh Boyer (1):
powerpc: Update ppc4xx maintainer
Li Zhong (1):
powerpc: Revert c6102609 and replace it with the correct fix for vio dma
mask setting
Luis Henriques (1):
powerpc/kconfig: Remove TSI108_BRIDGE duplicates
Mahesh Salgaonkar (2):
powerpc/book3s: Recover from MC in sapphire on SCOM read via MMIO.
powerpc/book3s: Fix CFAR clobbering issue in machine check handler.
Michael Ellerman (9):
selftests/powerpc: Import Anton's memcpy / copy_tofrom_user tests
powerpc: Add a cpu feature CPU_FTR_PMAO_BUG
powerpc/perf: Add lost exception workaround
powerpc/perf: Reject EBB events which specify a sample_type
powerpc/perf: Clean up the EBB hash defines a little
powerpc/perf: Avoid mutating event in power8_get_constraint()
powerpc/perf: Add BHRB constraint and IFM MMCRA handling for EBB
powerpc/perf: Enable BHRB access for EBB events
[git pull] Please pull powerpc.git powernv-cpuidle branch
Hi Linus ! This is the branch I mentioned in my other pull request which contains our improved cpuidle support for the powernv platform (non-virtualized). It adds support for the fast sleep feature of the processor which provides higher power savings than our usual nap mode but at the cost of losing the timers while asleep, and thus exploits the new timer broadcast framework to work around that limitation. It's based on a tip timer tree that you seem to have already merged Cheers, Ben. The following changes since commit 849401b66d305f3feb75b6db7459b95ad190552a: tick: Fixup more fallout from hrtimer broadcast mode (2014-02-09 15:11:47 +0100) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc.git powernv-cpuidle for you to fetch changes up to 039c5b62c44a55ac9d28acc273ba663c65ea: cpuidle/powernv: Parse device tree to setup idle states (2014-03-05 15:57:08 +1100) Preeti U Murthy (3): powerpc: Split timer_interrupt() into timer handling and interrupt handling routines cpuidle/powernv: Add Fast-Sleep CPU idle state cpuidle/powernv: Parse device tree to setup idle states Srivatsa S. Bhat (2): powerpc: Free up the slot of PPC_MSG_CALL_FUNC_SINGLE IPI message powerpc: Implement tick broadcast IPI as a fixed IPI message Vaidyanathan Srinivasan (2): powerpc/powernv: Add context management for Fast Sleep powerpc/powernv: Add OPAL call to resync timebase on wakeup arch/powerpc/Kconfig | 2 + arch/powerpc/include/asm/opal.h| 2 + arch/powerpc/include/asm/processor.h | 1 + arch/powerpc/include/asm/smp.h | 2 +- arch/powerpc/include/asm/time.h| 1 + arch/powerpc/kernel/exceptions-64s.S | 10 ++- arch/powerpc/kernel/idle_power7.S | 90 +- arch/powerpc/kernel/smp.c | 25 -- arch/powerpc/kernel/time.c | 90 +- arch/powerpc/platforms/cell/interrupt.c| 2 +- arch/powerpc/platforms/powernv/opal-wrappers.S | 1 + arch/powerpc/platforms/ps3/smp.c | 2 +- drivers/cpuidle/cpuidle-powernv.c | 102 ++--- 13 files changed, 253 insertions(+), 77 deletions(-) ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
RE: [PATCH 2/2] Make the diu driver work without board level initilization
Thanks, This has been fixed in the update version, please help to review it at: http://patchwork.ozlabs.org/patch/335225/ I forgot to add the V2 information in the subject in the update patch so this may confuse the reviewer, sorry for that. It is not fixed in that patch (or did you link the wrong version?). You should never use \ to continue a line in C, other than in macros. Further, it is not permitted to wrap kernel output strings. This is an exception to the 80-column rule. Checkpatch should have told you this. [Jason Jin-R64188] Thanks for pointing out this, I confused the internal version and external version. I'll fix it in next version. Thanks. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] powerpc, ptrace: Add few more ptrace request macros
Anshuman Khandual khand...@linux.vnet.ibm.com wrote:
This patch adds few more ptrace request macros expanding
the existing capability. These ptrace requests macros can
be classified into two categories.
Why is this only an RFC?
Also, please share the test case that you wrote for this.
Mikey
(1) Transactional memory
/* TM special purpose registers */
PTRACE_GETTM_SPRREGS
PTRACE_SETTM_SPRREGS
/* Checkpointed GPR registers */
PTRACE_GETTM_CGPRREGS
PTRACE_SETTM_CGPRREGS
/* Checkpointed FPR registers */
PTRACE_GETTM_CFPRREGS
PTRACE_SETTM_CFPRREGS
/* Checkpointed VMX registers */
PTRACE_GETTM_CVMXREGS
PTRACE_SETTM_CVMXREGS
(2) Miscellaneous
/* TAR, PPR, DSCR registers */
PTRACE_GETMSCREGS
PTRACE_SETMSCREGS
This patch also adds mutliple new generic ELF core note sections in
this regard which can be listed as follows.
NT_PPC_TM_SPR /* Transactional memory specific registers */
NT_PPC_TM_CGPR /* Transactional memory checkpointed GPR */
NT_PPC_TM_CFPR /* Transactional memory checkpointed FPR */
NT_PPC_TM_CVMX /* Transactional memory checkpointed VMX */
NT_PPC_MISC /* Miscellaneous registers */
Signed-off-by: Anshuman Khandual khand...@linux.vnet.ibm.com
---
arch/powerpc/include/asm/switch_to.h | 8 +
arch/powerpc/include/uapi/asm/ptrace.h | 61 +++
arch/powerpc/kernel/process.c | 24 ++
arch/powerpc/kernel/ptrace.c | 658
+++--
include/uapi/linux/elf.h | 5 +
5 files changed, 729 insertions(+), 27 deletions(-)
diff --git a/arch/powerpc/include/asm/switch_to.h
b/arch/powerpc/include/asm/switch_to.h
index 0e83e7d..73e2601 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -80,6 +80,14 @@ static inline void flush_spe_to_thread(struct task_struct
*t)
}
#endif
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+extern void flush_tmreg_to_thread(struct task_struct *);
+#else
+static inline void flush_tmreg_to_thread(struct task_struct *t)
+{
+}
+#endif
+
static inline void clear_task_ebb(struct task_struct *t)
{
#ifdef CONFIG_PPC_BOOK3S_64
diff --git a/arch/powerpc/include/uapi/asm/ptrace.h
b/arch/powerpc/include/uapi/asm/ptrace.h
index 77d2ed3..fd962d6 100644
--- a/arch/powerpc/include/uapi/asm/ptrace.h
+++ b/arch/powerpc/include/uapi/asm/ptrace.h
@@ -190,6 +190,67 @@ struct pt_regs {
#define PPC_PTRACE_SETHWDEBUG0x88
#define PPC_PTRACE_DELHWDEBUG0x87
+/* Transactional memory registers */
+
+/*
+ * SPR
+ *
+ * struct data {
+ * u64 tm_tfhar;
+ * u64 tm_texasr;
+ * u64 tm_tfiar;
+ * unsigned long tm_orig_msr;
+ * u64 tm_tar;
+ * u64 tm_ppr;
+ * u64 tm_dscr;
+ * };
+ */
+#define PTRACE_GETTM_SPRREGS 0x70
+#define PTRACE_SETTM_SPRREGS 0x71
+
+/*
+ * Checkpointed GPR
+ *
+ * struct data {
+ * struct pt_regs ckpt_regs;
+ * };
+ */
+#define PTRACE_GETTM_CGPRREGS0x72
+#define PTRACE_SETTM_CGPRREGS0x73
+
+/*
+ * Checkpointed FPR
+ *
+ * struct data {
+ * u64 fpr[32];
+ * u64 fpscr;
+ * };
+ */
+#define PTRACE_GETTM_CFPRREGS0x74
+#define PTRACE_SETTM_CFPRREGS0x75
+
+/*
+ * Checkpointed VMX
+ *
+ * struct data {
+ * vector128 vr[32];
+ * vector128 vscr;
+ * unsigned long vrsave;
+ *};
+ */
+#define PTRACE_GETTM_CVMXREGS0x76
+#define PTRACE_SETTM_CVMXREGS0x77
+
+/* Miscellaneous registers */
+#define PTRACE_GETMSCREGS0x78
+#define PTRACE_SETMSCREGS0x79
+
+/*
+ * XXX: A note to application developers. The existing data layout
+ * of the above four ptrace requests can change when new registers
+ * are available for each category in forthcoming processors.
+ */
+
#ifndef __ASSEMBLY__
struct ppc_debug_info {
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index af064d2..e5dfd8e 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -673,6 +673,30 @@ static inline void __switch_to_tm(struct task_struct
*prev)
}
}
+void flush_tmreg_to_thread(struct task_struct *tsk)
+{
+ /*
+ * If task is not current, it should have been flushed
+ * already to it's thread_struct during __switch_to().
+ */
+ if (tsk != current)
+ return;
+
+ preempt_disable();
+ if (tsk-thread.regs) {
+ /*
+ * If we are still current, the TM state need to
+ * be flushed to thread_struct as it will be still
+ * present in the current cpu
+ */
+ if (MSR_TM_ACTIVE(tsk-thread.regs-msr)) {
+ __switch_to_tm(tsk);
+
Re: [PATCH bisect 2/2] ASoC: fsl_sai: Separately enable interrupts for Tx and Rx streams
On Tue, Apr 01, 2014 at 05:42:54PM +0100, Mark Brown wrote: On Tue, Apr 01, 2014 at 09:21:57PM +0800, Nicolin Chen wrote: Sir, I just rebased my for-next branch again and found that it's missing two applied patches: ASoC: fsl_sai: Add isr to deal with error flag and ASoC: fsl_sai: Improve fsl_sai_isr(), so that's why this PATCH-2 could not be applied against it as it needs the macro that's included in the patch ASoC: fsl_sai: Add isr to deal with error flag. Ah, those dropped out of -next due to the merge window. I've applied your new patch now. I can find them on the fsl-sai topic now. Thank you. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
[PATCH] power, sched: stop updating inside arch_update_cpu_topology() when nothing to be update
During the testing, we encounter below WARN followed by Oops: WARNING: at kernel/sched/core.c:6218 ... NIP [c0101660] .build_sched_domains+0x11d0/0x1200 LR [c0101358] .build_sched_domains+0xec8/0x1200 PACATMSCRATCH [8000f032] Call Trace: [c0001b103850] [c0101358] .build_sched_domains+0xec8/0x1200 [c0001b1039a0] [c010aad4] .partition_sched_domains+0x484/0x510 [c0001b103aa0] [c016d0a8] .rebuild_sched_domains+0x68/0xa0 [c0001b103b30] [c005cbf0] .topology_work_fn+0x10/0x30 ... Oops: Kernel access of bad area, sig: 11 [#1] ... NIP [c045c000] .__bitmap_weight+0x60/0xf0 LR [c010132c] .build_sched_domains+0xe9c/0x1200 PACATMSCRATCH [80029032] Call Trace: [c0001b1037a0] [c0288ff4] .kmem_cache_alloc_node_trace+0x184/0x3a0 [c0001b103850] [c010132c] .build_sched_domains+0xe9c/0x1200 [c0001b1039a0] [c010aad4] .partition_sched_domains+0x484/0x510 [c0001b103aa0] [c016d0a8] .rebuild_sched_domains+0x68/0xa0 [c0001b103b30] [c005cbf0] .topology_work_fn+0x10/0x30 ... This was caused by that 'sd-groups == NULL' after building groups, which was caused by the empty 'sd-span'. The cpu's domain contain nothing because the cpu was assigned to wrong node inside arch_update_cpu_topology() by calling update_lookup_table() with the uninitialized param, in the case when there is nothing to be update. Thus we should stop the updating in such cases, this patch will achieve this and fix the issue. CC: Benjamin Herrenschmidt b...@kernel.crashing.org CC: Paul Mackerras pau...@samba.org CC: Nathan Fontenot nf...@linux.vnet.ibm.com CC: Stephen Rothwell s...@canb.auug.org.au CC: Andrew Morton a...@linux-foundation.org CC: Robert Jennings r...@linux.vnet.ibm.com CC: Jesse Larrew jlar...@linux.vnet.ibm.com CC: Srivatsa S. Bhat srivatsa.b...@linux.vnet.ibm.com CC: Alistair Popple alist...@popple.id.au Signed-off-by: Michael Wang wang...@linux.vnet.ibm.com --- arch/powerpc/mm/numa.c |9 + 1 file changed, 9 insertions(+) diff --git a/arch/powerpc/mm/numa.c b/arch/powerpc/mm/numa.c index 30a42e2..6757690 100644 --- a/arch/powerpc/mm/numa.c +++ b/arch/powerpc/mm/numa.c @@ -1591,6 +1591,14 @@ int arch_update_cpu_topology(void) cpu = cpu_last_thread_sibling(cpu); } + /* +* The 'cpu_associativity_changes_mask' could be cleared if +* all the cpus it indicates won't change their node, in +* which case the 'updated_cpus' will be empty. +*/ + if (!cpumask_weight(updated_cpus)) + goto out; + stop_machine(update_cpu_topology, updates[0], updated_cpus); /* @@ -1612,6 +1620,7 @@ int arch_update_cpu_topology(void) changed = 1; } +out: kfree(updates); return changed; } -- 1.7.9.5 ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [RFC] powerpc, ptrace: Add few more ptrace request macros
On 04/02/2014 06:13 AM, Michael Neuling wrote: Anshuman Khandual khand...@linux.vnet.ibm.com wrote: This patch adds few more ptrace request macros expanding the existing capability. These ptrace requests macros can be classified into two categories. Why is this only an RFC? Looking for comments, suggestions, concerns from people. But looks like its bit big a patch to review at once. Also, please share the test case that you wrote for this. Will split the patch into multiple components, add the test case and send out again. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH REPOST v5 1/3] powernv, cpufreq: Select CPUFreq related Kconfig options for powernv
On Wed, 2014-04-02 at 00:03 +0200, Rafael J. Wysocki wrote: Rafael, are you going to take these or should I send them to Linus ? (I'd rather you take them :-) I can do that, but the timing is pretty bad. How urgent are they? To be honest pretty urgent. It's a new drop-in driver so it shouldn't be a huge deal. We have distros really waiting for this to hit upstream... But I'll leave that decision to you :-) Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [PATCH 1/1] mm: move FAULT_AROUND_ORDER to arch/
On Tuesday 25 March 2014 11:20 PM, Dave Hansen wrote: On 03/25/2014 10:36 AM, Kirill A. Shutemov wrote: +/* + * Fault around order is a control knob to decide the fault around pages. + * Default value is set to 0UL (disabled), but the arch can override it as + * desired. + */ +#ifndef FAULT_AROUND_ORDER +#define FAULT_AROUND_ORDER0UL +#endif FAULT_AROUND_ORDER == 0 case should be handled separately in do_read_fault(): no reason to go to do_fault_around() if we are going to fault in only one page. Isn't this the kind of thing we want to do in Kconfig? I am still investigating this option since this looks better. But it is taking time, my bad. I will get back on this. With Regards Maddy ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
Re: [git pull] Please pull powerpc.git merge branch
On Wed, 2014-04-02 at 10:34 +1100, Benjamin Herrenschmidt wrote: Hi Linus ! This time around, the powerpc merges are going to be a little bit more complicated than usual. Looks like I sent this one twice, one with merge and one with next in the subject. They are otherwise identical (it's next really). I though I had cancelled the sending of the first one with the bad subject but it looks like my mailer was faster than me. Cheers, Ben. ___ Linuxppc-dev mailing list Linuxppc-dev@lists.ozlabs.org https://lists.ozlabs.org/listinfo/linuxppc-dev
