Re: [llvm-commits] [llvm-gcc] REM Patch
I've applied this. Thanks! Evan On Nov 1, 2006, at 7:18 PM, Reid Spencer wrote: > Jim & all > > The attached patch should now be applied to llvm-gcc because the > corresponding REM patch for LLVM has been applied to CVS. This should > show up in llvm-gcc subversion repository in the next 24 hours. If you > can't wait that long and you're updating to LLVM CVS Head, apply it to > your working copy of llvm-gcc now. > > Thanks, > > Reid. > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/TestRunner.sh
Changes in directory llvm/test: TestRunner.sh updated: 1.12 -> 1.13 --- Log message: Add some documentation about the arguments. --- Diffs of the changes: (+3 -0) TestRunner.sh |3 +++ 1 files changed, 3 insertions(+) Index: llvm/test/TestRunner.sh diff -u llvm/test/TestRunner.sh:1.12 llvm/test/TestRunner.sh:1.13 --- llvm/test/TestRunner.sh:1.12Sat Jun 17 03:06:33 2006 +++ llvm/test/TestRunner.sh Wed Nov 1 21:37:39 2006 @@ -8,6 +8,9 @@ # # %s - Replaced with the input name of the program, or the program to # execute, as appropriate. +# %llvmgcc - llvm-gcc command +# %llvmgxx - llvm-g++ command +# %prcontext - prcontext.tcl script # FILENAME=$1 ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] [llvm-gcc] REM Patch
Jim & all The attached patch should now be applied to llvm-gcc because the corresponding REM patch for LLVM has been applied to CVS. This should show up in llvm-gcc subversion repository in the next 24 hours. If you can't wait that long and you're updating to LLVM CVS Head, apply it to your working copy of llvm-gcc now. Thanks, Reid. Index: gcc/llvm-convert.cpp === --- gcc/llvm-convert.cpp (revision 193) +++ gcc/llvm-convert.cpp (working copy) @@ -558,7 +558,12 @@ case RDIV_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::FDiv); break; - case TRUNC_MOD_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::Rem);break; + case TRUNC_MOD_EXPR: +if (TYPE_UNSIGNED(TREE_TYPE(exp))) + Result = EmitBinOp(exp, DestLoc, Instruction::URem); +else + Result = EmitBinOp(exp, DestLoc, Instruction::SRem); +break; case BIT_AND_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::And);break; case BIT_IOR_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::Or );break; case BIT_XOR_EXPR: Result = EmitBinOp(exp, DestLoc, Instruction::Xor);break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/test/Regression/CodeGen/Alpha/2006-11-01-vastart.ll
Changes in directory llvm/test/Regression/CodeGen/Alpha:
2006-11-01-vastart.ll added (r1.1)
---
Log message:
a regression :(
---
Diffs of the changes: (+18 -0)
2006-11-01-vastart.ll | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/test/Regression/CodeGen/Alpha/2006-11-01-vastart.ll
diff -c /dev/null llvm/test/Regression/CodeGen/Alpha/2006-11-01-vastart.ll:1.1
*** /dev/null Wed Nov 1 21:04:47 2006
--- llvm/test/Regression/CodeGen/Alpha/2006-11-01-vastart.llWed Nov 1
21:04:37 2006
***
*** 0
--- 1,18
+ ; RUN: llvm-as < %s | llc -march=alpha
+
+ target datalayout = "e-p:64:64"
+ target endian = little
+ target pointersize = 64
+ target triple = "alphaev67-unknown-linux-gnu"
+ %struct.va_list = type { sbyte*, int, int }
+
+ implementation ; Functions:
+
+ void %yyerror(int, ...) {
+ entry:
+ call void %llvm.va_start( %struct.va_list* null )
+ ret void
+ }
+
+ declare void %llvm.va_start(%struct.va_list*)
+
___
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[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaInstrInfo.td
Changes in directory llvm/lib/Target/Alpha:
AlphaISelLowering.cpp updated: 1.71 -> 1.72
AlphaInstrInfo.td updated: 1.133 -> 1.134
---
Log message:
fix 2006-11-01-vastart.ll
---
Diffs of the changes: (+5 -3)
AlphaISelLowering.cpp |2 +-
AlphaInstrInfo.td |6 --
2 files changed, 5 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.71
llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.72
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.71Tue Oct 31 10:49:55 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp Wed Nov 1 21:05:26 2006
@@ -565,7 +565,7 @@
case ISD::VASTART: {
SDOperand Chain = Op.getOperand(0);
SDOperand VAListP = Op.getOperand(1);
-SrcValueSDNode *VAListS = cast(Op.getOperand(3));
+SrcValueSDNode *VAListS = cast(Op.getOperand(2));
// vastart stores the address of the VarArgsBase and VarArgsOffset
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.133
llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.134
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.133 Tue Oct 31 17:46:56 2006
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Nov 1 21:05:26 2006
@@ -404,6 +404,7 @@
def JSR_COROUTINE : MbrForm< 0x1A, 0x03, (ops GPRC:$RD, GPRC:$RS,
s14imm:$DISP), "jsr_coroutine $RD,($RS),$DISP", s_jsr>; //Jump to subroutine
return
+
let OperandList = (ops GPRC:$RA, s64imm:$DISP, GPRC:$RB) in {
def LDQ : MForm<0x29, 0, 1, "ldq $RA,$DISP($RB)",
[(set GPRC:$RA, (load (add GPRC:$RB, immSExt16:$DISP)))],
s_ild>;
@@ -421,6 +422,8 @@
[(set GPRC:$RA, (zextloadi16 (add GPRC:$RB,
immSExt16:$DISP)))], s_ild>;
def LDWUr : MForm<0x0C, 0, 1, "ldwu $RA,$DISP($RB)\t\t!gprellow",
[(set GPRC:$RA, (zextloadi16 (Alpha_gprello
tglobaladdr:$DISP, GPRC:$RB)))], s_ild>;
+
+
def STB : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)",
[(truncstorei8 GPRC:$RA, (add GPRC:$RB, immSExt16:$DISP))],
s_ist>;
def STBr : MForm<0x0E, 1, 0, "stb $RA,$DISP($RB)\t\t!gprellow",
@@ -649,6 +652,7 @@
//misc FP selects
//Select double
+
def : Pat<(select (seteq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
(FCMOVNET F8RC:$sf, F8RC:$st, (CMPTEQ F8RC:$RA, F8RC:$RB))>;
def : Pat<(select (setoeq F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf),
@@ -976,8 +980,6 @@
//def UNPKBW : OForm< 0x1C, 0x34, "UNPKBW $RA,$RB,$RC">; //Unpack bytes to
words
//CVTLQ F-P 17.010 Convert longword to quadword
//CVTQL F-P 17.030 Convert quadword to longword
-//def AMASK: OForm< 0x11, 0x61, "AMASK $RA,$RB,$RC", []>; //Architecture
mask
-//def AMASKi : OFormL<0x11, 0x61, "AMASK $RA,$L,$RC", []>; //Architecture
mask
//Constant handling
___
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[llvm-commits] CVS: llvm/lib/Bytecode/Reader/Reader.cpp
Changes in directory llvm/lib/Bytecode/Reader: Reader.cpp updated: 1.200 -> 1.201 --- Log message: For PR950: http://llvm.org/PR950 : Replace the REM instruction with UREM, SREM and FREM. --- Diffs of the changes: (+13 -8) Reader.cpp | 21 + 1 files changed, 13 insertions(+), 8 deletions(-) Index: llvm/lib/Bytecode/Reader/Reader.cpp diff -u llvm/lib/Bytecode/Reader/Reader.cpp:1.200 llvm/lib/Bytecode/Reader/Reader.cpp:1.201 --- llvm/lib/Bytecode/Reader/Reader.cpp:1.200 Thu Oct 26 01:15:43 2006 +++ llvm/lib/Bytecode/Reader/Reader.cpp Wed Nov 1 19:53:58 2006 @@ -652,7 +652,14 @@ break; case 11: // Rem -Opcode = Instruction::Rem; + // As with "Div", make the signed/unsigned or floating point Rem + // instruction choice based on the type of the operands. + if (iType == 10 || iType == 11) +Opcode = Instruction::FRem; + else if (iType >= 2 && iType <= 9 && iType % 2 != 0) +Opcode = Instruction::SRem; + else +Opcode = Instruction::URem; break; case 12: // And Opcode = Instruction::And; @@ -1654,18 +1661,16 @@ else Opcode = Instruction::UDiv; break; - case 11: // Rem - // As with "Div", make the signed/unsigned Rem instruction choice based - // on the type of the instruction. + // As with "Div", make the signed/unsigned or floating point Rem + // instruction choice based on the type of the operands. if (ArgVec[0]->getType()->isFloatingPoint()) -Opcode = Instruction::Rem; +Opcode = Instruction::FRem; else if (ArgVec[0]->getType()->isSigned()) -Opcode = Instruction::Rem; +Opcode = Instruction::SRem; else -Opcode = Instruction::Rem; +Opcode = Instruction::URem; break; - case 12: // And Opcode = Instruction::And; break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/tools/llvm2cpp/CppWriter.cpp
Changes in directory llvm/tools/llvm2cpp: CppWriter.cpp updated: 1.18 -> 1.19 --- Log message: For PR950: http://llvm.org/PR950 : Replace the REM instruction with UREM, SREM and FREM. --- Diffs of the changes: (+9 -3) CppWriter.cpp | 12 +--- 1 files changed, 9 insertions(+), 3 deletions(-) Index: llvm/tools/llvm2cpp/CppWriter.cpp diff -u llvm/tools/llvm2cpp/CppWriter.cpp:1.18 llvm/tools/llvm2cpp/CppWriter.cpp:1.19 --- llvm/tools/llvm2cpp/CppWriter.cpp:1.18 Thu Oct 26 01:15:43 2006 +++ llvm/tools/llvm2cpp/CppWriter.cpp Wed Nov 1 19:53:59 2006 @@ -776,7 +776,9 @@ case Instruction::UDiv: Out << "getUDiv"; break; case Instruction::SDiv: Out << "getSDiv"; break; case Instruction::FDiv: Out << "getFDiv"; break; -case Instruction::Rem:Out << "getRem"; break; +case Instruction::URem: Out << "getURem"; break; +case Instruction::SRem: Out << "getSRem"; break; +case Instruction::FRem: Out << "getFRem"; break; case Instruction::And:Out << "getAnd"; break; case Instruction::Or: Out << "getOr"; break; case Instruction::Xor:Out << "getXor"; break; @@ -1026,7 +1028,9 @@ case Instruction::UDiv: case Instruction::SDiv: case Instruction::FDiv: -case Instruction::Rem: +case Instruction::URem: +case Instruction::SRem: +case Instruction::FRem: case Instruction::And: case Instruction::Or: case Instruction::Xor: @@ -1040,7 +1044,9 @@ case Instruction::UDiv:Out << "Instruction::UDiv"; break; case Instruction::SDiv:Out << "Instruction::SDiv"; break; case Instruction::FDiv:Out << "Instruction::FDiv"; break; -case Instruction::Rem: Out << "Instruction::Rem"; break; +case Instruction::URem:Out << "Instruction::URem"; break; +case Instruction::SRem:Out << "Instruction::SRem"; break; +case Instruction::FRem:Out << "Instruction::FRem"; break; case Instruction::And: Out << "Instruction::And"; break; case Instruction::Or: Out << "Instruction::Or"; break; case Instruction::Xor: Out << "Instruction::Xor"; break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/Constants.h Instruction.def
Changes in directory llvm/include/llvm: Constants.h updated: 1.92 -> 1.93 Instruction.def updated: 1.20 -> 1.21 --- Log message: For PR950: http://llvm.org/PR950 : Replace the REM instruction with UREM, SREM and FREM. --- Diffs of the changes: (+44 -40) Constants.h |4 ++ Instruction.def | 80 2 files changed, 44 insertions(+), 40 deletions(-) Index: llvm/include/llvm/Constants.h diff -u llvm/include/llvm/Constants.h:1.92 llvm/include/llvm/Constants.h:1.93 --- llvm/include/llvm/Constants.h:1.92 Thu Oct 26 14:13:30 2006 +++ llvm/include/llvm/Constants.h Wed Nov 1 19:53:58 2006 @@ -551,7 +551,9 @@ static Constant *getUDiv(Constant *C1, Constant *C2); static Constant *getSDiv(Constant *C1, Constant *C2); static Constant *getFDiv(Constant *C1, Constant *C2); - static Constant *getRem(Constant *C1, Constant *C2); + static Constant *getURem(Constant *C1, Constant *C2); // unsigned rem + static Constant *getSRem(Constant *C1, Constant *C2); // signed rem + static Constant *getFRem(Constant *C1, Constant *C2); static Constant *getAnd(Constant *C1, Constant *C2); static Constant *getOr(Constant *C1, Constant *C2); static Constant *getXor(Constant *C1, Constant *C2); Index: llvm/include/llvm/Instruction.def diff -u llvm/include/llvm/Instruction.def:1.20 llvm/include/llvm/Instruction.def:1.21 --- llvm/include/llvm/Instruction.def:1.20 Thu Oct 26 01:15:43 2006 +++ llvm/include/llvm/Instruction.def Wed Nov 1 19:53:58 2006 @@ -90,53 +90,55 @@ // Standard binary operators... FIRST_BINARY_INST( 7) -HANDLE_BINARY_INST( 7, Add , BinaryOperator) -HANDLE_BINARY_INST( 8, Sub , BinaryOperator) -HANDLE_BINARY_INST( 9, Mul , BinaryOperator) -HANDLE_BINARY_INST(10, UDiv , BinaryOperator) -HANDLE_BINARY_INST(11, SDiv , BinaryOperator) -HANDLE_BINARY_INST(12, FDiv , BinaryOperator) -HANDLE_BINARY_INST(13, Rem , BinaryOperator) +HANDLE_BINARY_INST( 7, Add , BinaryOperator) +HANDLE_BINARY_INST( 8, Sub , BinaryOperator) +HANDLE_BINARY_INST( 9, Mul , BinaryOperator) +HANDLE_BINARY_INST(10, UDiv , BinaryOperator) +HANDLE_BINARY_INST(11, SDiv , BinaryOperator) +HANDLE_BINARY_INST(12, FDiv , BinaryOperator) +HANDLE_BINARY_INST(13, URem , BinaryOperator) +HANDLE_BINARY_INST(14, SRem , BinaryOperator) +HANDLE_BINARY_INST(15, FRem , BinaryOperator) // Logical operators... -HANDLE_BINARY_INST(14, And , BinaryOperator) -HANDLE_BINARY_INST(15, Or, BinaryOperator) -HANDLE_BINARY_INST(16, Xor , BinaryOperator) +HANDLE_BINARY_INST(16, And , BinaryOperator) +HANDLE_BINARY_INST(17, Or, BinaryOperator) +HANDLE_BINARY_INST(18, Xor , BinaryOperator) // Binary comparison operators... -HANDLE_BINARY_INST(17, SetEQ , SetCondInst) -HANDLE_BINARY_INST(18, SetNE , SetCondInst) -HANDLE_BINARY_INST(19, SetLE , SetCondInst) -HANDLE_BINARY_INST(20, SetGE , SetCondInst) -HANDLE_BINARY_INST(21, SetLT , SetCondInst) -HANDLE_BINARY_INST(22, SetGT , SetCondInst) - LAST_BINARY_INST(22) +HANDLE_BINARY_INST(19, SetEQ , SetCondInst) +HANDLE_BINARY_INST(20, SetNE , SetCondInst) +HANDLE_BINARY_INST(21, SetLE , SetCondInst) +HANDLE_BINARY_INST(22, SetGE , SetCondInst) +HANDLE_BINARY_INST(23, SetLT , SetCondInst) +HANDLE_BINARY_INST(24, SetGT , SetCondInst) + LAST_BINARY_INST(24) // Memory operators... - FIRST_MEMORY_INST(23) -HANDLE_MEMORY_INST(23, Malloc, MallocInst) // Heap management instructions -HANDLE_MEMORY_INST(24, Free , FreeInst ) -HANDLE_MEMORY_INST(25, Alloca, AllocaInst) // Stack management -HANDLE_MEMORY_INST(26, Load , LoadInst ) // Memory manipulation instrs -HANDLE_MEMORY_INST(27, Store , StoreInst ) -HANDLE_MEMORY_INST(28, GetElementPtr, GetElementPtrInst) - LAST_MEMORY_INST(28) + FIRST_MEMORY_INST(25) +HANDLE_MEMORY_INST(25, Malloc, MallocInst) // Heap management instructions +HANDLE_MEMORY_INST(26, Free , FreeInst ) +HANDLE_MEMORY_INST(27, Alloca, AllocaInst) // Stack management +HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs +HANDLE_MEMORY_INST(29, Store , StoreInst ) +HANDLE_MEMORY_INST(30, GetElementPtr, GetElementPtrInst) + LAST_MEMORY_INST(30) // Other operators... - FIRST_OTHER_INST(29) -HANDLE_OTHER_INST(29, PHI, PHINode) // PHI node instruction -HANDLE_OTHER_INST(30, Cast , CastInst ) // Type cast -HANDLE_OTHER_INST(31, Call , CallInst ) // Call a function -HANDLE_OTHER_INST(32, Shl, ShiftInst ) // Shift operations -HANDLE_OTHER_INST(33, Shr, ShiftInst ) -HANDLE_OTHER_INST(34, Select , SelectInst ) // select instruction -HANDLE_OTHER_INST(35, UserOp1, Instruction) // May be used internally in a pass -HANDLE_OTHER_INST(36, UserOp2, Instruction) -HANDLE_OTHER_INST(37, VAArg , VAArgInst ) // vaarg instruction -HANDLE_OTHER_INST(38, ExtractElement, ExtractElementInst)// extract from vector. -HANDLE_OTHER_INST(39, InsertElement, InsertElementInst) // insert into vector -HANDLE_OTHER_INST(40, ShuffleVector, Shuf
[llvm-commits] CVS: llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp
Changes in directory llvm/projects/Stacker/lib/compiler: StackerCompiler.cpp updated: 1.20 -> 1.21 --- Log message: For PR950: http://llvm.org/PR950 : Replace the REM instruction with UREM, SREM and FREM. --- Diffs of the changes: (+1 -1) StackerCompiler.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp diff -u llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.20 llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.21 --- llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp:1.20 Thu Oct 26 01:15:43 2006 +++ llvm/projects/Stacker/lib/compiler/StackerCompiler.cpp Wed Nov 1 19:53:59 2006 @@ -1052,7 +1052,7 @@ LoadInst* op1 = cast(pop_integer(bb)); LoadInst* op2 = cast(pop_integer(bb)); BinaryOperator* divop = -BinaryOperator::create( Instruction::Rem, op1, op2); +BinaryOperator::create( Instruction::SRem, op1, op2); bb->getInstList().push_back( divop ); push_value( bb, divop ); break; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/Scalar/InstructionCombining.cpp PredicateSimplifier.cpp Reassociate.cpp
Changes in directory llvm/lib/Transforms/Scalar:
InstructionCombining.cpp updated: 1.533 -> 1.534
PredicateSimplifier.cpp updated: 1.30 -> 1.31
Reassociate.cpp updated: 1.64 -> 1.65
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+134 -119)
InstructionCombining.cpp | 245 ---
PredicateSimplifier.cpp |4
Reassociate.cpp |4
3 files changed, 134 insertions(+), 119 deletions(-)
Index: llvm/lib/Transforms/Scalar/InstructionCombining.cpp
diff -u llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.533
llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.534
--- llvm/lib/Transforms/Scalar/InstructionCombining.cpp:1.533 Wed Nov 1
01:43:41 2006
+++ llvm/lib/Transforms/Scalar/InstructionCombining.cpp Wed Nov 1 19:53:58 2006
@@ -131,12 +131,16 @@
Instruction *visitAdd(BinaryOperator &I);
Instruction *visitSub(BinaryOperator &I);
Instruction *visitMul(BinaryOperator &I);
+Instruction *visitURem(BinaryOperator &I);
+Instruction *visitSRem(BinaryOperator &I);
+Instruction *visitFRem(BinaryOperator &I);
+Instruction *commonRemTransforms(BinaryOperator &I);
+Instruction *commonIRemTransforms(BinaryOperator &I);
Instruction *commonDivTransforms(BinaryOperator &I);
Instruction *commonIDivTransforms(BinaryOperator &I);
Instruction *visitUDiv(BinaryOperator &I);
Instruction *visitSDiv(BinaryOperator &I);
Instruction *visitFDiv(BinaryOperator &I);
-Instruction *visitRem(BinaryOperator &I);
Instruction *visitAnd(BinaryOperator &I);
Instruction *visitOr (BinaryOperator &I);
Instruction *visitXor(BinaryOperator &I);
@@ -2412,9 +2416,13 @@
return Result;
}
-Instruction *InstCombiner::visitRem(BinaryOperator &I) {
+/// This function implements the transforms on rem instructions that work
+/// regardless of the kind of rem instruction it is (urem, srem, or frem). It
+/// is used by the visitors to those instructions.
+/// @brief Transforms common to all three rem instructions
+Instruction *InstCombiner::commonRemTransforms(BinaryOperator &I) {
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
-
+
// 0 % X == 0, we don't need to preserve faults!
if (Constant *LHS = dyn_cast(Op0))
if (LHS->isNullValue())
@@ -2424,34 +2432,52 @@
return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType()));
if (isa(Op1))
return ReplaceInstUsesWith(I, Op1); // X % undef -> undef
-
- if (I.getType()->isSigned()) {
-if (Value *RHSNeg = dyn_castNegVal(Op1))
- if (!isa(RHSNeg) || !RHSNeg->getType()->isSigned() ||
- cast(RHSNeg)->getSExtValue() > 0) {
-// X % -Y -> X % Y
-AddUsesToWorkList(I);
-I.setOperand(1, RHSNeg);
+
+ // Handle cases involving: rem X, (select Cond, Y, Z)
+ if (SelectInst *SI = dyn_cast(Op1)) {
+// rem X, (Cond ? 0 : Y) -> rem X, Y. If the rem and the select are in
+// the same basic block, then we replace the select with Y, and the
+// condition of the select with false (if the cond value is in the same
+// BB). If the select has uses other than the div, this allows them to be
+// simplified also.
+if (Constant *ST = dyn_cast(SI->getOperand(1)))
+ if (ST->isNullValue()) {
+Instruction *CondI = dyn_cast(SI->getOperand(0));
+if (CondI && CondI->getParent() == I.getParent())
+ UpdateValueUsesWith(CondI, ConstantBool::getFalse());
+else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+ I.setOperand(1, SI->getOperand(2));
+else
+ UpdateValueUsesWith(SI, SI->getOperand(2));
+return &I;
+ }
+// Likewise for: rem X, (Cond ? Y : 0) -> rem X, Y
+if (Constant *ST = dyn_cast(SI->getOperand(2)))
+ if (ST->isNullValue()) {
+Instruction *CondI = dyn_cast(SI->getOperand(0));
+if (CondI && CondI->getParent() == I.getParent())
+ UpdateValueUsesWith(CondI, ConstantBool::getTrue());
+else if (I.getParent() != SI->getParent() || SI->hasOneUse())
+ I.setOperand(1, SI->getOperand(1));
+else
+ UpdateValueUsesWith(SI, SI->getOperand(1));
return &I;
}
-
-// If the top bits of both operands are zero (i.e. we can prove they are
-// unsigned inputs), turn this into a urem.
-uint64_t Mask = 1ULL << (I.getType()->getPrimitiveSizeInBits()-1);
-if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
- const Type *NTy = Op0->getType()->getUnsignedVersion();
- Value *LHS = InsertCastBefore(Op0, NTy, I);
- Value *RHS;
- if (Constant *R = dyn_cast(Op1))
-RHS = ConstantExpr::getCast(R, NTy);
- else
-RHS = InsertCastBefore(Op1, NTy, I);
- Instruction *Rem = BinaryOperator::createRem(LHS, RHS, I.getName());
- InsertNewInstBefore(Rem, I);
- return new CastInst
[llvm-commits] CVS: llvm/lib/AsmParser/Lexer.l llvmAsmParser.y
Changes in directory llvm/lib/AsmParser:
Lexer.l updated: 1.80 -> 1.81
llvmAsmParser.y updated: 1.271 -> 1.272
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+19 -8)
Lexer.l |5 -
llvmAsmParser.y | 22 +++---
2 files changed, 19 insertions(+), 8 deletions(-)
Index: llvm/lib/AsmParser/Lexer.l
diff -u llvm/lib/AsmParser/Lexer.l:1.80 llvm/lib/AsmParser/Lexer.l:1.81
--- llvm/lib/AsmParser/Lexer.l:1.80 Thu Oct 26 01:15:43 2006
+++ llvm/lib/AsmParser/Lexer.l Wed Nov 1 19:53:58 2006
@@ -261,7 +261,10 @@
udiv{ RET_TOK(BinaryOpVal, UDiv, UDIV); }
sdiv{ RET_TOK(BinaryOpVal, SDiv, SDIV); }
fdiv{ RET_TOK(BinaryOpVal, FDiv, FDIV); }
-rem { RET_TOK(BinaryOpVal, Rem, REM); }
+rem { RET_TOK_OBSOLETE(BinaryOpVal, URem, UREM); }
+urem{ RET_TOK(BinaryOpVal, URem, UREM); }
+srem{ RET_TOK(BinaryOpVal, SRem, SREM); }
+frem{ RET_TOK(BinaryOpVal, FRem, FREM); }
and { RET_TOK(BinaryOpVal, And, AND); }
or { RET_TOK(BinaryOpVal, Or , OR ); }
xor { RET_TOK(BinaryOpVal, Xor, XOR); }
Index: llvm/lib/AsmParser/llvmAsmParser.y
diff -u llvm/lib/AsmParser/llvmAsmParser.y:1.271
llvm/lib/AsmParser/llvmAsmParser.y:1.272
--- llvm/lib/AsmParser/llvmAsmParser.y:1.271Thu Oct 26 01:15:43 2006
+++ llvm/lib/AsmParser/llvmAsmParser.y Wed Nov 1 19:53:58 2006
@@ -836,7 +836,7 @@
// Depending on the opcode ..
switch (OI.opcode) {
default:
- GenerateError("Invalid Obsolete OpCode");
+ GenerateError("Invalid obsolete opCode (check Lexer.l)");
break;
case Instruction::UDiv:
// Handle cases where the opcode needs to change
@@ -845,12 +845,17 @@
else if (Ty->isSigned())
OI.opcode = Instruction::SDiv;
break;
+case Instruction::URem:
+ if (Ty->isFloatingPoint())
+OI.opcode = Instruction::FRem;
+ else if (Ty->isSigned())
+OI.opcode = Instruction::SRem;
+ break;
}
// Its not obsolete any more, we fixed it.
OI.obsolete = false;
}
-
-
+
// common code from the two 'RunVMAsmParser' functions
static Module* RunParser(Module * M) {
@@ -1113,7 +1118,7 @@
// Binary Operators
%type ArithmeticOps LogicalOps SetCondOps // Binops
Subcatagories
-%token ADD SUB MUL UDIV SDIV FDIV REM AND OR XOR
+%token ADD SUB MUL UDIV SDIV FDIV UREM SREM FREM AND OR XOR
%token SETLE SETGE SETLT SETGT SETEQ SETNE // Binary Comparators
// Memory Instructions
@@ -1151,7 +1156,7 @@
// Operations that are notably excluded from this list include:
// RET, BR, & SWITCH because they end basic blocks and are treated specially.
//
-ArithmeticOps: ADD | SUB | MUL | UDIV | SDIV | FDIV | REM ;
+ArithmeticOps: ADD | SUB | MUL | UDIV | SDIV | FDIV | UREM | SREM | FREM;
LogicalOps : AND | OR | XOR;
SetCondOps : SETLE | SETGE | SETLT | SETGT | SETEQ | SETNE;
@@ -2465,8 +2470,11 @@
!isa((*$2).get()))
GEN_ERROR(
"Arithmetic operator requires integer, FP, or packed operands!");
-if (isa((*$2).get()) && $1.opcode == Instruction::Rem)
- GEN_ERROR("Rem not supported on packed types!");
+if (isa((*$2).get()) &&
+($1.opcode == Instruction::URem ||
+ $1.opcode == Instruction::SRem ||
+ $1.opcode == Instruction::FRem))
+ GEN_ERROR("U/S/FRem not supported on packed types!");
// Upgrade the opcode from obsolete versions before we do anything with it.
sanitizeOpCode($1,*$2);
CHECK_FOR_ERROR;
___
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[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.56 -> 1.57
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+1 -1)
ScalarEvolution.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.56
llvm/lib/Analysis/ScalarEvolution.cpp:1.57
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.56 Wed Nov 1 15:53:12 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp Wed Nov 1 19:53:58 2006
@@ -2147,7 +2147,7 @@
if (SCEVConstant *StartC = dyn_cast(Start)) {
ConstantInt *StartCC = StartC->getValue();
Constant *StartNegC = ConstantExpr::getNeg(StartCC);
-Constant *Rem = ConstantExpr::getRem(StartNegC, StepC->getValue());
+Constant *Rem = ConstantExpr::getSRem(StartNegC, StepC->getValue());
if (Rem->isNullValue()) {
Constant *Result =ConstantExpr::getSDiv(StartNegC,StepC->getValue());
return SCEVUnknown::get(Result);
___
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[llvm-commits] CVS: llvm/docs/LangRef.html
Changes in directory llvm/docs: LangRef.html updated: 1.159 -> 1.160 --- Log message: For PR950: http://llvm.org/PR950 : Replace the REM instruction with UREM, SREM and FREM. --- Diffs of the changes: (+57 -13) LangRef.html | 70 --- 1 files changed, 57 insertions(+), 13 deletions(-) Index: llvm/docs/LangRef.html diff -u llvm/docs/LangRef.html:1.159 llvm/docs/LangRef.html:1.160 --- llvm/docs/LangRef.html:1.159Thu Oct 26 01:15:43 2006 +++ llvm/docs/LangRef.html Wed Nov 1 19:53:58 2006 @@ -80,7 +80,9 @@ 'udiv' Instruction 'sdiv' Instruction 'fdiv' Instruction - 'rem' Instruction + 'urem' Instruction + 'srem' Instruction + 'frem' Instruction 'setcc' Instructions @@ -1699,30 +1701,72 @@ - 'rem' + 'urem' Instruction + + +Syntax: += urem , ; yields {ty}:result + +Overview: +The 'urem' instruction returns the remainder from the +unsigned division of its two arguments. +Arguments: +The two arguments to the 'urem' instruction must be +integer values. Both arguments must have identical +types. +Semantics: +This instruction returns the unsigned integer remainder of a division. +This instruction always performs an unsigned division to get the remainder, +regardless of whether the arguments are unsigned or not. +Example: + = urem uint 4, %var ; yields {uint}:result = 4 % %var + + + + + 'srem' Instruction Syntax: - = rem , ; yields {ty}:result + = srem , ; yields {ty}:result Overview: -The 'rem' instruction returns the remainder from the -division of its two operands. +The 'srem' instruction returns the remainder from the +signed division of its two operands. Arguments: -The two arguments to the 'rem' instruction must be either integer or floating point -values. -This instruction can also take packed versions of the values. -Both arguments must have identical types. +The two arguments to the 'srem' instruction must be +integer values. Both arguments must have identical +types. Semantics: -This returns the remainder of a division (where the result +This instruction returns the remainder of a division (where the result has the same sign as the divisor), not the modulus (where the result has the same sign as the dividend) of a value. For more information about the difference, see http://mathforum.org/dr.math/problems/anne.4.28.99.html";>The Math Forum. Example: - = rem int 4, %var ; yields {int}:result = 4 % %var + = srem int 4, %var ; yields {int}:result = 4 % %var + + + + + 'frem' +Instruction + +Syntax: + = frem , ; yields {ty}:result + +Overview: +The 'frem' instruction returns the remainder from the +division of its two operands. +Arguments: +The two arguments to the 'frem' instruction must be +floating point values. Both arguments must have +identical types. +Semantics: +This instruction returns the remainder of a division. +Example: + = frem float 4.0, %var ; yields {float}:result = 4.0 % %var @@ -3956,7 +4000,7 @@ mailto:[EMAIL PROTECTED]">Chris Lattner http://llvm.org";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/10/26 06:15:43 $ + Last modified: $Date: 2006/11/02 01:53:58 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/VMCore/ConstantFolding.cpp Constants.cpp Instruction.cpp Instructions.cpp
Changes in directory llvm/lib/VMCore:
ConstantFolding.cpp updated: 1.95 -> 1.96
Constants.cpp updated: 1.168 -> 1.169
Instruction.cpp updated: 1.55 -> 1.56
Instructions.cpp updated: 1.44 -> 1.45
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+108 -47)
ConstantFolding.cpp | 92
Constants.cpp | 38 -
Instruction.cpp |8 +++-
Instructions.cpp| 17 -
4 files changed, 108 insertions(+), 47 deletions(-)
Index: llvm/lib/VMCore/ConstantFolding.cpp
diff -u llvm/lib/VMCore/ConstantFolding.cpp:1.95
llvm/lib/VMCore/ConstantFolding.cpp:1.96
--- llvm/lib/VMCore/ConstantFolding.cpp:1.95Thu Oct 26 01:15:43 2006
+++ llvm/lib/VMCore/ConstantFolding.cpp Wed Nov 1 19:53:58 2006
@@ -40,10 +40,12 @@
virtual Constant *add(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *sub(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *mul(const Constant *V1, const Constant *V2) const = 0;
+virtual Constant *urem(const Constant *V1, const Constant *V2) const = 0;
+virtual Constant *srem(const Constant *V1, const Constant *V2) const = 0;
+virtual Constant *frem(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *udiv(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *sdiv(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *fdiv(const Constant *V1, const Constant *V2) const = 0;
-virtual Constant *rem(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *op_and(const Constant *V1, const Constant *V2) const = 0;
virtual Constant *op_or (const Constant *V1, const Constant *V2) const = 0;
virtual Constant *op_xor(const Constant *V1, const Constant *V2) const = 0;
@@ -117,8 +119,14 @@
virtual Constant *fdiv(const Constant *V1, const Constant *V2) const {
return SubClassName::FDiv((const ArgType *)V1, (const ArgType *)V2);
}
- virtual Constant *rem(const Constant *V1, const Constant *V2) const {
-return SubClassName::Rem((const ArgType *)V1, (const ArgType *)V2);
+ virtual Constant *urem(const Constant *V1, const Constant *V2) const {
+return SubClassName::URem((const ArgType *)V1, (const ArgType *)V2);
+ }
+ virtual Constant *srem(const Constant *V1, const Constant *V2) const {
+return SubClassName::SRem((const ArgType *)V1, (const ArgType *)V2);
+ }
+ virtual Constant *frem(const Constant *V1, const Constant *V2) const {
+return SubClassName::FRem((const ArgType *)V1, (const ArgType *)V2);
}
virtual Constant *op_and(const Constant *V1, const Constant *V2) const {
return SubClassName::And((const ArgType *)V1, (const ArgType *)V2);
@@ -192,7 +200,9 @@
static Constant *SDiv(const ArgType *V1, const ArgType *V2) { return 0; }
static Constant *UDiv(const ArgType *V1, const ArgType *V2) { return 0; }
static Constant *FDiv(const ArgType *V1, const ArgType *V2) { return 0; }
- static Constant *Rem (const ArgType *V1, const ArgType *V2) { return 0; }
+ static Constant *URem(const ArgType *V1, const ArgType *V2) { return 0; }
+ static Constant *SRem(const ArgType *V1, const ArgType *V2) { return 0; }
+ static Constant *FRem(const ArgType *V1, const ArgType *V2) { return 0; }
static Constant *And (const ArgType *V1, const ArgType *V2) { return 0; }
static Constant *Or (const ArgType *V1, const ArgType *V2) { return 0; }
static Constant *Xor (const ArgType *V1, const ArgType *V2) { return 0; }
@@ -392,8 +402,14 @@
static Constant *FDiv(const ConstantPacked *V1, const ConstantPacked *V2) {
return EvalVectorOp(V1, V2, ConstantExpr::getFDiv);
}
- static Constant *Rem(const ConstantPacked *V1, const ConstantPacked *V2) {
-return EvalVectorOp(V1, V2, ConstantExpr::getRem);
+ static Constant *URem(const ConstantPacked *V1, const ConstantPacked *V2) {
+return EvalVectorOp(V1, V2, ConstantExpr::getURem);
+ }
+ static Constant *SRem(const ConstantPacked *V1, const ConstantPacked *V2) {
+return EvalVectorOp(V1, V2, ConstantExpr::getSRem);
+ }
+ static Constant *FRem(const ConstantPacked *V1, const ConstantPacked *V2) {
+return EvalVectorOp(V1, V2, ConstantExpr::getFRem);
}
static Constant *And(const ConstantPacked *V1, const ConstantPacked *V2) {
return EvalVectorOp(V1, V2, ConstantExpr::getAnd);
@@ -510,30 +526,36 @@
#undef DEF_CAST
static Constant *UDiv(const ConstantInt *V1, const ConstantInt *V2) {
-if (V2->isNullValue())
+if (V2->isNullValue()) // X / 0
return 0;
BuiltinType R = (BuiltinType)(V1->getZExtValue() / V2->getZExtValue());
return ConstantInt::get(*Ty, R);
}
static Constant *SDiv(const ConstantInt *V1, const ConstantInt *V2) {
-if (V2->isNullValue())
+if (V2->isNullValue()) // X / 0
ret
[llvm-commits] CVS: llvm/lib/Target/CBackend/Writer.cpp
Changes in directory llvm/lib/Target/CBackend:
Writer.cpp updated: 1.276 -> 1.277
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+28 -10)
Writer.cpp | 38 --
1 files changed, 28 insertions(+), 10 deletions(-)
Index: llvm/lib/Target/CBackend/Writer.cpp
diff -u llvm/lib/Target/CBackend/Writer.cpp:1.276
llvm/lib/Target/CBackend/Writer.cpp:1.277
--- llvm/lib/Target/CBackend/Writer.cpp:1.276 Thu Oct 26 01:17:40 2006
+++ llvm/lib/Target/CBackend/Writer.cpp Wed Nov 1 19:53:58 2006
@@ -593,7 +593,9 @@
case Instruction::SDiv:
case Instruction::UDiv:
case Instruction::FDiv:
-case Instruction::Rem:
+case Instruction::URem:
+case Instruction::SRem:
+case Instruction::FRem:
case Instruction::And:
case Instruction::Or:
case Instruction::Xor:
@@ -613,10 +615,12 @@
case Instruction::Add: Out << " + "; break;
case Instruction::Sub: Out << " - "; break;
case Instruction::Mul: Out << " * "; break;
+ case Instruction::URem:
+ case Instruction::SRem:
+ case Instruction::FRem: Out << " % "; break;
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::FDiv: Out << " / "; break;
- case Instruction::Rem: Out << " % "; break;
case Instruction::And: Out << " & "; break;
case Instruction::Or: Out << " | "; break;
case Instruction::Xor: Out << " ^ "; break;
@@ -825,8 +829,12 @@
bool Result = false;
const Type* Ty = CE->getOperand(0)->getType();
switch (CE->getOpcode()) {
- case Instruction::UDiv: Result = Ty->isSigned(); break;
- case Instruction::SDiv: Result = Ty->isUnsigned(); break;
+ case Instruction::UDiv:
+ case Instruction::URem:
+Result = Ty->isSigned(); break;
+ case Instruction::SDiv:
+ case Instruction::SRem:
+Result = Ty->isUnsigned(); break;
default: break;
}
if (Result) {
@@ -856,13 +864,16 @@
// for most instructions, it doesn't matter
break;
case Instruction::UDiv:
- // For UDiv to have unsigned operands
+case Instruction::URem:
+ // For UDiv/URem get correct type
if (OpTy->isSigned()) {
OpTy = OpTy->getUnsignedVersion();
shouldCast = true;
}
break;
case Instruction::SDiv:
+case Instruction::SRem:
+ // For SDiv/SRem get correct type
if (OpTy->isUnsigned()) {
OpTy = OpTy->getSignedVersion();
shouldCast = true;
@@ -919,8 +930,12 @@
bool Result = false;
const Type* Ty = I.getOperand(0)->getType();
switch (I.getOpcode()) {
- case Instruction::UDiv: Result = Ty->isSigned(); break;
- case Instruction::SDiv: Result = Ty->isUnsigned(); break;
+ case Instruction::UDiv:
+ case Instruction::URem:
+Result = Ty->isSigned(); break;
+ case Instruction::SDiv:
+ case Instruction::SRem:
+Result = Ty->isUnsigned(); break;
default: break;
}
if (Result) {
@@ -950,6 +965,7 @@
// for most instructions, it doesn't matter
break;
case Instruction::UDiv:
+case Instruction::URem:
// For UDiv to have unsigned operands
if (OpTy->isSigned()) {
OpTy = OpTy->getUnsignedVersion();
@@ -957,6 +973,7 @@
}
break;
case Instruction::SDiv:
+case Instruction::SRem:
if (OpTy->isUnsigned()) {
OpTy = OpTy->getSignedVersion();
shouldCast = true;
@@ -1774,8 +1791,7 @@
Out << "-(";
writeOperand(BinaryOperator::getNegArgument(cast(&I)));
Out << ")";
- } else if (I.getOpcode() == Instruction::Rem &&
- I.getType()->isFloatingPoint()) {
+ } else if (I.getOpcode() == Instruction::FRem) {
// Output a call to fmod/fmodf instead of emitting a%b
if (I.getType() == Type::FloatTy)
Out << "fmodf(";
@@ -1800,10 +1816,12 @@
case Instruction::Add: Out << " + "; break;
case Instruction::Sub: Out << " - "; break;
case Instruction::Mul: Out << '*'; break;
+case Instruction::URem:
+case Instruction::SRem:
+case Instruction::FRem: Out << '%'; break;
case Instruction::UDiv:
case Instruction::SDiv:
case Instruction::FDiv: Out << '/'; break;
-case Instruction::Rem: Out << '%'; break;
case Instruction::And: Out << " & "; break;
case Instruction::Or: Out << " | "; break;
case Instruction::Xor: Out << " ^ "; break;
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.313 -> 1.314
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+4 -8)
SelectionDAGISel.cpp | 12
1 files changed, 4 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.313
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.314
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.313Wed Nov 1
19:41:49 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 1 19:53:58 2006
@@ -528,16 +528,12 @@
else
visitIntBinary(I, ISD::MUL, ISD::VMUL);
}
+ void visitURem(User &I) { visitIntBinary(I, ISD::UREM, 0); }
+ void visitSRem(User &I) { visitIntBinary(I, ISD::SREM, 0); }
+ void visitFRem(User &I) { visitFPBinary (I, ISD::FREM, 0); }
void visitUDiv(User &I) { visitIntBinary(I, ISD::UDIV, ISD::VUDIV); }
void visitSDiv(User &I) { visitIntBinary(I, ISD::SDIV, ISD::VSDIV); }
- void visitFDiv(User &I) { visitFPBinary(I, ISD::FDIV, ISD::VSDIV); }
- void visitRem(User &I) {
-const Type *Ty = I.getType();
-if (Ty->isFloatingPoint())
- visitFPBinary(I, ISD::FREM, 0);
-else
- visitIntBinary(I, Ty->isSigned() ? ISD::SREM : ISD::UREM, 0);
- }
+ void visitFDiv(User &I) { visitFPBinary (I, ISD::FDIV, ISD::VSDIV); }
void visitAnd(User &I) { visitIntBinary(I, ISD::AND, ISD::VAND); }
void visitOr (User &I) { visitIntBinary(I, ISD::OR, ISD::VOR); }
void visitXor(User &I) { visitIntBinary(I, ISD::XOR, ISD::VXOR); }
___
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[llvm-commits] CVS: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
Changes in directory llvm/lib/ExecutionEngine/Interpreter:
Execution.cpp updated: 1.143 -> 1.144
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+50 -12)
Execution.cpp | 62 ++
1 files changed, 50 insertions(+), 12 deletions(-)
Index: llvm/lib/ExecutionEngine/Interpreter/Execution.cpp
diff -u llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.143
llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.144
--- llvm/lib/ExecutionEngine/Interpreter/Execution.cpp:1.143Tue Oct 31
21:45:43 2006
+++ llvm/lib/ExecutionEngine/Interpreter/Execution.cpp Wed Nov 1 19:53:58 2006
@@ -48,6 +48,12 @@
const Type *Ty);
static GenericValue executeFDivInst(GenericValue Src1, GenericValue Src2,
const Type *Ty);
+static GenericValue executeURemInst(GenericValue Src1, GenericValue Src2,
+const Type *Ty);
+static GenericValue executeSRemInst(GenericValue Src1, GenericValue Src2,
+const Type *Ty);
+static GenericValue executeFRemInst(GenericValue Src1, GenericValue Src2,
+const Type *Ty);
static GenericValue executeAndInst(GenericValue Src1, GenericValue Src2,
const Type *Ty);
static GenericValue executeOrInst(GenericValue Src1, GenericValue Src2,
@@ -105,10 +111,18 @@
return executeFDivInst(getOperandValue(CE->getOperand(0), SF),
getOperandValue(CE->getOperand(1), SF),
CE->getOperand(0)->getType());
- case Instruction::Rem:
-return executeRemInst(getOperandValue(CE->getOperand(0), SF),
+ case Instruction::URem:
+return executeURemInst(getOperandValue(CE->getOperand(0), SF),
getOperandValue(CE->getOperand(1), SF),
CE->getOperand(0)->getType());
+ case Instruction::SRem:
+return executeSRemInst(getOperandValue(CE->getOperand(0), SF),
+ getOperandValue(CE->getOperand(1), SF),
+ CE->getOperand(0)->getType());
+ case Instruction::FRem:
+return executeFRemInst(getOperandValue(CE->getOperand(0), SF),
+ getOperandValue(CE->getOperand(1), SF),
+ CE->getOperand(0)->getType());
case Instruction::And:
return executeAndInst(getOperandValue(CE->getOperand(0), SF),
getOperandValue(CE->getOperand(1), SF),
@@ -300,18 +314,40 @@
return Dest;
}
-static GenericValue executeRemInst(GenericValue Src1, GenericValue Src2,
+static GenericValue executeURemInst(GenericValue Src1, GenericValue Src2,
+ const Type *Ty) {
+ GenericValue Dest;
+ switch (Ty->getTypeID()) {
+IMPLEMENT_SIGNLESS_BINOP(%, UByte, SByte);
+IMPLEMENT_SIGNLESS_BINOP(%, UShort, Short);
+IMPLEMENT_SIGNLESS_BINOP(%, UInt, Int);
+IMPLEMENT_SIGNLESS_BINOP(%, ULong, Long);
+ default:
+std::cout << "Unhandled type for URem instruction: " << *Ty << "\n";
+abort();
+ }
+ return Dest;
+}
+
+static GenericValue executeSRemInst(GenericValue Src1, GenericValue Src2,
+ const Type *Ty) {
+ GenericValue Dest;
+ switch (Ty->getTypeID()) {
+IMPLEMENT_SIGNLESS_BINOP(%, SByte, UByte);
+IMPLEMENT_SIGNLESS_BINOP(%, Short, UShort);
+IMPLEMENT_SIGNLESS_BINOP(%, Int, UInt);
+IMPLEMENT_SIGNLESS_BINOP(%, Long, ULong);
+ default:
+std::cout << "Unhandled type for Rem instruction: " << *Ty << "\n";
+abort();
+ }
+ return Dest;
+}
+
+static GenericValue executeFRemInst(GenericValue Src1, GenericValue Src2,
const Type *Ty) {
GenericValue Dest;
switch (Ty->getTypeID()) {
-IMPLEMENT_BINARY_OPERATOR(%, UByte);
-IMPLEMENT_BINARY_OPERATOR(%, SByte);
-IMPLEMENT_BINARY_OPERATOR(%, UShort);
-IMPLEMENT_BINARY_OPERATOR(%, Short);
-IMPLEMENT_BINARY_OPERATOR(%, UInt);
-IMPLEMENT_BINARY_OPERATOR(%, Int);
-IMPLEMENT_BINARY_OPERATOR(%, ULong);
-IMPLEMENT_BINARY_OPERATOR(%, Long);
case Type::FloatTyID:
Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal);
break;
@@ -544,7 +580,9 @@
case Instruction::UDiv: R = executeUDivInst (Src1, Src2, Ty); break;
case Instruction::SDiv: R = executeSDivInst (Src1, Src2, Ty); break;
case Instruction::FDiv: R = executeFDivInst (Src1, Src2, Ty); break;
- case Instruction::Rem: R = executeRemInst (Src1, Src2, Ty); break;
+ case Instruction::URem: R = executeURemInst (Src1, Src2, Ty); break;
+ case Instruction::SRem: R = executeSRemInst (Src1, Src2, Ty); break;
+ case Instruction::FRem: R = executeFRemInst (Src1, Src2, Ty); break;
case Instruction::And: R = executeAndInst (Src1, Src2, Ty); break;
case Instructi
[llvm-commits] CVS: llvm/include/llvm/Support/PatternMatch.h
Changes in directory llvm/include/llvm/Support:
PatternMatch.h updated: 1.10 -> 1.11
---
Log message:
For PR950: http://llvm.org/PR950 :
Replace the REM instruction with UREM, SREM and FREM.
---
Diffs of the changes: (+14 -2)
PatternMatch.h | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Support/PatternMatch.h
diff -u llvm/include/llvm/Support/PatternMatch.h:1.10
llvm/include/llvm/Support/PatternMatch.h:1.11
--- llvm/include/llvm/Support/PatternMatch.h:1.10 Thu Oct 26 01:15:43 2006
+++ llvm/include/llvm/Support/PatternMatch.hWed Nov 1 19:53:58 2006
@@ -130,9 +130,21 @@
}
template
-inline BinaryOp_match m_Rem(const LHS &L,
+inline BinaryOp_match m_URem(const LHS &L,
+ const RHS &R) {
+ return BinaryOp_match(L, R);
+}
+
+template
+inline BinaryOp_match m_SRem(const LHS &L,
+ const RHS &R) {
+ return BinaryOp_match(L, R);
+}
+
+template
+inline BinaryOp_match m_FRem(const LHS &L,
const RHS &R) {
- return BinaryOp_match(L, R);
+ return BinaryOp_match(L, R);
}
template
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[llvm-commits] CVS: llvm/test/Regression/CodeGen/PowerPC/inlineasm-copy.ll
Changes in directory llvm/test/Regression/CodeGen/PowerPC:
inlineasm-copy.ll added (r1.1)
---
Log message:
new testcase
---
Diffs of the changes: (+14 -0)
inlineasm-copy.ll | 14 ++
1 files changed, 14 insertions(+)
Index: llvm/test/Regression/CodeGen/PowerPC/inlineasm-copy.ll
diff -c /dev/null llvm/test/Regression/CodeGen/PowerPC/inlineasm-copy.ll:1.1
*** /dev/null Wed Nov 1 19:45:38 2006
--- llvm/test/Regression/CodeGen/PowerPC/inlineasm-copy.ll Wed Nov 1
19:45:28 2006
***
*** 0
--- 1,14
+ ; RUN: llvm-as < %s | llc -march=ppc32 &&
+ ; RUN: llvm-as < %s | llc -march=ppc32 | not grep mr
+
+ int %test(int %Y, int %X) {
+ entry:
+ %tmp = tail call int asm "foo $0", "=r"( ) ;
[#uses=1]
+ ret int %tmp
+ }
+
+ int %test2(int %Y, int %X) {
+ entry:
+ %tmp1 = tail call int asm "foo $0, $1", "=r,r"( int %X )
; [#uses=1]
+ ret int %tmp1
+ }
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetLowering.h
Changes in directory llvm/include/llvm/Target:
TargetLowering.h updated: 1.83 -> 1.84
---
Log message:
generalize this api
---
Diffs of the changes: (+8 -2)
TargetLowering.h | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
Index: llvm/include/llvm/Target/TargetLowering.h
diff -u llvm/include/llvm/Target/TargetLowering.h:1.83
llvm/include/llvm/Target/TargetLowering.h:1.84
--- llvm/include/llvm/Target/TargetLowering.h:1.83 Tue Oct 31 13:40:43 2006
+++ llvm/include/llvm/Target/TargetLowering.h Wed Nov 1 19:39:10 2006
@@ -687,8 +687,14 @@
/// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
/// {edx}), return the register number and the register class for the
- /// register. This should only be used for C_Register constraints. On
error,
- /// this returns a register number of 0.
+ /// register.
+ ///
+ /// Given a register class constraint, like 'r', if this corresponds directly
+ /// to an LLVM register class, return a register of 0 and the register class
+ /// pointer.
+ ///
+ /// This should only be used for C_Register constraints. On error,
+ /// this returns a register number of 0 and a null register class pointer..
virtual std::pair
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
___
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[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h
Changes in directory llvm/lib/Target/PowerPC:
PPCISelLowering.cpp updated: 1.216 -> 1.217
PPCISelLowering.h updated: 1.53 -> 1.54
---
Log message:
Implement the getRegForInlineAsmConstraint method for PPC. With recent
sdisel changes, this eliminates a ton of copies around common inline asms.
For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
---
Diffs of the changes: (+29 -56)
PPCISelLowering.cpp | 75 +++-
PPCISelLowering.h | 10 --
2 files changed, 29 insertions(+), 56 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.216
llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.217
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.216 Tue Oct 31 13:40:43 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Wed Nov 1 19:44:04 2006
@@ -28,8 +28,8 @@
#include "llvm/Target/TargetOptions.h"
using namespace llvm;
-PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
- : TargetLowering(TM) {
+PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
+ : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
// Fold away setcc operations if possible.
setSetCCIsExpensive();
@@ -2600,63 +2600,34 @@
return TargetLowering::getConstraintType(ConstraintLetter);
}
-
-std::vector PPCTargetLowering::
-getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT::ValueType VT) const {
+std::pair
+PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
+MVT::ValueType VT) const {
if (Constraint.size() == 1) {
-switch (Constraint[0]) { // GCC RS6000 Constraint Letters
-default: break; // Unknown constriant letter
-case 'b':
- return make_vector(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
- PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
- PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31,
- 0);
-case 'r':
- return make_vector(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
- PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
- PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
- PPC::R12, PPC::R13, PPC::R14, PPC::R15,
- PPC::R16, PPC::R17, PPC::R18, PPC::R19,
- PPC::R20, PPC::R21, PPC::R22, PPC::R23,
- PPC::R24, PPC::R25, PPC::R26, PPC::R27,
- PPC::R28, PPC::R29, PPC::R30, PPC::R31,
- 0);
-case 'f':
- return make_vector(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
- PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
- PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
- PPC::F12, PPC::F13, PPC::F14, PPC::F15,
- PPC::F16, PPC::F17, PPC::F18, PPC::F19,
- PPC::F20, PPC::F21, PPC::F22, PPC::F23,
- PPC::F24, PPC::F25, PPC::F26, PPC::F27,
- PPC::F28, PPC::F29, PPC::F30, PPC::F31,
- 0);
+// GCC RS6000 Constraint Letters
+switch (Constraint[0]) {
+case 'b': // R1-R31
+case 'r': // R0-R31
+ if (VT == MVT::i64 && PPCSubTarget.isPPC64())
+return std::make_pair(0U, PPC::G8RCRegisterClass);
+ return std::make_pair(0U, PPC::GPRCRegisterClass);
+case 'f':
+ if (VT == MVT::f32)
+return std::make_pair(0U, PPC::F4RCRegisterClass);
+ else if (VT == MVT::f64)
+return std::make_pair(0U, PPC::F8RCRegisterClass);
+ break;
case 'v':
- return make_vector(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
- PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
- PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
- PPC::V12, PPC::V13, PPC::V14, PPC::V15,
- PPC::V16, PPC::V17, PPC::V18, PPC::V19,
- PPC::V20, PP
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAGISel.cpp updated: 1.312 -> 1.313
---
Log message:
Allow the getRegForInlineAsmConstraint method to return a register class with
no fixes physreg. Treat this as permission to use any register in the register
class. When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time. This eliminates a ton
of copies around common inline asms. For example:
int test2(int Y, int X) {
asm("foo %0, %1" : "=r"(X): "r"(X));
return X;
}
now compiles to:
_test2:
foo r3, r4
blr
instead of:
_test2:
mr r2, r4
foo r2, r2
mr r3, r2
blr
GCC produces:
_test2:
foo r4, r4
mr r3,r4
blr
---
Diffs of the changes: (+32 -4)
SelectionDAGISel.cpp | 36
1 files changed, 32 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.312
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.313
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.312Tue Oct 31
17:06:00 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Nov 1 19:41:49 2006
@@ -2231,6 +2231,8 @@
MVT::ValueType RegVT;
MVT::ValueType ValueVT = VT;
+ // If this is a constraint for a specific physical register, like {r17},
+ // assign it now.
if (PhysReg.first) {
if (VT == MVT::Other)
ValueVT = *PhysReg.second->vt_begin();
@@ -2260,10 +2262,36 @@
return RegsForValue(Regs, RegVT, ValueVT);
}
- // This is a reference to a register class. Allocate NumRegs consecutive,
- // available, registers from the class.
- std::vector RegClassRegs =
-TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+ // Otherwise, if this was a reference to an LLVM register class, create vregs
+ // for this reference.
+ std::vector RegClassRegs;
+ if (PhysReg.second) {
+// If this is an early clobber or tied register, our regalloc doesn't know
+// how to maintain the constraint. If it isn't, go ahead and create vreg
+// and let the regalloc do the right thing.
+if (!isOutReg || !isInReg) {
+ if (VT == MVT::Other)
+ValueVT = *PhysReg.second->vt_begin();
+ RegVT = *PhysReg.second->vt_begin();
+
+ // Create the appropriate number of virtual registers.
+ SSARegMap *RegMap = DAG.getMachineFunction().getSSARegMap();
+ for (; NumRegs; --NumRegs)
+Regs.push_back(RegMap->createVirtualRegister(PhysReg.second));
+
+ return RegsForValue(Regs, RegVT, ValueVT);
+}
+
+// Otherwise, we can't allocate it. Let the code below figure out how to
+// maintain these constraints.
+RegClassRegs.assign(PhysReg.second->begin(), PhysReg.second->end());
+
+ } else {
+// This is a reference to a register class that doesn't directly correspond
+// to an LLVM register class. Allocate NumRegs consecutive, available,
+// registers from the class.
+RegClassRegs = TLI.getRegClassForInlineAsmConstraint(ConstrCode, VT);
+ }
const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo();
MachineFunction &MF = *CurMBB->getParent();
___
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Re: [llvm-commits] REM Patch
On Wed, 2006-11-01 at 15:13 -0800, Chris Lattner wrote:
> On Oct 31, 2006, at 3:01 PM, Reid Spencer wrote:
>
> > Chris,
> >
> > Here's the patch for conversion of Rem -> [USF]Rem instructions.
> > Please
> > review at your earliest convenience. This passes dejagnu and llvm-test
> > suites. I've reviewed and modified this patch to make it as simple to
> > review as possible. Fortunately its a lot simpler than DIV.
>
> Looks good. Some comments: LangRef says that rem can be applied to
> vectors, but the asmparser rejects them, please update LangRef.
Done.
>
>
> Some comments about instcombine below, prefixed by ***. After making
> these changes and testing them, please commit.
>
> -Chris
>
>
> ***This xform (visitURem):
> +if (Instruction *Op0I = dyn_cast(Op0)) {
> + // X mul (C1 urem C2) --> 0 iff C1 urem C2 == 0
> + if (ConstantExpr::getURem(GetFactor(Op0I), RHS)->isNullValue())
> return ReplaceInstUsesWith(I, Constant::getNullValue
> (I.getType()));
> }
> }
>
> *** is doing "(X mul C1) urem C2 --> 0 iff C1 urem C2 == 0"
> please update the comment.
Done.
>
> This xform also applies in the srem case, where the code is copied,
> but the comment unmodified. Please move it to intcommon.
Done.
> if (Instruction *RHSI = dyn_cast(I.getOperand(1))) {
> -// Turn A % (C << N), where C is 2^k, into A & ((C << N)-1)
> [urem only].
> -if (I.getType()->isUnsigned() &&
> -RHSI->getOpcode() == Instruction::Shl &&
> -isa(RHSI->getOperand(0)) &&
> -RHSI->getOperand(0)->getType()->isUnsigned()) {
> +// Turn A urem (2^C << N) -> A & ((C << N)-1) [urem only].
> +if (RHSI->getOpcode() == Instruction::Shl &&
> +isa(RHSI->getOperand(0))) {
>
> *** Please change the comment back, your change is not correct. You
> can drop 'urem only'.
Done.
>
>
> + // If the top bits of both operands are zero (i.e. we can prove
> they are
> + // unsigned inputs), turn this into a urem.
> + uint64_t Mask = 1ULL << (I.getType()->getPrimitiveSizeInBits()-1);
> + if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
> +// X srem Y -> X urem Y, iff X and Y don't have sign bit set
> +return BinaryOperator::createURem(Op0, Op1, I.getName());;
> }
> *** ";;" -> ";"
Done.
>
> @@ -4564,41 +4608,24 @@ Instruction *InstCombiner::visitSetCondI
>
> // If the first operand is (add|sub|and|or|xor|rem) with a
> constant, and
> // the second operand is a constant, simplify a bit.
> if (BinaryOperator *BO = dyn_cast(Op0)) {
> switch (BO->getOpcode()) {
> -#if 0
> +case Instruction::URem:
> + break;
> *** No need for this case stmt, just remove it.
>
Done.
> case Instruction::SRem:
> // If we have a signed (X % (2^c)) == 0, turn it into an
> unsigned one.
> if (CI->isNullValue() && isa(BO->getOperand
> (1)) &&
> BO->hasOneUse()) {
> int64_t V = cast(BO->getOperand(1))-
> >getSExtValue();
> if (V > 1 && isPowerOf2_64(V)) {
> unsigned L2 = Log2_64(V);
> const Type *UTy = BO->getType()->getUnsignedVersion();
> Value *NewX = InsertNewInstBefore(new CastInst(BO-
> >getOperand(0),
>UTy,
> "tmp"), I);
> Constant *RHSCst = ConstantInt::get(UTy, 1ULL << L2);
> - Value *NewRem =InsertNewInstBefore
> (BinaryOperator::createRem(NewX,
> + Value *NewRem =InsertNewInstBefore
> (BinaryOperator::createURem(NewX,
> RHSCst, BO-
> >getName()), I);
> return BinaryOperator::create(I.getOpcode(), NewRem,
> Constant::getNullValue
> (UTy));
> }
> }
> *** There is no need to insert the casts here. It should just
> replace the srem with a urem in place, no need to change the sign of
> the inputs. The old code needed the casts because the sign of the
> operation was tied to the sign of the inputs.
Right. Done.
Reid.
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[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp VirtRegMap.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocSimple.cpp updated: 1.75 -> 1.76
VirtRegMap.cpp updated: 1.77 -> 1.78
---
Log message:
Rename
---
Diffs of the changes: (+2 -2)
RegAllocSimple.cpp |2 +-
VirtRegMap.cpp |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.75
llvm/lib/CodeGen/RegAllocSimple.cpp:1.76
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.75Wed Nov 1 17:06:55 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Wed Nov 1 17:18:32 2006
@@ -200,7 +200,7 @@
if (physReg == 0) {
if (op.isDef()) {
int TiedOp = TM->getInstrInfo()
- ->getTiedToSrcOperand(MI->getOpcode(), i);
+ ->findTiedToSrcOperand(MI->getOpcode(), i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.77
llvm/lib/CodeGen/VirtRegMap.cpp:1.78
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.77Wed Nov 1 17:06:55 2006
+++ llvm/lib/CodeGen/VirtRegMap.cpp Wed Nov 1 17:18:32 2006
@@ -821,7 +821,7 @@
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
-int TiedOp = TII->getTiedToSrcOperand(MI.getOpcode(), i);
+int TiedOp = TII->findTiedToSrcOperand(MI.getOpcode(), i);
if (TiedOp != -1)
PhysReg = MI.getOperand(TiedOp).getReg();
else
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[llvm-commits] CVS: llvm/lib/Target/TargetInstrInfo.cpp
Changes in directory llvm/lib/Target:
TargetInstrInfo.cpp updated: 1.20 -> 1.21
---
Log message:
Rename
---
Diffs of the changes: (+3 -1)
TargetInstrInfo.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/TargetInstrInfo.cpp
diff -u llvm/lib/Target/TargetInstrInfo.cpp:1.20
llvm/lib/Target/TargetInstrInfo.cpp:1.21
--- llvm/lib/Target/TargetInstrInfo.cpp:1.20Wed Nov 1 17:00:31 2006
+++ llvm/lib/Target/TargetInstrInfo.cpp Wed Nov 1 17:14:15 2006
@@ -38,8 +38,10 @@
TargetInstrDescriptors = NULL; // reset global variable
}
+/// findTiedToSrcOperand - Returns the operand that is tied to the specified
+/// dest operand. Returns -1 if there isn't one.
int
-TargetInstrInfo::getTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
+TargetInstrInfo::findTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const
{
for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
if (i == OpNum)
continue;
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target: TargetInstrInfo.h updated: 1.101 -> 1.102 --- Log message: Rename --- Diffs of the changes: (+2 -2) TargetInstrInfo.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) Index: llvm/include/llvm/Target/TargetInstrInfo.h diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.101 llvm/include/llvm/Target/TargetInstrInfo.h:1.102 --- llvm/include/llvm/Target/TargetInstrInfo.h:1.101Wed Nov 1 16:59:52 2006 +++ llvm/include/llvm/Target/TargetInstrInfo.h Wed Nov 1 17:14:00 2006 @@ -240,9 +240,9 @@ return -1; } - /// getTiedToSrcOperand - Returns the operand that is tied to the specified + /// findTiedToSrcOperand - Returns the operand that is tied to the specified /// dest operand. Returns -1 if there isn't one. - int getTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const; + int findTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const; /// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL /// instruction if it has one. This is used by codegen passes that update ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] REM Patch
On Oct 31, 2006, at 3:01 PM, Reid Spencer wrote:
> Chris,
>
> Here's the patch for conversion of Rem -> [USF]Rem instructions.
> Please
> review at your earliest convenience. This passes dejagnu and llvm-test
> suites. I've reviewed and modified this patch to make it as simple to
> review as possible. Fortunately its a lot simpler than DIV.
Looks good. Some comments: LangRef says that rem can be applied to
vectors, but the asmparser rejects them, please update LangRef.
Some comments about instcombine below, prefixed by ***. After making
these changes and testing them, please commit.
-Chris
***This xform (visitURem):
+if (Instruction *Op0I = dyn_cast(Op0)) {
+ // X mul (C1 urem C2) --> 0 iff C1 urem C2 == 0
+ if (ConstantExpr::getURem(GetFactor(Op0I), RHS)->isNullValue())
return ReplaceInstUsesWith(I, Constant::getNullValue
(I.getType()));
}
}
*** is doing "(X mul C1) urem C2 --> 0 iff C1 urem C2 == 0"
please update the comment.
This xform also applies in the srem case, where the code is copied,
but the comment unmodified. Please move it to intcommon.
if (Instruction *RHSI = dyn_cast(I.getOperand(1))) {
-// Turn A % (C << N), where C is 2^k, into A & ((C << N)-1)
[urem only].
-if (I.getType()->isUnsigned() &&
-RHSI->getOpcode() == Instruction::Shl &&
-isa(RHSI->getOperand(0)) &&
-RHSI->getOperand(0)->getType()->isUnsigned()) {
+// Turn A urem (2^C << N) -> A & ((C << N)-1) [urem only].
+if (RHSI->getOpcode() == Instruction::Shl &&
+isa(RHSI->getOperand(0))) {
*** Please change the comment back, your change is not correct. You
can drop 'urem only'.
+ // If the top bits of both operands are zero (i.e. we can prove
they are
+ // unsigned inputs), turn this into a urem.
+ uint64_t Mask = 1ULL << (I.getType()->getPrimitiveSizeInBits()-1);
+ if (MaskedValueIsZero(Op1, Mask) && MaskedValueIsZero(Op0, Mask)) {
+// X srem Y -> X urem Y, iff X and Y don't have sign bit set
+return BinaryOperator::createURem(Op0, Op1, I.getName());;
}
*** ";;" -> ";"
@@ -4564,41 +4608,24 @@ Instruction *InstCombiner::visitSetCondI
// If the first operand is (add|sub|and|or|xor|rem) with a
constant, and
// the second operand is a constant, simplify a bit.
if (BinaryOperator *BO = dyn_cast(Op0)) {
switch (BO->getOpcode()) {
-#if 0
+case Instruction::URem:
+ break;
*** No need for this case stmt, just remove it.
case Instruction::SRem:
// If we have a signed (X % (2^c)) == 0, turn it into an
unsigned one.
if (CI->isNullValue() && isa(BO->getOperand
(1)) &&
BO->hasOneUse()) {
int64_t V = cast(BO->getOperand(1))-
>getSExtValue();
if (V > 1 && isPowerOf2_64(V)) {
unsigned L2 = Log2_64(V);
const Type *UTy = BO->getType()->getUnsignedVersion();
Value *NewX = InsertNewInstBefore(new CastInst(BO-
>getOperand(0),
UTy,
"tmp"), I);
Constant *RHSCst = ConstantInt::get(UTy, 1ULL << L2);
- Value *NewRem =InsertNewInstBefore
(BinaryOperator::createRem(NewX,
+ Value *NewRem =InsertNewInstBefore
(BinaryOperator::createURem(NewX,
RHSCst, BO-
>getName()), I);
return BinaryOperator::create(I.getOpcode(), NewRem,
Constant::getNullValue
(UTy));
}
}
*** There is no need to insert the casts here. It should just
replace the srem with a urem in place, no need to change the sign of
the inputs. The old code needed the casts because the sign of the
operation was tied to the sign of the inputs.
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/CondPropagate.cpp
Changes in directory llvm/lib/Transforms/Scalar:
CondPropagate.cpp updated: 1.7 -> 1.8
---
Log message:
There can be more than one PHINode at the start of the block.
---
Diffs of the changes: (+4 -5)
CondPropagate.cpp |9 -
1 files changed, 4 insertions(+), 5 deletions(-)
Index: llvm/lib/Transforms/Scalar/CondPropagate.cpp
diff -u llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.7
llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.8
--- llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.7Wed Nov 1 16:26:43 2006
+++ llvm/lib/Transforms/Scalar/CondPropagate.cppWed Nov 1 17:04:45 2006
@@ -196,11 +196,10 @@
// Get the old block we are threading through.
BasicBlock *OldSucc = FromBr->getSuccessor(0);
- // OldSucc had multiple successors. If ToBB has multiple predecessors, the
- // edge between them would be critical, which we already took care of.
- // If ToBB has single operand PHI node than take care of it here.
- if (isa(ToBB->begin())) {
-PHINode *PN = cast(ToBB->begin());
+ // OldSucc had multiple successors. If ToBB has multiple predecessors, then
+ // the edge between them would be critical, which we already took care of.
+ // If ToBB has single operand PHI node then take care of it here.
+ while (PHINode *PN = dyn_cast(ToBB->begin())) {
assert(PN->getNumIncomingValues() == 1 && "Critical Edge Found!");
PN->replaceAllUsesWith(PN->getIncomingValue(0));
PN->eraseFromParent();
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[llvm-commits] CVS: llvm/lib/CodeGen/RegAllocSimple.cpp TwoAddressInstructionPass.cpp VirtRegMap.cpp
Changes in directory llvm/lib/CodeGen:
RegAllocSimple.cpp updated: 1.74 -> 1.75
TwoAddressInstructionPass.cpp updated: 1.38 -> 1.39
VirtRegMap.cpp updated: 1.76 -> 1.77
---
Log message:
Two-address instructions no longer have to be A := A op C. Now any pair of dest
/ src operands can be tied together.
---
Diffs of the changes: (+144 -118)
RegAllocSimple.cpp| 17 +--
TwoAddressInstructionPass.cpp | 229 ++
VirtRegMap.cpp| 16 +-
3 files changed, 144 insertions(+), 118 deletions(-)
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.74
llvm/lib/CodeGen/RegAllocSimple.cpp:1.75
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.74Mon Sep 4 21:12:02 2006
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Wed Nov 1 17:06:55 2006
@@ -199,17 +199,20 @@
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
-if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
+int TiedOp = TM->getInstrInfo()
+ ->getTiedToSrcOperand(MI->getOpcode(), i);
+if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
- // must be same register number as the first operand
- // This maps a = b + c into b = b + c, and saves b into a's spot.
- assert(MI->getOperand(1).isRegister() &&
- MI->getOperand(1).getReg() &&
- MI->getOperand(1).isUse() &&
+ // must be same register number as the source operand that is
+ // tied to. This maps a = b + c into b = b + c, and saves b into
+ // a's spot.
+ assert(MI->getOperand(TiedOp).isRegister() &&
+ MI->getOperand(TiedOp).getReg() &&
+ MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");
- physReg = MI->getOperand(1).getReg();
+ physReg = MI->getOperand(TiedOp).getReg();
}
spillVirtReg(MBB, next(MI), virtualReg, physReg);
} else {
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.38
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.39
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.38 Mon Sep 4 21:12:02 2006
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Wed Nov 1 17:06:55 2006
@@ -95,122 +95,141 @@
mi != me; ++mi) {
unsigned opcode = mi->getOpcode();
- // ignore if it is not a two-address instruction
- if (!TII.isTwoAddrInstr(opcode))
-continue;
-
- ++NumTwoAddressInstrs;
- DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
- assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
- mi->getOperand(1).isUse() && "two address instruction invalid");
-
- // if the two operands are the same we just remove the use
- // and mark the def as def&use, otherwise we have to insert a copy.
- if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
-// rewrite:
-// a = b op c
-// to:
-// a = b
-// a = a op c
-unsigned regA = mi->getOperand(0).getReg();
-unsigned regB = mi->getOperand(1).getReg();
-
-assert(MRegisterInfo::isVirtualRegister(regA) &&
- MRegisterInfo::isVirtualRegister(regB) &&
- "cannot update physical register live information");
+ bool FirstTied = true;
+ for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
+int ti = TII.getOperandConstraint(opcode, si,
TargetInstrInfo::TIED_TO);
+if (ti == -1)
+ continue;
+
+if (FirstTied) {
+ ++NumTwoAddressInstrs;
+ DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
+}
+FirstTied = false;
+
+assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg()
&&
+ mi->getOperand(si).isUse() && "two address instruction
invalid");
+
+// if the two operands are the same we just remove the use
+// and mark the def as def&use, otherwise we have to insert a copy.
+if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
+ // rewrite:
+ // a = b op c
+ // to:
+ // a = b
+ // a = a op c
+ unsigned regA = mi->getOperand(ti).getReg();
+ unsigned regB = mi->getOperand(si).getReg();
+
+ assert(MRegisterInfo::isVirtualRegister(regA) &&
+ MRegisterInfo::isVirtualRegister(regB) &&
+ "cannot update physical register live information");
#ifndef NDEBUG
-// First, verify that we do not have a use of a in the instruction (a =
-// b + a for example) because our transformation will not work
[llvm-commits] CVS: llvm/utils/TableGen/CodeGenTarget.cpp
Changes in directory llvm/utils/TableGen:
CodeGenTarget.cpp updated: 1.70 -> 1.71
---
Log message:
Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else
throw an exception.
---
Diffs of the changes: (+3 -0)
CodeGenTarget.cpp |3 +++
1 files changed, 3 insertions(+)
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.70
llvm/utils/TableGen/CodeGenTarget.cpp:1.71
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.70 Tue Oct 31 18:27:05 2006
+++ llvm/utils/TableGen/CodeGenTarget.cpp Wed Nov 1 17:03:11 2006
@@ -280,6 +280,7 @@
assert(pos != std::string::npos && "Unrecognized constraint");
std::string Name = CStr.substr(1, pos); // Skip '$'
+ // TIED_TO: $src1 = $dst
const std::string delims(" \t");
std::string::size_type wpos = Name.find_first_of(delims);
if (wpos != std::string::npos)
@@ -291,6 +292,8 @@
if (wpos != std::string::npos)
Name = Name.substr(wpos+1);
unsigned TIdx = I->getOperandNamed(Name);
+ if (TIdx >= FIdx)
+throw "Illegal tied-to operand constraint '" + CStr + "'";
return std::make_pair(FIdx, (TIdx << 16) | 1);
}
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[llvm-commits] CVS: llvm/lib/Target/TargetInstrInfo.cpp
Changes in directory llvm/lib/Target:
TargetInstrInfo.cpp updated: 1.19 -> 1.20
---
Log message:
Added getTiedToSrcOperand() to check for two-address'ness.
---
Diffs of the changes: (+12 -0)
TargetInstrInfo.cpp | 12
1 files changed, 12 insertions(+)
Index: llvm/lib/Target/TargetInstrInfo.cpp
diff -u llvm/lib/Target/TargetInstrInfo.cpp:1.19
llvm/lib/Target/TargetInstrInfo.cpp:1.20
--- llvm/lib/Target/TargetInstrInfo.cpp:1.19Thu May 11 20:46:26 2006
+++ llvm/lib/Target/TargetInstrInfo.cpp Wed Nov 1 17:00:31 2006
@@ -38,6 +38,18 @@
TargetInstrDescriptors = NULL; // reset global variable
}
+int
+TargetInstrInfo::getTiedToSrcOperand(MachineOpCode Opc, unsigned OpNum) const {
+ for (unsigned i = 0, e = getNumOperands(Opc); i != e; ++i) {
+if (i == OpNum)
+ continue;
+int ti = getOperandConstraint(Opc, i, TIED_TO);
+if (ti == (int)OpNum)
+ return i;
+ }
+ return -1;
+}
+
// commuteInstruction - The default implementation of this method just
exchanges
// operand 1 and 2.
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[llvm-commits] CVS: llvm/include/llvm/Target/TargetInstrInfo.h
Changes in directory llvm/include/llvm/Target:
TargetInstrInfo.h updated: 1.100 -> 1.101
---
Log message:
Added getTiedToSrcOperand() to check for two-address'ness.
---
Diffs of the changes: (+5 -1)
TargetInstrInfo.h |6 +-
1 files changed, 5 insertions(+), 1 deletion(-)
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.100
llvm/include/llvm/Target/TargetInstrInfo.h:1.101
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.100Tue Oct 31 18:25:20 2006
+++ llvm/include/llvm/Target/TargetInstrInfo.h Wed Nov 1 16:59:52 2006
@@ -230,7 +230,7 @@
/// getOperandConstraint - Returns the value of the specific constraint if
/// it is set. Returns -1 if it is not set.
int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
- OperandConstraint Constraint) {
+ OperandConstraint Constraint) const {
assert(OpNum < get(Opcode).numOperands &&
"Invalid operand # of TargetInstrInfo");
if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) {
@@ -240,6 +240,10 @@
return -1;
}
+ /// getTiedToSrcOperand - Returns the operand that is tied to the specified
+ /// dest operand. Returns -1 if there isn't one.
+ int getTiedToSrcOperand(MachineOpCode Opcode, unsigned OpNum) const;
+
/// getDWARF_LABELOpcode - Return the opcode of the target's DWARF_LABEL
/// instruction if it has one. This is used by codegen passes that update
/// DWARF line number info as they modify the code.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
ScheduleDAGRRList.cpp updated: 1.16 -> 1.17
---
Log message:
Clean up.
---
Diffs of the changes: (+11 -5)
ScheduleDAGRRList.cpp | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.16
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.17
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.16Wed Nov 1
16:17:06 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Nov 1 16:39:30 2006
@@ -719,7 +719,14 @@
return SethiUllmanNumber;
unsigned Opc = SU->Node->getOpcode();
- if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
+ if (Opc == ISD::CopyFromReg && !isCopyFromLiveIn(SU))
+// CopyFromReg should be close to its def because it restricts allocation
+// choices. But if it is a livein then perhaps we want it closer to the
+// uses so it can be coalesced.
+SethiUllmanNumber = INT_MIN + 10;
+ else if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
+// CopyToReg should be close to its uses to facilitate coalescing and avoid
+// spilling.
SethiUllmanNumber = INT_MAX - 10;
else if (SU->NumSuccsLeft == 0)
// If SU does not have a use, i.e. it doesn't produce a value that would
@@ -727,10 +734,9 @@
// Give it a small SethiUllman number so it will be scheduled right before
its
// predecessors that it doesn't lengthen their live ranges.
SethiUllmanNumber = INT_MIN + 10;
- // FIXME: remove this else if? It seems to reduce register spills but often
- // ends up increasing runtime. Need to investigate.
- else if (SU->NumPredsLeft == 0 &&
- (Opc != ISD::CopyFromReg || isCopyFromLiveIn(SU)))
+ else if (SU->NumPredsLeft == 0)
+// If SU does not have a def, schedule it close to its uses because it does
+// not lengthen any live ranges.
SethiUllmanNumber = INT_MAX - 10;
else {
int Extra = 0;
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[llvm-commits] CVS: llvm/lib/Transforms/Scalar/CondPropagate.cpp
Changes in directory llvm/lib/Transforms/Scalar:
CondPropagate.cpp updated: 1.6 -> 1.7
---
Log message:
Handle PHINode with only one incoming value.
This fixes http://llvm.org/bugs/show_bug.cgi?id=979
---
Diffs of the changes: (+9 -5)
CondPropagate.cpp | 14 +-
1 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/Transforms/Scalar/CondPropagate.cpp
diff -u llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.6
llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.7
--- llvm/lib/Transforms/Scalar/CondPropagate.cpp:1.6Sun Aug 27 17:42:52 2006
+++ llvm/lib/Transforms/Scalar/CondPropagate.cppWed Nov 1 16:26:43 2006
@@ -196,11 +196,15 @@
// Get the old block we are threading through.
BasicBlock *OldSucc = FromBr->getSuccessor(0);
- // ToBB should not have any PHI nodes in it to update, because OldSucc had
- // multiple successors. If OldSucc had multiple successor and ToBB had
- // multiple predecessors, the edge between them would be critical, which we
- // already took care of.
- assert(!isa(ToBB->begin()) && "Critical Edge Found!");
+ // OldSucc had multiple successors. If ToBB has multiple predecessors, the
+ // edge between them would be critical, which we already took care of.
+ // If ToBB has single operand PHI node than take care of it here.
+ if (isa(ToBB->begin())) {
+PHINode *PN = cast(ToBB->begin());
+assert(PN->getNumIncomingValues() == 1 && "Critical Edge Found!");
+PN->replaceAllUsesWith(PN->getIncomingValue(0));
+PN->eraseFromParent();
+ }
// Update PHI nodes in OldSucc to know that FromBB no longer branches to it.
OldSucc->removePredecessor(FromBB);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: ScheduleDAGRRList.cpp updated: 1.15 -> 1.16 --- Log message: CopyFromReg starts a live range so its use should not be considered a floater. --- Diffs of the changes: (+1 -1) ScheduleDAGRRList.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.15 llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.16 --- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp:1.15Sat Oct 14 03:34:06 2006 +++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Wed Nov 1 16:17:06 2006 @@ -555,7 +555,7 @@ SUnit *PredSU = I->first; unsigned Opc = PredSU->Node->getOpcode(); if (Opc != ISD::EntryToken && Opc != ISD::TokenFactor && -Opc != ISD::CopyFromReg && Opc != ISD::CopyToReg) +Opc != ISD::CopyToReg) return false; } return true; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Analysis/ScalarEvolution.cpp
Changes in directory llvm/lib/Analysis:
ScalarEvolution.cpp updated: 1.55 -> 1.56
---
Log message:
Make ScalarEvolution actually use a ZeroExtend expression instead of
having SCZeroExtendExpr be equivalent to SCTruncate
---
Diffs of the changes: (+2 -2)
ScalarEvolution.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/Analysis/ScalarEvolution.cpp
diff -u llvm/lib/Analysis/ScalarEvolution.cpp:1.55
llvm/lib/Analysis/ScalarEvolution.cpp:1.56
--- llvm/lib/Analysis/ScalarEvolution.cpp:1.55 Thu Oct 26 01:15:43 2006
+++ llvm/lib/Analysis/ScalarEvolution.cpp Wed Nov 1 15:53:12 2006
@@ -229,7 +229,7 @@
SCEVZeroExtendExpr*> > SCEVZeroExtends;
SCEVZeroExtendExpr::SCEVZeroExtendExpr(const SCEVHandle &op, const Type *ty)
- : SCEV(scTruncate), Op(op), Ty(ty) {
+ : SCEV(scZeroExtend), Op(op), Ty(ty) {
assert(Op->getType()->isInteger() && Ty->isInteger() &&
Ty->isUnsigned() &&
"Cannot zero extend non-integer value!");
@@ -1359,7 +1359,7 @@
return SCEVTruncateExpr::get(getSCEV(CI->getOperand(0)),
CI->getType()->getUnsignedVersion());
if (SrcTy->isUnsigned() &&
-SrcTy->getPrimitiveSize() > DestTy->getPrimitiveSize())
+SrcTy->getPrimitiveSize() <= DestTy->getPrimitiveSize())
return SCEVZeroExtendExpr::get(getSCEV(CI->getOperand(0)),
CI->getType()->getUnsignedVersion());
}
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[llvm-commits] CVS: llvm/lib/CodeGen/BranchFolding.cpp
Changes in directory llvm/lib/CodeGen:
BranchFolding.cpp updated: 1.29 -> 1.30
---
Log message:
give branch folding a simple heuristic to decide which block to split so that
it inserts an uncond branch where it is less likely to cause a problem. This
fixes some perf issues on ppc.
---
Diffs of the changes: (+49 -6)
BranchFolding.cpp | 55 --
1 files changed, 49 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/BranchFolding.cpp
diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.29
llvm/lib/CodeGen/BranchFolding.cpp:1.30
--- llvm/lib/CodeGen/BranchFolding.cpp:1.29 Tue Oct 31 19:16:12 2006
+++ llvm/lib/CodeGen/BranchFolding.cpp Wed Nov 1 13:36:29 2006
@@ -283,6 +283,44 @@
return NewMBB;
}
+/// EstimateRuntime - Make a rough estimate for how long it will take to run
+/// the specified code.
+static unsigned EstimateRuntime(MachineBasicBlock::iterator I,
+MachineBasicBlock::iterator E,
+const TargetInstrInfo *TII) {
+ unsigned Time = 0;
+ for (; I != E; ++I) {
+const TargetInstrDescriptor &TID = TII->get(I->getOpcode());
+if (TID.Flags & M_CALL_FLAG)
+ Time += 10;
+else if (TID.Flags & (M_LOAD_FLAG|M_STORE_FLAG))
+ Time += 2;
+else
+ ++Time;
+ }
+ return Time;
+}
+
+/// ShouldSplitFirstBlock - We need to either split MBB1 at MBB1I or MBB2 at
+/// MBB2I and then insert an unconditional branch in the other block.
Determine
+/// which is the best to split
+static bool ShouldSplitFirstBlock(MachineBasicBlock *MBB1,
+ MachineBasicBlock::iterator MBB1I,
+ MachineBasicBlock *MBB2,
+ MachineBasicBlock::iterator MBB2I,
+ const TargetInstrInfo *TII) {
+ // TODO: if we had some notion of which block was hotter, we could split
+ // the hot block, so it is the fall-through. Since we don't have profile
info
+ // make a decision based on which will hurt most to split.
+ unsigned MBB1Time = EstimateRuntime(MBB1->begin(), MBB1I, TII);
+ unsigned MBB2Time = EstimateRuntime(MBB2->begin(), MBB2I, TII);
+
+ // If the MBB1 prefix takes "less time" to run than the MBB2 prefix, split
the
+ // MBB1 block so it falls through. This will penalize the MBB2 path, but
will
+ // have a lower overall impact on the program execution.
+ return MBB1Time < MBB2Time;
+}
+
bool BranchFolder::TailMergeBlocks(MachineFunction &MF) {
MadeChange = false;
@@ -355,12 +393,17 @@
MergePotentials.pop_back();
continue;
}
- // TODO: if we had some notion of which block was hotter, we could split
- // the hot block, so it is the fall-through. For now, just split the
- // second block.
- MBB2 = SplitMBBAt(*MBB2, BBI2);
- BBI2 = MBB2->begin();
- (MergePotentials.end()-2)->second = MBB2;
+
+ // Decide whether we want to split CurMBB or MBB2.
+ if (ShouldSplitFirstBlock(CurMBB, BBI1, MBB2, BBI2, TII)) {
+CurMBB = SplitMBBAt(*CurMBB, BBI1);
+BBI1 = CurMBB->begin();
+MergePotentials.back().second = CurMBB;
+ } else {
+MBB2 = SplitMBBAt(*MBB2, BBI2);
+BBI2 = MBB2->begin();
+(MergePotentials.end()-2)->second = MBB2;
+ }
}
if (MBB2->begin() == BBI2) {
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[llvm-commits] CVS: llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.ll
Changes in directory llvm/test/Regression/Transforms/ScalarRepl: phinodepromote.ll updated: 1.2 -> 1.3 --- Log message: extra pass is required now --- Diffs of the changes: (+1 -1) phinodepromote.ll |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.ll diff -u llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.ll:1.2 llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.ll:1.3 --- llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.ll:1.2Sun Sep 19 13:45:45 2004 +++ llvm/test/Regression/Transforms/ScalarRepl/phinodepromote.llWed Nov 1 12:30:25 2006 @@ -1,4 +1,4 @@ -; RUN: llvm-as < %s | opt -instcombine -mem2reg | llvm-dis | not grep alloca +; RUN: llvm-as < %s | opt -simplifycfg -instcombine -mem2reg | llvm-dis | not grep alloca ; ; This tests to see if mem2reg can promote alloca instructions whose addresses ; are used by PHI nodes that are immediately loaded. The LLVM C++ front-end ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Transforms/IPO/GlobalOpt.cpp
Changes in directory llvm/lib/Transforms/IPO:
GlobalOpt.cpp updated: 1.69 -> 1.70
---
Log message:
Fix GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll and McGill/chomp
---
Diffs of the changes: (+14 -8)
GlobalOpt.cpp | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
Index: llvm/lib/Transforms/IPO/GlobalOpt.cpp
diff -u llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.69
llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.70
--- llvm/lib/Transforms/IPO/GlobalOpt.cpp:1.69 Fri Oct 20 02:07:24 2006
+++ llvm/lib/Transforms/IPO/GlobalOpt.cpp Wed Nov 1 12:03:33 2006
@@ -104,17 +104,20 @@
/// ever stored to this global, keep track of what value it is.
Value *StoredOnceValue;
- // AccessingFunction/HasMultipleAccessingFunctions - These start out
- // null/false. When the first accessing function is noticed, it is recorded.
- // When a second different accessing function is noticed,
- // HasMultipleAccessingFunctions is set to true.
+ /// AccessingFunction/HasMultipleAccessingFunctions - These start out
+ /// null/false. When the first accessing function is noticed, it is
recorded.
+ /// When a second different accessing function is noticed,
+ /// HasMultipleAccessingFunctions is set to true.
Function *AccessingFunction;
bool HasMultipleAccessingFunctions;
- // HasNonInstructionUser - Set to true if this global has a user that is not
- // an instruction (e.g. a constant expr or GV initializer).
+ /// HasNonInstructionUser - Set to true if this global has a user that is not
+ /// an instruction (e.g. a constant expr or GV initializer).
bool HasNonInstructionUser;
+ /// HasPHIUser - Set to true if this global has a user that is a PHI node.
+ bool HasPHIUser;
+
/// isNotSuitableForSRA - Keep track of whether any SRA preventing users of
/// the global exist. Such users include GEP instruction with variable
/// indexes, and non-gep/load/store users like constant expr casts.
@@ -122,7 +125,8 @@
GlobalStatus() : isLoaded(false), StoredType(NotStored), StoredOnceValue(0),
AccessingFunction(0), HasMultipleAccessingFunctions(false),
- HasNonInstructionUser(false), isNotSuitableForSRA(false) {}
+ HasNonInstructionUser(false), HasPHIUser(false),
+ isNotSuitableForSRA(false) {}
};
@@ -238,6 +242,7 @@
if (PHIUsers.insert(PN).second) // Not already visited.
if (AnalyzeGlobal(I, GS, PHIUsers)) return true;
GS.isNotSuitableForSRA = true;
+GS.HasPHIUser = true;
} else if (isa(I)) {
GS.isNotSuitableForSRA = true;
} else if (isa(I) || isa(I)) {
@@ -1321,7 +1326,8 @@
// boolean.
if (Constant *SOVConstant = dyn_cast(GS.StoredOnceValue))
if (GV->getType()->getElementType() != Type::BoolTy &&
-!GV->getType()->getElementType()->isFloatingPoint()) {
+!GV->getType()->getElementType()->isFloatingPoint() &&
+!GS.HasPHIUser) {
DEBUG(std::cerr << " *** SHRINKING TO BOOL: " << *GV);
ShrinkGlobalToBoolean(GV, SOVConstant);
++NumShrunkToBool;
___
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[llvm-commits] CVS: llvm/test/Regression/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
Changes in directory llvm/test/Regression/Transforms/GlobalOpt:
2006-11-01-ShrinkGlobalPhiCrash.ll added (r1.1)
---
Log message:
new testcase that crashes global opt, reduced from chomp
---
Diffs of the changes: (+33 -0)
2006-11-01-ShrinkGlobalPhiCrash.ll | 33 +
1 files changed, 33 insertions(+)
Index:
llvm/test/Regression/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
diff -c /dev/null
llvm/test/Regression/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll:1.1
*** /dev/null Wed Nov 1 12:03:03 2006
---
llvm/test/Regression/Transforms/GlobalOpt/2006-11-01-ShrinkGlobalPhiCrash.ll
Wed Nov 1 12:02:53 2006
***
*** 0
--- 1,33
+ ; RUN: llvm-as < %s | opt -globalopt -disable-output
+ %struct._list = type { int*, %struct._list* }
+ %struct._play = type { int, int*, %struct._list*, %struct._play* }
+ %nrow = internal global int 0 ; [#uses=2]
+
+ implementation ; Functions:
+
+ void %make_play() {
+ entry:
+ br label %cond_true16.i
+
+ cond_true16.i:; preds = %cond_true16.i, %entry
+ %low.0.in.i.0 = phi int* [ %nrow, %entry ], [ null, %cond_true16.i ]
; [#uses=1]
+ %low.0.i = load int* %low.0.in.i.0 ; [#uses=0]
+ br label %cond_true16.i
+ }
+
+ void %make_wanted() {
+ entry:
+ unreachable
+ }
+
+ void %get_good_move() {
+ entry:
+ ret void
+ }
+
+ void %main() {
+ entry:
+ store int 8, int* %nrow
+ tail call void %make_play( )
+ ret void
+ }
___
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[llvm-commits] CVS: llvm/docs/ReleaseNotes.html
Changes in directory llvm/docs: ReleaseNotes.html updated: 1.362 -> 1.363 --- Log message: Partial update for Release 1.9 --- Diffs of the changes: (+25 -59) ReleaseNotes.html | 84 -- 1 files changed, 25 insertions(+), 59 deletions(-) Index: llvm/docs/ReleaseNotes.html diff -u llvm/docs/ReleaseNotes.html:1.362 llvm/docs/ReleaseNotes.html:1.363 --- llvm/docs/ReleaseNotes.html:1.362 Wed Aug 9 12:08:27 2006 +++ llvm/docs/ReleaseNotes.html Wed Nov 1 10:15:04 2006 @@ -4,11 +4,11 @@ - LLVM 1.8 Release Notes + LLVM 1.9 Release Notes -LLVM 1.8 Release Notes +LLVM 1.9 Release Notes Introduction @@ -32,7 +32,7 @@ This document contains the release notes for the LLVM compiler -infrastructure, release 1.8. Here we describe the status of LLVM, including any +infrastructure, release 1.9. Here we describe the status of LLVM, including any known problems and major improvements from the previous release. The most up-to-date version of this document (corresponding to LLVM CVS) can be found on the -This is the ninth public release of the LLVM Compiler Infrastructure. This -release incorporates a large number of enhancements and new features, -including DWARF debugging support (C and C++ on Darwin/PPC), improved inline -assembly support, a new http://llvm.org/nightlytest/";>nightly -tester, llvm-config enhancements, many bugs -fixed, and performance and compile time improvements. +This is the tenth public release of the LLVM Compiler Infrastructure. This +release incorporates a large number of enhancements and new features. -New Features in LLVM 1.8 +New Features in LLVM 1.9 -DWARF debugging -support - +DWARF debugging +support for X86/ELF - -The llvm-gcc4 C front-end now generates debugging info for C and C++. This -information is propagated through the compiler and the code generator can -currently produce DWARF debugging information from it. DWARF is a standard -debugging format used on many platforms, but currently LLVM only includes -target support for Mac OS X targets for the 1.8 release. - - +The llvm-gcc4 C front-end now generates debugging info for C and C++ for +X86/ELF platforms (Linux). This extends the PPC/Darwin and X86/Darwin debugging +support available in release 18.8 DWARF is a standard debugging format used on +many platforms. -Inline Assembly -Support - +Signed Instructions - -Inline assembly support is substantially improved in LLVM 1.8 over LLVM 1.7. -Many unsupported features are now supported, and inline asm support in the X86 -backend is far better. llvm-gcc4 now supports global register variables as -well. - +As a step towards making LLVM's integer types signless, several new +instructions have been added to LLVM. The DIV instruction has become UDIV, SDIV, +and FDIV. The REM instruction has become UREM, SREM and FREM. The SHR +instruction has become ASHR and LSHR. See the Language + Reference for details on these new instructions. -Loop Optimizer Improvements - +New Feature C - -The loop optimizer passes now uses "Loop-Closed SSA Form", which makes it -easier to update SSA form as loop transformations change the code. An -immediate benefit of this is that the loop unswitching pass can now unswitch -loops in more cases. - - +Describe feature C here. -Jump Table Support for Switches - - +New Feature D - -The code generator now lowers switch statements to jump tables, providing -significant performance boosts for applications (e.g. interpreters) whose -performance is highly correlated to switch statement performance. - +Describe feature D here. -Deallocation of JIT'd -Machine Code - - +New Feature E - -The LLVM JIT now allows clients to deallocate machine code JIT'd to its code -buffer. This is important for long living applications that depend on the JIT. - - +Describe feature E here. Other Improvements - - This release includes many other improvements, including improvements to the optimizers and code generators (improving the generated code) changes to speed up the compiler in many ways (improving algorithms and fine tuning @@ -684,7 +650,7 @@ src="http://www.w3.org/Icons/valid-html401"; alt="Valid HTML 4.01!" /> http://llvm.org/";>The LLVM Compiler Infrastructure - Last modified: $Date: 2006/08/09 17:08:27 $ + Last modified: $Date: 2006/11/01 16:15:04 $ ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
Changes in directory llvm/lib/Target/ARM:
ARMAsmPrinter.cpp updated: 1.25 -> 1.26
---
Log message:
print null values in bss
---
Diffs of the changes: (+4 -2)
ARMAsmPrinter.cpp |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/ARM/ARMAsmPrinter.cpp
diff -u llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.25
llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.26
--- llvm/lib/Target/ARM/ARMAsmPrinter.cpp:1.25 Thu Oct 19 08:30:40 2006
+++ llvm/lib/Target/ARM/ARMAsmPrinter.cpp Wed Nov 1 08:26:44 2006
@@ -303,8 +303,10 @@
break;
}
- assert (!C->isNullValue());
- SwitchToDataSection(".data", I);
+ if (C->isNullValue())
+SwitchToDataSection(".bss", I);
+ else
+SwitchToDataSection(".data", I);
EmitAlignment(Align, I);
O << "\t.type " << name << ", %object\n";
___
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[llvm-commits] CVS: llvm/lib/Target/ARM/ARMInstrInfo.td
Changes in directory llvm/lib/Target/ARM: ARMInstrInfo.td updated: 1.71 -> 1.72 --- Log message: implement zextload bool and truncstore bool --- Diffs of the changes: (+10 -0) ARMInstrInfo.td | 10 ++ 1 files changed, 10 insertions(+) Index: llvm/lib/Target/ARM/ARMInstrInfo.td diff -u llvm/lib/Target/ARM/ARMInstrInfo.td:1.71 llvm/lib/Target/ARM/ARMInstrInfo.td:1.72 --- llvm/lib/Target/ARM/ARMInstrInfo.td:1.71Tue Oct 24 11:47:57 2006 +++ llvm/lib/Target/ARM/ARMInstrInfo.td Wed Nov 1 08:13:27 2006 @@ -347,3 +347,13 @@ (LDRB IntRegs:$addr)>; def : Pat<(extloadi16 IntRegs:$addr), (LDRH IntRegs:$addr)>; + +// zextload bool -> zextload byte +def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>; +def : Pat<(i32 (zextloadi1 IntRegs:$addr)), (LDRB IntRegs:$addr)>; + +// truncstore bool -> truncstore byte. +def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr), + (STRB IntRegs:$addr, IntRegs:$src)>; +def : Pat<(truncstorei1 IntRegs:$src, IntRegs:$addr), + (STRB IntRegs:$addr, IntRegs:$src)>; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/include/llvm/CodeGen/AsmPrinter.h
Changes in directory llvm/include/llvm/CodeGen: AsmPrinter.h updated: 1.56 -> 1.57 --- Log message: Add a printSetLabel that takes two id's. --- Diffs of the changes: (+2 -0) AsmPrinter.h |2 ++ 1 files changed, 2 insertions(+) Index: llvm/include/llvm/CodeGen/AsmPrinter.h diff -u llvm/include/llvm/CodeGen/AsmPrinter.h:1.56 llvm/include/llvm/CodeGen/AsmPrinter.h:1.57 --- llvm/include/llvm/CodeGen/AsmPrinter.h:1.56 Tue Oct 31 00:11:06 2006 +++ llvm/include/llvm/CodeGen/AsmPrinter.h Wed Nov 1 03:22:43 2006 @@ -206,6 +206,8 @@ /// printSetLabel - This method prints a set label for the specified /// MachineBasicBlock void printSetLabel(unsigned uid, const MachineBasicBlock *MBB) const; +void printSetLabel(unsigned uid, unsigned uid2, + const MachineBasicBlock *MBB) const; /// printDataDirective - This method prints the asm directive for the /// specified type. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.115 -> 1.116
---
Log message:
Add a printSetLabel that takes two id's.
---
Diffs of the changes: (+13 -0)
AsmPrinter.cpp | 13 +
1 files changed, 13 insertions(+)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.115
llvm/lib/CodeGen/AsmPrinter.cpp:1.116
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.115 Tue Oct 31 02:31:23 2006
+++ llvm/lib/CodeGen/AsmPrinter.cpp Wed Nov 1 03:23:08 2006
@@ -875,6 +875,19 @@
<< '_' << uid << '\n';
}
+void AsmPrinter::printSetLabel(unsigned uid, unsigned uid2,
+ const MachineBasicBlock *MBB) const {
+ if (!TAI->getSetDirective())
+return;
+
+ O << TAI->getSetDirective() << ' ' << TAI->getPrivateGlobalPrefix()
+<< getFunctionNumber() << '_' << uid << '_' << uid2
+<< "_set_" << MBB->getNumber() << ',';
+ printBasicBlockLabel(MBB, false, false);
+ O << '-' << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
+<< '_' << uid << '_' << uid2 << '\n';
+}
+
/// printDataDirective - This method prints the asm directive for the
/// specified type.
void AsmPrinter::printDataDirective(const Type *type) {
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[llvm-commits] [llvm-gcc] SHR Patch
This patch is for llvm-gcc to make it emit ashr (arithmetic shift right) and lshr (logical shift right) instructions. It needs to be applied to llvm-gcc after the SHR.patch is applied to LLVM. Reid. Index: gcc/llvm-convert.cpp === --- gcc/llvm-convert.cpp (revision 193) +++ gcc/llvm-convert.cpp (working copy) @@ -565,12 +565,19 @@ case TRUTH_AND_EXPR: Result = EmitTruthOp(exp, Instruction::And); break; case TRUTH_OR_EXPR: Result = EmitTruthOp(exp, Instruction::Or); break; case TRUTH_XOR_EXPR: Result = EmitTruthOp(exp, Instruction::Xor); break; - case RSHIFT_EXPR:Result = EmitShiftOp(exp,DestLoc,Instruction::Shr);break; + case RSHIFT_EXPR: +Result = EmitShiftOp(exp,DestLoc, + TYPE_UNSIGNED(TREE_TYPE(exp)) ? Instruction::LShr : Instruction::AShr); +break; case LSHIFT_EXPR:Result = EmitShiftOp(exp,DestLoc,Instruction::Shl);break; - case RROTATE_EXPR: Result = EmitRotateOp(exp, Instruction::Shr, - Instruction::Shl); break; - case LROTATE_EXPR: Result = EmitRotateOp(exp, Instruction::Shl, - Instruction::Shr); break; + case RROTATE_EXPR: +Result = EmitRotateOp(exp, + TYPE_UNSIGNED(TREE_TYPE(exp)) ? Instruction::LShr : Instruction::AShr, + Instruction::Shl); +break; + case LROTATE_EXPR: +Result = EmitRotateOp(exp, Instruction::Shl, Instruction::LShr); +break; case MIN_EXPR: Result = EmitMinMaxExpr(exp, Instruction::SetLE); break; case MAX_EXPR: Result = EmitMinMaxExpr(exp, Instruction::SetGE); break; case CONSTRUCTOR:Result = EmitCONSTRUCTOR(exp, DestLoc); break; @@ -1718,7 +1725,8 @@ } Value *ShAmt = ConstantInt::get(Type::UByteTy, ValSizeInBits-LV.BitSize); - Val = new ShiftInst(Instruction::Shr, Val, ShAmt, "tmp", CurBB); + Val = new ShiftInst(Val->getType()->isSigned() ? +Instruction::AShr : Instruction::LShr, Val, ShAmt, "tmp", CurBB); } return CastToType(Val, ConvertType(TREE_TYPE(exp))); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
