Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
We overload ISD::FADD and quite a lot of others. Why not ISD::ConstantFP too? Fair enough, after pondering on it, I agree with you. The proposed semantics are that a ConstantFP (and also a normal Constant?) produce the splatted immediate value? Constant sounds good too. And UNDEF, for that matter. And yes, that's the semantics I mean. If so, this sounds fine. This should also reduce codegen memory usage for many common cases, a very nice bonus :) :) Please add a dag combine xform from build_vector [c,c,c,c] - constantfp and friends. I sketched out some of the code for this. One question that's come up so far is whether if the vector has some undef elements but all the non-undef elements are equal it should still be folded. My initial preference is to still fold it, since that lets things like isBuildVectorAllZeros become trivial to unnecessary, but it is a pessimization in some obscure cases. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jul 3, 2007, at 2:13 PM, Dan Gohman wrote: We overload ISD::FADD and quite a lot of others. Why not ISD::ConstantFP too? Fair enough, after pondering on it, I agree with you. The proposed semantics are that a ConstantFP (and also a normal Constant?) produce the splatted immediate value? Constant sounds good too. And UNDEF, for that matter. And yes, that's the semantics I mean. Ok, makes sense. I think we already use UNDEF for vectors. Please add a dag combine xform from build_vector [c,c,c,c] - constantfp and friends. I sketched out some of the code for this. One question that's come up so far is whether if the vector has some undef elements but all the non-undef elements are equal it should still be folded. My initial preference is to still fold it, since that lets things like isBuildVectorAllZeros become trivial to unnecessary, but it is a pessimization in some obscure cases. I'm not sure about it. One specific issue is with shuffle masks, which we want to retain the undef element values for. I don't think there is a good way to retain shuffle masks but not other build vectors, so we probably need to keep the individual undef elements in it. isBuildVectorAllZeros and friends are another issue. To me there are actually two issues that should be resolved at some point: 1. vector constant and shuffle mask matching code is crazily complex, particularly in the x86 backend. For vector constants, this is only slightly annoying. For vector shuffle masks, the selected shuffles are currently whatever is best for yonah, and it's not really possible to prefer different shuffles on different subtargets. We really want to add a layer of abstraction in the shuffle/constant matching code, which would make the undef handling stuff happen implicitly. Making a more declarative description of the various masks would make it much easier to maintain, understand, and debug. 2. the x86 backend specifically has a problem with the way it selects vector constants (I think this is in the readme). In particular, if you have a 4 x f32 and a 4 x i32 zero vector, you'll get two different pxor instructions, because they are of different type. There are two different ways to solve this problem: The easy answer is to do what the ppc backend does. It always selects zero (and -1) vectors to 4 x i32 IIRC, and then does a bitcast to the desired type if needed. This ensures that the constant vectors always get CSEd. The tricky part of this is to ensure that the 0/-1 vectors still get folded if you have operations (like ~) that require one of these as an operand. This ugliness is why we have vnot and vnot_conv and have to duplicate patterns. The better fix is to change the way the select phase produces code. In particular, the reason these two zero vectors don't get CSE'd after selection is because they have two different value types, and the autocse stuff doesn't know that the two VTs end up in the same register class. To solve this, it seems like we can add a new MVT type, where a certain range of MVTs (128-255?) correspond to register class ID's. At selection time, instead of giving the new nodes their old MVT's, they would get new MVT's that correspond to the regclass of the result (ok, we'd keep MVT::Other, MVT::Flag and maybe some others). This makes the scheduler slightly simpler (because it doesn't need to map MVT - regclass) anymore, and opens up future possibilities. In particular, it lets us fix a long-standing class of issues where we can't have fp stack and SSE registers around at the same time, both with MVT::f32 or f64 type. The current scheduler can only map f32 to one register class (thus, it can't keep the distinction) but with this change the select pass can pick any regclass it wants. Anyway, this is a bit of a crazy tangent, but I think undef's in buildvector should probably stay :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jun 29, 2007, at 12:38 PM, Dan Gohman wrote: Just as there isn't a special ADD node kind for vectors -- just an ADD kind with nodes that can have a vector ValueType, ConstantFP can also be vectorized. A ConstantFP with a vector ValueType is a vector constant, equivalent to what is currently represented as a splat BUILD_VECTOR, except that it's easier to work with :). I'm not opposed to doing this, but I don't think we should overload ConstantFP() and getConstantFP() for this. Could you make a new VectorConstantFP or something? We overload ISD::FADD and quite a lot of others. Why not ISD::ConstantFP too? Fair enough, after pondering on it, I agree with you. The proposed semantics are that a ConstantFP (and also a normal Constant?) produce the splatted immediate value? If so, this sounds fine. This should also reduce codegen memory usage for many common cases, a very nice bonus :) Please add a dag combine xform from build_vector [c,c,c,c] - constantfp and friends. Thanks Dan, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Just as there isn't a special ADD node kind for vectors -- just an ADD kind with nodes that can have a vector ValueType, ConstantFP can also be vectorized. A ConstantFP with a vector ValueType is a vector constant, equivalent to what is currently represented as a splat BUILD_VECTOR, except that it's easier to work with :). I'm not opposed to doing this, but I don't think we should overload ConstantFP() and getConstantFP() for this. Could you make a new VectorConstantFP or something? We overload ISD::FADD and quite a lot of others. Why not ISD::ConstantFP too? Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 Fri Jun 22
09:59:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 25
11:23:39 2007
@@ -673,7 +673,9 @@
SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT,
bool isTarget) {
assert(MVT::isFloatingPoint(VT) Cannot create integer FP
constant!);
- if (VT == MVT::f32)
+ MVT::ValueType EltVT =
+MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
I don't understand this change. getConstantFP shouldn't be called on
vectors, should it? This seems to be a strange thing to overload.
Oops; that's a small part of an unrelated set of changes I'm working
on. That code isn't used currently.
Just as there isn't a special ADD node kind for vectors -- just an ADD
kind with nodes that can have a vector ValueType, ConstantFP can also
be vectorized. A ConstantFP with a vector ValueType is a vector constant,
equivalent to what is currently represented as a splat BUILD_VECTOR,
except that it's easier to work with :).
Dan
--
Dan Gohman, Cray Inc.
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jun 27, 2007, at 7:59 AM, Dan Gohman wrote:
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409Fri Jun 22
09:59:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 25
11:23:39 2007
@@ -673,7 +673,9 @@
SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType
VT,
bool isTarget) {
assert(MVT::isFloatingPoint(VT) Cannot create integer FP
constant!);
- if (VT == MVT::f32)
+ MVT::ValueType EltVT =
+MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
I don't understand this change. getConstantFP shouldn't be called on
vectors, should it? This seems to be a strange thing to overload.
Oops; that's a small part of an unrelated set of changes I'm working
on. That code isn't used currently.
Just as there isn't a special ADD node kind for vectors -- just an ADD
kind with nodes that can have a vector ValueType, ConstantFP can also
be vectorized. A ConstantFP with a vector ValueType is a vector
constant,
equivalent to what is currently represented as a splat BUILD_VECTOR,
except that it's easier to work with :).
I'm not opposed to doing this, but I don't think we should overload
ConstantFP() and getConstantFP() for this. Could you make a new
VectorConstantFP or something?
-Chris
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.500 Fri Jun 22
09:59:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jun 25
11:23:39 2007
@@ -173,15 +173,13 @@
+ /// ScalarizeVectorOp - Given an operand of vector type, convert
it into the
+ /// equivalent operation that returns a scalar value.
+ SDOperand ScalarizeVectorOp(SDOperand O);
This comment should explicitly mention that the function is only
supposed to be called on single-element vector types.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 Fri Jun 22
09:59:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cppMon Jun 25
11:23:39 2007
@@ -673,7 +673,9 @@
SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT,
bool isTarget) {
assert(MVT::isFloatingPoint(VT) Cannot create integer FP
constant!);
- if (VT == MVT::f32)
+ MVT::ValueType EltVT =
+MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
I don't understand this change. getConstantFP shouldn't be called on
vectors, should it? This seems to be a strange thing to overload.
-Chris
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.218 - 1.219
LegalizeDAG.cpp updated: 1.411 - 1.412
SelectionDAG.cpp updated: 1.349 - 1.350
SelectionDAGISel.cpp updated: 1.287 - 1.288
TargetLowering.cpp updated: 1.76 - 1.77
---
Log message:
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
---
Diffs of the changes: (+252 -223)
DAGCombiner.cpp | 76 ++---
LegalizeDAG.cpp | 289 +--
SelectionDAG.cpp | 97 +++--
SelectionDAGISel.cpp | 12 +-
TargetLowering.cpp |1
5 files changed, 252 insertions(+), 223 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.218
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.219
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.218 Thu Oct 12 15:58:32 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Oct 13 16:12:22 2006
@@ -503,8 +503,6 @@
case ISD::BRCOND: return visitBRCOND(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
- // FIXME - Switch over after StoreSDNode comes online.
- case ISD::TRUNCSTORE: // Fall thru
case ISD::STORE: return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@@ -2687,9 +2685,12 @@
// TODO: Handle store large - read small portion.
// TODO: Handle TRUNCSTORE/LOADEXT
if (LD-getExtensionType() == ISD::NON_EXTLOAD) {
-if (Chain.getOpcode() == ISD::STORE Chain.getOperand(2) == Ptr
-Chain.getOperand(1).getValueType() == N-getValueType(0))
+if (ISD::isNON_TRUNCStore(Chain.Val)) {
+ StoreSDNode *PrevST = castStoreSDNode(Chain);
+ if (PrevST-getBasePtr() == Ptr
+ PrevST-getValue().getValueType() == N-getValueType(0))
return CombineTo(N, Chain.getOperand(1), Chain);
+}
}
if (CombinerAA) {
@@ -2725,13 +2726,13 @@
}
SDOperand DAGCombiner::visitSTORE(SDNode *N) {
- SDOperand Chain= N-getOperand(0);
- SDOperand Value= N-getOperand(1);
- SDOperand Ptr = N-getOperand(2);
- SDOperand SrcValue = N-getOperand(3);
+ StoreSDNode *ST = castStoreSDNode(N);
+ SDOperand Chain = ST-getChain();
+ SDOperand Value = ST-getValue();
+ SDOperand Ptr = ST-getBasePtr();
// FIXME - Switch over after StoreSDNode comes online.
- if (N-getOpcode() == ISD::TRUNCSTORE) {
+ if (ST-isTruncatingStore()) {
if (CombinerAA) {
// Walk up chain skipping non-aliasing memory nodes.
SDOperand BetterChain = FindBetterChain(N, Chain);
@@ -2739,9 +2740,9 @@
// If there is a better chain.
if (Chain != BetterChain) {
// Replace the chain to avoid dependency.
-SDOperand ReplTStore = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
-BetterChain, Value, Ptr, SrcValue,
-N-getOperand(4));
+SDOperand ReplTStore =
+ DAG.getTruncStore(BetterChain, Value, Ptr, ST-getSrcValue(),
+ST-getSrcValueOffset(), ST-getStoredVT());
// Create token to keep both nodes around.
return DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplTStore);
@@ -2752,27 +2753,30 @@
}
// If this is a store that kills a previous store, remove the previous store.
- if (Chain.getOpcode() == ISD::STORE Chain.getOperand(2) == Ptr
- Chain.Val-hasOneUse() /* Avoid introducing DAG cycles */
- // Make sure that these stores are the same value type:
- // FIXME: we really care that the second store is = size of the first.
- Value.getValueType() == Chain.getOperand(1).getValueType()) {
-// Create a new store of Value that replaces both stores.
-SDNode *PrevStore = Chain.Val;
-if (PrevStore-getOperand(1) == Value) // Same value multiply stored.
- return Chain;
-SDOperand NewStore = DAG.getStore(PrevStore-getOperand(0), Value, Ptr,
- SrcValue);
-CombineTo(N, NewStore); // Nuke this store.
-CombineTo(PrevStore, NewStore); // Nuke the previous store.
-return SDOperand(N, 0);
+ if (ISD::isNON_TRUNCStore(Chain.Val)) {
+StoreSDNode *PrevST = castStoreSDNode(Chain);
+if (PrevST-getBasePtr() == Ptr
+Chain.Val-hasOneUse() /* Avoid introducing DAG cycles */
+// Make sure that these stores are the same value type:
+// FIXME: we really care that the second store is = size of the first.
+Value.getValueType() == PrevST-getValue().getValueType()) {
+ // Create a new store of Value that replaces both stores.
+ if (PrevST-getValue() == Value) // Same value multiply stored.
+return Chain;
+ SDOperand NewStore = DAG.getStore(PrevST-getChain(), Value, Ptr,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGPrinter.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.211 - 1.212
LegalizeDAG.cpp updated: 1.409 - 1.410
SelectionDAG.cpp updated: 1.347 - 1.348
SelectionDAGPrinter.cpp updated: 1.37 - 1.38
TargetLowering.cpp updated: 1.75 - 1.76
---
Log message:
Naming consistency.
---
Diffs of the changes: (+20 -20)
DAGCombiner.cpp | 20 ++--
LegalizeDAG.cpp |6 +++---
SelectionDAG.cpp|4 ++--
SelectionDAGPrinter.cpp |2 +-
TargetLowering.cpp |8
5 files changed, 20 insertions(+), 20 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.211
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.212
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.211 Mon Oct 9 15:57:24 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Oct 11 02:09:31 2006
@@ -1077,7 +1077,7 @@
// fold (zext_inreg (extload x)) - (zextload x)
if (ISD::isEXTLoad(N0.Val)) {
LoadSDNode *LN0 = castLoadSDNode(N0);
-MVT::ValueType EVT = LN0-getLoadVT();
+MVT::ValueType EVT = LN0-getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
@@ -1093,7 +1093,7 @@
// fold (zext_inreg (sextload x)) - (zextload x) iff load has one use
if (ISD::isSEXTLoad(N0.Val) N0.hasOneUse()) {
LoadSDNode *LN0 = castLoadSDNode(N0);
-MVT::ValueType EVT = LN0-getLoadVT();
+MVT::ValueType EVT = LN0-getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
@@ -1123,7 +1123,7 @@
else
EVT = MVT::Other;
- LoadedVT = LN0-getLoadVT();
+ LoadedVT = LN0-getLoadedVT();
if (EVT != MVT::Other LoadedVT EVT
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
@@ -1874,7 +1874,7 @@
// fold (sext ( extload x)) - (sext (truncate (sextload x)))
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) N0.hasOneUse()) {
LoadSDNode *LN0 = castLoadSDNode(N0);
-MVT::ValueType EVT = LN0-getLoadVT();
+MVT::ValueType EVT = LN0-getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0-getChain(),
LN0-getBasePtr(), LN0-getSrcValue(),
LN0-getSrcValueOffset(), EVT);
@@ -1943,7 +1943,7 @@
// fold (zext ( extload x)) - (zext (truncate (zextload x)))
if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) N0.hasOneUse()) {
LoadSDNode *LN0 = castLoadSDNode(N0);
-MVT::ValueType EVT = LN0-getLoadVT();
+MVT::ValueType EVT = LN0-getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0-getChain(),
LN0-getBasePtr(), LN0-getSrcValue(),
LN0-getSrcValueOffset(), EVT);
@@ -2014,7 +2014,7 @@
if (N0.getOpcode() == ISD::LOAD !ISD::isNON_EXTLoad(N0.Val)
N0.hasOneUse()) {
LoadSDNode *LN0 = castLoadSDNode(N0);
-MVT::ValueType EVT = LN0-getLoadVT();
+MVT::ValueType EVT = LN0-getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(LN0-getExtensionType(), VT,
LN0-getChain(), LN0-getBasePtr(),
LN0-getSrcValue(),
@@ -2069,7 +2069,7 @@
// fold (sext_inreg (extload x)) - (sextload x)
if (ISD::isEXTLoad(N0.Val)
- EVT == castLoadSDNode(N0)-getLoadVT()
+ EVT == castLoadSDNode(N0)-getLoadedVT()
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = castLoadSDNode(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0-getChain(),
@@ -2081,7 +2081,7 @@
}
// fold (sext_inreg (zextload x)) - (sextload x) iff load has one use
if (ISD::isZEXTLoad(N0.Val) N0.hasOneUse()
- EVT == castLoadSDNode(N0)-getLoadVT()
+ EVT == castLoadSDNode(N0)-getLoadedVT()
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = castLoadSDNode(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0-getChain(),
@@ -3282,7 +3282,7 @@
LoadSDNode *RLD = castLoadSDNode(RHS);
// If this is an EXTLOAD, the VT's must match.
- if (LLD-getLoadVT() == RLD-getLoadVT()) {
+ if (LLD-getLoadedVT() == RLD-getLoadedVT()) {
// FIXME: this conflates two src values, discarding one. This is not
// the right thing to do, but nothing uses srcvalues now. When they
do,
// turn SrcValue into a list of locations.
@@ -3307,7 +3307,7 @@
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.204 - 1.205
LegalizeDAG.cpp updated: 1.401 - 1.402
SelectionDAG.cpp updated: 1.341 - 1.342
TargetLowering.cpp updated: 1.72 - 1.73
---
Log message:
Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.
---
Diffs of the changes: (+102 -118)
DAGCombiner.cpp| 67 ++-
LegalizeDAG.cpp| 90 ++---
SelectionDAG.cpp | 25 --
TargetLowering.cpp | 38 ++
4 files changed, 102 insertions(+), 118 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.204
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.205
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.204 Tue Sep 26 12:44:58 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Oct 3 19:52:21 2006
@@ -217,7 +217,7 @@
SDOperand visitBRCOND(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
-SDOperand visitXEXTLOAD(SDNode *N);
+SDOperand visitLOADX(SDNode *N);
SDOperand visitSTORE(SDNode *N);
SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
@@ -511,9 +511,7 @@
case ISD::BRCOND: return visitBRCOND(N);
case ISD::BR_CC: return visitBR_CC(N);
case ISD::LOAD: return visitLOAD(N);
- case ISD::EXTLOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD: return visitXEXTLOAD(N);
+ case ISD::LOADX: return visitLOADX(N);
case ISD::STORE: return visitSTORE(N);
case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
@@ -1082,12 +1080,12 @@
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (zext_inreg (extload x)) - (zextload x)
- if (N0.getOpcode() == ISD::EXTLOAD) {
+ if (ISD::isEXTLoad(N0.Val)) {
MVT::ValueType EVT = castVTSDNode(N0.getOperand(3))-getVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
@@ -1097,12 +1095,12 @@
}
}
// fold (zext_inreg (sextload x)) - (zextload x) iff load has one use
- if (N0.getOpcode() == ISD::SEXTLOAD N0.hasOneUse()) {
+ if (ISD::isSEXTLoad(N0.Val) N0.hasOneUse()) {
MVT::ValueType EVT = castVTSDNode(N0.getOperand(3))-getVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL MVT::getSizeInBits(EVT))
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
N0.getOperand(1), N0.getOperand(2),
EVT);
@@ -1115,8 +1113,8 @@
// fold (and (load x), 255) - (zextload x, i8)
// fold (and (extload x, i16), 255) - (zextload x, i8)
if (N1C
- (N0.getOpcode() == ISD::LOAD || N0.getOpcode() == ISD::EXTLOAD ||
- N0.getOpcode() == ISD::ZEXTLOAD)
+ (N0.getOpcode() == ISD::LOAD || ISD::isEXTLoad(N0.Val) ||
+ ISD::isZEXTLoad(N0.Val))
N0.hasOneUse()) {
MVT::ValueType EVT, LoadedVT;
if (N1C-getValue() == 255)
@@ -1131,7 +1129,7 @@
LoadedVT = N0.getOpcode() == ISD::LOAD ? VT :
castVTSDNode(N0.getOperand(3))-getVT();
if (EVT != MVT::Other LoadedVT EVT
-(!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
+(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
load
// the correct bytes. For little endian systems, we merely need to read
@@ -1863,7 +1861,7 @@
// fold (sext (load x)) - (sext (truncate (sextload x)))
if (N0.getOpcode() == ISD::LOAD N0.hasOneUse()
- (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD,
N0.getValueType({
+ (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType({
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD,
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.179 - 1.180
LegalizeDAG.cpp updated: 1.385 - 1.386
SelectionDAG.cpp updated: 1.320 - 1.321
SelectionDAGISel.cpp updated: 1.267 - 1.268
---
Log message:
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
---
Diffs of the changes: (+177 -275)
DAGCombiner.cpp | 76 +--
LegalizeDAG.cpp | 87 ++-
SelectionDAG.cpp | 163 ++-
SelectionDAGISel.cpp | 126 ---
4 files changed, 177 insertions(+), 275 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.179
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.180
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.179 Tue Jul 25 15:44:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Aug 7 21:23:41 2006
@@ -510,7 +510,7 @@
}
SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
- std::vectorSDOperand Ops;
+ SmallVectorSDOperand, 8 Ops;
bool Changed = false;
// If the token factor has two operands and one is the entry token, replace
@@ -539,7 +539,7 @@
}
}
if (Changed)
-return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
+return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops[0], Ops.size());
return SDOperand();
}
@@ -1284,7 +1284,7 @@
// Produce a vector of zeros.
SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
std::vectorSDOperand Ops(MVT::getVectorNumElements(VT), El);
- return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops);
+ return DAG.getNode(ISD::BUILD_VECTOR, VT, Ops[0], Ops.size());
}
}
@@ -1953,14 +1953,14 @@
// If this is a conversion of N elements of one type to N elements of another
// type, convert each element. This handles FP-INT cases.
if (SrcBitSize == DstBitSize) {
-std::vectorSDOperand Ops;
+SmallVectorSDOperand, 8 Ops;
for (unsigned i = 0, e = BV-getNumOperands()-2; i != e; ++i) {
Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT,
BV-getOperand(i)));
AddToWorkList(Ops.back().Val);
}
Ops.push_back(*(BV-op_end()-2)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT));
-return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops[0], Ops.size());
}
// Otherwise, we're growing or shrinking the elements. To avoid having to
@@ -1992,7 +1992,7 @@
if (SrcBitSize DstBitSize) {
unsigned NumInputsPerOutput = DstBitSize/SrcBitSize;
-std::vectorSDOperand Ops;
+SmallVectorSDOperand, 8 Ops;
for (unsigned i = 0, e = BV-getNumOperands()-2; i != e;
i += NumInputsPerOutput) {
bool isLE = TLI.isLittleEndian();
@@ -2016,13 +2016,13 @@
Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT));// Add element size.
-return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops[0], Ops.size());
}
// Finally, this must be the case where we are shrinking elements: each input
// turns into multiple outputs.
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
- std::vectorSDOperand Ops;
+ SmallVectorSDOperand, 8 Ops;
for (unsigned i = 0, e = BV-getNumOperands()-2; i != e; ++i) {
if (BV-getOperand(i).getOpcode() == ISD::UNDEF) {
for (unsigned j = 0; j != NumOutputsPerInput; ++j)
@@ -2043,7 +2043,7 @@
}
Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements.
Ops.push_back(DAG.getValueType(DstEltVT));// Add element size.
- return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops);
+ return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, Ops[0], Ops.size());
}
@@ -2448,10 +2448,11 @@
// vector with the inserted element.
if (InVec.getOpcode() == ISD::BUILD_VECTOR isaConstantSDNode(EltNo)) {
unsigned Elt = castConstantSDNode(EltNo)-getValue();
-std::vectorSDOperand Ops(InVec.Val-op_begin(), InVec.Val-op_end());
+SmallVectorSDOperand, 8 Ops(InVec.Val-op_begin(), InVec.Val-op_end());
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.126 - 1.127
LegalizeDAG.cpp updated: 1.315 - 1.316
SelectionDAG.cpp updated: 1.270 - 1.271
SelectionDAGISel.cpp updated: 1.192 - 1.193
---
Log message:
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
---
Diffs of the changes: (+5 -181)
DAGCombiner.cpp | 68
LegalizeDAG.cpp | 94 ---
SelectionDAG.cpp | 16
SelectionDAGISel.cpp |8 ++--
4 files changed, 5 insertions(+), 181 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.127
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.126 Mon Mar 13 12:37:30 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 16 19:40:33 2006
@@ -206,9 +206,7 @@
SDOperand visitFNEG(SDNode *N);
SDOperand visitFABS(SDNode *N);
SDOperand visitBRCOND(SDNode *N);
-SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
-SDOperand visitBRTWOWAY_CC(SDNode *N);
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
@@ -639,9 +637,7 @@
case ISD::FNEG: return visitFNEG(N);
case ISD::FABS: return visitFABS(N);
case ISD::BRCOND: return visitBRCOND(N);
- case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N);
case ISD::BR_CC: return visitBR_CC(N);
- case ISD::BRTWOWAY_CC:return visitBRTWOWAY_CC(N);
case ISD::LOAD: return visitLOAD(N);
case ISD::STORE: return visitSTORE(N);
}
@@ -2219,35 +2215,6 @@
return SDOperand();
}
-SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
- SDOperand Chain = N-getOperand(0);
- SDOperand N1 = N-getOperand(1);
- SDOperand N2 = N-getOperand(2);
- SDOperand N3 = N-getOperand(3);
- ConstantSDNode *N1C = dyn_castConstantSDNode(N1);
-
- // unconditional branch to true mbb
- if (N1C N1C-getValue() == 1)
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
- // unconditional branch to false mbb
- if (N1C N1C-isNullValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
- // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if
- // BRTWOWAY_CC is legal on the target.
- if (N1.getOpcode() == ISD::SETCC
- TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) {
-std::vectorSDOperand Ops;
-Ops.push_back(Chain);
-Ops.push_back(N1.getOperand(2));
-Ops.push_back(N1.getOperand(0));
-Ops.push_back(N1.getOperand(1));
-Ops.push_back(N2);
-Ops.push_back(N3);
-return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
//
SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
@@ -2273,41 +2240,6 @@
return SDOperand();
}
-SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
- SDOperand Chain = N-getOperand(0);
- SDOperand CCN = N-getOperand(1);
- SDOperand LHS = N-getOperand(2);
- SDOperand RHS = N-getOperand(3);
- SDOperand N4 = N-getOperand(4);
- SDOperand N5 = N-getOperand(5);
-
- SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
-castCondCodeSDNode(CCN)-get(), false);
- ConstantSDNode *SCCC = dyn_cast_or_nullConstantSDNode(SCC.Val);
-
- // fold select_cc lhs, rhs, x, x, cc - x
- if (N4 == N5)
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc true, x, y - x
- if (SCCC SCCC-getValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
- // fold select_cc false, x, y - y
- if (SCCC SCCC-isNullValue())
-return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
- // fold to a simpler setcc
- if (SCC.Val SCC.getOpcode() == ISD::SETCC) {
-std::vectorSDOperand Ops;
-Ops.push_back(Chain);
-Ops.push_back(SCC.getOperand(2));
-Ops.push_back(SCC.getOperand(0));
-Ops.push_back(SCC.getOperand(1));
-Ops.push_back(N4);
-Ops.push_back(N5);
-return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops);
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitLOAD(SDNode *N) {
SDOperand Chain= N-getOperand(0);
SDOperand Ptr = N-getOperand(1);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.316
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.315 Wed Mar 15 16:19:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Mar 16 19:40:33 2006
@@ -945,100 +945,6 @@
break;
}
break;
- case ISD::BRCONDTWOWAY:
-Tmp1 = LegalizeOp(Node-getOperand(0)); // Legalize the chain.
-switch
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.103 - 1.104
LegalizeDAG.cpp updated: 1.305 - 1.306
SelectionDAG.cpp updated: 1.256 - 1.257
---
Log message:
kill ADD_PARTS SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
---
Diffs of the changes: (+47 -62)
DAGCombiner.cpp | 46
LegalizeDAG.cpp | 57 +--
SelectionDAG.cpp |6 +++--
3 files changed, 47 insertions(+), 62 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.104
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.103 Thu Feb 16 15:11:51 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 16 23:43:56 2006
@@ -157,14 +157,11 @@
SDOperand visitSELECT(SDNode *N);
SDOperand visitSELECT_CC(SDNode *N);
SDOperand visitSETCC(SDNode *N);
-SDOperand visitADD_PARTS(SDNode *N);
-SDOperand visitSUB_PARTS(SDNode *N);
SDOperand visitSIGN_EXTEND(SDNode *N);
SDOperand visitZERO_EXTEND(SDNode *N);
SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
SDOperand visitTRUNCATE(SDNode *N);
SDOperand visitBIT_CONVERT(SDNode *N);
-
SDOperand visitFADD(SDNode *N);
SDOperand visitFSUB(SDNode *N);
SDOperand visitFMUL(SDNode *N);
@@ -183,7 +180,6 @@
SDOperand visitBRCONDTWOWAY(SDNode *N);
SDOperand visitBR_CC(SDNode *N);
SDOperand visitBRTWOWAY_CC(SDNode *N);
-
SDOperand visitLOAD(SDNode *N);
SDOperand visitSTORE(SDNode *N);
@@ -550,8 +546,6 @@
case ISD::SELECT: return visitSELECT(N);
case ISD::SELECT_CC: return visitSELECT_CC(N);
case ISD::SETCC: return visitSETCC(N);
- case ISD::ADD_PARTS: return visitADD_PARTS(N);
- case ISD::SUB_PARTS: return visitSUB_PARTS(N);
case ISD::SIGN_EXTEND:return visitSIGN_EXTEND(N);
case ISD::ZERO_EXTEND:return visitZERO_EXTEND(N);
case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N);
@@ -1509,46 +1503,6 @@
castCondCodeSDNode(N-getOperand(2))-get());
}
-SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) {
- SDOperand LHSLo = N-getOperand(0);
- SDOperand RHSLo = N-getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, 0) + (b_Hi, b_Lo) - (b_Hi + a_Hi, b_Lo)
- if (TLI.MaskedValueIsZero(LHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::ADD, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, RHSLo, Hi);
-return SDOperand();
- }
- // fold (a_Hi, a_Lo) + (b_Hi, 0) - (a_Hi + b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::ADD, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, LHSLo, Hi);
-return SDOperand();
- }
- return SDOperand();
-}
-
-SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) {
- SDOperand LHSLo = N-getOperand(0);
- SDOperand RHSLo = N-getOperand(2);
- MVT::ValueType VT = LHSLo.getValueType();
-
- // fold (a_Hi, a_Lo) - (b_Hi, 0) - (a_Hi - b_Hi, a_Lo)
- if (TLI.MaskedValueIsZero(RHSLo, (1ULL MVT::getSizeInBits(VT))-1)) {
-SDOperand Hi = DAG.getNode(ISD::SUB, VT, N-getOperand(1),
- N-getOperand(3));
-WorkList.push_back(Hi.Val);
-CombineTo(N, LHSLo, Hi);
-return SDOperand();
- }
- return SDOperand();
-}
-
SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDOperand N0 = N-getOperand(0);
ConstantSDNode *N0C = dyn_castConstantSDNode(N0);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.306
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.305 Thu Feb 16 22:32:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Feb 16 23:43:56 2006
@@ -575,7 +575,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
break;
}
-break;
+break;
case ISD::Constant:
// We know we don't need to expand constants here, constants only have one
@@ -1749,8 +1749,6 @@
}
break;
- case ISD::ADD_PARTS:
- case ISD::SUB_PARTS:
case ISD::SHL_PARTS:
case ISD::SRA_PARTS:
case ISD::SRL_PARTS: {
@@ -1830,7 +1828,32 @@
break;
}
break;
+
+ case ISD::ADDC:
+ case ISD::SUBC:
+Tmp1 = LegalizeOp(Node-getOperand(0));
+Tmp2 = LegalizeOp(Node-getOperand(1));
+Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
+// Since this produces two values, make sure to remember that we legalized
+// both of
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.79 - 1.80
LegalizeDAG.cpp updated: 1.258 - 1.259
SelectionDAG.cpp updated: 1.235 - 1.236
---
Log message:
Add bswap, rotl, and rotr nodes
Add dag combiner code to recognize rotl, rotr
Add ppc code to match rotl
Targets should add rotl/rotr patterns if they have them
---
Diffs of the changes: (+65 -2)
DAGCombiner.cpp | 38 --
LegalizeDAG.cpp | 18 ++
SelectionDAG.cpp | 11 +++
3 files changed, 65 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.79
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.80
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.79 Thu Jan 5 19:56:02 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jan 11 15:21:00 2006
@@ -1133,8 +1133,6 @@
N1),
DAG.getConstant(N1C-getValue() | C1-getValue(), VT));
}
-
-
// fold (or (setcc x), (setcc y)) - (setcc (or x, y))
if (isSetCCEquivalent(N0, LL, LR, CC0) isSetCCEquivalent(N1, RL, RR,
CC1)){
ISD::CondCode Op0 = castCondCodeSDNode(CC0)-get();
@@ -1180,6 +1178,42 @@
WorkList.push_back(ORNode.Val);
return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
}
+ // canonicalize shl to left side in a shl/srl pair, to match rotate
+ if (N0.getOpcode() == ISD::SRL N1.getOpcode() == ISD::SHL)
+std::swap(N0, N1);
+ // check for rotl, rotr
+ if (N0.getOpcode() == ISD::SHL N1.getOpcode() == ISD::SRL
+ N0.getOperand(0) == N1.getOperand(0)
+ TLI.isOperationLegal(ISD::ROTL, VT)) {
+// fold (or (shl x, C1), (srl x, C2)) - (rotl x, C1)
+if (N0.getOperand(1).getOpcode() == ISD::Constant
+N1.getOperand(1).getOpcode() == ISD::Constant) {
+ uint64_t c1val = castConstantSDNode(N0.getOperand(1))-getValue();
+ uint64_t c2val = castConstantSDNode(N1.getOperand(1))-getValue();
+ if ((c1val + c2val) == OpSizeInBits)
+return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1));
+}
+// fold (or (shl x, y), (srl x, (sub 32, y))) - (rotl x, y)
+if (N1.getOperand(1).getOpcode() == ISD::SUB
+N0.getOperand(1) == N1.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_castConstantSDNode(N1.getOperand(1).getOperand(0)))
+if (SUBC-getValue() == OpSizeInBits)
+ return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
N0.getOperand(1));
+// fold (or (shl x, (sub 32, y)), (srl x, r)) - (rotr x, y)
+if (N0.getOperand(1).getOpcode() == ISD::SUB
+N1.getOperand(1) == N0.getOperand(1).getOperand(1))
+ if (ConstantSDNode *SUBC =
+ dyn_castConstantSDNode(N0.getOperand(1).getOperand(0)))
+if (SUBC-getValue() == OpSizeInBits) {
+ if (TLI.isOperationLegal(ISD::ROTR, VT))
+return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
+ N1.getOperand(1));
+ else
+return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0),
+ N0.getOperand(1));
+}
+ }
return SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.258
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.259
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.258 Tue Jan 10 13:43:26 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 11 15:21:00 2006
@@ -2112,6 +2112,24 @@
}
break;
+ case ISD::ROTL:
+ case ISD::ROTR:
+Tmp1 = LegalizeOp(Node-getOperand(0)); // LHS
+Tmp2 = LegalizeOp(Node-getOperand(1)); // RHS
+switch (TLI.getOperationAction(Node-getOpcode(), Node-getValueType(0))) {
+case TargetLowering::Custom:
+case TargetLowering::Promote:
+case TargetLowering::Expand:
+ assert(0 Cannot handle this yet!);
+case TargetLowering::Legal:
+ if (Tmp1 != Node-getOperand(0) ||
+ Tmp2 != Node-getOperand(1))
+Result = DAG.getNode(Node-getOpcode(), Node-getValueType(0), Tmp1,
+ Tmp2);
+ break;
+}
+break;
+
case ISD::CTPOP:
case ISD::CTTZ:
case ISD::CTLZ:
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.235
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.236
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.235Mon Jan 9
12:29:18 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Jan 11 15:21:00 2006
@@ -983,6 +983,8 @@
case ISD::SHL:
case ISD::SRA:
case ISD::SRL:
+ case ISD::ROTL:
+ case ISD::ROTR:
assert(VT == N1.getValueType()
Shift operators return type must be the same as their first arg);
assert(MVT::isInteger(VT) MVT::isInteger(N2.getValueType())
@@ -1039,6 +1041,12 @@
