Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
On Jun 29, 2007, at 1:10 AM, Duncan Sands wrote: > Hi, > > It seems like folding undef/X to undef isn't safe either though, > > here is my understanding of how to fold undef. I hope it clarifies > this confusing area. Of course, I could be confused myself but I > hope not :) > > (1) When is it OK to fold "y=foo(undef)" to "y=undef"? I claim that > it is OK if and only if foo is surjective, i.e. if for each possible > value for y there exists a value for x such that y=foo(x). > "Surjective" > is sometimes called "onto". > > Before I explain why I think this, an example: > y=(undef == z) > The possible values of y are 0 and 1 because the result of == is > an i1. Surjectivity means: can I get (undef==z) to produce each of > 0 and 1 by plugging in different values for undef? Obviously I can, > so in this case I can fold to "y=undef". Yep, I agree. > (2) What to do when foo is not surjective? Choose some value for > undef > and fold to "y=foo(value_chosen)". In general foo will involve some > other variables, so the trick is to find a constant value for y > that is > always obtainable no matter what those other variables are (while > it is > logically correct to replace y with a function of those other > variables, > which is what foo(0) will give in general for example, it is more > efficient > to use a constant value if possible). > > Example: folding "y=undef udiv x". This could be folded to 0 or to 1, > since 0 is what you get by substituting undef=0, and 1 is what you get > by substituting undef=x. (If x=0 then in both cases you get 0/0 which > is, I hear, undefined so you can choose it to be 0 or 1 as you like). > Of course you could also fold it to "1 div x" or "intmax div x" or > "(x*x) div x" if you really felt like it, but 0 and 1 are the only > constants that can always be obtained regardless of the value of x, > so they are the most efficient choices. Yes. Duncan, this whole write-up is very helpful. Can you find some place to put this so that we can find it again in the future? How about the programmer's manual? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jul 3, 2007, at 2:13 PM, Dan Gohman wrote: >>> We overload ISD::FADD and quite a lot of others. Why not >>> ISD::ConstantFP too? >> >> Fair enough, after pondering on it, I agree with you. The proposed >> semantics are that a ConstantFP (and also a normal Constant?) produce >> the splatted immediate value? > > Constant sounds good too. And UNDEF, for that matter. And yes, > that's the > semantics I mean. Ok, makes sense. I think we already use UNDEF for vectors. >> Please add a dag combine xform from build_vector [c,c,c,c] -> >> constantfp and friends. > > I sketched out some of the code for this. One question that's come > up so far is > whether if the vector has some undef elements but all the non-undef > elements > are equal it should still be folded. My initial preference is to > still fold it, > since that lets things like isBuildVectorAllZeros become trivial to > unnecessary, > but it is a pessimization in some obscure cases. I'm not sure about it. One specific issue is with shuffle masks, which we want to retain the undef element values for. I don't think there is a good way to retain shuffle masks but not other build vectors, so we probably need to keep the individual undef elements in it. isBuildVectorAllZeros and friends are another issue. To me there are actually two issues that should be resolved at some point: 1. vector constant and shuffle mask matching code is crazily complex, particularly in the x86 backend. For vector constants, this is only slightly annoying. For vector shuffle masks, the selected shuffles are currently whatever is best for yonah, and it's not really possible to prefer different shuffles on different subtargets. We really want to add a layer of abstraction in the shuffle/constant matching code, which would make the undef handling stuff happen implicitly. Making a more declarative description of the various masks would make it much easier to maintain, understand, and debug. 2. the x86 backend specifically has a problem with the way it selects vector constants (I think this is in the readme). In particular, if you have a 4 x f32 and a 4 x i32 zero vector, you'll get two different pxor instructions, because they are of different type. There are two different ways to solve this problem: The easy answer is to do what the ppc backend does. It always selects zero (and -1) vectors to 4 x i32 IIRC, and then does a bitcast to the desired type if needed. This ensures that the constant vectors always get CSEd. The tricky part of this is to ensure that the 0/-1 vectors still get folded if you have operations (like ~) that require one of these as an operand. This ugliness is why we have "vnot" and "vnot_conv" and have to duplicate patterns. The better fix is to change the way the select phase produces code. In particular, the reason these two zero vectors don't get CSE'd after selection is because they have two different value types, and the autocse stuff doesn't "know" that the two VTs end up in the same register class. To solve this, it seems like we can add a new MVT type, where a certain range of MVTs (128-255?) correspond to register class ID's. At selection time, instead of giving the new nodes their old MVT's, they would get new MVT's that correspond to the regclass of the result (ok, we'd keep MVT::Other, MVT::Flag and maybe some others). This makes the scheduler slightly simpler (because it doesn't need to map MVT -> regclass) anymore, and opens up future possibilities. In particular, it lets us fix a long-standing class of issues where we can't have fp stack and SSE registers around at the same time, both with MVT::f32 or f64 type. The current scheduler can only map f32 to one register class (thus, it can't keep the distinction) but with this change the select pass can pick any regclass it wants. Anyway, this is a bit of a crazy tangent, but I think undef's in buildvector should probably stay :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
>> We overload ISD::FADD and quite a lot of others. Why not >> ISD::ConstantFP too? > > Fair enough, after pondering on it, I agree with you. The proposed > semantics are that a ConstantFP (and also a normal Constant?) produce > the splatted immediate value? Constant sounds good too. And UNDEF, for that matter. And yes, that's the semantics I mean. > If so, this sounds fine. This should also reduce codegen memory > usage for many common cases, a very nice bonus :) :) > Please add a dag combine xform from build_vector [c,c,c,c] -> > constantfp and friends. I sketched out some of the code for this. One question that's come up so far is whether if the vector has some undef elements but all the non-undef elements are equal it should still be folded. My initial preference is to still fold it, since that lets things like isBuildVectorAllZeros become trivial to unnecessary, but it is a pessimization in some obscure cases. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jun 29, 2007, at 12:38 PM, Dan Gohman wrote: >>> Just as there isn't a special ADD node kind for vectors -- just >>> an ADD >>> kind with nodes that can have a vector ValueType, ConstantFP can >>> also >>> be "vectorized". A ConstantFP with a vector ValueType is a vector >>> constant, >>> equivalent to what is currently represented as a splat BUILD_VECTOR, >>> except that it's easier to work with :). >> >> I'm not opposed to doing this, but I don't think we should overload >> ConstantFP() and getConstantFP() for this. Could you make a new >> VectorConstantFP or something? > > We overload ISD::FADD and quite a lot of others. Why not > ISD::ConstantFP too? Fair enough, after pondering on it, I agree with you. The proposed semantics are that a ConstantFP (and also a normal Constant?) produce the splatted immediate value? If so, this sounds fine. This should also reduce codegen memory usage for many common cases, a very nice bonus :) Please add a dag combine xform from build_vector [c,c,c,c] -> constantfp and friends. Thanks Dan, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
>> Just as there isn't a special ADD node kind for vectors -- just an ADD >> kind with nodes that can have a vector ValueType, ConstantFP can also >> be "vectorized". A ConstantFP with a vector ValueType is a vector >> constant, >> equivalent to what is currently represented as a splat BUILD_VECTOR, >> except that it's easier to work with :). > > I'm not opposed to doing this, but I don't think we should overload > ConstantFP() and getConstantFP() for this. Could you make a new > VectorConstantFP or something? We overload ISD::FADD and quite a lot of others. Why not ISD::ConstantFP too? Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> Duncan pointed out that I confused myself. If something is undef, we > can choose to pick any specific value for the undef to pick the > cancellation. Thanks Chris and Duncan for explaining this. I'll submit a fix for the DAGCombiner changes accordingly. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
On Jun 27, 2007, at 1:50 PM, Dan Gohman wrote: I think that undef udiv intmax -> 0, no? If not, plz update instcombine as well. >>> >>> intmax udiv intmax -> 1. >>> It seems like folding undef/X to undef isn't safe either though, >>> with >>> the way it sounds like undef is intended to work. This code: >>> >>> %x = udiv i32 undef, %intmax >>> %y = udiv i32 %x, 2 >>> >>> will always set %y to 0. Maybe instcombine can fold the second >>> udiv by looking through its operands, but it can't safely fold the >>> first. The best it could do is try to fold away all of %x's uses so >>> that %x isn't needed anymore. Duncan pointed out that I confused myself. If something is undef, we can choose to pick any specific value for the undef to pick the cancellation. >> Ug, excellent point. At this point, I'm inclined to just give up >> folding of udiv undefs. What do you think? > > udiv isn't the only one, the way this is going... > > %x = mul i32 undef, 2 > %y = srem i32 %x, 2 This is fine, we fold the mul to 0 (because the undef could be zero). > %x = and i32 undef, 0x > %y = and i32 %x,0x > > and so on for a lot of others. For and, we fold undef to 0 (because the undef could be 0) For or undef, X, we fold to -1, because the undef could be -1. >>> Even simple things like undef+X don't seem to be safe to fold. >>> >>> %x = undef; >>> if (%x >= 0) >>> %z = %y / (%x + 1); // don't divide by undef! >> >> Fortunately, this isn't a problem. LLVM has no copy instruction, so >> the code is really this: >> >>> if (undef >= 0) >>> %z = %y / (undef + 1); // don't divide by undef! >> >> There is nothing that specifies the two undefs are the same value. >> Also, in C, if you have an undefined variable, you aren't guaranteed >> to get the same undef value each time you read the variable, so >> transforming C into LLVM is ok :) > > In C, an uninitialized variable has an "indeterminate value", which is > potentially a trap representation, which can't even be multiplied by > zero without incurring undefined behavior. I don't know where it > suggests that a variable with indeterminate value might be different > on each read though. There have been discussions about this issue on the GCC list. I remember the resolution (they take the same basic approach we do), but I don't remember why. I think a DR may be submitted to the C committee on the issue. IIRC, the basic reason this (allowing an undefined value to have multiple values) bites GCC is due to regalloc. For example, if you have: int x; int y; y = 1; print(x, y); ... y = 2; print(x, y); Because there is no live range for x (just uses) x and y can be allocated to the same register. Doing so causes the value of x to follow the value of y. > LLVM does so have copy instructions. The syntax is a little odd > though, > and the keyword is spelled 'bitcast' ;-). Point taken. :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
On Jun 28, 2007, at 3:09 AM, Duncan Sands wrote: > Hi, > >>> It seems like folding undef/X to undef isn't safe either though, >>> with >>> the way it sounds like undef is intended to work. This code: >>> >>> %x = udiv i32 undef, %intmax >>> %y = udiv i32 %x, 2 >>> >>> will always set %y to 0. Maybe instcombine can fold the second >>> udiv by looking through its operands, but it can't safely fold the >>> first. The best it could do is try to fold away all of %x's uses so >>> that %x isn't needed anymore. > > presumably undef/X should be folded to 0. [This means that undef/0 > gets > folded to 0, not sure if that's OK]. Ah, duncan's right. I confused myself. We can fold undef/x -> 0 because there is some value of the undef where it is always safe to produce zero for any x. In particular, if the undef was 0, x can be anything (if it is also zero, the result is undefined, so zero is fine). -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>>> I think that undef udiv intmax -> 0, no? If not, plz update >>> instcombine as well. >> >> intmax udiv intmax -> 1. >> >> It seems like folding undef/X to undef isn't safe either though, with >> the way it sounds like undef is intended to work. This code: >> >> %x = udiv i32 undef, %intmax >> %y = udiv i32 %x, 2 >> >> will always set %y to 0. Maybe instcombine can fold the second >> udiv by looking through its operands, but it can't safely fold the >> first. The best it could do is try to fold away all of %x's uses so >> that %x isn't needed anymore. > > Ug, excellent point. At this point, I'm inclined to just give up > folding of udiv undefs. What do you think? udiv isn't the only one, the way this is going... %x = mul i32 undef, 2 %y = srem i32 %x, 2 %x = and i32 undef, 0x %y = and i32 %x,0x and so on for a lot of others. add, sub, and xor, might be different though; the example below is relevant. >> Even simple things like undef+X don't seem to be safe to fold. >> >> %x = undef; >> if (%x >= 0) >> %z = %y / (%x + 1); // don't divide by undef! > > Fortunately, this isn't a problem. LLVM has no copy instruction, so > the code is really this: > >> if (undef >= 0) >> %z = %y / (undef + 1); // don't divide by undef! > > There is nothing that specifies the two undefs are the same value. > Also, in C, if you have an undefined variable, you aren't guaranteed > to get the same undef value each time you read the variable, so > transforming C into LLVM is ok :) In C, an uninitialized variable has an "indeterminate value", which is potentially a trap representation, which can't even be multiplied by zero without incurring undefined behavior. I don't know where it suggests that a variable with indeterminate value might be different on each read though. LLVM does so have copy instructions. The syntax is a little odd though, and the keyword is spelled 'bitcast' ;-). %x = bitcast i64 undef to i64; if (%x >= 0) %z = %y / (%x + 1); // don't divide by undef! Now what should instcombine do? Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
>> I think that undef udiv intmax -> 0, no? If not, plz update >> instcombine as well. > > intmax udiv intmax -> 1. > > It seems like folding undef/X to undef isn't safe either though, with > the way it sounds like undef is intended to work. This code: > > %x = udiv i32 undef, %intmax > %y = udiv i32 %x, 2 > > will always set %y to 0. Maybe instcombine can fold the second > udiv by looking through its operands, but it can't safely fold the > first. The best it could do is try to fold away all of %x's uses so > that %x isn't needed anymore. Ug, excellent point. At this point, I'm inclined to just give up folding of udiv undefs. What do you think? > Even simple things like undef+X don't seem to be safe to fold. > > %x = undef; > if (%x >= 0) > %z = %y / (%x + 1); // don't divide by undef! Fortunately, this isn't a problem. LLVM has no copy instruction, so the code is really this: > if (undef >= 0) > %z = %y / (undef + 1); // don't divide by undef! There is nothing that specifies the two undefs are the same value. Also, in C, if you have an undefined variable, you aren't guaranteed to get the same undef value each time you read the variable, so transforming C into LLVM is ok :) > (offtopic, wouldn't it be nifty to have a parser for LLVM that > used a C-ish expression syntax?). Hopefully I'll check in a new parser in a few weeks for llvm that accepts something very *very* similar to C. :) -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jun 27, 2007, at 7:59 AM, Dan Gohman wrote:
>>> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>>> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
>>> lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
>>> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409Fri Jun 22
>>> 09:59:07 2007
>>> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 25
>>> 11:23:39 2007
>>> @@ -673,7 +673,9 @@
>>> SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType
>>> VT,
>>>bool isTarget) {
>>>assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP
>>> constant!");
>>> - if (VT == MVT::f32)
>>> + MVT::ValueType EltVT =
>>> +MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
>>
>> I don't understand this change. getConstantFP shouldn't be called on
>> vectors, should it? This seems to be a strange thing to overload.
>
> Oops; that's a small part of an unrelated set of changes I'm working
> on. That code isn't used currently.
>
> Just as there isn't a special ADD node kind for vectors -- just an ADD
> kind with nodes that can have a vector ValueType, ConstantFP can also
> be "vectorized". A ConstantFP with a vector ValueType is a vector
> constant,
> equivalent to what is currently represented as a splat BUILD_VECTOR,
> except that it's easier to work with :).
I'm not opposed to doing this, but I don't think we should overload
ConstantFP() and getConstantFP() for this. Could you make a new
VectorConstantFP or something?
-Chris
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+ + // If either operand is undef, the result is undef + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) +return DAG.getNode(ISD::UNDEF, VT); + return SDOperand(); } >>> >>> This is not safe for sdiv/udiv. Safe xforms are: >>> >>>// undef / X -> 0 >>>// X / undef -> undef >>> >>> If in doubt, plz check instcombine. >> >> Thanks for correcting me on the undef rules. I'll check in a fix >> for the code soon. For this sdiv/udiv one though, why is undef/X not >> undef? For any non-zero value of X there's at least one value the >> undef might have which makes the divide have a non-zero result. > > I think that undef udiv intmax -> 0, no? If not, plz update > instcombine as well. intmax udiv intmax -> 1. It seems like folding undef/X to undef isn't safe either though, with the way it sounds like undef is intended to work. This code: %x = udiv i32 undef, %intmax %y = udiv i32 %x, 2 will always set %y to 0. Maybe instcombine can fold the second udiv by looking through its operands, but it can't safely fold the first. The best it could do is try to fold away all of %x's uses so that %x isn't needed anymore. Even simple things like undef+X don't seem to be safe to fold. %x = undef; if (%x >= 0) %z = %y / (%x + 1); // don't divide by undef! (offtopic, wouldn't it be nifty to have a parser for LLVM that used a C-ish expression syntax?). It seems that only undef*0 and undef+0 and a few similar things are really safe here. And those aren't specific to undef. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
>> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
>> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
>> lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
>> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 Fri Jun 22
>> 09:59:07 2007
>> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jun 25
>> 11:23:39 2007
>> @@ -673,7 +673,9 @@
>> SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT,
>>bool isTarget) {
>>assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP
>> constant!");
>> - if (VT == MVT::f32)
>> + MVT::ValueType EltVT =
>> +MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
>
> I don't understand this change. getConstantFP shouldn't be called on
> vectors, should it? This seems to be a strange thing to overload.
Oops; that's a small part of an unrelated set of changes I'm working
on. That code isn't used currently.
Just as there isn't a special ADD node kind for vectors -- just an ADD
kind with nodes that can have a vector ValueType, ConstantFP can also
be "vectorized". A ConstantFP with a vector ValueType is a vector constant,
equivalent to what is currently represented as a splat BUILD_VECTOR,
except that it's easier to work with :).
Dan
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
> --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.500 Fri Jun 22
> 09:59:07 2007
> +++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jun 25
> 11:23:39 2007
> @@ -173,15 +173,13 @@
> + /// ScalarizeVectorOp - Given an operand of vector type, convert
> it into the
> + /// equivalent operation that returns a scalar value.
> + SDOperand ScalarizeVectorOp(SDOperand O);
This comment should explicitly mention that the function is only
supposed to be called on single-element vector types.
> Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 llvm/
> lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.410
> --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.409 Fri Jun 22
> 09:59:07 2007
> +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cppMon Jun 25
> 11:23:39 2007
> @@ -673,7 +673,9 @@
> SDOperand SelectionDAG::getConstantFP(double Val, MVT::ValueType VT,
>bool isTarget) {
>assert(MVT::isFloatingPoint(VT) && "Cannot create integer FP
> constant!");
> - if (VT == MVT::f32)
> + MVT::ValueType EltVT =
> +MVT::isVector(VT) ? MVT::getVectorElementType(VT) : VT;
I don't understand this change. getConstantFP shouldn't be called on
vectors, should it? This seems to be a strange thing to overload.
-Chris
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> Thanks for all the review comments! I've addressed a few comments > below; I'll get to the others soon. Thanks! I also filed pr1529, which is the only failure that showed on the ppc nightly tester. >>> @@ -1162,6 +1179,11 @@ >>> SDOperand Op = BuildSDIV(N); >>> if (Op.Val) return Op; >>>} >>> + >>> + // If either operand is undef, the result is undef >>> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) >>> +return DAG.getNode(ISD::UNDEF, VT); >>> + >>>return SDOperand(); >>> } >> >> This is not safe for sdiv/udiv. Safe xforms are: >> >>// undef / X -> 0 >>// X / undef -> undef >> >> If in doubt, plz check instcombine. > > Thanks for correcting me on the undef rules. I'll check in a fix > for the code soon. For this sdiv/udiv one though, why is undef/X not > undef? For any non-zero value of X there's at least one value the > undef might have which makes the divide have a non-zero result. I think that undef udiv intmax -> 0, no? If not, plz update instcombine as well. >>> @@ -2742,6 +2807,30 @@ >>>SDOperand N0 = N->getOperand(0); >>>MVT::ValueType VT = N->getValueType(0); >>> >>> + // If the input is a BUILD_VECTOR with all constant elements, >>> fold this now. >>> + // Only do this before legalize, since afterward the target may >>> be depending >>> + // on the bitconvert. >> >> Interesting. This is a good solution for now, but maybe this argues >> for having a "target build vector", like "target constant", which >> would be unmolested by the optimizer? > > It's a similar situation for SimplifyVBinOp, and a few other > places, as > you noticed, and we don't want to clone all those if we don't need to. > An alternative would be to replace the conservative checks with > specific checks for >!AfterLegalize || TLI.isOperationLegal() > as is done in other places to protect against creating illegal nodes. I think it certainly would be better to check isOperationLegal. The only hard part is that some operations (like buildvector) are legal with certain operands. We don't have a way to capture that. :( >>> +MVT::ValueType VT = MVT::getVectorType(DstEltVT, >>> + Ops.size()); >>> +return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); >> >> This idiom occurs in several places. Do you think it makes sense to >> have a helper method on SelectionDAG to do this? > > Sure. Thanks for all the great changes Dan! -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Hi Chris, Thanks for all the review comments! I've addressed a few comments below; I'll get to the others soon. >> @@ -1162,6 +1179,11 @@ >> SDOperand Op = BuildSDIV(N); >> if (Op.Val) return Op; >>} >> + >> + // If either operand is undef, the result is undef >> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) >> +return DAG.getNode(ISD::UNDEF, VT); >> + >>return SDOperand(); >> } > > This is not safe for sdiv/udiv. Safe xforms are: > >// undef / X -> 0 >// X / undef -> undef > > If in doubt, plz check instcombine. Thanks for correcting me on the undef rules. I'll check in a fix for the code soon. For this sdiv/udiv one though, why is undef/X not undef? For any non-zero value of X there's at least one value the undef might have which makes the divide have a non-zero result. >> @@ -2742,6 +2807,30 @@ >>SDOperand N0 = N->getOperand(0); >>MVT::ValueType VT = N->getValueType(0); >> >> + // If the input is a BUILD_VECTOR with all constant elements, >> fold this now. >> + // Only do this before legalize, since afterward the target may >> be depending >> + // on the bitconvert. > > Interesting. This is a good solution for now, but maybe this argues > for having a "target build vector", like "target constant", which > would be unmolested by the optimizer? It's a similar situation for SimplifyVBinOp, and a few other places, as you noticed, and we don't want to clone all those if we don't need to. An alternative would be to replace the conservative checks with specific checks for !AfterLegalize || TLI.isOperationLegal() as is done in other places to protect against creating illegal nodes. >> +MVT::ValueType VT = MVT::getVectorType(DstEltVT, >> + Ops.size()); >> +return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); > > This idiom occurs in several places. Do you think it makes sense to > have a helper method on SelectionDAG to do this? Sure. Dan -- Dan Gohman, Cray Inc. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Another great change.
> @@ -856,6 +844,10 @@
>ConstantSDNode *N0C = dyn_cast(N0);
>ConstantSDNode *N1C = dyn_cast(N1);
>MVT::ValueType VT = N0.getValueType();
> +
> + // fold vector ops
> + SDOperand FoldedVOp = SimplifyVBinOp(N);
> + if (FoldedVOp.Val) return FoldedVOp;
I'm concerned that this adds a significant amount of control flow for
non-vector operations. What do you think of:
// fold vector ops
if (MVT::isVector(N->getValueType(VT))) {
SDOperand FoldedVOp = SimplifyVBinOp(N);
if (FoldedVOp.Val) return FoldedVOp;
}
for each of these?
> @@ -1098,6 +1106,11 @@
>SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1);
>if (RMUL.Val != 0)
> return RMUL;
> +
> + // If either operand is undef, the result is undef
> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
> +return DAG.getNode(ISD::UNDEF, VT);
> +
>return SDOperand();
> }
This isn't safe for multiply. In particular, undef*X could be well
defined to be 0 if X is dynamically always zero. As such, this
should return Zero. Note that this should return vector zero (or
disable the xform) in the vector case.
This xform is safe for add/sub, because there is no defined value
that (when combined with an undef) can produce a defined result.
> @@ -1162,6 +1179,11 @@
> SDOperand Op = BuildSDIV(N);
> if (Op.Val) return Op;
>}
> +
> + // If either operand is undef, the result is undef
> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
> +return DAG.getNode(ISD::UNDEF, VT);
> +
>return SDOperand();
> }
This is not safe for sdiv/udiv. Safe xforms are:
// undef / X -> 0
// X / undef -> undef
If in doubt, plz check instcombine.
> @@ -1229,6 +1260,10 @@
> return Sub;
>}
>
> + // If either operand is undef, the result is undef
> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
> +return DAG.getNode(ISD::UNDEF, VT);
> +
>return SDOperand();
> }
// undef % X -> 0
// X % undef -> undef
for both srem and urem.
> @@ -1283,6 +1323,10 @@
> return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
> DAG.getConstant(MVT::getSizeInBits
> (N0.getValueType())-1,
> TLI.getShiftAmountTy()));
> + // If either operand is undef, the result is undef
> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
> +return DAG.getNode(ISD::UNDEF, VT);
mulhs/mulhu seem to be the same as mul, they should produce zero
instead of undef.
> @@ -1336,6 +1385,10 @@
> return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1));
>}
>
> + // If either operand is undef, the result is undef
> + if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)
> +return DAG.getNode(ISD::UNDEF, VT);
I think this is dead. The only way to get into this code is if N0-
>opcode == N1->opcode.
> @@ -2742,6 +2807,30 @@
>SDOperand N0 = N->getOperand(0);
>MVT::ValueType VT = N->getValueType(0);
>
> + // If the input is a BUILD_VECTOR with all constant elements,
> fold this now.
> + // Only do this before legalize, since afterward the target may
> be depending
> + // on the bitconvert.
Interesting. This is a good solution for now, but maybe this argues
for having a "target build vector", like "target constant", which
would be unmolested by the optimizer?
> +MVT::ValueType VT = MVT::getVectorType(DstEltVT,
> + Ops.size());
> +return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
This idiom occurs in several places. Do you think it makes sense to
have a helper method on SelectionDAG to do this?
> +SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
> + // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of
> + // EXTRACT_SUBVECTOR operations. If so, and if the
> EXTRACT_SUBVECTOR vector
> + // inputs come from at most two distinct vectors, turn this into
> a shuffle
> + // node.
Also, if they come from a single vector with the right subvectors, it
could be a noop :)
> @@ -4177,24 +4121,28 @@
>return SDOperand();
> }
>
> +/// SimplifyVBinOp - Visit a binary vector operation, like ADD.
> +SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) {
> + // After legalize, the target may be depending on adds and other
> + // binary ops to provide legal ways to construct constants or other
> + // things. Simplifying them may result in a loss of legality.
> + if (AfterLegalize) return SDOperand();
It would be nice if this wasn't required :(
More tomorrow. Thanks again for tackling this Dan!
-Chris
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp TargetLowering.cpp
On Jun 22, 2007, at 7:59 AM, Dan Gohman wrote: > Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from > TargetLowering to SelectionDAG so that they have more convenient > access to the current DAG, in preparation for the ValueType routines > being changed from standalone functions to members of SelectionDAG for > the pre-legalize vector type changes. Ah, that's also a much more logical place for them anyway. They originally started out in DAGCombine, this is their third home :). Thanks Dan, -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.313 -> 1.314
---
Log message:
Xforms:
(add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
(sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
---
Diffs of the changes: (+64 -0)
DAGCombiner.cpp | 64
1 files changed, 64 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.313
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.314
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.313 Tue Jun 19 09:13:56 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 21 02:39:16 2007
@@ -801,6 +801,55 @@
return SDOperand();
}
+static
+SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp,
+ SelectionDAG &DAG) {
+ MVT::ValueType VT = N->getValueType(0);
+ unsigned Opc = N->getOpcode();
+ bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC;
+ SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1);
+ SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2);
+ ISD::CondCode CC = ISD::SETCC_INVALID;
+ if (isSlctCC)
+CC = cast(Slct.getOperand(4))->get();
+ else {
+SDOperand CCOp = Slct.getOperand(0);
+if (CCOp.getOpcode() == ISD::SETCC)
+ CC = cast(CCOp.getOperand(2))->get();
+ }
+
+ bool DoXform = false;
+ bool InvCC = false;
+ assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) &&
+ "Bad input!");
+ if (LHS.getOpcode() == ISD::Constant &&
+ cast(LHS)->isNullValue())
+DoXform = true;
+ else if (CC != ISD::SETCC_INVALID &&
+ RHS.getOpcode() == ISD::Constant &&
+ cast(RHS)->isNullValue()) {
+std::swap(LHS, RHS);
+bool isInt = MVT::isInteger(isSlctCC ? Slct.getOperand(0).getValueType()
+:
Slct.getOperand(0).getOperand(0).getValueType());
+CC = ISD::getSetCCInverse(CC, isInt);
+DoXform = true;
+InvCC = true;
+ }
+
+ if (DoXform) {
+SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS);
+if (isSlctCC)
+ return DAG.getSelectCC(OtherOp, Result,
+ Slct.getOperand(0), Slct.getOperand(1), CC);
+SDOperand CCOp = Slct.getOperand(0);
+if (InvCC)
+ CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0),
+ CCOp.getOperand(1), CC);
+return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result);
+ }
+ return SDOperand();
+}
+
SDOperand DAGCombiner::visitADD(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
@@ -869,6 +918,16 @@
if (Result.Val) return Result;
}
+ // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c))
+ if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) {
+SDOperand Result = combineSelectAndUse(N, N0, N1, DAG);
+if (Result.Val) return Result;
+ }
+ if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
+if (Result.Val) return Result;
+ }
+
return SDOperand();
}
@@ -960,6 +1019,11 @@
// fold (A+B)-B -> A
if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
return N0.getOperand(0);
+ // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c))
+ if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) {
+SDOperand Result = combineSelectAndUse(N, N1, N0, DAG);
+if (Result.Val) return Result;
+ }
return SDOperand();
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ScheduleDAG.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.312 -> 1.313
ScheduleDAG.cpp updated: 1.125 -> 1.126
SelectionDAG.cpp updated: 1.407 -> 1.408
---
Log message:
Pass a SelectionDAG into SDNode::dump everywhere it's used, in prepration
for needing the DAG node to print pre-legalize extended value types, and
to get better debug messages with target-specific nodes.
---
Diffs of the changes: (+7 -7)
DAGCombiner.cpp | 10 +-
ScheduleDAG.cpp |2 +-
SelectionDAG.cpp |2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.312
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.313
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.312 Thu Jun 14 17:58:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 19 09:13:56 2007
@@ -113,7 +113,7 @@
bool AddTo = true) {
assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
++NodesCombined;
- DOUT << "\nReplacing.1 "; DEBUG(N->dump());
+ DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
DOUT << " and " << NumTo-1 << " other values\n";
std::vector NowDead;
@@ -164,7 +164,7 @@
// Replace the old value with the new one.
++NodesCombined;
- DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
+ DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG));
DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
DOUT << '\n';
@@ -592,7 +592,7 @@
RV.Val->getOpcode() != ISD::DELETED_NODE &&
"Node was deleted but visit returned new node!");
-DOUT << "\nReplacing.3 "; DEBUG(N->dump());
+DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
DOUT << '\n';
std::vector NowDead;
@@ -3314,7 +3314,7 @@
Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
++PreIndexedNodes;
++NodesCombined;
- DOUT << "\nReplacing.4 "; DEBUG(N->dump());
+ DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
DOUT << '\n';
std::vector NowDead;
@@ -3445,7 +3445,7 @@
: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
++PostIndexedNodes;
++NodesCombined;
-DOUT << "\nReplacing.5 "; DEBUG(N->dump());
+DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG));
DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
DOUT << '\n';
std::vector NowDead;
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.125
llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.126
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.125 Tue Mar 20 15:43:18 2007
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp Tue Jun 19 09:13:56 2007
@@ -476,7 +476,7 @@
switch (Node->getOpcode()) {
default:
#ifndef NDEBUG
- Node->dump();
+ Node->dump(&DAG);
#endif
assert(0 && "This target-independent node should have been selected!");
case ISD::EntryToken: // fall thru
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.407
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.408
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.407Thu Jun 14
17:58:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Jun 19 09:13:56 2007
@@ -512,7 +512,7 @@
// not subject to CSE.
if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
!N->isTargetOpcode()) {
-N->dump();
+N->dump(this);
cerr << "\n";
assert(0 && "Node is not in map!");
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.311 -> 1.312
LegalizeDAG.cpp updated: 1.496 -> 1.497
SelectionDAG.cpp updated: 1.406 -> 1.407
SelectionDAGISel.cpp updated: 1.462 -> 1.463
---
Log message:
Rename MVT::getVectorBaseType to MVT::getVectorElementType.
---
Diffs of the changes: (+10 -10)
DAGCombiner.cpp |2 +-
LegalizeDAG.cpp | 10 +-
SelectionDAG.cpp |4 ++--
SelectionDAGISel.cpp |4 ++--
4 files changed, 10 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.311
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.312
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.311 Thu May 24 21:19:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Jun 14 17:58:02 2007
@@ -1809,7 +1809,7 @@
return DAG.getConstant(0, VT);
} else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) {
// Produce a vector of zeros.
- SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT));
+ SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT));
std::vector Ops(MVT::getVectorNumElements(VT), El);
return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size());
}
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.496
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.497
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.496 Wed Jun 13 10:12:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Jun 14 17:58:02 2007
@@ -1014,7 +1014,7 @@
unsigned NumElts = MVT::getVectorNumElements(Tmp1.getValueType());
MVT::ValueType ShufMaskVT = MVT::getIntVectorWithNumElements(NumElts);
-MVT::ValueType ShufMaskEltVT = MVT::getVectorBaseType(ShufMaskVT);
+MVT::ValueType ShufMaskEltVT = MVT::getVectorElementType(ShufMaskVT);
// We generate a shuffle of InVec and ScVec, so the shuffle mask should
// be 0,1,2,3,4,5... with the appropriate element replaced with elt 0
of
@@ -1110,7 +1110,7 @@
// FALLTHROUGH
case TargetLowering::Expand: {
MVT::ValueType VT = Node->getValueType(0);
- MVT::ValueType EltVT = MVT::getVectorBaseType(VT);
+ MVT::ValueType EltVT = MVT::getVectorElementType(VT);
MVT::ValueType PtrVT = TLI.getPointerTy();
SDOperand Mask = Node->getOperand(2);
unsigned NumElems = Mask.getNumOperands();
@@ -2386,7 +2386,7 @@
"Cannot expand this binary operator!");
// Expand the operation into a bunch of nasty scalar code.
SmallVector Ops;
- MVT::ValueType EltVT = MVT::getVectorBaseType(Node->getValueType(0));
+ MVT::ValueType EltVT = MVT::getVectorElementType(Node->getValueType(0));
MVT::ValueType PtrVT = TLI.getPointerTy();
for (unsigned i = 0, e =
MVT::getVectorNumElements(Node->getValueType(0));
i != e; ++i) {
@@ -4006,7 +4006,7 @@
// Build the shuffle constant vector: <0, 0, 0, 0>
MVT::ValueType MaskVT =
MVT::getIntVectorWithNumElements(NumElems);
-SDOperand Zero = DAG.getConstant(0, MVT::getVectorBaseType(MaskVT));
+SDOperand Zero = DAG.getConstant(0, MVT::getVectorElementType(MaskVT));
std::vector ZeroVec(NumElems, Zero);
SDOperand SplatMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
&ZeroVec[0], ZeroVec.size());
@@ -4036,7 +4036,7 @@
E = Values.end(); I != E; ++I) {
for (std::vector::iterator II = I->second.begin(),
EE = I->second.end(); II != EE; ++II)
-MaskVec[*II] = DAG.getConstant(i, MVT::getVectorBaseType(MaskVT));
+MaskVec[*II] = DAG.getConstant(i, MVT::getVectorElementType(MaskVT));
i += NumElems;
}
SDOperand ShuffleMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.406
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.407
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.406Wed Jun 13
10:12:02 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Jun 14 17:58:02 2007
@@ -1114,7 +1114,7 @@
break;
case ISD::SCALAR_TO_VECTOR:
assert(MVT::isVector(VT) && !MVT::isVector(Operand.getValueType()) &&
- MVT::getVectorBaseType(VT) == Operand.getValueType() &&
+ MVT::getVectorElementType(VT) == Operand.getValueType() &&
"Illegal SCALAR_TO_VECTOR node!");
break;
case ISD::FNEG:
@@ -1593,7 +1593,7 @@
ExtType = ISD::NON_EXTLOAD;
if (MVT::isVector(VT))
-assert(EVT == MVT::getVectorBaseType(VT) && "Invalid vector extload!");
+assert(EVT == MVT::getVectorElementType(VT) && "Invalid vector extload!");
else
assert(EVT < VT && "Should only be an extending load, not truncating!");
assert((ExtT
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.310 -> 1.311
---
Log message:
tighten up recursion depth again
---
Diffs of the changes: (+13 -11)
DAGCombiner.cpp | 24 +---
1 files changed, 13 insertions(+), 11 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.310
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.311
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.310 Wed May 23 21:35:39 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu May 24 21:19:06 2007
@@ -353,15 +353,15 @@
/// specified expression for the same cost as the expression itself, or 2 if we
/// can compute the negated form more cheaply than the expression itself.
static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
- // Don't recurse exponentially.
- if (Depth > 6) return false;
-
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return 2;
// Don't allow anything with multiple uses.
if (!Op.hasOneUse()) return 0;
+ // Don't recurse exponentially.
+ if (Depth > 6) return 0;
+
switch (Op.getOpcode()) {
default: return false;
case ISD::ConstantFP:
@@ -401,13 +401,15 @@
/// GetNegatedExpression - If isNegatibleForFree returns true, this function
/// returns the newly negated expression.
-static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG) {
+static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG,
+ unsigned Depth = 0) {
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
// Don't allow anything with multiple uses.
assert(Op.hasOneUse() && "Unknown reuse!");
+ assert(Depth <= 6 && "GetNegatedExpression doesn't match
isNegatibleForFree");
switch (Op.getOpcode()) {
default: assert(0 && "Unknown code");
case ISD::ConstantFP:
@@ -418,13 +420,13 @@
assert(UnsafeFPMath);
// -(A+B) -> -A - B
-if (isNegatibleForFree(Op.getOperand(0)))
+if (isNegatibleForFree(Op.getOperand(0), Depth+1))
return DAG.getNode(ISD::FSUB, Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG),
+ GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
Op.getOperand(1));
// -(A+B) -> -B - A
return DAG.getNode(ISD::FSUB, Op.getValueType(),
- GetNegatedExpression(Op.getOperand(1), DAG),
+ GetNegatedExpression(Op.getOperand(1), DAG, Depth+1),
Op.getOperand(0));
case ISD::FSUB:
// We can't turn -(A-B) into B-A when we honor signed zeros.
@@ -439,21 +441,21 @@
assert(!HonorSignDependentRoundingFPMath());
// -(X*Y) -> -X * Y
-if (isNegatibleForFree(Op.getOperand(0)))
+if (isNegatibleForFree(Op.getOperand(0), Depth+1))
return DAG.getNode(Op.getOpcode(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG),
+ GetNegatedExpression(Op.getOperand(0), DAG, Depth+1),
Op.getOperand(1));
// -(X*Y) -> X * -Y
return DAG.getNode(Op.getOpcode(), Op.getValueType(),
Op.getOperand(0),
- GetNegatedExpression(Op.getOperand(1), DAG));
+ GetNegatedExpression(Op.getOperand(1), DAG, Depth+1));
case ISD::FP_EXTEND:
case ISD::FP_ROUND:
case ISD::FSIN:
return DAG.getNode(Op.getOpcode(), Op.getValueType(),
- GetNegatedExpression(Op.getOperand(0), DAG));
+ GetNegatedExpression(Op.getOperand(0), DAG, Depth+1));
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.309 -> 1.310
---
Log message:
Fix a typo that caused combiner to create mal-formed pre-indexed store where
value store is the same as the base pointer.
---
Diffs of the changes: (+6 -6)
DAGCombiner.cpp | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.309
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.310
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.309 Wed May 23 02:35:22 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 23 21:35:39 2007
@@ -3267,12 +3267,12 @@
return false;
// Try turning it into a pre-indexed load / store except when:
- // 1) The base is a frame index.
- // 2) If N is a store and the ptr is either the same as or is a
+ // 1) The new base ptr is a frame index.
+ // 2) If N is a store and the new base ptr is either the same as or is a
//predecessor of the value being stored.
- // 3) Another use of base ptr is a predecessor of N. If ptr is folded
+ // 3) Another use of old base ptr is a predecessor of N. If ptr is folded
//that would create a cycle.
- // 4) All uses are load / store ops that use it as base ptr.
+ // 4) All uses are load / store ops that use it as old base ptr.
// Check #1. Preinc'ing a frame index would require copying the stack
pointer
// (plus the implicit offset) to a register to preinc anyway.
@@ -3282,11 +3282,11 @@
// Check #2.
if (!isLoad) {
SDOperand Val = cast(N)->getValue();
-if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
+if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val))
return false;
}
- // Now check for #2 and #3.
+ // Now check for #3 and #4.
bool RealUse = false;
for (SDNode::use_iterator I = Ptr.Val->use_begin(),
E = Ptr.Val->use_end(); I != E; ++I) {
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.308 -> 1.309
---
Log message:
prevent exponential recursion in isNegatibleForFree
---
Diffs of the changes: (+9 -6)
DAGCombiner.cpp | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.308
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.309
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.308 Fri May 18 13:41:29 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 23 02:35:22 2007
@@ -352,7 +352,10 @@
/// isNegatibleForFree - Return 1 if we can compute the negated form of the
/// specified expression for the same cost as the expression itself, or 2 if we
/// can compute the negated form more cheaply than the expression itself.
-static char isNegatibleForFree(SDOperand Op) {
+static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) {
+ // Don't recurse exponentially.
+ if (Depth > 6) return false;
+
// fneg is removable even if it has multiple uses.
if (Op.getOpcode() == ISD::FNEG) return 2;
@@ -368,10 +371,10 @@
if (!UnsafeFPMath) return 0;
// -(A+B) -> -A - B
-if (char V = isNegatibleForFree(Op.getOperand(0)))
+if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
return V;
// -(A+B) -> -B - A
-return isNegatibleForFree(Op.getOperand(1));
+return isNegatibleForFree(Op.getOperand(1), Depth+1);
case ISD::FSUB:
// We can't turn -(A-B) into B-A when we honor signed zeros.
if (!UnsafeFPMath) return 0;
@@ -384,15 +387,15 @@
if (HonorSignDependentRoundingFPMath()) return 0;
// -(X*Y) -> (-X * Y) or (X*-Y)
-if (char V = isNegatibleForFree(Op.getOperand(0)))
+if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1))
return V;
-return isNegatibleForFree(Op.getOperand(1));
+return isNegatibleForFree(Op.getOperand(1), Depth+1);
case ISD::FP_EXTEND:
case ISD::FP_ROUND:
case ISD::FSIN:
-return isNegatibleForFree(Op.getOperand(0));
+return isNegatibleForFree(Op.getOperand(0), Depth+1);
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.307 -> 1.308
---
Log message:
Qualify calls to getTypeForValueType with MVT:: too.
---
Diffs of the changes: (+3 -3)
DAGCombiner.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.307
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.308
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.307 Wed May 16 17:45:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri May 18 13:41:29 2007
@@ -2689,7 +2689,7 @@
TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(getTypeForValueType(VT));
+ getABITypeAlignment(MVT::getTypeForValueType(VT));
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
@@ -3569,7 +3569,7 @@
unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
- getABITypeAlignment(getTypeForValueType(SVT));
+ getABITypeAlignment(MVT::getTypeForValueType(SVT));
if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset());
@@ -3765,7 +3765,7 @@
if (VecIn2.Val) {
Ops[1] = VecIn2;
} else {
- // Use an undef vbuild_vector as input for the second operand.
+ // Use an undef vbuild_vector as input for the second operand.
std::vector UnOps(NumInScalars,
DAG.getNode(ISD::UNDEF,
cast(EltType)->getVT()));
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.306 -> 1.307
---
Log message:
Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores.
---
Diffs of the changes: (+3 -1)
DAGCombiner.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.306
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.307
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.306 Wed May 16 01:37:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 16 17:45:30 2007
@@ -2685,6 +2685,7 @@
// fold (conv (load x)) -> (load (conv*)x)
// If the resultant load doesn't need a higher alignment than the original!
if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+ ISD::isUNINDEXEDLoad(N0.Val) &&
TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
@@ -3563,7 +3564,8 @@
// If this is a store of a bit convert, store the input value if the
// resultant store does not need a higher alignment than the original.
- if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore()) {
+ if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
+ ST->getAddressingMode() == ISD::UNINDEXED) {
unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.305 -> 1.306 --- Log message: Use a ptr set instead of a linear search to unique TokenFactor operands. This fixes PR1423: http://llvm.org/PR1423 --- Diffs of the changes: (+13 -10) DAGCombiner.cpp | 23 +-- 1 files changed, 13 insertions(+), 10 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.305 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.306 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.305 Tue May 15 21:04:50 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 16 01:37:59 2007 @@ -29,17 +29,18 @@ //===--===// #define DEBUG_TYPE "dagcombine" -#include "llvm/ADT/Statistic.h" -#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/MathExtras.h" +#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/ADT/SmallPtrSet.h" +#include "llvm/ADT/Statistic.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/MathExtras.h" #include using namespace llvm; @@ -713,10 +714,10 @@ return N->getOperand(1); } - - SmallVector TFs; // List of token factors to visit. - SmallVector Ops; // Ops for replacing token factor. - bool Changed = false; // If we should replace this token factor. + SmallVector TFs; // List of token factors to visit. + SmallVector Ops;// Ops for replacing token factor. + SmallPtrSet SeenOps; + bool Changed = false; // If we should replace this token factor. // Start out with this token factor. TFs.push_back(N); @@ -750,9 +751,11 @@ // Fall thru default: -// Only add if not there prior. -if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) +// Only add if it isn't already in the list. +if (SeenOps.insert(Op.Val)) Ops.push_back(Op); +else + Changed = true; break; } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.304 -> 1.305
---
Log message:
Bug fix: should check ABI alignment, not pref. alignment.
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.304
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.305
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.304 Tue May 15 12:05:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 15 21:04:50 2007
@@ -2685,7 +2685,7 @@
TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast(N0);
unsigned Align = TLI.getTargetMachine().getTargetData()->
- getPrefTypeAlignment(getTypeForValueType(VT));
+ getABITypeAlignment(getTypeForValueType(VT));
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
@@ -3564,7 +3564,7 @@
unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
- getPrefTypeAlignment(getTypeForValueType(SVT));
+ getABITypeAlignment(getTypeForValueType(SVT));
if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT))
return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
ST->getSrcValueOffset());
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> Fix an infinite recursion in GetNegatedExpression. Doh, thanks a lot Lauro! -Chris > > > --- > Diffs of the changes: (+1 -1) > > DAGCombiner.cpp |2 +- > 1 files changed, 1 insertion(+), 1 deletion(-) > > > Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp > diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.303 llvm/ > lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.304 > --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.303 Mon May 14 > 17:04:50 2007 > +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 15 > 12:05:43 2007 > @@ -449,7 +449,7 @@ >case ISD::FP_ROUND: >case ISD::FSIN: > return DAG.getNode(Op.getOpcode(), Op.getValueType(), > - GetNegatedExpression(Op, DAG)); > + GetNegatedExpression(Op.getOperand(0), DAG)); >} > } > > > > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.303 -> 1.304 --- Log message: Fix an infinite recursion in GetNegatedExpression. --- Diffs of the changes: (+1 -1) DAGCombiner.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.303 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.304 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.303 Mon May 14 17:04:50 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 15 12:05:43 2007 @@ -449,7 +449,7 @@ case ISD::FP_ROUND: case ISD::FSIN: return DAG.getNode(Op.getOpcode(), Op.getValueType(), - GetNegatedExpression(Op, DAG)); + GetNegatedExpression(Op.getOperand(0), DAG)); } } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.302 -> 1.303
---
Log message:
implement a simple fneg optimization/propagation thing. This compiles:
CodeGen/PowerPC/fneg.ll into:
_t4:
fmul f0, f3, f4
fmadd f1, f1, f2, f0
blr
instead of:
_t4:
fneg f0, f3
fmul f0, f0, f4
fmsub f1, f1, f2, f0
blr
---
Diffs of the changes: (+144 -7)
DAGCombiner.cpp | 151 +---
1 files changed, 144 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.302
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.303
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.302 Wed May 9 16:49:47 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 14 17:04:50 2007
@@ -344,9 +344,114 @@
}
+//===--===//
+// Helper Functions
+//===--===//
+/// isNegatibleForFree - Return 1 if we can compute the negated form of the
+/// specified expression for the same cost as the expression itself, or 2 if we
+/// can compute the negated form more cheaply than the expression itself.
+static char isNegatibleForFree(SDOperand Op) {
+ // fneg is removable even if it has multiple uses.
+ if (Op.getOpcode() == ISD::FNEG) return 2;
+
+ // Don't allow anything with multiple uses.
+ if (!Op.hasOneUse()) return 0;
+
+ switch (Op.getOpcode()) {
+ default: return false;
+ case ISD::ConstantFP:
+return 1;
+ case ISD::FADD:
+// FIXME: determine better conditions for this xform.
+if (!UnsafeFPMath) return 0;
+
+// -(A+B) -> -A - B
+if (char V = isNegatibleForFree(Op.getOperand(0)))
+ return V;
+// -(A+B) -> -B - A
+return isNegatibleForFree(Op.getOperand(1));
+ case ISD::FSUB:
+// We can't turn -(A-B) into B-A when we honor signed zeros.
+if (!UnsafeFPMath) return 0;
+
+// -(A-B) -> B-A
+return 1;
+
+ case ISD::FMUL:
+ case ISD::FDIV:
+if (HonorSignDependentRoundingFPMath()) return 0;
+
+// -(X*Y) -> (-X * Y) or (X*-Y)
+if (char V = isNegatibleForFree(Op.getOperand(0)))
+ return V;
+
+return isNegatibleForFree(Op.getOperand(1));
+
+ case ISD::FP_EXTEND:
+ case ISD::FP_ROUND:
+ case ISD::FSIN:
+return isNegatibleForFree(Op.getOperand(0));
+ }
+}
-//===--===//
+/// GetNegatedExpression - If isNegatibleForFree returns true, this function
+/// returns the newly negated expression.
+static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG) {
+ // fneg is removable even if it has multiple uses.
+ if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0);
+
+ // Don't allow anything with multiple uses.
+ assert(Op.hasOneUse() && "Unknown reuse!");
+
+ switch (Op.getOpcode()) {
+ default: assert(0 && "Unknown code");
+ case ISD::ConstantFP:
+return DAG.getConstantFP(-cast(Op)->getValue(),
+ Op.getValueType());
+ case ISD::FADD:
+// FIXME: determine better conditions for this xform.
+assert(UnsafeFPMath);
+
+// -(A+B) -> -A - B
+if (isNegatibleForFree(Op.getOperand(0)))
+ return DAG.getNode(ISD::FSUB, Op.getValueType(),
+ GetNegatedExpression(Op.getOperand(0), DAG),
+ Op.getOperand(1));
+// -(A+B) -> -B - A
+return DAG.getNode(ISD::FSUB, Op.getValueType(),
+ GetNegatedExpression(Op.getOperand(1), DAG),
+ Op.getOperand(0));
+ case ISD::FSUB:
+// We can't turn -(A-B) into B-A when we honor signed zeros.
+assert(UnsafeFPMath);
+
+// -(A-B) -> B-A
+return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1),
+ Op.getOperand(0));
+
+ case ISD::FMUL:
+ case ISD::FDIV:
+assert(!HonorSignDependentRoundingFPMath());
+
+// -(X*Y) -> -X * Y
+if (isNegatibleForFree(Op.getOperand(0)))
+ return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+ GetNegatedExpression(Op.getOperand(0), DAG),
+ Op.getOperand(1));
+
+// -(X*Y) -> X * -Y
+return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+ Op.getOperand(0),
+ GetNegatedExpression(Op.getOperand(1), DAG));
+
+ case ISD::FP_EXTEND:
+ case ISD::FP_ROUND:
+ case ISD::FSIN:
+return DAG.getNode(Op.getOpcode(), Op.getValueType(),
+ GetNegatedExpression(Op, DAG));
+ }
+}
// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
@@ -416,6 +521,10 @@
return SDOperand();
}
+//===--===//
+// Ma
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.301 -> 1.302
---
Log message:
Can't fold the bit_convert is the store is a truncating store.
---
Diffs of the changes: (+2 -2)
DAGCombiner.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.301
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.302
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.301 Mon May 7 16:36:06 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed May 9 16:49:47 2007
@@ -3422,8 +3422,8 @@
SDOperand Ptr = ST->getBasePtr();
// If this is a store of a bit convert, store the input value if the
- // resultant store does not need a higher alignment than the original.
- if (Value.getOpcode() == ISD::BIT_CONVERT) {
+ // resultant store does not need a higher alignment than the original.
+ if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore()) {
unsigned Align = ST->getAlignment();
MVT::ValueType SVT = Value.getOperand(0).getValueType();
unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.300 -> 1.301 --- Log message: Forgot a check. --- Diffs of the changes: (+1 -1) DAGCombiner.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.300 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.301 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.300 Mon May 7 16:27:48 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 7 16:36:06 2007 @@ -3428,7 +3428,7 @@ MVT::ValueType SVT = Value.getOperand(0).getValueType(); unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> getPrefTypeAlignment(getTypeForValueType(SVT)); -if (Align <= OrigAlign) +if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), ST->getSrcValueOffset()); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.299 -> 1.300
---
Log message:
Enable a couple of xforms:
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment
---
Diffs of the changes: (+27 -16)
DAGCombiner.cpp | 43 +++
1 files changed, 27 insertions(+), 16 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.299
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.300
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.299 Thu May 3 18:52:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon May 7 16:27:48 2007
@@ -34,7 +34,9 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
+#include "llvm/Target/TargetData.h"
#include "llvm/Target/TargetLowering.h"
+#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
@@ -2569,17 +2571,22 @@
return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0));
// fold (conv (load x)) -> (load (conv*)x)
- // FIXME: These xforms need to know that the resultant load doesn't need a
- // higher alignment than the original!
- if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
+ // If the resultant load doesn't need a higher alignment than the original!
+ if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+ TLI.isOperationLegal(ISD::LOAD, VT)) {
LoadSDNode *LN0 = cast(N0);
-SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
- LN0->getSrcValue(), LN0->getSrcValueOffset(),
- LN0->isVolatile(), LN0->getAlignment());
-AddToWorkList(N);
-CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
- Load.getValue(1));
-return Load;
+unsigned Align = TLI.getTargetMachine().getTargetData()->
+ getPrefTypeAlignment(getTypeForValueType(VT));
+unsigned OrigAlign = LN0->getAlignment();
+if (Align <= OrigAlign) {
+ SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(),
+ LN0->getSrcValue(),
LN0->getSrcValueOffset(),
+ LN0->isVolatile(), LN0->getAlignment());
+ AddToWorkList(N);
+ CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load),
+Load.getValue(1));
+ return Load;
+}
}
return SDOperand();
@@ -3414,12 +3421,16 @@
SDOperand Value = ST->getValue();
SDOperand Ptr = ST->getBasePtr();
- // If this is a store of a bit convert, store the input value.
- // FIXME: This needs to know that the resultant store does not need a
- // higher alignment than the original.
- if (0 && Value.getOpcode() == ISD::BIT_CONVERT) {
-return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
-ST->getSrcValueOffset());
+ // If this is a store of a bit convert, store the input value if the
+ // resultant store does not need a higher alignment than the original.
+ if (Value.getOpcode() == ISD::BIT_CONVERT) {
+unsigned Align = ST->getAlignment();
+MVT::ValueType SVT = Value.getOperand(0).getValueType();
+unsigned OrigAlign = TLI.getTargetMachine().getTargetData()->
+ getPrefTypeAlignment(getTypeForValueType(SVT));
+if (Align <= OrigAlign)
+ return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(),
+ ST->getSrcValueOffset());
}
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.298 -> 1.299 --- Log message: Don't create indexed load / store with zero offset! --- Diffs of the changes: (+8 -0) DAGCombiner.cpp |8 1 files changed, 8 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.298 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.299 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.298 Tue May 1 03:53:39 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu May 3 18:52:19 2007 @@ -3110,6 +3110,10 @@ ISD::MemIndexedMode AM = ISD::UNINDEXED; if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) return false; + // Don't create a indexed load / store with zero offset. + if (isa(Offset) && + cast(Offset)->getValue() == 0) +return false; // Try turning it into a pre-indexed load / store except when: // 1) The base is a frame index. @@ -3239,6 +3243,10 @@ std::swap(BasePtr, Offset); if (Ptr != BasePtr) continue; + // Don't create a indexed load / store with zero offset. + if (isa(Offset) && + cast(Offset)->getValue() == 0) +continue; // Try turning it into a post-indexed load / store except when // 1) All uses are load / store ops that use it as base ptr. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> Forgot about chain result; also UNDEF cannot have multiple values.
Nice! Thanks Evan,
-Chris
> ---
> Diffs of the changes: (+12 -12)
>
> DAGCombiner.cpp | 24
> 1 files changed, 12 insertions(+), 12 deletions(-)
>
>
> Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297 llvm/
> lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.298
> --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297 Mon Apr 30
> 19:38:21 2007
> +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 1
> 03:53:39 2007
> @@ -3331,19 +3331,19 @@
>// the updated indexed value in case of indexed loads), change
> uses of the
>// chain value into uses of the chain input (i.e. delete the
> dead load).
>if (!LD->isVolatile()) {
> -bool HasUses = false;
> -SmallVector VTs;
> -for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
> - if (!N->hasNUsesOfValue(0, i)) {
> -HasUses = true;
> -break;
> +if (N->getValueType(1) == MVT::Other) {
> + // Unindexed loads.
> + if (N->hasNUsesOfValue(0, 0))
> +return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType
> (0)), Chain);
> +} else {
> + // Indexed loads.
> + assert(N->getValueType(2) == MVT::Other && "Malformed
> indexed loads?");
> + if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
> +SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType
> (0));
> +SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType
> (1));
> +SDOperand To[] = { Undef0, Undef1, Chain };
> +return CombineTo(N, To, 3);
>}
> - VTs.push_back(N->getValueType(i));
> -}
> -if (!HasUses) {
> - SmallVector Ops;
> - return CombineTo(N, DAG.getNode(ISD::UNDEF, &VTs[0], VTs.size
> (), 0, 0),
> - Chain);
> }
>}
>
>
>
>
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.297 -> 1.298
---
Log message:
Forgot about chain result; also UNDEF cannot have multiple values.
---
Diffs of the changes: (+12 -12)
DAGCombiner.cpp | 24
1 files changed, 12 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.298
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297 Mon Apr 30 19:38:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 1 03:53:39 2007
@@ -3331,19 +3331,19 @@
// the updated indexed value in case of indexed loads), change uses of the
// chain value into uses of the chain input (i.e. delete the dead load).
if (!LD->isVolatile()) {
-bool HasUses = false;
-SmallVector VTs;
-for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- if (!N->hasNUsesOfValue(0, i)) {
-HasUses = true;
-break;
+if (N->getValueType(1) == MVT::Other) {
+ // Unindexed loads.
+ if (N->hasNUsesOfValue(0, 0))
+return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)),
Chain);
+} else {
+ // Indexed loads.
+ assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
+ if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
+SDOperand Undef0 = DAG.getNode(ISD::UNDEF, N->getValueType(0));
+SDOperand Undef1 = DAG.getNode(ISD::UNDEF, N->getValueType(1));
+SDOperand To[] = { Undef0, Undef1, Chain };
+return CombineTo(N, To, 3);
}
- VTs.push_back(N->getValueType(i));
-}
-if (!HasUses) {
- SmallVector Ops;
- return CombineTo(N, DAG.getNode(ISD::UNDEF, &VTs[0], VTs.size(), 0, 0),
- Chain);
}
}
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Doh. Brain cramp.
Evan
On Apr 30, 2007, at 9:39 PM, Chris Lattner wrote:
>> +bool HasUses = false;
>> +SmallVector VTs;
>> +for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
>> + if (!N->hasNUsesOfValue(0, i)) {
>> +HasUses = true;
>> +break;
>> + }
>> + VTs.push_back(N->getValueType(i));
>> +}
>> +if (!HasUses) {
>> + SmallVector Ops;
>> + return CombineTo(N, DAG.getNode(ISD::UNDEF, &VTs[0], VTs.size
>> (), 0, 0),
>> + Chain);
>
> This can never trigger and isn't right if it did.
>
> #1: This should trigger if the chain has uses but the other values do
> not. If the entire node is dead, it will already have been removed.
>
> #2. you can't create an undef with multiple results, you have to
> create multiple undefs :)
>
> I'd suggest just writing this as:
>
>if (N->getValueType(1) == MVT::Other) {
> // single result case.
>} else {
> assert(N->getValueType(2) == MVT::Other);
> // multi result case.
>}
>
> This lets you drop the looping and smallvector.
>
> -Chris
>
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Re: [llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> +bool HasUses = false;
> +SmallVector VTs;
> +for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
> + if (!N->hasNUsesOfValue(0, i)) {
> +HasUses = true;
> +break;
> + }
> + VTs.push_back(N->getValueType(i));
> +}
> +if (!HasUses) {
> + SmallVector Ops;
> + return CombineTo(N, DAG.getNode(ISD::UNDEF, &VTs[0], VTs.size
> (), 0, 0),
> + Chain);
This can never trigger and isn't right if it did.
#1: This should trigger if the chain has uses but the other values do
not. If the entire node is dead, it will already have been removed.
#2. you can't create an undef with multiple results, you have to
create multiple undefs :)
I'd suggest just writing this as:
if (N->getValueType(1) == MVT::Other) {
// single result case.
} else {
assert(N->getValueType(2) == MVT::Other);
// multi result case.
}
This lets you drop the looping and smallvector.
-Chris
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.296 -> 1.297
---
Log message:
* Only turn a load to UNDEF if all of its outputs have no uses (indexed loads
produce two results.)
* Do not touch volatile loads.
---
Diffs of the changes: (+20 -5)
DAGCombiner.cpp | 25 -
1 files changed, 20 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.296
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.297
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.296 Sun Apr 22 18:15:30 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 30 19:38:21 2007
@@ -3326,11 +3326,26 @@
LoadSDNode *LD = cast(N);
SDOperand Chain = LD->getChain();
SDOperand Ptr = LD->getBasePtr();
-
- // If there are no uses of the loaded value, change uses of the chain value
- // into uses of the chain input (i.e. delete the dead load).
- if (N->hasNUsesOfValue(0, 0))
-return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain);
+
+ // If load is not volatile and there are no uses of the loaded value (and
+ // the updated indexed value in case of indexed loads), change uses of the
+ // chain value into uses of the chain input (i.e. delete the dead load).
+ if (!LD->isVolatile()) {
+bool HasUses = false;
+SmallVector VTs;
+for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
+ if (!N->hasNUsesOfValue(0, i)) {
+HasUses = true;
+break;
+ }
+ VTs.push_back(N->getValueType(i));
+}
+if (!HasUses) {
+ SmallVector Ops;
+ return CombineTo(N, DAG.getNode(ISD::UNDEF, &VTs[0], VTs.size(), 0, 0),
+ Chain);
+}
+ }
// If this load is directly stored, replace the load value with the stored
// value.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.294 -> 1.295
SelectionDAG.cpp updated: 1.399 -> 1.400
SelectionDAGISel.cpp updated: 1.422 -> 1.423
---
Log message:
Revert Christopher Lamb's load/store alignment changes.
---
Diffs of the changes: (+36 -79)
DAGCombiner.cpp | 70 +--
SelectionDAG.cpp | 33
SelectionDAGISel.cpp | 12 +++-
3 files changed, 36 insertions(+), 79 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.294
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.295
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.294 Sat Apr 21 03:16:25 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 21 13:36:27 2007
@@ -1263,9 +1263,7 @@
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
- LN0->isVolatile(),
- LN0->getAlignment());
+ LN0->getSrcValueOffset(), EVT);
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -1282,9 +1280,7 @@
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
- LN0->isVolatile(),
- LN0->getAlignment());
+ LN0->getSrcValueOffset(), EVT);
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -1324,8 +1320,7 @@
AddToWorkList(NewPtr.Val);
SDOperand Load =
DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
- LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
- LN0->isVolatile(), LN0->getAlignment());
+ LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
AddToWorkList(N);
CombineTo(N0.Val, Load, Load.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -2125,8 +2120,7 @@
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
- N0.getValueType(),
- LN0->isVolatile());
+ N0.getValueType());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2142,9 +2136,7 @@
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
- LN0->isVolatile(),
- LN0->getAlignment());
+ LN0->getSrcValueOffset(), EVT);
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2220,9 +2212,7 @@
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
- N0.getValueType(),
- LN0->isVolatile(),
- LN0->getAlignment());
+ N0.getValueType());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2237,9 +2227,7 @@
MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT,
- LN0->isVolatile(),
- L
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.293 -> 1.294
SelectionDAG.cpp updated: 1.398 -> 1.399
SelectionDAGISel.cpp updated: 1.421 -> 1.422
---
Log message:
add support for alignment attributes on load/store instructions
---
Diffs of the changes: (+79 -36)
DAGCombiner.cpp | 70 +--
SelectionDAG.cpp | 33 +++-
SelectionDAGISel.cpp | 12 +---
3 files changed, 79 insertions(+), 36 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.293
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.294
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.293 Tue Apr 17 22:06:49 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Apr 21 03:16:25 2007
@@ -1263,7 +1263,9 @@
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT);
+ LN0->getSrcValueOffset(), EVT,
+ LN0->isVolatile(),
+ LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -1280,7 +1282,9 @@
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT);
+ LN0->getSrcValueOffset(), EVT,
+ LN0->isVolatile(),
+ LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -1320,7 +1324,8 @@
AddToWorkList(NewPtr.Val);
SDOperand Load =
DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr,
- LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
+ LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT,
+ LN0->isVolatile(), LN0->getAlignment());
AddToWorkList(N);
CombineTo(N0.Val, Load, Load.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
@@ -2120,7 +2125,8 @@
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
- N0.getValueType());
+ N0.getValueType(),
+ LN0->isVolatile());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2136,7 +2142,9 @@
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT);
+ LN0->getSrcValueOffset(), EVT,
+ LN0->isVolatile(),
+ LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2212,7 +2220,9 @@
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(),
- N0.getValueType());
+ N0.getValueType(),
+ LN0->isVolatile(),
+ LN0->getAlignment());
CombineTo(N, ExtLoad);
CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
ExtLoad.getValue(1));
@@ -2227,7 +2237,9 @@
MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT);
+ LN0->getSrcValueOffset(), EVT,
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.292 -> 1.293 --- Log message: allow SRL to simplify its operands, as it doesn't demand all bits as input. --- Diffs of the changes: (+7 -1) DAGCombiner.cpp |8 +++- 1 files changed, 7 insertions(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.292 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.293 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.292 Tue Apr 17 22:05:22 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 17 22:06:49 2007 @@ -1728,7 +1728,7 @@ // if (shl x, c) is known to be zero, return 0 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) return DAG.getConstant(0, VT); - if (SimplifyDemandedBits(SDOperand(N, 0))) + if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) return SDOperand(N, 0); // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) if (N1C && N0.getOpcode() == ISD::SHL && @@ -1907,6 +1907,12 @@ return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); } } + + // fold operands of srl based on knowledge that the low bits are not + // demanded. + if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) +return SDOperand(N, 0); + return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.291 -> 1.292
---
Log message:
When replacing a node in SimplifyDemandedBits, if the old node used any
single-use nodes, they will be dead soon. Make sure to remove them before
processing other nodes. This implements CodeGen/X86/shl_elim.ll
---
Diffs of the changes: (+8 -1)
DAGCombiner.cpp |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.291
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.292
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.291 Tue Apr 17 14:03:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 17 22:05:22 2007
@@ -182,6 +182,13 @@
// something else needing this node.
if (TLO.Old.Val->use_empty()) {
removeFromWorkList(TLO.Old.Val);
+
+// If the operands of this node are only used by the node, they will
now
+// be dead. Make sure to visit them first to delete dead nodes early.
+for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i)
+ if (TLO.Old.Val->getOperand(i).Val->hasOneUse())
+AddToWorkList(TLO.Old.Val->getOperand(i).Val);
+
DAG.DeleteNode(TLO.Old.Val);
}
return true;
@@ -1838,6 +1845,7 @@
// if (srl x, c) is known to be zero, return 0
if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >>
(64-OpSizeInBits)))
return DAG.getConstant(0, VT);
+
// fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SRL &&
N0.getOperand(1).getOpcode() == ISD::Constant) {
@@ -1899,7 +1907,6 @@
return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT));
}
}
-
return SDOperand();
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.290 -> 1.291
---
Log message:
SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits
a chance to hack on it. This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }
into:
_baz:
slwi r2, r3, 8
srwi r2, r2, 9
extsh r3, r2
blr
instead of:
_baz:
srwi r2, r4, 24
rlwimi r2, r3, 8, 0, 23
srwi r2, r2, 9
extsh r3, r2
blr
This implements CodeGen/PowerPC/sign_ext_inreg1.ll
---
Diffs of the changes: (+6 -1)
DAGCombiner.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.290
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.291
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.290 Wed Apr 11 11:51:53 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Apr 17 14:03:21 2007
@@ -2429,10 +2429,15 @@
return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
}
- // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
+ // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero.
if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
return DAG.getZeroExtendInReg(N0, EVT);
+ // fold operands of sext_in_reg based on knowledge that the top bits are not
+ // demanded.
+ if (SimplifyDemandedBits(SDOperand(N, 0)))
+return SDOperand(N, 0);
+
// fold (sext_in_reg (load x)) -> (smaller sextload x)
// fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits))
SDOperand NarrowLoad = ReduceLoadWidth(N);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.289 -> 1.290 --- Log message: fix an infinite loop compiling ldecod, notice by JeffC. --- Diffs of the changes: (+1 -1) DAGCombiner.cpp |2 +- 1 files changed, 1 insertion(+), 1 deletion(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.289 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.290 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.289 Wed Apr 11 01:50:51 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 11 11:51:53 2007 @@ -2320,7 +2320,7 @@ SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, VT), DAG.getConstant(0, VT), - cast(N0.getOperand(2))->get()); + cast(N0.getOperand(2))->get(), true); if (SCC.Val) return SCC; } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.288 -> 1.289
---
Log message:
Fix this harder.
---
Diffs of the changes: (+19 -12)
DAGCombiner.cpp | 31 +++
1 files changed, 19 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.288
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.289
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.288 Wed Apr 11 01:43:25 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 11 01:50:51 2007
@@ -266,7 +266,8 @@
SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N);
SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
- SDOperand N3, ISD::CondCode CC);
+ SDOperand N3, ISD::CondCode CC,
+ bool NotExtCompare = false);
SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
ISD::CondCode Cond, bool foldBooleans = true);
SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *,
MVT::ValueType);
@@ -2133,10 +2134,10 @@
// sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
SDOperand SCC =
-SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
- DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
- cast(N0.getOperand(2))->get());
-if (SCC.Val && SCC.Val != N) return SCC;
+ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
+ DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
+ cast(N0.getOperand(2))->get(), true);
+if (SCC.Val) return SCC;
}
return SDOperand();
@@ -2225,8 +2226,8 @@
SDOperand SCC =
SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
DAG.getConstant(1, VT), DAG.getConstant(0, VT),
- cast(N0.getOperand(2))->get());
-if (SCC.Val && SCC.Val != N) return SCC;
+ cast(N0.getOperand(2))->get(), true);
+if (SCC.Val) return SCC;
}
return SDOperand();
@@ -2317,10 +2318,10 @@
// aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
if (N0.getOpcode() == ISD::SETCC) {
SDOperand SCC =
-SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
- DAG.getConstant(1, VT), DAG.getConstant(0, VT),
- cast(N0.getOperand(2))->get());
-if (SCC.Val && SCC.Val != N && SCC.getOpcode() != ISD::ZERO_EXTEND)
+ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
+ DAG.getConstant(1, VT), DAG.getConstant(0, VT),
+ cast(N0.getOperand(2))->get());
+if (SCC.Val)
return SCC;
}
@@ -4047,7 +4048,7 @@
SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
SDOperand N2, SDOperand N3,
-ISD::CondCode CC) {
+ISD::CondCode CC, bool NotExtCompare) {
MVT::ValueType VT = N2.getValueType();
ConstantSDNode *N1C = dyn_cast(N1.Val);
@@ -4123,6 +4124,12 @@
// fold select C, 16, 0 -> shl C, 4
if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
+
+// If the caller doesn't want us to simplify this into a zext of a compare,
+// don't do it.
+if (NotExtCompare && N2C->getValue() == 1)
+ return SDOperand();
+
// Get a SetCC of the condition
// FIXME: Should probably make sure that setcc is legal if we ever have a
// target where it isn't.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.287 -> 1.288 --- Log message: don't create shifts by zero, fix some problems with my previous patch --- Diffs of the changes: (+7 -3) DAGCombiner.cpp | 10 +++--- 1 files changed, 7 insertions(+), 3 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.287 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.288 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.287 Wed Apr 11 00:32:27 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 11 01:43:25 2007 @@ -2136,7 +2136,7 @@ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get()); -if (SCC.Val) return SCC; +if (SCC.Val && SCC.Val != N) return SCC; } return SDOperand(); @@ -2226,7 +2226,7 @@ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get()); -if (SCC.Val) return SCC; +if (SCC.Val && SCC.Val != N) return SCC; } return SDOperand(); @@ -2320,7 +2320,8 @@ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), DAG.getConstant(1, VT), DAG.getConstant(0, VT), cast(N0.getOperand(2))->get()); -if (SCC.Val) return SCC; +if (SCC.Val && SCC.Val != N && SCC.getOpcode() != ISD::ZERO_EXTEND) + return SCC; } return SDOperand(); @@ -4139,6 +4140,9 @@ } AddToWorkList(SCC.Val); AddToWorkList(Temp.Val); + +if (N2C->getValue() == 1) + return Temp; // shl setcc result by log2 n2c return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, DAG.getConstant(Log2_64(N2C->getValue()), ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.286 -> 1.287
---
Log message:
Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often
allows other simplifications. For example, this compiles:
int isnegative(unsigned int X) {
return !(X < 2147483648U);
}
Into this code:
x86:
movl 4(%esp), %eax
shrl $31, %eax
ret
arm:
mov r0, r0, lsr #31
bx lr
thumb:
lsr r0, r0, #31
bx lr
instead of:
x86:
cmpl $0, 4(%esp)
sets %al
movzbl %al, %eax
ret
arm:
mov r3, #0
cmp r0, #0
movlt r3, #1
mov r0, r3
bx lr
thumb:
mov r2, #1
mov r1, #0
cmp r0, #0
blt LBB1_2 @entry
LBB1_1: @entry
cpy r2, r1
LBB1_2: @entry
cpy r0, r2
bx lr
Testcase here: test/CodeGen/Generic/ispositive.ll
---
Diffs of the changes: (+29 -0)
DAGCombiner.cpp | 29 +
1 files changed, 29 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.286
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.287
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.286 Wed Apr 11 00:11:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 11 00:32:27 2007
@@ -2130,6 +2130,15 @@
}
}
+ // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc
+ if (N0.getOpcode() == ISD::SETCC) {
+SDOperand SCC =
+SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
+ DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT),
+ cast(N0.getOperand(2))->get());
+if (SCC.Val) return SCC;
+ }
+
return SDOperand();
}
@@ -2210,6 +2219,16 @@
ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
+
+ // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
+ if (N0.getOpcode() == ISD::SETCC) {
+SDOperand SCC =
+ SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
+ DAG.getConstant(1, VT), DAG.getConstant(0, VT),
+ cast(N0.getOperand(2))->get());
+if (SCC.Val) return SCC;
+ }
+
return SDOperand();
}
@@ -2294,6 +2313,16 @@
ExtLoad.getValue(1));
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
+
+ // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc
+ if (N0.getOpcode() == ISD::SETCC) {
+SDOperand SCC =
+SimplifySelectCC(N0.getOperand(0), N0.getOperand(1),
+ DAG.getConstant(1, VT), DAG.getConstant(0, VT),
+ cast(N0.getOperand(2))->get());
+if (SCC.Val) return SCC;
+ }
+
return SDOperand();
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.285 -> 1.286
---
Log message:
Codegen integer abs more efficiently using the trick from the PPC CWG. This
improves codegen on many architectures. Tests committed as CodeGen/*/iabs.ll
X86 Old:X86 New:
_test: _test:
movl 4(%esp), %ecx movl 4(%esp), %eax
movl %ecx, %eax movl %eax, %ecx
negl %eax sarl $31, %ecx
testl %ecx, %ecxaddl %ecx, %eax
cmovns %ecx, %eax xorl %ecx, %eax
ret ret
PPC Old:PPC New:
_test: _test:
cmpwi cr0, r3, -1 srawi r2, r3, 31
neg r2, r3 add r3, r3, r2
bgt cr0, LBB1_2 ; xor r3, r3, r2
LBB1_1: ; blr
mr r3, r2
LBB1_2: ;
blr
ARM Old:ARM New:
_test: _test:
rsb r3, r0, #0 add r3, r0, r0, asr #31
cmp r0, #0 eor r0, r3, r0, asr #31
movge r3, r0bx lr
mov r0, r3
bx lr
Thumb Old: Thumb New:
_test: _test:
neg r2, r0 asr r2, r0, #31
cmp r0, #0 add r0, r0, r2
bge LBB1_2 eor r0, r2
LBB1_1: @ bx lr
cpy r0, r2
LBB1_2: @
bx lr
Sparc Old: Sparc New:
test: test:
save -96, %o6, %o6 save -96, %o6, %o6
sethi 0, %l0sra %i0, 31, %l0
sub %l0, %i0, %l0 add %i0, %l0, %l1
subcc %i0, -1, %l1 xor %l1, %l0, %i0
bg .BB1_2 restore %g0, %g0, %g0
nop retl
.BB1_1:nop
or %g0, %l0, %i0
.BB1_2:
restore %g0, %g0, %g0
retl
nop
It also helps alpha/ia64 :)
---
Diffs of the changes: (+18 -4)
DAGCombiner.cpp | 22 ++
1 files changed, 18 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.285
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.286
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.285 Mon Apr 2 16:36:32 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Apr 11 00:11:38 2007
@@ -4159,13 +4159,27 @@
// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
- N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
-if (ConstantSDNode *SubC = dyn_cast(N2.getOperand(0))) {
+ N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
+ N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) {
+MVT::ValueType XType = N0.getValueType();
+SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
+ DAG.getConstant(MVT::getSizeInBits(XType)-1,
+ TLI.getShiftAmountTy()));
+SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
+AddToWorkList(Shift.Val);
+AddToWorkList(Add.Val);
+return DAG.getNode(ISD::XOR, XType, Add, Shift);
+ }
+ // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
+ // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
+ if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
+ N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
+if (ConstantSDNode *SubC = dyn_cast(N3.getOperand(0))) {
MVT::ValueType XType = N0.getValueType();
if (SubC->isNullValue() && MVT::isInteger(XType)) {
SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
DAG.getConstant(MVT::getSizeInBits(XType)-1,
-TLI.getShiftAmountTy()));
+ TLI.getShiftAmountTy()));
SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
AddToWorkList(Shift.Val);
AddToWorkList(Add.Val);
@@ -4173,7 +4187,7 @@
}
}
}
-
+
return SDOperand();
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.284 -> 1.285
LegalizeDAG.cpp updated: 1.485 -> 1.486
---
Log message:
1. Insert custom lowering hooks for ISD::ROTR and ISD::ROTL.
2. Help DAGCombiner recognize zero/sign/any-extended versions of ROTR and ROTL
patterns. This was motivated by the X86/rotate.ll testcase, which should now
generate code for other platforms (and soon-to-come platforms.) Rewrote code
slightly to make it easier to read.
---
Diffs of the changes: (+76 -25)
DAGCombiner.cpp | 81
LegalizeDAG.cpp | 20 +++--
2 files changed, 76 insertions(+), 25 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.285
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284 Fri Mar 30 16:38:07 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Apr 2 16:36:32 2007
@@ -1488,23 +1488,24 @@
}
unsigned OpSizeInBits = MVT::getSizeInBits(VT);
+ SDOperand LHSShiftArg = LHSShift.getOperand(0);
+ SDOperand LHSShiftAmt = LHSShift.getOperand(1);
+ SDOperand RHSShiftAmt = RHSShift.getOperand(1);
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
// fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2)
- if (LHSShift.getOperand(1).getOpcode() == ISD::Constant &&
- RHSShift.getOperand(1).getOpcode() == ISD::Constant) {
-uint64_t LShVal = cast(LHSShift.getOperand(1))->getValue();
-uint64_t RShVal = cast(RHSShift.getOperand(1))->getValue();
+ if (LHSShiftAmt.getOpcode() == ISD::Constant &&
+ RHSShiftAmt.getOpcode() == ISD::Constant) {
+uint64_t LShVal = cast(LHSShiftAmt)->getValue();
+uint64_t RShVal = cast(RHSShiftAmt)->getValue();
if ((LShVal + RShVal) != OpSizeInBits)
return 0;
SDOperand Rot;
if (HasROTL)
- Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
-LHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt);
else
- Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
-RHSShift.getOperand(1));
+ Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt);
// If there is an AND of either shifted operand, apply it to the result.
if (LHSMask.Val || RHSMask.Val) {
@@ -1532,33 +1533,69 @@
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y)
// fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y))
- if (RHSShift.getOperand(1).getOpcode() == ISD::SUB &&
- LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) {
+ if (RHSShiftAmt.getOpcode() == ISD::SUB &&
+ LHSShiftAmt == RHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_cast(RHSShift.getOperand(1).getOperand(0))) {
+ dyn_cast(RHSShiftAmt.getOperand(0))) {
if (SUBC->getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
}
}
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y)
// fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y))
- if (LHSShift.getOperand(1).getOpcode() == ISD::SUB &&
- RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) {
+ if (LHSShiftAmt.getOpcode() == ISD::SUB &&
+ RHSShiftAmt == LHSShiftAmt.getOperand(1)) {
if (ConstantSDNode *SUBC =
- dyn_cast(LHSShift.getOperand(1).getOperand(0))) {
+ dyn_cast(LHSShiftAmt.getOperand(0))) {
if (SUBC->getValue() == OpSizeInBits)
if (HasROTL)
- return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0),
- LHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val;
else
- return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0),
- RHSShift.getOperand(1)).Val;
+ return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val;
+}
+ }
+
+ // Look for sign/zext/any-extended cases:
+ if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) &&
+ (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND
+ || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) {
+SDOperand LExtOp0 = LHSShiftAmt.getOperand(0);
+SDOperand RExtOp0 = RHSShiftAmt.getOperand(0);
+if (RExtOp0.getOpcode()
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.283 -> 1.284
SelectionDAG.cpp updated: 1.393 -> 1.394
---
Log message:
Fix incorrect combination of different loads. Reenable zext-over-truncate
combination.
---
Diffs of the changes: (+71 -75)
DAGCombiner.cpp |4 -
SelectionDAG.cpp | 142 +++
2 files changed, 71 insertions(+), 75 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.283
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.284
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.283 Thu Mar 29 02:56:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 30 16:38:07 2007
@@ -2110,9 +2110,7 @@
// fold (zext (truncate (load x))) -> (zext (smaller load x))
// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
- // FIXME: Temporarily disable this for big endian machines until llvm-gcc
- // build issue has been resolved.
- if (TLI.isLittleEndian() && N0.getOpcode() == ISD::TRUNCATE) {
+ if (N0.getOpcode() == ISD::TRUNCATE) {
SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
if (NarrowLoad.Val) {
if (NarrowLoad.Val != N0.Val)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.393
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.394
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.393Sun Mar 4
14:40:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Fri Mar 30 16:38:07 2007
@@ -285,78 +285,76 @@
AddNodeIDOperands(ID, N->op_begin(), N->getNumOperands());
// Handle SDNode leafs with special info.
- if (N->getNumOperands() == 0) {
-switch (N->getOpcode()) {
-default: break; // Normal nodes don't need extra info.
-case ISD::TargetConstant:
-case ISD::Constant:
- ID.AddInteger(cast(N)->getValue());
- break;
-case ISD::TargetConstantFP:
-case ISD::ConstantFP:
- ID.AddDouble(cast(N)->getValue());
- break;
-case ISD::TargetGlobalAddress:
-case ISD::GlobalAddress: {
- GlobalAddressSDNode *GA = cast(N);
- ID.AddPointer(GA->getGlobal());
- ID.AddInteger(GA->getOffset());
- break;
-}
-case ISD::BasicBlock:
- ID.AddPointer(cast(N)->getBasicBlock());
- break;
-case ISD::Register:
- ID.AddInteger(cast(N)->getReg());
- break;
-case ISD::SRCVALUE: {
- SrcValueSDNode *SV = cast(N);
- ID.AddPointer(SV->getValue());
- ID.AddInteger(SV->getOffset());
- break;
-}
-case ISD::FrameIndex:
-case ISD::TargetFrameIndex:
- ID.AddInteger(cast(N)->getIndex());
- break;
-case ISD::JumpTable:
-case ISD::TargetJumpTable:
- ID.AddInteger(cast(N)->getIndex());
- break;
-case ISD::ConstantPool:
-case ISD::TargetConstantPool: {
- ConstantPoolSDNode *CP = cast(N);
- ID.AddInteger(CP->getAlignment());
- ID.AddInteger(CP->getOffset());
- if (CP->isMachineConstantPoolEntry())
-CP->getMachineCPVal()->AddSelectionDAGCSEId(ID);
- else
-ID.AddPointer(CP->getConstVal());
- break;
-}
-case ISD::LOAD: {
- LoadSDNode *LD = cast(N);
- ID.AddInteger(LD->getAddressingMode());
- ID.AddInteger(LD->getExtensionType());
- ID.AddInteger(LD->getLoadedVT());
- ID.AddPointer(LD->getSrcValue());
- ID.AddInteger(LD->getSrcValueOffset());
- ID.AddInteger(LD->getAlignment());
- ID.AddInteger(LD->isVolatile());
- break;
-}
-case ISD::STORE: {
- StoreSDNode *ST = cast(N);
- ID.AddInteger(ST->getAddressingMode());
- ID.AddInteger(ST->isTruncatingStore());
- ID.AddInteger(ST->getStoredVT());
- ID.AddPointer(ST->getSrcValue());
- ID.AddInteger(ST->getSrcValueOffset());
- ID.AddInteger(ST->getAlignment());
- ID.AddInteger(ST->isVolatile());
- break;
-}
-}
+ switch (N->getOpcode()) {
+ default: break; // Normal nodes don't need extra info.
+ case ISD::TargetConstant:
+ case ISD::Constant:
+ID.AddInteger(cast(N)->getValue());
+break;
+ case ISD::TargetConstantFP:
+ case ISD::ConstantFP:
+ID.AddDouble(cast(N)->getValue());
+break;
+ case ISD::TargetGlobalAddress:
+ case ISD::GlobalAddress: {
+GlobalAddressSDNode *GA = cast(N);
+ID.AddPointer(GA->getGlobal());
+ID.AddInteger(GA->getOffset());
+break;
+ }
+ case ISD::BasicBlock:
+ID.AddPointer(cast(N)->getBasicBlock());
+break;
+ case ISD::Register:
+ID.AddInteger(cast(N)->getReg());
+break;
+ case ISD::SRCVALUE: {
+SrcValueSDNode *SV = cast(N);
+ID.AddPointer(SV->getValue());
+ID.AddInteger(SV->getOffset());
+break;
+ }
+ case ISD::FrameIndex:
+ case ISD::TargetFrameIndex:
+ID.AddInteger(cast(N)->getIndex());
+break;
+ case ISD::JumpTable:
+ case ISD::TargetJumpTable:
+ID.AddInt
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.282 -> 1.283
---
Log message:
Disable load width reduction xform of variant (zext (truncate load x)) for
big endian targets until llvm-gcc build issue has been resolved.
---
Diffs of the changes: (+3 -1)
DAGCombiner.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.282
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.283
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.282 Mon Mar 26 02:12:51 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 29 02:56:46 2007
@@ -2110,7 +2110,9 @@
// fold (zext (truncate (load x))) -> (zext (smaller load x))
// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
- if (N0.getOpcode() == ISD::TRUNCATE) {
+ // FIXME: Temporarily disable this for big endian machines until llvm-gcc
+ // build issue has been resolved.
+ if (TLI.isLittleEndian() && N0.getOpcode() == ISD::TRUNCATE) {
SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
if (NarrowLoad.Val) {
if (NarrowLoad.Val != N0.Val)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.281 -> 1.282
---
Log message:
SIGN_EXTEND_INREG requires one extra operand, a ValueType node.
---
Diffs of the changes: (+6 -2)
DAGCombiner.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.281
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.282
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.281 Fri Mar 23 19:02:43 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Mar 26 02:12:51 2007
@@ -2327,8 +2327,12 @@
CombineTo(N->getOperand(0).Val, Load);
} else
CombineTo(N0.Val, Load, Load.getValue(1));
-if (ShAmt)
- return DAG.getNode(N->getOpcode(), VT, Load);
+if (ShAmt) {
+ if (Opc == ISD::SIGN_EXTEND_INREG)
+return DAG.getNode(Opc, VT, Load, N->getOperand(1));
+ else
+return DAG.getNode(Opc, VT, Load);
+}
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.280 -> 1.281 --- Log message: Adjust offset to compensate for big endian machines. --- Diffs of the changes: (+5 -7) DAGCombiner.cpp | 12 +--- 1 files changed, 5 insertions(+), 7 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.280 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.281 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.280 Fri Mar 23 17:13:36 2007 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 23 19:02:43 2007 @@ -2292,7 +2292,6 @@ N0 = N0.getOperand(0); if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) return SDOperand(); -ShAmt /= 8; CombineSRL = true; } } @@ -2308,12 +2307,11 @@ "Cannot truncate to larger type!"); LoadSDNode *LN0 = cast(N0); MVT::ValueType PtrType = N0.getOperand(1).getValueType(); -// For big endian targets, we need to add an offset to the pointer to load -// the correct bytes. For little endian systems, we merely need to read -// fewer bytes from the same pointer. -uint64_t PtrOff = ShAmt - ? ShAmt : (TLI.isLittleEndian() ? 0 - : (MVT::getSizeInBits(N0.getValueType()) - EVTBits) / 8); +// For big endian targets, we need to adjust the offset to the pointer to +// load the correct bytes. +if (!TLI.isLittleEndian()) + ShAmt = MVT::getSizeInBits(N0.getValueType()) - ShAmt - EVTBits; +uint64_t PtrOff = ShAmt / 8; SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), DAG.getConstant(PtrOff, PtrType)); AddToWorkList(NewPtr.Val); ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.279 -> 1.280
---
Log message:
Make sure SEXTLOAD of the specific type is supported on the target.
---
Diffs of the changes: (+4 -0)
DAGCombiner.cpp |4
1 files changed, 4 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.279
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.280
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.279 Fri Mar 23 15:55:21 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 23 17:13:36 2007
@@ -2272,9 +2272,13 @@
MVT::ValueType VT = N->getValueType(0);
MVT::ValueType EVT = N->getValueType(0);
+ // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then
+ // extended to VT.
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
EVT = cast(N->getOperand(1))->getVT();
+if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))
+ return SDOperand();
}
unsigned EVTBits = MVT::getSizeInBits(EVT);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.278 -> 1.279
---
Log message:
Also replace uses of SRL if that's also folded during ReduceLoadWidth().
---
Diffs of the changes: (+8 -1)
DAGCombiner.cpp |9 -
1 files changed, 8 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.278
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.279
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.278 Thu Mar 22 21:16:52 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Mar 23 15:55:21 2007
@@ -2279,6 +2279,7 @@
unsigned EVTBits = MVT::getSizeInBits(EVT);
unsigned ShAmt = 0;
+ bool CombineSRL = false;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) {
ShAmt = N01->getValue();
@@ -2288,6 +2289,7 @@
if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
return SDOperand();
ShAmt /= 8;
+CombineSRL = true;
}
}
}
@@ -2317,7 +2319,12 @@
: DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT);
AddToWorkList(N);
-CombineTo(N0.Val, Load, Load.getValue(1));
+if (CombineSRL) {
+ std::vector NowDead;
+ DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), NowDead);
+ CombineTo(N->getOperand(0).Val, Load);
+} else
+ CombineTo(N0.Val, Load, Load.getValue(1));
if (ShAmt)
return DAG.getNode(N->getOpcode(), VT, Load);
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.277 -> 1.278
---
Log message:
A couple of bug fixes for reducing load width xform:
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.
---
Diffs of the changes: (+16 -7)
DAGCombiner.cpp | 23 ---
1 files changed, 16 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.277
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.278
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.277 Wed Mar 21 20:54:19 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Mar 22 21:16:52 2007
@@ -2017,8 +2017,11 @@
// fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
-if (NarrowLoad.Val)
- N0 = NarrowLoad;
+if (NarrowLoad.Val) {
+ if (NarrowLoad.Val != N0.Val)
+CombineTo(N0.Val, NarrowLoad);
+ return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad);
+}
}
// See if the value being truncated is already sign extended. If so, just
@@ -2109,8 +2112,11 @@
// fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
-if (NarrowLoad.Val)
- N0 = NarrowLoad;
+if (NarrowLoad.Val) {
+ if (NarrowLoad.Val != N0.Val)
+CombineTo(N0.Val, NarrowLoad);
+ return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad);
+}
}
// fold (zext (truncate x)) -> (and x, mask)
@@ -2189,8 +2195,11 @@
// fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
if (N0.getOpcode() == ISD::TRUNCATE) {
SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
-if (NarrowLoad.Val)
- N0 = NarrowLoad;
+if (NarrowLoad.Val) {
+ if (NarrowLoad.Val != N0.Val)
+CombineTo(N0.Val, NarrowLoad);
+ return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad);
+}
}
// fold (aext (truncate x))
@@ -2278,7 +2287,7 @@
N0 = N0.getOperand(0);
if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
return SDOperand();
-ShAmt /= EVTBits;
+ShAmt /= 8;
}
}
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.276 -> 1.277
---
Log message:
More opportunities to reduce load size.
---
Diffs of the changes: (+101 -45)
DAGCombiner.cpp | 146 ++--
1 files changed, 101 insertions(+), 45 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.276
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.277
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.276 Wed Mar 21 15:14:05 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 21 20:54:19 2007
@@ -273,6 +273,7 @@
SDOperand BuildSDIV(SDNode *N);
SDOperand BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDOperand LHS, SDOperand RHS);
+SDOperand ReduceLoadWidth(SDNode *N);
/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes,
/// looking for aliasing nodes and adding them to the Aliases vector.
@@ -2012,9 +2013,17 @@
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
+ // fold (sext (truncate (load x))) -> (sext (smaller load x))
+ // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))
+ if (N0.getOpcode() == ISD::TRUNCATE) {
+SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+if (NarrowLoad.Val)
+ N0 = NarrowLoad;
+ }
+
+ // See if the value being truncated is already sign extended. If so, just
+ // eliminate the trunc/sext pair.
if (N0.getOpcode() == ISD::TRUNCATE) {
-// See if the value being truncated is already sign extended. If so, just
-// eliminate the trunc/sext pair.
SDOperand Op = N0.getOperand(0);
unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
@@ -2096,6 +2105,14 @@
if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
+ // fold (zext (truncate (load x))) -> (zext (smaller load x))
+ // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n)))
+ if (N0.getOpcode() == ISD::TRUNCATE) {
+SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+if (NarrowLoad.Val)
+ N0 = NarrowLoad;
+ }
+
// fold (zext (truncate x)) -> (and x, mask)
if (N0.getOpcode() == ISD::TRUNCATE &&
(!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) {
@@ -2168,6 +2185,14 @@
N0.getOpcode() == ISD::SIGN_EXTEND)
return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
+ // fold (aext (truncate (load x))) -> (aext (smaller load x))
+ // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n)))
+ if (N0.getOpcode() == ISD::TRUNCATE) {
+SDOperand NarrowLoad = ReduceLoadWidth(N0.Val);
+if (NarrowLoad.Val)
+ N0 = NarrowLoad;
+ }
+
// fold (aext (truncate x))
if (N0.getOpcode() == ISD::TRUNCATE) {
SDOperand TruncOp = N0.getOperand(0);
@@ -2226,6 +2251,72 @@
return SDOperand();
}
+/// ReduceLoadWidth - If the result of a wider load is shifted to right of N
+/// bits and then truncated to a narrower type and where N is a multiple
+/// of number of bits of the narrower type, transform it to a narrower load
+/// from address + N / num of bits of new type. If the result is to be
+/// extended, also fold the extension to form a extending load.
+SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) {
+ unsigned Opc = N->getOpcode();
+ ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
+ SDOperand N0 = N->getOperand(0);
+ MVT::ValueType VT = N->getValueType(0);
+ MVT::ValueType EVT = N->getValueType(0);
+
+ if (Opc == ISD::SIGN_EXTEND_INREG) {
+ExtType = ISD::SEXTLOAD;
+EVT = cast(N->getOperand(1))->getVT();
+ }
+
+ unsigned EVTBits = MVT::getSizeInBits(EVT);
+ unsigned ShAmt = 0;
+ if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
+if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) {
+ ShAmt = N01->getValue();
+ // Is the shift amount a multiple of size of VT?
+ if ((ShAmt & (EVTBits-1)) == 0) {
+N0 = N0.getOperand(0);
+if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits)
+ return SDOperand();
+ShAmt /= EVTBits;
+ }
+}
+ }
+
+ if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+ // Do not allow folding to i1 here. i1 is implicitly stored in memory in
+ // zero extended form: by shrinking the load, we lose track of the fact
+ // that it is already zero extended.
+ // FIXME: This should be reevaluated.
+ VT != MVT::i1) {
+assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits &&
+ "Cannot truncate to larger type!");
+LoadSDNode *LN0 = cast(N0);
+MVT::ValueType PtrType = N0.getOperand(1).getValueType();
+// For big endian targets, we need to add an offset to the pointer to load
+// the co
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.275 -> 1.276
---
Log message:
fold (truncate (srl (load x), c)) -> (smaller load (x+c/vt bits))
---
Diffs of the changes: (+24 -6)
DAGCombiner.cpp | 30 --
1 files changed, 24 insertions(+), 6 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.275
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.276
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.275 Wed Mar 7 02:07:03 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 21 15:14:05 2007
@@ -2298,6 +2298,7 @@
SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
SDOperand N0 = N->getOperand(0);
MVT::ValueType VT = N->getValueType(0);
+ unsigned VTBits = MVT::getSizeInBits(VT);
// noop truncate
if (N0.getValueType() == N->getValueType(0))
@@ -2322,30 +2323,47 @@
// and the truncate
return N0.getOperand(0);
}
+
// fold (truncate (load x)) -> (smaller load x)
+ // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits))
+ unsigned ShAmt = 0;
+ if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
+if (ConstantSDNode *N01 = dyn_cast(N0.getOperand(1))) {
+ ShAmt = N01->getValue();
+ // Is the shift amount a multiple of size of VT?
+ if ((ShAmt & (VTBits-1)) == 0) {
+N0 = N0.getOperand(0);
+if (MVT::getSizeInBits(N0.getValueType()) <= VTBits)
+ return SDOperand();
+ShAmt /= VTBits;
+ }
+}
+ }
if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
// Do not allow folding to i1 here. i1 is implicitly stored in memory in
// zero extended form: by shrinking the load, we lose track of the fact
// that it is already zero extended.
// FIXME: This should be reevaluated.
VT != MVT::i1) {
-assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
+assert(MVT::getSizeInBits(N0.getValueType()) > VTBits &&
"Cannot truncate to larger type!");
LoadSDNode *LN0 = cast(N0);
MVT::ValueType PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to load
// the correct bytes. For little endian systems, we merely need to read
// fewer bytes from the same pointer.
-uint64_t PtrOff =
- (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
-SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() :
- DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
- DAG.getConstant(PtrOff, PtrType));
+uint64_t PtrOff = ShAmt
+ ? ShAmt : (TLI.isLittleEndian() ? 0
+ : (MVT::getSizeInBits(N0.getValueType()) - VTBits) / 8);
+SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(),
+ DAG.getConstant(PtrOff, PtrType));
AddToWorkList(NewPtr.Val);
SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset());
AddToWorkList(N);
CombineTo(N0.Val, Load, Load.getValue(1));
+if (ShAmt)
+ return DAG.getNode(ISD::TRUNCATE, VT, Load);
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
return SDOperand();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.274 -> 1.275
---
Log message:
Avoid combining indexed load further.
---
Diffs of the changes: (+14 -8)
DAGCombiner.cpp | 22 ++
1 files changed, 14 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.274
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.275
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.274 Sun Mar 4 14:40:38 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Mar 7 02:07:03 2007
@@ -1245,7 +1245,7 @@
SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// fold (zext_inreg (extload x)) -> (zextload x)
- if (ISD::isEXTLoad(N0.Val)) {
+ if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
@@ -1261,7 +1261,8 @@
}
}
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
- if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
+ if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+ N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into
@@ -1282,6 +1283,7 @@
if (N1C && N0.getOpcode() == ISD::LOAD) {
LoadSDNode *LN0 = cast(N0);
if (LN0->getExtensionType() != ISD::SEXTLOAD &&
+LN0->getAddressingMode() == ISD::UNINDEXED &&
N0.hasOneUse()) {
MVT::ValueType EVT, LoadedVT;
if (N1C->getValue() == 255)
@@ -2064,7 +2066,8 @@
// fold (sext (sextload x)) -> (sext (truncate (sextload x)))
// fold (sext ( extload x)) -> (sext (truncate (sextload x)))
- if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
+ if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
+ ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
@@ -2135,7 +2138,8 @@
// fold (zext (zextload x)) -> (zext (truncate (zextload x)))
// fold (zext ( extload x)) -> (zext (truncate (zextload x)))
- if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
+ if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) &&
+ ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
@@ -2205,7 +2209,8 @@
// fold (aext (zextload x)) -> (aext (truncate (zextload x)))
// fold (aext (sextload x)) -> (aext (truncate (sextload x)))
// fold (aext ( extload x)) -> (aext (truncate (extload x)))
- if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
+ if (N0.getOpcode() == ISD::LOAD &&
+ !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
@@ -2263,6 +2268,7 @@
// fold (sext_inreg (extload x)) -> (sextload x)
if (ISD::isEXTLoad(N0.Val) &&
+ ISD::isUNINDEXEDLoad(N0.Val) &&
EVT == cast(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast(N0);
@@ -2274,7 +2280,8 @@
return SDOperand(N, 0); // Return N so it doesn't get rechecked!
}
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
- if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
+ if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) &&
+ N0.hasOneUse() &&
EVT == cast(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast(N0);
@@ -2868,8 +2875,7 @@
if (LD->getAddressingMode() != ISD::UNINDEXED)
return false;
VT = LD->getLoadedVT();
-if (LD->getAddressingMode() != ISD::UNINDEXED &&
-!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
+if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
return false;
Ptr = LD->getBasePtr();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.273 -> 1.274
SelectionDAG.cpp updated: 1.392 -> 1.393
---
Log message:
fold away addc nodes when we know there cannot be a carry-out.
---
Diffs of the changes: (+28 -8)
DAGCombiner.cpp | 35 +++
SelectionDAG.cpp |1 +
2 files changed, 28 insertions(+), 8 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.273
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.274
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.273 Sun Mar 4 14:08:45 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Mar 4 14:40:38 2007
@@ -754,7 +754,7 @@
// If the flag result is dead, turn this into an ADD.
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
- SDOperand(N, 1));
+ DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
// canonicalize constant to RHS.
if (N0C && !N1C) {
@@ -762,9 +762,25 @@
return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
}
- // fold (add x, 0) -> x + no carry out
- //if (N1C && N1C->isNullValue())
- // return N0;
+ // fold (addc x, 0) -> x + no carry out
+ if (N1C && N1C->isNullValue())
+return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
+
+ // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
+ uint64_t LHSZero, LHSOne;
+ uint64_t RHSZero, RHSOne;
+ uint64_t Mask = MVT::getIntVTBitMask(VT);
+ TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne);
+ if (LHSZero) {
+TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne);
+
+// If all possibly-set bits on the LHS are clear on the RHS, return an OR.
+// If all possibly-set bits on the RHS are clear on the LHS, return an OR.
+if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) ||
+(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
+ return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1),
+ DAG.getNode(ISD::CARRY_FALSE, MVT::Flag));
+ }
return SDOperand();
}
@@ -772,19 +788,22 @@
SDOperand DAGCombiner::visitADDE(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
+ SDOperand CarryIn = N->getOperand(2);
ConstantSDNode *N0C = dyn_cast(N0);
ConstantSDNode *N1C = dyn_cast(N1);
//MVT::ValueType VT = N0.getValueType();
// canonicalize constant to RHS
if (N0C && !N1C) {
-SDOperand Ops[] = { N1, N0, N->getOperand(2) };
+SDOperand Ops[] = { N1, N0, CarryIn };
return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
}
- // fold (add x, 0) -> x
- //if (N1C && N1C->isNullValue())
- // return N0;
+ // fold (adde x, y, false) -> (addc x, y)
+ if (CarryIn.getOpcode() == ISD::CARRY_FALSE) {
+SDOperand Ops[] = { N1, N0 };
+return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
+ }
return SDOperand();
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.392
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.393
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.392Sun Mar 4
14:01:46 2007
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Mar 4 14:40:38 2007
@@ -2774,6 +2774,7 @@
case ISD::VECTOR_SHUFFLE: return "vector_shuffle";
case ISD::VVECTOR_SHUFFLE: return "vvector_shuffle";
case ISD::VBIT_CONVERT:return "vbit_convert";
+ case ISD::CARRY_FALSE: return "carry_false";
case ISD::ADDC:return "addc";
case ISD::ADDE:return "adde";
case ISD::SUBC:return "subc";
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.272 -> 1.273
---
Log message:
generalize
---
Diffs of the changes: (+9 -5)
DAGCombiner.cpp | 14 +-
1 files changed, 9 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.272
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.273
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.272 Sun Mar 4 14:03:15 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Mar 4 14:08:45 2007
@@ -757,8 +757,10 @@
SDOperand(N, 1));
// canonicalize constant to RHS.
- if (N0C && !N1C)
-return DAG.getNode(ISD::ADDC, VT, N1, N0);
+ if (N0C && !N1C) {
+SDOperand Ops[] = { N1, N0 };
+return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2);
+ }
// fold (add x, 0) -> x + no carry out
//if (N1C && N1C->isNullValue())
@@ -772,11 +774,13 @@
SDOperand N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast(N0);
ConstantSDNode *N1C = dyn_cast(N1);
- MVT::ValueType VT = N0.getValueType();
+ //MVT::ValueType VT = N0.getValueType();
// canonicalize constant to RHS
- if (N0C && !N1C)
-return DAG.getNode(ISD::ADDE, VT, N1, N0, N->getOperand(2));
+ if (N0C && !N1C) {
+SDOperand Ops[] = { N1, N0, N->getOperand(2) };
+return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3);
+ }
// fold (add x, 0) -> x
//if (N1C && N1C->isNullValue())
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.271 -> 1.272
---
Log message:
canonicalize constants to the RHS of addc/adde. If nothing uses the carry out
of
addc, turn it into add.
This allows us to compile:
long long test(long long A, unsigned B) {
return (A + ((long long)B << 32)) & 123;
}
into:
_test:
movl $123, %eax
andl 4(%esp), %eax
xorl %edx, %edx
ret
instead of:
_test:
xorl %edx, %edx
movl %edx, %eax
addl 4(%esp), %eax ;; add of zero
andl $123, %eax
ret
---
Diffs of the changes: (+47 -0)
DAGCombiner.cpp | 47 +++
1 files changed, 47 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.271
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.272
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.271 Sun Feb 25 21:13:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Mar 4 14:03:15 2007
@@ -205,6 +205,8 @@
SDOperand visitTokenFactor(SDNode *N);
SDOperand visitADD(SDNode *N);
SDOperand visitSUB(SDNode *N);
+SDOperand visitADDC(SDNode *N);
+SDOperand visitADDE(SDNode *N);
SDOperand visitMUL(SDNode *N);
SDOperand visitSDIV(SDNode *N);
SDOperand visitUDIV(SDNode *N);
@@ -502,6 +504,8 @@
case ISD::TokenFactor:return visitTokenFactor(N);
case ISD::ADD:return visitADD(N);
case ISD::SUB:return visitSUB(N);
+ case ISD::ADDC: return visitADDC(N);
+ case ISD::ADDE: return visitADDE(N);
case ISD::MUL:return visitMUL(N);
case ISD::SDIV: return visitSDIV(N);
case ISD::UDIV: return visitUDIV(N);
@@ -740,6 +744,49 @@
return SDOperand();
}
+SDOperand DAGCombiner::visitADDC(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ SDOperand N1 = N->getOperand(1);
+ ConstantSDNode *N0C = dyn_cast(N0);
+ ConstantSDNode *N1C = dyn_cast(N1);
+ MVT::ValueType VT = N0.getValueType();
+
+ // If the flag result is dead, turn this into an ADD.
+ if (N->hasNUsesOfValue(0, 1))
+return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0),
+ SDOperand(N, 1));
+
+ // canonicalize constant to RHS.
+ if (N0C && !N1C)
+return DAG.getNode(ISD::ADDC, VT, N1, N0);
+
+ // fold (add x, 0) -> x + no carry out
+ //if (N1C && N1C->isNullValue())
+ // return N0;
+
+ return SDOperand();
+}
+
+SDOperand DAGCombiner::visitADDE(SDNode *N) {
+ SDOperand N0 = N->getOperand(0);
+ SDOperand N1 = N->getOperand(1);
+ ConstantSDNode *N0C = dyn_cast(N0);
+ ConstantSDNode *N1C = dyn_cast(N1);
+ MVT::ValueType VT = N0.getValueType();
+
+ // canonicalize constant to RHS
+ if (N0C && !N1C)
+return DAG.getNode(ISD::ADDE, VT, N1, N0, N->getOperand(2));
+
+ // fold (add x, 0) -> x
+ //if (N1C && N1C->isNullValue())
+ // return N0;
+
+ return SDOperand();
+}
+
+
+
SDOperand DAGCombiner::visitSUB(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.270 -> 1.271
---
Log message:
Fold (sext (truncate x)) more aggressively, by avoiding creation of a
sextinreg if not needed. This is useful in two cases: before legalize,
it avoids creating a sextinreg that will be trivially removed. After legalize
if the target doesn't support sextinreg, the trunc/sext would not have been
removed before.
---
Diffs of the changes: (+34 -10)
DAGCombiner.cpp | 44 ++--
1 files changed, 34 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.270
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.271
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.270 Thu Feb 8 16:13:59 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Feb 25 21:13:59 2007
@@ -1940,18 +1940,42 @@
if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
- // fold (sext (truncate x)) -> (sextinreg x).
- if (N0.getOpcode() == ISD::TRUNCATE &&
- (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
- N0.getValueType( {
+ if (N0.getOpcode() == ISD::TRUNCATE) {
+// See if the value being truncated is already sign extended. If so, just
+// eliminate the trunc/sext pair.
SDOperand Op = N0.getOperand(0);
-if (Op.getValueType() < VT) {
- Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
-} else if (Op.getValueType() > VT) {
- Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
+unsigned OpBits = MVT::getSizeInBits(Op.getValueType());
+unsigned MidBits = MVT::getSizeInBits(N0.getValueType());
+unsigned DestBits = MVT::getSizeInBits(VT);
+unsigned NumSignBits = TLI.ComputeNumSignBits(Op);
+
+if (OpBits == DestBits) {
+ // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign
+ // bits, it is already ready.
+ if (NumSignBits > DestBits-MidBits)
+return Op;
+} else if (OpBits < DestBits) {
+ // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign
+ // bits, just sext from i32.
+ if (NumSignBits > OpBits-MidBits)
+return DAG.getNode(ISD::SIGN_EXTEND, VT, Op);
+} else {
+ // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign
+ // bits, just truncate to i32.
+ if (NumSignBits > OpBits-MidBits)
+return DAG.getNode(ISD::TRUNCATE, VT, Op);
+}
+
+// fold (sext (truncate x)) -> (sextinreg x).
+if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG,
+ N0.getValueType())) {
+ if (Op.getValueType() < VT)
+Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op);
+ else if (Op.getValueType() > VT)
+Op = DAG.getNode(ISD::TRUNCATE, VT, Op);
+ return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
+ DAG.getValueType(N0.getValueType()));
}
-return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op,
- DAG.getValueType(N0.getValueType()));
}
// fold (sext (load x)) -> (sext (truncate (sextload x)))
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp TargetLowering.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.269 -> 1.270
TargetLowering.cpp updated: 1.88 -> 1.89
---
Log message:
Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
---
Diffs of the changes: (+426 -399)
DAGCombiner.cpp| 404 --
TargetLowering.cpp | 421 +
2 files changed, 426 insertions(+), 399 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.269
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.270
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.269 Sat Jan 20 04:10:26 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Feb 8 16:13:59 2007
@@ -423,7 +423,7 @@
/// DagCombineInfo - Expose the DAG combiner to the target combiner impls.
TargetLowering::DAGCombinerInfo
-DagCombineInfo(DAG, !RunningAfterLegalize, this);
+DagCombineInfo(DAG, !RunningAfterLegalize, false, this);
// while the worklist isn't empty, inspect the node on the end of it and
// try and combine it.
@@ -3944,407 +3944,13 @@
return SDOperand();
}
+/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
SDOperand N1, ISD::CondCode Cond,
bool foldBooleans) {
- // These setcc operations always fold.
- switch (Cond) {
- default: break;
- case ISD::SETFALSE:
- case ISD::SETFALSE2: return DAG.getConstant(0, VT);
- case ISD::SETTRUE:
- case ISD::SETTRUE2: return DAG.getConstant(1, VT);
- }
-
- if (ConstantSDNode *N1C = dyn_cast(N1.Val)) {
-uint64_t C1 = N1C->getValue();
-if (isa(N0.Val)) {
- return DAG.FoldSetCC(VT, N0, N1, Cond);
-} else {
- // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
- // equality comparison, then we're just comparing whether X itself is
- // zero.
- if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
- N0.getOperand(0).getOpcode() == ISD::CTLZ &&
- N0.getOperand(1).getOpcode() == ISD::Constant) {
-unsigned ShAmt = cast(N0.getOperand(1))->getValue();
-if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
-ShAmt == Log2_32(MVT::getSizeInBits(N0.getValueType( {
- if ((C1 == 0) == (Cond == ISD::SETEQ)) {
-// (srl (ctlz x), 5) == 0 -> X != 0
-// (srl (ctlz x), 5) != 1 -> X != 0
-Cond = ISD::SETNE;
- } else {
-// (srl (ctlz x), 5) != 0 -> X == 0
-// (srl (ctlz x), 5) == 1 -> X == 0
-Cond = ISD::SETEQ;
- }
- SDOperand Zero = DAG.getConstant(0, N0.getValueType());
- return DAG.getSetCC(VT, N0.getOperand(0).getOperand(0),
- Zero, Cond);
-}
- }
-
- // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
- if (N0.getOpcode() == ISD::ZERO_EXTEND) {
-unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
-
-// If the comparison constant has bits in the upper part, the
-// zero-extended value could never match.
-if (C1 & (~0ULL << InSize)) {
- unsigned VSize = MVT::getSizeInBits(N0.getValueType());
- switch (Cond) {
- case ISD::SETUGT:
- case ISD::SETUGE:
- case ISD::SETEQ: return DAG.getConstant(0, VT);
- case ISD::SETULT:
- case ISD::SETULE:
- case ISD::SETNE: return DAG.getConstant(1, VT);
- case ISD::SETGT:
- case ISD::SETGE:
-// True if the sign bit of C1 is set.
-return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
- case ISD::SETLT:
- case ISD::SETLE:
-// True if the sign bit of C1 isn't set.
-return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
- default:
-break;
- }
-}
-
-// Otherwise, we can perform the comparison with the low bits.
-switch (Cond) {
-case ISD::SETEQ:
-case ISD::SETNE:
-case ISD::SETUGT:
-case ISD::SETUGE:
-case ISD::SETULT:
-case ISD::SETULE:
- return DAG.getSetCC(VT, N0.getOperand(0),
- DAG.getConstant(C1, N0.getOperand(0).getValueType()),
- Cond);
-default:
- break; // todo, be more careful with signed comparisons
-}
- } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
-MVT::ValueType ExtSrcTy = cast(N0.getOperand(1))->getVT();
-unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
-MVT::ValueType ExtDstTy = N0.getValueType();
-unsigned ExtDstTyBits = M
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.268 -> 1.269
---
Log message:
Fix for PR1108: http://llvm.org/PR1108 : type of insert_vector_elt index
operand is PtrVT, not MVT::i32.
---
Diffs of the changes: (+4 -3)
DAGCombiner.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.268
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.269
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.268 Fri Jan 19 11:51:44 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Jan 20 04:10:26 2007
@@ -3251,7 +3251,7 @@
SmallVector BuildVecIndices;
for (unsigned i = 0; i != NumInScalars; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) {
-BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy()));
continue;
}
@@ -3265,12 +3265,13 @@
// Otherwise, use InIdx + VecSize
unsigned Idx = cast(Extract.getOperand(1))->getValue();
- BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, MVT::i32));
+ BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars,
+TLI.getPointerTy()));
}
// Add count and size info.
BuildVecIndices.push_back(NumElts);
-BuildVecIndices.push_back(DAG.getValueType(MVT::i32));
+BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy()));
// Return the new VVECTOR_SHUFFLE node.
SDOperand Ops[5];
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.267 -> 1.268
---
Log message:
Remove this xform:
(shl (add x, c1), c2) -> (add (shl x, c2), c1< (add (add (shl x, c2), c1<(N01);
+ if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() &&
+ isa(N00.getOperand(1))) {
+N0 = DAG.getNode(ISD::ADD, VT,
+ DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01),
+ DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01));
+return DAG.getNode(ISD::ADD, VT, N0, N1);
+ }
+ return SDOperand();
+}
+
SDOperand DAGCombiner::visitADD(SDNode *N) {
SDOperand N0 = N->getOperand(0);
SDOperand N1 = N->getOperand(1);
@@ -711,6 +727,16 @@
}
}
+ // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1hasOneUse()) {
+SDOperand Result = combineShlAddConstant(N1, N0, DAG);
+if (Result.Val) return Result;
+ }
+
return SDOperand();
}
@@ -1615,13 +1641,6 @@
if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
DAG.getConstant(~0ULL << N1C->getValue(), VT));
- // fold (shl (add x, c1), c2) -> (add (shl x, c2), c1
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.266 -> 1.267
---
Log message:
Fix PR1114: http://llvm.org/PR1114 and
CodeGen/Generic/2007-01-15-LoadSelectCycle.ll by being
careful when folding "c ? load p : load q" that C doesn't reach either load.
If so, folding this into load (c ? p : q) will induce a cycle in the graph.
---
Diffs of the changes: (+41 -25)
DAGCombiner.cpp | 66 ++--
1 files changed, 41 insertions(+), 25 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.266
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.267
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.266 Mon Jan 15 22:55:25 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 15 23:59:59 2007
@@ -3709,36 +3709,52 @@
// the right thing to do, but nothing uses srcvalues now. When they
do,
// turn SrcValue into a list of locations.
SDOperand Addr;
-if (TheSelect->getOpcode() == ISD::SELECT)
- Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
- TheSelect->getOperand(0), LLD->getBasePtr(),
- RLD->getBasePtr());
-else
- Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(),
+if (TheSelect->getOpcode() == ISD::SELECT) {
+ // Check that the condition doesn't reach either load. If so,
folding
+ // this will induce a cycle into the DAG.
+ if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
+ !RLD->isPredecessor(TheSelect->getOperand(0).Val)) {
+Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(),
+ TheSelect->getOperand(0), LLD->getBasePtr(),
+ RLD->getBasePtr());
+ }
+} else {
+ // Check that the condition doesn't reach either load. If so,
folding
+ // this will induce a cycle into the DAG.
+ if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) &&
+ !RLD->isPredecessor(TheSelect->getOperand(0).Val) &&
+ !LLD->isPredecessor(TheSelect->getOperand(1).Val) &&
+ !RLD->isPredecessor(TheSelect->getOperand(1).Val)) {
+Addr = DAG.getNode(ISD::SELECT_CC,
LLD->getBasePtr().getValueType(),
TheSelect->getOperand(0),
TheSelect->getOperand(1),
LLD->getBasePtr(), RLD->getBasePtr(),
TheSelect->getOperand(4));
-
-SDOperand Load;
-if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
- Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
- Addr,LLD->getSrcValue(),
LLD->getSrcValueOffset());
-else {
- Load = DAG.getExtLoad(LLD->getExtensionType(),
-TheSelect->getValueType(0),
-LLD->getChain(), Addr, LLD->getSrcValue(),
-LLD->getSrcValueOffset(),
-LLD->getLoadedVT());
+ }
+}
+
+if (Addr.Val) {
+ SDOperand Load;
+ if (LLD->getExtensionType() == ISD::NON_EXTLOAD)
+Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(),
+ Addr,LLD->getSrcValue(),
+ LLD->getSrcValueOffset());
+ else {
+Load = DAG.getExtLoad(LLD->getExtensionType(),
+ TheSelect->getValueType(0),
+ LLD->getChain(), Addr, LLD->getSrcValue(),
+ LLD->getSrcValueOffset(),
+ LLD->getLoadedVT());
+ }
+ // Users of the select now use the result of the load.
+ CombineTo(TheSelect, Load);
+
+ // Users of the old loads now use the new load's chain. We know the
+ // old-load value is dead now.
+ CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
+ CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
+ return true;
}
-// Users of the select now use the result of the load.
-CombineTo(TheSelect, Load);
-
-// Users of the old loads now use the new load's chain. We know the
-// old-load value is dead now.
-CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1));
-CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1));
-return true;
}
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.265 -> 1.266
---
Log message:
add options to view the dags before the first or second pass of dag combine.
---
Diffs of the changes: (+18 -0)
DAGCombiner.cpp | 18 ++
1 files changed, 18 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.265
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.266
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.265 Mon Jan 8 17:04:05 2007
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 15 22:55:25 2007
@@ -46,6 +46,20 @@
STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
namespace {
+#ifndef NDEBUG
+ static cl::opt
+ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
+cl::desc("Pop up a window to show dags before the first "
+ "dag combine pass"));
+ static cl::opt
+ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
+cl::desc("Pop up a window to show dags before the second "
+ "dag combine pass"));
+#else
+ static const bool ViewDAGCombine1 = false;
+ static const bool ViewDAGCombine2 = false;
+#endif
+
static cl::opt
CombinerAA("combiner-alias-analysis", cl::Hidden,
cl::desc("Turn on alias analysis during testing"));
@@ -4512,6 +4526,10 @@
// SelectionDAG::Combine - This is the entry point for the file.
//
void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) {
+ if (!RunningAfterLegalize && ViewDAGCombine1)
+viewGraph();
+ if (RunningAfterLegalize && ViewDAGCombine2)
+viewGraph();
/// run - This is the main entry point to this class.
///
DAGCombiner(*this, AA).Run(RunningAfterLegalize);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.264 -> 1.265 --- Log message: Implement some trivial FP foldings when -enable-unsafe-fp-math is specified. This implements CodeGen/PowerPC/unsafe-math.ll --- Diffs of the changes: (+15 -0) DAGCombiner.cpp | 15 +++ 1 files changed, 15 insertions(+) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.264 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.265 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.264 Tue Dec 19 16:41:21 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 8 17:04:05 2007 @@ -35,6 +35,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetLowering.h" +#include "llvm/Target/TargetOptions.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/CommandLine.h" #include @@ -2401,6 +2402,13 @@ // fold ((-A) + B) -> B-A if (N0.getOpcode() == ISD::FNEG) return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); + + // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) + if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && + N0.Val->hasOneUse() && isa(N0.getOperand(1))) +return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), + DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); + return SDOperand(); } @@ -2436,6 +2444,13 @@ // fold (fmul X, 2.0) -> (fadd X, X) if (N1CFP && N1CFP->isExactlyValue(+2.0)) return DAG.getNode(ISD::FADD, VT, N0, N0); + + // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) + if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && + N0.Val->hasOneUse() && isa(N0.getOperand(1))) +return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), + DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); + return SDOperand(); } ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.263 -> 1.264
ScheduleDAGList.cpp updated: 1.70 -> 1.71
---
Log message:
Eliminate static ctors from Statistics
---
Diffs of the changes: (+6 -12)
DAGCombiner.cpp | 12
ScheduleDAGList.cpp |6 ++
2 files changed, 6 insertions(+), 12 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.263
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.264
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.263 Sat Dec 16 00:25:23 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Dec 19 16:41:21 2006
@@ -40,15 +40,11 @@
#include
using namespace llvm;
+STATISTIC(NodesCombined , "Number of dag nodes combined");
+STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created");
+STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created");
+
namespace {
- static Statistic NodesCombined ("dagcombiner",
- "Number of dag nodes combined");
-
- static Statistic PreIndexedNodes ("pre_indexed_ops",
- "Number of pre-indexed nodes created");
- static Statistic PostIndexedNodes ("post_indexed_ops",
- "Number of post-indexed nodes created");
-
static cl::opt
CombinerAA("combiner-alias-analysis", cl::Hidden,
cl::desc("Turn on alias analysis during testing"));
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.70
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.71
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.70 Thu Dec 7
14:04:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Tue Dec 19 16:41:21 2006
@@ -34,10 +34,8 @@
#include
using namespace llvm;
-namespace {
- static Statistic NumNoops ("scheduler", "Number of noops inserted");
- static Statistic NumStalls("scheduler", "Number of pipeline stalls");
-}
+STATISTIC(NumNoops , "Number of noops inserted");
+STATISTIC(NumStalls, "Number of pipeline stalls");
static RegisterScheduler
tdListDAGScheduler("list-td", " Top-down list scheduler",
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.262 -> 1.263
---
Log message:
Cannot combine an indexed load / store any further.
---
Diffs of the changes: (+10 -1)
DAGCombiner.cpp | 11 ++-
1 files changed, 10 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.262
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.263
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.262 Fri Dec 15 15:38:30 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sat Dec 16 00:25:23 2006
@@ -2727,12 +2727,17 @@
SDOperand Ptr;
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast(N)) {
+if (LD->getAddressingMode() != ISD::UNINDEXED)
+ return false;
VT = LD->getLoadedVT();
-if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
+if (LD->getAddressingMode() != ISD::UNINDEXED &&
+!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
return false;
Ptr = LD->getBasePtr();
} else if (StoreSDNode *ST = dyn_cast(N)) {
+if (ST->getAddressingMode() != ISD::UNINDEXED)
+ return false;
VT = ST->getStoredVT();
if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
!TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
@@ -2846,12 +2851,16 @@
SDOperand Ptr;
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast(N)) {
+if (LD->getAddressingMode() != ISD::UNINDEXED)
+ return false;
VT = LD->getLoadedVT();
if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
!TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
return false;
Ptr = LD->getBasePtr();
} else if (StoreSDNode *ST = dyn_cast(N)) {
+if (ST->getAddressingMode() != ISD::UNINDEXED)
+ return false;
VT = ST->getStoredVT();
if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
!TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.261 -> 1.262
---
Log message:
This code was usurping the sextload expand in teh legalizer. Just make
sure the right conditions are checked.
---
Diffs of the changes: (+9 -7)
DAGCombiner.cpp | 16 +---
1 files changed, 9 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.261
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.262
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.261 Mon Dec 11 22:16:14 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Dec 15 15:38:30 2006
@@ -1943,13 +1943,15 @@
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast(N0);
MVT::ValueType EVT = LN0->getLoadedVT();
-SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
- LN0->getBasePtr(), LN0->getSrcValue(),
- LN0->getSrcValueOffset(), EVT);
-CombineTo(N, ExtLoad);
-CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
- ExtLoad.getValue(1));
-return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) {
+ SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
+ LN0->getBasePtr(), LN0->getSrcValue(),
+ LN0->getSrcValueOffset(), EVT);
+ CombineTo(N, ExtLoad);
+ CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
+ExtLoad.getValue(1));
+ return SDOperand(N, 0); // Return N so it doesn't get rechecked!
+}
}
return SDOperand();
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.260 -> 1.261
---
Log message:
make this code more aggressive about turning store fpimm into store int imm.
This is not sufficient to fix X86/store-fp-constant.ll
---
Diffs of the changes: (+32 -9)
DAGCombiner.cpp | 41 -
1 files changed, 32 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.260
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.261
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.260 Mon Dec 11 11:25:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 11 22:16:14 2006
@@ -3038,15 +3038,38 @@
if (ConstantFPSDNode *CFP = dyn_cast(Value)) {
if (Value.getOpcode() != ISD::TargetConstantFP) {
SDOperand Tmp;
- if (CFP->getValueType(0) == MVT::f32) {
-Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
-return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
-ST->getSrcValueOffset());
- } else if (TLI.isTypeLegal(MVT::i64)) {
-assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
-Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
-return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
-ST->getSrcValueOffset());
+ switch (CFP->getValueType(0)) {
+ default: assert(0 && "Unknown FP type");
+ case MVT::f32:
+if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) {
+ Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
+ return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
+ ST->getSrcValueOffset());
+}
+break;
+ case MVT::f64:
+if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) {
+ Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
+ return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
+ ST->getSrcValueOffset());
+} else if (TLI.isTypeLegal(MVT::i32)) {
+ // Many FP stores are not make apparent until after legalize, e.g.
for
+ // argument passing. Since this is so common, custom legalize the
+ // 64-bit integer store into two 32-bit stores.
+ uint64_t Val = DoubleToBits(CFP->getValue());
+ SDOperand Lo = DAG.getConstant(Val & 0x, MVT::i32);
+ SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32);
+ if (!TLI.isLittleEndian()) std::swap(Lo, Hi);
+
+ SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(),
+ ST->getSrcValueOffset());
+ Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr,
+DAG.getConstant(4, Ptr.getValueType()));
+ SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(),
+ ST->getSrcValueOffset()+4);
+ return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1);
+}
+break;
}
}
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.259 -> 1.260
---
Log message:
Don't convert store double C, Ptr to store long C, Ptr if i64 is not a legal
type.
---
Diffs of the changes: (+12 -9)
DAGCombiner.cpp | 21 -
1 files changed, 12 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.259
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.260
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.259 Sun Dec 10 20:23:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Dec 11 11:25:19 2006
@@ -3035,17 +3035,20 @@
}
// Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr'
- // FIXME: We shouldn't do this for TargetConstantFP's.
if (ConstantFPSDNode *CFP = dyn_cast(Value)) {
-SDOperand Tmp;
-if (CFP->getValueType(0) == MVT::f32) {
- Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
-} else {
- assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
- Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
+if (Value.getOpcode() != ISD::TargetConstantFP) {
+ SDOperand Tmp;
+ if (CFP->getValueType(0) == MVT::f32) {
+Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32);
+return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
+ST->getSrcValueOffset());
+ } else if (TLI.isTypeLegal(MVT::i64)) {
+assert(CFP->getValueType(0) == MVT::f64 && "Unknown FP type!");
+Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64);
+return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
+ST->getSrcValueOffset());
+ }
}
-return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(),
-ST->getSrcValueOffset());
}
if (CombinerAA) {
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.257 -> 1.258
---
Log message:
Fix CodeGen/PowerPC/2006-12-07-SelectCrash.ll on PPC64
---
Diffs of the changes: (+4 -1)
DAGCombiner.cpp |5 -
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.257
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.258
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.257 Thu Dec 7 14:04:42 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Dec 7 16:36:47 2006
@@ -3755,7 +3755,10 @@
// cast from setcc result type to select result type
if (AfterLegalize) {
SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
- Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
+ if (N2.getValueType() < SCC.getValueType())
+Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
+ else
+Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
} else {
SCC = DAG.getSetCC(MVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp LegalizeDAG.cpp ScheduleDAG.cpp ScheduleDAGList.cpp ScheduleDAGRRList.cpp ScheduleDAGSimple.cpp SelectionDAG.cpp SelectionDAGISel.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.256 -> 1.257
LegalizeDAG.cpp updated: 1.421 -> 1.422
ScheduleDAG.cpp updated: 1.111 -> 1.112
ScheduleDAGList.cpp updated: 1.69 -> 1.70
ScheduleDAGRRList.cpp updated: 1.22 -> 1.23
ScheduleDAGSimple.cpp updated: 1.19 -> 1.20
SelectionDAG.cpp updated: 1.375 -> 1.376
SelectionDAGISel.cpp updated: 1.324 -> 1.325
SelectionDAGPrinter.cpp updated: 1.44 -> 1.45
---
Log message:
Removing even more includes.
---
Diffs of the changes: (+144 -155)
DAGCombiner.cpp | 32 -
LegalizeDAG.cpp |9 ++---
ScheduleDAG.cpp | 48 --
ScheduleDAGList.cpp | 17 -
ScheduleDAGRRList.cpp | 31 -
ScheduleDAGSimple.cpp | 30 +++-
SelectionDAG.cpp| 86
SelectionDAGISel.cpp| 25 ++---
SelectionDAGPrinter.cpp | 21 +--
9 files changed, 144 insertions(+), 155 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.256
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.257
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.256 Wed Dec 6 11:46:32 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Dec 7 14:04:42 2006
@@ -38,8 +38,6 @@
#include "llvm/Support/Compiler.h"
#include "llvm/Support/CommandLine.h"
#include
-#include
-#include
using namespace llvm;
namespace {
@@ -101,9 +99,9 @@
bool AddTo = true) {
assert(N->getNumValues() == NumTo && "Broken CombineTo call!");
++NodesCombined;
- DEBUG(std::cerr << "\nReplacing.1 "; N->dump();
-std::cerr << "\nWith: "; To[0].Val->dump(&DAG);
-std::cerr << " and " << NumTo-1 << " other values\n");
+ DOUT << "\nReplacing.1 "; DEBUG(N->dump());
+ DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG));
+ DOUT << " and " << NumTo-1 << " other values\n";
std::vector NowDead;
DAG.ReplaceAllUsesWith(N, To, &NowDead);
@@ -152,9 +150,9 @@
// Replace the old value with the new one.
++NodesCombined;
- DEBUG(std::cerr << "\nReplacing.2 "; TLO.Old.Val->dump();
-std::cerr << "\nWith: "; TLO.New.Val->dump(&DAG);
-std::cerr << '\n');
+ DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump());
+ DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG));
+ DOUT << '\n';
std::vector NowDead;
DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead);
@@ -455,9 +453,9 @@
RV.Val->getOpcode() != ISD::DELETED_NODE &&
"Node was deleted but visit returned new node!");
-DEBUG(std::cerr << "\nReplacing.3 "; N->dump();
- std::cerr << "\nWith: "; RV.Val->dump(&DAG);
- std::cerr << '\n');
+DOUT << "\nReplacing.3 "; DEBUG(N->dump());
+DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG));
+DOUT << '\n';
std::vector NowDead;
if (N->getNumValues() == RV.Val->getNumValues())
DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead);
@@ -2801,9 +2799,9 @@
Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
++PreIndexedNodes;
++NodesCombined;
- DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
-std::cerr << "\nWith: "; Result.Val->dump(&DAG);
-std::cerr << '\n');
+ DOUT << "\nReplacing.4 "; DEBUG(N->dump());
+ DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+ DOUT << '\n';
std::vector NowDead;
if (isLoad) {
DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
@@ -2924,9 +2922,9 @@
: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
++PostIndexedNodes;
++NodesCombined;
-DEBUG(std::cerr << "\nReplacing.5 "; N->dump();
- std::cerr << "\nWith: "; Result.Val->dump(&DAG);
- std::cerr << '\n');
+DOUT << "\nReplacing.5 "; DEBUG(N->dump());
+DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG));
+DOUT << '\n';
std::vector NowDead;
if (isLoad) {
DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.421
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.422
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.421 Wed Nov 29 13:13:47 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Thu Dec 7 14:04:42 2006
@@ -24,7 +24,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Compiler.h"
#include "llvm/ADT/SmallVector.h"
-#include
#include
using namespace llvm;
@@ -556,7 +555,7 @@
}
// Otherwise this is an unhandled builtin node. splat.
#ifndef NDEBUG
-std::cerr << "NODE: "; Node->dump(); std::cerr << "\n";
+cerr << "NODE: "; Node->dump(); cerr << "\n";
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp ScheduleDAGList.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.255 -> 1.256
ScheduleDAGList.cpp updated: 1.68 -> 1.69
---
Log message:
Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.
---
Diffs of the changes: (+5 -5)
DAGCombiner.cpp |6 +++---
ScheduleDAGList.cpp |4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.255
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.256
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.255 Sun Nov 26 22:40:53 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Dec 6 11:46:32 2006
@@ -43,12 +43,12 @@
using namespace llvm;
namespace {
- static Statistic<> NodesCombined ("dagcombiner",
+ static Statistic NodesCombined ("dagcombiner",
"Number of dag nodes combined");
- static Statistic<> PreIndexedNodes ("pre_indexed_ops",
+ static Statistic PreIndexedNodes ("pre_indexed_ops",
"Number of pre-indexed nodes created");
- static Statistic<> PostIndexedNodes ("post_indexed_ops",
+ static Statistic PostIndexedNodes ("post_indexed_ops",
"Number of post-indexed nodes created");
static cl::opt
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.68
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.69
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp:1.68 Sat Nov 4
03:44:31 2006
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGList.cpp Wed Dec 6 11:46:32 2006
@@ -36,8 +36,8 @@
using namespace llvm;
namespace {
- static Statistic<> NumNoops ("scheduler", "Number of noops inserted");
- static Statistic<> NumStalls("scheduler", "Number of pipeline stalls");
+ static Statistic NumNoops ("scheduler", "Number of noops inserted");
+ static Statistic NumStalls("scheduler", "Number of pipeline stalls");
}
static RegisterScheduler
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.254 -> 1.255
---
Log message:
For better or worse, load from i1 is assumed to be zero extended. Do not
form a load from i1 from larger loads that may not be zext'd.
---
Diffs of the changes: (+6 -1)
DAGCombiner.cpp |7 ++-
1 files changed, 6 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.254
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.255
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.254 Mon Nov 20 12:05:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Nov 26 22:40:53 2006
@@ -2192,7 +2192,12 @@
return N0.getOperand(0);
}
// fold (truncate (load x)) -> (smaller load x)
- if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) {
+ if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() &&
+ // Do not allow folding to i1 here. i1 is implicitly stored in memory in
+ // zero extended form: by shrinking the load, we lose track of the fact
+ // that it is already zero extended.
+ // FIXME: This should be reevaluated.
+ VT != MVT::i1) {
assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
"Cannot truncate to larger type!");
LoadSDNode *LN0 = cast(N0);
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.252 -> 1.253
SelectionDAG.cpp updated: 1.373 -> 1.374
---
Log message:
Fix an incorrectly inverted condition.
---
Diffs of the changes: (+1 -2)
DAGCombiner.cpp |2 +-
SelectionDAG.cpp |1 -
2 files changed, 1 insertion(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.252
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.253
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.252 Fri Nov 10 19:00:15 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 15 18:08:20 2006
@@ -2856,7 +2856,7 @@
} else
return false;
- if (!Ptr.Val->hasOneUse())
+ if (Ptr.Val->hasOneUse())
return false;
for (SDNode::use_iterator I = Ptr.Val->use_begin(),
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.373
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.374
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.373Sat Nov 11
14:07:59 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Nov 15 18:08:20 2006
@@ -1481,7 +1481,6 @@
// Perform various simplifications.
ConstantSDNode *N1C = dyn_cast(N1.Val);
ConstantSDNode *N2C = dyn_cast(N2.Val);
- //ConstantSDNode *N3C = dyn_cast(N3.Val);
switch (Opcode) {
case ISD::SETCC: {
// Use FoldSetCC to simplify SETCC's.
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.251 -> 1.252
---
Log message:
disallow preinc of a frameindex. This is not profitable and causes 2-addr
pass to explode. This fixes a bunch of llc-beta failures on ppc last night.
---
Diffs of the changes: (+11 -5)
DAGCombiner.cpp | 16 +++-
1 files changed, 11 insertions(+), 5 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.251
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.252
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.251 Fri Nov 10 18:56:29 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 10 19:00:15 2006
@@ -2750,14 +2750,20 @@
if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
return false;
- // Try turning it into a pre-indexed load / store except when
- // 1) If N is a store and the ptr is either the same as or is a
+ // Try turning it into a pre-indexed load / store except when:
+ // 1) The base is a frame index.
+ // 2) If N is a store and the ptr is either the same as or is a
//predecessor of the value being stored.
- // 2) Another use of base ptr is a predecessor of N. If ptr is folded
+ // 3) Another use of base ptr is a predecessor of N. If ptr is folded
//that would create a cycle.
- // 3) All uses are load / store ops that use it as base ptr.
+ // 4) All uses are load / store ops that use it as base ptr.
- // Checking #1.
+ // Check #1. Preinc'ing a frame index would require copying the stack
pointer
+ // (plus the implicit offset) to a register to preinc anyway.
+ if (isa(BasePtr))
+return false;
+
+ // Check #2.
if (!isLoad) {
SDOperand Val = cast(N)->getValue();
if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.250 -> 1.251
---
Log message:
reduce indentation by using early exits. No functionality change.
---
Diffs of the changes: (+163 -156)
DAGCombiner.cpp | 319
1 files changed, 163 insertions(+), 156 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.250
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.251
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.250 Fri Nov 10 18:39:41 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 10 18:56:29 2006
@@ -2737,83 +2737,89 @@
} else
return false;
- if ((Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) &&
- Ptr.Val->use_size() > 1) {
-SDOperand BasePtr;
-SDOperand Offset;
-ISD::MemIndexedMode AM = ISD::UNINDEXED;
-if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
- // Try turning it into a pre-indexed load / store except when
- // 1) If N is a store and the ptr is either the same as or is a
- //predecessor of the value being stored.
- // 2) Another use of base ptr is a predecessor of N. If ptr is folded
- //that would create a cycle.
- // 3) All uses are load / store ops that use it as base ptr.
-
- // Checking #1.
- if (!isLoad) {
-SDOperand Val = cast(N)->getValue();
-if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
- return false;
- }
-
- // Now check for #2 and #3.
- bool RealUse = false;
- for (SDNode::use_iterator I = Ptr.Val->use_begin(),
- E = Ptr.Val->use_end(); I != E; ++I) {
-SDNode *Use = *I;
-if (Use == N)
- continue;
-if (Use->isPredecessor(N))
- return false;
+ // If the pointer is not an add/sub, or if it doesn't have multiple uses,
bail
+ // out. There is no reason to make this a preinc/predec.
+ if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) ||
+ Ptr.Val->hasOneUse())
+return false;
-if (!((Use->getOpcode() == ISD::LOAD &&
- cast(Use)->getBasePtr() == Ptr) ||
- (Use->getOpcode() == ISD::STORE) &&
- cast(Use)->getBasePtr() == Ptr))
- RealUse = true;
- }
- if (!RealUse)
-return false;
-
- SDOperand Result = isLoad
-? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
-: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
- ++PreIndexedNodes;
- ++NodesCombined;
- DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
-std::cerr << "\nWith: "; Result.Val->dump(&DAG);
-std::cerr << '\n');
- std::vector NowDead;
- if (isLoad) {
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
- NowDead);
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
- NowDead);
- } else {
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
- NowDead);
- }
+ // Ask the target to do addressing mode selection.
+ SDOperand BasePtr;
+ SDOperand Offset;
+ ISD::MemIndexedMode AM = ISD::UNINDEXED;
+ if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG))
+return false;
+
+ // Try turning it into a pre-indexed load / store except when
+ // 1) If N is a store and the ptr is either the same as or is a
+ //predecessor of the value being stored.
+ // 2) Another use of base ptr is a predecessor of N. If ptr is folded
+ //that would create a cycle.
+ // 3) All uses are load / store ops that use it as base ptr.
+
+ // Checking #1.
+ if (!isLoad) {
+SDOperand Val = cast(N)->getValue();
+if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
+ return false;
+ }
- // Nodes can end up on the worklist more than once. Make sure we do
- // not process a node that has been replaced.
- for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
-removeFromWorkList(NowDead[i]);
- // Finally, since the node is now dead, remove it from the graph.
- DAG.DeleteNode(N);
-
- // Replace the uses of Ptr with uses of the updated base value.
- DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
-NowDead);
- removeFromWorkList(Ptr.Val);
- for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
-removeFromWorkList(NowDead[i]);
- DAG.DeleteNode(Ptr.Val);
+ // Now check for #2 and #3.
+ bool RealUse = false;
+ for (SDNode::use_iterator I = Ptr.Val->use_begin(),
+ E = Ptr.Val->use_end(); I != E; ++I) {
+SDNode *Use = *I;
+if (Use == N)
+ continue;
+if (Use->isPredecessor(N))
+ return false;
- return true;
-}
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.249 -> 1.250
---
Log message:
move big chunks of code out-of-line, no functionality change.
---
Diffs of the changes: (+241 -235)
DAGCombiner.cpp | 476
1 files changed, 241 insertions(+), 235 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.249
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.250
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.249 Fri Nov 10 15:37:15 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 10 18:39:41 2006
@@ -178,241 +178,10 @@
return true;
}
-/// CombineToPreIndexedLoadStore - Try turning a load / store and a
-/// pre-indexed load / store when the base pointer is a add or subtract
-/// and it has other uses besides the load / store. After the
-/// transformation, the new indexed load / store has effectively folded
-/// the add / subtract in and all of its other uses are redirected to the
-/// new load / store.
-bool CombineToPreIndexedLoadStore(SDNode *N) {
- if (!AfterLegalize)
-return false;
-
- bool isLoad = true;
- SDOperand Ptr;
- MVT::ValueType VT;
- if (LoadSDNode *LD = dyn_cast(N)) {
-VT = LD->getLoadedVT();
-if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
-!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
- return false;
-Ptr = LD->getBasePtr();
- } else if (StoreSDNode *ST = dyn_cast(N)) {
-VT = ST->getStoredVT();
-if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
-!TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
- return false;
-Ptr = ST->getBasePtr();
-isLoad = false;
- } else
-return false;
-
- if ((Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) &&
- Ptr.Val->use_size() > 1) {
-SDOperand BasePtr;
-SDOperand Offset;
-ISD::MemIndexedMode AM = ISD::UNINDEXED;
-if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
- // Try turning it into a pre-indexed load / store except when
- // 1) If N is a store and the ptr is either the same as or is a
- //predecessor of the value being stored.
- // 2) Another use of base ptr is a predecessor of N. If ptr is folded
- //that would create a cycle.
- // 3) All uses are load / store ops that use it as base ptr.
-
- // Checking #1.
- if (!isLoad) {
-SDOperand Val = cast(N)->getValue();
-if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
- return false;
- }
-
- // Now check for #2 and #3.
- bool RealUse = false;
- for (SDNode::use_iterator I = Ptr.Val->use_begin(),
- E = Ptr.Val->use_end(); I != E; ++I) {
-SDNode *Use = *I;
-if (Use == N)
- continue;
-if (Use->isPredecessor(N))
- return false;
-
-if (!((Use->getOpcode() == ISD::LOAD &&
- cast(Use)->getBasePtr() == Ptr) ||
- (Use->getOpcode() == ISD::STORE) &&
- cast(Use)->getBasePtr() == Ptr))
- RealUse = true;
- }
- if (!RealUse)
-return false;
-
- SDOperand Result = isLoad
-? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
-: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
- ++PreIndexedNodes;
- ++NodesCombined;
- DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
-std::cerr << "\nWith: "; Result.Val->dump(&DAG);
-std::cerr << '\n');
- std::vector NowDead;
- if (isLoad) {
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
- NowDead);
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
- NowDead);
- } else {
-DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
- NowDead);
- }
-
- // Nodes can end up on the worklist more than once. Make sure we do
- // not process a node that has been replaced.
- for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
-removeFromWorkList(NowDead[i]);
- // Finally, since the node is now dead, remove it from the graph.
- DAG.DeleteNode(N);
-
- // Replace the uses of Ptr with uses of the updated base value.
- DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
-NowDead);
- removeFromWorkList(Ptr.Val);
- for (unsigned i = 0, e = NowDead.size(); i
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.248 -> 1.249
---
Log message:
Fix a dag combiner bug exposed by my recent instcombine patch. This fixes
CodeGen/Generic/2006-11-10-DAGCombineMiscompile.ll and PPC gsm/toast
---
Diffs of the changes: (+1 -1)
DAGCombiner.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.248
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.249
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.248 Fri Nov 10 02:28:11 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 10 15:37:15 2006
@@ -1723,7 +1723,7 @@
abort();
}
// fold !(x or y) -> (!x and !y) iff x or y are setcc
- if (N1C && N1C->getValue() == 1 &&
+ if (N1C && N1C->getValue() == 1 && VT == MVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.247 -> 1.248
---
Log message:
When forming a pre-indexed store, make sure ptr isn't the same or is a pred of
value being stored. It would cause a cycle.
---
Diffs of the changes: (+16 -7)
DAGCombiner.cpp | 23 ---
1 files changed, 16 insertions(+), 7 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.247
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.248
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.247 Thu Nov 9 13:10:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 10 02:28:11 2006
@@ -214,11 +214,20 @@
ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
// Try turning it into a pre-indexed load / store except when
- // 1) Another use of base ptr is a predecessor of N. If ptr is folded
+ // 1) If N is a store and the ptr is either the same as or is a
+ //predecessor of the value being stored.
+ // 2) Another use of base ptr is a predecessor of N. If ptr is folded
//that would create a cycle.
- // 2) All uses are load / store ops that use it as base ptr.
+ // 3) All uses are load / store ops that use it as base ptr.
- // Now check for #1 and #2.
+ // Checking #1.
+ if (!isLoad) {
+SDOperand Val = cast(N)->getValue();
+if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val))
+ return false;
+ }
+
+ // Now check for #2 and #3.
bool RealUse = false;
for (SDNode::use_iterator I = Ptr.Val->use_begin(),
E = Ptr.Val->use_end(); I != E; ++I) {
@@ -323,12 +332,12 @@
continue;
// Try turning it into a post-indexed load / store except when
-// 1) Op must be independent of N, i.e. Op is neither a predecessor
+// 1) All uses are load / store ops that use it as base ptr.
+// 2) Op must be independent of N, i.e. Op is neither a predecessor
//nor a successor of N. Otherwise, if Op is folded that would
//create a cycle.
-// 2) All uses are load / store ops that use it as base ptr.
-// Check for #3.
+// Check for #1.
bool TryNext = false;
for (SDNode::use_iterator II = BasePtr.Val->use_begin(),
EE = BasePtr.Val->use_end(); II != EE; ++II) {
@@ -359,7 +368,7 @@
if (TryNext)
continue;
-// Check for #1
+// Check for #2
if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) {
SDOperand Result = isLoad
? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.246 -> 1.247
---
Log message:
Don't attempt expensive pre-/post- indexed dag combine if target does not
support them.
---
Diffs of the changes: (+18 -1)
DAGCombiner.cpp | 19 ++-
1 files changed, 18 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.246
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.247
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.246 Thu Nov 9 11:54:19 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 9 13:10:46 2006
@@ -190,9 +190,18 @@
bool isLoad = true;
SDOperand Ptr;
+ MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast(N)) {
+VT = LD->getLoadedVT();
+if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) &&
+!TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT))
+ return false;
Ptr = LD->getBasePtr();
} else if (StoreSDNode *ST = dyn_cast(N)) {
+VT = ST->getStoredVT();
+if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) &&
+!TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT))
+ return false;
Ptr = ST->getBasePtr();
isLoad = false;
} else
@@ -281,8 +290,16 @@
SDOperand Ptr;
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast(N)) {
+VT = LD->getLoadedVT();
+if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) &&
+!TLI.isIndexedLoadLegal(ISD::POST_DEC, VT))
+ return false;
Ptr = LD->getBasePtr();
} else if (StoreSDNode *ST = dyn_cast(N)) {
+VT = ST->getStoredVT();
+if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) &&
+!TLI.isIndexedStoreLegal(ISD::POST_DEC, VT))
+ return false;
Ptr = ST->getBasePtr();
isLoad = false;
} else
@@ -299,7 +316,7 @@
SDOperand BasePtr;
SDOperand Offset;
ISD::MemIndexedMode AM = ISD::UNINDEXED;
- if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
+ if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG))
{
if (Ptr == Offset)
std::swap(BasePtr, Offset);
if (Ptr != BasePtr)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.245 -> 1.246
SelectionDAG.cpp updated: 1.371 -> 1.372
---
Log message:
Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
---
Diffs of the changes: (+11 -9)
DAGCombiner.cpp |4 ++--
SelectionDAG.cpp | 16 +---
2 files changed, 11 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.245
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.246
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.245 Wed Nov 8 22:29:46 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 9 11:54:19 2006
@@ -202,7 +202,7 @@
Ptr.Val->use_size() > 1) {
SDOperand BasePtr;
SDOperand Offset;
-ISD::MemOpAddrMode AM = ISD::UNINDEXED;
+ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
// Try turning it into a pre-indexed load / store except when
// 1) Another use of base ptr is a predecessor of N. If ptr is folded
@@ -298,7 +298,7 @@
SDOperand BasePtr;
SDOperand Offset;
- ISD::MemOpAddrMode AM = ISD::UNINDEXED;
+ ISD::MemIndexedMode AM = ISD::UNINDEXED;
if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
if (Ptr == Offset)
std::swap(BasePtr, Offset);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.371
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.372
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.371Wed Nov 8
13:16:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu Nov 9 11:54:19 2006
@@ -1619,8 +1619,9 @@
return SDOperand(N, 0);
}
-SDOperand SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
- SDOperand Offset, ISD::MemOpAddrMode
AM){
+SDOperand
+SelectionDAG::getIndexedLoad(SDOperand OrigLoad, SDOperand Base,
+ SDOperand Offset, ISD::MemIndexedMode AM) {
LoadSDNode *LD = cast(OrigLoad);
assert(LD->getOffset().getOpcode() == ISD::UNDEF &&
"Load is already a indexed load!");
@@ -1722,8 +1723,9 @@
return SDOperand(N, 0);
}
-SDOperand SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base,
- SDOperand Offset, ISD::MemOpAddrMode
AM){
+SDOperand
+SelectionDAG::getIndexedStore(SDOperand OrigStore, SDOperand Base,
+ SDOperand Offset, ISD::MemIndexedMode AM) {
StoreSDNode *ST = cast(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
@@ -2841,7 +2843,7 @@
}
}
-const char *SDNode::getAddressingModeName(ISD::MemOpAddrMode AM) {
+const char *SDNode::getIndexedModeName(ISD::MemIndexedMode AM) {
switch (AM) {
default:
return "";
@@ -2943,7 +2945,7 @@
if (doExt)
std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
-const char *AM = getAddressingModeName(LD->getAddressingMode());
+const char *AM = getIndexedModeName(LD->getAddressingMode());
if (AM != "")
std::cerr << " " << AM;
} else if (const StoreSDNode *ST = dyn_cast(this)) {
@@ -2951,7 +2953,7 @@
std::cerr << " getStoredVT()) << ">";
-const char *AM = getAddressingModeName(ST->getAddressingMode());
+const char *AM = getIndexedModeName(ST->getAddressingMode());
if (AM != "")
std::cerr << " " << AM;
}
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.244 -> 1.245
---
Log message:
getPostIndexedAddressParts change: passes in load/store instead of its loaded /
stored VT.
---
Diffs of the changes: (+1 -3)
DAGCombiner.cpp |4 +---
1 files changed, 1 insertion(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.244
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.245
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.244 Wed Nov 8 14:27:27 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 8 22:29:46 2006
@@ -282,10 +282,8 @@
MVT::ValueType VT;
if (LoadSDNode *LD = dyn_cast(N)) {
Ptr = LD->getBasePtr();
-VT = LD->getLoadedVT();
} else if (StoreSDNode *ST = dyn_cast(N)) {
Ptr = ST->getBasePtr();
-VT = ST->getStoredVT();
isLoad = false;
} else
return false;
@@ -301,7 +299,7 @@
SDOperand BasePtr;
SDOperand Offset;
ISD::MemOpAddrMode AM = ISD::UNINDEXED;
- if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG))
{
+ if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM,DAG)) {
if (Ptr == Offset)
std::swap(BasePtr, Offset);
if (Ptr != BasePtr)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.243 -> 1.244
---
Log message:
Match more post-indexed ops.
---
Diffs of the changes: (+6 -2)
DAGCombiner.cpp |8 ++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.243
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.244
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.243 Wed Nov 8 13:16:43 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 8 14:27:27 2006
@@ -301,8 +301,12 @@
SDOperand BasePtr;
SDOperand Offset;
ISD::MemOpAddrMode AM = ISD::UNINDEXED;
- if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG)
&&
- BasePtr == Ptr) {
+ if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG))
{
+if (Ptr == Offset)
+ std::swap(BasePtr, Offset);
+if (Ptr != BasePtr)
+ continue;
+
// Try turning it into a post-indexed load / store except when
// 1) Op must be independent of N, i.e. Op is neither a predecessor
//nor a successor of N. Otherwise, if Op is folded that would
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG: DAGCombiner.cpp updated: 1.242 -> 1.243 SelectionDAG.cpp updated: 1.370 -> 1.371 --- Log message: Remove redundant . --- Diffs of the changes: (+0 -2) DAGCombiner.cpp |1 - SelectionDAG.cpp |1 - 2 files changed, 2 deletions(-) Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.242 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.243 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.242 Wed Nov 8 02:30:28 2006 +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 8 13:16:43 2006 @@ -38,7 +38,6 @@ #include "llvm/Support/Compiler.h" #include "llvm/Support/CommandLine.h" #include -#include #include #include using namespace llvm; Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.370 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.371 --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.370Sun Nov 5 13:31:28 2006 +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed Nov 8 13:16:43 2006 @@ -28,7 +28,6 @@ #include "llvm/ADT/StringExtras.h" #include #include -#include #include using namespace llvm; ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.241 -> 1.242
---
Log message:
- When performing pre-/post- indexed load/store transformation, do not worry
about whether the new base ptr would be live below the load/store. Let two
address pass split it back to non-indexed ops.
- Minor tweaks / fixes.
---
Diffs of the changes: (+30 -91)
DAGCombiner.cpp | 121 +---
1 files changed, 30 insertions(+), 91 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.241
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.242
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.241 Wed Nov 8 00:56:05 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 8 02:30:28 2006
@@ -208,61 +208,26 @@
// Try turning it into a pre-indexed load / store except when
// 1) Another use of base ptr is a predecessor of N. If ptr is folded
//that would create a cycle.
- // 2) All uses are load / store ops that use it as base ptr and
offset
- //is just an addressing mode immediate.
- // 3) If the would-be new base may not to be dead at N.
-
- bool OffIsAMImm = Offset.getOpcode() == ISD::Constant && TLI.
-isLegalAddressImmediate(cast(Offset)->getValue());
-
- // Check for #3.
- for (SDNode::use_iterator I = BasePtr.Val->use_begin(),
- E = BasePtr.Val->use_end(); I != E; ++I) {
+ // 2) All uses are load / store ops that use it as base ptr.
+
+ // Now check for #1 and #2.
+ bool RealUse = false;
+ for (SDNode::use_iterator I = Ptr.Val->use_begin(),
+ E = Ptr.Val->use_end(); I != E; ++I) {
SDNode *Use = *I;
-if (Use == Ptr.Val)
+if (Use == N)
continue;
-if (Use->getOpcode() == ISD::CopyToReg)
+if (Use->isPredecessor(N))
return false;
-if (OffIsAMImm && (Use->getOpcode() == ISD::ADD ||
- Use->getOpcode() == ISD::SUB)) {
- for (SDNode::use_iterator II = Use->use_begin(),
- EE = Use->use_end(); II != EE; ++II) {
-SDNode *UseUse = *II;
-if (UseUse->getOpcode() == ISD::LOAD &&
-cast(UseUse)->getBasePtr().Val == Use)
- return false;
-else if (UseUse->getOpcode() == ISD::STORE &&
- cast(UseUse)->getBasePtr().Val == Use)
- return false;
- }
-}
- }
- // Now check for #1 and #2.
- if (OffIsAMImm) {
-unsigned NumRealUses = 0;
-for (SDNode::use_iterator I = Ptr.Val->use_begin(),
- E = Ptr.Val->use_end(); I != E; ++I) {
- SDNode *Use = *I;
- if (Use == N)
-continue;
- if (Use->isPredecessor(N))
-return false;
-
- if (!OffIsAMImm) {
-NumRealUses++;
- } else if (Use->getOpcode() == ISD::LOAD) {
-if (cast(Use)->getBasePtr().Val != Ptr.Val)
- NumRealUses++;
- } else if (Use->getOpcode() == ISD::STORE) {
-if (cast(Use)->getBasePtr().Val != Ptr.Val)
- NumRealUses++;
- } else
-NumRealUses++;
-}
-if (NumRealUses == 0)
- return false;
+if (!((Use->getOpcode() == ISD::LOAD &&
+ cast(Use)->getBasePtr() == Ptr) ||
+ (Use->getOpcode() == ISD::STORE) &&
+ cast(Use)->getBasePtr() == Ptr))
+ RealUse = true;
}
+ if (!RealUse)
+return false;
SDOperand Result = isLoad
? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
@@ -343,12 +308,7 @@
// 1) Op must be independent of N, i.e. Op is neither a predecessor
//nor a successor of N. Otherwise, if Op is folded that would
//create a cycle.
-// 2) All uses are load / store ops that use it as base ptr and
offset
-//is just an addressing mode immediate.
-// 3) If the would-be new base may not to be dead at N.
-
-bool OffIsAMImm = Offset.getOpcode() == ISD::Constant && TLI.
-
isLegalAddressImmediate(cast(Offset)->getValue());
+// 2) All uses are load / store ops that use it as base ptr.
// Check for #3.
bool TryNext = false;
@@ -357,51 +317,30 @@
SDNode *Use = *II;
if (Use == Ptr.Val)
continue;
- if (Use->getOpcode() == ISD::CopyToReg) {
-TryNext = true;
-break;
-
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.240 -> 1.241
---
Log message:
Fixed a minor bug preventing some pre-indexed load / store transformation.
---
Diffs of the changes: (+3 -3)
DAGCombiner.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.240
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.241
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.240 Tue Nov 7 20:38:55 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Nov 8 00:56:05 2006
@@ -239,8 +239,8 @@
}
// Now check for #1 and #2.
- unsigned NumRealUses = 0;
if (OffIsAMImm) {
+unsigned NumRealUses = 0;
for (SDNode::use_iterator I = Ptr.Val->use_begin(),
E = Ptr.Val->use_end(); I != E; ++I) {
SDNode *Use = *I;
@@ -260,9 +260,9 @@
} else
NumRealUses++;
}
+if (NumRealUses == 0)
+ return false;
}
- if (NumRealUses == 0)
-return false;
SDOperand Result = isLoad
? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.239 -> 1.240
---
Log message:
Fix a obscure post-indexed load / store dag combine bug.
---
Diffs of the changes: (+1 -1)
DAGCombiner.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.239
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.240
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.239 Tue Nov 7 03:03:05 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 7 20:38:55 2006
@@ -338,7 +338,7 @@
SDOperand Offset;
ISD::MemOpAddrMode AM = ISD::UNINDEXED;
if (TLI.getPostIndexedAddressParts(Op, VT, BasePtr, Offset, AM,DAG)
&&
- BasePtr.Val == Ptr.Val) {
+ BasePtr == Ptr) {
// Try turning it into a post-indexed load / store except when
// 1) Op must be independent of N, i.e. Op is neither a predecessor
//nor a successor of N. Otherwise, if Op is folded that would
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.238 -> 1.239
---
Log message:
Add post-indexed load / store transformations.
---
Diffs of the changes: (+199 -50)
DAGCombiner.cpp | 249
1 files changed, 199 insertions(+), 50 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.238
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.239
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.238 Mon Nov 6 02:14:30 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Nov 7 03:03:05 2006
@@ -47,6 +47,11 @@
static Statistic<> NodesCombined ("dagcombiner",
"Number of dag nodes combined");
+ static Statistic<> PreIndexedNodes ("pre_indexed_ops",
+ "Number of pre-indexed nodes created");
+ static Statistic<> PostIndexedNodes ("post_indexed_ops",
+ "Number of post-indexed nodes created");
+
static cl::opt
CombinerAA("combiner-alias-analysis", cl::Hidden,
cl::desc("Turn on alias analysis during testing"));
@@ -174,13 +179,16 @@
return true;
}
-/// CombineToPreIndexedLoadStore - Try turning a load / store into a
-/// pre-indexed load store when the base pointer is a add or subtract
-/// and it has other uses besides the load / store. When the
-/// transformation is done, the new indexed load / store effectively
-/// folded the add / subtract in and all of its other uses are redirected
-/// to the new load / store.
+/// CombineToPreIndexedLoadStore - Try turning a load / store and a
+/// pre-indexed load / store when the base pointer is a add or subtract
+/// and it has other uses besides the load / store. After the
+/// transformation, the new indexed load / store has effectively folded
+/// the add / subtract in and all of its other uses are redirected to the
+/// new load / store.
bool CombineToPreIndexedLoadStore(SDNode *N) {
+ if (!AfterLegalize)
+return false;
+
bool isLoad = true;
SDOperand Ptr;
if (LoadSDNode *LD = dyn_cast(N)) {
@@ -191,8 +199,7 @@
} else
return false;
- if (AfterLegalize &&
- (Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) &&
+ if ((Ptr.getOpcode() == ISD::ADD || Ptr.getOpcode() == ISD::SUB) &&
Ptr.Val->use_size() > 1) {
SDOperand BasePtr;
SDOperand Offset;
@@ -203,57 +210,56 @@
//that would create a cycle.
// 2) All uses are load / store ops that use it as base ptr and
offset
//is just an addressing mode immediate.
- // 3) If the would-be new base may not to be dead at N. FIXME: The
- //proper check is too expensive (in turns of compile time) to
- //check. Just make sure other uses of the new base are not also
- //themselves use of loads / stores.
-
- bool OffIsAMImm = Offset.getOpcode() == ISD::Constant &&
-TLI.isLegalAddressImmediate(
- cast(Offset)->getValue());
+ // 3) If the would-be new base may not to be dead at N.
+
+ bool OffIsAMImm = Offset.getOpcode() == ISD::Constant && TLI.
+isLegalAddressImmediate(cast(Offset)->getValue());
// Check for #3.
- if (OffIsAMImm && BasePtr.Val->use_size() > 1) {
-for (SDNode::use_iterator I = BasePtr.Val->use_begin(),
- E = BasePtr.Val->use_end(); I != E; ++I) {
- SDNode *Use = *I;
- if (Use == Ptr.Val)
-continue;
- if (Use->getOpcode() == ISD::ADD || Use->getOpcode() ==
ISD::SUB){
-for (SDNode::use_iterator II = Use->use_begin(),
- EE = Use->use_end(); II != EE; ++II) {
- SDNode *UseUse = *II;
- if (UseUse->getOpcode() == ISD::LOAD &&
- cast(UseUse)->getBasePtr().Val == Use)
-return false;
- else if (UseUse->getOpcode() == ISD::STORE &&
- cast(UseUse)->getBasePtr().Val == Use)
-return false;
-}
+ for (SDNode::use_iterator I = BasePtr.Val->use_begin(),
+ E = BasePtr.Val->use_end(); I != E; ++I) {
+SDNode *Use = *I;
+if (Use == Ptr.Val)
+ continue;
+if (Use->getOpcode() == ISD::CopyToReg)
+ return false;
+if (OffIsAMImm && (Use->getOpcode() == ISD::ADD ||
+ Use->getOpcode() == ISD::SUB)) {
+ for (SDNode::use_iterator II = Use->use_begin(),
+ EE = Use->use_end(); II != EE; ++II) {
+SDNode *UseUse = *II;
+
[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.237 -> 1.238
---
Log message:
Add comment.
---
Diffs of the changes: (+10 -4)
DAGCombiner.cpp | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.237
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.238
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.237 Sun Nov 5 13:31:28 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Nov 6 02:14:30 2006
@@ -174,7 +174,13 @@
return true;
}
-bool CombineToIndexedLoadStore(SDNode *N) {
+/// CombineToPreIndexedLoadStore - Try turning a load / store into a
+/// pre-indexed load store when the base pointer is a add or subtract
+/// and it has other uses besides the load / store. When the
+/// transformation is done, the new indexed load / store effectively
+/// folded the add / subtract in and all of its other uses are redirected
+/// to the new load / store.
+bool CombineToPreIndexedLoadStore(SDNode *N) {
bool isLoad = true;
SDOperand Ptr;
if (LoadSDNode *LD = dyn_cast(N)) {
@@ -811,7 +817,7 @@
return DAG.getNode(ISD::OR, VT, N0, N1);
}
}
-
+
return SDOperand();
}
@@ -2871,7 +2877,7 @@
}
// Try transforming N to an indexed load.
- if (CombineToIndexedLoadStore(N))
+ if (CombineToPreIndexedLoadStore(N))
return SDOperand(N, 0);
return SDOperand();
@@ -2917,7 +2923,7 @@
}
// Try transforming N to an indexed store.
- if (CombineToIndexedLoadStore(N))
+ if (CombineToPreIndexedLoadStore(N))
return SDOperand(N, 0);
return SDOperand();
___
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.236 -> 1.237
SelectionDAG.cpp updated: 1.369 -> 1.370
---
Log message:
Unbreak VC++ build.
---
Diffs of the changes: (+9 -9)
DAGCombiner.cpp |2 +-
SelectionDAG.cpp | 16
2 files changed, 9 insertions(+), 9 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.236
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.237
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.236 Sun Nov 5 03:31:14 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Nov 5 13:31:28 2006
@@ -383,7 +383,7 @@
bool isAlias(SDOperand Ptr1, int64_t Size1,
const Value *SrcValue1, int SrcValueOffset1,
SDOperand Ptr2, int64_t Size2,
- const Value *SrcValue2, int SrcValueOffset1);
+ const Value *SrcValue2, int SrcValueOffset2);
/// FindAliasInfo - Extracts the relevant alias information from the memory
/// node. Returns true if the operand was a load.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.369
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.370
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.369Sun Nov 5
03:30:09 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Nov 5 13:31:28 2006
@@ -1657,16 +1657,16 @@
return getNode(ISD::VLOAD, getVTList(MVT::Vector, MVT::Other), Ops, 5);
}
-SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Value,
+SDOperand SelectionDAG::getStore(SDOperand Chain, SDOperand Val,
SDOperand Ptr, const Value *SV, int SVOffset,
bool isVolatile) {
- MVT::ValueType VT = Value.getValueType();
+ MVT::ValueType VT = Val.getValueType();
// FIXME: Alignment == 1 for now.
unsigned Alignment = 1;
SDVTList VTs = getVTList(MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDOperand Ops[] = { Chain, Value, Ptr, Undef };
+ SDOperand Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
@@ -1679,7 +1679,7 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
- SDNode *N = new StoreSDNode(Chain, Value, Ptr, Undef, ISD::UNINDEXED, false,
+ SDNode *N = new StoreSDNode(Chain, Val, Ptr, Undef, ISD::UNINDEXED, false,
VT, SV, SVOffset, Alignment, isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
@@ -1687,11 +1687,11 @@
return SDOperand(N, 0);
}
-SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Value,
+SDOperand SelectionDAG::getTruncStore(SDOperand Chain, SDOperand Val,
SDOperand Ptr, const Value *SV,
int SVOffset, MVT::ValueType SVT,
bool isVolatile) {
- MVT::ValueType VT = Value.getValueType();
+ MVT::ValueType VT = Val.getValueType();
bool isTrunc = VT != SVT;
assert(VT > SVT && "Not a truncation?");
@@ -1702,7 +1702,7 @@
unsigned Alignment = 1;
SDVTList VTs = getVTList(MVT::Other);
SDOperand Undef = getNode(ISD::UNDEF, Ptr.getValueType());
- SDOperand Ops[] = { Chain, Value, Ptr, Undef };
+ SDOperand Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
ID.AddInteger(ISD::UNINDEXED);
@@ -1715,7 +1715,7 @@
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
return SDOperand(E, 0);
- SDNode *N = new StoreSDNode(Chain, Value, Ptr, Undef, ISD::UNINDEXED,
isTrunc,
+ SDNode *N = new StoreSDNode(Chain, Val, Ptr, Undef, ISD::UNINDEXED, isTrunc,
SVT, SV, SVOffset, Alignment, isVolatile);
N->setValueTypes(VTs);
CSEMap.InsertNode(N, IP);
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.235 -> 1.236
---
Log message:
Added pre-indexed store support.
---
Diffs of the changes: (+24 -10)
DAGCombiner.cpp | 34 --
1 files changed, 24 insertions(+), 10 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.235
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.236
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.235 Fri Nov 3 01:21:16 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Nov 5 03:31:14 2006
@@ -175,9 +175,13 @@
}
bool CombineToIndexedLoadStore(SDNode *N) {
+ bool isLoad = true;
SDOperand Ptr;
if (LoadSDNode *LD = dyn_cast(N)) {
Ptr = LD->getBasePtr();
+ } else if (StoreSDNode *ST = dyn_cast(N)) {
+Ptr = ST->getBasePtr();
+isLoad = false;
} else
return false;
@@ -234,10 +238,9 @@
if (Use->isPredecessor(N))
return false;
-if (!OffIsAMImm)
+if (!OffIsAMImm) {
NumRealUses++;
-// FIXME: Do we need a target hook here
-else if (Use->getOpcode() == ISD::LOAD) {
+} else if (Use->getOpcode() == ISD::LOAD) {
if (cast(Use)->getBasePtr().Val != Ptr.Val)
NumRealUses++;
} else if (Use->getOpcode() == ISD::STORE) {
@@ -249,17 +252,23 @@
if (NumRealUses == 0)
return false;
- SDOperand Result =
-DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM);
+ SDOperand Result = isLoad
+? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM)
+: DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM);
++NodesCombined;
DEBUG(std::cerr << "\nReplacing.4 "; N->dump();
std::cerr << "\nWith: "; Result.Val->dump(&DAG);
std::cerr << '\n');
std::vector NowDead;
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
-NowDead);
- DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
-NowDead);
+ if (isLoad) {
+DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0),
+ NowDead);
+DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2),
+ NowDead);
+ } else {
+DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1),
+ NowDead);
+ }
// Nodes can end up on the worklist more than once. Make sure we do
// not process a node that has been replaced.
@@ -269,7 +278,8 @@
DAG.DeleteNode(N);
// Replace the uses of Ptr with uses of the updated base value.
- DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(1), NowDead);
+ DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0),
+NowDead);
removeFromWorkList(Ptr.Val);
for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
removeFromWorkList(NowDead[i]);
@@ -2906,6 +2916,10 @@
}
}
+ // Try transforming N to an indexed store.
+ if (CombineToIndexedLoadStore(N))
+return SDOperand(N, 0);
+
return SDOperand();
}
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.234 -> 1.235
---
Log message:
Rename
---
Diffs of the changes: (+1 -1)
DAGCombiner.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.234
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.235
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.234 Thu Nov 2 21:30:34 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Nov 3 01:21:16 2006
@@ -187,7 +187,7 @@
SDOperand BasePtr;
SDOperand Offset;
ISD::MemOpAddrMode AM = ISD::UNINDEXED;
-if (TLI.getLegalPreIndexedAddressBase(N, BasePtr, Offset, AM, DAG)) {
+if (TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) {
// Try turning it into a pre-indexed load / store except when
// 1) Another use of base ptr is a predecessor of N. If ptr is folded
//that would create a cycle.
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[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Changes in directory llvm/lib/CodeGen/SelectionDAG:
DAGCombiner.cpp updated: 1.233 -> 1.234
---
Log message:
Remove dead variable. Fix 80 column violations.
---
Diffs of the changes: (+3 -3)
DAGCombiner.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.233
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.234
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.233 Thu Nov 2 21:06:21 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Thu Nov 2 21:30:34 2006
@@ -176,7 +176,6 @@
bool CombineToIndexedLoadStore(SDNode *N) {
SDOperand Ptr;
- bool isLoad = true;
if (LoadSDNode *LD = dyn_cast(N)) {
Ptr = LD->getBasePtr();
} else
@@ -200,7 +199,8 @@
//themselves use of loads / stores.
bool OffIsAMImm = Offset.getOpcode() == ISD::Constant &&
-
TLI.isLegalAddressImmediate(cast(Offset)->getValue());
+TLI.isLegalAddressImmediate(
+ cast(Offset)->getValue());
// Check for #3.
if (OffIsAMImm && BasePtr.Val->use_size() > 1) {
@@ -209,7 +209,7 @@
SDNode *Use = *I;
if (Use == Ptr.Val)
continue;
- if (Use->getOpcode() == ISD::ADD || Use->getOpcode() ==
ISD::SUB) {
+ if (Use->getOpcode() == ISD::ADD || Use->getOpcode() ==
ISD::SUB){
for (SDNode::use_iterator II = Use->use_begin(),
EE = Use->use_end(); II != EE; ++II) {
SDNode *UseUse = *II;
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