Mesa (master): gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> false

2016-06-25 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 1c5a10497ab93495710989fe6c7dd1e776c51b05
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c5a10497ab93495710989fe6c7dd1e776c51b05

Author: Marek Olšák 
Date:   Tue Jun 21 21:29:39 2016 +0200

gallium/radeon/winsyses: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher 
Reviewed-by: Vedran Miletić 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeon/radeon_winsys.h| 43 +--
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 14 ++--
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 31 
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 10 +--
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 20 +++---
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 14 ++--
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 36 +-
 src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 10 +--
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 88 +++
 9 files changed, 134 insertions(+), 132 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index bbf91a8..afb970e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -254,10 +254,10 @@ struct radeon_info {
 uint64_tgart_size;
 uint64_tvram_size;
 boolhas_dedicated_vram;
-boolean has_virtual_memory;
+boolhas_virtual_memory;
 boolgfx_ib_pad_with_type2;
-boolean has_sdma;
-boolean has_uvd;
+boolhas_sdma;
+boolhas_uvd;
 uint32_tvce_fw_version;
 uint32_tvce_harvest_config;
 uint32_tclock_crystal_freq;
@@ -266,7 +266,7 @@ struct radeon_info {
 uint32_tdrm_major; /* version */
 uint32_tdrm_minor;
 uint32_tdrm_patchlevel;
-boolean has_userptr;
+boolhas_userptr;
 
 /* Shader cores. */
 uint32_tr600_max_quad_pipes; /* wave size / 16 */
@@ -279,7 +279,7 @@ struct radeon_info {
 uint32_tr300_num_gb_pipes;
 uint32_tr300_num_z_pipes;
 uint32_tr600_gb_backend_map; /* R600 harvest config */
-boolean r600_gb_backend_map_valid;
+boolr600_gb_backend_map_valid;
 uint32_tr600_num_banks;
 uint32_tnum_render_backends;
 uint32_tnum_tile_pipes; /* pipe count from PIPE_CONFIG 
*/
@@ -554,12 +554,12 @@ struct radeon_winsys {
  * \param buf   A winsys buffer object to get the handle from.
  * \param whandle   A winsys handle pointer.
  * \param strideA stride of the buffer in bytes, for texturing.
- * \return  TRUE on success.
+ * \return  true on success.
  */
-boolean (*buffer_get_handle)(struct pb_buffer *buf,
- unsigned stride, unsigned offset,
- unsigned slice_size,
- struct winsys_handle *whandle);
+bool (*buffer_get_handle)(struct pb_buffer *buf,
+  unsigned stride, unsigned offset,
+  unsigned slice_size,
+  struct winsys_handle *whandle);
 
 /**
  * Return the virtual address of a buffer.
@@ -676,14 +676,14 @@ struct radeon_winsys {
 struct pb_buffer *buf);
 
 /**
- * Return TRUE if there is enough memory in VRAM and GTT for the buffers
+ * Return true if there is enough memory in VRAM and GTT for the buffers
  * added so far. If the validation fails, all buffers which have
  * been added since the last call of cs_validate will be removed and
  * the CS will be flushed (provided there are still any buffers).
  *
  * \param csA command stream to validate.
  */
-boolean (*cs_validate)(struct radeon_winsys_cs *cs);
+bool (*cs_validate)(struct radeon_winsys_cs *cs);
 
 /**
  * Check whether the given number of dwords is available in the IB.
@@ -695,14 +695,15 @@ struct radeon_winsys {
 bool (*cs_check_space)(struct radeon_winsys_cs *cs, unsigned dw);
 
 /**
- * Return TRUE if there is enough memory in VRAM and GTT for the buffers
+ * Return true if there is enough memory in VRAM and GTT for the buffers
  * added so far.
  *
  * \param csA command stream to validate.
  * \param vram  VRAM memory size pending to be

Mesa (master): gallium/radeon: use r600_resource_reference

2016-06-25 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: d5383a7d3114aa5f81a704ff84f58de6b41f94bd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5383a7d3114aa5f81a704ff84f58de6b41f94bd

Author: Marek Olšák 
Date:   Tue Jun 21 21:13:00 2016 +0200

gallium/radeon: use r600_resource_reference

Reviewed-by: Alex Deucher 
Reviewed-by: Vedran Miletić 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/r600/r600_pipe.c|  4 ++--
 src/gallium/drivers/r600/r600_shader.c  |  2 +-
 src/gallium/drivers/r600/r600_state.c   | 16 ++--
 src/gallium/drivers/r600/r600_state_common.c|  2 +-
 src/gallium/drivers/radeon/r600_buffer_common.c |  4 ++--
 src/gallium/drivers/radeon/r600_query.c | 14 +++---
 src/gallium/drivers/radeon/r600_streamout.c |  2 +-
 src/gallium/drivers/radeon/r600_texture.c   | 14 +++---
 src/gallium/drivers/radeon/radeon_video.c   |  2 +-
 src/gallium/drivers/radeonsi/si_compute.c   |  6 ++
 src/gallium/drivers/radeonsi/si_descriptors.c   |  2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c |  4 +---
 12 files changed, 32 insertions(+), 40 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index 57721d9..119c76b 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -71,8 +71,8 @@ static void r600_destroy_context(struct pipe_context *context)
 
r600_sb_context_destroy(rctx->sb_context);
 
-   pipe_resource_reference((struct pipe_resource**)>dummy_cmask, 
NULL);
-   pipe_resource_reference((struct pipe_resource**)>dummy_fmask, 
NULL);
+   r600_resource_reference(>dummy_cmask, NULL);
+   r600_resource_reference(>dummy_fmask, NULL);
 
for (sh = 0; sh < PIPE_SHADER_TYPES; sh++) {
rctx->b.b.set_constant_buffer(>b.b, sh, 
R600_BUFFER_INFO_CONST_BUFFER, NULL);
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 9a1008e..ff098f1 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -288,7 +288,7 @@ error:
 
 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct 
r600_pipe_shader *shader)
 {
-   pipe_resource_reference((struct pipe_resource**)>bo, NULL);
+   r600_resource_reference(>bo, NULL);
r600_bytecode_clear(>shader.bc);
r600_release_command_buffer(>command_buffer);
 }
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 89a9f25..e805d33 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -967,10 +967,8 @@ static void r600_init_color_surface(struct r600_context 
*rctx,
surf->cb_color_cmask = surf->cb_color_base;
surf->cb_color_mask = 0;
 
-   pipe_resource_reference((struct pipe_resource**)>cb_buffer_cmask,
-   >resource.b.b);
-   pipe_resource_reference((struct pipe_resource**)>cb_buffer_fmask,
-   >resource.b.b);
+   r600_resource_reference(>cb_buffer_cmask, >resource);
+   r600_resource_reference(>cb_buffer_fmask, >resource);
 
if (rtex->cmask.size) {
surf->cb_color_cmask = rtex->cmask.offset >> 8;
@@ -1003,7 +1001,7 @@ static void r600_init_color_surface(struct r600_context 
*rctx,
struct pipe_transfer *transfer;
void *ptr;
 
-   pipe_resource_reference((struct 
pipe_resource**)>dummy_cmask, NULL);
+   r600_resource_reference(>dummy_cmask, NULL);
rctx->dummy_cmask = r600_buffer_create_helper(rscreen, 
cmask.size, cmask.alignment);
 
/* Set the contents to 0xCC. */
@@ -1011,19 +1009,17 @@ static void r600_init_color_surface(struct r600_context 
*rctx,
memset(ptr, 0xCC, cmask.size);
pipe_buffer_unmap(>b.b, transfer);
}
-   pipe_resource_reference((struct 
pipe_resource**)>cb_buffer_cmask,
-   >dummy_cmask->b.b);
+   r600_resource_reference(>cb_buffer_cmask, 
rctx->dummy_cmask);
 
/* FMASK. */
if (!rctx->dummy_fmask ||
rctx->dummy_fmask->b.b.width0 < fmask.size ||
rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
-   pipe_resource_reference((struct 
pipe_resource**)>dummy_fmask, NULL);
+   r600_resource_reference(>dummy_fmask, NULL);
rctx->dummy_fmask = r600_buffer_create_helper(rscreen, 
fmask.size, fmask.alignment);
 
}
-   pipe_resource_reference((struct 
pipe_resource**)>cb_buffer_fmask,
-

Mesa (master): radeonsi: make si_is_format_supported static

2016-06-25 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: d93bacc1fa4bf1d6d358da3615b00305e8518f33
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d93bacc1fa4bf1d6d358da3615b00305e8518f33

Author: Marek Olšák 
Date:   Tue Jun 21 21:46:16 2016 +0200

radeonsi: make si_is_format_supported static

Reviewed-by: Alex Deucher 
Reviewed-by: Vedran Miletić 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_pipe.c  |  1 -
 src/gallium/drivers/radeonsi/si_state.c | 11 ++-
 src/gallium/drivers/radeonsi/si_state.h |  5 -
 3 files changed, 6 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 0670372..d835681 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -692,7 +692,6 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws)
sscreen->b.b.destroy = si_destroy_screen;
sscreen->b.b.get_param = si_get_param;
sscreen->b.b.get_shader_param = si_get_shader_param;
-   sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.b.resource_create = r600_resource_create_common;
 
si_init_screen_state_functions(sscreen);
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index e6d1025..2e2c5ca 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1759,11 +1759,11 @@ static bool si_is_zs_format_supported(enum pipe_format 
format)
return si_translate_dbformat(format) != V_028040_Z_INVALID;
 }
 
-boolean si_is_format_supported(struct pipe_screen *screen,
-   enum pipe_format format,
-   enum pipe_texture_target target,
-   unsigned sample_count,
-   unsigned usage)
+static boolean si_is_format_supported(struct pipe_screen *screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned sample_count,
+ unsigned usage)
 {
unsigned retval = 0;
 
@@ -3514,6 +3514,7 @@ static void si_apply_opaque_metadata(struct 
r600_common_screen *rscreen,
 
 void si_init_screen_state_functions(struct si_screen *sscreen)
 {
+   sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
 }
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index 8d538e1..2e4923d 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -309,11 +309,6 @@ struct si_shader_selector;
 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
  struct r600_atom **list_elem,
  void (*emit_func)(struct si_context *ctx, struct r600_atom 
*state));
-boolean si_is_format_supported(struct pipe_screen *screen,
-   enum pipe_format format,
-   enum pipe_texture_target target,
-   unsigned sample_count,
-   unsigned usage);
 void si_init_state_functions(struct si_context *sctx);
 void si_init_screen_state_functions(struct si_screen *sscreen);
 void

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Mesa (master): radeonsi: boolean -> bool, TRUE -> true, FALSE -> false

2016-06-25 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 3eacbc52d51789f7c58dfe5ca1317962eb9d1a6a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eacbc52d51789f7c58dfe5ca1317962eb9d1a6a

Author: Marek Olšák 
Date:   Tue Jun 21 21:29:39 2016 +0200

radeonsi: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher 
Reviewed-by: Vedran Miletić 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_blit.c  |  2 +-
 src/gallium/drivers/radeonsi/si_pipe.c  |  6 +++---
 src/gallium/drivers/radeonsi/si_pipe.h  |  2 +-
 src/gallium/drivers/radeonsi/si_state.c | 20 ++--
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 73a72e0..46daeac 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -849,7 +849,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
util_blitter_blit_generic(sctx->blitter, dst_view, ,
  src_view, src_box, src_width0, src_height0,
  PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, 
NULL,
- FALSE);
+ false);
si_blitter_end(ctx);
 
pipe_surface_reference(_view, NULL);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index e025df4..0670372 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -164,7 +164,7 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen,
sctx->ce_suballocator =
u_suballocator_create(>b.b, 1024 * 1024,
  PIPE_BIND_CUSTOM,
- PIPE_USAGE_DEFAULT, 
FALSE);
+ PIPE_USAGE_DEFAULT, 
false);
if (!sctx->ce_suballocator)
goto fail;
}
@@ -704,7 +704,7 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws)
return NULL;
}
 
-   if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
+   if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
si_init_perfcounters(sscreen);
 
sscreen->b.has_cp_dma = true;
@@ -714,7 +714,7 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws)
HAVE_LLVM < 0x0308 ||
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 
-   if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
+   if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | 
DBG_CS;
 
/* Create the auxiliary context. This must be done last. */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index fe92c6a..d181905 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -309,7 +309,7 @@ struct si_context {
 
/* Scratch buffer */
struct r600_resource*scratch_buffer;
-   boolean emit_scratch_reloc;
+   boolemit_scratch_reloc;
unsignedscratch_waves;
unsignedspi_tmpring_size;
 
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 04e9f19..e6d1025 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1290,7 +1290,7 @@ static uint32_t si_translate_texformat(struct pipe_screen 
*screen,
bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
  sscreen->b.info.drm_minor >= 31) ||
 sscreen->b.info.drm_major == 3;
-   boolean uniform = TRUE;
+   bool uniform = true;
int i;
 
/* Colorspace (return non-RGB formats directly). */
@@ -1751,7 +1751,7 @@ static bool si_is_vertex_format_supported(struct 
pipe_screen *screen, enum pipe_
 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
 {
return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
-   r600_translate_colorswap(format, FALSE) != ~0U;
+   r600_translate_colorswap(format, false) != ~0U;
 }
 
 static bool si_is_zs_format_supported(enum pipe_format format)
@@ -1769,15 +1769,15 @@ boolean si_is_format_supported(struct pipe_screen 
*screen,
 
if (target >= PIPE_MAX_TEXTURE_TYPES) {
R600_ERR("r600: unsupported texture type %d\n", target);
-   return FALSE;
+   return false;
}
 
if

Mesa (master): gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> false

2016-06-25 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 7db10093d3ee26b0a5050ae01750465da1a76970
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7db10093d3ee26b0a5050ae01750465da1a76970

Author: Marek Olšák 
Date:   Tue Jun 21 21:29:39 2016 +0200

gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> false

Reviewed-by: Alex Deucher 
Reviewed-by: Vedran Miletić 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeon/r600_buffer_common.c| 12 ++---
 src/gallium/drivers/radeon/r600_perfcounter.c  | 22 
 src/gallium/drivers/radeon/r600_pipe_common.c  |  2 +-
 src/gallium/drivers/radeon/r600_pipe_common.h  | 10 ++--
 src/gallium/drivers/radeon/r600_query.c| 58 +++---
 src/gallium/drivers/radeon/r600_query.h| 30 +--
 src/gallium/drivers/radeon/r600_texture.c  |  4 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c| 10 ++--
 src/gallium/drivers/radeon/radeon_uvd.c|  2 +-
 9 files changed, 75 insertions(+), 75 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c 
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 4b0cf42..9583d70 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -30,18 +30,18 @@
 #include 
 #include 
 
-boolean r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
-   struct pb_buffer *buf,
-   enum radeon_bo_usage usage)
+bool r600_rings_is_buffer_referenced(struct r600_common_context *ctx,
+struct pb_buffer *buf,
+enum radeon_bo_usage usage)
 {
if (ctx->ws->cs_is_buffer_referenced(ctx->gfx.cs, buf, usage)) {
-   return TRUE;
+   return true;
}
if (radeon_emitted(ctx->dma.cs, 0) &&
ctx->ws->cs_is_buffer_referenced(ctx->dma.cs, buf, usage)) {
-   return TRUE;
+   return true;
}
-   return FALSE;
+   return false;
 }
 
 void *r600_buffer_map_sync_with_rings(struct r600_common_context *ctx,
diff --git a/src/gallium/drivers/radeon/r600_perfcounter.c 
b/src/gallium/drivers/radeon/r600_perfcounter.c
index af9a692..471c1dc 100644
--- a/src/gallium/drivers/radeon/r600_perfcounter.c
+++ b/src/gallium/drivers/radeon/r600_perfcounter.c
@@ -418,8 +418,8 @@ error:
return NULL;
 }
 
-static boolean r600_init_block_names(struct r600_common_screen *screen,
-struct r600_perfcounter_block *block)
+static bool r600_init_block_names(struct r600_common_screen *screen,
+ struct r600_perfcounter_block *block)
 {
unsigned i, j, k;
unsigned groups_shader = 1, groups_se = 1, groups_instance = 1;
@@ -452,7 +452,7 @@ static boolean r600_init_block_names(struct 
r600_common_screen *screen,
 
block->group_names = MALLOC(block->num_groups * 
block->group_name_stride);
if (!block->group_names)
-   return FALSE;
+   return false;
 
groupname = block->group_names;
for (i = 0; i < groups_shader; ++i) {
@@ -487,7 +487,7 @@ static boolean r600_init_block_names(struct 
r600_common_screen *screen,
block->selector_names = MALLOC(block->num_groups * block->num_selectors 
*
   block->selector_name_stride);
if (!block->selector_names)
-   return FALSE;
+   return false;
 
groupname = block->group_names;
p = block->selector_names;
@@ -499,7 +499,7 @@ static boolean r600_init_block_names(struct 
r600_common_screen *screen,
groupname += block->group_name_stride;
}
 
-   return TRUE;
+   return true;
 }
 
 int r600_get_perfcounter_info(struct r600_common_screen *screen,
@@ -577,17 +577,17 @@ void r600_perfcounters_destroy(struct r600_common_screen 
*rscreen)
rscreen->perfcounters->cleanup(rscreen);
 }
 
-boolean r600_perfcounters_init(struct r600_perfcounters *pc,
-  unsigned num_blocks)
+bool r600_perfcounters_init(struct r600_perfcounters *pc,
+   unsigned num_blocks)
 {
pc->blocks = CALLOC(num_blocks, sizeof(struct r600_perfcounter_block));
if (!pc->blocks)
-   return FALSE;
+   return false;
 
-   pc->separate_se = debug_get_bool_option("RADEON_PC_SEPARATE_SE", FALSE);
-   pc->separate_instance = 
debug_get_bool_option("RADEON_PC_SEPARATE_INSTANCE", FALSE);
+   pc->separate_se = debug_get_bool_option("RADEON_PC_SEPARATE_SE", false);
+   pc->separate_instance = 
debug_get_bool_option("RADEON_PC_SEPARATE_INSTANCE", false);
 
-   return TRUE;
+   return true;
 }
 
 void r600_perfcounters_add_block(struct

Mesa (master): nir: Add a NIR_VALIDATE environment variable

2016-06-25 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 81978c6febd43b8a88a4db09133f9659e15b492c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81978c6febd43b8a88a4db09133f9659e15b492c

Author: Jason Ekstrand 
Date:   Thu Jun 23 14:22:03 2016 -0700

nir: Add a NIR_VALIDATE environment variable

It defaults to true so default behavior doesn't change but it allows you to
do NIR_VALIDATE=false if you don't want validation.  Disabling validation
can substantially speed up shader compiles so you frequently want to turn
it off if compiler invariants aren't in question.
Reviewed-by: Matt Turner 

Reviewed-by: Matt Turner 
Signed-off-by: Rob Clark 

---

 src/compiler/nir/nir_validate.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index e5f5b8a..63e85cf 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -1124,6 +1124,12 @@ dump_errors(validate_state *state)
 void
 nir_validate_shader(nir_shader *shader)
 {
+   static int should_validate = -1;
+   if (should_validate < 0)
+  should_validate = env_var_as_boolean("NIR_VALIDATE", true);
+   if (!should_validate)
+  return;
+
validate_state state;
init_validate_state();
 

___
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mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): st/nine: Use offset_units_unscaled

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: b76fa5673924ce09e28f3000808e3bd50ffe4570
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b76fa5673924ce09e28f3000808e3bd50ffe4570

Author: Axel Davy 
Date:   Tue Jun 14 23:24:24 2016 +0200

st/nine: Use offset_units_unscaled

offset_units_unscaled enables proper support
for depth bias for gallium nine. Use it
if available.

Solves issues with some games using depth bias.
For example:
https://github.com/iXit/Mesa-3D/issues/220

Signed-off-by: Axel Davy 

---

 src/gallium/state_trackers/nine/device9.c|  1 +
 src/gallium/state_trackers/nine/device9.h|  1 +
 src/gallium/state_trackers/nine/nine_pipe.c  | 18 +-
 src/gallium/state_trackers/nine/nine_pipe.h  |  2 +-
 src/gallium/state_trackers/nine/nine_state.c |  2 +-
 5 files changed, 13 insertions(+), 11 deletions(-)

diff --git a/src/gallium/state_trackers/nine/device9.c 
b/src/gallium/state_trackers/nine/device9.c
index bb1735a..b4ce3c8 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -427,6 +427,7 @@ NineDevice9_ctor( struct NineDevice9 *This,
 This->driver_caps.window_space_position_support = 
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
 This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
 This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen, 
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
+This->driver_caps.offset_units_unscaled = 
GET_PCAP(POLYGON_OFFSET_UNITS_UNSCALED);
 
 nine_ff_init(This); /* initialize fixed function code */
 
diff --git a/src/gallium/state_trackers/nine/device9.h 
b/src/gallium/state_trackers/nine/device9.h
index 73a43cf..d584a35 100644
--- a/src/gallium/state_trackers/nine/device9.h
+++ b/src/gallium/state_trackers/nine/device9.h
@@ -121,6 +121,7 @@ struct NineDevice9
 boolean window_space_position_support;
 boolean vs_integer;
 boolean ps_integer;
+boolean offset_units_unscaled;
 } driver_caps;
 
 struct {
diff --git a/src/gallium/state_trackers/nine/nine_pipe.c 
b/src/gallium/state_trackers/nine/nine_pipe.c
index 79b910c..c1814fe 100644
--- a/src/gallium/state_trackers/nine/nine_pipe.c
+++ b/src/gallium/state_trackers/nine/nine_pipe.c
@@ -70,7 +70,9 @@ nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state 
*dsa_state,
 }
 
 void
-nine_convert_rasterizer_state(struct pipe_rasterizer_state *rast_state, const 
DWORD *rs)
+nine_convert_rasterizer_state(struct NineDevice9 *device,
+  struct pipe_rasterizer_state *rast_state,
+  const DWORD *rs)
 {
 struct pipe_rasterizer_state rast;
 
@@ -120,14 +122,12 @@ nine_convert_rasterizer_state(struct 
pipe_rasterizer_state *rast_state, const DW
 /* offset_units has the ogl/d3d11 meaning.
  * d3d9: offset = scale * dz + bias
  * ogl/d3d11: offset = scale * dz + r * bias
- * with r implementation dependant and is supposed to be
- * the smallest value the depth buffer format can hold.
- * In practice on current and past hw it seems to be 2^-23
- * for all formats except float formats where it varies depending
- * on the content.
- * For now use 1 << 23, but in the future perhaps add a way in gallium
- * to get r for the format or get the gallium behaviour */
-rast.offset_units = asfloat(rs[D3DRS_DEPTHBIAS]) * (float)(1 << 23);
+ * with r implementation dependent (+ different formula for float depth
+ * buffers). r=2^-23 is often the right value for gallium drivers.
+ * If possible, use offset_units_unscaled, which gives the d3d9
+ * behaviour, else scale by 1 << 23 */
+rast.offset_units = asfloat(rs[D3DRS_DEPTHBIAS]) * 
(device->driver_caps.offset_units_unscaled ? 1.0f : (float)(1 << 23));
+rast.offset_units_unscaled = device->driver_caps.offset_units_unscaled;
 rast.offset_scale = asfloat(rs[D3DRS_SLOPESCALEDEPTHBIAS]);
  /* rast.offset_clamp = 0.0f; */
 
diff --git a/src/gallium/state_trackers/nine/nine_pipe.h 
b/src/gallium/state_trackers/nine/nine_pipe.h
index 4d2bc92..fe8e910 100644
--- a/src/gallium/state_trackers/nine/nine_pipe.h
+++ b/src/gallium/state_trackers/nine/nine_pipe.h
@@ -38,7 +38,7 @@ extern const enum pipe_format 
nine_d3d9_to_pipe_format_map[120];
 extern const D3DFORMAT nine_pipe_to_d3d9_format_map[PIPE_FORMAT_COUNT];
 
 void nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *, const 
DWORD *);
-void nine_convert_rasterizer_state(struct pipe_rasterizer_state *, const DWORD 
*);
+void nine_convert_rasterizer_state(struct NineDevice9 *, struct 
pipe_rasterizer_state *, const DWORD *);
 void nine_convert_blend_state(struct pipe_blend_state *, const DWORD *);
 void nine_convert_sampler_state(struct cso_context *, int idx, const DWORD *);
 
diff --git a/src/gallium/state_trackers/nine/nine_state.c

Mesa (master): r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: 400e8d8c4080de0d9ab907b6ebbcc15c1ab02822
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=400e8d8c4080de0d9ab907b6ebbcc15c1ab02822

Author: Axel Davy 
Date:   Tue Jun 14 22:22:50 2016 +0200

r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for r600

Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.

v2: Increase the num_dw field for the poly offset atom

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/r600/r600_state.c | 37 ---
 1 file changed, 13 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index afb0e2f..578aef9 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -254,16 +254,24 @@ static void r600_emit_polygon_offset(struct r600_context 
*rctx, struct r600_atom
struct r600_poly_offset_state *state = (struct 
r600_poly_offset_state*)a;
float offset_units = state->offset_units;
float offset_scale = state->offset_scale;
+   uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
 
switch (state->zs_format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
offset_units *= 2.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
break;
case PIPE_FORMAT_Z16_UNORM:
offset_units *= 4.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
break;
-   default:;
+   default:
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
+   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
}
 
radeon_set_context_reg_seq(cs, R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE, 
4);
@@ -271,6 +279,9 @@ static void r600_emit_polygon_offset(struct r600_context 
*rctx, struct r600_atom
radeon_emit(cs, fui(offset_units));
radeon_emit(cs, fui(offset_scale));
radeon_emit(cs, fui(offset_units));
+
+   radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+  pa_su_poly_offset_db_fmt_cntl);
 }
 
 static uint32_t r600_get_blend_control(const struct pipe_blend_state *state, 
unsigned i)
@@ -1058,25 +1069,6 @@ static void r600_init_depth_surface(struct r600_context 
*rctx,
surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | 
S_028000_SLICE_TILE_MAX(slice);
surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
 
-   switch (surf->base.format) {
-   case PIPE_FORMAT_Z24X8_UNORM:
-   case PIPE_FORMAT_Z24_UNORM_S8_UINT:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
-   break;
-   case PIPE_FORMAT_Z32_FLOAT:
-   case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
-   S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
-   break;
-   case PIPE_FORMAT_Z16_UNORM:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
-   break;
-   default:;
-   }
-
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
surf->db_htile_data_base = 0;
@@ -1456,9 +1448,6 @@ static void r600_emit_framebuffer_state(struct 
r600_context *rctx, struct r600_a
   
RADEON_PRIO_DEPTH_BUFFER_MSAA :
   
RADEON_PRIO_DEPTH_BUFFER);
 
-   radeon_set_context_reg(cs, 
R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
-  surf->pa_su_poly_offset_db_fmt_cntl);
-
radeon_set_context_reg_seq(cs, R_028000_DB_DEPTH_SIZE, 2);
radeon_emit(cs, surf->db_depth_size); /* R_028000_DB_DEPTH_SIZE 
*/
radeon_emit(cs, surf->db_depth_view); /* R_028004_DB_DEPTH_VIEW 
*/
@@ -3084,7 +3073,7 @@ void r600_init_state_functions(struct r600_context *rctx)
r600_init_atom(rctx, >db_misc_state.atom, id++, 
r600_emit_db_misc_state, 7);
r600_init_atom(rctx, >db_state.atom, id++, r600_emit_db_state, 
11);
r600_init_atom(rctx, >dsa_state.atom, id++, r600_emit_cso_state, 
0);
-   r600_init_atom(rctx, >poly_offset_state.atom, id++, 
r600_emit_polygon_offset, 6);
+   r600_init_atom(rctx, >poly_offset_state.atom, id++, 
r600_emit_polygon_offset, 9);

Mesa (master): gallium: Add a cap for offset_units_unscaled

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: 59a692916ca251db995050f7fc0bb7b4e6e4780b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59a692916ca251db995050f7fc0bb7b4e6e4780b

Author: Axel Davy 
Date:   Mon Jun 13 22:28:32 2016 +0200

gallium: Add a cap for offset_units_unscaled

D3D9 has a different behaviour for depth bias.

For OGL/D3D1X, the depth bias unit is the
minimal resolvable value for the depth buffer,
which depends on the format (and has different
behaviour for float depth buffers).

For D3D9, the depth bias unit is 1.0f.

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/docs/source/cso/rasterizer.rst   | 6 ++
 src/gallium/docs/source/screen.rst   | 2 ++
 src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
 src/gallium/drivers/i915/i915_screen.c   | 1 +
 src/gallium/drivers/ilo/ilo_screen.c | 1 +
 src/gallium/drivers/llvmpipe/lp_screen.c | 1 +
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
 src/gallium/drivers/r300/r300_screen.c   | 1 +
 src/gallium/drivers/r600/r600_pipe.c | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
 src/gallium/drivers/softpipe/sp_screen.c | 1 +
 src/gallium/drivers/svga/svga_screen.c   | 1 +
 src/gallium/drivers/swr/swr_screen.cpp   | 1 +
 src/gallium/drivers/vc4/vc4_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/include/pipe/p_defines.h | 1 +
 src/gallium/include/pipe/p_state.h   | 7 +++
 19 files changed, 31 insertions(+)

diff --git a/src/gallium/docs/source/cso/rasterizer.rst 
b/src/gallium/docs/source/cso/rasterizer.rst
index 8d473b8..616e451 100644
--- a/src/gallium/docs/source/cso/rasterizer.rst
+++ b/src/gallium/docs/source/cso/rasterizer.rst
@@ -127,6 +127,12 @@ offset_tri
 
 offset_units
 Specifies the polygon offset bias
+offset_units_unscaled
+Specifies the unit of the polygon offset bias. If false, use the
+GL/D3D1X behaviour. If true, offset_units is a floating point offset
+which isn't scaled (D3D9). Note that GL/D3D1X behaviour has different
+formula whether the depth buffer is unorm or float, which is not
+the case for D3D9.
 offset_scale
 Specifies the polygon offset scale
 offset_clamp
diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index a20b372..141b45a 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -343,6 +343,8 @@ The integer capabilities:
 * ``PIPE_CAP_TGSI_VOTE``: Whether the ``VOTE_*`` ops can be used in shaders.
 * ``PIPE_CAP_MAX_WINDOW_RECTANGLES``: The maxium number of window rectangles
   supported in ``set_window_rectangles``.
+* ``PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED``: If true, the driver implements 
support
+  for ``pipe_rasterizer_state::offset_units_unscaled``.
 
 
 .. _pipe_capf:
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 9138024..93b70e0 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -264,6 +264,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/i915/i915_screen.c 
b/src/gallium/drivers/i915/i915_screen.c
index e898f7e..3f0ab98 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -275,6 +275,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
cap)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
   return 0;
 
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index a775aa6..2024688 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -504,6 +504,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 7d01e64..684c7a5 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -327,6 +327,7 @@

Mesa (master): r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: f6704f2a4db7113e597d4bab2cefc02e166c2ad9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6704f2a4db7113e597d4bab2cefc02e166c2ad9

Author: Axel Davy 
Date:   Tue Jun 14 23:13:26 2016 +0200

r600g: Implement POLYGON_OFFSET_UNITS_UNSCALED

Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.

PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/r600/evergreen_state.c   | 39 +++-
 src/gallium/drivers/r600/r600_pipe.c |  2 +-
 src/gallium/drivers/r600/r600_pipe.h |  2 ++
 src/gallium/drivers/r600/r600_state.c| 35 +
 src/gallium/drivers/r600/r600_state_common.c |  4 ++-
 5 files changed, 46 insertions(+), 36 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 797f593..fab0359 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -492,6 +492,7 @@ static void *evergreen_create_rs_state(struct pipe_context 
*ctx,
rs->offset_units = state->offset_units;
rs->offset_scale = state->offset_scale * 16.0f;
rs->offset_enable = state->offset_point || state->offset_line || 
state->offset_tri;
+   rs->offset_units_unscaled = state->offset_units_unscaled;
 
if (state->point_size_per_vertex) {
psize_min = util_get_min_point_size(state);
@@ -1665,24 +1666,26 @@ static void evergreen_emit_polygon_offset(struct 
r600_context *rctx, struct r600
float offset_scale = state->offset_scale;
uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
 
-   switch (state->zs_format) {
-   case PIPE_FORMAT_Z24X8_UNORM:
-   case PIPE_FORMAT_Z24_UNORM_S8_UINT:
-   case PIPE_FORMAT_X8Z24_UNORM:
-   case PIPE_FORMAT_S8_UINT_Z24_UNORM:
-   offset_units *= 2.0f;
-   pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
-   break;
-   case PIPE_FORMAT_Z16_UNORM:
-   offset_units *= 4.0f;
-   pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
-   break;
-   default:
-   pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
-   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+   if (!state->offset_units_unscaled) {
+   switch (state->zs_format) {
+   case PIPE_FORMAT_Z24X8_UNORM:
+   case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+   case PIPE_FORMAT_X8Z24_UNORM:
+   case PIPE_FORMAT_S8_UINT_Z24_UNORM:
+   offset_units *= 2.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
+   break;
+   case PIPE_FORMAT_Z16_UNORM:
+   offset_units *= 4.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
+   break;
+   default:
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) 
|
+   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+   }
}
 
radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 
4);
diff --git a/src/gallium/drivers/r600/r600_pipe.c 
b/src/gallium/drivers/r600/r600_pipe.c
index fe1af7c..57721d9 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -282,6 +282,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 1;
 
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
@@ -370,7 +371,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
-   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 0;
 
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
diff --git a/src/gallium/drivers/r600/r600_pipe.h

Mesa (master): r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreen

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: fe2ec50d754d9ddf38d167ff56e376577732c128
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe2ec50d754d9ddf38d167ff56e376577732c128

Author: Axel Davy 
Date:   Tue Jun 14 22:30:11 2016 +0200

r600g: move PA_SU_POLY_OFFSET_DB_FMT_CNTL to poly offset states for evergreen

Emit PA_SU_POLY_OFFSET_DB_FMT_CNTL with the other poly_offset states.
This will be useful to implement
PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.

v2: Increase the num_dw field for the poly offset atom

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/r600/evergreen_state.c | 38 ++
 1 file changed, 13 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 0b8488d..797f593 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1222,27 +1222,6 @@ static void evergreen_init_depth_surface(struct 
r600_context *rctx,
surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x *
   levelinfo->nblk_y / 64 - 
1);
 
-   switch (surf->base.format) {
-   case PIPE_FORMAT_Z24X8_UNORM:
-   case PIPE_FORMAT_Z24_UNORM_S8_UINT:
-   case PIPE_FORMAT_X8Z24_UNORM:
-   case PIPE_FORMAT_S8_UINT_Z24_UNORM:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
-   break;
-   case PIPE_FORMAT_Z32_FLOAT:
-   case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
-   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
-   break;
-   case PIPE_FORMAT_Z16_UNORM:
-   surf->pa_su_poly_offset_db_fmt_cntl =
-   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
-   break;
-   default:;
-   }
-
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
uint64_t stencil_offset;
unsigned stile_split = rtex->surface.stencil_tile_split;
@@ -1627,8 +1606,6 @@ static void evergreen_emit_framebuffer_state(struct 
r600_context *rctx, struct r
   
RADEON_PRIO_DEPTH_BUFFER_MSAA :
   
RADEON_PRIO_DEPTH_BUFFER);
 
-   radeon_set_context_reg(cs, 
R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
-  zb->pa_su_poly_offset_db_fmt_cntl);
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, 
zb->db_depth_view);
 
radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 8);
@@ -1686,6 +1663,7 @@ static void evergreen_emit_polygon_offset(struct 
r600_context *rctx, struct r600
struct r600_poly_offset_state *state = (struct 
r600_poly_offset_state*)a;
float offset_units = state->offset_units;
float offset_scale = state->offset_scale;
+   uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
 
switch (state->zs_format) {
case PIPE_FORMAT_Z24X8_UNORM:
@@ -1693,11 +1671,18 @@ static void evergreen_emit_polygon_offset(struct 
r600_context *rctx, struct r600
case PIPE_FORMAT_X8Z24_UNORM:
case PIPE_FORMAT_S8_UINT_Z24_UNORM:
offset_units *= 2.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-24);
break;
case PIPE_FORMAT_Z16_UNORM:
offset_units *= 4.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-16);
break;
-   default:;
+   default:
+   pa_su_poly_offset_db_fmt_cntl =
+   S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS((char)-23) |
+   S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
}
 
radeon_set_context_reg_seq(cs, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE, 
4);
@@ -1705,6 +1690,9 @@ static void evergreen_emit_polygon_offset(struct 
r600_context *rctx, struct r600
radeon_emit(cs, fui(offset_units));
radeon_emit(cs, fui(offset_scale));
radeon_emit(cs, fui(offset_units));
+
+   radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+  pa_su_poly_offset_db_fmt_cntl);
 }
 
 static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct 
r600_atom *atom)
@@ -3645,7 +3633,7 @@ void evergreen_init_state_functions(struct r600_context 
*rctx)
r600_init_atom(rctx, >db_misc_state.atom, id++, 
evergreen_emit_db_misc_state, 10);
r600_init_atom(rctx, >db_state.atom, id++, 
evergreen_emit_db_state, 14);
r600_init_atom(rctx, >dsa_state.atom,

Mesa (master): radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALED

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: be7957b156e30ffe9fb647b58ba00e236e498c3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be7957b156e30ffe9fb647b58ba00e236e498c3f

Author: Axel Davy 
Date:   Tue Jun 14 22:41:50 2016 +0200

radeonsi: Implement POLYGON_OFFSET_UNITS_UNSCALED

Empirical tests show that the polygon offset
behaviour is entirely determined by the content of
the PA_SU_POLY_OFFSET states, and not by the depth buffer
format bound.

PA_SU_POLY_OFFSET seems to directly set the parameters of
the polygon offset formula, and setting 0 for
PA_SU_POLY_OFFSET_DB_FMT_CNTL (ie setting the unorm depth
bias behaviour with a scale of 2^0 = 1.0f) gives the unscaled
behaviour.

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_pipe.c  |  2 +-
 src/gallium/drivers/radeonsi/si_state.c | 32 ++--
 2 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 37406aa..e025df4 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -357,6 +357,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_GENERATE_MIPMAP:
+   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 1;
 
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
@@ -415,7 +416,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
-   case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 0;
 
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index ccae571..04e9f19 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -810,20 +810,24 @@ static void *si_create_rs_state(struct pipe_context *ctx,
float offset_scale = state->offset_scale * 16.0f;
uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
 
-   switch (i) {
-   case 0: /* 16-bit zbuffer */
-   offset_units *= 4.0f;
-   pa_su_poly_offset_db_fmt_cntl = 
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
-   break;
-   case 1: /* 24-bit zbuffer */
-   offset_units *= 2.0f;
-   pa_su_poly_offset_db_fmt_cntl = 
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
-   break;
-   case 2: /* 32-bit zbuffer */
-   offset_units *= 1.0f;
-   pa_su_poly_offset_db_fmt_cntl = 
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
-   
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
-   break;
+   if (!state->offset_units_unscaled) {
+   switch (i) {
+   case 0: /* 16-bit zbuffer */
+   offset_units *= 4.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
+   break;
+   case 1: /* 24-bit zbuffer */
+   offset_units *= 2.0f;
+   pa_su_poly_offset_db_fmt_cntl =
+   
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
+   break;
+   case 2: /* 32-bit zbuffer */
+   offset_units *= 1.0f;
+   pa_su_poly_offset_db_fmt_cntl = 
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
+   
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+   break;
+   }
}
 
si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,

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Mesa (master): radeon: Remove useless pa_su_poly_offset_db_fmt_cntl

2016-06-25 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: c2b7b48a54e0124dd8aa0513a264d76535ea9829
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2b7b48a54e0124dd8aa0513a264d76535ea9829

Author: Axel Davy 
Date:   Tue Jun 14 22:32:04 2016 +0200

radeon: Remove useless pa_su_poly_offset_db_fmt_cntl

pa_su_poly_offset_db_fmt_cntl usages were removed in
previous patches.

Signed-off-by: Axel Davy 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_pipe_common.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 8117c9a..a70c7fe 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -317,7 +317,6 @@ struct r600_surface {
unsigned db_htile_surface;
unsigned db_htile_data_base;
unsigned db_preload_control;/* EG and later */
-   unsigned pa_su_poly_offset_db_fmt_cntl;
 };
 
 struct r600_common_screen {

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