Mesa (master): vbo: remove MaxVertexAttribStride assert check.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 48e28ab961f54466c033b087931ee17d502821db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48e28ab961f54466c033b087931ee17d502821db

Author: Dave Airlie 
Date:   Tue May 15 15:44:04 2018 +1000

vbo: remove MaxVertexAttribStride assert check.

Some drivers (virgl) don't support GL4.4 or GLES3.1 yet,
so never fill in this const.

Reviewed-by: Mathias Fröhlich 
Signed-off-by: Dave Airlie 

---

 src/mesa/vbo/vbo_exec_draw.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
index 342fbc6070..8d74725db3 100644
--- a/src/mesa/vbo/vbo_exec_draw.c
+++ b/src/mesa/vbo/vbo_exec_draw.c
@@ -201,7 +201,6 @@ vbo_exec_bind_arrays(struct gl_context *ctx)
 
/* Bind the buffer object */
const GLuint stride = exec->vtx.vertex_size*sizeof(GLfloat);
-   assert(stride <= ctx->Const.MaxVertexAttribStride);
_mesa_bind_vertex_buffer(ctx, vao, 0, exec->vtx.bufferobj, buffer_offset,
 stride);
 

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Mesa (master): mesa: drop GL_EXT_polygon_offset support

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c0c69bd8ddf384379863d8b4bcbc670e86984ae5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0c69bd8ddf384379863d8b4bcbc670e86984ae5

Author: Timothy Arceri 
Date:   Fri May 11 15:33:22 2018 +1000

mesa: drop GL_EXT_polygon_offset support

glPolygonOffset() has been part of the GL standard since 1.1. Also
niether AMD or Nvidia support this in their binary drivers.

Reviewed-by: Marek Olšák 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=61761

---

 docs/relnotes/18.2.0.html   | 64 +
 src/mapi/glapi/gen/gl_API.xml   | 10 --
 src/mapi/glapi/tests/check_table.cpp|  1 -
 src/mesa/main/dlist.c   | 11 --
 src/mesa/main/extensions_table.h|  1 -
 src/mesa/main/get_hash_params.py|  1 -
 src/mesa/main/polygon.c |  8 -
 src/mesa/main/polygon.h |  3 --
 src/mesa/main/tests/dispatch_sanity.cpp |  1 -
 9 files changed, 64 insertions(+), 36 deletions(-)

diff --git a/docs/relnotes/18.2.0.html b/docs/relnotes/18.2.0.html
new file mode 100644
index 00..f3bdb6605c
--- /dev/null
+++ b/docs/relnotes/18.2.0.html
@@ -0,0 +1,64 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 18.2.0 Release Notes / TBD
+
+
+Mesa 18.2.0 is a new development release. People who are concerned
+with stability and reliability should stick with a previous release or
+wait for Mesa 18.2.1.
+
+
+Mesa 18.2.0 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+
+
+SHA256 checksums
+
+TBD.
+
+
+
+New features
+
+
+Note: some of the new features are only available with certain drivers.
+
+
+
+TBD
+
+
+Bug fixes
+
+
+TBD
+
+
+Changes
+
+
+Removed GL_EXT_polygon_offset applications should use glPolygonOffset 
instead.
+
+
+
+
+
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index db312370b1..8ad45970c9 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8423,16 +8423,6 @@
 
 
 
-
-
-
-
-
-
-
-
-
-
 
 
 
diff --git a/src/mapi/glapi/tests/check_table.cpp 
b/src/mapi/glapi/tests/check_table.cpp
index 6230f1273f..761f2a24e0 100644
--- a/src/mapi/glapi/tests/check_table.cpp
+++ b/src/mapi/glapi/tests/check_table.cpp
@@ -1260,7 +1260,6 @@ const struct name_offset known_dispatch[] = {
{ "glTextureStorage1DEXT", _O(TextureStorage1DEXT) },
{ "glTextureStorage2DEXT", _O(TextureStorage2DEXT) },
{ "glTextureStorage3DEXT", _O(TextureStorage3DEXT) },
-   { "glPolygonOffsetEXT", _O(PolygonOffsetEXT) },
{ "glSampleMaskSGIS", _O(SampleMaskSGIS) },
{ "glSamplePatternSGIS", _O(SamplePatternSGIS) },
{ "glColorPointerEXT", _O(ColorPointerEXT) },
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 9e6cb725f5..8be223559a 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -3486,14 +3486,6 @@ save_PolygonOffset(GLfloat factor, GLfloat units)
 
 
 static void GLAPIENTRY
-save_PolygonOffsetEXT(GLfloat factor, GLfloat bias)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   /* XXX mult by DepthMaxF here??? */
-   save_PolygonOffset(factor, ctx->DrawBuffer->_DepthMaxF * bias);
-}
-
-static void GLAPIENTRY
 save_PolygonOffsetClampEXT(GLfloat factor, GLfloat units, GLfloat clamp)
 {
GET_CURRENT_CONTEXT(ctx);
@@ -9839,9 +9831,6 @@ _mesa_initialize_save_table(const struct gl_context *ctx)
SET_BlendColorEXT(table, save_BlendColorEXT);
 #endif
 
-   /* 3. GL_EXT_polygon_offset */
-   SET_PolygonOffsetEXT(table, save_PolygonOffsetEXT);
-
/* 6. GL_EXT_texture3d */
 #if 0
SET_CopyTexSubImage3DEXT(table, save_CopyTexSubImage3D);
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 945b462122..38d241db52 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -240,7 +240,6 @@ EXT(EXT_packed_float, 
EXT_packed_float
 EXT(EXT_packed_pixels   , dummy_true   
  , GLL,  x ,  x ,  x , 1997)
 EXT(EXT_pixel_buffer_object , EXT_pixel_buffer_object  
  , GLL, GLC,  x ,  x , 2004)
 EXT(EXT_point_parameters, EXT_point_parameters 
  , GLL,  x ,  x ,  x , 1997)
-EXT(EXT_polygon_offset  , dummy_true   
  , GLL,  x ,  x ,  x , 1995)
 EXT(EXT_polygon_offset_clamp, ARB_polygon_offset_clamp 
  , GLL, GLC, ES1, ES2, 2014)
 EXT(EXT_primitive_bounding_box  , O

Mesa (master): tgsi: fix incorrect tgsi_shader_info::num_tokens computation

[Brian Paul]

Module: Mesa
Branch: master
Commit: 8fde9429c36b75d9e5afec4e221aff9b47db54f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fde9429c36b75d9e5afec4e221aff9b47db54f6

Author: Brian Paul 
Date:   Thu May 17 13:38:05 2018 -0600

tgsi: fix incorrect tgsi_shader_info::num_tokens computation

We were incrementing num_tokens in each loop iteration while parsing
the shader.  But each call to tgsi_parse_token() can consume more than
one token (and often does).  Instead, just call the tgsi_num_tokens()
function.

Luckily, this issue doesn't seem to effect any current users of this
field (llvmpipe just checks for <= 1, for example).

Reviewed-by: Neha Bhende
Reviewed-by: Roland Scheidegger 

---

 src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 18488d776e..685a413c4e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -836,13 +836,12 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
   procType == PIPE_SHADER_TESS_EVAL ||
   procType == PIPE_SHADER_COMPUTE);
info->processor = procType;
+   info->num_tokens = tgsi_num_tokens(parse.Tokens);
 
/**
 ** Loop over incoming program tokens/instructions
 */
while (!tgsi_parse_end_of_tokens(&parse)) {
-  info->num_tokens++;
-
   tgsi_parse_token( &parse );
 
   switch( parse.FullToken.Token.Type ) {

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Mesa (master): radv: add radv_emit_shader_pointer() helper

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: fcba3934fc138d6b9bfa911bd6c8f1155f577b58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcba3934fc138d6b9bfa911bd6c8f1155f577b58

Author: Samuel Pitoiset 
Date:   Thu May 17 14:08:43 2018 +0200

radv: add radv_emit_shader_pointer() helper

For future work (support for 32-bit GPU pointers).

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_cmd_buffer.c | 13 ++---
 src/amd/vulkan/radv_device.c |  8 ++--
 src/amd/vulkan/radv_private.h| 10 ++
 3 files changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1ca687494a..a8359ac092 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -587,9 +587,9 @@ radv_emit_userdata_address(struct radv_cmd_buffer 
*cmd_buffer,
return;
assert(loc->num_sgprs == 2);
assert(!loc->indirect);
-   radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + loc->sgpr_idx * 4, va);
 }
 
 static void
@@ -1442,10 +1442,9 @@ emit_stage_descriptor_set_userdata(struct 
radv_cmd_buffer *cmd_buffer,
 
assert(!desc_set_loc->indirect);
assert(desc_set_loc->num_sgprs == 2);
-   radeon_set_sh_reg_seq(cmd_buffer->cs,
- base_reg + desc_set_loc->sgpr_idx * 4, 2);
-   radeon_emit(cmd_buffer->cs, va);
-   radeon_emit(cmd_buffer->cs, va >> 32);
+
+   radv_emit_shader_pointer(cmd_buffer->cs,
+base_reg + desc_set_loc->sgpr_idx * 4, va);
 }
 
 static void
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7067f5b01d..c52b3a591f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1963,9 +1963,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
   R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
 
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
}
} else {
uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
@@ -1976,9 +1974,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
   R_00B530_SPI_SHADER_USER_DATA_LS_0};
 
for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
-   radeon_set_sh_reg_seq(cs, regs[i], 2);
-   radeon_emit(cs, va);
-   radeon_emit(cs, va >> 32);
+   radv_emit_shader_pointer(cs, regs[i], va);
}
}
 }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 304ed17f01..adfd75c2a8 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -59,6 +59,7 @@
 #include "ac_surface.h"
 #include "radv_descriptor_set.h"
 #include "radv_extensions.h"
+#include "radv_cs.h"
 
 #include 
 
@@ -1128,6 +1129,15 @@ bool radv_get_memory_fd(struct radv_device *device,
struct radv_device_memory *memory,
int *pFD);
 
+static inline void
+radv_emit_shader_pointer(struct radeon_winsys_cs *cs,
+uint32_t sh_offset, uint64_t va)
+{
+   radeon_set_sh_reg_seq(cs, sh_offset, 2);
+   radeon_emit(cs, va);
+   radeon_emit(cs, va >> 32);
+}
+
 static inline struct radv_descriptor_state *
 radv_get_descriptors_state(struct radv_cmd_buffer *cmd_buffer,
   VkPipelineBindPoint bind_point)

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Mesa (master): radv: add some helpers for cleaning up radv_get_preamble_cs()

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 9b2c310a70c5be08debae3ed5054a5619914ef5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b2c310a70c5be08debae3ed5054a5619914ef5d

Author: Samuel Pitoiset 
Date:   Thu May 17 10:11:44 2018 +0200

radv: add some helpers for cleaning up radv_get_preamble_cs()

Because this function looks a bit ugly to me.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_device.c | 214 ++-
 1 file changed, 128 insertions(+), 86 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 51b44cc222..7067f5b01d 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1861,6 +1861,128 @@ radv_get_hs_offchip_param(struct radv_device *device, 
uint32_t *max_offchip_buff
return hs_offchip_param;
 }
 
+static void
+radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_winsys_cs *cs,
+   struct radeon_winsys_bo *esgs_ring_bo,
+   uint32_t esgs_ring_size,
+   struct radeon_winsys_bo *gsvs_ring_bo,
+   uint32_t gsvs_ring_size)
+{
+   if (!esgs_ring_bo && !gsvs_ring_bo)
+   return;
+
+   if (esgs_ring_bo)
+   radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
+
+   if (gsvs_ring_bo)
+   radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+   radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
+   radeon_emit(cs, esgs_ring_size >> 8);
+   radeon_emit(cs, gsvs_ring_size >> 8);
+   } else {
+   radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
+   radeon_emit(cs, esgs_ring_size >> 8);
+   radeon_emit(cs, gsvs_ring_size >> 8);
+   }
+}
+
+static void
+radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_winsys_cs 
*cs,
+  unsigned hs_offchip_param, unsigned tf_ring_size,
+  struct radeon_winsys_bo *tess_rings_bo)
+{
+   uint64_t tf_va;
+
+   if (!tess_rings_bo)
+   return;
+
+   tf_va = radv_buffer_get_va(tess_rings_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= CIK) {
+   radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
+  S_030938_SIZE(tf_ring_size / 4));
+   radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
+  tf_va >> 8);
+   if (queue->device->physical_device->rad_info.chip_class >= 
GFX9) {
+   radeon_set_uconfig_reg(cs, 
R_030944_VGT_TF_MEMORY_BASE_HI,
+  S_030944_BASE_HI(tf_va >> 40));
+   }
+   radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
+  hs_offchip_param);
+   } else {
+   radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
+ S_008988_SIZE(tf_ring_size / 4));
+   radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
+ tf_va >> 8);
+   radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
+hs_offchip_param);
+   }
+}
+
+static void
+radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_winsys_cs 
*cs,
+ struct radeon_winsys_bo *compute_scratch_bo)
+{
+   uint64_t scratch_va;
+
+   if (!compute_scratch_bo)
+   return;
+
+   scratch_va = radv_buffer_get_va(compute_scratch_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
+
+   radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
+   radeon_emit(cs, scratch_va);
+   radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
+   S_008F04_SWIZZLE_ENABLE(1));
+}
+
+static void
+radv_emit_global_shader_pointers(struct radv_queue *queue,
+struct radeon_winsys_cs *cs,
+struct radeon_winsys_bo *descriptor_bo)
+{
+   uint64_t va;
+
+   if (!descriptor_bo)
+   return;
+
+   va = radv_buffer_get_va(descriptor_bo);
+
+   radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
+
+   if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
+   uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
+  R_00B130_SPI_SHADER_USER_DATA_VS_0,
+  R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
+  R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
+
+   fo

Mesa (master): amd: remove support for LLVM 4.0

[Marek Olšák]

Module: Mesa
Branch: master
Commit: f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9eb1ef870eba9fdacf9a8cbd815ec3bff81db05

Author: Marek Olšák 
Date:   Wed May 16 22:23:41 2018 -0400

amd: remove support for LLVM 4.0

It doesn't support GFX9.

Acked-by: Dave Airlie 
Acked-by: Samuel Pitoiset 

---

 .travis.yml|   6 +-
 configure.ac   |   4 +-
 meson.build|   4 +-
 src/amd/common/ac_llvm_build.c | 282 -
 src/amd/common/ac_llvm_helper.cpp  |  12 -
 src/amd/vulkan/radv_debug.c|   8 +-
 src/amd/vulkan/radv_device.c   |   9 +-
 src/amd/vulkan/radv_nir_to_llvm.c  |   2 +-
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c  |   7 -
 src/gallium/drivers/radeonsi/si_get.c  |   4 +-
 src/gallium/drivers/radeonsi/si_pipe.c |   2 +-
 .../drivers/radeonsi/si_shader_tgsi_setup.c|   3 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c  |   7 -
 13 files changed, 121 insertions(+), 229 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index e0d6a827a6..c8b68a6696 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -123,7 +123,7 @@ matrix:
 - BUILD=make
 - MAKEFLAGS="-j4"
 - MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=4.0
+- LLVM_VERSION=5.0
 - LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
 - DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
 - DRI_DRIVERS=""
@@ -134,12 +134,12 @@ matrix:
   addons:
 apt:
   sources:
-- llvm-toolchain-trusty-4.0
+- llvm-toolchain-trusty-5.0
   packages:
 # LLVM packaging is broken and misses these dependencies
 - libedit-dev
 # From sources above
-- llvm-4.0-dev
+- llvm-5.0-dev
 # Common
 - xz-utils
 - x11proto-xf86vidmode-dev
diff --git a/configure.ac b/configure.ac
index 401025bf2e..62063c1c8a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -107,8 +107,8 @@ dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
 LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
-LLVM_REQUIRED_RADEONSI=4.0.0
-LLVM_REQUIRED_RADV=4.0.0
+LLVM_REQUIRED_RADEONSI=5.0.0
+LLVM_REQUIRED_RADV=5.0.0
 LLVM_REQUIRED_SWR=4.0.0
 
 dnl Check for progs
diff --git a/meson.build b/meson.build
index 0f88ddfe8e..d0cb896163 100644
--- a/meson.build
+++ b/meson.build
@@ -1107,7 +1107,9 @@ if with_gallium_opencl
   # TODO: optional modules
 endif
 
-if with_amd_vk or with_gallium_radeonsi or with_gallium_swr
+if with_amd_vk or with_gallium_radeonsi
+  _llvm_version = '>= 5.0.0'
+elif with_gallium_swr
   _llvm_version = '>= 4.0.0'
 elif with_gallium_opencl or with_gallium_r600
   _llvm_version = '>= 3.9.0'
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 6f5f04496e..36c1d62637 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -888,127 +888,91 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
bool writeonly_memory,
bool swizzle_enable_hint)
 {
-   static unsigned dfmt[] = {
-   V_008F0C_BUF_DATA_FORMAT_32,
-   V_008F0C_BUF_DATA_FORMAT_32_32,
-   V_008F0C_BUF_DATA_FORMAT_32_32_32,
-   V_008F0C_BUF_DATA_FORMAT_32_32_32_32
-   };
+   /* Split 3 channel stores, becase LLVM doesn't support 3-channel
+* intrinsics. */
+   if (num_channels == 3) {
+   LLVMValueRef v[3], v01;
+
+   for (int i = 0; i < 3; i++) {
+   v[i] = LLVMBuildExtractElement(ctx->builder, vdata,
+   LLVMConstInt(ctx->i32, i, 0), "");
+   }
+   v01 = ac_build_gather_values(ctx, v, 2);
+
+   ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,
+   soffset, inst_offset, glc, slc,
+   writeonly_memory, 
swizzle_enable_hint);
+   ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
+   soffset, inst_offset + 8,
+   glc, slc,
+   writeonly_memory, 
swizzle_enable_hint);
+   return;
+   }
 
/* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
 * (voffset is swizzled, but soffset isn't swizzled).
 * llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
 */
-   if (!swizzle_enable_hint || HAVE_LLVM >= 0x0500) {
-   /* Split 3 channel stores, becase LLVM doesn't support 3-channel
-* intrinsics. */
-   if (num_chann

Mesa (master): docs: update calendar, add news and link release notes to 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: master
Commit: 11a0d5563f49b84f27b2707d77a8553da52d73ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11a0d5563f49b84f27b2707d77a8553da52d73ba

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:45:26 2018 +

docs: update calendar, add news and link release notes to 18.0.4

Signed-off-by: Juan A. Suarez Romero 

---

 docs/index.html| 6 ++
 docs/release-calendar.html | 8 +---
 docs/relnotes.html | 1 +
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/docs/index.html b/docs/index.html
index de65588743..5644ead731 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,12 @@
 
 News
 
+May 17, 2018
+
+Mesa 18.0.4 is released.
+This is a bug-fix release.
+
+
 May 7, 2018
 
 Mesa 18.0.3 is released.
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 49f4300d38..ba297532dc 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -39,13 +39,7 @@ if you'd like to nominate a patch in the next stable release.
 Notes
 
 
-18.0
-2018-05-18
-18.0.4
-Juan A. Suarez Romero
-
-
-
+18.0
 2018-06-01
 18.0.5
 Juan A. Suarez Romero
diff --git a/docs/relnotes.html b/docs/relnotes.html
index 78af393a51..6f90021610 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 
 
 
+18.0.4 release notes
 18.0.3 release notes
 18.0.2 release notes
 18.0.1 release notes

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Mesa (18.0): docs: add sha256 checksums for 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: 18.0
Commit: 69ef6e4a75255e60a4c4a2419d03c9352b9eb8f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ef6e4a75255e60a4c4a2419d03c9352b9eb8f2

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:40:11 2018 +

docs: add sha256 checksums for 18.0.4

Signed-off-by: Juan A. Suarez Romero 

---

 docs/relnotes/18.0.4.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/18.0.4.html b/docs/relnotes/18.0.4.html
index 4da04995b9..3f738bd337 100644
--- a/docs/relnotes/18.0.4.html
+++ b/docs/relnotes/18.0.4.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  
mesa-18.0.4.tar.gz
+1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  
mesa-18.0.4.tar.xz
 
 
 

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Mesa (master): docs: add sha256 checksums for 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: master
Commit: 042e21976a73c9b37e6866aa2fadea39fbc97cdd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=042e21976a73c9b37e6866aa2fadea39fbc97cdd

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:40:11 2018 +

docs: add sha256 checksums for 18.0.4

Signed-off-by: Juan A. Suarez Romero 
(cherry picked from commit 69ef6e4a75255e60a4c4a2419d03c9352b9eb8f2)

---

 docs/relnotes/18.0.4.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/18.0.4.html b/docs/relnotes/18.0.4.html
index 4da04995b9..3f738bd337 100644
--- a/docs/relnotes/18.0.4.html
+++ b/docs/relnotes/18.0.4.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+d1dc3469faccdd73439479426952d71a9e8f684e8d03b6687063c12b13430801  
mesa-18.0.4.tar.gz
+1f3bcfe7cef0a5c20dae2b41df5d7e0a985e06be0183fa4d43b6068fcba2920f  
mesa-18.0.4.tar.xz
 
 
 

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Mesa (master): docs: add release notes for 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: master
Commit: bb7750e8da3fac75a0503e2e9a53190d865babcf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb7750e8da3fac75a0503e2e9a53190d865babcf

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:14:17 2018 +

docs: add release notes for 18.0.4

Signed-off-by: Juan A. Suarez Romero 
(cherry picked from commit 3b49ab6219790c341ffb78a6eeaaa8b1a4b29bcc)

---

 docs/relnotes/18.0.4.html | 156 ++
 1 file changed, 156 insertions(+)

diff --git a/docs/relnotes/18.0.4.html b/docs/relnotes/18.0.4.html
new file mode 100644
index 00..4da04995b9
--- /dev/null
+++ b/docs/relnotes/18.0.4.html
@@ -0,0 +1,156 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 18.0.4 Release Notes / May 17, 2018
+
+
+Mesa 18.0.4 is a bug fix release which fixes bugs found since the 18.0.3 
release.
+
+
+Mesa 18.0.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=91808";>Bug 91808 
- trine1 misrender r600g
+
+https://bugs.freedesktop.org/show_bug.cgi?id=100430";>Bug 
100430 - [radv] graphical glitches on dolphin emulator
+
+https://bugs.freedesktop.org/show_bug.cgi?id=106243";>Bug 
106243 - [kbl] GPU HANG: 9:0:0x85db, in Cinnamon
+
+https://bugs.freedesktop.org/show_bug.cgi?id=106480";>Bug 
106480 - A2B10G10R10_SNORM vertex attribute doesn't work.
+
+
+
+
+Changes
+
+Bas Nieuwenhuizen (3):
+
+  radv: Translate logic ops.
+  radv: Fix up 2_10_10_10 alpha sign.
+  radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
+
+
+Dave Airlie (3):
+
+  r600: fix constant buffer bounds.
+  radv: resolve all layers in compute resolve path.
+  radv: use compute path for multi-layer images.
+
+
+Deepak Rawat (1):
+
+  egl/x11: Send invalidate to driver on copy_region path in 
swap_buffer
+
+
+Ian Romanick (1):
+
+  mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
+
+
+Jan Vesely (8):
+
+  clover: Add explicit virtual destructor to argument class
+  eg/compute: Drop reference on code_bo in destructor.
+  r600: Cleanup constant buffers on context destruction
+  eg/compute: Drop reference to kernel_param bo in destructor
+  pipe-loader: Free driver_name in error path
+  gallium/auxiliary: Add helper function to count the number of entries in 
hash table
+  winsys/radeon: Destroy fd_hash table when the last winsys is 
removed.
+  winsys/amdgpu: Destroy dev_hash table when the last winsys is 
removed.
+
+
+Jason Ekstrand (1):
+
+  i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
+
+
+Jose Maria Casanova Crespo (2):
+
+  intel/compiler: fix 16-bit int brw_negate_immediate and 
brw_abs_immediate
+  intel/compiler: fix brw_imm_w for negative 16-bit integers
+
+
+Juan A. Suarez Romero (7):
+
+  docs: add sha256 checksums for 18.0.3
+  cherry-ignore: add explicit 18.1 only nominations
+  cherry-ignore: glsl: change ast_type_qualifier bitset size to work 
around GCC 5.4 bug
+  cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex 
arrays attribs
+  cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type 
to TYPE_INT
+  cherry-ignore: radv/resolve: do fmask decompress on all layers.
+  Update version to 18.0.4
+
+
+Kai Wasserbäch (1):
+
+  opencl: autotools: Fix linking order for OpenCL target
+
+
+Kenneth Graunke (1):
+
+  i965: Don't leak blorp on Gen4-5.
+
+
+Lionel Landwerlin (2):
+
+  i965: require pixel scoreboard stall prior to ISP disable
+  anv: emit pixel scoreboard stall before ISP disable
+
+
+Matthew Nicholls (1):
+
+  radv: fix multisample image copies
+
+
+Neil Roberts (1):
+
+  spirv: Apply OriginUpperLeft to FragCoord
+
+
+Rhys Perry (1):
+
+  mesa: fix error handling in get_framebuffer_parameteriv
+
+
+Ross Burton (1):
+
+  src/intel/Makefile.vulkan.am: add missing MKDIR_GEN
+
+
+
+
+
+

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Mesa: tag mesa-18.0.4: mesa-18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: refs/tags/mesa-18.0.4
Tag:4d9750867adfd20d229260c69243f66f4b05d386
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=4d9750867adfd20d229260c69243f66f4b05d386

Tagger: Juan A. Suarez Romero 
Date:   Thu May 17 18:37:43 2018 +

mesa-18.0.4
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Mesa (master): mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.

[Mathias Fröhlich]

Module: Mesa
Branch: master
Commit: 984cb4e512f47fe6682f51985a0722c95e21f446
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=984cb4e512f47fe6682f51985a0722c95e21f446

Author: Mathias Fröhlich 
Date:   Sun May 13 09:18:57 2018 +0200

mesa: Flag _NEW_ARRAY only if we are changing ctx->Array.VAO.

For the VAO internal helper functions that may be called
with a non current VAO, flag the _NEW_ARRAY state only
if it is the current ctx->Array.VAO.

Reviewed-by: Brian Paul 
Signed-off-by: Mathias Fröhlich 

---

 src/mesa/main/varray.c | 20 ++--
 1 file changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index 4859f16050..a3e1aebb76 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -178,7 +178,8 @@ _mesa_vertex_attrib_binding(struct gl_context *ctx,
   array->BufferBindingIndex = bindingIndex;
 
   vao->NewArrays |= vao->_Enabled & array_bit;
-  ctx->NewState |= _NEW_ARRAY;
+  if (vao == ctx->Array.VAO)
+ ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -213,7 +214,8 @@ _mesa_bind_vertex_buffer(struct gl_context *ctx,
  vao->VertexAttribBufferMask |= binding->_BoundArrays;
 
   vao->NewArrays |= vao->_Enabled & binding->_BoundArrays;
-  ctx->NewState |= _NEW_ARRAY;
+  if (vao == ctx->Array.VAO)
+ ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -235,7 +237,8 @@ vertex_binding_divisor(struct gl_context *ctx,
if (binding->InstanceDivisor != divisor) {
   binding->InstanceDivisor = divisor;
   vao->NewArrays |= vao->_Enabled & binding->_BoundArrays;
-  ctx->NewState |= _NEW_ARRAY;
+  if (vao == ctx->Array.VAO)
+ ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -345,7 +348,8 @@ _mesa_update_array_format(struct gl_context *ctx,
array->_ElementSize = elementSize;
 
vao->NewArrays |= vao->_Enabled & VERT_BIT(attrib);
-   ctx->NewState |= _NEW_ARRAY;
+   if (vao == ctx->Array.VAO)
+  ctx->NewState |= _NEW_ARRAY;
 }
 
 /**
@@ -1080,7 +1084,9 @@ _mesa_enable_vertex_array_attrib(struct gl_context *ctx,
   const GLbitfield array_bit = VERT_BIT(attrib);
   vao->_Enabled |= array_bit;
   vao->NewArrays |= array_bit;
-  ctx->NewState |= _NEW_ARRAY;
+
+  if (vao == ctx->Array.VAO)
+ ctx->NewState |= _NEW_ARRAY;
 
   /* Update the map mode if needed */
   if (array_bit & (VERT_BIT_POS|VERT_BIT_GENERIC0))
@@ -1165,7 +1171,9 @@ _mesa_disable_vertex_array_attrib(struct gl_context *ctx,
   const GLbitfield array_bit = VERT_BIT(attrib);
   vao->_Enabled &= ~array_bit;
   vao->NewArrays |= array_bit;
-  ctx->NewState |= _NEW_ARRAY;
+
+  if (vao == ctx->Array.VAO)
+ ctx->NewState |= _NEW_ARRAY;
 
   /* Update the map mode if needed */
   if (array_bit & (VERT_BIT_POS|VERT_BIT_GENERIC0))

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Mesa (master): mesa: Remove flush_vertices argument from VAO methods.

[Mathias Fröhlich]

Module: Mesa
Branch: master
Commit: 5c7e3a90edf81000b8295ad9bb1029b8a24c6007
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c7e3a90edf81000b8295ad9bb1029b8a24c6007

Author: Mathias Fröhlich 
Date:   Sun May 13 09:18:57 2018 +0200

mesa: Remove flush_vertices argument from VAO methods.

The flush_vertices argument is now unused, remove it.

Reviewed-by: Brian Paul 
Signed-off-by: Mathias Fröhlich 

---

 src/mesa/drivers/common/meta.c   | 32 ++-
 src/mesa/main/bufferobj.c|  2 +-
 src/mesa/main/enable.c   |  4 +--
 src/mesa/main/varray.c   | 44 +++-
 src/mesa/main/varray.h   |  8 +++---
 src/mesa/state_tracker/st_cb_rasterpos.c |  4 +--
 src/mesa/vbo/vbo_context.c   |  2 +-
 src/mesa/vbo/vbo_exec_draw.c |  6 ++---
 src/mesa/vbo/vbo_save_api.c  |  6 ++---
 9 files changed, 51 insertions(+), 57 deletions(-)

diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 830d82ad49..6b1713e3b1 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -348,18 +348,18 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
GL_FALSE, GL_FALSE,
offsetof(struct vertex, x));
  _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_GENERIC(0),
-  *buf_obj, 0, sizeof(struct vertex), true);
+  *buf_obj, 0, sizeof(struct vertex));
  _mesa_enable_vertex_array_attrib(ctx, array_obj,
-  VERT_ATTRIB_GENERIC(0), true);
+  VERT_ATTRIB_GENERIC(0));
  if (texcoord_size > 0) {
 _mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_GENERIC(1),
   texcoord_size, GL_FLOAT, GL_RGBA,
   GL_FALSE, GL_FALSE, GL_FALSE,
   offsetof(struct vertex, tex));
 _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_GENERIC(1),
- *buf_obj, 0, sizeof(struct vertex), true);
+ *buf_obj, 0, sizeof(struct vertex));
 _mesa_enable_vertex_array_attrib(ctx, array_obj,
- VERT_ATTRIB_GENERIC(1), true);
+ VERT_ATTRIB_GENERIC(1));
  }
   } else {
  _mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_POS,
@@ -367,9 +367,8 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
GL_FALSE, GL_FALSE,
offsetof(struct vertex, x));
  _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_POS,
-  *buf_obj, 0, sizeof(struct vertex), true);
- _mesa_enable_vertex_array_attrib(ctx, array_obj,
-  VERT_ATTRIB_POS, true);
+  *buf_obj, 0, sizeof(struct vertex));
+ _mesa_enable_vertex_array_attrib(ctx, array_obj, VERT_ATTRIB_POS);
 
  if (texcoord_size > 0) {
 _mesa_update_array_format(ctx, array_obj, VERT_ATTRIB_TEX(0),
@@ -377,9 +376,9 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
   GL_FALSE, GL_FALSE,
   offsetof(struct vertex, tex));
 _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_TEX(0),
- *buf_obj, 0, sizeof(struct vertex), true);
+ *buf_obj, 0, sizeof(struct vertex));
 _mesa_enable_vertex_array_attrib(ctx, array_obj,
- VERT_ATTRIB_TEX(0), true);
+ VERT_ATTRIB_TEX(0));
  }
 
  if (color_size > 0) {
@@ -388,9 +387,9 @@ _mesa_meta_setup_vertex_objects(struct gl_context *ctx,
   GL_FALSE, GL_FALSE,
   offsetof(struct vertex, r));
 _mesa_bind_vertex_buffer(ctx, array_obj, VERT_ATTRIB_COLOR0,
- *buf_obj, 0, sizeof(struct vertex), true);
+ *buf_obj, 0, sizeof(struct vertex));
 _mesa_enable_vertex_array_attrib(ctx, array_obj,
- VERT_ATTRIB_COLOR0, true);
+ VERT_ATTRIB_COLOR0);
  }
   }
} else {
@@ -3347,9 +3346,8 @@ _mesa_meta_DrawTex(struct gl_context *ctx, GLfloat x, 
GLfloat y, GLfloat z,
 GL_FALSE, GL_FALSE,
 offsetof(struct vertex, x));
   _mesa_bind_vertex_buffer(ctx, arr

Mesa (master): mesa: The glArrayElement api is independent of the current program.

[Mathias Fröhlich]

Module: Mesa
Branch: master
Commit: 6fac626193a077cba3154acf3820b30fc6f3e874
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fac626193a077cba3154acf3820b30fc6f3e874

Author: Mathias Fröhlich 
Date:   Sun May 13 09:18:57 2018 +0200

mesa: The glArrayElement api is independent of the current program.

All the shader program dependent handling is done on the level
of the gl_Context::Array._DrawVAO/_DrawVAOEnabledAttribs.
So, skip array element invalidation on _NEW_PROGRAM.

Reviewed-by: Brian Paul 
Signed-off-by: Mathias Fröhlich 

---

 src/mesa/main/api_arrayelt.c | 2 +-
 src/mesa/vbo/vbo_context.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/api_arrayelt.c b/src/mesa/main/api_arrayelt.c
index 2dfa74f64b..afa3012021 100644
--- a/src/mesa/main/api_arrayelt.c
+++ b/src/mesa/main/api_arrayelt.c
@@ -1823,7 +1823,7 @@ _ae_invalidate_state(struct gl_context *ctx)
 * Luckily, neither the drivers nor tnl muck with the state that
 * concerns us here:
 */
-   assert(ctx->NewState & (_NEW_ARRAY | _NEW_PROGRAM));
+   assert(ctx->NewState & _NEW_ARRAY);
 
assert(!actx->mapped_vbos);
actx->dirty_state = true;
diff --git a/src/mesa/vbo/vbo_context.c b/src/mesa/vbo/vbo_context.c
index ee2e31ab7a..cf9405df3d 100644
--- a/src/mesa/vbo/vbo_context.c
+++ b/src/mesa/vbo/vbo_context.c
@@ -157,7 +157,7 @@ vbo_exec_invalidate_state(struct gl_context *ctx)
struct vbo_context *vbo = vbo_context(ctx);
struct vbo_exec_context *exec = &vbo->exec;
 
-   if (ctx->NewState & (_NEW_PROGRAM | _NEW_ARRAY)) {
+   if (ctx->NewState & _NEW_ARRAY) {
   _ae_invalidate_state(ctx);
}
if (ctx->NewState & _NEW_EVAL)

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Mesa (master): mesa: Remove FLUSH_VERTICES from VAO state changes.

[Mathias Fröhlich]

Module: Mesa
Branch: master
Commit: 9c7be67968aaba224d518dee86dff736a4b599c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c7be67968aaba224d518dee86dff736a4b599c6

Author: Mathias Fröhlich 
Date:   Sun May 13 09:18:57 2018 +0200

mesa: Remove FLUSH_VERTICES from VAO state changes.

Pending draw calls on immediate mode or display list calls do
not depend on changes of the VAO state. So, remove calls to
FLUSH_VERTICES and flag _NEW_ARRAY as appropriate.

Reviewed-by: Brian Paul 
Signed-off-by: Mathias Fröhlich 

---

 src/mesa/main/varray.c | 65 +-
 1 file changed, 6 insertions(+), 59 deletions(-)

diff --git a/src/mesa/main/varray.c b/src/mesa/main/varray.c
index d16807b406..2ced74a76c 100644
--- a/src/mesa/main/varray.c
+++ b/src/mesa/main/varray.c
@@ -172,16 +172,13 @@ _mesa_vertex_attrib_binding(struct gl_context *ctx,
   else
  vao->VertexAttribBufferMask &= ~array_bit;
 
-  if (flush_vertices) {
- FLUSH_VERTICES(ctx, _NEW_ARRAY);
-  }
-
   vao->BufferBinding[array->BufferBindingIndex]._BoundArrays &= ~array_bit;
   vao->BufferBinding[bindingIndex]._BoundArrays |= array_bit;
 
   array->BufferBindingIndex = bindingIndex;
 
   vao->NewArrays |= vao->_Enabled & array_bit;
+  ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -204,9 +201,6 @@ _mesa_bind_vertex_buffer(struct gl_context *ctx,
if (binding->BufferObj != vbo ||
binding->Offset != offset ||
binding->Stride != stride) {
-  if (flush_vertices) {
- FLUSH_VERTICES(ctx, _NEW_ARRAY);
-  }
 
   _mesa_reference_buffer_object(ctx, &binding->BufferObj, vbo);
 
@@ -219,6 +213,7 @@ _mesa_bind_vertex_buffer(struct gl_context *ctx,
  vao->VertexAttribBufferMask |= binding->_BoundArrays;
 
   vao->NewArrays |= vao->_Enabled & binding->_BoundArrays;
+  ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -238,9 +233,9 @@ vertex_binding_divisor(struct gl_context *ctx,
assert(!vao->SharedAndImmutable);
 
if (binding->InstanceDivisor != divisor) {
-  FLUSH_VERTICES(ctx, _NEW_ARRAY);
   binding->InstanceDivisor = divisor;
   vao->NewArrays |= vao->_Enabled & binding->_BoundArrays;
+  ctx->NewState |= _NEW_ARRAY;
}
 }
 
@@ -322,8 +317,6 @@ get_array_format(const struct gl_context *ctx, GLint 
sizeMax, GLint *size)
  * \param doublesDouble values not reduced to floats
  * \param relativeOffset Offset of the first element relative to the binding
  *   offset.
- * \param flush_verties  Should \c FLUSH_VERTICES be invoked before updating
- *   state?
  */
 void
 _mesa_update_array_format(struct gl_context *ctx,
@@ -623,7 +616,6 @@ _mesa_VertexPointer_no_error(GLint size, GLenum type, 
GLsizei stride,
  const GLvoid *ptr)
 {
GET_CURRENT_CONTEXT(ctx);
-   FLUSH_VERTICES(ctx, 0);
 
update_array(ctx, VERT_ATTRIB_POS, GL_RGBA, 4, size, type, stride,
 GL_FALSE, GL_FALSE, GL_FALSE, ptr);
@@ -635,8 +627,6 @@ _mesa_VertexPointer(GLint size, GLenum type, GLsizei 
stride, const GLvoid *ptr)
 {
GET_CURRENT_CONTEXT(ctx);
 
-   FLUSH_VERTICES(ctx, 0);
-
GLenum format = GL_RGBA;
GLbitfield legalTypes = (ctx->API == API_OPENGLES)
   ? (BYTE_BIT | SHORT_BIT | FLOAT_BIT | FIXED_ES_BIT)
@@ -660,7 +650,6 @@ void GLAPIENTRY
 _mesa_NormalPointer_no_error(GLenum type, GLsizei stride, const GLvoid *ptr )
 {
GET_CURRENT_CONTEXT(ctx);
-   FLUSH_VERTICES(ctx, 0);
 
update_array(ctx, VERT_ATTRIB_NORMAL, GL_RGBA, 3, 3, type, stride, GL_TRUE,
 GL_FALSE, GL_FALSE, ptr);
@@ -672,8 +661,6 @@ _mesa_NormalPointer(GLenum type, GLsizei stride, const 
GLvoid *ptr )
 {
GET_CURRENT_CONTEXT(ctx);
 
-   FLUSH_VERTICES(ctx, 0);
-
GLenum format = GL_RGBA;
const GLbitfield legalTypes = (ctx->API == API_OPENGLES)
   ? (BYTE_BIT | SHORT_BIT | FLOAT_BIT | FIXED_ES_BIT)
@@ -698,7 +685,6 @@ _mesa_ColorPointer_no_error(GLint size, GLenum type, 
GLsizei stride,
 const GLvoid *ptr)
 {
GET_CURRENT_CONTEXT(ctx);
-   FLUSH_VERTICES(ctx, 0);
 
GLenum format = get_array_format(ctx, BGRA_OR_4, &size);
update_array(ctx, VERT_ATTRIB_COLOR0, format, BGRA_OR_4, size,
@@ -712,8 +698,6 @@ _mesa_ColorPointer(GLint size, GLenum type, GLsizei stride, 
const GLvoid *ptr)
GET_CURRENT_CONTEXT(ctx);
const GLint sizeMin = (ctx->API == API_OPENGLES) ? 4 : 3;
 
-   FLUSH_VERTICES(ctx, 0);
-
GLenum format = get_array_format(ctx, BGRA_OR_4, &size);
const GLbitfield legalTypes = (ctx->API == API_OPENGLES)
   ? (UNSIGNED_BYTE_BIT | HALF_BIT | FLOAT_BIT | FIXED_ES_BIT)
@@ -740,7 +724,6 @@ void GLAPIENTRY
 _mesa_FogCoordPointer_no_error(GLenum type, GLsizei stride, const GLvoid *ptr)
 {
GET_CURRENT_CONTEXT(ctx);
-   FLUSH_VERTICES(ctx, 0);
 
update_array(ctx, VERT_ATTRIB_FOG, GL_RGBA, 1, 1, type, stride, GL_FALSE,
 GL_FALSE, GL_FALSE, ptr);
@

Mesa (18.0): Update version to 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: 18.0
Commit: a7f75b9487fa6cc422fd997891d5a909cc1042f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7f75b9487fa6cc422fd997891d5a909cc1042f8

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:09:26 2018 +

Update version to 18.0.4

Signed-off-by: Juan A. Suarez Romero 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index d1ac72de28..ae357e4b02 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-18.0.3
+18.0.4

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Mesa (18.0): docs: add release notes for 18.0.4

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: 18.0
Commit: 3b49ab6219790c341ffb78a6eeaaa8b1a4b29bcc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b49ab6219790c341ffb78a6eeaaa8b1a4b29bcc

Author: Juan A. Suarez Romero 
Date:   Thu May 17 18:14:17 2018 +

docs: add release notes for 18.0.4

Signed-off-by: Juan A. Suarez Romero 

---

 docs/relnotes/18.0.4.html | 156 ++
 1 file changed, 156 insertions(+)

diff --git a/docs/relnotes/18.0.4.html b/docs/relnotes/18.0.4.html
new file mode 100644
index 00..4da04995b9
--- /dev/null
+++ b/docs/relnotes/18.0.4.html
@@ -0,0 +1,156 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 18.0.4 Release Notes / May 17, 2018
+
+
+Mesa 18.0.4 is a bug fix release which fixes bugs found since the 18.0.3 
release.
+
+
+Mesa 18.0.4 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=91808";>Bug 91808 
- trine1 misrender r600g
+
+https://bugs.freedesktop.org/show_bug.cgi?id=100430";>Bug 
100430 - [radv] graphical glitches on dolphin emulator
+
+https://bugs.freedesktop.org/show_bug.cgi?id=106243";>Bug 
106243 - [kbl] GPU HANG: 9:0:0x85db, in Cinnamon
+
+https://bugs.freedesktop.org/show_bug.cgi?id=106480";>Bug 
106480 - A2B10G10R10_SNORM vertex attribute doesn't work.
+
+
+
+
+Changes
+
+Bas Nieuwenhuizen (3):
+
+  radv: Translate logic ops.
+  radv: Fix up 2_10_10_10 alpha sign.
+  radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
+
+
+Dave Airlie (3):
+
+  r600: fix constant buffer bounds.
+  radv: resolve all layers in compute resolve path.
+  radv: use compute path for multi-layer images.
+
+
+Deepak Rawat (1):
+
+  egl/x11: Send invalidate to driver on copy_region path in 
swap_buffer
+
+
+Ian Romanick (1):
+
+  mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
+
+
+Jan Vesely (8):
+
+  clover: Add explicit virtual destructor to argument class
+  eg/compute: Drop reference on code_bo in destructor.
+  r600: Cleanup constant buffers on context destruction
+  eg/compute: Drop reference to kernel_param bo in destructor
+  pipe-loader: Free driver_name in error path
+  gallium/auxiliary: Add helper function to count the number of entries in 
hash table
+  winsys/radeon: Destroy fd_hash table when the last winsys is 
removed.
+  winsys/amdgpu: Destroy dev_hash table when the last winsys is 
removed.
+
+
+Jason Ekstrand (1):
+
+  i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
+
+
+Jose Maria Casanova Crespo (2):
+
+  intel/compiler: fix 16-bit int brw_negate_immediate and 
brw_abs_immediate
+  intel/compiler: fix brw_imm_w for negative 16-bit integers
+
+
+Juan A. Suarez Romero (7):
+
+  docs: add sha256 checksums for 18.0.3
+  cherry-ignore: add explicit 18.1 only nominations
+  cherry-ignore: glsl: change ast_type_qualifier bitset size to work 
around GCC 5.4 bug
+  cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex 
arrays attribs
+  cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type 
to TYPE_INT
+  cherry-ignore: radv/resolve: do fmask decompress on all layers.
+  Update version to 18.0.4
+
+
+Kai Wasserbäch (1):
+
+  opencl: autotools: Fix linking order for OpenCL target
+
+
+Kenneth Graunke (1):
+
+  i965: Don't leak blorp on Gen4-5.
+
+
+Lionel Landwerlin (2):
+
+  i965: require pixel scoreboard stall prior to ISP disable
+  anv: emit pixel scoreboard stall before ISP disable
+
+
+Matthew Nicholls (1):
+
+  radv: fix multisample image copies
+
+
+Neil Roberts (1):
+
+  spirv: Apply OriginUpperLeft to FragCoord
+
+
+Rhys Perry (1):
+
+  mesa: fix error handling in get_framebuffer_parameteriv
+
+
+Ross Burton (1):
+
+  src/intel/Makefile.vulkan.am: add missing MKDIR_GEN
+
+
+
+
+
+

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Mesa (master): docs: add 18.0.5 in the release calendar

[Juan Antonio Suárez Romero]

Module: Mesa
Branch: master
Commit: 0a2c94755688762bf091de62ce5b19363bac7f9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a2c94755688762bf091de62ce5b19363bac7f9c

Author: Juan A. Suarez Romero 
Date:   Mon May 14 16:17:38 2018 +0200

docs: add 18.0.5 in the release calendar

Mesa 18.1 series has not been released yet, so let's extend 18.0 lifetime.

v2: Add missing closing TR tags (Eric Engestrom)

CC: Andres Gomez 
CC: Emil Velikov 
Reviewed-by: Andres Gomez 

---

 docs/release-calendar.html | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index e4e1a1e61f..49f4300d38 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -37,11 +37,18 @@ if you'd like to nominate a patch in the next stable 
release.
 Release
 Release manager
 Notes
+
 
-18.0
+18.0
 2018-05-18
 18.0.4
 Juan A. Suarez Romero
+
+
+
+2018-06-01
+18.0.5
+Juan A. Suarez Romero
 Last planned 18.0.x release
 
 

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Mesa (master): swr/rast: fix VCVTPD2PS generation for AVX512

[George Kyriazis]

Module: Mesa
Branch: master
Commit: 7970fcff2540b7678cc07ed269ec7fb860a4d2de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7970fcff2540b7678cc07ed269ec7fb860a4d2de

Author: Alok Hota 
Date:   Wed May 16 11:14:19 2018 -0500

swr/rast: fix VCVTPD2PS generation for AVX512

Reviewed-By: George Kyriazis 

---

 .../swr/rasterizer/jitter/functionpasses/lower_x86.cpp   | 12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git 
a/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
index 3caea67e16..e0296f6255 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
@@ -265,8 +265,16 @@ namespace SwrJit
 // Assuming the intrinsics are consistent and place the src 
operand and mask last in the argument list.
 if (mTarget == AVX512)
 {
-args.push_back(GetZeroVec(vecWidth, pElemTy));
-args.push_back(GetMask(vecWidth));
+if (pFunc->getName().equals("meta.intrinsic.VCVTPD2PS")) {
+args.push_back(GetZeroVec(W256, 
pCallInst->getType()->getScalarType()));
+args.push_back(GetMask(W256));
+// for AVX512 VCVTPD2PS, we also have to add rounding 
mode
+args.push_back(B->C(_MM_FROUND_TO_NEAREST_INT |
+_MM_FROUND_NO_EXC));
+} else {
+args.push_back(GetZeroVec(vecWidth, pElemTy));
+args.push_back(GetMask(vecWidth));
+}
 }
 
 return B->CALLA(pIntrin, args);

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Mesa (master): swr/rast: Added FEClipRectangles event

[George Kyriazis]

Module: Mesa
Branch: master
Commit: 936ce75285c35f30e55ec74772e48bac6f7d8176
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=936ce75285c35f30e55ec74772e48bac6f7d8176

Author: Alok Hota 
Date:   Wed May 16 11:14:21 2018 -0500

swr/rast: Added FEClipRectangles event

and also added some comments

Reviewed-By: George Kyriazis 

---

 src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp | 1 +
 src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h   | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp 
b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
index f1355dd0d9..f289a319ca 100644
--- a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.cpp
@@ -54,6 +54,7 @@ BUCKET_DESC gCoreBuckets[] = {
 { "FEClipPoints", "", false, 0x },
 { "FEClipLines", "", false, 0x },
 { "FEClipTriangles", "", false, 0x },
+{ "FEClipRectangles", "", false, 0x },
 { "FECullZeroAreaAndBackface", "", false, 0x },
 { "FECullBetweenCenters", "", false, 0x },
 { "FEEarlyRastEnter", "", false, 0x },
diff --git a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h 
b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
index 3a7ee4c3f0..704da650d8 100644
--- a/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
+++ b/src/gallium/drivers/swr/rasterizer/core/rdtsc_core.h
@@ -29,6 +29,9 @@
 
 #include 
 
+///
+// NOTE:  This enum MUST be kept in sync with gCoreBuckets in rdtsc_core.cpp
+///
 enum CORE_BUCKETS
 {
 APIClearRenderTarget,

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Mesa (master): swr/rast: Whitespace and tab-to-spaces changes

[George Kyriazis]

Module: Mesa
Branch: master
Commit: a33d3761331ac025c74eeb111bb04d228857b8ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a33d3761331ac025c74eeb111bb04d228857b8ce

Author: Alok Hota 
Date:   Wed May 16 11:14:20 2018 -0500

swr/rast: Whitespace and tab-to-spaces changes

Reviewed-By: George Kyriazis 

---

 .../drivers/swr/rasterizer/jitter/JitManager.cpp   |  1 -
 .../swr/rasterizer/jitter/builder_gfx_mem.cpp  | 27 --
 .../swr/rasterizer/jitter/builder_gfx_mem.h|  2 +-
 .../drivers/swr/rasterizer/jitter/builder_mem.cpp  |  1 -
 .../rasterizer/jitter/functionpasses/lower_x86.cpp |  4 ++--
 5 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
index efb747abde..e9412b1b53 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp
@@ -580,7 +580,6 @@ int ExecUnhookedProcess(const std::string& CmdLine, 
std::string* pStdOut, std::s
 return ExecCmd(CmdLine, "", pStdOut, pStdErr);
 }
 
-
 /// notifyObjectCompiled - Provides a pointer to compiled code for Module M.
 void JitCache::notifyObjectCompiled(const llvm::Module *M, 
llvm::MemoryBufferRef Obj)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp 
b/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
index c6d0619043..3013bc53d7 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_gfx_mem.cpp
@@ -57,14 +57,15 @@ namespace SwrJit
 
 
 //
-/// @brief Generate a masked gather operation in LLVM IR.  If not  
+/// @brief Generate a masked gather operation in LLVM IR.  If not
 /// supported on the underlying platform, emulate it with loads
 /// @param vSrc - SIMD wide value that will be loaded if mask is invalid
 /// @param pBase - Int8* base VB address pointer value
 /// @param vIndices - SIMD wide value of VB byte offsets
 /// @param vMask - SIMD wide mask that controls whether to access memory 
or the src values
 /// @param scale - value to scale indices by
-Value* BuilderGfxMem::GATHERPS(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask, uint8_t scale, JIT_MEM_CLIENT usage)
+Value* BuilderGfxMem::GATHERPS(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask,
+   uint8_t scale, JIT_MEM_CLIENT usage)
 {
 // address may be coming in as 64bit int now so get the pointer
 if (pBase->getType() == mInt64Ty)
@@ -77,14 +78,15 @@ namespace SwrJit
 }
 
 //
-/// @brief Generate a masked gather operation in LLVM IR.  If not  
+/// @brief Generate a masked gather operation in LLVM IR.  If not
 /// supported on the underlying platform, emulate it with loads
 /// @param vSrc - SIMD wide value that will be loaded if mask is invalid
 /// @param pBase - Int8* base VB address pointer value
 /// @param vIndices - SIMD wide value of VB byte offsets
 /// @param vMask - SIMD wide mask that controls whether to access memory 
or the src values
 /// @param scale - value to scale indices by
-Value* BuilderGfxMem::GATHERDD(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask, uint8_t scale, JIT_MEM_CLIENT usage)
+Value* BuilderGfxMem::GATHERDD(Value* vSrc, Value* pBase, Value* vIndices, 
Value* vMask,
+   uint8_t scale, JIT_MEM_CLIENT usage)
 {
 
 // address may be coming in as 64bit int now so get the pointer
@@ -98,38 +100,39 @@ namespace SwrJit
 }
 
 
-Value* BuilderGfxMem::OFFSET_TO_NEXT_COMPONENT(Value* base, Constant 
*offset)
+Value* BuilderGfxMem::OFFSET_TO_NEXT_COMPONENT(Value* base, Constant* 
offset)
 {
 return ADD(base, offset);
 }
-
-Value* BuilderGfxMem::GEP(Value* Ptr, Value* Idx, Type *Ty, const Twine 
&Name)
+
+Value* BuilderGfxMem::GEP(Value* Ptr, Value* Idx, Type* Ty, const Twine& 
Name)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ptr, Idx, nullptr, Name);
 }
 
-Value* BuilderGfxMem::GEP(Type *Ty, Value* Ptr, Value* Idx, const Twine 
&Name)
+Value* BuilderGfxMem::GEP(Type* Ty, Value* Ptr, Value* Idx, const Twine& 
Name)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ty, Ptr, Idx, Name);
 }
 
-Value* BuilderGfxMem::GEP(Value* Ptr, const std::initializer_list 
&indexList, Type *Ty)
+Value* BuilderGfxMem::GEP(Value* Ptr, const std::initializer_list& 
indexList, Type* Ty)
 {
 Ptr = TranslationHelper(Ptr, Ty);
 return Builder::GEP(Ptr, indexList);
 }
 
-Value* BuilderGfxMem::GEP(Value* Ptr, const 
std::initializer_lis

Mesa (master): swr/rast: Remove unneeded virtual from methods

[George Kyriazis]

Module: Mesa
Branch: master
Commit: 7926d18fa5df028f73fbbb8f30f81cb7f3c79901
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7926d18fa5df028f73fbbb8f30f81cb7f3c79901

Author: Alok Hota 
Date:   Wed May 16 11:14:17 2018 -0500

swr/rast: Remove unneeded virtual from methods

Reviewed-By: George Kyriazis 

---

 src/gallium/drivers/swr/rasterizer/jitter/JitManager.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h 
b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
index 54a25d8913..152776a651 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/JitManager.h
@@ -108,12 +108,12 @@ public:
 }
 
 /// notifyObjectCompiled - Provides a pointer to compiled code for Module 
M.
-virtual void notifyObjectCompiled(const llvm::Module *M, 
llvm::MemoryBufferRef Obj);
+void notifyObjectCompiled(const llvm::Module *M, llvm::MemoryBufferRef 
Obj) override;
 
 /// Returns a pointer to a newly allocated MemoryBuffer that contains the
 /// object which corresponds with Module M, or 0 if an object is not
 /// available.
-virtual std::unique_ptr getObject(const llvm::Module* 
M);
+std::unique_ptr getObject(const llvm::Module* M) 
override;
 
 private:
 std::string mCpu;

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Mesa (master): swr/rast: Rectlist support for GS

[George Kyriazis]

Module: Mesa
Branch: master
Commit: a0dddac1cb88b1d518d9875cec2e8133ec6cddfc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0dddac1cb88b1d518d9875cec2e8133ec6cddfc

Author: Alok Hota 
Date:   Wed May 16 11:14:18 2018 -0500

swr/rast: Rectlist support for GS

Add rectlist as an option for GS.  Needed to support some driver
optimizations.

Reviewed-By: George Kyriazis 

---

 src/gallium/drivers/swr/rasterizer/core/clip.cpp   | 24 
 src/gallium/drivers/swr/rasterizer/core/clip.h |  6 ++
 .../drivers/swr/rasterizer/core/frontend.cpp   |  2 +
 src/gallium/drivers/swr/rasterizer/core/pa.h   | 68 ++
 .../drivers/swr/rasterizer/core/rdtsc_core.h   |  1 +
 src/gallium/drivers/swr/rasterizer/core/state.h|  2 +-
 6 files changed, 102 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.cpp 
b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
index 780ca15ce7..e6c2218068 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.cpp
@@ -160,6 +160,15 @@ int ClipTriToPlane( const float *pInPts, int numInPts,
 return i;
 }
 
+void ClipRectangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask,
+simdscalari const &primId, simdscalari const &viewportIdx, simdscalari 
const &rtIdx)
+{
+RDTSC_BEGIN(FEClipRectangles, pDC->drawId);
+Clipper clipper(workerId, pDC);
+clipper.ExecuteStage(pa, prims, primMask, primId, viewportIdx, rtIdx);
+RDTSC_END(FEClipRectangles, 1);
+}
+
 void ClipTriangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask,
simdscalari const &primId, simdscalari const &viewportIdx, 
simdscalari const &rtIdx)
 {
@@ -188,6 +197,21 @@ void ClipPoints(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simdvector p
 }
 
 #if USE_SIMD16_FRONTEND
+void SIMDCALL ClipRectangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask,
+simd16scalari const &primId, simd16scalari const &viewportIdx, 
simd16scalari const &rtIdx)
+{
+RDTSC_BEGIN(FEClipRectangles, pDC->drawId);
+
+enum { VERTS_PER_PRIM = 3 };
+
+Clipper clipper(workerId, pDC);
+
+pa.useAlternateOffset = false;
+clipper.ExecuteStage(pa, prims, primMask, primId, viewportIdx, rtIdx);
+
+RDTSC_END(FEClipRectangles, 1);
+}
+
 void SIMDCALL ClipTriangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask,
simd16scalari const &primId, simd16scalari 
const &viewportIdx, simd16scalari const &rtIdx)
 {
diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index 0f8399c742..90ae426357 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -531,6 +531,10 @@ public:
 {
 clipTopology = TOP_POINT_LIST;
 }
+else if (pa.binTopology == TOP_RECT_LIST)
+{
+clipTopology = TOP_RECT_LIST;
+}
 }
 else if (NumVertsPerPrim == 2)
 {
@@ -1149,10 +1153,12 @@ private:
 
 
 // pipeline stage functions
+void ClipRectangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask, simdscalari const &primId, simdscalari 
const &viewportIdx, simdscalari const &rtIdx);
 void ClipTriangles(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, 
simdvector prims[], uint32_t primMask, simdscalari const &primId, simdscalari 
const &viewportIdx, simdscalari const &rtIdx);
 void ClipLines(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, simdvector 
prims[], uint32_t primMask, simdscalari const &primId, simdscalari const 
&viewportIdx, simdscalari const &rtIdx);
 void ClipPoints(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t workerId, simdvector 
prims[], uint32_t primMask, simdscalari const &primId, simdscalari const 
&viewportIdx, simdscalari const &rtIdx);
 #if USE_SIMD16_FRONTEND
+void SIMDCALL ClipRectangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const &primId, 
simd16scalari const &viewportIdx, simd16scalari const &rtIdx);
 void SIMDCALL ClipTriangles_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const &primId, 
simd16scalari const &viewportIdx, simd16scalari const &rtIdx);
 void SIMDCALL ClipLines_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const &primId, 
simd16scalari const &viewportIdx, simd16scalari const &rtIdx);
 void SIMDCALL ClipPoints_simd16(DRAW_CONTEXT *pDC, PA_STATE& pa, uint32_t 
workerId, simd16vector prims[], uint32_t primMask, simd16scalari const &primId, 
simd16scalari const &vi

Mesa (master): broadcom/vc4: Drop libdrm_vc4 requirement

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 1ec01a911b7b4dc63c47fb16288b6d9962aeb60f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ec01a911b7b4dc63c47fb16288b6d9962aeb60f

Author: Stefan Schake 
Date:   Wed Apr 25 00:00:55 2018 +0200

broadcom/vc4: Drop libdrm_vc4 requirement

This was missed in the move back to the local uapi copy.
libdrm_vc4 only seems to consist of headers that also exist in the
Mesa tree.

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 configure.ac | 1 -
 1 file changed, 1 deletion(-)

diff --git a/configure.ac b/configure.ac
index 30980151ee..681696e789 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2727,7 +2727,6 @@ if test -n "$with_gallium_drivers"; then
 ;;
 xvc4)
 HAVE_GALLIUM_VC4=yes
-require_libdrm "vc4"
 
 PKG_CHECK_MODULES([SIMPENROSE], [simpenrose],
   [USE_VC4_SIMULATOR=yes;

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Mesa (master): broadcom/vc4: Native fence fd support

[Eric Anholt]

Module: Mesa
Branch: master
Commit: b0acc3a5628c6c6dd669cbb7cff2d974b175605e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0acc3a5628c6c6dd669cbb7cff2d974b175605e

Author: Stefan Schake 
Date:   Wed Apr 25 00:01:00 2018 +0200

broadcom/vc4: Native fence fd support

With the syncobj support in place, lets use it to implement the
EGL_ANDROID_native_fence_sync extension. This mostly follows previous
implementations in freedreno and etnaviv.

v2: Drop the flags (Eric)
Handle in_fence_fd already in job_submit (Eric)
Drop extra vc4_fence_context_init (Eric)
Dup fds with CLOEXEC (Eric)
Mention exact extension name (Eric)

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 src/gallium/drivers/vc4/vc4_context.c | 21 ++-
 src/gallium/drivers/vc4/vc4_context.h |  5 +++
 src/gallium/drivers/vc4/vc4_fence.c   | 70 +--
 src/gallium/drivers/vc4/vc4_job.c | 12 +-
 src/gallium/drivers/vc4/vc4_screen.c  |  6 ++-
 src/gallium/drivers/vc4/vc4_screen.h  |  4 +-
 6 files changed, 107 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_context.c 
b/src/gallium/drivers/vc4/vc4_context.c
index 0deb3ef85e..9ff39c2655 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -59,8 +59,17 @@ vc4_pipe_flush(struct pipe_context *pctx, struct 
pipe_fence_handle **fence,
 
 if (fence) {
 struct pipe_screen *screen = pctx->screen;
+int fd = -1;
+
+if (flags & PIPE_FLUSH_FENCE_FD) {
+/* The vc4_fence takes ownership of the returned fd. */
+drmSyncobjExportSyncFile(vc4->fd, vc4->job_syncobj,
+ &fd);
+}
+
 struct vc4_fence *f = vc4_fence_create(vc4->screen,
-   vc4->last_emit_seqno);
+   vc4->last_emit_seqno,
+   fd);
 screen->fence_reference(screen, fence, NULL);
 *fence = (struct pipe_fence_handle *)f;
 }
@@ -124,8 +133,12 @@ vc4_context_destroy(struct pipe_context *pctx)
 
 vc4_program_fini(pctx);
 
-if (vc4->screen->has_syncobj)
+if (vc4->screen->has_syncobj) {
 drmSyncobjDestroy(vc4->fd, vc4->job_syncobj);
+drmSyncobjDestroy(vc4->fd, vc4->in_syncobj);
+}
+if (vc4->in_fence_fd >= 0)
+close(vc4->in_fence_fd);
 
 ralloc_free(vc4);
 }
@@ -167,6 +180,10 @@ vc4_context_create(struct pipe_screen *pscreen, void 
*priv, unsigned flags)
 if (err)
 goto fail;
 
+err = vc4_fence_context_init(vc4);
+if (err)
+goto fail;
+
 slab_create_child(&vc4->transfer_pool, &screen->transfer_pool);
 
vc4->uploader = u_upload_create_default(&vc4->base);
diff --git a/src/gallium/drivers/vc4/vc4_context.h 
b/src/gallium/drivers/vc4/vc4_context.h
index d094957bb5..ce8bcffac0 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -411,6 +411,10 @@ struct vc4_context {
 
 /** Handle of syncobj containing the last submitted job fence. */
 uint32_t job_syncobj;
+
+int in_fence_fd;
+/** Handle of the syncobj that holds in_fence_fd for submission. */
+uint32_t in_syncobj;
 };
 
 struct vc4_rasterizer_state {
@@ -506,6 +510,7 @@ void vc4_write_uniforms(struct vc4_context *vc4,
 
 void vc4_flush(struct pipe_context *pctx);
 int vc4_job_init(struct vc4_context *vc4);
+int vc4_fence_context_init(struct vc4_context *vc4);
 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 struct pipe_surface *cbuf,
 struct pipe_surface *zsbuf);
diff --git a/src/gallium/drivers/vc4/vc4_fence.c 
b/src/gallium/drivers/vc4/vc4_fence.c
index f61e7c6a5e..7071425595 100644
--- a/src/gallium/drivers/vc4/vc4_fence.c
+++ b/src/gallium/drivers/vc4/vc4_fence.c
@@ -34,26 +34,39 @@
  * fired off as our fence marker.
  */
 
+#include 
+#include 
+
 #include "util/u_inlines.h"
 
 #include "vc4_screen.h"
+#include "vc4_context.h"
 #include "vc4_bufmgr.h"
 
 struct vc4_fence {
 struct pipe_reference reference;
 uint64_t seqno;
+int fd;
 };
 
+static inline struct vc4_fence *
+vc4_fence(struct pipe_fence_handle *pfence)
+{
+return (struct vc4_fence *)pfence;
+}
+
 static void
 vc4_fence_reference(struct pipe_screen *pscreen,
 struct pipe_fence_handle **pp,
 struct pipe_fence_handle *pf)
 {
 struct vc4_fence **p = (struct vc4_fence **)pp;
-struct vc4_fence *f = (struct vc4_fence *)pf;
+struct vc4_fence *f = vc4_fence(pf);
 struct vc4_fence *old = *p;
 
 if (pipe_reference(&(*p)-

Mesa (master): drm-uapi: Update vc4 header with syncobj submit support

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 580d1f4c607bc6cd5bf24f9d303a502d6d9dcaec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=580d1f4c607bc6cd5bf24f9d303a502d6d9dcaec

Author: Stefan Schake 
Date:   Wed Apr 25 00:00:56 2018 +0200

drm-uapi: Update vc4 header with syncobj submit support

v2: Synchronized with kernel v2
v3: Update for the finalized kernel ABI (pad2 field)

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 include/drm-uapi/vc4_drm.h | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/include/drm-uapi/vc4_drm.h b/include/drm-uapi/vc4_drm.h
index 4117117b42..31f50de39a 100644
--- a/include/drm-uapi/vc4_drm.h
+++ b/include/drm-uapi/vc4_drm.h
@@ -183,10 +183,17 @@ struct drm_vc4_submit_cl {
/* ID of the perfmon to attach to this job. 0 means no perfmon. */
__u32 perfmonid;
 
-   /* Unused field to align this struct on 64 bits. Must be set to 0.
-* If one ever needs to add an u32 field to this struct, this field
-* can be used.
+   /* Syncobj handle to wait on. If set, processing of this render job
+* will not start until the syncobj is signaled. 0 means ignore.
 */
+   __u32 in_sync;
+
+   /* Syncobj handle to export fence to. If set, the fence in the syncobj
+* will be replaced with a fence that signals upon completion of this
+* render job. 0 means ignore.
+*/
+   __u32 out_sync;
+
__u32 pad2;
 };
 

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Mesa (master): broadcom/vc4: Store job fence in syncobj

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 44036c354d800dda08d3688b042130039f3d592a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44036c354d800dda08d3688b042130039f3d592a

Author: Stefan Schake 
Date:   Wed Apr 25 00:00:59 2018 +0200

broadcom/vc4: Store job fence in syncobj

This gives us access to the fence created for the render job.

v2: Drop flag (Eric)

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 src/gallium/drivers/vc4/vc4_context.c | 10 --
 src/gallium/drivers/vc4/vc4_context.h |  5 -
 src/gallium/drivers/vc4/vc4_job.c | 24 +++-
 3 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_context.c 
b/src/gallium/drivers/vc4/vc4_context.c
index c1e041d1ef..0deb3ef85e 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -124,6 +124,9 @@ vc4_context_destroy(struct pipe_context *pctx)
 
 vc4_program_fini(pctx);
 
+if (vc4->screen->has_syncobj)
+drmSyncobjDestroy(vc4->fd, vc4->job_syncobj);
+
 ralloc_free(vc4);
 }
 
@@ -132,6 +135,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv, 
unsigned flags)
 {
 struct vc4_screen *screen = vc4_screen(pscreen);
 struct vc4_context *vc4;
+int err;
 
 /* Prevent dumping of the shaders built during context setup. */
 uint32_t saved_shaderdb_flag = vc4_debug & VC4_DEBUG_SHADERDB;
@@ -157,10 +161,12 @@ vc4_context_create(struct pipe_screen *pscreen, void 
*priv, unsigned flags)
 vc4_query_init(pctx);
 vc4_resource_context_init(pctx);
 
-vc4_job_init(vc4);
-
 vc4->fd = screen->fd;
 
+err = vc4_job_init(vc4);
+if (err)
+goto fail;
+
 slab_create_child(&vc4->transfer_pool, &screen->transfer_pool);
 
vc4->uploader = u_upload_create_default(&vc4->base);
diff --git a/src/gallium/drivers/vc4/vc4_context.h 
b/src/gallium/drivers/vc4/vc4_context.h
index 16bebeec40..d094957bb5 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -408,6 +408,9 @@ struct vc4_context {
 
 struct vc4_hwperfmon *perfmon;
 /** @} */
+
+/** Handle of syncobj containing the last submitted job fence. */
+uint32_t job_syncobj;
 };
 
 struct vc4_rasterizer_state {
@@ -502,7 +505,7 @@ void vc4_write_uniforms(struct vc4_context *vc4,
 struct vc4_texture_stateobj *texstate);
 
 void vc4_flush(struct pipe_context *pctx);
-void vc4_job_init(struct vc4_context *vc4);
+int vc4_job_init(struct vc4_context *vc4);
 struct vc4_job *vc4_get_job(struct vc4_context *vc4,
 struct pipe_surface *cbuf,
 struct pipe_surface *zsbuf);
diff --git a/src/gallium/drivers/vc4/vc4_job.c 
b/src/gallium/drivers/vc4/vc4_job.c
index 41c274ca1b..3b0ba8b69c 100644
--- a/src/gallium/drivers/vc4/vc4_job.c
+++ b/src/gallium/drivers/vc4/vc4_job.c
@@ -477,6 +477,9 @@ vc4_job_submit(struct vc4_context *vc4, struct vc4_job *job)
 }
 submit.flags |= job->flags;
 
+if (vc4->screen->has_syncobj)
+submit.out_sync = vc4->job_syncobj;
+
 if (!(vc4_debug & VC4_DEBUG_NORAST)) {
 int ret;
 
@@ -530,7 +533,7 @@ vc4_job_hash(const void *key)
 return _mesa_hash_data(key, sizeof(struct vc4_job_key));
 }
 
-void
+int
 vc4_job_init(struct vc4_context *vc4)
 {
 vc4->jobs = _mesa_hash_table_create(vc4,
@@ -539,5 +542,24 @@ vc4_job_init(struct vc4_context *vc4)
 vc4->write_jobs = _mesa_hash_table_create(vc4,
   _mesa_hash_pointer,
   _mesa_key_pointer_equal);
+
+if (vc4->screen->has_syncobj) {
+/* Create the syncobj as signaled since with no job executed
+ * there is nothing to wait on.
+ */
+int ret = drmSyncobjCreate(vc4->fd,
+   DRM_SYNCOBJ_CREATE_SIGNALED,
+   &vc4->job_syncobj);
+if (ret) {
+/* If the screen indicated syncobj support, we should
+ * be able to create a signaled syncobj.
+ * At this point it is too late to pretend the screen
+ * has no syncobj support.
+ */
+return ret;
+}
+}
+
+return 0;
 }
 

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Mesa (master): broadcom/vc4: Bump libdrm requirement

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 4fc0ebdff55419965919e4d6bf3c7f7f2759f7aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fc0ebdff55419965919e4d6bf3c7f7f2759f7aa

Author: Stefan Schake 
Date:   Wed Apr 25 00:00:57 2018 +0200

broadcom/vc4: Bump libdrm requirement

Require a version of libdrm with syncobj support.

v2: Don't require a libdrm_vc4, just bump core libdrm if vc4 enabled (by
anholt)

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 configure.ac | 2 ++
 meson.build  | 6 ++
 2 files changed, 8 insertions(+)

diff --git a/configure.ac b/configure.ac
index 681696e789..401025bf2e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -80,6 +80,7 @@ LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
 LIBDRM_FREEDRENO_REQUIRED=2.4.92
 LIBDRM_ETNAVIV_REQUIRED=2.4.89
+LIBDRM_VC4_REQUIRED=2.4.89
 
 dnl Versions for external dependencies
 DRI2PROTO_REQUIRED=2.8
@@ -2727,6 +2728,7 @@ if test -n "$with_gallium_drivers"; then
 ;;
 xvc4)
 HAVE_GALLIUM_VC4=yes
+PKG_CHECK_MODULES([VC4], [libdrm >= $LIBDRM_VC4_REQUIRED])
 
 PKG_CHECK_MODULES([SIMPENROSE], [simpenrose],
   [USE_VC4_SIMULATOR=yes;
diff --git a/meson.build b/meson.build
index b8ebda9cdc..0f88ddfe8e 100644
--- a/meson.build
+++ b/meson.build
@@ -1055,6 +1055,12 @@ _libdrm_checks = [
   ['freedreno', with_gallium_freedreno],
 ]
 
+# VC4 only needs core libdrm support of this version, not a libdrm_vc4
+# library.
+if with_gallium_vc4
+  _drm_ver = '2.4.89'
+endif
+
 # Loop over the enables versions and get the highest libdrm requirement for all
 # active drivers.
 foreach d : _libdrm_checks

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Mesa (master): broadcom/vc4: Detect syncobj support

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 9ed05e2520f77a11f73d21bccfe149b2b800082c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ed05e2520f77a11f73d21bccfe149b2b800082c

Author: Stefan Schake 
Date:   Wed Apr 25 00:00:58 2018 +0200

broadcom/vc4: Detect syncobj support

We need to know if the kernel supports syncobj submission since otherwise
all the DRM syncobj calls fail.

v2: Use drmGetCap to detect syncobj support (Eric)

Signed-off-by: Stefan Schake 
Reviewed-by: Eric Anholt 

---

 src/gallium/drivers/vc4/vc4_screen.c | 6 ++
 src/gallium/drivers/vc4/vc4_screen.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_screen.c 
b/src/gallium/drivers/vc4/vc4_screen.c
index 81c8049325..5476b8cf10 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -659,7 +659,9 @@ struct pipe_screen *
 vc4_screen_create(int fd, struct renderonly *ro)
 {
 struct vc4_screen *screen = rzalloc(NULL, struct vc4_screen);
+uint64_t syncobj_cap = 0;
 struct pipe_screen *pscreen;
+int err;
 
 pscreen = &screen->base;
 
@@ -695,6 +697,10 @@ vc4_screen_create(int fd, struct renderonly *ro)
 screen->has_perfmon_ioctl =
 vc4_has_feature(screen, DRM_VC4_PARAM_SUPPORTS_PERFMON);
 
+err = drmGetCap(fd, DRM_CAP_SYNCOBJ, &syncobj_cap);
+if (err == 0 && syncobj_cap)
+screen->has_syncobj = true;
+
 if (!vc4_get_chip_info(screen))
 goto fail;
 
diff --git a/src/gallium/drivers/vc4/vc4_screen.h 
b/src/gallium/drivers/vc4/vc4_screen.h
index 0b884423ba..438e90a1a2 100644
--- a/src/gallium/drivers/vc4/vc4_screen.h
+++ b/src/gallium/drivers/vc4/vc4_screen.h
@@ -98,6 +98,7 @@ struct vc4_screen {
 bool has_madvise;
 bool has_tiling_ioctl;
 bool has_perfmon_ioctl;
+bool has_syncobj;
 
 struct vc4_simulator_file *sim_file;
 };

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Mesa (master): v3d: Add support for glSampleMask / glSampleCoverage.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 97894b1267923dee25ea5263e547ac8822ef7095
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97894b1267923dee25ea5263e547ac8822ef7095

Author: Eric Anholt 
Date:   Tue May  8 14:28:33 2018 -0700

v3d: Add support for glSampleMask / glSampleCoverage.

---

 src/broadcom/cle/v3d_packet_v41.xml|  5 +
 src/broadcom/cle/v3d_packet_v42.xml|  5 +
 src/gallium/drivers/v3d/v3d_context.h  |  2 +-
 src/gallium/drivers/v3d/v3d_program.c  |  2 +-
 src/gallium/drivers/v3d/v3d_uniforms.c |  2 +-
 src/gallium/drivers/v3d/v3dx_emit.c| 23 ++-
 src/gallium/drivers/v3d/v3dx_state.c   |  2 +-
 7 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/src/broadcom/cle/v3d_packet_v41.xml 
b/src/broadcom/cle/v3d_packet_v41.xml
index 1fb5d5d284..c516561407 100644
--- a/src/broadcom/cle/v3d_packet_v41.xml
+++ b/src/broadcom/cle/v3d_packet_v41.xml
@@ -475,6 +475,11 @@
 
   
 
+  
+ 
+
+  
+
   
 
   
diff --git a/src/broadcom/cle/v3d_packet_v42.xml 
b/src/broadcom/cle/v3d_packet_v42.xml
index a562d662ff..fb4425968c 100644
--- a/src/broadcom/cle/v3d_packet_v42.xml
+++ b/src/broadcom/cle/v3d_packet_v42.xml
@@ -476,6 +476,11 @@
 
   
 
+  
+ 
+
+  
+
   
 
   
diff --git a/src/gallium/drivers/v3d/v3d_context.h 
b/src/gallium/drivers/v3d/v3d_context.h
index d110ed5022..47945f9649 100644
--- a/src/gallium/drivers/v3d/v3d_context.h
+++ b/src/gallium/drivers/v3d/v3d_context.h
@@ -61,7 +61,7 @@ void v3d_job_add_bo(struct v3d_job *job, struct v3d_bo *bo);
 
 #define VC5_DIRTY_BLEND_COLOR   (1 <<  7)
 #define VC5_DIRTY_STENCIL_REF   (1 <<  8)
-#define VC5_DIRTY_SAMPLE_MASK   (1 <<  9)
+#define VC5_DIRTY_SAMPLE_STATE  (1 <<  9)
 #define VC5_DIRTY_FRAMEBUFFER   (1 << 10)
 #define VC5_DIRTY_STIPPLE   (1 << 11)
 #define VC5_DIRTY_VIEWPORT  (1 << 12)
diff --git a/src/gallium/drivers/v3d/v3d_program.c 
b/src/gallium/drivers/v3d/v3d_program.c
index 63e6fda547..036f7c6e67 100644
--- a/src/gallium/drivers/v3d/v3d_program.c
+++ b/src/gallium/drivers/v3d/v3d_program.c
@@ -399,7 +399,7 @@ v3d_update_compiled_fs(struct v3d_context *v3d, uint8_t 
prim_mode)
 VC5_DIRTY_FRAMEBUFFER |
 VC5_DIRTY_ZSA |
 VC5_DIRTY_RASTERIZER |
-VC5_DIRTY_SAMPLE_MASK |
+VC5_DIRTY_SAMPLE_STATE |
 VC5_DIRTY_FRAGTEX |
 VC5_DIRTY_UNCOMPILED_FS))) {
 return;
diff --git a/src/gallium/drivers/v3d/v3d_uniforms.c 
b/src/gallium/drivers/v3d/v3d_uniforms.c
index 9dd128ab41..ad46c69121 100644
--- a/src/gallium/drivers/v3d/v3d_uniforms.c
+++ b/src/gallium/drivers/v3d/v3d_uniforms.c
@@ -475,7 +475,7 @@ v3d_set_shader_uniform_dirty_flags(struct 
v3d_compiled_shader *shader)
 break;
 
 case QUNIFORM_SAMPLE_MASK:
-dirty |= VC5_DIRTY_SAMPLE_MASK;
+dirty |= VC5_DIRTY_SAMPLE_STATE;
 break;
 
 default:
diff --git a/src/gallium/drivers/v3d/v3dx_emit.c 
b/src/gallium/drivers/v3d/v3dx_emit.c
index 8a65478a16..161ce51b2f 100644
--- a/src/gallium/drivers/v3d/v3dx_emit.c
+++ b/src/gallium/drivers/v3d/v3dx_emit.c
@@ -387,8 +387,17 @@ v3dX(emit_state)(struct pipe_context *pctx)
 config.enable_depth_offset =
 v3d->rasterizer->base.offset_tri;
 
+/* V3D follows GL behavior where the sample mask only
+ * applies when MSAA is enabled.  Gallium has sample
+ * mask apply anyway, and the MSAA blit shaders will
+ * set sample mask without explicitly setting
+ * rasterizer oversample.  Just force it on here,
+ * since the blit shaders are the only way to have
+ * !multisample && samplemask != 0xf.
+ */
 config.rasterizer_oversample_mode =
-v3d->rasterizer->base.multisample;
+v3d->rasterizer->base.multisample ||
+v3d->sample_mask != 0xf;
 
 config.direct3d_provoking_vertex =
 v3d->rasterizer->base.flatshade_first;
@@ -719,4 +728,16 @@ v3dX(emit_state)(struct pipe_context *pctx)
 }
 }
 }
+
+#if V3D_VERSION >= 40
+if (v3d->dirty & VC5_DIRTY_SAMPLE_STATE) {
+cl_emit(&job->bcl, SAMPLE_STATE, state) {
+/* Note: SampleCoverage was handled at the
+ * state_tracker level by converting to sample_mask.
+ */
+state.coverage = fui(1.0) >> 16;
+state.mask = job->msaa

Mesa (master): v3d: Enable NaN propagation in the VS and CS as well.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 9bbc3f8cf1f116aa17ebcd399c0d3a8fb07b5266
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bbc3f8cf1f116aa17ebcd399c0d3a8fb07b5266

Author: Eric Anholt 
Date:   Tue May  8 13:22:57 2018 -0700

v3d: Enable NaN propagation in the VS and CS as well.

Fixes piglit vs-isnan-*.shader_test at the expense of gl-1.0-spot-light.

---

 src/broadcom/cle/v3d_packet_v33.xml | 4 +++-
 src/broadcom/cle/v3d_packet_v41.xml | 4 +++-
 src/broadcom/cle/v3d_packet_v42.xml | 4 +++-
 src/gallium/drivers/v3d/v3dx_draw.c | 4 +++-
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/broadcom/cle/v3d_packet_v33.xml 
b/src/broadcom/cle/v3d_packet_v33.xml
index aac9fbfd28..22d43cc802 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -702,15 +702,17 @@
 
 
 
-
+
 
 
 
 
+
 
 
 
 
+
 
   
 
diff --git a/src/broadcom/cle/v3d_packet_v41.xml 
b/src/broadcom/cle/v3d_packet_v41.xml
index 5f6d643195..1fb5d5d284 100644
--- a/src/broadcom/cle/v3d_packet_v41.xml
+++ b/src/broadcom/cle/v3d_packet_v41.xml
@@ -781,17 +781,19 @@
 
 
 
-
+
 
 
 
 
 
+
 
 
 
 
 
+
 
   
 
diff --git a/src/broadcom/cle/v3d_packet_v42.xml 
b/src/broadcom/cle/v3d_packet_v42.xml
index f180e5eec5..a562d662ff 100644
--- a/src/broadcom/cle/v3d_packet_v42.xml
+++ b/src/broadcom/cle/v3d_packet_v42.xml
@@ -782,17 +782,19 @@
 
 
 
-
+
 
 
 
 
 
+
 
 
 
 
 
+
 
   
 
diff --git a/src/gallium/drivers/v3d/v3dx_draw.c 
b/src/gallium/drivers/v3d/v3dx_draw.c
index 28b35165c7..4d872b30ec 100644
--- a/src/gallium/drivers/v3d/v3dx_draw.c
+++ b/src/gallium/drivers/v3d/v3dx_draw.c
@@ -183,7 +183,9 @@ v3d_emit_gl_shader_state(struct v3d_context *v3d,
 shader.number_of_varyings_in_fragment_shader =
 v3d->prog.fs->prog_data.base->num_inputs;
 
-shader.propagate_nans = true;
+shader.coordinate_shader_propagate_nans = true;
+shader.vertex_shader_propagate_nans = true;
+shader.fragment_shader_propagate_nans = true;
 
 shader.coordinate_shader_code_address =
 cl_address(v3d->prog.cs->bo, 0);

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Mesa (master): i965/clear: Drop a stale comment in fast_clear_depth

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 43616404be311e787f043f49d0a8341ef54459cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43616404be311e787f043f49d0a8341ef54459cb

Author: Nanley Chery 
Date:   Sun Apr  8 14:00:30 2018 -0700

i965/clear: Drop a stale comment in fast_clear_depth

This comment made more sense when it was above the calls to
intel_miptree_slice_set_needs_depth_resolve(). We stopped using these
functions at commit 554f7d6d02931ea45653c8872565d21c1678a6da
("i965: Move depth to the new resolve functions").

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_clear.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index a65839a0a0..24c8b24244 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -228,13 +228,9 @@ brw_fast_clear_depth(struct gl_context *ctx)
   }
}
 
-   /* Now, the HiZ buffer contains data that needs to be resolved to the depth
-* buffer.
-*/
intel_miptree_set_aux_state(brw, mt, depth_irb->mt_level,
depth_irb->mt_layer, num_layers,
ISL_AUX_STATE_CLEAR);
-
return true;
 }
 

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Mesa (master): i965/blorp: Also skip the fast clear if the clear color differs

[Nanley Chery]

Module: Mesa
Branch: master
Commit: f8ac11d69f1a05378896023577d6455764b5cdf2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f8ac11d69f1a05378896023577d6455764b5cdf2

Author: Nanley Chery 
Date:   Tue Mar 27 15:08:53 2018 -0700

i965/blorp: Also skip the fast clear if the clear color differs

If the aux state is CLEAR and clear color value has changed, only the
surface state must be updated. The bit-pattern in the aux buffer is
exactly the same.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 04155b7d4c..9d57745cc5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1229,13 +1229,12 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
  brw_meta_convert_fast_clear_color(brw, irb->mt,
&ctx->Color.ClearColor);
 
-  bool same_clear_color =
- !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
+  intel_miptree_set_clear_color(brw, irb->mt, clear_color);
 
-  /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
+  /* If the buffer is already in ISL_AUX_STATE_CLEAR, the clear
* is redundant and can be skipped.
*/
-  if (aux_state == ISL_AUX_STATE_CLEAR && same_clear_color)
+  if (aux_state == ISL_AUX_STATE_CLEAR)
  return;
 
   DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,

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Mesa (master): i965: Prepare to delete intel_miptree_alloc_ccs()

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 6c41a2ef3b72f9465646fea7ac941e8deb1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c41a2ef3b72f9465646fea7ac941e8deb1b

Author: Nanley Chery 
Date:   Wed May  2 20:05:08 2018 -0700

i965: Prepare to delete intel_miptree_alloc_ccs()

We're going to delete intel_miptree_alloc_ccs() in the next commit. With
that in mind, replace the use of this function in
do_single_blorp_clear() with intel_miptree_alloc_aux() and move the
delayed allocation logic to it's callers.

v2: Duplicate the delayed allocation comment (Topi Pohjolainen).

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c |  2 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 27 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  2 +-
 3 files changed, 16 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index f538cd03bc..2ea13bb743 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1208,7 +1208,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 */
if (can_fast_clear && !irb->mt->aux_buf) {
   assert(irb->mt->aux_usage == ISL_AUX_USAGE_CCS_D);
-  if (!intel_miptree_alloc_ccs(brw, irb->mt)) {
+  if (!intel_miptree_alloc_aux(brw, irb->mt)) {
  /* There are a few reasons in addition to out-of-memory, that can
   * cause intel_miptree_alloc_non_msrt_mcs to fail.  Try to recover by
   * falling back to non-fast clear.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ccde5beb3c..a1834fe911 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -60,10 +60,6 @@ static void *intel_miptree_map_raw(struct brw_context *brw,
 static void intel_miptree_unmap_raw(struct intel_mipmap_tree *mt);
 
 static bool
-intel_miptree_alloc_aux(struct brw_context *brw,
-struct intel_mipmap_tree *mt);
-
-static bool
 intel_miptree_supports_mcs(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
 {
@@ -791,7 +787,12 @@ intel_miptree_create(struct brw_context *brw,
 
mt->offset = 0;
 
-   if (!intel_miptree_alloc_aux(brw, mt)) {
+   /* Create the auxiliary surface up-front. CCS_D, on the other hand, can only
+* compress clear color so we wait until an actual fast-clear to allocate
+* it.
+*/
+   if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+   !intel_miptree_alloc_aux(brw, mt)) {
   intel_miptree_release(&mt);
   return NULL;
}
@@ -882,7 +883,12 @@ intel_miptree_create_for_bo(struct brw_context *brw,
if (!(flags & MIPTREE_CREATE_NO_AUX)) {
   intel_miptree_choose_aux_usage(brw, mt);
 
-  if (!intel_miptree_alloc_aux(brw, mt)) {
+  /* Create the auxiliary surface up-front. CCS_D, on the other hand, can
+   * only compress clear color so we wait until an actual fast-clear to
+   * allocate it.
+   */
+  if (mt->aux_usage != ISL_AUX_USAGE_CCS_D &&
+  !intel_miptree_alloc_aux(brw, mt)) {
  intel_miptree_release(&mt);
  return NULL;
   }
@@ -1776,7 +1782,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
return true;
 }
 
-bool
+static bool
 intel_miptree_alloc_ccs(struct brw_context *brw,
 struct intel_mipmap_tree *mt)
 {
@@ -1897,7 +1903,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
  * create the auxiliary surfaces up-front.  CCS_D, on the other hand, can only
  * compress clear color so we wait until an actual fast-clear to allocate it.
  */
-static bool
+bool
 intel_miptree_alloc_aux(struct brw_context *brw,
 struct intel_mipmap_tree *mt)
 {
@@ -1919,11 +1925,6 @@ intel_miptree_alloc_aux(struct brw_context *brw,
   return true;
 
case ISL_AUX_USAGE_CCS_D:
-  /* Since CCS_D can only compress clear color so we wait until an actual
-   * fast-clear to allocate it.
-   */
-  return true;
-
case ISL_AUX_USAGE_CCS_E:
   assert(_mesa_is_format_color_format(mt->format));
   assert(mt->surf.samples == 1);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 9adcc5ab0c..aa360fcb35 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -354,7 +354,7 @@ struct intel_mipmap_tree
 };
 
 bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
+intel_miptree_alloc_aux(struct brw_context *brw,
 struct intel_mipmap_tree *mt);
 
 enum intel_miptree_create_flags {

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Mesa (master): i965/miptree: Add and use a memset option in alloc_aux_buffer

[Nanley Chery]

Module: Mesa
Branch: master
Commit: b58675e93f03eee46de63bb596d4b97561fdaf42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b58675e93f03eee46de63bb596d4b97561fdaf42

Author: Nanley Chery 
Date:   Mon Apr 30 10:44:01 2018 -0700

i965/miptree: Add and use a memset option in alloc_aux_buffer

Add infrastructure for initializing the clear color BO.
intel_miptree_init_mcs is no longer needed with change.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68 ---
 1 file changed, 31 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c01a71d445..d132b20abe 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1655,41 +1655,13 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
 }
 
-static bool
-intel_miptree_init_mcs(struct brw_context *brw,
-   struct intel_mipmap_tree *mt,
-   int init_value)
-{
-   assert(mt->aux_buf != NULL);
-
-   /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
-*
-* When MCS buffer is enabled and bound to MSRT, it is required that it
-* is cleared prior to any rendering.
-*
-* Since we don't use the MCS buffer for any purpose other than rendering,
-* it makes sense to just clear it immediately upon allocation.
-*
-* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
-*/
-   void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
-   if (unlikely(map == NULL)) {
-  fprintf(stderr, "Failed to map mcs buffer into GTT\n");
-  intel_miptree_aux_buffer_free(mt->aux_buf);
-  mt->aux_buf = NULL;
-  return false;
-   }
-   void *data = map;
-   memset(data, init_value, mt->aux_buf->surf.size);
-   brw_bo_unmap(mt->aux_buf->bo);
-   return true;
-}
-
 static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
const char *name,
const struct isl_surf *aux_surf,
uint32_t alloc_flags,
+   bool wants_memset,
+   uint8_t memset_value,
struct intel_mipmap_tree *mt)
 {
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
@@ -1720,6 +1692,19 @@ intel_alloc_aux_buffer(struct brw_context *brw,
   return NULL;
}
 
+   /* Initialize the bo to the desired value */
+   if (wants_memset) {
+  assert(!(alloc_flags & BO_ALLOC_BUSY));
+
+  void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
+  if (map == NULL) {
+ intel_miptree_aux_buffer_free(buf);
+ return NULL;
+  }
+  memset(map, memset_value, aux_surf->size);
+  brw_bo_unmap(buf->bo);
+   }
+
if (devinfo->gen >= 10) {
   buf->clear_color_bo = buf->bo;
   brw_bo_reference(buf->clear_color_bo);
@@ -1758,10 +1743,19 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 * to be just used by the GPU.
 */
const uint32_t alloc_flags = 0;
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
-&temp_mcs_surf, alloc_flags, mt);
-   if (!mt->aux_buf ||
-   !intel_miptree_init_mcs(brw, mt, 0xFF)) {
+   /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
+*
+* When MCS buffer is enabled and bound to MSRT, it is required that it
+* is cleared prior to any rendering.
+*
+* Since we don't use the MCS buffer for any purpose other than rendering,
+* it makes sense to just clear it immediately upon allocation.
+*
+* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
+*/
+   mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree", &temp_mcs_surf,
+alloc_flags, true, 0xFF, mt);
+   if (!mt->aux_buf) {
   free(aux_state);
   return false;
}
@@ -1805,7 +1799,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * bits in the aux buffer.
 */
mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
-BO_ALLOC_ZEROED, mt);
+BO_ALLOC_ZEROED, false, 0, mt);
if (!mt->aux_buf) {
   free(aux_state);
   return false;
@@ -1871,8 +1865,8 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(ok);
 
const uint32_t alloc_flags = BO_ALLOC_BUSY;
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree",
-&temp_hiz_surf, alloc_flags, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", &temp_hiz_surf,
+alloc_flags, false, 0, mt);
 
if (!mt->aux_buf) {
   free(aux_state);

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Mesa (master): i965/clear: Remove an early return in fast_clear_depth

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 5b315f3ad1451b7c24e29f534cd1c7ed0de0fa77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b315f3ad1451b7c24e29f534cd1c7ed0de0fa77

Author: Nanley Chery 
Date:   Tue Apr 24 17:16:50 2018 -0700

i965/clear: Remove an early return in fast_clear_depth

Reduce complexity and allow the next patch to delete some code. With
this change, clear operations will still be skipped and setting the
aux_state will cause no side-effects.

Remove the associated comment which implies an early return.

Reviewed-by: Rafael Antognolli 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_clear.c | 5 -
 1 file changed, 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 2f61ea8ef1..ba79447fc8 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -231,10 +231,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
}
 
if (!need_clear) {
-  /* If all of the layers we intend to clear are already in the clear
-   * state then simply updating the miptree fast clear value is sufficient
-   * to change their clear value.
-   */
   if (devinfo->gen >= 10 && !same_clear_value) {
  /* Before gen10, it was enough to just update the clear value in the
   * miptree. But on gen10+, we let blorp update the clear value state
@@ -255,7 +251,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
  }
  brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
   }
-  return true;
}
 
for (unsigned a = 0; a < num_layers; a++) {

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Mesa (master): i965/blorp: Disable BLORP clear color updates

[Nanley Chery]

Module: Mesa
Branch: master
Commit: edfb57c0a0adacad4ccb42a49c19c14314a09565
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edfb57c0a0adacad4ccb42a49c19c14314a09565

Author: Nanley Chery 
Date:   Thu Apr 26 17:13:36 2018 -0700

i965/blorp: Disable BLORP clear color updates

With the previous patches, we now update the indirect clear color buffer
every time the clear color changes. Avoid redundant updates.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9d57745cc5..636591c0b7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1261,7 +1261,8 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   brw_emit_end_of_pipe_sync(brw, PIPE_CONTROL_RENDER_TARGET_FLUSH);
 
   struct blorp_batch batch;
-  blorp_batch_init(&brw->blorp, &batch, brw, 0);
+  blorp_batch_init(&brw->blorp, &batch, brw,
+   BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
   blorp_fast_clear(&batch, &surf, isl_format,
level, irb->mt_layer, num_layers,
x0, y0, x1, y1);
@@ -1615,7 +1616,8 @@ intel_hiz_exec(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
   &level, start_layer, num_layers, isl_tmp);
 
struct blorp_batch batch;
-   blorp_batch_init(&brw->blorp, &batch, brw, 0);
+   blorp_batch_init(&brw->blorp, &batch, brw,
+BLORP_BATCH_NO_UPDATE_CLEAR_COLOR);
blorp_hiz_op(&batch, &surf, level, start_layer, num_layers, op);
blorp_batch_finish(&batch);
 

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Mesa (master): intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 02f5512fed2e6fc2b92a32623fb979117d41239b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02f5512fed2e6fc2b92a32623fb979117d41239b

Author: Nanley Chery 
Date:   Thu Apr 26 17:09:29 2018 -0700

intel/blorp: Add a NO_UPDATE_CLEAR_COLOR batch flag

Allow callers to handle updating the indirect clear color buffer
themselves. This can reduce the number of clear color updates in the
case where a caller performs multiple fast clears with the same clear
color.

Reviewed-by: Jason Ekstrand 

---

 src/intel/blorp/blorp.h   | 5 +
 src/intel/blorp/blorp_genX_exec.h | 6 --
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 4626f2f83c..f22110bc84 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -72,6 +72,11 @@ enum blorp_batch_flags {
 
/* This flag indicates that the blorp call should be predicated. */
BLORP_BATCH_PREDICATE_ENABLE  = (1 << 1),
+
+   /* This flag indicates that blorp should *not* update the indirect clear
+* color buffer.
+*/
+   BLORP_BATCH_NO_UPDATE_CLEAR_COLOR = (1 << 2),
 };
 
 struct blorp_batch {
diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index 593521b95c..446743b591 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1700,8 +1700,10 @@ blorp_update_clear_color(struct blorp_batch *batch,
 static void
 blorp_exec(struct blorp_batch *batch, const struct blorp_params *params)
 {
-   blorp_update_clear_color(batch, ¶ms->dst, params->fast_clear_op);
-   blorp_update_clear_color(batch, ¶ms->depth, params->hiz_op);
+   if (!(batch->flags & BLORP_BATCH_NO_UPDATE_CLEAR_COLOR)) {
+  blorp_update_clear_color(batch, ¶ms->dst, params->fast_clear_op);
+  blorp_update_clear_color(batch, ¶ms->depth, params->hiz_op);
+   }
 
 #if GEN_GEN >= 8
if (params->hiz_op != ISL_AUX_OP_NONE) {

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Mesa (master): i965/miptree: Drop the mt param from alloc_aux_buffer

[Nanley Chery]

Module: Mesa
Branch: master
Commit: beed9c4550c1c65fed97c539ade023a66a679d15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=beed9c4550c1c65fed97c539ade023a66a679d15

Author: Nanley Chery 
Date:   Wed May  2 14:30:17 2018 -0700

i965/miptree: Drop the mt param from alloc_aux_buffer

Drop an unused parameter.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d9a8c0f848..ccde5beb3c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1659,8 +1659,7 @@ static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
const struct isl_surf *aux_surf,
bool wants_memset,
-   uint8_t memset_value,
-   struct intel_mipmap_tree *mt)
+   uint8_t memset_value)
 {
struct intel_miptree_aux_buffer *buf = calloc(sizeof(*buf), 1);
if (!buf)
@@ -1766,7 +1765,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 *
 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf, true, 0xFF, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf, true, 0xFF);
if (!mt->aux_buf) {
   free(aux_state);
   return false;
@@ -1810,7 +1809,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
 * bits in the aux buffer.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf, true, 0, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf, true, 0);
if (!mt->aux_buf) {
   free(aux_state);
   return false;
@@ -1875,7 +1874,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
   isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &temp_hiz_surf);
assert(ok);
 
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf, false, 0, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf, false, 0);
 
if (!mt->aux_buf) {
   free(aux_state);

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Mesa (master): i965/miptree: Drop the name param from alloc_aux_buffer

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 3dd7f600e04a3dd758e57b8ff70ba242b491580a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3dd7f600e04a3dd758e57b8ff70ba242b491580a

Author: Nanley Chery 
Date:   Tue May  1 14:35:35 2018 -0700

i965/miptree: Drop the name param from alloc_aux_buffer

A name of "aux-miptree" should be sufficient.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index bf0731f1f3..931f71f6d9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1657,7 +1657,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
 
 static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
-   const char *name,
const struct isl_surf *aux_surf,
uint32_t alloc_flags,
bool wants_memset,
@@ -1684,7 +1683,7 @@ intel_alloc_aux_buffer(struct brw_context *brw,
 * Therefore one can pass the ISL dimensions in terms of bytes instead of
 * trying to recalculate based on different format block sizes.
 */
-   buf->bo = brw_bo_alloc_tiled(brw->bufmgr, name, size,
+   buf->bo = brw_bo_alloc_tiled(brw->bufmgr, "aux-miptree", size,
 I915_TILING_Y, aux_surf->row_pitch,
 alloc_flags);
if (!buf->bo) {
@@ -1764,7 +1763,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 *
 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree", &temp_mcs_surf,
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf,
 alloc_flags, true, 0xFF, mt);
if (!mt->aux_buf) {
   free(aux_state);
@@ -1809,7 +1808,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
 * bits in the aux buffer.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf,
 BO_ALLOC_ZEROED, false, 0, mt);
if (!mt->aux_buf) {
   free(aux_state);
@@ -1876,7 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
assert(ok);
 
const uint32_t alloc_flags = 0;
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", &temp_hiz_surf,
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf,
 alloc_flags, false, 0, mt);
 
if (!mt->aux_buf) {

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Mesa (master): i965/miptree: Initialize the indirect clear color to zero

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 58d99a21f125b4a834dd7af58b4f05a3a601f7c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58d99a21f125b4a834dd7af58b4f05a3a601f7c7

Author: Nanley Chery 
Date:   Mon Apr 30 11:30:32 2018 -0700

i965/miptree: Initialize the indirect clear color to zero

The indirect clear color isn't correctly tracked in
intel_miptree::fast_clear_color. The initial value of ::fast_clear_color
is zero, while that of the indirect clear color is undefined.

Topi Pohjolainen discovered this issue with MCS buffers. This issue is
apparent when fast-clearing an MCS buffer for the first time with
glClearColor = {0.0,}. Although the indirect clear color is undefined,
the initial aux state of the MCS is CLEAR and the tracked clear color is
zero, so we avoid updating the indirect clear color with {0.0,}.

Make the indirect clear color match the initial value of
::fast_clear_color.

Note: although we only have to drop HiZ's BO_ALLOC_BUSY flag for gen10+,
we also drop it pre-gen10 to keep things simple. We add this flag back
for pre-gen10 in a later patch.

v2: Add a note about dropping HiZ's BO_ALLOC_BUSY flag (Topi).

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 33 ++-
 1 file changed, 22 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index d132b20abe..bf0731f1f3 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -978,11 +978,11 @@ create_ccs_buf_for_image(struct brw_context *brw,
 * system with CCS, we don't have the extra space at the end of the aux
 * buffer. So create a new bo here that will store that clear color.
 */
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   if (devinfo->gen >= 10) {
+   if (brw->isl_dev.ss.clear_color_state_size > 0) {
   mt->aux_buf->clear_color_bo =
- brw_bo_alloc(brw->bufmgr, "clear_color_bo",
-  brw->isl_dev.ss.clear_color_state_size);
+ brw_bo_alloc_tiled(brw->bufmgr, "clear_color_bo",
+brw->isl_dev.ss.clear_color_state_size,
+I915_TILING_NONE, 0, BO_ALLOC_ZEROED);
   if (!mt->aux_buf->clear_color_bo) {
  free(mt->aux_buf);
  mt->aux_buf = NULL;
@@ -1670,9 +1670,9 @@ intel_alloc_aux_buffer(struct brw_context *brw,
 
uint64_t size = aux_surf->size;
 
-   const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   if (devinfo->gen >= 10) {
-  /* On CNL, instead of setting the clear color in the SURFACE_STATE, we
+   const bool has_indirect_clear = brw->isl_dev.ss.clear_color_state_size > 0;
+   if (has_indirect_clear) {
+  /* On CNL+, instead of setting the clear color in the SURFACE_STATE, we
* will set a pointer to a dword somewhere that contains the color. So,
* allocate the space for the clear color value here on the aux buffer.
*/
@@ -1693,7 +1693,8 @@ intel_alloc_aux_buffer(struct brw_context *brw,
}
 
/* Initialize the bo to the desired value */
-   if (wants_memset) {
+   const bool needs_memset = wants_memset || has_indirect_clear;
+   if (needs_memset) {
   assert(!(alloc_flags & BO_ALLOC_BUSY));
 
   void *map = brw_bo_map(brw, buf->bo, MAP_WRITE | MAP_RAW);
@@ -1701,11 +1702,21 @@ intel_alloc_aux_buffer(struct brw_context *brw,
  intel_miptree_aux_buffer_free(buf);
  return NULL;
   }
-  memset(map, memset_value, aux_surf->size);
+
+  /* Memset the aux_surf portion of the BO. */
+  if (wants_memset)
+ memset(map, memset_value, aux_surf->size);
+
+  /* Zero the indirect clear color to match ::fast_clear_color. */
+  if (has_indirect_clear) {
+ memset((char *)map + buf->clear_color_offset, 0,
+brw->isl_dev.ss.clear_color_state_size);
+  }
+
   brw_bo_unmap(buf->bo);
}
 
-   if (devinfo->gen >= 10) {
+   if (has_indirect_clear) {
   buf->clear_color_bo = buf->bo;
   brw_bo_reference(buf->clear_color_bo);
}
@@ -1864,7 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
   isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &temp_hiz_surf);
assert(ok);
 
-   const uint32_t alloc_flags = BO_ALLOC_BUSY;
+   const uint32_t alloc_flags = 0;
mt->aux_buf = intel_alloc_aux_buffer(brw, "hiz-miptree", &temp_hiz_surf,
 alloc_flags, false, 0, mt);
 

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Mesa (master): i965/miptree: Zero-initialize CCS_D buffers

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 8a9491058da72ee2df75da25bb147010a451fb68
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a9491058da72ee2df75da25bb147010a451fb68

Author: Nanley Chery 
Date:   Wed May  2 09:38:47 2018 -0700

i965/miptree: Zero-initialize CCS_D buffers

Before this patch, the aux_state was actually AUX_INVALID because the BO
was never defined. This was fine on single slice miptrees because we
would fast-clear the resource right after creation. For multi-slice
miptrees on SKL+ however, this results in undefined behavior when
accessing a non-base slice. Here's a specific example:

1) Fast clear level 0
   * Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
   * Level 0 transitions to the CLEAR state.
2) Render to level 1
   * Level 1 may have a 2-bit pattern of 2's.
   * Rendering with a 2 in the CCS is undefined.

Cc: 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index dd851ff9b5..c01a71d445 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1801,13 +1801,11 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * A CCS value of 0 indicates that the corresponding block is in the
 * pass-through state which is what we want.
 *
-* For CCS_D, on the other hand, we don't care as we're about to perform a
-* fast-clear operation.  In that case, being hot in caches more useful.
+* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
+* bits in the aux buffer.
 */
-   const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
-BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
-   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
-&temp_ccs_surf, alloc_flags, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
+BO_ALLOC_ZEROED, mt);
if (!mt->aux_buf) {
   free(aux_state);
   return false;

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Mesa (master): i965: Update the indirect buffer in set_clear_color

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 82849fb6d54629a0c7c5a118ed8780a3ae573b25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82849fb6d54629a0c7c5a118ed8780a3ae573b25

Author: Nanley Chery 
Date:   Sun Apr  8 14:00:30 2018 -0700

i965: Update the indirect buffer in set_clear_color

For depth buffers, we avoid fast-clearing if the aux_state is already
CLEAR. We do the same for color buffers only if the clear color
doesn't change. We require that the clear colors match because, in
that case, we don't update the indirect clear color outside of BLORP.

Update the indirect clear color for color buffers as well. We'll
enable the same depth buffer optimization for color buffers in a
later patch.

Note that we're now actually updating the indirect clear color twice
in the case where we use BLORP to perform the fast-clear. This is
only temporary. In later patches, we'll prevent BLORP from performing
the update.

v2: Add more context to the commit message (Topi).

Reviewed-by: Jason Ekstrand 
Reviewed-by: Topi Pohjolainen 

---

 src/mesa/drivers/dri/i965/brw_clear.c | 37 ---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 ++
 2 files changed, 13 insertions(+), 37 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index ba79447fc8..a65839a0a0 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -108,7 +108,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
struct intel_mipmap_tree *mt = depth_irb->mt;
struct gl_renderbuffer_attachment *depth_att = 
&fb->Attachment[BUFFER_DEPTH];
const struct gen_device_info *devinfo = &brw->screen->devinfo;
-   bool same_clear_value = true;
 
if (devinfo->gen < 6)
   return false;
@@ -215,42 +214,6 @@ brw_fast_clear_depth(struct gl_context *ctx)
 
   const union isl_color_value clear_color = { .f32 = {clear_value, } };
   intel_miptree_set_clear_color(brw, mt, clear_color);
-  same_clear_value = false;
-   }
-
-   bool need_clear = false;
-   for (unsigned a = 0; a < num_layers; a++) {
-  enum isl_aux_state aux_state =
- intel_miptree_get_aux_state(mt, depth_irb->mt_level,
- depth_irb->mt_layer + a);
-
-  if (aux_state != ISL_AUX_STATE_CLEAR) {
- need_clear = true;
- break;
-  }
-   }
-
-   if (!need_clear) {
-  if (devinfo->gen >= 10 && !same_clear_value) {
- /* Before gen10, it was enough to just update the clear value in the
-  * miptree. But on gen10+, we let blorp update the clear value state
-  * buffer when doing a fast clear. Since we are skipping the fast
-  * clear here, we need to update the clear color ourselves.
-  */
- uint32_t clear_offset = mt->aux_buf->clear_color_offset;
- union isl_color_value clear_color = { .f32 = { clear_value, } };
-
- /* We can't update the clear color while the hardware is still using
-  * the previous one for a resolve or sampling from it. So make sure
-  * that there's no pending commands at this point.
-  */
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
- for (int i = 0; i < 4; i++) {
-brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
- clear_offset + i * 4, clear_color.u32[i]);
- }
- brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
-  }
}
 
for (unsigned a = 0; a < num_layers; a++) {
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 88db0fc80b..0c7c89a9ac 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3728,6 +3728,19 @@ intel_miptree_set_clear_color(struct brw_context *brw,
 {
if (memcmp(&mt->fast_clear_color, &clear_color, sizeof(clear_color)) != 0) {
   mt->fast_clear_color = clear_color;
+  if (mt->aux_buf->clear_color_bo) {
+ /* We can't update the clear color while the hardware is still using
+  * the previous one for a resolve or sampling from it. Make sure that
+  * there are no pending commands at this point.
+  */
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_CS_STALL);
+ for (int i = 0; i < 4; i++) {
+brw_store_data_imm32(brw, mt->aux_buf->clear_color_bo,
+ mt->aux_buf->clear_color_offset + i * 4,
+ mt->fast_clear_color.u32[i]);
+ }
+ brw_emit_pipe_control_flush(brw, PIPE_CONTROL_STATE_CACHE_INVALIDATE);
+  }
   brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
   return true;
}

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Mesa (master): i965: Use set_clear_color for depth miptrees

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 6f609ca609f3011b756bb920a7b06946a8a8c0b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f609ca609f3011b756bb920a7b06946a8a8c0b7

Author: Nanley Chery 
Date:   Thu Apr 26 18:49:19 2018 -0700

i965: Use set_clear_color for depth miptrees

Reduce code duplication now and prevent it in the following commits.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_clear.c |  3 ++-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 13 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  5 -
 3 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 3d540d6d90..2f61ea8ef1 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -213,7 +213,8 @@ brw_fast_clear_depth(struct gl_context *ctx)
  }
   }
 
-  intel_miptree_set_depth_clear_value(brw, mt, clear_value);
+  const union isl_color_value clear_color = { .f32 = {clear_value, } };
+  intel_miptree_set_clear_color(brw, mt, clear_color);
   same_clear_value = false;
}
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 506cf73e62..88db0fc80b 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3734,19 +3734,6 @@ intel_miptree_set_clear_color(struct brw_context *brw,
return false;
 }
 
-bool
-intel_miptree_set_depth_clear_value(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-float clear_value)
-{
-   if (mt->fast_clear_color.f32[0] != clear_value) {
-  mt->fast_clear_color.f32[0] = clear_value;
-  brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
-  return true;
-   }
-   return false;
-}
-
 union isl_color_value
 intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
   const struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 2d827afa53..42f73ba1f9 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -716,11 +716,6 @@ intel_miptree_get_clear_color(const struct gen_device_info 
*devinfo,
   struct brw_bo **clear_color_bo,
   uint32_t *clear_color_offset);
 
-bool
-intel_miptree_set_depth_clear_value(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-float clear_value);
-
 #ifdef __cplusplus
 }
 #endif

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Mesa (master): i965/miptree: Drop the alloc_flags param from alloc_aux_buffer

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 6b1836aabeab3cd4d7d318214d7d2c59386ba7ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b1836aabeab3cd4d7d318214d7d2c59386ba7ee

Author: Nanley Chery 
Date:   Wed May  2 12:46:54 2018 -0700

i965/miptree: Drop the alloc_flags param from alloc_aux_buffer

We have enough information to determine the optimal flags internally.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 931f71f6d9..d9a8c0f848 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1658,7 +1658,6 @@ intel_miptree_copy_teximage(struct brw_context *brw,
 static struct intel_miptree_aux_buffer *
 intel_alloc_aux_buffer(struct brw_context *brw,
const struct isl_surf *aux_surf,
-   uint32_t alloc_flags,
bool wants_memset,
uint8_t memset_value,
struct intel_mipmap_tree *mt)
@@ -1679,6 +1678,17 @@ intel_alloc_aux_buffer(struct brw_context *brw,
   size += brw->isl_dev.ss.clear_color_state_size;
}
 
+   /* If the buffer needs to be initialised (requiring the buffer to be
+* immediately mapped to cpu space for writing), do not use the gpu access
+* flag which can cause an unnecessary delay if the backing pages happened
+* to be just used by the GPU.
+*/
+   const bool alloc_zeroed = wants_memset && memset_value == 0;
+   const bool needs_memset =
+  !alloc_zeroed && (wants_memset || has_indirect_clear);
+   const uint32_t alloc_flags =
+  alloc_zeroed ? BO_ALLOC_ZEROED : (needs_memset ? 0 : BO_ALLOC_BUSY);
+
/* ISL has stricter set of alignment rules then the drm allocator.
 * Therefore one can pass the ISL dimensions in terms of bytes instead of
 * trying to recalculate based on different format block sizes.
@@ -1692,7 +1702,6 @@ intel_alloc_aux_buffer(struct brw_context *brw,
}
 
/* Initialize the bo to the desired value */
-   const bool needs_memset = wants_memset || has_indirect_clear;
if (needs_memset) {
   assert(!(alloc_flags & BO_ALLOC_BUSY));
 
@@ -1747,12 +1756,6 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
   isl_surf_get_mcs_surf(&brw->isl_dev, &mt->surf, &temp_mcs_surf);
assert(ok);
 
-   /* Buffer needs to be initialised requiring the buffer to be immediately
-* mapped to cpu space for writing. Therefore do not use the gpu access
-* flag which can cause an unnecessary delay if the backing pages happened
-* to be just used by the GPU.
-*/
-   const uint32_t alloc_flags = 0;
/* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
 *
 * When MCS buffer is enabled and bound to MSRT, it is required that it
@@ -1763,8 +1766,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 *
 * Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf,
-alloc_flags, true, 0xFF, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf, true, 0xFF, mt);
if (!mt->aux_buf) {
   free(aux_state);
   return false;
@@ -1808,8 +1810,7 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
 * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
 * bits in the aux buffer.
 */
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf,
-BO_ALLOC_ZEROED, false, 0, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf, true, 0, mt);
if (!mt->aux_buf) {
   free(aux_state);
   return false;
@@ -1874,9 +1875,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
   isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &temp_hiz_surf);
assert(ok);
 
-   const uint32_t alloc_flags = 0;
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf,
-alloc_flags, false, 0, mt);
+   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf, false, 0, mt);
 
if (!mt->aux_buf) {
   free(aux_state);

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Mesa (master): i965/miptree: Unify aux buffer allocation

[Nanley Chery]

Module: Mesa
Branch: master
Commit: bb18af82c30f702788108e67270b3f473dfaec80
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb18af82c30f702788108e67270b3f473dfaec80

Author: Nanley Chery 
Date:   Mon Apr 30 17:00:32 2018 -0700

i965/miptree: Unify aux buffer allocation

There isn't much that changes between the aux allocation functions.
Remove the duplicated code.

v2: Inline the switch statement (Jason).

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 215 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |   9 --
 2 files changed, 82 insertions(+), 142 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a1834fe911..b5d7d691ec 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1739,95 +1739,9 @@ intel_alloc_aux_buffer(struct brw_context *brw,
return buf;
 }
 
-static bool
-intel_miptree_alloc_mcs(struct brw_context *brw,
-struct intel_mipmap_tree *mt,
-GLuint num_samples)
-{
-   assert(brw->screen->devinfo.gen >= 7); /* MCS only used on Gen7+ */
-   assert(mt->aux_buf == NULL);
-   assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
-
-   /* Multisampled miptrees are only supported for single level. */
-   assert(mt->first_level == 0);
-   enum isl_aux_state **aux_state =
-  create_aux_state_map(mt, ISL_AUX_STATE_CLEAR);
-   if (!aux_state)
-  return false;
-
-   struct isl_surf temp_mcs_surf;
-
-   MAYBE_UNUSED bool ok =
-  isl_surf_get_mcs_surf(&brw->isl_dev, &mt->surf, &temp_mcs_surf);
-   assert(ok);
-
-   /* From the Ivy Bridge PRM, Vol 2 Part 1 p326:
-*
-* When MCS buffer is enabled and bound to MSRT, it is required that it
-* is cleared prior to any rendering.
-*
-* Since we don't use the MCS buffer for any purpose other than rendering,
-* it makes sense to just clear it immediately upon allocation.
-*
-* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
-*/
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_mcs_surf, true, 0xFF);
-   if (!mt->aux_buf) {
-  free(aux_state);
-  return false;
-   }
-
-   mt->aux_state = aux_state;
-
-   return true;
-}
-
-static bool
-intel_miptree_alloc_ccs(struct brw_context *brw,
-struct intel_mipmap_tree *mt)
-{
-   assert(mt->aux_buf == NULL);
-   assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E ||
-  mt->aux_usage == ISL_AUX_USAGE_CCS_D);
-
-   struct isl_surf temp_ccs_surf;
-
-   if (!isl_surf_get_ccs_surf(&brw->isl_dev, &mt->surf, &temp_ccs_surf, 0))
-  return false;
-
-   assert(temp_ccs_surf.size &&
-  (temp_ccs_surf.size % temp_ccs_surf.row_pitch == 0));
-
-   enum isl_aux_state **aux_state =
-  create_aux_state_map(mt, ISL_AUX_STATE_PASS_THROUGH);
-   if (!aux_state)
-  return false;
-
-   /* When CCS_E is used, we need to ensure that the CCS starts off in a valid
-* state.  From the Sky Lake PRM, "MCS Buffer for Render Target(s)":
-*
-*"If Software wants to enable Color Compression without Fast clear,
-*Software needs to initialize MCS with zeros."
-*
-* A CCS value of 0 indicates that the corresponding block is in the
-* pass-through state which is what we want.
-*
-* For CCS_D, do the same thing. On gen9+, this avoids having any undefined
-* bits in the aux buffer.
-*/
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_ccs_surf, true, 0);
-   if (!mt->aux_buf) {
-  free(aux_state);
-  return false;
-   }
-
-   mt->aux_state = aux_state;
-
-   return true;
-}
 
 /**
- * Helper for intel_miptree_alloc_hiz() that sets
+ * Helper for intel_miptree_alloc_aux() that sets
  * \c mt->level[level].has_hiz. Return true if and only if
  * \c has_hiz was set.
  */
@@ -1862,39 +1776,6 @@ intel_miptree_level_enable_hiz(struct brw_context *brw,
return true;
 }
 
-bool
-intel_miptree_alloc_hiz(struct brw_context *brw,
-   struct intel_mipmap_tree *mt)
-{
-   assert(mt->aux_buf == NULL);
-   assert(mt->aux_usage == ISL_AUX_USAGE_HIZ);
-
-   enum isl_aux_state **aux_state =
-  create_aux_state_map(mt, ISL_AUX_STATE_AUX_INVALID);
-   if (!aux_state)
-  return false;
-
-   struct isl_surf temp_hiz_surf;
-
-   MAYBE_UNUSED bool ok =
-  isl_surf_get_hiz_surf(&brw->isl_dev, &mt->surf, &temp_hiz_surf);
-   assert(ok);
-
-   mt->aux_buf = intel_alloc_aux_buffer(brw, &temp_hiz_surf, false, 0);
-
-   if (!mt->aux_buf) {
-  free(aux_state);
-  return false;
-   }
-
-   for (unsigned level = mt->first_level; level <= mt->last_level; ++level)
-  intel_miptree_level_enable_hiz(brw, mt, level);
-
-   mt->aux_state = aux_state;
-
-   return true;
-}
-
 
 /**
  * Allocate the initial aux surface for a miptree based on mt->aux_usage
@@ -1907,33 +1788,101 @@ bool
 inte

Mesa (master): Revert "i965: Make the miptree clear color setter take a gl_color_union"

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 92a0a87b6f78b316f47132bb8f67c1ba28d3c020
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92a0a87b6f78b316f47132bb8f67c1ba28d3c020

Author: Nanley Chery 
Date:   Fri Apr 27 12:27:07 2018 -0700

Revert "i965: Make the miptree clear color setter take a gl_color_union"

This reverts commit 1d94aa19877fb702ffacacde28ad7253cce72c97.

The next patch will make depth miptrees use the clear color setter that
was originally being used for color miptrees. Go back to using the
isl_color_value parameter because it's the same type as the
fast_clear_color field used by color and depth miptrees.

Reviewed-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 5 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +-
 3 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 2ea13bb743..04155b7d4c 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1225,9 +1225,12 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
if (can_fast_clear) {
   const enum isl_aux_state aux_state =
  intel_miptree_get_aux_state(irb->mt, irb->mt_level, irb->mt_layer);
+  union isl_color_value clear_color =
+ brw_meta_convert_fast_clear_color(brw, irb->mt,
+   &ctx->Color.ClearColor);
 
   bool same_clear_color =
- !intel_miptree_set_clear_color(brw, irb->mt, &ctx->Color.ClearColor);
+ !intel_miptree_set_clear_color(brw, irb->mt, clear_color);
 
   /* If the buffer is already in INTEL_FAST_CLEAR_STATE_CLEAR, the clear
* is redundant and can be skipped.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index b5d7d691ec..506cf73e62 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -36,7 +36,6 @@
 
 #include "brw_blorp.h"
 #include "brw_context.h"
-#include "brw_meta_util.h"
 #include "brw_state.h"
 
 #include "main/enums.h"
@@ -3725,11 +3724,8 @@ get_isl_dim_layout(const struct gen_device_info *devinfo,
 bool
 intel_miptree_set_clear_color(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-  const union gl_color_union *color)
+  union isl_color_value clear_color)
 {
-   const union isl_color_value clear_color =
-  brw_meta_convert_fast_clear_color(brw, mt, color);
-
if (memcmp(&mt->fast_clear_color, &clear_color, sizeof(clear_color)) != 0) {
   mt->fast_clear_color = clear_color;
   brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 903d99137f..2d827afa53 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -706,7 +706,7 @@ intel_miptree_sample_with_hiz(struct brw_context *brw,
 bool
 intel_miptree_set_clear_color(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
-  const union gl_color_union *color);
+  union isl_color_value clear_color);
 
 /* Get a clear color suitable for filling out an ISL surface state. */
 union isl_color_value

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Mesa (master): i965/miptree: Fix handling of uninitialized MCS buffers

[Nanley Chery]

Module: Mesa
Branch: master
Commit: 816f2dc67da72be8993e724aeda4c2ec2f5a2978
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=816f2dc67da72be8993e724aeda4c2ec2f5a2978

Author: Nanley Chery 
Date:   Mon Apr 30 10:40:18 2018 -0700

i965/miptree: Fix handling of uninitialized MCS buffers

Before this patch, if we failed to initialize an MCS buffer, we'd
end up in a state in which the miptree thinks it has an MCS buffer,
but doesn't. We also leaked the clear_color_bo if it existed.

With this patch, we now free the miptree aux buffer resources and let
intel_miptree_alloc_mcs() know that the MCS buffer no longer exists.

Cc: 
Reviewed-by: Tapani Pälli 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 67086ee6c0..dd851ff9b5 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1655,7 +1655,7 @@ intel_miptree_copy_teximage(struct brw_context *brw,
intel_obj->needs_validate = true;
 }
 
-static void
+static bool
 intel_miptree_init_mcs(struct brw_context *brw,
struct intel_mipmap_tree *mt,
int init_value)
@@ -1675,13 +1675,14 @@ intel_miptree_init_mcs(struct brw_context *brw,
void *map = brw_bo_map(brw, mt->aux_buf->bo, MAP_WRITE | MAP_RAW);
if (unlikely(map == NULL)) {
   fprintf(stderr, "Failed to map mcs buffer into GTT\n");
-  brw_bo_unreference(mt->aux_buf->bo);
-  free(mt->aux_buf);
-  return;
+  intel_miptree_aux_buffer_free(mt->aux_buf);
+  mt->aux_buf = NULL;
+  return false;
}
void *data = map;
memset(data, init_value, mt->aux_buf->surf.size);
brw_bo_unmap(mt->aux_buf->bo);
+   return true;
 }
 
 static struct intel_miptree_aux_buffer *
@@ -1759,15 +1760,14 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
const uint32_t alloc_flags = 0;
mt->aux_buf = intel_alloc_aux_buffer(brw, "mcs-miptree",
 &temp_mcs_surf, alloc_flags, mt);
-   if (!mt->aux_buf) {
+   if (!mt->aux_buf ||
+   !intel_miptree_init_mcs(brw, mt, 0xFF)) {
   free(aux_state);
   return false;
}
 
mt->aux_state = aux_state;
 
-   intel_miptree_init_mcs(brw, mt, 0xFF);
-
return true;
 }
 

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Mesa (master): radv: only declare the ESGS rings for pre GFX9 chips

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 1fba2e10b3f383953412fb2d6fcf4cd5cff6dea7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fba2e10b3f383953412fb2d6fcf4cd5cff6dea7

Author: Samuel Pitoiset 
Date:   Tue May 15 22:27:28 2018 +0200

radv: only declare the ESGS rings for pre GFX9 chips

GFX9 uses LDS instead.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_nir_to_llvm.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 82b1e3637f..dba615025d 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -3017,9 +3017,16 @@ ac_nir_eliminate_const_vs_outputs(struct 
radv_shader_context *ctx)
 static void
 ac_setup_rings(struct radv_shader_context *ctx)
 {
-   if ((ctx->stage == MESA_SHADER_VERTEX && ctx->options->key.vs.as_es) ||
-   (ctx->stage == MESA_SHADER_TESS_EVAL && 
ctx->options->key.tes.as_es)) {
-   ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_VS, false));
+   if (ctx->options->chip_class <= VI &&
+   (ctx->stage == MESA_SHADER_GEOMETRY ||
+ctx->options->key.vs.as_es || ctx->options->key.tes.as_es)) {
+   unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? 
RING_ESGS_GS
+  : 
RING_ESGS_VS;
+   LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
+
+   ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
+  ctx->ring_offsets,
+  offset);
}
 
if (ctx->is_gs_copy_shader) {
@@ -3030,7 +3037,6 @@ ac_setup_rings(struct radv_shader_context *ctx)
uint32_t num_entries = 64;
LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, 
ctx->max_gsvs_emit_size, false);
LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, 
ctx->max_gsvs_emit_size << 16, false);
-   ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
ctx->gsvs_ring = ac_build_load_to_sgpr(&ctx->ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
 
ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, 
ctx->gsvs_ring, ctx->ac.v4i32, "");

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Mesa (master): radv: do not emit unnecessary GS output stores

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: a6e44d12714871193ef130845b1f8727ffdbf01e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6e44d12714871193ef130845b1f8727ffdbf01e

Author: Samuel Pitoiset 
Date:   Wed May 16 17:43:22 2018 +0200

radv: do not emit unnecessary GS output stores

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index b4af0f2941..05ae709685 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1684,6 +1684,8 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned 
stream, LLVMValueRef *addr
/* loop num outputs */
idx = 0;
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
+   unsigned output_usage_mask =
+   ctx->shader_info->info.gs.output_usage_mask[i];
LLVMValueRef *out_ptr = &addrs[i * 4];
int length = 4;
int slot = idx;
@@ -1697,8 +1699,13 @@ visit_emit_vertex(struct ac_shader_abi *abi, unsigned 
stream, LLVMValueRef *addr
length = ctx->num_output_clips + ctx->num_output_culls;
if (length > 4)
slot_inc = 2;
+   output_usage_mask = (1 << length) - 1;
}
+
for (unsigned j = 0; j < length; j++) {
+   if (!(output_usage_mask & (1 << j)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
 out_ptr[j], "");
LLVMValueRef voffset = LLVMConstInt(ctx->ac.i32, (slot 
* 4 + j) * ctx->gs_max_out_vertices, false);

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Mesa (master): radv: do not emit unnecessary ES output stores

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 56d53ed1d69e4c365d146cf37ebaf712362e4755
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56d53ed1d69e4c365d146cf37ebaf712362e4755

Author: Samuel Pitoiset 
Date:   Wed May 16 17:43:23 2018 +0200

radv: do not emit unnecessary ES output stores

GFX9:
Totals from affected shaders:
SGPRS: 472 -> 464 (-1.69 %)
VGPRS: 576 -> 584 (1.39 %)
Code Size: 45432 -> 44324 (-2.44 %) bytes
Max Waves: 40 -> 40 (0.00 %)

VI:
SGPRS: 720 -> 720 (0.00 %)
VGPRS: 728 -> 728 (0.00 %)
Code Size: 45348 -> 43992 (-2.99 %) bytes
Max Waves: 120 -> 120 (0.00 %)

This affects Rise of Tomb Raider and the three Vulkan demos
that use a geometry shader (geometryshader, deferredshadows
and viewportarray).

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_nir_to_llvm.c | 26 +++---
 1 file changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 05ae709685..82b1e3637f 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2582,14 +2582,26 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
LLVMValueRef dw_addr = NULL;
LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
+   unsigned output_usage_mask;
int param_index;
int length = 4;
 
if (!(ctx->output_mask & (1ull << i)))
continue;
 
-   if (i == VARYING_SLOT_CLIP_DIST0)
+   if (ctx->stage == MESA_SHADER_VERTEX) {
+   output_usage_mask =
+   ctx->shader_info->info.vs.output_usage_mask[i];
+   } else {
+   assert(ctx->stage == MESA_SHADER_TESS_EVAL);
+   output_usage_mask =
+   ctx->shader_info->info.tes.output_usage_mask[i];
+   }
+
+   if (i == VARYING_SLOT_CLIP_DIST0) {
length = ctx->num_output_clips + ctx->num_output_culls;
+   output_usage_mask = (1 << length) - 1;
+   }
 
param_index = shader_io_get_unique_index(i);
 
@@ -2598,14 +2610,22 @@ handle_es_outputs_post(struct radv_shader_context *ctx,
   LLVMConstInt(ctx->ac.i32, 
param_index * 4, false),
   "");
}
+
for (j = 0; j < length; j++) {
+   if (!(output_usage_mask & (1 << j)))
+   continue;
+
LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
out_ptr[j], "");
out_val = LLVMBuildBitCast(ctx->ac.builder, out_val, 
ctx->ac.i32, "");
 
if (ctx->ac.chip_class  >= GFX9) {
-   ac_lds_store(&ctx->ac, dw_addr,
+   LLVMValueRef dw_addr_offset =
+   LLVMBuildAdd(ctx->ac.builder, dw_addr,
+LLVMConstInt(ctx->ac.i32,
+ j, false), 
"");
+
+   ac_lds_store(&ctx->ac, dw_addr_offset,
 LLVMBuildLoad(ctx->ac.builder, 
out_ptr[j], ""));
-   dw_addr = LLVMBuildAdd(ctx->ac.builder, 
dw_addr, ctx->ac.i32_1, "");
} else {
ac_build_buffer_store_dword(&ctx->ac,
ctx->esgs_ring,

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Mesa (master): radv: allow to print GPU info with RADV_DEBUG=info

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: d349d4bd24aef5b76d5ebb999f55416a14b039f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d349d4bd24aef5b76d5ebb999f55416a14b039f1

Author: Samuel Pitoiset 
Date:   Wed May 16 15:52:37 2018 +0200

radv: allow to print GPU info with RADV_DEBUG=info

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_debug.h  | 1 +
 src/amd/vulkan/radv_device.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 9dda9b6b0c..b6993cee1c 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -45,6 +45,7 @@ enum {
RADV_DEBUG_PREOPTIR  = 0x8000,
RADV_DEBUG_NO_DYNAMIC_BOUNDS = 0x1,
RADV_DEBUG_NO_OUT_OF_ORDER   = 0x2,
+   RADV_DEBUG_INFO  = 0x4,
 };
 
 enum {
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e24b8c2a76..778887bd58 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -329,6 +329,9 @@ radv_physical_device_init(struct radv_physical_device 
*device,
goto fail;
}
 
+   if ((device->instance->debug_flags & RADV_DEBUG_INFO))
+   ac_print_gpu_info(&device->rad_info);
+
return VK_SUCCESS;
 
 fail:
@@ -391,6 +394,7 @@ static const struct debug_control radv_debug_options[] = {
{"preoptir", RADV_DEBUG_PREOPTIR},
{"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
{"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
+   {"info", RADV_DEBUG_INFO},
{NULL, 0}
 };
 

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Mesa (master): radv: remove the radv_finishme() when compiling shaders

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 6211799aff761282d07b0ce3efde88e67caeb04a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6211799aff761282d07b0ce3efde88e67caeb04a

Author: Samuel Pitoiset 
Date:   Thu May 17 09:56:48 2018 +0200

radv: remove the radv_finishme() when compiling shaders

Having an entrypoint different than "main" doesn't mean we
have multiple shaders per module.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_shader.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 1968758a39..7589d9c88a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -163,10 +163,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
   const VkSpecializationInfo *spec_info,
   const VkPipelineCreateFlags flags)
 {
-   if (strcmp(entrypoint_name, "main") != 0) {
-   radv_finishme("Multiple shaders per module not really 
supported");
-   }
-
nir_shader *nir;
nir_function *entry_point;
if (module->nir) {

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Mesa (master): radv: only pass the global BO list at submit time if enabled

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 507402ada6dbe56daca49c1f9bdba3b445132e50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=507402ada6dbe56daca49c1f9bdba3b445132e50

Author: Samuel Pitoiset 
Date:   Thu May 17 11:36:09 2018 +0200

radv: only pass the global BO list at submit time if enabled

That way the winsys might use a faster path when the global
BO list is NULL.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_device.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 2ce0c9dbd0..e24b8c2a76 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2472,6 +2472,8 @@ VkResult radv_QueueSubmit(
 
for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += 
advance) {
struct radeon_winsys_cs *initial_preamble = (do_flush 
&& !j) ? initial_flush_preamble_cs : initial_preamble_cs;
+   const struct radv_winsys_bo_list *bo_list = NULL;
+
advance = MIN2(max_cs_submission,
   pSubmits[i].commandBufferCount - j);
 
@@ -2481,12 +2483,14 @@ VkResult radv_QueueSubmit(
sem_info.cs_emit_wait = j == 0;
sem_info.cs_emit_signal = j + advance == 
pSubmits[i].commandBufferCount;
 
-   if (unlikely(queue->device->use_global_bo_list))
+   if (unlikely(queue->device->use_global_bo_list)) {

pthread_mutex_lock(&queue->device->bo_list.mutex);
+   bo_list = &queue->device->bo_list.list;
+   }
 
ret = queue->device->ws->cs_submit(ctx, 
queue->queue_idx, cs_array + j,
advance, 
initial_preamble, continue_preamble_cs,
-   &sem_info, 
&queue->device->bo_list.list,
+   &sem_info, bo_list,
can_patch, base_fence);
 
if (unlikely(queue->device->use_global_bo_list))

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Mesa (master): radv: remove radv_device::llvm_supports_spill

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 1e86eaf7d83e73b0287722a868718eb18675ce08
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e86eaf7d83e73b0287722a868718eb18675ce08

Author: Samuel Pitoiset 
Date:   Thu May 17 09:56:47 2018 +0200

radv: remove radv_device::llvm_supports_spill

It's always true.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_device.c  | 2 --
 src/amd/vulkan/radv_private.h | 1 -
 src/amd/vulkan/radv_shader.c  | 5 +
 3 files changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index a7f4a5ab7b..2ce0c9dbd0 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1454,8 +1454,6 @@ VkResult radv_CreateDevice(
device->always_use_syncobj = 
device->physical_device->rad_info.has_syncobj_wait_for_submit;
 #endif
 
-   device->llvm_supports_spill = true;
-
/* The maximum number of scratch waves. Scratch space isn't divided
 * evenly between CUs. The number is only a function of the number of 
CUs.
 * We can decrease the constant to decrease the scratch buffer size.
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e3eed887fa..304ed17f01 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -624,7 +624,6 @@ struct radv_device {
struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
 
bool always_use_syncobj;
-   bool llvm_supports_spill;
bool has_distributed_tess;
bool pbb_allowed;
bool dfsm_allowed;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index dfe63d60d4..1968758a39 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -376,9 +376,6 @@ radv_fill_shader_variant(struct radv_device *device,
struct radv_shader_info *info = &variant->info.info;
unsigned vgpr_comp_cnt = 0;
 
-   if (scratch_enabled && !device->llvm_supports_spill)
-   radv_finishme("shader scratch support only available with LLVM 
4.0");
-
variant->code_size = binary->code_size;
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
 S_00B12C_SCRATCH_EN(scratch_enabled);
@@ -554,7 +551,7 @@ radv_shader_variant_create(struct radv_device *device,
options.key = *key;
 
options.unsafe_math = !!(device->instance->debug_flags & 
RADV_DEBUG_UNSAFE_MATH);
-   options.supports_spill = device->llvm_supports_spill;
+   options.supports_spill = true;
 
return shader_variant_create(device, module, shaders, shader_count, 
shaders[shader_count - 1]->info.stage,
 &options, false, code_out, code_size_out);

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