Mesa (master): intel/genxml: Fix a few invalid field widths
Module: Mesa Branch: master Commit: cf440d85db6d0ec3d2d5467cfa3d0462e4267261 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf440d85db6d0ec3d2d5467cfa3d0462e4267261 Author: Chris Wilson Date: Sat May 5 19:36:25 2018 +0100 intel/genxml: Fix a few invalid field widths A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin Reviewed-by: Jason Ekstrand Reviewed-by: Lionel Landwerlin --- src/intel/genxml/gen4.xml | 12 ++-- src/intel/genxml/gen45.xml | 12 ++-- src/intel/genxml/gen5.xml | 12 ++-- src/intel/genxml/gen6.xml | 6 +++--- src/intel/genxml/gen7.xml | 6 +++--- src/intel/genxml/gen75.xml | 8 6 files changed, 28 insertions(+), 28 deletions(-) diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml index 6f513c5833..cd50a1012b 100644 --- a/src/intel/genxml/gen4.xml +++ b/src/intel/genxml/gen4.xml @@ -961,12 +961,12 @@ - - - - - - + + + + + + diff --git a/src/intel/genxml/gen45.xml b/src/intel/genxml/gen45.xml index fbd57a00c5..4d2c1534d3 100644 --- a/src/intel/genxml/gen45.xml +++ b/src/intel/genxml/gen45.xml @@ -994,12 +994,12 @@ - - - - - - + + + + + + diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index 5c93ecdda3..5bb5a2c331 100644 --- a/src/intel/genxml/gen5.xml +++ b/src/intel/genxml/gen5.xml @@ -1086,12 +1086,12 @@ i - - - - - - + + + + + + diff --git a/src/intel/genxml/gen6.xml b/src/intel/genxml/gen6.xml index 0493221bd7..f258065eba 100644 --- a/src/intel/genxml/gen6.xml +++ b/src/intel/genxml/gen6.xml @@ -1888,7 +1888,7 @@ - + @@ -1904,7 +1904,7 @@ - + @@ -1920,7 +1920,7 @@ - + diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index baf42a7d32..895f5d232b 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2537,7 +2537,7 @@ - + @@ -2553,7 +2553,7 @@ - + @@ -2569,7 +2569,7 @@ - + diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 7b635b22da..fe59446d83 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -3021,7 +3021,7 @@ - + @@ -3037,7 +3037,7 @@ - + @@ -3053,7 +3053,7 @@ - + @@ -3069,7 +3069,7 @@ - + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext
Module: Mesa Branch: master Commit: 525b4f7548462bfc2e82f2d1f04f61ce6854a3c5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=525b4f7548462bfc2e82f2d1f04f61ce6854a3c5 Author: Chris Wilson Date: Sat Jan 20 00:19:47 2018 + i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext The forward port of commit 6d87500fe12e ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs") failed to adapt the set of allowed attributes for the earlier introduction of context priorities (commit 1617fca6d12e "i965: Pass the EGL/DRI context priority through to the kernel"). Fixes: 6d87500fe12e ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs") Signed-off-by: Chris Wilson Cc: Adam Jackson Cc: Nicolai Hähnle Cc: Emil Velikov Cc: Kenneth Graunke Reviewed-by: Tapani Pälli Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_context.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 296335040d..b830e71247 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -860,7 +860,9 @@ brwCreateContext(gl_api api, return false; } - if (ctx_config->attribute_mask & ~__DRIVER_CONTEXT_ATTRIB_RESET_STRATEGY) { + if (ctx_config->attribute_mask & + ~(__DRIVER_CONTEXT_ATTRIB_RESET_STRATEGY | + __DRIVER_CONTEXT_ATTRIB_PRIORITY)) { *dri_ctx_error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE; return false; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Future-proof ring names for aubinator_error_decode
Module: Mesa Branch: master Commit: 34499e8ddce09a55210e776700ee6de2fc6df6b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34499e8ddce09a55210e776700ee6de2fc6df6b2 Author: Chris Wilson Date: Wed Jan 17 15:41:25 2018 + intel: Future-proof ring names for aubinator_error_decode The kernel is moving to a $class$instance naming scheme in preparation for accommodating more rings in the future in a consistent manner. It is already using the naming scheme internally, and now we are looking at updating some soft-ABI such as the error state to use the new naming scheme. This of course means we need to teach aubinator_error_decode how to map both sets of ring names onto its register maps. Signed-off-by: Chris Wilson Cc: Michel Thierry Cc: Michal Wajdeczko Cc: Tvrtko Ursulin Cc: Lionel Landwerlin Cc: Kenneth Graunke Reviewed-by: Kenneth Graunke Reviewed-by: Michel Thierry --- src/intel/tools/aubinator_error_decode.c | 122 +-- 1 file changed, 98 insertions(+), 24 deletions(-) diff --git a/src/intel/tools/aubinator_error_decode.c b/src/intel/tools/aubinator_error_decode.c index 9dd70790e1..01c6a7a365 100644 --- a/src/intel/tools/aubinator_error_decode.c +++ b/src/intel/tools/aubinator_error_decode.c @@ -74,40 +74,95 @@ print_register(struct gen_spec *spec, const char *name, uint32_t reg) } struct ring_register_mapping { - const char *ring_name; + unsigned ring_class; + unsigned ring_instance; const char *register_name; }; +enum { + RCS, + BCS, + VCS, + VECS, +}; + static const struct ring_register_mapping acthd_registers[] = { - { "blt", "BCS_ACTHD_UDW" }, - { "bsd", "VCS_ACTHD_UDW" }, - { "bsd2", "VCS2_ACTHD_UDW" }, - { "render", "ACTHD_UDW" }, - { "vebox", "VECS_ACTHD_UDW" }, + { BCS, 0, "BCS_ACTHD_UDW" }, + { VCS, 0, "VCS_ACTHD_UDW" }, + { VCS, 1, "VCS2_ACTHD_UDW" }, + { RCS, 0, "ACTHD_UDW" }, + { VECS, 0, "VECS_ACTHD_UDW" }, }; static const struct ring_register_mapping ctl_registers[] = { - { "blt", "BCS_RING_BUFFER_CTL" }, - { "bsd", "VCS_RING_BUFFER_CTL" }, - { "bsd2", "VCS2_RING_BUFFER_CTL" }, - { "render", "RCS_RING_BUFFER_CTL" }, - { "vebox", "VECS_RING_BUFFER_CTL" }, + { BCS, 0, "BCS_RING_BUFFER_CTL" }, + { VCS, 0, "VCS_RING_BUFFER_CTL" }, + { VCS, 1, "VCS2_RING_BUFFER_CTL" }, + { RCS, 0, "RCS_RING_BUFFER_CTL" }, + { VECS, 0, "VECS_RING_BUFFER_CTL" }, }; static const struct ring_register_mapping fault_registers[] = { - { "blt", "BCS_FAULT_REG" }, - { "bsd", "VCS_FAULT_REG" }, - { "render", "RCS_FAULT_REG" }, - { "vebox", "VECS_FAULT_REG" }, + { BCS, 0, "BCS_FAULT_REG" }, + { VCS, 0, "VCS_FAULT_REG" }, + { RCS, 0, "RCS_FAULT_REG" }, + { VECS, 0, "VECS_FAULT_REG" }, }; +static int ring_name_to_class(const char *ring_name, + unsigned int *class) +{ + static const char *class_names[] = { + [RCS] = "rcs", + [BCS] = "bcs", + [VCS] = "vcs", + [VECS] = "vecs", + }; + for (size_t i = 0; i < ARRAY_SIZE(class_names); i++) { + if (strcmp(ring_name, class_names[i])) + continue; + + *class = i; + return atoi(ring_name + strlen(class_names[i])); + } + + static const struct { + const char *name; + unsigned int class; + int instance; + } legacy_names[] = { + { "render", RCS, 0 }, + { "blt", BCS, 0 }, + { "bsd", VCS, 0 }, + { "bsd2", VCS, 1 }, + { "vebox", VECS, 0 }, + }; + for (size_t i = 0; i < ARRAY_SIZE(legacy_names); i++) { + if (strcmp(ring_name, legacy_names[i].name)) + continue; + + *class = legacy_names[i].class; + return legacy_names[i].instance; + } + + return -1; +} + static const char * register_name_from_ring(const struct ring_register_mapping *mapping, unsigned nb_mapping, const char *ring_name) { + unsigned int class; + int instance; + + instance = ring_name_to_class(ring_name, &class); + if (instance < 0) + return NULL; + for (unsigned i = 0; i < nb_mapping; i++) { - if (strcmp(mapping[i].ring_name, ring_name) == 0) + if (mapping[i].ring_class == class && + mapping[i].ring_instance == instance) return mapping[i].register_name; } return NULL; @@ -117,16 +172,35 @@ static const char * instdone_register_for_ring(const struct gen_device_info *devinfo,
Mesa (master): i965: Allow old begin/end queryobj for gen4/ 5 with HW contexts
Module: Mesa Branch: master Commit: a68873f668acf70fc8c5158d3aafc63838efa697 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a68873f668acf70fc8c5158d3aafc63838efa697 Author: Chris Wilson Date: Thu Nov 23 09:57:08 2017 + i965: Allow old begin/end queryobj for gen4/5 with HW contexts Since we have HW contexts on gen4/5, we could take advantage of them, as done for gen6+ in commit e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+."), to only emit a pair of counters at begin/end queryobj, rather than around every primitive. However, to keep queryobj working in the meantime as we bringup support for HW ctx on gen4/5, we can keep using the existing code. References: e32cd5ffbb72 ("i965: Rely on hardware contexts for query objects on Gen6+.") Cc: Kenneth Graunke Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_queryobj.c | 6 -- 1 file changed, 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index bd3f5738eb..f667f55b6b 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -480,9 +480,6 @@ brw_emit_query_begin(struct brw_context *brw) struct gl_context *ctx = &brw->ctx; struct brw_query_object *query = brw->query.obj; - if (brw->hw_ctx) - return; - /* Skip if we're not doing any queries, or we've already recorded the * initial query value for this batchbuffer. */ @@ -507,9 +504,6 @@ brw_emit_query_end(struct brw_context *brw) { struct brw_query_object *query = brw->query.obj; - if (brw->hw_ctx) - return; - if (!brw->query.begin_emitted) return; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Report supported context priorities to EGL/DRI
Module: Mesa Branch: master Commit: f72392231b227f2d08d1dc73cb590f41ffc32492 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f72392231b227f2d08d1dc73cb590f41ffc32492 Author: Chris Wilson Date: Tue Apr 11 16:17:36 2017 +0100 i965: Report supported context priorities to EGL/DRI Hook up the RendererQuery for __DRI2_RENDERER_HAS_CONTEXT_PRIORITY to report the available DRM_I915_GEM_CONTEXT_SETPARAM options based on the per-client default context. The kernel will validate the request to change the property, so we get an accurate reflection of available support (based on kernel version and privilege) and we should only have to do it once during screen setup -- although the SETPARAM should be fast, they are still an ioctl each. Signed-off-by: Chris Wilson Cc: Kenneth Graunke Reviewed-by: Emil Velikov Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_screen.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 28e83cf9b2..5975b91a76 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1371,6 +1371,19 @@ brw_query_renderer_integer(__DRIscreen *dri_screen, case __DRI2_RENDERER_HAS_TEXTURE_3D: value[0] = 1; return 0; + case __DRI2_RENDERER_HAS_CONTEXT_PRIORITY: + value[0] = 0; + if (brw_hw_context_set_priority(screen->bufmgr, + 0, BRW_CONTEXT_HIGH_PRIORITY) == 0) + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH; + if (brw_hw_context_set_priority(screen->bufmgr, + 0, BRW_CONTEXT_LOW_PRIORITY) == 0) + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW; + /* reset to default last, just in case */ + if (brw_hw_context_set_priority(screen->bufmgr, + 0, BRW_CONTEXT_MEDIUM_PRIORITY) == 0) + value[0] |= __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM; + return 0; default: return driQueryRendererIntegerCommon(dri_screen, param, value); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): egl: Support IMG_context_priority
Module: Mesa Branch: master Commit: 95ecf3df62372b5ba50d4b967994fff9464298ef URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=95ecf3df62372b5ba50d4b967994fff9464298ef Author: Chris Wilson Date: Thu Oct 27 19:34:46 2016 +0100 egl: Support IMG_context_priority IMG_context_priority https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt "This extension allows an EGLContext to be created with a priority hint. It is possible that an implementation will not honour the hint, especially if there are constraints on the number of high priority contexts available in the system, or system policy limits access to high priority contexts to appropriate system privilege level. A query is provided to find the real priority level assigned to the context after creation." The extension adds a new eglCreateContext attribute for choosing a priority hint. This stub parses the attribute and copies into the base struct _egl_context, and hooks up the query similarly. Since the attribute is purely a hint, I have no qualms about the lack of implementation before reporting back the value the user gave! v2: Remember to set the default ContextPriority value to medium. v3: Use the driRendererQuery interface to probe the backend for supported priority values and use those to mask the EGL interface. v4: Treat the priority attrib as a hint and gracefully mask any requests not supported by the driver, the EGLContext will remain at medium priority. Signed-off-by: Chris Wilson Cc: Rob Clark Reviewed-by: Ben Widawsky Reviewed-by: Emil Velikov Reviewed-by: Eric Engestrom Reviewed-by: Kenneth Graunke --- include/GL/internal/dri_interface.h | 8 + src/egl/drivers/dri2/egl_dri2.c | 5 src/egl/main/eglapi.c | 2 ++ src/egl/main/eglcontext.c | 58 + src/egl/main/eglcontext.h | 1 + src/egl/main/egldisplay.h | 5 6 files changed, 79 insertions(+) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index aefba92c02..7ed0169a98 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -1782,6 +1782,14 @@ typedef struct __DRIDriverVtableExtensionRec { */ #define __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB 0x000c +/* Bitmaks of supported/available context priorities - must match + * __EGL_CONTEXT_PRIORITY_LOW_BIT et al + */ +#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY 0x000d +#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW(1 << 0) +#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM (1 << 1) +#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH (1 << 2) + typedef struct __DRI2rendererQueryExtensionRec __DRI2rendererQueryExtension; struct __DRI2rendererQueryExtensionRec { __DRIextension base; diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index d7a88b2984..e18e05e4a9 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -687,6 +687,11 @@ dri2_setup_screen(_EGLDisplay *disp) disp->Extensions.KHR_no_config_context = EGL_TRUE; disp->Extensions.KHR_surfaceless_context = EGL_TRUE; + /* Report back to EGL the bitmask of priorities supported */ + disp->Extensions.IMG_context_priority = + dri2_renderer_query_integer(dri2_dpy, + __DRI2_RENDERER_HAS_CONTEXT_PRIORITY); + if (dri2_renderer_query_integer(dri2_dpy, __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB)) disp->Extensions.KHR_gl_colorspace = EGL_TRUE; diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c index 38fc9311cb..215332f99c 100644 --- a/src/egl/main/eglapi.c +++ b/src/egl/main/eglapi.c @@ -490,6 +490,8 @@ _eglCreateExtensionsString(_EGLDisplay *dpy) _EGL_CHECK_EXTENSION(EXT_image_dma_buf_import_modifiers); _EGL_CHECK_EXTENSION(EXT_swap_buffers_with_damage); + _EGL_CHECK_EXTENSION(IMG_context_priority); + _EGL_CHECK_EXTENSION(KHR_cl_event2); _EGL_CHECK_EXTENSION(KHR_config_attribs); _EGL_CHECK_EXTENSION(KHR_create_context); diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c index 1b03160439..8c64f9ab82 100644 --- a/src/egl/main/eglcontext.c +++ b/src/egl/main/eglcontext.c @@ -332,6 +332,60 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay *dpy, ctx->NoError = !!val; break; + case EGL_CONTEXT_PRIORITY_LEVEL_IMG: + /* The EGL_IMG_context_priority spec says: + * + * "EGL_CONTEXT_PRIORITY_LEVEL_IMG determines the priority level of + * the context to be created. This attribute is a hint, as an + * implementation may not support multiple contexts at some + * priority levels and system policy may limit access to high + * priority con
Mesa (master): relnotes/17.3: EGL_IMG_context_priority is now implemented
Module: Mesa Branch: master Commit: aa65dcd1d7cc36192b05b41cd9e68b4f58aa51f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa65dcd1d7cc36192b05b41cd9e68b4f58aa51f6 Author: Chris Wilson Date: Wed May 3 15:42:35 2017 +0100 relnotes/17.3: EGL_IMG_context_priority is now implemented Suggested-by: Emil Velikov Signed-off-by: Chris Wilson Reviewed-by: Kenneth Graunke --- docs/relnotes/17.3.0.html | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/relnotes/17.3.0.html b/docs/relnotes/17.3.0.html index 61750194f7..b156158da5 100644 --- a/docs/relnotes/17.3.0.html +++ b/docs/relnotes/17.3.0.html @@ -52,6 +52,7 @@ Note: some of the new features are only available with certain drivers. GL_EXT_memory_object on radeonsi GL_EXT_memory_object_fd on radeonsi EGL_ANDROID_native_fence_sync on radeonsi with a future kernel (possibly 4.15) +EGL_IMG_context_priority on i965 Bug fixes ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): egl,dri: Propagate context priority hint to driver-> CreateContext
Module: Mesa Branch: master Commit: 5c5618338a3cf27343d1420fb78daec4b176b0d3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c5618338a3cf27343d1420fb78daec4b176b0d3 Author: Chris Wilson Date: Thu Oct 27 19:54:49 2016 +0100 egl,dri: Propagate context priority hint to driver->CreateContext Jump through the layers of abstraction between egl and dri in order to feed the context priority attribute through to the backend. This requires us to read the value from the base _egl_context, convert it to a DRI attribute, parse it again in the generic context creator before passing it to the driver as a function parameter. In order to not require us to pass back the actual value of the context priority after creation, we impose that drivers should report the available set of priorities during screen setup (and then they may chose to fail if given an invalid value as that should have been checked at the user boundary.) Signed-off-by: Chris Wilson Acked-by: Ben Widawsky # i915/i965 Reviewed-by: Emil Velikov Reviewed-by: Eric Engestrom Reviewed-by: Kenneth Graunke --- include/GL/internal/dri_interface.h| 6 src/egl/drivers/dri2/egl_dri2.c| 38 +- src/gallium/state_trackers/dri/dri_context.c | 1 + src/gallium/state_trackers/dri/dri_context.h | 1 + src/mesa/drivers/dri/common/dri_util.c | 7 - src/mesa/drivers/dri/common/dri_util.h | 9 +++--- src/mesa/drivers/dri/i915/intel_screen.c | 11 src/mesa/drivers/dri/i965/brw_context.c| 7 +++-- src/mesa/drivers/dri/i965/brw_context.h| 17 ++-- src/mesa/drivers/dri/nouveau/nouveau_context.c | 1 + src/mesa/drivers/dri/nouveau/nouveau_context.h | 4 +-- src/mesa/drivers/dri/r200/r200_context.c | 1 + src/mesa/drivers/dri/r200/r200_context.h | 1 + src/mesa/drivers/dri/radeon/radeon_context.c | 1 + src/mesa/drivers/dri/radeon/radeon_context.h | 1 + src/mesa/drivers/dri/swrast/swrast.c | 1 + 16 files changed, 77 insertions(+), 30 deletions(-) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index 7ed0169a98..98402eae05 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -1100,6 +1100,12 @@ struct __DRIdri2LoaderExtensionRec { #define __DRI_CTX_RESET_LOSE_CONTEXT 1 /*@}*/ +#define __DRI_CTX_ATTRIB_PRIORITY 4 + +#define __DRI_CTX_PRIORITY_LOW 0 +#define __DRI_CTX_PRIORITY_MEDIUM 1 +#define __DRI_CTX_PRIORITY_HIGH2 + /** * \name Reasons that __DRIdri2Extension::createContextAttribs might fail */ diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index e18e05e4a9..503450542e 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -92,6 +92,8 @@ #define DRM_FORMAT_MOD_INVALID ((1ULL<<56) - 1) #endif +#define NUM_ATTRIBS 10 + static void dri_set_background_context(void *loaderPrivate) { @@ -1166,7 +1168,7 @@ dri2_fill_context_attribs(struct dri2_egl_context *dri2_ctx, { int pos = 0; - assert(*num_attribs >= 8); + assert(*num_attribs >= NUM_ATTRIBS); ctx_attribs[pos++] = __DRI_CTX_ATTRIB_MAJOR_VERSION; ctx_attribs[pos++] = dri2_ctx->base.ClientMajorVersion; @@ -1203,6 +1205,28 @@ dri2_fill_context_attribs(struct dri2_egl_context *dri2_ctx, ctx_attribs[pos++] = __DRI_CTX_RESET_LOSE_CONTEXT; } + if (dri2_ctx->base.ContextPriority != EGL_CONTEXT_PRIORITY_MEDIUM_IMG) { + unsigned val; + + switch (dri2_ctx->base.ContextPriority) { + case EGL_CONTEXT_PRIORITY_HIGH_IMG: + val = __DRI_CTX_PRIORITY_HIGH; + break; + case EGL_CONTEXT_PRIORITY_MEDIUM_IMG: + val = __DRI_CTX_PRIORITY_MEDIUM; + break; + case EGL_CONTEXT_PRIORITY_LOW_IMG: + val = __DRI_CTX_PRIORITY_LOW; + break; + default: + _eglError(EGL_BAD_CONFIG, "eglCreateContext"); + return false; + } + + ctx_attribs[pos++] = __DRI_CTX_ATTRIB_PRIORITY; + ctx_attribs[pos++] = val; + } + *num_attribs = pos; return true; @@ -1317,8 +1341,8 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf, if (dri2_dpy->image_driver) { unsigned error; - unsigned num_attribs = 8; - uint32_t ctx_attribs[8]; + unsigned num_attribs = NUM_ATTRIBS; + uint32_t ctx_attribs[NUM_ATTRIBS]; if (!dri2_fill_context_attribs(dri2_ctx, dri2_dpy, ctx_attribs, &num_attribs)) @@ -1337,8 +1361,8 @@ dri2_create_context(_EGLDriver *drv, _EGLDisplay *disp, _EGLConfig *conf, } else if (dri2_dpy->dri2) { if (dri2_dpy->dri2->base.version >= 3) { unsigned error; - unsigned num_attribs = 8; - uint32_t ctx_attribs[8]; + u
Mesa (master): i965: Record the presence of the kernel scheduler
Module: Mesa Branch: master Commit: 21023954f898bf871696e6e0eae2848e019fb2f9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21023954f898bf871696e6e0eae2848e019fb2f9 Author: Chris Wilson Date: Wed Sep 27 16:14:33 2017 +0100 i965: Record the presence of the kernel scheduler Mention to the debug log if the kernel scheduler is enabled; and in particular if it has preemption enabled. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Ben Widawsky Reviewed-by: Joonas Lahtinen Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_screen.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index ea04a72e86..28e83cf9b2 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -2518,6 +2518,17 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) intel_screen_init_surface_formats(screen); + if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) { + unsigned int caps = intel_get_integer(screen, I915_PARAM_HAS_SCHEDULER); + if (caps) { + fprintf(stderr, "Kernel scheduler detected: %08x\n", caps); + if (caps & I915_SCHEDULER_CAP_PRIORITY) +fprintf(stderr, " - User priority sorting enabled\n"); + if (caps & I915_SCHEDULER_CAP_PREEMPTION) +fprintf(stderr, " - Preemption enabled\n"); + } + } + return (const __DRIconfig**) intel_screen_make_configs(dri_screen); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Sync i915_drm.h from kernel for IMG_context_priority
Module: Mesa Branch: master Commit: 98c2b7f9fa1748acb06321f74ec69361d4c8b57d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98c2b7f9fa1748acb06321f74ec69361d4c8b57d Author: Chris Wilson Date: Wed Sep 27 18:37:07 2017 +0100 i965: Sync i915_drm.h from kernel for IMG_context_priority Pulling in changes up to kernel commit ac14fbd460d0ec16e7750e40dcd8199b0ff83d0a Author: Chris Wilson Date: Tue Oct 3 21:34:53 2017 +0100 drm/i915/scheduler: Support user-defined priorities and including the fixup from kernel commit 822a4b673284672af697ccd66e8795f8a712a90d Author: Joonas Lahtinen Date: Fri Oct 6 13:45:59 2017 +0300 drm/i915: Don't use BIT() in UAPI section for implementing IMG_context_priority. Signed-off-by: Chris Wilson Reviewed-by: Kenneth Graunke --- include/drm-uapi/i915_drm.h | 27 --- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/include/drm-uapi/i915_drm.h b/include/drm-uapi/i915_drm.h index 1ad52282c8..890df227ae 100644 --- a/include/drm-uapi/i915_drm.h +++ b/include/drm-uapi/i915_drm.h @@ -397,10 +397,20 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_MIN_EU_IN_POOL 39 #define I915_PARAM_MMAP_GTT_VERSION 40 -/* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution +/* + * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution * priorities and the driver will attempt to execute batches in priority order. + * The param returns a capability bitmask, nonzero implies that the scheduler + * is enabled, with different features present according to the mask. + * + * The initial priority for each batch is supplied by the context and is + * controlled via I915_CONTEXT_PARAM_PRIORITY. */ #define I915_PARAM_HAS_SCHEDULER41 +#define I915_SCHEDULER_CAP_ENABLED (1ul << 0) +#define I915_SCHEDULER_CAP_PRIORITY (1ul << 1) +#define I915_SCHEDULER_CAP_PREEMPTION(1ul << 2) + #define I915_PARAM_HUC_STATUS 42 /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of @@ -1308,14 +1318,16 @@ struct drm_i915_reg_read { * be specified */ __u64 offset; +#define I915_REG_READ_8B_WA (1ul << 0) + __u64 val; /* Return value */ }; /* Known registers: * * Render engine timestamp - 0x2358 + 64bit - gen7+ * - Note this register returns an invalid value if using the default - * single instruction 8byte read, in order to workaround that use - * offset (0x2538 | 1) instead. + * single instruction 8byte read, in order to workaround that pass + * flag I915_REG_READ_8B_WA in offset field. * */ @@ -1358,6 +1370,10 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_GTT_SIZE0x3 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE0x4 #define I915_CONTEXT_PARAM_BANNABLE0x5 +#define I915_CONTEXT_PARAM_PRIORITY0x6 +#define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */ +#define I915_CONTEXT_DEFAULT_PRIORITY0 +#define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */ __u64 value; }; @@ -1509,6 +1525,11 @@ struct drm_i915_perf_oa_config { __u32 n_boolean_regs; __u32 n_flex_regs; + /* +* These fields are pointers to tuples of u32 values (register +* address, value). For example the expected length of the buffer +* pointed by mux_regs_ptr is (2 * sizeof(u32) * n_mux_regs). +*/ __u64 mux_regs_ptr; __u64 boolean_regs_ptr; __u64 flex_regs_ptr; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Pass the EGL/ DRI context priority through to the kernel
Module: Mesa Branch: master Commit: 1617fca6d12e418e02d18733dd0d1964c7ecbda9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1617fca6d12e418e02d18733dd0d1964c7ecbda9 Author: Chris Wilson Date: Tue Apr 11 15:24:54 2017 +0100 i965: Pass the EGL/DRI context priority through to the kernel Decode the EGL/DRI priority enum into the [-1023, 1023] range as interpreted by the kernel and call DRM_I915_GEM_CONTEXT_SETPARAM to adjust the priority. We use 0 as the default medium priority (also the kernel default) and so only need adjust up or down. By only doing the adjustment if not setting to medium, we can faithfully report any error whilst setting without worrying about kernel version. Signed-off-by: Chris Wilson Cc: Kenneth Graunke Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 19 +++ src/mesa/drivers/dri/i965/brw_bufmgr.h | 9 + src/mesa/drivers/dri/i965/brw_context.c | 18 ++ 3 files changed, 46 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 7c5a9651eb..17036b53bc 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -1299,6 +1299,25 @@ brw_create_hw_context(struct brw_bufmgr *bufmgr) return create.ctx_id; } +int +brw_hw_context_set_priority(struct brw_bufmgr *bufmgr, +uint32_t ctx_id, +int priority) +{ + struct drm_i915_gem_context_param p = { + .ctx_id = ctx_id, + .param = I915_CONTEXT_PARAM_PRIORITY, + .value = priority, + }; + int err; + + err = 0; + if (drmIoctl(bufmgr->fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &p)) + err = -errno; + + return err; +} + void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id) { diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h b/src/mesa/drivers/dri/i965/brw_bufmgr.h index de0ba1dad1..ee91324043 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.h +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h @@ -322,6 +322,15 @@ void brw_bufmgr_enable_reuse(struct brw_bufmgr *bufmgr); int brw_bo_wait(struct brw_bo *bo, int64_t timeout_ns); uint32_t brw_create_hw_context(struct brw_bufmgr *bufmgr); + +#define BRW_CONTEXT_LOW_PRIORITY ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2) +#define BRW_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY) +#define BRW_CONTEXT_HIGH_PRIORITY ((I915_CONTEXT_MAX_USER_PRIORITY+1)/2) + +int brw_hw_context_set_priority(struct brw_bufmgr *bufmgr, +uint32_t ctx_id, +int priority); + void brw_destroy_hw_context(struct brw_bufmgr *bufmgr, uint32_t ctx_id); int brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd); diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index a86367cc46..c8de074638 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -956,6 +956,24 @@ brwCreateContext(gl_api api, intelDestroyContext(driContextPriv); return false; } + + int hw_priority = BRW_CONTEXT_MEDIUM_PRIORITY; + switch (priority) { + case __DRI_CTX_PRIORITY_LOW: + hw_priority = BRW_CONTEXT_LOW_PRIORITY; + break; + case __DRI_CTX_PRIORITY_HIGH: + hw_priority = BRW_CONTEXT_HIGH_PRIORITY; + break; + } + if (hw_priority != I915_CONTEXT_DEFAULT_PRIORITY && + brw_hw_context_set_priority(brw->bufmgr, brw->hw_ctx, hw_priority)) { + fprintf(stderr, +"Failed to set priority [%d:%d] for hardware context.\n", + priority, hw_priority); + intelDestroyContext(driContextPriv); + return false; + } } if (brw_init_pipe_control(brw, devinfo)) { ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Do not log a perf warning when mapping an idle bo
Module: Mesa Branch: master Commit: b7c655f700d5e12d3cd81b1cb66fce17019f934d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7c655f700d5e12d3cd81b1cb66fce17019f934d Author: Chris Wilson Date: Wed Oct 18 09:49:31 2017 +0100 i965: Do not log a perf warning when mapping an idle bo We only want to scare the user away from causing a GPU stall for mapping a busy bo. The time taken to instantiate the set of pages for a buffer and their mmapping is unavoidable and flagging idle bo as being busy is "crying wolf". Reported-by: Tvrtko Ursulin Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 82bf30727e..7c5a9651eb 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -669,11 +669,12 @@ bo_wait_with_stall_warning(struct brw_context *brw, struct brw_bo *bo, const char *action) { - double elapsed = unlikely(brw && brw->perf_debug) ? -get_time() : 0.0; + bool busy = brw && brw->perf_debug && !bo->idle; + double elapsed = unlikely(busy) ? -get_time() : 0.0; brw_bo_wait_rendering(bo); - if (unlikely(brw && brw->perf_debug)) { + if (unlikely(busy)) { elapsed += get_time(); if (elapsed > 1e-5) /* 0.01ms */ perf_debug("%s a busy \"%s\" BO stalled and took %.03f ms.\n", ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Prefer using streaming reads from WC mmaps
Module: Mesa Branch: master Commit: b4f639d02ae5fb54ab7f449c86c8bb602517455c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4f639d02ae5fb54ab7f449c86c8bb602517455c Author: Chris Wilson Date: Sat Jul 22 10:28:14 2017 +0100 i965: Prefer using streaming reads from WC mmaps For buffer objects, where we primarily expect to be writing to them and so already have a WC mmap (for !llc access) reusing the existing mmap and keeping the buffer out of the CPU cache seems preferable. Cc: Kenneth Graunke Cc: Matt Turner Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 18 +++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c index e932badaaf..ee59116828 100644 --- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c @@ -32,12 +32,15 @@ #include "main/imports.h" #include "main/mtypes.h" #include "main/macros.h" +#include "main/streaming-load-memcpy.h" #include "main/bufferobj.h" +#include "x86/common_x86_asm.h" #include "brw_context.h" #include "intel_blit.h" #include "intel_buffer_objects.h" #include "intel_batchbuffer.h" +#include "intel_tiled_memcpy.h" static void mark_buffer_gpu_usage(struct intel_buffer_object *intel_obj, @@ -337,14 +340,23 @@ brw_get_buffer_subdata(struct gl_context *ctx, intel_batchbuffer_flush(brw); } - void *map = brw_bo_map(brw, intel_obj->buffer, MAP_READ); + unsigned int map_flags = MAP_READ; + mem_copy_fn memcpy_fn = memcpy; + if (!intel_obj->buffer->cache_coherent && cpu_has_sse4_1) { + /* Rather than acquire a new WB mmaping of the buffer object and pull + * it into the CPU cache, keep using the WC mmap that we have for writes, + * and use the magic movntd instructions instead. + */ + map_flags |= MAP_COHERENT; + memcpy_fn = (mem_copy_fn) _mesa_streaming_load_memcpy; + } + void *map = brw_bo_map(brw, intel_obj->buffer, map_flags); if (unlikely(!map)) { _mesa_error_no_memory(__func__); return; } - - memcpy(data, map + offset, size); + memcpy_fn(data, map + offset, size); brw_bo_unmap(intel_obj->buffer); mark_buffer_inactive(intel_obj); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Resolve framebuffers before signaling the fence
Module: Mesa Branch: master Commit: 618be8cc1ad1760103930b69ffbf528d7b861ab3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=618be8cc1ad1760103930b69ffbf528d7b861ab3 Author: Chris Wilson Date: Mon Jun 12 15:17:20 2017 +0100 i965: Resolve framebuffers before signaling the fence From KHR_fence_sync: When the condition of the sync object is satisfied by the fence command, the sync is signaled by the associated client API context, causing any eglClientWaitSyncKHR commands (see below) blocking on to unblock. The only condition currently supported is EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by completion of the fence command corresponding to the sync object, and all preceding commands in the associated client API context's command stream. The sync object will not be signaled until all effects from these commands on the client API's internal and framebuffer state are fully realized. No other state is affected by execution of the fence command. If clients are passing the fence fd (from EGL_ANDROID_native_fence_sync) to a compositor, that fence must only be signaled once the framebuffer is resolved and not before as is currently the case. v2: fixup assert to use GL_SYNC_GPU_COMMANDS_COMPLETE (Chad) Reported-by: Sergi Granell Fixes: c636284ee8ee ("i965/sync: Implement DRI2_Fence extension") Signed-off-by: Chris Wilson Cc: Sergi Granell Cc: Rob Clark Cc: Chad Versace Cc: Daniel Stone Cc: Kenneth Graunke Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_sync.c | 32 1 file changed, 32 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_sync.c b/src/mesa/drivers/dri/i965/brw_sync.c index a8356c304f..edfb1881bc 100644 --- a/src/mesa/drivers/dri/i965/brw_sync.c +++ b/src/mesa/drivers/dri/i965/brw_sync.c @@ -110,6 +110,35 @@ brw_fence_finish(struct brw_fence *fence) static bool MUST_CHECK brw_fence_insert_locked(struct brw_context *brw, struct brw_fence *fence) { + __DRIcontext *driContext = brw->driContext; + __DRIdrawable *driDrawable = driContext->driDrawablePriv; + + /* +* From KHR_fence_sync: +* +* When the condition of the sync object is satisfied by the fence +* command, the sync is signaled by the associated client API context, +* causing any eglClientWaitSyncKHR commands (see below) blocking on +*to unblock. The only condition currently supported is +* EGL_SYNC_PRIOR_COMMANDS_COMPLETE_KHR, which is satisfied by +* completion of the fence command corresponding to the sync object, +* and all preceding commands in the associated client API context's +* command stream. The sync object will not be signaled until all +* effects from these commands on the client API's internal and +* framebuffer state are fully realized. No other state is affected by +* execution of the fence command. +* +* Note the emphasis there on ensuring that the framebuffer is fully +* realised before the fence is signaled. We cannot just flush the batch, +* but must also resolve the drawable first. The importance of this is, +* for example, in creating a fence for a frame to be passed to a +* remote compositor. Without us flushing the drawable explicitly, the +* resolve will be in a following batch (when the client finally calls +* SwapBuffers, or triggers a resolve via some other path) and so the +* compositor may read the incomplete framebuffer instead. +*/ + if (driDrawable) + intel_resolve_for_dri2_flush(brw, driDrawable); brw_emit_mi_flush(brw); switch (fence->type) { @@ -335,6 +364,9 @@ brw_gl_fence_sync(struct gl_context *ctx, struct gl_sync_object *_sync, struct brw_context *brw = brw_context(ctx); struct brw_gl_sync *sync = (struct brw_gl_sync *) _sync; + /* brw_fence_insert_locked() assumes it must do a complete flush */ + assert(condition == GL_SYNC_GPU_COMMANDS_COMPLETE); + brw_fence_init(brw, &sync->fence, BRW_FENCE_TYPE_BO_WAIT); if (!brw_fence_insert_locked(brw, &sync->fence)) { ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Mark freshly allocate bo as idle
Module: Mesa Branch: master Commit: 05d5caffc402f532502b7b8e301a80ef140b7317 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=05d5caffc402f532502b7b8e301a80ef140b7317 Author: Chris Wilson Date: Fri Jun 9 00:35:09 2017 +0100 i965: Mark freshly allocate bo as idle When created, buffers are idle, so mark them as such to save an early ioctl or mistakenly assuming the fresh buffer is busy. Signed-off-by: Chris Wilson Cc: Kenneth Graunke Cc: Matt Turner Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index 42cc0c28f3..6cb91f9a23 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -324,6 +324,7 @@ retry: goto err; bo->size = bo_size; + bo->idle = true; memclear(create); create.size = bo_size; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Order write of query availablity with earlier writes
Module: Mesa Branch: master Commit: 8d07cb125c6afc11b6b8c7a97ec848868814b1d6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d07cb125c6afc11b6b8c7a97ec848868814b1d6 Author: Chris Wilson Date: Thu Oct 6 21:07:18 2016 +0100 i965: Order write of query availablity with earlier writes Currently we signal the availabilty of the query result using an unordered pipe-control write. As it is unordered, it may be executed before the write of the query result itself - and so an observer may read the query result too early. Fix this by requesting that the write of the availablity flag is ordered after earlier pipe control writes. Testcase: piglit/arb_query_buffer_object-qbo/*async* Signed-off-by: Chris Wilson Reviewed-by: Alejandro Piñeiro --- src/mesa/drivers/dri/i965/gen6_queryobj.c | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c index cb4f46c28b..a28f83af1d 100644 --- a/src/mesa/drivers/dri/i965/gen6_queryobj.c +++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c @@ -60,8 +60,17 @@ set_query_availability(struct brw_context *brw, struct brw_query_object *query, */ if (brw->ctx.Extensions.ARB_query_buffer_object && brw_is_query_pipelined(query)) { - brw_emit_pipe_control_write(brw, - PIPE_CONTROL_WRITE_IMMEDIATE, + unsigned flags = PIPE_CONTROL_WRITE_IMMEDIATE; + + if (available) { + /* Order available *after* the query results. */ + flags |= PIPE_CONTROL_FLUSH_ENABLE; + } else { + /* Make it unavailable *before* any pipelined reads. */ + flags |= PIPE_CONTROL_CS_STALL; + } + + brw_emit_pipe_control_write(brw, flags, query->bo, 2 * sizeof(uint64_t), available, 0); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Embrace "unlimited" GTT mmap support
Module: Mesa Branch: master Commit: f92a87a14068dd17a32b41b1586421cef6eaa37f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f92a87a14068dd17a32b41b1586421cef6eaa37f Author: Chris Wilson Date: Wed Aug 24 20:35:46 2016 +0100 i965: Embrace "unlimited" GTT mmap support From about kernel 4.9, GTT mmaps are virtually unlimited. A new parameter, I915_PARAM_MMAP_GTT_VERSION, is added to advertise the feature so query it and use it to avoid limiting tiled allocations to only fit within the mappable aperture. A couple of caveats: - fence support is still limited by stride to 262144 and the stride needs to be a multiple of tile_width (as before, and same limitation as the current 3D pipeline in hardware) - the max_gtt_map_object_size forcing untiled may be hiding a few bugs in handling of large objects, though none were spotted in piglits. See kernel commit 4cc6907501ed ("drm/i915: Add I915_PARAM_MMAP_GTT_VERSION to advertise unlimited mmaps"). v2: Include some commentary on mmap virtual space vs CPU addressable space. Signed-off-by: Chris Wilson Cc: Kenneth Graunke Reviewed-by: Kenneth Graunke Reviewed-by: Daniel Vetter --- src/mesa/drivers/dri/i965/brw_context.c | 17 ++- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 48 src/mesa/drivers/dri/i965/intel_screen.h | 2 ++ 4 files changed, 53 insertions(+), 16 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index d6f0d7b..1364393 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1044,21 +1044,6 @@ brwCreateContext(gl_api api, brw->urb.max_ds_entries = devinfo->urb.max_ds_entries; brw->urb.max_gs_entries = devinfo->urb.max_gs_entries; - /* Estimate the size of the mappable aperture into the GTT. There's an -* ioctl to get the whole GTT size, but not one to get the mappable subset. -* It turns out it's basically always 256MB, though some ancient hardware -* was smaller. -*/ - uint32_t gtt_size = 256 * 1024 * 1024; - - /* We don't want to map two objects such that a memcpy between them would -* just fault one mapping in and then the other over and over forever. So -* we would need to divide the GTT size by 2. Additionally, some GTT is -* taken up by things like the framebuffer and the ringbuffer and such, so -* be more conservative. -*/ - brw->max_gtt_map_object_size = gtt_size / 4; - if (brw->gen == 6) brw->urb.gs_present = false; @@ -1069,6 +1054,8 @@ brwCreateContext(gl_api api, brw->predicate.state = BRW_PREDICATE_STATE_RENDER; + brw->max_gtt_map_object_size = screen->max_gtt_map_object_size; + brw->use_resource_streamer = screen->has_resource_streamer && (env_var_as_boolean("INTEL_USE_HW_BT", false) || env_var_as_boolean("INTEL_USE_GATHER", false)); diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index e0f7000..1a4efa3 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -853,7 +853,7 @@ struct brw_context */ bool perf_debug; - uint32_t max_gtt_map_object_size; + uint64_t max_gtt_map_object_size; int gen; int gt; diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 7876652..cb007d7 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -995,6 +995,17 @@ intel_get_boolean(struct intel_screen *screen, int param) return (intel_get_param(screen, param, &value) == 0) && value; } +static int +intel_get_integer(struct intel_screen *screen, int param) +{ + int value = -1; + + if (intel_get_param(screen, param, &value) == 0) + return value; + + return -1; +} + static void intelDestroyScreen(__DRIscreen * sPriv) { @@ -1565,6 +1576,43 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) if (INTEL_DEBUG & DEBUG_AUB) drm_intel_bufmgr_gem_set_aub_dump(intelScreen->bufmgr, true); +#ifndef I915_PARAM_MMAP_GTT_VERSION +#define I915_PARAM_MMAP_GTT_VERSION 40 /* XXX delete me with new libdrm */ +#endif + if (intel_get_integer(intelScreen, I915_PARAM_MMAP_GTT_VERSION) >= 1) { + /* Theorectically unlimited! At least for individual objects... + * + * Currently the entire (global) address space for all GTT maps is + * limited to 64bits. That is all objects on the system that are + * setup for GTT mmapping must fit within 64bits. An attempt to use + * one that exceeds the limit with fail in drm_intel_bo_map_gtt(). + * + * Long before we hit that limit, we will be practically limited by + * that any single object must fit in physi
Mesa (master): i965: Disallow fast blit paths for CopyTexImage with PixelTransfer ops
Module: Mesa Branch: master Commit: be519c2d50f4aaa48fdb8b27707114cc5bfd348f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be519c2d50f4aaa48fdb8b27707114cc5bfd348f Author: Chris Wilson Date: Sat Sep 5 19:19:33 2015 +0100 i965: Disallow fast blit paths for CopyTexImage with PixelTransfer ops glCopyTexImage behaves similarly to glReadPixels with respect to the pixel transfer operations. Therefore if any are set we cannot use the simple blit-only fast paths. (Though if would be possible to relax the blorp path to handle pixel zoom, or we can just enhance meta.) Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Kenneth Graunke Reviwewed-by: Iago Toral Reviewed-by: Kenneth Graunke Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |4 src/mesa/drivers/dri/i965/intel_tex_copy.c |4 2 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp index 205c905..ba11d3d 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp @@ -215,6 +215,10 @@ brw_blorp_copytexsubimage(struct brw_context *brw, struct intel_renderbuffer *src_irb = intel_renderbuffer(src_rb); struct intel_texture_image *intel_image = intel_texture_image(dst_image); + /* No pixel transfer operations (zoom, bias, mapping), just a blit */ + if (brw->ctx._ImageTransferState) + return false; + /* Sync up the state of window system buffers. We need to do this before * we go looking at the src renderbuffer's miptree. */ diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c b/src/mesa/drivers/dri/i965/intel_tex_copy.c index 4d8c82e..ecdd052 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_copy.c +++ b/src/mesa/drivers/dri/i965/intel_tex_copy.c @@ -55,6 +55,10 @@ intel_copy_texsubimage(struct brw_context *brw, const GLenum internalFormat = intelImage->base.Base.InternalFormat; bool ret; + /* No pixel transfer operations (zoom, bias, mapping), just a blit */ + if (brw->ctx._ImageTransferState) + return false; + intel_prepare_render(brw); /* glCopyTexSubImage() can be called on a multisampled renderbuffer (if ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Disallow PixelTransfer operations for tiled-memcpy TexImage/ReadPixels
Module: Mesa Branch: master Commit: 099f5b3a62be1919add02a4cb887841c9f0f2fe4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=099f5b3a62be1919add02a4cb887841c9f0f2fe4 Author: Chris Wilson Date: Fri Sep 4 19:02:28 2015 +0100 i965: Disallow PixelTransfer operations for tiled-memcpy TexImage/ReadPixels The tiled memcpy fast paths perform a simple blit (with only a couple of trivial pixel conversion routines) and do not accommodate PixelTransfer operations. Therefore if any are set, fallback to the regular routines. Note that PixelTransfer only applies to TexImage and ReadPixels, not to GetTexImage. Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Kenneth Graunke Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/intel_pixel_read.c |4 src/mesa/drivers/dri/i965/intel_tex_subimage.c |4 2 files changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 3fe506e..eb366cd 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -109,6 +109,10 @@ intel_readpixels_tiled_memcpy(struct gl_context * ctx, pack->Invert) return false; + /* Only a simple blit, no scale, bias or other mapping. */ + if (ctx->_ImageTransferState) + return false; + /* This renderbuffer can come from a texture. In this case, we impose * some of the same restrictions we have for textures and adjust for * miplevels. diff --git a/src/mesa/drivers/dri/i965/intel_tex_subimage.c b/src/mesa/drivers/dri/i965/intel_tex_subimage.c index 31e511f..44921e5 100644 --- a/src/mesa/drivers/dri/i965/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/i965/intel_tex_subimage.c @@ -118,6 +118,10 @@ intel_texsubimage_tiled_memcpy(struct gl_context * ctx, packing->Invert) return false; + /* Only a simple blit, no scale, bias or other mapping. */ + if (ctx->_ImageTransferState) + return false; + if (!intel_get_memcpy(texImage->TexFormat, format, type, &mem_copy, &cpp, INTEL_UPLOAD)) return false; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta: Compute correct buffer size with SkipRows/SkipPixels
Module: Mesa Branch: master Commit: f30cf3258e495a583e011e07d5b4a19031c5518f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f30cf3258e495a583e011e07d5b4a19031c5518f Author: Chris Wilson Date: Tue Sep 1 09:31:15 2015 +0100 meta: Compute correct buffer size with SkipRows/SkipPixels If the user is specifying a subregion of a buffer using SKIP_ROWS and SKIP_PIXELS, we must compute the buffer size carefully as the end of the last row may be much shorter than stride*image_height*depth. The current code tries to memcpy from beyond the end of the user data, for example causing: ==28136== Invalid read of size 8 ==28136==at 0x4C2D94E: memcpy@@GLIBC_2.14 (vg_replace_strmem.c:915) ==28136==by 0xB4ADFE3: brw_bo_write (brw_batch.c:1856) ==28136==by 0xB5B3531: brw_buffer_data (intel_buffer_objects.c:208) ==28136==by 0xB0F6275: _mesa_buffer_data (bufferobj.c:1600) ==28136==by 0xB0F6346: _mesa_BufferData (bufferobj.c:1631) ==28136==by 0xB37A1EE: create_texture_for_pbo (meta_tex_subimage.c:103) ==28136==by 0xB37A467: _mesa_meta_pbo_TexSubImage (meta_tex_subimage.c:176) ==28136==by 0xB5C8D61: intelTexSubImage (intel_tex_subimage.c:195) ==28136==by 0xB254AB4: _mesa_texture_sub_image (teximage.c:3654) ==28136==by 0xB254C9F: texsubimage (teximage.c:3712) ==28136==by 0xB2550E9: _mesa_TexSubImage2D (teximage.c:3853) ==28136==by 0x401CA0: UploadTexSubImage2D (teximage.c:171) ==28136== Address 0xd8bfbe0 is 0 bytes after a block of size 1,024 alloc'd ==28136==at 0x4C28C20: malloc (vg_replace_malloc.c:296) ==28136==by 0x402014: PerfDraw (teximage.c:270) ==28136==by 0x402648: Draw (glmain.c:182) ==28136==by 0x8385E63: ??? (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x83896C8: fgEnumWindows (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x838641C: glutMainLoopEvent (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x8386C1C: glutMainLoop (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x4019C1: main (glmain.c:262) ==28136== ==28136== Invalid read of size 8 ==28136==at 0x4C2D940: memcpy@@GLIBC_2.14 (vg_replace_strmem.c:915) ==28136==by 0xB4ADFE3: brw_bo_write (brw_batch.c:1856) ==28136==by 0xB5B3531: brw_buffer_data (intel_buffer_objects.c:208) ==28136==by 0xB0F6275: _mesa_buffer_data (bufferobj.c:1600) ==28136==by 0xB0F6346: _mesa_BufferData (bufferobj.c:1631) ==28136==by 0xB37A1EE: create_texture_for_pbo (meta_tex_subimage.c:103) ==28136==by 0xB37A467: _mesa_meta_pbo_TexSubImage (meta_tex_subimage.c:176) ==28136==by 0xB5C8D61: intelTexSubImage (intel_tex_subimage.c:195) ==28136==by 0xB254AB4: _mesa_texture_sub_image (teximage.c:3654) ==28136==by 0xB254C9F: texsubimage (teximage.c:3712) ==28136==by 0xB2550E9: _mesa_TexSubImage2D (teximage.c:3853) ==28136==by 0x401CA0: UploadTexSubImage2D (teximage.c:171) ==28136== Address 0xd8bfbe8 is 8 bytes after a block of size 1,024 alloc'd ==28136==at 0x4C28C20: malloc (vg_replace_malloc.c:296) ==28136==by 0x402014: PerfDraw (teximage.c:270) ==28136==by 0x402648: Draw (glmain.c:182) ==28136==by 0x8385E63: ??? (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x83896C8: fgEnumWindows (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x838641C: glutMainLoopEvent (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x8386C1C: glutMainLoop (in /usr/lib/x86_64-linux-gnu/libglut.so.3.9.0) ==28136==by 0x4019C1: main (glmain.c:262) ==28136== Fixes regression from commit 7f396189f073d626c5f7a2c232dac92b65f5a23f Author: Jason Ekstrand Date: Mon Jan 5 18:17:04 2015 -0800 meta: Add a BlitFramebuffers-based implementation of TexSubImage v2: However, the teximage we create does need to be width x full_height x 1 Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Neil Roberts Reviewed-by Neil Roberts --- src/mesa/drivers/common/meta_tex_subimage.c | 45 ++- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/src/mesa/drivers/common/meta_tex_subimage.c b/src/mesa/drivers/common/meta_tex_subimage.c index 16d8f5d..33c22aa 100644 --- a/src/mesa/drivers/common/meta_tex_subimage.c +++ b/src/mesa/drivers/common/meta_tex_subimage.c @@ -46,8 +46,9 @@ #include "varray.h" static struct gl_texture_image * -create_texture_for_pbo(struct gl_context *ctx, bool create_pbo, - GLenum pbo_target, int width, int height, +create_texture_for_pbo(struct gl_context *ctx, + bool create_pbo, GLenum pbo_target, + int dims, int width, int height, int depth, GLenum format, GLenum type, const void *pixels, const struct gl_pixelstore_attrib *packing, GLuint *tmp_pbo, GLuint *tmp_tex) @@ -73,13 +74,18 @@ create_texture_for_pbo(struct gl_context *ctx, bool create_pbo
Mesa (master): i965: Prevent coordinate overflow in intel_emit_linear_blit
Module: Mesa Branch: master Commit: d38a5601068ae1d923efece8f2875f4474e4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d38a5601068ae1d923efece8f2875f4474e4 Author: Chris Wilson Date: Sat Jun 6 09:33:33 2015 +0100 i965: Prevent coordinate overflow in intel_emit_linear_blit Fixes regression from commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1 Author: Kenneth Graunke Date: Wed Apr 15 03:04:33 2015 -0700 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. which adjusted the coordinates to be relative to the nearest cacheline. However, this then offsets the coordinates by up to 63 and this may then cause them to overflow the BLT limits. For the well aligned large transfer case, we can use 32bpp pixels and so reduce the coordinates by 4 (versus the current 8bpp pixels). We also have to be more careful doing the last line just in case it may exceed the coordinate limit. Reported-and-tested-by: kaillass...@hotmail.fr Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by: Chris Wilson Cc: Kenneth Graunke Cc: Ian Romanick Cc: Anuj Phogat Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Anuj Phogat --- src/mesa/drivers/dri/i965/intel_blit.c | 72 +++- 1 file changed, 34 insertions(+), 38 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 6d92580..5a1da12 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -796,47 +796,43 @@ intel_emit_linear_blit(struct brw_context *brw, int16_t src_x, dst_x; bool ok; - /* The pitch given to the GPU must be DWORD aligned, and -* we want width to match pitch. Max width is (1 << 15 - 1), -* rounding that down to the nearest DWORD is 1 << 15 - 4 -*/ - pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4); - height = (pitch == 0) ? 1 : size / pitch; - src_x = src_offset % 64; - dst_x = dst_offset % 64; - ok = intelEmitCopyBlit(brw, 1, - pitch, src_bo, src_offset - src_x, I915_TILING_NONE, - INTEL_MIPTREE_TRMODE_NONE, - pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, - INTEL_MIPTREE_TRMODE_NONE, - src_x, 0, /* src x/y */ - dst_x, 0, /* dst x/y */ - pitch, height, /* w, h */ - GL_COPY); - if (!ok) - _mesa_problem(ctx, "Failed to linear blit %dx%d\n", pitch, height); - - src_offset += pitch * height; - dst_offset += pitch * height; - src_x = src_offset % 64; - dst_x = dst_offset % 64; - size -= pitch * height; - assert (size < (1 << 15)); - pitch = ALIGN(size, 4); - - if (size != 0) { + do { + /* The pitch given to the GPU must be DWORD aligned, and + * we want width to match pitch. Max width is (1 << 15 - 1), + * rounding that down to the nearest DWORD is 1 << 15 - 4 + */ + pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 64), 4); + height = (size < pitch || pitch == 0) ? 1 : size / pitch; + + src_x = src_offset % 64; + dst_x = dst_offset % 64; + pitch = ALIGN(MIN2(size, (1 << 15) - 64), 4); + assert(src_x + pitch < 1 << 15); + assert(dst_x + pitch < 1 << 15); + ok = intelEmitCopyBlit(brw, 1, -pitch, src_bo, src_offset - src_x, I915_TILING_NONE, + pitch, src_bo, src_offset - src_x, I915_TILING_NONE, INTEL_MIPTREE_TRMODE_NONE, -pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, + pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE, INTEL_MIPTREE_TRMODE_NONE, -src_x, 0, /* src x/y */ -dst_x, 0, /* dst x/y */ -size, 1, /* w, h */ -GL_COPY); - if (!ok) - _mesa_problem(ctx, "Failed to linear blit %dx%d\n", size, 1); - } + src_x, 0, /* src x/y */ + dst_x, 0, /* dst x/y */ + MIN2(size, pitch), height, /* w, h */ + GL_COPY); + if (!ok) { + _mesa_problem(ctx, "Failed to linear blit %dx%d\n", + MIN2(size, pitch), height); + return; + } + + pitch *= height; + if (size <= pitch) + return; + + src_offset += pitch; + dst_offset += pitch; + size -= pitch; + } while (1); } /** ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Always re-emit the pipeline select during invariant state emission
Module: Mesa Branch: master Commit: 4e5752e2b78243a71766538f62ca0a80488047a7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e5752e2b78243a71766538f62ca0a80488047a7 Author: Chris Wilson Date: Sun Aug 23 09:24:57 2015 +0100 i965: Always re-emit the pipeline select during invariant state emission On the older platforms where we don't have logical contexts preserving state across batches, we emit the invariant state setup on every batch using the brw_invariant_state atom. This includes the pipeline selection which is cached with the introduction of commit 0e0e23ef537c9add672ff322f34e129a07edc55e Author: Jordan Justen Date: Wed Apr 22 11:43:50 2015 -0700 i965/state: Emit pipeline select when changing pipelines However, we do not reset the cache between batches on context-less platforms resulting in us not setting the pipeline selection and can cause GPU hangs if a media pipelined was loaded in the meantime (e.g. mixing mplayer/gstreamer using libva and gnome-shell). A simple solution is to just forcibly re-emit the pipeline select along with the invariant state and reset the cache at that point. Reported-and-tested-by: Tomasz C. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254 Signed-off-by: Chris Wilson Cc: Jordan Justen Cc: Kenneth Graunke Reviewed-by: Jordan Justen Cc: "10.6 11.0" --- src/mesa/drivers/dri/i965/brw_misc_state.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index e9d9467..2751152 100644 --- a/src/mesa/drivers/dri/i965/brw_misc_state.c +++ b/src/mesa/drivers/dri/i965/brw_misc_state.c @@ -878,7 +878,8 @@ brw_upload_invariant_state(struct brw_context *brw) { const bool is_965 = brw->gen == 4 && !brw->is_g4x; - brw_select_pipeline(brw, BRW_RENDER_PIPELINE); + brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE); + brw->last_pipeline = BRW_RENDER_PIPELINE; if (brw->gen < 6) { /* Disable depth offset clamping. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Move control flush into pipelined conditional render
Module: Mesa Branch: master Commit: 6817e0f1ce71d2a6d347d4c182f2cf4742dd5deb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6817e0f1ce71d2a6d347d4c182f2cf4742dd5deb Author: Chris Wilson Date: Fri Aug 21 15:28:22 2015 +0100 i965: Move control flush into pipelined conditional render The nv_conditional_render piglits were sporadically failing. Moving the control flush from the write and placing it just before the read was sufficient to make the piglits pass a 1000/1000 times. The bspec says that the flush enable bit "waits until all previous writes of immediate data from post sync circles are complete before executing the next command" - the operative word being previous! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90691 Signed-off-by: Chris Wilson Cc: Neil Roberts Cc: Kenneth Graunke Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_conditional_render.c |6 ++ src/mesa/drivers/dri/i965/brw_queryobj.c | 19 +-- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_conditional_render.c b/src/mesa/drivers/dri/i965/brw_conditional_render.c index 6d37c3b..122a4ec 100644 --- a/src/mesa/drivers/dri/i965/brw_conditional_render.c +++ b/src/mesa/drivers/dri/i965/brw_conditional_render.c @@ -56,6 +56,12 @@ set_predicate_for_result(struct brw_context *brw, assert(query->bo != NULL); + /* Needed to ensure the memory is coherent for the MI_LOAD_REGISTER_MEM +* command when loading the values into the predicate source registers for +* conditional rendering. +*/ + brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE); + brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index d6b012c..a8e5aba 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -66,20 +66,11 @@ brw_write_timestamp(struct brw_context *brw, drm_intel_bo *query_bo, int idx) void brw_write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx) { - uint32_t flags; - - flags = (PIPE_CONTROL_WRITE_DEPTH_COUNT | -PIPE_CONTROL_DEPTH_STALL); - - /* Needed to ensure the memory is coherent for the MI_LOAD_REGISTER_MEM -* command when loading the values into the predicate source registers for -* conditional rendering. -*/ - if (brw->predicate.supported) - flags |= PIPE_CONTROL_FLUSH_ENABLE; - - brw_emit_pipe_control_write(brw, flags, query_bo, - idx * sizeof(uint64_t), 0, 0); + brw_emit_pipe_control_write(brw, + PIPE_CONTROL_WRITE_DEPTH_COUNT | + PIPE_CONTROL_DEPTH_STALL, + query_bo, idx * sizeof(uint64_t), + 0, 0); } /** ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix HW binding tables editing
Module: Mesa Branch: master Commit: ffadfbf5d076638fa4022106cfe989bc5a145f20 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffadfbf5d076638fa4022106cfe989bc5a145f20 Author: Chris Wilson Date: Wed Aug 5 13:58:46 2015 +0100 i965: Fix HW binding tables editing Since the introduction of new gl_shader_stages in commit a2af956963b6bc4d29f37485e44c98008d2ef077 Author: Fabian Bieler Date: Fri Mar 7 10:19:09 2014 +0100 mesa: add tessellation shader enums the translation table for the stage into the HW binding table edit command was broken, and so we used illegal commands. Fix the array initialisation to be impervious to changes in the gl_shader_stages enum and add the asserts that would have caught the issue earlier. Signed-off-by: Chris Wilson Cc: Abdiel Janulgue Cc: Jordan Justen Cc: Matt Turner Cc: Kenneth Graunke Reviewed-by: Matt Turner --- src/mesa/drivers/dri/i965/brw_binding_tables.c | 15 +-- 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c b/src/mesa/drivers/dri/i965/brw_binding_tables.c index 8d3697a..b188fc7 100644 --- a/src/mesa/drivers/dri/i965/brw_binding_tables.c +++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c @@ -44,10 +44,10 @@ #include "brw_state.h" #include "intel_batchbuffer.h" -static const GLuint stage_to_bt_edit[MESA_SHADER_FRAGMENT + 1] = { - _3DSTATE_BINDING_TABLE_EDIT_VS, - _3DSTATE_BINDING_TABLE_EDIT_GS, - _3DSTATE_BINDING_TABLE_EDIT_PS, +static const GLuint stage_to_bt_edit[] = { + [MESA_SHADER_VERTEX] = _3DSTATE_BINDING_TABLE_EDIT_VS, + [MESA_SHADER_GEOMETRY] = _3DSTATE_BINDING_TABLE_EDIT_GS, + [MESA_SHADER_FRAGMENT] = _3DSTATE_BINDING_TABLE_EDIT_PS, }; static uint32_t @@ -233,7 +233,8 @@ gen7_edit_hw_binding_table_entry(struct brw_context *brw, uint32_t index, uint32_t surf_offset) { - assert(stage <= MESA_SHADER_FRAGMENT); + assert(stage < ARRAY_SIZE(stage_to_bt_edit)); + assert(stage_to_bt_edit[stage]); uint32_t dw2 = SET_FIELD(index, BRW_BINDING_TABLE_INDEX) | (brw->gen >= 8 ? GEN8_SURFACE_STATE_EDIT(surf_offset) : @@ -259,7 +260,9 @@ gen7_update_binding_table_from_array(struct brw_context *brw, int num_surfaces) { uint32_t dw2 = 0; - assert(stage <= MESA_SHADER_FRAGMENT); + + assert(stage < ARRAY_SIZE(stage_to_bt_edit)); + assert(stage_to_bt_edit[stage]); BEGIN_BATCH(num_surfaces + 2); OUT_BATCH(stage_to_bt_edit[stage] << 16 | num_surfaces); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use updated kernel interface for accurate TIMESTAMP reads
Module: Mesa Branch: master Commit: 013d731a67538a2eb8f508fa54bb86191f0e5491 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=013d731a67538a2eb8f508fa54bb86191f0e5491 Author: Chris Wilson Date: Tue Jul 21 11:12:57 2015 +0100 i965: Use updated kernel interface for accurate TIMESTAMP reads I was mistaken, I thought we already had fixed this in the kernel a couple of years ago. We had not, and the broken read (the hardware shifts the register output on 64bit kernels, but not on 32bit kernels) is now enshrined into the ABI. I also had the buggy architecture reversed, believing it to be 32bit that had the shifted results. On the basis of those mistakes, I wrote commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 Author: Chris Wilson Date: Wed Apr 29 13:32:38 2015 +0100 i965: Query whether we have kernel support for the TIMESTAMP register once Now that we do have an extended register read interface for always reporting the full 36bit TIMESTAMP (irrespective of whether the hardware is buggy or not), make use of it and in the process fix my reversed detection of the buggy reads for unpatched kernels. Signed-off-by: Chris Wilson Cc: Martin Peres Cc: Kenneth Graunke Cc: Michał Winiarski Cc: Daniel Vetter Tested-and-acked-by: Chris Forbes Reviewed-by: Daniel Vetter --- src/mesa/drivers/dri/i965/brw_queryobj.c | 15 +++-- src/mesa/drivers/dri/i965/intel_screen.c | 49 ++ src/mesa/drivers/dri/i965/intel_screen.h |2 +- 3 files changed, 49 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_queryobj.c b/src/mesa/drivers/dri/i965/brw_queryobj.c index aea4d9b..d6b012c 100644 --- a/src/mesa/drivers/dri/i965/brw_queryobj.c +++ b/src/mesa/drivers/dri/i965/brw_queryobj.c @@ -497,13 +497,22 @@ brw_get_timestamp(struct gl_context *ctx) struct brw_context *brw = brw_context(ctx); uint64_t result = 0; - drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result); + switch (brw->intelScreen->hw_has_timestamp) { + case 3: /* New kernel, always full 36bit accuracy */ + drm_intel_reg_read(brw->bufmgr, TIMESTAMP | 1, &result); + break; + case 2: /* 64bit kernel, result is left-shifted by 32bits, losing 4bits */ + drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result); + result = result >> 32; + break; + case 1: /* 32bit kernel, result is 36bit wide but may be inaccurate! */ + drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &result); + break; + } /* See logic in brw_queryobj_get_results() */ - result = result >> 32; result *= 80; result &= (1ull << 36) - 1; - return result; } diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 1470b05..65a1766 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1123,25 +1123,48 @@ intel_detect_swizzling(struct intel_screen *screen) return true; } -static bool +static int intel_detect_timestamp(struct intel_screen *screen) { - uint64_t dummy = 0; - int loop = 10; + uint64_t dummy = 0, last = 0; + int upper, lower, loops; - /* -* On 32bit systems, some old kernels trigger a hw bug resulting in the -* TIMESTAMP register being shifted and the low 32bits always zero. Detect -* this by repeating the read a few times and check the register is -* incrementing every 80ns as expected and not stuck on zero (as would be -* the case with the buggy kernel/hw.). + /* On 64bit systems, some old kernels trigger a hw bug resulting in the +* TIMESTAMP register being shifted and the low 32bits always zero. +* +* More recent kernels offer an interface to read the full 36bits +* everywhere. */ - do { + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP | 1, &dummy) == 0) + return 3; + + /* Determine if we have a 32bit or 64bit kernel by inspecting the +* upper 32bits for a rapidly changing timestamp. +*/ + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &last)) + return 0; + + upper = lower = 0; + for (loops = 0; loops < 10; loops++) { + /* The TIMESTAMP should change every 80ns, so several round trips + * through the kernel should be enough to advance it. + */ if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) -return false; - } while ((dummy & 0x) == 0 && --loop); + return 0; + + upper += (dummy >> 32) != (last >> 32); + if (upper > 1) /* beware 32bit counter overflow */ + return 2; /* upper dword holds the low 32bits of the timestamp */ + + lower += (dummy & 0x) != (last & 0x); + if (lower > 1) + return 1; /* timestamp is unshifted */ + + last = dummy; + } - return loop > 0; + /* No advancement? No timestamp! */ + re
Mesa (master): i965: Move pipecontrol workaround bo to brw_pipe_control
Module: Mesa Branch: master Commit: f1d08c4f75794add30d1714a4cd9ce2bf335148d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1d08c4f75794add30d1714a4cd9ce2bf335148d Author: Chris Wilson Date: Fri May 1 11:25:20 2015 +0100 i965: Move pipecontrol workaround bo to brw_pipe_control With the exception of gen8, the sole user of the workaround bo are for emitting pipe controls. Move it out of the purview of the batchbuffer and into the pipecontrol. Signed-off-by: Chris Wilson Reviewed-by: Kenneth Graunke Reviewed-by: Martin Peres --- src/mesa/drivers/dri/i965/brw_context.c |7 + src/mesa/drivers/dri/i965/brw_context.h | 12 +--- src/mesa/drivers/dri/i965/brw_pipe_control.c | 40 + src/mesa/drivers/dri/i965/gen8_depth_state.c |2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 12 src/mesa/drivers/dri/i965/intel_extensions.c | 28 - 6 files changed, 64 insertions(+), 37 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 4b51fe5..8150b94 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -819,6 +819,12 @@ brwCreateContext(gl_api api, } } + if (brw_init_pipe_control(brw, devinfo)) { + *dri_ctx_error = __DRI_CTX_ERROR_NO_MEMORY; + intelDestroyContext(driContextPriv); + return false; + } + brw_init_state(brw); intelInitExtensions(ctx); @@ -942,6 +948,7 @@ intelDestroyContext(__DRIcontext * driContextPriv) if (ctx->swrast_context) _swrast_DestroyContext(&brw->ctx); + brw_fini_pipe_control(brw); intel_batchbuffer_free(brw); drm_intel_bo_unreference(brw->throttle_batch[1]); diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 7596139..65f34c3 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -869,8 +869,6 @@ struct intel_batchbuffer { drm_intel_bo *bo; /** Last BO submitted to the hardware. Used for glFinish(). */ drm_intel_bo *last_bo; - /** BO for post-sync nonzero writes for gen6 workaround. */ - drm_intel_bo *workaround_bo; uint16_t emit, total; uint16_t used, reserved_space; @@ -882,8 +880,6 @@ struct intel_batchbuffer { enum brw_gpu_ring ring; bool needs_sol_reset; - uint8_t pipe_controls_since_last_cs_stall; - struct { uint16_t used; int reloc_count; @@ -1035,6 +1031,10 @@ struct brw_context drm_intel_context *hw_ctx; + /** BO for post-sync nonzero writes for gen6 workaround. */ + drm_intel_bo *workaround_bo; + uint8_t pipe_controls_since_last_cs_stall; + /** * Set of drm_intel_bo * that have been rendered to within this batchbuffer * and would need flushing before being used from another cache domain that @@ -2001,6 +2001,10 @@ gen9_use_linear_1d_layout(const struct brw_context *brw, const struct intel_mipmap_tree *mt); /* brw_pipe_control.c */ +int brw_init_pipe_control(struct brw_context *brw, + const struct brw_device_info *info); +void brw_fini_pipe_control(struct brw_context *brw); + void brw_emit_pipe_control_flush(struct brw_context *brw, uint32_t flags); void brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags, drm_intel_bo *bo, uint32_t offset, diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index b4c86b9..7ee3cb6 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -72,13 +72,13 @@ gen7_cs_stall_every_four_pipe_controls(struct brw_context *brw, uint32_t flags) if (brw->gen == 7 && !brw->is_haswell) { if (flags & PIPE_CONTROL_CS_STALL) { /* If we're doing a CS stall, reset the counter and carry on. */ - brw->batch.pipe_controls_since_last_cs_stall = 0; + brw->pipe_controls_since_last_cs_stall = 0; return 0; } /* If this is the fourth pipe control without a CS stall, do one now. */ - if (++brw->batch.pipe_controls_since_last_cs_stall == 4) { - brw->batch.pipe_controls_since_last_cs_stall = 0; + if (++brw->pipe_controls_since_last_cs_stall == 4) { + brw->pipe_controls_since_last_cs_stall = 0; return PIPE_CONTROL_CS_STALL; } } @@ -213,7 +213,7 @@ gen7_emit_vs_workaround_flush(struct brw_context *brw) brw_emit_pipe_control_write(brw, PIPE_CONTROL_WRITE_IMMEDIATE | PIPE_CONTROL_DEPTH_STALL, - brw->batch.workaround_bo, 0, + brw->workaround_bo, 0, 0, 0); } @@ -227,
Mesa (master): loader: Look for any version of currently linked libudev.so
Module: Mesa Branch: master Commit: f2413457937f8f4a92e11379569be69e508d7477 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2413457937f8f4a92e11379569be69e508d7477 Author: Chris Wilson Date: Wed Jun 10 08:28:13 2015 +0100 loader: Look for any version of currently linked libudev.so Since there was an ABI break and linking twice against libudev.so.0 and libudev.so.1 causes the application to quickly crash, we first check if the application is currently linked against libudev before dlopening a local handle. However for backwards/forwards compatability, we need to inspect the application for current linkage against all known versions first. Not doing so causes a crash when both libraries are present and so mesa chooses libudev.so.1 but the application was linked against libudev.so.0. Signed-off-by: Chris Wilson Emil Velikov: I'm ever so slightly conserned that RTLD_NOLOAD is not part of the POSIX standard, thus it's missing on some platforms (*BSD seems ok, while Solaris, MacOS are not). Reviewed-by: Emil Velikov Cc: mesa-sta...@lists.freedesktop.org --- src/loader/loader.c | 46 -- 1 file changed, 28 insertions(+), 18 deletions(-) diff --git a/src/loader/loader.c b/src/loader/loader.c index 8452cd3..8780587 100644 --- a/src/loader/loader.c +++ b/src/loader/loader.c @@ -128,26 +128,36 @@ static void *udev_handle = NULL; static void * udev_dlopen_handle(void) { - if (!udev_handle) { - udev_handle = dlopen("libudev.so.1", RTLD_LOCAL | RTLD_LAZY); - - if (!udev_handle) { - /* libudev.so.1 changed the return types of the two unref functions - * from voids to pointers. We don't use those return values, and the - * only ABI I've heard that cares about this kind of change (calling - * a function with a void * return that actually only returns void) - * might be ia64. - */ - udev_handle = dlopen("libudev.so.0", RTLD_LOCAL | RTLD_LAZY); - - if (!udev_handle) { -log_(_LOADER_WARNING, "Couldn't dlopen libudev.so.1 or " - "libudev.so.0, driver detection may be broken.\n"); - } + char name[80]; + unsigned flags = RTLD_NOLOAD | RTLD_LOCAL | RTLD_LAZY; + int version; + + /* libudev.so.1 changed the return types of the two unref functions +* from voids to pointers. We don't use those return values, and the +* only ABI I've heard that cares about this kind of change (calling +* a function with a void * return that actually only returns void) +* might be ia64. +*/ + + /* First try opening an already linked libudev, then try loading one */ + do { + for (version = 1; version >= 0; version--) { + snprintf(name, sizeof(name), "libudev.so.%d", version); + udev_handle = dlopen(name, flags); + if (udev_handle) +return udev_handle; } - } - return udev_handle; + if ((flags & RTLD_NOLOAD) == 0) + break; + + flags &= ~RTLD_NOLOAD; + } while (1); + + log_(_LOADER_WARNING, +"Couldn't dlopen libudev.so.1 or " +"libudev.so.0, driver detection may be broken.\n"); + return NULL; } static int dlsym_failed = 0; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Query whether we have kernel support for the TIMESTAMP register once
Module: Mesa Branch: master Commit: c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 Author: Chris Wilson Date: Wed Apr 29 13:32:38 2015 +0100 i965: Query whether we have kernel support for the TIMESTAMP register once Move the query for the TIMESTAMP register from context init to the screen, so that it is only queried once for all contexts. On 32bit systems, some old kernels trigger a hw bug resulting in the TIMESTAMP register being shifted and the low 32bits always zero. Detect this by repeating the read a few times and check the register is incrementing every 80ns as expected and not stuck on zero (as would be the case with the buggy kernel/hw.). Signed-off-by: Chris Wilson Cc: Martin Peres Reviewed-by: Martin Peres Reviewed-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/intel_extensions.c |6 +- src/mesa/drivers/dri/i965/intel_screen.c | 22 ++ src/mesa/drivers/dri/i965/intel_screen.h |2 ++ 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 3423190..740ac81 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -282,8 +282,6 @@ intelInitExtensions(struct gl_context *ctx) } if (brw->gen >= 6) { - uint64_t dummy; - ctx->Extensions.ARB_blend_func_extended = !driQueryOptionb(&brw->optionCache, "disable_blend_func_extended"); ctx->Extensions.ARB_conditional_render_inverted = true; @@ -307,9 +305,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.EXT_transform_feedback = true; ctx->Extensions.OES_depth_texture_cube_map = true; - /* Test if the kernel has the ioctl. */ - if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0) - ctx->Extensions.ARB_timer_query = true; + ctx->Extensions.ARB_timer_query = brw->intelScreen->hw_has_timestamp; /* Only enable this in core profile because other parts of Mesa behave * slightly differently when the extension is enabled. diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index f9398d7..c0f5c92 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1123,6 +1123,27 @@ intel_detect_swizzling(struct intel_screen *screen) return true; } +static bool +intel_detect_timestamp(struct intel_screen *screen) +{ + uint64_t dummy = 0; + int loop = 10; + + /* +* On 32bit systems, some old kernels trigger a hw bug resulting in the +* TIMESTAMP register being shifted and the low 32bits always zero. Detect +* this by repeating the read a few times and check the register is +* incrementing every 80ns as expected and not stuck on zero (as would be +* the case with the buggy kernel/hw.). +*/ + do { + if (drm_intel_reg_read(screen->bufmgr, TIMESTAMP, &dummy)) +return false; + } while ((dummy & 0x) == 0 && --loop); + + return loop > 0; +} + /** * Return array of MSAA modes supported by the hardware. The array is * zero-terminated and sorted in decreasing order. @@ -1378,6 +1399,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp) intelScreen->hw_must_use_separate_stencil = intelScreen->devinfo->gen >= 7; intelScreen->hw_has_swizzling = intel_detect_swizzling(intelScreen); + intelScreen->hw_has_timestamp = intel_detect_timestamp(intelScreen); const char *force_msaa = getenv("INTEL_FORCE_MSAA"); if (force_msaa) { diff --git a/src/mesa/drivers/dri/i965/intel_screen.h b/src/mesa/drivers/dri/i965/intel_screen.h index 742b3d3..941e0fc 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.h +++ b/src/mesa/drivers/dri/i965/intel_screen.h @@ -52,6 +52,8 @@ struct intel_screen bool hw_has_swizzling; + bool hw_has_timestamp; + /** * Does the kernel support context reset notifications? */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix HW blitter pitch limits
Module: Mesa Branch: master Commit: 8da79b8378ae87474d8c47ad955e4833edf98359 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8da79b8378ae87474d8c47ad955e4833edf98359 Author: Chris Wilson Date: Fri Jun 5 13:49:08 2015 +0100 i965: Fix HW blitter pitch limits The BLT pitch is specified in bytes for linear surfaces and in dwords for tiled surfaces. In both cases the programmable limit is 32,767, so adjust the check to compensate for the effect of tiling. v2: Tweak whitespace for functions (Kenneth) Signed-off-by: Chris Wilson Cc: Kristian Høgsberg Cc: Kenneth Graunke Reviewed-by Kenneth Graunke Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/intel_blit.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 7680a40..aae0d25 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -130,6 +130,15 @@ set_blitter_tiling(struct brw_context *brw, ADVANCE_BATCH(); \ } while (0) +static int +blt_pitch(struct intel_mipmap_tree *mt) +{ + int pitch = mt->pitch; + if (mt->tiling) + pitch /= 4; + return pitch; +} + /** * Implements a rectangular block transfer (blit) of pixels between two * miptrees. @@ -197,14 +206,14 @@ intel_miptree_blit(struct brw_context *brw, * * Furthermore, intelEmitCopyBlit (which is called below) uses a signed * 16-bit integer to represent buffer pitch, so it can only handle buffer -* pitches < 32k. +* pitches < 32k. However, the pitch is measured in bytes for linear buffers +* and dwords for tiled buffers. * * As a result of these two limitations, we can only use the blitter to do -* this copy when the miptree's pitch is less than 32k. +* this copy when the miptree's pitch is less than 32k linear or 128k tiled. */ - if (src_mt->pitch >= 32768 || - dst_mt->pitch >= 32768) { - perf_debug("Falling back due to >=32k pitch\n"); + if (blt_pitch(src_mt) >= 32768 || blt_pitch(dst_mt) >= 32768) { + perf_debug("Falling back due to >= 32k/128k pitch\n"); return false; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Blit RGBX<->RGBA drawpixels
Module: Mesa Branch: master Commit: c2d0606827412b710dcaed80268fc665de8c9c5d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2d0606827412b710dcaed80268fc665de8c9c5d Author: Chris Wilson Date: Fri Jun 5 14:33:36 2015 +0100 i915: Blit RGBX<->RGBA drawpixels The blitter already has code to accommodate filling in the alpha channel for BGRX destination formats, so expand this to also allow filling the alpha channgel in RGBX formats. More importantly for the next patch is moving the test into its own function for the purpose of exporting the check to the callers. v2: Fix alpha expansion as spotted by Alexander with the fix suggested by Kenneth Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Alexander Monakov Cc: Kristian Høgsberg Cc: Kenneth Graunke Reviewed-by Kenneth Graunke Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/intel_blit.c | 36 +--- 1 file changed, 29 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index aae0d25..059165e 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -139,6 +139,31 @@ blt_pitch(struct intel_mipmap_tree *mt) return pitch; } +static bool +blt_compatible_formats(mesa_format src, mesa_format dst) +{ + /* The BLT doesn't handle sRGB conversion */ + assert(src == _mesa_get_srgb_format_linear(src)); + assert(dst == _mesa_get_srgb_format_linear(dst)); + + /* No swizzle or format conversions possible, except... */ + if (src == dst) + return true; + + /* ...we can either discard the alpha channel when going from A->X, +* or we can fill the alpha channel with 0xff when going from X->A +*/ + if (src == MESA_FORMAT_B8G8R8A8_UNORM || src == MESA_FORMAT_B8G8R8X8_UNORM) + return (dst == MESA_FORMAT_B8G8R8A8_UNORM || + dst == MESA_FORMAT_B8G8R8X8_UNORM); + + if (src == MESA_FORMAT_R8G8B8A8_UNORM || src == MESA_FORMAT_R8G8B8X8_UNORM) + return (dst == MESA_FORMAT_R8G8B8A8_UNORM || + dst == MESA_FORMAT_R8G8B8X8_UNORM); + + return false; +} + /** * Implements a rectangular block transfer (blit) of pixels between two * miptrees. @@ -181,11 +206,7 @@ intel_miptree_blit(struct brw_context *brw, * the X channel don't matter), and XRGB to ARGB by setting the A * channel to 1.0 at the end. */ - if (src_format != dst_format && - ((src_format != MESA_FORMAT_B8G8R8A8_UNORM && -src_format != MESA_FORMAT_B8G8R8X8_UNORM) || - (dst_format != MESA_FORMAT_B8G8R8A8_UNORM && -dst_format != MESA_FORMAT_B8G8R8X8_UNORM))) { + if (!blt_compatible_formats(src_format, dst_format)) { perf_debug("%s: Can't use hardware blitter from %s to %s, " "falling back.\n", __func__, _mesa_get_format_name(src_format), @@ -270,8 +291,9 @@ intel_miptree_blit(struct brw_context *brw, return false; } - if (src_mt->format == MESA_FORMAT_B8G8R8X8_UNORM && - dst_mt->format == MESA_FORMAT_B8G8R8A8_UNORM) { + /* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */ + if (_mesa_get_format_bits(src_format, GL_ALPHA_BITS) == 0 && + _mesa_get_format_bits(dst_format, GL_ALPHA_BITS) > 0) { intel_miptree_set_alpha_to_one(brw, dst_mt, dst_x, dst_y, width, height); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Export format comparison for blitting between miptrees
Module: Mesa Branch: master Commit: 922c0c9fd526ce19b87bc74a3159dec7705c1de1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=922c0c9fd526ce19b87bc74a3159dec7705c1de1 Author: Chris Wilson Date: Fri Jun 5 14:45:18 2015 +0100 i965: Export format comparison for blitting between miptrees Since the introduction of commit 536003c11e4cb1172c540932ce3cce06f03bf44e Author: Boyan Ding Date: Wed Mar 25 19:36:54 2015 +0800 i965: Add XRGB format to intel_screen_make_configs winsys buffers no longer have an alpha channel. This causes _mesa_format_matches_format_and_type() to reject previously working BGRA uploads from using the BLT fast path. Instead of using the generic routine for matching formats exactly, export the slightly more relaxed check from intel_miptree_blit() which importantly allows the blitter routine to apply a small number of format conversions. References: https://bugs.freedesktop.org/show_bug.cgi?id=90839 Signed-off-by: Chris Wilson Cc: Jason Ekstrand Cc: Alexander Monakov Cc: Kristian Høgsberg Cc: Kenneth Graunke Reviewed-by: Kenneth Graunke Cc: mesa-sta...@lists.freedesktop.org --- src/mesa/drivers/dri/i965/intel_blit.c |6 +++--- src/mesa/drivers/dri/i965/intel_blit.h |2 ++ src/mesa/drivers/dri/i965/intel_pixel_draw.c | 11 +-- 3 files changed, 14 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 059165e..5afc771 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -139,8 +139,8 @@ blt_pitch(struct intel_mipmap_tree *mt) return pitch; } -static bool -blt_compatible_formats(mesa_format src, mesa_format dst) +bool +intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst) { /* The BLT doesn't handle sRGB conversion */ assert(src == _mesa_get_srgb_format_linear(src)); @@ -206,7 +206,7 @@ intel_miptree_blit(struct brw_context *brw, * the X channel don't matter), and XRGB to ARGB by setting the A * channel to 1.0 at the end. */ - if (!blt_compatible_formats(src_format, dst_format)) { + if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) { perf_debug("%s: Can't use hardware blitter from %s to %s, " "falling back.\n", __func__, _mesa_get_format_name(src_format), diff --git a/src/mesa/drivers/dri/i965/intel_blit.h b/src/mesa/drivers/dri/i965/intel_blit.h index f563939..2287c37 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.h +++ b/src/mesa/drivers/dri/i965/intel_blit.h @@ -46,6 +46,8 @@ intelEmitCopyBlit(struct brw_context *brw, GLshort w, GLshort h, GLenum logicop ); +bool intel_miptree_blit_compatible_formats(mesa_format src, mesa_format dst); + bool intel_miptree_blit(struct brw_context *brw, struct intel_mipmap_tree *src_mt, int src_level, int src_slice, diff --git a/src/mesa/drivers/dri/i965/intel_pixel_draw.c b/src/mesa/drivers/dri/i965/intel_pixel_draw.c index 4ecefc8..d68cbb6 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_draw.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_draw.c @@ -28,6 +28,7 @@ #include "main/glheader.h" #include "main/enums.h" #include "main/image.h" +#include "main/glformats.h" #include "main/mtypes.h" #include "main/condrender.h" #include "main/fbobject.h" @@ -76,8 +77,14 @@ do_blit_drawpixels(struct gl_context * ctx, struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; struct intel_renderbuffer *irb = intel_renderbuffer(rb); - if (!_mesa_format_matches_format_and_type(irb->mt->format, format, type, - false)) { + mesa_format src_format = _mesa_format_from_format_and_type(format, type); + mesa_format dst_format = irb->mt->format; + + /* We can safely discard sRGB encode/decode for the DrawPixels interface */ + src_format = _mesa_get_srgb_format_linear(src_format); + dst_format = _mesa_get_srgb_format_linear(dst_format); + + if (!intel_miptree_blit_compatible_formats(src_format, dst_format)) { DBG("%s: bad format for blit\n", __func__); return false; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Throttle to the previous frame
Module: Mesa Branch: master Commit: 64788b2e8dc2ddedc2712ed02b7e9096638b7bae URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64788b2e8dc2ddedc2712ed02b7e9096638b7bae Author: Chris Wilson Date: Fri Sep 19 10:10:13 2014 +0100 i965: Throttle to the previous frame In order to facilitate the concurrency offered by triple buffering and to offset the latency induced by swapping via an external process, which may incur extra rendering itself, only throttle to the previous frame and not the last. The second issue that mostly affects swap benchmarks, but also can incur jitter in the throttling, is that the throttle bo is closer to the next SwapBuffers rather than immediately after the previous SwapBuffers. Throttling to the previous frame doubles the maximum possible latency at the benefit of improving throughput and reducing jitter. v2: Rename "first_post_swapbuffer" batches array to a plain throttle_batch[] as the pluralisation was contorting the name and not making it clear as to whether it was the first batch or first_post_swap batch. Not least of which was that not all throttle points are SwapBuffers. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Kenneth Graunke Cc: Ben Widawsky Cc: Kristian Høgsberg Cc: Chad Versace Cc: Ian Romanick Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 19 --- src/mesa/drivers/dri/i965/brw_context.h |2 +- src/mesa/drivers/dri/i965/intel_batchbuffer.c |7 --- 3 files changed, 17 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 5120372..8257fb6 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -935,8 +935,10 @@ intelDestroyContext(__DRIcontext * driContextPriv) intel_batchbuffer_free(brw); - drm_intel_bo_unreference(brw->first_post_swapbuffers_batch); - brw->first_post_swapbuffers_batch = NULL; + drm_intel_bo_unreference(brw->throttle_batch[1]); + drm_intel_bo_unreference(brw->throttle_batch[0]); + brw->throttle_batch[1] = NULL; + brw->throttle_batch[0] = NULL; driDestroyOptionCache(&brw->optionCache); @@ -1245,11 +1247,14 @@ intel_prepare_render(struct brw_context *brw) * the swap, and getting our hands on that doesn't seem worth it, * so we just us the first batch we emitted after the last swap. */ - if (brw->need_swap_throttle && brw->first_post_swapbuffers_batch) { - if (!brw->disable_throttling) - drm_intel_bo_wait_rendering(brw->first_post_swapbuffers_batch); - drm_intel_bo_unreference(brw->first_post_swapbuffers_batch); - brw->first_post_swapbuffers_batch = NULL; + if (brw->need_swap_throttle && brw->throttle_batch[0]) { + if (brw->throttle_batch[1]) { + if (!brw->disable_throttling) +drm_intel_bo_wait_rendering(brw->throttle_batch[1]); + drm_intel_bo_unreference(brw->throttle_batch[1]); + } + brw->throttle_batch[1] = brw->throttle_batch[0]; + brw->throttle_batch[0] = NULL; brw->need_swap_throttle = false; /* Throttling here is more precise than the throttle ioctl, so skip it */ brw->need_flush_throttle = false; diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index eebd7ce..8b29e2a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1030,7 +1030,7 @@ struct brw_context bool front_buffer_dirty; /** Framerate throttling: @{ */ - drm_intel_bo *first_post_swapbuffers_batch; + drm_intel_bo *throttle_batch[2]; /* Limit the number of outstanding SwapBuffers by waiting for an earlier * frame of rendering to complete. This gives a very precise cap to the diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 5ac4d18..87862cd 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -168,6 +168,7 @@ static void brw_new_batch(struct brw_context *brw) { /* Create a new batchbuffer and reset the associated state: */ + drm_intel_gem_bo_clear_relocs(brw->batch.bo, 0); intel_batchbuffer_reset(brw); /* If the kernel supports hardware contexts, then most hardware state is @@ -289,9 +290,9 @@ _intel_batchbuffer_flush(struct brw_context *brw, if (brw->batch.used == 0) return 0; - if (brw->first_post_swapbuffers_batch == NULL) { - brw->first_post_swapbuffers_batch = brw->batch.bo; - drm_intel_bo_reference(brw->first_post_swapbuffers_batch); + if (brw->throttle_batch[0] == NULL) { + brw->throttle_batch[0] = brw->batch.bo; + drm_intel_bo_reference(brw->throttle_batch[0]); } if (unlikely(INTEL
Mesa (master): i965: Defer the throttle until we submit new commands
Module: Mesa Branch: master Commit: eeb504e0ae7796e7ba475f6e9d6c26daa6b06608 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeb504e0ae7796e7ba475f6e9d6c26daa6b06608 Author: Chris Wilson Date: Wed Mar 11 12:21:29 2015 + i965: Defer the throttle until we submit new commands Currently, we throttle before the user begins preparing commands for the next frame when we acquire the draw/read buffers. However, construction of the command buffer can itself take significant time relative to the frame time. If we move the throttle from the buffer acquire to the command submit phase we can allow the user to improve concurrency between the CPU and GPU (i.e. reduce the amount of time we waste inside the throttle). v2: Whitespace + delay throttling until after the next submission for greater parallelism Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Kenneth Graunke Cc: Ben Widawsky Cc: Kristian Høgsberg Cc: Chad Versace Cc: Ian Romanick Reviewed-by: Chad Versace [v1] --- src/mesa/drivers/dri/i965/brw_context.c | 34 --- src/mesa/drivers/dri/i965/intel_batchbuffer.c | 44 + 2 files changed, 44 insertions(+), 34 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 8257fb6..88685cd 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1231,40 +1231,6 @@ intel_prepare_render(struct brw_context *brw) */ if (brw_is_front_buffer_drawing(ctx->DrawBuffer)) brw->front_buffer_dirty = true; - - /* Wait for the swapbuffers before the one we just emitted, so we -* don't get too many swaps outstanding for apps that are GPU-heavy -* but not CPU-heavy. -* -* We're using intelDRI2Flush (called from the loader before -* swapbuffer) and glFlush (for front buffer rendering) as the -* indicator that a frame is done and then throttle when we get -* here as we prepare to render the next frame. At this point for -* round trips for swap/copy and getting new buffers are done and -* we'll spend less time waiting on the GPU. -* -* Unfortunately, we don't have a handle to the batch containing -* the swap, and getting our hands on that doesn't seem worth it, -* so we just us the first batch we emitted after the last swap. -*/ - if (brw->need_swap_throttle && brw->throttle_batch[0]) { - if (brw->throttle_batch[1]) { - if (!brw->disable_throttling) -drm_intel_bo_wait_rendering(brw->throttle_batch[1]); - drm_intel_bo_unreference(brw->throttle_batch[1]); - } - brw->throttle_batch[1] = brw->throttle_batch[0]; - brw->throttle_batch[0] = NULL; - brw->need_swap_throttle = false; - /* Throttling here is more precise than the throttle ioctl, so skip it */ - brw->need_flush_throttle = false; - } - - if (brw->need_flush_throttle) { - __DRIscreen *psp = brw->intelScreen->driScrnPriv; - drmCommandNone(psp->fd, DRM_I915_GEM_THROTTLE); - brw->need_flush_throttle = false; - } } /** diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 87862cd..3cf44ad 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -33,6 +33,9 @@ #include "intel_fbo.h" #include "brw_context.h" +#include +#include + static void intel_batchbuffer_reset(struct brw_context *brw); @@ -226,6 +229,44 @@ brw_finish_batch(struct brw_context *brw) brw->cache.bo_used_by_gpu = true; } +static void +throttle(struct brw_context *brw) +{ + /* Wait for the swapbuffers before the one we just emitted, so we +* don't get too many swaps outstanding for apps that are GPU-heavy +* but not CPU-heavy. +* +* We're using intelDRI2Flush (called from the loader before +* swapbuffer) and glFlush (for front buffer rendering) as the +* indicator that a frame is done and then throttle when we get +* here as we prepare to render the next frame. At this point for +* round trips for swap/copy and getting new buffers are done and +* we'll spend less time waiting on the GPU. +* +* Unfortunately, we don't have a handle to the batch containing +* the swap, and getting our hands on that doesn't seem worth it, +* so we just use the first batch we emitted after the last swap. +*/ + if (brw->need_swap_throttle && brw->throttle_batch[0]) { + if (brw->throttle_batch[1]) { + if (!brw->disable_throttling) +drm_intel_bo_wait_rendering(brw->throttle_batch[1]); + drm_intel_bo_unreference(brw->throttle_batch[1]); + } + brw->throttle_batch[1] = brw->throttle_batch[0]; +
Mesa (master): i965: Throttle rendering to an fbo
Module: Mesa Branch: master Commit: 8b9bd19021c0efef33d66ae24f8871b826d66e8a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b9bd19021c0efef33d66ae24f8871b826d66e8a Author: Chris Wilson Date: Thu Feb 26 11:25:18 2015 + i965: Throttle rendering to an fbo When rendering to an fbo, even though it may be acting as a winsys frontbuffer or just generally, we never throttle. However, when rendering to an fbo, there is no natural frame boundary. Conventionally we use SwapBuffers and glFinish, but potential callers avoid often glFinish for being too heavy handed (waiting on all outstanding rendering to complete). The kernel provides a soft-throttling option for this case that waits for rendering older than 20ms to be complete (that's a little too lax to be used for swapbuffers, but is here a useful safety net). The remaining choice is then either never to throttle, throttle after every draw call, or at after intermediate user defined point such as glFlush and thus all the implied flushes. This patch opts for the latter as that is the current method used for flushing to front buffers. v2: Defer the throttling from inside the flush to the next intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at "frame" boundaries. v3: Rename from need_front_throttle to need_flush_throttle to avoid any ambiguity between front buffer rendering and fbo rendering. (Chad) v4: Whitespace Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Kenneth Graunke Cc: Ben Widawsky Cc: Kristian Høgsberg Cc: Chad Versace Cc: Ian Romanick Reviewed-by: Chad Versace --- src/mesa/drivers/dri/i965/brw_context.c | 16 src/mesa/drivers/dri/i965/brw_context.h | 14 +- src/mesa/drivers/dri/i965/intel_screen.c |8 3 files changed, 29 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 0881e48..5120372 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -234,8 +234,8 @@ intel_glFlush(struct gl_context *ctx) intel_batchbuffer_flush(brw); intel_flush_front(ctx); - if (brw_is_front_buffer_drawing(ctx->DrawBuffer)) - brw->need_throttle = true; + + brw->need_flush_throttle = true; } static void @@ -1245,12 +1245,20 @@ intel_prepare_render(struct brw_context *brw) * the swap, and getting our hands on that doesn't seem worth it, * so we just us the first batch we emitted after the last swap. */ - if (brw->need_throttle && brw->first_post_swapbuffers_batch) { + if (brw->need_swap_throttle && brw->first_post_swapbuffers_batch) { if (!brw->disable_throttling) drm_intel_bo_wait_rendering(brw->first_post_swapbuffers_batch); drm_intel_bo_unreference(brw->first_post_swapbuffers_batch); brw->first_post_swapbuffers_batch = NULL; - brw->need_throttle = false; + brw->need_swap_throttle = false; + /* Throttling here is more precise than the throttle ioctl, so skip it */ + brw->need_flush_throttle = false; + } + + if (brw->need_flush_throttle) { + __DRIscreen *psp = brw->intelScreen->driScrnPriv; + drmCommandNone(psp->fd, DRM_I915_GEM_THROTTLE); + brw->need_flush_throttle = false; } } diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 682fbe9..eebd7ce 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1031,7 +1031,19 @@ struct brw_context /** Framerate throttling: @{ */ drm_intel_bo *first_post_swapbuffers_batch; - bool need_throttle; + + /* Limit the number of outstanding SwapBuffers by waiting for an earlier +* frame of rendering to complete. This gives a very precise cap to the +* latency between input and output such that rendering never gets more +* than a frame behind the user. (With the caveat that we technically are +* not using the SwapBuffers itself as a barrier but the first batch +* submitted afterwards, which may be immediately prior to the next +* SwapBuffers.) +*/ + bool need_swap_throttle; + + /** General throttling, not caught by throttling between SwapBuffers */ + bool need_flush_throttle; /** @} */ GLuint stats_wm; diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index cea7ddf..3640b67 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -174,10 +174,10 @@ intel_dri2_flush_with_flags(__DRIcontext *cPriv, if (flags & __DRI2_FLUSH_DRAWABLE) intel_resolve_for_dri2_flush(brw, dPriv); - if (reason == __DRI2_THROTT
Mesa (master): i915: out-of-bounds write in calc_live_regs()
Module: Mesa Branch: master Commit: 67582e6eef789324b527b4753065aea366145f4e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67582e6eef789324b527b4753065aea366145f4e Author: Chris Wilson Date: Fri Sep 30 22:10:33 2011 +0100 i915: out-of-bounds write in calc_live_regs() >From a Coverity defect report. src/mesa/drivers/dri/i915/i915_fragprog.c 301 /* 302 * TODO: consider moving this into core 303 */ 304 static bool calc_live_regs( struct i915_fragment_program *p ) 305 { 306 const struct gl_fragment_program *program = &p->FragProg; 307 GLuint regsUsed = 0x; -> 308 uint8_t live_components[16] = { 0, }; 309 GLint i; 310 311 for (i = program->Base.NumInstructions - 1; i >= 0; i--) { 312 struct prog_instruction *inst = &program->Base.Instructions[i]; 313 int opArgs = _mesa_num_inst_src_regs(inst->Opcode); 314 int a; 315 316 /* Register is written to: unmark as live for this and preceeding ops */ 317 if (inst->DstReg.File == PROGRAM_TEMPORARY) { -> 318 if (inst->DstReg.Index > 16) 319 return false; 320 -> 321 live_components[inst->DstReg.Index] &= ~inst->DstReg.WriteMask; 322 if (live_components[inst->DstReg.Index] == 0) 323 regsUsed &= ~(1 << inst->DstReg.Index); 324 } 325 326 for (a = 0; a < opArgs; a++) { 327 /* Register is read from: mark as live for this and preceeding ops */ 328 if (inst->SrcReg[a].File == PROGRAM_TEMPORARY) { 329 unsigned c; 330 331 if (inst->SrcReg[a].Index > 16) 332 return false; 333 334 regsUsed |= 1 << inst->SrcReg[a].Index; 335 336 for (c = 0; c < 4; c++) { 337 const unsigned field = GET_SWZ(inst->SrcReg[a].Swizzle, c); 338 339 if (field <= SWIZZLE_W) 340 live_components[inst->SrcReg[a].Index] |= (1U << field); 341 } 342 } 343 } 344 345 p->usedRegs[i] = regsUsed; 346 } Reported-by: Vinson Lee Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40022 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_fragprog.c |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c b/src/mesa/drivers/dri/i915/i915_fragprog.c index d155b85..e155d16 100644 --- a/src/mesa/drivers/dri/i915/i915_fragprog.c +++ b/src/mesa/drivers/dri/i915/i915_fragprog.c @@ -304,8 +304,8 @@ do { \ static bool calc_live_regs( struct i915_fragment_program *p ) { const struct gl_fragment_program *program = &p->FragProg; -GLuint regsUsed = 0x; -uint8_t live_components[16] = { 0, }; +GLuint regsUsed = ~((1 << I915_MAX_TEMPORARY) - 1); +uint8_t live_components[I915_MAX_TEMPORARY] = { 0, }; GLint i; for (i = program->Base.NumInstructions - 1; i >= 0; i--) { @@ -315,7 +315,7 @@ static bool calc_live_regs( struct i915_fragment_program *p ) /* Register is written to: unmark as live for this and preceeding ops */ if (inst->DstReg.File == PROGRAM_TEMPORARY) { - if (inst->DstReg.Index > 16) + if (inst->DstReg.Index >= I915_MAX_TEMPORARY) return false; live_components[inst->DstReg.Index] &= ~inst->DstReg.WriteMask; @@ -328,7 +328,7 @@ static bool calc_live_regs( struct i915_fragment_program *p ) if (inst->SrcReg[a].File == PROGRAM_TEMPORARY) { unsigned c; - if (inst->SrcReg[a].Index > 16) + if (inst->SrcReg[a].Index >= I915_MAX_TEMPORARY) return false; regsUsed |= 1 << inst->SrcReg[a].Index; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Assign instead of compare inside assert
Module: Mesa Branch: master Commit: ebca47af8507e0fc3f03d6c0f49be6b2d4d9a8a4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebca47af8507e0fc3f03d6c0f49be6b2d4d9a8a4 Author: Chris Wilson Date: Fri Sep 30 21:58:59 2011 +0100 i965: Assign instead of compare inside assert This is from a Coverity defect report. src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 1314 void 1315 vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src, 1316const struct glsl_type *type, bool predicated) ... 1351 /* Do we need to worry about swizzling a swizzle? */ ->1352 assert(src->swizzle = BRW_SWIZZLE_NOOP); 1353 src->swizzle = swizzle_for_size(type->vector_elements); Reported-by: Vinson Lee Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40158 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index 98ecd25..5815e31 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1472,7 +1472,7 @@ vec4_visitor::emit_block_move(dst_reg *dst, src_reg *src, dst->writemask = (1 << type->vector_elements) - 1; /* Do we need to worry about swizzling a swizzle? */ - assert(src->swizzle = BRW_SWIZZLE_NOOP); + assert(src->swizzle == BRW_SWIZZLE_NOOP); src->swizzle = swizzle_for_size(type->vector_elements); vec4_instruction *inst = emit(MOV(*dst, *src)); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/gen6: Fix assign instead of compare in assert
Module: Mesa Branch: master Commit: 8ccbcda5c64a8bea47f6b41d46bf015ba8e515fc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ccbcda5c64a8bea47f6b41d46bf015ba8e515fc Author: Chris Wilson Date: Fri Sep 30 21:48:18 2011 +0100 i965/gen6: Fix assign instead of compare in assert This is from a Coverity defect report. src/mesa/drivers/dri/i965/brw_vec4_emit.cpp 268 static void 269 check_gen6_math_src_arg(struct brw_reg src) 270 { 271 /* Source swizzles are ignored. */ 272 assert(!src.abs); 273 assert(!src.negate); -> 274 assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); 275 } Reported-by: Vinson Lee Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40214 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp index 1eb8f3f..3feecbf 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp @@ -257,7 +257,7 @@ check_gen6_math_src_arg(struct brw_reg src) /* Source swizzles are ignored. */ assert(!src.abs); assert(!src.negate); - assert(src.dw1.bits.swizzle = BRW_SWIZZLE_XYZW); + assert(src.dw1.bits.swizzle == BRW_SWIZZLE_XYZW); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Raise const.MaxTextureLevels to 14 (8192)
Module: Mesa Branch: master Commit: f61d1deac7d19dcec38b7852a635d92680624a32 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f61d1deac7d19dcec38b7852a635d92680624a32 Author: Chris Wilson Date: Thu Jun 2 08:27:09 2011 +0100 i965: Raise const.MaxTextureLevels to 14 (8192) Mesa now limits, by default, the max number of texture levels to 15 so we can now support the architectural maximum for gen4-6 of 14. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.c |6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index df753ab..0256ab9 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -94,9 +94,9 @@ GLboolean brwCreateContext( int api, ctx->Const.MaxVertexTextureImageUnits + ctx->Const.MaxTextureImageUnits; - /* Mesa limits textures to 4kx4k; it would be nice to fix that someday -*/ - ctx->Const.MaxTextureLevels = 13; + ctx->Const.MaxTextureLevels = 14; /* 8192 */ + if (ctx->Const.MaxTextureLevels > MAX_TEXTURE_LEVELS) + ctx->Const.MaxTextureLevels = MAX_TEXTURE_LEVELS; ctx->Const.Max3DTextureLevels = 9; ctx->Const.MaxCubeTextureLevels = 12; ctx->Const.MaxTextureRectSize = (1<<12); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Revert "i965: Reinstate max-index paranoia"
Module: Mesa Branch: master Commit: f703ba8c42e924ee6d5e4308c3888e434d8ba98c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f703ba8c42e924ee6d5e4308c3888e434d8ba98c Author: Chris Wilson Date: Tue Apr 12 19:13:22 2011 +0100 Revert "i965: Reinstate max-index paranoia" This reverts commit b4cbd2b312d53a50603e2cda925711bc9def4517. It looked like a safe sanity check. It missed the issue of the start of the buffer not being at 0, but even that was not enough to explain why setting the max vertex index caused glyphs to be dropped from the game 'Achron'. Instead, the issue appears to be related to the use of the vertex bias and so we would need to re-emit the max-index every time we adjusted the bias, so re-emitting the relocations and defeating the original optimisation. Reported-and-tested-by: Thomas Jones Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35163 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index f1d0069..9389eb6 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -575,7 +575,7 @@ static void brw_emit_vertices(struct brw_context *brw) if (intel->gen >= 5) { OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1); } else - OUT_BATCH(buffer->bo->size / buffer->stride); + OUT_BATCH(0); OUT_BATCH(0); /* Instance data step rate */ brw->vb.current_buffers[i].handle = buffer->bo->handle; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Fix regression in clear_with_blit from 7bae1c3d
Module: Mesa Branch: master Commit: c40b7910ee1338b9d391816df5391ce43f509ef0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c40b7910ee1338b9d391816df5391ce43f509ef0 Author: Chris Wilson Date: Thu Mar 31 11:41:46 2011 +0100 intel: Fix regression in clear_with_blit from 7bae1c3d Oops, the mask was being used in the loop to determine whether to use include the stencil || depth values. This began to fail when mask was cleared at the beginning of the loop. So reorder the tests and do the work up-front along with determining the depth_stencil value to use. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35822 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_blit.c | 23 --- 1 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index d6a648c..487c9ea 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -211,7 +211,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) { struct intel_context *intel = intel_context(ctx); struct gl_framebuffer *fb = ctx->DrawBuffer; - GLuint clear_depth; + GLuint clear_depth_value, clear_depth_mask; GLboolean all; GLint cx, cy, cw, ch; GLbitfield fail_mask = 0; @@ -220,12 +220,15 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) /* * Compute values for clearing the buffers. */ - clear_depth = 0; + clear_depth_value = 0; + clear_depth_mask = 0; if (mask & BUFFER_BIT_DEPTH) { - clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); + clear_depth_value = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); + clear_depth_mask = XY_BLT_WRITE_RGB; } if (mask & BUFFER_BIT_STENCIL) { - clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; + clear_depth_value |= (ctx->Stencil.Clear & 0xff) << 24; + clear_depth_mask |= XY_BLT_WRITE_ALPHA; } cx = fb->_Xmin; @@ -245,6 +248,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) mask &= (1 << BUFFER_COUNT) - 1; while (mask) { GLuint buf = _mesa_ffs(mask) - 1; + GLboolean is_depth_stencil = buf == BUFFER_DEPTH || buf == BUFFER_STENCIL; struct intel_renderbuffer *irb; drm_intel_bo *write_buffer; int x1, y1, x2, y2; @@ -283,11 +287,8 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) /* Setup the blit command */ if (cpp == 4) { -if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { - if (mask & BUFFER_BIT_DEPTH) - CMD |= XY_BLT_WRITE_RGB; - if (mask & BUFFER_BIT_STENCIL) - CMD |= XY_BLT_WRITE_ALPHA; +if (is_depth_stencil) { + CMD |= clear_depth_mask; } else { /* clearing RGBA */ CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; @@ -304,8 +305,8 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) #endif BR13 |= (pitch * cpp); - if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { -clear_val = clear_depth; + if (is_depth_stencil) { +clear_val = clear_depth_value; } else { uint8_t clear[4]; GLclampf *color = ctx->Color.ClearColor; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Remove the unrelaxed relocation assertion
Module: Mesa Branch: master Commit: 6584d0cd4fa3a3255a4c0962f31338601df705cb URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6584d0cd4fa3a3255a4c0962f31338601df705cb Author: Chris Wilson Date: Wed Mar 30 15:10:50 2011 +0100 intel: Remove the unrelaxed relocation assertion Now that we purposefully generate delta that point outside of the target buffer, the assertion has outlived its usefulness. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_batchbuffer.c |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 42b4f92..53d6e7c 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -176,8 +176,6 @@ intel_batchbuffer_emit_reloc(struct intel_context *intel, { int ret; - assert(delta < buffer->size); - ret = drm_intel_bo_emit_reloc(intel->batch.bo, 4*intel->batch.used, buffer, delta, read_domains, write_domain); @@ -203,8 +201,6 @@ intel_batchbuffer_emit_reloc_fenced(struct intel_context *intel, { int ret; - assert(delta < buffer->size); - ret = drm_intel_bo_emit_reloc_fence(intel->batch.bo, 4*intel->batch.used, buffer, delta, read_domains, write_domain); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Add some defense against buffer allocation failure for subimage blits
Module: Mesa Branch: master Commit: 5eb9f687087a4bc71775a32efcd848fc6cd67694 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5eb9f687087a4bc71775a32efcd848fc6cd67694 Author: Chris Wilson Date: Fri Mar 4 15:04:36 2011 + intel: Add some defense against buffer allocation failure for subimage blits Once more! This time without the unwarranted conversion from drm_intel_bo_alloc_tiled. Signed-off-by: [a very embarrassed] Chris Wilson --- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 10 +- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 6b7f13f..8b43c40 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -92,6 +92,7 @@ intelTexSubimage(struct gl_context * ctx, { unsigned long pitch; uint32_t tiling_mode = I915_TILING_NONE; + temp_bo = drm_intel_bo_alloc_tiled(intel->bufmgr, "subimage blit bo", width, height, @@ -99,7 +100,14 @@ intelTexSubimage(struct gl_context * ctx, &tiling_mode, &pitch, 0); -drm_intel_gem_bo_map_gtt(temp_bo); + if (temp_bo == NULL) +return; + +if (drm_intel_gem_bo_map_gtt(temp_bo)) { +drm_intel_bo_unreference(temp_bo); +return; + } + texImage->Data = temp_bo->virtual; texImage->ImageOffsets[0] = 0; dstRowStride = pitch; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Revert "intel: Add some defense against buffer allocation failure for subimage blits"
Module: Mesa Branch: master Commit: f5a9a0bc22c4b717c2c32f4ddf283878d6c7ba93 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5a9a0bc22c4b717c2c32f4ddf283878d6c7ba93 Author: Chris Wilson Date: Wed Mar 30 10:54:31 2011 +0100 Revert "intel: Add some defense against buffer allocation failure for subimage blits" This reverts commit de7678ef521f4fb34459e407a66ab8bf8be733e1. The conversion from using drm_intel_bo_alloc_tiled to a plain drm_intel_bo_alloc forgot that the tiled variant adjusts the allocation height even for TILING_NONE. Reported-by: Dave Airlie Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35786 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index d0f8294..6b7f13f 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -90,19 +90,19 @@ intelTexSubimage(struct gl_context * ctx, intel->gen < 6 && target == GL_TEXTURE_2D && drm_intel_bo_busy(dst_bo)) { -dstRowStride = width * intelImage->mt->cpp; - temp_bo = drm_intel_bo_alloc(intel->bufmgr, "subimage blit bo", - dstRowStride * height, 0); - if (!temp_bo) -return; - -if (drm_intel_gem_bo_map_gtt(temp_bo)) { -drm_intel_bo_unreference(temp_bo); -return; - } - +unsigned long pitch; +uint32_t tiling_mode = I915_TILING_NONE; +temp_bo = drm_intel_bo_alloc_tiled(intel->bufmgr, + "subimage blit bo", + width, height, + intelImage->mt->cpp, + &tiling_mode, + &pitch, + 0); +drm_intel_gem_bo_map_gtt(temp_bo); texImage->Data = temp_bo->virtual; texImage->ImageOffsets[0] = 0; +dstRowStride = pitch; intel_miptree_get_image_offset(intelImage->mt, level, intelImage->face, 0, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Protect intel_clear_with_blit from failed buffer allocations
Module: Mesa Branch: master Commit: 7bae1c3d85344b7229e0124d1f54376392682430 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bae1c3d85344b7229e0124d1f54376392682430 Author: Chris Wilson Date: Tue Mar 29 15:40:21 2011 +0100 intel: Protect intel_clear_with_blit from failed buffer allocations Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34419 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_blit.c | 21 +++-- 1 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_blit.c b/src/mesa/drivers/dri/intel/intel_blit.c index e1ab7f1..d6a648c 100644 --- a/src/mesa/drivers/dri/intel/intel_blit.c +++ b/src/mesa/drivers/dri/intel/intel_blit.c @@ -239,12 +239,12 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) if (cw == 0 || ch == 0) return 0; - GLuint buf; all = (cw == fb->Width && ch == fb->Height); /* Loop over all renderbuffers */ - for (buf = 0; buf < BUFFER_COUNT && mask; buf++) { - const GLbitfield bufBit = 1 << buf; + mask &= (1 << BUFFER_COUNT) - 1; + while (mask) { + GLuint buf = _mesa_ffs(mask) - 1; struct intel_renderbuffer *irb; drm_intel_bo *write_buffer; int x1, y1, x2, y2; @@ -253,11 +253,15 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) int pitch, cpp; drm_intel_bo *aper_array[2]; - if (!(mask & bufBit)) -continue; + mask &= ~(1 << buf); - /* OK, clear this renderbuffer */ irb = intel_get_renderbuffer(fb, buf); + if (irb == NULL || irb->region == NULL || irb->region->buffer == NULL) { + fail_mask |= 1 << buf; + continue; + } + + /* OK, clear this renderbuffer */ write_buffer = intel_region_buffer(intel, irb->region, all ? INTEL_WRITE_FULL : INTEL_WRITE_PART); @@ -333,8 +337,7 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) clear[3], clear[3]); break; default: - fail_mask |= bufBit; - mask &= ~bufBit; + fail_mask |= 1 << buf; continue; } } @@ -367,8 +370,6 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask) if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL); - else -mask &= ~bufBit;/* turn off bit, for faster loop exit */ } return fail_mask; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Avoid name clash of loop counter and member
Module: Mesa Branch: master Commit: 252eaa765e69a70036ec33a7e1e0ffeac1aab2ff URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=252eaa765e69a70036ec33a7e1e0ffeac1aab2ff Author: Chris Wilson Date: Tue Mar 29 15:39:01 2011 +0100 i965: Avoid name clash of loop counter and member src/mesa/drivers/dri/i965/brw_fs.cpp:565 warning: name lookup of ‘c’ changed Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index b2336b7..bdf0523 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -547,16 +547,16 @@ fs_visitor::emit_general_interpolation(ir_variable *ir) * handed us defined values in only the constant offset * field of the setup reg. */ - for (unsigned int c = 0; c < type->vector_elements; c++) { - struct brw_reg interp = interp_reg(location, c); + for (unsigned int k = 0; k < type->vector_elements; k++) { + struct brw_reg interp = interp_reg(location, k); interp = suboffset(interp, 3); emit(FS_OPCODE_CINTERP, attr, fs_reg(interp)); attr.reg_offset++; } } else { /* Perspective interpolation case. */ - for (unsigned int c = 0; c < type->vector_elements; c++) { - struct brw_reg interp = interp_reg(location, c); + for (unsigned int k = 0; k < type->vector_elements; k++) { + struct brw_reg interp = interp_reg(location, k); emit(FS_OPCODE_LINTERP, attr, this->delta_x, this->delta_y, fs_reg(interp)); attr.reg_offset++; @@ -564,7 +564,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir) if (intel->gen < 6 && !(is_gl_Color && c->key.linear_color)) { attr.reg_offset -= type->vector_elements; - for (unsigned int c = 0; c < type->vector_elements; c++) { + for (unsigned int k = 0; k < type->vector_elements; k++) { emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w); attr.reg_offset++; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Detect allocation failure of batch buffer
Module: Mesa Branch: master Commit: b094dff50a05e56f5415d31daa5e4542f321c858 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b094dff50a05e56f5415d31daa5e4542f321c858 Author: Chris Wilson Date: Thu Mar 10 18:01:32 2011 + i915: Detect allocation failure of batch buffer Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_vtbl.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 921183b..942ebec 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -307,6 +307,10 @@ i915_emit_state(struct intel_context *intel) false); count = 0; again: + if (intel->batch.bo == NULL) { + _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state"); + assert(0); + } aper_count = 0; dirty = get_dirty(state); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Add some defense against bo allocation failure
Module: Mesa Branch: master Commit: f627d429bda8196fd20f2023374ad6d34e4becb6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f627d429bda8196fd20f2023374ad6d34e4becb6 Author: Chris Wilson Date: Fri Mar 4 15:04:09 2011 + intel: Add some defense against bo allocation failure Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_regions.c | 18 +++--- 1 files changed, 11 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index 0857fa8..a4da1ce 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -149,11 +149,6 @@ intel_region_alloc_internal(struct intel_screen *screen, { struct intel_region *region; - if (buffer == NULL) { - _DBG("%s <-- NULL\n", __FUNCTION__); - return NULL; - } - region = calloc(sizeof(*region), 1); if (region == NULL) return region; @@ -180,6 +175,7 @@ intel_region_alloc(struct intel_screen *screen, drm_intel_bo *buffer; unsigned long flags = 0; unsigned long aligned_pitch; + struct intel_region *region; if (expect_accelerated_upload) flags |= BO_ALLOC_FOR_RENDER; @@ -187,9 +183,17 @@ intel_region_alloc(struct intel_screen *screen, buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region", width, height, cpp, &tiling, &aligned_pitch, flags); + if (buffer == NULL) + return NULL; - return intel_region_alloc_internal(screen, cpp, width, height, - aligned_pitch / cpp, tiling, buffer); + region = intel_region_alloc_internal(screen, cpp, width, height, +aligned_pitch / cpp, tiling, buffer); + if (region == NULL) { + drm_intel_bo_unreference(buffer); + return NULL; + } + + return region; } GLboolean ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: check for miptree allocation failure
Module: Mesa Branch: master Commit: 6547253bd138db815173c00ca2dc220e8ad20ab1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6547253bd138db815173c00ca2dc220e8ad20ab1 Author: Chris Wilson Date: Fri Mar 4 15:14:11 2011 + intel: check for miptree allocation failure Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_tex_validate.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c b/src/mesa/drivers/dri/intel/intel_tex_validate.c index 8537e7f..a11b07e 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_validate.c +++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c @@ -140,6 +140,8 @@ intel_finalize_mipmap_tree(struct intel_context *intel, GLuint unit) cpp, comp_byte, GL_TRUE); + if (!intelObj->mt) + return GL_FALSE; } /* Pull in any images not in the object's tree: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Add some defense against buffer allocation failure for subimage blits
Module: Mesa Branch: master Commit: de7678ef521f4fb34459e407a66ab8bf8be733e1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de7678ef521f4fb34459e407a66ab8bf8be733e1 Author: Chris Wilson Date: Fri Mar 4 15:04:36 2011 + intel: Add some defense against buffer allocation failure for subimage blits Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_tex_subimage.c | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_subimage.c b/src/mesa/drivers/dri/intel/intel_tex_subimage.c index 6b7f13f..d0f8294 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_subimage.c +++ b/src/mesa/drivers/dri/intel/intel_tex_subimage.c @@ -90,19 +90,19 @@ intelTexSubimage(struct gl_context * ctx, intel->gen < 6 && target == GL_TEXTURE_2D && drm_intel_bo_busy(dst_bo)) { -unsigned long pitch; -uint32_t tiling_mode = I915_TILING_NONE; -temp_bo = drm_intel_bo_alloc_tiled(intel->bufmgr, - "subimage blit bo", - width, height, - intelImage->mt->cpp, - &tiling_mode, - &pitch, - 0); -drm_intel_gem_bo_map_gtt(temp_bo); +dstRowStride = width * intelImage->mt->cpp; + temp_bo = drm_intel_bo_alloc(intel->bufmgr, "subimage blit bo", + dstRowStride * height, 0); + if (!temp_bo) +return; + +if (drm_intel_gem_bo_map_gtt(temp_bo)) { +drm_intel_bo_unreference(temp_bo); +return; + } + texImage->Data = temp_bo->virtual; texImage->ImageOffsets[0] = 0; -dstRowStride = pitch; intel_miptree_get_image_offset(intelImage->mt, level, intelImage->face, 0, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix extending VB packets
Module: Mesa Branch: master Commit: 9d31138f53c0bee9193af73850ab6febddd29f51 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d31138f53c0bee9193af73850ab6febddd29f51 Author: Chris Wilson Date: Thu Mar 3 22:34:22 2011 + i965: Fix extending VB packets Computation of the delta of this array from the last had a silly little bug and ignored any initial delta==0 causing grief in Nexuiz and friends. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4478ef9..e96c32a 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -484,7 +484,7 @@ static void brw_prepare_vertices(struct brw_context *brw) } /* can we simply extend the current vb? */ - if (0 && j == brw->vb.nr_current_buffers) { + if (j == brw->vb.nr_current_buffers) { int delta = 0; for (i = 0; i < j; i++) { int d; @@ -494,7 +494,7 @@ static void brw_prepare_vertices(struct brw_context *brw) break; d = brw->vb.buffers[i].offset - brw->vb.current_buffers[i].offset; -if (delta == 0) +if (i == 0) delta = d / brw->vb.current_buffers[i].stride; if (delta * brw->vb.current_buffers[i].stride != d) break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Handle URB_FENCE erratum for Broadwater
Module: Mesa Branch: master Commit: 18dd7932c7fc13e230384bcab08311a5de5d6de7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18dd7932c7fc13e230384bcab08311a5de5d6de7 Author: Chris Wilson Date: Thu Mar 3 18:15:03 2011 + i965: Handle URB_FENCE erratum for Broadwater There is a silicon bug which causes unpredictable behaviour if the URB_FENCE command should cross a cache-line boundary. Pad before the command to avoid such occurrences. As this command only applies to gen4/5, do the fixup unconditionally as the specs do not actually state for which chip it was fixed (and the cost is negligible)... Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_urb.c |8 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index dfc1551..b0419d8 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -248,5 +248,13 @@ void brw_upload_urb_fence(struct brw_context *brw) uf.bits1.sf_fence = brw->urb.cs_start; uf.bits1.cs_fence = brw->urb.size; + /* erratum: URB_FENCE must not cross a 64byte cacheline */ + if ((brw->intel.batch.used & 15) > 12) { + int pad = 16 - (brw->intel.batch.used & 15); + do +brw->intel.batch.map[brw->intel.batch.used++] = MI_NOOP; + while (--pad); + } + BRW_BATCH_STRUCT(brw, &uf); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Align index to type size and flush if the type changes
Module: Mesa Branch: master Commit: 1546291e5b8d3ac02f5bee38252f9d479bcf95cc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1546291e5b8d3ac02f5bee38252f9d479bcf95cc Author: Chris Wilson Date: Thu Mar 3 15:56:39 2011 + i965: Align index to type size and flush if the type changes Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.h |4 ++-- src/mesa/drivers/dri/i965/brw_draw_upload.c | 21 ++--- src/mesa/drivers/dri/intel/intel_buffer_objects.c |6 +++--- src/mesa/drivers/dri/intel/intel_buffer_objects.h |1 + src/mesa/drivers/dri/intel/intel_tex_image.c |3 ++- 5 files changed, 22 insertions(+), 13 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 897220b..26a6388 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -517,9 +517,9 @@ struct brw_context */ const struct _mesa_index_buffer *ib; - /* Updates to these fields are signaled by BRW_NEW_INDEX_BUFFER. */ + /* Updates are signaled by BRW_NEW_INDEX_BUFFER. */ drm_intel_bo *bo; - unsigned int offset; + GLuint type; /* Offset to index buffer index to use in CMD_3D_PRIM so that we can * avoid re-uploading the IB packet over and over if we're actually diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 351ae07..4478ef9 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -343,7 +343,8 @@ static void brw_prepare_vertices(struct brw_context *brw) struct brw_vertex_buffer *buffer = &brw->vb.buffers[j]; /* Named buffer object: Just reference its contents directly. */ - buffer->bo = intel_bufferobj_source(intel, intel_buffer, +buffer->bo = intel_bufferobj_source(intel, +intel_buffer, type_size, &buffer->offset); drm_intel_bo_reference(buffer->bo); buffer->offset += (uintptr_t)glarray->Ptr; @@ -670,7 +671,6 @@ static void brw_prepare_indices(struct brw_context *brw) intel_upload_data(&brw->intel, index_buffer->ptr, ib_size, ib_type_size, &bo, &offset); brw->ib.start_vertex_offset = offset / ib_type_size; - offset = 0; } else { offset = (GLuint) (unsigned long) index_buffer->ptr; @@ -687,7 +687,6 @@ static void brw_prepare_indices(struct brw_context *brw) intel_upload_data(&brw->intel, map, ib_size, ib_type_size, &bo, &offset); brw->ib.start_vertex_offset = offset / ib_type_size; - offset = 0; ctx->Driver.UnmapBuffer(ctx, GL_ELEMENT_ARRAY_BUFFER_ARB, bufferobj); } else { @@ -697,22 +696,30 @@ static void brw_prepare_indices(struct brw_context *brw) */ brw->ib.start_vertex_offset = offset / ib_type_size; - bo = intel_bufferobj_source(intel, intel_buffer_object(bufferobj), + bo = intel_bufferobj_source(intel, + intel_buffer_object(bufferobj), + ib_type_size, &offset); drm_intel_bo_reference(bo); + + brw->ib.start_vertex_offset += offset / ib_type_size; } } - if (brw->ib.bo != bo || brw->ib.offset != offset) { + if (brw->ib.bo != bo) { drm_intel_bo_unreference(brw->ib.bo); brw->ib.bo = bo; - brw->ib.offset = offset; brw_add_validated_bo(brw, brw->ib.bo); brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER; } else { drm_intel_bo_unreference(bo); } + + if (index_buffer->type != brw->ib.type) { + brw->ib.type = index_buffer->type; + brw->state.dirty.brw |= BRW_NEW_INDEX_BUFFER; + } } const struct brw_tracked_state brw_indices = { @@ -739,7 +746,7 @@ static void brw_emit_index_buffer(struct brw_context *brw) 1); OUT_RELOC(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, - brw->ib.offset); + 0); OUT_RELOC(brw->ib.bo, I915_GEM_DOMAIN_VERTEX, 0, brw->ib.bo->size - 1); diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c index 2f750a7..439d6fc 100644 --- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c @@ -723,11 +723,11 @@ void intel_upload_unmap(struct intel_context *intel, drm_intel_bo * intel_bufferobj_source(struct intel_context *intel, struct intel_buffer_obje
Mesa (master): intel: Add couple of missing gen6 commands to decode
Module: Mesa Branch: master Commit: 1c0d09cd4efabf4e804780ebc45f1d120f6509c5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c0d09cd4efabf4e804780ebc45f1d120f6509c5 Author: Chris Wilson Date: Sun Feb 27 19:21:54 2011 + intel: Add couple of missing gen6 commands to decode Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_decode.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_decode.c b/src/mesa/drivers/dri/intel/intel_decode.c index 25b4131..688b8fe 100644 --- a/src/mesa/drivers/dri/intel/intel_decode.c +++ b/src/mesa/drivers/dri/intel/intel_decode.c @@ -1601,10 +1601,12 @@ decode_3d_965(uint32_t *data, int count, uint32_t hw_offset, uint32_t devid, int { 0x790a, 3, 3, "3DSTATE_AA_LINE_PARAMETERS" }, { 0x790b, 4, 4, "3DSTATE_GS_SVB_INDEX" }, { 0x790d, 3, 3, "3DSTATE_MULTISAMPLE" }, + { 0x7910, 2, 2, "3DSTATE_CLEAR_PARAMS" }, { 0x7b00, 6, 6, "3DPRIMITIVE" }, { 0x7802, 4, 4, "3DSTATE_SAMPLER_STATE_POINTERS" }, { 0x7805, 3, 3, "3DSTATE_URB" }, { 0x780e, 4, 4, "3DSTATE_CC_STATE_POINTERS" }, + { 0x780f, 2, 2, "3DSTATE_SCISSOR_STATE_POINTERS" }, { 0x7810, 6, 6, "3DSTATE_VS_STATE" }, { 0x7811, 7, 7, "3DSTATE_GS_STATE" }, { 0x7812, 4, 4, "3DSTATE_CLIP_STATE" }, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Prevent using a zero sized (or of unknown type) vertex array
Module: Mesa Branch: master Commit: b93684f5f311f89c965960ab42bfea71a397b180 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b93684f5f311f89c965960ab42bfea71a397b180 Author: Chris Wilson Date: Thu Mar 3 11:25:30 2011 + i965: Prevent using a zero sized (or of unknown type) vertex array Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 11 ++- 1 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 185f1ff..351ae07 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -208,7 +208,7 @@ static GLuint get_surface_type( GLenum type, GLuint size, case GL_UNSIGNED_SHORT: return ushort_types_scale[size]; case GL_UNSIGNED_BYTE: return ubyte_types_scale[size]; default: assert(0); return 0; - } + } } } @@ -225,11 +225,11 @@ static GLuint get_size( GLenum type ) case GL_UNSIGNED_INT: return sizeof(GLuint); case GL_UNSIGNED_SHORT: return sizeof(GLushort); case GL_UNSIGNED_BYTE: return sizeof(GLubyte); - default: return 0; - } + default: assert(0); return 0; + } } -static GLuint get_index_type(GLenum type) +static GLuint get_index_type(GLenum type) { switch (type) { case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE; @@ -295,7 +295,8 @@ static void brw_prepare_vertices(struct brw_context *brw) struct brw_vertex_element *input = &brw->vb.inputs[i]; vs_inputs &= ~(1 << i); - brw->vb.enabled[brw->vb.nr_enabled++] = input; + if (input->glarray->Size && get_size(input->glarray->Type)) + brw->vb.enabled[brw->vb.nr_enabled++] = input; } if (brw->vb.nr_enabled == 0) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): configure: Bump libdrm requirements
Module: Mesa Branch: master Commit: faf1ddacfb006fe50d81aab50b33356567cafaba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=faf1ddacfb006fe50d81aab50b33356567cafaba Author: Chris Wilson Date: Tue Mar 1 18:39:15 2011 + configure: Bump libdrm requirements In my last commit I introduced a build dependency upon a new libdrm. Add the associated autoconf checks. As the headers are part of the core libdrm, we need to bump that version and so may as well bump the chipset specific versions simultaneously. Signed-off-by: Chris Wilson --- configure.ac |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/configure.ac b/configure.ac index fbc7436..dcfddb1 100644 --- a/configure.ac +++ b/configure.ac @@ -18,12 +18,12 @@ AC_CONFIG_AUX_DIR([bin]) AC_CANONICAL_HOST dnl Versions for external dependencies -LIBDRM_REQUIRED=2.4.23 -LIBDRM_RADEON_REQUIRED=2.4.23 -LIBDRM_INTEL_REQUIRED=2.4.23 +LIBDRM_REQUIRED=2.4.24 +LIBDRM_RADEON_REQUIRED=2.4.24 +LIBDRM_INTEL_REQUIRED=2.4.24 DRI2PROTO_REQUIRED=2.1 GLPROTO_REQUIRED=1.4.11 -LIBDRM_XORG_REQUIRED=2.4.23 +LIBDRM_XORG_REQUIRED=2.4.24 LIBKMS_XORG_REQUIRED=1.0.0 dnl Check for progs ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use negative relocation deltas to minimse vertex uploads
Module: Mesa Branch: master Commit: 900a5c91eeb3acae7ee0ad331154531c4dba96e1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=900a5c91eeb3acae7ee0ad331154531c4dba96e1 Author: Chris Wilson Date: Tue Mar 1 14:46:50 2011 + i965: Use negative relocation deltas to minimse vertex uploads With relaxed relocation checking in the kernel, we can specify a negative delta (i.e. pointing outside of the target bo) in order to fake a range in a large buffer. We only then need to upload the elements used and adjust the buffer offset such that they correspond with the indices used in the DrawArrays. (Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6) Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.h |2 +- src/mesa/drivers/dri/i965/brw_draw_upload.c | 21 ++--- src/mesa/drivers/dri/intel/intel_screen.c | 11 +++ src/mesa/drivers/dri/intel/intel_screen.h |1 + 4 files changed, 27 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 2e8561d..897220b 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -460,7 +460,7 @@ struct brw_context GLboolean has_negative_rhw_bug; GLboolean has_aa_line_parameters; GLboolean has_pln; -; + struct { struct brw_state_flags dirty; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 1e129f9..185f1ff 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -278,7 +278,7 @@ static void brw_prepare_vertices(struct brw_context *brw) GLuint interleaved = 0, total_size = 0; unsigned int min_index = brw->vb.min_index; unsigned int max_index = brw->vb.max_index; - int i, j; + int delta, i, j; struct brw_vertex_element *upload[VERT_ATTRIB_MAX]; GLuint nr_uploads = 0; @@ -401,21 +401,25 @@ static void brw_prepare_vertices(struct brw_context *brw) * only the used elements [min_index, max_index] so long as we adjust all * the values used in the 3DPRIMITIVE i.e. by setting the vertex bias. */ + brw->vb.start_vertex_bias = 0; + delta = min_index; if (nr_uploads == brw->vb.nr_enabled) { - brw->vb.start_vertex_bias = min_index; - } else { - brw->vb.start_vertex_bias = 0; - min_index = 0; + brw->vb.start_vertex_bias = -delta; + delta = 0; } + if (delta && !brw->intel.intelScreen->relaxed_relocations) + min_index = delta = 0; /* Handle any arrays to be uploaded. */ if (nr_uploads > 1) { if (interleaved && interleaved <= 2*total_size) { +struct brw_vertex_buffer *buffer = &brw->vb.buffers[j]; /* All uploads are interleaved, so upload the arrays together as * interleaved. First, upload the contents and set up upload[0]. */ copy_array_to_vbo_array(brw, upload[0], min_index, max_index, -&brw->vb.buffers[j], interleaved); +buffer, interleaved); +buffer->offset -= delta * interleaved; for (i = 0; i < nr_uploads; i++) { /* Then, just point upload[i] at upload[0]'s buffer. */ @@ -462,14 +466,17 @@ static void brw_prepare_vertices(struct brw_context *brw) intel_upload_unmap(&brw->intel, map, offset * count, offset, &buffer->bo, &buffer->offset); buffer->stride = offset; +buffer->offset -= delta * offset; nr_uploads = 0; } } /* Upload non-interleaved arrays */ for (i = 0; i < nr_uploads; i++) { + struct brw_vertex_buffer *buffer = &brw->vb.buffers[j]; copy_array_to_vbo_array(brw, upload[i], min_index, max_index, - &brw->vb.buffers[j], upload[i]->element_size); + buffer, upload[i]->element_size); + buffer->offset -= delta * buffer->stride; upload[i]->buffer = j++; upload[i]->offset = 0; } diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c index 746da46..5c95c72 100644 --- a/src/mesa/drivers/dri/intel/intel_screen.c +++ b/src/mesa/drivers/dri/intel/intel_screen.c @@ -309,6 +309,13 @@ intel_get_param(__DRIscreen *psp, int param, int *value) return GL_TRUE; } +static GLboolean +intel_get_boolean(__DRIscreen *psp, int param) +{ + int value = 0; + return intel_get_param(psp, param, &value) && value; +} + static void nop_callback(GLuint key, void *data, void *userData) { @@ -482,6 +489,10 @@ intel_init_bufmgr(struct intel_screen *intelScreen) intelScreen->named_regions = _mesa_NewHashTable(); + intelScreen->relaxed_relocations =
Mesa (master): i965: Undo 'continuation of vb packets'
Module: Mesa Branch: master Commit: 9fa380ccdcf987430b9bff8e5216869e05b0aaea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fa380ccdcf987430b9bff8e5216869e05b0aaea Author: Chris Wilson Date: Tue Mar 1 15:57:42 2011 + i965: Undo 'continuation of vb packets' This breaks nexuiz for unknown reason; disable until a true fix can be found. --- src/mesa/drivers/dri/i965/brw_draw_upload.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index baf35a6..1e129f9 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -475,7 +475,7 @@ static void brw_prepare_vertices(struct brw_context *brw) } /* can we simply extend the current vb? */ - if (j == brw->vb.nr_current_buffers) { + if (0 && j == brw->vb.nr_current_buffers) { int delta = 0; for (i = 0; i < j; i++) { int d; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix uploading of shortened vertex packets
Module: Mesa Branch: master Commit: 69b3f24658b74f15b622adda6464a6fcb87f4ee6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69b3f24658b74f15b622adda6464a6fcb87f4ee6 Author: Chris Wilson Date: Tue Mar 1 14:12:22 2011 + i965: Fix uploading of shortened vertex packets ... handle all cases and not just the interleaved upload. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c | 25 + 1 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4156523..baf35a6 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -242,30 +242,31 @@ static GLuint get_index_type(GLenum type) static void copy_array_to_vbo_array(struct brw_context *brw, struct brw_vertex_element *element, - int count, + int min, int max, struct brw_vertex_buffer *buffer, GLuint dst_stride) { + int src_stride = element->glarray->StrideB; + const unsigned char *src = element->glarray->Ptr + min * src_stride; + int count = max - min + 1; GLuint size = count * dst_stride; - buffer->stride = dst_stride; - if (dst_stride == element->glarray->StrideB) { - intel_upload_data(&brw->intel, element->glarray->Ptr, size, dst_stride, + if (dst_stride == src_stride) { + intel_upload_data(&brw->intel, src, size, dst_stride, &buffer->bo, &buffer->offset); } else { - const unsigned char *src = element->glarray->Ptr; - char *map = intel_upload_map(&brw->intel, size, dst_stride); + char * const map = intel_upload_map(&brw->intel, size, dst_stride); char *dst = map; - int i; - for (i = 0; i < count; i++) { + while (count--) { memcpy(dst, src, dst_stride); -src += element->glarray->StrideB; +src += src_stride; dst += dst_stride; } intel_upload_unmap(&brw->intel, map, size, dst_stride, &buffer->bo, &buffer->offset); } + buffer->stride = dst_stride; } static void brw_prepare_vertices(struct brw_context *brw) @@ -413,7 +414,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* All uploads are interleaved, so upload the arrays together as * interleaved. First, upload the contents and set up upload[0]. */ -copy_array_to_vbo_array(brw, upload[0], max_index - min_index + 1, +copy_array_to_vbo_array(brw, upload[0], min_index, max_index, &brw->vb.buffers[j], interleaved); for (i = 0; i < nr_uploads; i++) { @@ -443,7 +444,7 @@ static void brw_prepare_vertices(struct brw_context *brw) offset = ALIGN(offset, get_size(upload[i]->glarray->Type)); dst = map + offset; - src += min_index * size; + src += min_index * stride; for (n = 0; n < count; n++) { memcpy(dst, src, size); @@ -467,7 +468,7 @@ static void brw_prepare_vertices(struct brw_context *brw) } /* Upload non-interleaved arrays */ for (i = 0; i < nr_uploads; i++) { - copy_array_to_vbo_array(brw, upload[i], max_index - min_index + 1, + copy_array_to_vbo_array(brw, upload[i], min_index, max_index, &brw->vb.buffers[j], upload[i]->element_size); upload[i]->buffer = j++; upload[i]->offset = 0; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Upload all vertices used
Module: Mesa Branch: master Commit: 6ddfb322f58c7e00db73e25689ee55ffabd9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ddfb322f58c7e00db73e25689ee55ffabd9 Author: Chris Wilson Date: Thu Feb 24 14:06:55 2011 + i965: Upload all vertices used ... and take advantage of start_vertex_bias to trim to [min_index, max_index] where possible (i.e. when we need to upload all arrays). Fixes half_float_vertex(misc.fillmode.wireframe) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34595 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_context.h |2 - src/mesa/drivers/dri/i965/brw_draw_upload.c | 67 +++ 2 files changed, 38 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 3e52304..2e8561d 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -424,8 +424,6 @@ struct brw_vertex_element { gl_vert_attrib attrib; /** Size of a complete element */ GLuint element_size; - /** Number of uploaded elements for this input. */ - GLuint count; /** Offset of the first element within the buffer object */ unsigned int offset; }; diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 7234ce2..4156523 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -240,12 +240,13 @@ static GLuint get_index_type(GLenum type) } static void -copy_array_to_vbo_array( struct brw_context *brw, -struct brw_vertex_element *element, -struct brw_vertex_buffer *buffer, -GLuint dst_stride) +copy_array_to_vbo_array(struct brw_context *brw, + struct brw_vertex_element *element, + int count, + struct brw_vertex_buffer *buffer, + GLuint dst_stride) { - GLuint size = element->count * dst_stride; + GLuint size = count * dst_stride; buffer->stride = dst_stride; if (dst_stride == element->glarray->StrideB) { @@ -257,7 +258,7 @@ copy_array_to_vbo_array( struct brw_context *brw, char *dst = map; int i; - for (i = 0; i < element->count; i++) { + for (i = 0; i < count; i++) { memcpy(dst, src, dst_stride); src += element->glarray->StrideB; dst += dst_stride; @@ -271,9 +272,9 @@ static void brw_prepare_vertices(struct brw_context *brw) { struct gl_context *ctx = &brw->intel.ctx; struct intel_context *intel = intel_context(ctx); - GLbitfield vs_inputs = brw->vs.prog_data->inputs_read; + GLbitfield vs_inputs = brw->vs.prog_data->inputs_read; const unsigned char *ptr = NULL; - GLuint interleaved = 0, total_size = 0, count = -1; + GLuint interleaved = 0, total_size = 0; unsigned int min_index = brw->vb.min_index; unsigned int max_index = brw->vb.max_index; int i, j; @@ -349,7 +350,6 @@ static void brw_prepare_vertices(struct brw_context *brw) input->buffer = j++; input->offset = 0; } -input->count = glarray->_MaxElement; /* This is a common place to reach if the user mistakenly supplies * a pointer in place of a VBO offset. If we just let it go through, @@ -365,8 +365,6 @@ static void brw_prepare_vertices(struct brw_context *brw) */ assert(input->offset < brw->vb.buffers[input->buffer].bo->size); } else { -input->count = glarray->StrideB ? max_index + 1 : 1; - /* Queue the buffer object up to be uploaded in the next pass, * when we've decided if we're doing interleaved or not. */ @@ -386,30 +384,37 @@ static void brw_prepare_vertices(struct brw_context *brw) { interleaved = 0; } -else if (total_size & (type_size -1)) +else if ((uintptr_t)(glarray->Ptr - ptr) & (type_size -1)) { /* enforce natural alignment (for doubles) */ interleaved = 0; } -if (count > input->count) - count = input->count; - upload[nr_uploads++] = input; +total_size = ALIGN(total_size, type_size); total_size += input->element_size; } } + /* If we need to upload all the arrays, then we can trim those arrays to +* only the used elements [min_index, max_index] so long as we adjust all +* the values used in the 3DPRIMITIVE i.e. by setting the vertex bias. +*/ + if (nr_uploads == brw->vb.nr_enabled) { + brw->vb.start_vertex_bias = min_index; + } else { + brw->vb.start_vertex_bias = 0; + min_index = 0; + } + /* Handle any arrays to be uploaded. */ if (nr_upload
Mesa (master): intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
Module: Mesa Branch: master Commit: c0ad70ae31ee5501281b434d56e389fc92b13a3a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0ad70ae31ee5501281b434d56e389fc92b13a3a Author: Neil Roberts Date: Sat Feb 5 10:21:11 2011 + intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer In the case where glBlitFramebuffer is being used to copy to a texture without scaling it is faster if we can use the hardware to do a blit rather than having to do a texture render. In most of the drivers glCopyTexSubImage2D will use a blit so this patch makes it check for when glBlitFramebuffer is doing a simple copy and then divert to glCopyTexSubImage2D. This was originally proposed as an extension to the common meta-ops. However, it was rejected as using the BLT is only advantageous for Intel hardware. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_fbo.c | 81 ++- src/mesa/drivers/dri/intel/intel_tex.h |8 +++ src/mesa/drivers/dri/intel/intel_tex_copy.c | 41 +++--- 3 files changed, 108 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index 886b25c..8b57eb1 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -34,6 +34,7 @@ #include "main/framebuffer.h" #include "main/renderbuffer.h" #include "main/context.h" +#include "main/teximage.h" #include "main/texrender.h" #include "drivers/common/meta.h" @@ -647,6 +648,84 @@ intel_validate_framebuffer(struct gl_context *ctx, struct gl_framebuffer *fb) } } +/** + * Try to do a glBlitFramebuffer using glCopyTexSubImage2D + * We can do this when the dst renderbuffer is actually a texture and + * there is no scaling, mirroring or scissoring. + * + * \return new buffer mask indicating the buffers left to blit using the + * normal path. + */ +static GLbitfield +intel_blit_framebuffer_copy_tex_sub_image(struct gl_context *ctx, + GLint srcX0, GLint srcY0, + GLint srcX1, GLint srcY1, + GLint dstX0, GLint dstY0, + GLint dstX1, GLint dstY1, + GLbitfield mask, GLenum filter) +{ + if (mask & GL_COLOR_BUFFER_BIT) { + const struct gl_framebuffer *drawFb = ctx->DrawBuffer; + const struct gl_framebuffer *readFb = ctx->ReadBuffer; + const struct gl_renderbuffer_attachment *drawAtt = + &drawFb->Attachment[drawFb->_ColorDrawBufferIndexes[0]]; + + /* If the source and destination are the same size with no + mirroring, the rectangles are within the size of the + texture and there is no scissor then we can use + glCopyTexSubimage2D to implement the blit. This will end + up as a fast hardware blit on some drivers */ + if (drawAtt && drawAtt->Texture && + srcX0 - srcX1 == dstX0 - dstX1 && + srcY0 - srcY1 == dstY0 - dstY1 && + srcX1 >= srcX0 && + srcY1 >= srcY0 && + srcX0 >= 0 && srcX1 <= readFb->Width && + srcY0 >= 0 && srcY1 <= readFb->Height && + dstX0 >= 0 && dstX1 <= drawFb->Width && + dstY0 >= 0 && dstY1 <= drawFb->Height && + !ctx->Scissor.Enabled) { + const struct gl_texture_object *texObj = drawAtt->Texture; + const GLuint dstLevel = drawAtt->TextureLevel; + const GLenum target = texObj->Target; + + struct gl_texture_image *texImage = +_mesa_select_tex_image(ctx, texObj, target, dstLevel); + GLenum internalFormat = texImage->InternalFormat; + + if (intel_copy_texsubimage(intel_context(ctx), target, +intel_texture_image(texImage), +internalFormat, +dstX0, dstY0, +srcX0, srcY0, +srcX1 - srcX0, /* width */ +srcY1 - srcY0)) +mask &= ~GL_COLOR_BUFFER_BIT; + } + } + + return mask; +} + +static void +intel_blit_framebuffer(struct gl_context *ctx, + GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1, + GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1, + GLbitfield mask, GLenum filter) +{ + /* Try faster, glCopyTexSubImage2D approach first which uses the BLT. */ + mask = intel_blit_framebuffer_copy_tex_sub_image(ctx, +
Mesa (master): i965: Remember to pack the constant blend color as floats into the batch
Module: Mesa Branch: master Commit: f19439940c43aa9d937716c6f1ee70cc26799e08 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f19439940c43aa9d937716c6f1ee70cc26799e08 Author: Chris Wilson Date: Thu Feb 24 12:59:52 2011 + i965: Remember to pack the constant blend color as floats into the batch Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_cc.c |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index b7048ec..412d82a 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -238,10 +238,10 @@ static void upload_blend_constant_color(struct brw_context *brw) BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR << 16 | (5-2)); - OUT_BATCH(ctx->Color.BlendColor[0]); - OUT_BATCH(ctx->Color.BlendColor[1]); - OUT_BATCH(ctx->Color.BlendColor[2]); - OUT_BATCH(ctx->Color.BlendColor[3]); + OUT_BATCH_F(ctx->Color.BlendColor[0]); + OUT_BATCH_F(ctx->Color.BlendColor[1]); + OUT_BATCH_F(ctx->Color.BlendColor[2]); + OUT_BATCH_F(ctx->Color.BlendColor[3]); CACHED_BATCH(); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Reset the buffer offset after releasing reference to packed upload
Module: Mesa Branch: master Commit: 5ce0f7f10908a0636900bae783cb426a6c607673 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ce0f7f10908a0636900bae783cb426a6c607673 Author: Chris Wilson Date: Thu Feb 24 12:29:51 2011 + intel: Reset the buffer offset after releasing reference to packed upload Fixes oglc/vbo(basic.bufferdata) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |1 + src/mesa/drivers/dri/intel/intel_buffer_objects.c | 134 - 2 files changed, 77 insertions(+), 58 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4efb3cd..7234ce2 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -338,6 +338,7 @@ static void brw_prepare_vertices(struct brw_context *brw) } if (k == i) { struct brw_vertex_buffer *buffer = &brw->vb.buffers[j]; + /* Named buffer object: Just reference its contents directly. */ buffer->bo = intel_bufferobj_source(intel, intel_buffer, &buffer->offset); diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c index bc57803..2f750a7 100644 --- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c @@ -53,6 +53,15 @@ intel_bufferobj_alloc_buffer(struct intel_context *intel, intel_obj->Base.Size, 64); } +static void +release_buffer(struct intel_buffer_object *intel_obj) +{ + drm_intel_bo_unreference(intel_obj->buffer); + intel_obj->buffer = NULL; + intel_obj->offset = 0; + intel_obj->source = 0; +} + /** * There is some duplication between mesa's bufferobjects and our * bufmgr buffers. Both have an integer handle and a hashtable to @@ -81,8 +90,7 @@ intel_bufferobj_release_region(struct intel_context *intel, intel_obj->region->pbo = NULL; intel_obj->region = NULL; - drm_intel_bo_unreference(intel_obj->buffer); - intel_obj->buffer = NULL; + release_buffer(intel_obj); } /* Break the COW tie to the region. Both the pbo and the region end @@ -152,11 +160,9 @@ intel_bufferobj_data(struct gl_context * ctx, if (intel_obj->region) intel_bufferobj_release_region(intel, intel_obj); - if (intel_obj->buffer != NULL) { - drm_intel_bo_unreference(intel_obj->buffer); - intel_obj->buffer = NULL; - intel_obj->source = 0; - } + if (intel_obj->buffer != NULL) + release_buffer(intel_obj); + free(intel_obj->sys_buffer); intel_obj->sys_buffer = NULL; @@ -204,6 +210,7 @@ intel_bufferobj_subdata(struct gl_context * ctx, { struct intel_context *intel = intel_context(ctx); struct intel_buffer_object *intel_obj = intel_buffer_object(obj); + bool busy; if (size == 0) return; @@ -213,47 +220,53 @@ intel_bufferobj_subdata(struct gl_context * ctx, if (intel_obj->region) intel_bufferobj_cow(intel, intel_obj); + /* If we have a single copy in system memory, update that */ if (intel_obj->sys_buffer) { - if (intel_obj->buffer) { -drm_intel_bo_unreference(intel_obj->buffer); -intel_obj->buffer = NULL; -intel_obj->source = 0; + if (intel_obj->source) +release_buffer(intel_obj); + + if (intel_obj->buffer == NULL) { +memcpy((char *)intel_obj->sys_buffer + offset, data, size); +return; } - memcpy((char *)intel_obj->sys_buffer + offset, data, size); - } else { - bool busy = -drm_intel_bo_busy(intel_obj->buffer) || -drm_intel_bo_references(intel->batch.bo, intel_obj->buffer); - /* replace the current busy bo with fresh data */ - if (busy && size == intel_obj->Base.Size) { -drm_intel_bo_unreference(intel_obj->buffer); -intel_bufferobj_alloc_buffer(intel, intel_obj); -drm_intel_bo_subdata(intel_obj->buffer, 0, size, data); - } else if (intel->gen < 6) { -if (busy) { - drm_intel_bo *temp_bo; + free(intel_obj->sys_buffer); + intel_obj->sys_buffer = NULL; + } - temp_bo = drm_intel_bo_alloc(intel->bufmgr, "subdata temp", size, 64); + /* Otherwise we need to update the copy in video memory. */ + busy = + drm_intel_bo_busy(intel_obj->buffer) || + drm_intel_bo_references(intel->batch.bo, intel_obj->buffer); - drm_intel_bo_subdata(temp_bo, 0, size, data); + /* replace the current busy bo with fresh data */ + if (busy && size == intel_obj->Base.Size) { + drm_intel_bo_unreference(intel_obj
Mesa (master): i965: Unmap the correct pointer after discontiguous upload
Module: Mesa Branch: master Commit: 135ccb2daecb7792dfb17e66ab0acb79a97f78c8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=135ccb2daecb7792dfb17e66ab0acb79a97f78c8 Author: Chris Wilson Date: Thu Feb 24 10:58:22 2011 + i965: Unmap the correct pointer after discontiguous upload Fixes piglit/fbo-depth-sample-compare: ==14722== Invalid free() / delete / delete[] ==14722==at 0x4C240FD: free (vg_replace_malloc.c:366) ==14722==by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695) ==14722==by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722==by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722==by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722==by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722==by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722==by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722==by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722==by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722==by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722==by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd ==14722==at 0x4C244E8: malloc (vg_replace_malloc.c:236) ==14722==by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256) ==14722==by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722==by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722==by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722==by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722==by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722==by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722==by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722==by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722==by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722==by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 140fb4e..4efb3cd 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -253,7 +253,8 @@ copy_array_to_vbo_array( struct brw_context *brw, &buffer->bo, &buffer->offset); } else { const unsigned char *src = element->glarray->Ptr; - char *dst = intel_upload_map(&brw->intel, size, dst_stride); + char *map = intel_upload_map(&brw->intel, size, dst_stride); + char *dst = map; int i; for (i = 0; i < element->count; i++) { @@ -261,7 +262,7 @@ copy_array_to_vbo_array( struct brw_context *brw, src += element->glarray->StrideB; dst += dst_stride; } - intel_upload_unmap(&brw->intel, dst, size, dst_stride, + intel_upload_unmap(&brw->intel, map, size, dst_stride, &buffer->bo, &buffer->offset); } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Protect against waiting on a NULL render target bo
Module: Mesa Branch: master Commit: a2029a78c39427f9bd7e24bbe5a5ff124f9d446b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2029a78c39427f9bd7e24bbe5a5ff124f9d446b Author: Chris Wilson Date: Thu Feb 24 10:12:37 2011 + intel: Protect against waiting on a NULL render target bo If we fall back to software rendering due to the render target being absent (GPU hang or other error in creating the named target), then we do not need to nor should we wait upon the results. Reported-by: Magnus Kessler Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index d22fa27..c2e2a98 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -581,7 +581,7 @@ intelFinish(struct gl_context * ctx) irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); - if (irb && irb->region) + if (irb && irb->region && irb->region->buffer) drm_intel_bo_wait_rendering(irb->region->buffer); } if (fb->_DepthBuffer) { ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: gen3 is particular sensitive to batch size
Module: Mesa Branch: master Commit: 671018aa99528a41955654f62120eeea0c5517e1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=671018aa99528a41955654f62120eeea0c5517e1 Author: Chris Wilson Date: Wed Feb 23 23:09:36 2011 + intel: gen3 is particular sensitive to batch size ... and prefers a small batch whereas gen4+ prefer a large batch to carry more state. Tuning using openarena/padman indicate that a batch size of just 4096 is best for those cases. Bugzilla: https://bugs.freedesktop.org/process_bug.cgi Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 7dbd9d9..d22fa27 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -746,7 +746,7 @@ intelInitContext(struct intel_context *intel, driParseConfigFiles(&intel->optionCache, &intelScreen->optionCache, sPriv->myNum, (intel->gen >= 4) ? "i965" : "i915"); - if (intelScreen->deviceID == PCI_CHIP_I865_G) + if (intel->gen < 4) intel->maxBatchSize = 4096; else intel->maxBatchSize = sizeof(intel->batch.map); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: And remember assign the new value to the state reg...
Module: Mesa Branch: master Commit: 19ac5fa50dbb2f80eb0d47866b1474e3bd7a84dc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19ac5fa50dbb2f80eb0d47866b1474e3bd7a84dc Author: Chris Wilson Date: Wed Feb 23 22:09:12 2011 + i915: And remember assign the new value to the state reg... Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_state.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_state.c b/src/mesa/drivers/dri/i915/i915_state.c index 93d344d..58d4f5d 100644 --- a/src/mesa/drivers/dri/i915/i915_state.c +++ b/src/mesa/drivers/dri/i915/i915_state.c @@ -98,6 +98,7 @@ i915_update_stencil(struct gl_context * ctx) dw &= ~(mask); \ dw |= (set); \ dirty |= dw != i915->state.Ctx[reg]; \ + i915->state.Ctx[reg] = dw; \ } while(0) /* Set front state. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Trim the interleaved upload to the minimum number of vertices
Module: Mesa Branch: master Commit: 3adc108b4a7460ef5d92c0f5f0ee655d4ca6cb32 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3adc108b4a7460ef5d92c0f5f0ee655d4ca6cb32 Author: Chris Wilson Date: Tue Feb 22 11:17:39 2011 + i965: Trim the interleaved upload to the minimum number of vertices ... should have no impact on a properly formatted draw operation. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |6 +- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 4520749..140fb4e 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -272,7 +272,7 @@ static void brw_prepare_vertices(struct brw_context *brw) struct intel_context *intel = intel_context(ctx); GLbitfield vs_inputs = brw->vs.prog_data->inputs_read; const unsigned char *ptr = NULL; - GLuint interleaved = 0, total_size = 0; + GLuint interleaved = 0, total_size = 0, count = -1; unsigned int min_index = brw->vb.min_index; unsigned int max_index = brw->vb.max_index; int i, j; @@ -390,6 +390,9 @@ static void brw_prepare_vertices(struct brw_context *brw) interleaved = 0; } +if (count > input->count) + count = input->count; + upload[nr_uploads++] = input; total_size += input->element_size; } @@ -401,6 +404,7 @@ static void brw_prepare_vertices(struct brw_context *brw) /* All uploads are interleaved, so upload the arrays together as * interleaved. First, upload the contents and set up upload[0]. */ +upload[0]->count = count; /* trim the upload over all arrays */ copy_array_to_vbo_array(brw, upload[0], &brw->vb.buffers[j], interleaved); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Reinstate max-index paranoia
Module: Mesa Branch: master Commit: b4cbd2b312d53a50603e2cda925711bc9def4517 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4cbd2b312d53a50603e2cda925711bc9def4517 Author: Chris Wilson Date: Tue Feb 22 11:19:32 2011 + i965: Reinstate max-index paranoia Don't trust the applications not to reference beyond the end of the vertex buffers. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 6ea877b..4520749 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -550,7 +550,7 @@ static void brw_emit_vertices(struct brw_context *brw) if (intel->gen >= 5) { OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1); } else - OUT_BATCH(0); + OUT_BATCH(buffer->bo->size / buffer->stride); OUT_BATCH(0); /* Instance data step rate */ brw->vb.current_buffers[i].handle = buffer->bo->handle; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Zero the offset into the vbo when uploading non-interleaved
Module: Mesa Branch: master Commit: 3377faffcdc7227bd27381894c87c7600547744f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3377faffcdc7227bd27381894c87c7600547744f Author: Chris Wilson Date: Tue Feb 22 11:18:25 2011 + i965: Zero the offset into the vbo when uploading non-interleaved Fixes regression from 559435d9152acc7162e4e60aae6591c7c6c8274b. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index b15c05a..6ea877b 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -454,6 +454,7 @@ static void brw_prepare_vertices(struct brw_context *brw) upload[i], &brw->vb.buffers[j], upload[i]->element_size); upload[i]->buffer = j++; + upload[i]->offset = 0; } /* can we simply extend the current vb? */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Fix insufficient integer width for upload buffer offset
Module: Mesa Branch: master Commit: 5a1fbf0f70a1c2d444f61494f86e26ca866c31d5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a1fbf0f70a1c2d444f61494f86e26ca866c31d5 Author: Chris Wilson Date: Mon Feb 21 20:56:06 2011 + intel: Fix insufficient integer width for upload buffer offset I was being overly miserly and gave the offset of the buffer into the bo insufficient bits, distracted by the adjacency of the buffer[4096]. Ref: https://bugs.freedesktop.org/show_bug.cgi?id=34541 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_context.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h index 1ab38b1..772b2fb 100644 --- a/src/mesa/drivers/dri/intel/intel_context.h +++ b/src/mesa/drivers/dri/intel/intel_context.h @@ -201,8 +201,8 @@ struct intel_context struct { drm_intel_bo *bo; GLuint offset; - uint16_t buffer_len; - uint16_t buffer_offset; + uint32_t buffer_len; + uint32_t buffer_offset; char buffer[4096]; } upload; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Remove spurious duplicate ADVANCE_BATCH
Module: Mesa Branch: master Commit: a43f20e0699f0b60d1e1e3e7a0693192f8d2895d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a43f20e0699f0b60d1e1e3e7a0693192f8d2895d Author: Chris Wilson Date: Mon Feb 21 16:02:26 2011 + i965: Remove spurious duplicate ADVANCE_BATCH ... a leftover from a bad merge. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i965/brw_draw_upload.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c index 09d7a5e..17af046 100644 --- a/src/mesa/drivers/dri/i965/brw_draw_upload.c +++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c @@ -559,7 +559,6 @@ static void brw_emit_vertices(struct brw_context *brw) brw->vb.nr_current_buffers = i; ADVANCE_BATCH(); } - ADVANCE_BATCH(); BEGIN_BATCH(1 + brw->vb.nr_enabled * 2); OUT_BATCH((CMD_VERTEX_ELEMENT << 16) | (2*brw->vb.nr_enabled - 1)); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): 33 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c6793fb6bc89df16c23f727bcb072a157ab8d10 Author: Chris Wilson Date: Thu Nov 25 15:41:37 2010 + i915: Emit a single relocation per vbo Reducing the number of relocations has lots of nice knock-on effects, not least including reducing batch buffer size, auxilliary array sizes (vmalloced and copied into the kernel), processing of uncached relocations etc. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e Author: Chris Wilson Date: Fri Nov 26 11:18:50 2010 + i915: Suppress emission of redundant stencil updates Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c97e288fb6a105ea60c377aef4472cc33ca01bc Author: Chris Wilson Date: Fri Nov 26 10:57:06 2010 + i915: Separate BLEND from general context state. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f82585e279276e08c719d55218cd64a2c880a6b Author: Chris Wilson Date: Fri Nov 26 10:25:23 2010 + i915: Only flag context changes if the actual state is changed Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b0cad38c57fbe59710cb4058866b2e68f6d471a Author: Chris Wilson Date: Thu Nov 25 22:27:37 2010 + i915: suppress repeated sampler state emission Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87641cffd97f328e846604d314c21582f426a19a Author: Chris Wilson Date: Thu Nov 25 21:39:21 2010 + i915: Eliminate redundant CONSTANTS updates Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=41260a9bf63aa61f88f188053f1ed4dba3a852d2 Author: Chris Wilson Date: Tue Feb 8 22:58:35 2011 + i965: Use compiler builtins when available Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ea6e98c7be6483514769b03ffa6c6f4f7b2e0be Author: Chris Wilson Date: Sun Feb 20 15:36:52 2011 + i965: Micro-optimise check_state Replace the intermediate tests due to the logical or with the bitwise or. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=50ade6ea697953bb17e3ca7210515fbd0411cd1e Author: Chris Wilson Date: Thu Dec 30 21:47:39 2010 + intel: use throttle ioctl for throttling Rather than waiting on the first batch after the last swapbuffers to be retired, call into the kernel to wait upon the retirement of any request less than 20ms old. This has the twofold advantage of (a) not blocking any other clients from utilizing the device whilst we wait and (b) we attain higher throughput without overloading the system. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46131a824ffa3b658c822fd6cc543a5935773a6f Author: Chris Wilson Date: Sat Feb 12 11:28:25 2011 + i965: Remove unused 'next_free_page' member Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57ca0803b34587f1148b218a11d2193b0d4f4c97 Author: Chris Wilson Date: Fri Feb 11 00:03:48 2011 + intel: Skip the flush before read-pixels via blit As we will flush when reading the return values of the blit, we can forgo the earlier flush. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c625aa19cb53ed27f91bfd16fea6ea727e9a5bbd Author: Chris Wilson Date: Fri Feb 18 10:37:43 2011 + intel: extend current vertex buffers If the next vertex arrays are a (discontiguous) continuation of the current arrays, such that the new vertices are simply offset from the start of the current vertex buffer definitions we can reuse those defintions and avoid the overhead of relocations and invalidations. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a07e4811794051dc65187d17b7f85e340e61854e Author: Chris Wilson Date: Fri Feb 18 12:30:37 2011 + intel: Use specified alignment for writes into the upload buffer Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9e591391d490c83ce301aa568a2e0afe4cc3c0a Author: Chris Wilson Date: Fri Feb 11 15:29:26 2011 + i965: Clean up brw_prepare_vertices() Use a temporary glarray variable to replace the numerous input->glarray. Signed-off-by: Chris Wilson URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3630d5b69afcecc3142d2c4897835175886f4bd8 Author: Chris Wilson Date: Fri Feb 11 19:40:08 2011 + intel: combine short memcpy using a temporary allocated buffer Using a temporary buffer for large discontiguous uploads in
Mesa (master): intel: Check for unsupported texture when finishing using as a render target
Module: Mesa Branch: master Commit: 8b9570e685f010745e2dfb1bff00d555e2e5f6ba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b9570e685f010745e2dfb1bff00d555e2e5f6ba Author: Chris Wilson Date: Tue Dec 21 11:55:11 2010 + intel: Check for unsupported texture when finishing using as a render target Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32541 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_fbo.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c b/src/mesa/drivers/dri/intel/intel_fbo.c index f6fe7b1..c3f528c 100644 --- a/src/mesa/drivers/dri/intel/intel_fbo.c +++ b/src/mesa/drivers/dri/intel/intel_fbo.c @@ -547,7 +547,8 @@ intel_finish_render_texture(struct gl_context * ctx, _glthread_GetID(), att->Texture->Name); /* Flag that this image may now be validated into the object's miptree. */ - intel_image->used_as_render_target = GL_FALSE; + if (intel_image) + intel_image->used_as_render_target = GL_FALSE; /* Since we've (probably) rendered to the texture and will (likely) use * it in the texture domain later on in this batchbuffer, flush the ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Check for a NULL src buffer prior to blt
Module: Mesa Branch: master Commit: 66708fd8a98cc28dab756b9e29d026194ccdfcee URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66708fd8a98cc28dab756b9e29d026194ccdfcee Author: Chris Wilson Date: Thu Aug 5 08:37:31 2010 +0100 intel: Check for a NULL src buffer prior to blt This can only happen along a malloc failure path, but check anyway. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_tex_copy.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c b/src/mesa/drivers/dri/intel/intel_tex_copy.c index 224b506..6efb2dd 100644 --- a/src/mesa/drivers/dri/intel/intel_tex_copy.c +++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c @@ -102,7 +102,7 @@ do_copy_texsubimage(struct intel_context *intel, GLcontext *ctx = &intel->ctx; const struct intel_region *src = get_teximage_source(intel, internalFormat); - if (!intelImage->mt || !src) { + if (!intelImage->mt || !src || !src->buffer) { if (INTEL_DEBUG & DEBUG_FALLBACKS) fprintf(stderr, "%s fail %p %p (0x%08x)\n", __FUNCTION__, intelImage->mt, src, internalFormat); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Check for region allocation failure.
Module: Mesa Branch: master Commit: 85cfe321805264686ef8989e45a911a999ed928a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=85cfe321805264686ef8989e45a911a999ed928a Author: Chris Wilson Date: Thu Aug 5 08:34:09 2010 +0100 intel: Check for region allocation failure. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_regions.c |6 ++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_regions.c b/src/mesa/drivers/dri/intel/intel_regions.c index fe4de18..680d18b 100644 --- a/src/mesa/drivers/dri/intel/intel_regions.c +++ b/src/mesa/drivers/dri/intel/intel_regions.c @@ -155,6 +155,9 @@ intel_region_alloc_internal(struct intel_context *intel, } region = calloc(sizeof(*region), 1); + if (region == NULL) + return region; + region->cpp = cpp; region->width = width; region->height = height; @@ -189,6 +192,9 @@ intel_region_alloc(struct intel_context *intel, region = intel_region_alloc_internal(intel, cpp, width, height, aligned_pitch / cpp, buffer); + if (region == NULL) + return region; + region->tiling = tiling; return region; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.8): i915: Fix off-by-one for drawing rectangle.
Module: Mesa Branch: 7.8 Commit: a48edfad8ab95c331d768ba30a16ea51faec05da URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a48edfad8ab95c331d768ba30a16ea51faec05da Author: Chris Wilson Date: Sat Jun 5 09:33:58 2010 +0100 i915: Fix off-by-one for drawing rectangle. The drawing rectangle is given in *inclusive* pixel values, so the range is only [0,2047]. Hence when rendering to a 2048 wide target, such as an extended desktop, we would issue an illegal instruction zeroing the draw area. Fixes: Bug 27408: Primary and Secondary display blanks in extended desktop mode with Compiz enabled https://bugs.freedesktop.org/show_bug.cgi?id=27408 Signed-off-by: Chris Wilson (cherry picked from commit add3260157368458501709d08a3f913ed448234f) Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i915/i915_vtbl.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 0a93e64..b7e38bd 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -627,8 +627,8 @@ i915_set_draw_region(struct intel_context *intel, state->Buffer[I915_DESTREG_DRAWRECT2] = 0; state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x; state->Buffer[I915_DESTREG_DRAWRECT4] = - ((ctx->DrawBuffer->Width + draw_x) & 0x) | - ((ctx->DrawBuffer->Height + draw_y) << 16); + ((ctx->DrawBuffer->Width + draw_x - 1) & 0x) | + ((ctx->DrawBuffer->Height + draw_y - 1) << 16); state->Buffer[I915_DESTREG_DRAWRECT5] = (draw_y << 16) | draw_x; I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Only emit a MI_FLUSH when the drawing rectangle offset changes.
Module: Mesa Branch: master Commit: 6d741627b00677d269537ad36e5f2ecd31fd98b5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d741627b00677d269537ad36e5f2ecd31fd98b5 Author: Chris Wilson Date: Sat Jun 5 10:04:59 2010 +0100 i915: Only emit a MI_FLUSH when the drawing rectangle offset changes. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_context.h |1 + src/mesa/drivers/dri/i915/i915_vtbl.c| 31 ++--- 2 files changed, 24 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_context.h b/src/mesa/drivers/dri/i915/i915_context.h index a7b9aae..c585849 100644 --- a/src/mesa/drivers/dri/i915/i915_context.h +++ b/src/mesa/drivers/dri/i915/i915_context.h @@ -261,6 +261,7 @@ struct i915_context struct i915_fragment_program *current_program; struct i915_hw_state state; + uint32_t last_draw_offset; }; diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index b2f9b90..29939c7 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -366,13 +366,16 @@ i915_emit_state(struct intel_context *intel) } if (dirty & I915_UPLOAD_BUFFERS) { - GLuint count = 15; + GLuint count; if (INTEL_DEBUG & DEBUG_STATE) fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); + count = 14; + if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP) + count++; if (state->depth_region) - count += 3; + count += 3; BEGIN_BATCH(count); OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); @@ -394,8 +397,8 @@ i915_emit_state(struct intel_context *intel) OUT_BATCH(state->Buffer[I915_DESTREG_SR1]); OUT_BATCH(state->Buffer[I915_DESTREG_SR2]); - assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); - OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); + if (state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP) + OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); @@ -532,7 +535,7 @@ i915_set_draw_region(struct intel_context *intel, struct intel_renderbuffer *irb = intel_renderbuffer(rb); GLuint value; struct i915_hw_state *state = &i915->state; - uint32_t draw_x, draw_y; + uint32_t draw_x, draw_y, draw_offset; if (state->draw_region != color_regions[0]) { intel_region_release(&state->draw_region); @@ -621,15 +624,26 @@ i915_set_draw_region(struct intel_context *intel, draw_y = 0; } + draw_offset = (draw_y << 16) | draw_x; + /* When changing drawing rectangle offset, an MI_FLUSH is first required. */ - state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE; + if (draw_offset != i915->last_draw_offset) { + FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET, + (ctx->DrawBuffer->Width + draw_x > 2048) || + (ctx->DrawBuffer->Height + draw_y > 2048)); + + state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE; + i915->last_draw_offset = draw_offset; + } else + state->Buffer[I915_DESTREG_DRAWRECT0] = MI_NOOP; + state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO; state->Buffer[I915_DESTREG_DRAWRECT2] = 0; - state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x; + state->Buffer[I915_DESTREG_DRAWRECT3] = draw_offset; state->Buffer[I915_DESTREG_DRAWRECT4] = ((ctx->DrawBuffer->Width + draw_x - 1) & 0x) | ((ctx->DrawBuffer->Height + draw_y - 1) << 16); - state->Buffer[I915_DESTREG_DRAWRECT5] = (draw_y << 16) | draw_x; + state->Buffer[I915_DESTREG_DRAWRECT5] = draw_offset; I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); } @@ -646,6 +660,7 @@ i915_new_batch(struct intel_context *intel) * difficulties associated with them (physical address requirements). */ i915->state.emitted = 0; + i915->last_draw_offset = 0; } static void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Fix off-by-one for drawing rectangle.
Module: Mesa Branch: master Commit: add3260157368458501709d08a3f913ed448234f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=add3260157368458501709d08a3f913ed448234f Author: Chris Wilson Date: Sat Jun 5 09:33:58 2010 +0100 i915: Fix off-by-one for drawing rectangle. The drawing rectangle is given in *inclusive* pixel values, so the range is only [0,2047]. Hence when rendering to a 2048 wide target, such as an extended desktop, we would issue an illegal instruction zeroing the draw area. Fixes: Bug 27408: Primary and Secondary display blanks in extended desktop mode with Compiz enabled https://bugs.freedesktop.org/show_bug.cgi?id=27408 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_vtbl.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 974ab3e..b2f9b90 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -627,8 +627,8 @@ i915_set_draw_region(struct intel_context *intel, state->Buffer[I915_DESTREG_DRAWRECT2] = 0; state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x; state->Buffer[I915_DESTREG_DRAWRECT4] = - ((ctx->DrawBuffer->Width + draw_x) & 0x) | - ((ctx->DrawBuffer->Height + draw_y) << 16); + ((ctx->DrawBuffer->Width + draw_x - 1) & 0x) | + ((ctx->DrawBuffer->Height + draw_y - 1) << 16); state->Buffer[I915_DESTREG_DRAWRECT5] = (draw_y << 16) | draw_x; I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Inhibit render cache flush when changing drawing rectangle offset.
Module: Mesa Branch: master Commit: ff74c2ced5e7234902d43712a3759f91fd534a91 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff74c2ced5e7234902d43712a3759f91fd534a91 Author: Chris Wilson Date: Sat Jun 5 09:32:28 2010 +0100 i915: Inhibit render cache flush when changing drawing rectangle offset. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/i915_vtbl.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c b/src/mesa/drivers/dri/i915/i915_vtbl.c index 0a93e64..974ab3e 100644 --- a/src/mesa/drivers/dri/i915/i915_vtbl.c +++ b/src/mesa/drivers/dri/i915/i915_vtbl.c @@ -622,7 +622,7 @@ i915_set_draw_region(struct intel_context *intel, } /* When changing drawing rectangle offset, an MI_FLUSH is first required. */ - state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH; + state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE; state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO; state->Buffer[I915_DESTREG_DRAWRECT2] = 0; state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Initialize batch->reserved_space on allocation
Module: Mesa Branch: master Commit: 8accf0a891c85c7d747c5f7f4a4d8a99adb91b2a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8accf0a891c85c7d747c5f7f4a4d8a99adb91b2a Author: Chris Wilson Date: Mon May 31 09:58:25 2010 +0100 intel: Initialize batch->reserved_space on allocation Fixes the assert (and buffer overrun): glknots: intel_batchbuffer.c:164: _intel_batchbuffer_flush: Assertion 'used >= batch->buf->size' failed. Reported in bug: Bug 28274 - xscreensaver's glknots hangs GPU (945GME/Pineview) https://bugs.freedesktop.org/show_bug.cgi?id=28274 Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_batchbuffer.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 446ce29..27bd4fe 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -55,6 +55,7 @@ intel_batchbuffer_reset(struct intel_batchbuffer *batch) } batch->size = intel->maxBatchSize; batch->ptr = batch->map; + batch->reserved_space = BATCH_RESERVED; batch->dirty_state = ~0; } @@ -180,8 +181,6 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, /* Check that we didn't just wrap our batchbuffer at a bad time. */ assert(!intel->no_batch_wrap); - batch->reserved_space = BATCH_RESERVED; - /* TODO: Just pass the relocation list and dma buffer up to the * kernel. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Always return VOLATILE for ObjectPurgeable(VOLATILE)
Module: Mesa Branch: master Commit: 24f90112761d108a4a131fad11bd7b426d8edfa0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24f90112761d108a4a131fad11bd7b426d8edfa0 Author: Chris Wilson Date: Fri Mar 5 23:10:45 2010 + Always return VOLATILE for ObjectPurgeable(VOLATILE) Fixes fdo bug 26128. The spec mandates that VOLATILE is returned from ObjectPurgeable(VOLATILE) irrespective of the actual status of the object upon completion of marking it purgeable. Conform to the spec, even though it seems wrong. Signed-off-by: Chris Wilson --- src/mesa/main/bufferobj.c | 20 1 files changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c index c532cbe..71d1514 100644 --- a/src/mesa/main/bufferobj.c +++ b/src/mesa/main/bufferobj.c @@ -1809,6 +1809,8 @@ _mesa_TextureObjectPurgeable(GLcontext *ctx, GLuint name, GLenum option) GLenum GLAPIENTRY _mesa_ObjectPurgeableAPPLE(GLenum objectType, GLuint name, GLenum option) { + GLenum retval; + GET_CURRENT_CONTEXT(ctx); ASSERT_OUTSIDE_BEGIN_END_WITH_RETVAL(ctx, 0); @@ -1832,17 +1834,27 @@ _mesa_ObjectPurgeableAPPLE(GLenum objectType, GLuint name, GLenum option) switch (objectType) { case GL_TEXTURE: - return _mesa_TextureObjectPurgeable (ctx, name, option); + retval = _mesa_TextureObjectPurgeable (ctx, name, option); + break; case GL_RENDERBUFFER_EXT: - return _mesa_RenderObjectPurgeable (ctx, name, option); + retval = _mesa_RenderObjectPurgeable (ctx, name, option); + break; case GL_BUFFER_OBJECT_APPLE: - return _mesa_BufferObjectPurgeable (ctx, name, option); + retval = _mesa_BufferObjectPurgeable (ctx, name, option); + break; default: _mesa_error(ctx, GL_INVALID_ENUM, "glObjectPurgeable(name = 0x%x) invalid type: %d", name, objectType); return 0; } + + /* In strict conformance to the spec, we must only return VOLATILE when +* when passed the VOLATILE option. Madness. +* +* XXX First fix the spec, then fix me. +*/ + return option == GL_VOLATILE_APPLE ? GL_VOLATILE_APPLE : retval; } @@ -1902,7 +1914,7 @@ _mesa_RenderObjectUnpurgeable(GLcontext *ctx, GLuint name, GLenum option) if (ctx->Driver.RenderObjectUnpurgeable) retval = ctx->Driver.RenderObjectUnpurgeable(ctx, bufObj, option); - return retval; + return option; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): APPLE_object_purgeable: intel
Module: Mesa Branch: master Commit: 755915fa5d9ea782d142b3f8755b62d6de28fe29 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=755915fa5d9ea782d142b3f8755b62d6de28fe29 Author: Chris Wilson Date: Wed Jan 13 18:35:25 2010 + APPLE_object_purgeable: intel Implement support for purgeable objects by using the GEM madvise ioctl. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_buffer_objects.c | 134 - src/mesa/drivers/dri/intel/intel_extensions.c |3 + 2 files changed, 136 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c b/src/mesa/drivers/dri/intel/intel_buffer_objects.c index 312866d..7599bea 100644 --- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c +++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c @@ -31,10 +31,12 @@ #include "main/macros.h" #include "main/bufferobj.h" -#include "intel_context.h" #include "intel_blit.h" #include "intel_buffer_objects.h" #include "intel_batchbuffer.h" +#include "intel_context.h" +#include "intel_fbo.h" +#include "intel_mipmap_tree.h" #include "intel_regions.h" static GLboolean @@ -588,6 +590,126 @@ intel_bufferobj_copy_subdata(GLcontext *ctx, intel_batchbuffer_emit_mi_flush(intel->batch); } +#if FEATURE_APPLE_object_purgeable +static GLenum +intel_buffer_purgeable(GLcontext * ctx, + drm_intel_bo *buffer, + GLenum option) +{ + int retained = 0; + + if (buffer != NULL) + retained = drm_intel_bo_madvise (buffer, I915_MADV_DONTNEED); + + return retained ? GL_VOLATILE_APPLE : GL_RELEASED_APPLE; +} + +static GLenum +intel_buffer_object_purgeable(GLcontext * ctx, + struct gl_buffer_object *obj, + GLenum option) +{ + struct intel_buffer_object *intel; + + intel = intel_buffer_object (obj); + if (intel->buffer != NULL) + return intel_buffer_purgeable (ctx, intel->buffer, option); + + if (option == GL_RELEASED_APPLE) { + if (intel->sys_buffer != NULL) { + free(intel->sys_buffer); + intel->sys_buffer = NULL; + } + + return GL_RELEASED_APPLE; + } else { + /* XXX Create the buffer and madvise(MADV_DONTNEED)? */ + return intel_buffer_purgeable (ctx, + intel_bufferobj_buffer(intel_context(ctx), +intel, INTEL_READ), + option); + } +} + +static GLenum +intel_texture_object_purgeable(GLcontext * ctx, + struct gl_texture_object *obj, + GLenum option) +{ + struct intel_texture_object *intel; + + intel = intel_texture_object(obj); + if (intel->mt == NULL || intel->mt->region == NULL) + return GL_RELEASED_APPLE; + + return intel_buffer_purgeable (ctx, intel->mt->region->buffer, option); +} + +static GLenum +intel_render_object_purgeable(GLcontext * ctx, + struct gl_renderbuffer *obj, + GLenum option) +{ + struct intel_renderbuffer *intel; + + intel = intel_renderbuffer(obj); + if (intel->region == NULL) + return GL_RELEASED_APPLE; + + return intel_buffer_purgeable (ctx, intel->region->buffer, option); +} + +static GLenum +intel_buffer_unpurgeable(GLcontext * ctx, + drm_intel_bo *buffer, + GLenum option) +{ + int retained; + + retained = 0; + if (buffer != NULL) + retained = drm_intel_bo_madvise (buffer, I915_MADV_WILLNEED); + + return retained ? GL_RETAINED_APPLE : GL_UNDEFINED_APPLE; +} + +static GLenum +intel_buffer_object_unpurgeable(GLcontext * ctx, +struct gl_buffer_object *obj, +GLenum option) +{ + return intel_buffer_unpurgeable (ctx, intel_buffer_object (obj)->buffer, option); +} + +static GLenum +intel_texture_object_unpurgeable(GLcontext * ctx, + struct gl_texture_object *obj, + GLenum option) +{ + struct intel_texture_object *intel; + + intel = intel_texture_object(obj); + if (intel->mt == NULL || intel->mt->region == NULL) + return GL_UNDEFINED_APPLE; + + return intel_buffer_unpurgeable (ctx, intel->mt->region->buffer, option); +} + +static GLenum +intel_render_object_unpurgeable(GLcontext * ctx, +struct gl_renderbuffer *obj, +GLenum option) +{ + struct intel_renderbuffer *intel; + + intel = intel_renderbuffer(obj); + if (intel->region == NULL) + return GL_UNDEFINED_APPLE; + + return intel_buffer_unpurgeable (ctx, intel->region->buffer, option); +} +#endif
Mesa (master): Merge branch 'object-purgeable'
Module: Mesa Branch: master Commit: 6ba31fb2dbe6a90e6d60a49b3e5bd2edce05241d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ba31fb2dbe6a90e6d60a49b3e5bd2edce05241d Author: Chris Wilson Date: Fri Mar 5 15:03:51 2010 + Merge branch 'object-purgeable' Acked-by: Brian Paul --- ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): APPLE_object_purgeable: core
Module: Mesa Branch: master Commit: 99864d595f7d4c13e9548f83d5972db9af64e67b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99864d595f7d4c13e9548f83d5972db9af64e67b Author: Chris Wilson Date: Fri Nov 13 12:19:35 2009 + APPLE_object_purgeable: core Signed-off-by: Chris Wilson --- src/mesa/main/api_exec.c |6 + src/mesa/main/bufferobj.c | 356 src/mesa/main/bufferobj.h | 11 ++ src/mesa/main/dd.h | 17 ++ src/mesa/main/dlist.c |6 + src/mesa/main/extensions.c |4 + src/mesa/main/mfeatures.h |1 + src/mesa/main/mtypes.h |4 + 8 files changed, 405 insertions(+), 0 deletions(-) diff --git a/src/mesa/main/api_exec.c b/src/mesa/main/api_exec.c index 70c154b..fa8d409 100644 --- a/src/mesa/main/api_exec.c +++ b/src/mesa/main/api_exec.c @@ -758,4 +758,10 @@ _mesa_init_exec_table(struct _glapi_table *exec) SET_EGLImageTargetTexture2DOES(exec, _mesa_EGLImageTargetTexture2DOES); SET_EGLImageTargetRenderbufferStorageOES(exec, _mesa_EGLImageTargetRenderbufferStorageOES); #endif + +#if FEATURE_APPLE_object_purgeable + SET_ObjectPurgeableAPPLE(exec, _mesa_ObjectPurgeableAPPLE); + SET_ObjectUnpurgeableAPPLE(exec, _mesa_ObjectUnpurgeableAPPLE); + SET_GetObjectParameterivAPPLE(exec, _mesa_GetObjectParameterivAPPLE); +#endif } diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c index 971b280..3c48f6c 100644 --- a/src/mesa/main/bufferobj.c +++ b/src/mesa/main/bufferobj.c @@ -37,6 +37,8 @@ #include "image.h" #include "context.h" #include "bufferobj.h" +#include "fbobject.h" +#include "texobj.h" /* Debug flags */ @@ -1710,3 +1712,357 @@ _mesa_FlushMappedBufferRange(GLenum target, GLintptr offset, GLsizeiptr length) if (ctx->Driver.FlushMappedBufferRange) ctx->Driver.FlushMappedBufferRange(ctx, target, offset, length, bufObj); } + +#if FEATURE_APPLE_object_purgeable +static GLenum +_mesa_BufferObjectPurgeable(GLcontext *ctx, GLuint name, GLenum option) +{ + struct gl_buffer_object *bufObj; + GLenum retval; + + bufObj = _mesa_lookup_bufferobj(ctx, name); + if (!bufObj) { + _mesa_error(ctx, GL_INVALID_VALUE, + "glObjectPurgeable(name = 0x%x)", name); + return 0; + } + if (!_mesa_is_bufferobj(bufObj)) { + _mesa_error(ctx, GL_INVALID_OPERATION, "glObjectPurgeable(buffer 0)" ); + return 0; + } + + if (bufObj->Purgeable) { + _mesa_error(ctx, GL_INVALID_OPERATION, + "glObjectPurgeable(name = 0x%x) is already purgeable", name); + return GL_VOLATILE_APPLE; + } + + bufObj->Purgeable = GL_TRUE; + + retval = GL_VOLATILE_APPLE; + if (ctx->Driver.BufferObjectPurgeable) + retval = ctx->Driver.BufferObjectPurgeable(ctx, bufObj, option); + + return retval; +} + +static GLenum +_mesa_RenderObjectPurgeable(GLcontext *ctx, GLuint name, GLenum option) +{ + struct gl_renderbuffer *bufObj; + GLenum retval; + + bufObj = _mesa_lookup_renderbuffer(ctx, name); + if (!bufObj) { + _mesa_error(ctx, GL_INVALID_VALUE, + "glObjectUnpurgeable(name = 0x%x)", name); + return 0; + } + + if (bufObj->Purgeable) { + _mesa_error(ctx, GL_INVALID_OPERATION, + "glObjectPurgeable(name = 0x%x) is already purgeable", name); + return GL_VOLATILE_APPLE; + } + + bufObj->Purgeable = GL_TRUE; + + retval = GL_VOLATILE_APPLE; + if (ctx->Driver.RenderObjectPurgeable) + retval = ctx->Driver.RenderObjectPurgeable(ctx, bufObj, option); + + return retval; +} + +static GLenum +_mesa_TextureObjectPurgeable(GLcontext *ctx, GLuint name, GLenum option) +{ + struct gl_texture_object *bufObj; + GLenum retval; + + bufObj = _mesa_lookup_texture(ctx, name); + if (!bufObj) { + _mesa_error(ctx, GL_INVALID_VALUE, + "glObjectPurgeable(name = 0x%x)", name); + return 0; + } + + if (bufObj->Purgeable) { + _mesa_error(ctx, GL_INVALID_OPERATION, + "glObjectPurgeable(name = 0x%x) is already purgeable", name); + return GL_VOLATILE_APPLE; + } + + bufObj->Purgeable = GL_TRUE; + + retval = GL_VOLATILE_APPLE; + if (ctx->Driver.TextureObjectPurgeable) + retval = ctx->Driver.TextureObjectPurgeable(ctx, bufObj, option); + + return retval; +} + +GLenum GLAPIENTRY +_mesa_ObjectPurgeableAPPLE(GLenum objectType, GLuint name, GLenum option) +{ + GET_CURRENT_CONTEXT(ctx); + ASSERT_OUTSIDE_BEGIN_END_WITH_RETVAL(ctx, 0); + + if (name == 0) { + _mesa_error(ctx, GL_INVALID_VALUE, + "glObjectPurgeable(name = 0x%x)", name); + return 0; + } + + switch (option) { + case GL_VOLATILE_APPLE: + case GL_RELEASED_APPLE: + break; + + default: + _mesa_error(ctx, GL_INVALID_ENUM, +
Mesa (master): APPLE_object_purgeable: autogenerated files
Module: Mesa Branch: master Commit: 894d0ab9388543642b6940f09358844736a8bd3a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=894d0ab9388543642b6940f09358844736a8bd3a Author: Chris Wilson Date: Thu Nov 12 10:15:49 2009 + APPLE_object_purgeable: autogenerated files --- src/mesa/glapi/glapidispatch.h | 37 +- src/mesa/glapi/glapioffsets.h | 22 +- src/mesa/glapi/glapitable.h| 17 +- src/mesa/glapi/glapitemp.h | 44 +- src/mesa/glapi/glprocs.h | 640 +++--- src/mesa/main/enums.c | 6108 src/mesa/main/remap_helper.h | 3040 ++-- src/mesa/sparc/glapi_sparc.S | 19 +- src/mesa/x86-64/glapi_x86-64.S | 195 +- src/mesa/x86/glapi_x86.S | 23 +- 10 files changed, 5182 insertions(+), 4963 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=894d0ab9388543642b6940f09358844736a8bd3a ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): APPLE_object_purgeable: xml
Module: Mesa Branch: master Commit: e5c49e49cce6c14bc9e973dea4d69e0b7d36086d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5c49e49cce6c14bc9e973dea4d69e0b7d36086d Author: Chris Wilson Date: Thu Nov 12 10:12:56 2009 + APPLE_object_purgeable: xml Signed-off-by: Chris Wilson --- src/mesa/glapi/gen/APPLE_object_purgeable.xml | 37 + src/mesa/glapi/gen/Makefile |1 + src/mesa/glapi/gen/gl_API.xml |1 + 3 files changed, 39 insertions(+), 0 deletions(-) diff --git a/src/mesa/glapi/gen/APPLE_object_purgeable.xml b/src/mesa/glapi/gen/APPLE_object_purgeable.xml new file mode 100644 index 000..62fa64a --- /dev/null +++ b/src/mesa/glapi/gen/APPLE_object_purgeable.xml @@ -0,0 +1,37 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/mesa/glapi/gen/Makefile b/src/mesa/glapi/gen/Makefile index 8e9c909..8aa74ce 100644 --- a/src/mesa/glapi/gen/Makefile +++ b/src/mesa/glapi/gen/Makefile @@ -79,6 +79,7 @@ API_XML = \ ARB_seamless_cube_map.xml \ ARB_sync.xml \ ARB_vertex_array_object.xml \ + APPLE_object_purgeable.xml \ APPLE_vertex_array_object.xml \ EXT_draw_buffers2.xml \ EXT_framebuffer_object.xml \ diff --git a/src/mesa/glapi/gen/gl_API.xml b/src/mesa/glapi/gen/gl_API.xml index 0b3d57b..4a4d0d5 100644 --- a/src/mesa/glapi/gen/gl_API.xml +++ b/src/mesa/glapi/gen/gl_API.xml @@ -11978,6 +11978,7 @@ +http://www.w3.org/2001/XInclude"/> http://www.w3.org/2001/XInclude"/> ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Check that we have a bufmgr or bail out when initializing the context.
Module: Mesa Branch: master Commit: 5abee283d310a70efa4c713707f06624d5462322 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5abee283d310a70efa4c713707f06624d5462322 Author: Chris Wilson Date: Thu Jan 21 17:39:01 2010 + intel: Check that we have a bufmgr or bail out when initializing the context. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_context.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index ced8d5a..3c36c3f 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -594,6 +594,10 @@ intelInitContext(struct intel_context *intel, struct intel_screen *intelScreen = sPriv->private; int bo_reuse_mode; + /* we can't do anything without a connection to the device */ + if (intelScreen->bufmgr == NULL) + return GL_FALSE; + if (!_mesa_initialize_context(&intel->ctx, mesaVis, shareCtx, functions, (void *) intel)) { printf("%s: failed to init mesa context\n", __FUNCTION__); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Fix logic !gen >= 3
Module: Mesa Branch: master Commit: 415b7c7775dd7240abd2c929ea3335304a790d39 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=415b7c7775dd7240abd2c929ea3335304a790d39 Author: Chris Wilson Date: Mon Feb 22 09:51:33 2010 + i915: Fix logic !gen >= 3 The effect of this was that all objects were aligned to 128 bytes on all generations, rather than just gen2. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/intel_tris.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 9975e2f..0afbda2 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -217,7 +217,7 @@ void intel_flush_prim(struct intel_context *intel) intel->prim.count = 0; offset = intel->prim.start_offset; intel->prim.start_offset = intel->prim.current_offset; - if (!intel->gen >= 3) + if (intel->gen < 3) intel->prim.start_offset = ALIGN(intel->prim.start_offset, 128); intel->prim.flush = NULL; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: assert that we do not overflow the batch buffer.
Module: Mesa Branch: master Commit: 15904c057beec3029a8ed2035d7ba50f9414943d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15904c057beec3029a8ed2035d7ba50f9414943d Author: Chris Wilson Date: Mon Feb 22 09:53:36 2010 + intel: assert that we do not overflow the batch buffer. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_batchbuffer.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.c b/src/mesa/drivers/dri/intel/intel_batchbuffer.c index 9261f2f..4c99dcd 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.c @@ -158,9 +158,10 @@ _intel_batchbuffer_flush(struct intel_batchbuffer *batch, const char *file, } /* Mark the end of the buffer. */ - *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; /* noop */ + *(GLuint *) (batch->ptr) = MI_BATCH_BUFFER_END; batch->ptr += 4; used = batch->ptr - batch->map; + assert (used <= batch->buf->size); /* Workaround for recursive batchbuffer flushing: If the window is * moved, we can get into a case where we try to flush during a ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: Remove superfluous MI_NOOP from vertex emission
Module: Mesa Branch: master Commit: ac6ce53af7f67d01afd8e33d297f95c21aa3405e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac6ce53af7f67d01afd8e33d297f95c21aa3405e Author: Chris Wilson Date: Mon Feb 22 09:50:15 2010 + i915: Remove superfluous MI_NOOP from vertex emission Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/i915/intel_tris.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i915/intel_tris.c b/src/mesa/drivers/dri/i915/intel_tris.c index 3816ada..9975e2f 100644 --- a/src/mesa/drivers/dri/i915/intel_tris.c +++ b/src/mesa/drivers/dri/i915/intel_tris.c @@ -98,8 +98,7 @@ static void intel_start_inline(struct intel_context *intel, uint32_t prim) /* Emit a slot which will be filled with the inline primitive * command later. */ - BEGIN_BATCH(2); - OUT_BATCH(0); + BEGIN_BATCH(1); assert((intel->batch->dirty_state & (1<<1)) == 0); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Re: Mesa (master): intel: Disallow relocations to the byte beyond the end of the buffer
Excerpts from Eric Anholt's message of Mon Oct 19 16:20:50 +0100 2009: > On Sat, 2009-10-17 at 00:28 -0700, Chris Wilson wrote: > > intel: Disallow relocations to the byte beyond the end of the buffer > > What did you find that needed this? There have been a couple of people who have reported a KERN_ERR with the delta pointing to the tail byte, the latest on Saturday: 08:57 < spstarr> [ 148.557731] [drm:i915_gem_object_pin_and_relocate] ERROR Relocation beyond target object bounds: obj 8800b950fc00 target 2381 delta 131072 size 131072. An hour later, spstarr reported having rebuilt mesa, but never did paste the offending backtrace. So I'm still none the wiser. :( -ickle -- Chris Wilson, Intel Open Source Technology Centre ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Disallow relocations to the byte beyond the end of the buffer
Module: Mesa Branch: master Commit: 60a39b6799c72430851d92f93758e2f25487a0f4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=60a39b6799c72430851d92f93758e2f25487a0f4 Author: Chris Wilson Date: Sat Oct 17 08:25:48 2009 +0100 intel: Disallow relocations to the byte beyond the end of the buffer --- src/mesa/drivers/dri/intel/intel_batchbuffer.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index 9a619fb..d4899aa 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -157,7 +157,7 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d) #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ - assert((unsigned) (delta) <= buf->size);\ + assert((unsigned) (delta) < buf->size); \ intel_batchbuffer_emit_reloc(intel->batch, buf, \ read_domains, write_domain, delta); \ } while (0) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Suppress a compiler warning for an pointer->int cast
Module: Mesa Branch: master Commit: f194d2737b059cf6b99caa18f8ec2d46a55ada88 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f194d2737b059cf6b99caa18f8ec2d46a55ada88 Author: Chris Wilson Date: Sat Oct 3 23:08:39 2009 +0100 intel: Suppress a compiler warning for an pointer->int cast intel_pixel_read.c: In function ‘do_blit_readpixels’: intel_pixel_read.c:221: warning: cast from pointer to integer of different size Cast via an intermediate (GLintptr) instead and hope the result fits within GLuint... [It should as we simply do not support textures *that* large!] Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_pixel_read.c |5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_pixel_read.c b/src/mesa/drivers/dri/intel/intel_pixel_read.c index bc67f62..44a8695 100644 --- a/src/mesa/drivers/dri/intel/intel_pixel_read.c +++ b/src/mesa/drivers/dri/intel/intel_pixel_read.c @@ -216,9 +216,8 @@ do_blit_readpixels(GLcontext * ctx, rowLength = -rowLength; } - /* XXX 64-bit cast? */ - dst_offset = (GLuint) _mesa_image_address(2, pack, pixels, width, height, - format, type, 0, 0, 0); + dst_offset = (GLintptr) _mesa_image_address(2, pack, pixels, width, height, + format, type, 0, 0, 0); /* Although the blits go on the command buffer, need to do this and ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Assert that relocation offsets are within the target
Module: Mesa Branch: master Commit: 470ec8d42e1941c0ad773084693323f96a83e64d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=470ec8d42e1941c0ad773084693323f96a83e64d Author: Chris Wilson Date: Fri Oct 2 19:46:03 2009 +0100 intel: Assert that relocation offsets are within the target This should catch the common programming error where we attempt to emit a relocation to beyond the end of the target buffer. Signed-off-by: Chris Wilson --- src/mesa/drivers/dri/intel/intel_batchbuffer.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_batchbuffer.h b/src/mesa/drivers/dri/intel/intel_batchbuffer.h index 51579df..9a619fb 100644 --- a/src/mesa/drivers/dri/intel/intel_batchbuffer.h +++ b/src/mesa/drivers/dri/intel/intel_batchbuffer.h @@ -157,7 +157,7 @@ intel_batchbuffer_require_space(struct intel_batchbuffer *batch, #define OUT_BATCH(d) intel_batchbuffer_emit_dword(intel->batch, d) #define OUT_RELOC(buf, read_domains, write_domain, delta) do { \ - assert((delta) >= 0); \ + assert((unsigned) (delta) <= buf->size);\ intel_batchbuffer_emit_reloc(intel->batch, buf, \ read_domains, write_domain, delta); \ } while (0) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit