Mesa (master): virgl: use bits in caps set v2

[Dave Airlie]

Module: Mesa
Branch: master
Commit: a7b74a77fa63efe6d6462ff4f201bea03fa23a33
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7b74a77fa63efe6d6462ff4f201bea03fa23a33

Author: gurchetansi...@chromium.org 
Date:   Mon Jun  4 10:25:20 2018 -0700

virgl: use bits in caps set v2

Let's add another field to caps v2, that can help report boolean
values.

Suggested-by: Gert Wollny 
Suggested-by: Dave Airlie 
Reviewed-by: Dave Airlie 

---

 src/gallium/drivers/virgl/virgl_hw.h | 5 +
 src/gallium/drivers/virgl/virgl_winsys.h | 1 +
 2 files changed, 6 insertions(+)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index a2c70bf86b..ee58520f9b 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -197,6 +197,10 @@ enum virgl_formats {
VIRGL_FORMAT_MAX,
 };
 
+/* These are used by the capability_bits field in virgl_caps_v2. */
+#define VIRGL_CAP_NONE 0
+#define VIRGL_CAP_TGSI_INVARIANT   (1 << 0)
+
 #define VIRGL_BIND_DEPTH_STENCIL (1 << 0)
 #define VIRGL_BIND_RENDER_TARGET (1 << 1)
 #define VIRGL_BIND_SAMPLER_VIEW  (1 << 3)
@@ -293,6 +297,7 @@ struct virgl_caps_v2 {
 uint32_t texture_buffer_offset_alignment;
 uint32_t uniform_buffer_offset_alignment;
 uint32_t shader_buffer_offset_alignment;
+uint32_t capability_bits;
 };
 
 union virgl_caps {
diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index 83cb93138a..9ebb31a1e4 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -135,5 +135,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct 
virgl_drm_caps *caps)
caps->caps.v2.texture_buffer_offset_alignment = 0;
caps->caps.v2.uniform_buffer_offset_alignment = 256;
caps->caps.v2.shader_buffer_offset_alignment = 32;
+   caps->caps.v2.capability_bits = 0;
 }
 #endif

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Mesa (master): virgl: add shader offset alignment to to v2 caps struct

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6ce94a50bbe2bfc0f5dfb58d39f5ddfece7a3320
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ce94a50bbe2bfc0f5dfb58d39f5ddfece7a3320

Author: gurchetansi...@chromium.org 
Date:   Mon Jun  4 09:03:37 2018 -0700

virgl: add shader offset alignment to to v2 caps struct

This is the SSBO analogue to fe0647. User supplied data must
be a multiple of GL_SHADER_STORAGE_BUFFER_OFFSET_ALIGNMENT.

This fixes 44 GLES31 tests on airlied@'s GLES31 sketch branches with
Nvidia hardware, but this patch standalone can applied to master. The
alignment restriction on Nvidia is 32, hence the default value.

Example tests:
   dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.0
   dEQP-GLES31.functional.ssbo.layout.multi_basic_types.single_buffer.std430

v2: Move to a better place in case statement
v3: Rebase

Reviewed-by: Dave Airlie 

---

 src/gallium/drivers/virgl/virgl_hw.h | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 3 ++-
 src/gallium/drivers/virgl/virgl_winsys.h | 1 +
 3 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index 261b690f53..a2c70bf86b 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -292,6 +292,7 @@ struct virgl_caps_v2 {
 int32_t max_texture_gather_offset;
 uint32_t texture_buffer_offset_alignment;
 uint32_t uniform_buffer_offset_alignment;
+uint32_t shader_buffer_offset_alignment;
 };
 
 union virgl_caps {
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index b5f5d9921a..e8d1c75177 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -211,6 +211,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
   return vscreen->caps.caps.v1.bset.polygon_offset_clamp;
case PIPE_CAP_QUERY_SO_OVERFLOW:
   return vscreen->caps.caps.v1.bset.transform_feedback_overflow_query;
+   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
+  return vscreen->caps.caps.v2.shader_buffer_offset_alignment;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
@@ -236,7 +238,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
-   case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index 690e610e19..83cb93138a 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -134,5 +134,6 @@ static inline void virgl_ws_fill_new_caps_defaults(struct 
virgl_drm_caps *caps)
caps->caps.v2.max_texture_gather_offset = 7;
caps->caps.v2.texture_buffer_offset_alignment = 0;
caps->caps.v2.uniform_buffer_offset_alignment = 256;
+   caps->caps.v2.shader_buffer_offset_alignment = 32;
 }
 #endif

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Mesa (master): nir: use num_components wrappers in print/validate.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 67eccd6aa2b3fcc79a232479a58a0f52b9980001
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67eccd6aa2b3fcc79a232479a58a0f52b9980001

Author: Dave Airlie 
Date:   Tue May 15 11:11:12 2018 +1000

nir: use num_components wrappers in print/validate.

These wrappers were introduces, so start using them.

Reviewed-by: Jason Ekstrand 

---

 src/compiler/nir/nir_print.c|  4 +---
 src/compiler/nir/nir_validate.c | 16 
 2 files changed, 5 insertions(+), 15 deletions(-)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index fad274e62f..7c3e93eb82 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -199,9 +199,7 @@ print_alu_src(nir_alu_instr *instr, unsigned src, 
print_state *state)
   }
}
 
-   unsigned live_channels = instr->src[src].src.is_ssa
-  ? instr->src[src].src.ssa->num_components
-  : instr->src[src].src.reg.reg->num_components;
+   unsigned live_channels = nir_src_num_components(instr->src[src].src);
 
if (print_swizzle || used_channels != live_channels) {
   fprintf(fp, ".");
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index eee737e806..abfd1712b3 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -228,15 +228,9 @@ validate_alu_src(nir_alu_instr *instr, unsigned index, 
validate_state *state)
 {
nir_alu_src *src = >src[index];
 
-   unsigned num_components;
-   if (src->src.is_ssa) {
-  num_components = src->src.ssa->num_components;
-   } else {
-  if (src->src.reg.reg->is_packed)
- num_components = 4; /* can't check anything */
-  else
- num_components = src->src.reg.reg->num_components;
-   }
+   unsigned num_components = nir_src_num_components(src->src);
+   if (!src->src.is_ssa && src->src.reg.reg->is_packed)
+  num_components = 4; /* can't check anything */
for (unsigned i = 0; i < 4; i++) {
   validate_assert(state, src->swizzle[i] < 4);
 
@@ -333,9 +327,7 @@ validate_alu_dest(nir_alu_instr *instr, validate_state 
*state)
 {
nir_alu_dest *dest = >dest;
 
-   unsigned dest_size =
-  dest->dest.is_ssa ? dest->dest.ssa.num_components
-: dest->dest.reg.reg->num_components;
+   unsigned dest_size = nir_dest_num_components(dest->dest);
bool is_packed = !dest->dest.is_ssa && dest->dest.reg.reg->is_packed;
/*
 * validate that the instruction doesn't write to components not in the

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Mesa (master): drisw: learn to query shmid handle type

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9feaf333716f08111ac8a921940e3a0e3666df0e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9feaf333716f08111ac8a921940e3a0e3666df0e

Author: Marc-André Lureau 
Date:   Mon Jun 15 14:48:27 2015 +0200

drisw: learn to query shmid handle type

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/gallium/include/state_tracker/drisw_api.h |  1 +
 src/gallium/include/state_tracker/sw_winsys.h |  3 +--
 src/gallium/include/state_tracker/winsys_handle.h |  1 +
 src/gallium/winsys/sw/dri/dri_sw_winsys.c | 10 +-
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/gallium/include/state_tracker/drisw_api.h 
b/src/gallium/include/state_tracker/drisw_api.h
index 36bef087a4..e365ab81f1 100644
--- a/src/gallium/include/state_tracker/drisw_api.h
+++ b/src/gallium/include/state_tracker/drisw_api.h
@@ -2,6 +2,7 @@
 #define _DRISW_API_H_
 
 #include "pipe/p_compiler.h"
+#include "sw_winsys.h"
 
 struct pipe_screen;
 struct dri_drawable;
diff --git a/src/gallium/include/state_tracker/sw_winsys.h 
b/src/gallium/include/state_tracker/sw_winsys.h
index 0b792cd0ce..cd5838ad1d 100644
--- a/src/gallium/include/state_tracker/sw_winsys.h
+++ b/src/gallium/include/state_tracker/sw_winsys.h
@@ -37,14 +37,13 @@
 
 #include "pipe/p_compiler.h" /* for boolean */
 #include "pipe/p_format.h"
-
+#include "state_tracker/winsys_handle.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 
-struct winsys_handle;
 struct pipe_screen;
 struct pipe_context;
 struct pipe_resource;
diff --git a/src/gallium/include/state_tracker/winsys_handle.h 
b/src/gallium/include/state_tracker/winsys_handle.h
index 746e87683a..167c1a937f 100644
--- a/src/gallium/include/state_tracker/winsys_handle.h
+++ b/src/gallium/include/state_tracker/winsys_handle.h
@@ -9,6 +9,7 @@ extern "C" {
 #define WINSYS_HANDLE_TYPE_SHARED 0
 #define WINSYS_HANDLE_TYPE_KMS1
 #define WINSYS_HANDLE_TYPE_FD 2
+#define WINSYS_HANDLE_TYPE_SHMID   3
 
 /**
  * For use with pipe_screen::{texture_from_handle|texture_get_handle}.
diff --git a/src/gallium/winsys/sw/dri/dri_sw_winsys.c 
b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
index b36a53e960..8335e52200 100644
--- a/src/gallium/winsys/sw/dri/dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
@@ -209,7 +209,15 @@ dri_sw_displaytarget_get_handle(struct sw_winsys *winsys,
 struct sw_displaytarget *dt,
 struct winsys_handle *whandle)
 {
-   assert(0);
+   struct dri_sw_displaytarget *dri_sw_dt = dri_sw_displaytarget(dt);
+
+   if (whandle->type == WINSYS_HANDLE_TYPE_SHMID) {
+  if (dri_sw_dt->shmid < 0)
+ return FALSE;
+  whandle->handle = dri_sw_dt->shmid;
+  return TRUE;
+   }
+
return FALSE;
 }
 

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Mesa (master): drisw: use getImageShm() if available

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 17b27725fe5dd61ed461a45fb320464b45f045d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17b27725fe5dd61ed461a45fb320464b45f045d8

Author: Marc-André Lureau 
Date:   Mon Jun 15 15:09:58 2015 +0200

drisw: use getImageShm() if available

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/gallium/state_trackers/dri/drisw.c | 23 ++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/dri/drisw.c 
b/src/gallium/state_trackers/dri/drisw.c
index 40cbca5494..e24fcba386 100644
--- a/src/gallium/state_trackers/dri/drisw.c
+++ b/src/gallium/state_trackers/dri/drisw.c
@@ -117,6 +117,26 @@ get_image2(__DRIdrawable *dPriv, int x, int y, int width, 
int height, int stride
  data, dPriv->loaderPrivate);
 }
 
+static inline bool
+get_image_shm(__DRIdrawable *dPriv, int x, int y, int width, int height,
+  struct pipe_resource *res)
+{
+   __DRIscreen *sPriv = dPriv->driScreenPriv;
+   const __DRIswrastLoaderExtension *loader = sPriv->swrast_loader;
+   struct winsys_handle whandle;
+
+   whandle.type = WINSYS_HANDLE_TYPE_SHMID;
+
+   if (loader->base.version < 4 || !loader->getImageShm)
+  return FALSE;
+
+   if (!res->screen->resource_get_handle(res->screen, NULL, res, , 
PIPE_HANDLE_USAGE_WRITE))
+  return FALSE;
+
+   loader->getImageShm(dPriv, x, y, width, height, whandle.handle, 
dPriv->loaderPrivate);
+   return TRUE;
+}
+
 static void
 drisw_update_drawable_info(struct dri_drawable *drawable)
 {
@@ -364,7 +384,8 @@ drisw_update_tex_buffer(struct dri_drawable *drawable,
x, y, w, h, );
 
/* Copy the Drawable content to the mapped texture buffer */
-   get_image(dPriv, x, y, w, h, map);
+   if (!get_image_shm(dPriv, x, y, w, h, res))
+  get_image(dPriv, x, y, w, h, map);
 
/* The pipe transfer has a pitch rounded up to the nearest 64 pixels.
   get_image() has a pitch rounded up to 4 bytes.  */

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Mesa (master): gallium: move winsys handle to it's own file.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: d2eaff33d0132ef17eb458f04e5369985129ce31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2eaff33d0132ef17eb458f04e5369985129ce31

Author: Marc-André Lureau 
Date:   Tue May 29 11:17:11 2018 +1000

gallium: move winsys handle to it's own file.

This will be used in the drisw interface later, which isn't
drm specific.

Reviewed-by: Marek Olšák 

---

 src/gallium/include/state_tracker/drm_driver.h| 49 +--
 src/gallium/include/state_tracker/winsys_handle.h | 57 +++
 2 files changed, 59 insertions(+), 47 deletions(-)

diff --git a/src/gallium/include/state_tracker/drm_driver.h 
b/src/gallium/include/state_tracker/drm_driver.h
index f188b5a7d4..19cd19f26e 100644
--- a/src/gallium/include/state_tracker/drm_driver.h
+++ b/src/gallium/include/state_tracker/drm_driver.h
@@ -4,58 +4,13 @@
 
 #include "pipe/p_compiler.h"
 
+#include "winsys_handle.h"
+
 struct pipe_screen;
 struct pipe_screen_config;
 struct pipe_context;
 struct pipe_resource;
 
-#define DRM_API_HANDLE_TYPE_SHARED 0
-#define DRM_API_HANDLE_TYPE_KMS1
-#define DRM_API_HANDLE_TYPE_FD 2
-
-
-/**
- * For use with pipe_screen::{texture_from_handle|texture_get_handle}.
- */
-struct winsys_handle
-{
-   /**
-* Input for texture_from_handle, valid values are
-* DRM_API_HANDLE_TYPE_SHARED or DRM_API_HANDLE_TYPE_FD.
-* Input to texture_get_handle,
-* to select handle for kms, flink, or prime.
-*/
-   unsigned type;
-   /**
-* Input for texture_get_handle, allows to export the offset
-* of a specific layer of an array texture.
-*/
-   unsigned layer;
-   /**
-* Input to texture_from_handle.
-* Output for texture_get_handle.
-*/
-   unsigned handle;
-   /**
-* Input to texture_from_handle.
-* Output for texture_get_handle.
-*/
-   unsigned stride;
-   /**
-* Input to texture_from_handle.
-* Output for texture_get_handle.
-*/
-   unsigned offset;
-
-   /**
-* Input to resource_from_handle.
-* Output from resource_get_handle.
-*/
-   uint64_t modifier;
-};
-
-
-
 /**
  * Configuration queries.
  */
diff --git a/src/gallium/include/state_tracker/winsys_handle.h 
b/src/gallium/include/state_tracker/winsys_handle.h
new file mode 100644
index 00..9217e4dcbf
--- /dev/null
+++ b/src/gallium/include/state_tracker/winsys_handle.h
@@ -0,0 +1,57 @@
+
+#ifndef _WINSYS_HANDLE_H_
+#define _WINSYS_HANDLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define DRM_API_HANDLE_TYPE_SHARED 0
+#define DRM_API_HANDLE_TYPE_KMS1
+#define DRM_API_HANDLE_TYPE_FD 2
+
+/**
+ * For use with pipe_screen::{texture_from_handle|texture_get_handle}.
+ */
+struct winsys_handle
+{
+   /**
+* Input for texture_from_handle, valid values are
+* WINSYS_HANDLE_TYPE_SHARED or WINSYS_HANDLE_TYPE_FD.
+* Input to texture_get_handle,
+* to select handle for kms, flink, or prime.
+*/
+   unsigned type;
+   /**
+* Input for texture_get_handle, allows to export the offset
+* of a specific layer of an array texture.
+*/
+   unsigned layer;
+   /**
+* Input to texture_from_handle.
+* Output for texture_get_handle.
+*/
+   unsigned handle;
+   /**
+* Input to texture_from_handle.
+* Output for texture_get_handle.
+*/
+   unsigned stride;
+   /**
+* Input to texture_from_handle.
+* Output for texture_get_handle.
+*/
+   unsigned offset;
+
+   /**
+* Input to resource_from_handle.
+* Output from resource_get_handle.
+*/
+   uint64_t modifier;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WINSYS_HANDLE_H_ */

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Mesa (master): drisw: use putImageShm if available

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 63c427fa71a07649d5c033a5c6184ef701348590
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63c427fa71a07649d5c033a5c6184ef701348590

Author: Marc-André Lureau 
Date:   Wed Jun 10 17:34:15 2015 +0200

drisw: use putImageShm if available

If the DRIswrastLoaderExtension implements putImageShm, bind it to
drisw_loader_funcs.

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/gallium/include/state_tracker/drisw_api.h |  3 +++
 src/gallium/state_trackers/dri/drisw.c| 37 +--
 2 files changed, 32 insertions(+), 8 deletions(-)

diff --git a/src/gallium/include/state_tracker/drisw_api.h 
b/src/gallium/include/state_tracker/drisw_api.h
index 03d5ee405a..36bef087a4 100644
--- a/src/gallium/include/state_tracker/drisw_api.h
+++ b/src/gallium/include/state_tracker/drisw_api.h
@@ -18,6 +18,9 @@ struct drisw_loader_funcs
   void *data, unsigned width, unsigned height);
void (*put_image2) (struct dri_drawable *dri_drawable,
void *data, int x, int y, unsigned width, unsigned 
height, unsigned stride);
+   void (*put_image_shm) (struct dri_drawable *dri_drawable,
+  int shmid, char *shmaddr, unsigned offset,
+  int x, int y, unsigned width, unsigned height, 
unsigned stride);
 };
 
 #endif
diff --git a/src/gallium/state_trackers/dri/drisw.c 
b/src/gallium/state_trackers/dri/drisw.c
index eb5752386d..40cbca5494 100644
--- a/src/gallium/state_trackers/dri/drisw.c
+++ b/src/gallium/state_trackers/dri/drisw.c
@@ -26,14 +26,6 @@
  *
  **/
 
-/* TODO:
- *
- * xshm / EGLImage:
- *
- * Allow the loaders to use the XSHM extension. It probably requires callbacks
- * for createImage/destroyImage similar to DRI2 getBuffers.
- */
-
 #include "util/u_format.h"
 #include "util/u_memory.h"
 #include "util/u_inlines.h"
@@ -87,6 +79,19 @@ put_image2(__DRIdrawable *dPriv, void *data, int x, int y,
 }
 
 static inline void
+put_image_shm(__DRIdrawable *dPriv, int shmid, char *shmaddr,
+  unsigned offset, int x, int y,
+  unsigned width, unsigned height, unsigned stride)
+{
+   __DRIscreen *sPriv = dPriv->driScreenPriv;
+   const __DRIswrastLoaderExtension *loader = sPriv->swrast_loader;
+
+   loader->putImageShm(dPriv, __DRI_SWRAST_IMAGE_OP_SWAP,
+   x, y, width, height, stride,
+   shmid, shmaddr, offset, dPriv->loaderPrivate);
+}
+
+static inline void
 get_image(__DRIdrawable *dPriv, int x, int y, int width, int height, void 
*data)
 {
__DRIscreen *sPriv = dPriv->driScreenPriv;
@@ -153,6 +158,17 @@ drisw_put_image2(struct dri_drawable *drawable,
 }
 
 static inline void
+drisw_put_image_shm(struct dri_drawable *drawable,
+int shmid, char *shmaddr, unsigned offset,
+int x, int y, unsigned width, unsigned height,
+unsigned stride)
+{
+   __DRIdrawable *dPriv = drawable->dPriv;
+
+   put_image_shm(dPriv, shmid, shmaddr, offset, x, y, width, height, stride);
+}
+
+static inline void
 drisw_present_texture(__DRIdrawable *dPriv,
   struct pipe_resource *ptex, struct pipe_box *sub_box)
 {
@@ -394,6 +410,7 @@ static struct drisw_loader_funcs drisw_lf = {
 static const __DRIconfig **
 drisw_init_screen(__DRIscreen * sPriv)
 {
+   const __DRIswrastLoaderExtension *loader = sPriv->swrast_loader;
const __DRIconfig **configs;
struct dri_screen *screen;
struct pipe_screen *pscreen = NULL;
@@ -409,6 +426,10 @@ drisw_init_screen(__DRIscreen * sPriv)
 
sPriv->driverPrivate = (void *)screen;
sPriv->extensions = drisw_screen_extensions;
+   if (loader->base.version >= 4) {
+  if (loader->putImageShm)
+ drisw_lf.put_image_shm = drisw_put_image_shm;
+   }
 
if (pipe_loader_sw_probe_dri(>dev, _lf)) {
   dri_init_options(screen);

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Mesa (master): drisw/glx: implement getImageShm

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 33ce3aa512fa9c8313003f61516588e1ae3e5f8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33ce3aa512fa9c8313003f61516588e1ae3e5f8f

Author: Marc-André Lureau 
Date:   Mon Jun 15 15:07:34 2015 +0200

drisw/glx: implement getImageShm

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/glx/drisw_glx.c | 31 ++-
 1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index 641917361b..3ff6a9617f 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx/drisw_glx.c
@@ -313,6 +313,32 @@ swrastGetImage(__DRIdrawable * read,
swrastGetImage2(read, x, y, w, h, 0, data, loaderPrivate);
 }
 
+static void
+swrastGetImageShm(__DRIdrawable * read,
+  int x, int y, int w, int h,
+  int shmid, void *loaderPrivate)
+{
+   struct drisw_drawable *prp = loaderPrivate;
+   __GLXDRIdrawable *pread = &(prp->base);
+   Display *dpy = pread->psc->dpy;
+   Drawable readable;
+   XImage *ximage;
+
+   if (!prp->ximage || shmid != prp->shminfo.shmid) {
+  if (!XCreateDrawable(prp, shmid, dpy))
+ return;
+   }
+   readable = pread->xDrawable;
+
+   ximage = prp->ximage;
+   ximage->data = prp->shminfo.shmaddr; /* no offset */
+   ximage->width = w;
+   ximage->height = h;
+   ximage->bytes_per_line = bytes_per_line(w * ximage->bits_per_pixel, 32);
+
+   XShmGetImage(dpy, readable, ximage, x, y, ~0L);
+}
+
 static __DRIswrastLoaderExtension swrastLoaderExtension = {
.base = {__DRI_SWRAST_LOADER, 4 },
 
@@ -322,6 +348,7 @@ static __DRIswrastLoaderExtension swrastLoaderExtension = {
.putImage2   = swrastPutImage2,
.getImage2   = swrastGetImage2,
.putImageShm = swrastPutImageShm,
+   .getImageShm = swrastGetImageShm,
 };
 
 static const __DRIextension *loader_extensions[] = {
@@ -802,8 +829,10 @@ driswCreateScreen(int screen, struct glx_display *priv)
if (extensions == NULL)
   goto handle_error;
 
-   if (!check_xshm(psc->base.dpy))
+   if (!check_xshm(psc->base.dpy)) {
   swrastLoaderExtension.putImageShm = NULL;
+  swrastLoaderExtension.getImageShm = NULL;
+   }
 
for (i = 0; extensions[i]; i++) {
   if (strcmp(extensions[i]->name, __DRI_CORE) == 0)

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Mesa (master): glx/drisw: make the shm/non-shm loader extensions separately.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: d3ff4787322c5855aad1e9ee0ee0aa141f7d6420
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3ff4787322c5855aad1e9ee0ee0aa141f7d6420

Author: Dave Airlie 
Date:   Tue May 29 13:04:03 2018 +1000

glx/drisw: make the shm/non-shm loader extensions separately.

I disliked removing the const here, function tables are meant
to be const just to avoid having to think about them,
make a second table for the shm vs non-shm paths to use.

Reviewed-by: Adam Jackson 

---

 src/glx/drisw_glx.c | 32 
 1 file changed, 24 insertions(+), 8 deletions(-)

diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index 3ff6a9617f..a2777100a3 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx/drisw_glx.c
@@ -339,7 +339,7 @@ swrastGetImageShm(__DRIdrawable * read,
XShmGetImage(dpy, readable, ximage, x, y, ~0L);
 }
 
-static __DRIswrastLoaderExtension swrastLoaderExtension = {
+static const __DRIswrastLoaderExtension swrastLoaderExtension_shm = {
.base = {__DRI_SWRAST_LOADER, 4 },
 
.getDrawableInfo = swrastGetDrawableInfo,
@@ -351,7 +351,22 @@ static __DRIswrastLoaderExtension swrastLoaderExtension = {
.getImageShm = swrastGetImageShm,
 };
 
-static const __DRIextension *loader_extensions[] = {
+static const __DRIextension *loader_extensions_shm[] = {
+   _shm.base,
+   NULL
+};
+
+static const __DRIswrastLoaderExtension swrastLoaderExtension = {
+   .base = {__DRI_SWRAST_LOADER, 3 },
+
+   .getDrawableInfo = swrastGetDrawableInfo,
+   .putImage= swrastPutImage,
+   .getImage= swrastGetImage,
+   .putImage2   = swrastPutImage2,
+   .getImage2   = swrastGetImage2,
+};
+
+static const __DRIextension *loader_extensions_noshm[] = {
,
NULL
 };
@@ -811,6 +826,7 @@ driswCreateScreen(int screen, struct glx_display *priv)
struct drisw_screen *psc;
struct glx_config *configs = NULL, *visuals = NULL;
int i;
+   const __DRIextension **loader_extensions_local;
 
psc = calloc(1, sizeof *psc);
if (psc == NULL)
@@ -829,10 +845,10 @@ driswCreateScreen(int screen, struct glx_display *priv)
if (extensions == NULL)
   goto handle_error;
 
-   if (!check_xshm(psc->base.dpy)) {
-  swrastLoaderExtension.putImageShm = NULL;
-  swrastLoaderExtension.getImageShm = NULL;
-   }
+   if (!check_xshm(psc->base.dpy))
+  loader_extensions_local = loader_extensions_noshm;
+   else
+  loader_extensions_local = loader_extensions_shm;
 
for (i = 0; extensions[i]; i++) {
   if (strcmp(extensions[i]->name, __DRI_CORE) == 0)
@@ -850,12 +866,12 @@ driswCreateScreen(int screen, struct glx_display *priv)
 
if (psc->swrast->base.version >= 4) {
   psc->driScreen =
- psc->swrast->createNewScreen2(screen, loader_extensions,
+ psc->swrast->createNewScreen2(screen, loader_extensions_local,
extensions,
_configs, psc);
} else {
   psc->driScreen =
- psc->swrast->createNewScreen(screen, loader_extensions,
+ psc->swrast->createNewScreen(screen, loader_extensions_local,
   _configs, psc);
}
if (psc->driScreen == NULL) {

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Mesa (master): drisw/glx: use XShm if possible

[Dave Airlie]

Module: Mesa
Branch: master
Commit: bcd80be49a8260c2233dd07b2048d459a91a9c91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcd80be49a8260c2233dd07b2048d459a91a9c91

Author: Marc-André Lureau 
Date:   Wed Jun 10 17:58:31 2015 +0200

drisw/glx: use XShm if possible

Implements putImageShm from DRIswrastLoaderExtension.

If XShm extension is not available, or fails, it will fallback on
regular XPutImage().

Tested on Linux only with 16bpp and 32bpp visual.

(airlied: tested on 24bpp as well)

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/glx/drisw_glx.c  | 165 +++
 src/glx/drisw_priv.h |   3 +
 2 files changed, 144 insertions(+), 24 deletions(-)

diff --git a/src/glx/drisw_glx.c b/src/glx/drisw_glx.c
index df2467a5c2..641917361b 100644
--- a/src/glx/drisw_glx.c
+++ b/src/glx/drisw_glx.c
@@ -28,10 +28,12 @@
 #include 
 #include "dri_common.h"
 #include "drisw_priv.h"
+#include 
+#include 
 
 static Bool
-XCreateDrawable(struct drisw_drawable * pdp,
-Display * dpy, XID drawable, int visualid)
+XCreateGCs(struct drisw_drawable * pdp,
+   Display * dpy, XID drawable, int visualid)
 {
XGCValues gcvalues;
long visMask;
@@ -56,15 +58,78 @@ XCreateDrawable(struct drisw_drawable * pdp,
if (!pdp->visinfo || num_visuals == 0)
   return False;
 
-   /* create XImage */
-   pdp->ximage = XCreateImage(dpy,
-  pdp->visinfo->visual,
-  pdp->visinfo->depth,
-  ZPixmap, 0, /* format, offset */
-  NULL,   /* data */
-  0, 0,   /* width, height */
-  32, /* bitmap_pad */
-  0); /* bytes_per_line */
+   return True;
+}
+
+static int xshm_error = 0;
+static int xshm_opcode = -1;
+
+/**
+ * Catches potential Xlib errors.
+ */
+static int
+handle_xerror(Display *dpy, XErrorEvent *event)
+{
+   (void) dpy;
+
+   assert(xshm_opcode != -1);
+   if (event->request_code != xshm_opcode ||
+   event->minor_code != X_ShmAttach)
+  return 0;
+
+   xshm_error = 1;
+   return 0;
+}
+
+static Bool
+XCreateDrawable(struct drisw_drawable * pdp, int shmid, Display * dpy)
+{
+   if (pdp->ximage) {
+  XDestroyImage(pdp->ximage);
+  pdp->ximage = NULL;
+   }
+
+   if (!xshm_error && shmid >= 0) {
+  pdp->shminfo.shmid = shmid;
+  pdp->ximage = XShmCreateImage(dpy,
+pdp->visinfo->visual,
+pdp->visinfo->depth,
+ZPixmap,  /* format */
+NULL, /* data */
+>shminfo,/* shminfo */
+0, 0);/* width, height */
+  if (pdp->ximage != NULL) {
+ int (*old_handler)(Display *, XErrorEvent *);
+
+ /* dispatch pending errors */
+ XSync(dpy, False);
+
+ old_handler = XSetErrorHandler(handle_xerror);
+ /* This may trigger the X protocol error we're ready to catch: */
+ XShmAttach(dpy, >shminfo);
+ XSync(dpy, False);
+
+ if (xshm_error) {
+ /* we are on a remote display, this error is normal, don't print it */
+XDestroyImage(pdp->ximage);
+pdp->ximage = NULL;
+ }
+
+ (void) XSetErrorHandler(old_handler);
+  }
+   }
+
+   if (pdp->ximage == NULL) {
+  pdp->shminfo.shmid = -1;
+  pdp->ximage = XCreateImage(dpy,
+ pdp->visinfo->visual,
+ pdp->visinfo->depth,
+ ZPixmap, 0, /* format, offset */
+ NULL,   /* data */
+ 0, 0,   /* width, height */
+ 32, /* bitmap_pad */
+ 0); /* bytes_per_line */
+   }
 
   /**
* swrast does not handle 24-bit depth with 24 bpp, so let X do the
@@ -79,7 +144,9 @@ XCreateDrawable(struct drisw_drawable * pdp,
 static void
 XDestroyDrawable(struct drisw_drawable * pdp, Display * dpy, XID drawable)
 {
-   XDestroyImage(pdp->ximage);
+   if (pdp->ximage)
+  XDestroyImage(pdp->ximage);
+
free(pdp->visinfo);
 
XFreeGC(dpy, pdp->gc);
@@ -133,9 +200,9 @@ bytes_per_line(unsigned pitch_bits, unsigned mul)
 }
 
 static void
-swrastPutImage2(__DRIdrawable * draw, int op,
+swrastXPutImage(__DRIdrawable * draw, int op,
 int x, int y, int w, int h, int stride,
-char *data

Mesa (master): drisw: use shared memory when possible

[Dave Airlie]

Module: Mesa
Branch: master
Commit: cf54bd5e8381dba18d52fe438acda20cc1685bf3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf54bd5e8381dba18d52fe438acda20cc1685bf3

Author: Marc-André Lureau 
Date:   Wed Jun 10 17:45:11 2015 +0200

drisw: use shared memory when possible

If drisw_loader_funcs implements put_image_shm, allocates display
target data with shared memory and display with put_image_shm().

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 src/gallium/winsys/sw/dri/dri_sw_winsys.c | 72 +--
 1 file changed, 60 insertions(+), 12 deletions(-)

diff --git a/src/gallium/winsys/sw/dri/dri_sw_winsys.c 
b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
index 00849985d6..b36a53e960 100644
--- a/src/gallium/winsys/sw/dri/dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/dri/dri_sw_winsys.c
@@ -26,6 +26,9 @@
  *
  **/
 
+#include 
+#include 
+
 #include "pipe/p_compiler.h"
 #include "pipe/p_format.h"
 #include "util/u_inlines.h"
@@ -45,6 +48,7 @@ struct dri_sw_displaytarget
unsigned stride;
 
unsigned map_flags;
+   int shmid;
void *data;
void *mapped;
const void *front_private;
@@ -79,6 +83,25 @@ dri_sw_is_displaytarget_format_supported( struct sw_winsys 
*ws,
return TRUE;
 }
 
+static char *
+alloc_shm(struct dri_sw_displaytarget *dri_sw_dt, unsigned size)
+{
+   char *addr;
+
+   dri_sw_dt->shmid = shmget(IPC_PRIVATE, size, IPC_CREAT|0777);
+   if (dri_sw_dt->shmid < 0)
+  return NULL;
+
+   addr = (char *) shmat(dri_sw_dt->shmid, 0, 0);
+   /* mark the segment immediately for deletion to avoid leaks */
+   shmctl(dri_sw_dt->shmid, IPC_RMID, 0);
+
+   if (addr == (char *) -1)
+  return NULL;
+
+   return addr;
+}
+
 static struct sw_displaytarget *
 dri_sw_displaytarget_create(struct sw_winsys *winsys,
 unsigned tex_usage,
@@ -88,6 +111,7 @@ dri_sw_displaytarget_create(struct sw_winsys *winsys,
 const void *front_private,
 unsigned *stride)
 {
+   struct dri_sw_winsys *ws = dri_sw_winsys(winsys);
struct dri_sw_displaytarget *dri_sw_dt;
unsigned nblocksy, size, format_stride;
 
@@ -106,7 +130,13 @@ dri_sw_displaytarget_create(struct sw_winsys *winsys,
nblocksy = util_format_get_nblocksy(format, height);
size = dri_sw_dt->stride * nblocksy;
 
-   dri_sw_dt->data = align_malloc(size, alignment);
+   dri_sw_dt->shmid = -1;
+   if (ws->lf->put_image_shm)
+  dri_sw_dt->data = alloc_shm(dri_sw_dt, size);
+
+   if(!dri_sw_dt->data)
+  dri_sw_dt->data = align_malloc(size, alignment);
+
if(!dri_sw_dt->data)
   goto no_data;
 
@@ -125,7 +155,12 @@ dri_sw_displaytarget_destroy(struct sw_winsys *ws,
 {
struct dri_sw_displaytarget *dri_sw_dt = dri_sw_displaytarget(dt);
 
-   align_free(dri_sw_dt->data);
+   if (dri_sw_dt->shmid >= 0) {
+  shmdt(dri_sw_dt->data);
+  shmctl(dri_sw_dt->shmid, IPC_RMID, 0);
+   } else {
+  align_free(dri_sw_dt->data);
+   }
 
FREE(dri_sw_dt);
 }
@@ -187,25 +222,38 @@ dri_sw_displaytarget_display(struct sw_winsys *ws,
struct dri_sw_winsys *dri_sw_ws = dri_sw_winsys(ws);
struct dri_sw_displaytarget *dri_sw_dt = dri_sw_displaytarget(dt);
struct dri_drawable *dri_drawable = (struct dri_drawable *)context_private;
-   unsigned width, height;
+   unsigned width, height, x = 0, y = 0;
unsigned blsize = util_format_get_blocksize(dri_sw_dt->format);
+   unsigned offset = 0;
+   void *data = dri_sw_dt->data;
 
/* Set the width to 'stride / cpp'.
 *
 * PutImage correctly clips to the width of the dst drawable.
 */
-   width = dri_sw_dt->stride / blsize;
-
-   height = dri_sw_dt->height;
-
if (box) {
-   void *data;
-   data = (char *)dri_sw_dt->data + (dri_sw_dt->stride * box->y) + box->x 
* blsize;
-   dri_sw_ws->lf->put_image2(dri_drawable, data,
- box->x, box->y, box->width, box->height, 
dri_sw_dt->stride);
+  offset = (dri_sw_dt->stride * box->y) + box->x * blsize;
+  data += offset;
+  x = box->x;
+  y = box->y;
+  width = box->width;
+  height = box->height;
} else {
-   dri_sw_ws->lf->put_image(dri_drawable, dri_sw_dt->data, width, height);
+  width = dri_sw_dt->stride / blsize;
+  height = dri_sw_dt->height;
}
+
+   if (dri_sw_dt->shmid != -1) {
+  dri_sw_ws->lf->put_image_shm(dri_drawable, dri_sw_dt->shmid, 
dri_sw_dt->data, offset,
+   x, y, width, height, dri_sw_dt->stride);
+  return;
+   }
+
+   if (box)
+  dri_sw_ws->lf->put_image2(dri_drawable, data,
+x, y, width, height, dri_sw_dt->stride);
+   else
+

Mesa (master): dri: add putImageShm and getImageShm to swrastLoader

[Dave Airlie]

Module: Mesa
Branch: master
Commit: de8085e649235cd120e9eb06b82cc1dbabeb8652
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de8085e649235cd120e9eb06b82cc1dbabeb8652

Author: Marc-André Lureau 
Date:   Wed Jun 10 17:28:47 2015 +0200

dri: add putImageShm and getImageShm to swrastLoader

Add new API to put and get an image using shared memory. Instead of only
passing the data pointer, 3 arguments are given: the shmid, the data
offset and the shmaddr.

Bump interface version.

Reviewed-by: Dave Airlie 
Reviewed-by: Adam Jackson 

---

 include/GL/internal/dri_interface.h | 20 +++-
 1 file changed, 19 insertions(+), 1 deletion(-)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 319a1fe4f9..c32cdd3767 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -589,7 +589,7 @@ struct __DRIdamageExtensionRec {
  * SWRast Loader extension.
  */
 #define __DRI_SWRAST_LOADER "DRI_SWRastLoader"
-#define __DRI_SWRAST_LOADER_VERSION 3
+#define __DRI_SWRAST_LOADER_VERSION 4
 struct __DRIswrastLoaderExtensionRec {
 __DRIextension base;
 
@@ -631,6 +631,24 @@ struct __DRIswrastLoaderExtensionRec {
void (*getImage2)(__DRIdrawable *readable,
 int x, int y, int width, int height, int stride,
 char *data, void *loaderPrivate);
+
+/**
+ * Put shm image to drawable
+ *
+ * \since 4
+ */
+void (*putImageShm)(__DRIdrawable *drawable, int op,
+int x, int y, int width, int height, int stride,
+int shmid, char *shmaddr, unsigned offset,
+void *loaderPrivate);
+/**
+ * Get shm image from readable
+ *
+ * \since 4
+ */
+void (*getImageShm)(__DRIdrawable *readable,
+int x, int y, int width, int height,
+int shmid, void *loaderPrivate);
 };
 
 /**

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Mesa (master): gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*

[Dave Airlie]

Module: Mesa
Branch: master
Commit: b7ac0779e0228969536a6738926b8b7a0d565cd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7ac0779e0228969536a6738926b8b7a0d565cd4

Author: Dave Airlie 
Date:   Tue May 29 11:21:38 2018 +1000

gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_*

This just renames this as we want to add an shm handle which
isn't really drm related.

Originally by: Marc-André Lureau 
(airlied: I used this sed script instead)
This was generated with:
 git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g'

Reviewed-by: Marek Olšák 

---

 src/gallium/auxiliary/renderonly/renderonly.c |  4 +--
 src/gallium/auxiliary/renderonly/renderonly.h |  2 +-
 src/gallium/auxiliary/vl/vl_winsys_dri.c  |  2 +-
 src/gallium/auxiliary/vl/vl_winsys_dri3.c |  4 +--
 src/gallium/drivers/etnaviv/etnaviv_resource.c|  8 +++---
 src/gallium/drivers/etnaviv/etnaviv_screen.c  |  4 +--
 src/gallium/drivers/freedreno/freedreno_screen.c  | 12 -
 src/gallium/drivers/nouveau/nouveau_screen.c  | 12 -
 src/gallium/drivers/radeonsi/si_texture.c |  2 +-
 src/gallium/drivers/tegra/tegra_screen.c  |  4 +--
 src/gallium/drivers/v3d/v3d_resource.c| 10 
 src/gallium/drivers/vc4/vc4_resource.c| 10 
 src/gallium/include/pipe/p_screen.h   |  6 ++---
 src/gallium/include/state_tracker/winsys_handle.h |  6 ++---
 src/gallium/state_trackers/dri/dri2.c | 30 +++
 src/gallium/state_trackers/nine/swapchain9.c  |  2 +-
 src/gallium/state_trackers/va/buffer.c|  2 +-
 src/gallium/state_trackers/va/surface.c   |  4 +--
 src/gallium/state_trackers/vdpau/output.c |  2 +-
 src/gallium/state_trackers/vdpau/surface.c|  2 +-
 src/gallium/state_trackers/xa/xa_tracker.c|  8 +++---
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 10 
 src/gallium/winsys/i915/drm/i915_drm_buffer.c | 12 -
 src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 14 +--
 src/gallium/winsys/svga/drm/vmw_screen_dri.c  | 14 +--
 src/gallium/winsys/svga/drm/vmw_screen_ioctl.c|  6 ++---
 src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 12 -
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c   | 12 -
 src/mesa/state_tracker/st_cb_memoryobjects.c  |  2 +-
 src/mesa/state_tracker/st_vdpau.c |  2 +-
 30 files changed, 110 insertions(+), 110 deletions(-)

diff --git a/src/gallium/auxiliary/renderonly/renderonly.c 
b/src/gallium/auxiliary/renderonly/renderonly.c
index d31f458845..f83910a940 100644
--- a/src/gallium/auxiliary/renderonly/renderonly.c
+++ b/src/gallium/auxiliary/renderonly/renderonly.c
@@ -98,7 +98,7 @@ renderonly_create_kms_dumb_buffer_for_resource(struct 
pipe_resource *rsc,
 
/* fill in winsys handle */
memset(out_handle, 0, sizeof(*out_handle));
-   out_handle->type = DRM_API_HANDLE_TYPE_FD;
+   out_handle->type = WINSYS_HANDLE_TYPE_FD;
out_handle->stride = create_dumb.pitch;
 
err = drmPrimeHandleToFD(ro->kms_fd, create_dumb.handle, O_CLOEXEC,
@@ -130,7 +130,7 @@ renderonly_create_gpu_import_for_resource(struct 
pipe_resource *rsc,
boolean status;
int fd, err;
struct winsys_handle handle = {
-  .type = DRM_API_HANDLE_TYPE_FD
+  .type = WINSYS_HANDLE_TYPE_FD
};
 
scanout = CALLOC_STRUCT(renderonly_scanout);
diff --git a/src/gallium/auxiliary/renderonly/renderonly.h 
b/src/gallium/auxiliary/renderonly/renderonly.h
index 6a89c29e2e..a8d6a686ed 100644
--- a/src/gallium/auxiliary/renderonly/renderonly.h
+++ b/src/gallium/auxiliary/renderonly/renderonly.h
@@ -85,7 +85,7 @@ renderonly_get_handle(struct renderonly_scanout *scanout,
if (!scanout)
   return FALSE;
 
-   assert(handle->type == DRM_API_HANDLE_TYPE_KMS);
+   assert(handle->type == WINSYS_HANDLE_TYPE_KMS);
handle->handle = scanout->handle;
handle->stride = scanout->stride;
 
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri.c
index 79ebf750cd..bb1ff50488 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri.c
@@ -231,7 +231,7 @@ vl_dri2_screen_texture_from_drawable(struct vl_screen 
*vscreen, void *drawable)
}
 
memset(_handle, 0, sizeof(dri2_handle));
-   dri2_handle.type = DRM_API_HANDLE_TYPE_SHARED;
+   dri2_handle.type = WINSYS_HANDLE_TYPE_SHARED;
dri2_handle.handle = back_left->name;
dri2_handle.stride = back_left->pitch;
 
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 8251087f3f..8e3c4a0e04 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -271,7 +271,7 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
   pixmap_buffer_texture = buffer->texture;
}
memset(

Mesa (master): r600: Fix SSG when not all components are written

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 1aec4a07d45164fdb9ba4bc97f330a0e217e3bef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1aec4a07d45164fdb9ba4bc97f330a0e217e3bef

Author: Gert Wollny <gw.foss...@gmail.com>
Date:   Sat May 26 18:48:32 2018 +0200

r600: Fix SSG when not all components are written

Make sure only those components are written to that are specified in the
write mask.

Fixes:
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_float_fragment
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_float_fragment
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_float_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.lowp_vec3_fragment
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.mediump_vec3_fragment
  dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_vertex
  
dEQP-GLES2.functional.shaders.operator.common_functions.sign.highp_vec3_fragment
Signed-off-by: Gert Wollny <gw.foss...@gmail.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index da89bb28e7..c9f2fa6485 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -6679,11 +6679,15 @@ static int tgsi_issg(struct r600_shader_ctx *ctx)
 static int tgsi_ssg(struct r600_shader_ctx *ctx)
 {
struct tgsi_full_instruction *inst = 
>parse.FullToken.FullInstruction;
+   unsigned write_mask = inst->Dst[0].Register.WriteMask;
+   int last_inst = tgsi_last_instruction(write_mask);
struct r600_bytecode_alu alu;
int i, r;
 
/* tmp = (src > 0 ? 1 : src) */
-   for (i = 0; i < 4; i++) {
+   for (i = 0; i <= last_inst; i++) {
+   if (!(write_mask & (1 << i)))
+   continue;
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_CNDGT;
alu.is_op3 = 1;
@@ -6695,7 +6699,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
alu.src[1].sel = V_SQ_ALU_SRC_1;
r600_bytecode_src([2], >src[0], i);
 
-   if (i == 3)
+   if (i == last_inst)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
@@ -6703,7 +6707,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
}
 
/* dst = (-tmp > 0 ? -1 : tmp) */
-   for (i = 0; i < 4; i++) {
+   for (i = 0; i <= last_inst; i++) {
+   if (!(write_mask & (1 << i)))
+   continue;
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP3_CNDGT;
alu.is_op3 = 1;
@@ -6719,7 +6725,7 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
alu.src[2].sel = ctx->temp_reg;
alu.src[2].chan = i;
 
-   if (i == 3)
+   if (i == last_inst)
alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, );
if (r)

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Mesa (master): r600: Correct IDIV if DST and SRC use the same temporary

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 42cd2810aa30dfd825d46a305134fbc8f239247c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42cd2810aa30dfd825d46a305134fbc8f239247c

Author: Gert Wollny <gw.foss...@gmail.com>
Date:   Sat May 26 18:48:31 2018 +0200

r600: Correct IDIV if DST and SRC use the same temporary

In cases like

  IDIV TEMP[0].xy TEMP[0].xx TEMP[1].yy

the result will be written to the same register that is also a source register.
Since the components are evaluated one by one, this may result in overwriting
the source value for a later operation. Work around this by adding another
temporary to store the result if the destination temporary index is equal to
one of the source temporary indices.

Fixes:
  dEQP-GLES2.functional.shaders.operator.binary_operator.div.*
Signed-off-by: Gert Wollny <gw.foss...@gmail.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 52 --
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index bd511c76ac..da89bb28e7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -5727,10 +5727,19 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
struct r600_bytecode_alu alu;
int i, r, j;
unsigned write_mask = inst->Dst[0].Register.WriteMask;
+   int lasti = tgsi_last_instruction(write_mask);
int tmp0 = ctx->temp_reg;
int tmp1 = r600_get_temp(ctx);
int tmp2 = r600_get_temp(ctx);
int tmp3 = r600_get_temp(ctx);
+   int tmp4 = 0;
+
+   /* Use additional temp if dst register and src register are the same */
+   if (inst->Src[0].Register.Index == inst->Dst[0].Register.Index ||
+   inst->Src[1].Register.Index == inst->Dst[0].Register.Index) {
+   tmp4 = r600_get_temp(ctx);
+   }
+
/* Unsigned path:
 *
 * we need to represent src1 as src2*q + r, where q - quotient, r - 
remainder
@@ -6345,7 +6354,13 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
alu.dst.chan = 2;
alu.dst.write = 1;
} else {
-   tgsi_dst(ctx, >Dst[0], i, );
+   if (tmp4 > 0) {
+   alu.dst.sel = tmp4;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   } else {
+   tgsi_dst(ctx, >Dst[0], i, );
+   }
}
 
alu.src[0].sel = tmp1;
@@ -6387,7 +6402,13 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
alu.op = ALU_OP3_CNDGE_INT;
alu.is_op3 = 1;
 
-   tgsi_dst(ctx, >Dst[0], i, );
+   if (tmp4 > 0) {
+   alu.dst.sel = tmp4;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   } else {
+   tgsi_dst(ctx, >Dst[0], i, 
);
+   }
 
r600_bytecode_src([0], >src[0], i);
alu.src[1].sel = tmp0;
@@ -6423,7 +6444,13 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
alu.op = ALU_OP3_CNDGE_INT;
alu.is_op3 = 1;
 
-   tgsi_dst(ctx, >Dst[0], i, );
+   if (tmp4 > 0) {
+   alu.dst.sel = tmp4;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   } else {
+   tgsi_dst(ctx, >Dst[0], i, 
);
+   }
 
alu.src[0].sel = tmp2;
alu.src[0].chan = 2;
@@ -6438,6 +6465,25 @@ static int tgsi_divmod(struct r600_shader_ctx *ctx, int 
mod, int signed_op)
}
}
}
+
+   if (tmp4 > 0) {
+   for (i = 0; i <= lasti; ++i) {
+   if (!(write_mask & (1<<i)))
+   continue;
+
+   memset(, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+   tgsi_dst(ctx, >Dst[0], i, );
+   alu.src[0].sel = tmp4;
+   alu.src[0].chan = i;
+
+   if (i == lasti)
+  

Mesa (master): tgsi/scan: add hw atomic to the list of memory accessing files

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f2f464de576187891eeadb3e7fadf9ddbf322cba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2f464de576187891eeadb3e7fadf9ddbf322cba

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu May 10 01:01:58 2018 +0100

tgsi/scan: add hw atomic to the list of memory accessing files

This fixes 4 out of 5 cases in:
arb_framebuffer_no_attachments-atomic on cayman.

Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Cc: "18.0 18.1" <mesa-sta...@lists.freedesktop.org>

---

 src/gallium/auxiliary/tgsi/tgsi_scan.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 685a413c4e..e13500a7f7 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -50,7 +50,8 @@ is_memory_file(unsigned file)
return file == TGSI_FILE_SAMPLER ||
   file == TGSI_FILE_SAMPLER_VIEW ||
   file == TGSI_FILE_IMAGE ||
-  file == TGSI_FILE_BUFFER;
+  file == TGSI_FILE_BUFFER ||
+  file == TGSI_FILE_HW_ATOMIC;
 }
 
 

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Mesa (master): virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: bfa74bb44ddf3e81dedf9af28f86110dfd47dc45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfa74bb44ddf3e81dedf9af28f86110dfd47dc45

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri May 18 10:44:27 2018 +1000

virgl: set texture buffer offset alignment to disable ARB_texture_buffer_range.

The host side hasn't got support for this feature yet, so don't enable it
unless we get the caps from the host.

This makes the texture buffer range piglit tests skip now.

Fixes: fe0647df5a7 (virgl: add offset alignment values to to v2 caps struct)
Reviewed-by: Gurchetan Singh <gurchetansi...@chromium.org>

---

 src/gallium/drivers/virgl/virgl_winsys.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index 99e98ad9c9..690e610e19 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -132,7 +132,7 @@ static inline void virgl_ws_fill_new_caps_defaults(struct 
virgl_drm_caps *caps)
caps->caps.v2.max_texel_offset = 7;
caps->caps.v2.min_texture_gather_offset = -8;
caps->caps.v2.max_texture_gather_offset = 7;
-   caps->caps.v2.texture_buffer_offset_alignment = 32;
+   caps->caps.v2.texture_buffer_offset_alignment = 0;
caps->caps.v2.uniform_buffer_offset_alignment = 256;
 }
 #endif

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Mesa (master): vbo: remove MaxVertexAttribStride assert check.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 48e28ab961f54466c033b087931ee17d502821db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48e28ab961f54466c033b087931ee17d502821db

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue May 15 15:44:04 2018 +1000

vbo: remove MaxVertexAttribStride assert check.

Some drivers (virgl) don't support GL4.4 or GLES3.1 yet,
so never fill in this const.

Reviewed-by: Mathias Fröhlich <mathias.froehl...@web.de>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/mesa/vbo/vbo_exec_draw.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/mesa/vbo/vbo_exec_draw.c b/src/mesa/vbo/vbo_exec_draw.c
index 342fbc6070..8d74725db3 100644
--- a/src/mesa/vbo/vbo_exec_draw.c
+++ b/src/mesa/vbo/vbo_exec_draw.c
@@ -201,7 +201,6 @@ vbo_exec_bind_arrays(struct gl_context *ctx)
 
/* Bind the buffer object */
const GLuint stride = exec->vtx.vertex_size*sizeof(GLfloat);
-   assert(stride <= ctx->Const.MaxVertexAttribStride);
_mesa_bind_vertex_buffer(ctx, vao, 0, exec->vtx.bufferobj, buffer_offset,
 stride);
 

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Mesa (master): ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic

[Dave Airlie]

Module: Mesa
Branch: master
Commit: eba4cf797c0cee710b04f4d992e5b16796964ecd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eba4cf797c0cee710b04f4d992e5b16796964ecd

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed May 16 09:36:22 2018 +1000

ac/llvm: use amdgcn.tbuffer.store instead of SI.tbuffer.store intrinsic

Drop the use of the old intrinsic.

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_llvm_build.c | 92 +++---
 1 file changed, 60 insertions(+), 32 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index c9b2e36b63..6f5f04496e 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -888,11 +888,18 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
bool writeonly_memory,
bool swizzle_enable_hint)
 {
+   static unsigned dfmt[] = {
+   V_008F0C_BUF_DATA_FORMAT_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32_32,
+   V_008F0C_BUF_DATA_FORMAT_32_32_32_32
+   };
+
/* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
 * (voffset is swizzled, but soffset isn't swizzled).
 * llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
 */
-   if (!swizzle_enable_hint) {
+   if (!swizzle_enable_hint || HAVE_LLVM >= 0x0500) {
/* Split 3 channel stores, becase LLVM doesn't support 3-channel
 * intrinsics. */
if (num_channels == 3) {
@@ -915,42 +922,63 @@ ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
}
 
unsigned func = CLAMP(num_channels, 1, 3) - 1;
-   static const char *types[] = {"f32", "v2f32", "v4f32"};
char name[256];
-   LLVMValueRef offset = soffset;
-
-   if (inst_offset)
-   offset = LLVMBuildAdd(ctx->builder, offset,
- LLVMConstInt(ctx->i32, 
inst_offset, 0), "");
-   if (voffset)
-   offset = LLVMBuildAdd(ctx->builder, offset, voffset, 
"");
-
-   LLVMValueRef args[] = {
-   ac_to_float(ctx, vdata),
-   LLVMBuildBitCast(ctx->builder, rsrc, ctx->v4i32, ""),
-   LLVMConstInt(ctx->i32, 0, 0),
-   offset,
-   LLVMConstInt(ctx->i1, glc, 0),
-   LLVMConstInt(ctx->i1, slc, 0),
-   };
-
-   snprintf(name, sizeof(name), "llvm.amdgcn.buffer.store.%s",
-types[func]);
-
-   ac_build_intrinsic(ctx, name, ctx->voidt,
-  args, ARRAY_SIZE(args),
-  writeonly_memory ?
+
+   if (!swizzle_enable_hint) {
+   LLVMValueRef offset = soffset;
+
+   static const char *types[] = {"f32", "v2f32", "v4f32"};
+
+   if (inst_offset)
+   offset = LLVMBuildAdd(ctx->builder, offset,
+ LLVMConstInt(ctx->i32, 
inst_offset, 0), "");
+   if (voffset)
+   offset = LLVMBuildAdd(ctx->builder, offset, 
voffset, "");
+
+   LLVMValueRef args[] = {
+   ac_to_float(ctx, vdata),
+   LLVMBuildBitCast(ctx->builder, rsrc, 
ctx->v4i32, ""),
+   LLVMConstInt(ctx->i32, 0, 0),
+   offset,
+   LLVMConstInt(ctx->i1, glc, 0),
+   LLVMConstInt(ctx->i1, slc, 0),
+   };
+
+   snprintf(name, sizeof(name), 
"llvm.amdgcn.buffer.store.%s",
+types[func]);
+
+   ac_build_intrinsic(ctx, name, ctx->voidt,
+  args, ARRAY_SIZE(args),
+  writeonly_memory ?
   AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
   AC_FUNC_ATTR_WRITEONLY);
-   return;
+   return;
+   } else {
+   static const char *types[] = {"i32", "v2i32", "v4i32"};
+   LLVMValueRef args[] = {
+   vdata,
+   LLVMBuildBitCast(ctx->builder, rsrc, 
ctx->v4i32, ""),

Mesa (master): virgl: enable vertex streams when glsl level is high enough.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9585e702065d9c2db57ab32f53a42d1ceafdb4a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9585e702065d9c2db57ab32f53a42d1ceafdb4a3

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Dec 21 16:59:58 2015 +1000

virgl: enable vertex streams when glsl level is high enough.

This enabled the vertex streams out when the host supports
GL4.0.

---

 src/gallium/drivers/virgl/virgl_encode.c | 2 +-
 src/gallium/drivers/virgl/virgl_screen.c | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index a6f6d13f85..f3cbd1ca4b 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -232,7 +232,7 @@ static void virgl_emit_shader_streamout(struct 
virgl_context *ctx,
VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) 
|

VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset);
  virgl_encoder_write_dword(ctx->cbuf, tmp);
- virgl_encoder_write_dword(ctx->cbuf, 0);
+ virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream);
   }
}
 }
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index ab35b1fe2c..1ca9e85de7 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -198,12 +198,13 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
   return vscreen->caps.caps.v1.bset.has_sample_shading;
case PIPE_CAP_CULL_DISTANCE:
   return vscreen->caps.caps.v1.bset.has_cull;
+   case PIPE_CAP_MAX_VERTEX_STREAMS:
+  return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
-   case PIPE_CAP_MAX_VERTEX_STREAMS:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:

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Mesa (master): radv: resolve all layers in compute resolve path.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 98dbaa445a83108b59bd56e8f3224c13c36ba1d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98dbaa445a83108b59bd56e8f3224c13c36ba1d5

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri May 11 14:54:21 2018 +1000

radv: resolve all layers in compute resolve path.

This path should iterate across all layers, I've some ideas
for doing this in a single pass, but this is simpler for now.

This passes the tests because we don't use the fragment path
unless we have DCC, and we don't have DCC on layered images.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Cc: <mesa-sta...@lists.freedesktop.org>

---

 src/amd/vulkan/radv_meta_resolve_cs.c | 48 ++-
 1 file changed, 42 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c 
b/src/amd/vulkan/radv_meta_resolve_cs.c
index 274e64999a..322e72e465 100644
--- a/src/amd/vulkan/radv_meta_resolve_cs.c
+++ b/src/amd/vulkan/radv_meta_resolve_cs.c
@@ -508,12 +508,48 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer 
*cmd_buffer)
if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
continue;
 
-   emit_resolve(cmd_buffer,
-src_iview,
-dst_iview,
-&(VkOffset2D) { 0, 0 },
-&(VkOffset2D) { 0, 0 },
-&(VkExtent2D) { fb->width, fb->height });
+   struct radv_image *src_image = src_iview->image;
+   struct radv_image *dst_image = dst_iview->image;
+   for (uint32_t layer = 0; layer < src_image->info.array_size; 
layer++) {
+
+   struct radv_image_view tsrc_iview;
+   radv_image_view_init(_iview, cmd_buffer->device,
+&(VkImageViewCreateInfo) {
+.sType = 
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+.image = 
radv_image_to_handle(src_image),
+.viewType = 
radv_meta_get_view_type(src_image),
+.format = 
src_image->vk_format,
+.subresourceRange 
= {
+.aspectMask = 
VK_IMAGE_ASPECT_COLOR_BIT,
+.baseMipLevel = 
src_iview->base_mip,
+.levelCount = 1,
+.baseArrayLayer = 
layer,
+.layerCount = 1,
+},
+});
+
+   struct radv_image_view tdst_iview;
+   radv_image_view_init(_iview, cmd_buffer->device,
+&(VkImageViewCreateInfo) {
+.sType = 
VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
+.image = 
radv_image_to_handle(dst_image),
+.viewType = 
radv_meta_get_view_type(dst_image),
+.format = 
vk_to_non_srgb_format(dst_image->vk_format),
+.subresourceRange 
= {
+.aspectMask = 
VK_IMAGE_ASPECT_COLOR_BIT,
+.baseMipLevel = 
dst_iview->base_mip,
+.levelCount = 1,
+.baseArrayLayer = 
layer,
+.layerCount = 1,
+},
+});
+   emit_resolve(cmd_buffer,
+_iview,
+_iview,
+&(VkOffset2D) { 0, 0 },
+&(VkOffset2D) { 0, 0 },
+&(VkExtent2D) { fb->width, fb->height });
+   }
}
 
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |

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Mesa (master): radv/resolve: do fmask decompress on all layers.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b16fc6cda11576a4dd6c8d95f7bee94121c4b8e7

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri May 11 14:53:28 2018 +1000

radv/resolve: do fmask decompress on all layers.

For a multi-layer subpass resolve we want to make sure we flush all
the layers.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Cc: <mesa-sta...@lists.freedesktop.org>

---

 src/amd/vulkan/radv_meta_resolve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_resolve.c 
b/src/amd/vulkan/radv_meta_resolve.c
index f3e088b10c..75916713c0 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -695,7 +695,7 @@ radv_decompress_resolve_subpass_src(struct radv_cmd_buffer 
*cmd_buffer)
VkImageResolve region = {};
region.srcSubresource.baseArrayLayer = 0;
region.srcSubresource.mipLevel = 0;
-   region.srcSubresource.layerCount = 1;
+   region.srcSubresource.layerCount = src_image->info.array_size;
 
radv_decompress_resolve_src(cmd_buffer, src_image,
src_att.layout, 1, );

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Mesa (master): radv: use compute path for multi-layer images.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 5978d54a09e6ad151c0bd365de0e2c82bbf493d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5978d54a09e6ad151c0bd365de0e2c82bbf493d1

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri May 11 14:55:29 2018 +1000

radv: use compute path for multi-layer images.

I don't think the hw resolve path can't handle multi-layer images.

This fixes all the:
dEQP-VK.renderpass.multisample_resolve.layers_*
tests on my VI card.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Cc: <mesa-sta...@lists.freedesktop.org>

---

 src/amd/vulkan/radv_meta_resolve.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_resolve.c 
b/src/amd/vulkan/radv_meta_resolve.c
index 75916713c0..d4d3552f31 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -358,6 +358,8 @@ static void radv_pick_resolve_method_images(struct 
radv_image *src_image,
*method = RESOLVE_COMPUTE;
else if (vk_format_is_int(src_image->vk_format))
*method = RESOLVE_COMPUTE;
+   else if (src_image->info.array_size > 1)
+   *method = RESOLVE_COMPUTE;

if (radv_layout_dcc_compressed(dest_image, dest_image_layout, 
queue_mask)) {
*method = RESOLVE_FRAGMENT;

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Mesa (master): virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE

[Dave Airlie]

Module: Mesa
Branch: master
Commit: fb4011ace9022e674639f2743272b7eba650cde3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb4011ace9022e674639f2743272b7eba650cde3

Author: Gert Wollny <gert.wol...@collabora.com>
Date:   Wed May  9 16:51:49 2018 +0200

virgl: Add support for passing GL_ANY_SAMPLES_PASSED_CONSERVATIVE

This is needed for fixing CTS:
   dEQP-GLES3.functional.occlusion_query.conservative*

Reviewed-by: Dave Airlie <airl...@redhat.com>
Signed-off-by: Gert Wollny <gert.wol...@collabora.com>

---

 src/gallium/drivers/virgl/virgl_query.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_query.c 
b/src/gallium/drivers/virgl/virgl_query.c
index 3a930d2966..e4d955442b 100644
--- a/src/gallium/drivers/virgl/virgl_query.c
+++ b/src/gallium/drivers/virgl/virgl_query.c
@@ -48,12 +48,13 @@ struct virgl_query {
 #define VIRGL_QUERY_SO_OVERFLOW_PREDICATE 8
 #define VIRGL_QUERY_GPU_FINISHED  9
 #define VIRGL_QUERY_PIPELINE_STATISTICS  10
+#define VIRGL_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE 11
 
 static const int pquery_map[] =
 {
VIRGL_QUERY_OCCLUSION_COUNTER,
VIRGL_QUERY_OCCLUSION_PREDICATE,
-   -1,
+   VIRGL_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE,
VIRGL_QUERY_TIMESTAMP,
VIRGL_QUERY_TIMESTAMP_DISJOINT,
VIRGL_QUERY_TIME_ELAPSED,

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Mesa (master): r600: fix constant buffer bounds.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: ce027ac5c798b39582288e5d7d9973b3cdda591e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce027ac5c798b39582288e5d7d9973b3cdda591e

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed May  9 23:17:09 2018 +0100

r600: fix constant buffer bounds.

If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).

If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.

This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-sta...@lists.freedesktop.org>

Reviewed-by: Roland Scheidegger <srol...@vmware.com>

---

 src/gallium/drivers/r600/evergreen_state.c | 2 +-
 src/gallium/drivers/r600/r600_state.c  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 48934158bd..05f4a65059 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2202,7 +2202,7 @@ static void evergreen_emit_constant_buffers(struct 
r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 8, 0) | pkt_flags);
radeon_emit(cs, (buffer_id_base + buffer_index) * 8);
radeon_emit(cs, va); /* RESOURCEi_WORD0 */
-   radeon_emit(cs, rbuffer->b.b.width0 - cb->buffer_offset - 1); 
/* RESOURCEi_WORD1 */
+   radeon_emit(cs, cb->buffer_size -1); /* RESOURCEi_WORD1 */
radeon_emit(cs, /* RESOURCEi_WORD2 */
S_030008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : 
r600_endian_swap(32)) |
S_030008_STRIDE(gs_ring_buffer ? 4 : 16) |
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 923817119f..a37a701837 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1729,7 +1729,7 @@ static void r600_emit_constant_buffers(struct 
r600_context *rctx,
radeon_emit(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
radeon_emit(cs, (buffer_id_base + buffer_index) * 7);
radeon_emit(cs, offset); /* RESOURCEi_WORD0 */
-   radeon_emit(cs, rbuffer->b.b.width0 - offset - 1); /* 
RESOURCEi_WORD1 */
+   radeon_emit(cs, cb->buffer_size - 1); /* RESOURCEi_WORD1 */
radeon_emit(cs, /* RESOURCEi_WORD2 */
S_038008_ENDIAN_SWAP(gs_ring_buffer ? ENDIAN_NONE : 
r600_endian_swap(32)) |
S_038008_STRIDE(gs_ring_buffer ? 4 : 16));

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Mesa (master): radv: handle arrays in the fmask descriptor.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 56766b8515bf73a0f4fc84fad81ba808a520391a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56766b8515bf73a0f4fc84fad81ba808a520391a

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 07:13:46 2018 +

radv: handle arrays in the fmask descriptor.

This fixes the fmask descriptor generation to handle 2d ms arrays.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index bfe497caa3..ad480901ee 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -619,7 +619,7 @@ si_make_texture_descriptor(struct radv_device *device,
S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
-   S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 1, 
0, false, false));
+   S_008F1C_TYPE(radv_tex_dim(image->type, view_type, 
image->info.array_size, 0, false, false));
fmask_state[4] = 0;
fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
fmask_state[6] = 0;

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Mesa (master): radv: set fmask_surf_index on fmask surfaces.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e66f64c2855604c6148e8e865a65411ff0c3ba02
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e66f64c2855604c6148e8e865a65411ff0c3ba02

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue May  1 12:32:02 2018 +1000

radv: set fmask_surf_index on fmask surfaces.

This is needed for gfx9 and later for all fmask surface index.

(Mentioned by Marek on irc)

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_image.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index a6f3628c8f..bfe497caa3 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -742,8 +742,10 @@ radv_image_get_fmask_info(struct radv_device *device,
info.samples = 1;
fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
 
-   if (!image->shareable)
+   if (!image->shareable) {
+   info.fmask_surf_index = >fmask_mrt_offset_counter;
info.surf_index = >fmask_mrt_offset_counter;
+   }
 
/* Force 2D tiling if it wasn't set. This may occur when creating
 * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample

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Mesa (master): ac/radv/radeonsi: refactor raster_config default values getters.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 899df55ee046847dfd2a49059a649da4e6c29fdb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=899df55ee046847dfd2a49059a649da4e6c29fdb

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 10:09:36 2018 +1000

ac/radv/radeonsi: refactor raster_config default values getters.

This just makes this common code between the two drivers.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_gpu_info.c| 93 +
 src/amd/common/ac_gpu_info.h|  4 +-
 src/amd/vulkan/si_cmd_buffer.c  | 85 ++
 src/gallium/drivers/radeonsi/si_state.c | 85 ++
 4 files changed, 102 insertions(+), 165 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 12b03c4ea2..47a87650a6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -554,3 +554,96 @@ ac_get_gs_table_depth(enum chip_class chip_class, enum 
radeon_family family)
unreachable("Unknown GPU");
}
 }
+
+void
+ac_get_raster_config(struct radeon_info *info,
+uint32_t *raster_config_p,
+uint32_t *raster_config_1_p)
+{
+   unsigned num_rb = MIN2(info->num_render_backends, 16);
+   unsigned raster_config, raster_config_1;
+   switch (info->family) {
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   raster_config = 0x2a00126a;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_VERDE:
+   raster_config = 0x124a;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_OLAND:
+   raster_config = 0x0082;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_HAINAN:
+   raster_config = 0x;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_BONAIRE:
+   raster_config = 0x1612;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_HAWAII:
+   raster_config = 0x3a00161a;
+   raster_config_1 = 0x002e;
+   break;
+   case CHIP_FIJI:
+   if (info->cik_macrotile_mode_array[0] == 0x00e8) {
+   /* old kernels with old tiling config */
+   raster_config = 0x1612;
+   raster_config_1 = 0x002a;
+   } else {
+   raster_config = 0x3a00161a;
+   raster_config_1 = 0x002e;
+   }
+   break;
+   case CHIP_POLARIS10:
+   raster_config = 0x1612;
+   raster_config_1 = 0x002a;
+   break;
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   raster_config = 0x1612;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_VEGAM:
+   raster_config = 0x3a00161a;
+   raster_config_1 = 0x002e;
+   break;
+   case CHIP_TONGA:
+   raster_config = 0x1612;
+   raster_config_1 = 0x002a;
+   break;
+   case CHIP_ICELAND:
+   if (num_rb == 1)
+   raster_config = 0x;
+   else
+   raster_config = 0x0002;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_CARRIZO:
+   raster_config = 0x0002;
+   raster_config_1 = 0x;
+   break;
+   case CHIP_KAVERI:
+   /* KV should be 0x0002, but that causes problems with 
radeon */
+   raster_config = 0x; /* 0x0002 */
+   raster_config_1 = 0x;
+   break;
+   case CHIP_KABINI:
+   case CHIP_MULLINS:
+   case CHIP_STONEY:
+   raster_config = 0x;
+   raster_config_1 = 0x;
+   break;
+   default:
+   fprintf(stderr,
+   "ac: Unknown GPU, using 0 for raster_config\n");
+   raster_config = 0x;
+   raster_config_1 = 0x;
+   break;
+   }
+   *raster_config_p = raster_config;
+   *raster_config_1_p = raster_config_1;
+}
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 003d340e0c..9227ff3779 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -131,7 +131,9 @@ void ac_compute_driver_uuid(char *uuid, size_t size);
 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 void ac_print_gpu_info(struct radeon_info *info);
 int ac_get_gs_table_depth(enum ch

Mesa (master): radeonsi: use common gs_table_depth code

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 8de7ff91bec8fb848512185885b9c9a2283c1a8a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8de7ff91bec8fb848512185885b9c9a2283c1a8a

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 09:57:20 2018 +1000

radeonsi: use common gs_table_depth code

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/gallium/drivers/radeonsi/si_pipe.c | 33 ++---
 1 file changed, 2 insertions(+), 31 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index b3ef098b8e..327dd7c424 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -661,37 +661,8 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
 
 static void si_init_gs_info(struct si_screen *sscreen)
 {
-   /* gs_table_depth is not used by GFX9 */
-   if (sscreen->info.chip_class >= GFX9)
-   return;
-
-   switch (sscreen->info.family) {
-   case CHIP_OLAND:
-   case CHIP_HAINAN:
-   case CHIP_KAVERI:
-   case CHIP_KABINI:
-   case CHIP_MULLINS:
-   case CHIP_ICELAND:
-   case CHIP_CARRIZO:
-   case CHIP_STONEY:
-   sscreen->gs_table_depth = 16;
-   return;
-   case CHIP_TAHITI:
-   case CHIP_PITCAIRN:
-   case CHIP_VERDE:
-   case CHIP_BONAIRE:
-   case CHIP_HAWAII:
-   case CHIP_TONGA:
-   case CHIP_FIJI:
-   case CHIP_POLARIS10:
-   case CHIP_POLARIS11:
-   case CHIP_POLARIS12:
-   case CHIP_VEGAM:
-   sscreen->gs_table_depth = 32;
-   return;
-   default:
-   unreachable("unknown GPU");
-   }
+   sscreen->gs_table_depth = 
ac_get_gs_table_depth(sscreen->info.chip_class,
+   sscreen->info.family);
 }
 
 static void si_handle_env_var_force_family(struct si_screen *sscreen)

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Mesa (master): radv: use common gs_table_depth code.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9afe9c0fe2702f6555dbb39e2667e98e3ce2c42d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9afe9c0fe2702f6555dbb39e2667e98e3ce2c42d

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 09:57:10 2018 +1000

radv: use common gs_table_depth code.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_device.c | 32 ++--
 1 file changed, 2 insertions(+), 30 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index bc6cdc7945..629957afec 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1353,36 +1353,8 @@ static void radv_bo_list_remove(struct radv_device 
*device,
 static void
 radv_device_init_gs_info(struct radv_device *device)
 {
-   if (device->physical_device->rad_info.chip_class >= GFX9)
-   return;
-
-   switch (device->physical_device->rad_info.family) {
-   case CHIP_OLAND:
-   case CHIP_HAINAN:
-   case CHIP_KAVERI:
-   case CHIP_KABINI:
-   case CHIP_MULLINS:
-   case CHIP_ICELAND:
-   case CHIP_CARRIZO:
-   case CHIP_STONEY:
-   device->gs_table_depth = 16;
-   return;
-   case CHIP_TAHITI:
-   case CHIP_PITCAIRN:
-   case CHIP_VERDE:
-   case CHIP_BONAIRE:
-   case CHIP_HAWAII:
-   case CHIP_TONGA:
-   case CHIP_FIJI:
-   case CHIP_POLARIS10:
-   case CHIP_POLARIS11:
-   case CHIP_POLARIS12:
-   case CHIP_VEGAM:
-   device->gs_table_depth = 32;
-   return;
-   default:
-   unreachable("unknown GPU");
-   }
+   device->gs_table_depth = 
ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
+  
device->physical_device->rad_info.family);
 }
 
 static int radv_get_device_extension_index(const char *name)

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Mesa (master): ac/radv/radeonsi: refactor max simd waves into common code.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f77caa741135e0dbdcbbf9e619195f47c2c591b2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f77caa741135e0dbdcbbf9e619195f47c2c591b2

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 10:16:07 2018 +1000

ac/radv/radeonsi: refactor max simd waves into common code.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_gpu_info.h | 16 
 src/amd/vulkan/radv_shader.c | 12 +---
 src/gallium/drivers/radeonsi/si_shader.c | 12 +---
 3 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9227ff3779..de566c62fa 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -134,6 +134,22 @@ int ac_get_gs_table_depth(enum chip_class chip_class, enum 
radeon_family family)
 void ac_get_raster_config(struct radeon_info *info,
  uint32_t *raster_config_p,
  uint32_t *raster_config_1_p);
+
+static inline unsigned ac_get_max_simd_waves(enum radeon_family family)
+{
+
+   switch (family) {
+   /* These always have 8 waves: */
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   case CHIP_VEGAM:
+   return 8;
+   default:
+   return 10;
+   }
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 8e8a32f025..aaa6702975 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -615,17 +615,7 @@ generate_shader_stats(struct radv_device *device,
unsigned max_simd_waves;
unsigned lds_per_wave = 0;
 
-   switch (device->physical_device->rad_info.family) {
-   /* These always have 8 waves: */
-   case CHIP_POLARIS10:
-   case CHIP_POLARIS11:
-   case CHIP_POLARIS12:
-   case CHIP_VEGAM:
-   max_simd_waves = 8;
-   break;
-   default:
-   max_simd_waves = 10;
-   }
+   max_simd_waves = 
ac_get_max_simd_waves(device->physical_device->rad_info.family);
 
conf = >config;
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 4eff4f57b9..b866f14623 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5459,17 +5459,7 @@ static void si_calculate_max_simd_waves(struct si_shader 
*shader)
unsigned lds_per_wave = 0;
unsigned max_simd_waves;
 
-   switch (sscreen->info.family) {
-   /* These always have 8 waves: */
-   case CHIP_POLARIS10:
-   case CHIP_POLARIS11:
-   case CHIP_POLARIS12:
-   case CHIP_VEGAM:
-   max_simd_waves = 8;
-   break;
-   default:
-   max_simd_waves = 10;
-   }
+   max_simd_waves = ac_get_max_simd_waves(sscreen->info.family);
 
/* Compute LDS usage for PS. */
switch (shader->selector->type) {

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Mesa (master): ac/info: move gs table depth to common code.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 5e2ef28390bdb6fdaff885f147c9b29686fa6a46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e2ef28390bdb6fdaff885f147c9b29686fa6a46

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 09:56:43 2018 +1000

ac/info: move gs table depth to common code.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_gpu_info.c | 33 +
 src/amd/common/ac_gpu_info.h |  1 +
 2 files changed, 34 insertions(+)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ef0364b053..12b03c4ea2 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -521,3 +521,36 @@ void ac_print_gpu_info(struct radeon_info *info)
   G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
}
 }
+
+int
+ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
+{
+   if (chip_class >= GFX9)
+   return -1;
+
+   switch (family) {
+   case CHIP_OLAND:
+   case CHIP_HAINAN:
+   case CHIP_KAVERI:
+   case CHIP_KABINI:
+   case CHIP_MULLINS:
+   case CHIP_ICELAND:
+   case CHIP_CARRIZO:
+   case CHIP_STONEY:
+   return 16;
+   case CHIP_TAHITI:
+   case CHIP_PITCAIRN:
+   case CHIP_VERDE:
+   case CHIP_BONAIRE:
+   case CHIP_HAWAII:
+   case CHIP_TONGA:
+   case CHIP_FIJI:
+   case CHIP_POLARIS10:
+   case CHIP_POLARIS11:
+   case CHIP_POLARIS12:
+   case CHIP_VEGAM:
+   return 32;
+   default:
+   unreachable("Unknown GPU");
+   }
+}
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 75cb98020d..003d340e0c 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -130,6 +130,7 @@ void ac_compute_driver_uuid(char *uuid, size_t size);
 
 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size);
 void ac_print_gpu_info(struct radeon_info *info);
+int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family 
family);
 
 #ifdef __cplusplus
 }

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Mesa (master): ac/radv/radeonsi: refactor harvest config register getters.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: a90c9f33cf5c8f7674de989b2c9146466e871459
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a90c9f33cf5c8f7674de989b2c9146466e871459

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 10:42:21 2018 +1000

ac/radv/radeonsi: refactor harvest config register getters.

This refactors the code out to share it between radv and radeonsi.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Acked-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_gpu_info.c| 113 
 src/amd/common/ac_gpu_info.h|   4 ++
 src/amd/vulkan/si_cmd_buffer.c  | 108 ++
 src/gallium/drivers/radeonsi/si_state.c | 111 ++-
 4 files changed, 130 insertions(+), 206 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 47a87650a6..031fd183b6 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -647,3 +647,116 @@ ac_get_raster_config(struct radeon_info *info,
*raster_config_p = raster_config;
*raster_config_1_p = raster_config_1;
 }
+
+void
+ac_get_harvested_configs(struct radeon_info *info,
+unsigned raster_config,
+unsigned *cik_raster_config_1_p,
+unsigned *raster_config_se)
+{
+   unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
+   unsigned num_se = MAX2(info->max_se, 1);
+   unsigned rb_mask = info->enabled_rb_mask;
+   unsigned num_rb = MIN2(info->num_render_backends, 16);
+   unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
+   unsigned rb_per_se = num_rb / num_se;
+   unsigned se_mask[4];
+   unsigned se;
+
+   se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
+   se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
+   se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
+   se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
+
+   assert(num_se == 1 || num_se == 2 || num_se == 4);
+   assert(sh_per_se == 1 || sh_per_se == 2);
+   assert(rb_per_pkr == 1 || rb_per_pkr == 2);
+
+
+   if (info->chip_class >= CIK) {
+   unsigned raster_config_1 = *cik_raster_config_1_p;
+   if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+(!se_mask[2] && !se_mask[3]))) {
+   raster_config_1 &= C_028354_SE_PAIR_MAP;
+
+   if (!se_mask[0] && !se_mask[1]) {
+   raster_config_1 |=
+   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
+   } else {
+   raster_config_1 |=
+   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
+   }
+   *cik_raster_config_1_p = raster_config_1;
+   }
+   }
+
+   for (se = 0; se < num_se; se++) {
+   unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * 
rb_per_se);
+   unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
+   int idx = (se / 2) * 2;
+
+   raster_config_se[se] = raster_config;
+   if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
+   raster_config_se[se] &= C_028350_SE_MAP;
+
+   if (!se_mask[idx]) {
+   raster_config_se[se] |=
+   
S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
+   } else {
+   raster_config_se[se] |=
+   
S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
+   }
+   }
+
+   pkr0_mask &= rb_mask;
+   pkr1_mask &= rb_mask;
+   if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
+   raster_config_se[se] &= C_028350_PKR_MAP;
+
+   if (!pkr0_mask) {
+   raster_config_se[se] |=
+   
S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
+   } else {
+   raster_config_se[se] |=
+   
S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
+   }
+   }
+
+   if (rb_per_se >= 2) {
+   unsigned rb0_mask = 1 << (se * rb_per_se);
+   unsigned rb1_mask = rb0_mask << 1;
+
+   rb0_mask &= rb_mask;
+   r

Mesa (master): radeonsi: don't runtime check gs table info

[Dave Airlie]

Module: Mesa
Branch: master
Commit: b25f6cde89c21b19f4582f19630f6d7e96a04913
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b25f6cde89c21b19f4582f19630f6d7e96a04913

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 09:52:28 2018 +1000

radeonsi: don't runtime check gs table info

We can just unreachable here, this aligns with radv code, makes
it easier to move to common code.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/gallium/drivers/radeonsi/si_pipe.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index f2fdb98413..b3ef098b8e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -659,11 +659,11 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
FREE(sscreen);
 }
 
-static bool si_init_gs_info(struct si_screen *sscreen)
+static void si_init_gs_info(struct si_screen *sscreen)
 {
/* gs_table_depth is not used by GFX9 */
if (sscreen->info.chip_class >= GFX9)
-   return true;
+   return;
 
switch (sscreen->info.family) {
case CHIP_OLAND:
@@ -675,7 +675,7 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_CARRIZO:
case CHIP_STONEY:
sscreen->gs_table_depth = 16;
-   return true;
+   return;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
@@ -688,9 +688,9 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_POLARIS12:
case CHIP_VEGAM:
sscreen->gs_table_depth = 32;
-   return true;
+   return;
default:
-   return false;
+   unreachable("unknown GPU");
}
 }
 
@@ -853,8 +853,8 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
(void) mtx_init(>aux_context_lock, mtx_plain);
(void) mtx_init(>gpu_load_mutex, mtx_plain);
 
-   if (!si_init_gs_info(sscreen) ||
-   !si_init_shader_cache(sscreen)) {
+   si_init_gs_info(sscreen);
+   if (!si_init_shader_cache(sscreen)) {
FREE(sscreen);
return NULL;
}

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Mesa (master): radv/gfx9: don't use gs_table_depth on gfx9.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 40783a7fa372ef12184d893efaed27f2c3cebbbc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40783a7fa372ef12184d893efaed27f2c3cebbbc

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 09:50:28 2018 +1000

radv/gfx9: don't use gs_table_depth on gfx9.

Missed this on initial radeonsi port, we shouldn't use this value
on gfx9, but also in gfx8 only for when we have a geom shader.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_device.c   | 6 +++---
 src/amd/vulkan/radv_pipeline.c | 5 +++--
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 25c0d47da8..bc6cdc7945 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1353,6 +1353,9 @@ static void radv_bo_list_remove(struct radv_device 
*device,
 static void
 radv_device_init_gs_info(struct radv_device *device)
 {
+   if (device->physical_device->rad_info.chip_class >= GFX9)
+   return;
+
switch (device->physical_device->rad_info.family) {
case CHIP_OLAND:
case CHIP_HAINAN:
@@ -1375,9 +1378,6 @@ radv_device_init_gs_info(struct radv_device *device)
case CHIP_POLARIS11:
case CHIP_POLARIS12:
case CHIP_VEGAM:
-   case CHIP_VEGA10:
-   case CHIP_VEGA12:
-   case CHIP_RAVEN:
device->gs_table_depth = 32;
return;
default:
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 20afeda448..b4e4f3211e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3206,8 +3206,9 @@ radv_compute_ia_multi_vgt_param_helpers(struct 
radv_pipeline *pipeline,
}
}
/* GS requirement. */
-   if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= 
pipeline->device->gs_table_depth - 3)
-   ia_multi_vgt_param.partial_es_wave = true;
+   if (radv_pipeline_has_gs(pipeline) && 
device->physical_device->rad_info.chip_class <= VI)
+   if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= 
pipeline->device->gs_table_depth - 3)
+   ia_multi_vgt_param.partial_es_wave = true;
 
ia_multi_vgt_param.wd_switch_on_eop = false;
if (device->physical_device->rad_info.chip_class >= CIK) {

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Mesa (master): radv: only set raster_config_1 outside the index registers.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 8e4d54505ab2fa8b47d3df27a69449d4913e1d36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e4d54505ab2fa8b47d3df27a69449d4913e1d36

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Apr 23 10:39:33 2018 +1000

radv: only set raster_config_1 outside the index registers.

This follows what radeonsi does.

Ported from radeonsi:
radeonsi: emit PA_SC_RASTER_CONFIG_1 only once

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/si_cmd_buffer.c | 31 ---
 1 file changed, 16 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index b7a2ca244b..2140368c80 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -63,19 +63,6 @@ si_write_harvested_raster_configs(struct 
radv_physical_device *physical_device,
 * fields are for, so I'm leaving them as their default
 * values. */
 
-   if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
-(!se_mask[2] && !se_mask[3]))) {
-   raster_config_1 &= C_028354_SE_PAIR_MAP;
-
-   if (!se_mask[0] && !se_mask[1]) {
-   raster_config_1 |=
-   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
-   } else {
-   raster_config_1 |=
-   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
-   }
-   }
-
for (se = 0; se < num_se; se++) {
unsigned raster_config_se = raster_config;
unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * 
rb_per_se);
@@ -156,8 +143,6 @@ si_write_harvested_raster_configs(struct 
radv_physical_device *physical_device,
   S_030800_SE_INDEX(se) | 
S_030800_SH_BROADCAST_WRITES(1) |
   
S_030800_INSTANCE_BROADCAST_WRITES(1));
radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, 
raster_config_se);
-   if (physical_device->rad_info.chip_class >= CIK)
-   radeon_set_context_reg(cs, 
R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
}
 
/* GRBM_GFX_INDEX has a different offset on SI and CI+ */
@@ -170,6 +155,22 @@ si_write_harvested_raster_configs(struct 
radv_physical_device *physical_device,
radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX,
   S_030800_SE_BROADCAST_WRITES(1) | 
S_030800_SH_BROADCAST_WRITES(1) |
   S_030800_INSTANCE_BROADCAST_WRITES(1));
+
+   if (physical_device->rad_info.chip_class >= CIK) {
+   if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
+(!se_mask[2] && !se_mask[3]))) {
+   raster_config_1 &= C_028354_SE_PAIR_MAP;
+
+   if (!se_mask[0] && !se_mask[1]) {
+   raster_config_1 |=
+   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
+   } else {
+   raster_config_1 |=
+   
S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
+   }
+   }
+   radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, 
raster_config_1);
+   }
 }
 
 static void

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Mesa (master): virgl: disable virgl when no 3D for virtio gpu.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6c5abb68c79d4acf71112b5ba4924a5af2d1e5c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c5abb68c79d4acf71112b5ba4924a5af2d1e5c9

Author: Lepton Wu <lep...@chromium.org>
Date:   Thu Apr  5 12:38:48 2018 -0700

virgl: disable virgl when no 3D for virtio gpu.

If users are running mesa under old version of qemu or have turned off
GL at runtime, virtio gpu driver actually doesn't work. Adds a detection
here so mesa can fall back to software rendering.

v2:
 - move detection from loader to virgl (Ilia, Emil)

Signed-off-by: Lepton Wu <lep...@chromium.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c 
b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index cf3c3bac4b..4198ed7feb 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -800,8 +800,15 @@ virgl_drm_winsys_create(int drmFD)
 {
struct virgl_drm_winsys *qdws;
int ret;
+   int gl = 0;
struct drm_virtgpu_getparam getparam = {0};
 
+   getparam.param = VIRTGPU_PARAM_3D_FEATURES;
+   getparam.value = (uint64_t)(uintptr_t)
+   ret = drmIoctl(drmFD, DRM_IOCTL_VIRTGPU_GETPARAM, );
+   if (ret < 0 || !gl)
+  return NULL;
+
qdws = CALLOC_STRUCT(virgl_drm_winsys);
if (!qdws)
   return NULL;
@@ -914,6 +921,10 @@ virgl_drm_screen_create(int fd)
   int dup_fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 
   vws = virgl_drm_winsys_create(dup_fd);
+  if (!vws) {
+ close(dup_fd);
+ goto unlock;
+  }
 
   pscreen = virgl_create_screen(vws);
   if (pscreen) {

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Mesa (master): radv: mark const structs as extern in header file to avoid lto damage

[Dave Airlie]

Module: Mesa
Branch: master
Commit: a8420e253038fd4ef063af4ee370038075ee7aeb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8420e253038fd4ef063af4ee370038075ee7aeb

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri Apr 13 12:40:55 2018 +1000

radv: mark const structs as extern in header file to avoid lto damage

The copr repo from che was using LTO and he reported radv broke
recently with it. When testing with lto builds here I noticed
that we weren't seeing any instance extensions reported.

It appears LTO was treating the const without extern as an empty
struct, this is possibly a gcc bug, but we can work around it
just by marking these with extern.

Acked-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_extensions.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index dbe0ff4ac5..ec34551696 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -195,9 +195,9 @@ struct radv_device_extension_table {
};
 };
 
-const VkExtensionProperties 
radv_instance_extensions[RADV_INSTANCE_EXTENSION_COUNT];
-const VkExtensionProperties 
radv_device_extensions[RADV_DEVICE_EXTENSION_COUNT];
-const struct radv_instance_extension_table radv_supported_instance_extensions;
+extern const VkExtensionProperties 
radv_instance_extensions[RADV_INSTANCE_EXTENSION_COUNT];
+extern const VkExtensionProperties 
radv_device_extensions[RADV_DEVICE_EXTENSION_COUNT];
+extern const struct radv_instance_extension_table 
radv_supported_instance_extensions;
 
 
 struct radv_physical_device;

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Mesa (master): virgl: add ARB_cull_distance support.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: fa683385de515c24f4c7cf62dfce8a16faa4b2be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa683385de515c24f4c7cf62dfce8a16faa4b2be

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Mar 13 15:37:36 2018 +1000

virgl: add ARB_cull_distance support.

This just allows the properties through to the host if we have
cull dist support.

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_context.c |  2 +-
 src/gallium/drivers/virgl/virgl_context.h |  2 +-
 src/gallium/drivers/virgl/virgl_screen.c  |  3 ++-
 src/gallium/drivers/virgl/virgl_tgsi.c| 11 +--
 4 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_context.c 
b/src/gallium/drivers/virgl/virgl_context.c
index f1b6ef4501..8d701bb8f4 100644
--- a/src/gallium/drivers/virgl/virgl_context.c
+++ b/src/gallium/drivers/virgl/virgl_context.c
@@ -469,7 +469,7 @@ static void *virgl_shader_encoder(struct pipe_context *ctx,
struct tgsi_token *new_tokens;
int ret;
 
-   new_tokens = virgl_tgsi_transform(shader->tokens);
+   new_tokens = virgl_tgsi_transform(vctx, shader->tokens);
if (!new_tokens)
   return NULL;
 
diff --git a/src/gallium/drivers/virgl/virgl_context.h 
b/src/gallium/drivers/virgl/virgl_context.h
index d8d4ccbb39..3492dcfa49 100644
--- a/src/gallium/drivers/virgl/virgl_context.h
+++ b/src/gallium/drivers/virgl/virgl_context.h
@@ -109,6 +109,6 @@ void virgl_transfer_inline_write(struct pipe_context *ctx,
 unsigned stride,
 unsigned layer_stride);
 
-struct tgsi_token *virgl_tgsi_transform(const struct tgsi_token *tokens_in);
+struct tgsi_token *virgl_tgsi_transform(struct virgl_context *vctx, const 
struct tgsi_token *tokens_in);
 
 #endif
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 1878def474..02613f1866 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -196,6 +196,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
   return vscreen->caps.caps.v1.bset.has_sample_shading;
+   case PIPE_CAP_CULL_DISTANCE:
+  return vscreen->caps.caps.v1.bset.has_cull;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_FAKE_SW_MSAA:
@@ -239,7 +241,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_PCI_FUNCTION:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
-   case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
case PIPE_CAP_TGSI_VOTE:
case PIPE_CAP_MAX_WINDOW_RECTANGLES:
diff --git a/src/gallium/drivers/virgl/virgl_tgsi.c 
b/src/gallium/drivers/virgl/virgl_tgsi.c
index ca0591322d..ff5abf6ddb 100644
--- a/src/gallium/drivers/virgl/virgl_tgsi.c
+++ b/src/gallium/drivers/virgl/virgl_tgsi.c
@@ -27,8 +27,10 @@
 */
 #include "tgsi/tgsi_transform.h"
 #include "virgl_context.h"
+#include "virgl_screen.h"
 struct virgl_transform_context {
struct tgsi_transform_context base;
+   bool cull_enabled;
 };
 
 static void
@@ -55,9 +57,13 @@ static void
 virgl_tgsi_transform_property(struct tgsi_transform_context *ctx,
   struct tgsi_full_property *prop)
 {
+   struct virgl_transform_context *vtctx = (struct virgl_transform_context 
*)ctx;
switch (prop->Property.PropertyName) {
case TGSI_PROPERTY_NUM_CLIPDIST_ENABLED:
case TGSI_PROPERTY_NUM_CULLDIST_ENABLED:
+  if (vtctx->cull_enabled)
+ctx->emit_property(ctx, prop);
+  break;
case TGSI_PROPERTY_NEXT_SHADER:
   break;
default:
@@ -82,9 +88,9 @@ virgl_tgsi_transform_instruction(struct 
tgsi_transform_context *ctx,
ctx->emit_instruction(ctx, inst);
 }
 
-struct tgsi_token *virgl_tgsi_transform(const struct tgsi_token *tokens_in)
+struct tgsi_token *virgl_tgsi_transform(struct virgl_context *vctx, const 
struct tgsi_token *tokens_in)
 {
-
+   struct virgl_screen *vscreen = (struct virgl_screen *)vctx->base.screen;
struct virgl_transform_context transform;
const uint newLen = tgsi_num_tokens(tokens_in);
struct tgsi_token *new_tokens;
@@ -97,6 +103,7 @@ struct tgsi_token *virgl_tgsi_transform(const struct 
tgsi_token *tokens_in)
transform.base.transform_declaration = virgl_tgsi_transform_declaration;
transform.base.transform_property = virgl_tgsi_transform_property;
transform.base.transform_instruction = virgl_tgsi_transform_instruction;
+   transform.cull_enabled = vscreen->caps.caps.v1.bset.has_cull;
tgsi_transform_shader(tokens_in, new_tokens, newLen, );
 
return new_tokens;

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Mesa (master): virgl: Implement seamless cube maps

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 1117edc60dd2746819d1d4e3bfd809ec3a4f5902
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1117edc60dd2746819d1d4e3bfd809ec3a4f5902

Author: Stéphane Marchesin <marc...@chromium.org>
Date:   Fri Mar 16 19:15:02 2018 -0700

virgl: Implement seamless cube maps

This was previously ignored.

Along with the virglrenderer patch, this fixes ~100 dEQP tests:
dEQP-GLES3.functional.texture.filtering.cube.*

Signed-off-by: Stéphane Marchesin <marc...@chromium.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_encode.c   | 3 ++-
 src/gallium/drivers/virgl/virgl_protocol.h | 1 +
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 80e60bc284..a6f6d13f85 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -566,7 +566,8 @@ int virgl_encode_sampler_state(struct virgl_context *ctx,
   VIRGL_OBJ_SAMPLE_STATE_S0_MIN_MIP_FILTER(state->min_mip_filter) |
   VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(state->mag_img_filter) |
   VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(state->compare_mode) |
-  VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func);
+  VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(state->compare_func) |
+  VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(state->seamless_cube_map);
 
virgl_encoder_write_dword(ctx->cbuf, tmp);
virgl_encoder_write_dword(ctx->cbuf, fui(state->lod_bias));
diff --git a/src/gallium/drivers/virgl/virgl_protocol.h 
b/src/gallium/drivers/virgl/virgl_protocol.h
index 7688ac5e8e..5dc2874d1d 100644
--- a/src/gallium/drivers/virgl/virgl_protocol.h
+++ b/src/gallium/drivers/virgl/virgl_protocol.h
@@ -330,6 +330,7 @@ enum virgl_context_cmd {
 #define VIRGL_OBJ_SAMPLE_STATE_S0_MAG_IMG_FILTER(x) (((x) & 0x3) << 13)
 #define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_MODE(x) (((x) & 0x1) << 15)
 #define VIRGL_OBJ_SAMPLE_STATE_S0_COMPARE_FUNC(x) (((x) & 0x7) << 16)
+#define VIRGL_OBJ_SAMPLE_STATE_S0_SEAMLESS_CUBE_MAP(x) (((x) & 0x1) << 19)
 
 #define VIRGL_OBJ_SAMPLER_STATE_LOD_BIAS 3
 #define VIRGL_OBJ_SAMPLER_STATE_MIN_LOD 4

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Mesa (master): radv: don't export NULL layer.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 32791a05024d54736eab21379e849480fea78559
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32791a05024d54736eab21379e849480fea78559

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 20:02:58 2018 +

radv: don't export NULL layer.

We have some cases where in subpass we want the layer but having
it be 0 and loaded in the frag shader without the vertex shader
exporting it is fine.

So don't export the layer if we don't have a value to put in it.

Fixes: d4c74aed7a8 (radv/multiview: mark layer_input if we have input 
attachments.)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 7379f348d8..ad046adfdb 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2363,7 +2363,7 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
outinfo->export_prim_id = true;
}
 
-   if (export_layer_id) {
+   if (export_layer_id && layer_value) {
LLVMValueRef values[4];
 
values[0] = layer_value;

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Mesa (master): radv/multiview: mark layer_input if we have input attachments.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: d4c74aed7a81c65ef91d4d3065b3f822355746e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4c74aed7a81c65ef91d4d3065b3f822355746e7

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 03:41:18 2018 +

radv/multiview: mark layer_input if we have input attachments.

This fixes:
dEQP-VK.multiview.input_attachments*

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_shader_info.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 7208bd2f58..9c18791524 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -122,8 +122,10 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
 
enum glsl_sampler_dim dim = glsl_get_sampler_dim(type);
if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
-   dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
+   dim == GLSL_SAMPLER_DIM_SUBPASS_MS) {
+   info->ps.layer_input = true;
info->ps.uses_input_attachments = true;
+   }
mark_sampler_desc(instr->variables[0]->var, info);
 
if (nir_intrinsic_image_store ||

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Mesa (master): radv/query: handle multiview queries properly. (v3)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 32b4f3c38dc25694437af6f017b45b9658eac3bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32b4f3c38dc25694437af6f017b45b9658eac3bc

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar 15 20:23:30 2018 +

radv/query: handle multiview queries properly. (v3)

For multiview we need to emit a number of sequential queries
depending on the view mask.

This avoids dEQP-VK.multiview.queries.15 waiting forever
on the CPU for query results that are never coming.

We only really want to emit one query,
and the rest should be blank (amdvlk does the same),
so we emit begin/end pairs for all the others except
the first query.

v2: fix tests
v3: split out patch.

Fixes: dEQP-VK.multiview.queries*
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_query.c | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 5fae8b6565..7a20314f61 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1178,6 +1178,25 @@ void radv_CmdBeginQuery(
va += pool->stride * query;
 
emit_begin_query(cmd_buffer, va, pool->type);
+
+   /*
+* For multiview we have to emit a query for each bit in the mask,
+* however the first query we emit will get the totals for all the
+* operations, so we don't want to get a real value in the other
+* queries. This emits a fake begin/end sequence so the waiting
+* code gets a completed query value and doesn't hang, but the
+* query returns 0.
+*/
+   if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
+   uint64_t avail_va = va + pool->availability_offset + 4 * query;
+
+   for (unsigned i = 0; i < 
util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
+   va += pool->stride;
+   avail_va += 4;
+   emit_begin_query(cmd_buffer, va, pool->type);
+   emit_end_query(cmd_buffer, va, avail_va, pool->type);
+   }
+   }
 }
 
 

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Mesa (master): radv: lower constant initializers on output variables earlier

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e8d9b7ab02fc56cadffc7a2bb993b39cccde2b66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8d9b7ab02fc56cadffc7a2bb993b39cccde2b66

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 04:27:49 2018 +

radv: lower constant initializers on output variables earlier

If a shader only writes to an output via a constant initializer we
need to lower it before we call nir_remove_dead_variables so that
this pass sees the stores from the initializer and doesn't kill the
output.

Fixes test failures in new work-in-progress CTS tests:
dEQP-VK.spirv_assembly.instruction.graphics.variable_init.output.float

This is ported from anv:
99b57daf4a anv/pipeline: lower constant initializers on output variables earlier
from Iago Toral Quiroga <ito...@igalia.com>

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_shader.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 180b427a44..ac577c36e9 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -244,6 +244,11 @@ radv_shader_compile_to_nir(struct radv_device *device,
assert(exec_list_length(>functions) == 1);
entry_point->name = ralloc_strdup(entry_point, "main");
 
+   /* Make sure we lower constant initializers on output variables 
so that
+* nir_remove_dead_variables below sees the corresponding stores
+*/
+   NIR_PASS_V(nir, nir_lower_constant_initializers, 
nir_var_shader_out);
+
NIR_PASS_V(nir, nir_remove_dead_variables,
   nir_var_shader_in | nir_var_shader_out | 
nir_var_system_value);
 

___
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Mesa (master): radv/query: split out begin/end query emission

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 4034dc5c72791e010eb64dece4bca542f56cec09
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4034dc5c72791e010eb64dece4bca542f56cec09

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 01:24:52 2018 +

radv/query: split out begin/end query emission

This just splits out the begin/end query hw emissions,
it makes it easier to add multiview support for queries.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_query.c | 98 ++---
 1 file changed, 57 insertions(+), 41 deletions(-)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 9fee4d2b49..5fae8b6565 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1077,33 +1077,12 @@ void radv_CmdResetQueryPool(
}
 }
 
-void radv_CmdBeginQuery(
-VkCommandBuffer commandBuffer,
-VkQueryPool queryPool,
-uint32_tquery,
-VkQueryControlFlags flags)
+static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
+uint64_t va,
+VkQueryType query_type)
 {
-   RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
struct radeon_winsys_cs *cs = cmd_buffer->cs;
-   uint64_t va = radv_buffer_get_va(pool->bo);
-   va += pool->stride * query;
-
-   radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
-
-   if (cmd_buffer->pending_reset_query) {
-   if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
-   /* Only need to flush caches if the query pool size is
-* large enough to be resetted using the compute shader
-* path. Small pools don't need any cache flushes
-* because we use a CP dma clear.
-*/
-   si_emit_cache_flush(cmd_buffer);
-   cmd_buffer->pending_reset_query = false;
-   }
-   }
-
-   switch (pool->type) {
+   switch (query_type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 7);
 
@@ -1127,26 +1106,15 @@ void radv_CmdBeginQuery(
default:
unreachable("beginning unhandled query type");
}
-}
 
+}
 
-void radv_CmdEndQuery(
-VkCommandBuffer commandBuffer,
-VkQueryPool queryPool,
-uint32_tquery)
+static void emit_end_query(struct radv_cmd_buffer *cmd_buffer,
+  uint64_t va, uint64_t avail_va,
+  VkQueryType query_type)
 {
-   RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
-   RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
struct radeon_winsys_cs *cs = cmd_buffer->cs;
-   uint64_t va = radv_buffer_get_va(pool->bo);
-   uint64_t avail_va = va + pool->availability_offset + 4 * query;
-   va += pool->stride * query;
-
-   /* Do not need to add the pool BO to the list because the query must
-* currently be active, which means the BO is already in the list.
-*/
-
-   switch (pool->type) {
+   switch (query_type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 14);
 
@@ -1182,6 +1150,54 @@ void radv_CmdEndQuery(
}
 }
 
+void radv_CmdBeginQuery(
+VkCommandBuffer commandBuffer,
+VkQueryPool queryPool,
+uint32_tquery,
+VkQueryControlFlags flags)
+{
+   RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
+   RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
+   struct radeon_winsys_cs *cs = cmd_buffer->cs;
+   uint64_t va = radv_buffer_get_va(pool->bo);
+
+   radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
+
+   if (cmd_buffer->pending_reset_query) {
+   if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
+   /* Only need to flush caches if the query pool size is
+* large enough to be resetted using the compute shader
+* path. Small pools don't need any cache flushes
+* because we use a CP dma clear.
+*/
+   si_emit_cache_flush(cmd_buffer);
+   cmd_buffer->pending_reset_query = false;
+   }
+   }
+
+   va += pool->stride * query;
+
+   emit_begin_query(cmd_buffer

Mesa (master): radv/query: handle multiview timestamp queries.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 032014ac01a2dfd6c8e689b3d59989eb6fa2396b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=032014ac01a2dfd6c8e689b3d59989eb6fa2396b

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 19 01:27:37 2018 +

radv/query: handle multiview timestamp queries.

For each view bit we need to emit a timestamp query.

Fixes: dEQP-VK.multiview.queries*

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/vulkan/radv_query.c | 79 -
 1 file changed, 43 insertions(+), 36 deletions(-)

diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 7a20314f61..cc943d5de0 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1233,42 +1233,49 @@ void radv_CmdWriteTimestamp(
 
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 5);
 
-   MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cs, 28);
-
-   switch(pipelineStage) {
-   case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
-   radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
-   radeon_emit(cs, COPY_DATA_COUNT_SEL | COPY_DATA_WR_CONFIRM |
-   COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
-   COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
-   radeon_emit(cs, 0);
-   radeon_emit(cs, 0);
-   radeon_emit(cs, query_va);
-   radeon_emit(cs, query_va >> 32);
-
-   radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
-   radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
-   S_370_WR_CONFIRM(1) |
-   S_370_ENGINE_SEL(V_370_ME));
-   radeon_emit(cs, avail_va);
-   radeon_emit(cs, avail_va >> 32);
-   radeon_emit(cs, 1);
-   break;
-   default:
-   si_cs_emit_write_event_eop(cs,
-  false,
-  
cmd_buffer->device->physical_device->rad_info.chip_class,
-  mec,
-  V_028A90_BOTTOM_OF_PIPE_TS, 0,
-  3, query_va, 0, 0);
-   si_cs_emit_write_event_eop(cs,
-  false,
-  
cmd_buffer->device->physical_device->rad_info.chip_class,
-  mec,
-  V_028A90_BOTTOM_OF_PIPE_TS, 0,
-  1, avail_va, 0, 1);
-   break;
-   }
+   int num_queries = 1;
+   if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask)
+   num_queries = 
util_bitcount(cmd_buffer->state.subpass->view_mask);
 
+   MAYBE_UNUSED unsigned cdw_max = 
radeon_check_space(cmd_buffer->device->ws, cs, 28 * num_queries);
+
+   for (unsigned i = 0; i < num_queries; i++) {
+   switch(pipelineStage) {
+   case VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT:
+   radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
+   radeon_emit(cs, COPY_DATA_COUNT_SEL | 
COPY_DATA_WR_CONFIRM |
+   COPY_DATA_SRC_SEL(COPY_DATA_TIMESTAMP) |
+   COPY_DATA_DST_SEL(V_370_MEM_ASYNC));
+   radeon_emit(cs, 0);
+   radeon_emit(cs, 0);
+   radeon_emit(cs, query_va);
+   radeon_emit(cs, query_va >> 32);
+
+   radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
+   radeon_emit(cs, S_370_DST_SEL(V_370_MEM_ASYNC) |
+   S_370_WR_CONFIRM(1) |
+   S_370_ENGINE_SEL(V_370_ME));
+   radeon_emit(cs, avail_va);
+   radeon_emit(cs, avail_va >> 32);
+   radeon_emit(cs, 1);
+   break;
+   default:
+   si_cs_emit_write_event_eop(cs,
+  false,
+  
cmd_buffer->device->physical_device->rad_info.chip_class,
+  mec,
+  V_028A90_BOTTOM_OF_PIPE_TS, 
0,
+  3, query_va, 0, 0);
+   si_cs_emit_write_event_eop(cs,
+  false,
+  
cmd_buffer->device->physical_device->rad_info.chip_class,
+ 

Mesa (master): radv: handle exporting view index to fragment shader. (v1.1)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 8f052a3e257a61240cb311032497d016278117a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f052a3e257a61240cb311032497d016278117a8

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri Mar 16 05:57:11 2018 +

radv: handle exporting view index to fragment shader. (v1.1)

The fragment shader was trying to read this, but nothing
was exporting it from the vertex shader. This handles
it like the prim id export.

Fixes:
dEQP-VK.multiview.secondary_cmd_buffer.*
dEQP-VK.multiview.index.fragment_shader.*

v1.1: updated to use 0x1 (Samuel)

Fixes: e3265c10c89 (radv: Implement multiview draws.)
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 18 --
 src/amd/vulkan/radv_pipeline.c|  4 
 src/amd/vulkan/radv_shader.h  |  2 ++
 src/amd/vulkan/radv_shader_info.c |  2 ++
 4 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index cedcd38b3a..7379f348d8 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2183,7 +2183,7 @@ radv_load_output(struct radv_shader_context *ctx, 
unsigned index, unsigned chan)
 
 static void
 handle_vs_outputs_post(struct radv_shader_context *ctx,
-  bool export_prim_id,
+  bool export_prim_id, bool export_layer_id,
   struct radv_vs_output_info *outinfo)
 {
uint32_t param_count = 0;
@@ -2363,6 +2363,18 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
outinfo->export_prim_id = true;
}
 
+   if (export_layer_id) {
+   LLVMValueRef values[4];
+
+   values[0] = layer_value;
+   for (unsigned j = 1; j < 4; j++)
+   values[j] = ctx->ac.f32_0;
+
+   radv_export_param(ctx, param_count, values, 0x1);
+
+   outinfo->vs_output_param_offset[VARYING_SLOT_LAYER] = 
param_count++;
+   }
+
outinfo->pos_exports = num_pos_exports;
outinfo->param_exports = param_count;
 }
@@ -2825,6 +2837,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi, 
unsigned max_outputs,
handle_es_outputs_post(ctx, 
>shader_info->vs.es_info);
else
handle_vs_outputs_post(ctx, 
ctx->options->key.vs.export_prim_id,
+  
ctx->options->key.vs.export_layer_id,
   >shader_info->vs.outinfo);
break;
case MESA_SHADER_FRAGMENT:
@@ -2841,6 +2854,7 @@ handle_shader_outputs_post(struct ac_shader_abi *abi, 
unsigned max_outputs,
handle_es_outputs_post(ctx, 
>shader_info->tes.es_info);
else
handle_vs_outputs_post(ctx, 
ctx->options->key.tes.export_prim_id,
+  
ctx->options->key.tes.export_layer_id,
   >shader_info->tes.outinfo);
break;
default:
@@ -3439,7 +3453,7 @@ ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
}
idx += slot_inc;
}
-   handle_vs_outputs_post(ctx, false, >shader_info->vs.outinfo);
+   handle_vs_outputs_post(ctx, false, false, 
>shader_info->vs.outinfo);
 }
 
 void
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 52a6d23718..89c5e69941 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1718,8 +1718,12 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
/* TODO: These are no longer used as keys we should refactor 
this */
keys[MESA_SHADER_VERTEX].vs.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+   keys[MESA_SHADER_VERTEX].vs.export_layer_id =
+   
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
keys[MESA_SHADER_TESS_EVAL].tes.export_prim_id =

pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.prim_id_input;
+   keys[MESA_SHADER_TESS_EVAL].tes.export_layer_id =
+   
pipeline->shaders[MESA_SHADER_FRAGMENT]->info.info.ps.layer_input;
}
 
if (device->physical_device->rad_info.chip_class >= GFX9 && 
modules[MESA_SHADER_TESS_CTRL]) {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 40e92b52f3..ae30d6125b 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -58,11 +58,13 @@ struct radv_vs_variant_key {
uint32_t as_es:1;
uint32_t as

Mesa (master): radv: migrate lds size calculations to shader gen.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9188bd78d7e2754f36ad66db3fab80c8ee9f5093
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9188bd78d7e2754f36ad66db3fab80c8ee9f5093

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 13:30:14 2018 +1000

radv: migrate lds size calculations to shader gen.

This moves the lds_size calcs into the shader so we have all
the size stuff in one file.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 33 +
 src/amd/vulkan/radv_pipeline.c| 29 -
 src/amd/vulkan/radv_shader.h  |  1 +
 3 files changed, 38 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index b175ec386c..d76969828e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -174,6 +174,38 @@ get_tcs_num_patches(struct radv_shader_context *ctx)
return num_patches;
 }
 
+static unsigned
+calculate_tess_lds_size(struct radv_shader_context *ctx)
+{
+   unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
+   unsigned num_tcs_output_cp;
+   unsigned num_tcs_outputs, num_tcs_patch_outputs;
+   unsigned input_vertex_size, output_vertex_size;
+   unsigned input_patch_size, output_patch_size;
+   unsigned pervertex_output_patch_size;
+   unsigned output_patch0_offset;
+   unsigned num_patches;
+   unsigned lds_size;
+
+   num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+   num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   num_tcs_patch_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+
+   input_vertex_size = ctx->tcs_num_inputs * 16;
+   output_vertex_size = num_tcs_outputs * 16;
+
+   input_patch_size = num_tcs_input_cp * input_vertex_size;
+
+   pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
+   output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs 
* 16;
+
+   num_patches = ctx->tcs_num_patches;
+   output_patch0_offset = input_patch_size * num_patches;
+
+   lds_size = output_patch0_offset + output_patch_size * num_patches;
+   return lds_size;
+}
+
 /* Tessellation shaders pass outputs to the next shader using LDS.
  *
  * LS outputs = TCS inputs
@@ -3130,6 +3162,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
shaders[i]->info.gs.vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.num_patches = ctx.tcs_num_patches;
+   shader_info->tcs.lds_size = 
calculate_tess_lds_size();
}
}
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 771bc2e408..a4836abf7f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1306,38 +1306,17 @@ static struct radv_tessellation_state
 calculate_tess_state(struct radv_pipeline *pipeline,
 const VkGraphicsPipelineCreateInfo *pCreateInfo)
 {
-   unsigned num_tcs_input_cp = 
pCreateInfo->pTessellationState->patchControlPoints;
-   unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
-   unsigned num_tcs_patch_outputs;
-   unsigned input_vertex_size, output_vertex_size, 
pervertex_output_patch_size;
-   unsigned input_patch_size, output_patch_size, output_patch0_offset;
+   unsigned num_tcs_input_cp;
+   unsigned num_tcs_output_cp;
unsigned lds_size;
unsigned num_patches;
struct radv_tessellation_state tess = {0};
 
-   /* This calculates how shader inputs and outputs among VS, TCS, and TES
-* are laid out in LDS. */
-   num_tcs_inputs = 
util_last_bit64(radv_get_vertex_shader(pipeline)->info.info.vs.ls_outputs_written);
-   num_tcs_outputs = 
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.outputs_written);
 //tcs->outputs_written
+   num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
num_tcs_output_cp = 
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS 
VERTICES OUT
-   num_tcs_patch_outputs = 
util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.info.tcs.patch_outputs_written);
-
-   /* Ensure that we only need one wave per SIMD so we don't need to check
-* resource usage. Also ensures that the number of tcs in and out
-* vertices per threadgroup are at most 256.
-*/
-   input_vertex_size = num_tcs_inputs * 16;
-   output_vertex_size = num_tcs_outputs * 16;
-
-   input_patch_size = num_tcs_input_cp * input_vertex_size;
-
-   pe

Mesa (master): radv: use num_patches output from tcs shader.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f50d520acfb1a79c935e3f8838310a6db39d2427
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f50d520acfb1a79c935e3f8838310a6db39d2427

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 11:22:07 2018 +1000

radv: use num_patches output from tcs shader.

Instead of recalculating the value, use the shader calculated value.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_pipeline.c | 30 ++
 1 file changed, 2 insertions(+), 28 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b4e96238d7..898124fa82 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1311,7 +1311,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
unsigned num_tcs_patch_outputs;
unsigned input_vertex_size, output_vertex_size, 
pervertex_output_patch_size;
unsigned input_patch_size, output_patch_size, output_patch0_offset;
-   unsigned lds_size, hardware_lds_size;
+   unsigned lds_size;
unsigned num_patches;
struct radv_tessellation_state tess = {0};
 
@@ -1334,34 +1334,8 @@ calculate_tess_state(struct radv_pipeline *pipeline,
 
pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs 
* 16;
-   /* Ensure that we only need one wave per SIMD so we don't need to check
-* resource usage. Also ensures that the number of tcs in and out
-* vertices per threadgroup are at most 256.
-*/
-   num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
-
-   /* Make sure that the data fits in LDS. This assumes the shaders only
-* use LDS for the inputs and outputs.
-*/
-   hardware_lds_size = 
pipeline->device->physical_device->rad_info.chip_class >= CIK ? 65536 : 32768;
-   num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + 
output_patch_size));
-
-   /* Make sure the output data fits in the offchip buffer */
-   num_patches = MIN2(num_patches,
-   (pipeline->device->tess_offchip_block_dw_size * 4) /
-   output_patch_size);
-
-   /* Not necessary for correctness, but improves performance. The
-* specific value is taken from the proprietary driver.
-*/
-   num_patches = MIN2(num_patches, 40);
-
-   /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
-   if (pipeline->device->physical_device->rad_info.chip_class == SI) {
-   unsigned one_wave = 64 / MAX2(num_tcs_input_cp, 
num_tcs_output_cp);
-   num_patches = MIN2(num_patches, one_wave);
-   }
 
+   num_patches = 
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
output_patch0_offset = input_patch_size * num_patches;
 
lds_size = output_patch0_offset + output_patch_size * num_patches;

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Mesa (master): radv: drop tess offchip layout for tcs.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 010d055aae7611f0a53b8b3dd3df98a71e52ad6a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=010d055aae7611f0a53b8b3dd3df98a71e52ad6a

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 07:14:04 2018 +

radv: drop tess offchip layout for tcs.

This removes the last TCS specific user sgpr.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 116 +-
 src/amd/vulkan/radv_pipeline.c|   9 ---
 src/amd/vulkan/radv_shader.c  |   1 +
 src/amd/vulkan/radv_shader.h  |   2 +-
 4 files changed, 90 insertions(+), 38 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 73a5a9a069..1b50b2cc1f 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -106,6 +106,7 @@ struct radv_shader_context {
uint64_t tcs_outputs_read;
uint32_t tcs_vertices_per_patch;
uint32_t tcs_num_inputs;
+   uint32_t tcs_num_patches;
 };
 
 enum radeon_llvm_calling_convention {
@@ -136,6 +137,46 @@ static LLVMValueRef get_rel_patch_id(struct 
radv_shader_context *ctx)
}
 }
 
+static unsigned
+get_tcs_num_patches(struct radv_shader_context *ctx)
+{
+   unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
+   unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+   uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+   uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
+   uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   uint32_t num_tcs_patch_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+   uint32_t output_vertex_size = num_tcs_outputs * 16;
+   uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * 
output_vertex_size;
+   uint32_t output_patch_size = pervertex_output_patch_size + 
num_tcs_patch_outputs * 16;
+   unsigned num_patches;
+   unsigned hardware_lds_size;
+
+   /* Ensure that we only need one wave per SIMD so we don't need to check
+* resource usage. Also ensures that the number of tcs in and out
+* vertices per threadgroup are at most 256.
+*/
+   num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
+   /* Make sure that the data fits in LDS. This assumes the shaders only
+* use LDS for the inputs and outputs.
+*/
+   hardware_lds_size = ctx->options->chip_class >= CIK ? 65536 : 32768;
+   num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + 
output_patch_size));
+   /* Make sure the output data fits in the offchip buffer */
+   num_patches = MIN2(num_patches, 
(ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
+   /* Not necessary for correctness, but improves performance. The
+* specific value is taken from the proprietary driver.
+*/
+   num_patches = MIN2(num_patches, 40);
+
+   /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
+   if (ctx->options->chip_class == SI) {
+   unsigned one_wave = 64 / MAX2(num_tcs_input_cp, 
num_tcs_output_cp);
+   num_patches = MIN2(num_patches, one_wave);
+   }
+   return num_patches;
+}
+
 /* Tessellation shaders pass outputs to the next shader using LDS.
  *
  * LS outputs = TCS inputs
@@ -195,17 +236,17 @@ get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
uint32_t output_patch0_offset = input_patch_size;
-   LLVMValueRef num_patches = ac_unpack_param(>ac, 
ctx->tcs_offchip_layout, 0, 9);
+   unsigned num_patches = ctx->tcs_num_patches;
 
+   output_patch0_offset *= num_patches;
output_patch0_offset /= 4;
-   return LLVMBuildMul(ctx->ac.builder,
-   num_patches,
-   LLVMConstInt(ctx->ac.i32, output_patch0_offset, 
false), "");
+   return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
 }
 
 static LLVMValueRef
 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
 {
+   assert (ctx->stage == MESA_SHADER_TESS_CTRL);
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
uint32_t output_patch0_offset = input_patch_size;
@@ -213,15 +254,12 @@ get_tcs_out_patch0_patch_data_offset(struct 
radv_shader_context *ctx)
uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.o

Mesa (master): radv: migrate unique index info shader info (v2)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 2012dae19a1ef73224c4e54eab4cd731f1d59ddf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2012dae19a1ef73224c4e54eab4cd731f1d59ddf

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 05:48:40 2018 +

radv: migrate unique index info shader info (v2)

This just moves this function to an inline so the shader_info
pass can use it.

v2: use inline (Samuel)

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 22 --
 src/amd/vulkan/radv_shader.h  | 21 +
 2 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 8c31695928..0d62768ecd 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -659,28 +659,6 @@ set_vs_specific_input_locs(struct radv_shader_context *ctx,
}
 }
 
-static unsigned shader_io_get_unique_index(gl_varying_slot slot)
-{
-   /* handle patch indices separate */
-   if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
-   return 0;
-   if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
-   return 1;
-   if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
-   return 2 + (slot - VARYING_SLOT_PATCH0);
-
-   if (slot == VARYING_SLOT_POS)
-   return 0;
-   if (slot == VARYING_SLOT_PSIZ)
-   return 1;
-   if (slot == VARYING_SLOT_CLIP_DIST0)
-   return 2;
-   /* 3 is reserved for clip dist as well */
-   if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
-   return 4 + (slot - VARYING_SLOT_VAR0);
-   unreachable("illegal slot in get unique index\n");
-}
-
 static void set_llvm_calling_convention(LLVMValueRef func,
 gl_shader_stage stage)
 {
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 5c3f0ff6c4..47cb23df0d 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -338,4 +338,25 @@ radv_can_dump_shader_stats(struct radv_device *device,
   module && !module->nir;
 }
 
+static inline unsigned shader_io_get_unique_index(gl_varying_slot slot)
+{
+   /* handle patch indices separate */
+   if (slot == VARYING_SLOT_TESS_LEVEL_OUTER)
+   return 0;
+   if (slot == VARYING_SLOT_TESS_LEVEL_INNER)
+   return 1;
+   if (slot >= VARYING_SLOT_PATCH0 && slot <= VARYING_SLOT_TESS_MAX)
+   return 2 + (slot - VARYING_SLOT_PATCH0);
+   if (slot == VARYING_SLOT_POS)
+   return 0;
+   if (slot == VARYING_SLOT_PSIZ)
+   return 1;
+   if (slot == VARYING_SLOT_CLIP_DIST0)
+   return 2;
+   /* 3 is reserved for clip dist as well */
+   if (slot >= VARYING_SLOT_VAR0 && slot <= VARYING_SLOT_VAR31)
+   return 4 + (slot - VARYING_SLOT_VAR0);
+   unreachable("illegal slot in get unique index\n");
+}
+
 #endif

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Mesa (master): radv: drop ls_out_layout const.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f343d11ae7ff9fec6736a3933ff6272cba824f74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f343d11ae7ff9fec6736a3933ff6272cba824f74

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 05:53:33 2018 +

radv: drop ls_out_layout const.

We can precalculate input_vertex_size at compile time.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 30 --
 src/amd/vulkan/radv_pipeline.c| 10 --
 src/amd/vulkan/radv_shader.h  |  1 -
 3 files changed, 4 insertions(+), 37 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 0d62768ecd..996add72ae 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -60,7 +60,6 @@ struct radv_shader_context {
LLVMValueRef vertex_buffers;
LLVMValueRef rel_auto_id;
LLVMValueRef vs_prim_id;
-   LLVMValueRef ls_out_layout;
LLVMValueRef es2gs_offset;
 
LLVMValueRef tcs_offchip_layout;
@@ -162,14 +161,8 @@ static LLVMValueRef get_rel_patch_id(struct 
radv_shader_context *ctx)
 static LLVMValueRef
 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
 {
-   if (ctx->stage == MESA_SHADER_VERTEX)
-   return ac_unpack_param(>ac, ctx->ls_out_layout, 0, 13);
-   else if (ctx->stage == MESA_SHADER_TESS_CTRL)
-   return ac_unpack_param(>ac, ctx->tcs_in_layout, 0, 13);
-   else {
-   assert(0);
-   return NULL;
-   }
+   assert (ctx->stage == MESA_SHADER_TESS_CTRL);
+   return ac_unpack_param(>ac, ctx->tcs_in_layout, 0, 13);
 }
 
 static LLVMValueRef
@@ -463,14 +456,11 @@ static void allocate_user_sgprs(struct 
radv_shader_context *ctx,
case MESA_SHADER_VERTEX:
if (!ctx->is_gs_copy_shader)
user_sgpr_info->sgpr_count += count_vs_user_sgprs(ctx);
-   if (ctx->options->key.vs.as_ls)
-   user_sgpr_info->sgpr_count++;
break;
case MESA_SHADER_TESS_CTRL:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
-   user_sgpr_info->sgpr_count++;
}
user_sgpr_info->sgpr_count += 4;
break;
@@ -743,9 +733,6 @@ static void create_function(struct radv_shader_context *ctx,
if (ctx->options->key.vs.as_es)
add_arg(, ARG_SGPR, ctx->ac.i32,
>es2gs_offset);
-   else if (ctx->options->key.vs.as_ls)
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >ls_out_layout);
 
declare_vs_input_vgprs(ctx, );
break;
@@ -772,9 +759,6 @@ static void create_function(struct radv_shader_context *ctx,
previous_stage, );
 
add_arg(, ARG_SGPR, ctx->ac.i32,
-   >ls_out_layout);
-
-   add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_offchip_layout);
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_out_offsets);
@@ -1011,17 +995,10 @@ static void create_function(struct radv_shader_context 
*ctx,
   previous_stage, _sgpr_idx);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
-   if (ctx->options->key.vs.as_ls) {
-   set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
-  _sgpr_idx, 1);
-   }
break;
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
   previous_stage, _sgpr_idx);
-   if (has_previous_stage)
-   set_loc_shader(ctx, AC_UD_VS_LS_TCS_IN_LAYOUT,
-  _sgpr_idx, 1);
set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, _sgpr_idx, 
4);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
@@ -2411,7 +2388,8 @@ static void
 handle_ls_outputs_post(struct radv_shader_context *ctx)
 {
LLVMValueRef vertex_id = ctx->rel_auto_id;
-   LLVMValueRef vertex_dw_stride = ac_unpack_param(>ac, 
ctx->ls_out_layout, 13, 8);
+   uint32_t num_tcs_inputs = 
util_last_bit64(ctx->shader_info->info.vs.ls_outputs_written);
+   L

Mesa (master): radv/shader_info: start gathering tess output info (v2)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: d89b16b7b9c3de8b7a7b896822f3893fdda4dbec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d89b16b7b9c3de8b7a7b896822f3893fdda4dbec

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 05:49:04 2018 +

radv/shader_info: start gathering tess output info (v2)

This gathers the ls outputs written by the vertex shader,
and the tcs outputs, these are needed to calculate certain
tcs parameters.

These have to be separate for combined gfx9 shaders.

This is a bit pessimistic compared to the nir pass,
as we don't work out the individual slots for tcs outputs,
but I actually thing it should be fine to just mark the whole
thing used here.

v2: move to radv, handle clip dist (Samuel),
handle compacts and patchs properly.
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_shader.h  |  5 
 src/amd/vulkan/radv_shader_info.c | 49 +--
 2 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 47cb23df0d..99f677c524 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -133,6 +133,7 @@ struct radv_shader_info {
bool uses_invocation_id;
bool uses_prim_id;
struct {
+   uint64_t ls_outputs_written;
uint8_t input_usage_mask[VERT_ATTRIB_MAX];
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
bool has_vertex_buffers; /* needs vertex buffers and base/start 
*/
@@ -160,6 +161,10 @@ struct radv_shader_info {
bool uses_thread_id[3];
bool uses_local_invocation_idx;
} cs;
+   struct {
+   uint64_t outputs_written;
+   uint64_t patch_outputs_written;
+   } tcs;
 };
 
 struct radv_userdata_info {
diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 3cce0c2f6e..ded3281516 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -30,6 +30,23 @@ static void mark_sampler_desc(const nir_variable *var,
info->desc_set_used_mask |= (1 << var->data.descriptor_set);
 }
 
+static void mark_ls_output(struct radv_shader_info *info,
+  uint32_t param, int num_slots)
+{
+   uint64_t mask = (1ull << num_slots) - 1ull;
+   info->vs.ls_outputs_written |= (mask << param);
+}
+
+static void mark_tess_output(struct radv_shader_info *info,
+bool is_patch, uint32_t param, int num_slots)
+{
+   uint64_t mask = (1ull << num_slots) - 1ull;
+   if (is_patch)
+   info->tcs.patch_outputs_written |= (mask << param);
+   else
+   info->tcs.outputs_written |= (mask << param);
+}
+
 static void
 gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
  struct radv_shader_info *info)
@@ -162,6 +179,17 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
} else if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
info->tes.output_usage_mask[idx] |=
instr->const_index[0] << comp;
+   } else if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
+   unsigned param = 
shader_io_get_unique_index(idx);
+   const struct glsl_type *type = var->type;
+   if (!var->data.patch)
+   type = 
glsl_get_array_element(var->type);
+   unsigned slots =
+   var->data.compact ? 
DIV_ROUND_UP(glsl_get_length(type), 4)
+   : glsl_count_attribute_slots(type, 
false);
+   if (idx == VARYING_SLOT_CLIP_DIST0)
+   slots = 
(nir->info.clip_distance_array_size + nir->info.cull_distance_array_size > 4) ? 
2 : 1;
+   mark_tess_output(info, var->data.patch, param, 
slots);
}
}
break;
@@ -253,6 +281,18 @@ gather_info_input_decl(const nir_shader *nir, const 
nir_variable *var,
 }
 
 static void
+gather_info_output_decl_ls(const nir_shader *nir, const nir_variable *var,
+  struct radv_shader_info *info)
+{
+   int idx = var->data.location;
+   unsigned param = shader_io_get_unique_index(idx);
+   int num_slots = glsl_count_attribute_slots(var->type, false);
+   if (idx == VARYING_SLOT_CLIP_DIST0)
+   num_slots = (nir->info.clip_distance_array_size + 
nir->info.cull_distance_array_size > 4

Mesa (master): radv: pass num_patches to tes from tcs

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6db44d6a8c35e414c393246d0d657dbcac3b981b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6db44d6a8c35e414c393246d0d657dbcac3b981b

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 07:31:55 2018 +

radv: pass num_patches to tes from tcs

TES needs num_patches to do some of the calculations.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 4 +++-
 src/amd/vulkan/radv_pipeline.c| 4 
 src/amd/vulkan/radv_shader.h  | 3 ++-
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 1b50b2cc1f..a1f7a3469e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1170,7 +1170,7 @@ static LLVMValueRef calc_param_stride(struct 
radv_shader_context *ctx,
else
param_stride = LLVMConstInt(ctx->ac.i32, 
ctx->tcs_num_patches, false);
} else {
-   LLVMValueRef num_patches = ac_unpack_param(>ac, 
ctx->tcs_offchip_layout, 0, 9);
+   LLVMValueRef num_patches = LLVMConstInt(ctx->ac.i32, 
ctx->tcs_num_patches, false);
LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, 
ctx->tcs_vertices_per_patch, false);
if (vertex_index)
param_stride = LLVMBuildMul(ctx->ac.builder, 
vertices_per_patch,
@@ -3109,6 +3109,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.tcs_vertices_per_patch = 
shaders[i]->info.tess.tcs_vertices_out;
+   ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.options->key.vs.as_ls) {
@@ -3176,6 +3177,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
shader_info->tcs.outputs_written = 
ctx.tess_outputs_written;
shader_info->tcs.patch_outputs_written = 
ctx.tess_patch_outputs_written;
+   shader_info->tcs.num_patches = ctx.tcs_num_patches;
assert(ctx.tess_outputs_written == 
ctx.shader_info->info.tcs.outputs_written);
assert(ctx.tess_patch_outputs_written == 
ctx.shader_info->info.tcs.patch_outputs_written);
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX && 
ctx.options->key.vs.as_ls) {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 641dc5558b..cc7824566e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1785,6 +1785,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,

  _sizes[MESA_SHADER_TESS_CTRL]);
}
modules[MESA_SHADER_VERTEX] = NULL;
+   keys[MESA_SHADER_TESS_EVAL].tes.num_patches = 
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
}
 
if (device->physical_device->rad_info.chip_class >= GFX9 && 
modules[MESA_SHADER_GEOMETRY]) {
@@ -1804,6 +1805,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
if (i == MESA_SHADER_TESS_CTRL) {
keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 
util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.info.vs.ls_outputs_written);
}
+   if (i == MESA_SHADER_TESS_EVAL) {
+   keys[MESA_SHADER_TESS_EVAL].tes.num_patches = 
pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
+   }
pipeline->shaders[i] = 
radv_shader_variant_create(device, modules[i], [i], 1,
  
pipeline->layout,
  keys 
+ i, [i],
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 3726adb259..984d335766 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -63,6 +63,7 @@ struct radv_vs_variant_key {
 struct radv_tes_variant_key {
uint32_t as_es:1;
uint32_t export_prim_id:1;
+   uint32_t num_patches;
 };
 
 struct radv_tcs_variant_key {
@@ -237,7 +238,7 @@ struct radv_shader

Mesa (master): radv/tess: remove last chunk of tess sgprs

[Dave Airlie]

Module: Mesa
Branch: master
Commit: bf9a0ea85350d60304f8bfa664ba0d939af1c729
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf9a0ea85350d60304f8bfa664ba0d939af1c729

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 19:15:25 2018 +

radv/tess: remove last chunk of tess sgprs

This removes the last TES-specifc user sgpr.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 50 ---
 src/amd/vulkan/radv_pipeline.c| 18 ++
 src/amd/vulkan/radv_shader.h  |  4 ++--
 3 files changed, 19 insertions(+), 53 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index a1f7a3469e..c9782778be 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -62,7 +62,6 @@ struct radv_shader_context {
LLVMValueRef vs_prim_id;
LLVMValueRef es2gs_offset;
 
-   LLVMValueRef tcs_offchip_layout;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -533,14 +532,11 @@ static void allocate_user_sgprs(struct 
radv_shader_context *ctx,
}
break;
case MESA_SHADER_TESS_EVAL:
-   user_sgpr_info->sgpr_count += 1;
break;
case MESA_SHADER_GEOMETRY:
if (has_previous_stage) {
if (previous_stage == MESA_SHADER_VERTEX) {
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
-   } else {
-   user_sgpr_info->sgpr_count++;
}
}
user_sgpr_info->sgpr_count += 2;
@@ -861,7 +857,6 @@ static void create_function(struct radv_shader_context *ctx,
   previous_stage, _sgpr_info,
   , _sets);
 
-   add_arg(, ARG_SGPR, ctx->ac.i32, >tcs_offchip_layout);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -896,10 +891,7 @@ static void create_function(struct radv_shader_context 
*ctx,
   _sgpr_info, ,
   _sets);
 
-   if (previous_stage == MESA_SHADER_TESS_EVAL) {
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_offchip_layout);
-   } else {
+   if (previous_stage != MESA_SHADER_TESS_EVAL) {
declare_vs_specific_input_sgprs(ctx, stage,

has_previous_stage,
previous_stage,
@@ -1055,7 +1047,6 @@ static void create_function(struct radv_shader_context 
*ctx,
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
case MESA_SHADER_TESS_EVAL:
-   set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT, _sgpr_idx, 
1);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
@@ -1066,9 +1057,6 @@ static void create_function(struct radv_shader_context 
*ctx,
   has_previous_stage,
   previous_stage,
   _sgpr_idx);
-   else
-   set_loc_shader(ctx, AC_UD_TES_OFFCHIP_LAYOUT,
-  _sgpr_idx, 1);
}
set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
   _sgpr_idx, 2);
@@ -1149,35 +1137,27 @@ radv_load_resource(struct ac_shader_abi *abi, 
LLVMValueRef index,
  */
 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context 
*ctx)
 {
-   if (ctx->stage == MESA_SHADER_TESS_CTRL) {
-   uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
-   uint32_t output_vertex_size = num_tcs_outputs * 16;
-   uint32_t pervertex_output_patch_size = 
ctx->tcs_vertices_per_patch * output_vertex_size;
-   uint32_t num_patches = ctx->tcs_num_patches;
+   uint32_t num_patches = ctx->tcs_num_patches;
+   uint32_t num_tcs_outputs;
+   if (ctx->stage == MESA_SHADER_TESS_CTRL)
+   num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   else
+   num_tcs_outputs = ctx->op

Mesa (master): radv: drop geometry stride user sgpr.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9d0d806332a32cd60b4f53fe805650751001d169
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d0d806332a32cd60b4f53fe805650751001d169

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 14:03:32 2018 +1000

radv: drop geometry stride user sgpr.

This removes the other geometry specific user sgpr.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 37 +++--
 src/amd/vulkan/radv_pipeline.c|  9 -
 src/amd/vulkan/radv_shader.h  |  1 -
 3 files changed, 19 insertions(+), 28 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index de784959fb..cedcd38b3a 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -69,7 +69,6 @@ struct radv_shader_context {
LLVMValueRef tes_u;
LLVMValueRef tes_v;
 
-   LLVMValueRef gsvs_ring_stride;
LLVMValueRef gs2vs_offset;
LLVMValueRef gs_wave_id;
LLVMValueRef gs_vtx_offset[6];
@@ -103,6 +102,8 @@ struct radv_shader_context {
uint32_t tcs_vertices_per_patch;
uint32_t tcs_num_inputs;
uint32_t tcs_num_patches;
+   uint32_t max_gsvs_emit_size;
+   uint32_t gsvs_vertex_size;
 };
 
 enum radeon_llvm_calling_convention {
@@ -568,7 +569,6 @@ static void allocate_user_sgprs(struct radv_shader_context 
*ctx,
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
}
}
-   user_sgpr_info->sgpr_count += 1;
break;
default:
break;
@@ -927,8 +927,6 @@ static void create_function(struct radv_shader_context *ctx,
);
}
 
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >gsvs_ring_stride);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -956,8 +954,6 @@ static void create_function(struct radv_shader_context *ctx,
   _sgpr_info, ,
   _sets);
 
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >gsvs_ring_stride);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -1083,8 +1079,6 @@ static void create_function(struct radv_shader_context 
*ctx,
   previous_stage,
   _sgpr_idx);
}
-   set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
-  _sgpr_idx, 1);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
@@ -2929,6 +2923,8 @@ ac_setup_rings(struct radv_shader_context *ctx)
if (ctx->stage == MESA_SHADER_GEOMETRY) {
LLVMValueRef tmp;
uint32_t num_entries = 64;
+   LLVMValueRef gsvs_ring_stride = LLVMConstInt(ctx->ac.i32, 
ctx->max_gsvs_emit_size, false);
+   LLVMValueRef gsvs_ring_desc = LLVMConstInt(ctx->ac.i32, 
ctx->max_gsvs_emit_size << 16, false);
ctx->esgs_ring = ac_build_load_to_sgpr(>ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
ctx->gsvs_ring = ac_build_load_to_sgpr(>ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
 
@@ -2936,10 +2932,10 @@ ac_setup_rings(struct radv_shader_context *ctx)
 
tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
if (ctx->options->chip_class >= VI)
-   tmp = LLVMBuildMul(ctx->ac.builder, 
LLVMBuildLShr(ctx->ac.builder, ctx->gsvs_ring_stride, LLVMConstInt(ctx->ac.i32, 
16, false), ""), tmp, "");
+   tmp = LLVMBuildMul(ctx->ac.builder, gsvs_ring_stride, 
tmp, "");
ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, 
ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, 
ctx->ac.i32_1, "");
-   tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, 
"");
+   tmp = LLVMBuildOr(ctx->ac.builder, tmp, gsvs_ring_desc, "");
ctx->gsvs_ring = LLVMBuildInsertEle

Mesa (master): radv/tess: drop tcs_in_layout setting completely.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6adf99165c97fb53f37be1c5b6007632838dd49b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6adf99165c97fb53f37be1c5b6007632838dd49b

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 06:14:40 2018 +

radv/tess: drop tcs_in_layout setting completely.

Inline all calcs at shader creation.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 26 +-
 src/amd/vulkan/radv_pipeline.c| 12 ++--
 src/amd/vulkan/radv_shader.h  |  1 +
 3 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 996add72ae..9eeea597fc 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -65,7 +65,6 @@ struct radv_shader_context {
LLVMValueRef tcs_offchip_layout;
LLVMValueRef tcs_out_offsets;
LLVMValueRef tcs_out_layout;
-   LLVMValueRef tcs_in_layout;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -108,6 +107,7 @@ struct radv_shader_context {
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
uint32_t tcs_vertices_per_patch;
+   uint32_t tcs_num_inputs;
 };
 
 enum radeon_llvm_calling_convention {
@@ -162,7 +162,11 @@ static LLVMValueRef
 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
 {
assert (ctx->stage == MESA_SHADER_TESS_CTRL);
-   return ac_unpack_param(>ac, ctx->tcs_in_layout, 0, 13);
+   uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+   uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
+
+   input_patch_size /= 4;
+   return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
 }
 
 static LLVMValueRef
@@ -462,7 +466,7 @@ static void allocate_user_sgprs(struct radv_shader_context 
*ctx,
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
}
-   user_sgpr_info->sgpr_count += 4;
+   user_sgpr_info->sgpr_count += 3;
break;
case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
@@ -764,8 +768,6 @@ static void create_function(struct radv_shader_context *ctx,
>tcs_out_offsets);
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_out_layout);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_in_layout);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -789,8 +791,6 @@ static void create_function(struct radv_shader_context *ctx,
>tcs_out_offsets);
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_out_layout);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_in_layout);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -999,7 +999,7 @@ static void create_function(struct radv_shader_context *ctx,
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
   previous_stage, _sgpr_idx);
-   set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, _sgpr_idx, 
4);
+   set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, _sgpr_idx, 
3);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
@@ -1226,7 +1226,8 @@ load_tcs_varyings(struct ac_shader_abi *abi,
unsigned param = shader_io_get_unique_index(location);
 
if (load_input) {
-   stride = ac_unpack_param(>ac, ctx->tcs_in_layout, 13, 8);
+   uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
+   stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
dw_addr = get_tcs_in_current_patch_offset(ctx);
} else {
if (!is_patch) {
@@ -3019,6 +3020,10 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
ctx.tcs_vertices_per_patch = 
shaders[i]->info.tess.tcs_vertices_out;
+   if (shader_count == 1)
+   

Mesa (master): radv: get rid of geometry user sgpr for num entries.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6f051549c30ecd8340028025f9c947d1ad5a04ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f051549c30ecd8340028025f9c947d1ad5a04ce

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 13:48:46 2018 +1000

radv: get rid of geometry user sgpr for num entries.

This drops one of the geometry specific user sgprs,
we can work this out at compile time.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 15 +++
 src/amd/vulkan/radv_pipeline.c|  9 +
 2 files changed, 8 insertions(+), 16 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index d76969828e..de784959fb 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -70,7 +70,6 @@ struct radv_shader_context {
LLVMValueRef tes_v;
 
LLVMValueRef gsvs_ring_stride;
-   LLVMValueRef gsvs_num_entries;
LLVMValueRef gs2vs_offset;
LLVMValueRef gs_wave_id;
LLVMValueRef gs_vtx_offset[6];
@@ -569,7 +568,7 @@ static void allocate_user_sgprs(struct radv_shader_context 
*ctx,
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
}
}
-   user_sgpr_info->sgpr_count += 2;
+   user_sgpr_info->sgpr_count += 1;
break;
default:
break;
@@ -930,8 +929,6 @@ static void create_function(struct radv_shader_context *ctx,
 
add_arg(, ARG_SGPR, ctx->ac.i32,
>gsvs_ring_stride);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >gsvs_num_entries);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -961,8 +958,6 @@ static void create_function(struct radv_shader_context *ctx,
 
add_arg(, ARG_SGPR, ctx->ac.i32,
>gsvs_ring_stride);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >gsvs_num_entries);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -1089,7 +1084,7 @@ static void create_function(struct radv_shader_context 
*ctx,
   _sgpr_idx);
}
set_loc_shader(ctx, AC_UD_GS_VS_RING_STRIDE_ENTRIES,
-  _sgpr_idx, 2);
+  _sgpr_idx, 1);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
@@ -2933,12 +2928,16 @@ ac_setup_rings(struct radv_shader_context *ctx)
}
if (ctx->stage == MESA_SHADER_GEOMETRY) {
LLVMValueRef tmp;
+   uint32_t num_entries = 64;
ctx->esgs_ring = ac_build_load_to_sgpr(>ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_ESGS_GS, false));
ctx->gsvs_ring = ac_build_load_to_sgpr(>ac, 
ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_GSVS_GS, false));
 
ctx->gsvs_ring = LLVMBuildBitCast(ctx->ac.builder, 
ctx->gsvs_ring, ctx->ac.v4i32, "");
 
-   ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, 
ctx->gsvs_ring, ctx->gsvs_num_entries, LLVMConstInt(ctx->ac.i32, 2, false), "");
+   tmp = LLVMConstInt(ctx->ac.i32, num_entries, false);
+   if (ctx->options->chip_class >= VI)
+   tmp = LLVMBuildMul(ctx->ac.builder, 
LLVMBuildLShr(ctx->ac.builder, ctx->gsvs_ring_stride, LLVMConstInt(ctx->ac.i32, 
16, false), ""), tmp, "");
+   ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, 
ctx->gsvs_ring, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
tmp = LLVMBuildExtractElement(ctx->ac.builder, ctx->gsvs_ring, 
ctx->ac.i32_1, "");
tmp = LLVMBuildOr(ctx->ac.builder, tmp, ctx->gsvs_ring_stride, 
"");
ctx->gsvs_ring = LLVMBuildInsertElement(ctx->ac.builder, 
ctx->gsvs_ring, tmp, ctx->ac.i32_1, "");
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a4836abf7f..b6ca2db691 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2622,16 +2622,9 @@ radv_pipeline_generate_geometry_shader(struct 
radeon_winsys_cs *cs,
 
AC_UD

Mesa (master): radv: drop tcs_out_layout

[Dave Airlie]

Module: Mesa
Branch: master
Commit: b0460bbf1c7d09122c5e23546a23a8550375e03a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0460bbf1c7d09122c5e23546a23a8550375e03a

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 06:38:30 2018 +

radv: drop tcs_out_layout

Move all calculations to shader generation.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 22 +-
 src/amd/vulkan/radv_pipeline.c|  8 ++--
 2 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9eeea597fc..11d0c1721f 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -64,7 +64,6 @@ struct radv_shader_context {
 
LLVMValueRef tcs_offchip_layout;
LLVMValueRef tcs_out_offsets;
-   LLVMValueRef tcs_out_layout;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -172,13 +171,22 @@ get_tcs_in_patch_stride(struct radv_shader_context *ctx)
 static LLVMValueRef
 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
 {
-   return ac_unpack_param(>ac, ctx->tcs_out_layout, 0, 13);
+   uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   uint32_t num_tcs_patch_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
+   uint32_t output_vertex_size = num_tcs_outputs * 16;
+   uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * 
output_vertex_size;
+   uint32_t output_patch_size = pervertex_output_patch_size + 
num_tcs_patch_outputs * 16;
+   output_patch_size /= 4;
+   return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
 }
 
 static LLVMValueRef
 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
 {
-   return ac_unpack_param(>ac, ctx->tcs_out_layout, 13, 8);
+   uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   uint32_t output_vertex_size = num_tcs_outputs * 16;
+   output_vertex_size /= 4;
+   return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
 }
 
 static LLVMValueRef
@@ -466,7 +474,7 @@ static void allocate_user_sgprs(struct radv_shader_context 
*ctx,
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
}
-   user_sgpr_info->sgpr_count += 3;
+   user_sgpr_info->sgpr_count += 2;
break;
case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
@@ -766,8 +774,6 @@ static void create_function(struct radv_shader_context *ctx,
>tcs_offchip_layout);
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_out_offsets);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_out_layout);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -789,8 +795,6 @@ static void create_function(struct radv_shader_context *ctx,
>tcs_offchip_layout);
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_out_offsets);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_out_layout);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -999,7 +1003,7 @@ static void create_function(struct radv_shader_context 
*ctx,
case MESA_SHADER_TESS_CTRL:
set_vs_specific_input_locs(ctx, stage, has_previous_stage,
   previous_stage, _sgpr_idx);
-   set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, _sgpr_idx, 
3);
+   set_loc_shader(ctx, AC_UD_TCS_OFFCHIP_LAYOUT, _sgpr_idx, 
2);
if (ctx->abi.view_index)
set_loc_shader(ctx, AC_UD_VIEW_INDEX, _sgpr_idx, 
1);
break;
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 557d5ec58b..01808cc3f5 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -62,7 +62,6 @@ struct radv_blend_state {
 
 struct radv_tessellation_state {
uint32_t ls_hs_config;
-   uint32_t tcs_out_layout;
uint32_t tcs_out_offsets;
uint32_t offchip_layout;
unsigned num_patches;
@@ -1382,8 +1381,6 @@ calculate_tess_state(struct r

Mesa (master): radv: drop scanning the tess shader in the nir code.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 384aced65e7768f7bba1a6159c6730efdd514d6c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=384aced65e7768f7bba1a6159c6730efdd514d6c

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 12:28:12 2018 +1000

radv: drop scanning the tess shader in the nir code.

This drops the now unneeded scanning and results in favour
of the ones in the info.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 33 -
 src/amd/vulkan/radv_pipeline.c|  7 +++
 src/amd/vulkan/radv_shader.h  |  5 -
 3 files changed, 3 insertions(+), 42 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index c9782778be..b175ec386c 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -98,8 +98,6 @@ struct radv_shader_context {
unsigned gs_max_out_vertices;
 
unsigned tes_primitive_mode;
-   uint64_t tess_outputs_written;
-   uint64_t tess_patch_outputs_written;
 
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
@@ -1216,18 +1214,6 @@ static LLVMValueRef 
get_tcs_tes_buffer_address_params(struct radv_shader_context
return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
 }
 
-static void
-mark_tess_output(struct radv_shader_context *ctx,
-bool is_patch, uint32_t param, int num_slots)
-
-{
-   uint64_t slot_mask = (1ull << num_slots) - 1;
-   if (is_patch) {
-   ctx->tess_patch_outputs_written |= (slot_mask << param);
-   } else
-   ctx->tess_outputs_written |= (slot_mask << param);
-}
-
 static LLVMValueRef
 get_dw_address(struct radv_shader_context *ctx,
   LLVMValueRef dw_addr,
@@ -1323,7 +1309,6 @@ store_tcs_output(struct ac_shader_abi *abi,
const unsigned component = var->data.location_frac;
const bool is_patch = var->data.patch;
const bool is_compact = var->data.compact;
-   const unsigned count = glsl_count_attribute_slots(var->type, false);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
@@ -1352,11 +1337,6 @@ store_tcs_output(struct ac_shader_abi *abi,
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
 
-   if (param_index)
-   mark_tess_output(ctx, is_patch, param, count);
-   else
-   mark_tess_output(ctx, is_patch, param, 1);
-
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
 param_index);
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, 
is_compact,
@@ -2462,9 +2442,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
if (i == VARYING_SLOT_CLIP_DIST0)
length = ctx->num_output_clips + ctx->num_output_culls;
int param = shader_io_get_unique_index(i);
-   mark_tess_output(ctx, false, param, 1);
-   if (length > 4)
-   mark_tess_output(ctx, false, param + 1, 1);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, 
base_dw_addr,
LLVMConstInt(ctx->ac.i32, 
param * 4, false),
"");
@@ -2608,13 +2585,11 @@ write_tess_factors(struct radv_shader_context *ctx)
 
if (inner_comps) {
tess_inner_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
-   mark_tess_output(ctx, true, tess_inner_index, 1);
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
 LLVMConstInt(ctx->ac.i32, 
tess_inner_index * 4, false), "");
}
 
tess_outer_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
-   mark_tess_output(ctx, true, tess_outer_index, 1);
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
 LLVMConstInt(ctx->ac.i32, tess_outer_index * 
4, false), "");
 
@@ -3062,7 +3037,6 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
for(int i = 0; i < shader_count; ++i) {
ctx.stage = shaders[i]->info.stage;
ctx.output_mask = 0;
-   ctx.tess_outputs_written = 0;
ctx.num_output_clips = 
shaders[i]->info.clip_distance_array_size;
ctx.num_output_culls = 
shaders[i]->info.cull_distance_array_size;
 
@@ -3155,14 +3129,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
shader_info->gs.max_gsvs_emit_size = 
shader_info->gs.gsvs_

Mesa (master): radv: drop tcs_out_offsets

[Dave Airlie]

Module: Mesa
Branch: master
Commit: ee31cff856e0bdca11561b95a9b327a11dd0be3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee31cff856e0bdca11561b95a9b327a11dd0be3e

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 06:51:15 2018 +

radv: drop tcs_out_offsets

Move all calculations to shader generation.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 39 +++
 src/amd/vulkan/radv_pipeline.c| 10 ++
 2 files changed, 29 insertions(+), 20 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 11d0c1721f..73a5a9a069 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -63,7 +63,6 @@ struct radv_shader_context {
LLVMValueRef es2gs_offset;
 
LLVMValueRef tcs_offchip_layout;
-   LLVMValueRef tcs_out_offsets;
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
@@ -192,17 +191,37 @@ get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
 static LLVMValueRef
 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
 {
+   assert (ctx->stage == MESA_SHADER_TESS_CTRL);
+   uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+   uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
+   uint32_t output_patch0_offset = input_patch_size;
+   LLVMValueRef num_patches = ac_unpack_param(>ac, 
ctx->tcs_offchip_layout, 0, 9);
+
+   output_patch0_offset /= 4;
return LLVMBuildMul(ctx->ac.builder,
-   ac_unpack_param(>ac, ctx->tcs_out_offsets, 0, 
16),
-   LLVMConstInt(ctx->ac.i32, 4, false), "");
+   num_patches,
+   LLVMConstInt(ctx->ac.i32, output_patch0_offset, 
false), "");
 }
 
 static LLVMValueRef
 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
 {
-   return LLVMBuildMul(ctx->ac.builder,
-   ac_unpack_param(>ac, ctx->tcs_out_offsets, 16, 
16),
-   LLVMConstInt(ctx->ac.i32, 4, false), "");
+   uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
+   uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * 
input_vertex_size;
+   uint32_t output_patch0_offset = input_patch_size;
+
+   uint32_t num_tcs_outputs = 
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
+   uint32_t output_vertex_size = num_tcs_outputs * 16;
+   uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch * 
output_vertex_size;
+   LLVMValueRef num_patches = ac_unpack_param(>ac, 
ctx->tcs_offchip_layout, 0, 9);
+
+   output_patch0_offset /= 4;
+   LLVMValueRef value = LLVMBuildMul(ctx->ac.builder,
+ num_patches,
+ LLVMConstInt(ctx->ac.i32, 
output_patch0_offset, false), "");
+   return LLVMBuildAdd(ctx->ac.builder,
+   value,
+   LLVMConstInt(ctx->ac.i32, 
pervertex_output_patch_size / 4, false), "");
 }
 
 static LLVMValueRef
@@ -474,7 +493,7 @@ static void allocate_user_sgprs(struct radv_shader_context 
*ctx,
if (previous_stage == MESA_SHADER_VERTEX)
user_sgpr_info->sgpr_count += 
count_vs_user_sgprs(ctx);
}
-   user_sgpr_info->sgpr_count += 2;
+   user_sgpr_info->sgpr_count += 1;
break;
case MESA_SHADER_TESS_EVAL:
user_sgpr_info->sgpr_count += 1;
@@ -772,8 +791,6 @@ static void create_function(struct radv_shader_context *ctx,
 
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_offchip_layout);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_out_offsets);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -793,8 +810,6 @@ static void create_function(struct radv_shader_context *ctx,
 
add_arg(, ARG_SGPR, ctx->ac.i32,
>tcs_offchip_layout);
-   add_arg(, ARG_SGPR, ctx->ac.i32,
-   >tcs_out_offsets);
if (needs_view_index)
add_arg(, ARG_SGPR, ctx->ac.i32,
>abi.view_index);
@@ -1003,7 +1018,7 @@ static void create_function(struct radv_shad

Mesa (master): virgl: resize resource bo allocation if we need to.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 4b15b5e803eb4705f8532e6cc41cfdc8bd065de9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b15b5e803eb4705f8532e6cc41cfdc8bd065de9

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Mar 12 10:21:21 2018 +1000

virgl: resize resource bo allocation if we need to.

This fixes an illegal command buffer on the host seen with
piglit arb_internalformat_query2-max-dimensions

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 8 ++--
 src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c | 8 ++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c 
b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index 77854680e5..cf3c3bac4b 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -620,8 +620,12 @@ static void virgl_drm_add_res(struct virgl_drm_winsys 
*qdws,
unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
 
if (cbuf->cres > cbuf->nres) {
-  fprintf(stderr,"failure to add relocation\n");
-  return;
+  cbuf->nres += 256;
+  cbuf->res_bo = realloc(cbuf->res_bo, cbuf->nres * sizeof(struct 
virgl_hw_buf*));
+  if (!cbuf->res_bo) {
+  fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, 
cbuf->nres);
+  return;
+  }
}
 
cbuf->res_bo[cbuf->cres] = NULL;
diff --git a/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c 
b/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
index f62d0d0981..9a96c6eb83 100644
--- a/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
+++ b/src/gallium/winsys/virgl/vtest/virgl_vtest_winsys.c
@@ -460,8 +460,12 @@ static void virgl_vtest_add_res(struct virgl_vtest_winsys 
*vtws,
unsigned hash = res->res_handle & (sizeof(cbuf->is_handle_added)-1);
 
if (cbuf->cres > cbuf->nres) {
-  fprintf(stderr,"failure to add relocation\n");
-  return;
+  cbuf->nres += 256;
+  cbuf->res_bo = realloc(cbuf->res_bo, cbuf->nres * sizeof(struct 
virgl_hw_buf*));
+  if (!cbuf->res_bo) {
+  fprintf(stderr,"failure to add relocation %d, %d\n", cbuf->cres, 
cbuf->nres);
+  return;
+  }
}
 
cbuf->res_bo[cbuf->cres] = NULL;

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Mesa (master): radv: drop assert on bindingDescriptorCount > 0

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 3b0f2081b5dc351d40d67b99f8f1def551a8374d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b0f2081b5dc351d40d67b99f8f1def551a8374d

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar  8 10:15:12 2018 +1000

radv: drop assert on bindingDescriptorCount > 0

The spec is pretty clear that this can be 0, and that it operates
as a reserved binding.

Fixes:
dEQP-VK.binding_model.descriptor_update.empty_descriptor.uniform_buffer

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_descriptor_set.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/amd/vulkan/radv_descriptor_set.c 
b/src/amd/vulkan/radv_descriptor_set.c
index daff7b2fcd..3d56f8c217 100644
--- a/src/amd/vulkan/radv_descriptor_set.c
+++ b/src/amd/vulkan/radv_descriptor_set.c
@@ -137,7 +137,6 @@ VkResult radv_CreateDescriptorSetLayout(
}
 
set_layout->size = align(set_layout->size, alignment);
-   assert(binding->descriptorCount > 0);
set_layout->binding[b].type = binding->descriptorType;
set_layout->binding[b].array_size = binding->descriptorCount;
set_layout->binding[b].offset = set_layout->size;

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Mesa (master): ac/nir: pass the nir variable through tcs loading.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 4f0c89d66c570e82d832e2e49227517302e271a2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f0c89d66c570e82d832e2e49227517302e271a2

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Mar 14 10:19:45 2018 +1000

ac/nir: pass the nir variable through tcs loading.

I was going to have to add another parameter to this monster,
so we should just pass the nir_variable in, I can't find any
reason this would be a bad idea.

This needed for the next fix.

Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 10 +++---
 src/amd/common/ac_shader_abi.h   |  8 +++-
 src/amd/vulkan/radv_nir_to_llvm.c| 10 +-
 src/gallium/drivers/radeonsi/si_shader.c |  9 -
 4 files changed, 15 insertions(+), 22 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ade042d3d9..b0c0d76b47 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1804,19 +1804,15 @@ visit_store_var(struct ac_nir_context *ctx,
LLVMValueRef vertex_index = NULL;
LLVMValueRef indir_index = NULL;
unsigned const_index = 0;
-   const unsigned location = 
instr->variables[0]->var->data.location;
-   const unsigned driver_location = 
instr->variables[0]->var->data.driver_location;
-   const unsigned comp = 
instr->variables[0]->var->data.location_frac;
const bool is_patch = 
instr->variables[0]->var->data.patch;
-   const bool is_compact = 
instr->variables[0]->var->data.compact;
 
get_deref_offset(ctx, instr->variables[0],
 false, NULL, is_patch ? NULL : 
_index,
 _index, _index);
 
-   ctx->abi->store_tcs_outputs(ctx->abi, vertex_index, 
indir_index,
-   const_index, location, 
driver_location,
-   src, comp, is_patch, 
is_compact, writemask);
+   ctx->abi->store_tcs_outputs(ctx->abi, 
instr->variables[0]->var,
+   vertex_index, indir_index,
+   const_index, src, 
writemask);
return;
}
 
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 901e49b1f9..0737d697ff 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -28,6 +28,8 @@
 
 #include "compiler/shader_enums.h"
 
+struct nir_variable;
+
 #define AC_LLVM_MAX_OUTPUTS (VARYING_SLOT_VAR31 + 1)
 
 enum ac_descriptor_type {
@@ -111,15 +113,11 @@ struct ac_shader_abi {
   bool load_inputs);
 
void (*store_tcs_outputs)(struct ac_shader_abi *abi,
+ const struct nir_variable *var,
  LLVMValueRef vertex_index,
  LLVMValueRef param_index,
  unsigned const_index,
- unsigned location,
- unsigned driver_location,
  LLVMValueRef src,
- unsigned component,
- bool is_patch,
- bool is_compact,
  unsigned writemask);
 
LLVMValueRef (*load_tess_coord)(struct ac_shader_abi *abi);
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index fccd97b6cf..a4c0a41e3e 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1296,18 +1296,18 @@ load_tcs_varyings(struct ac_shader_abi *abi,
 
 static void
 store_tcs_output(struct ac_shader_abi *abi,
+const nir_variable *var,
 LLVMValueRef vertex_index,
 LLVMValueRef param_index,
 unsigned const_index,
-unsigned location,
-unsigned driver_location,
 LLVMValueRef src,
-unsigned component,
-bool is_patch,
-bool is_compact,
 unsigned writemask)
 {
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
+   const unsigned location = var->data.location;
+   const unsigned component = var->data.location_frac;
+   const bool is_patch = var->data.patch;
+   const bool is_compact = var->data

Mesa (master): radv: mark all tess output for an indirect access.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 27a5e5366e89498d98d786cc84fafbdb220c4d94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27a5e5366e89498d98d786cc84fafbdb220c4d94

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Mar 14 10:21:46 2018 +1000

radv: mark all tess output for an indirect access.

If a shader does a tcs store with an indirect access, we
were only marking the first spot as used. For indirect access
we always now mark all slots used by the variable.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.)
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 21 +
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index a4c0a41e3e..d4c99539aa 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1205,13 +1205,14 @@ static LLVMValueRef 
get_tcs_tes_buffer_address_params(struct radv_shader_context
 
 static void
 mark_tess_output(struct radv_shader_context *ctx,
-bool is_patch, uint32_t param)
+bool is_patch, uint32_t param, int num_slots)
 
 {
+   uint64_t slot_mask = (1ull << num_slots) - 1;
if (is_patch) {
-   ctx->tess_patch_outputs_written |= (1ull << param);
+   ctx->tess_patch_outputs_written |= (slot_mask << param);
} else
-   ctx->tess_outputs_written |= (1ull << param);
+   ctx->tess_outputs_written |= (slot_mask << param);
 }
 
 static LLVMValueRef
@@ -1308,6 +1309,7 @@ store_tcs_output(struct ac_shader_abi *abi,
const unsigned component = var->data.location_frac;
const bool is_patch = var->data.patch;
const bool is_compact = var->data.compact;
+   const unsigned count = glsl_count_attribute_slots(var->type, false);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
@@ -1336,7 +1338,10 @@ store_tcs_output(struct ac_shader_abi *abi,
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
 
-   mark_tess_output(ctx, is_patch, param);
+   if (param_index)
+   mark_tess_output(ctx, is_patch, param, count);
+   else
+   mark_tess_output(ctx, is_patch, param, 1);
 
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
 param_index);
@@ -2442,9 +2447,9 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
if (i == VARYING_SLOT_CLIP_DIST0)
length = ctx->num_output_clips + ctx->num_output_culls;
int param = shader_io_get_unique_index(i);
-   mark_tess_output(ctx, false, param);
+   mark_tess_output(ctx, false, param, 1);
if (length > 4)
-   mark_tess_output(ctx, false, param + 1);
+   mark_tess_output(ctx, false, param + 1, 1);
LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, 
base_dw_addr,
LLVMConstInt(ctx->ac.i32, 
param * 4, false),
"");
@@ -2588,13 +2593,13 @@ write_tess_factors(struct radv_shader_context *ctx)
 
if (inner_comps) {
tess_inner_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
-   mark_tess_output(ctx, true, tess_inner_index);
+   mark_tess_output(ctx, true, tess_inner_index, 1);
lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
 LLVMConstInt(ctx->ac.i32, 
tess_inner_index * 4, false), "");
}
 
tess_outer_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
-   mark_tess_output(ctx, true, tess_outer_index);
+   mark_tess_output(ctx, true, tess_outer_index, 1);
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
 LLVMConstInt(ctx->ac.i32, tess_outer_index * 
4, false), "");
 

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Mesa (master): radv: get correct offset into LDS for indexed vars.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: f9de2d409bf4f068a99d358d592d96ab4803f7fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9de2d409bf4f068a99d358d592d96ab4803f7fb

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Mar 14 05:41:53 2018 +1000

radv: get correct offset into LDS for indexed vars.

This seems more correct to me, since if we have an array
of floats they'll be vec4 aligned, and if we do af[2],
we want the const index to increase by 2 slots in the non
compact case.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105464
Fixes: 94f9591995 (radv/ac: add support for TCS/TES inputs/outputs.)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 056eb23ab6..fccd97b6cf 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1239,7 +1239,7 @@ get_dw_address(struct radv_shader_context *ctx,
LLVMConstInt(ctx->ac.i32, 
4, false), ""), "");
else if (const_index && !compact_const_index)
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
-  LLVMConstInt(ctx->ac.i32, const_index, 
false), "");
+  LLVMConstInt(ctx->ac.i32, const_index * 
4, false), "");
 
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
   LLVMConstInt(ctx->ac.i32, param * 4, false), "");

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Mesa (master): u_vbuf/translate: pass max_index into the set_buffer.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e76cf1ff12703964262c7bdef6083e723f0b46ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e76cf1ff12703964262c7bdef6083e723f0b46ba

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri Mar  9 06:18:55 2018 +1000

u_vbuf/translate: pass max_index into the set_buffer.

This fixes a memory trashing crash (not the test) seen with
dEQP-GLES3.stress.draw.unaligned_data.random.203
on virgl.

Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/auxiliary/util/u_vbuf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/util/u_vbuf.c 
b/src/gallium/auxiliary/util/u_vbuf.c
index d30a702210..95d7990c6c 100644
--- a/src/gallium/auxiliary/util/u_vbuf.c
+++ b/src/gallium/auxiliary/util/u_vbuf.c
@@ -448,7 +448,7 @@ u_vbuf_translate_buffers(struct u_vbuf *mgr, struct 
translate_key *key,
  map -= (ptrdiff_t)vb->stride * min_index;
   }
 
-  tr->set_buffer(tr, i, map, vb->stride, ~0);
+  tr->set_buffer(tr, i, map, vb->stride, info->max_index);
}
 
/* Translate. */

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Mesa (master): r600: implement callstack workaround for evergreen.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 5d4fbc2b54cb2aaea1cbb52ec087f31009f3ac76
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d4fbc2b54cb2aaea1cbb52ec087f31009f3ac76

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri Mar  9 16:03:53 2018 +1000

r600: implement callstack workaround for evergreen.

This is ported from the sb backend, there are some issues with
evergreen stacks on the boundary between entries and ALU_PUSH_BEFORE
instructions.

Whenever we are going to use a push before, we check the stack
usage and if we have to use the workaround, then we switch to
a separate push.

I noticed this problem dealing with some of the soft fp64 shaders,
in nosb mode, they are quite stack happy.

This fixes all the glitches and inconsistencies I've seen with them

Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Tested-by: Elie Tournier <elie.tourn...@collabora.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 39 +++---
 1 file changed, 31 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 4b44f66141..6b5c42f86d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -377,7 +377,7 @@ struct r600_shader_tgsi_instruction {
 static int emit_gs_ring_writes(struct r600_shader_ctx *ctx, const struct 
pipe_stream_output_info *so, int stream, bool ind);
 static const struct r600_shader_tgsi_instruction 
r600_shader_tgsi_instruction[], eg_shader_tgsi_instruction[], 
cm_shader_tgsi_instruction[];
 static int tgsi_helper_tempx_replicate(struct r600_shader_ctx *ctx);
-static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned 
reason);
+static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason);
 static void fc_pushlevel(struct r600_shader_ctx *ctx, int type);
 static int tgsi_else(struct r600_shader_ctx *ctx);
 static int tgsi_endif(struct r600_shader_ctx *ctx);
@@ -393,6 +393,15 @@ static void r600_bytecode_src(struct r600_bytecode_alu_src 
*bc_src,
 static int do_lds_fetch_values(struct r600_shader_ctx *ctx, unsigned temp_reg,
   unsigned dst_reg, unsigned mask);
 
+static bool ctx_needs_stack_workaround_8xx(struct r600_shader_ctx *ctx)
+{
+   if (ctx->bc->family == CHIP_HEMLOCK ||
+   ctx->bc->family == CHIP_CYPRESS ||
+   ctx->bc->family == CHIP_JUNIPER)
+   return false;
+   return true;
+}
+
 static int tgsi_last_instruction(unsigned writemask)
 {
int i, lasti = 0;
@@ -10168,7 +10177,7 @@ static int pops(struct r600_shader_ctx *ctx, int pops)
return 0;
 }
 
-static inline void callstack_update_max_depth(struct r600_shader_ctx *ctx,
+static inline int callstack_update_max_depth(struct r600_shader_ctx *ctx,
   unsigned reason)
 {
struct r600_stack_info *stack = >bc->stack;
@@ -10186,7 +10195,7 @@ static inline void callstack_update_max_depth(struct 
r600_shader_ctx *ctx,
/* pre-r8xx: if any non-WQM PUSH instruction is invoked, 2 
elements on
 * the stack must be reserved to hold the current 
active/continue
 * masks */
-   if (reason == FC_PUSH_VPM) {
+   if (reason == FC_PUSH_VPM || stack->push > 0) {
elements += 2;
}
break;
@@ -10212,7 +10221,7 @@ static inline void callstack_update_max_depth(struct 
r600_shader_ctx *ctx,
 *NOTE: it seems we also need to reserve additional element 
in some
 *other cases, e.g. when we have 4 levels of PUSH_VPM in 
the shader,
 *then STACK_SIZE should be 2 instead of 1 */
-   if (reason == FC_PUSH_VPM) {
+   if (reason == FC_PUSH_VPM || stack->push > 0) {
elements += 1;
}
break;
@@ -10231,6 +10240,7 @@ static inline void callstack_update_max_depth(struct 
r600_shader_ctx *ctx,
 
if (entries > stack->max_entries)
stack->max_entries = entries;
+   return elements;
 }
 
 static inline void callstack_pop(struct r600_shader_ctx *ctx, unsigned reason)
@@ -10254,7 +10264,7 @@ static inline void callstack_pop(struct r600_shader_ctx 
*ctx, unsigned reason)
}
 }
 
-static inline void callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
+static inline int callstack_push(struct r600_shader_ctx *ctx, unsigned reason)
 {
switch (reason) {
case FC_PUSH_VPM:
@@ -10262,6 +10272,7 @@ static inline void callstack_push(struct 
r600_shader_ctx *ctx, unsigned reason)
break;
case FC_PUSH_WQM:
++ctx->bc->stack.push_wqm;
+   break;
 

Mesa (master): ac/nir: don't put lod into args if it's zero.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: fb077b072823ecb193f4494daeceddf0f21aede2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb077b072823ecb193f4494daeceddf0f21aede2

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Mar  7 03:24:25 2018 +

ac/nir: don't put lod into args if it's zero.

If it's zero but put it in args we still end up consuming a
register for it.

This fixes some spilling in the NIR paths in Dirt Rally that
isn't seen with TGSI.

Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ea51c3a54a..cca796de71 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5070,8 +5070,7 @@ static void visit_tex(struct ac_nir_context *ctx, 
nir_tex_instr *instr)
}
 
/* Pack LOD */
-   if (lod && ((instr->op == nir_texop_txl && !lod_is_zero) ||
-   instr->op == nir_texop_txf)) {
+   if (lod && ((instr->op == nir_texop_txl || instr->op == nir_texop_txf) 
&& !lod_is_zero)) {
address[count++] = lod;
} else if (instr->op == nir_texop_txf_ms && sample_index) {
address[count++] = sample_index;

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Mesa (master): virgl: add offset alignment values to to v2 caps struct

[Dave Airlie]

Module: Mesa
Branch: master
Commit: fe0647df5a70a4954d9399f0860a12ff691a88ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe0647df5a70a4954d9399f0860a12ff691a88ee

Author: gurchetansi...@chromium.org <gurchetansi...@chromium.org>
Date:   Thu Feb 22 18:02:18 2018 -0800

virgl: add offset alignment values to to v2 caps struct

glBindBufferRange(..) in vrend_draw_bind_ubo is failing with
more than one uniform block. This is due to improper alignment
of the start of the second block. Let's query the proper
alignment from the driver and pass it back to Mesa.

Let's query for the texture alignment too, even though the Virgl
renderer doesn't call glTexBufferRange yet.

The default values are the widest workable range possible (for example,
GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT on Nvidia is 256).

Fixes:
dEQP-GLES3.functional.ubo.* on Nvidia

Example test:
dEQP-GLES3.functional.ubo.multi_basic_types.single_buffer.shared_vertex

Note: This is based on "virgl: reduce some default capset limits.",
which hasn't landed in Mesa yet but should relatively soon.

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_hw.h | 2 ++
 src/gallium/drivers/virgl/virgl_screen.c | 4 ++--
 src/gallium/drivers/virgl/virgl_winsys.h | 2 ++
 3 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index 833ab91eee..93849c03dd 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -284,6 +284,8 @@ struct virgl_caps_v2 {
 int32_t max_texel_offset;
 int32_t min_texture_gather_offset;
 int32_t max_texture_gather_offset;
+uint32_t texture_buffer_offset_alignment;
+uint32_t uniform_buffer_offset_alignment;
 };
 
 union virgl_caps {
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 22a694ea27..49a0c57cda 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -140,7 +140,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_USER_VERTEX_BUFFERS:
   return 0;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
-  return 16;
+  return vscreen->caps.caps.v2.uniform_buffer_offset_alignment;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
   return vscreen->caps.caps.v1.bset.streamout_pause_resume;
@@ -163,7 +163,7 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
   return vscreen->caps.caps.v1.max_tbo_size > 0;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
-  return 0;
+  return vscreen->caps.caps.v2.texture_buffer_offset_alignment;
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
   return 0;
case PIPE_CAP_CUBE_MAP_ARRAY:
diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index 95e21a8afd..99e98ad9c9 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -132,5 +132,7 @@ static inline void virgl_ws_fill_new_caps_defaults(struct 
virgl_drm_caps *caps)
caps->caps.v2.max_texel_offset = 7;
caps->caps.v2.min_texture_gather_offset = -8;
caps->caps.v2.max_texture_gather_offset = 7;
+   caps->caps.v2.texture_buffer_offset_alignment = 32;
+   caps->caps.v2.uniform_buffer_offset_alignment = 256;
 }
 #endif

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Mesa (master): virgl: handle getting new capsets.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: cd32258ec12e8edaf9facfa0715ad40032530f7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd32258ec12e8edaf9facfa0715ad40032530f7e

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Feb 15 14:20:37 2018 +1000

virgl: handle getting new capsets.

This checks the kernel api is new enough and asks for the
larger caps size since the kernel won't mess it up now.

Reviewed-by: Stéphane Marchesin <marc...@chromium.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_winsys.h   | 25 ++-
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c| 52 ++
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.h|  1 +
 src/gallium/winsys/virgl/drm/virtgpu_drm.h |  1 +
 .../winsys/virgl/vtest/virgl_vtest_socket.c|  2 +-
 .../winsys/virgl/vtest/virgl_vtest_winsys.c|  2 +
 6 files changed, 52 insertions(+), 31 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index ea21f2b671..d633678597 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -109,5 +109,28 @@ struct virgl_winsys {
  struct pipe_box *sub_box);
 };
 
-
+/* this defaults all newer caps,
+ * the kernel will overwrite these if newer version is available.
+ */
+static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
+{
+   caps->caps.v2.min_aliased_point_size = 0.f;
+   caps->caps.v2.max_aliased_point_size = 255.f;
+   caps->caps.v2.min_smooth_point_size = 0.f;
+   caps->caps.v2.max_smooth_point_size = 255.f;
+   caps->caps.v2.min_aliased_line_width = 0.f;
+   caps->caps.v2.max_aliased_line_width = 255.f;
+   caps->caps.v2.min_smooth_line_width = 0.f;
+   caps->caps.v2.max_smooth_line_width = 255.f;
+   caps->caps.v2.max_texture_lod_bias = 16.0f;
+   caps->caps.v2.max_geom_output_vertices = 256;
+   caps->caps.v2.max_geom_total_output_components = 16384;
+   caps->caps.v2.max_vertex_outputs = 32;
+   caps->caps.v2.max_vertex_attribs = 16;
+   caps->caps.v2.max_shader_patch_varyings = 0;
+   caps->caps.v2.min_texel_offset = -8;
+   caps->caps.v2.max_texel_offset = 7;
+   caps->caps.v2.min_texture_gather_offset = -8;
+   caps->caps.v2.max_texture_gather_offset = 7;
+}
 #endif
diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c 
b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index fd6ae98a51..77854680e5 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -705,46 +705,28 @@ static int virgl_drm_get_caps(struct virgl_winsys *vws,
struct virgl_drm_winsys *vdws = virgl_drm_winsys(vws);
struct drm_virtgpu_get_caps args;
int ret;
-   bool fill_v2 = false;
 
-   memset(, 0, sizeof(args));
+   virgl_ws_fill_new_caps_defaults(caps);
 
-   args.cap_set_id = 1;
+   memset(, 0, sizeof(args));
+   if (vdws->has_capset_query_fix) {
+  /* if we have the query fix - try and get cap set id 2 first */
+  args.cap_set_id = 2;
+  args.size = sizeof(union virgl_caps);
+   } else {
+  args.cap_set_id = 1;
+  args.size = sizeof(struct virgl_caps_v1);
+   }
args.addr = (unsigned long)>caps;
-   args.size = sizeof(union virgl_caps);
 
ret = drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, );
-
if (ret == -1 && errno == EINVAL) {
   /* Fallback to v1 */
+  args.cap_set_id = 1;
   args.size = sizeof(struct virgl_caps_v1);
   ret = drmIoctl(vdws->fd, DRM_IOCTL_VIRTGPU_GET_CAPS, );
   if (ret == -1)
   return ret;
-  fill_v2 = true;
-   }
-   if (caps->caps.max_version == 1)
-   fill_v2 = true;
-
-   if (fill_v2) {
-  caps->caps.v2.min_aliased_point_size = 0.f;
-  caps->caps.v2.max_aliased_point_size = 255.f;
-  caps->caps.v2.min_smooth_point_size = 0.f;
-  caps->caps.v2.max_smooth_point_size = 255.f;
-  caps->caps.v2.min_aliased_line_width = 0.f;
-  caps->caps.v2.max_aliased_line_width = 255.f;
-  caps->caps.v2.min_smooth_line_width = 0.f;
-  caps->caps.v2.max_smooth_line_width = 255.f;
-  caps->caps.v2.max_texture_lod_bias = 16.0f;
-  caps->caps.v2.max_geom_output_vertices = 256;
-  caps->caps.v2.max_geom_total_output_components = 16384;
-  caps->caps.v2.max_vertex_outputs = 32;
-  caps->caps.v2.max_vertex_attribs = 16;
-  caps->caps.v2.max_shader_patch_varyings = 0;
-  caps->caps.v2.min_texel_offset = -8;
-  caps->caps.v2.max_texel_offset = 7;
-  caps->caps.v2.min_texture_gather_offset = -8;
-  caps->caps.v2.max_texture_gather_offset = 7;
}
return ret;
 }
@@ -813,6 +795,8 @@ static struct virgl_winsys *
 virgl_drm_winsys_create(int drmFD)
 {
struct virgl_drm_winsys *qdws;
+   int ret;
+   struct drm_virtgpu_g

Mesa (master): virgl: reduce some default capset limits.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9283cf2ad19b0eacc20b9aa5984bac077e9c475c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9283cf2ad19b0eacc20b9aa5984bac077e9c475c

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 21 11:48:05 2018 +1000

virgl: reduce some default capset limits.

Since v2 might take a while to rollout, we should reduce
these inside some gathered minimums and then v2 can increase
them using host values.

Reviewed-by: Stéphane Marchesin <marc...@chromium.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_winsys.h | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_winsys.h 
b/src/gallium/drivers/virgl/virgl_winsys.h
index d633678597..95e21a8afd 100644
--- a/src/gallium/drivers/virgl/virgl_winsys.h
+++ b/src/gallium/drivers/virgl/virgl_winsys.h
@@ -114,17 +114,17 @@ struct virgl_winsys {
  */
 static inline void virgl_ws_fill_new_caps_defaults(struct virgl_drm_caps *caps)
 {
-   caps->caps.v2.min_aliased_point_size = 0.f;
+   caps->caps.v2.min_aliased_point_size = 1.f;
caps->caps.v2.max_aliased_point_size = 255.f;
-   caps->caps.v2.min_smooth_point_size = 0.f;
-   caps->caps.v2.max_smooth_point_size = 255.f;
-   caps->caps.v2.min_aliased_line_width = 0.f;
-   caps->caps.v2.max_aliased_line_width = 255.f;
+   caps->caps.v2.min_smooth_point_size = 1.f;
+   caps->caps.v2.max_smooth_point_size = 190.f;
+   caps->caps.v2.min_aliased_line_width = 1.f;
+   caps->caps.v2.max_aliased_line_width = 10.f;
caps->caps.v2.min_smooth_line_width = 0.f;
-   caps->caps.v2.max_smooth_line_width = 255.f;
-   caps->caps.v2.max_texture_lod_bias = 16.0f;
+   caps->caps.v2.max_smooth_line_width = 10.f;
+   caps->caps.v2.max_texture_lod_bias = 15.0f;
caps->caps.v2.max_geom_output_vertices = 256;
-   caps->caps.v2.max_geom_total_output_components = 16384;
+   caps->caps.v2.max_geom_total_output_components = 1024;
caps->caps.v2.max_vertex_outputs = 32;
caps->caps.v2.max_vertex_attribs = 16;
caps->caps.v2.max_shader_patch_varyings = 0;

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Mesa (master): r600/cayman: fix fragcood loading recip generation.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: bf2af063c3ac1ef7b948ddfb203aea04f857fc0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf2af063c3ac1ef7b948ddfb203aea04f857fc0f

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar  1 03:38:32 2018 +

r600/cayman: fix fragcood loading recip generation.

This fixes some hangs seen where the recip_ieee opcodes would
end up split across the wrong slots.

Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 46eeb9021f..4b44f66141 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -3768,7 +3768,7 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
alu.dst.sel = 
shader->input[ctx.fragcoord_input].gpr;
alu.dst.chan = j;
alu.dst.write = (j == 3);
-   alu.last = 1;
+   alu.last = (j == 3);
if ((r = r600_bytecode_add_alu(ctx.bc, )))
return r;
}

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Mesa (master): radeonsi/nir: increase values to 8 for gs fetch.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6c1b5a40fde6f4ca77f8b866e99673b34df42116
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c1b5a40fde6f4ca77f8b866e99673b34df42116

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar  1 10:01:33 2018 +1000

radeonsi/nir: increase values to 8 for gs fetch.

This stops a crash when running (still fails):
tests/spec/arb_gpu_shader_fp64/execution/explicit-location-gs-fs-vs.shader_test

Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index d410a6c2d6..147bd9511d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -740,7 +740,7 @@ LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
 {
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 
-   LLVMValueRef value[4];
+   LLVMValueRef value[8];
for (unsigned i = component; i < num_components + component; i++) {
value[i] = si_llvm_load_input_gs(>abi, driver_location  / 
4,
 vertex_index, type, i);

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Mesa (master): ac/nir: don't apply slice rounding on txf_ms

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 69495b30a38fbb01a937cdea6f7674f89a2e60e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69495b30a38fbb01a937cdea6f7674f89a2e60e7

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar  1 09:24:01 2018 +1000

ac/nir: don't apply slice rounding on txf_ms

This matches the tgsi code.

Fixes arb_texture_multisample texelFetch piglit tests.

Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Fixes: f4e499ec7914 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 88e0cf9b4b..3c5be7e203 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5105,7 +5105,7 @@ static void visit_tex(struct ac_nir_context *ctx, 
nir_tex_instr *instr)
 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS ||
 instr->sampler_dim == GLSL_SAMPLER_DIM_SUBPASS_MS) 
&&
instr->is_array &&
-   instr->op != nir_texop_txf) {
+   instr->op != nir_texop_txf && instr->op != 
nir_texop_txf_ms) {
coords[2] = apply_round_slice(>ac, 
coords[2]);
}
address[count++] = coords[2];

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Mesa (master): ac/nir: fix shared atomic operations.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 49879f3778707e50b2b2d5968996d60557bd99d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49879f3778707e50b2b2d5968996d60557bd99d4

Author: Dave Airlie <airl...@redhat.com>
Date:   Thu Mar  1 09:38:19 2018 +1000

ac/nir: fix shared atomic operations.

The nir->llvm conversion was using the wrong srcs.

Fixes:
tests/spec/arb_compute_shader/execution/shared-atomics.shader_test

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3c5be7e203..afe17a8f11 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3991,10 +3991,10 @@ visit_store_shared(struct ac_nir_context *ctx,
 
 static LLVMValueRef visit_var_atomic(struct ac_nir_context *ctx,
 const nir_intrinsic_instr *instr,
-LLVMValueRef ptr)
+LLVMValueRef ptr, int src_idx)
 {
LLVMValueRef result;
-   LLVMValueRef src = get_src(ctx, instr->src[0]);
+   LLVMValueRef src = get_src(ctx, instr->src[src_idx]);
 
if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
@@ -4574,8 +4574,8 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_shared_atomic_xor:
case nir_intrinsic_shared_atomic_exchange:
case nir_intrinsic_shared_atomic_comp_swap: {
-   LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[1]);
-   result = visit_var_atomic(ctx, instr, ptr);
+   LLVMValueRef ptr = get_memory_ptr(ctx, instr->src[0]);
+   result = visit_var_atomic(ctx, instr, ptr, 1);
break;
}
case nir_intrinsic_var_atomic_add:
@@ -4589,7 +4589,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_var_atomic_exchange:
case nir_intrinsic_var_atomic_comp_swap: {
LLVMValueRef ptr = build_gep_for_deref(ctx, 
instr->variables[0]);
-   result = visit_var_atomic(ctx, instr, ptr);
+   result = visit_var_atomic(ctx, instr, ptr, 0);
break;
}
case nir_intrinsic_interp_var_at_centroid:

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Mesa (master): r600: fix whitespace in recent 1d texture commit.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 8369fdee8ba311aab6a6cf5e75f5f12f56469779
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8369fdee8ba311aab6a6cf5e75f5f12f56469779

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 28 20:15:30 2018 +

r600: fix whitespace in recent 1d texture commit.

trivial fix.

---

 src/gallium/drivers/r600/r600_texture.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/r600/r600_texture.c 
b/src/gallium/drivers/r600/r600_texture.c
index 1fbb682d67..fbcc878a24 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -1056,7 +1056,7 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
/* 1D textures should be linear - fixes image operations on 1d 
*/
if (templ->target == PIPE_TEXTURE_1D ||
templ->target == PIPE_TEXTURE_1D_ARRAY)
-   return RADEON_SURF_MODE_LINEAR_ALIGNED;
+   return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
/* Textures likely to be mapped often. */
if (templ->usage == PIPE_USAGE_STAGING ||

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Mesa (master): r600/shader: when using images always load thread id gpr at start (v2)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 7cb9353de38461c6492712b7b43ee69c57921705
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cb9353de38461c6492712b7b43ee69c57921705

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 28 06:42:53 2018 +

r600/shader: when using images always load thread id gpr at start (v2)

The delayed loading code was fail if we had control flow.

This fixes:
tests/spec/arb_shader_image_load_store/execution/image_checkerboard.shader_test

v2: don't use temp_reg before setting temp_reg up.

Tested-by: Gert Wollny <gw.foss...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 22 +++---
 1 file changed, 7 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index f2fc3f4c6f..46eeb9021f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -367,7 +367,6 @@ struct r600_shader_ctx {
unsignedtess_input_info; /* temp with 
tess input offsets */
unsignedtess_output_info; /* temp with 
tess input offsets */
unsignedthread_id_gpr; /* temp with 
thread id calculated for images */
-   bool thread_id_gpr_loaded;
 };
 
 struct r600_shader_tgsi_instruction {
@@ -3279,9 +3278,6 @@ static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
struct r600_bytecode_alu alu;
int r;
 
-   if (ctx->thread_id_gpr_loaded)
-   return 0;
-
memset(, 0, sizeof(struct r600_bytecode_alu));
alu.op = ALU_OP1_MBCNT_32LO_ACCUM_PREV_INT;
alu.dst.sel = ctx->temp_reg;
@@ -3326,7 +3322,6 @@ static int load_thread_id_gpr(struct r600_shader_ctx *ctx)
   ctx->temp_reg, 0);
if (r)
return r;
-   ctx->thread_id_gpr_loaded = true;
return 0;
 }
 
@@ -3434,12 +3429,12 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
ctx.gs_next_vertex = 0;
ctx.gs_stream_output_info = 
 
+   ctx.thread_id_gpr = -1;
ctx.face_gpr = -1;
ctx.fixed_pt_position_gpr = -1;
ctx.fragcoord_input = -1;
ctx.colors_used = 0;
ctx.clip_vertex_write = 0;
-   ctx.thread_id_gpr_loaded = false;
 
ctx.helper_invoc_reg = -1;
ctx.cs_block_size_reg = -1;
@@ -3573,7 +3568,6 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
 
if (shader->uses_images) {
ctx.thread_id_gpr = ++regno;
-   ctx.thread_id_gpr_loaded = false;
}
ctx.temp_reg = ++regno;
 
@@ -3616,6 +3610,12 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
if (shader->vs_as_gs_a)
vs_add_primid_output(, key.vs.prim_id_out);
 
+   if (ctx.thread_id_gpr != -1) {
+   r = load_thread_id_gpr();
+   if (r)
+   return r;
+   }
+
if (ctx.type == PIPE_SHADER_TESS_EVAL)
r600_fetch_tess_io_info();
 
@@ -8650,10 +8650,6 @@ static int tgsi_load_rat(struct r600_shader_ctx *ctx)
unsigned rat_index_mode;
unsigned immed_base;
 
-   r = load_thread_id_gpr(ctx);
-   if (r)
-   return r;
-
rat_index_mode = inst->Src[0].Indirect.Index == 2 ? 2 : 0; // 
CF_INDEX_1 : CF_INDEX_NONE
 
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
@@ -8981,10 +8977,6 @@ static int tgsi_atomic_op_rat(struct r600_shader_ctx 
*ctx)
immed_base = R600_IMAGE_IMMED_RESOURCE_OFFSET;
rat_base = ctx->shader->rat_base;
 
-   r = load_thread_id_gpr(ctx);
-   if (r)
-   return r;
-
 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
immed_base += ctx->info.file_count[TGSI_FILE_IMAGE];
rat_base += ctx->info.file_count[TGSI_FILE_IMAGE];

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Mesa (master): r600: partly revert disabling tiling for 1d texture.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: a5853a2d51382cae42397f353817e479
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5853a2d51382cae42397f353817e479

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 28 04:37:45 2018 +

r600: partly revert disabling tiling for 1d texture.

Previously we had a check for 1d of narrow 2D textures, however
narrow 2d textures caused gpu hangs, but it was correct for 1d
textures.

This fixes a bunch of 1D image piglits for me.

Fixes: 7b8e1c089d (r600/texture: drop lowering 1d/2d images to linear.)
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_texture.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_texture.c 
b/src/gallium/drivers/r600/r600_texture.c
index 03cdcd22ee..1fbb682d67 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -1053,6 +1053,11 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
if (templ->bind & PIPE_BIND_LINEAR)
return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
+   /* 1D textures should be linear - fixes image operations on 1d 
*/
+   if (templ->target == PIPE_TEXTURE_1D ||
+   templ->target == PIPE_TEXTURE_1D_ARRAY)
+   return RADEON_SURF_MODE_LINEAR_ALIGNED;
+
/* Textures likely to be mapped often. */
if (templ->usage == PIPE_USAGE_STAGING ||
templ->usage == PIPE_USAGE_STREAM)

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Mesa (master): ac/radv: move load base vertex abi setup to vertex shader.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: c7b25005a135199a84d3eec7cc96b6a789ece0b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7b25005a135199a84d3eec7cc96b6a789ece0b3

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 28 09:53:51 2018 +1000

ac/radv: move load base vertex abi setup to vertex shader.

This was segfaulting:
dEQP-VK.memory.pipeline_barrier.host_write_index_buffer.1024

Fixes: 8de6f797070 (ac/radeonsi: add load_base_vertex() to the abi)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 44d96d27d7..8b662f884f 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6920,7 +6920,6 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.gs_max_out_vertices = 
shaders[i]->info.gs.vertices_out;
ctx.abi.load_inputs = load_gs_input;
ctx.abi.emit_primitive = visit_end_primitive;
-   ctx.abi.load_base_vertex = radv_load_base_vertex;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read = 
shaders[i]->info.patch_outputs_read;
@@ -6944,6 +6943,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
MAX2(1, 
ctx.shader_info->vs.vgpr_comp_cnt);
}
}
+   ctx.abi.load_base_vertex = radv_load_base_vertex;
} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
shader_info->fs.can_discard = 
shaders[i]->info.fs.uses_discard;
ctx.abi.lookup_interp_param = lookup_interp_param;

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Mesa (master): ac/shader: fix vertex input with components.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 3401b028df1074a06a7fbc3fb1cda949646ef75d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3401b028df1074a06a7fbc3fb1cda949646ef75d

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 27 12:34:54 2018 +1000

ac/shader: fix vertex input with components.

This fixes:
dEQP-VK.glsl.440.linkage.varying.component.*

Fixes: 1c57a6da5e3 (ac/shader: scan vertex inputs usage mask)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_shader_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_shader_info.c b/src/amd/common/ac_shader_info.c
index 5ae8a72046..d76fecd244 100644
--- a/src/amd/common/ac_shader_info.c
+++ b/src/amd/common/ac_shader_info.c
@@ -141,7 +141,7 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
if (var->data.mode == nir_var_shader_in) {
unsigned idx = var->data.location;
uint8_t mask =
-   
nir_ssa_def_components_read(>dest.ssa);
+   
nir_ssa_def_components_read(>dest.ssa) << var->data.location_frac;
info->vs.input_usage_mask[idx] |= mask;
}
}

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Mesa (master): radv: remove device pointer from buffer.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6bafd4f4dd3b22a87bc904251bfe16db943176b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bafd4f4dd3b22a87bc904251bfe16db943176b1

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 27 14:31:31 2018 +1000

radv: remove device pointer from buffer.

This is never used.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_private.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 797bc8cd0a..c72df5a737 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -736,7 +736,6 @@ struct radv_descriptor_update_template {
 };
 
 struct radv_buffer {
-   struct radv_device *  device;
VkDeviceSize size;
 
VkBufferUsageFlags   usage;

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Mesa (master): radv: merge tess rings into a single bo

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 1fc19a0f274e83a4066d9ea0741ea854288f5a15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fc19a0f274e83a4066d9ea0741ea854288f5a15

Author: Dave Airlie <airl...@redhat.com>
Date:   Sun Feb 25 23:23:45 2018 +

radv: merge tess rings into a single bo

Inspired by a passing commit to radeonsi.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_device.c  | 92 ++-
 src/amd/vulkan/radv_private.h |  3 +-
 2 files changed, 39 insertions(+), 56 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index f197b7f484..763c4e41c8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1066,10 +1066,8 @@ radv_queue_finish(struct radv_queue *queue)
queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
if (queue->gsvs_ring_bo)
queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
-   if (queue->tess_factor_ring_bo)
-   queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
-   if (queue->tess_offchip_ring_bo)
-   queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
+   if (queue->tess_rings_bo)
+   queue->device->ws->buffer_destroy(queue->tess_rings_bo);
if (queue->compute_scratch_bo)
queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
 }
@@ -1396,22 +1394,22 @@ fill_geom_tess_rings(struct radv_queue *queue,
 uint32_t gsvs_ring_size,
 struct radeon_winsys_bo *gsvs_ring_bo,
 uint32_t tess_factor_ring_size,
-struct radeon_winsys_bo *tess_factor_ring_bo,
+uint32_t tess_offchip_ring_offset,
 uint32_t tess_offchip_ring_size,
-struct radeon_winsys_bo *tess_offchip_ring_bo)
+struct radeon_winsys_bo *tess_rings_bo)
 {
uint64_t esgs_va = 0, gsvs_va = 0;
-   uint64_t tess_factor_va = 0, tess_offchip_va = 0;
+   uint64_t tess_va = 0, tess_offchip_va = 0;
uint32_t *desc = [4];
 
if (esgs_ring_bo)
esgs_va = radv_buffer_get_va(esgs_ring_bo);
if (gsvs_ring_bo)
gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
-   if (tess_factor_ring_bo)
-   tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
-   if (tess_offchip_ring_bo)
-   tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
+   if (tess_rings_bo) {
+   tess_va = radv_buffer_get_va(tess_rings_bo);
+   tess_offchip_va = tess_va + tess_offchip_ring_offset;
+   }
 
/* stride 0, num records - size, add tid, swizzle, elsize4,
   index stride 64 */
@@ -1488,8 +1486,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
S_008F0C_ADD_TID_ENABLE(true);
desc += 4;
 
-   desc[0] = tess_factor_va;
-   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
+   desc[0] = tess_va;
+   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
S_008F04_STRIDE(0) |
S_008F04_SWIZZLE_ENABLE(false);
desc[2] = tess_factor_ring_size;
@@ -1598,13 +1596,13 @@ radv_get_preamble_cs(struct radv_queue *queue,
struct radeon_winsys_bo *compute_scratch_bo = NULL;
struct radeon_winsys_bo *esgs_ring_bo = NULL;
struct radeon_winsys_bo *gsvs_ring_bo = NULL;
-   struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
-   struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
+   struct radeon_winsys_bo *tess_rings_bo = NULL;
struct radeon_winsys_cs *dest_cs[3] = {0};
bool add_tess_rings = false, add_sample_positions = false;
unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
unsigned max_offchip_buffers;
unsigned hs_offchip_param = 0;
+   unsigned tess_offchip_ring_offset;
uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | 
RADEON_FLAG_NO_INTERPROCESS_SHARING;
if (!queue->has_tess_rings) {
if (needs_tess_rings)
@@ -1617,6 +1615,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
tess_factor_ring_size = 32768 * 
queue->device->physical_device->rad_info.max_se;
hs_offchip_param = radv_get_hs_offchip_param(queue->device,
 _offchip_buffers);
+   tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
tess_offchip_ring_size = max_offchip_buffers *
queue->device->tess_offchip_block_dw_size * 4;
 
@@ -1684,33 +1683,25 @@ radv_get_preamble_cs(struct radv_queue *

Mesa (master): radv: expose async compute on SI

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 250468f6b7bb85b6c0097120ec9860d9185fd03a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=250468f6b7bb85b6c0097120ec9860d9185fd03a

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 26 20:51:55 2018 +

radv: expose async compute on SI

It looks like we had all the pieces in place for this,
just never tested it and turned it on.

I don't see any CTS regressions and the computeshader
demo runs.

Acked-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 763c4e41c8..92865122ad 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -880,7 +880,6 @@ static void 
radv_get_physical_device_queue_family_properties(
int num_queue_families = 1;
int idx;
if (pdevice->rad_info.num_compute_rings > 0 &&
-   pdevice->rad_info.chip_class >= CIK &&
!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
num_queue_families++;
 
@@ -907,7 +906,6 @@ static void 
radv_get_physical_device_queue_family_properties(
}
 
if (pdevice->rad_info.num_compute_rings > 0 &&
-   pdevice->rad_info.chip_class >= CIK &&
!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
if (*pCount > idx) {
*pQueueFamilyProperties[idx] = 
(VkQueueFamilyProperties) {

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Mesa (master): r600: fix tgsi clock last setting

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 0cc5be7741aa77bd65046d627370c18839e0da25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cc5be7741aa77bd65046d627370c18839e0da25

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 26 11:05:45 2018 +1000

r600: fix tgsi clock last setting

On cayman this was hitting an assert later, which probably wasn't
see on non-cayman due to having the t slot.

Fixes: 9041730d1 (r600: add support for ARB_shader_clock.)

---

 src/gallium/drivers/r600/r600_shader.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 9f6780f219..f2fc3f4c6f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -10742,6 +10742,7 @@ static int tgsi_clock(struct r600_shader_ctx *ctx)
alu.op = ALU_OP1_MOV;
tgsi_dst(ctx, >Dst[0], 1, );
alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
+   alu.last = 1;
r = r600_bytecode_add_alu(ctx->bc, );
if (r)
return r;

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Mesa (master): r600: add time lo/hi debugging output.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 4d72a1efeaa2266cd8ea512d5d2279325d6e3807
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d72a1efeaa2266cd8ea512d5d2279325d6e3807

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 26 11:05:26 2018 +1000

r600: add time lo/hi debugging output.

This just adds the these to the debug prints.

---

 src/gallium/drivers/r600/r600_asm.c| 6 ++
 src/gallium/drivers/r600/sb/sb_bc_dump.cpp | 6 ++
 2 files changed, 12 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index fdccae8c04..427e7856d2 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2009,6 +2009,12 @@ static int print_src(struct r600_bytecode_alu *alu, 
unsigned idx)
o += fprintf(stderr, "LDS_OQ_B_POP");
need_chan = 1;
break;
+   case EG_V_SQ_ALU_SRC_TIME_LO:
+   o += fprintf(stderr, "TIME_LO");
+   break;
+   case EG_V_SQ_ALU_SRC_TIME_HI:
+   o += fprintf(stderr, "TIME_HI");
+   break;
case EG_V_SQ_ALU_SRC_SE_ID:
o += fprintf(stderr, "SE_ID");
break;
diff --git a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp 
b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
index a3acb21e2f..9b2674daf2 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
@@ -333,6 +333,12 @@ static void print_src(sb_ostream , bc_alu , unsigned 
idx)
case ALU_SRC_0:
s << "0";
break;
+   case ALU_SRC_TIME_LO:
+   s << "TIME_LO";
+   break;
+   case ALU_SRC_TIME_HI:
+   s << "TIME_HI";
+   break;
case ALU_SRC_MASK_LO:
s << "MASK_LO";
break;

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Mesa (master): r600: Take ALU_EXTENDED into account when evaluating jump offsets

[Dave Airlie]

Module: Mesa
Branch: master
Commit: c7cadcbda47537d474eea52b9e77e57ef9287f9b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7cadcbda47537d474eea52b9e77e57ef9287f9b

Author: Gert Wollny <gw.foss...@gmail.com>
Date:   Sat Feb 24 11:31:22 2018 +0100

r600: Take ALU_EXTENDED into account when evaluating jump offsets

ALU_EXTENDED needs 4 DWORDS instead of the usual 2, hence if the last ALU
clause within a IF-JUMP or ELSE branch is ALU_EXTENDED the target jump
offset needs to be adjusted accordingly.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104654
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Gert Wollny <gw.foss...@gmail.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index b49c79c040..9f6780f219 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -10409,17 +10409,22 @@ static int tgsi_else(struct r600_shader_ctx *ctx)
 
 static int tgsi_endif(struct r600_shader_ctx *ctx)
 {
+   int offset = 2;
pops(ctx, 1);
if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].type != FC_IF) {
R600_ERR("if/endif unbalanced in shader\n");
return -1;
}
 
+   /* ALU_EXTENDED needs 4 DWords instead of two, adjust jump target 
offset accordingly */
+   if (ctx->bc->cf_last->eg_alu_extended)
+   offset += 2;
+
if (ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid == NULL) {
-   ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = 
ctx->bc->cf_last->id + 2;
+   ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->cf_addr = 
ctx->bc->cf_last->id + offset;
ctx->bc->fc_stack[ctx->bc->fc_sp - 1].start->pop_count = 1;
} else {
-   ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = 
ctx->bc->cf_last->id + 2;
+   ctx->bc->fc_stack[ctx->bc->fc_sp - 1].mid[0]->cf_addr = 
ctx->bc->cf_last->id + offset;
}
fc_poplevel(ctx);
 

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Mesa (master): radv: don't send num_tcs_input_cp to sgprs.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: baa0feb73d0c011f3a2b29626244d3936532361e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=baa0feb73d0c011f3a2b29626244d3936532361e

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 04:59:53 2018 +

radv: don't send num_tcs_input_cp to sgprs.

We never use it in the shaders.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_pipeline.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index a2dec0e3bd..9990a3e863 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -68,7 +68,6 @@ struct radv_tessellation_state {
uint32_t offchip_layout;
unsigned num_patches;
unsigned lds_size;
-   unsigned num_tcs_input_cp;
uint32_t tf_param;
 };
 
@@ -1397,7 +1396,6 @@ calculate_tess_state(struct radv_pipeline *pipeline,
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
tess.num_patches = num_patches;
-   tess.num_tcs_input_cp = num_tcs_input_cp;
 
struct radv_shader_variant *tes = radv_get_tess_eval_shader(pipeline);
unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 
0;
@@ -2621,8 +2619,7 @@ radv_pipeline_generate_tess_shaders(struct 
radeon_winsys_cs *cs,
radeon_set_sh_reg_seq(cs, base_reg + loc->sgpr_idx * 4, 4);
radeon_emit(cs, tess->offchip_layout);
radeon_emit(cs, tess->tcs_out_offsets);
-   radeon_emit(cs, tess->tcs_out_layout |
-   tess->num_tcs_input_cp << 26);
+   radeon_emit(cs, tess->tcs_out_layout);
radeon_emit(cs, tess->tcs_in_layout);
}
 

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Mesa (master): ac/radv: remove total_vertices variable

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 0e6f0d400b9078262844de6664f5f83f6566b567
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e6f0d400b9078262844de6664f5f83f6566b567

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 06:53:21 2018 +

ac/radv: remove total_vertices variable

This just removes an unneeded variable.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1cea5486e4..88b1abd2ae 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2771,14 +2771,12 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct 
radv_shader_context *ctx,
LLVMValueRef vertex_index,
LLVMValueRef param_index)
 {
-   LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
+   LLVMValueRef base_addr, vertices_per_patch, num_patches;
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
 
vertices_per_patch = unpack_param(>ac, ctx->tcs_offchip_layout, 9, 
6);
num_patches = unpack_param(>ac, ctx->tcs_offchip_layout, 0, 9);
-   total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
- num_patches, "");
 
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
if (vertex_index) {
@@ -2788,7 +2786,8 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct 
radv_shader_context *ctx,
base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
 vertex_index, "");
 
-   param_stride = total_vertices;
+   param_stride = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
+   num_patches, "");
} else {
base_addr = rel_patch_id;
param_stride = num_patches;

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Mesa (master): ac/radv: don't mark tess inner as used if we don't use it.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e9b9fb36168cccdc6a1c14e86b4aec5321bd57e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9b9fb36168cccdc6a1c14e86b4aec5321bd57e0

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 20:33:17 2018 +

ac/radv: don't mark tess inner as used if we don't use it.

This just avoids marking it as a used output if we don't
actually use it.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 19 +++
 1 file changed, 11 insertions(+), 8 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 2185c53834..1cea5486e4 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6360,8 +6360,8 @@ write_tess_factors(struct radv_shader_context *ctx)
struct ac_build_if_state if_ctx, inner_if_ctx;
LLVMValueRef invocation_id = unpack_param(>ac, 
ctx->abi.tcs_rel_ids, 8, 5);
LLVMValueRef rel_patch_id = unpack_param(>ac, 
ctx->abi.tcs_rel_ids, 0, 8);
-   unsigned tess_inner_index, tess_outer_index;
-   LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
+   unsigned tess_inner_index = 0, tess_outer_index;
+   LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
int i;
emit_barrier(>ac, ctx->stage);
@@ -6390,14 +6390,17 @@ write_tess_factors(struct radv_shader_context *ctx)
LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
  invocation_id, ctx->ac.i32_0, ""));
 
-   tess_inner_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
-   tess_outer_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
+   lds_base = get_tcs_out_current_patch_data_offset(ctx);
+
+   if (inner_comps) {
+   tess_inner_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
+   mark_tess_output(ctx, true, tess_inner_index);
+   lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
+LLVMConstInt(ctx->ac.i32, 
tess_inner_index * 4, false), "");
+   }
 
-   mark_tess_output(ctx, true, tess_inner_index);
+   tess_outer_index = 
shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
mark_tess_output(ctx, true, tess_outer_index);
-   lds_base = get_tcs_out_current_patch_data_offset(ctx);
-   lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
-LLVMConstInt(ctx->ac.i32, tess_inner_index * 
4, false), "");
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
 LLVMConstInt(ctx->ac.i32, tess_outer_index * 
4, false), "");
 

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Mesa (master): ac/radv: cleanup some tcs output values access

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 77fd1b9187a3aec665257ced5e58fae6fc89290f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77fd1b9187a3aec665257ced5e58fae6fc89290f

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 06:19:07 2018 +

ac/radv: cleanup some tcs output values access

Just consolidates some code to make it easier to change.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 88b1abd2ae..ec4dd098ed 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -383,6 +383,12 @@ get_tcs_out_patch_stride(struct radv_shader_context *ctx)
 }
 
 static LLVMValueRef
+get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
+{
+   return unpack_param(>ac, ctx->tcs_out_layout, 13, 8);
+}
+
+static LLVMValueRef
 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
 {
return LLVMBuildMul(ctx->ac.builder,
@@ -2899,7 +2905,7 @@ load_tcs_varyings(struct ac_shader_abi *abi,
dw_addr = get_tcs_in_current_patch_offset(ctx);
} else {
if (!is_patch) {
-   stride = unpack_param(>ac, ctx->tcs_out_layout, 
13, 8);
+   stride = get_tcs_out_vertex_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
@@ -2955,7 +2961,7 @@ store_tcs_output(struct ac_shader_abi *abi,
}
 
if (!is_patch) {
-   stride = unpack_param(>ac, ctx->tcs_out_layout, 13, 8);
+   stride = get_tcs_out_vertex_stride(ctx);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);

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Mesa (master): radv/tess: don't need to look in constant for vertices_per_patch

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 95ddd423bce3b6e836f3ae305cbad0622e22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=95ddd423bce3b6e836f3ae305cbad0622e22

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 19 04:55:52 2018 +

radv/tess: don't need to look in constant for vertices_per_patch

This just avoids passing this value via user sgprs.

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 5 -
 src/amd/vulkan/radv_pipeline.c  | 2 +-
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index ec4dd098ed..351e6fa9ef 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -127,6 +127,7 @@ struct radv_shader_context {
 
uint32_t tcs_patch_outputs_read;
uint64_t tcs_outputs_read;
+   uint32_t tcs_vertices_per_patch;
 };
 
 static inline struct radv_shader_context *
@@ -2781,7 +2782,7 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct 
radv_shader_context *ctx,
LLVMValueRef param_stride, constant16;
LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
 
-   vertices_per_patch = unpack_param(>ac, ctx->tcs_offchip_layout, 9, 
6);
+   vertices_per_patch = LLVMConstInt(ctx->ac.i32, 
ctx->tcs_vertices_per_patch, false);
num_patches = unpack_param(>ac, ctx->tcs_offchip_layout, 0, 9);
 
constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
@@ -6905,11 +6906,13 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.abi.load_tess_varyings = load_tcs_varyings;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
+   ctx.tcs_vertices_per_patch = 
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_varyings = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
+   ctx.tcs_vertices_per_patch = 
shaders[i]->info.tess.tcs_vertices_out;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.options->key.vs.as_ls) {
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 88646fda2f..a2dec0e3bd 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1391,7 +1391,7 @@ calculate_tess_state(struct radv_pipeline *pipeline,
tess.tcs_out_offsets = (output_patch0_offset / 16) |
((perpatch_output_offset / 16) << 16);
tess.offchip_layout = (pervertex_output_patch_size * num_patches << 16) 
|
-   (num_tcs_output_cp << 9) | num_patches;
+   num_patches;
 
tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |

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Mesa (master): ac/nir: to integer the args to bcsel.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: d5b2d7ed670e6b6a2d7a96e588cb3de852d0b289
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b2d7ed670e6b6a2d7a96e588cb3de852d0b289

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 20 10:15:18 2018 +1000

ac/nir: to integer the args to bcsel.

dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw
was hitting an llvm assert due to one value being an int and the
other a float.

This just casts both values to integer and fixes the test.

Fixes: 
dEQP-VK.tessellation.invariance.outer_edge_symmetry.triangles_equal_spacing_ccw
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/common/ac_nir_to_llvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 12f097e2b2..2185c53834 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1314,7 +1314,8 @@ static LLVMValueRef emit_bcsel(struct ac_llvm_context 
*ctx,
 {
LLVMValueRef v = LLVMBuildICmp(ctx->builder, LLVMIntNE, src0,
   ctx->i32_0, "");
-   return LLVMBuildSelect(ctx->builder, v, src1, src2, "");
+   return LLVMBuildSelect(ctx->builder, v, ac_to_integer(ctx, src1),
+  ac_to_integer(ctx, src2), "");
 }
 
 static LLVMValueRef emit_minmax_int(struct ac_llvm_context *ctx,

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Mesa (master): virgl: remap query types to hw support.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 60c14a0db25d3dd246744858179a52548325c25f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=60c14a0db25d3dd246744858179a52548325c25f

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 14 12:52:27 2018 +1000

virgl: remap query types to hw support.

The gallium query types changed, so we need to remap from the
gallium ones to the virgl ones.

Fixes:
dEQP-GLES3.functional.transform_feedback.basic_types*

"This also fixes:

dEQP-GLES3.functional.transform_feedback.array.separate*
dEQP-GLES3.functional.transform_feedback.array_element*
dEQP-GLES3.functional.transform_feedback.interpolation.*

Gallium's p_defines.h and virglrenderer's p_defines.h have diverged
quite a bit, so not including
PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE there makes sense for now."
 - Gurchetan Singh

Fixes: 3f6b3d9db (gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
Reviewed-by: Gurchetan Singh <gurchetansi...@chromium.org>
Tested-by: Gurchetan Singh <gurchetansi...@chromium.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_query.c | 37 +++--
 1 file changed, 35 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_query.c 
b/src/gallium/drivers/virgl/virgl_query.c
index e6ca4609c0..3a930d2966 100644
--- a/src/gallium/drivers/virgl/virgl_query.c
+++ b/src/gallium/drivers/virgl/virgl_query.c
@@ -37,6 +37,39 @@ struct virgl_query {
unsigned result_size;
unsigned result_gotten_sent;
 };
+#define VIRGL_QUERY_OCCLUSION_COUNTER 0
+#define VIRGL_QUERY_OCCLUSION_PREDICATE   1
+#define VIRGL_QUERY_TIMESTAMP 2
+#define VIRGL_QUERY_TIMESTAMP_DISJOINT3
+#define VIRGL_QUERY_TIME_ELAPSED  4
+#define VIRGL_QUERY_PRIMITIVES_GENERATED  5
+#define VIRGL_QUERY_PRIMITIVES_EMITTED6
+#define VIRGL_QUERY_SO_STATISTICS 7
+#define VIRGL_QUERY_SO_OVERFLOW_PREDICATE 8
+#define VIRGL_QUERY_GPU_FINISHED  9
+#define VIRGL_QUERY_PIPELINE_STATISTICS  10
+
+static const int pquery_map[] =
+{
+   VIRGL_QUERY_OCCLUSION_COUNTER,
+   VIRGL_QUERY_OCCLUSION_PREDICATE,
+   -1,
+   VIRGL_QUERY_TIMESTAMP,
+   VIRGL_QUERY_TIMESTAMP_DISJOINT,
+   VIRGL_QUERY_TIME_ELAPSED,
+   VIRGL_QUERY_PRIMITIVES_GENERATED,
+   VIRGL_QUERY_PRIMITIVES_EMITTED,
+   VIRGL_QUERY_SO_STATISTICS,
+   VIRGL_QUERY_SO_OVERFLOW_PREDICATE,
+   -1,
+   VIRGL_QUERY_GPU_FINISHED,
+   VIRGL_QUERY_PIPELINE_STATISTICS,
+};
+
+static int pipe_to_virgl_query(enum pipe_query_type ptype)
+{
+   return pquery_map[ptype];
+}
 
 static inline struct virgl_query *virgl_query(struct pipe_query *q)
 {
@@ -75,11 +108,11 @@ static struct pipe_query *virgl_create_query(struct 
pipe_context *ctx,
}
 
handle = virgl_object_assign_handle();
-   query->type = query_type;
+   query->type = pipe_to_virgl_query(query_type);
query->index = index;
query->handle = handle;
query->buf->clean = FALSE;
-   virgl_encoder_create_query(vctx, handle, query_type, index, query->buf, 0);
+   virgl_encoder_create_query(vctx, handle, query->type, index, query->buf, 0);
 
return (struct pipe_query *)query;
 }

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Mesa (master): r600: fix regression in gl_FragColor drawing

[Dave Airlie]

Module: Mesa
Branch: master
Commit: b9d2ff05a64f751f5814314b2cce45e6270ddf7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9d2ff05a64f751f5814314b2cce45e6270ddf7f

Author: Dave Airlie <airl...@redhat.com>
Date:   Wed Feb 14 13:59:09 2018 +1000

r600: fix regression in gl_FragColor drawing

This fixes a regression in the broadcast color to all color bufs case.

Fixes: 6c691081a (r600: fixup sparse color exports.)
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 7d60bd90c3..b49c79c040 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -4123,6 +4123,8 @@ static int r600_shader_from_tgsi(struct r600_context 
*rctx,
output[j].op = 
CF_OP_EXPORT;
output[j].type = 
V_SQ_CF_ALLOC_EXPORT_WORD0_SQ_EXPORT_PIXEL;

shader->nr_ps_color_exports++;
+   if (k > 
shader->ps_export_highest)
+   
shader->ps_export_highest = k;

shader->ps_color_export_mask |= (0xf << (j * 4));
}
}

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Mesa (master): r600: fix array spill if temp[0] is before all arrays

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9c9a9bee4431124439c57a9429e745dd4837fcdf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c9a9bee4431124439c57a9429e745dd4837fcdf

Author: Dave Airlie <airl...@redhat.com>
Date:   Mon Feb 12 14:46:50 2018 +1000

r600: fix array spill if temp[0] is before all arrays

I found a shader with
DCL TEMP[0], LOCAL
DCL TEMP[1..256], ARRAY(1), LOCAL
DCL TEMP[257..512], ARRAY(2), LOCAL
DCL TEMP[513..768], ARRAY(3), LOCAL
DCL TEMP[769], LOCAL

This would remap badly, as it would add up all the spilled sizes
and subtract it from the temp for 0. If the current temp is less
than the array start break out.

Fixes: 1d871aa6 (r600g: Implement spilling of temp arrays (v2))
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/r600/r600_shader.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 4141e86430..7d60bd90c3 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -920,6 +920,8 @@ static int map_tgsi_reg_index_to_r600_gpr(struct 
r600_shader_ctx *ctx, unsigned
}
}
 
+   if (tgsi_reg_index < ctx->array_infos[i].range.First)
+   break;
if (ctx->spilled_arrays[i]) {
spilled_size += ctx->array_infos[i].range.Last - 
ctx->array_infos[i].range.First + 1;
}

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Mesa (master): virgl: add ARB_sample_shading support.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 8f2656c75b8e91a8e90755280845d0e278a62ab4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f2656c75b8e91a8e90755280845d0e278a62ab4

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 13 14:08:14 2018 +1000

virgl: add ARB_sample_shading support.

This enable ARB_sample_shading if the renderer supports it.

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_encode.c   | 3 ++-
 src/gallium/drivers/virgl/virgl_protocol.h | 1 +
 src/gallium/drivers/virgl/virgl_screen.c   | 5 +++--
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index 2ee8eac771..80e60bc284 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -180,7 +180,8 @@ int virgl_encode_rasterizer_state(struct virgl_context *ctx,
   VIRGL_OBJ_RS_S0_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
   VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(state->line_last_pixel) |
   VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(state->half_pixel_center) |
-  VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule);
+  VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(state->bottom_edge_rule) |
+  VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(state->force_persample_interp);
 
virgl_encoder_write_dword(ctx->cbuf, tmp); /* S0 */
virgl_encoder_write_dword(ctx->cbuf, fui(state->point_size)); /* S1 */
diff --git a/src/gallium/drivers/virgl/virgl_protocol.h 
b/src/gallium/drivers/virgl/virgl_protocol.h
index 1430422b9c..7688ac5e8e 100644
--- a/src/gallium/drivers/virgl/virgl_protocol.h
+++ b/src/gallium/drivers/virgl/virgl_protocol.h
@@ -181,6 +181,7 @@ enum virgl_context_cmd {
 #define VIRGL_OBJ_RS_S0_LINE_LAST_PIXEL(x) (((x) & 0x1) << 28)
 #define VIRGL_OBJ_RS_S0_HALF_PIXEL_CENTER(x) (((x) & 0x1) << 29)
 #define VIRGL_OBJ_RS_S0_BOTTOM_EDGE_RULE(x) (((x) & 0x1) << 30)
+#define VIRGL_OBJ_RS_S0_FORCE_PERSAMPLE_INTERP(x) (((x) & 0x1) << 31)
 
 #define VIRGL_OBJ_RS_POINT_SIZE 3
 #define VIRGL_OBJ_RS_SPRITE_COORD_ENABLE 4
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index 2af621ec2d..f4f3195ce3 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -193,9 +193,11 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
   return vscreen->caps.caps.v1.max_texture_gather_components;
case PIPE_CAP_DRAW_INDIRECT:
   return vscreen->caps.caps.v1.bset.has_indirect_draw;
+   case PIPE_CAP_SAMPLE_SHADING:
+   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
+  return vscreen->caps.caps.v1.bset.has_sample_shading;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
-   case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
@@ -217,7 +219,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_DEPTH_BOUNDS_TEST:
case PIPE_CAP_TGSI_TXQS:
-   case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
case PIPE_CAP_SHAREABLE_SHADERS:
case PIPE_CAP_CLEAR_TEXTURE:
case PIPE_CAP_DRAW_PARAMETERS:

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Mesa (master): virgl: add ARB_draw_indirect support.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9b95b70719bfd19e57a8ae89065eac84f513d297
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b95b70719bfd19e57a8ae89065eac84f513d297

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 13 13:57:28 2018 +1000

virgl: add ARB_draw_indirect support.

This relies on the renderer code landing first.

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_encode.c   | 15 ++-
 src/gallium/drivers/virgl/virgl_protocol.h | 12 
 src/gallium/drivers/virgl/virgl_screen.c   |  3 ++-
 3 files changed, 28 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_encode.c 
b/src/gallium/drivers/virgl/virgl_encode.c
index ee68fe068f..2ee8eac771 100644
--- a/src/gallium/drivers/virgl/virgl_encode.c
+++ b/src/gallium/drivers/virgl/virgl_encode.c
@@ -417,7 +417,10 @@ int virgl_encoder_set_index_buffer(struct virgl_context 
*ctx,
 int virgl_encoder_draw_vbo(struct virgl_context *ctx,
   const struct pipe_draw_info *info)
 {
-   virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, 
VIRGL_DRAW_VBO_SIZE));
+   uint32_t length = VIRGL_DRAW_VBO_SIZE;
+   if (info->indirect)
+  length = VIRGL_DRAW_VBO_SIZE_INDIRECT;
+   virgl_encoder_write_cmd_dword(ctx, VIRGL_CMD0(VIRGL_CCMD_DRAW_VBO, 0, 
length));
virgl_encoder_write_dword(ctx->cbuf, info->start);
virgl_encoder_write_dword(ctx->cbuf, info->count);
virgl_encoder_write_dword(ctx->cbuf, info->mode);
@@ -433,6 +436,16 @@ int virgl_encoder_draw_vbo(struct virgl_context *ctx,
   virgl_encoder_write_dword(ctx->cbuf, 
info->count_from_stream_output->buffer_size);
else
   virgl_encoder_write_dword(ctx->cbuf, 0);
+   if (length == VIRGL_DRAW_VBO_SIZE_INDIRECT) {
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* vertices per patch */
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* drawid */
+  virgl_encoder_write_res(ctx, virgl_resource(info->indirect->buffer));
+  virgl_encoder_write_dword(ctx->cbuf, info->indirect->offset);
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect stride */
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count */
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count offset */
+  virgl_encoder_write_dword(ctx->cbuf, 0); /* indirect draw count handle */
+   }
return 0;
 }
 
diff --git a/src/gallium/drivers/virgl/virgl_protocol.h 
b/src/gallium/drivers/virgl/virgl_protocol.h
index a2f1e81830..1430422b9c 100644
--- a/src/gallium/drivers/virgl/virgl_protocol.h
+++ b/src/gallium/drivers/virgl/virgl_protocol.h
@@ -275,6 +275,8 @@ enum virgl_context_cmd {
 
 /* draw VBO */
 #define VIRGL_DRAW_VBO_SIZE 12
+#define VIRGL_DRAW_VBO_SIZE_TESS 14
+#define VIRGL_DRAW_VBO_SIZE_INDIRECT 20
 #define VIRGL_DRAW_VBO_START 1
 #define VIRGL_DRAW_VBO_COUNT 2
 #define VIRGL_DRAW_VBO_MODE 3
@@ -287,6 +289,16 @@ enum virgl_context_cmd {
 #define VIRGL_DRAW_VBO_MIN_INDEX 10
 #define VIRGL_DRAW_VBO_MAX_INDEX 11
 #define VIRGL_DRAW_VBO_COUNT_FROM_SO 12
+/* tess packet */
+#define VIRGL_DRAW_VBO_VERTICES_PER_PATCH 13
+#define VIRGL_DRAW_VBO_DRAWID 14
+/* indirect packet */
+#define VIRGL_DRAW_VBO_INDIRECT_HANDLE 15
+#define VIRGL_DRAW_VBO_INDIRECT_OFFSET 16
+#define VIRGL_DRAW_VBO_INDIRECT_STRIDE 17
+#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT 18
+#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_OFFSET 19
+#define VIRGL_DRAW_VBO_INDIRECT_DRAW_COUNT_HANDLE 20
 
 /* create surface */
 #define VIRGL_OBJ_SURFACE_SIZE 5
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index ae062917e6..2af621ec2d 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -191,6 +191,8 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
   return vscreen->caps.caps.v1.bset.texture_query_lod;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
   return vscreen->caps.caps.v1.max_texture_gather_components;
+   case PIPE_CAP_DRAW_INDIRECT:
+  return vscreen->caps.caps.v1.bset.has_indirect_draw;
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_SAMPLE_SHADING:
@@ -198,7 +200,6 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_MAX_VERTEX_STREAMS:
-   case PIPE_CAP_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:

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Mesa (master): gallium: drop all the guard band float caps.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 9ddacd9af488485bfc5da1797e67ff322080c0d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ddacd9af488485bfc5da1797e67ff322080c0d4

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Feb 13 05:21:12 2018 +1000

gallium: drop all the guard band float caps.

Nobody queries these and nobody sets them to anything useful,
the docs say TODO.

Drop them until a use appears.

Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/docs/source/screen.rst   | 4 
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 5 -
 src/gallium/drivers/freedreno/freedreno_screen.c | 5 -
 src/gallium/drivers/llvmpipe/lp_screen.c | 5 -
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 6 --
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 6 --
 src/gallium/drivers/r300/r300_screen.c   | 5 -
 src/gallium/drivers/r600/r600_pipe_common.c  | 5 -
 src/gallium/drivers/radeonsi/si_get.c| 5 -
 src/gallium/drivers/softpipe/sp_screen.c | 5 -
 src/gallium/drivers/svga/svga_screen.c   | 5 -
 src/gallium/drivers/swr/swr_screen.cpp   | 5 -
 src/gallium/drivers/vc4/vc4_screen.c | 5 -
 src/gallium/drivers/vc5/vc5_screen.c | 5 -
 src/gallium/drivers/virgl/virgl_screen.c | 5 -
 src/gallium/include/pipe/p_defines.h | 4 
 16 files changed, 80 deletions(-)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index cb3418fce3..95b6253449 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -431,10 +431,6 @@ The floating-point capabilities are:
   applied to anisotropically filtered textures.
 * ``PIPE_CAPF_MAX_TEXTURE_LOD_BIAS``: The maximum :term:`LOD` bias that may be 
applied
   to filtered textures.
-* ``PIPE_CAPF_GUARD_BAND_LEFT``,
-  ``PIPE_CAPF_GUARD_BAND_TOP``,
-  ``PIPE_CAPF_GUARD_BAND_RIGHT``,
-  ``PIPE_CAPF_GUARD_BAND_BOTTOM``: TODO
 
 
 .. _pipe_shader_cap:
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index d5d1f4fdad..16b58d3f03 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -367,11 +367,6 @@ etna_screen_get_paramf(struct pipe_screen *pscreen, enum 
pipe_capf param)
   return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
   return util_last_bit(screen->specs.max_texture_size);
-   case PIPE_CAPF_GUARD_BAND_LEFT:
-   case PIPE_CAPF_GUARD_BAND_TOP:
-   case PIPE_CAPF_GUARD_BAND_RIGHT:
-   case PIPE_CAPF_GUARD_BAND_BOTTOM:
-  return 0.0f;
}
 
debug_printf("unknown paramf %d", param);
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 438817d003..eb5c436e10 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -476,11 +476,6 @@ fd_screen_get_paramf(struct pipe_screen *pscreen, enum 
pipe_capf param)
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return 15.0f;
-   case PIPE_CAPF_GUARD_BAND_LEFT:
-   case PIPE_CAPF_GUARD_BAND_TOP:
-   case PIPE_CAPF_GUARD_BAND_RIGHT:
-   case PIPE_CAPF_GUARD_BAND_BOTTOM:
-   return 0.0f;
}
debug_printf("unknown paramf %d\n", param);
return 0;
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index b46ea06775..439e15bc1a 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -420,11 +420,6 @@ llvmpipe_get_paramf(struct pipe_screen *screen, enum 
pipe_capf param)
   return 16.0; /* not actually signficant at this time */
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
   return 16.0; /* arbitrary */
-   case PIPE_CAPF_GUARD_BAND_LEFT:
-   case PIPE_CAPF_GUARD_BAND_TOP:
-   case PIPE_CAPF_GUARD_BAND_RIGHT:
-   case PIPE_CAPF_GUARD_BAND_BOTTOM:
-  return 0.0;
}
/* should only get here on unhandled cases */
debug_printf("Unexpected PIPE_CAP %d query\n", param);
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 4c13d04eb7..5c006e6be7 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -396,12 +396,6 @@ nv50_screen_get_paramf(struct pipe_screen *pscreen, enum 
pipe_capf param)
   return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
   return 4.0f;
-   case PIPE_CAPF_GUARD_BAND_LEFT:
-   case PIPE_CAPF_GUARD_BAND_TOP:
-  return 0.0f;
-   case PIPE_CAPF_GUARD_BAND_RIGHT:
-   case PIPE_CAPF_GUARD_BAND_BOTTOM:
-  return 0.0f; /* that or infinity */
}
 
NOUVEAU_ERR("unknown P

Mesa (master): virgl: Support v2 caps struct (v2)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 5e4a2b394eb03d5b49df8d3f2263c65b24ad2bb9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e4a2b394eb03d5b49df8d3f2263c65b24ad2bb9

Author: Stéphane Marchesin <marc...@chromium.org>
Date:   Fri Feb  9 17:21:59 2018 -0800

virgl: Support v2 caps struct (v2)

This struct allows us to report:
- accurate max point size/line width.
- accurate texel and texture gather offsets
- vertex/geometry limits.

Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/gallium/drivers/virgl/virgl_hw.h| 28 ++
 src/gallium/drivers/virgl/virgl_screen.c| 29 +++
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 38 -
 3 files changed, 82 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/virgl/virgl_hw.h 
b/src/gallium/drivers/virgl/virgl_hw.h
index e3c56db2ac..833ab91eee 100644
--- a/src/gallium/drivers/virgl/virgl_hw.h
+++ b/src/gallium/drivers/virgl/virgl_hw.h
@@ -232,6 +232,11 @@ struct virgl_caps_bool_set1 {
 unsigned poly_stipple:1; /* not in GL 3.1 core profile */
 unsigned mirror_clamp:1;
 unsigned texture_query_lod:1;
+unsigned has_fp64:1;
+unsigned has_tessellation_shaders:1;
+unsigned has_indirect_draw:1;
+unsigned has_sample_shading:1;
+unsigned has_cull:1;
 };
 
 /* endless expansion capabilites - current gallium has 252 formats */
@@ -259,9 +264,32 @@ struct virgl_caps_v1 {
 uint32_t max_texture_gather_components;
 };
 
+struct virgl_caps_v2 {
+struct virgl_caps_v1 v1;
+float min_aliased_point_size;
+float max_aliased_point_size;
+float min_smooth_point_size;
+float max_smooth_point_size;
+float min_aliased_line_width;
+float max_aliased_line_width;
+float min_smooth_line_width;
+float max_smooth_line_width;
+float max_texture_lod_bias;
+uint32_t max_geom_output_vertices;
+uint32_t max_geom_total_output_components;
+uint32_t max_vertex_outputs;
+uint32_t max_vertex_attribs;
+uint32_t max_shader_patch_varyings;
+int32_t min_texel_offset;
+int32_t max_texel_offset;
+int32_t min_texture_gather_offset;
+int32_t max_texture_gather_offset;
+};
+
 union virgl_caps {
 uint32_t max_version;
 struct virgl_caps_v1 v1;
+struct virgl_caps_v2 v2;
 };
 
 enum virgl_errors {
diff --git a/src/gallium/drivers/virgl/virgl_screen.c 
b/src/gallium/drivers/virgl/virgl_screen.c
index ca73b90e0f..72dce08c28 100644
--- a/src/gallium/drivers/virgl/virgl_screen.c
+++ b/src/gallium/drivers/virgl/virgl_screen.c
@@ -113,11 +113,13 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
   return vscreen->caps.caps.v1.max_texture_array_layers;
case PIPE_CAP_MIN_TEXEL_OFFSET:
+  return vscreen->caps.caps.v2.min_texel_offset;
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
-  return -8;
+  return vscreen->caps.caps.v2.min_texture_gather_offset;
case PIPE_CAP_MAX_TEXEL_OFFSET:
+  return vscreen->caps.caps.v2.max_texel_offset;
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
-  return 7;
+  return vscreen->caps.caps.v2.max_texture_gather_offset;
case PIPE_CAP_CONDITIONAL_RENDER:
   return vscreen->caps.caps.v1.bset.conditional_render;
case PIPE_CAP_TEXTURE_BARRIER:
@@ -182,9 +184,9 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
   return 0;
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
-  return 256;
+  return vscreen->caps.caps.v2.max_geom_output_vertices;
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
-  return 16384;
+  return vscreen->caps.caps.v2.max_geom_total_output_components;
case PIPE_CAP_TEXTURE_QUERY_LOD:
   return vscreen->caps.caps.v1.bset.texture_query_lod;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
@@ -310,11 +312,13 @@ virgl_get_shader_param(struct pipe_screen *screen,
  return 1;
   case PIPE_SHADER_CAP_MAX_INPUTS:
  if (vscreen->caps.caps.v1.glsl_level < 150)
-return 16;
+return vscreen->caps.caps.v2.max_vertex_attribs;
  return (shader == PIPE_SHADER_VERTEX ||
- shader == PIPE_SHADER_GEOMETRY) ? 16 : 32;
+ shader == PIPE_SHADER_GEOMETRY) ? 
vscreen->caps.caps.v2.max_vertex_attribs : 32;
   case PIPE_SHADER_CAP_MAX_OUTPUTS:
- return 32;
+ if (shader == PIPE_SHADER_FRAGMENT)
+return vscreen->caps.caps.v1.max_render_targets;
+ return vscreen->caps.caps.v2.max_vertex_outputs;
  // case PIPE_SHADER_CAP_MAX_CONSTS:
  //return 4096;
   case PIPE_SHADER_CAP_MAX_TEMPS:
@@ -350,19 +354,20 @@ virgl_get_shader_param(struct pipe_screen *screen,
 static float
 vi