Mesa (master): i965: Stop passing num_samples to intel_miptree_alloc_hiz().

[Paul Berry]

Module: Mesa
Branch: master
Commit: bdf13dc8324c391b7d34f8bdaea72c4452ab7edb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdf13dc8324c391b7d34f8bdaea72c4452ab7edb

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Apr 25 10:57:48 2013 -0700

i965: Stop passing num_samples to intel_miptree_alloc_hiz().

The number of samples is already available in the miptree data
structure, so there's no need to pass it in.

I suspect this may fix a subtle bug because in one case
(intel_renderbuffer_update_wrapper) we were always passing zero for
num_samples, even though the buffer in question was not guaranteed to
be single-sampled.  But I wasn't able to find a failing test case.

Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/intel/intel_fbo.c |4 ++--
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |7 +++
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h |3 +--
 3 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c 
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 15d3918..6730d26 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -526,7 +526,7 @@ intel_renderbuffer_update_wrapper(struct intel_context 
*intel,
 
if (mt-hiz_mt == NULL 
intel-vtbl.is_hiz_depth_format(intel, rb-Format)) {
-  intel_miptree_alloc_hiz(intel, mt, 0 /* num_samples */);
+  intel_miptree_alloc_hiz(intel, mt);
   if (!mt-hiz_mt)
 return false;
}
@@ -1025,7 +1025,7 @@ intel_renderbuffer_move_to_temp(struct intel_context 
*intel,
  false /* force_y_tiling */);
 
if (intel-vtbl.is_hiz_depth_format(intel, new_mt-format)) {
-  intel_miptree_alloc_hiz(intel, new_mt, irb-mt-num_samples);
+  intel_miptree_alloc_hiz(intel, new_mt);
}
 
intel_miptree_copy_teximage(intel, intel_image, new_mt, invalidate);
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 12a4a22..c5f9f1f 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -573,7 +573,7 @@ intel_miptree_create_for_renderbuffer(struct intel_context 
*intel,
   goto fail;
 
if (intel-vtbl.is_hiz_depth_format(intel, format)) {
-  ok = intel_miptree_alloc_hiz(intel, mt, num_samples);
+  ok = intel_miptree_alloc_hiz(intel, mt);
   if (!ok)
  goto fail;
}
@@ -1066,8 +1066,7 @@ intel_miptree_slice_enable_hiz(struct intel_context 
*intel,
 
 bool
 intel_miptree_alloc_hiz(struct intel_context *intel,
-   struct intel_mipmap_tree *mt,
-GLuint num_samples)
+   struct intel_mipmap_tree *mt)
 {
assert(mt-hiz_mt == NULL);
mt-hiz_mt = intel_miptree_create(intel,
@@ -1079,7 +1078,7 @@ intel_miptree_alloc_hiz(struct intel_context *intel,
  mt-logical_height0,
  mt-logical_depth0,
  true,
- num_samples,
+ mt-num_samples,
  false /* force_y_tiling */);
 
if (!mt-hiz_mt)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 29cd09d..b7376e0 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -540,8 +540,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
 
 bool
 intel_miptree_alloc_hiz(struct intel_context *intel,
-   struct intel_mipmap_tree *mt,
-GLuint num_samples);
+   struct intel_mipmap_tree *mt);
 
 bool
 intel_miptree_slice_has_hiz(struct intel_mipmap_tree *mt,

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Mesa (master): glsl: Fix make check breakage after adding options to do_common_optimization.

[Paul Berry]

Module: Mesa
Branch: master
Commit: b0bb6103d23c16d23b0ec617746b4b0d1c22075d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0bb6103d23c16d23b0ec617746b4b0d1c22075d

Author: Paul Berry stereotype...@gmail.com
Date:   Mon May 13 07:52:08 2013 -0700

glsl: Fix make check breakage after adding options to do_common_optimization.

Commit b765740 (glsl: Pass struct shader_compiler_options into
do_common_optimization.) added a new parameter to
do_common_optimization() but didn't update test_optpass.cpp, causing
make check to break.

This patch makes the proper updates to test_optpass.cpp so that the
build succeeds again.

---

 src/glsl/test_optpass.cpp |   14 +-
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/src/glsl/test_optpass.cpp b/src/glsl/test_optpass.cpp
index 117b0b0..fc10cbbd 100644
--- a/src/glsl/test_optpass.cpp
+++ b/src/glsl/test_optpass.cpp
@@ -54,7 +54,8 @@ static string read_stdin_to_eof()
 }
 
 static GLboolean
-do_optimization(struct exec_list *ir, const char *optimization)
+do_optimization(struct exec_list *ir, const char *optimization,
+const struct gl_shader_compiler_options *options)
 {
int int_0;
int int_1;
@@ -64,7 +65,7 @@ do_optimization(struct exec_list *ir, const char 
*optimization)
 
if (sscanf(optimization, do_common_optimization ( %d , %d ) ,
   int_0, int_1) == 2) {
-  return do_common_optimization(ir, int_0 != 0, false, int_1);
+  return do_common_optimization(ir, int_0 != 0, false, int_1, options);
} else if (strcmp(optimization, do_algebraic) == 0) {
   return do_algebraic(ir);
} else if (strcmp(optimization, do_constant_folding) == 0) {
@@ -141,7 +142,8 @@ do_optimization(struct exec_list *ir, const char 
*optimization)
 
 static GLboolean
 do_optimization_passes(struct exec_list *ir, char **optimizations,
-   int num_optimizations, bool quiet)
+   int num_optimizations, bool quiet,
+   const struct gl_shader_compiler_options *options)
 {
GLboolean overall_progress = false;
 
@@ -150,7 +152,7 @@ do_optimization_passes(struct exec_list *ir, char 
**optimizations,
   if (!quiet) {
  printf(*** Running optimization %s..., optimization);
   }
-  GLboolean progress = do_optimization(ir, optimization);
+  GLboolean progress = do_optimization(ir, optimization, options);
   if (!quiet) {
  printf(%s\n, progress ? progress : no progress);
   }
@@ -240,9 +242,11 @@ int test_optpass(int argc, char **argv)
/* Optimization passes */
if (!state-error) {
   GLboolean progress;
+  const struct gl_shader_compiler_options *options =
+ ctx-ShaderCompilerOptions[_mesa_shader_type_to_index(shader_type)];
   do {
  progress = do_optimization_passes(shader-ir, argv[optind],
-   argc - optind, quiet != 0);
+   argc - optind, quiet != 0, options);
   } while (loop  progress);
}
 

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Mesa (9.1): intel: Allocate hiz in intel_renderbuffer_move_to_temp()

[Paul Berry]

Module: Mesa
Branch: 9.1
Commit: 496996010561463bf0f2e2a7632978c548065b98
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=496996010561463bf0f2e2a7632978c548065b98

Author: Chad Versace chad.vers...@linux.intel.com
Date:   Fri Apr  5 15:18:00 2013 -0700

intel: Allocate hiz in intel_renderbuffer_move_to_temp()

When moving the renderbuffer to a new miptree, we neglected to allocate
the hiz buffer for the new miptree. Oops.

Fixes all Piglit depthstencil-render-miplevels tests from crash to pass on
Sandybridge.

Note: This is a candidate for the 9.1 branch.
Reviewed-by: Eric Anholt e...@anholt.net
Reviewed-by: Paul Berry stereotype...@gmail.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
(cherry picked from commit aa391976dfa12479185d9eeed1f2a0b4dce6c49b)

---

 src/mesa/drivers/dri/intel/intel_fbo.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c 
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 37ecbd1..41412ee 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -999,6 +999,10 @@ intel_renderbuffer_move_to_temp(struct intel_context 
*intel,
  irb-mt-num_samples,
  false /* force_y_tiling */);
 
+   if (intel-vtbl.is_hiz_depth_format(intel, new_mt-format)) {
+  intel_miptree_alloc_hiz(intel, new_mt, irb-mt-num_samples);
+   }
+
intel_miptree_copy_teximage(intel, intel_image, new_mt);
intel_miptree_reference(irb-mt, intel_image-mt);
intel_renderbuffer_set_draw_offset(irb);

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Mesa (master): intel: Do a depth resolve before copying images between miptrees.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 46ea8041074df79561f9771e2ecf198f2cbd088f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46ea8041074df79561f9771e2ecf198f2cbd088f

Author: Paul Berry stereotype...@gmail.com
Date:   Thu May 16 14:12:15 2013 -0700

intel: Do a depth resolve before copying images between miptrees.

When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage()
to reassemble a depth miptree that has been broken apart into pieces
(to deal with misalignment of levels/layers within the miptree), it
just copies the depth data, not the HiZ data.  This is reasonable,
since the alignment restrictions of HiZ are a large part of the reason
why the miptree had to be broken apart in the first place.  However,
in order for the depth copy to be sufficient, we need to do a depth
resolve first, to make sure any deferred depth writes that are in the
HiZ buffer get performed.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and
https://bugs.freedesktop.org/show_bug.cgi?id=64659.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 7f4cb4a..2dfa787 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -902,6 +902,12 @@ intel_miptree_copy_slice(struct intel_context *intel,
dst_mt, dst_x, dst_y, dst_mt-region-pitch,
width, height);
 
+   /* Since we are about to copy depth data using either the blitter or swrast
+* (neither of which respect HiZ), we need to do a depth resolve first.
+*/
+   intel_miptree_slice_resolve_depth(intel, src_mt, level, slice);
+   intel_miptree_slice_resolve_depth(intel, dst_mt, level, slice);
+
if (!intelEmitCopyBlit(intel,
  dst_mt-region-cpp,
  src_mt-region-pitch, src_mt-region-bo,

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Mesa (9.1): intel: Do a depth resolve before copying images between miptrees.

[Paul Berry]

Module: Mesa
Branch: 9.1
Commit: cbe0e50247c909a7d34f71d9a1a4852b6c3af472
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbe0e50247c909a7d34f71d9a1a4852b6c3af472

Author: Paul Berry stereotype...@gmail.com
Date:   Thu May 16 14:12:15 2013 -0700

intel: Do a depth resolve before copying images between miptrees.

When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage()
to reassemble a depth miptree that has been broken apart into pieces
(to deal with misalignment of levels/layers within the miptree), it
just copies the depth data, not the HiZ data.  This is reasonable,
since the alignment restrictions of HiZ are a large part of the reason
why the miptree had to be broken apart in the first place.  However,
in order for the depth copy to be sufficient, we need to do a depth
resolve first, to make sure any deferred depth writes that are in the
HiZ buffer get performed.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and
https://bugs.freedesktop.org/show_bug.cgi?id=64659.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com
(cherry picked from commit 46ea8041074df79561f9771e2ecf198f2cbd088f)

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index a063f87..43f3779 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -725,6 +725,12 @@ intel_miptree_copy_slice(struct intel_context *intel,
dst_mt, dst_x, dst_y, dst_mt-region-pitch,
width, height);
 
+   /* Since we are about to copy depth data using either the blitter or swrast
+* (neither of which respect HiZ), we need to do a depth resolve first.
+*/
+   intel_miptree_slice_resolve_depth(intel, src_mt, level, slice);
+   intel_miptree_slice_resolve_depth(intel, dst_mt, level, slice);
+
if (!intelEmitCopyBlit(intel,
  dst_mt-region-cpp,
  src_mt-region-pitch, src_mt-region-bo,

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Mesa (master): intel: Don't try to blorp or blit CopyTexSubImage(1D_ARRAY).

[Paul Berry]

Module: Mesa
Branch: master
Commit: 2fd785d12602103a1c05fd52903bdb4ffefadaad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fd785d12602103a1c05fd52903bdb4ffefadaad

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Jun  2 16:25:03 2013 -0700

intel: Don't try to blorp or blit CopyTexSubImage(1D_ARRAY).

Blorp and the hardware blitter can't be used to implement
CopyTexSubImage when the image type is 1D_ARRAY, because of a
coordinate system mismatch (the Y coordinate in the source image is
supposed to be matched up to the Z coordinate in the destination
texture).

The hardware blitter path (intel_copy_texsubimage) contained a perf
debug warning for this case, but it failed to actually fall back.  The
blorp path didn't even check.

Fixes piglit test copyteximage 1D_ARRAY.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp |6 ++
 src/mesa/drivers/dri/intel/intel_tex_copy.c  |1 +
 2 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index c70dc22..a6b2bbf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -347,6 +347,12 @@ brw_blorp_copytexsubimage(struct intel_context *intel,
   return false;
}
 
+   /* We can't use blorp to copy to a 1D array texture, since it can only
+* write to one layer of the texture at a time.
+*/
+   if (dst_mt-target == GL_TEXTURE_1D_ARRAY)
+  return false;
+
/* Source clipping shouldn't be necessary, since copytexsubimage (in
 * src/mesa/main/teximage.c) calls _mesa_clip_copytexsubimage() which
 * takes care of it.
diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c 
b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 363cbbd..d8e65ba 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -83,6 +83,7 @@ intel_copy_texsubimage(struct intel_context *intel,
if (intelImage-base.Base.TexObject-Target == GL_TEXTURE_1D_ARRAY ||
intelImage-base.Base.TexObject-Target == GL_TEXTURE_2D_ARRAY) {
   perf_debug(no support for array textures\n);
+  return false;
}
 
/* glCopyTexImage (and the glBlitFramebuffer() path that reuses this)

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Mesa (master): i965/gen6+: Fix multisample assertions in CopyTexSubImage hw blitter path.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 32d1f423bccb1ad7199f072d4ac09ed88b693b1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32d1f423bccb1ad7199f072d4ac09ed88b693b1f

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Jun  2 14:31:46 2013 -0700

i965/gen6+: Fix multisample assertions in CopyTexSubImage hw blitter path.

Commit 045612c (intel: Add an assert for glCopyTexSubImage() being
called on MSAA buffers) added an assertion to intel_copy_texsubimage()
to make sure that multisampling was not in use, based on the
assumption that glCopyTexSubImage() can't legally be used with
multisampling.

However, there is one case where glCopyTexSubImage() can legally be
used with multisampling: when the source buffer is a multisampled
window system buffer.  If the source and destination color formats
don't match, the blorp path will fail, so intel_copy_texsubimage()
will be called.  In this case, we need intel_copy_texsubimage() to
return false so that we fall back to meta to do the copy.  (The
multisampled source buffer won't cause a problem for the meta path,
because it uses glReadPixels, which forces a multisample resolve).

It's still safe to assert that the destination image is
single-sampled, because it's not legal to call glCopyTexSubImage() on
multisampled textures.

Fixes some failures with piglit tests copyteximage
{1D,2D,CUBE,RECT,2D_ARRAY} (with samples=... argument).

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_tex_copy.c |   13 +
 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_tex_copy.c 
b/src/mesa/drivers/dri/intel/intel_tex_copy.c
index 6fb4e38..363cbbd 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_copy.c
@@ -62,11 +62,16 @@ intel_copy_texsubimage(struct intel_context *intel,
 
intel_prepare_render(intel);
 
-   /* glCopyTexSubImage() can't be called on multisampled renderbuffers or
-* textures.
+   /* glCopyTexSubImage() can be called on a multisampled renderbuffer (if
+* that renderbuffer is associated with the window system framebuffer),
+* however the hardware blitter can't handle this case, so fall back to
+* meta (which can, since it uses ReadPixels).
 */
-   assert(!irb-Base.Base.NumSamples);
-   assert(!intelImage-base.Base.NumSamples);
+   if (irb-Base.Base.NumSamples != 0)
+  return false;
+
+   /* glCopyTexSubImage() can't be called on a multisampled texture. */
+   assert(intelImage-base.Base.NumSamples == 0);
 
if (!intelImage-mt || !irb || !irb-mt) {
   if (unlikely(INTEL_DEBUG  DEBUG_PERF))

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Mesa (master): intel: flush fake front buffer more robustly.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 447df5eabac62d11740b23987cf91fb269bffcc6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=447df5eabac62d11740b23987cf91fb269bffcc6

Author: Paul Berry stereotype...@gmail.com
Date:   Wed May 29 09:48:26 2013 -0700

intel: flush fake front buffer more robustly.

When a fake front buffer is in use, if we request the front buffer
(using screen-dri2.loader-getBuffersWithFormat()), the X server
copies the real front buffer to the fake front buffer and returns the
fake front buffer.  We sometimes make redundant requests for the front
buffer (due to using a single counter to track invalidates for both
the front and back buffers), so there's a danger of pending front
buffer rendering getting overwritten when the redundant front buffer
request occurs.

Previous to this patch, intel_update_renderbuffers() worked around
that problem by sometimes doing intel_flush() and intel_flush_front()
before calling intel_query_dri2_buffers().  But it only did the
workaround when the front buffer was bound for drawing; it didn't do
it when the front buffer was bound for reading.

This patch moves the workaround code to intel_query_dri2_buffers(), so
that it happens in exactly the circumstances where it is needed.

This should fix some of the sporadic failures in Piglit tests
fbo-sys-blit and fbo-sys-sub-blit.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com

---

 src/mesa/drivers/dri/intel/intel_context.c |   20 +---
 1 files changed, 9 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_context.c 
b/src/mesa/drivers/dri/intel/intel_context.c
index 54d0a69..7f8a2bb 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -186,17 +186,6 @@ intel_update_renderbuffers(__DRIcontext *context, 
__DRIdrawable *drawable)
int i, count;
const char *region_name;
 
-   /* If we're rendering to the fake front buffer, make sure all the
-* pending drawing has landed on the real front buffer.  Otherwise
-* when we eventually get to DRI2GetBuffersWithFormat the stale
-* real front buffer contents will get copied to the new fake front
-* buffer.
-*/
-   if (intel-is_front_buffer_rendering) {
-  intel_flush(intel-ctx);
-  intel_flush_front(intel-ctx);
-   }
-
/* Set this up front, so that in case our buffers get invalidated
 * while we're getting new buffers, we don't clobber the stamp and
 * thus ignore the invalidate. */
@@ -925,6 +914,15 @@ intel_query_dri2_buffers(struct intel_context *intel,
if ((intel-is_front_buffer_rendering ||
intel-is_front_buffer_reading ||
!back_rb)  front_rb) {
+  /* If a fake front buffer is in use, then querying for
+   * __DRI_BUFFER_FRONT_LEFT will cause the server to copy the image from
+   * the real front buffer to the fake front buffer.  So before doing the
+   * query, we need to make sure all the pending drawing has landed in the
+   * real front buffer.
+   */
+  intel_flush(intel-ctx);
+  intel_flush_front(intel-ctx);
+
   attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
   attachments[i++] = intel_bits_per_pixel(front_rb);
}

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Mesa (master): intel: make intel_flush_front safe to call during initial MakeCurrent

[Paul Berry]

Module: Mesa
Branch: master
Commit: 03cc31031315059a80d12485a402ea2a8731dc8a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03cc31031315059a80d12485a402ea2a8731dc8a

Author: Paul Berry stereotype...@gmail.com
Date:   Thu May 30 07:08:07 2013 -0700

intel: make intel_flush_front safe to call during initial MakeCurrent

The patch that follows will fix a bug that prevents
intel_flush_front() from being called often enough.  In doing so, it
will create a situation where intel_flush_front() is called during the
initial call to glXMakeCurrent().  In this circumstance,
ctx-DrawBuffer hasn't been initialized yet and is NULL.  Fortunately,
intel-front_buffer_dirty is false, so intel_flush_front() doesn't
actually need to do anything.  To avoid a segfault, swap the order of
terms in intel_flush_front()'s if statement.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com

---

 src/mesa/drivers/dri/intel/intel_context.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_context.c 
b/src/mesa/drivers/dri/intel/intel_context.c
index 8c88b3c..54d0a69 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -132,7 +132,7 @@ intel_flush_front(struct gl_context *ctx)
 __DRIdrawable *driDrawable = driContext-driDrawablePriv;
 __DRIscreen *const screen = intel-intelScreen-driScrnPriv;
 
-if (_mesa_is_winsys_fbo(ctx-DrawBuffer)  intel-front_buffer_dirty) {
+if (intel-front_buffer_dirty  _mesa_is_winsys_fbo(ctx-DrawBuffer)) {
   if (screen-dri2.loader-flushFrontBuffer != NULL 
   driDrawable 
   driDrawable-loaderPrivate) {

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Mesa (master): intel: flush fake front buffer if server is about to destroy it.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 9e3475b39ae34244045e0dcd6b98e1526c10c6bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e3475b39ae34244045e0dcd6b98e1526c10c6bf

Author: Paul Berry stereotype...@gmail.com
Date:   Fri May 31 09:45:49 2013 -0700

intel: flush fake front buffer if server is about to destroy it.

Fixes piglit test spec/!OpenGL 1.0/gl-1.0-front-invalidate-back

Reviewed-by: Anuj Phogat anuj.pho...@gmail.com

---

 src/mesa/drivers/dri/intel/intel_context.c |9 +
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_context.c 
b/src/mesa/drivers/dri/intel/intel_context.c
index 7f8a2bb..09b33b1 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -925,6 +925,15 @@ intel_query_dri2_buffers(struct intel_context *intel,
 
   attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
   attachments[i++] = intel_bits_per_pixel(front_rb);
+   } else if (front_rb  intel-front_buffer_dirty) {
+  /* We have pending front buffer rendering, but we aren't querying for a
+   * front buffer.  If the front buffer we have is a fake front buffer,
+   * the X server is going to throw it away when it processes the query.
+   * So before doing the query, make sure all the pending drawing has
+   * landed in the real front buffer.
+   */
+  intel_flush(intel-ctx);
+  intel_flush_front(intel-ctx);
}
 
if (back_rb) {

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Mesa (master): intel: Conditionally compile mcs-related code for i965 only.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8f5147c199748ae129c527322823c2b40fb36941
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f5147c199748ae129c527322823c2b40fb36941

Author: Paul Berry stereotype...@gmail.com
Date:   Mon May 20 13:29:39 2013 -0700

intel: Conditionally compile mcs-related code for i965 only.

This patch ifdefs out intel_mipmap_tree::mcs_mt when building the i915
(pre-Gen4) driver (MCS buffers aren't supported until Gen7, so there
is no need for this field in the i915 driver).  This should make it a
bit easier to implement fast color clears without undue risk to i915.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |8 +++-
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h |2 ++
 2 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 08b5d42..ee763e5 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -671,7 +671,9 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
   intel_region_release(((*mt)-region));
   intel_miptree_release((*mt)-stencil_mt);
   intel_miptree_release((*mt)-hiz_mt);
+#ifndef I915
   intel_miptree_release((*mt)-mcs_mt);
+#endif
   intel_miptree_release((*mt)-singlesample_mt);
   intel_resolve_map_clear((*mt)-hiz_map);
 
@@ -1012,8 +1014,11 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
 struct intel_mipmap_tree *mt,
 GLuint num_samples)
 {
-   assert(mt-mcs_mt == NULL);
assert(intel-gen = 7); /* MCS only used on Gen7+ */
+#ifdef I915
+   return false;
+#else
+   assert(mt-mcs_mt == NULL);
 
/* Choose the correct format for the MCS buffer.  All that really matters
 * is that we allocate the right buffer size, since we'll always be
@@ -1070,6 +1075,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
intel_miptree_unmap_raw(intel, mt-mcs_mt);
 
return mt-mcs_mt;
+#endif
 }
 
 /**
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index cac518c..639d4be 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -373,6 +373,7 @@ struct intel_mipmap_tree
 */
struct intel_mipmap_tree *stencil_mt;
 
+#ifndef I915
/**
 * \brief MCS miptree for multisampled textures.
 *
@@ -381,6 +382,7 @@ struct intel_mipmap_tree
 * (INTEL_MSAA_FORMAT_CMS).
 */
struct intel_mipmap_tree *mcs_mt;
+#endif
 
/* These are also refcounted:
 */

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Mesa (master): i965/gen7+: Create helper functions for single-sample MCS buffers.

[Paul Berry]

Module: Mesa
Branch: master
Commit: dd3f950115218c69c9118436a5110a1ee6a2dda5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd3f950115218c69c9118436a5110a1ee6a2dda5

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Apr 30 18:51:51 2013 -0700

i965/gen7+: Create helper functions for single-sample MCS buffers.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |  119 
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h |9 ++
 2 files changed, 128 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 601666c..a75ac81 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -124,6 +124,125 @@ compute_msaa_layout(struct intel_context *intel, 
gl_format format, GLenum target
 
 
 /**
+ * For single-sampled render targets (non-MSRT), the MCS buffer is a
+ * scaled-down bitfield representation of the color buffer which is capable of
+ * recording when blocks of the color buffer are equal to the clear value.
+ * This function returns the block size that will be used by the MCS buffer
+ * corresponding to a certain color miptree.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 11.7 MCS Buffer for Render Target(s),
+ * beneath the Fast Color Clear bullet (p327):
+ *
+ * The following table describes the RT alignment
+ *
+ *   Pixels  Lines
+ * TiledY RT CL
+ * bpp
+ *  32  8  4
+ *  64  4  4
+ * 128  2  4
+ * TiledX RT CL
+ * bpp
+ *  32 16  2
+ *  64  8  2
+ * 128  4  2
+ *
+ * This alignment has the following uses:
+ *
+ * - For figuring out the size of the MCS buffer.  Each 4k tile in the MCS
+ *   buffer contains 128 blocks horizontally and 256 blocks vertically.
+ *
+ * - For figuring out alignment restrictions for a fast clear operation.  Fast
+ *   clear operations must always clear aligned multiples of 16 blocks
+ *   horizontally and 32 blocks vertically.
+ *
+ * - For scaling down the coordinates sent through the render pipeline during
+ *   a fast clear.  X coordinates must be scaled down by 8 times the block
+ *   width, and Y coordinates by 16 times the block height.
+ *
+ * - For scaling down the coordinates sent through the render pipeline during
+ *   a Render Target Resolve operation.  X coordinates must be scaled down
+ *   by half the block width, and Y coordinates by half the block height.
+ */
+void
+intel_get_non_msrt_mcs_alignment(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned *width_px, unsigned *height)
+{
+   switch (mt-region-tiling) {
+   default:
+  assert(!Non-MSRT MCS requires X or Y tiling);
+  /* In release builds, fall through */
+   case I915_TILING_Y:
+  *width_px = 32 / mt-cpp;
+  *height = 4;
+  break;
+   case I915_TILING_X:
+  *width_px = 64 / mt-cpp;
+  *height = 2;
+   }
+}
+
+
+/**
+ * For a single-sampled render target (non-MSRT), determine if an MCS buffer
+ * can be used.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 11.7 MCS Buffer for Render Target(s),
+ * beneath the Fast Color Clear bullet (p326):
+ *
+ * - Support is limited to tiled render targets.
+ * - Support is for non-mip-mapped and non-array surface types only.
+ *
+ * And then later, on p327:
+ *
+ * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
+ *   64bpp, and 128bpp.
+ */
+bool
+intel_is_non_msrt_mcs_buffer_supported(struct intel_context *intel,
+   struct intel_mipmap_tree *mt)
+{
+#ifdef I915
+   /* MCS is not supported on the i915 (pre-Gen4) driver */
+   return false;
+#else
+   struct brw_context *brw = brw_context(intel-ctx);
+
+   /* MCS support does not exist prior to Gen7 */
+   if (intel-gen  7)
+  return false;
+
+   /* MCS is only supported for color buffers */
+   switch (_mesa_get_format_base_format(mt-format)) {
+   case GL_DEPTH_COMPONENT:
+   case GL_DEPTH_STENCIL:
+   case GL_STENCIL_INDEX:
+  return false;
+   }
+
+   if (mt-region-tiling != I915_TILING_X 
+   mt-region-tiling != I915_TILING_Y)
+  return false;
+   if (mt-cpp != 4  mt-cpp != 8  mt-cpp != 16)
+  return false;
+   if (mt-first_level != 0 || mt-last_level != 0)
+  return false;
+   if (mt-physical_depth0 != 1)
+  return false;
+
+   /* There's no point in using an MCS buffer if the surface isn't in a
+* renderable format.
+*/
+   if (!brw-format_supported_as_render_target[mt-format])
+  return false;
+
+   return true;
+#endif
+}
+
+
+/**
  * @param for_bo Indicates that the caller is
  *intel_miptree_create_for_bo(). If true, then do not create
  *\c

Mesa (master): intel: Keep region name in intel_miptree_create_for_dri2_buffer().

[Paul Berry]

Module: Mesa
Branch: master
Commit: a5efdca7b70a237b8786c595453f4599e38263ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5efdca7b70a237b8786c595453f4599e38263ea

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May 28 13:29:53 2013 -0700

intel: Keep region name in intel_miptree_create_for_dri2_buffer().

When processing a buffer received from the X server,
intel_process_dri2_buffer() examines intel_region::name to determine
whether it's received a brand new buffer, or the same buffer it
received from the X server the last time it made a request.

However, this didn't work properly, because in the call to
intel_miptree_create_for_dri2_buffer(), we create a fresh intel_region
object to represent the buffer, and this was causing us to forget the
buffer's previous name.

This patch fixes things by copying over the region name when creating
the fresh intel_region object.

At the moment, this is just a minor performance optimization.
However, when fast color clears are added, it will be necessary to
ensure that the fast color clear state for a buffer doesn't get
discarded the next time we receive that buffer from the X server.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index c336c46..08b5d42 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -575,6 +575,7 @@ intel_miptree_create_for_dri2_buffer(struct intel_context 
*intel,
  region-tiling);
if (!singlesample_mt)
   return NULL;
+   singlesample_mt-region-name = region-name;
 
if (num_samples == 0)
   return singlesample_mt;

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Mesa (master): i965/gen7+: Implement fast color clear operation in BLORP.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab

Author: Paul Berry stereotype...@gmail.com
Date:   Wed May  1 08:04:12 2013 -0700

i965/gen7+: Implement fast color clear operation in BLORP.

Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.

In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
fast color clear value, if any. We use it to set the SURFACE_STATE's
clear color for render targets.

v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree.  Generate a
perf_debug message if clearing to a color that isn't compatible with
fast color clear.  Fix control reaches end of non-void function
build warning.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_blorp.cpp   |1 +
 src/mesa/drivers/dri/i965/brw_blorp.h |   11 ++-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |  149 -
 src/mesa/drivers/dri/i965/brw_clear.c |2 +-
 src/mesa/drivers/dri/i965/brw_defines.h   |2 +
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |   18 ++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |   10 +-
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c|   48 +++
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h|   13 ++
 9 files changed, 240 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index a2d02bf..9c9a4a7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -145,6 +145,7 @@ brw_blorp_params::brw_blorp_params()
  y1(0),
  depth_format(0),
  hiz_op(GEN6_HIZ_OP_NONE),
+ fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
  num_samples(0),
  use_wm_prog(false)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 51b23db..0808206 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -47,7 +47,8 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
 bool mirror_x, bool mirror_y);
 
 bool
-brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb);
+brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
+  bool partial_clear);
 
 #ifdef __cplusplus
 } /* end extern C */
@@ -192,6 +193,13 @@ struct brw_blorp_prog_data
bool persample_msaa_dispatch;
 };
 
+
+enum gen7_fast_clear_op {
+   GEN7_FAST_CLEAR_OP_NONE,
+   GEN7_FAST_CLEAR_OP_FAST_CLEAR,
+};
+
+
 class brw_blorp_params
 {
 public:
@@ -209,6 +217,7 @@ public:
brw_blorp_surface_info src;
brw_blorp_surface_info dst;
enum gen6_hiz_op hiz_op;
+   enum gen7_fast_clear_op fast_clear_op;
unsigned num_samples;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index b626659..1f98360 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -49,7 +49,8 @@ public:
brw_blorp_clear_params(struct brw_context *brw,
   struct gl_framebuffer *fb,
   struct gl_renderbuffer *rb,
-  GLubyte *color_mask);
+  GLubyte *color_mask,
+  bool partial_clear);
 
virtual uint32_t get_wm_prog(struct brw_context *brw,
 brw_blorp_prog_data **prog_data) const;
@@ -105,10 +106,53 @@ brw_blorp_clear_program::~brw_blorp_clear_program()
ralloc_free(mem_ctx);
 }
 
+
+/**
+ * Determine if fast color clear supports the given clear color.
+ *
+ * Fast color clear can only clear to color values of 1.0 or 0.0.  At the
+ * moment we only support floating point, unorm, and snorm buffers.
+ */
+static bool
+is_color_fast_clear_compatible(struct intel_context *intel,
+   gl_format format,
+   const union gl_color_union *color)
+{
+   if (_mesa_is_format_integer_color(format))
+  return false;
+
+   for (int i = 0; i  4; i++) {
+  if (color-f[i] != 0.0  color-f[i] != 1.0) {
+ perf_debug(Clear color unsupported by fast color clear.  
+Falling back to slow clear.);
+ return false;
+  }
+   }
+   return true;
+}
+
+
+/**
+ * Convert the given color to a bitfield suitable for ORing into DWORD 7 of
+ * SURFACE_STATE.
+ */
+static uint32_t
+compute_fast_clear_color_bits(const union gl_color_union *color)
+{
+   uint32_t bits = 0;
+   for (int i = 0; i  4; i++) {
+  if (color-f[i] != 0.0)
+ bits |= 1  (GEN7_SURFACE_CLEAR_COLOR_SHIFT + (3 - i

Mesa (master): i965/blorp: Expand clear class hierarchy to prepare for RT resolves.

[Paul Berry]

Module: Mesa
Branch: master
Commit: fac32c0bd31601c37f3aa01d69b655e0f75bbdef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fac32c0bd31601c37f3aa01d69b655e0f75bbdef

Author: Paul Berry stereotype...@gmail.com
Date:   Mon May  6 09:38:42 2013 -0700

i965/blorp: Expand clear class hierarchy to prepare for RT resolves.

The fragment shaders that to do color clears will be re-used to
perform so-called render target resolves (the resolves associated
with fast color clears).  To prepare for that, this patch expands the
class hierarchy for blorp params by adding
brw_blorp_const_color_params (which will be used for all blorp
operations where the fragment shader outputs a constant color).

Some other data structures and functions were also renamed to use
const_color nomenclature where appropriate.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |   58 ++--
 src/mesa/drivers/dri/i965/brw_context.h   |2 +-
 2 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 1f98360..8df493e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -37,13 +37,28 @@ extern C {
 #include brw_eu.h
 #include brw_state.h
 
-struct brw_blorp_clear_prog_key
+struct brw_blorp_const_color_prog_key
 {
bool use_simd16_replicated_data;
bool pad[3];
 };
 
-class brw_blorp_clear_params : public brw_blorp_params
+/**
+ * Parameters for a blorp operation where the fragment shader outputs a
+ * constant color.  This is used for both fast color clears and color
+ * resolves.
+ */
+class brw_blorp_const_color_params : public brw_blorp_params
+{
+public:
+   virtual uint32_t get_wm_prog(struct brw_context *brw,
+brw_blorp_prog_data **prog_data) const;
+
+protected:
+   brw_blorp_const_color_prog_key wm_prog_key;
+};
+
+class brw_blorp_clear_params : public brw_blorp_const_color_params
 {
 public:
brw_blorp_clear_params(struct brw_context *brw,
@@ -51,20 +66,14 @@ public:
   struct gl_renderbuffer *rb,
   GLubyte *color_mask,
   bool partial_clear);
-
-   virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
-
-private:
-   brw_blorp_clear_prog_key wm_prog_key;
 };
 
-class brw_blorp_clear_program
+class brw_blorp_const_color_program
 {
 public:
-   brw_blorp_clear_program(struct brw_context *brw,
-  const brw_blorp_clear_prog_key *key);
-   ~brw_blorp_clear_program();
+   brw_blorp_const_color_program(struct brw_context *brw,
+ const brw_blorp_const_color_prog_key *key);
+   ~brw_blorp_const_color_program();
 
const GLuint *compile(struct brw_context *brw, GLuint *program_size);
 
@@ -75,7 +84,7 @@ private:
 
void *mem_ctx;
struct brw_context *brw;
-   const brw_blorp_clear_prog_key *key;
+   const brw_blorp_const_color_prog_key *key;
struct brw_compile func;
 
/* Thread dispatch header */
@@ -91,9 +100,9 @@ private:
GLuint base_mrf;
 };
 
-brw_blorp_clear_program::brw_blorp_clear_program(
+brw_blorp_const_color_program::brw_blorp_const_color_program(
   struct brw_context *brw,
-  const brw_blorp_clear_prog_key *key)
+  const brw_blorp_const_color_prog_key *key)
: mem_ctx(ralloc_context(NULL)),
  brw(brw),
  key(key)
@@ -101,7 +110,7 @@ brw_blorp_clear_program::brw_blorp_clear_program(
brw_init_compile(brw, func, mem_ctx);
 }
 
-brw_blorp_clear_program::~brw_blorp_clear_program()
+brw_blorp_const_color_program::~brw_blorp_const_color_program()
 {
ralloc_free(mem_ctx);
 }
@@ -258,17 +267,18 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct 
brw_context *brw,
 }
 
 uint32_t
-brw_blorp_clear_params::get_wm_prog(struct brw_context *brw,
-   brw_blorp_prog_data **prog_data) const
+brw_blorp_const_color_params::get_wm_prog(struct brw_context *brw,
+  brw_blorp_prog_data **prog_data)
+   const
 {
uint32_t prog_offset;
-   if (!brw_search_cache(brw-cache, BRW_BLORP_CLEAR_PROG,
+   if (!brw_search_cache(brw-cache, BRW_BLORP_CONST_COLOR_PROG,
  this-wm_prog_key, sizeof(this-wm_prog_key),
  prog_offset, prog_data)) {
-  brw_blorp_clear_program prog(brw, this-wm_prog_key);
+  brw_blorp_const_color_program prog(brw, this-wm_prog_key);
   GLuint program_size;
   const GLuint *program = prog.compile(brw, program_size);
-  brw_upload_cache(brw-cache, BRW_BLORP_CLEAR_PROG,
+  brw_upload_cache(brw-cache, BRW_BLORP_CONST_COLOR_PROG,
this-wm_prog_key, sizeof(this-wm_prog_key),
program, program_size

Mesa (master): i965/gen7+: Disable fast color clears on shared regions.

[Paul Berry]

Module: Mesa
Branch: master
Commit: ef9142d4a37c28bf6ae3527f71b9aa1b57ba9eb0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef9142d4a37c28bf6ae3527f71b9aa1b57ba9eb0

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May 21 14:21:44 2013 -0700

i965/gen7+: Disable fast color clears on shared regions.

In certain circumstances the memory region underlying a miptree is
shared with other miptrees, or with other code outside Mesa's control.
This happens, for instance, when an extension like GL_OES_EGL_image or
GLX_EXT_texture_from_pixmap extension is used to associate a miptree
with an image existing outside of Mesa.

When this happens, we need to disable fast color clears on the miptree
in question, since there's no good synchronization mechanism to ensure
that deferred clear writes get performed by the time the buffer is
examined from the other miptree, or from outside of Mesa.

Fortunately, this should not be a performance hit for most
applications, since most applications that use these extensions use
them for importing textures into Mesa, rather than for exporting
rendered images out of Mesa.  So most of the time the miptrees
involved will never experience a clear.

v2: Rework based on the fact that we have decided not to use an
accessor function to protect access to the region.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |   34 
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h |4 +++
 src/mesa/drivers/dri/intel/intel_screen.c  |3 ++
 src/mesa/drivers/dri/intel/intel_tex_image.c   |1 +
 4 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 4c98e90..5b767df 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -1475,6 +1475,40 @@ intel_miptree_resolve_color(struct intel_context *intel,
 
 
 /**
+ * Make it possible to share the region backing the given miptree with another
+ * process or another miptree.
+ *
+ * Fast color clears are unsafe with shared buffers, so we need to resolve and
+ * then discard the MCS buffer, if present.  We also set the mcs_state to
+ * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
+ * future.
+ */
+void
+intel_miptree_make_shareable(struct intel_context *intel,
+ struct intel_mipmap_tree *mt)
+{
+#ifdef I915
+   /* Nothing needs to be done for I915 */
+   (void) intel;
+   (void) mt;
+#else
+   /* MCS buffers are also used for multisample buffers, but we can't resolve
+* away a multisample MCS buffer because it's an integral part of how the
+* pixel data is stored.  Fortunately this code path should never be
+* reached for multisample buffers.
+*/
+   assert(mt-msaa_layout == INTEL_MSAA_LAYOUT_NONE);
+
+   if (mt-mcs_mt) {
+  intel_miptree_resolve_color(intel, mt);
+  intel_miptree_release(mt-mcs_mt);
+  mt-mcs_state = INTEL_MCS_STATE_NONE;
+   }
+#endif
+}
+
+
+/**
  * \brief Get pointer offset into stencil buffer.
  *
  * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 8ea1bef..6dab092 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -723,6 +723,10 @@ intel_miptree_resolve_color(struct intel_context *intel,
 struct intel_mipmap_tree *mt);
 
 void
+intel_miptree_make_shareable(struct intel_context *intel,
+ struct intel_mipmap_tree *mt);
+
+void
 intel_miptree_downsample(struct intel_context *intel,
  struct intel_mipmap_tree *mt);
 
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c 
b/src/mesa/drivers/dri/intel/intel_screen.c
index b4758f9..60a69a6 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -300,6 +300,8 @@ intel_setup_image_from_mipmap_tree(struct intel_context 
*intel, __DRIimage *imag
unsigned int draw_x, draw_y;
uint32_t mask_x, mask_y;
 
+   intel_miptree_make_shareable(intel, mt);
+
intel_miptree_check_level_layer(mt, level, zoffset);
 
intel_region_get_tile_masks(mt-region, mask_x, mask_y, false);
@@ -396,6 +398,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
}
 
irb = intel_renderbuffer(rb);
+   intel_miptree_make_shareable(intel, irb-mt);
image = calloc(1, sizeof *image);
if (image == NULL)
   return NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c 
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index fba02c2..b91b2b5 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -342,6 +342,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint

Mesa (master): i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 460b7bc7a103d7a7518b4187f0c1dfc452f75137
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=460b7bc7a103d7a7518b4187f0c1dfc452f75137

Author: Paul Berry stereotype...@gmail.com
Date:   Wed May  1 07:16:52 2013 -0700

i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.

On Gen7+, MCS buffers are used both for compressed multisampled color
buffers and for fast clear of single-sampled color buffers.

Previous to this patch series, we didn't support fast clear, so we
only used MCS with multisampled bolor buffers.

As a first step to implementing fast clears, this patch modifies the
code that sets up SURFACE_STATE so that it configures the MCS buffer
whenever it is present, regardless of whether we are multisampling or
not.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |2 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +-
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h|8 +---
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 68c7ca1..208c66a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -194,7 +194,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[3] = pitch_bytes - 1;
 
surf[4] = gen7_surface_msaa_bits(surface-num_samples, 
surface-msaa_layout);
-   if (surface-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+   if (surface-mt-mcs_mt) {
   gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface-mt-mcs_mt,
 is_render_target);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 6a7c8de..3164f99 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -609,7 +609,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
  min_array_element  GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
  (depth - 1)  GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 
-   if (irb-mt-msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+   if (irb-mt-mcs_mt) {
   gen7_set_surface_mcs_info(brw, surf, brw-wm.surf_offset[unit],
 irb-mt-mcs_mt, true /* is RT */);
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index d66d0b5..e2a7fe8 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -443,11 +443,13 @@ struct intel_mipmap_tree
 
 #ifndef I915
/**
-* \brief MCS miptree for multisampled textures.
+* \brief MCS miptree.
 *
 * This miptree contains the multisample control surface, which stores
-* the necessary information to implement compressed MSAA on Gen7+
-* (INTEL_MSAA_FORMAT_CMS).
+* the necessary information to implement compressed MSAA
+* (INTEL_MSAA_FORMAT_CMS) and fast color clear behaviour on Gen7+.
+*
+* NULL if no MCS miptree is in use for this surface.
 */
struct intel_mipmap_tree *mcs_mt;
 

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Mesa (master): i965/gen7+: Create an enum for keeping track of fast color clear state.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May  7 14:04:29 2013 -0700

i965/gen7+: Create an enum for keeping track of fast color clear state.

This patch includes code to update the fast color clear state
appropriately when rendering occurs.  The state will also need to be
updated when a fast clear or a resolve operation is performed; those
state updates will be added when the fast clear and resolve operations
are added.

v2: Create a new function, intel_miptree_used_for_rendering() to
handle updating the fast color clear state when rendering occurs.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  |2 +
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  |1 +
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |1 +
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c|4 +
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h|   94 +
 6 files changed, 104 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 4d4d300..ceabedb 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1346,6 +1346,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
   }
}
 
+   intel_miptree_used_for_rendering(irb-mt);
+
region = irb-mt-region;
 
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index bb87f6b..3ccd90e 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1075,6 +1075,7 @@ gen6_blorp_exec(struct intel_context *intel,
   uint32_t wm_surf_offset_texture = 0;
   uint32_t sampler_offset;
   wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
+  intel_miptree_used_for_rendering(params-dst.mt);
   wm_surf_offset_renderbuffer =
  gen6_blorp_emit_surface_state(brw, params, params-dst,
I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index aa9a3ef..68c7ca1 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -862,6 +862,7 @@ gen7_blorp_exec(struct intel_context *intel,
   uint32_t wm_surf_offset_renderbuffer;
   uint32_t wm_surf_offset_texture = 0;
   wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params);
+  intel_miptree_used_for_rendering(params-dst.mt);
   wm_surf_offset_renderbuffer =
  gen7_blorp_emit_surface_state(brw, params, params-dst,
I915_GEM_DOMAIN_RENDER,
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 22ceaa5..6a7c8de 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -545,6 +545,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
 8 * 4, 32, brw-wm.surf_offset[unit]);
memset(surf, 0, 8 * 4);
 
+   intel_miptree_used_for_rendering(irb-mt);
+
/* Render targets can't use IMS layout */
assert(irb-mt-msaa_layout != INTEL_MSAA_LAYOUT_IMS);
 
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index ee763e5..601666c 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -154,6 +154,9 @@ intel_miptree_create_layout(struct intel_context *intel,
mt-logical_width0 = width0;
mt-logical_height0 = height0;
mt-logical_depth0 = depth0;
+#ifndef I915
+   mt-mcs_state = INTEL_MCS_STATE_NONE;
+#endif
 
/* The cpp is bytes per (1, blockheight)-sized block for compressed
 * textures.  This is why you'll see divides by blockheight all over
@@ -1048,6 +1051,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
 *
 * The MCS surface must be stored as Tile Y.
 */
+   mt-mcs_state = INTEL_MCS_STATE_MSAA;
mt-mcs_mt = intel_miptree_create(intel,
  mt-target,
  format,
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 639d4be..d66d0b5 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -200,6 +200,74 @@ enum intel_msaa_layout
INTEL_MSAA_LAYOUT_CMS,
 };
 
+
+#ifndef I915
+/**
+ * Enum for keeping track of the state of an MCS buffer

Mesa (master): i965/gen7+: Ensure that front/ back buffers are fast-clear resolved.

[Paul Berry]

Module: Mesa
Branch: master
Commit: e9dfcb38e97ac05023759b749fb6f8f56ab28f57
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9dfcb38e97ac05023759b749fb6f8f56ab28f57

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May  7 15:38:45 2013 -0700

i965/gen7+: Ensure that front/back buffers are fast-clear resolved.

We already had code in intel_downsample_for_dri2_flush() for
downsampling front and back buffers when multisampling was in use.
This patch extends that function to perform fast color clear resolves
when necessary.

To account for the additional functionality, the function is renamed
to simply intel_resolve_for_dri2_flush().

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_context.c |   21 -
 src/mesa/drivers/dri/intel/intel_context.h |4 ++--
 src/mesa/drivers/dri/intel/intel_screen.c  |2 +-
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_context.c 
b/src/mesa/drivers/dri/intel/intel_context.c
index 09b33b1..f669ae0 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -95,12 +95,12 @@ intelGetString(struct gl_context * ctx, GLenum name)
 }
 
 void
-intel_downsample_for_dri2_flush(struct intel_context *intel,
-__DRIdrawable *drawable)
+intel_resolve_for_dri2_flush(struct intel_context *intel,
+ __DRIdrawable *drawable)
 {
if (intel-gen  6) {
-  /* MSAA is not supported, so don't waste time checking for
-   * a multisample buffer.
+  /* MSAA and fast color clear are not supported, so don't waste time
+   * checking whether a resolve is needed.
*/
   return;
}
@@ -120,7 +120,10 @@ intel_downsample_for_dri2_flush(struct intel_context 
*intel,
   rb = intel_get_renderbuffer(fb, buffers[i]);
   if (rb == NULL || rb-mt == NULL)
  continue;
-  intel_miptree_downsample(intel, rb-mt);
+  if (rb-mt-num_samples = 1)
+ intel_miptree_resolve_color(intel, rb-mt);
+  else
+ intel_miptree_downsample(intel, rb-mt);
}
 }
 
@@ -137,14 +140,14 @@ intel_flush_front(struct gl_context *ctx)
   driDrawable 
   driDrawable-loaderPrivate) {
 
- /* Downsample before flushing FAKE_FRONT_LEFT to FRONT_LEFT.
+ /* Resolve before flushing FAKE_FRONT_LEFT to FRONT_LEFT.
   *
-  * This potentially downsamples both front and back buffer. It
-  * is unnecessary to downsample the back, but harms nothing except
+  * This potentially resolves both front and back buffer. It
+  * is unnecessary to resolve the back, but harms nothing except
   * performance. And no one cares about front-buffer render
   * performance.
   */
- intel_downsample_for_dri2_flush(intel, driDrawable);
+ intel_resolve_for_dri2_flush(intel, driDrawable);
 
  screen-dri2.loader-flushFrontBuffer(driDrawable,
driDrawable-loaderPrivate);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h 
b/src/mesa/drivers/dri/intel/intel_context.h
index 5420e76..552b9cf 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -615,8 +615,8 @@ void intel_update_renderbuffers(__DRIcontext *context,
 void intel_prepare_render(struct intel_context *intel);
 
 void
-intel_downsample_for_dri2_flush(struct intel_context *intel,
-__DRIdrawable *drawable);
+intel_resolve_for_dri2_flush(struct intel_context *intel,
+ __DRIdrawable *drawable);
 
 void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
  uint32_t buffer_id);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c 
b/src/mesa/drivers/dri/intel/intel_screen.c
index 325304d..b4758f9 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -170,7 +170,7 @@ intelDRI2Flush(__DRIdrawable *drawable)
if (intel-gen  4)
   INTEL_FIREVERTICES(intel);
 
-   intel_downsample_for_dri2_flush(intel, drawable);
+   intel_resolve_for_dri2_flush(intel, drawable);
intel-need_throttle = true;
 
if (intel-batch.used)

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Mesa (master): i965/blorp: Write blorp code to do render target resolves.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 418aecea7d626d57da8987c062aeb3d046c6dd9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=418aecea7d626d57da8987c062aeb3d046c6dd9a

Author: Paul Berry stereotype...@gmail.com
Date:   Mon May  6 10:37:04 2013 -0700

i965/blorp: Write blorp code to do render target resolves.

This patch implements the render target resolve blorp operation.
This will be needed when a buffer that has experienced a fast color
clear is later used for a purpose other than as a render target
(texturing, glReadPixels, or swapped to the screen).  It resolves any
remaining deferred clear operation that was not taken care of during
normal rendering.

Fortunately not much work is necessary; all we need to do is scale
down the size of the rectangle primitive being emitted, run the
fragment shader with the Render Target Resolve Enable bit set, and
ensure that the fragment shader writes to the render target using the
replicated color message.  We already have a fragment shader that
does that (the shader that we use for fast color clears), so for
simplicity we re-use it.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_blorp.h  |5 ++
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp  |   60 
 src/mesa/drivers/dri/i965/brw_defines.h|1 +
 src/mesa/drivers/dri/i965/gen7_blorp.cpp   |3 +
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |   23 +
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h |4 ++
 6 files changed, 96 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h 
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0808206..ffc27cc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -50,6 +50,10 @@ bool
 brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
   bool partial_clear);
 
+void
+brw_blorp_resolve_color(struct intel_context *intel,
+struct intel_mipmap_tree *mt);
+
 #ifdef __cplusplus
 } /* end extern C */
 
@@ -197,6 +201,7 @@ struct brw_blorp_prog_data
 enum gen7_fast_clear_op {
GEN7_FAST_CLEAR_OP_NONE,
GEN7_FAST_CLEAR_OP_FAST_CLEAR,
+   GEN7_FAST_CLEAR_OP_RESOLVE,
 };
 
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 8df493e..1e2205e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -68,6 +68,20 @@ public:
   bool partial_clear);
 };
 
+
+/**
+ * Parameters for a blorp operation that performs a render target resolve.
+ * This is used to resolve pending fast clear pixels before a color buffer is
+ * used for texturing, ReadPixels, or scanout.
+ */
+class brw_blorp_rt_resolve_params : public brw_blorp_const_color_params
+{
+public:
+   brw_blorp_rt_resolve_params(struct brw_context *brw,
+   struct intel_mipmap_tree *mt);
+};
+
+
 class brw_blorp_const_color_program
 {
 public:
@@ -266,6 +280,43 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct 
brw_context *brw,
}
 }
 
+
+brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params(
+  struct brw_context *brw,
+  struct intel_mipmap_tree *mt)
+{
+   dst.set(brw, mt, 0 /* level */, 0 /* layer */);
+
+   /* From the Ivy Bridge PRM, Vol2 Part1 11.9 Render Target Resolve:
+*
+* A rectangle primitive must be scaled down by the following factors
+* with respect to render target being resolved.
+*
+* The scaledown factors in the table that follows are related to the
+* alignment size returned by intel_get_non_msrt_mcs_alignment(), but with
+* X and Y alignment each divided by 2.
+*/
+   unsigned x_align, y_align;
+   intel_get_non_msrt_mcs_alignment(brw-intel, mt, x_align, y_align);
+   unsigned x_scaledown = x_align / 2;
+   unsigned y_scaledown = y_align / 2;
+   x0 = y0 = 0;
+   x1 = ALIGN(mt-logical_width0, x_scaledown) / x_scaledown;
+   y1 = ALIGN(mt-logical_height0, y_scaledown) / y_scaledown;
+
+   fast_clear_op = GEN7_FAST_CLEAR_OP_RESOLVE;
+
+   /* Note: there is no need to initialize push constants because it doesn't
+* matter what data gets dispatched to the render target.  However, we must
+* ensure that the fragment shader delivers the data using the replicated
+* color message.
+*/
+   use_wm_prog = true;
+   memset(wm_prog_key, 0, sizeof(wm_prog_key));
+   wm_prog_key.use_simd16_replicated_data = true;
+}
+
+
 uint32_t
 brw_blorp_const_color_params::get_wm_prog(struct brw_context *brw,
   brw_blorp_prog_data **prog_data)
@@ -452,4 +503,13 @@ brw_blorp_clear_color(struct intel_context *intel, struct 
gl_framebuffer *fb,
return true;
 }
 
+void
+brw_blorp_resolve_color(struct intel_context *intel, struct intel_mipmap_tree 
*mt)
+{
+   struct brw_context *brw = brw_context(intel-ctx

Mesa (master): i965/gen7: Enable support for fast color clears.

[Paul Berry]

Module: Mesa
Branch: master
Commit: b09a75407886fba476bb79d65b408ffc08876a75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b09a75407886fba476bb79d65b408ffc08876a75

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May 21 11:58:38 2013 -0700

i965/gen7: Enable support for fast color clears.

This patch adds code to place mcs_state into INTEL_MCS_STATE_RESOLVED
for miptrees that are capable of supporting fast color clears.  This
will have no effect on buffers that don't undergo a fast color clear;
however, for buffers that do undergo a fast color clear, an MCS
miptree will be allocated (at the time of the first fast clear), and
will be used thereafter.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/intel/intel_mipmap_tree.c |   20 
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 5b767df..1776a4b 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -608,6 +608,16 @@ intel_miptree_create(struct intel_context *intel,
return NULL;
}
 
+#ifndef I915
+   /* If this miptree is capable of supporting fast color clears, set
+* mcs_state appropriately to ensure that fast clears will occur.
+* Allocation of the MCS miptree will be deferred until the first fast
+* clear actually occurs.
+*/
+   if (intel_is_non_msrt_mcs_buffer_supported(intel, mt))
+  mt-mcs_state = INTEL_MCS_STATE_RESOLVED;
+#endif
+
return mt;
 }
 
@@ -699,6 +709,16 @@ intel_miptree_create_for_dri2_buffer(struct intel_context 
*intel,
   return NULL;
singlesample_mt-region-name = region-name;
 
+#ifndef I915
+   /* If this miptree is capable of supporting fast color clears, set
+* mcs_state appropriately to ensure that fast clears will occur.
+* Allocation of the MCS miptree will be deferred until the first fast
+* clear actually occurs.
+*/
+   if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt))
+  singlesample_mt-mcs_state = INTEL_MCS_STATE_RESOLVED;
+#endif
+
if (num_samples == 0)
   return singlesample_mt;
 

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Mesa (master): i965/gen7+: Resolve color buffers when necessary.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 67cd0f97030a358777c01ee6ad79926717dfdf42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67cd0f97030a358777c01ee6ad79926717dfdf42

Author: Paul Berry stereotype...@gmail.com
Date:   Tue May  7 14:55:42 2013 -0700

i965/gen7+: Resolve color buffers when necessary.

Resolve color buffers that have been fast-color cleared:
1. before texturing from the buffer (brw_predraw_resolve_buffers())
2. before using the buffer as the source in a blorp blit
   (brw_blorp_blit_miptrees())
3. before mapping the buffer's miptree (intel_miptree_map_raw(),
   intel_texsubimage_tiled_memcpy())
4. before accessing the buffer using the hardware blitter
   (intel_miptree_blit(), do_blit_bitmap())

v2: Rework based on the fact that we have decided not to use an
accessor function to protect access to the region.

Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp|7 +++
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp   |1 +
 src/mesa/drivers/dri/i965/brw_draw.c|6 +-
 src/mesa/drivers/dri/intel/intel_blit.c |   11 +--
 src/mesa/drivers/dri/intel/intel_mipmap_tree.c  |5 +
 src/mesa/drivers/dri/intel/intel_pixel_bitmap.c |5 +
 src/mesa/drivers/dri/intel/intel_tex_subimage.c |5 +
 7 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index a6b2bbf..7b063ff 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -134,6 +134,13 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
 float dst_x1, float dst_y1,
 bool mirror_x, bool mirror_y)
 {
+   /* Get ready to blit.  This includes depth resolving the src and dst
+* buffers if necessary.  Note: it's not necessary to do a color resolve on
+* the destination buffer because we use the standard render path to render
+* to destination color buffers, and the standard render path is
+* fast-color-aware.
+*/
+   intel_miptree_resolve_color(intel, src_mt);
intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_layer);
intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_layer);
 
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 1e2205e..85449bd 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -507,6 +507,7 @@ void
 brw_blorp_resolve_color(struct intel_context *intel, struct intel_mipmap_tree 
*mt)
 {
struct brw_context *brw = brw_context(intel-ctx);
+
brw_blorp_rt_resolve_params params(brw, mt);
brw_blorp_exec(intel, params);
mt-mcs_state = INTEL_MCS_STATE_RESOLVED;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 657d6ee..5730eed 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -41,6 +41,7 @@
 #include swrast_setup/swrast_setup.h
 #include drivers/common/meta.h
 
+#include brw_blorp.h
 #include brw_draw.h
 #include brw_defines.h
 #include brw_context.h
@@ -310,7 +311,9 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
if (depth_irb)
   intel_renderbuffer_resolve_hiz(intel, depth_irb);
 
-   /* Resolve depth buffer of each enabled depth texture. */
+   /* Resolve depth buffer of each enabled depth texture, and color buffer of
+* each fast-clear-enabled color texture.
+*/
for (int i = 0; i  BRW_MAX_TEX_UNIT; i++) {
   if (!ctx-Texture.Unit[i]._ReallyEnabled)
 continue;
@@ -318,6 +321,7 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
   if (!tex_obj || !tex_obj-mt)
 continue;
   intel_miptree_all_slices_resolve_depth(intel, tex_obj-mt);
+  intel_miptree_resolve_color(intel, tex_obj-mt);
}
 }
 
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c 
b/src/mesa/drivers/dri/intel/intel_blit.c
index 1f6ad09..fffbef4 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -140,11 +140,13 @@ intel_miptree_blit(struct intel_context *intel,
   return false;
}
 
-   /* The blitter has no idea about HiZ, so we need to get the real depth
-* data into the two miptrees before we do anything.
+   /* The blitter has no idea about HiZ or fast color clears, so we need to
+* resolve the miptrees before we do anything.
 */
intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_slice);
+   intel_miptree_resolve_color(intel, src_mt);
+   intel_miptree_resolve_color(intel, dst_mt);
 
if (src_flip)
   src_y = src_mt-level[src_level].height - src_y - height;
@@ -368,6 +370,11 @@ intelClearWithBlit(struct gl_context *ctx

Mesa (master): i965: Add an assertion to brwProgramStringNotify.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 292368570a13501dfa95b1b0dd70966caf6ffc6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=292368570a13501dfa95b1b0dd70966caf6ffc6b

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Jul  2 08:02:47 2013 -0700

i965: Add an assertion to brwProgramStringNotify.

driver-ProgramStringNotify is only called for ARB programs, fixed
function vertex programs, and ir_to_mesa (which isn't used by the i965
back-end).  Therefore, even after geometry shaders are added,
brwProgramStringNotify should only ever be called with a target of
GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.

This patch adds an assertion to clarify that.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_program.c |   18 --
 1 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 87986a9..cd37e70 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -126,7 +126,8 @@ brwProgramStringNotify(struct gl_context *ctx,
 {
struct brw_context *brw = brw_context(ctx);
 
-   if (target == GL_FRAGMENT_PROGRAM_ARB) {
+   switch (target) {
+   case GL_FRAGMENT_PROGRAM_ARB: {
   struct gl_fragment_program *fprog = (struct gl_fragment_program *) prog;
   struct brw_fragment_program *newFP = brw_fragment_program(fprog);
   const struct brw_fragment_program *curFP =
@@ -135,8 +136,9 @@ brwProgramStringNotify(struct gl_context *ctx,
   if (newFP == curFP)
 brw-state.dirty.brw |= BRW_NEW_FRAGMENT_PROGRAM;
   newFP-id = get_new_program_id(brw-intel.intelScreen);
+  break;
}
-   else if (target == GL_VERTEX_PROGRAM_ARB) {
+   case GL_VERTEX_PROGRAM_ARB: {
   struct gl_vertex_program *vprog = (struct gl_vertex_program *) prog;
   struct brw_vertex_program *newVP = brw_vertex_program(vprog);
   const struct brw_vertex_program *curVP =
@@ -152,6 +154,18 @@ brwProgramStringNotify(struct gl_context *ctx,
   /* Also tell tnl about it:
*/
   _tnl_program_string(ctx, target, prog);
+  break;
+   }
+   default:
+  /*
+   * driver-ProgramStringNotify is only called for ARB programs, fixed
+   * function vertex programs, and ir_to_mesa (which isn't used by the
+   * i965 back-end).  Therefore, even after geometry shaders are added,
+   * this function should only ever be called with a target of
+   * GL_VERTEX_PROGRAM_ARB or GL_FRAGMENT_PROGRAM_ARB.
+   */
+  assert(!Unexpected target in brwProgramStringNotify);
+  break;
}
 
brw_add_texrect_params(prog);

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Mesa (master): glsl ES: Fix magnitude of gl_MaxVertexUniformVectors.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8f51d68f8c2020ad35b442c4af693ad7a5e5dd0d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f51d68f8c2020ad35b442c4af693ad7a5e5dd0d

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Jul  7 11:47:22 2013 -0700

glsl ES: Fix magnitude of gl_MaxVertexUniformVectors.

Previously, we set it equal to MaxVertexUniformComponents.  It should
be MaxVertexUniformComponents / 4.

NOTE: This is a candidate for the stable branches.

Cc: mesa-sta...@lists.freedesktop.org

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/builtin_variables.cpp |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp
index f4ac205..58019c6 100644
--- a/src/glsl/builtin_variables.cpp
+++ b/src/glsl/builtin_variables.cpp
@@ -533,7 +533,7 @@ generate_common_ES_uniforms(exec_list *instructions,
add_builtin_constant(instructions, symtab, gl_MaxVertexAttribs,
state-Const.MaxVertexAttribs);
add_builtin_constant(instructions, symtab, gl_MaxVertexUniformVectors,
-   state-Const.MaxVertexUniformComponents);
+   state-Const.MaxVertexUniformComponents / 4);
add_builtin_constant(instructions, symtab, gl_MaxVertexTextureImageUnits,
state-Const.MaxVertexTextureImageUnits);
add_builtin_constant(instructions, symtab, 
gl_MaxCombinedTextureImageUnits,

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Mesa (master): glsl: Make gl_TexCoord compatibility-only

[Paul Berry]

Module: Mesa
Branch: master
Commit: c6bfe62e2166e44f035df3d7788ac2f97609f3d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6bfe62e2166e44f035df3d7788ac2f97609f3d2

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Jul  7 11:49:22 2013 -0700

glsl: Make gl_TexCoord compatibility-only

gl_TexCoord was deprecated in GLSL 1.30.  In GLSL 1.40 it was marked
as ARB_compatibility-only, and in GLSL 1.50 and above it was marked as
only appearing in the compatibility profile.  It has never appeared in
GLSL ES.

However, Mesa erroneously included it in all desktop versions of GLSL,
even versions 1.40 and 1.50 (which do not currently support the
compatibility profile).  This patch makes gl_TexCoord available in the
compatibility profile (and GLSL versions 1.30 and prior) only.

NOTE: although this is a simple bug fix, it probably isn't sensible to
cherry-pick it to stable release branches, since its only effect is to
cause incorrectly-written shaders to fail to compile.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/builtin_variables.cpp |   56 +--
 1 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/src/glsl/builtin_variables.cpp b/src/glsl/builtin_variables.cpp
index 58019c6..eccd15a 100644
--- a/src/glsl/builtin_variables.cpp
+++ b/src/glsl/builtin_variables.cpp
@@ -748,20 +748,22 @@ generate_110_vs_variables(exec_list *instructions,
}
generate_110_uniforms(instructions, state, add_deprecated);
 
-   /* From page 54 (page 60 of the PDF) of the GLSL 1.20 spec:
-*
-* As with all arrays, indices used to subscript gl_TexCoord must
-* either be an integral constant expressions, or this array must be
-* re-declared by the shader with a size. The size can be at most
-* gl_MaxTextureCoords. Using indexes close to 0 may aid the
-* implementation in preserving varying resources.
-*/
-   const glsl_type *const vec4_array_type =
-  glsl_type::get_array_instance(glsl_type::vec4_type, 0);
+   if (add_deprecated) {
+  /* From page 54 (page 60 of the PDF) of the GLSL 1.20 spec:
+   *
+   * As with all arrays, indices used to subscript gl_TexCoord must
+   * either be an integral constant expressions, or this array must be
+   * re-declared by the shader with a size. The size can be at most
+   * gl_MaxTextureCoords. Using indexes close to 0 may aid the
+   * implementation in preserving varying resources.
+   */
+  const glsl_type *const vec4_array_type =
+ glsl_type::get_array_instance(glsl_type::vec4_type, 0);
 
-   add_variable(instructions, state-symbols,
-   gl_TexCoord, vec4_array_type, ir_var_shader_out,
-VARYING_SLOT_TEX0);
+  add_variable(instructions, state-symbols,
+   gl_TexCoord, vec4_array_type, ir_var_shader_out,
+   VARYING_SLOT_TEX0);
+   }
 
generate_ARB_draw_buffers_variables(instructions, state, false,
   vertex_shader);
@@ -944,20 +946,22 @@ generate_110_fs_variables(exec_list *instructions,
 
generate_110_uniforms(instructions, state, add_deprecated);
 
-   /* From page 54 (page 60 of the PDF) of the GLSL 1.20 spec:
-*
-* As with all arrays, indices used to subscript gl_TexCoord must
-* either be an integral constant expressions, or this array must be
-* re-declared by the shader with a size. The size can be at most
-* gl_MaxTextureCoords. Using indexes close to 0 may aid the
-* implementation in preserving varying resources.
-*/
-   const glsl_type *const vec4_array_type =
-  glsl_type::get_array_instance(glsl_type::vec4_type, 0);
+   if (add_deprecated) {
+  /* From page 54 (page 60 of the PDF) of the GLSL 1.20 spec:
+   *
+   * As with all arrays, indices used to subscript gl_TexCoord must
+   * either be an integral constant expressions, or this array must be
+   * re-declared by the shader with a size. The size can be at most
+   * gl_MaxTextureCoords. Using indexes close to 0 may aid the
+   * implementation in preserving varying resources.
+   */
+  const glsl_type *const vec4_array_type =
+ glsl_type::get_array_instance(glsl_type::vec4_type, 0);
 
-   add_variable(instructions, state-symbols,
-   gl_TexCoord, vec4_array_type, ir_var_shader_in,
-VARYING_SLOT_TEX0);
+  add_variable(instructions, state-symbols,
+   gl_TexCoord, vec4_array_type, ir_var_shader_in,
+   VARYING_SLOT_TEX0);
+   }
 
generate_ARB_draw_buffers_variables(instructions, state, false,
   fragment_shader);

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Mesa (master): glsl: don't rename variables in interface block arrays.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 42a921fa92fae8fb8692e7c65c61235588385b3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42a921fa92fae8fb8692e7c65c61235588385b3e

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Jul 22 15:49:48 2013 -0700

glsl: don't rename variables in interface block arrays.

The linker matches up variables in interface blocks according to their
block name and variable name.  When support for interface block arrays
was added in commit d6863acb, we renamed variables appearing in
interface blocks so that their name included the array size.  For
example, in a block like this:

out foo {
   float bar
} baz[3];

The variable bar would get renamed to bar[3].

This is unnecessary, and leads to problems in supporting geometry
shaders, since geometry shaders require vertex shader outputs which
are non-arrays to be linked up to geometry shader inputs which are
arrays.

This patch makes the behaviour of interface block arrays the same as
simple non-array interface blocks; in both cases, the variables
contained within them are not renamed.

Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/lower_named_interface_blocks.cpp |8 ++--
 1 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/glsl/lower_named_interface_blocks.cpp 
b/src/glsl/lower_named_interface_blocks.cpp
index d0d491d..20196a3 100644
--- a/src/glsl/lower_named_interface_blocks.cpp
+++ b/src/glsl/lower_named_interface_blocks.cpp
@@ -129,9 +129,9 @@ flatten_named_interface_blocks_declarations::run(exec_list 
*instructions)
 iface_field_name);
  if (!found_var) {
 ir_variable *new_var;
+char *var_name =
+   ralloc_strdup(mem_ctx, iface_t-fields.structure[i].name);
 if (array_t == NULL) {
-   char *var_name =
-  ralloc_strdup(mem_ctx, iface_t-fields.structure[i].name);
new_var =
   new(mem_ctx) ir_variable(iface_t-fields.structure[i].type,
var_name,
@@ -141,10 +141,6 @@ flatten_named_interface_blocks_declarations::run(exec_list 
*instructions)
   glsl_type::get_array_instance(
  iface_t-fields.structure[i].type,
  array_t-length);
-   char *var_name =
-  ralloc_asprintf(mem_ctx, %s[%d],
-  iface_t-fields.structure[i].name,
-  array_t-length);
new_var =
   new(mem_ctx) ir_variable(new_array_type,
var_name,

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Mesa (master): i965: Initialize inout_offset parameter to brw_search_cache( ).

[Paul Berry]

Module: Mesa
Branch: master
Commit: b8f13fbb856534cbc1345325b74ec47711493dd6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8f13fbb856534cbc1345325b74ec47711493dd6

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Jul 24 09:24:51 2013 -0700

i965: Initialize inout_offset parameter to brw_search_cache().

Two callers of brw_search_cache() weren't initializing that function's
inout_offset parameter: brw_blorp_const_color_params::get_wm_prog()
and brw_blorp_const_color_params::get_wm_prog().

That's a benign problem, since the only effect of not initializing
inout_offset prior to calling brw_search_cache() is that the bit
corresponding to cache_id in brw-state.dirty.cache may not be set
reliably.  This is ok, since the cache_id's used by
brw_blorp_const_color_params::get_wm_prog() and
brw_blorp_blit_params::get_wm_prog() (BRW_BLORP_CONST_COLOR_PROG and
BRW_BLORP_BLIT_PROG, respectively) correspond to dirty bits that are
not used.

However, failing to initialize this parameter causes valgrind to
complain.  So let's go ahead and fix it to reduce valgrind noise.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66779

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  |2 +-
 src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 6610ef0..bce2d4d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -2280,7 +2280,7 @@ uint32_t
 brw_blorp_blit_params::get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const
 {
-   uint32_t prog_offset;
+   uint32_t prog_offset = 0;
if (!brw_search_cache(brw-cache, BRW_BLORP_BLIT_PROG,
  this-wm_prog_key, sizeof(this-wm_prog_key),
  prog_offset, prog_data)) {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 6588b7f..f26f39d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -342,7 +342,7 @@ brw_blorp_const_color_params::get_wm_prog(struct 
brw_context *brw,
   brw_blorp_prog_data **prog_data)
const
 {
-   uint32_t prog_offset;
+   uint32_t prog_offset = 0;
if (!brw_search_cache(brw-cache, BRW_BLORP_CONST_COLOR_PROG,
  this-wm_prog_key, sizeof(this-wm_prog_key),
  prog_offset, prog_data)) {

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Mesa (master): glsl: Handle empty if statement encountered during loop analysis.

[Paul Berry]

Module: Mesa
Branch: master
Commit: a5eecb246d66fd8f27eca3c4f6f83bf2641b9403
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5eecb246d66fd8f27eca3c4f6f83bf2641b9403

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Jul 24 08:04:44 2013 -0700

glsl: Handle empty if statement encountered during loop analysis.

The is_loop_terminator() function was asserting that the following
kind of if statement could never occur:

if (...) { } else { }

(presumably based on the assumption that such an if statement would be
eliminated by previous optimization stages).  But that isn't the
case--it's possible that previous optimization stages might simplify
more complex code down to this empty if statement, in which case it
won't be eliminated until the next time through the optimization loop.

So is_loop_terminator() needs to handle it.  Fortunately it's easy to
handle--it's not a loop terminator because it does nothing.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64330
CC: mesa-sta...@lists.freedesktop.org

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/loop_analysis.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/glsl/loop_analysis.cpp b/src/glsl/loop_analysis.cpp
index 191e92d..40897bb 100644
--- a/src/glsl/loop_analysis.cpp
+++ b/src/glsl/loop_analysis.cpp
@@ -503,7 +503,8 @@ is_loop_terminator(ir_if *ir)
 
ir_instruction *const inst =
   (ir_instruction *) ir-then_instructions.get_head();
-   assert(inst != NULL);
+   if (inst == NULL)
+  return false;
 
if (inst-ir_type != ir_type_loop_jump)
   return false;

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Mesa (wip): glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

[Paul Berry]

Module: Mesa
Branch: wip
Commit: 4d7899fe81b6ffc521c6f9688e25bcde4012e556
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d7899fe81b6ffc521c6f9688e25bcde4012e556

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Jul 25 19:56:43 2013 -0700

glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

The majority of calls to _mesa_glsl_error(), _mesa_glsl_warning(), and
_mesa_glsl_parse_state::check_version() use a message that begins with
a lower case letter and ends without a period.  This patch makes all
messages follow that convention.

Also, error/warning messages shouldn't end in '\n', since
_mesa_glsl_msg() automatically adds '\n' at the end of the message.

Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/ast_function.cpp |2 +-
 src/glsl/ast_to_hir.cpp   |  100 ++--
 src/glsl/ast_type.cpp |2 +-
 src/glsl/glsl_lexer.ll|   10 ++--
 src/glsl/glsl_parser.yy   |   92 +-
 src/glsl/glsl_parser_extras.cpp   |   16 ++--
 src/glsl/hir_field_selection.cpp  |   20 +++---
 src/glsl/ir_function_detect_recursion.cpp |2 +-
 8 files changed, 122 insertions(+), 122 deletions(-)

diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index e34c1dd..7df2b69 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -626,7 +626,7 @@ process_vec_mat_constructor(exec_list *instructions,
 *  int i = { 1 }; // illegal, i is not an aggregate
 */
if (constructor_type-vector_elements = 1) {
-  _mesa_glsl_error(loc, state, Aggregates can only initialize vectors, 
+  _mesa_glsl_error(loc, state, aggregates can only initialize vectors, 
matrices, arrays, and structs);
   return ir_rvalue::error_value(ctx);
}
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index bfd5fda..2569cde 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -195,7 +195,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
 */
if (!type_a-is_numeric() || !type_b-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -207,7 +207,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   arithmetic operator);
   return glsl_type::error_type;
}
@@ -386,7 +386,7 @@ unary_arithmetic_result_type(const struct glsl_type *type,
 */
if (!type-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -473,11 +473,11 @@ modulus_result_type(const struct glsl_type *type_a,
 *unsigned.
 */
if (!type_a-is_integer()) {
-  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (!type_b-is_integer()) {
-  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (type_a-base_type != type_b-base_type) {
@@ -523,7 +523,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
|| !type_a-is_scalar()
|| !type_b-is_scalar()) {
   _mesa_glsl_error(loc, state,
-  Operands to relational operators must be scalar and 
+  operands to relational operators must be scalar and 
   numeric);
   return glsl_type::error_type;
}
@@ -535,7 +535,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   relational operator);
   return glsl_type::error_type;
}
@@ -593,7 +593,7 @@ shift_result_type(const struct glsl_type *type_a,
 * a scalar as well.
 */
if (type_a-is_scalar()  !type_b-is_scalar()) {
-  _mesa_glsl_error(loc, state, If the first operand of %s is scalar, the 
+  _mesa_glsl_error(loc, state

Mesa (wip): glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

[Paul Berry]

Module: Mesa
Branch: wip
Commit: 0809899f89a8efa04bdc52d44a170234d02cdd7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0809899f89a8efa04bdc52d44a170234d02cdd7c

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Jul 25 19:56:43 2013 -0700

glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

The majority of calls to _mesa_glsl_error(), _mesa_glsl_warning(), and
_mesa_glsl_parse_state::check_version() use a message that begins with
a lower case letter and ends without a period.  This patch makes all
messages follow that convention.

Also, error/warning messages shouldn't end in '\n', since
_mesa_glsl_msg() automatically adds '\n' at the end of the message.

---

 src/glsl/ast_function.cpp |2 +-
 src/glsl/ast_to_hir.cpp   |  100 ++--
 src/glsl/ast_type.cpp |2 +-
 src/glsl/glsl_lexer.ll|   10 ++--
 src/glsl/glsl_parser.yy   |   92 +-
 src/glsl/glsl_parser_extras.cpp   |   16 ++--
 src/glsl/hir_field_selection.cpp  |   20 +++---
 src/glsl/ir_function_detect_recursion.cpp |2 +-
 8 files changed, 122 insertions(+), 122 deletions(-)

diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index e34c1dd..7df2b69 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -626,7 +626,7 @@ process_vec_mat_constructor(exec_list *instructions,
 *  int i = { 1 }; // illegal, i is not an aggregate
 */
if (constructor_type-vector_elements = 1) {
-  _mesa_glsl_error(loc, state, Aggregates can only initialize vectors, 
+  _mesa_glsl_error(loc, state, aggregates can only initialize vectors, 
matrices, arrays, and structs);
   return ir_rvalue::error_value(ctx);
}
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index bfd5fda..2569cde 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -195,7 +195,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
 */
if (!type_a-is_numeric() || !type_b-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -207,7 +207,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   arithmetic operator);
   return glsl_type::error_type;
}
@@ -386,7 +386,7 @@ unary_arithmetic_result_type(const struct glsl_type *type,
 */
if (!type-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -473,11 +473,11 @@ modulus_result_type(const struct glsl_type *type_a,
 *unsigned.
 */
if (!type_a-is_integer()) {
-  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (!type_b-is_integer()) {
-  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (type_a-base_type != type_b-base_type) {
@@ -523,7 +523,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
|| !type_a-is_scalar()
|| !type_b-is_scalar()) {
   _mesa_glsl_error(loc, state,
-  Operands to relational operators must be scalar and 
+  operands to relational operators must be scalar and 
   numeric);
   return glsl_type::error_type;
}
@@ -535,7 +535,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   relational operator);
   return glsl_type::error_type;
}
@@ -593,7 +593,7 @@ shift_result_type(const struct glsl_type *type_a,
 * a scalar as well.
 */
if (type_a-is_scalar()  !type_b-is_scalar()) {
-  _mesa_glsl_error(loc, state, If the first operand of %s is scalar, the 
+  _mesa_glsl_error(loc, state, if the first operand of %s is scalar

Mesa (master): glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 4d7899fe81b6ffc521c6f9688e25bcde4012e556
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d7899fe81b6ffc521c6f9688e25bcde4012e556

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Jul 25 19:56:43 2013 -0700

glsl: Be consistent about '\n', '.', and capitalization in errors/warnings.

The majority of calls to _mesa_glsl_error(), _mesa_glsl_warning(), and
_mesa_glsl_parse_state::check_version() use a message that begins with
a lower case letter and ends without a period.  This patch makes all
messages follow that convention.

Also, error/warning messages shouldn't end in '\n', since
_mesa_glsl_msg() automatically adds '\n' at the end of the message.

Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/ast_function.cpp |2 +-
 src/glsl/ast_to_hir.cpp   |  100 ++--
 src/glsl/ast_type.cpp |2 +-
 src/glsl/glsl_lexer.ll|   10 ++--
 src/glsl/glsl_parser.yy   |   92 +-
 src/glsl/glsl_parser_extras.cpp   |   16 ++--
 src/glsl/hir_field_selection.cpp  |   20 +++---
 src/glsl/ir_function_detect_recursion.cpp |2 +-
 8 files changed, 122 insertions(+), 122 deletions(-)

diff --git a/src/glsl/ast_function.cpp b/src/glsl/ast_function.cpp
index e34c1dd..7df2b69 100644
--- a/src/glsl/ast_function.cpp
+++ b/src/glsl/ast_function.cpp
@@ -626,7 +626,7 @@ process_vec_mat_constructor(exec_list *instructions,
 *  int i = { 1 }; // illegal, i is not an aggregate
 */
if (constructor_type-vector_elements = 1) {
-  _mesa_glsl_error(loc, state, Aggregates can only initialize vectors, 
+  _mesa_glsl_error(loc, state, aggregates can only initialize vectors, 
matrices, arrays, and structs);
   return ir_rvalue::error_value(ctx);
}
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index bfd5fda..2569cde 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -195,7 +195,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
 */
if (!type_a-is_numeric() || !type_b-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -207,7 +207,7 @@ arithmetic_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   arithmetic operator);
   return glsl_type::error_type;
}
@@ -386,7 +386,7 @@ unary_arithmetic_result_type(const struct glsl_type *type,
 */
if (!type-is_numeric()) {
   _mesa_glsl_error(loc, state,
-  Operands to arithmetic operators must be numeric);
+  operands to arithmetic operators must be numeric);
   return glsl_type::error_type;
}
 
@@ -473,11 +473,11 @@ modulus_result_type(const struct glsl_type *type_a,
 *unsigned.
 */
if (!type_a-is_integer()) {
-  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, LHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (!type_b-is_integer()) {
-  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer.);
+  _mesa_glsl_error(loc, state, RHS of operator %% must be an integer);
   return glsl_type::error_type;
}
if (type_a-base_type != type_b-base_type) {
@@ -523,7 +523,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
|| !type_a-is_scalar()
|| !type_b-is_scalar()) {
   _mesa_glsl_error(loc, state,
-  Operands to relational operators must be scalar and 
+  operands to relational operators must be scalar and 
   numeric);
   return glsl_type::error_type;
}
@@ -535,7 +535,7 @@ relational_result_type(ir_rvalue * value_a, ir_rvalue * 
value_b,
if (!apply_implicit_conversion(type_a, value_b, state)
 !apply_implicit_conversion(type_b, value_a, state)) {
   _mesa_glsl_error(loc, state,
-  Could not implicitly convert operands to 
+  could not implicitly convert operands to 
   relational operator);
   return glsl_type::error_type;
}
@@ -593,7 +593,7 @@ shift_result_type(const struct glsl_type *type_a,
 * a scalar as well.
 */
if (type_a-is_scalar()  !type_b-is_scalar()) {
-  _mesa_glsl_error(loc, state, If the first operand of %s is scalar, the 
+  _mesa_glsl_error(loc

Mesa (master): glsl: Remove bogus check on return value of link_uniform_blocks().

[Paul Berry]

Module: Mesa
Branch: master
Commit: 4682b9b7bf0caa7bd0f6af3ae820a1df08af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4682b9b7bf0caa7bd0f6af3ae820a1df08af

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Jul 27 15:07:08 2013 -0700

glsl: Remove bogus check on return value of link_uniform_blocks().

A comment in link_intrastage_shaders(), and an if-test that followed
it, seemed to indicate that link_uniform_blocks() would return a
negative value in the event of an error.  But this is not the
case--all error checking has already been performed by
validate_intrastage_interface_blocks(), and link_uniform_blocks() can
only return unsigned values.

So get rid of the if-test and change the return type of
link_intrastage_shaders() to clarify that it can only return unsigned
values.

Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/glsl/link_uniform_blocks.cpp |2 +-
 src/glsl/linker.cpp  |6 ++
 src/glsl/linker.h|2 +-
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/glsl/link_uniform_blocks.cpp b/src/glsl/link_uniform_blocks.cpp
index c72d1d8..1083653 100644
--- a/src/glsl/link_uniform_blocks.cpp
+++ b/src/glsl/link_uniform_blocks.cpp
@@ -137,7 +137,7 @@ struct block {
bool has_instance_name;
 };
 
-int
+unsigned
 link_uniform_blocks(void *mem_ctx,
 struct gl_shader_program *prog,
 struct gl_shader **shader_list,
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index ac010cf..4ffd40e 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -964,12 +964,10 @@ link_intrastage_shaders(void *mem_ctx,
  num_shaders))
   return NULL;
 
-   /* Check that uniform blocks between shaders for a stage agree. */
-   const int num_uniform_blocks =
+   /* Link up uniform blocks defined within this stage. */
+   const unsigned num_uniform_blocks =
   link_uniform_blocks(mem_ctx, prog, shader_list, num_shaders,
   uniform_blocks);
-   if (num_uniform_blocks  0)
-  return NULL;
 
/* Check that there is only a single definition of each function signature
 * across all shaders.
diff --git a/src/glsl/linker.h b/src/glsl/linker.h
index 2fe2410..85a6817 100644
--- a/src/glsl/linker.h
+++ b/src/glsl/linker.h
@@ -53,7 +53,7 @@ extern bool
 link_uniform_blocks_are_compatible(const gl_uniform_block *a,
   const gl_uniform_block *b);
 
-extern int
+extern unsigned
 link_uniform_blocks(void *mem_ctx,
 struct gl_shader_program *prog,
 struct gl_shader **shader_list,

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Mesa (master): glsl: Add error message for intrastage interface block mismatch.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 659ec1c958b59b77b5334d1121722ea0c80dddf8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=659ec1c958b59b77b5334d1121722ea0c80dddf8

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Jul 27 14:58:43 2013 -0700

glsl: Add error message for intrastage interface block mismatch.

Previously we failed to link (which is correct), but we did not output
an error message, which could have been confusing for users.

Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/glsl/link_interface_blocks.cpp |5 -
 src/glsl/linker.cpp|3 ++-
 src/glsl/linker.h  |3 ++-
 3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/glsl/link_interface_blocks.cpp 
b/src/glsl/link_interface_blocks.cpp
index b91860d..4f67291 100644
--- a/src/glsl/link_interface_blocks.cpp
+++ b/src/glsl/link_interface_blocks.cpp
@@ -32,7 +32,8 @@
 #include main/macros.h
 
 bool
-validate_intrastage_interface_blocks(const gl_shader **shader_list,
+validate_intrastage_interface_blocks(struct gl_shader_program *prog,
+ const gl_shader **shader_list,
  unsigned num_shaders)
 {
glsl_symbol_table interfaces;
@@ -62,6 +63,8 @@ validate_intrastage_interface_blocks(const gl_shader 
**shader_list,
 interfaces.add_interface(iface_type-name, iface_type,
  (enum ir_variable_mode) var-mode);
  } else if (old_iface_type != iface_type) {
+linker_error(prog, definitions of interface block `%s' do not
+  match\n, iface_type-name);
 return false;
  }
   }
diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 4ffd40e..3d9c59d 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -960,7 +960,8 @@ link_intrastage_shaders(void *mem_ctx,
 
/* Check that interface blocks defined in multiple shaders are consistent.
 */
-   if (!validate_intrastage_interface_blocks((const gl_shader **)shader_list,
+   if (!validate_intrastage_interface_blocks(prog,
+ (const gl_shader **)shader_list,
  num_shaders))
   return NULL;
 
diff --git a/src/glsl/linker.h b/src/glsl/linker.h
index 85a6817..9f5deb5 100644
--- a/src/glsl/linker.h
+++ b/src/glsl/linker.h
@@ -61,7 +61,8 @@ link_uniform_blocks(void *mem_ctx,
 struct gl_uniform_block **blocks_ret);
 
 bool
-validate_intrastage_interface_blocks(const gl_shader **shader_list,
+validate_intrastage_interface_blocks(struct gl_shader_program *prog,
+ const gl_shader **shader_list,
  unsigned num_shaders);
 
 bool

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Mesa (master): glsl: Improve error message for interstage interface block mismatch.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 5fe6b90c87c055fdfe24eb8b2075e6725ad59ecd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fe6b90c87c055fdfe24eb8b2075e6725ad59ecd

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Jul 27 15:24:46 2013 -0700

glsl: Improve error message for interstage interface block mismatch.

We're now emitting this error from a point where we have easy access
to the name of the block that failed to match, so go ahead and include
that in the error message, as we do for intrastage interface block
mismatches.

Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/glsl/link_interface_blocks.cpp |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/glsl/link_interface_blocks.cpp 
b/src/glsl/link_interface_blocks.cpp
index ffb4453..928a88e 100644
--- a/src/glsl/link_interface_blocks.cpp
+++ b/src/glsl/link_interface_blocks.cpp
@@ -105,7 +105,8 @@ validate_interstage_interface_blocks(struct 
gl_shader_program *prog,
  continue;
 
   if (var-interface_type != expected_type) {
- linker_error(prog, interface block mismatch between shader 
stages\n);
+ linker_error(prog, definitions of interface block `%s' do not 
+  match\n, var-interface_type-name);
  return;
   }
}

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Mesa (master): glsl: Remove redundant writes to prog-LinkStatus

[Paul Berry]

Module: Mesa
Branch: master
Commit: 1299694ed5e3c2f51c076b020a9ad2fef2e1d059
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1299694ed5e3c2f51c076b020a9ad2fef2e1d059

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Jul 27 15:37:15 2013 -0700

glsl: Remove redundant writes to prog-LinkStatus

The linker_error() function sets prog-LinkStatus to false.  There's
no reason for the caller of linker_error() to also do so.

Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/glsl/ir_function_detect_recursion.cpp |1 -
 src/mesa/program/ir_to_mesa.cpp   |1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/src/glsl/ir_function_detect_recursion.cpp 
b/src/glsl/ir_function_detect_recursion.cpp
index 5df3ac5..280c473 100644
--- a/src/glsl/ir_function_detect_recursion.cpp
+++ b/src/glsl/ir_function_detect_recursion.cpp
@@ -319,7 +319,6 @@ emit_errors_linked(const void *key, void *data, void 
*closure)
 
linker_error(prog, function `%s' has static recursion.\n, proto);
ralloc_free(proto);
-   prog-LinkStatus = false;
 }
 
 
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 4af1c82..f0fc1b9 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -3108,7 +3108,6 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
for (i = 0; i  prog-NumShaders; i++) {
   if (!prog-Shaders[i]-CompileStatus) {
 linker_error(prog, linking with uncompiled shader);
-prog-LinkStatus = GL_FALSE;
   }
}
 

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Mesa (master): glsl: Use a consistent technique for tracking link success/ failure.

[Paul Berry]

Module: Mesa
Branch: master
Commit: b95d237fe6731055dad2ff3eaa59e4d6fc14bfff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b95d237fe6731055dad2ff3eaa59e4d6fc14bfff

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Jul 27 11:08:31 2013 -0700

glsl: Use a consistent technique for tracking link success/failure.

This patch changes link_shaders() so that it sets prog-LinkStatus to
true when it starts, and then relies on linker_error() to set it to
false if a link failure occurs.

Previously, link_shaders() would set prog-LinkStatus to true halfway
through its execution; as a result, linker functions that executed
during the first half of link_shaders() would have to do their own
success/failure tracking; if they didn't, then calling linker_error()
would add an error message to the log, but not cause the link to fail.
Since it wasn't always obvious from looking at a linker function
whether it was called before or after link_shaders() set
prog-LinkStatus to true, this carried a high risk of bugs.

Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/glsl/link_interface_blocks.cpp |   19 +++---
 src/glsl/link_varyings.cpp |   12 ++--
 src/glsl/link_varyings.h   |2 +-
 src/glsl/linker.cpp|  117 +---
 src/glsl/linker.h  |7 +-
 5 files changed, 75 insertions(+), 82 deletions(-)

diff --git a/src/glsl/link_interface_blocks.cpp 
b/src/glsl/link_interface_blocks.cpp
index 4f67291..ffb4453 100644
--- a/src/glsl/link_interface_blocks.cpp
+++ b/src/glsl/link_interface_blocks.cpp
@@ -31,7 +31,7 @@
 #include linker.h
 #include main/macros.h
 
-bool
+void
 validate_intrastage_interface_blocks(struct gl_shader_program *prog,
  const gl_shader **shader_list,
  unsigned num_shaders)
@@ -65,16 +65,15 @@ validate_intrastage_interface_blocks(struct 
gl_shader_program *prog,
  } else if (old_iface_type != iface_type) {
 linker_error(prog, definitions of interface block `%s' do not
   match\n, iface_type-name);
-return false;
+return;
  }
   }
}
-
-   return true;
 }
 
-bool
-validate_interstage_interface_blocks(const gl_shader *producer,
+void
+validate_interstage_interface_blocks(struct gl_shader_program *prog,
+ const gl_shader *producer,
  const gl_shader *consumer)
 {
glsl_symbol_table interfaces;
@@ -105,9 +104,9 @@ validate_interstage_interface_blocks(const gl_shader 
*producer,
   if (expected_type == NULL)
  continue;
 
-  if (var-interface_type != expected_type)
- return false;
+  if (var-interface_type != expected_type) {
+ linker_error(prog, interface block mismatch between shader 
stages\n);
+ return;
+  }
}
-
-   return true;
 }
diff --git a/src/glsl/link_varyings.cpp b/src/glsl/link_varyings.cpp
index 51cbdaa..2c7e451 100644
--- a/src/glsl/link_varyings.cpp
+++ b/src/glsl/link_varyings.cpp
@@ -43,7 +43,7 @@
 /**
  * Validate that outputs from one stage match inputs of another
  */
-bool
+void
 cross_validate_outputs_to_inputs(struct gl_shader_program *prog,
 gl_shader *producer, gl_shader *consumer)
 {
@@ -106,7 +106,7 @@ cross_validate_outputs_to_inputs(struct gl_shader_program 
*prog,
producer_stage, output-name,
output-type-name,
consumer_stage, input-type-name);
-  return false;
+  return;
}
 }
 
@@ -121,7 +121,7 @@ cross_validate_outputs_to_inputs(struct gl_shader_program 
*prog,
 (output-centroid) ? has : lacks,
 consumer_stage,
 (input-centroid) ? has : lacks);
-   return false;
+   return;
 }
 
 if (input-invariant != output-invariant) {
@@ -133,7 +133,7 @@ cross_validate_outputs_to_inputs(struct gl_shader_program 
*prog,
 (output-invariant) ? has : lacks,
 consumer_stage,
 (input-invariant) ? has : lacks);
-   return false;
+   return;
 }
 
 if (input-interpolation != output-interpolation) {
@@ -147,12 +147,10 @@ cross_validate_outputs_to_inputs(struct gl_shader_program 
*prog,
 output-interpolation_string(),
 consumer_stage,
 input-interpolation_string());
-   return false;
+   return;
 }
   }
}
-
-   return true;
 }
 
 
diff --git a/src/glsl/link_varyings.h b/src/glsl/link_varyings.h
index 7f7be35..cfc6e47 100644
--- a/src/glsl/link_varyings.h
+++ b/src/glsl/link_varyings.h
@@ -214,7 +214,7

Mesa (master): 36 new commits

[Paul Berry]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34c55b59251a9c6e9979c1c0094c5158ce3503cb
Author: Paul Berry stereotype...@gmail.com
Date:   Sun Jul 28 21:48:55 2013 -0700

main: Warn that geometry shader support is experimental.

Geometry shader support in the Mesa front end is still fairly
preliminary.  Many features are untested, and the following things are
known not to work:

- The gl_in interface block
- The gl_ClipDistance input
- Transform feedback of geometry shader outputs
- Constants that are new in GLSL 1.50 (e.g. gl_MaxGeometryInputComponents)

This isn't a problem, since no back-end drivers currently enable
geometry shaders.  However, to make sure no one gets the wrong
impression, emit a nasty warning to let the user know that geometry
shader support isn't complete.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cfefe6965d50d8b1b494396d7b3b16d87bb2060
Author: Paul Berry stereotype...@gmail.com
Date:   Tue Jul 30 21:13:48 2013 -0700

glsl: Implement rules for geometry shader input sizes.

Section 4.3.8.1 (Input Layout Qualifiers) of the GLSL 1.50 spec
contains some tricky rules for how the sizes of geometry shader input
arrays are related to the input layout specification.  In essence,
those rules boil down to the following:

- If an input array declaration does not specify a size, and it
  follows an input layout declaration, it is sized according to the
  input layout.

- If an input layout declaration follows an input array declaration
  that didn't specify a size, the input array declaration is given a
  size at the time the input layout declaration appears.

- All input layout declarations and input array sizes must ultimately
  match.  Inconsistencies are reported as soon as they are detected,
  at compile time if the inconsistency is within one compilation unit,
  otherwise at link time.

- At least one compilation unit must contain an input layout
  declaration.

(Note: the geom_array_resize_visitor class was contributed by Bryan
Cain bryanca...@gmail.com.)

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20ae8e0c9168d900246d5940e07cf668dba8f0ce
Author: Paul Berry stereotype...@gmail.com
Date:   Wed Jul 24 14:57:24 2013 -0700

glsl: Allow geometry shader input instance arrays to be unsized.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1f1d8522c4650f55fac3a57466c9788f80f82f6
Author: Paul Berry stereotype...@gmail.com
Date:   Mon Jul 22 11:44:24 2013 -0700

glsl: Permit non-ubo input interface arrays to use non-const indexing.

From the GLSL ES 3.00 spec:

All indexes used to index a uniform block array must be constant
integral expressions.

Similar text exists in GLSL specs since 1.50.

When we implemented this, the only type of interface block supported
by Mesa was uniform blocks, so we required all indexes used to index
any interface block to be constant integral expressions.

Now that we are adding interface block support for GLSL 1.50, we need
a more specific check.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6065a87bce0c3fb0d9694c381c5a31b63e1f0300
Author: Eric Anholt e...@anholt.net
Date:   Wed Jun 12 18:12:40 2013 -0700

glsl: Cross-validate GS layout qualifiers while intrastage linking.

This gets piglit's geometry-basic test running.

TODO: Still need to validate that the GS layout qualifiers don't get used
in places they shouldn't (like an interface block, or a particular shader
input or output)

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=010a6a8fd343537101e7ac5e8dfcf9b07fc841fb
Author: Eric Anholt e...@anholt.net
Date:   Wed Jun 12 17:21:44 2013 -0700

glsl: Export the compiler's GS layout qualifiers to the gl_shader.

Next step is to validate them at link time.

v2 (Paul Berry stereotype...@gmail.com): Don't attempt to export the
layout qualifiers in the event of a compile error, since some of them
are set up by ast_to_hir(), and ast_to_hir() isn't guaranteed to have
run in the event of a compile error.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

v3 (Paul Berry stereotype...@gmail.com): Use PRIM_UNKNOWN to
represent

Mesa (master): glsl: Enable ARB_fragment_coord_conventions functionality in GLSL 1.50.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 417dc8081ba123fb93c34a3b14cd174dbce702f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=417dc8081ba123fb93c34a3b14cd174dbce702f5

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Aug  6 12:17:17 2013 -0700

glsl: Enable ARB_fragment_coord_conventions functionality in GLSL 1.50.

GLSL 1.50 incorporates the functionality of the
ARB_fragment_coord_conventions extension, so we need to make this
functionality available even if the extension isn't enabled.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

---

 src/glsl/ast_to_hir.cpp |3 ++-
 src/glsl/glsl_parser.yy |3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 482ab3c..bfdf8e3 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2332,7 +2332,8 @@ get_variable_being_redeclared(ir_variable *var, 
ast_declaration *decl,
   earlier-type = var-type;
   delete var;
   var = NULL;
-   } else if (state-ARB_fragment_coord_conventions_enable
+   } else if ((state-ARB_fragment_coord_conventions_enable ||
+   state-is_version(150, 0))
   strcmp(var-name, gl_FragCoord) == 0
   earlier-type == var-type
   earlier-mode == var-mode) {
diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index a847d2a..e3a57ea 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -1158,7 +1158,8 @@ layout_qualifier_id:
   memset( $$, 0, sizeof($$));
 
   /* Layout qualifiers for ARB_fragment_coord_conventions. */
-  if (!$$.flags.i  state-ARB_fragment_coord_conventions_enable) {
+  if (!$$.flags.i  (state-ARB_fragment_coord_conventions_enable ||
+  state-is_version(150, 0))) {
  if (strcmp($1, origin_upper_left) == 0) {
 $$.flags.q.origin_upper_left = 1;
  } else if (strcmp($1, pixel_center_integer) == 0) {

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Mesa (master): main: Fix deprecation of glLineWidth()

[Paul Berry]

Module: Mesa
Branch: master
Commit: 13fedf2883c7a1d7ff911b75eb88df00ba22eea7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13fedf2883c7a1d7ff911b75eb88df00ba22eea7

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Aug  5 15:46:43 2013 -0700

main: Fix deprecation of glLineWidth()

From section E.1 (Profiles and Deprecated Features of OpenGL 3.0)
of the OpenGL 3.0 spec:

LineWidth is not deprecated, but values greater than 1.0
will generate an INVALID VALUE error

From context it is clear that values greater than 1.0 should only
generate an INVALID VALUE error in a forward-compatible context.

The code was correctly quoting this spec text, but it was disallowing
all line widths in forward-compatible contexts, instead of just widths
greater than 1.0.

This patch introduces the correct check, so that setting a line width
of 1.0 or less is permitted.

Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/mesa/main/lines.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/mesa/main/lines.c b/src/mesa/main/lines.c
index 0df9d66..3c08ed2 100644
--- a/src/mesa/main/lines.c
+++ b/src/mesa/main/lines.c
@@ -62,7 +62,8 @@ _mesa_LineWidth( GLfloat width )
 */
if (ctx-API == API_OPENGL_CORE
 ((ctx-Const.ContextFlags  GL_CONTEXT_FLAG_FORWARD_COMPATIBLE_BIT)
-   != 0)) {
+   != 0)
+width  1.0) {
   _mesa_error( ctx, GL_INVALID_VALUE, glLineWidth );
   return;
}

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Mesa (master): i965/gen7+: Fix build error introduced by renaming upload_3dstate_so_decl_list.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 3b837e637efcb64bdd1db1f1281b0e321524788d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b837e637efcb64bdd1db1f1281b0e321524788d

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Aug 13 19:29:59 2013 -0700

i965/gen7+: Fix build error introduced by renaming upload_3dstate_so_decl_list.

Commit 9f9ccf707c54156b4559a4b1206022c2ca2d45cd renamed
upload_3dstate_so_decl_list to gen7_upload_3dstate_so_decl_list but
forgot to update the caller.

---

 src/mesa/drivers/dri/i965/gen7_sol_state.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_sol_state.c 
b/src/mesa/drivers/dri/i965/gen7_sol_state.c
index 185e422..fc69bfc 100644
--- a/src/mesa/drivers/dri/i965/gen7_sol_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sol_state.c
@@ -227,7 +227,7 @@ upload_sol_state(struct brw_context *brw)
if (active) {
   upload_3dstate_so_buffers(brw);
   /* BRW_NEW_VUE_MAP_GEOM_OUT */
-  upload_3dstate_so_decl_list(brw, brw-vue_map_geom_out);
+  gen7_upload_3dstate_so_decl_list(brw, brw-vue_map_geom_out);
}
 
/* Finally, set up the SOL stage.  This command must always follow updates 
to

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Mesa (master): glsl/ast: Fix assertion failure when GS input declared as non-array.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 91c8fea924c05801a1e05edcee00e53ea73e48b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91c8fea924c05801a1e05edcee00e53ea73e48b8

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Aug 12 06:39:23 2013 -0700

glsl/ast: Fix assertion failure when GS input declared as non-array.

Previously, if a geometry shader input was declared as a non-array, we
would flag the proper compiler error, but then before we got a chance
to report it to the client, handle_geometry_shader_input_decl() would
assertion fail.

With this patch, handle_geometry_shader_input_decl() ignores
non-arrays.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/ast_to_hir.cpp |   16 
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 3610014..8e1e6e5 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2546,9 +2546,8 @@ process_initializer(ir_variable *var, ast_declaration 
*decl,
 
 
 /**
- * Do additional processing necessary for geometry shader input array
- * declarations (this covers both interface blocks arrays and input variable
- * arrays).
+ * Do additional processing necessary for geometry shader input declarations
+ * (this covers both interface blocks arrays and bare input variables).
  */
 static void
 handle_geometry_shader_input_decl(struct _mesa_glsl_parse_state *state,
@@ -2559,7 +2558,16 @@ handle_geometry_shader_input_decl(struct 
_mesa_glsl_parse_state *state,
   num_vertices = vertices_per_prim(state-gs_input_prim_type);
}
 
-   assert(var-type-is_array());
+   /* Geometry shader input variables must be arrays.  Caller should have
+* reported an error for this.
+*/
+   if (!var-type-is_array()) {
+  assert(state-error);
+
+  /* To avoid cascading failures, short circuit the checks below. */
+  return;
+   }
+
if (var-type-length == 0) {
   /* Section 4.3.8.1 (Input Layout Qualifiers) of the GLSL 1.50 spec says:
*

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Mesa (master): glsl/ast: Don't perform GS input array checks on non-inputs.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 825f9ff5d3a0c4d6da20e14c34e3220be624ef8e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=825f9ff5d3a0c4d6da20e14c34e3220be624ef8e

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Aug 12 06:39:23 2013 -0700

glsl/ast: Don't perform GS input array checks on non-inputs.

Previously, we were accidentally calling
handle_geometry_shader_input_decl() on non-input interface block
declarations, resulting in bogus error checking.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/ast_to_hir.cpp |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 8e1e6e5..1bfa887 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4600,7 +4600,7 @@ ast_interface_block::hir(exec_list *instructions,
   }
 
   var-interface_type = block_type;
-  if (state-target == geometry_shader)
+  if (state-target == geometry_shader  var_mode == ir_var_shader_in)
  handle_geometry_shader_input_decl(state, loc, var);
   state-symbols-add_variable(var);
   instructions-push_tail(var);

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Mesa (master): glsl/ast: Check that geometry shader interface block inputs are arrays.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 336351e971d6232bbed11d9812ebf05341b6aa36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=336351e971d6232bbed11d9812ebf05341b6aa36

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Aug 12 06:39:23 2013 -0700

glsl/ast: Check that geometry shader interface block inputs are arrays.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/ast_to_hir.cpp |   13 +
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 49804b7..3610014 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -4528,6 +4528,19 @@ ast_interface_block::hir(exec_list *instructions,
 */
assert(declared_variables.is_empty());
 
+   /* From section 4.3.4 (Inputs) of the GLSL 1.50 spec:
+*
+* Geometry shader input variables get the per-vertex values written
+* out by vertex shader output variables of the same names. Since a
+* geometry shader operates on a set of vertices, each input varying
+* variable (or input block, see interface blocks below) needs to be
+* declared as an array.
+*/
+   if (state-target == geometry_shader  !this-is_array 
+   var_mode == ir_var_shader_in) {
+  _mesa_glsl_error(loc, state, geometry shader inputs must be arrays);
+   }
+
/* Page 39 (page 45 of the PDF) of section 4.3.7 in the GLSL ES 3.00 spec
 * says:
 *

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Mesa (master): glsl: Fix incorrect pattern matching in ir_set_program_inouts

[Paul Berry]

Module: Mesa
Branch: master
Commit: 98d2498404ba69a3efc1c765b1a1885d151181ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98d2498404ba69a3efc1c765b1a1885d151181ed

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug  9 07:58:43 2013 -0700

glsl: Fix incorrect pattern matching in ir_set_program_inouts

In commit 8fc41df (glsl: Modify ir_set_program_inouts to handle
geometry shaders), when attempting to pattern match the foo part of
expressions such as:

   foo[i][j]
   foo[i]

I incorrectly called as_dereference_variable() on the subexpression
foo[i] instead of foo.  As a result, the pattern never matched, so
ir_set_program_inouts would fall back on marking the entire variable
as used, rather than just the portion indexed by the array.

This didn't result in incorrect behaviour, but it could have resulted
in inefficiency by causing the back-end to allocate resources for
unused parts of an input or output array.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/ir_set_program_inouts.cpp |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/glsl/ir_set_program_inouts.cpp 
b/src/glsl/ir_set_program_inouts.cpp
index c6abc82..6196d6a 100644
--- a/src/glsl/ir_set_program_inouts.cpp
+++ b/src/glsl/ir_set_program_inouts.cpp
@@ -235,7 +235,7 @@ 
ir_set_program_inouts_visitor::visit_enter(ir_dereference_array *ir)
* inner_array = foo[i]
*/
   if (ir_dereference_variable * const deref_var =
-  inner_array-as_dereference_variable()) {
+  inner_array-array-as_dereference_variable()) {
  if (this-shader_type == GL_GEOMETRY_SHADER 
  deref_var-var-mode == ir_var_shader_in) {
 /* foo is a geometry shader input, so i is the vertex, and j the
@@ -253,7 +253,7 @@ 
ir_set_program_inouts_visitor::visit_enter(ir_dereference_array *ir)
  }
   }
} else if (ir_dereference_variable * const deref_var =
-  ir-as_dereference_variable()) {
+  ir-array-as_dereference_variable()) {
   /* ir = foo[i], where foo is a variable. */
   if (this-shader_type == GL_GEOMETRY_SHADER 
   deref_var-var-mode == ir_var_shader_in) {

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Mesa (master): i965: STATIC_ASSERT that there aren' t too many BRW_NEW_* flags.

[Paul Berry]

Module: Mesa
Branch: master
Commit: c6b6c936434b98b0262fd0856b00f13f43edc6ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6b6c936434b98b0262fd0856b00f13f43edc6ba

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 18 09:19:35 2013 -0700

i965: STATIC_ASSERT that there aren't too many BRW_NEW_* flags.

We are getting close to the maximum number of BRW_NEW_* bits that can
be stored in brw-state.dirty.brw without overflowing 32 bits, and
geometry shaders are going to add more.  Add a STATIC_ASSERT so that
we will be alerted when we need to switch to 64 bits.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.c |5 +
 src/mesa/drivers/dri/i965/brw_context.h |1 +
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 11d438b..44a35d1 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -448,6 +448,11 @@ brwCreateContext(int api,
brw-state.dirty.mesa = ~0;
brw-state.dirty.brw = ~0;
 
+   /* Make sure that brw-state.dirty.brw has enough bits to hold all possible
+* dirty flags.
+*/
+   STATIC_ASSERT(BRW_NUM_STATE_BITS = 8 * sizeof(brw-state.dirty.brw));
+
brw-emit_state_always = 0;
 
brw-batch.need_workaround_flush = true;
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 4067645..419cf17 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -155,6 +155,7 @@ enum brw_state_id {
BRW_STATE_UNIFORM_BUFFER,
BRW_STATE_META_IN_PROGRESS,
BRW_STATE_INTERPOLATION_MAP,
+   BRW_NUM_STATE_BITS
 };
 
 #define BRW_NEW_URB_FENCE   (1  BRW_STATE_URB_FENCE)

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Mesa (master): 24 new commits

[Paul Berry]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=60ddb96f7e0ea8dfb277cd1f249c7912c07c46b1
Author: Paul Berry stereotype...@gmail.com
Date:   Fri Mar 22 12:34:19 2013 -0700

i965/gs: Add a data structure for tracking VS output VUE map.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06918f84c2d1092ac327d836ce9f136f41736e6f
Author: Paul Berry stereotype...@gmail.com
Date:   Tue Jun 11 14:23:12 2013 -0700

i965/vec4: Make a function for setting up vec4 program key clip info.

This functionality will need to be reused by geometry shaders.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b5d10bcd353bf5bef1cd12f3a84625e56af3bb0
Author: Paul Berry stereotype...@gmail.com
Date:   Wed Mar 27 12:39:37 2013 -0700

i965: Make prim_to_hw_prim accessible outside brw_draw.c.

We will need access to this array in order to configure the geometry
shader.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16512ba70d5a9b4645508030acf1572ee7c660a3
Author: Paul Berry stereotype...@gmail.com
Date:   Tue Feb 19 07:31:16 2013 -0800

i965/gs: add GS visitors.

This patch introduces the vec4_gs_visitor class, which translates
geometry shaders from GLSL IR to back-end opcodes.

This class is derived from vec4_visitor (which is also the base class
for vec4_vs_visitor), so as a result most of the back end code is
shared.  The only parts that differ are:

- Geometry shaders use a different input payload organization, since
  the inputs need to match up with the outputs of the previous
  pipeline stage (vec4_gs_visitor::setup_payload() and
  vec4_gs_visitor::setup_varying_inputs()).

- Geometry shader input array dereferences need a special stride
  computation, since all geometry shader inputs are interleaved into
  one giant array (vec4_gs_visitor::compute_array_stride()).

- There are no geometry shader system values
  (vec4_gs_visitor::make_reg_for_system_value()).

- At the beginning of a geometry shader, extra data in R0 needs to be
  zeroed out, and a vertex counter needs to be initialized
  (vec4_gs_visitor::emit_prolog()).

- When EmitVertex() appears in the shader, the current contents of
  output variables need to be emitted to the URB, and the vertex
  counter needs to be incremented
  (vec4_gs_visitor::visit(ir_emit_vertex *)).

- When generating a URB_WRITE message to output vertex data, the
  current state of the vertex counter needs to be used to store a
  write offset in the message header
  (vec4_gs_visitor::emit_urb_write_header()).

- The URB_WRITE message that outputs vertex data needs to be sent
  using GS_OPCODE_URB_WRITE, since VS_OPCODE_URB_WRITE would overwrite
  the offsets in the message header
  (vec4_gs_visitor::emit_urb_write_opcode()).

- At the end of a geometry shader, the final vertex count needs to be
  delivered using a URB WRITE message
  (vec4_gs_visitor::emit_thread_end()).

- EndPrimitive() functionality is not implemented yet
  (vec4_gs_visitor::visit(ir_end_primitive *)).

- There is no support for assembly shaders
  (vec4_gs_visitor::emit_program_code()).

v2: Make num_input_vertices const.  Refer to registers as rN rather
than gN, for consistency with the PRM.  Fix misspelling.  Improve
comment in the ir_emit_vertex visitor explaining why we emit vertices
inside a conditional.  Enclose the conditional code in the
ir_emit_vertex visitor between curly braces.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35bdd552d5beb31e9b8319986c8f78d762c1228c
Author: Paul Berry stereotype...@gmail.com
Date:   Tue Feb 19 07:31:16 2013 -0800

i965/gs: Add GS_OPCODE_SET_DWORD_2_IMMED.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7417eddea9969cf09f36b05f218a59b22c076f0c
Author: Paul Berry stereotype...@gmail.com
Date:   Sat Mar 23 08:18:43 2013 -0700

i965/gs: Add GS_OPCODE_SET_VERTEX_COUNT.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn

Mesa (master): i965: Don' t try to fall back when creating unrecognized program targets.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 4bf91ca791844c16fda48f54386f1b30f6acefca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf91ca791844c16fda48f54386f1b30f6acefca

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug 23 11:43:26 2013 -0700

i965: Don't try to fall back when creating unrecognized program targets.

If brwNewProgram is asked to create a program for an unrecognized
target, don't bother falling back on _mesa_new_program().  That just
hides bugs.

Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com

v2: Use assert() rather than _mesa_problem().

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_program.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index c40d506..9a517be 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -114,7 +114,8 @@ static struct gl_program *brwNewProgram( struct gl_context 
*ctx,
}
 
default:
-  return _mesa_new_program(ctx, target, id);
+  assert(!Unsupported target in brwNewProgram());
+  return NULL;
}
 }
 

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Mesa (master): i965: Remove redundant (and uninitialized) field vec4_generator::ctx.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 612226c43b072eb45dc3ed21484054824e1c863c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=612226c43b072eb45dc3ed21484054824e1c863c

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Aug 22 17:15:04 2013 -0700

i965: Remove redundant (and uninitialized) field vec4_generator::ctx.

We never noticed that this field was uninitialized because it is only
used in an error path that reports internal Mesa errors.

But it's silly to have it around anyway because brw-ctx is
equivalent.

Should fix Coverity defect CID 1063351: Uninitialized pointer field
(UNINIT_CTOR) /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp: 148

Reviewed-by: Ian Romanick ian.d.roman...@intel.com

---

 src/mesa/drivers/dri/i965/brw_vec4.h|1 -
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |4 ++--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 5d8f0bf..a39dc50 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -659,7 +659,6 @@ private:
void mark_surface_used(unsigned surf_index);
 
struct brw_context *brw;
-   struct gl_context *ctx;
 
struct brw_compile *p;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 8d3696c..1f00260 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -1014,10 +1014,10 @@ 
vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
 
default:
   if (inst-opcode  (int) ARRAY_SIZE(opcode_descs)) {
- _mesa_problem(ctx, Unsupported opcode in `%s' in VS\n,
+ _mesa_problem(brw-ctx, Unsupported opcode in `%s' in VS\n,
opcode_descs[inst-opcode].name);
   } else {
- _mesa_problem(ctx, Unsupported opcode %d in VS, inst-opcode);
+ _mesa_problem(brw-ctx, Unsupported opcode %d in VS, inst-opcode);
   }
   abort();
}

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Mesa (master): i965: Allow C++ type safety in the use of enum brw_urb_write_flags.

[Paul Berry]

Module: Mesa
Branch: master
Commit: cfe39ea14edc8db13c549b853b214e676f8276f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfe39ea14edc8db13c549b853b214e676f8276f1

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug 23 13:19:19 2013 -0700

i965: Allow C++ type safety in the use of enum brw_urb_write_flags.

(From a suggestion by Francisco Jerez)

If an enum represents a bitfield of flags, e.g.:

enum E {
  A = 1,
  B = 2,
  C = 4,
  D = 8,
};

then C++ normally prohibits statements like this:

enum E x = A | B;

because A and B are implicitly converted to ints before OR-ing them,
and an int can't be stored in an enum without a type cast.  C, on the
other hand, allows an int to be implicitly converted to an enum
without casting.

In the past we've dealt with this situation by storing flag bitfields
as ints.  This avoids ugly casting at the expense of some type safety
that C++ would normally have offered (e.g. we get no warning if we
accidentally use the wrong enum type).

However, we can get the best of both worlds if we override the |
operator.  The ugly casting is confined to the operator overload, and
we still get the benefit of C++ making sure we don't use the wrong
enum type.

v2: Remove unnecessary comment and unnecessary use of enum keyword.
Use static_cast.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Reviewed-by: Francisco Jerez curroje...@riseup.net

---

 src/mesa/drivers/dri/i965/brw_clip.h   |2 +-
 src/mesa/drivers/dri/i965/brw_clip_util.c  |2 +-
 src/mesa/drivers/dri/i965/brw_eu.h |   16 +++-
 src/mesa/drivers/dri/i965/brw_eu_emit.c|4 ++--
 src/mesa/drivers/dri/i965/brw_sf_emit.c|   12 
 src/mesa/drivers/dri/i965/brw_vec4.h   |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |3 ++-
 7 files changed, 30 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clip.h 
b/src/mesa/drivers/dri/i965/brw_clip.h
index 5af0ad3..41f5c75 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -173,7 +173,7 @@ void brw_clip_init_planes( struct brw_clip_compile *c );
 
 void brw_clip_emit_vue(struct brw_clip_compile *c, 
   struct brw_indirect vert,
-   unsigned flags,
+   enum brw_urb_write_flags flags,
   GLuint header);
 
 void brw_clip_kill_thread(struct brw_clip_compile *c);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c 
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index d5c50d7..24d053e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -313,7 +313,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
 
 void brw_clip_emit_vue(struct brw_clip_compile *c, 
   struct brw_indirect vert,
-   unsigned flags,
+   enum brw_urb_write_flags flags,
   GLuint header)
 {
struct brw_compile *p = c-func;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 9053ea2..387450b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -229,6 +229,8 @@ void brw_set_dp_write_message(struct brw_compile *p,
  GLuint send_commit_msg);
 
 enum brw_urb_write_flags {
+   BRW_URB_WRITE_NO_FLAGS = 0,
+
/**
 * Causes a new URB entry to be allocated, and its address stored in the
 * destination register (gen  7).
@@ -271,11 +273,23 @@ enum brw_urb_write_flags {
   BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
 };
 
+#ifdef __cplusplus
+/**
+ * Allow brw_urb_write_flags enums to be ORed together.
+ */
+inline brw_urb_write_flags
+operator|(brw_urb_write_flags x, brw_urb_write_flags y)
+{
+   return static_castbrw_urb_write_flags(static_castint(x) |
+   static_castint(y));
+}
+#endif
+
 void brw_urb_WRITE(struct brw_compile *p,
   struct brw_reg dest,
   GLuint msg_reg_nr,
   struct brw_reg src0,
-   unsigned flags,
+   enum brw_urb_write_flags flags,
   GLuint msg_length,
   GLuint response_length,
   GLuint offset,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index b55b57e..ecf8597 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -515,7 +515,7 @@ static void brw_set_ff_sync_message(struct brw_compile *p,
 
 static void brw_set_urb_message( struct brw_compile *p,
 struct brw_instruction *insn,
- unsigned flags,
+ enum brw_urb_write_flags flags,
 GLuint msg_length,
 GLuint

Mesa (master): mesa/main: Check for 0 size draws after validation.

[Paul Berry]

Module: Mesa
Branch: master
Commit: cd18269705c948f5141478a48cf82a1fddd06b83
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd18269705c948f5141478a48cf82a1fddd06b83

Author: Fabian Bieler fabianbie...@fastmail.fm
Date:   Sat May 25 13:33:42 2013 +0200

mesa/main: Check for 0 size draws after validation.

When validating draw parameters move check for 0 draw count last
(drawing with count 0 is not an error), so that other parameters (e.g.: the
primitive type) are validated and the correct errors (if applicable) are
generated.

From the OpenGL 3.3 spec page 33 (page 48 of the PDF):
[Regarding DrawArraysOneInstance, in terms of which other draw operations
are defined:]
If count is negative, an INVALID_VALUE error is generated.

This patch also changes the bahavior of MultiDrawElements to perform the draw
operation if some primitive's index counts are zero.

Signed-off-by: Fabian Bieler fabianbie...@fastmail.fm
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Paul Berry stereotype...@gmail.com

---

 src/mesa/main/api_validate.c  |   51 -
 src/mesa/vbo/vbo_exec_array.c |   12 +
 2 files changed, 42 insertions(+), 21 deletions(-)

diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index 243bb89..0029921 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -402,9 +402,8 @@ _mesa_validate_DrawElements(struct gl_context *ctx,
   return GL_FALSE;
}
 
-   if (count = 0) {
-  if (count  0)
-_mesa_error(ctx, GL_INVALID_VALUE, glDrawElements(count) );
+   if (count  0) {
+  _mesa_error(ctx, GL_INVALID_VALUE, glDrawElements(count) );
   return GL_FALSE;
}
 
@@ -436,6 +435,9 @@ _mesa_validate_DrawElements(struct gl_context *ctx,
if (!check_index_bounds(ctx, count, type, indices, basevertex))
   return GL_FALSE;
 
+   if (count == 0)
+  return GL_FALSE;
+
return GL_TRUE;
 }
 
@@ -456,10 +458,9 @@ _mesa_validate_MultiDrawElements(struct gl_context *ctx,
FLUSH_CURRENT(ctx, 0);
 
for (i = 0; i  primcount; i++) {
-  if (count[i] = 0) {
- if (count[i]  0)
-_mesa_error(ctx, GL_INVALID_VALUE,
-glMultiDrawElements(count) );
+  if (count[i]  0) {
+ _mesa_error(ctx, GL_INVALID_VALUE,
+ glMultiDrawElements(count) );
  return GL_FALSE;
   }
}
@@ -531,9 +532,8 @@ _mesa_validate_DrawRangeElements(struct gl_context *ctx, 
GLenum mode,
   return GL_FALSE;
}
 
-   if (count = 0) {
-  if (count  0)
-_mesa_error(ctx, GL_INVALID_VALUE, glDrawRangeElements(count) );
+   if (count  0) {
+  _mesa_error(ctx, GL_INVALID_VALUE, glDrawRangeElements(count) );
   return GL_FALSE;
}
 
@@ -570,6 +570,9 @@ _mesa_validate_DrawRangeElements(struct gl_context *ctx, 
GLenum mode,
if (!check_index_bounds(ctx, count, type, indices, basevertex))
   return GL_FALSE;
 
+   if (count == 0)
+  return GL_FALSE;
+
return GL_TRUE;
 }
 
@@ -587,9 +590,8 @@ _mesa_validate_DrawArrays(struct gl_context *ctx,
   = ctx-TransformFeedback.CurrentObject;
FLUSH_CURRENT(ctx, 0);
 
-   if (count = 0) {
-  if (count  0)
- _mesa_error(ctx, GL_INVALID_VALUE, glDrawArrays(count) );
+   if (count  0) {
+  _mesa_error(ctx, GL_INVALID_VALUE, glDrawArrays(count) );
   return GL_FALSE;
}
 
@@ -628,6 +630,9 @@ _mesa_validate_DrawArrays(struct gl_context *ctx,
   xfb_obj-GlesRemainingPrims -= prim_count;
}
 
+   if (count == 0)
+  return GL_FALSE;
+
return GL_TRUE;
 }
 
@@ -640,10 +645,9 @@ _mesa_validate_DrawArraysInstanced(struct gl_context *ctx, 
GLenum mode, GLint fi
   = ctx-TransformFeedback.CurrentObject;
FLUSH_CURRENT(ctx, 0);
 
-   if (count = 0) {
-  if (count  0)
- _mesa_error(ctx, GL_INVALID_VALUE,
- glDrawArraysInstanced(count=%d), count);
+   if (count  0) {
+  _mesa_error(ctx, GL_INVALID_VALUE,
+  glDrawArraysInstanced(count=%d), count);
   return GL_FALSE;
}
 
@@ -696,6 +700,9 @@ _mesa_validate_DrawArraysInstanced(struct gl_context *ctx, 
GLenum mode, GLint fi
   xfb_obj-GlesRemainingPrims -= prim_count;
}
 
+   if (count == 0)
+  return GL_FALSE;
+
return GL_TRUE;
 }
 
@@ -721,10 +728,9 @@ _mesa_validate_DrawElementsInstanced(struct gl_context 
*ctx,
   return GL_FALSE;
}
 
-   if (count = 0) {
-  if (count  0)
-_mesa_error(ctx, GL_INVALID_VALUE,
- glDrawElementsInstanced(count=%d), count);
+   if (count  0) {
+  _mesa_error(ctx, GL_INVALID_VALUE,
+  glDrawElementsInstanced(count=%d), count);
   return GL_FALSE;
}
 
@@ -761,6 +767,9 @@ _mesa_validate_DrawElementsInstanced(struct gl_context *ctx,
  return GL_FALSE;
}
 
+   if (count == 0)
+  return GL_FALSE;
+
if (!check_index_bounds(ctx, count, type, indices, basevertex))
   return GL_FALSE

Mesa (master): i965: Rename user-defined gs structs from vec4_gs to gs.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 56a2e57bdb98a7fb4f1f404cbae1b9b396eee0de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56a2e57bdb98a7fb4f1f404cbae1b9b396eee0de

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug 23 21:49:50 2013 -0700

i965: Rename user-defined gs structs from vec4_gs to gs.

Now that the name gs is no longer used to refer to the legacy fixed
function geometry shaders, we can use it to refer to user-defined
geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h   |4 ++--
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h   |   12 ++--
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 381fe1f..4045c86 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -531,10 +531,10 @@ struct brw_vs_prog_data {
 };
 
 
-/* Note: brw_vec4_gs_prog_data_compare() must be updated when adding fields to
+/* Note: brw_gs_prog_data_compare() must be updated when adding fields to
  * this struct!
  */
-struct brw_vec4_gs_prog_data
+struct brw_gs_prog_data
 {
struct brw_vec4_prog_data base;
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 3549d5d..91a24ee 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -34,7 +34,7 @@ const unsigned MAX_GS_INPUT_VERTICES = 6;
 namespace brw {
 
 vec4_gs_visitor::vec4_gs_visitor(struct brw_context *brw,
- struct brw_vec4_gs_compile *c,
+ struct brw_gs_compile *c,
  struct gl_shader_program *prog,
  struct brw_shader *shader,
  void *mem_ctx)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
index e998666..87b58ab 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
@@ -33,7 +33,7 @@
 #include brw_vec4.h
 
 
-struct brw_vec4_gs_prog_key
+struct brw_gs_prog_key
 {
struct brw_vec4_prog_key base;
 
@@ -44,11 +44,11 @@ struct brw_vec4_gs_prog_key
 /**
  * Scratch data used when compiling a GLSL geometry shader.
  */
-struct brw_vec4_gs_compile
+struct brw_gs_compile
 {
struct brw_vec4_compile base;
-   struct brw_vec4_gs_prog_key key;
-   struct brw_vec4_gs_prog_data prog_data;
+   struct brw_gs_prog_key key;
+   struct brw_gs_prog_data prog_data;
 
struct brw_geometry_program *gp;
 };
@@ -61,7 +61,7 @@ class vec4_gs_visitor : public vec4_visitor
 {
 public:
vec4_gs_visitor(struct brw_context *brw,
-   struct brw_vec4_gs_compile *c,
+   struct brw_gs_compile *c,
struct gl_shader_program *prog,
struct brw_shader *shader,
void *mem_ctx);
@@ -82,7 +82,7 @@ private:
int setup_varying_inputs(int payload_reg, int *attribute_map);
 
src_reg vertex_count;
-   const struct brw_vec4_gs_compile * const c;
+   const struct brw_gs_compile * const c;
 };
 
 } /* namespace brw */

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965: rename legacy gs structs and functions to ff_gs.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 32e16e23377ecbba7783e33428ebb4575b874fe5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32e16e23377ecbba7783e33428ebb4575b874fe5

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug 23 20:14:00 2013 -0700

i965: rename legacy gs structs and functions to ff_gs.

ff is for fixed function.  This frees up the name gs to refer to
user-defined geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h  |   14 ++--
 src/mesa/drivers/dri/i965/brw_gs.c   |   42 
 src/mesa/drivers/dri/i965/brw_gs.h   |   19 ++--
 src/mesa/drivers/dri/i965/brw_gs_emit.c  |  150 +
 src/mesa/drivers/dri/i965/brw_gs_state.c |   17 ++--
 src/mesa/drivers/dri/i965/brw_misc_state.c   |   10 +-
 src/mesa/drivers/dri/i965/brw_state.h|2 +-
 src/mesa/drivers/dri/i965/brw_state_dump.c   |4 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c |8 +-
 src/mesa/drivers/dri/i965/gen6_gs_state.c|   10 +-
 src/mesa/drivers/dri/i965/gen6_sol.c |   12 +-
 src/mesa/drivers/dri/i965/gen6_urb.c |8 +-
 src/mesa/drivers/dri/i965/gen7_disable.c |2 +-
 src/mesa/drivers/dri/i965/gen7_urb.c |4 +-
 14 files changed, 156 insertions(+), 146 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index c456e61..381fe1f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -474,7 +474,7 @@ struct brw_clip_prog_data {
GLuint total_grf;
 };
 
-struct brw_gs_prog_data {
+struct brw_ff_gs_prog_data {
GLuint urb_read_length;
GLuint total_grf;
 
@@ -678,8 +678,8 @@ enum brw_cache_id {
BRW_SF_UNIT, /* scissor state on gen6 */
BRW_VS_UNIT,
BRW_VS_PROG,
-   BRW_GS_UNIT,
-   BRW_GS_PROG,
+   BRW_FF_GS_UNIT,
+   BRW_FF_GS_PROG,
BRW_CLIP_VP,
BRW_CLIP_UNIT,
BRW_CLIP_PROG,
@@ -768,8 +768,8 @@ enum shader_time_shader_type {
 #define CACHE_NEW_SF_UNIT(1BRW_SF_UNIT)
 #define CACHE_NEW_VS_UNIT(1BRW_VS_UNIT)
 #define CACHE_NEW_VS_PROG(1BRW_VS_PROG)
-#define CACHE_NEW_GS_UNIT(1BRW_GS_UNIT)
-#define CACHE_NEW_GS_PROG(1BRW_GS_PROG)
+#define CACHE_NEW_FF_GS_UNIT (1BRW_FF_GS_UNIT)
+#define CACHE_NEW_FF_GS_PROG (1BRW_FF_GS_PROG)
 #define CACHE_NEW_CLIP_VP(1BRW_CLIP_VP)
 #define CACHE_NEW_CLIP_UNIT  (1BRW_CLIP_UNIT)
 #define CACHE_NEW_CLIP_PROG  (1BRW_CLIP_PROG)
@@ -1162,7 +1162,7 @@ struct brw_context
} vs;
 
struct {
-  struct brw_gs_prog_data *prog_data;
+  struct brw_ff_gs_prog_data *prog_data;
 
   bool prog_active;
   /** Offset in the program cache to the CLIP program pre-gen6 */
@@ -1171,7 +1171,7 @@ struct brw_context
 
   uint32_t bind_bo_offset;
   uint32_t surf_offset[BRW_MAX_GS_SURFACES];
-   } gs;
+   } ff_gs;
 
struct {
   struct brw_clip_prog_data *prog_data;
diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index bd32db1..3882c06 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -45,10 +45,10 @@
 
 #include glsl/ralloc.h
 
-static void compile_gs_prog( struct brw_context *brw,
-struct brw_gs_prog_key *key )
+static void compile_ff_gs_prog(struct brw_context *brw,
+   struct brw_ff_gs_prog_key *key)
 {
-   struct brw_gs_compile c;
+   struct brw_ff_gs_compile c;
const GLuint *program;
void *mem_ctx;
GLuint program_size;
@@ -114,13 +114,13 @@ static void compile_gs_prog( struct brw_context *brw,
*/
   switch (key-primitive) {
   case _3DPRIM_QUADLIST:
-brw_gs_quads( c, key );
+brw_ff_gs_quads( c, key );
 break;
   case _3DPRIM_QUADSTRIP:
-brw_gs_quad_strip( c, key );
+brw_ff_gs_quad_strip( c, key );
 break;
   case _3DPRIM_LINELOOP:
-brw_gs_lines( c );
+brw_ff_gs_lines( c );
 break;
   default:
 ralloc_free(mem_ctx);
@@ -142,16 +142,16 @@ static void compile_gs_prog( struct brw_context *brw,
   printf(\n);
 }
 
-   brw_upload_cache(brw-cache, BRW_GS_PROG,
+   brw_upload_cache(brw-cache, BRW_FF_GS_PROG,
c.key, sizeof(c.key),
program, program_size,
c.prog_data, sizeof(c.prog_data),
-   brw-gs.prog_offset, brw-gs.prog_data);
+   brw-ff_gs.prog_offset, brw-ff_gs.prog_data);
ralloc_free(mem_ctx);
 }
 
-static void populate_key( struct brw_context *brw,
- struct brw_gs_prog_key *key )
+static void populate_key(struct brw_context *brw,
+ struct brw_ff_gs_prog_key *key)
 {
static const

Mesa (master): i965: Move vec4 register allocation data structures to brw- vec4.

[Paul Berry]

Module: Mesa
Branch: master
Commit: b3a4d5c78544ee957c4880cec7eb67f00ae04afd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3a4d5c78544ee957c4880cec7eb67f00ae04afd

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Aug 23 22:26:19 2013 -0700

i965: Move vec4 register allocation data structures to brw-vec4.

This will avoid confusion when we add geometry shaders, since these
data structures will be shared by vertex and geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h|   31 +++-
 .../drivers/dri/i965/brw_vec4_reg_allocate.cpp |   31 ++-
 2 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 4045c86..13daf1e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1120,20 +1120,11 @@ struct brw_context
 */
struct brw_vue_map vue_map_geom_out;
 
+   /**
+* Data structures used by all vec4 program compiles (not specific to any
+* particular program).
+*/
struct {
-  struct brw_vs_prog_data *prog_data;
-
-  drm_intel_bo *scratch_bo;
-  drm_intel_bo *const_bo;
-  /** Offset in the program cache to the VS program */
-  uint32_t prog_offset;
-  uint32_t state_offset;
-
-  uint32_t push_const_offset; /* Offset in the batchbuffer */
-  int push_const_size; /* in 256-bit register increments */
-
-  /** @{ register allocator */
-
   struct ra_regs *regs;
 
   /**
@@ -1147,7 +1138,19 @@ struct brw_context
* GRF for that object.
   */
   uint8_t *ra_reg_to_grf;
-  /** @} */
+   } vec4;
+
+   struct {
+  struct brw_vs_prog_data *prog_data;
+
+  drm_intel_bo *scratch_bo;
+  drm_intel_bo *const_bo;
+  /** Offset in the program cache to the VS program */
+  uint32_t prog_offset;
+  uint32_t state_offset;
+
+  uint32_t push_const_offset; /* Offset in the batchbuffer */
+  int push_const_size; /* in 256-bit register increments */
 
   uint32_t bind_bo_offset;
   uint32_t surf_offset[BRW_MAX_VS_SURFACES];
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 7984203..3777027 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -114,14 +114,14 @@ brw_vec4_alloc_reg_set(struct brw_context *brw)
   ra_reg_count += base_reg_count - (class_sizes[i] - 1);
}
 
-   ralloc_free(brw-vs.ra_reg_to_grf);
-   brw-vs.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
-   ralloc_free(brw-vs.regs);
-   brw-vs.regs = ra_alloc_reg_set(brw, ra_reg_count);
+   ralloc_free(brw-vec4.ra_reg_to_grf);
+   brw-vec4.ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
+   ralloc_free(brw-vec4.regs);
+   brw-vec4.regs = ra_alloc_reg_set(brw, ra_reg_count);
if (brw-gen = 6)
-  ra_set_allocate_round_robin(brw-vs.regs);
-   ralloc_free(brw-vs.classes);
-   brw-vs.classes = ralloc_array(brw, int, class_count + 1);
+  ra_set_allocate_round_robin(brw-vec4.regs);
+   ralloc_free(brw-vec4.classes);
+   brw-vec4.classes = ralloc_array(brw, int, class_count + 1);
 
/* Now, add the registers to their classes, and add the conflicts
 * between them and the base GRF registers (and also each other).
@@ -129,17 +129,17 @@ brw_vec4_alloc_reg_set(struct brw_context *brw)
int reg = 0;
for (int i = 0; i  class_count; i++) {
   int class_reg_count = base_reg_count - (class_sizes[i] - 1);
-  brw-vs.classes[i] = ra_alloc_reg_class(brw-vs.regs);
+  brw-vec4.classes[i] = ra_alloc_reg_class(brw-vec4.regs);
 
   for (int j = 0; j  class_reg_count; j++) {
-ra_class_add_reg(brw-vs.regs, brw-vs.classes[i], reg);
+ra_class_add_reg(brw-vec4.regs, brw-vec4.classes[i], reg);
 
-brw-vs.ra_reg_to_grf[reg] = j;
+brw-vec4.ra_reg_to_grf[reg] = j;
 
 for (int base_reg = j;
  base_reg  j + class_sizes[i];
  base_reg++) {
-   ra_add_transitive_reg_conflict(brw-vs.regs, base_reg, reg);
+   ra_add_transitive_reg_conflict(brw-vec4.regs, base_reg, reg);
 }
 
 reg++;
@@ -147,7 +147,7 @@ brw_vec4_alloc_reg_set(struct brw_context *brw)
}
assert(reg == ra_reg_count);
 
-   ra_set_finalize(brw-vs.regs, NULL);
+   ra_set_finalize(brw-vec4.regs, NULL);
 }
 
 void
@@ -191,13 +191,14 @@ vec4_visitor::reg_allocate()
int node_count = virtual_grf_count;
int first_payload_node = node_count;
node_count += payload_reg_count;
-   struct ra_graph *g = ra_alloc_interference_graph(brw-vs.regs, node_count);
+   struct ra_graph *g =
+  ra_alloc_interference_graph(brw-vec4.regs, node_count);
 
for (int i = 0; i  virtual_grf_count; i

Mesa (master): i965: Move data from brw- vs into a base class if gs will also need it.

[Paul Berry]

Module: Mesa
Branch: master
Commit: ec94e3c3d02857e26ba66e7e6a4b54044c820a0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec94e3c3d02857e26ba66e7e6a4b54044c820a0a

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 24 08:24:57 2013 -0700

i965: Move data from brw-vs into a base class if gs will also need it.

This paves the way for sharing the code that will set up the vertex
and geometry shader pipeline state.

v2: Rename the base class to brw_stage_state.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h  |   47 -
 src/mesa/drivers/dri/i965/brw_draw.c |3 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c   |6 +-
 src/mesa/drivers/dri/i965/brw_vs.c   |   12 +++---
 src/mesa/drivers/dri/i965/brw_vs_state.c |   25 ++-
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |   43 +++-
 src/mesa/drivers/dri/i965/brw_vtbl.c |2 +-
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c |8 ++-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4 +-
 src/mesa/drivers/dri/i965/gen6_sampler_state.c   |2 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c|   23 ++-
 src/mesa/drivers/dri/i965/gen7_vs_state.c|   18 +
 12 files changed, 108 insertions(+), 85 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index dcd4c9a..bd33fd2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -818,6 +818,32 @@ struct brw_query_object {
 
 
 /**
+ * Data shared between brw_context::vs and brw_context::gs
+ */
+struct brw_stage_state
+{
+   drm_intel_bo *scratch_bo;
+   drm_intel_bo *const_bo;
+   /** Offset in the program cache to the program */
+   uint32_t prog_offset;
+   uint32_t state_offset;
+
+   uint32_t push_const_offset; /* Offset in the batchbuffer */
+   int push_const_size; /* in 256-bit register increments */
+
+   uint32_t bind_bo_offset;
+   uint32_t surf_offset[BRW_MAX_VEC4_SURFACES];
+
+   /** SAMPLER_STATE count and table offset */
+   uint32_t sampler_count;
+   uint32_t sampler_offset;
+
+   /** Offsets in the batch to sampler default colors (texture border color) */
+   uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
+};
+
+
+/**
  * brw_context is derived from gl_context.
  */
 struct brw_context 
@@ -1141,27 +1167,8 @@ struct brw_context
} vec4;
 
struct {
+  struct brw_stage_state base;
   struct brw_vs_prog_data *prog_data;
-
-  drm_intel_bo *scratch_bo;
-  drm_intel_bo *const_bo;
-  /** Offset in the program cache to the VS program */
-  uint32_t prog_offset;
-  uint32_t state_offset;
-
-  uint32_t push_const_offset; /* Offset in the batchbuffer */
-  int push_const_size; /* in 256-bit register increments */
-
-  uint32_t bind_bo_offset;
-  uint32_t surf_offset[BRW_MAX_VEC4_SURFACES];
-
-  /** SAMPLER_STATE count and table offset */
-  uint32_t sampler_count;
-  uint32_t sampler_offset;
-
-  /** Offsets in the batch to sampler default colors (texture border color)
-   */
-  uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
} vs;
 
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index c7164ac..96ba817 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -376,7 +376,8 @@ static bool brw_try_draw_prims( struct gl_context *ctx,
 * index.
 */
brw-wm.sampler_count = 
_mesa_fls(ctx-FragmentProgram._Current-Base.SamplersUsed);
-   brw-vs.sampler_count = 
_mesa_fls(ctx-VertexProgram._Current-Base.SamplersUsed);
+   brw-vs.base.sampler_count =
+  _mesa_fls(ctx-VertexProgram._Current-Base.SamplersUsed);
 
/* We have to validate the textures *before* checking for fallbacks;
 * otherwise, the software fallback won't be able to rely on the
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3492ea9..16a41cc 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -77,7 +77,7 @@ static void upload_binding_table_pointers(struct brw_context 
*brw)
 {
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS  16 | (6 - 2));
-   OUT_BATCH(brw-vs.bind_bo_offset);
+   OUT_BATCH(brw-vs.base.bind_bo_offset);
OUT_BATCH(0); /* gs */
OUT_BATCH(0); /* clip */
OUT_BATCH(0); /* sf */
@@ -113,7 +113,7 @@ static void upload_gen6_binding_table_pointers(struct 
brw_context *brw)
 GEN6_BINDING_TABLE_MODIFY_GS |
 GEN6_BINDING_TABLE_MODIFY_PS |
 (4 - 2));
-   OUT_BATCH(brw-vs.bind_bo_offset); /* vs */
+   OUT_BATCH(brw-vs.base.bind_bo_offset); /* vs */
OUT_BATCH(brw-ff_gs.bind_bo_offset); /* gs */
OUT_BATCH(brw-wm.bind_bo_offset); /* wm/ps */
ADVANCE_BATCH();
@@ -150,7 +150,7

Mesa (master): i965/gs: Update defines related to GS surface organization.

[Paul Berry]

Module: Mesa
Branch: master
Commit: cdf03b69282d12f9d27daf2edb3abb351f5de7f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cdf03b69282d12f9d27daf2edb3abb351f5de7f6

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 09:28:08 2013 -0700

i965/gs: Update defines related to GS surface organization.

Defines that previously referred to VS now refer to VEC4, since they
will be shared by the user-programmable vertex shader and geometry
shader stages.

Defines that previously referred to the Gen6 geometry shader stage
(which is only used for transform feedback) are now renamed to
explicitly refer to Gen6, to avoid confusion with the Gen7
user-programmable geometry shader stage.

Based on work by Eric Anholt e...@anholt.net.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h  |   22 +++---
 src/mesa/drivers/dri/i965/brw_gs_emit.c  |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp  |   10 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   |4 ++--
 src/mesa/drivers/dri/i965/brw_vec4_vp.cpp|2 +-
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |8 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |4 ++--
 src/mesa/drivers/dri/i965/gen6_sol.c |6 +++---
 8 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 13daf1e..dcd4c9a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -615,10 +615,10 @@ struct brw_gs_prog_data
  *|  36 | UBO 11  |
  *+---+
  *
- * Our VS binding tables are programmed as follows:
+ * Our VS (and Gen7 GS) binding tables are programmed as follows:
  *
  *+-+-+
- *|   0 | VS Pull Constant Buffer |
+ *|   0 | Pull Constant Buffer|
  *+-+-+
  *|   1 | Texture 0   |
  *|   . | .   |
@@ -648,14 +648,14 @@ struct brw_gs_prog_data
 /** Maximum size of the binding table. */
 #define BRW_MAX_WM_SURFACES  (SURF_INDEX_WM_SHADER_TIME + 1)
 
-#define SURF_INDEX_VERT_CONST_BUFFER (0)
-#define SURF_INDEX_VS_TEXTURE(t) (SURF_INDEX_VERT_CONST_BUFFER + 1 + (t))
-#define SURF_INDEX_VS_UBO(u) (SURF_INDEX_VS_TEXTURE(BRW_MAX_TEX_UNIT) 
+ u)
-#define SURF_INDEX_VS_SHADER_TIME(SURF_INDEX_VS_UBO(12))
-#define BRW_MAX_VS_SURFACES  (SURF_INDEX_VS_SHADER_TIME + 1)
+#define SURF_INDEX_VEC4_CONST_BUFFER (0)
+#define SURF_INDEX_VEC4_TEXTURE(t)   (SURF_INDEX_VEC4_CONST_BUFFER + 1 + (t))
+#define SURF_INDEX_VEC4_UBO(u)   
(SURF_INDEX_VEC4_TEXTURE(BRW_MAX_TEX_UNIT) + u)
+#define SURF_INDEX_VEC4_SHADER_TIME  (SURF_INDEX_VEC4_UBO(12))
+#define BRW_MAX_VEC4_SURFACES(SURF_INDEX_VEC4_SHADER_TIME + 1)
 
-#define SURF_INDEX_SOL_BINDING(t)((t))
-#define BRW_MAX_GS_SURFACES  
SURF_INDEX_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
+#define SURF_INDEX_GEN6_SOL_BINDING(t) (t)
+#define BRW_MAX_GEN6_GS_SURFACES   
SURF_INDEX_GEN6_SOL_BINDING(BRW_MAX_SOL_BINDINGS)
 
 /**
  * Stride in bytes between shader_time entries.
@@ -1153,7 +1153,7 @@ struct brw_context
   int push_const_size; /* in 256-bit register increments */
 
   uint32_t bind_bo_offset;
-  uint32_t surf_offset[BRW_MAX_VS_SURFACES];
+  uint32_t surf_offset[BRW_MAX_VEC4_SURFACES];
 
   /** SAMPLER_STATE count and table offset */
   uint32_t sampler_count;
@@ -1173,7 +1173,7 @@ struct brw_context
   uint32_t state_offset;
 
   uint32_t bind_bo_offset;
-  uint32_t surf_offset[BRW_MAX_GS_SURFACES];
+  uint32_t surf_offset[BRW_MAX_GEN6_GS_SURFACES];
} ff_gs;
 
struct {
diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c 
b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index 7fff53e..2c94eb0 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -436,7 +436,7 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct 
brw_ff_gs_prog_key *key,
   final_write ? c-reg.temp : brw_null_reg(), /* dest 
*/
   1, /* msg_reg_nr */
   c-reg.header, /* src0 */
-  SURF_INDEX_SOL_BINDING(binding), /* 
binding_table_index */
+  SURF_INDEX_GEN6_SOL_BINDING(binding), /* 
binding_table_index */
   final_write); /* send_commit_msg */
  }
   }
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 1f00260..bf04bd9 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -155,7 +155,7 @@ vec4_generator::~vec4_generator()
 void
 vec4_generator::mark_surface_used(unsigned surf_index

Mesa (master): i965/gs: Create brw_context:: gs structure to track GS program state.

[Paul Berry]

Module: Mesa
Branch: master
Commit: a702f6325cefa7b82af9ea318551fe8e7ea3121d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a702f6325cefa7b82af9ea318551fe8e7ea3121d

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Mar 22 12:34:19 2013 -0700

i965/gs: Create brw_context::gs structure to track GS program state.

v2: Change name from vec4_gs to simply gs.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index bd33fd2..0171b5b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1172,6 +1172,11 @@ struct brw_context
} vs;
 
struct {
+  struct brw_stage_state base;
+  struct brw_gs_prog_data *prog_data;
+   } gs;
+
+   struct {
   struct brw_ff_gs_prog_data *prog_data;
 
   bool prog_active;

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Mesa (master): i965: Make CACHE_NEW_GS_PROG.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 53f6e79633e59331711f9fc422ce79865db62d42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53f6e79633e59331711f9fc422ce79865db62d42

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 24 09:14:38 2013 -0700

i965: Make CACHE_NEW_GS_PROG.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.h |2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 0171b5b..3f17f1d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -680,6 +680,7 @@ enum brw_cache_id {
BRW_VS_PROG,
BRW_FF_GS_UNIT,
BRW_FF_GS_PROG,
+   BRW_GS_PROG,
BRW_CLIP_VP,
BRW_CLIP_UNIT,
BRW_CLIP_PROG,
@@ -770,6 +771,7 @@ enum shader_time_shader_type {
 #define CACHE_NEW_VS_PROG(1BRW_VS_PROG)
 #define CACHE_NEW_FF_GS_UNIT (1BRW_FF_GS_UNIT)
 #define CACHE_NEW_FF_GS_PROG (1BRW_FF_GS_PROG)
+#define CACHE_NEW_GS_PROG(1BRW_GS_PROG)
 #define CACHE_NEW_CLIP_VP(1BRW_CLIP_VP)
 #define CACHE_NEW_CLIP_UNIT  (1BRW_CLIP_UNIT)
 #define CACHE_NEW_CLIP_PROG  (1BRW_CLIP_PROG)

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Mesa (master): i965/gs: Allocate URB space for use by GS.

[Paul Berry]

Module: Mesa
Branch: master
Commit: fffba41c6828b8f46a162185147d3e9b9cc479e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fffba41c6828b8f46a162185147d3e9b9cc479e4

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Mar 27 09:49:17 2013 -0700

i965/gs: Allocate URB space for use by GS.

Previously, we gave all of the URB space (other than the small amount
that is used for push constants) to the vertex shader.  However, when
a geometry shader is active, we need to divide it up between the
vertex and geometry shaders.

The size of the URB entries for the vertex and geometry shaders can
vary dramatically from one shader to the next.  So it doesn't make
sense to simply split the available space in two.  In particular:

- On Ivy Bridge GT1, this would not leave enough space for the worst
  case geometry shader, which requires 64k of URB space.

- Due to hardware-imposed limits on the maximum number of URB entries,
  sometimes a given shader stage will only be capable of using a small
  amount of URB space.  When this happens, it may make sense to
  allocate substantially less than half of the available space to that
  stage.

Our algorithm for dividing space between the two stages is to first
compute (a) the minimum amount of URB space that each stage needs in
order to function properly, and (b) the amount of additional URB space
that each stage wants (i.e. that it would be capable of making use
of).  If the total amount of space available is not enough to satisfy
needs + wants, then each stage's wants amount is scaled back by the
same factor in order to fit.

When only a vertex shader is active, this algorithm produces
equivalent results to the old algorithm (if the vertex shader stage
can make use of all the available URB space, we assign all the space
to it; if it can't, we let it use as much as it can).

In the future, when we need to support tessellation control and
tessellation evaluation pipeline stages, it should be straightforward
to expand this algorithm to cover them.

v2: Use unsigned rather than GLuint.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h  |6 +-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |   16 ++--
 src/mesa/drivers/dri/i965/gen7_urb.c |  156 +-
 3 files changed, 143 insertions(+), 35 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 3f17f1d..0bfe606 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1511,8 +1511,10 @@ void
 gen7_allocate_push_constants(struct brw_context *brw);
 
 void
-gen7_emit_urb_state(struct brw_context *brw, GLuint nr_vs_entries,
-GLuint vs_size, GLuint vs_start);
+gen7_emit_urb_state(struct brw_context *brw,
+unsigned nr_vs_entries, unsigned vs_size,
+unsigned vs_start, unsigned nr_gs_entries,
+unsigned gs_size, unsigned gs_start);
 
 
 
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a387836..6c798b1 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -51,14 +51,16 @@ static void
 gen7_blorp_emit_urb_config(struct brw_context *brw,
const brw_blorp_params *params)
 {
-   /* The minimum valid value is 32. See 3DSTATE_URB_VS,
-* Dword 1.15:0 VS Number of URB Entries.
+   /* The minimum valid number of VS entries is 32. See 3DSTATE_URB_VS, Dword
+* 1.15:0 VS Number of URB Entries.
 */
-   int num_vs_entries = 32;
-   int vs_size = 2;
-   int vs_start = 2; /* skip over push constants */
-
-   gen7_emit_urb_state(brw, num_vs_entries, vs_size, vs_start);
+   gen7_emit_urb_state(brw,
+   32 /* num_vs_entries */,
+   2 /* vs_size */,
+   2 /* vs_start */,
+   0 /* num_gs_entries */,
+   1 /* gs_size */,
+   2 /* gs_start */);
 }
 
 
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 927af37..ed5cda8 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -74,34 +74,137 @@ gen7_upload_urb(struct brw_context *brw)
 {
const int push_size_kB = brw-is_haswell  brw-gt == 3 ? 32 : 16;
 
-   /* Total space for entries is URB size - 16kB for push constants */
-   int handle_region_size = (brw-urb.size - push_size_kB) * 1024; /* bytes */
-
/* CACHE_NEW_VS_PROG */
unsigned vs_size = MAX2(brw-vs.prog_data-base.urb_entry_size, 1);
-
-   int nr_vs_entries = handle_region_size / (vs_size * 64);
-   if (nr_vs_entries  brw-urb.max_vs_entries)
-  nr_vs_entries = brw-urb.max_vs_entries;
-
-   /* According to volume 2a, nr_vs_entries must be a multiple of 8. */
-   brw-urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 8

Mesa (master): i965/gen7: Emit CS stall after 3DSTATE_PUSH_CONSTANT_ALLOC_PS.

[Paul Berry]

Module: Mesa
Branch: master
Commit: df62421382c39678ac014e88cee7c73c64d42107
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df62421382c39678ac014e88cee7c73c64d42107

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Aug 29 10:17:31 2013 -0700

i965/gen7: Emit CS stall after 3DSTATE_PUSH_CONSTANT_ALLOC_PS.

This is required by the internal hardware docs and the PRM.  Probably
the reason we were getting away with not doing it was because we only
emitted 3DSTATE_PUSH_CONSTANT_ALLOC_PS during startup.  However that's
going to change with the introduction of geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/gen7_urb.c |   30 ++
 1 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index ed5cda8..6346794 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -67,6 +67,36 @@ gen7_allocate_push_constants(struct brw_context *brw)
OUT_BATCH(_3DSTATE_PUSH_CONSTANT_ALLOC_PS  16 | (2 - 2));
OUT_BATCH(size | size  GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT);
ADVANCE_BATCH();
+
+   /* From p292 of the Ivy Bridge PRM (11.2.4 3DSTATE_PUSH_CONSTANT_ALLOC_PS):
+*
+* A PIPE_CONTOL command with the CS Stall bit set must be programmed
+* in the ring after this instruction.
+*
+* No such restriction exists for Haswell.
+*/
+   if (!brw-is_haswell) {
+  BEGIN_BATCH(4);
+  OUT_BATCH(_3DSTATE_PIPE_CONTROL | (4 - 2));
+  /* From p61 of the Ivy Bridge PRM (1.10.4 PIPE_CONTROL Command: DW1[20]
+   * CS Stall):
+   *
+   * One of the following must also be set:
+   * - Render Target Cache Flush Enable ([12] of DW1)
+   * - Depth Cache Flush Enable ([0] of DW1)
+   * - Stall at Pixel Scoreboard ([1] of DW1)
+   * - Depth Stall ([13] of DW1)
+   * - Post-Sync Operation ([13] of DW1)
+   *
+   * We choose to do a Post-Sync Operation (Write Immediate Data), since
+   * it seems like it will incur the least additional performance penalty.
+   */
+  OUT_BATCH(PIPE_CONTROL_CS_STALL | PIPE_CONTROL_WRITE_IMMEDIATE);
+  OUT_RELOC(brw-batch.workaround_bo,
+I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION, 0);
+  OUT_BATCH(0);
+  ADVANCE_BATCH();
+   }
 }
 
 static void

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Mesa (master): i965: Make sure constants re-sent after constant buffer reallocation.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 555f9cf46d2108d1f9cdb52c112e5568f2a2ee2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=555f9cf46d2108d1f9cdb52c112e5568f2a2ee2e

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 18 08:23:51 2013 -0700

i965: Make sure constants re-sent after constant buffer reallocation.

The hardware requires that after constant buffers for a stage are
allocated using a 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS}
command, and prior to execution of a 3DPRIMITIVE, the corresponding
stage's constant buffers must be reprogrammed using a
3DSTATE_CONSTANT_{VS,HS,DS,GS,PS} command.

Previously we didn't need to worry about this, because we only
programmed 3DSTATE_PUSH_CONSTANT_ALLOC_{VS,HS,DS,GS,PS} once on
startup (or, previous to that, whenever BRW_NEW_CONTEXT was flagged).
But now that we reallocate the constant buffers whenever geometry
shaders are switched on and off, we need to make sure the constant
buffers are reprogrammed.

We do this by adding a new bit, BRW_NEW_PUSH_CONSTANT_ALLOCATION, to
brw-state.dirty.brw.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |2 ++
 src/mesa/drivers/dri/i965/gen6_gs_state.c |2 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c |3 ++-
 src/mesa/drivers/dri/i965/gen6_wm_state.c |3 ++-
 src/mesa/drivers/dri/i965/gen7_urb.c  |   13 +
 src/mesa/drivers/dri/i965/gen7_vs_state.c |3 ++-
 src/mesa/drivers/dri/i965/gen7_wm_state.c |3 ++-
 7 files changed, 24 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index a14e2b5..974b76a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -158,6 +158,7 @@ enum brw_state_id {
BRW_STATE_UNIFORM_BUFFER,
BRW_STATE_META_IN_PROGRESS,
BRW_STATE_INTERPOLATION_MAP,
+   BRW_STATE_PUSH_CONSTANT_ALLOCATION,
BRW_NUM_STATE_BITS
 };
 
@@ -194,6 +195,7 @@ enum brw_state_id {
 #define BRW_NEW_UNIFORM_BUFFER  (1  BRW_STATE_UNIFORM_BUFFER)
 #define BRW_NEW_META_IN_PROGRESS(1  BRW_STATE_META_IN_PROGRESS)
 #define BRW_NEW_INTERPOLATION_MAP   (1  BRW_STATE_INTERPOLATION_MAP)
+#define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1  
BRW_STATE_PUSH_CONSTANT_ALLOCATION)
 
 struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/gen6_gs_state.c 
b/src/mesa/drivers/dri/i965/gen6_gs_state.c
index ac78286..9648fb7 100644
--- a/src/mesa/drivers/dri/i965/gen6_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_gs_state.c
@@ -81,7 +81,7 @@ upload_gs_state(struct brw_context *brw)
 const struct brw_tracked_state gen6_gs_state = {
.dirty = {
   .mesa  = _NEW_TRANSFORM,
-  .brw   = BRW_NEW_CONTEXT,
+  .brw   = BRW_NEW_CONTEXT | BRW_NEW_PUSH_CONSTANT_ALLOCATION,
   .cache = CACHE_NEW_FF_GS_PROG
},
.emit = upload_gs_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 0342a22..98c7aec 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -206,7 +206,8 @@ const struct brw_tracked_state gen6_vs_state = {
   .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,
   .brw   = (BRW_NEW_CONTEXT |
BRW_NEW_VERTEX_PROGRAM |
-   BRW_NEW_BATCH),
+   BRW_NEW_BATCH |
+BRW_NEW_PUSH_CONSTANT_ALLOCATION),
   .cache = CACHE_NEW_VS_PROG | CACHE_NEW_SAMPLER
},
.emit = upload_vs_state,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index e286785..6725805 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -229,7 +229,8 @@ const struct brw_tracked_state gen6_wm_state = {
_NEW_POLYGON |
 _NEW_MULTISAMPLE),
   .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
-   BRW_NEW_BATCH),
+   BRW_NEW_BATCH |
+BRW_NEW_PUSH_CONSTANT_ALLOCATION),
   .cache = (CACHE_NEW_SAMPLER |
CACHE_NEW_WM_PROG)
},
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 5a7ab47..6683117 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -81,6 +81,19 @@ gen7_allocate_push_constants(struct brw_context *brw)
 
gen7_emit_push_constant_state(brw, multiplier * vs_size,
  multiplier * gs_size, multiplier * fs_size);
+
+   /* From p115 of the Ivy Bridge PRM (3.2.1.4 3DSTATE_PUSH_CONSTANT_ALLOC_VS):
+*
+* Programming Restriction:
+*
+* The 3DSTATE_CONSTANT_VS must be reprogrammed prior to the next
+* 3DPRIMITIVE command after programming the
+* 3DSTATE_PUSH_CONSTANT_ALLOC_VS.
+*
+* Similar text exists for the other

Mesa (master): i965/gs: Allocate push constant space for use by GS.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 27eecefc670c8b9e75f8520df7c9c7846923bf20
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27eecefc670c8b9e75f8520df7c9c7846923bf20

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Mar 27 10:34:55 2013 -0700

i965/gs: Allocate push constant space for use by GS.

Previously, we would always use the same push constant allocation
regardless of what shader programs were being run: the available push
constant space was split into 2 equal size partitions, one for the
vertex shader, and one for the fragment shader.

Now that we are adding geometry shader support, we need to do
something smarter.  This patch adjusts things so that when a geometry
shader is in use, we split the available push constant space into 3
nearly-equal size partitions instead of 2.

Since the push constant allocation is now affected by GL state, it can
no longer be set up by brw_upload_initial_gpu_state(); instead it must
be set up by a state atom.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h  |3 +-
 src/mesa/drivers/dri/i965/brw_defines.h  |1 +
 src/mesa/drivers/dri/i965/brw_state.h|4 +-
 src/mesa/drivers/dri/i965/brw_state_upload.c |5 +--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp |6 ++
 src/mesa/drivers/dri/i965/gen7_urb.c |   71 +-
 6 files changed, 68 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 0bfe606..a14e2b5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1508,7 +1508,8 @@ gen6_get_sample_position(struct gl_context *ctx,
 
 /* gen7_urb.c */
 void
-gen7_allocate_push_constants(struct brw_context *brw);
+gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size,
+  unsigned gs_size, unsigned fs_size);
 
 void
 gen7_emit_urb_state(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 832ff55..8d9a824 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1284,6 +1284,7 @@ enum brw_message_target {
 # define GEN7_URB_STARTING_ADDRESS_SHIFT25
 
 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */
+#define _3DSTATE_PUSH_CONSTANT_ALLOC_GS 0x7915 /* GEN7+ */
 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS 0x7916 /* GEN7+ */
 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
 
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 85f82fe..4814639 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -112,6 +112,7 @@ extern const struct brw_tracked_state 
gen7_cc_viewport_state_pointer;
 extern const struct brw_tracked_state gen7_clip_state;
 extern const struct brw_tracked_state gen7_disable_stages;
 extern const struct brw_tracked_state gen7_ps_state;
+extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sbe_state;
 extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_sf_state;
@@ -220,9 +221,6 @@ uint32_t
 get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
   int fs_attr, bool two_side_color, uint32_t *max_source_attr);
 
-/* gen7_urb.c */
-void gen7_allocate_push_constants(struct brw_context *brw);
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index b883002..9638c69 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -188,6 +188,7 @@ static const struct brw_tracked_state *gen7_atoms[] =
gen7_cc_viewport_state_pointer, /* must do after brw_cc_vp */
gen7_sf_clip_viewport,
 
+   gen7_push_constant_space,
gen7_urb,
gen6_blend_state,  /* must do before cc unit */
gen6_color_calc_state, /* must do before cc unit */
@@ -251,10 +252,6 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
   return;
 
brw_upload_invariant_state(brw);
-
-   if (brw-gen = 7) {
-  gen7_allocate_push_constants(brw);
-   }
 }
 
 void brw_init_state( struct brw_context *brw )
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 6c798b1..9df3d92 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -51,6 +51,12 @@ static void
 gen7_blorp_emit_urb_config(struct brw_context *brw,
const brw_blorp_params *params)
 {
+   unsigned urb_size = (brw-is_haswell  brw-gt == 3) ? 32 : 16;
+   gen7_emit_push_constant_state(brw,
+ urb_size / 2 /* vs_size

Mesa (master): i965: generalize brw_vs_pull_constants in preparation for GS .

[Paul Berry]

Module: Mesa
Branch: master
Commit: 1b19f2c576a343aca946494cf3486395b03b3531
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b19f2c576a343aca946494cf3486395b03b3531

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 24 13:08:57 2013 -0700

i965: generalize brw_vs_pull_constants in preparation for GS.

v2: Use GLbitfield instead of GLbitfield64 in
brw_upload_vec4_pull_constants.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_state.h|8 +++
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |   69 +
 2 files changed, 51 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4814639..695a84c 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -221,6 +221,14 @@ uint32_t
 get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
   int fs_attr, bool two_side_color, uint32_t *max_source_attr);
 
+/* brw_vs_surface_state.c */
+void
+brw_upload_vec4_pull_constants(struct brw_context *brw,
+   GLbitfield brw_new_constbuf,
+   const struct gl_program *prog,
+   struct brw_stage_state *stage_state,
+   const struct brw_vec4_prog_data *prog_data);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index f1e1a4e..b55febe 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -35,56 +35,49 @@
 #include brw_context.h
 #include brw_state.h
 
-/* Creates a new VS constant buffer reflecting the current VS program's
- * constants, if needed by the VS program.
- *
- * Otherwise, constants go through the CURBEs using the brw_constant_buffer
- * state atom.
- */
-static void
-brw_upload_vs_pull_constants(struct brw_context *brw)
-{
-   struct brw_stage_state *stage_state = brw-vs.base;
 
-   /* BRW_NEW_VERTEX_PROGRAM */
-   struct brw_vertex_program *vp =
-  (struct brw_vertex_program *) brw-vertex_program;
+void
+brw_upload_vec4_pull_constants(struct brw_context *brw,
+   GLbitfield brw_new_constbuf,
+   const struct gl_program *prog,
+   struct brw_stage_state *stage_state,
+   const struct brw_vec4_prog_data *prog_data)
+{
int i;
 
/* Updates the ParamaterValues[i] pointers for all parameters of the
 * basic type of PROGRAM_STATE_VAR.
 */
-   _mesa_load_state_parameters(brw-ctx, vp-program.Base.Parameters);
+   _mesa_load_state_parameters(brw-ctx, prog-Parameters);
 
-   /* CACHE_NEW_VS_PROG */
-   if (!brw-vs.prog_data-base.nr_pull_params) {
+   if (!prog_data-nr_pull_params) {
   if (stage_state-const_bo) {
 drm_intel_bo_unreference(stage_state-const_bo);
 stage_state-const_bo = NULL;
 stage_state-surf_offset[SURF_INDEX_VEC4_CONST_BUFFER] = 0;
-brw-state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
+brw-state.dirty.brw |= brw_new_constbuf;
   }
   return;
}
 
/* _NEW_PROGRAM_CONSTANTS */
drm_intel_bo_unreference(stage_state-const_bo);
-   uint32_t size = brw-vs.prog_data-base.nr_pull_params * 4;
-   stage_state-const_bo = drm_intel_bo_alloc(brw-bufmgr, vp_const_buffer,
-  size, 64);
+   uint32_t size = prog_data-nr_pull_params * 4;
+   stage_state-const_bo = drm_intel_bo_alloc(brw-bufmgr, vec4_const_buffer,
+   size, 64);
 
drm_intel_gem_bo_map_gtt(stage_state-const_bo);
-   for (i = 0; i  brw-vs.prog_data-base.nr_pull_params; i++) {
+
+   for (i = 0; i  prog_data-nr_pull_params; i++) {
   memcpy(stage_state-const_bo-virtual + i * 4,
-brw-vs.prog_data-base.pull_param[i],
+prog_data-pull_param[i],
 4);
}
 
if (0) {
-  for (i = 0; i  ALIGN(brw-vs.prog_data-base.nr_pull_params, 4) / 4;
-   i++) {
+  for (i = 0; i  ALIGN(prog_data-nr_pull_params, 4) / 4; i++) {
 float *row = (float *)stage_state-const_bo-virtual + i * 4;
-printf(vs const surface %3d: %4.3f %4.3f %4.3f %4.3f\n,
+printf(const surface %3d: %4.3f %4.3f %4.3f %4.3f\n,
i, row[0], row[1], row[2], row[3]);
   }
}
@@ -95,7 +88,31 @@ brw_upload_vs_pull_constants(struct brw_context *brw)
brw-vtbl.create_constant_surface(brw, stage_state-const_bo, 0, size,
  stage_state-surf_offset[surf], false);
 
-   brw-state.dirty.brw |= BRW_NEW_VS_CONSTBUF;
+   brw-state.dirty.brw |= brw_new_constbuf;
+}
+
+
+/* Creates a new VS constant buffer reflecting the current VS program's
+ * constants, if needed by the VS program.
+ *
+ * Otherwise

Mesa (master): i965/gs: Implement support for geometry shader surfaces.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 130f0f78bebea8e0666479bfa4e4221245801aaa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=130f0f78bebea8e0666479bfa4e4221245801aaa

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 06:47:34 2013 -0700

i965/gs: Implement support for geometry shader surfaces.

This patch implements pull constant upload, binding table upload, and
surface setup for geometry shaders, by re-using vertex shader code
that was generalized in previous patches.

Based on work by Eric Anholt e...@anholt.net.

v2: Update ditry bits for brw_gs_ubo_surfaces to account for commit
77d8fbc (mesa: add  use a new driver flag for UBO updates instead of
_NEW_BUFFER_OBJECT).

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/Makefile.sources   |1 +
 src/mesa/drivers/dri/i965/brw_context.h  |2 +
 src/mesa/drivers/dri/i965/brw_gs_surface_state.c |  122 ++
 src/mesa/drivers/dri/i965/brw_state.h|3 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |3 +
 5 files changed, 131 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 290cd93..81a16ff 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -63,6 +63,7 @@ i965_FILES = \
brw_gs.c \
brw_gs_emit.c \
brw_gs_state.c \
+   brw_gs_surface_state.c \
brw_interpolation_map.c \
brw_lower_texture_gradients.cpp \
brw_misc_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 974b76a..f4a8647 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -148,6 +148,7 @@ enum brw_state_id {
BRW_STATE_BATCH,
BRW_STATE_INDEX_BUFFER,
BRW_STATE_VS_CONSTBUF,
+   BRW_STATE_GS_CONSTBUF,
BRW_STATE_PROGRAM_CACHE,
BRW_STATE_STATE_BASE_ADDRESS,
BRW_STATE_VUE_MAP_VS,
@@ -185,6 +186,7 @@ enum brw_state_id {
 /** \see brw.state.depth_region */
 #define BRW_NEW_INDEX_BUFFER   (1  BRW_STATE_INDEX_BUFFER)
 #define BRW_NEW_VS_CONSTBUF(1  BRW_STATE_VS_CONSTBUF)
+#define BRW_NEW_GS_CONSTBUF(1  BRW_STATE_GS_CONSTBUF)
 #define BRW_NEW_PROGRAM_CACHE  (1  BRW_STATE_PROGRAM_CACHE)
 #define BRW_NEW_STATE_BASE_ADDRESS (1  BRW_STATE_STATE_BASE_ADDRESS)
 #define BRW_NEW_VUE_MAP_VS (1  BRW_STATE_VUE_MAP_VS)
diff --git a/src/mesa/drivers/dri/i965/brw_gs_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
new file mode 100644
index 000..bae6015
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_gs_surface_state.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include main/mtypes.h
+#include program/prog_parameter.h
+
+#include brw_context.h
+#include brw_state.h
+
+
+/* Creates a new GS constant buffer reflecting the current GS program's
+ * constants, if needed by the GS program.
+ *
+ * Otherwise, constants go through the CURBEs using the brw_constant_buffer
+ * state atom.
+ */
+static void
+brw_upload_gs_pull_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = brw-gs.base;
+
+   /* BRW_NEW_GEOMETRY_PROGRAM */
+   struct brw_geometry_program *gp =
+  (struct brw_geometry_program *) brw-geometry_program;
+
+   if (!gp)
+  return;
+
+   /* CACHE_NEW_GS_PROG */
+   const struct brw_vec4_prog_data *prog_data = brw-gs.prog_data-base;
+
+   /* _NEW_PROGRAM_CONSTANTS */
+   brw_upload_vec4_pull_constants(brw, BRW_NEW_GS_CONSTBUF, gp-program.Base,
+  stage_state, prog_data);
+}
+
+const struct brw_tracked_state brw_gs_pull_constants = {
+   .dirty = {
+  .mesa = (_NEW_PROGRAM_CONSTANTS),
+  .brw = (BRW_NEW_BATCH

Mesa (master): i965/vs: generalize brw_vs_binding_table in preparation for GS.

[Paul Berry]

Module: Mesa
Branch: master
Commit: f986222754f5b7f53f1ad53586b3cd42257fabc7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f986222754f5b7f53f1ad53586b3cd42257fabc7

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 01:23:08 2013 -0700

i965/vs: generalize brw_vs_binding_table in preparation for GS.

v2: Use GLbitfield instead of GLbitfield64 in
brw_vec4_upload_binding_table.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_state.h|6 +++
 src/mesa/drivers/dri/i965/brw_vs_surface_state.c |   42 +++---
 2 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 695a84c..c2df9e5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -122,6 +122,7 @@ extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state gen7_wm_state;
 extern const struct brw_tracked_state haswell_cut_index;
 
+
 /* brw_misc_state.c */
 void brw_upload_invariant_state(struct brw_context *brw);
 uint32_t
@@ -228,6 +229,11 @@ brw_upload_vec4_pull_constants(struct brw_context *brw,
const struct gl_program *prog,
struct brw_stage_state *stage_state,
const struct brw_vec4_prog_data *prog_data);
+void
+brw_vec4_upload_binding_table(struct brw_context *brw,
+  GLbitfield brw_new_binding_table,
+  struct brw_stage_state *stage_state,
+  const struct brw_vec4_prog_data *prog_data);
 
 #ifdef __cplusplus
 }
diff --git a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
index b55febe..dbf26f4 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_surface_state.c
@@ -149,14 +149,13 @@ const struct brw_tracked_state brw_vs_ubo_surfaces = {
.emit = brw_upload_vs_ubo_surfaces,
 };
 
-/**
- * Constructs the binding table for the WM surface state, which maps unit
- * numbers to surface state objects.
- */
-static void
-brw_vs_upload_binding_table(struct brw_context *brw)
+
+void
+brw_vec4_upload_binding_table(struct brw_context *brw,
+  GLbitfield brw_new_binding_table,
+  struct brw_stage_state *stage_state,
+  const struct brw_vec4_prog_data *prog_data)
 {
-   struct brw_stage_state *stage_state = brw-vs.base;
uint32_t *bind;
int i;
 
@@ -164,13 +163,13 @@ brw_vs_upload_binding_table(struct brw_context *brw)
   gen7_create_shader_time_surface(brw, 
stage_state-surf_offset[SURF_INDEX_VEC4_SHADER_TIME]);
}
 
-   /* CACHE_NEW_VS_PROG: Skip making a binding table if we don't use textures 
or
-* pull constants.
+   /* Skip making a binding table if we don't use textures or pull
+* constants.
 */
-   const unsigned entries = brw-vs.prog_data-base.binding_table_size;
+   const unsigned entries = prog_data-binding_table_size;
if (entries == 0) {
   if (stage_state-bind_bo_offset != 0) {
-brw-state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
+brw-state.dirty.brw |= brw_new_binding_table;
 stage_state-bind_bo_offset = 0;
   }
   return;
@@ -183,12 +182,29 @@ brw_vs_upload_binding_table(struct brw_context *brw)
  sizeof(uint32_t) * entries,
  32, stage_state-bind_bo_offset);
 
-   /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */
+   /* BRW_NEW_SURFACES and BRW_NEW_*_CONSTBUF */
for (i = 0; i  entries; i++) {
   bind[i] = stage_state-surf_offset[i];
}
 
-   brw-state.dirty.brw |= BRW_NEW_VS_BINDING_TABLE;
+   brw-state.dirty.brw |= brw_new_binding_table;
+}
+
+
+/**
+ * Constructs the binding table for the WM surface state, which maps unit
+ * numbers to surface state objects.
+ */
+static void
+brw_vs_upload_binding_table(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = brw-vs.base;
+   /* CACHE_NEW_VS_PROG */
+   const struct brw_vec4_prog_data *prog_data = brw-vs.prog_data-base;
+
+   /* BRW_NEW_SURFACES and BRW_NEW_VS_CONSTBUF */
+   brw_vec4_upload_binding_table(brw, BRW_NEW_VS_BINDING_TABLE, stage_state,
+ prog_data);
 }
 
 const struct brw_tracked_state brw_vs_binding_table = {

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Mesa (master): i965: Modify signature to update_texture_surface functions.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 5a8033f142e86ed51511c695138cacaf4532e6cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a8033f142e86ed51511c695138cacaf4532e6cf

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 08:50:57 2013 -0700

i965: Modify signature to update_texture_surface functions.

Previously these functions would accept a pointer to the binding table
and an index indicating which entry in the binding table should be
updated.  Now they merely take a pointer to the binding table entry to
be updated.

This will make it easier to generalize brw_texture_surfaces to support
geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |3 +--
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c  |   20 +---
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |   16 +++-
 3 files changed, 17 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 7aafe6e..939083b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -864,8 +864,7 @@ struct brw_context
 
   void (*update_texture_surface)(struct gl_context *ctx,
  unsigned unit,
- uint32_t *binding_table,
- unsigned surf_index);
+ uint32_t *surf_offset);
   void (*update_renderbuffer_surface)(struct brw_context *brw,
  struct gl_renderbuffer *rb,
  bool layered,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 9f84c93..862989f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -194,8 +194,7 @@ brw_get_texture_swizzle(const struct gl_context *ctx,
 static void
 brw_update_buffer_texture_surface(struct gl_context *ctx,
   unsigned unit,
-  uint32_t *binding_table,
-  unsigned surf_index)
+  uint32_t *surf_offset)
 {
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx-Texture.Unit[unit]._Current;
@@ -213,7 +212,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
}
 
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, binding_table[surf_index]);
+ 6 * 4, 32, surf_offset);
 
surf[0] = (BRW_SURFACE_BUFFER  BRW_SURFACE_TYPE_SHIFT |
  (brw_format_for_mesa_format(format)  BRW_SURFACE_FORMAT_SHIFT));
@@ -226,7 +225,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
 
   /* Emit relocation to surface contents. */
   drm_intel_bo_emit_reloc(brw-batch.bo,
- binding_table[surf_index] + 4,
+ *surf_offset + 4,
  bo, 0, I915_GEM_DOMAIN_SAMPLER, 0);
 
   int w = intel_obj-Base.Size / texel_size;
@@ -247,8 +246,7 @@ brw_update_buffer_texture_surface(struct gl_context *ctx,
 static void
 brw_update_texture_surface(struct gl_context *ctx,
unsigned unit,
-   uint32_t *binding_table,
-   unsigned surf_index)
+   uint32_t *surf_offset)
 {
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx-Texture.Unit[unit]._Current;
@@ -260,12 +258,12 @@ brw_update_texture_surface(struct gl_context *ctx,
uint32_t *surf;
 
if (tObj-Target == GL_TEXTURE_BUFFER) {
-  brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
+  brw_update_buffer_texture_surface(ctx, unit, surf_offset);
   return;
}
 
surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
- 6 * 4, 32, binding_table[surf_index]);
+ 6 * 4, 32, surf_offset);
 
surf[0] = (translate_tex_target(tObj-Target)  BRW_SURFACE_TYPE_SHIFT |
  BRW_SURFACE_MIPMAPLAYOUT_BELOW  BRW_SURFACE_MIPLAYOUT_SHIFT |
@@ -293,7 +291,7 @@ brw_update_texture_surface(struct gl_context *ctx,
 
/* Emit relocation to surface contents */
drm_intel_bo_emit_reloc(brw-batch.bo,
-  binding_table[surf_index] + 4,
+  *surf_offset + 4,
   intelObj-mt-region-bo,
surf[1] - intelObj-mt-region-bo-offset,
   I915_GEM_DOMAIN_SAMPLER, 0);
@@ -763,7 +761,7 @@ brw_update_texture_surfaces(struct brw_context *brw)
  /* _NEW_TEXTURE */
  if (ctx-Texture.Unit[unit]._ReallyEnabled) {
 brw-vtbl.update_texture_surface(ctx

Mesa (master): i965/gs: generalize brw_texture_surfaces in preparation for gs.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 08d8ff0965af7e2dd7beb074efa08ec062b6a04a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08d8ff0965af7e2dd7beb074efa08ec062b6a04a

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Jun 21 09:24:16 2013 -0700

i965/gs: generalize brw_texture_surfaces in preparation for gs.

There is a slight functionality change.  Previously we would compute a
common value for num_samplers for all stages, and populate that many
entries in each stage's surf_offset table regardless of how many
samplers each stage used.  Now we only populate the number of entries
in the surf_offset table corresponding to the number of samplers
actually used by the stage.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |   64 +++---
 1 files changed, 33 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 862989f..a1f97b7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -732,51 +732,53 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces 
= {
.emit = brw_update_renderbuffer_surfaces,
 };
 
-/**
- * Construct SURFACE_STATE objects for enabled textures.
- */
+
 static void
-brw_update_texture_surfaces(struct brw_context *brw)
+update_stage_texture_surfaces(struct brw_context *brw,
+  const struct gl_program *prog,
+  uint32_t *surf_offset)
 {
-   struct gl_context *ctx = brw-ctx;
+   if (!prog)
+  return;
 
-   /* BRW_NEW_VERTEX_PROGRAM and BRW_NEW_FRAGMENT_PROGRAM:
-* Unfortunately, we're stuck using the gl_program structs until the
-* ARB_fragment_program front-end gets converted to GLSL IR.  These
-* have the downside that SamplerUnits is split and only contains the
-* mappings for samplers active in that stage.
-*/
-   struct gl_program *vs = (struct gl_program *) brw-vertex_program;
-   struct gl_program *fs = (struct gl_program *) brw-fragment_program;
+   struct gl_context *ctx = brw-ctx;
 
-   unsigned num_samplers = _mesa_fls(vs-SamplersUsed | fs-SamplersUsed);
+   unsigned num_samplers = _mesa_fls(prog-SamplersUsed);
 
for (unsigned s = 0; s  num_samplers; s++) {
-  brw-vs.base.surf_offset[SURF_INDEX_VEC4_TEXTURE(s)] = 0;
-  brw-wm.surf_offset[SURF_INDEX_TEXTURE(s)] = 0;
+  surf_offset[s] = 0;
 
-  if (vs-SamplersUsed  (1  s)) {
- const unsigned unit = vs-SamplerUnits[s];
+  if (prog-SamplersUsed  (1  s)) {
+ const unsigned unit = prog-SamplerUnits[s];
 
  /* _NEW_TEXTURE */
  if (ctx-Texture.Unit[unit]._ReallyEnabled) {
-brw-vtbl.update_texture_surface(ctx, unit,
- brw-vs.base.surf_offset +
- SURF_INDEX_VEC4_TEXTURE(s));
+brw-vtbl.update_texture_surface(ctx, unit, surf_offset + s);
  }
   }
+   }
+}
 
-  if (fs-SamplersUsed  (1  s)) {
- const unsigned unit = fs-SamplerUnits[s];
 
- /* _NEW_TEXTURE */
- if (ctx-Texture.Unit[unit]._ReallyEnabled) {
-brw-vtbl.update_texture_surface(ctx, unit,
- brw-wm.surf_offset +
- SURF_INDEX_TEXTURE(s));
- }
-  }
-   }
+/**
+ * Construct SURFACE_STATE objects for enabled textures.
+ */
+static void
+brw_update_texture_surfaces(struct brw_context *brw)
+{
+   /* BRW_NEW_VERTEX_PROGRAM */
+   struct gl_program *vs = (struct gl_program *) brw-vertex_program;
+
+   /* BRW_NEW_FRAGMENT_PROGRAM */
+   struct gl_program *fs = (struct gl_program *) brw-fragment_program;
+
+   /* _NEW_TEXTURE */
+   update_stage_texture_surfaces(brw, vs,
+ brw-vs.base.surf_offset +
+ SURF_INDEX_VEC4_TEXTURE(0));
+   update_stage_texture_surfaces(brw, fs,
+ brw-wm.surf_offset +
+ SURF_INDEX_TEXTURE(0));
 
brw-state.dirty.brw |= BRW_NEW_SURFACES;
 }

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Mesa (master): i965/vs: generalize gen6_vs_push_constants in preparation for GS.

[Paul Berry]

Module: Mesa
Branch: master
Commit: f560ce4a38f1316586ad2650488f1a812cfab058
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f560ce4a38f1316586ad2650488f1a812cfab058

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Mar 27 13:15:45 2013 -0700

i965/vs: generalize gen6_vs_push_constants in preparation for GS.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |7 
 src/mesa/drivers/dri/i965/gen6_vs_state.c |   45 ++--
 2 files changed, 36 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index f4a8647..7aafe6e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1628,6 +1628,13 @@ brw_setup_vec4_key_clip_info(struct brw_context *brw,
  struct brw_vec4_prog_key *key,
  bool program_uses_clip_distance);
 
+void
+gen6_upload_vec4_push_constants(struct brw_context *brw,
+const struct gl_program *prog,
+const struct brw_vec4_prog_data *prog_data,
+struct brw_stage_state *stage_state,
+enum state_struct_type type);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 98c7aec..569ec8c 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -33,32 +33,30 @@
 #include program/prog_statevars.h
 #include intel_batchbuffer.h
 
-static void
-gen6_upload_vs_push_constants(struct brw_context *brw)
+void
+gen6_upload_vec4_push_constants(struct brw_context *brw,
+const struct gl_program *prog,
+const struct brw_vec4_prog_data *prog_data,
+struct brw_stage_state *stage_state,
+enum state_struct_type type)
 {
struct gl_context *ctx = brw-ctx;
-   struct brw_stage_state *stage_state = brw-vs.base;
-
-   /* _BRW_NEW_VERTEX_PROGRAM */
-   const struct brw_vertex_program *vp =
-  brw_vertex_program_const(brw-vertex_program);
 
/* Updates the ParamaterValues[i] pointers for all parameters of the
 * basic type of PROGRAM_STATE_VAR.
 */
/* XXX: Should this happen somewhere before to get our state flag set? */
-   _mesa_load_state_parameters(ctx, vp-program.Base.Parameters);
+   _mesa_load_state_parameters(ctx, prog-Parameters);
 
-   /* CACHE_NEW_VS_PROG */
-   if (brw-vs.prog_data-base.nr_params == 0) {
+   if (prog_data-nr_params == 0) {
   stage_state-push_const_size = 0;
} else {
   int params_uploaded;
   float *param;
   int i;
 
-  param = brw_state_batch(brw, AUB_TRACE_VS_CONSTANTS,
- brw-vs.prog_data-base.nr_params * sizeof(float),
+  param = brw_state_batch(brw, type,
+ prog_data-nr_params * sizeof(float),
  32, stage_state-push_const_offset);
 
   /* _NEW_PROGRAM_CONSTANTS
@@ -67,13 +65,13 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
* side effect of dereferencing uniforms, so _NEW_PROGRAM_CONSTANTS
* wouldn't be set for them.
   */
-  for (i = 0; i  brw-vs.prog_data-base.nr_params; i++) {
- param[i] = *brw-vs.prog_data-base.param[i];
+  for (i = 0; i  prog_data-nr_params; i++) {
+ param[i] = *prog_data-param[i];
   }
-  params_uploaded = brw-vs.prog_data-base.nr_params / 4;
+  params_uploaded = prog_data-nr_params / 4;
 
   if (0) {
-printf(VS constant buffer:\n);
+printf(Constant buffer:\n);
 for (i = 0; i  params_uploaded; i++) {
float *buf = param + i * 4;
printf(%d: %f %f %f %f\n,
@@ -87,6 +85,21 @@ gen6_upload_vs_push_constants(struct brw_context *brw)
}
 }
 
+static void
+gen6_upload_vs_push_constants(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = brw-vs.base;
+
+   /* _BRW_NEW_VERTEX_PROGRAM */
+   const struct brw_vertex_program *vp =
+  brw_vertex_program_const(brw-vertex_program);
+   /* CACHE_NEW_VS_PROG */
+   const struct brw_vec4_prog_data *prog_data = brw-vs.prog_data-base;
+
+   gen6_upload_vec4_push_constants(brw, vp-program.Base, prog_data,
+   stage_state, AUB_TRACE_VS_CONSTANTS);
+}
+
 const struct brw_tracked_state gen6_vs_push_constants = {
.dirty = {
   .mesa  = _NEW_TRANSFORM | _NEW_PROGRAM_CONSTANTS,

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Mesa (master): i965/gs: make the state atom for compiling Gen7 geometry shaders.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 4ec2604422fc820e35d8de7f1dd91500a270ff5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ec2604422fc820e35d8de7f1dd91500a270ff5a

Author: Paul Berry stereotype...@gmail.com
Date:   Fri Mar 22 12:34:19 2013 -0700

i965/gs: make the state atom for compiling Gen7 geometry shaders.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

v2: Use unsigned rather than GLuint.

---

 src/mesa/drivers/dri/i965/Makefile.sources|1 +
 src/mesa/drivers/dri/i965/brw_defines.h   |   10 +
 src/mesa/drivers/dri/i965/brw_draw.c  |2 +
 src/mesa/drivers/dri/i965/brw_state.h |1 +
 src/mesa/drivers/dri/i965/brw_state_cache.c   |3 +
 src/mesa/drivers/dri/i965/brw_state_dump.c|3 +
 src/mesa/drivers/dri/i965/brw_state_upload.c  |1 +
 src/mesa/drivers/dri/i965/brw_vec4_gs.c   |  287 +
 src/mesa/drivers/dri/i965/brw_vec4_gs.h   |   41 +++
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |   32 +++
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h   |   13 +
 src/mesa/drivers/dri/i965/brw_vs.c|   13 +-
 12 files changed, 401 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 81a16ff..1f3abac 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -88,6 +88,7 @@ i965_FILES = \
brw_vec4.cpp \
brw_vec4_copy_propagation.cpp \
brw_vec4_emit.cpp \
+   brw_vec4_gs.c \
brw_vec4_gs_visitor.cpp \
brw_vec4_live_variables.cpp \
brw_vec4_reg_allocate.cpp \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 8d9a824..ec6c854 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1283,6 +1283,11 @@ enum brw_message_target {
 # define GEN7_URB_ENTRY_SIZE_SHIFT  16
 # define GEN7_URB_STARTING_ADDRESS_SHIFT25
 
+/* GS URB Entry Allocation Size is a U9-1 field, so the maximum gs_size
+ * is 2^9, or 512.  It's counted in multiples of 64 bytes.
+ */
+#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES   (512*64)
+
 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */
 #define _3DSTATE_PUSH_CONSTANT_ALLOC_GS 0x7915 /* GEN7+ */
 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS 0x7916 /* GEN7+ */
@@ -1348,6 +1353,11 @@ enum brw_message_target {
 # define BRW_GS_EDGE_INDICATOR_0   (1  8)
 # define BRW_GS_EDGE_INDICATOR_1   (1  9)
 
+/* 3DSTATE_GS Output Vertex Size has an effective maximum of 62.  It's
+ * counted in multiples of 16 bytes.
+ */
+#define GEN7_MAX_GS_OUTPUT_VERTEX_SIZE_BYTES   (62*16)
+
 #define _3DSTATE_HS 0x781B /* GEN7+ */
 #define _3DSTATE_TE 0x781C /* GEN7+ */
 #define _3DSTATE_DS 0x781D /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 96ba817..5c17ce6 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -376,6 +376,8 @@ static bool brw_try_draw_prims( struct gl_context *ctx,
 * index.
 */
brw-wm.sampler_count = 
_mesa_fls(ctx-FragmentProgram._Current-Base.SamplersUsed);
+   brw-gs.base.sampler_count = ctx-GeometryProgram._Current ?
+  _mesa_fls(ctx-GeometryProgram._Current-Base.SamplersUsed) : 0;
brw-vs.base.sampler_count =
   _mesa_fls(ctx-VertexProgram._Current-Base.SamplersUsed);
 
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index c9dc507..d24bac5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -72,6 +72,7 @@ extern const struct brw_tracked_state brw_vs_samplers;
 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
 extern const struct brw_tracked_state brw_vs_unit;
+extern const struct brw_tracked_state brw_gs_prog;
 extern const struct brw_tracked_state brw_wm_prog;
 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
 extern const struct brw_tracked_state brw_texture_surfaces;
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c 
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index ddb275f..ef32840 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -50,6 +50,7 @@
 #include brw_vs.h
 #include brw_wm.h
 #include brw_vs.h
+#include brw_vec4_gs.h
 
 #define FILE_DEBUG_FLAG DEBUG_STATE
 
@@ -341,8 +342,10 @@ brw_init_caches(struct brw_context *brw)
  4096, 64);
 
cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
+   cache-aux_compare[BRW_GS_PROG] = brw_gs_prog_data_compare;
cache

Mesa (master): i965/gs: add geometry shader support to brw_texture_surfaces .

[Paul Berry]

Module: Mesa
Branch: master
Commit: 89563489ff3c61c0e40ce3540dd542b118436647
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89563489ff3c61c0e40ce3540dd542b118436647

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 08:05:44 2013 -0700

i965/gs: add geometry shader support to brw_texture_surfaces.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index a1f97b7..37dd5ab 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -769,6 +769,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
/* BRW_NEW_VERTEX_PROGRAM */
struct gl_program *vs = (struct gl_program *) brw-vertex_program;
 
+   /* BRW_NEW_GEOMETRY_PROGRAM */
+   struct gl_program *gs = (struct gl_program *) brw-geometry_program;
+
/* BRW_NEW_FRAGMENT_PROGRAM */
struct gl_program *fs = (struct gl_program *) brw-fragment_program;
 
@@ -776,6 +779,9 @@ brw_update_texture_surfaces(struct brw_context *brw)
update_stage_texture_surfaces(brw, vs,
  brw-vs.base.surf_offset +
  SURF_INDEX_VEC4_TEXTURE(0));
+   update_stage_texture_surfaces(brw, gs,
+ brw-gs.base.surf_offset +
+ SURF_INDEX_VEC4_TEXTURE(0));
update_stage_texture_surfaces(brw, fs,
  brw-wm.surf_offset +
  SURF_INDEX_TEXTURE(0));
@@ -788,6 +794,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
   .mesa = _NEW_TEXTURE,
   .brw = BRW_NEW_BATCH |
  BRW_NEW_VERTEX_PROGRAM |
+ BRW_NEW_GEOMETRY_PROGRAM |
  BRW_NEW_FRAGMENT_PROGRAM,
   .cache = 0
},

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Mesa (master): i965/gs: Implement support for geometry shader samplers.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 4cc692e355e1f2a15c0d3613aec5dfc3a8bf8935
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cc692e355e1f2a15c0d3613aec5dfc3a8bf8935

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 25 07:36:18 2013 -0700

i965/gs: Implement support for geometry shader samplers.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_state.h|1 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |1 +
 src/mesa/drivers/dri/i965/brw_wm_sampler_state.c |   28 ++
 3 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index d24bac5..22e4a61 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -69,6 +69,7 @@ extern const struct brw_tracked_state brw_state_base_address;
 extern const struct brw_tracked_state brw_urb_fence;
 extern const struct brw_tracked_state brw_vs_prog;
 extern const struct brw_tracked_state brw_vs_samplers;
+extern const struct brw_tracked_state brw_gs_samplers;
 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
 extern const struct brw_tracked_state brw_gs_ubo_surfaces;
 extern const struct brw_tracked_state brw_vs_unit;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 004e403..b6a6a0a 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -215,6 +215,7 @@ static const struct brw_tracked_state *gen7_atoms[] =
 
brw_fs_samplers,
brw_vs_samplers,
+   brw_gs_samplers,
gen6_multisample_state,
 
gen7_disable_stages,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index dd5896e..828820d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -443,6 +443,34 @@ const struct brw_tracked_state brw_vs_samplers = {
 };
 
 
+static void
+brw_upload_gs_samplers(struct brw_context *brw)
+{
+   struct brw_stage_state *stage_state = brw-gs.base;
+
+   /* BRW_NEW_GEOMETRY_PROGRAM */
+   struct gl_program *gs = (struct gl_program *) brw-geometry_program;
+   if (!gs)
+  return;
+
+   brw-vtbl.upload_sampler_state_table(brw, gs,
+stage_state-sampler_count,
+stage_state-sampler_offset,
+stage_state-sdc_offset);
+}
+
+
+const struct brw_tracked_state brw_gs_samplers = {
+   .dirty = {
+  .mesa = _NEW_TEXTURE,
+  .brw = BRW_NEW_BATCH |
+ BRW_NEW_GEOMETRY_PROGRAM,
+  .cache = 0
+   },
+   .emit = brw_upload_gs_samplers,
+};
+
+
 void
 gen4_init_vtable_sampler_functions(struct brw_context *brw)
 {

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Mesa (master): i965/vs: Move vs-specific code out of brw_vec4.h.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8f9a339c10c6a0904c0fbdfdcc7a65696d7246e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f9a339c10c6a0904c0fbdfdcc7a65696d7246e9

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 31 20:40:47 2013 -0700

i965/vs: Move vs-specific code out of brw_vec4.h.

Now brw_vec4.h contains only code that is shared between the vertex
and geometry shaders.

Acked-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4.h |   32 
 src/mesa/drivers/dri/i965/brw_vs.h   |   38 ++
 2 files changed, 38 insertions(+), 32 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index e970162..8cb884f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -43,8 +43,6 @@ extern C {
 
 #include glsl/ir.h
 
-struct brw_vs_compile;
-
 
 struct brw_vec4_compile {
GLuint last_scratch; /** measured in 32-byte (register size) units */
@@ -552,36 +550,6 @@ protected:
const bool debug_flag;
 };
 
-class vec4_vs_visitor : public vec4_visitor
-{
-public:
-   vec4_vs_visitor(struct brw_context *brw,
-   struct brw_vs_compile *vs_compile,
-   struct brw_vs_prog_data *vs_prog_data,
-   struct gl_shader_program *prog,
-   struct brw_shader *shader,
-   void *mem_ctx);
-
-protected:
-   virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
-   virtual void setup_payload();
-   virtual void emit_prolog();
-   virtual void emit_program_code();
-   virtual void emit_thread_end();
-   virtual void emit_urb_write_header(int mrf);
-   virtual vec4_instruction *emit_urb_write_opcode(bool complete);
-
-private:
-   int setup_attributes(int payload_reg);
-   void setup_vp_regs();
-   dst_reg get_vp_dst_reg(const prog_dst_register dst);
-   src_reg get_vp_src_reg(const prog_src_register src);
-
-   struct brw_vs_compile * const vs_compile;
-   struct brw_vs_prog_data * const vs_prog_data;
-   src_reg *vp_temp_regs;
-   src_reg vp_addr_reg;
-};
 
 /**
  * The vertex shader code generator.
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h 
b/src/mesa/drivers/dri/i965/brw_vs.h
index 90c96b6..747ba6c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -99,6 +99,44 @@ void brw_vs_prog_data_free(const void *in_prog_data);
 
 #ifdef __cplusplus
 } /* extern C */
+
+
+namespace brw {
+
+class vec4_vs_visitor : public vec4_visitor
+{
+public:
+   vec4_vs_visitor(struct brw_context *brw,
+   struct brw_vs_compile *vs_compile,
+   struct brw_vs_prog_data *vs_prog_data,
+   struct gl_shader_program *prog,
+   struct brw_shader *shader,
+   void *mem_ctx);
+
+protected:
+   virtual dst_reg *make_reg_for_system_value(ir_variable *ir);
+   virtual void setup_payload();
+   virtual void emit_prolog();
+   virtual void emit_program_code();
+   virtual void emit_thread_end();
+   virtual void emit_urb_write_header(int mrf);
+   virtual vec4_instruction *emit_urb_write_opcode(bool complete);
+
+private:
+   int setup_attributes(int payload_reg);
+   void setup_vp_regs();
+   dst_reg get_vp_dst_reg(const prog_dst_register dst);
+   src_reg get_vp_src_reg(const prog_src_register src);
+
+   struct brw_vs_compile * const vs_compile;
+   struct brw_vs_prog_data * const vs_prog_data;
+   src_reg *vp_temp_regs;
+   src_reg vp_addr_reg;
+};
+
+} /* namespace brw */
+
+
 #endif
 
 #endif

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Mesa (master): i965/vec4: Make with_writemask() non-static.

[Paul Berry]

Module: Mesa
Branch: master
Commit: e241e7c979ba2fc558caaeebf7be84f5c705022a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e241e7c979ba2fc558caaeebf7be84f5c705022a

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 31 20:51:48 2013 -0700

i965/vec4: Make with_writemask() non-static.

This will allow it to be shared between brw_vec4_visitor.cpp and
brw_vec4_vs_visitor.cpp (which will be created in the next patch).

Acked-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4.h   |3 +++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |2 +-
 2 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 8cb884f..c5101d3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -183,6 +183,9 @@ public:
src_reg *reladdr;
 };
 
+dst_reg
+with_writemask(dst_reg const r, int mask);
+
 class vec4_instruction : public backend_instruction {
 public:
/* Callers of this ralloc-based new need not call delete. It's
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 6771630..e3bbf91 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -908,7 +908,7 @@ vec4_visitor::emit_if_gen6(ir_if *ir)
emit(IF(this-result, src_reg(0), BRW_CONDITIONAL_NZ));
 }
 
-static dst_reg
+dst_reg
 with_writemask(dst_reg const  r, int mask)
 {
dst_reg result = r;

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Mesa (master): i965/gen7.5: Fix lower bound on number of VS URB entries.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 588ec545acc930470c605005292c8ef10adf4919
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=588ec545acc930470c605005292c8ef10adf4919

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 31 20:23:49 2013 -0700

i965/gen7.5: Fix lower bound on number of VS URB entries.

Haswell GT2 and GT3 require the number of vertex shader URB entries to
be at least 64, not 32.

At the moment, we always meet this requirement automatically, because
in the absence of a geometry shader, we assign all available URB space
to the vertex shader.  But when we turn on support for geometry
shaders, this lower limit will become important.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_context.c |7 +++
 src/mesa/drivers/dri/i965/brw_context.h |1 +
 src/mesa/drivers/dri/i965/gen6_urb.c|2 +-
 src/mesa/drivers/dri/i965/gen7_urb.c|7 ---
 4 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index d0b2fc1..4fcc9fb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -361,6 +361,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 70;
 brw-max_gs_threads = 70;
 brw-urb.size = 128;
+ brw-urb.min_vs_entries = 32;
 brw-urb.max_vs_entries = 640;
 brw-urb.max_gs_entries = 256;
   } else if (brw-gt == 2) {
@@ -368,6 +369,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 280;
 brw-max_gs_threads = 256;
 brw-urb.size = 256;
+ brw-urb.min_vs_entries = 64;
 brw-urb.max_vs_entries = 1664;
 brw-urb.max_gs_entries = 640;
   } else if (brw-gt == 3) {
@@ -375,6 +377,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 280;
 brw-max_gs_threads = 256;
 brw-urb.size = 512;
+ brw-urb.min_vs_entries = 64;
 brw-urb.max_vs_entries = 1664;
 brw-urb.max_gs_entries = 640;
   }
@@ -384,6 +387,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 36;
 brw-max_gs_threads = 36;
 brw-urb.size = 128;
+ brw-urb.min_vs_entries = 32;
 brw-urb.max_vs_entries = 512;
 brw-urb.max_gs_entries = 192;
   } else if (brw-gt == 2) {
@@ -391,6 +395,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 128;
 brw-max_gs_threads = 128;
 brw-urb.size = 256;
+ brw-urb.min_vs_entries = 32;
 brw-urb.max_vs_entries = 704;
 brw-urb.max_gs_entries = 320;
   } else {
@@ -402,6 +407,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 60;
 brw-max_gs_threads = 60;
 brw-urb.size = 64;/* volume 5c.5 section 5.1 */
+ brw-urb.min_vs_entries = 24;
 brw-urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 brw-urb.max_gs_entries = 256;
   } else {
@@ -409,6 +415,7 @@ brwCreateContext(int api,
 brw-max_vs_threads = 24;
 brw-max_gs_threads = 21; /* conservative; 24 if rendering disabled */
 brw-urb.size = 32;/* volume 5c.5 section 5.1 */
+ brw-urb.min_vs_entries = 24;
 brw-urb.max_vs_entries = 256; /* volume 2a (see 3DSTATE_URB) */
 brw-urb.max_gs_entries = 256;
   }
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 64371cf..57f086b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1073,6 +1073,7 @@ struct brw_context
 
   bool constrained;
 
+  GLuint min_vs_entries;/* Minimum number of VS entries */
   GLuint max_vs_entries;   /* Maximum number of VS entries */
   GLuint max_gs_entries;   /* Maximum number of GS entries */
 
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c 
b/src/mesa/drivers/dri/i965/gen6_urb.c
index e16d30a..bb4cfa8 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -83,7 +83,7 @@ gen6_upload_urb( struct brw_context *brw )
brw-urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4);
brw-urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4);
 
-   assert(brw-urb.nr_vs_entries = 24);
+   assert(brw-urb.nr_vs_entries = brw-urb.min_vs_entries);
assert(brw-urb.nr_vs_entries % 4 == 0);
assert(brw-urb.nr_gs_entries % 4 == 0);
assert(vs_size  5);
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 6683117..6dcdfe4 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -195,9 +195,10 @@ gen7_upload_urb(struct brw_context *brw)
 * additional space it could actually make use of).
 */
 
-   /* VS always requires at least 32 URB entries */
+   /* VS has a lower limit on the number of URB entries */
unsigned vs_chunks =
-  ALIGN(32 * vs_entry_size_bytes

Mesa (master): i965/vs: Move vs-specific code out of brw_vec4_visitor.cpp.

[Paul Berry]

Module: Mesa
Branch: master
Commit: ae79e3332eca5c8024c894c7c7689bfbf3311038
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae79e3332eca5c8024c894c7c7689bfbf3311038

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 31 20:56:06 2013 -0700

i965/vs: Move vs-specific code out of brw_vec4_visitor.cpp.

This patch creates a new file brw_vec4_vs_visitor.cpp, to contain code
that is specific to the vertex shader.  Now the organization of vertex
shader and geometry shader visitor code is symmetric: vs-specific code
is in brw_vec4_vs_visitor.cpp, gs-specific code is in
brw_vec4_gs_visitor.cpp, and code shared between vs and gs is in
brw_vec4_visitor.cpp.

Acked-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/Makefile.sources|1 +
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp|  192 --
 src/mesa/drivers/dri/i965/brw_vec4_vs_visitor.cpp |  225 +
 3 files changed, 226 insertions(+), 192 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 1f3abac..5299d0d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -94,6 +94,7 @@ i965_FILES = \
brw_vec4_reg_allocate.cpp \
brw_vec4_visitor.cpp \
brw_vec4_vp.cpp \
+   brw_vec4_vs_visitor.cpp \
brw_vs.c \
brw_vs_state.c \
brw_vs_surface_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index e3bbf91..ca52fd3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -22,12 +22,8 @@
  */
 
 #include brw_vec4.h
-#include brw_vs.h
 #include glsl/ir_uniform.h
 extern C {
-#include main/context.h
-#include main/macros.h
-#include program/prog_parameter.h
 #include program/sampler.h
 }
 
@@ -916,146 +912,6 @@ with_writemask(dst_reg const  r, int mask)
return result;
 }
 
-void
-vec4_vs_visitor::emit_prolog()
-{
-   dst_reg sign_recovery_shift;
-   dst_reg normalize_factor;
-   dst_reg es3_normalize_factor;
-
-   for (int i = 0; i  VERT_ATTRIB_MAX; i++) {
-  if (vs_prog_data-inputs_read  BITFIELD64_BIT(i)) {
- uint8_t wa_flags = vs_compile-key.gl_attrib_wa_flags[i];
- dst_reg reg(ATTR, i);
- dst_reg reg_d = reg;
- reg_d.type = BRW_REGISTER_TYPE_D;
- dst_reg reg_ud = reg;
- reg_ud.type = BRW_REGISTER_TYPE_UD;
-
- /* Do GL_FIXED rescaling for GLES2.0.  Our GL_FIXED attributes
-  * come in as floating point conversions of the integer values.
-  */
- if (wa_flags  BRW_ATTRIB_WA_COMPONENT_MASK) {
-dst_reg dst = reg;
-dst.type = brw_type_for_base_type(glsl_type::vec4_type);
-dst.writemask = (1  (wa_flags  BRW_ATTRIB_WA_COMPONENT_MASK)) - 
1;
-emit(MUL(dst, src_reg(dst), src_reg(1.0f / 65536.0f)));
- }
-
- /* Do sign recovery for 2101010 formats if required. */
- if (wa_flags  BRW_ATTRIB_WA_SIGN) {
-if (sign_recovery_shift.file == BAD_FILE) {
-   /* shift constant: 22,22,22,30 */
-   sign_recovery_shift = dst_reg(this, glsl_type::uvec4_type);
-   emit(MOV(with_writemask(sign_recovery_shift, WRITEMASK_XYZ), 
src_reg(22u)));
-   emit(MOV(with_writemask(sign_recovery_shift, WRITEMASK_W), 
src_reg(30u)));
-}
-
-emit(SHL(reg_ud, src_reg(reg_ud), src_reg(sign_recovery_shift)));
-emit(ASR(reg_d, src_reg(reg_d), src_reg(sign_recovery_shift)));
- }
-
- /* Apply BGRA swizzle if required. */
- if (wa_flags  BRW_ATTRIB_WA_BGRA) {
-src_reg temp = src_reg(reg);
-temp.swizzle = BRW_SWIZZLE4(2,1,0,3);
-emit(MOV(reg, temp));
- }
-
- if (wa_flags  BRW_ATTRIB_WA_NORMALIZE) {
-/* ES 3.0 has different rules for converting signed normalized
- * fixed-point numbers than desktop GL.
- */
-if (_mesa_is_gles3(ctx)  (wa_flags  BRW_ATTRIB_WA_SIGN)) {
-   /* According to equation 2.2 of the ES 3.0 specification,
-* signed normalization conversion is done by:
-*
-* f = c / (2^(b-1)-1)
-*/
-   if (es3_normalize_factor.file == BAD_FILE) {
-  /* mul constant: 1 / (2^(b-1) - 1) */
-  es3_normalize_factor = dst_reg(this, glsl_type::vec4_type);
-  emit(MOV(with_writemask(es3_normalize_factor, WRITEMASK_XYZ),
-   src_reg(1.0f / ((19) - 1;
-  emit(MOV(with_writemask(es3_normalize_factor, WRITEMASK_W),
-   src_reg(1.0f / ((11) - 1;
-   }
-
-   dst_reg dst = reg;
-   dst.type = brw_type_for_base_type(glsl_type::vec4_type

Mesa (master): i965/gs: Don't assign gl_Layer its own slot in the VUE map.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 9dfa8ae662f522d7fb9e9be11a71a2eafc7985f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9dfa8ae662f522d7fb9e9be11a71a2eafc7985f0

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 13:57:35 2013 -0700

i965/gs: Don't assign gl_Layer its own slot in the VUE map.

Reviewed-by: Chad Versace chad.vers...@linux.intel.com

---

 src/mesa/drivers/dri/i965/brw_vs.c |5 +
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index b81a538..7c7493f 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -64,6 +64,11 @@ brw_compute_vue_map(struct brw_context *brw, struct 
brw_vue_map *vue_map,
vue_map-slots_valid = slots_valid;
int i;
 
+   /* gl_Layer doesn't get its own varying slot--it's stored in the virst VUE
+* slot (VARYING_SLOT_PSIZ).
+*/
+   slots_valid = ~VARYING_BIT_LAYER;
+
/* Make sure that the values we store in vue_map-varying_to_slot and
 * vue_map-slot_to_varying won't overflow the signed chars that are used
 * to store them.  Note that since vue_map-slot_to_varying sometimes holds

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Mesa (master): vbo: Implement new gs prim types in vbo_count_tessellated_primitives.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 2924b5f73bd9468e59da9bf53e88c314669a729f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2924b5f73bd9468e59da9bf53e88c314669a729f

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Aug 27 20:51:31 2013 -0700

vbo: Implement new gs prim types in vbo_count_tessellated_primitives.

Reviewed-by: Matt Turner matts...@gmail.com

---

 src/mesa/vbo/vbo_exec.c |   12 
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/src/mesa/vbo/vbo_exec.c b/src/mesa/vbo/vbo_exec.c
index 9c20bde..aa2c7b0 100644
--- a/src/mesa/vbo/vbo_exec.c
+++ b/src/mesa/vbo/vbo_exec.c
@@ -149,6 +149,18 @@ vbo_count_tessellated_primitives(GLenum mode, GLuint count,
case GL_QUADS:
   num_primitives = (count / 4) * 2;
   break;
+   case GL_LINES_ADJACENCY:
+  num_primitives = count / 4;
+  break;
+   case GL_LINE_STRIP_ADJACENCY:
+  num_primitives = count = 4 ? count - 3 : 0;
+  break;
+   case GL_TRIANGLES_ADJACENCY:
+  num_primitives = count / 6;
+  break;
+   case GL_TRIANGLE_STRIP_ADJACENCY:
+  num_primitives = count = 6 ? (count - 4) / 2 : 0;
+  break;
default:
   assert(!Unexpected primitive type in count_tessellated_primitives);
   num_primitives = 0;

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Mesa (master): i965/gs: Add opcodes needed for EndPrimitive().

[Paul Berry]

Module: Mesa
Branch: master
Commit: 6ced0fa57f1ad308b8cdb0ad7ccb9dffb30ad107
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ced0fa57f1ad308b8cdb0ad7ccb9dffb30ad107

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Apr 21 08:51:33 2013 -0700

i965/gs: Add opcodes needed for EndPrimitive().

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_defines.h |   26 
 src/mesa/drivers/dri/i965/brw_shader.cpp|4 +
 src/mesa/drivers/dri/i965/brw_vec4.h|2 +
 src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |   88 +++
 4 files changed, 120 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 007e7fb..e9e0c4a 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -847,6 +847,32 @@ enum opcode {
 * scratch reads and writes to operate correctly.
 */
GS_OPCODE_SET_DWORD_2_IMMED,
+
+   /**
+* Prepare the dst register for storage in the Channel Mask fields of a
+* URB_WRITE message header.
+*
+* DWORD 4 of dst is shifted left by 4 bits, so that later,
+* GS_OPCODE_SET_CHANNEL_MASKS can OR DWORDs 0 and 4 together to form the
+* final channel mask.
+*
+* Note: since GS_OPCODE_SET_CHANNEL_MASKS ORs DWORDs 0 and 4 together to
+* form the final channel mask, DWORDs 0 and 4 of the dst register must not
+* have any extraneous bits set prior to execution of this opcode (that is,
+* they should be in the range 0x0 to 0xf).
+*/
+   GS_OPCODE_PREPARE_CHANNEL_MASKS,
+
+   /**
+* Set the Channel Mask fields of a URB_WRITE message header.
+*
+* - dst is the MRF containing the message header.
+*
+* - src.x is the channel mask, as prepared by
+*   GS_OPCODE_PREPARE_CHANNEL_MASKS.  DWORDs 0 and 4 are OR'ed together to
+*   form the final channel mask.
+*/
+   GS_OPCODE_SET_CHANNEL_MASKS,
 };
 
 #define BRW_PREDICATE_NONE 0
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index e7dbdbe..53364a5 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -507,6 +507,10 @@ brw_instruction_name(enum opcode op)
   return set_vertex_count;
case GS_OPCODE_SET_DWORD_2_IMMED:
   return set_dword_2_immed;
+   case GS_OPCODE_PREPARE_CHANNEL_MASKS:
+  return prepare_channel_masks;
+   case GS_OPCODE_SET_CHANNEL_MASKS:
+  return set_channel_masks;
 
default:
   /* Yes, this leaks.  It's in debug code, it should never occur, and if
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index c5101d3..cba5cd4 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -610,6 +610,8 @@ private:
void generate_gs_set_vertex_count(struct brw_reg dst,
  struct brw_reg src);
void generate_gs_set_dword_2_immed(struct brw_reg dst, struct brw_reg src);
+   void generate_gs_prepare_channel_masks(struct brw_reg dst);
+   void generate_gs_set_channel_masks(struct brw_reg dst, struct brw_reg src);
void generate_oword_dual_block_offsets(struct brw_reg m1,
  struct brw_reg index);
void generate_scratch_write(vec4_instruction *inst,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index bf04bd9..6916134 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -516,6 +516,86 @@ vec4_generator::generate_gs_set_dword_2_immed(struct 
brw_reg dst,
 }
 
 void
+vec4_generator::generate_gs_prepare_channel_masks(struct brw_reg dst)
+{
+   /* We want to left shift just DWORD 4 (the x component belonging to the
+* second geometry shader invocation) by 4 bits.  So generate the
+* instruction:
+*
+* shl(1) dst.41UD dst.40,1,0UD 4UD { align1 WE_all }
+*/
+   dst = suboffset(vec1(dst), 4);
+   brw_push_insn_state(p);
+   brw_set_access_mode(p, BRW_ALIGN_1);
+   brw_set_mask_control(p, BRW_MASK_DISABLE);
+   brw_SHL(p, dst, dst, brw_imm_ud(4));
+   brw_pop_insn_state(p);
+}
+
+void
+vec4_generator::generate_gs_set_channel_masks(struct brw_reg dst,
+  struct brw_reg src)
+{
+   /* From p21 of volume 4 part 2 of the Ivy Bridge PRM (2.4.3.1 Message
+* Header: M0.5):
+*
+* 15 Vertex 1 DATA [3] / Vertex 0 DATA[7] Channel Mask
+*
+*When Swizzle Control = URB_INTERLEAVED this bit controls Vertex 1
+*DATA[3], when Swizzle Control = URB_NOSWIZZLE this bit controls
+*Vertex 0 DATA[7].  This bit is ANDed with the corresponding
+*channel enable to determine the final channel enable

Mesa (master): i965/gen7: Extract a function for setting up a shader stage' s constants.

[Paul Berry]

Module: Mesa
Branch: master
Commit: ec5c92429044db5aa797c377fe29984538f09785
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec5c92429044db5aa797c377fe29984538f09785

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  9 07:28:17 2013 -0700

i965/gen7: Extract a function for setting up a shader stage's constants.

This will allow us to reuse some code when setting up the geometry
shader stage.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_state.h |6 +++
 src/mesa/drivers/dri/i965/gen7_vs_state.c |   61 +
 2 files changed, 42 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 22e4a61..4c4a536 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -240,6 +240,12 @@ brw_vec4_upload_binding_table(struct brw_context *brw,
   struct brw_stage_state *stage_state,
   const struct brw_vec4_prog_data *prog_data);
 
+/* gen7_vs_state.c */
+void
+gen7_upload_constant_state(struct brw_context *brw,
+   const struct brw_stage_state *stage_state,
+   bool active, unsigned opcode);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c 
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 6e72e8f..4fd1913 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -29,6 +29,40 @@
 #include program/prog_statevars.h
 #include intel_batchbuffer.h
 
+
+void
+gen7_upload_constant_state(struct brw_context *brw,
+   const struct brw_stage_state *stage_state,
+   bool active, unsigned opcode)
+{
+   if (!active || stage_state-push_const_size == 0) {
+  /* Disable the push constant buffers. */
+  BEGIN_BATCH(7);
+  OUT_BATCH(opcode  16 | (7 - 2));
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  ADVANCE_BATCH();
+   } else {
+  BEGIN_BATCH(7);
+  OUT_BATCH(opcode  16 | (7 - 2));
+  OUT_BATCH(stage_state-push_const_size);
+  OUT_BATCH(0);
+  /* Pointer to the constant buffer.  Covered by the set of state flags
+   * from gen6_prepare_wm_contants
+   */
+  OUT_BATCH(stage_state-push_const_offset | GEN7_MOCS_L3);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  OUT_BATCH(0);
+  ADVANCE_BATCH();
+   }
+}
+
+
 static void
 upload_vs_state(struct brw_context *brw)
 {
@@ -52,31 +86,8 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(stage_state-sampler_offset);
ADVANCE_BATCH();
 
-   if (stage_state-push_const_size == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(7);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS  16 | (7 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(7);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS  16 | (7 - 2));
-  OUT_BATCH(stage_state-push_const_size);
-  OUT_BATCH(0);
-  /* Pointer to the VS constant buffer.  Covered by the set of
-   * state flags from gen6_prepare_wm_contants
-   */
-  OUT_BATCH(stage_state-push_const_offset | GEN7_MOCS_L3);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   }
+   gen7_upload_constant_state(brw, stage_state, true /* active */,
+  _3DSTATE_CONSTANT_VS);
 
/* Use ALT floating point mode for ARB vertex programs, because they
 * require 0^0 == 1.

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Mesa (master): i965/gen7: Allow URB_WRITE channel masks to be used.

[Paul Berry]

Module: Mesa
Branch: master
Commit: bf5419e389a4a8339699e25ddb6cbe902cc22357
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf5419e389a4a8339699e25ddb6cbe902cc22357

Author: Paul Berry stereotype...@gmail.com
Date:   Sat Aug 10 21:57:59 2013 -0700

i965/gen7: Allow URB_WRITE channel masks to be used.

Previously, brw_urb_WRITE() would unconditionally override the channel
masks in the URB_WRITE message to 0xff (indicating that all channels
should be written to the URB).

In order to support geometry shader EndPrimitive functionality, we'll
need the ability to set the channel masks programatically, so that we
can output just 32 of the control data bits at a time.  So this patch
adds a flag that will prevent brw_urb_WRITE() from overriding them.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_eu.h  |6 ++
 src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 6ac1c68..4d47cdd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -258,6 +258,12 @@ enum brw_urb_write_flags {
BRW_URB_WRITE_PER_SLOT_OFFSET = 0x10,
 
/**
+* Indicates that the channel masks in the URB_WRITE message header should
+* not be overridden to 0xff (gen == 7).
+*/
+   BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
+
+   /**
 * Convenient combination of flags: end the thread while simultaneously
 * marking the given URB entry as complete.
 */
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 36c494e..a99a354 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2224,7 +2224,7 @@ void brw_urb_WRITE(struct brw_compile *p,
 
gen6_resolve_implied_move(p, src0, msg_reg_nr);
 
-   if (brw-gen == 7) {
+   if (brw-gen == 7  !(flags  BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
   /* Enable Channel Masks in the URB_WRITE_HWORD message header */
   brw_push_insn_state(p);
   brw_set_access_mode(p, BRW_ALIGN_1);

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Mesa (master): i965/gs: Set control data header size/ format appropriately for EndPrimitive().

[Paul Berry]

Module: Mesa
Branch: master
Commit: 247f90c77e8f3894e963d796628246ba0bde27b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=247f90c77e8f3894e963d796628246ba0bde27b5

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 18 21:18:19 2013 -0700

i965/gs: Set control data header size/format appropriately for EndPrimitive().

The gen7 geometry shader uses a control data header at the beginning
of the output URB entry to store either

(a) flag bits (1 bit/vertex) indicating whether EndPrimitive() was
called after each vertex, or

(b) stream ID bits (2 bits/vertex) indicating which stream each vertex
should be sent to (when multiple transform feedback streams are in
use).

Fortunately, OpenGL only requires separate streams to be supported
when the output type is points, and EndPrimitive() only has an effect
when the output type is line_strip or triangle_strip, so it's not a
problem that these two uses of the control data header are mutually
exclusive.

This patch modifies do_vec4_gs_prog() to determine the correct
hardware settings for configuring the control data header, and
modifies upload_gs_state() to propagate these settings to the
hardware.

In addition, it modifies do_vec4_gs_prog() to ensure that the output
URB entry is large enough to contain both the output vertices *and*
the control data header.

Finally, it modifies vec4_gs_visitor so that it accounts for the size
of the control data header when computing the offset within the URB
where output vertex data should be stored.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com

v2: Fixed incorrect handling of IVB/HSW differences.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |   14 +++
 src/mesa/drivers/dri/i965/brw_defines.h   |5 +++
 src/mesa/drivers/dri/i965/brw_vec4_gs.c   |   33 +
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |1 +
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h   |3 ++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp|2 +-
 src/mesa/drivers/dri/i965/gen7_gs_state.c |   41 ++---
 7 files changed, 84 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 57f086b..c566bba 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -548,6 +548,20 @@ struct brw_gs_prog_data
unsigned output_vertex_size_hwords;
 
unsigned output_topology;
+
+   /**
+* Size of the control data (cut bits or StreamID bits), in hwords (32
+* bytes).  0 if there is no control data.
+*/
+   unsigned control_data_header_size_hwords;
+
+   /**
+* Format of the control data (either GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID
+* if the control data is StreamID bits, or
+* GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT if the control data is cut bits).
+* Ignored if control_data_header_size is 0.
+*/
+   unsigned control_data_format;
 };
 
 /** Number of texture sampler units */
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 0406c4d..85e414d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1337,6 +1337,10 @@ enum brw_message_target {
 /* DW5 */
 # define GEN6_GS_MAX_THREADS_SHIFT 25
 # define HSW_GS_MAX_THREADS_SHIFT  24
+# define IVB_GS_CONTROL_DATA_FORMAT_SHIFT  24
+# define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_CUT 0
+# define GEN7_GS_CONTROL_DATA_FORMAT_GSCTL_SID 1
+# define GEN7_GS_CONTROL_DATA_HEADER_SIZE_SHIFT20
 # define GEN7_GS_DISPATCH_MODE_SINGLE  (0  11)
 # define GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE   (1  11)
 # define GEN7_GS_DISPATCH_MODE_DUAL_OBJECT (2  11)
@@ -1346,6 +1350,7 @@ enum brw_message_target {
 # define GEN7_GS_INCLUDE_PRIMITIVE_ID  (1  4)
 # define GEN7_GS_ENABLE(1  0)
 /* DW6 */
+# define HSW_GS_CONTROL_DATA_FORMAT_SHIFT  31
 # define GEN6_GS_REORDER   (1  30)
 # define GEN6_GS_DISCARD_ADJACENCY (1  29)
 # define GEN6_GS_SVBI_PAYLOAD_ENABLE   (1  28)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs.c 
b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
index 7ab03ac..f67ae2b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
@@ -62,6 +62,38 @@ do_gs_prog(struct brw_context *brw,
c.prog_data.base.param = rzalloc_array(NULL, const float *, param_count);
c.prog_data.base.pull_param = rzalloc_array(NULL, const float *, 
param_count);
 
+   if (gp-program.OutputType == GL_POINTS) {
+  /* When the output type is points, the geometry shader may output data
+   * to multiple streams, and EndPrimitive() has no effect.  So we

Mesa (master): glsl: During linking, record whether a GS uses EndPrimitive( ).

[Paul Berry]

Module: Mesa
Branch: master
Commit: 1a33e0233ad5bfd0b7f62ae25811532c5784653f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a33e0233ad5bfd0b7f62ae25811532c5784653f

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 18 20:59:37 2013 -0700

glsl: During linking, record whether a GS uses EndPrimitive().

This information will be useful in the i965 back end, since we can
save some compilation effort if we know from the outset that the
shader never calls EndPrimitive().

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/linker.cpp   |   31 +++
 src/mesa/main/mtypes.h|2 ++
 src/mesa/main/shaderapi.c |1 +
 3 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/src/glsl/linker.cpp b/src/glsl/linker.cpp
index 65afc2e..8a143fd 100644
--- a/src/glsl/linker.cpp
+++ b/src/glsl/linker.cpp
@@ -249,6 +249,33 @@ public:
 };
 
 
+/**
+ * Visitor that determines whether or not a shader uses ir_end_primitive.
+ */
+class find_end_primitive_visitor : public ir_hierarchical_visitor {
+public:
+   find_end_primitive_visitor()
+  : found(false)
+   {
+  /* empty */
+   }
+
+   virtual ir_visitor_status visit(ir_end_primitive *)
+   {
+  found = true;
+  return visit_stop;
+   }
+
+   bool end_primitive_found()
+   {
+  return found;
+   }
+
+private:
+   bool found;
+};
+
+
 void
 linker_error(gl_shader_program *prog, const char *fmt, ...)
 {
@@ -517,6 +544,10 @@ validate_geometry_shader_executable(struct 
gl_shader_program *prog,
 
analyze_clip_usage(geometry, prog, shader, prog-Geom.UsesClipDistance,
   prog-Geom.ClipDistanceArraySize);
+
+   find_end_primitive_visitor end_primitive;
+   end_primitive.run(shader-ir);
+   prog-Geom.UsesEndPrimitive = end_primitive.end_primitive_found();
 }
 
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index ca7111e..9df1654 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1931,6 +1931,7 @@ struct gl_geometry_program
GL_TRIANGLES, or GL_TRIANGLES_ADJACENCY_ARB */
GLenum OutputType; /** GL_POINTS, GL_LINE_STRIP or GL_TRIANGLE_STRIP */
GLboolean UsesClipDistance;
+   GLboolean UsesEndPrimitive;
 };
 
 
@@ -2364,6 +2365,7 @@ struct gl_shader_program
   GLboolean UsesClipDistance;
   GLuint ClipDistanceArraySize; /** Size of the gl_ClipDistance array, or
  0 if not present. */
+  GLboolean UsesEndPrimitive;
} Geom;
 
/** Vertex shader state */
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 4fe9d9c..a2386fb 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -1872,6 +1872,7 @@ _mesa_copy_linked_program_data(gl_shader_type type,
   dst_gp-InputType = src-Geom.InputType;
   dst_gp-OutputType = src-Geom.OutputType;
   dst_gp-UsesClipDistance = src-Geom.UsesClipDistance;
+  dst_gp-UsesEndPrimitive = src-Geom.UsesEndPrimitive;
}
   break;
default:

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Mesa (master): i965/vec4: Add the ability to emit opcodes with just a dst register.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 564a900a4539996b139b8d7618a40b22bbad1290
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=564a900a4539996b139b8d7618a40b22bbad1290

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Apr 21 08:51:33 2013 -0700

i965/vec4: Add the ability to emit opcodes with just a dst register.

This is needed for GS_OPCODE_PREPARE_CHANNEL_MASKS.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4.h   |2 ++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |6 ++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index cba5cd4..f0ab53d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -394,6 +394,8 @@ public:
 
vec4_instruction *emit(enum opcode opcode);
 
+   vec4_instruction *emit(enum opcode opcode, dst_reg dst);
+
vec4_instruction *emit(enum opcode opcode, dst_reg dst, src_reg src0);
 
vec4_instruction *emit(enum opcode opcode, dst_reg dst,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 4760a53..304636a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -83,6 +83,12 @@ vec4_visitor::emit(enum opcode opcode, dst_reg dst, src_reg 
src0)
 }
 
 vec4_instruction *
+vec4_visitor::emit(enum opcode opcode, dst_reg dst)
+{
+   return emit(new(mem_ctx) vec4_instruction(this, opcode, dst));
+}
+
+vec4_instruction *
 vec4_visitor::emit(enum opcode opcode)
 {
return emit(new(mem_ctx) vec4_instruction(this, opcode, dst_reg()));

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Mesa (master): i965/gs: Add a state atom to set up geometry shader state.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 79d9c6b7ffe32c146835d27431a66aaf413836fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79d9c6b7ffe32c146835d27431a66aaf413836fd

Author: Paul Berry stereotype...@gmail.com
Date:   Wed Mar 27 13:21:36 2013 -0700

i965/gs: Add a state atom to set up geometry shader state.

v2: Do not attempt to share the code that uploads
3DSTATE_BINDING_TABLE_POINTERS_GS, 3DSTATE_SAMPLER_STATE_POINTERS_GS,
or 3DSTATE_GS with VS.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com

v3: Add _NEW_TRANSFORM to gen7_gs_state.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/Makefile.sources   |1 +
 src/mesa/drivers/dri/i965/brw_defines.h  |7 ++
 src/mesa/drivers/dri/i965/brw_state.h|2 +
 src/mesa/drivers/dri/i965/brw_state_upload.c |2 +
 src/mesa/drivers/dri/i965/gen7_disable.c |   33 --
 src/mesa/drivers/dri/i965/gen7_gs_state.c|  144 ++
 6 files changed, 156 insertions(+), 33 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 5299d0d..07c1053 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -122,6 +122,7 @@ i965_FILES = \
gen7_blorp.cpp \
gen7_clip_state.c \
gen7_disable.c \
+gen7_gs_state.c \
gen7_misc_state.c \
gen7_sampler_state.c \
gen7_sf_state.c \
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index d5a12f1..0406c4d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1328,15 +1328,22 @@ enum brw_message_target {
 # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754  (0  16)
 # define GEN6_GS_FLOATING_POINT_MODE_ALT   (1  16)
 /* DW4 */
+# define GEN7_GS_OUTPUT_VERTEX_SIZE_SHIFT  23
+# define GEN7_GS_OUTPUT_TOPOLOGY_SHIFT 17
 # define GEN6_GS_URB_READ_LENGTH_SHIFT 11
 # define GEN7_GS_INCLUDE_VERTEX_HANDLES(1  10)
 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT   4
 # define GEN6_GS_DISPATCH_START_GRF_SHIFT  0
 /* DW5 */
 # define GEN6_GS_MAX_THREADS_SHIFT 25
+# define HSW_GS_MAX_THREADS_SHIFT  24
+# define GEN7_GS_DISPATCH_MODE_SINGLE  (0  11)
+# define GEN7_GS_DISPATCH_MODE_DUAL_INSTANCE   (1  11)
+# define GEN7_GS_DISPATCH_MODE_DUAL_OBJECT (2  11)
 # define GEN6_GS_STATISTICS_ENABLE (1  10)
 # define GEN6_GS_SO_STATISTICS_ENABLE  (1  9)
 # define GEN6_GS_RENDERING_ENABLE  (1  8)
+# define GEN7_GS_INCLUDE_PRIMITIVE_ID  (1  4)
 # define GEN7_GS_ENABLE(1  0)
 /* DW6 */
 # define GEN6_GS_REORDER   (1  30)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 4c4a536..04c1a97 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -116,6 +116,8 @@ extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_cc_viewport_state_pointer;
 extern const struct brw_tracked_state gen7_clip_state;
 extern const struct brw_tracked_state gen7_disable_stages;
+extern const struct brw_tracked_state gen7_gs_push_constants;
+extern const struct brw_tracked_state gen7_gs_state;
 extern const struct brw_tracked_state gen7_ps_state;
 extern const struct brw_tracked_state gen7_push_constant_space;
 extern const struct brw_tracked_state gen7_sbe_state;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index b6a6a0a..8f21f06 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -196,6 +196,7 @@ static const struct brw_tracked_state *gen7_atoms[] =
gen6_depth_stencil_state,  /* must do before cc unit */
 
gen6_vs_push_constants, /* Before vs_state */
+   gen7_gs_push_constants, /* Before gs_state */
gen6_wm_push_constants, /* Before wm_surfaces and constant_buffer */
 
/* Surface state setup.  Must come before the VS/WM unit.  The binding
@@ -220,6 +221,7 @@ static const struct brw_tracked_state *gen7_atoms[] =
 
gen7_disable_stages,
gen7_vs_state,
+   gen7_gs_state,
gen7_sol_state,
gen7_clip_state,
gen7_sbe_state,
diff --git a/src/mesa/drivers/dri/i965/gen7_disable.c 
b/src/mesa/drivers/dri/i965/gen7_disable.c
index 860aa95..98d115b 100644
--- a/src/mesa/drivers/dri/i965/gen7_disable.c
+++ b/src/mesa/drivers/dri/i965/gen7_disable.c
@@ -29,39 +29,6 @@
 static void
 disable_stages(struct brw_context *brw)
 {
-   assert(!brw-ff_gs.prog_active);
-
-   /* Disable the Geometry Shader (GS) Unit */
-   BEGIN_BATCH(7);
-   OUT_BATCH

Mesa (master): i965/gs: implement EndPrimitive() functionality in the visitor.

[Paul Berry]

Module: Mesa
Branch: master
Commit: ebcdaa7bbc3a10fe59447ae77b508ee85eaa582f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebcdaa7bbc3a10fe59447ae77b508ee85eaa582f

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Apr 21 08:51:33 2013 -0700

i965/gs: implement EndPrimitive() functionality in the visitor.

According to GLSL, the shader may call EndPrimitive() at any point
during its execution, causing the line or triangle strip currently
being output to be terminated and a new strip to be begun.

This is implemented in gen7 hardware by using one control data bit per
vertex, to indicate whether EndPrimitive() was called after that
vertex was emitted.

In order to make this work without sacrificing too much efficiency, we
accumulate 32 control data bits at a time in a GRF.  When we have
accumulated 32 bits (or when the shader terminates), we output them to
the appropriate DWORD in the control data header and reset the
accumulator to 0.

We have to take special care to make sure that EndPrimitive() calls
that occur prior to the first vertex have no effect.

Since geometry shaders that output a large number of vertices are
likely to be rare, an optimization kicks in if max_vertices = 32.  In
this case, we know that we can wait until the end of shader execution
before any control data bits need to be output.

I've tried to write the code in such a way that in the future, we can
easily adapt it to output stream ID bits (which are two bits/vertex
instead of one).

Fixes piglit tests spec/glsl-1.50/glsl-1.50-geometry-end-primitive *.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |  240 -
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h   |2 +
 2 files changed, 241 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 37cde64..960f970 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -135,6 +135,23 @@ vec4_gs_visitor::emit_prolog()
vec4_instruction *inst = emit(MOV(dst_reg(this-vertex_count), 0u));
inst-force_writemask_all = true;
 
+   if (c-control_data_header_size_bits  0) {
+  /* Create a virtual register to hold the current set of control data
+   * bits.
+   */
+  this-control_data_bits = src_reg(this, glsl_type::uint_type);
+
+  /* If we're outputting more than 32 control data bits, then EmitVertex()
+   * will set control_data_bits to 0 after emitting the first vertex.
+   * Otherwise, we need to initialize it to 0 here.
+   */
+  if (c-control_data_header_size_bits = 32) {
+ this-current_annotation = initialize control data bits;
+ inst = emit(MOV(dst_reg(this-control_data_bits), 0u));
+ inst-force_writemask_all = true;
+  }
+   }
+
this-current_annotation = NULL;
 }
 
@@ -150,6 +167,16 @@ vec4_gs_visitor::emit_program_code()
 void
 vec4_gs_visitor::emit_thread_end()
 {
+   if (c-control_data_header_size_bits  0) {
+  /* During shader execution, we only ever call emit_control_data_bits()
+   * just prior to outputting a vertex.  Therefore, the control data bits
+   * corresponding to the most recently output vertex still need to be
+   * emitted.
+   */
+  current_annotation = thread end: emit control data bits;
+  emit_control_data_bits();
+   }
+
/* MRF 0 is reserved for the debugger, so start with message header
 * in MRF 1.
 */
@@ -224,6 +251,124 @@ 
vec4_gs_visitor::compute_array_stride(ir_dereference_array *ir)
 }
 
 
+/**
+ * Write out a batch of 32 control data bits from the control_data_bits
+ * register to the URB.
+ *
+ * The current value of the vertex_count register determines which DWORD in
+ * the URB receives the control data bits.  The control_data_bits register is
+ * assumed to contain the correct data for the vertex that was most recently
+ * output, and all previous vertices that share the same DWORD.
+ *
+ * This function takes care of ensuring that if no vertices have been output
+ * yet, no control bits are emitted.
+ */
+void
+vec4_gs_visitor::emit_control_data_bits()
+{
+   assert(c-control_data_bits_per_vertex != 0);
+
+   /* Since the URB_WRITE_OWORD message operates with 128-bit (vec4 sized)
+* granularity, we need to use two tricks to ensure that the batch of 32
+* control data bits is written to the appropriate DWORD in the URB.  To
+* select which vec4 we are writing to, we use the slot {0,1} offset
+* fields of the message header.  To select which DWORD in the vec4 we are
+* writing to, we use the channel mask fields of the message header.  To
+* avoid penalizing geometry shaders that emit a small number of vertices
+* with extra bookkeeping, we only do each of these tricks when
+* c

Mesa (master): i965/gen7: Add the ability to send URB_WRITE_OWORD messages.

[Paul Berry]

Module: Mesa
Branch: master
Commit: a74af8148ded7417a46be5a9e300f2c6dfed4bed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a74af8148ded7417a46be5a9e300f2c6dfed4bed

Author: Paul Berry stereotype...@gmail.com
Date:   Sun Aug 11 20:29:34 2013 -0700

i965/gen7: Add the ability to send URB_WRITE_OWORD messages.

Previously, brw_urb_WRITE() would always generate a URB_WRITE_HWORD
message, we always wanted to write data to the URB in pairs of varying
slots or larger (an HWORD is 32 bytes, which is 2 varying slots).

In order to support geometry shader EndPrimitive functionality, we'll
need the ability to write to just a single OWORD (16 byte) slot, since
we'll only be outputting 32 of the control data bits at a time.  So
this patch adds a flag that will cause brw_urb_WRITE to generate a
URB_WRITE_OWORD message.

Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_defines.h |3 ++-
 src/mesa/drivers/dri/i965/brw_eu.h  |8 
 src/mesa/drivers/dri/i965/brw_eu_emit.c |7 ++-
 3 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 85e414d..007e7fb 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1172,7 +1172,8 @@ enum brw_message_target {
 #define BRW_MATH_DATA_VECTOR  0
 #define BRW_MATH_DATA_SCALAR  1
 
-#define BRW_URB_OPCODE_WRITE  0
+#define BRW_URB_OPCODE_WRITE_HWORD  0
+#define BRW_URB_OPCODE_WRITE_OWORD  1
 
 #define BRW_URB_SWIZZLE_NONE  0
 #define BRW_URB_SWIZZLE_INTERLEAVE1
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 4d47cdd..720bc74 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -264,6 +264,14 @@ enum brw_urb_write_flags {
BRW_URB_WRITE_USE_CHANNEL_MASKS = 0x20,
 
/**
+* Indicates that the data should be sent to the URB using the
+* URB_WRITE_OWORD message rather than URB_WRITE_HWORD (gen == 7).  This
+* causes offsets to be interpreted as multiples of an OWORD instead of an
+* HWORD, and only allows one OWORD to be written.
+*/
+   BRW_URB_WRITE_OWORD = 0x40,
+
+   /**
 * Convenient combination of flags: end the thread while simultaneously
 * marking the given URB entry as complete.
 */
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index a99a354..cce8752 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -529,7 +529,12 @@ static void brw_set_urb_message( struct brw_compile *p,
  msg_length, response_length, true,
   flags  BRW_URB_WRITE_EOT);
if (brw-gen == 7) {
-  insn-bits3.urb_gen7.opcode = 0; /* URB_WRITE_HWORD */
+  if (flags  BRW_URB_WRITE_OWORD) {
+ assert(msg_length == 2); /* header + one OWORD of data */
+ insn-bits3.urb_gen7.opcode = BRW_URB_OPCODE_WRITE_OWORD;
+  } else {
+ insn-bits3.urb_gen7.opcode = BRW_URB_OPCODE_WRITE_HWORD;
+  }
   insn-bits3.urb_gen7.offset = offset;
   assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
   insn-bits3.urb_gen7.swizzle_control = swizzle_control;

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Mesa (master): glsl/builtins: Fix {texture1D,texture2D, shadow1D}ArrayLod availibility.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 71ffac691b8423d823a4637a0542ccb4005cc996
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71ffac691b8423d823a4637a0542ccb4005cc996

Author: Paul Berry stereotype...@gmail.com
Date:   Thu Sep 12 09:11:37 2013 -0700

glsl/builtins: Fix {texture1D,texture2D,shadow1D}ArrayLod availibility.

These functions are defined in EXT_texture_array, which makes no
mention of what shader types they should be allowed in.  At the time
EXT_texture_array was introduced, functions ending in Lod were
available only in vertex shaders, however this restriction was lifted
in later spec versions and extensions.

We already have the function lod_exists_in_stage() for figuring out
whether functions ending in Lod should be available, so just re-use
that.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/glsl/builtin_functions.cpp |   10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp
index c468bd5..528af0d 100644
--- a/src/glsl/builtin_functions.cpp
+++ b/src/glsl/builtin_functions.cpp
@@ -214,9 +214,9 @@ gpu_shader5(const _mesa_glsl_parse_state *state)
 }
 
 static bool
-vs_texture_array(const _mesa_glsl_parse_state *state)
+texture_array_lod(const _mesa_glsl_parse_state *state)
 {
-   return state-target == vertex_shader 
+   return lod_exists_in_stage(state) 
   state-EXT_texture_array_enable;
 }
 
@@ -1609,7 +1609,7 @@ builtin_builder::create_builtins()
 NULL);
 
add_function(texture1DArrayLod,
-_texture(ir_txl, vs_texture_array, glsl_type::vec4_type, 
glsl_type::sampler1DArray_type, glsl_type::vec2_type),
+_texture(ir_txl, texture_array_lod, glsl_type::vec4_type, 
glsl_type::sampler1DArray_type, glsl_type::vec2_type),
 NULL);
 
add_function(texture1DProjLod,
@@ -1642,7 +1642,7 @@ builtin_builder::create_builtins()
 NULL);
 
add_function(texture2DArrayLod,
-_texture(ir_txl, vs_texture_array, glsl_type::vec4_type, 
glsl_type::sampler2DArray_type, glsl_type::vec3_type),
+_texture(ir_txl, texture_array_lod, glsl_type::vec4_type, 
glsl_type::sampler2DArray_type, glsl_type::vec3_type),
 NULL);
 
add_function(texture2DProjLod,
@@ -1725,7 +1725,7 @@ builtin_builder::create_builtins()
 NULL);
 
add_function(shadow1DArrayLod,
-_texture(ir_txl, vs_texture_array, glsl_type::vec4_type, 
glsl_type::sampler1DArrayShadow_type, glsl_type::vec3_type),
+_texture(ir_txl, texture_array_lod, glsl_type::vec4_type, 
glsl_type::sampler1DArrayShadow_type, glsl_type::vec3_type),
 NULL);
 
add_function(shadow1DProjLod,

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Mesa (master): i965/fs: Change brw_wm_prog_data:: urb_read_length to num_varying_inputs.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8c69eaba1a8a5e8a82112eb5c51b2f8978dd2c23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c69eaba1a8a5e8a82112eb5c51b2f8978dd2c23

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 17:35:32 2013 -0700

i965/fs: Change brw_wm_prog_data::urb_read_length to num_varying_inputs.

On gen4-5, the FS stage reads varying inputs from URB entries that
were output by the SF thread, where each register stores the
interpolation setup for two components of a vec4, therefore the FS
urb_read_length is twice the number of FS input varyings.  On gen6+,
varying inputs are directly deposited in the FS payload by the SF/SBE
fixed function logic, so urb_read_length is irrelevant.

However, in future patches, it will be nice to be able to consult
brw_wm_prog_data to determine how many varying inputs the FS expects
(rather than inferring it from gl_program::InputsRead).  So instead of
storing urb_read_length, we simply store num_varying_inputs in
brw_wm_prog_data.  On gen4-5, we multiply this by 2 to recover the URB
read length.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h  |2 +-
 src/mesa/drivers/dri/i965/brw_fs.cpp |7 ---
 src/mesa/drivers/dri/i965/brw_wm_state.c |3 ++-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 988e9fb..b9c9f50 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -314,7 +314,7 @@ struct brw_shader {
  */
 struct brw_wm_prog_data {
GLuint curb_read_length;
-   GLuint urb_read_length;
+   GLuint num_varying_inputs;
 
GLuint first_curbe_grf;
GLuint first_curbe_grf_16;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index e788196..2967665 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1272,8 +1272,7 @@ fs_visitor::calculate_urb_setup()
  c-prog_data.urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
 
-   /* Each attribute is 4 setup channels, each of which is half a reg. */
-   c-prog_data.urb_read_length = urb_next * 2;
+   c-prog_data.num_varying_inputs = urb_next;
 }
 
 void
@@ -1298,7 +1297,9 @@ fs_visitor::assign_urb_setup()
   }
}
 
-   this-first_non_payload_grf = urb_start + c-prog_data.urb_read_length;
+   /* Each attribute is 4 setup channels, each of which is half a reg. */
+   this-first_non_payload_grf =
+  urb_start + c-prog_data.num_varying_inputs * 2;
 }
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_state.c
index c98ebe7..9aa32c0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -133,7 +133,8 @@ brw_upload_wm_unit(struct brw_context *brw)
}
 
wm-thread3.dispatch_grf_start_reg = brw-wm.prog_data-first_curbe_grf;
-   wm-thread3.urb_entry_read_length = brw-wm.prog_data-urb_read_length;
+   wm-thread3.urb_entry_read_length =
+  brw-wm.prog_data-num_varying_inputs * 2;
wm-thread3.urb_entry_read_offset = 0;
wm-thread3.const_urb_entry_read_length =
   brw-wm.prog_data-curb_read_length;

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Mesa (master): i965/fs: Expose urb_setup as part of brw_wm_prog_data.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 58f01bd17d5587c21d7f543b8f3769f3405dc420
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58f01bd17d5587c21d7f543b8f3769f3405dc420

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 17:24:19 2013 -0700

i965/fs: Expose urb_setup as part of brw_wm_prog_data.

At the moment, for Gen6+, the FS assumes that all varying inputs are
delivered to it in the order in which they appear in the
gl_program::InputsRead bitfield, and the SF/SBE setup code ensures
that they are delivered in this order.

When we add support for more than 64 varying components, this will no
longer always be possible, because the Gen6+ SF/SBE stage is only
capable of performing arbitrary reorderings of 16 varying slots.

To allow extra flexibility in the ordering of FS varyings, this patch
causes the FS to advertise exactly what ordering it expects.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h  |7 +++
 src/mesa/drivers/dri/i965/brw_fs.cpp |   10 +-
 src/mesa/drivers/dri/i965/brw_fs.h   |1 -
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |4 ++--
 4 files changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 108e98c..988e9fb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -336,6 +336,13 @@ struct brw_wm_prog_data {
 */
uint32_t barycentric_interp_modes;
 
+   /**
+* Map from gl_varying_slot to the position within the FS setup data
+* payload where the varying's attribute vertex deltas should be delivered.
+* For varying slots that are not used by the FS, the value is -1.
+*/
+   int urb_setup[VARYING_SLOT_MAX];
+
/* Pointers to tracked values (only valid once
 * _mesa_load_state_parameters has been called at runtime).
 *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index daa23b4..e788196 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1004,7 +1004,7 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
int location = ir-location;
for (unsigned int i = 0; i  array_elements; i++) {
   for (unsigned int j = 0; j  type-matrix_columns; j++) {
-if (urb_setup[location] == -1) {
+if (c-prog_data.urb_setup[location] == -1) {
/* If there's no incoming setup data for this slot, don't
 * emit interpolation for it.
 */
@@ -1231,7 +1231,7 @@ void
 fs_visitor::calculate_urb_setup()
 {
for (unsigned int i = 0; i  VARYING_SLOT_MAX; i++) {
-  urb_setup[i] = -1;
+  c-prog_data.urb_setup[i] = -1;
}
 
int urb_next = 0;
@@ -1239,7 +1239,7 @@ fs_visitor::calculate_urb_setup()
if (brw-gen = 6) {
   for (unsigned int i = 0; i  VARYING_SLOT_MAX; i++) {
 if (fp-Base.InputsRead  BITFIELD64_BIT(i)) {
-   urb_setup[i] = urb_next++;
+   c-prog_data.urb_setup[i] = urb_next++;
 }
   }
} else {
@@ -1257,7 +1257,7 @@ fs_visitor::calculate_urb_setup()
 * incremented, mapped or not.
 */
if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
-  urb_setup[i] = urb_next;
+  c-prog_data.urb_setup[i] = urb_next;
 urb_next++;
 }
   }
@@ -1269,7 +1269,7 @@ fs_visitor::calculate_urb_setup()
* See compile_sf_prog() for more info.
*/
   if (fp-Base.InputsRead  BITFIELD64_BIT(VARYING_SLOT_PNTC))
- urb_setup[VARYING_SLOT_PNTC] = urb_next++;
+ c-prog_data.urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
 
/* Each attribute is 4 setup channels, each of which is half a reg. */
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index cb4ac3b..b77d4de 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -454,7 +454,6 @@ public:
int first_non_payload_grf;
/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
int max_grf;
-   int urb_setup[VARYING_SLOT_MAX];
 
fs_reg *fp_temp_regs;
fs_reg *fp_input_regs;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index d935c7b..8b505a0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2171,10 +2171,10 @@ fs_visitor::emit_dummy_fs()
 struct brw_reg
 fs_visitor::interp_reg(int location, int channel)
 {
-   int regnr = urb_setup[location] * 2 + channel / 2;
+   int regnr = c-prog_data.urb_setup[location] * 2 + channel / 2;
int stride = (channel  1) * 4;
 
-   assert(urb_setup[location] != -1);
+   assert(c-prog_data.urb_setup[location] != -1);
 
return brw_vec1_grf(regnr, stride);
 }

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Mesa (master): i965/sf: Use BRW_SF_URB_ENTRY_READ_OFFSET rather than hardcoded values.

[Paul Berry]

Module: Mesa
Branch: master
Commit: d5b4095356566b33a1c0a8163099d878fe83822a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b4095356566b33a1c0a8163099d878fe83822a

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 08:43:02 2013 -0700

i965/sf: Use BRW_SF_URB_ENTRY_READ_OFFSET rather than hardcoded values.

We always program the SF unit to start reading the vertex URB entry at
offset 1.  In upcoming patches, we'll be adding FS code that relies on
this.  So consistently use the constant BRW_SF_URB_ENTRY_READ_OFFSET
rather than hardcoding a 1.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |   10 ++
 src/mesa/drivers/dri/i965/brw_sf.h|2 --
 src/mesa/drivers/dri/i965/gen6_sf_state.c |2 +-
 src/mesa/drivers/dri/i965/gen7_sf_state.c |2 +-
 4 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index b9c9f50..4c6bedc 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -478,6 +478,16 @@ struct brw_sf_prog_data {
GLuint urb_entry_size;
 };
 
+
+/**
+ * We always program SF to start reading at an offset of 1 (2 varying slots)
+ * from the start of the vertex URB entry.  This causes it to skip:
+ * - VARYING_SLOT_PSIZ and BRW_VARYING_SLOT_NDC on gen4-5
+ * - VARYING_SLOT_PSIZ and VARYING_SLOT_POS on gen6+
+ */
+#define BRW_SF_URB_ENTRY_READ_OFFSET 1
+
+
 struct brw_clip_prog_data {
GLuint curb_read_length;/* user planes? */
GLuint clip_mode;
diff --git a/src/mesa/drivers/dri/i965/brw_sf.h 
b/src/mesa/drivers/dri/i965/brw_sf.h
index 09880fe..0006239 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.h
+++ b/src/mesa/drivers/dri/i965/brw_sf.h
@@ -105,6 +105,4 @@ void brw_emit_point_setup( struct brw_sf_compile *c, bool 
allocate );
 void brw_emit_point_sprite_setup( struct brw_sf_compile *c, bool allocate );
 void brw_emit_anyprim_setup( struct brw_sf_compile *c );
 
-#define BRW_SF_URB_ENTRY_READ_OFFSET 1
-
 #endif
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index c76debe..dfe9a31 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -138,7 +138,7 @@ upload_sf_state(struct brw_context *brw)
bool multisampled_fbo = ctx-DrawBuffer-Visual.samples  1;
 
int attr = 0, input_index = 0;
-   int urb_entry_read_offset = 1;
+   const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
float point_size;
uint16_t attr_overrides[VARYING_SLOT_MAX];
uint32_t point_sprite_origin;
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c 
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 0ff3388..715eb6c 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -40,7 +40,7 @@ upload_sbe_state(struct brw_context *brw)
uint32_t dw1, dw10, dw11;
int i;
int attr = 0, input_index = 0;
-   int urb_entry_read_offset = 1;
+   const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
uint16_t attr_overrides[VARYING_SLOT_MAX];
/* _NEW_BUFFERS */
bool render_to_fbo = _mesa_is_user_fbo(ctx-DrawBuffer);

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Mesa (master): i965/fs: Stop wasting input attribute space on gl_FragCoord and gl_FrontFacing.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 3a83b20dcccf21ec184e35bcfa9bc577379dfd51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a83b20dcccf21ec184e35bcfa9bc577379dfd51

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 22:18:27 2013 -0700

i965/fs: Stop wasting input attribute space on gl_FragCoord and gl_FrontFacing.

Previously, if a fragment shader accessed gl_FragCoord or
gl_FrontFacing, we would assign them their own slots in the fragment
shader input attribute array, using up space that could be made
available to real varyings.  This was not strictly necessary (since
these values are not true varyings, and are instead computed from
other data available in the FS payload).  But we had to do it anyway
because the SF/SBE setup code assumed that every 1 bit in the
gl_program::InputsRead bitfield corresponded to a genuine varying
variable.

Now that the SF/SBE code consults brw_wm_prog_data and only sets up
the attributes that the fragment shader actually needs, we don't have
to do this anymore.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h   |9 +
 src/mesa/drivers/dri/i965/brw_fs.cpp  |3 ++-
 src/mesa/drivers/dri/i965/gen6_sf_state.c |8 
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 4c6bedc..040a8d3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -439,6 +439,15 @@ void brw_compute_vue_map(struct brw_context *brw, struct 
brw_vue_map *vue_map,
  GLbitfield64 slots_valid, bool userclip_active);
 
 
+/**
+ * Bitmask indicating which fragment shader inputs represent varyings (and
+ * hence have to be delivered to the fragment shader by the SF/SBE stage).
+ */
+#define BRW_FS_VARYING_INPUT_MASK \
+   (BITFIELD64_RANGE(0, VARYING_SLOT_MAX)  \
+~VARYING_BIT_POS  ~VARYING_BIT_FACE)
+
+
 /*
  * Mapping of VUE map slots to interpolation modes.
  */
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 2967665..9cb7950 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1238,7 +1238,8 @@ fs_visitor::calculate_urb_setup()
/* Figure out where each of the incoming setup attributes lands. */
if (brw-gen = 6) {
   for (unsigned int i = 0; i  VARYING_SLOT_MAX; i++) {
-if (fp-Base.InputsRead  BITFIELD64_BIT(i)) {
+if (fp-Base.InputsRead  BRW_FS_VARYING_INPUT_MASK 
+ BITFIELD64_BIT(i)) {
c-prog_data.urb_setup[i] = urb_next++;
 }
   }
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 8bac559..6a9fa60 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -56,14 +56,6 @@ static uint32_t
 get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
   int fs_attr, bool two_side_color, uint32_t *max_source_attr)
 {
-   if (fs_attr == VARYING_SLOT_POS) {
-  /* This attribute will be overwritten by the fragment shader's
-   * interpolation code (see emit_interp() in brw_wm_fp.c), so just let it
-   * reference the first available attribute.
-   */
-  return 0;
-   }
-
/* Find the VUE slot for this attribute. */
int slot = vue_map-varying_to_slot[fs_attr];
 

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Mesa (master): i965/sf: Consult brw_wm_prog_data when setting up SF/ SBE state.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 0af1252ae478a28a76326a5c5d784864327793e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0af1252ae478a28a76326a5c5d784864327793e2

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 21:59:04 2013 -0700

i965/sf: Consult brw_wm_prog_data when setting up SF/SBE state.

Previously, the SF/SBE setup code delivered varying inputs to the FS
in the order in which they appear in the gl_program::InputsRead
bitfield, since that's what the FS expects.

When we add support for more than 64 varying components, this will no
longer always be the case, because the Gen6+ SF/SBE stage is only
capable of performing arbitrary reorderings of 16 varying slots.  So,
when there are more than 16 vec4's worth of varying inputs, the FS
will have to adjust the order its input varyings in order to partially
match the order of outputs from the geometry or vertex shader.

To allow extra flexibility in the ordering of FS varyings, this patch
causes the SF/SBE to deliver varying inputs to the FS in exactly the
order that the FS requests, by consulting brw_wm_prog_data::urb_setup
and brw_wm_prog_data::num_varying_inputs.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/gen6_sf_state.c |   45 +---
 src/mesa/drivers/dri/i965/gen7_sf_state.c |   13 +---
 2 files changed, 35 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 91b640d..8bac559 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -137,17 +137,23 @@ calculate_attr_overrides(const struct brw_context *brw,
 {
const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
uint32_t max_source_attr = 0;
-   int input_index = 0;
 
/* _NEW_LIGHT */
bool shade_model_flat = brw-ctx.Light.ShadeModel == GL_FLAT;
 
+   /* Initialize all the attr_overrides to 0.  In the loop below we'll modify
+* just the ones that correspond to inputs used by the fs.
+*/
+   memset(attr_overrides, 0, 16*sizeof(*attr_overrides));
+
for (int attr = 0; attr  VARYING_SLOT_MAX; attr++) {
   enum glsl_interp_qualifier interp_qualifier =
  brw-fragment_program-InterpQualifier[attr];
   bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == 
VARYING_SLOT_COL1;
+  /* CACHE_NEW_WM_PROG */
+  int input_index = brw-wm.prog_data-urb_setup[attr];
 
-  if (!(brw-fragment_program-Base.InputsRead  BITFIELD64_BIT(attr)))
+  if (input_index  0)
 continue;
 
   /* _NEW_POINT */
@@ -166,23 +172,23 @@ calculate_attr_overrides(const struct brw_context *brw,
interp_qualifier == INTERP_QUALIFIER_NONE))
  *flat_enables |= (1  input_index);
 
-  /* The hardware can only do the overrides on 16 overrides at a
-   * time, and the other up to 16 have to be lined up so that the
-   * input index = the output index.  We'll need to do some
-   * tweaking to make sure that's the case.
-   */
-  assert(input_index  16 || attr == input_index);
-
   /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
-  attr_overrides[input_index++] =
+  uint16_t attr_override =
  get_attr_override(brw-vue_map_geom_out,
   urb_entry_read_offset, attr,
brw-ctx.VertexProgram._TwoSideEnabled,
max_source_attr);
-   }
 
-   for (; input_index  VARYING_SLOT_MAX; input_index++)
-  attr_overrides[input_index] = 0;
+  /* The hardware can only do the overrides on 16 overrides at a
+   * time, and the other up to 16 have to be lined up so that the
+   * input index = the output index.  We'll need to do some
+   * tweaking to make sure that's the case.
+   */
+  if (input_index  16)
+ attr_overrides[input_index] = attr_override;
+  else
+ assert(attr_override == input_index);
+   }
 
/* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
 * 3DSTATE_SF DWord 1 bits 15:11, Vertex URB Entry Read Length:
@@ -207,8 +213,8 @@ static void
 upload_sf_state(struct brw_context *brw)
 {
struct gl_context *ctx = brw-ctx;
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   uint32_t num_outputs = 
_mesa_bitcount_64(brw-fragment_program-Base.InputsRead);
+   /* CACHE_NEW_WM_PROG */
+   uint32_t num_outputs = brw-wm.prog_data-num_varying_inputs;
uint32_t dw1, dw2, dw3, dw4, dw16, dw17;
int i;
/* _NEW_BUFFER */
@@ -217,7 +223,7 @@ upload_sf_state(struct brw_context *brw)
 
const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
float point_size;
-   uint16_t attr_overrides[VARYING_SLOT_MAX];
+   uint16_t attr_overrides[16];
uint32_t point_sprite_origin;
 
dw1 = GEN6_SF_SWIZZLE_ENABLE | num_outputs  GEN6_SF_NUM_OUTPUTS_SHIFT;
@@ -353,7 +359,9 @@ upload_sf_state(struct brw_context *brw)
 (1

Mesa (master): i965/fs: Consult brw_wm_prog_data:: num_varying_inputs when setting up WM state.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8c2b9bd1dfd482622260acbbc122bbfc8bd3bbf9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c2b9bd1dfd482622260acbbc122bbfc8bd3bbf9

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 11:30:19 2013 -0700

i965/fs: Consult brw_wm_prog_data::num_varying_inputs when setting up WM state.

Previously, we assumed that the number of varying inputs consumed by
the fragment shader was equal to the number of bits set in
gl_program::InputsRead.  However, we'll soon be making two changes
that will cause that not to be true:

- We'll stop wasting varying input space for gl_FragCoord and
  gl_FrontFacing, which aren't varyings.

- For fragment shaders that have more than 16 varying inputs, we'll
  adjust the layout of the inputs to account for the fact that the
  SF/SBE pipeline stage can't reorder inputs beyond the first 16; if
  there are GS outputs that the FS doens't use (or vice versa) this
  may cause the number of FS varying inputs to change.

So, instead of trying to guess the number of FS inputs from
gl_program::InputsRead, simply read it from
brw_wm_prog_data:num_varying_inputs, which is guaranteed to be correct
since it's populated by fs_visitor::calculate_urb_setup().

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/gen6_wm_state.c |3 ++-
 src/mesa/drivers/dri/i965/gen7_wm_state.c |5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c 
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 2b9f19c..af1c044 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -188,7 +188,8 @@ upload_wm_state(struct brw_context *brw)
   dw5 |= GEN6_WM_DISPATCH_ENABLE;
}
 
-   dw6 |= _mesa_bitcount_64(brw-fragment_program-Base.InputsRead) 
+   /* CACHE_NEW_WM_PROG */
+   dw6 |= brw-wm.prog_data-num_varying_inputs 
   GEN6_WM_NUM_SF_OUTPUTS_SHIFT;
if (multisampled_fbo) {
   /* _NEW_MULTISAMPLE */
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index e7bb861..e9fe95f 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -168,6 +168,7 @@ upload_ps_state(struct brw_context *brw)
 * rendering, CurrentFragmentProgram is used for this check to
 * differentiate between the GLSL and non-GLSL cases.
 */
+   /* BRW_NEW_FRAGMENT_PROGRAM */
if (ctx-Shader.CurrentFragmentProgram == NULL)
   dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
 
@@ -191,8 +192,8 @@ upload_ps_state(struct brw_context *brw)
   dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
}
 
-   /* BRW_NEW_FRAGMENT_PROGRAM */
-   if (brw-fragment_program-Base.InputsRead != 0)
+   /* CACHE_NEW_WM_PROG */
+   if (brw-wm.prog_data-num_varying_inputs != 0)
   dw4 |= GEN7_PS_ATTRIBUTE_ENABLE;
 
dw4 |= GEN7_PS_8_DISPATCH_ENABLE;

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Mesa (master): i965/sf: Consolidate common code for setting up gen6-7 attribute overrides.

[Paul Berry]

Module: Mesa
Branch: master
Commit: af84bbd2caec19c556d279c5a843566cbd99ecb3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af84bbd2caec19c556d279c5a843566cbd99ecb3

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 18:09:08 2013 -0700

i965/sf: Consolidate common code for setting up gen6-7 attribute overrides.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_state.h |9 +-
 src/mesa/drivers/dri/i965/gen6_sf_state.c |  153 
 src/mesa/drivers/dri/i965/gen7_sf_state.c |   64 +---
 3 files changed, 97 insertions(+), 129 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 04c1a97..14f5feb 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -225,9 +225,12 @@ void gen4_init_vtable_sampler_functions(struct brw_context 
*brw);
 void gen7_init_vtable_sampler_functions(struct brw_context *brw);
 
 /* gen6_sf_state.c */
-uint32_t
-get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
-  int fs_attr, bool two_side_color, uint32_t *max_source_attr);
+void
+calculate_attr_overrides(const struct brw_context *brw,
+ uint16_t *attr_overrides,
+ uint32_t *point_sprite_enables,
+ uint32_t *flat_enables,
+ uint32_t *urb_entry_read_length);
 
 /* brw_vs_surface_state.c */
 void
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index dfe9a31..91b640d 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -52,7 +52,7 @@
  * the VUE that are not needed by the fragment shader.  It is measured in
  * 256-bit increments.
  */
-uint32_t
+static uint32_t
 get_attr_override(const struct brw_vue_map *vue_map, int urb_entry_read_offset,
   int fs_attr, bool two_side_color, uint32_t *max_source_attr)
 {
@@ -123,21 +123,98 @@ get_attr_override(const struct brw_vue_map *vue_map, int 
urb_entry_read_offset,
return source_attr;
 }
 
+
+/**
+ * Create the mapping from the FS inputs we produce to the previous pipeline
+ * stage (GS or VS) outputs they source from.
+ */
+void
+calculate_attr_overrides(const struct brw_context *brw,
+ uint16_t *attr_overrides,
+ uint32_t *point_sprite_enables,
+ uint32_t *flat_enables,
+ uint32_t *urb_entry_read_length)
+{
+   const int urb_entry_read_offset = BRW_SF_URB_ENTRY_READ_OFFSET;
+   uint32_t max_source_attr = 0;
+   int input_index = 0;
+
+   /* _NEW_LIGHT */
+   bool shade_model_flat = brw-ctx.Light.ShadeModel == GL_FLAT;
+
+   for (int attr = 0; attr  VARYING_SLOT_MAX; attr++) {
+  enum glsl_interp_qualifier interp_qualifier =
+ brw-fragment_program-InterpQualifier[attr];
+  bool is_gl_Color = attr == VARYING_SLOT_COL0 || attr == 
VARYING_SLOT_COL1;
+
+  if (!(brw-fragment_program-Base.InputsRead  BITFIELD64_BIT(attr)))
+continue;
+
+  /* _NEW_POINT */
+  if (brw-ctx.Point.PointSprite 
+ (attr = VARYING_SLOT_TEX0  attr = VARYING_SLOT_TEX7) 
+ brw-ctx.Point.CoordReplace[attr - VARYING_SLOT_TEX0]) {
+*point_sprite_enables |= (1  input_index);
+  }
+
+  if (attr == VARYING_SLOT_PNTC)
+*point_sprite_enables |= (1  input_index);
+
+  /* flat shading */
+  if (interp_qualifier == INTERP_QUALIFIER_FLAT ||
+  (shade_model_flat  is_gl_Color 
+   interp_qualifier == INTERP_QUALIFIER_NONE))
+ *flat_enables |= (1  input_index);
+
+  /* The hardware can only do the overrides on 16 overrides at a
+   * time, and the other up to 16 have to be lined up so that the
+   * input index = the output index.  We'll need to do some
+   * tweaking to make sure that's the case.
+   */
+  assert(input_index  16 || attr == input_index);
+
+  /* BRW_NEW_VUE_MAP_GEOM_OUT | _NEW_LIGHT | _NEW_PROGRAM */
+  attr_overrides[input_index++] =
+ get_attr_override(brw-vue_map_geom_out,
+  urb_entry_read_offset, attr,
+   brw-ctx.VertexProgram._TwoSideEnabled,
+   max_source_attr);
+   }
+
+   for (; input_index  VARYING_SLOT_MAX; input_index++)
+  attr_overrides[input_index] = 0;
+
+   /* From the Sandy Bridge PRM, Volume 2, Part 1, documentation for
+* 3DSTATE_SF DWord 1 bits 15:11, Vertex URB Entry Read Length:
+*
+* This field should be set to the minimum length required to read the
+*  maximum source attribute.  The maximum source attribute is indicated
+*  by the maximum value of the enabled Attribute # Source Attribute if
+*  Attribute Swizzle Enable is set, Number of Output Attributes-1 if
+*  enable is not set

Mesa (master): i965/fs: Simplify computation of key. input_slots_valid during precompile.

[Paul Berry]

Module: Mesa
Branch: master
Commit: a4546ec114853235db375b20fb47ddcd6a7f21e7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4546ec114853235db375b20fb47ddcd6a7f21e7

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 11:55:17 2013 -0700

i965/fs: Simplify computation of key.input_slots_valid during precompile.

The for loop was rather silly.  In addition to checking brw-gen  6
on each loop iteration, it took pains to exclude bits from
fp-Base.InputsRead that don't correspond to fragment shader inputs.
But those bits would never have been set in the first place, since the
only bits that are ever set in fp-Base.InputsRead are fragment shader
inputs.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   12 +---
 1 files changed, 1 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 9cb7950..004b3b5 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3150,17 +3150,7 @@ brw_fs_precompile(struct gl_context *ctx, struct 
gl_shader_program *prog)
}
 
if (brw-gen  6)
-  key.input_slots_valid |= BITFIELD64_BIT(VARYING_SLOT_POS);
-
-   for (int i = 0; i  VARYING_SLOT_MAX; i++) {
-  if (!(fp-Base.InputsRead  BITFIELD64_BIT(i)))
-continue;
-
-  if (brw-gen  6) {
- if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
-key.input_slots_valid |= BITFIELD64_BIT(i);
-  }
-   }
+  key.input_slots_valid = fp-Base.InputsRead | VARYING_BIT_POS;
 
key.clamp_fragment_color = ctx-API == API_OPENGL_COMPAT;
 

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Mesa (master): i965/gs: Stop storing an input VUE map in the GS program key .

[Paul Berry]

Module: Mesa
Branch: master
Commit: 8a36f4382be0b9ad357f589dc326e14593bdbe8e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a36f4382be0b9ad357f589dc326e14593bdbe8e

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 14:02:22 2013 -0700

i965/gs: Stop storing an input VUE map in the GS program key.

Now that the vertex shader output VUE map is determined solely by a
64-bit bitfield, we don't have to store it in its entirety in the
geometry shader program key; instead, we can just store the bitfield,
and let the geometry shader infer the VUE map at compile time.

This dramatically reduces the size of the geometry shader program key,
which we want to keep small since it gets recomputed whenever the
active program changes.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4_gs.c   |6 --
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |4 ++--
 src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h   |3 ++-
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs.c 
b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
index 2d1d163..c526107 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
@@ -200,10 +200,12 @@ do_gs_prog(struct brw_context *brw,
 
c.prog_data.output_topology = prim_to_hw_prim[gp-program.OutputType];
 
+   brw_compute_vue_map(brw, c.input_vue_map, c.key.input_varyings);
+
/* GS inputs are read from the VUE 256 bits (2 vec4's) at a time, so we
 * need to program a URB read length of ceiling(num_slots / 2).
 */
-   c.prog_data.base.urb_read_length = (c.key.input_vue_map.num_slots + 1) / 2;
+   c.prog_data.base.urb_read_length = (c.input_vue_map.num_slots + 1) / 2;
 
void *mem_ctx = ralloc_context(NULL);
unsigned program_size;
@@ -272,7 +274,7 @@ brw_upload_gs_prog(struct brw_context *brw)
   key.base.tex);
 
/* BRW_NEW_VUE_MAP_VS */
-   key.input_vue_map = brw-vue_map_vs;
+   key.input_varyings = brw-vue_map_vs.slots_valid;
 
if (!brw_search_cache(brw-cache, BRW_GS_PROG,
  key, sizeof(key),
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index 960f970..cb7de8d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -70,8 +70,8 @@ vec4_gs_visitor::setup_varying_inputs(int payload_reg, int 
*attribute_map)
assert(num_input_vertices = MAX_GS_INPUT_VERTICES);
unsigned input_array_stride = c-prog_data.base.urb_read_length * 2;
 
-   for (int slot = 0; slot  c-key.input_vue_map.num_slots; slot++) {
-  int varying = c-key.input_vue_map.slot_to_varying[slot];
+   for (int slot = 0; slot  c-input_vue_map.num_slots; slot++) {
+  int varying = c-input_vue_map.slot_to_varying[slot];
   for (unsigned vertex = 0; vertex  num_input_vertices; vertex++) {
  attribute_map[BRW_VARYING_SLOT_COUNT * vertex + varying] =
 payload_reg + input_array_stride * vertex + slot;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h 
b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
index 90dd1de..e8da2e3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.h
@@ -37,7 +37,7 @@ struct brw_gs_prog_key
 {
struct brw_vec4_prog_key base;
 
-   struct brw_vue_map input_vue_map;
+   GLbitfield64 input_varyings;
 };
 
 
@@ -49,6 +49,7 @@ struct brw_gs_compile
struct brw_vec4_compile base;
struct brw_gs_prog_key key;
struct brw_gs_prog_data prog_data;
+   struct brw_vue_map input_vue_map;
 
struct brw_geometry_program *gp;
 

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Mesa (master): i965/vec4: Generate URB writes using a loop.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 784044c206efd774ce1f7a481311480f85446887
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=784044c206efd774ce1f7a481311480f85446887

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 12:30:06 2013 -0700

i965/vec4: Generate URB writes using a loop.

Previously we only ever did 1 or 2 URB writes, since the maximum
number of varyings we support is small enough to fit in 2 URB writes.
But GL 3.2 requires the geometry shader to support 128 output varying
components, and this could require up to 3 URB writes.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   52 ++--
 1 files changed, 21 insertions(+), 31 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 304636a..874e6e3 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2694,47 +2694,37 @@ vec4_visitor::emit_vertex()
   emit_clip_distances(output_reg[VARYING_SLOT_CLIP_DIST1], 4);
}
 
-   /* Set up the VUE data for the first URB write */
-   int slot;
-   for (slot = 0; slot  prog_data-vue_map.num_slots; ++slot) {
-  emit_urb_slot(mrf++, prog_data-vue_map.slot_to_varying[slot]);
-
-  /* If this was max_usable_mrf, we can't fit anything more into this URB
-   * WRITE.
+   /* We may need to split this up into several URB writes, so do them in a
+* loop.
+*/
+   int slot = 0;
+   bool complete = false;
+   do {
+  /* URB offset is in URB row increments, and each of our MRFs is half of
+   * one of those, since we're doing interleaved writes.
*/
-  if (mrf  max_usable_mrf) {
-slot++;
-break;
-  }
-   }
-
-   bool complete = slot = prog_data-vue_map.num_slots;
-   current_annotation = URB write;
-   vec4_instruction *inst = emit_urb_write_opcode(complete);
-   inst-base_mrf = base_mrf;
-   inst-mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf);
+  int offset = slot / 2;
 
-   /* Optional second URB write */
-   if (!complete) {
   mrf = base_mrf + 1;
-
   for (; slot  prog_data-vue_map.num_slots; ++slot) {
-assert(mrf  max_usable_mrf);
-
  emit_urb_slot(mrf++, prog_data-vue_map.slot_to_varying[slot]);
+
+ /* If this was max_usable_mrf, we can't fit anything more into this
+  * URB WRITE.
+  */
+ if (mrf  max_usable_mrf) {
+slot++;
+break;
+ }
   }
 
+  complete = slot = prog_data-vue_map.num_slots;
   current_annotation = URB write;
-  inst = emit_urb_write_opcode(true /* complete */);
+  vec4_instruction *inst = emit_urb_write_opcode(complete);
   inst-base_mrf = base_mrf;
   inst-mlen = align_interleaved_urb_mlen(brw, mrf - base_mrf);
-  /* URB destination offset.  In the previous write, we got MRFs
-   * 2-13 minus the one header MRF, so 12 regs.  URB offset is in
-   * URB row increments, and each of our MRFs is half of one of
-   * those, since we're doing interleaved writes.
-   */
-  inst-offset += (max_usable_mrf - base_mrf) / 2;
-   }
+  inst-offset += offset;
+   } while(!complete);
 }
 
 

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Mesa (master): i965/gen6+: Remove VUE map dependency on userclip_active.

[Paul Berry]

Module: Mesa
Branch: master
Commit: d1ad447f0187f5e6044fec65ace6ce1e10b156c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1ad447f0187f5e6044fec65ace6ce1e10b156c2

Author: Paul Berry stereotype...@gmail.com
Date:   Mon Sep  2 13:46:25 2013 -0700

i965/gen6+: Remove VUE map dependency on userclip_active.

Previously, on Gen6+, we laid out the vertex (or geometry) shader VUE
map differently depending whether user clipping was active.  If it was
active, we put the clip distances in slots 2 and 3 (where the clipper
expects them); if it was inactive, we assigned them in the order of
the gl_varying_slot enum.

This made for unnecessary recompiles, since turning clipping on/off
for a shader that used gl_ClipDistance might rearrange the varyings.
It also required extra bookkeeping, since it required the user
clipping flag to be provided to brw_compute_vue_map() as a parameter.

With this patch, we always put clip distances at in slots 2 and 3 if
they are written to.  do_vs_prog() and do_gs_prog() are responsible
for ensuring that clip distances are written to when user clipping is
enabled (as do_vs_prog() previously did for gen4-5).

This makes the only input to brw_compute_vue_map() a bitfield of which
varyings the shader writes to, a fact that we'll take advantage of in
forthcoming patches.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.h |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_gs.c |   15 ---
 src/mesa/drivers/dri/i965/brw_vs.c  |   26 +-
 3 files changed, 26 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 040a8d3..9d41529 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -436,7 +436,7 @@ static inline GLuint brw_varying_to_offset(struct 
brw_vue_map *vue_map,
 }
 
 void brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
- GLbitfield64 slots_valid, bool userclip_active);
+ GLbitfield64 slots_valid);
 
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs.c 
b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
index f67ae2b..2d1d163 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
@@ -94,9 +94,18 @@ do_gs_prog(struct brw_context *brw,
c.prog_data.control_data_header_size_hwords =
   ALIGN(c.control_data_header_size_bits, 256) / 256;
 
-   brw_compute_vue_map(brw, c.prog_data.base.vue_map,
-   gp-program.Base.OutputsWritten,
-   c.key.base.userclip_active);
+   GLbitfield64 outputs_written = gp-program.Base.OutputsWritten;
+
+   /* In order for legacy clipping to work, we need to populate the clip
+* distance varying slots whenever clipping is enabled, even if the vertex
+* shader doesn't write to gl_ClipDistance.
+*/
+   if (c.key.base.userclip_active) {
+  outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0);
+  outputs_written |= BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1);
+   }
+
+   brw_compute_vue_map(brw, c.prog_data.base.vue_map, outputs_written);
 
/* Compute the output vertex size.
 *
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c 
b/src/mesa/drivers/dri/i965/brw_vs.c
index 7c7493f..d5909a5 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -52,14 +52,10 @@ static inline void assign_vue_slot(struct brw_vue_map 
*vue_map,
 
 /**
  * Compute the VUE map for vertex shader program.
- *
- * Note that consumers of this map using cache keys must include
- * prog_data-userclip and prog_data-outputs_written in their key
- * (generated by CACHE_NEW_VS_PROG).
  */
 void
 brw_compute_vue_map(struct brw_context *brw, struct brw_vue_map *vue_map,
-GLbitfield64 slots_valid, bool userclip_active)
+GLbitfield64 slots_valid)
 {
vue_map-slots_valid = slots_valid;
int i;
@@ -112,10 +108,11 @@ brw_compute_vue_map(struct brw_context *brw, struct 
brw_vue_map *vue_map,
*/
   assign_vue_slot(vue_map, VARYING_SLOT_PSIZ);
   assign_vue_slot(vue_map, VARYING_SLOT_POS);
-  if (userclip_active) {
+  if (slots_valid  BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST0))
  assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST0);
+  if (slots_valid  BITFIELD64_BIT(VARYING_SLOT_CLIP_DIST1))
  assign_vue_slot(vue_map, VARYING_SLOT_CLIP_DIST1);
-  }
+
   /* front and back colors need to be consecutive so that we can use
* ATTRIBUTE_SWIZZLE_INPUTATTR_FACING to swizzle them when doing
* two-sided color.
@@ -272,15 +269,18 @@ do_vs_prog(struct brw_context *brw,
  outputs_written |= BITFIELD64_BIT(VARYING_SLOT_COL0);
   if (outputs_written  BITFIELD64_BIT(VARYING_SLOT_BFC1))
  outputs_written |= BITFIELD64_BIT(VARYING_SLOT_COL1

Mesa (master): i965/fs: When 64 input components, order them to match prev pipeline stage.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 875972029eddfd53cb90a8e34e9f27b2afed119f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=875972029eddfd53cb90a8e34e9f27b2afed119f

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 12:15:53 2013 -0700

i965/fs: When 64 input components, order them to match prev pipeline stage.

Since the SF/SBE stage is only capable of performing arbitrary
reorderings of 16 varying slots, we can't arrange the fragment shader
inputs in an arbitrary order if there are more than 16 input varying
slots in use.  We need to make sure that slots 16-31 match the
corresponding outputs of the previous pipeline stage.

The easiest way to accomplish this is to just make all varying slots
match up with the previous pipeline stage.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   49 +
 src/mesa/drivers/dri/i965/brw_wm.c   |3 +-
 2 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 004b3b5..2ebadc8 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1237,11 +1237,47 @@ fs_visitor::calculate_urb_setup()
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
if (brw-gen = 6) {
-  for (unsigned int i = 0; i  VARYING_SLOT_MAX; i++) {
-if (fp-Base.InputsRead  BRW_FS_VARYING_INPUT_MASK 
- BITFIELD64_BIT(i)) {
-   c-prog_data.urb_setup[i] = urb_next++;
-}
+  if (_mesa_bitcount_64(fp-Base.InputsRead 
+BRW_FS_VARYING_INPUT_MASK) = 16) {
+ /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
+  * first 16 varying inputs, so we can put them wherever we want.
+  * Just put them in order.
+  *
+  * This is useful because it means that (a) inputs not used by the
+  * fragment shader won't take up valuable register space, and (b) we
+  * won't have to recompile the fragment shader if it gets paired with
+  * a different vertex (or geometry) shader.
+  */
+ for (unsigned int i = 0; i  VARYING_SLOT_MAX; i++) {
+if (fp-Base.InputsRead  BRW_FS_VARYING_INPUT_MASK 
+BITFIELD64_BIT(i)) {
+   c-prog_data.urb_setup[i] = urb_next++;
+}
+ }
+  } else {
+ /* We have enough input varyings that the SF/SBE pipeline stage can't
+  * arbitrarily rearrange them to suit our whim; we have to put them
+  * in an order that matches the output of the previous pipeline stage
+  * (geometry or vertex shader).
+  */
+ struct brw_vue_map prev_stage_vue_map;
+ brw_compute_vue_map(brw, prev_stage_vue_map,
+ c-key.input_slots_valid);
+ int first_slot = 2 * BRW_SF_URB_ENTRY_READ_OFFSET;
+ assert(prev_stage_vue_map.num_slots = first_slot + 32);
+ for (int slot = first_slot; slot  prev_stage_vue_map.num_slots;
+  slot++) {
+int varying = prev_stage_vue_map.slot_to_varying[slot];
+/* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
+ * unused.
+ */
+if (varying != BRW_VARYING_SLOT_COUNT 
+(fp-Base.InputsRead  BRW_FS_VARYING_INPUT_MASK 
+ BITFIELD64_BIT(varying))) {
+   c-prog_data.urb_setup[varying] = slot - first_slot;
+}
+ }
+ urb_next = prev_stage_vue_map.num_slots - first_slot;
   }
} else {
   /* FINISHME: The sf doesn't map VS-FS inputs for us very well. */
@@ -3149,7 +3185,8 @@ brw_fs_precompile(struct gl_context *ctx, struct 
gl_shader_program *prog)
   key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
}
 
-   if (brw-gen  6)
+   if (brw-gen  6 || _mesa_bitcount_64(fp-Base.InputsRead 
+ BRW_FS_VARYING_INPUT_MASK)  16)
   key.input_slots_valid = fp-Base.InputsRead | VARYING_BIT_POS;
 
key.clamp_fragment_color = ctx-API == API_OPENGL_COMPAT;
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 1b23a4f..3d7ca2a 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -466,7 +466,8 @@ static void brw_wm_populate_key( struct brw_context *brw,
   (ctx-Multisample.SampleAlphaToCoverage || ctx-Color.AlphaEnabled);
 
/* BRW_NEW_VUE_MAP_GEOM_OUT */
-   if (brw-gen  6)
+   if (brw-gen  6 || _mesa_bitcount_64(fp-program.Base.InputsRead 
+ BRW_FS_VARYING_INPUT_MASK)  16)
   key-input_slots_valid = brw-vue_map_geom_out.slots_valid;
 
/* The unique fragment program ID */

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Mesa (master): i965/ff_gs: Generate URB writes using a loop.

[Paul Berry]

Module: Mesa
Branch: master
Commit: f5d38c58ee2a63849295cb2006c78d415af0b6ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5d38c58ee2a63849295cb2006c78d415af0b6ae

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 14:38:19 2013 -0700

i965/ff_gs: Generate URB writes using a loop.

Previously we only ever did 1 URB write, since the maximum number of
varyings we support is small enough to fit in 1 URB write (when using
BRW_URB_SWIZZLE_NONE, which is what the pre-Gen7 GS always uses).  But
we're about to increase the number of varying components we support
from 64 to 128.

With 128 varyings, the most URB writes we'll have to do is 2, but it's
just as easy to write a general-purpose loop.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_gs_emit.c |   65 +++
 1 files changed, 40 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs_emit.c 
b/src/mesa/drivers/dri/i965/brw_gs_emit.c
index 2c94eb0..9050b95 100644
--- a/src/mesa/drivers/dri/i965/brw_gs_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_gs_emit.c
@@ -169,31 +169,46 @@ static void brw_ff_gs_emit_vue(struct brw_ff_gs_compile 
*c,
bool last)
 {
struct brw_compile *p = c-func;
-   bool allocate = !last;
+   int write_offset = 0;
+   bool complete = false;
 
-   /* Copy the vertex from vertn into m1..mN+1:
-*/
-   brw_copy8(p, brw_message_reg(1), vert, c-nr_regs);
+   do {
+  /* We can't write more than 14 registers at a time to the URB */
+  int write_len = MIN2(c-nr_regs - write_offset, 14);
+  if (write_len == c-nr_regs - write_offset)
+ complete = true;
 
-   /* Send each vertex as a seperate write to the urb.  This is
-* different to the concept in brw_sf_emit.c, where subsequent
-* writes are used to build up a single urb entry.  Each of these
-* writes instantiates a seperate urb entry, and a new one must be
-* allocated each time.
-*/
-   brw_urb_WRITE(p, 
-allocate ? c-reg.temp
-  : retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
-0,
-c-reg.header,
-allocate ? BRW_URB_WRITE_ALLOCATE_COMPLETE
-  : BRW_URB_WRITE_EOT_COMPLETE,
-c-nr_regs + 1, /* msg length */
-allocate ? 1 : 0, /* response length */
-0, /* urb offset */
-BRW_URB_SWIZZLE_NONE);
-
-   if (allocate) {
+  /* Copy the vertex from vertn into m1..mN+1:
+   */
+  brw_copy8(p, brw_message_reg(1), offset(vert, write_offset), write_len);
+
+  /* Send the vertex data to the URB.  If this is the last write for this
+   * vertex, then we mark it as complete, and either end the thread or
+   * allocate another vertex URB entry (depending whether this is the last
+   * vertex).
+   */
+  enum brw_urb_write_flags flags;
+  if (!complete)
+ flags = BRW_URB_WRITE_NO_FLAGS;
+  else if (last)
+ flags = BRW_URB_WRITE_EOT_COMPLETE;
+  else
+ flags = BRW_URB_WRITE_ALLOCATE_COMPLETE;
+  brw_urb_WRITE(p,
+(flags  BRW_URB_WRITE_ALLOCATE) ? c-reg.temp
+: retype(brw_null_reg(), BRW_REGISTER_TYPE_UD),
+0,
+c-reg.header,
+flags,
+write_len + 1, /* msg length */
+(flags  BRW_URB_WRITE_ALLOCATE) ? 1
+: 0, /* response length */
+write_offset,  /* urb offset */
+BRW_URB_SWIZZLE_NONE);
+  write_offset += write_len;
+   } while (!complete);
+
+   if (!last) {
   brw_MOV(p, get_element_ud(c-reg.header, 0),
   get_element_ud(c-reg.temp, 0));
}

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Mesa (master): i965/gen6+: Support 128 varying components.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 24765c58bd7b041f92ff51ec354f5d6b0ce35daa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24765c58bd7b041f92ff51ec354f5d6b0ce35daa

Author: Paul Berry stereotype...@gmail.com
Date:   Tue Sep  3 12:37:47 2013 -0700

i965/gen6+: Support 128 varying components.

GL 3.2 requires us to support 128 varying components for geometry
shader outputs and fragment shader inputs, and 64 varying components
otherwise.  But there's no hardware limitation that restricts us to 64
varying components, and core Mesa doesn't currently allow different
stages to have different maximum values, so just go ahead and enable
128 varying components for all stages.  This gets us better test
coverage anyway.

Even though we are only working on GL 3.2 support for gen7 right now,
gen6 also supports 128 varying components, so go ahead and switch it
on there too.

Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_context.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 4fcc9fb..7b38ea3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -247,6 +247,9 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx-Const.DisableGLSLLineContinuations =
   driQueryOptionb(brw-optionCache, disable_glsl_line_continuations);
 
+   if (brw-gen = 6)
+  ctx-Const.MaxVarying = 32;
+
/* We want the GLSL compiler to emit code that uses condition codes */
for (int i = 0; i  MESA_SHADER_TYPES; i++) {
   ctx-ShaderCompilerOptions[i].MaxIfDepth = brw-gen  6 ? 16 : UINT_MAX;

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