[Mesa-dev] c99 vs v90
Hi folks, do we still need to support pre-c99 compilers or could we drop that compat stuff ? --mtx ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] i965: use mt->offset in intel_miptree_map_movntdqa().
On Tuesday, August 2, 2016 5:03:32 PM PDT Haixia Shi wrote: > We need to include mt->offset in the calculation of src pointer because its > value may be non-zero, for example in a cubemap texture. > > Signed-off-by: Haixia Shi > Cc: Jason Ekstrand > Cc: kenneth.w.grau...@intel.com > Cc: Chad Versace > > Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > index a988221..8e7c44c 100644 > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c > @@ -2462,6 +2462,9 @@ intel_miptree_map_movntdqa(struct brw_context *brw, > void *src = intel_miptree_map_raw(brw, mt); > if (!src) >return; > + > + src += mt->offset; > + > src += image_y * mt->pitch; > src += image_x * mt->cpp; Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 7/7] egl/android: Make drm_gralloc headers optional (v2)
On Wed, Aug 3, 2016 at 5:12 AM, Rob Herring wrote: > On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: >> Make the code at least compile when being built without drm_gralloc >> headers. >> >> v2: Replaced #ifdefs with stubs for gralloc_drm_get_gem_handle() >> and GRALLOC_MODULE_PERFORM_GET_DRM_FD. >> Removed explicit render node probing code. >> >> Signed-off-by: Tomasz Figa >> --- >> src/egl/Android.mk | 1 + >> src/egl/Makefile.am| 4 ++- >> src/egl/drivers/dri2/egl_dri2.h| 2 +- >> src/egl/drivers/dri2/platform_android.c| 2 +- >> .../drivers/dri2/platform_android_gralloc_drm.h| 41 >> ++ >> 5 files changed, 47 insertions(+), 3 deletions(-) >> create mode 100644 src/egl/drivers/dri2/platform_android_gralloc_drm.h >> >> diff --git a/src/egl/Android.mk b/src/egl/Android.mk >> index bfd56a7..72ec02a 100644 >> --- a/src/egl/Android.mk >> +++ b/src/egl/Android.mk >> @@ -41,6 +41,7 @@ LOCAL_SRC_FILES := \ >> LOCAL_CFLAGS := \ >> -D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_ANDROID \ >> -D_EGL_BUILT_IN_DRIVER_DRI2 \ >> + -DHAS_GRALLOC_DRM_HEADERS \ >> -DHAVE_ANDROID_PLATFORM >> >> LOCAL_C_INCLUDES := \ >> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am >> index 95ee6cc..e6ed8e6 100644 >> --- a/src/egl/Makefile.am >> +++ b/src/egl/Makefile.am >> @@ -86,7 +86,9 @@ endif >> >> if HAVE_EGL_PLATFORM_ANDROID >> AM_CFLAGS += -DHAVE_ANDROID_PLATFORM >> -dri2_backend_FILES += drivers/dri2/platform_android.c >> +dri2_backend_FILES += \ >> + drivers/dri2/platform_android.c \ >> + drivers/dri2/egl_dri2_drm_gralloc.h >> endif >> >> if HAVE_EGL_DRIVER_DRI2 >> diff --git a/src/egl/drivers/dri2/egl_dri2.h >> b/src/egl/drivers/dri2/egl_dri2.h >> index 3da6bef..14c1e05 100644 >> --- a/src/egl/drivers/dri2/egl_dri2.h >> +++ b/src/egl/drivers/dri2/egl_dri2.h >> @@ -64,8 +64,8 @@ >> # include >> #endif >> >> +#include "platform_android_gralloc_drm.h" > > This isn't needed here. > >> #include > > This should probably just be included by platform_android.c, but > that's a separate clean-up. > >> -#include >> #include > > Maybe this too? Good catch. I found this already long time ago and managed to forget in the end. I'll create a separate patch with this cleanup. > >> >> #endif /* HAVE_ANDROID_PLATFORM */ >> diff --git a/src/egl/drivers/dri2/platform_android.c >> b/src/egl/drivers/dri2/platform_android.c >> index 1768724..49a9eb0 100644 >> --- a/src/egl/drivers/dri2/platform_android.c >> +++ b/src/egl/drivers/dri2/platform_android.c >> @@ -38,7 +38,7 @@ >> #include "loader.h" >> #include "egl_dri2.h" >> #include "egl_dri2_fallbacks.h" >> -#include "gralloc_drm.h" >> +#include "platform_android_gralloc_drm.h" >> >> #define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1)) >> >> diff --git a/src/egl/drivers/dri2/platform_android_gralloc_drm.h >> b/src/egl/drivers/dri2/platform_android_gralloc_drm.h >> new file mode 100644 >> index 000..6757d1b >> --- /dev/null >> +++ b/src/egl/drivers/dri2/platform_android_gralloc_drm.h >> @@ -0,0 +1,41 @@ >> +/* >> + * Copyright 2016 Google Inc. All Rights Reserved. >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a >> + * copy of this software and associated documentation files (the >> "Software"), >> + * to deal in the Software without restriction, including without limitation >> + * the rights to use, copy, modify, merge, publish, distribute, sublicense, >> + * and/or sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice (including the next >> + * paragraph) shall be included in all copies or substantial portions of the >> + * Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF >> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER >> + * DEALINGS IN THE SOFTWARE. >> + */ >> + >> +#pragma once >> + >> +#ifdef HAS_GRALLOC_DRM_HEADERS >> + >> +#include >> +#include >> + >> +#else >> + >> +#define GRALLOC_MODULE_PERFORM_GET_DRM_FD 0x0FD4DEAD > > This leaves things a bit broken as droid_open_device can never work > with HAS_GRALLOC_DRM_HEADERS undefined. Yeah, I mostly intended to make it possible to just build the code without those headers for build testing at least. According to the discussion from my previous patch set, the private interface to gralloc was preferred, but I think this needs a bit more di
Re: [Mesa-dev] [PATCH v2 3/7] egl/android: Fix support for pbuffers (v2)
Hi Rob, On Wed, Aug 3, 2016 at 2:32 AM, Rob Herring wrote: > On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: >> From: Nicolas Boichat >> >> Existing image loader code supports creating images only for window >> surfaces. Moreover droid_create_surface() passes wrong surface type to >> dri2_get_dri_config(), resulting in incorrect configs being returned for >> pbuffers. This patch fixes these issues. >> >> In addition, the config generation code is fixed to include single >> buffered contexts required for pbuffers and make sure that generated >> configs support only surfaces which can handle their supported buffering >> modes. >> >> v2: Return error only in case of real error condition and ignore requests >> of unavailable buffers. >> Improve coding style. > > This still breaks Android for me. Just adding the hunks below is > enough to break things. It results in get_buffers() being called with > type == EGL_WINDOW_BIT and buffer_mask == __DRI_IMAGE_BUFFER_FRONT. I > don't see any requests for the front buffer without this change. I've > looked through the tree, but don't really see what would cause > buffer_mask to change. Thanks for testing again and sorry to hear that it still doesn't work correctly. It looks like somehow a single buffered config ends up being used for a window surface with your driver. Could you give me some instructions how to set up some environment for testing to reproduce the issue? Best regards, Tomasz ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] non-shared glapi still needed ?
Hi folks, is there still a real need for having non-shared glapi ? Otherwise, should we remove it ? --mtx ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 25/95] i965/vec4: fix base offset for nir_registers with doubles
Iago Toral Quiroga writes:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 8 +---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index cf35f2e..fde7b60 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -280,7 +280,8 @@ vec4_visitor::get_nir_dest(const nir_dest &dest)
>nir_ssa_values[dest.ssa.index] = dst;
>return dst;
> } else {
> - return dst_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
> + unsigned base_offset = dest.reg.base_offset * dest.reg.reg->bit_size /
> 32;
> + return dst_reg_for_nir_reg(this, dest.reg.reg, base_offset,
> dest.reg.indirect);
> }
> }
> @@ -308,8 +309,9 @@ vec4_visitor::get_nir_src(const nir_src &src, enum
> brw_reg_type type,
>reg = nir_ssa_values[src.ssa->index];
> }
> else {
> - reg = dst_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
> - src.reg.indirect);
> + unsigned base_offset = src.reg.base_offset * src.reg.reg->bit_size /
> 32;
> + reg = dst_reg_for_nir_reg(this, src.reg.reg, base_offset,
> +src.reg.indirect);
I think this wouldn't have been necessary if you had fixed the offset()
helper to take into account the register type (as it does in the FS
back-end)?
> }
>
> reg = retype(reg, type);
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] nir: Always print non-identity swizzles.
Seems reasonable to be too. Rb if you'd like On Aug 2, 2016 8:25 PM, "Timothy Arceri" wrote: > Reviewed-by: Timothy Arceri > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 33/95] i965/vec4: implement d2b
Iago Toral Quiroga writes:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 18 ++
> 1 file changed, 18 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 1525a3d..4014020 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -1497,6 +1497,24 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>emit(CMP(dst, op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ));
>break;
>
> + case nir_op_d2b: {
> + /* two-argument instructions can't take 64-bit immediates */
> + dst_reg zero = dst_reg(this, glsl_type::dvec4_type);
> + emit(MOV(zero, brw_imm_df(0.0)));
> +
> + dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
> + emit(CMP(tmp, op[0], src_reg(zero), BRW_CONDITIONAL_NZ));
> +
> + /* Convert the double CMP result to a single boolean result. For that
> + * we take the low 32-bit chunk of each DF component in the result.
> + * and do a final MOV to honor the original writemask
> + */
> + dst_reg result = dst_reg(this, glsl_type::bvec4_type);
> + emit(VEC4_OPCODE_PICK_LOW_32BIT, result, src_reg(tmp));
> + emit(MOV(dst, src_reg(result)));
Couldn't you just do a single CMP instruction of the double-precision
argument and a single-precision 0.0 immediate? I think you could
potentially also use a 32bit destination type on the CMP instruction so
you don't need to emit the PICK_LOW+MOV instructions afterwards. It may
hit an instruction decompression bug but it could be cleaned up by the
SIMD lowering pass afterwards, AFAICT the result would be two
uncompressed instructions instead of the two uncompressed plus two
compressed instructions above.
> + break;
> + }
> +
> case nir_op_i2b:
>emit(CMP(dst, op[0], brw_imm_d(0), BRW_CONDITIONAL_NZ));
>break;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] nir: Always print non-identity swizzles.
Reviewed-by: Timothy Arceri ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 28/95] i965/vec4: fix register allocation for 64-bit undef sources
Iago Toral Quiroga writes:
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 7b8e30d..65fa057 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -2009,7 +2009,8 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
> void
> vec4_visitor::nir_emit_undef(nir_ssa_undef_instr *instr)
> {
> - nir_ssa_values[instr->def.index] = dst_reg(VGRF, alloc.allocate(1));
> + nir_ssa_values[instr->def.index] =
> + dst_reg(VGRF, alloc.allocate(instr->def.bit_size / 32));
I think you want to use DIV_ROUND_UP here instead, with that fixed:
Reviewed-by: Francisco Jerez
> }
>
> }
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 09/95] i965/vec4: add support for printing DF immediates
Iago Toral Quiroga writes: > From: Connor Abbott > Reviewed-by: Francisco Jerez > --- > src/mesa/drivers/dri/i965/brw_vec4.cpp | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp > b/src/mesa/drivers/dri/i965/brw_vec4.cpp > index 162b481..bf6701e 100644 > --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp > +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp > @@ -1485,6 +1485,9 @@ vec4_visitor::dump_instruction(backend_instruction > *be_inst, FILE *file) > case BRW_REGISTER_TYPE_F: > fprintf(file, "%fF", inst->src[i].f); > break; > + case BRW_REGISTER_TYPE_DF: > +fprintf(file, "%fDF", inst->src[i].df); > +break; > case BRW_REGISTER_TYPE_D: > fprintf(file, "%dD", inst->src[i].d); > break; > -- > 2.7.4 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 13/95] i965: add brw_vecn_grf()
Iago Toral Quiroga writes:
> From: Connor Abbott
>
Reviewed-by: Francisco Jerez
> ---
> src/mesa/drivers/dri/i965/brw_reg.h | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
> b/src/mesa/drivers/dri/i965/brw_reg.h
> index 38cf8e3..e4c3e7a 100644
> --- a/src/mesa/drivers/dri/i965/brw_reg.h
> +++ b/src/mesa/drivers/dri/i965/brw_reg.h
> @@ -716,6 +716,12 @@ brw_vec16_grf(unsigned nr, unsigned subnr)
> return brw_vec16_reg(BRW_GENERAL_REGISTER_FILE, nr, subnr);
> }
>
> +static inline struct brw_reg
> +brw_vecn_grf(unsigned width, unsigned nr, unsigned subnr)
> +{
> + return brw_vecn_reg(width, BRW_GENERAL_REGISTER_FILE, nr, subnr);
> +}
> +
>
> static inline struct brw_reg
> brw_uw8_grf(unsigned nr, unsigned subnr)
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 16/95] i965/vec4: We only support 32-bit integer ALU operations for now
Iago Toral Quiroga writes:
> Add asserts so we remember to address this when we enable 64-bit
> integer support, as suggested by Connor and Jason.
Reviewed-by: Francisco Jerez
> ---
> src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 70
> ++
> 1 file changed, 52 insertions(+), 18 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> index 1d33fb2..25fd1fe 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
> @@ -1083,9 +1083,9 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
> }
>
> - case nir_op_fadd:
> - /* fall through */
> case nir_op_iadd:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fadd:
>inst = emit(ADD(dst, op[0], op[1]));
>inst->saturate = instr->dest.saturate;
>break;
> @@ -1096,6 +1096,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
>
> case nir_op_imul: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>if (devinfo->gen < 8) {
> nir_const_value *value0 = nir_src_as_const_value(instr->src[0].src);
> nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
> @@ -1131,6 +1132,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>
> case nir_op_imul_high:
> case nir_op_umul_high: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>struct brw_reg acc = retype(brw_acc_reg(8), dst.type);
>
>if (devinfo->gen >= 8)
> @@ -1169,6 +1171,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>
> case nir_op_idiv:
> case nir_op_udiv:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>emit_math(SHADER_OPCODE_INT_QUOTIENT, dst, op[0], op[1]);
>break;
>
> @@ -1178,6 +1181,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> * appears that our hardware just does the right thing for signed
> * remainder.
> */
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>emit_math(SHADER_OPCODE_INT_REMAINDER, dst, op[0], op[1]);
>break;
>
> @@ -1231,6 +1235,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
>
> case nir_op_uadd_carry: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
>
>emit(ADDC(dst_null_ud(), op[0], op[1]));
> @@ -1239,6 +1244,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> }
>
> case nir_op_usub_borrow: {
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
>struct brw_reg acc = retype(brw_acc_reg(8), BRW_REGISTER_TYPE_UD);
>
>emit(SUBB(dst_null_ud(), op[0], op[1]));
> @@ -1306,16 +1312,18 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
> }
>
> - case nir_op_fmin:
> case nir_op_imin:
> case nir_op_umin:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fmin:
>inst = emit_minmax(BRW_CONDITIONAL_L, dst, op[0], op[1]);
>inst->saturate = instr->dest.saturate;
>break;
>
> - case nir_op_fmax:
> case nir_op_imax:
> case nir_op_umax:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + case nir_op_fmax:
>inst = emit_minmax(BRW_CONDITIONAL_GE, dst, op[0], op[1]);
>inst->saturate = instr->dest.saturate;
>break;
> @@ -1328,26 +1336,30 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
> case nir_op_fddy_fine:
>unreachable("derivatives are not valid in vertex shaders");
>
> - case nir_op_flt:
> case nir_op_ilt:
> case nir_op_ult:
> - case nir_op_fge:
> case nir_op_ige:
> case nir_op_uge:
> - case nir_op_feq:
> case nir_op_ieq:
> - case nir_op_fne:
> case nir_op_ine:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + /* Fallthrough */
> + case nir_op_flt:
> + case nir_op_fge:
> + case nir_op_feq:
> + case nir_op_fne:
>emit(CMP(dst, op[0], op[1],
> brw_conditional_for_nir_comparison(instr->op)));
>break;
>
> - case nir_op_ball_fequal2:
> case nir_op_ball_iequal2:
> - case nir_op_ball_fequal3:
> case nir_op_ball_iequal3:
> - case nir_op_ball_fequal4:
> - case nir_op_ball_iequal4: {
> + case nir_op_ball_iequal4:
> + assert(nir_dest_bit_size(instr->dest.dest) < 64);
> + /* Fallthrough */
> + case nir_op_ball_fequal2:
> + case nir_op_ball_fequal3:
> + case nir_op_ball_fequal4: {
>unsigned swiz =
> brw_swizzle_for_size(nir_op_infos[instr->op].input_sizes[0]);
>
> @@ -1359,12 +1371,14 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
>break;
> }
>
> - case nir_op_bany_fnequal2:
> case nir_op_bany_inequal2:
> - case nir_op_bany_fnequal3:
> case nir_op_bany_inequal3:
> - case nir_op_bany_fnequal4:
Re: [Mesa-dev] [PATCH 15/95] i965/disasm: align16 DF source regions have a width of 2
Reviewed-by: Francisco Jerez Iago Toral Quiroga writes: > --- > src/mesa/drivers/dri/i965/brw_disasm.c | 5 - > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c > b/src/mesa/drivers/dri/i965/brw_disasm.c > index d74d5d5..c8bdeab 100644 > --- a/src/mesa/drivers/dri/i965/brw_disasm.c > +++ b/src/mesa/drivers/dri/i965/brw_disasm.c > @@ -918,7 +918,10 @@ src_da16(FILE *file, >format(file, ".%d", 16 / reg_type_size[_reg_type]); > string(file, "<"); > err |= control(file, "vert stride", vert_stride, _vert_stride, NULL); > - string(file, ",4,1>"); > + if (reg_type_size[_reg_type] == 8) > + string(file, ",2,1>"); > + else > + string(file, ",4,1>"); > err |= src_swizzle(file, BRW_SWIZZLE4(swz_x, swz_y, swz_z, swz_w)); > err |= control(file, "src da16 reg type", reg_encoding, _reg_type, NULL); > return err; > -- > 2.7.4 > > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 17/95] i965/vec4: add dst_null_df()
Reviewed-by: Francisco Jerez
Iago Toral Quiroga writes:
> ---
> src/mesa/drivers/dri/i965/brw_vec4.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
> b/src/mesa/drivers/dri/i965/brw_vec4.h
> index 3043147..afcf31e 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.h
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.h
> @@ -79,6 +79,11 @@ public:
>return dst_reg(brw_null_reg());
> }
>
> + dst_reg dst_null_df()
> + {
> + return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_DF));
> + }
> +
> dst_reg dst_null_d()
> {
>return dst_reg(retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 0/3] Destroy Present event contexts
On 02.08.2016 23:01, Leo Liu wrote: > On 08/01/2016 10:20 PM, Michel Dänzer wrote: >> On 28.07.2016 18:34, Michel Dänzer wrote: >>> Running XTS (the X test suite) on Xephyr using glamor running on Xorg, >>> I stumbled upon an issue: >>> >>> * XTS causes Xephyr to keep resetting and starting new server >>> generations >>> * glamor creates a new GLX context for each server generation but >>> re-uses >>>the same window >>> >>> This caused Xorg to accumulate stale Present event contexts from >>> previous >>> GLX contexts, so it kept getting slower due to sending out an increasing >>> number of copies of the same Present events to Xephyr. >>> >>> The first patch fixes this problem, and the other two patches apply the >>> same principle to the other places using Present event contexts. >>> >>> Note that destroying a Present event context doesn't actually work >>> without this xserver fix: >>> >>> https://patchwork.freedesktop.org/patch/101430/ >> v2 of that fix has landed in xserver master. >> >> >>> But these changes shouldn't make things any worse than they already >>> are with X servers lacking that fix. >>> >>> [PATCH 1/3] loader/dri3: Destroy Present event context when >>> [PATCH 2/3] vl/dri3: Destroy Present event context when destroying >>> [PATCH 3/3] anv/x11: Destroy Present event context when destroying >> Any comments on the v2 patches? Unless there are any objections, I'm >> going to push v2 of patches 1 & 2 later this week. I'm not going to push >> patch 3 myself without getting at least a Tested-by: from somebody. > > Patch 2 is: > Tested and Reviewed by: Leo Liu Thank you, Leo. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: add missing x swizzle in nir_print()
On Tue, Aug 2, 2016 at 5:28 PM, Timothy Arceri wrote: > Currently we only print the swizzle if the components are not > used in order. This means x is not printed when it is the only > component used. By checking if the last component is used we > can print the swizzle for this case. I agree. I've found this really annoying. I sent a patch "[PATCH] nir: Always print non-identity swizzles." in September of last year after my first attempt to fix it was met with resistance. Unfortunately no one, even those who complained about v1, replied. Perhaps I silence is agreement and I should have just pushed it. What do you think of that patch? Regardless, I definitely want to see this fixed this time. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nir: add missing x swizzle in nir_print()
Currently we only print the swizzle if the components are not
used in order. This means x is not printed when it is the only
component used. By checking if the last component is used we
can print the swizzle for this case.
---
src/compiler/nir/nir_print.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index 8987526..8bc99bc 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -185,9 +185,17 @@ print_alu_src(nir_alu_instr *instr, unsigned src,
print_state *state)
bool print_swizzle = false;
for (unsigned i = 0; i < 4; i++) {
- if (!nir_alu_instr_channel_used(instr, src, i))
+ if (!nir_alu_instr_channel_used(instr, src, i)) {
+ /* If the last component is not use print the swizzle */
+ if (instr->src[src].src.ssa &&
+ instr->src[src].src.ssa->num_components == i + 1) {
+print_swizzle = true;
+break;
+ }
continue;
+ }
+ /* If components are not used in order then print swizzle */
if (instr->src[src].swizzle[i] != i) {
print_swizzle = true;
break;
--
2.7.4
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Re: [Mesa-dev] [PATCH v2] i965: use mt->offset in intel_miptree_map_movntdqa().
On 08/02/2016 05:03 PM, Haixia Shi wrote: We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi Cc: Jason Ekstrand Cc: kenneth.w.grau...@intel.com Cc: Chad Versace Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a988221..8e7c44c 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2462,6 +2462,9 @@ intel_miptree_map_movntdqa(struct brw_context *brw, void *src = intel_miptree_map_raw(brw, mt); if (!src) return; + + src += mt->offset; + src += image_y * mt->pitch; src += image_x * mt->cpp; Ok. That looks better. For real this time, Reviewed-by: Chad Versace ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] i965: use mt->offset in intel_miptree_map_movntdqa().
We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi Cc: Jason Ekstrand Cc: kenneth.w.grau...@intel.com Cc: Chad Versace Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a988221..8e7c44c 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2462,6 +2462,9 @@ intel_miptree_map_movntdqa(struct brw_context *brw, void *src = intel_miptree_map_raw(brw, mt); if (!src) return; + + src += mt->offset; + src += image_y * mt->pitch; src += image_x * mt->cpp; -- 2.8.0.rc3.226.g39d4020 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: use mt->offset in intel_miptree_map_movntdqa().
On 08/02/2016 04:35 PM, Chad Versace wrote: On 08/02/2016 04:17 PM, Haixia Shi wrote: We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi Cc: Jason Ekstrand Cc: kenneth.w.grau...@intel.com Cc: Chad Versace Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a988221..a3d921f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2459,7 +2459,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, image_x += map->x; image_y += map->y; - void *src = intel_miptree_map_raw(brw, mt); + void *src = intel_miptree_map_raw(brw, mt) + mt->offset; if (!src) return; src += image_y * mt->pitch; Reviewed-by: Chad Versace I'll wait for others to voice any opposition before committing. Oops. I retract my r-b. There's actually a small bug in the patch. The test for !src needs to occur before adding the mt->offset. Otherwise, the test may pass with a false positive. Fix the bug, and I'll add my r-b back. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: use mt->offset in intel_miptree_map_movntdqa().
On 08/02/2016 04:17 PM, Haixia Shi wrote: We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi Cc: Jason Ekstrand Cc: kenneth.w.grau...@intel.com Cc: Chad Versace Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a988221..a3d921f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2459,7 +2459,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, image_x += map->x; image_y += map->y; - void *src = intel_miptree_map_raw(brw, mt); + void *src = intel_miptree_map_raw(brw, mt) + mt->offset; if (!src) return; src += image_y * mt->pitch; Reviewed-by: Chad Versace I'll wait for others to voice any opposition before committing. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/3] RadeonSI GLSL "lit" tests
On Tue, Aug 2, 2016 at 9:23 PM, Nicolai Hähnle wrote: > > > On 02.08.2016 21:06, Marek Olšák wrote: >> >> On Tue, Aug 2, 2016 at 3:40 PM, Nicolai Hähnle wrote: >>> >>> On 31.07.2016 22:29, Marek Olšák wrote: Inspired by LLVM, I created a small test suite that looks like "lit" tests, except that the input is GLSL and it verifies asm. The motivation was to verify that we generate optimal code when starting from GLSL. [PATCH 1/3] radeonsi: add environment variable SI_FORCE_FAMILY [PATCH 2/3] radeonsi: add a standalone compiler amdgcn_glslc [PATCH 3/3] radeonsi: add GLSL lit tests >>> >>> >>> >>> Good idea. Two comments: >>> >>> Please use .glsl or some such instead of .ll as a file extension. Those >>> files are not LLVM IR. >>> >>> There's a `make check` in Mesa, which I readily admit to not using >>> enough. >>> There are r300_compiler_tests that are hooked up to it. Perhaps it's >>> worth >>> wiring that up? >> >> >> Some of the tests currently fail and will continue to fail for quite >> some time. I don't think people would appreciate it if "make check" >> always failed. > > > llvm-lit has an "expected failures" mode which could be used. It works by > adding a line > > ; XFAIL: * > > to the test. "expected failures" doesn't say whether the failures are good or bad. I've always understood "expected failures" as "failing is the correct behavior here". Also, I guess people would be very unhappy that their make check failures can only be fixed by building LLVM from source, or worse (better?), by writing patches for LLVM. ;) Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965: use mt->offset in intel_miptree_map_movntdqa().
We need to include mt->offset in the calculation of src pointer because its value may be non-zero, for example in a cubemap texture. Signed-off-by: Haixia Shi Cc: Jason Ekstrand Cc: kenneth.w.grau...@intel.com Cc: Chad Versace Change-Id: I461ad5b204626d5a1c45611fc6b63735dcf29f63 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a988221..a3d921f 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -2459,7 +2459,7 @@ intel_miptree_map_movntdqa(struct brw_context *brw, image_x += map->x; image_y += map->y; - void *src = intel_miptree_map_raw(brw, mt); + void *src = intel_miptree_map_raw(brw, mt) + mt->offset; if (!src) return; src += image_y * mt->pitch; -- 2.8.0.rc3.226.g39d4020 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 4/7] egl/android: Refactor image creation to separate flink and prime paths (v2)
On 08/02/2016 04:07 AM, Tomasz Figa wrote: This patch splits current dri2_create_image_android_native_buffer() into main entry point and two additional functions, one for creating an image from flink name and one for handling prime FDs using the generic DMA-buf path. This makes the code cleaner and also prepares for disabling flink path more easily in the future. v2: Split into separate patch. Add error messages. Signed-off-by: Tomasz Figa --- src/egl/drivers/dri2/platform_android.c | 99 +++-- 1 file changed, 57 insertions(+), 42 deletions(-) Reviewed-by: Chad Versace ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 2/7] egl/android: Respect buffer mask in droid_image_get_buffers (v2)
On 08/02/2016 04:07 AM, Tomasz Figa wrote: Drivers can request different set of buffers depending on the buffer mask they pass to the get_buffers callback. This patch makes droid_image_get_buffers() respect this mask. v2: Return error only in case of real error condition and ignore requests of unavailable buffers. Signed-off-by: Tomasz Figa --- src/egl/drivers/dri2/platform_android.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) Reviewed-by: Chad Versace ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/7] radeonsi: program multi draw and indirect draw count parameters
Bas pointed out some things that mean this patch (and the next) probably
need to be reworked. The tests were probably not thorough enough.
Nicolai
On 02.08.2016 21:41, Nicolai Hähnle wrote:
From: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_state_draw.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index a918f85..46dd5c7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -643,17 +643,30 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 -
SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, di_src_sel);
} else {
+ uint64_t count_va = 0;
+
+ if (info->indirect_params) {
+ struct r600_resource *params_buf =
+ (struct r600_resource
*)info->indirect_params;
+
+ radeon_add_to_buffer_list(
+ &sctx->b, &sctx->b.gfx, params_buf,
+ RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
+
+ count_va = params_buf->gpu_address +
info->indirect_params_offset;
+ }
+
radeon_emit(cs, PKT3(info->indexed ?
PKT3_DRAW_INDEX_INDIRECT_MULTI :
PKT3_DRAW_INDIRECT_MULTI,
8, render_cond_bit));
radeon_emit(cs, info->indirect_offset);
radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 -
SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 -
SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, 0); /* draw_index */
- radeon_emit(cs, 1); /* count */
- radeon_emit(cs, 0); /* count_addr -- disabled */
- radeon_emit(cs, 0);
- radeon_emit(cs, 16); /* stride */
+ radeon_emit(cs, info->drawid);
+ radeon_emit(cs, info->indirect_count);
+ radeon_emit(cs, count_va);
+ radeon_emit(cs, count_va >> 32);
+ radeon_emit(cs, info->indirect_stride);
radeon_emit(cs, di_src_sel);
}
} else {
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Re: [Mesa-dev] [PATCH v2 1/7] egl/android: Remove unused variables in droid_get_buffers_with_format()
On 08/02/2016 04:07 AM, Tomasz Figa wrote: Fix compilation warnings due to unused variables left after some earlier code changes. Signed-off-by: Tomasz Figa --- src/egl/drivers/dri2/platform_android.c | 3 --- 1 file changed, 3 deletions(-) Reviewed-by: Chad Versace ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 7/7] egl/android: Make drm_gralloc headers optional (v2)
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote:
> Make the code at least compile when being built without drm_gralloc
> headers.
>
> v2: Replaced #ifdefs with stubs for gralloc_drm_get_gem_handle()
> and GRALLOC_MODULE_PERFORM_GET_DRM_FD.
> Removed explicit render node probing code.
>
> Signed-off-by: Tomasz Figa
> ---
> src/egl/Android.mk | 1 +
> src/egl/Makefile.am| 4 ++-
> src/egl/drivers/dri2/egl_dri2.h| 2 +-
> src/egl/drivers/dri2/platform_android.c| 2 +-
> .../drivers/dri2/platform_android_gralloc_drm.h| 41
> ++
> 5 files changed, 47 insertions(+), 3 deletions(-)
> create mode 100644 src/egl/drivers/dri2/platform_android_gralloc_drm.h
>
> diff --git a/src/egl/Android.mk b/src/egl/Android.mk
> index bfd56a7..72ec02a 100644
> --- a/src/egl/Android.mk
> +++ b/src/egl/Android.mk
> @@ -41,6 +41,7 @@ LOCAL_SRC_FILES := \
> LOCAL_CFLAGS := \
> -D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_ANDROID \
> -D_EGL_BUILT_IN_DRIVER_DRI2 \
> + -DHAS_GRALLOC_DRM_HEADERS \
> -DHAVE_ANDROID_PLATFORM
>
> LOCAL_C_INCLUDES := \
> diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
> index 95ee6cc..e6ed8e6 100644
> --- a/src/egl/Makefile.am
> +++ b/src/egl/Makefile.am
> @@ -86,7 +86,9 @@ endif
>
> if HAVE_EGL_PLATFORM_ANDROID
> AM_CFLAGS += -DHAVE_ANDROID_PLATFORM
> -dri2_backend_FILES += drivers/dri2/platform_android.c
> +dri2_backend_FILES += \
> + drivers/dri2/platform_android.c \
> + drivers/dri2/egl_dri2_drm_gralloc.h
> endif
>
> if HAVE_EGL_DRIVER_DRI2
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 3da6bef..14c1e05 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -64,8 +64,8 @@
> # include
> #endif
>
> +#include "platform_android_gralloc_drm.h"
This isn't needed here.
> #include
This should probably just be included by platform_android.c, but
that's a separate clean-up.
> -#include
> #include
Maybe this too?
>
> #endif /* HAVE_ANDROID_PLATFORM */
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index 1768724..49a9eb0 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -38,7 +38,7 @@
> #include "loader.h"
> #include "egl_dri2.h"
> #include "egl_dri2_fallbacks.h"
> -#include "gralloc_drm.h"
> +#include "platform_android_gralloc_drm.h"
>
> #define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1))
>
> diff --git a/src/egl/drivers/dri2/platform_android_gralloc_drm.h
> b/src/egl/drivers/dri2/platform_android_gralloc_drm.h
> new file mode 100644
> index 000..6757d1b
> --- /dev/null
> +++ b/src/egl/drivers/dri2/platform_android_gralloc_drm.h
> @@ -0,0 +1,41 @@
> +/*
> + * Copyright 2016 Google Inc. All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#pragma once
> +
> +#ifdef HAS_GRALLOC_DRM_HEADERS
> +
> +#include
> +#include
> +
> +#else
> +
> +#define GRALLOC_MODULE_PERFORM_GET_DRM_FD 0x0FD4DEAD
This leaves things a bit broken as droid_open_device can never work
with HAS_GRALLOC_DRM_HEADERS undefined. As we're both aligned in using
the render nodes, I'd like to be able to use the same fix. Since with
render nodes, it doesn't have to be the same fd now, the following
works for me:
droid_open_device(void)
{
#ifdef HAS_GRALLOC_DRM_HEADERS
// existing code
#else
return loader_open_device("/dev/dri/renderD128");
#endif
}
I can provide that patch, but just want to throw it out there for
context. We probably want to get the device path from a property or
something rather than hardcoding.
> +
> +static inline int gralloc_drm_get_gem_handle(buffer_handle_t handle)
> +{
> + r
[Mesa-dev] [PATCH 5/7] radeonsi: add has_draw_indirect_multi flag
From: Nicolai Hähnle
Prefer to use DRAW_(INDEX)_INDIRECT_MULTI when available in the firmware.
Versions for SI and CI already added as provided by the firmware team, but
keep in mind that they won't currently be used since the radeon kernel module
has no interface to query the firmware version.
---
src/gallium/drivers/radeonsi/si_pipe.c | 12
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 9304e5c..d2965050 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -754,6 +754,18 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws)
sscreen->b.chip_class >= VI &&
sscreen->b.info.max_se >= 2;
+ sscreen->has_draw_indirect_multi =
+ (sscreen->b.family >= CHIP_POLARIS10) ||
+ (sscreen->b.chip_class == VI &&
+sscreen->b.info.pfp_fw_version >= 121 &&
+sscreen->b.info.me_fw_version >= 87) ||
+ (sscreen->b.chip_class == CIK &&
+sscreen->b.info.pfp_fw_version >= 211 &&
+sscreen->b.info.me_fw_version >= 173) ||
+ (sscreen->b.chip_class == SI &&
+sscreen->b.info.pfp_fw_version >= 121 &&
+sscreen->b.info.me_fw_version >= 87);
+
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
pipe_mutex_init(sscreen->shader_parts_mutex);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 326b819..bb570bb 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -85,6 +85,7 @@ struct si_screen {
unsignedgs_table_depth;
unsignedtess_offchip_block_dw_size;
boolhas_distributed_tess;
+ boolhas_draw_indirect_multi;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
booluse_monolithic_shaders;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 54fe2bb..a918f85 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -634,7 +634,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, index_max_size);
}
- if (sctx->b.family < CHIP_POLARIS10) {
+ if (!sctx->screen->has_draw_indirect_multi) {
radeon_emit(cs, PKT3(info->indexed ?
PKT3_DRAW_INDEX_INDIRECT
: PKT3_DRAW_INDIRECT,
3, render_cond_bit));
--
2.7.4
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[Mesa-dev] [PATCH 7/7] radeonsi: enable MULTI_DRAW_INDIRECT_(PARAMS) pipe caps
From: Nicolai Hähnle This enables GL_ARB_indirect_parameters as well as a properly accelerated implementation of GL_ARB_multi_draw_indirect. Enabling the feature requires a sufficiently uptodate firmware -- those have already been released a long time ago, although this does mean that the feature only works with the amdgpu kernel module, since the radeon module doesn't have a way to query the firmware version. --- docs/GL3.txt | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 6 -- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index c185c69..8c7cd9d 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -283,7 +283,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve GL_ARB_ES3_2_compatibilitynot started GL_ARB_fragment_shader_interlock not started GL_ARB_gpu_shader_int64 started (airlied for core and Gallium, idr for i965) - GL_ARB_indirect_parametersDONE (nvc0) + GL_ARB_indirect_parametersDONE (nvc0, radeonsi) GL_ARB_parallel_shader_compilenot started, but Chia-I Wu did some related work in 2014 GL_ARB_pipeline_statistics_query DONE (i965, nvc0, radeonsi, softpipe, swr) GL_ARB_post_depth_coveragenot started diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index d2965050..0b56cd2 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -437,8 +437,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_VERTEXID_NOBASE: case PIPE_CAP_CLEAR_TEXTURE: case PIPE_CAP_DRAW_PARAMETERS: - case PIPE_CAP_MULTI_DRAW_INDIRECT: - case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_QUERY_BUFFER_OBJECT: case PIPE_CAP_CULL_DISTANCE: case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: @@ -446,6 +444,10 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_WINDOW_RECTANGLES: return 0; + case PIPE_CAP_MULTI_DRAW_INDIRECT: + case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: + return sscreen->has_draw_indirect_multi; + case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: return 30; -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/7] radeonsi: unify emitting PKT3_SET_BASE for indirect draws
From: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_state_draw.c | 25 +
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 24fa682..afb9bbf 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -591,8 +591,17 @@ static void si_emit_draw_packets(struct si_context *sctx,
sctx->last_sh_base_reg = sh_base_reg;
}
} else {
+ uint64_t indirect_va =
r600_resource(info->indirect)->gpu_address;
+
+ assert(indirect_va % 8 == 0);
+
si_invalidate_draw_sh_constants(sctx);
+ radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
+ radeon_emit(cs, 1);
+ radeon_emit(cs, indirect_va);
+ radeon_emit(cs, indirect_va >> 32);
+
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
(struct r600_resource *)info->indirect,
RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
@@ -608,17 +617,9 @@ static void si_emit_draw_packets(struct si_context *sctx,
RADEON_USAGE_READ,
RADEON_PRIO_INDEX_BUFFER);
if (info->indirect) {
- uint64_t indirect_va =
r600_resource(info->indirect)->gpu_address;
-
- assert(indirect_va % 8 == 0);
assert(index_va % 2 == 0);
assert(info->indirect_offset % 4 == 0);
- radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
- radeon_emit(cs, 1);
- radeon_emit(cs, indirect_va);
- radeon_emit(cs, indirect_va >> 32);
-
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
radeon_emit(cs, index_va);
radeon_emit(cs, index_va >> 32);
@@ -656,16 +657,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
}
} else {
if (info->indirect) {
- uint64_t indirect_va =
r600_resource(info->indirect)->gpu_address;
-
- assert(indirect_va % 8 == 0);
assert(info->indirect_offset % 4 == 0);
- radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
- radeon_emit(cs, 1);
- radeon_emit(cs, indirect_va);
- radeon_emit(cs, indirect_va >> 32);
-
if (sctx->b.family < CHIP_POLARIS10) {
radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3,
render_cond_bit));
radeon_emit(cs, info->indirect_offset);
--
2.7.4
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Re: [Mesa-dev] [PATCH v2 6/7] egl/android: Add support for YV12 pixel format (v2)
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: > This patch adds support for YV12 pixel format to the Android platform > backend. Only creating EGL images is supported, it is not added to the > list of available visuals. > > v2: Use const array defined just for YV12 instead of trying to be overly > generic. > > Signed-off-by: Tomasz Figa > Signed-off-by: Kalyan Kondapally I didn't exercise this path, but it didn't break anything, so: Tested-by: Rob Herring ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 5/7] egl/android: Make get_fourcc() accept HAL formats
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: > There are DRI_IMAGE_FOURCC macros, for which there are no corresponding > DRI_IMAGE_FORMAT macros. To support such formats we need to make the > lookup function take the native format directly. As a side effect, it > simplifies all existing calls to this function, because they all called > get_format() first to convert from native to DRI_IMAGE_FORMAT. > > Signed-off-by: Tomasz Figa Tested-by: Rob Herring ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 4/7] egl/android: Refactor image creation to separate flink and prime paths (v2)
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: > This patch splits current dri2_create_image_android_native_buffer() into > main entry point and two additional functions, one for creating an image > from flink name and one for handling prime FDs using the generic DMA-buf > path. This makes the code cleaner and also prepares for disabling flink > path more easily in the future. > > v2: Split into separate patch. > Add error messages. > > Signed-off-by: Tomasz Figa Tested-by: Rob Herring ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 2/7] egl/android: Respect buffer mask in droid_image_get_buffers (v2)
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: > Drivers can request different set of buffers depending on the buffer > mask they pass to the get_buffers callback. This patch makes > droid_image_get_buffers() respect this mask. > > v2: Return error only in case of real error condition and ignore requests > of unavailable buffers. > > Signed-off-by: Tomasz Figa Tested-by: Rob Herring ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 1/7] egl/android: Remove unused variables in droid_get_buffers_with_format()
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote: > Fix compilation warnings due to unused variables left after some earlier > code changes. > > Signed-off-by: Tomasz Figa Tested-by: Rob Herring ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/7] winsys/amdgpu: query ME/PFP/CE firmware versions
From: Nicolai Hähnle
The radeon kernel module doesn't have the firmware query interface, so the
corresponding values will remain 0.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 3 +++
src/gallium/drivers/radeon/radeon_winsys.h| 3 +++
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 22 ++
3 files changed, 28 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index caf2552..edaa0cf 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1108,6 +1108,9 @@ bool r600_common_screen_init(struct r600_common_screen
*rscreen,
printf("gfx_ib_pad_with_type2 = %i\n",
rscreen->info.gfx_ib_pad_with_type2);
printf("has_sdma = %i\n", rscreen->info.has_sdma);
printf("has_uvd = %i\n", rscreen->info.has_uvd);
+ printf("me_fw_version = %i\n", rscreen->info.me_fw_version);
+ printf("pfp_fw_version = %i\n", rscreen->info.pfp_fw_version);
+ printf("ce_fw_version = %i\n", rscreen->info.ce_fw_version);
printf("vce_fw_version = %i\n", rscreen->info.vce_fw_version);
printf("vce_harvest_config = %i\n",
rscreen->info.vce_harvest_config);
printf("clock_crystal_freq = %i\n",
rscreen->info.clock_crystal_freq);
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index ba56936..50dd92a 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -260,6 +260,9 @@ struct radeon_info {
boolhas_uvd;
uint32_tuvd_fw_version;
uint32_tvce_fw_version;
+uint32_tme_fw_version;
+uint32_tpfp_fw_version;
+uint32_tce_fw_version;
uint32_tvce_harvest_config;
uint32_tclock_crystal_freq;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 9a04cbe..1f24fcd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -99,6 +99,7 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int fd)
struct amdgpu_heap_info vram, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
+ uint32_t unused_feature;
int r, i, j;
drmDevicePtr devinfo;
@@ -151,6 +152,27 @@ static bool do_winsys_init(struct amdgpu_winsys *ws, int
fd)
goto fail;
}
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_ME, 0, 0,
+&ws->info.me_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
+ goto fail;
+ }
+
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0,
+&ws->info.pfp_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
+ goto fail;
+ }
+
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_GFX_CE, 0, 0,
+&ws->info.ce_fw_version, &unused_feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
+ goto fail;
+ }
+
r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_UVD, 0, 0,
&uvd_version, &uvd_feature);
if (r) {
--
2.7.4
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[Mesa-dev] [PATCH 4/7] radeonsi: transpose indirect/index draw dispatch
From: Nicolai Hähnle
This allows better code sharing for indirect draw calls.
---
src/gallium/drivers/radeonsi/si_state_draw.c | 76
1 file changed, 31 insertions(+), 45 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 6b8ab9f..54fe2bb 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -619,36 +619,45 @@ static void si_emit_draw_packets(struct si_context *sctx,
RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
}
- if (info->indexed) {
- if (info->indirect) {
- assert(info->indirect_offset % 4 == 0);
+ if (info->indirect) {
+ unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
+ :
V_0287F0_DI_SRC_SEL_AUTO_INDEX;
+
+ assert(info->indirect_offset % 4 == 0);
+ if (info->indexed) {
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
radeon_emit(cs, index_va);
radeon_emit(cs, index_va >> 32);
radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
radeon_emit(cs, index_max_size);
+ }
- if (sctx->b.family < CHIP_POLARIS10) {
- radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT,
3, render_cond_bit));
- radeon_emit(cs, info->indirect_offset);
- radeon_emit(cs, (sh_base_reg +
SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, (sh_base_reg +
SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
- } else {
- radeon_emit(cs,
PKT3(PKT3_DRAW_INDEX_INDIRECT_MULTI, 8, render_cond_bit));
- radeon_emit(cs, info->indirect_offset);
- radeon_emit(cs, (sh_base_reg +
SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, (sh_base_reg +
SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, 0); /* draw_index */
- radeon_emit(cs, 1); /* count */
- radeon_emit(cs, 0); /* count_addr -- disabled */
- radeon_emit(cs, 0);
- radeon_emit(cs, 16); /* stride */
- radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
- }
+ if (sctx->b.family < CHIP_POLARIS10) {
+ radeon_emit(cs, PKT3(info->indexed ?
PKT3_DRAW_INDEX_INDIRECT
+ : PKT3_DRAW_INDIRECT,
+3, render_cond_bit));
+ radeon_emit(cs, info->indirect_offset);
+ radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4
- SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE *
4 - SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, di_src_sel);
} else {
+ radeon_emit(cs, PKT3(info->indexed ?
PKT3_DRAW_INDEX_INDIRECT_MULTI :
+
PKT3_DRAW_INDIRECT_MULTI,
+8, render_cond_bit));
+ radeon_emit(cs, info->indirect_offset);
+ radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4
- SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE *
4 - SI_SH_REG_OFFSET) >> 2);
+ radeon_emit(cs, 0); /* draw_index */
+ radeon_emit(cs, 1); /* count */
+ radeon_emit(cs, 0); /* count_addr -- disabled */
+ radeon_emit(cs, 0);
+ radeon_emit(cs, 16); /* stride */
+ radeon_emit(cs, di_src_sel);
+ }
+ } else {
+ if (info->indexed) {
index_va += info->start * ib->index_size;
radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4,
render_cond_bit));
@@ -657,34 +666,11 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, (index_va >> 32UL) & 0xFF);
radeon_emit(cs, info->count);
radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
- }
- } else {
- if (info->indirect) {
- assert(info->indirect_offset % 4 == 0);
-
- if (s
[Mesa-dev] [PATCH 3/7] radeonsi: move index buffer calculations in si_emit_draw_packets up
From: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_state_draw.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index afb9bbf..6b8ab9f 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -520,6 +520,8 @@ static void si_emit_draw_packets(struct si_context *sctx,
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned sh_base_reg =
sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
bool render_cond_bit = sctx->b.render_cond &&
!sctx->b.render_cond_force_off;
+ uint32_t index_max_size = 0;
+ uint64_t index_va = 0;
if (info->count_from_stream_output) {
struct r600_so_target *t =
@@ -567,6 +569,16 @@ static void si_emit_draw_packets(struct si_context *sctx,
assert(!"unreachable");
return;
}
+
+ index_max_size = (ib->buffer->width0 - ib->offset) /
+ ib->index_size;
+ index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
+
+ assert(index_va % 2 == 0);
+
+ radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
+ (struct r600_resource *)ib->buffer,
+ RADEON_USAGE_READ,
RADEON_PRIO_INDEX_BUFFER);
}
if (!info->indirect) {
@@ -608,16 +620,7 @@ static void si_emit_draw_packets(struct si_context *sctx,
}
if (info->indexed) {
- uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
- ib->index_size;
- uint64_t index_va = r600_resource(ib->buffer)->gpu_address +
ib->offset;
-
- radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
- (struct r600_resource *)ib->buffer,
- RADEON_USAGE_READ,
RADEON_PRIO_INDEX_BUFFER);
-
if (info->indirect) {
- assert(index_va % 2 == 0);
assert(info->indirect_offset % 4 == 0);
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
--
2.7.4
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[Mesa-dev] [PATCH 6/7] radeonsi: program multi draw and indirect draw count parameters
From: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_state_draw.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index a918f85..46dd5c7 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -643,17 +643,30 @@ static void si_emit_draw_packets(struct si_context *sctx,
radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE *
4 - SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, di_src_sel);
} else {
+ uint64_t count_va = 0;
+
+ if (info->indirect_params) {
+ struct r600_resource *params_buf =
+ (struct r600_resource
*)info->indirect_params;
+
+ radeon_add_to_buffer_list(
+ &sctx->b, &sctx->b.gfx, params_buf,
+ RADEON_USAGE_READ,
RADEON_PRIO_DRAW_INDIRECT);
+
+ count_va = params_buf->gpu_address +
info->indirect_params_offset;
+ }
+
radeon_emit(cs, PKT3(info->indexed ?
PKT3_DRAW_INDEX_INDIRECT_MULTI :
PKT3_DRAW_INDIRECT_MULTI,
8, render_cond_bit));
radeon_emit(cs, info->indirect_offset);
radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4
- SI_SH_REG_OFFSET) >> 2);
radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE *
4 - SI_SH_REG_OFFSET) >> 2);
- radeon_emit(cs, 0); /* draw_index */
- radeon_emit(cs, 1); /* count */
- radeon_emit(cs, 0); /* count_addr -- disabled */
- radeon_emit(cs, 0);
- radeon_emit(cs, 16); /* stride */
+ radeon_emit(cs, info->drawid);
+ radeon_emit(cs, info->indirect_count);
+ radeon_emit(cs, count_va);
+ radeon_emit(cs, count_va >> 32);
+ radeon_emit(cs, info->indirect_stride);
radeon_emit(cs, di_src_sel);
}
} else {
--
2.7.4
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Re: [Mesa-dev] [PATCH v2] swr: build swr with -fno-strict-aliasing
Thanks! Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/3] RadeonSI GLSL "lit" tests
On 02.08.2016 21:06, Marek Olšák wrote: On Tue, Aug 2, 2016 at 3:40 PM, Nicolai Hähnle wrote: On 31.07.2016 22:29, Marek Olšák wrote: Inspired by LLVM, I created a small test suite that looks like "lit" tests, except that the input is GLSL and it verifies asm. The motivation was to verify that we generate optimal code when starting from GLSL. [PATCH 1/3] radeonsi: add environment variable SI_FORCE_FAMILY [PATCH 2/3] radeonsi: add a standalone compiler amdgcn_glslc [PATCH 3/3] radeonsi: add GLSL lit tests Good idea. Two comments: Please use .glsl or some such instead of .ll as a file extension. Those files are not LLVM IR. There's a `make check` in Mesa, which I readily admit to not using enough. There are r300_compiler_tests that are hooked up to it. Perhaps it's worth wiring that up? Some of the tests currently fail and will continue to fail for quite some time. I don't think people would appreciate it if "make check" always failed. llvm-lit has an "expected failures" mode which could be used. It works by adding a line ; XFAIL: * to the test. Nicolai Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 0/3] RadeonSI GLSL "lit" tests
On Tue, Aug 2, 2016 at 3:40 PM, Nicolai Hähnle wrote: > On 31.07.2016 22:29, Marek Olšák wrote: >> >> Inspired by LLVM, I created a small test suite that looks like "lit" >> tests, except that the input is GLSL and it verifies asm. >> >> The motivation was to verify that we generate optimal code when starting >> from GLSL. >> >> [PATCH 1/3] radeonsi: add environment variable SI_FORCE_FAMILY >> [PATCH 2/3] radeonsi: add a standalone compiler amdgcn_glslc >> [PATCH 3/3] radeonsi: add GLSL lit tests > > > Good idea. Two comments: > > Please use .glsl or some such instead of .ll as a file extension. Those > files are not LLVM IR. > > There's a `make check` in Mesa, which I readily admit to not using enough. > There are r300_compiler_tests that are hooked up to it. Perhaps it's worth > wiring that up? Some of the tests currently fail and will continue to fail for quite some time. I don't think people would appreciate it if "make check" always failed. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] swr: build swr with -fno-strict-aliasing
swr rasterizer contains numerous data transfers between vectors and ordinary C types. Fixing for strict aliasing will take time. --- src/gallium/drivers/swr/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/swr/Makefile.am b/src/gallium/drivers/swr/Makefile.am index 3459af3..33664d6 100644 --- a/src/gallium/drivers/swr/Makefile.am +++ b/src/gallium/drivers/swr/Makefile.am @@ -29,6 +29,7 @@ noinst_LTLIBRARIES = libmesaswr.la libmesaswr_la_SOURCES = $(LOADER_SOURCES) COMMON_CXXFLAGS = \ + -fno-strict-aliasing \ $(GALLIUM_DRIVER_CFLAGS) \ $(LLVM_CXXFLAGS) \ $(SWR_CXX11_CXXFLAGS) \ -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/12] RadeonSI: Prevent IB submissions with illegal memory usage
On Tue, Aug 2, 2016 at 5:15 PM, Nicolai Hähnle wrote: > On 29.07.2016 23:42, Marek Olšák wrote: >> >> This series ensures that memory usage of gfx IBs is below the kernel- >> exposed memory limits in most cases. >> >> It's not possible to prevent CS ioctl failures completely because it >> depends on whether continuous free space for all buffers is available, >> i.e. it depends on where some system buffers are pinned, rather than >> how much total free space you have. >> >> Piglit max-texture-size and tex3d-maxsize tests easily pass with this. >> >> There are also some cleanups. > > > Reading through the series, I believe that the individual patches are fine > (other than some bike-shedding perhaps), but it may be time to change the CS > submission approach into more of a transaction-with-commit/rollback one. > This is mostly because the whole dance around > r600_context_add_resource_size, radeon_add_to_buffer_list and > radeon_add_to_buffer_list_check_mem just feels very fragile. > > Basically, radeon_winsys_cs would have a "committed" pointer into the IB in > addition to the "current" pointer. Similarly, the buffer list would have a > "committed" index. Winsys callbacks cs_commit and cs_rollback would do the > obvious thing of moving the committed pointers to current or the other way > around. (On second thought, it's probably only the buffer list that needs > "committed" pointers.) > > Then, the buffer handling in the driver code would be simplified as follows: > > - As long as the CS already contains some committed draw/DMA call, > radeon_add_to_buffer_list always checks whether the memory size is exceeded. > If so, it calls cs_rollback, flushes, and returns a corresponding code. > > - There is no need to distinguish radeon_add_to_buffer_list and > radeon_add_to_buffer_list_check_mem anymore, since all additions are checked > if and only if there really is something to flush. > > - There is no more need for r600_context_add_resource_size. Instead, all > draw/DMA-related buffers (vertex & index buffers, indirect data, DMA > buffers) are added via radeon_add_to_buffer_list just before the call to > si_need_cs_space. If radeon_add_to_buffer_list indicates that a flush > happened, the sequence is repeated. > > - After each draw call, cs_commit is called. > > Another, tangentially related issue: we really shouldn't add buffers tied to > descriptors in the *_begin_new_cs and even the set_* functions; instead, it > should ideally happen at si_upload_descriptors time. Otherwise, we may end > up adding buffers to a CS that aren't needed anymore. Yeah, I agree it's fragile. On the other hand, moving more stuff into draw_vbo sounds like it would increase CPU overhead. The radeon winsys can roll back the buffer list with cs_validate. r300_emit_buffer_validate is an easy-to-read example showing how it works. It's pretty solid and never goes above the memory limits. We didn't use that approach for r600 because r600 can use a lot more buffers and tracking all of them can take a lot of CPU time. For example, r300 is limited to only 1 active query per draw call, but later hardware is unlimited. Initially, the solution was "don't check memory usage", because IB submissions almost never fail with real apps, but eventually r600_context_add_resource_size was added as a quick hack to help with low-memory cards and some synthetic tests. I'm sceptical that we can have something more robust and not regress performance, but maybe you are onto something that I'm not able to see. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Rework the unlit centroid workaround.
On Aug 2, 2016 12:36 PM, "Matt Turner" wrote: > > On Mon, Aug 1, 2016 at 8:59 PM, Kenneth Graunke wrote: > > Previously, for every input, we moved the dispatch mask to the flag > > register, then emitted two predicated PLN instructions, one with > > centroid barycentric coordinates (for normal pixels), and one with > > pixel barycentric coordinates (for unlit helper pixels). > > > > Instead, we can simply emit a set of predicated MOVs at the top of > > the program which copy the pixel barycentric coordinates over the > > centroid ones for unlit helper pixel channels. Then, we can just > > use normal PLNs. I like this approach *much* better than what we did before. Reviewed-by: Jason Ekstrand > > On Sandybridge: > > > > total instructions in shared programs: 7538470 -> 7534500 (-0.05%) > > instructions in affected programs: 101268 -> 97298 (-3.92%) > > helped: 705 > > HURT: 9 (all of which are SIMD16 programs) > > Reviewed-by: Matt Turner > > Maybe wait a few days before pushing so we can confirm that my patch > indeed doesn't cause any regressions on Gen7. They're pretty much orthogonal so I'm not too worried about that but sure. --Jason ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] configure.ac/swr: build swr with -fno-strict-aliasing
> On Aug 2, 2016, at 1:00 PM, Matt Turner wrote: > > On Tue, Aug 2, 2016 at 10:53 AM, Tim Rowley > wrote: >> swr rasterizer contains numerous data transfers between vectors >> and ordinary C types. Fixing for strict aliasing will take time. > > Oh, sorry! I forgot about swr. > >> --- >> configure.ac| 7 +++ >> src/gallium/drivers/swr/Makefile.am | 1 + >> 2 files changed, 8 insertions(+) >> >> diff --git a/configure.ac b/configure.ac >> index aea5890..fb4a12a 100644 >> --- a/configure.ac >> +++ b/configure.ac >> @@ -312,6 +312,8 @@ if test "x$GCC" = xyes; then >> MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith" >> MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith" >> >> +NO_STRICT_ALIASING_CFLAGS="-fno-strict-aliasing" >> + >> # Enable -Werror=vla if compiler supports it >> save_CFLAGS="$CFLAGS" >> AC_MSG_CHECKING([whether $CC supports -Werror=vla]) >> @@ -341,11 +343,16 @@ if test "x$GXX" = xyes; then >> >> # We don't want floating-point math functions to set errno or trap >> CXXFLAGS="$CXXFLAGS -fno-math-errno -fno-trapping-math" >> + >> +NO_STRICT_ALIASING_CXXFLAGS="-fno-strict-aliasing" >> fi >> >> AC_SUBST([MSVC2013_COMPAT_CFLAGS]) >> AC_SUBST([MSVC2013_COMPAT_CXXFLAGS]) >> >> +AC_SUBST([NO_STRICT_ALIASING_CFLAGS]) >> +AC_SUBST([NO_STRICT_ALIASING_CXXFLAGS]) >> + >> dnl even if the compiler appears to support it, using visibility attributes >> isn't >> dnl going to do anything useful currently on cygwin apart from emit lots of >> warnings >> case "$host_os" in >> diff --git a/src/gallium/drivers/swr/Makefile.am >> b/src/gallium/drivers/swr/Makefile.am >> index 3459af3..fa02349 100644 >> --- a/src/gallium/drivers/swr/Makefile.am >> +++ b/src/gallium/drivers/swr/Makefile.am >> @@ -29,6 +29,7 @@ noinst_LTLIBRARIES = libmesaswr.la >> libmesaswr_la_SOURCES = $(LOADER_SOURCES) >> >> COMMON_CXXFLAGS = \ >> + $(NO_STRICT_ALIASING_CXXFLAGS) \ > > I think you should just put -fno-strict-aliasing here instead. I don't > think the variable and substitutions in configure.ac add anything. My thinking behind using substitution was to handle non-gcc compilers, though both icc and clang seem to pass configure.ac’s gcc check and silently accept -fno-strict-aliasing. I’ll send another patch with just the swr makefile change. -Tim ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] configure.ac/swr: build swr with -fno-strict-aliasing
On Tue, Aug 2, 2016 at 10:53 AM, Tim Rowley wrote: > swr rasterizer contains numerous data transfers between vectors > and ordinary C types. Fixing for strict aliasing will take time. Oh, sorry! I forgot about swr. > --- > configure.ac| 7 +++ > src/gallium/drivers/swr/Makefile.am | 1 + > 2 files changed, 8 insertions(+) > > diff --git a/configure.ac b/configure.ac > index aea5890..fb4a12a 100644 > --- a/configure.ac > +++ b/configure.ac > @@ -312,6 +312,8 @@ if test "x$GCC" = xyes; then > MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith" > MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith" > > +NO_STRICT_ALIASING_CFLAGS="-fno-strict-aliasing" > + > # Enable -Werror=vla if compiler supports it > save_CFLAGS="$CFLAGS" > AC_MSG_CHECKING([whether $CC supports -Werror=vla]) > @@ -341,11 +343,16 @@ if test "x$GXX" = xyes; then > > # We don't want floating-point math functions to set errno or trap > CXXFLAGS="$CXXFLAGS -fno-math-errno -fno-trapping-math" > + > +NO_STRICT_ALIASING_CXXFLAGS="-fno-strict-aliasing" > fi > > AC_SUBST([MSVC2013_COMPAT_CFLAGS]) > AC_SUBST([MSVC2013_COMPAT_CXXFLAGS]) > > +AC_SUBST([NO_STRICT_ALIASING_CFLAGS]) > +AC_SUBST([NO_STRICT_ALIASING_CXXFLAGS]) > + > dnl even if the compiler appears to support it, using visibility attributes > isn't > dnl going to do anything useful currently on cygwin apart from emit lots of > warnings > case "$host_os" in > diff --git a/src/gallium/drivers/swr/Makefile.am > b/src/gallium/drivers/swr/Makefile.am > index 3459af3..fa02349 100644 > --- a/src/gallium/drivers/swr/Makefile.am > +++ b/src/gallium/drivers/swr/Makefile.am > @@ -29,6 +29,7 @@ noinst_LTLIBRARIES = libmesaswr.la > libmesaswr_la_SOURCES = $(LOADER_SOURCES) > > COMMON_CXXFLAGS = \ > + $(NO_STRICT_ALIASING_CXXFLAGS) \ I think you should just put -fno-strict-aliasing here instead. I don't think the variable and substitutions in configure.ac add anything. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 09/21] i965/fs: Rework representation of fragment output locations in NIR.
On Sunday, July 31, 2016 12:22:40 PM PDT Francisco Jerez wrote: > Kenneth Graunke writes: > > > On Friday, July 22, 2016 8:59:03 PM PDT Francisco Jerez wrote: > >> The problem with the current approach is that driver output locations > >> are represented as a linear offset within the nir_outputs array, which > >> makes it rather difficult for the back-end to figure out what color > >> output and index some nir_intrinsic_load/store_output was meant for, > >> because the offset of a given output within the nir_output array is > >> dependent on the type and size of all previously allocated outputs. > >> Instead this defines the driver location of an output to be the pair > >> formed by its GLSL-assigned location and index (I've borrowed the > >> bitfield macros from brw_defines.h in order to represent the pair of > >> integers as a single scalar value that can be assigned to > >> nir_variable_data::driver_location). nir_assign_var_locations is no > >> longer useful for fragment outputs. > >> > >> Because fragment outputs are now allocated independently rather than > >> within the nir_outputs array, the get_frag_output() helper becomes > >> necessary in order to obtain the right temporary register for a given > >> location-index pair. > >> > >> The type_size helper passed to nir_lower_io is now type_size_dvec4 > >> rather than type_size_vec4_times_4 so that output array offsets are > >> provided in terms of whole array elements rather than in terms of > >> scalar components (dvec4 is the largest vector type supported by the > >> GLSL so this will cause all individual fragment outputs to have a size > >> of one regardless of the type). > > > > I don't think you should need type_size_dvec4 - double-precision > > fragment shader outputs don't exist. GL_ARB_gpu_shader_fp64 says: > > > > (3) Should double-precision fragment shader outputs be supported? > > > > RESOLVED: Not in this extension. Note that we don't have > > double-precision framebuffer formats to accept such values. > > > > Why not just use type_size_vec4? With that changed, this patch would > > get my Reviewed-by. > > > > Yeah, I'm aware of that restriction (c.f. PATCH 7), but the point here > was to get output offsets counted in whole array elements regardless of > the type, type_size_dvec4 is strictly better for that purpose than > type_size_vec4, because dvec4 is the largest GLSL vector type, and they > are otherwise equivalent when used on types smaller than a dvec4. A > type_size_vectors helper may make sense instead though. Ah. I was concerned about the inconsistency in this patch - you use type_size_dvec4 for lowering, but allocate the registers with type_size_vec4_times_4, which both count doubles differently. It works because there are no doubles, of course, but it seemed like using type_size_vec4 for both would be more consistent. Then again, in the next patch, you drop the type_size_vec4_times_4 call in favor of allocating VGRFs of size 4 directly. I think I see what you mean, though. I'd always thought about FRAG_RESULT_DATA* as vec4-based. But it's not, exactly...array indexes correspond to render target indexes...so we want each array element to be 1. We could use a type size function that counts 1 per array element, and ignores structs completely. But that's basically what type_size_dvec4 does, and it already exists. I suppose in the presence of theoretical double outputs, we'd still want to count by 1. We'd just want to allocate registers of size 8 if the intrinsic's source's bit size is 64 instead of 32. You win :) Reviewed-by: Kenneth Graunke signature.asc Description: This is a digitally signed message part. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] configure.ac: add llvm inteljitevents component if enabled
Needed to successfully link llvmpipe or swr when using shared llvm libs.
---
configure.ac | 5 +
1 file changed, 5 insertions(+)
diff --git a/configure.ac b/configure.ac
index fb4a12a..edbc95b 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2497,6 +2497,11 @@ dnl in LLVM_LIBS.
if test "x$MESA_LLVM" != x0; then
+if test "x$HAVE_GALLIUM_LLVMPIPE" = xyes || "x$HAVE_GALLIUM_SWR" = xyes &&
\
+$LLVM_CONFIG --components | grep -q inteljitevents ; then
+ LLVM_COMPONENTS="${LLVM_COMPONENTS} inteljitevents"
+fi
+
if ! $LLVM_CONFIG --libs ${LLVM_COMPONENTS} >/dev/null; then
AC_MSG_ERROR([Calling ${LLVM_CONFIG} failed])
fi
--
2.7.4
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[Mesa-dev] [PATCH] configure.ac/swr: build swr with -fno-strict-aliasing
swr rasterizer contains numerous data transfers between vectors and ordinary C types. Fixing for strict aliasing will take time. --- configure.ac| 7 +++ src/gallium/drivers/swr/Makefile.am | 1 + 2 files changed, 8 insertions(+) diff --git a/configure.ac b/configure.ac index aea5890..fb4a12a 100644 --- a/configure.ac +++ b/configure.ac @@ -312,6 +312,8 @@ if test "x$GCC" = xyes; then MSVC2013_COMPAT_CFLAGS="-Werror=pointer-arith" MSVC2013_COMPAT_CXXFLAGS="-Werror=pointer-arith" +NO_STRICT_ALIASING_CFLAGS="-fno-strict-aliasing" + # Enable -Werror=vla if compiler supports it save_CFLAGS="$CFLAGS" AC_MSG_CHECKING([whether $CC supports -Werror=vla]) @@ -341,11 +343,16 @@ if test "x$GXX" = xyes; then # We don't want floating-point math functions to set errno or trap CXXFLAGS="$CXXFLAGS -fno-math-errno -fno-trapping-math" + +NO_STRICT_ALIASING_CXXFLAGS="-fno-strict-aliasing" fi AC_SUBST([MSVC2013_COMPAT_CFLAGS]) AC_SUBST([MSVC2013_COMPAT_CXXFLAGS]) +AC_SUBST([NO_STRICT_ALIASING_CFLAGS]) +AC_SUBST([NO_STRICT_ALIASING_CXXFLAGS]) + dnl even if the compiler appears to support it, using visibility attributes isn't dnl going to do anything useful currently on cygwin apart from emit lots of warnings case "$host_os" in diff --git a/src/gallium/drivers/swr/Makefile.am b/src/gallium/drivers/swr/Makefile.am index 3459af3..fa02349 100644 --- a/src/gallium/drivers/swr/Makefile.am +++ b/src/gallium/drivers/swr/Makefile.am @@ -29,6 +29,7 @@ noinst_LTLIBRARIES = libmesaswr.la libmesaswr_la_SOURCES = $(LOADER_SOURCES) COMMON_CXXFLAGS = \ + $(NO_STRICT_ALIASING_CXXFLAGS) \ $(GALLIUM_DRIVER_CFLAGS) \ $(LLVM_CXXFLAGS) \ $(SWR_CXX11_CXXFLAGS) \ -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Rework the unlit centroid workaround.
On Mon, Aug 1, 2016 at 8:59 PM, Kenneth Graunke wrote: > Previously, for every input, we moved the dispatch mask to the flag > register, then emitted two predicated PLN instructions, one with > centroid barycentric coordinates (for normal pixels), and one with > pixel barycentric coordinates (for unlit helper pixels). > > Instead, we can simply emit a set of predicated MOVs at the top of > the program which copy the pixel barycentric coordinates over the > centroid ones for unlit helper pixel channels. Then, we can just > use normal PLNs. > > On Sandybridge: > > total instructions in shared programs: 7538470 -> 7534500 (-0.05%) > instructions in affected programs: 101268 -> 97298 (-3.92%) > helped: 705 > HURT: 9 (all of which are SIMD16 programs) Reviewed-by: Matt Turner Maybe wait a few days before pushing so we can confirm that my patch indeed doesn't cause any regressions on Gen7. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 3/7] egl/android: Fix support for pbuffers (v2)
On Tue, Aug 2, 2016 at 6:07 AM, Tomasz Figa wrote:
> From: Nicolas Boichat
>
> Existing image loader code supports creating images only for window
> surfaces. Moreover droid_create_surface() passes wrong surface type to
> dri2_get_dri_config(), resulting in incorrect configs being returned for
> pbuffers. This patch fixes these issues.
>
> In addition, the config generation code is fixed to include single
> buffered contexts required for pbuffers and make sure that generated
> configs support only surfaces which can handle their supported buffering
> modes.
>
> v2: Return error only in case of real error condition and ignore requests
> of unavailable buffers.
> Improve coding style.
This still breaks Android for me. Just adding the hunks below is
enough to break things. It results in get_buffers() being called with
type == EGL_WINDOW_BIT and buffer_mask == __DRI_IMAGE_BUFFER_FRONT. I
don't see any requests for the front buffer without this change. I've
looked through the tree, but don't really see what would cause
buffer_mask to change.
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 4577875..3da6bef 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -291,6 +291,7 @@ struct dri2_egl_surface
> struct ANativeWindow *window;
> struct ANativeWindowBuffer *buffer;
> __DRIimage *dri_image;
> + __DRIimage *dri_front_image;
>
> /* EGL-owned buffers */
> __DRIbuffer *local_buffers[__DRI_BUFFER_COUNT];
> diff --git a/src/egl/drivers/dri2/platform_android.c
> b/src/egl/drivers/dri2/platform_android.c
> index d78c06d..420436c 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -286,7 +286,7 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp,
> EGLint type,
>window->query(window, NATIVE_WINDOW_HEIGHT, &dri2_surf->base.Height);
> }
>
> - config = dri2_get_dri_config(dri2_conf, EGL_WINDOW_BIT,
> + config = dri2_get_dri_config(dri2_conf, type,
> dri2_surf->base.GLColorspace);
> if (!config)
>goto cleanup_surface;
> @@ -347,6 +347,9 @@ droid_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp,
> _EGLSurface *surf)
>dri2_surf->window->common.decRef(&dri2_surf->window->common);
> }
>
> + if (dri2_surf->dri_front_image)
> + dri2_dpy->image->destroyImage(dri2_surf->dri_front_image);
> +
> (*dri2_dpy->core->destroyDrawable)(dri2_surf->dri_drawable);
>
> free(dri2_surf);
> @@ -696,14 +725,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv,
> _EGLDisplay *dpy)
>for (j = 0; dri2_dpy->driver_configs[j]; j++) {
> const EGLint surface_type = EGL_WINDOW_BIT | EGL_PBUFFER_BIT;
> struct dri2_egl_config *dri2_conf;
> - unsigned int double_buffered = 0;
> -
> - dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[j],
> -__DRI_ATTRIB_DOUBLE_BUFFER, &double_buffered);
> -
> - /* support only double buffered configs */
> - if (!double_buffered)
> -continue;
>
> dri2_conf = dri2_add_config(dpy, dri2_dpy->driver_configs[j],
> count + 1, surface_type, config_attrs, visuals[i].rgba_masks);
> @@ -726,6 +747,19 @@ droid_add_configs_for_visuals(_EGLDriver *drv,
> _EGLDisplay *dpy)
>/* there is no front buffer so no OpenGL */
>dri2_conf->base.RenderableType &= ~EGL_OPENGL_BIT;
>dri2_conf->base.Conformant &= ~EGL_OPENGL_BIT;
> +
> + for (j = 0; j < 2; j++) {
> + /* Unsupported color space variants should not affect surface type.
> */
> + if (!dri2_conf->dri_single_config[j] &&
> !dri2_conf->dri_double_config[j])
> +continue;
> +
> + /* Pbuffers support only single buffering. */
> + if (!dri2_conf->dri_single_config[j])
> +dri2_conf->base.SurfaceType &= ~EGL_PBUFFER_BIT;
> + /* Windows support only double buffering. */
> + if (!dri2_conf->dri_double_config[j])
> +dri2_conf->base.SurfaceType &= ~EGL_WINDOW_BIT;
> + }
> }
>
> return (count != 0);
> --
> 2.8.0.rc3.226.g39d4020
>
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Re: [Mesa-dev] [PATCH 12/12] gallium/radeon/winsyses: decrease max_alloc_size to 1/3 of largest heap
Am 02.08.2016 um 14:57 schrieb Alex Deucher: On Tue, Aug 2, 2016 at 4:55 AM, Marek Olšák wrote: On Tue, Aug 2, 2016 at 3:13 AM, Michel Dänzer wrote: On 01.08.2016 16:35, Michel Dänzer wrote: On 30.07.2016 06:42, Marek Olšák wrote: From: Marek Olšák This is controversial, but I don't see a better way out of this. Tonga has 2 GB of VRAM and 2 GB of GTT. amdgpu is not capable of submitting an IB referencing 1 GB of VRAM and 1 GB of GTT. The CS ioctl never succeeds even though it's far below the limits. Without this, "dEQP-GLES2.functional.color_clear.single_rgb" fails to submit an IB. With this, dEQP throws a framebuffer-incomplete exception and kills the process. IMO, failing the CS ioctl is worse for stability than failing big allocations. I can agree with that, but this change can't reliably prevent CS ioctl failures: I believe the problem is mostly due to BOs which are pinned for scanout. Since up to 6 CRTCs can scan out different buffers at any time, in the worst case it may not be possible to place any BOs whose size is >= ~1/7 of the VRAM size. At the end of the day, this needs to be solved in the kernel one way or another. Or if you do want to avoid the problem in userspace for now, maybe use 1 / (number of CRTCs + 1) instead of hardcoding 1/3? I don't know. I could avoid the problem by splitting buffers into 128MB blocks mapped into GPUVM consecutively, but that would prevent easy DMABUF sharing and CPU mappings would not be consecutive. I think it could be fixed to a certain extent by handling migrations to/from vram iteratively rather than trying to move the whole buffer at once. E.g., we may have enough room in vram, but not enough contiguous gtt aperture or system pages to map the whole buffer to do the transfer in one shot. Additional to that paging VRAM should help a lot with that as well. Anyway I have both VRAM paging and splitting moves on my TODO list. Good to know that I can use "dEQP-GLES2.functional.color_clear.single_rgb" as a test case. Regards, Christian. Alex ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] anv/blit2d: Add support for RGB destinations
This fixes 104 of the new image_clearing and copy_and_blit Vulkan CTS
tests.
Signed-off-by: Jason Ekstrand
Cc: "12.0"
---
src/intel/vulkan/anv_meta_blit2d.c | 210 -
1 file changed, 208 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_meta_blit2d.c
b/src/intel/vulkan/anv_meta_blit2d.c
index 30bc6ed..cb3548b 100644
--- a/src/intel/vulkan/anv_meta_blit2d.c
+++ b/src/intel/vulkan/anv_meta_blit2d.c
@@ -92,6 +92,21 @@ vk_format_for_size(int bs)
}
}
+/* This function returns the format corresponding to a single component of the
+ * RGB format for the given size returned by vk_format_for_size().
+ */
+static VkFormat
+vk_single_component_format_for_rgb_size(int bs)
+{
+ switch (bs) {
+ case 3: return VK_FORMAT_R8_UNORM;
+ case 6: return VK_FORMAT_R16_UNORM;
+ case 12: return VK_FORMAT_R32_UINT;
+ default:
+ unreachable("Invalid format block size");
+ }
+}
+
static void
create_iview(struct anv_cmd_buffer *cmd_buffer,
struct anv_meta_blit2d_surf *surf,
@@ -663,6 +678,141 @@ anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer
*cmd_buffer,
}
}
+static void
+anv_meta_blit2d_rgb_dst(struct anv_cmd_buffer *cmd_buffer,
+struct anv_meta_blit2d_surf *src,
+enum blit2d_src_type src_type,
+struct anv_meta_blit2d_surf *dst,
+unsigned num_rects,
+struct anv_meta_blit2d_rect *rects)
+{
+ struct anv_device *device = cmd_buffer->device;
+
+ for (unsigned r = 0; r < num_rects; ++r) {
+ struct blit2d_src_temps src_temps;
+ blit2d_bind_src(cmd_buffer, src, src_type, &rects[r], &src_temps);
+
+ assert(dst->bs % 3 == 0);
+ assert(dst->tiling == ISL_TILING_LINEAR);
+
+ uint32_t offset;
+ isl_tiling_get_intratile_offset_el(&cmd_buffer->device->isl_dev,
+ dst->tiling, 1, dst->pitch,
+ rects[r].dst_x, rects[r].dst_y,
+ &offset,
+ &rects[r].dst_x, &rects[r].dst_y);
+
+ /* A red surface three times as wide as the actual RGB destination */
+ struct anv_meta_blit2d_surf dst_R = {
+ .bo = dst->bo,
+ .tiling = dst->tiling,
+ .base_offset = dst->base_offset,
+ .bs = dst->bs / 3,
+ .pitch = dst->pitch,
+ };
+
+ struct blit2d_dst_temps dst_temps;
+ blit2d_bind_dst(cmd_buffer, &dst_R, offset,
+ (rects[r].dst_x + rects[r].width) * 3,
+ rects[r].dst_y + rects[r].height,
+ vk_single_component_format_for_rgb_size(dst->bs),
+ &dst_temps);
+
+ struct blit_vb_data {
+ float pos[2];
+ float tex_coord[3];
+ } *vb_data;
+
+ unsigned vb_size = sizeof(struct anv_vue_header) + 3 * sizeof(*vb_data);
+
+ struct anv_state vb_state =
+ anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, vb_size, 16);
+ memset(vb_state.map, 0, sizeof(struct anv_vue_header));
+ vb_data = vb_state.map + sizeof(struct anv_vue_header);
+
+ vb_data[0] = (struct blit_vb_data) {
+ .pos = {
+(rects[r].dst_x + rects[r].width) * 3,
+rects[r].dst_y + rects[r].height,
+ },
+ .tex_coord = {
+(rects[r].src_x + rects[r].width) * 3,
+rects[r].src_y + rects[r].height,
+src->pitch,
+ },
+ };
+
+ vb_data[1] = (struct blit_vb_data) {
+ .pos = {
+rects[r].dst_x * 3,
+rects[r].dst_y + rects[r].height,
+ },
+ .tex_coord = {
+rects[r].src_x * 3,
+rects[r].src_y + rects[r].height,
+src->pitch,
+ },
+ };
+
+ vb_data[2] = (struct blit_vb_data) {
+ .pos = {
+rects[r].dst_x * 3,
+rects[r].dst_y,
+ },
+ .tex_coord = {
+rects[r].src_x * 3,
+rects[r].src_y,
+src->pitch,
+ },
+ };
+
+ if (!device->info.has_llc)
+ anv_state_clflush(vb_state);
+
+ struct anv_buffer vertex_buffer = {
+ .device = device,
+ .size = vb_size,
+ .bo = &device->dynamic_state_block_pool.bo,
+ .offset = vb_state.offset,
+ };
+
+ anv_CmdBindVertexBuffers(anv_cmd_buffer_to_handle(cmd_buffer), 0, 2,
+ (VkBuffer[]) {
+anv_buffer_to_handle(&vertex_buffer),
+anv_buffer_to_handle(&vertex_buffer)
+ },
+ (VkDeviceSize[]) {
+0,
+sizeof(struct anv_vue_header),
+ });
+
+ ANV_CALL(CmdBeginRenderPass)(anv_cmd_buffer_to_handle(cmd_buffer),
+ &(VkRenderPassBeginInfo) {
+.sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
+.renderPass = device->meta_state.blit2d.render_pass,
+
[Mesa-dev] [PATCH 1/2] anv/blit2d: Add a format parameter to bind_dst and create_iview
Signed-off-by: Jasosn Ekstrand
Cc: "12.0"
---
src/intel/vulkan/anv_meta_blit2d.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/anv_meta_blit2d.c
b/src/intel/vulkan/anv_meta_blit2d.c
index 9d4c2fc..30bc6ed 100644
--- a/src/intel/vulkan/anv_meta_blit2d.c
+++ b/src/intel/vulkan/anv_meta_blit2d.c
@@ -99,6 +99,7 @@ create_iview(struct anv_cmd_buffer *cmd_buffer,
VkImageUsageFlags usage,
uint32_t width,
uint32_t height,
+ VkFormat format,
VkImage *img,
struct anv_image_view *iview)
{
@@ -106,8 +107,7 @@ create_iview(struct anv_cmd_buffer *cmd_buffer,
.sType = VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO,
.imageType = VK_IMAGE_TYPE_2D,
/* W-tiled images must be stencil-formatted. */
- .format = surf->tiling == ISL_TILING_W ?
-VK_FORMAT_S8_UINT : vk_format_for_size(surf->bs),
+ .format = format,
.extent = {
.width = width,
.height = height,
@@ -190,6 +190,8 @@ blit2d_bind_src(struct anv_cmd_buffer *cmd_buffer,
create_iview(cmd_buffer, src, offset, usage,
rect->src_x + rect->width, rect->src_y + rect->height,
+ src->tiling == ISL_TILING_W ?
+ VK_FORMAT_S8_UINT : vk_format_for_size(src->bs),
&tmp->image, &tmp->iview);
anv_CreateDescriptorPool(vk_device,
@@ -339,10 +341,11 @@ blit2d_bind_dst(struct anv_cmd_buffer *cmd_buffer,
uint64_t offset,
uint32_t width,
uint32_t height,
+enum isl_format format,
struct blit2d_dst_temps *tmp)
{
create_iview(cmd_buffer, dst, offset, VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT,
-width, height, &tmp->image, &tmp->iview);
+width, height, format, &tmp->image, &tmp->iview);
anv_CreateFramebuffer(anv_device_to_handle(cmd_buffer->device),
&(VkFramebufferCreateInfo) {
@@ -417,7 +420,8 @@ anv_meta_blit2d_normal_dst(struct anv_cmd_buffer
*cmd_buffer,
struct blit2d_dst_temps dst_temps;
blit2d_bind_dst(cmd_buffer, dst, offset, rects[r].dst_x + rects[r].width,
- rects[r].dst_y + rects[r].height, &dst_temps);
+ rects[r].dst_y + rects[r].height,
+ vk_format_for_size(dst->bs), &dst_temps);
struct blit_vb_data {
float pos[2];
@@ -555,7 +559,8 @@ anv_meta_blit2d_w_tiled_dst(struct anv_cmd_buffer
*cmd_buffer,
};
struct blit2d_dst_temps dst_temps;
- blit2d_bind_dst(cmd_buffer, &dst_Y, offset, xmax_Y, ymax_Y, &dst_temps);
+ blit2d_bind_dst(cmd_buffer, &dst_Y, offset, xmax_Y, ymax_Y,
+ vk_format_for_size(dst->bs), &dst_temps);
struct blit_vb_header {
struct anv_vue_header vue;
--
2.5.0.400.gff86faf
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Re: [Mesa-dev] [PATCH] ast: Updated AST_NUM_OPERATORS for coherence with ast_operators
On Tue, 2016-08-02 at 17:04 +0100, Eric Engestrom wrote:
> On Tue, Aug 02, 2016 at 12:20:54PM +0300, Andres Gomez wrote:
[snip]
> > I'm not sure I'm understanding what you mean.
> >
> > If you mean to remove the #define and add the value as and additional
> > element to the enum, the existence of the define is precisely for not
> > doing that, as explained in its comment.
>
> I've read the comment, so this isn't what I was suggesting (I learned
> something btw, it hadn't occurred to me adding the counter to the enum
> would cause a warning, but I guess it makes sense).
>
> >
> > If you mean to move the #define just below the enumeration, that's what
> > this patch does.
>
> What I meant is to move it to the end of the enum, not after it, so that
> it becomes explicit that it's part of it (for humans, that is; it makes
> no difference to the preprocessor). I expect it was originally just
> after the enum, but with time things got inserted in between.
>
> Something like this would be better IMHO:
>
> 8<--
>
> diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
> index 157895d..b5277fc 100644
> --- a/src/compiler/glsl/ast.h
> +++ b/src/compiler/glsl/ast.h
> @@ -198,6 +198,15 @@ enum ast_operators {
>
> ast_sequence,
> ast_aggregate
> +
> + /**
> +* Number of possible operators for an ast_expression
> +*
> +* This is done as a define instead of as an additional value in the enum
> so
> +* that the compiler won't generate spurious messages like "warning:
> +* enumeration value ‘ast_num_operators’ not handled in switch"
> +*/
> + #define AST_NUM_OPERATORS (ast_aggregate + 1)
> };
>
> /**
>
> 8<--
>
> It's not all that important, your change is good either way, so:
> Reviewed-by: Eric Engestrom
Ouch, right!
Thanks for review and extended comments. I will apply your changes and
push.
Thanks!
--
Br,
Andres
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[Mesa-dev] [PATCH mesa] glx/dri3: remove never-used field
This field was added in 2d94601582e4f0fcaf8c ("Add DRI3+Present loader"), which
was a v2. Guessing it was used in v1 and Keith forgot to remove it in v2.
Signed-off-by: Eric Engestrom
---
Fair warning: This patch will conflict with Jan Ziak's "[PATCH] dri: use 'bool'
instead of 'int' for boolean variables", depending on which is applied first.
Whoever picks one should pick the other and deal with the conflict right way :)
---
src/glx/dri3_priv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 0822377..31b2b98 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -78,7 +78,6 @@ struct dri3_display
int dri3Minor;
/* Present bits */
- int hasPresent;
int presentMajor;
int presentMinor;
};
--
2.9.0
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Re: [Mesa-dev] [PATCH] dri: use 'bool' instead of 'int' for boolean variables
On Tue, Aug 02, 2016 at 05:32:16PM +0200, Jan Ziak wrote:
> Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com>
Much better with the s/0/false/;s/1/true/ :)
Reviewed-by: Eric Engestrom
> ---
> src/egl/drivers/dri2/egl_dri2.h | 19 ++-
> src/egl/drivers/dri2/platform_drm.c | 6 +++---
> src/egl/drivers/dri2/platform_wayland.c | 20 ++--
> src/egl/drivers/dri2/platform_x11.c | 4 ++--
> src/gallium/auxiliary/vl/vl_winsys_dri3.c | 3 ++-
> src/glx/dri3_priv.h | 5 +++--
> src/loader/loader.c | 19 ++-
> src/loader/loader.h | 4 +++-
> 8 files changed, 43 insertions(+), 37 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
> index 4577875..f4e6be8 100644
> --- a/src/egl/drivers/dri2/egl_dri2.h
> +++ b/src/egl/drivers/dri2/egl_dri2.h
> @@ -28,6 +28,7 @@
> #ifndef EGL_DRI2_INCLUDED
> #define EGL_DRI2_INCLUDED
>
> +#include
> #include
>
> #ifdef HAVE_X11_PLATFORM
> @@ -160,7 +161,7 @@ struct dri2_egl_display
> int dri2_major;
> int dri2_minor;
> __DRIscreen *dri_screen;
> - int own_dri_screen;
> + bool own_dri_screen;
> const __DRIconfig **driver_configs;
> void *driver;
> const __DRIcoreExtension *core;
> @@ -181,8 +182,8 @@ struct dri2_egl_display
> * dri2_make_current (tracks if there are active contexts/surfaces). */
> int ref_count;
>
> - int own_device;
> - int invalidate_available;
> + bool own_device;
> + bool invalidate_available;
> int min_swap_interval;
> int max_swap_interval;
> int default_swap_interval;
> @@ -201,7 +202,7 @@ struct dri2_egl_display
> #ifdef HAVE_X11_PLATFORM
> xcb_connection_t *conn;
> int screen;
> - int swap_available;
> + bool swap_available;
> #ifdef HAVE_DRI3
> struct loader_dri3_extensions loader_dri3_ext;
> #endif
> @@ -214,13 +215,13 @@ struct dri2_egl_display
> struct wl_drm*wl_drm;
> struct wl_shm*wl_shm;
> struct wl_event_queue*wl_queue;
> - intauthenticated;
> + bool authenticated;
> intformats;
> uint32_t capabilities;
> #endif
>
> - int is_render_node;
> - intis_different_gpu;
> + bool is_render_node;
> + bool is_different_gpu;
> };
>
> struct dri2_egl_context
> @@ -244,7 +245,7 @@ struct dri2_egl_surface
> __DRIdrawable *dri_drawable;
> __DRIbuffer buffers[5];
> int buffer_count;
> - int have_fake_front;
> + bool have_fake_front;
>
> #ifdef HAVE_X11_PLATFORM
> xcb_drawable_t drawable;
> @@ -282,7 +283,7 @@ struct dri2_egl_surface
> #ifdef HAVE_DRM_PLATFORM
>struct gbm_bo *bo;
> #endif
> - int locked;
> + boollocked;
>int age;
> } color_buffers[4], *back, *current;
> #endif
> diff --git a/src/egl/drivers/dri2/platform_drm.c
> b/src/egl/drivers/dri2/platform_drm.c
> index 9373496..06c06ab 100644
> --- a/src/egl/drivers/dri2/platform_drm.c
> +++ b/src/egl/drivers/dri2/platform_drm.c
> @@ -56,7 +56,7 @@ lock_front_buffer(struct gbm_surface *_surf)
> bo = dri2_surf->current->bo;
>
> if (device->dri2) {
> - dri2_surf->current->locked = 1;
> + dri2_surf->current->locked = true;
>dri2_surf->current = NULL;
> }
>
> @@ -72,7 +72,7 @@ release_buffer(struct gbm_surface *_surf, struct gbm_bo *bo)
>
> for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
>if (dri2_surf->color_buffers[i].bo == bo) {
> - dri2_surf->color_buffers[i].locked = 0;
> + dri2_surf->color_buffers[i].locked = false;
>}
> }
> }
> @@ -621,7 +621,7 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
> fd = loader_open_device(buf);
>if (fd < 0)
> fd = loader_open_device("/dev/dri/card0");
> - dri2_dpy->own_device = 1;
> + dri2_dpy->own_device = true;
>gbm = gbm_create_device(fd);
>if (gbm == NULL)
> goto cleanup;
> diff --git a/src/egl/drivers/dri2/platform_wayland.c
> b/src/egl/drivers/dri2/platform_wayland.c
> index e714e44..675ca2b 100644
> --- a/src/egl/drivers/dri2/platform_wayland.c
> +++ b/src/egl/drivers/dri2/platform_wayland.c
> @@ -101,7 +101,7 @@ wl_buffer_release(void
Re: [Mesa-dev] [PATCH] dri: use 'bool' instead 'int' for boolean variables
On Mon, Aug 01, 2016 at 03:43:17PM +0200, ⚛ wrote: > On Mon, Aug 1, 2016 at 2:46 PM, Eric Engestrom > wrote: > > On Sun, Jul 31, 2016 at 05:49:02PM +0200, Jan Ziak wrote: > >> Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com> > > > > This is a good change, and with a couple things to fix below, it is: > > Reviewed-by: Eric Engestrom > > > >> +#include > > > > You should add this include to all the files that need it, instead of > > relying on it to be included by some other include. > > Done. > > >> + pdp->hasPresent = true; > > > > This is a bugfix, unrelated to this refactoring. It should be its own patch. > > However, I'm not positive it is correct, so it doesn't get my r-b (yet). > > I removed the "pdp->hasPresent = true". The change from "int > hasPresent" to "bool hasPresent" is still in the patch. > > grep -R "\" shows that the field isn't used anywhere. Indeed, I guess the field should be removed, but that should be another patch. Your latest version looks good; I'll look at it again, and r-b it :) Cheers, Eric ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] dir-locals.el: show-trailing-whitespace and whitespace support
Signed-off-by: Andres Gomez --- .dir-locals.el | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/.dir-locals.el b/.dir-locals.el index 4b53931..9c89a63 100644 --- a/.dir-locals.el +++ b/.dir-locals.el @@ -1,4 +1,5 @@ -((prog-mode +((nil . ((show-trailing-whitespace . t))) + (prog-mode (indent-tabs-mode . nil) (tab-width . 8) (c-basic-offset . 3) @@ -8,6 +9,10 @@ (c-set-offset 'case-label '0) (c-set-offset 'innamespace '0) (c-set-offset 'inline-open '0))) - ) + (whitespace-style face indentation lines-tail) + (whitespace-line-column . 79) + (eval ignore-errors +(require 'whitespace) +(whitespace-mode 1))) (makefile-mode (indent-tabs-mode . t)) ) -- 2.8.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] ast: Updated AST_NUM_OPERATORS for coherence with ast_operators
On Tue, Aug 02, 2016 at 12:20:54PM +0300, Andres Gomez wrote:
> On Mon, 2016-08-01 at 14:02 +0100, Eric Engestrom wrote:
> > On Sun, Jul 31, 2016 at 07:07:34PM +0300, Andres Gomez wrote:
>
> [snip]
>
> > > diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
> > > index 157895d..89f531c 100644
> > > --- a/src/compiler/glsl/ast.h
> > > +++ b/src/compiler/glsl/ast.h
> > > @@ -198,9 +198,19 @@ enum ast_operators {
> > >
> > > ast_sequence,
> > > ast_aggregate
> > > + /** Update AST_NUM_OPERATORS if more are appended */
> > > };
> > >
> > > /**
> > > + * Number of possible operators for an ast_expression
> > > + *
> > > + * This is done as a define instead of as an additional value in the
> > > enum so
> > > + * that the compiler won't generate spurious messages like "warning:
> > > + * enumeration value ‘ast_num_operators’ not handled in switch"
> > > + */
> > > +#define AST_NUM_OPERATORS (ast_aggregate + 1)
> >
> > Since you're moving the #define, why not move it at the end of the enum,
> > instead of adding the message there to go and look for the define?
> > Other than that, the change looks good :)
>
> I'm not sure I'm understanding what you mean.
>
> If you mean to remove the #define and add the value as and additional
> element to the enum, the existence of the define is precisely for not
> doing that, as explained in its comment.
I've read the comment, so this isn't what I was suggesting (I learned
something btw, it hadn't occurred to me adding the counter to the enum
would cause a warning, but I guess it makes sense).
>
> If you mean to move the #define just below the enumeration, that's what
> this patch does.
What I meant is to move it to the end of the enum, not after it, so that
it becomes explicit that it's part of it (for humans, that is; it makes
no difference to the preprocessor). I expect it was originally just
after the enum, but with time things got inserted in between.
Something like this would be better IMHO:
8<--
diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
index 157895d..b5277fc 100644
--- a/src/compiler/glsl/ast.h
+++ b/src/compiler/glsl/ast.h
@@ -198,6 +198,15 @@ enum ast_operators {
ast_sequence,
ast_aggregate
+
+ /**
+* Number of possible operators for an ast_expression
+*
+* This is done as a define instead of as an additional value in the enum so
+* that the compiler won't generate spurious messages like "warning:
+* enumeration value ‘ast_num_operators’ not handled in switch"
+*/
+ #define AST_NUM_OPERATORS (ast_aggregate + 1)
};
/**
8<--
It's not all that important, your change is good either way, so:
Reviewed-by: Eric Engestrom
Cheers,
Eric
>
> Could you clarify?
>
> Thanks!
> --
>
> Br,
>
> Andres
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Re: [Mesa-dev] [PATCH] vbo: fix format string compiler warning for 32-bit machines
On 08/02/2016 08:40 AM, Jan Ziak wrote: Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com> --- src/mesa/vbo/vbo_exec_array.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c index f371890..ae6a3da 100644 --- a/src/mesa/vbo/vbo_exec_array.c +++ b/src/mesa/vbo/vbo_exec_array.c @@ -1681,8 +1681,9 @@ vbo_exec_MultiDrawArraysIndirectCount(GLenum mode, if (MESA_VERBOSE & VERBOSE_DRAW) _mesa_debug(ctx, "glMultiDrawArraysIndirectCountARB" "(%s, %lx, %lx, %i, %i)\n", - _mesa_enum_to_string(mode), indirect, - drawcount, maxdrawcount, stride); + _mesa_enum_to_string(mode), + (unsigned long)indirect, (unsigned long)drawcount, + maxdrawcount, stride); /* If is zero, the array elements are treated as tightly packed. */ if (stride == 0) @@ -1709,9 +1710,9 @@ vbo_exec_MultiDrawElementsIndirectCount(GLenum mode, GLenum type, if (MESA_VERBOSE & VERBOSE_DRAW) _mesa_debug(ctx, "glMultiDrawElementsIndirectCountARB" "(%s, %s, %lx, %lx, %i, %i)\n", - _mesa_enum_to_string(mode), - _mesa_enum_to_string(type), indirect, - drawcount, maxdrawcount, stride); + _mesa_enum_to_string(mode), _mesa_enum_to_string(type), + (unsigned long)indirect, (unsigned long)drawcount, + maxdrawcount, stride); /* If is zero, the array elements are treated as tightly packed. */ if (stride == 0) Reviewed-by: Brian Paul ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] vbo: fix debug message format string in case of 32-bit machines
On 08/02/2016 08:45 AM, ⚛ wrote: On Tue, Aug 2, 2016 at 4:13 PM, Brian Paul wrote: In bufferobj.c, it looks like we're just using %d or %s and casting the arguments to int. But in other places, we're using %ld and casting to long. That's not going to accurately report 64-bit values, but I guess that hasn't been a concern so far. Thanks. I updated the patch. Btw: What is the use case for compiling Mesa with MSVC? It serves as our OpenGL driver in Windows VMs. It's shipped as part of the VMware "Tools" package. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] dri: use 'bool' instead of 'int' for boolean variables
Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com>
---
src/egl/drivers/dri2/egl_dri2.h | 19 ++-
src/egl/drivers/dri2/platform_drm.c | 6 +++---
src/egl/drivers/dri2/platform_wayland.c | 20 ++--
src/egl/drivers/dri2/platform_x11.c | 4 ++--
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 3 ++-
src/glx/dri3_priv.h | 5 +++--
src/loader/loader.c | 19 ++-
src/loader/loader.h | 4 +++-
8 files changed, 43 insertions(+), 37 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 4577875..f4e6be8 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -28,6 +28,7 @@
#ifndef EGL_DRI2_INCLUDED
#define EGL_DRI2_INCLUDED
+#include
#include
#ifdef HAVE_X11_PLATFORM
@@ -160,7 +161,7 @@ struct dri2_egl_display
int dri2_major;
int dri2_minor;
__DRIscreen *dri_screen;
- int own_dri_screen;
+ bool own_dri_screen;
const __DRIconfig **driver_configs;
void *driver;
const __DRIcoreExtension *core;
@@ -181,8 +182,8 @@ struct dri2_egl_display
* dri2_make_current (tracks if there are active contexts/surfaces). */
int ref_count;
- int own_device;
- int invalidate_available;
+ bool own_device;
+ bool invalidate_available;
int min_swap_interval;
int max_swap_interval;
int default_swap_interval;
@@ -201,7 +202,7 @@ struct dri2_egl_display
#ifdef HAVE_X11_PLATFORM
xcb_connection_t *conn;
int screen;
- int swap_available;
+ bool swap_available;
#ifdef HAVE_DRI3
struct loader_dri3_extensions loader_dri3_ext;
#endif
@@ -214,13 +215,13 @@ struct dri2_egl_display
struct wl_drm*wl_drm;
struct wl_shm*wl_shm;
struct wl_event_queue*wl_queue;
- int authenticated;
+ bool authenticated;
int formats;
uint32_t capabilities;
#endif
- int is_render_node;
- int is_different_gpu;
+ bool is_render_node;
+ bool is_different_gpu;
};
struct dri2_egl_context
@@ -244,7 +245,7 @@ struct dri2_egl_surface
__DRIdrawable *dri_drawable;
__DRIbuffer buffers[5];
int buffer_count;
- int have_fake_front;
+ bool have_fake_front;
#ifdef HAVE_X11_PLATFORM
xcb_drawable_t drawable;
@@ -282,7 +283,7 @@ struct dri2_egl_surface
#ifdef HAVE_DRM_PLATFORM
struct gbm_bo *bo;
#endif
- int locked;
+ boollocked;
int age;
} color_buffers[4], *back, *current;
#endif
diff --git a/src/egl/drivers/dri2/platform_drm.c
b/src/egl/drivers/dri2/platform_drm.c
index 9373496..06c06ab 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -56,7 +56,7 @@ lock_front_buffer(struct gbm_surface *_surf)
bo = dri2_surf->current->bo;
if (device->dri2) {
- dri2_surf->current->locked = 1;
+ dri2_surf->current->locked = true;
dri2_surf->current = NULL;
}
@@ -72,7 +72,7 @@ release_buffer(struct gbm_surface *_surf, struct gbm_bo *bo)
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
if (dri2_surf->color_buffers[i].bo == bo) {
-dri2_surf->color_buffers[i].locked = 0;
+dri2_surf->color_buffers[i].locked = false;
}
}
}
@@ -621,7 +621,7 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
fd = loader_open_device(buf);
if (fd < 0)
fd = loader_open_device("/dev/dri/card0");
- dri2_dpy->own_device = 1;
+ dri2_dpy->own_device = true;
gbm = gbm_create_device(fd);
if (gbm == NULL)
goto cleanup;
diff --git a/src/egl/drivers/dri2/platform_wayland.c
b/src/egl/drivers/dri2/platform_wayland.c
index e714e44..675ca2b 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -101,7 +101,7 @@ wl_buffer_release(void *data, struct wl_buffer *buffer)
return;
}
- dri2_surf->color_buffers[i].locked = 0;
+ dri2_surf->color_buffers[i].locked = false;
}
static const struct wl_buffer_listener wl_buffer_listener = {
@@ -288,7 +288,7 @@ dri2_wl_release_buffers(struct dri2_egl_surface *dri2_surf)
dri2_surf->color_buffers[i].dri_image = NULL;
dri2_surf->color_buffers[i].linear_copy = NU
Re: [Mesa-dev] [PATCH 00/12] RadeonSI: Prevent IB submissions with illegal memory usage
On 29.07.2016 23:42, Marek Olšák wrote: This series ensures that memory usage of gfx IBs is below the kernel- exposed memory limits in most cases. It's not possible to prevent CS ioctl failures completely because it depends on whether continuous free space for all buffers is available, i.e. it depends on where some system buffers are pinned, rather than how much total free space you have. Piglit max-texture-size and tex3d-maxsize tests easily pass with this. There are also some cleanups. Reading through the series, I believe that the individual patches are fine (other than some bike-shedding perhaps), but it may be time to change the CS submission approach into more of a transaction-with-commit/rollback one. This is mostly because the whole dance around r600_context_add_resource_size, radeon_add_to_buffer_list and radeon_add_to_buffer_list_check_mem just feels very fragile. Basically, radeon_winsys_cs would have a "committed" pointer into the IB in addition to the "current" pointer. Similarly, the buffer list would have a "committed" index. Winsys callbacks cs_commit and cs_rollback would do the obvious thing of moving the committed pointers to current or the other way around. (On second thought, it's probably only the buffer list that needs "committed" pointers.) Then, the buffer handling in the driver code would be simplified as follows: - As long as the CS already contains some committed draw/DMA call, radeon_add_to_buffer_list always checks whether the memory size is exceeded. If so, it calls cs_rollback, flushes, and returns a corresponding code. - There is no need to distinguish radeon_add_to_buffer_list and radeon_add_to_buffer_list_check_mem anymore, since all additions are checked if and only if there really is something to flush. - There is no more need for r600_context_add_resource_size. Instead, all draw/DMA-related buffers (vertex & index buffers, indirect data, DMA buffers) are added via radeon_add_to_buffer_list just before the call to si_need_cs_space. If radeon_add_to_buffer_list indicates that a flush happened, the sequence is repeated. - After each draw call, cs_commit is called. Another, tangentially related issue: we really shouldn't add buffers tied to descriptors in the *_begin_new_cs and even the set_* functions; instead, it should ideally happen at si_upload_descriptors time. Otherwise, we may end up adding buffers to a CS that aren't needed anymore. Cheers, Nicolai Please review. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] vbo: fix debug message format string in case of 32-bit machines
On Tue, Aug 2, 2016 at 4:13 PM, Brian Paul wrote: > In bufferobj.c, it looks like we're just using %d or %s and casting the > arguments to int. But in other places, we're using %ld and casting to long. > That's not going to accurately report 64-bit values, but I guess that hasn't > been a concern so far. Thanks. I updated the patch. Btw: What is the use case for compiling Mesa with MSVC? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 12/12] gallium/radeon/winsyses: decrease max_alloc_size to 1/3 of largest heap
On 02.08.2016 10:55, Marek Olšák wrote: On Tue, Aug 2, 2016 at 3:13 AM, Michel Dänzer wrote: On 01.08.2016 16:35, Michel Dänzer wrote: On 30.07.2016 06:42, Marek Olšák wrote: From: Marek Olšák This is controversial, but I don't see a better way out of this. Tonga has 2 GB of VRAM and 2 GB of GTT. amdgpu is not capable of submitting an IB referencing 1 GB of VRAM and 1 GB of GTT. The CS ioctl never succeeds even though it's far below the limits. Without this, "dEQP-GLES2.functional.color_clear.single_rgb" fails to submit an IB. With this, dEQP throws a framebuffer-incomplete exception and kills the process. IMO, failing the CS ioctl is worse for stability than failing big allocations. I can agree with that, but this change can't reliably prevent CS ioctl failures: I believe the problem is mostly due to BOs which are pinned for scanout. Since up to 6 CRTCs can scan out different buffers at any time, in the worst case it may not be possible to place any BOs whose size is >= ~1/7 of the VRAM size. At the end of the day, this needs to be solved in the kernel one way or another. Or if you do want to avoid the problem in userspace for now, maybe use 1 / (number of CRTCs + 1) instead of hardcoding 1/3? I don't know. I could avoid the problem by splitting buffers into 128MB blocks mapped into GPUVM consecutively, but that would prevent easy DMABUF sharing and CPU mappings would not be consecutive. That really sounds like the kind of thing the kernel should take care of... Nicolai Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] vbo: fix format string compiler warning for 32-bit machines
Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com> --- src/mesa/vbo/vbo_exec_array.c | 11 ++- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c index f371890..ae6a3da 100644 --- a/src/mesa/vbo/vbo_exec_array.c +++ b/src/mesa/vbo/vbo_exec_array.c @@ -1681,8 +1681,9 @@ vbo_exec_MultiDrawArraysIndirectCount(GLenum mode, if (MESA_VERBOSE & VERBOSE_DRAW) _mesa_debug(ctx, "glMultiDrawArraysIndirectCountARB" "(%s, %lx, %lx, %i, %i)\n", - _mesa_enum_to_string(mode), indirect, - drawcount, maxdrawcount, stride); + _mesa_enum_to_string(mode), + (unsigned long)indirect, (unsigned long)drawcount, + maxdrawcount, stride); /* If is zero, the array elements are treated as tightly packed. */ if (stride == 0) @@ -1709,9 +1710,9 @@ vbo_exec_MultiDrawElementsIndirectCount(GLenum mode, GLenum type, if (MESA_VERBOSE & VERBOSE_DRAW) _mesa_debug(ctx, "glMultiDrawElementsIndirectCountARB" "(%s, %s, %lx, %lx, %i, %i)\n", - _mesa_enum_to_string(mode), - _mesa_enum_to_string(type), indirect, - drawcount, maxdrawcount, stride); + _mesa_enum_to_string(mode), _mesa_enum_to_string(type), + (unsigned long)indirect, (unsigned long)drawcount, + maxdrawcount, stride); /* If is zero, the array elements are treated as tightly packed. */ if (stride == 0) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 08/12] gallium/radeon/winsyses: print CS submission error number
On 29.07.2016 23:42, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index fb517b9..35e1b48 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -935,7 +935,7 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
fprintf(stderr, "amdgpu: Not enough memory for command
submission.\n");
else
fprintf(stderr, "amdgpu: The CS has been rejected, "
- "see dmesg for more information.\n");
+ "see dmesg for more information (%i).\n", r);
amdgpu_fence_signalled(cs->fence);
} else {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 606c38d..4a6f005 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -447,7 +447,7 @@ void radeon_drm_cs_emit_ioctl_oneshot(void *job, int
thread_index)
}
} else {
fprintf(stderr, "radeon: The kernel rejected CS, "
-"see dmesg for more information.\n");
+"see dmesg for more information (%i).\n", r);
}
}
It would be nice to use strerror_r here:
char buf[128];
strerror_r(-r, buf, sizeof(buf));
... then use buf ...
That would also get rid of the ENOMEM special case.
Nicolai
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Re: [Mesa-dev] [PATCH 7/8] winsys/radeon: implement cs_get_next_fence
Patches 1-7:
Reviewed-by: Nicolai Hähnle
On 02.08.2016 12:27, Marek Olšák wrote:
From: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 30 +--
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 1 +
2 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index e06a01d..612a876 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -492,9 +492,14 @@ static int radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs,
}
if (fence) {
-radeon_fence_reference(fence, NULL);
-*fence = radeon_cs_create_fence(rcs);
+ if (cs->next_fence) {
+ radeon_fence_reference(fence, cs->next_fence);
+ } else {
+ radeon_fence_reference(fence, NULL);
+ *fence = radeon_cs_create_fence(rcs);
+ }
}
+radeon_fence_reference(&cs->next_fence, NULL);
radeon_drm_cs_sync_flush(rcs);
@@ -593,6 +598,7 @@ static void radeon_drm_cs_destroy(struct radeon_winsys_cs
*rcs)
p_atomic_dec(&cs->ws->num_cs);
radeon_destroy_cs_context(&cs->csc1);
radeon_destroy_cs_context(&cs->csc2);
+radeon_fence_reference(&cs->next_fence, NULL);
FREE(cs);
}
@@ -651,6 +657,25 @@ static void radeon_fence_reference(struct
pipe_fence_handle **dst,
pb_reference((struct pb_buffer**)dst, (struct pb_buffer*)src);
}
+static struct pipe_fence_handle *
+radeon_drm_cs_get_next_fence(struct radeon_winsys_cs *rcs)
+{
+ struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
+ struct pipe_fence_handle *fence = NULL;
+
+ if (cs->next_fence) {
+ radeon_fence_reference(&fence, cs->next_fence);
+ return fence;
+ }
+
+ fence = radeon_cs_create_fence(rcs);
+ if (!fence)
+ return NULL;
+
+ radeon_fence_reference(&cs->next_fence, fence);
+ return fence;
+}
+
void radeon_drm_cs_init_functions(struct radeon_drm_winsys *ws)
{
ws->base.ctx_create = radeon_drm_ctx_create;
@@ -663,6 +688,7 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys
*ws)
ws->base.cs_check_space = radeon_drm_cs_check_space;
ws->base.cs_get_buffer_list = radeon_drm_cs_get_buffer_list;
ws->base.cs_flush = radeon_drm_cs_flush;
+ws->base.cs_get_next_fence = radeon_drm_cs_get_next_fence;
ws->base.cs_is_buffer_referenced = radeon_bo_is_referenced;
ws->base.cs_sync_flush = radeon_drm_cs_sync_flush;
ws->base.fence_wait = radeon_fence_wait;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index b1d54f7..76004c5 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -76,6 +76,7 @@ struct radeon_drm_cs {
void *flush_data;
struct util_queue_fence flush_completed;
+struct pipe_fence_handle *next_fence;
};
int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo);
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Re: [Mesa-dev] [PATCH 8/8] gallium/radeon: use unflushed fences for deferred flushes
On 02.08.2016 12:27, Marek Olšák wrote:
From: Marek Olšák
+23% Bioshock Infinite performance.
---
src/gallium/drivers/radeon/r600_pipe_common.c | 45 ++-
1 file changed, 44 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 5e9d0b6..1a7bd7a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -47,6 +47,12 @@ struct r600_multi_fence {
struct pipe_reference reference;
struct pipe_fence_handle *gfx;
struct pipe_fence_handle *sdma;
+
+ /* If the context wasn't flushed at fence creation, this is non-NULL. */
+ struct {
+ struct r600_common_context *ctx;
+ unsigned ib_index;
+ } gfx_unflushed;
};
/*
@@ -262,6 +268,7 @@ static void r600_flush_from_st(struct pipe_context *ctx,
unsigned rflags = 0;
struct pipe_fence_handle *gfx_fence = NULL;
struct pipe_fence_handle *sdma_fence = NULL;
+ bool deferred_fence = false;
if (flags & PIPE_FLUSH_END_OF_FRAME)
rflags |= RADEON_FLUSH_END_OF_FRAME;
@@ -271,7 +278,22 @@ static void r600_flush_from_st(struct pipe_context *ctx,
if (rctx->dma.cs) {
rctx->dma.flush(rctx, rflags, fence ? &sdma_fence : NULL);
}
- rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
+
+ /* Instead of flushing, create a deferred fence. Constraints:
+* - The state tracker must allow a deferred flush.
+* - The state tracker must request a fence.
+* - At most one API context can exist to ensure thread-safety.
+* (that's a weak contraint though, we must be careful about
+*how PIPE_FLUSH_DEFERRED is used)
+*/
+ if (flags & PIPE_FLUSH_DEFERRED && fence &&
+ /* internal aux_context + 1 API context */
+ rctx->screen->num_contexts <= 2) {
+ gfx_fence = rctx->ws->cs_get_next_fence(rctx->gfx.cs);
+ deferred_fence = true;
+ } else {
+ rctx->gfx.flush(rctx, rflags, fence ? &gfx_fence : NULL);
+ }
/* Both engines can signal out of order, so we need to keep both
fences. */
if (gfx_fence || sdma_fence) {
@@ -284,6 +306,11 @@ static void r600_flush_from_st(struct pipe_context *ctx,
multi_fence->gfx = gfx_fence;
multi_fence->sdma = sdma_fence;
+ if (deferred_fence) {
+ multi_fence->gfx_unflushed.ctx = rctx;
+ multi_fence->gfx_unflushed.ib_index =
rctx->num_gfx_cs_flushes;
+ }
+
screen->fence_reference(screen, fence, NULL);
*fence = (struct pipe_fence_handle*)multi_fence;
}
@@ -962,6 +989,7 @@ static boolean r600_fence_finish(struct pipe_screen *screen,
{
struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
struct r600_multi_fence *rfence = (struct r600_multi_fence *)fence;
+ struct r600_common_context *rctx;
int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
if (rfence->sdma) {
@@ -978,6 +1006,21 @@ static boolean r600_fence_finish(struct pipe_screen
*screen,
if (!rfence->gfx)
return true;
+ /* Flush the gfx IB if it hasn't been flushed yet. */
+ rctx = rfence->gfx_unflushed.ctx;
+ if (rctx && rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes)
{
+ rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
It seems like a good idea to clear rfence->gfx_unflushed.ctx here.
So, I was feeling a bit iffy about the multi-context handling here --
e.g., what if a second context was created after the fence was created
but before it was waited on -- and I think we should go back and read
the spec on this again :-)
In particular, I'm looking at section 4.1.2 of OpenGL 4.5 (Compatibility
Profile), and it says: [...] if ClientWaitSync is called and all of the
following are true:
- the SYNC_FLUSH_COMMANDS_BIT bit is set in flags,
- sync is unsignaled when ClientWaitSync is called,
- and the calls to ClientWaitSync and FenceSync were issued *from the
same context*,
then the GL will behave as if the equivalent of Flush were inserted
immediately after the creation of sync.
So I think the multi-context dance isn't needed. Instead, while most of
this patch is fine as is, it seems like the proper solution is slightly
different: have a fence_finish callback associated to pipe_context
rather than pipe_screen, which optionally does the flush on unflushed
fences, but *only if in the same context*. Then the state tracker would
call that fence function instead.
At least that's how I'm reading that part of the spec...
Cheers,
Nicolai
+
+ if (!timeout)
+ return false;
+
+ /* Recompute th
Re: [Mesa-dev] [PATCH 0/3] Destroy Present event contexts
On 08/01/2016 10:20 PM, Michel Dänzer wrote: On 28.07.2016 18:34, Michel Dänzer wrote: Running XTS (the X test suite) on Xephyr using glamor running on Xorg, I stumbled upon an issue: * XTS causes Xephyr to keep resetting and starting new server generations * glamor creates a new GLX context for each server generation but re-uses the same window This caused Xorg to accumulate stale Present event contexts from previous GLX contexts, so it kept getting slower due to sending out an increasing number of copies of the same Present events to Xephyr. The first patch fixes this problem, and the other two patches apply the same principle to the other places using Present event contexts. Note that destroying a Present event context doesn't actually work without this xserver fix: https://patchwork.freedesktop.org/patch/101430/ v2 of that fix has landed in xserver master. But these changes shouldn't make things any worse than they already are with X servers lacking that fix. [PATCH 1/3] loader/dri3: Destroy Present event context when [PATCH 2/3] vl/dri3: Destroy Present event context when destroying [PATCH 3/3] anv/x11: Destroy Present event context when destroying Any comments on the v2 patches? Unless there are any objections, I'm going to push v2 of patches 1 & 2 later this week. I'm not going to push patch 3 myself without getting at least a Tested-by: from somebody. Patch 2 is: Tested and Reviewed by: Leo Liu Regards, Leo ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] vbo: fix debug message format string in case of 32-bit machines
On 08/01/2016 04:35 PM, Jan Ziak wrote:
Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com>
---
src/mesa/vbo/vbo_exec_array.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 90f1321..fe74c73 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -1680,7 +1680,7 @@ vbo_exec_MultiDrawArraysIndirectCount(GLenum mode,
if (MESA_VERBOSE & VERBOSE_DRAW)
_mesa_debug(ctx, "glMultiDrawArraysIndirectCountARB"
- "(%s, %lx, %lx, %i, %i)\n",
+ "(%s, %zx, %zx, %i, %i)\n",
_mesa_enum_to_string(mode), indirect,
drawcount, maxdrawcount, stride);
@@ -1708,7 +1708,7 @@ vbo_exec_MultiDrawElementsIndirectCount(GLenum mode,
GLenum type,
if (MESA_VERBOSE & VERBOSE_DRAW)
_mesa_debug(ctx, "glMultiDrawElementsIndirectCountARB"
- "(%s, %s, %lx, %lx, %i, %i)\n",
+ "(%s, %s, %zx, %zx, %i, %i)\n",
_mesa_enum_to_string(mode),
_mesa_enum_to_string(type), indirect,
drawcount, maxdrawcount, stride);
Unfortunately, the MSVC compiler (er, the runtime) doesn't understand
the 'z' modifier.
I just tried a test program with a printf("test %zx\n", k) where k's
type is size_t. The output was "test zx".
I also tried the mingw compiler and got:
Compiling src/mesa/vbo/vbo_exec_array.c ...
src/mesa/vbo/vbo_exec_array.c: In function
‘vbo_exec_MultiDrawArraysIndirectCount’:
src/mesa/vbo/vbo_exec_array.c:1662:19: warning: unknown conversion type
character ‘z’ in format [-Wformat]
src/mesa/vbo/vbo_exec_array.c:1662:19: warning: unknown conversion type
character ‘z’ in format [-Wformat]
src/mesa/vbo/vbo_exec_array.c:1662:19: warning: too many arguments for
format [-Wformat-extra-args]
Even without your patch, we've had a few mingw warnings in the same place:
Compiling src/mesa/vbo/vbo_exec_array.c ...
src/mesa/vbo/vbo_exec_array.c: In function
‘vbo_exec_MultiDrawArraysIndirectCount’:
src/mesa/vbo/vbo_exec_array.c:1662:19: warning: format ‘%lx’ expects
argument of type ‘long unsigned int’, but argument 4 has type ‘GLintptr’
[-Wformat]
src/mesa/vbo/vbo_exec_array.c:1662:19: warning: format ‘%lx’ expects
argument of type ‘long unsigned int’, but argument 5 has type ‘GLintptr’
[-Wformat]
In bufferobj.c, it looks like we're just using %d or %s and casting the
arguments to int. But in other places, we're using %ld and casting to
long. That's not going to accurately report 64-bit values, but I guess
that hasn't been a concern so far.
-Brian
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Re: [Mesa-dev] [PATCH] radeonsi: skip unnecessary si_update_shaders calls
Reviewed-by: Nicolai Hähnle
On 02.08.2016 12:34, Marek Olšák wrote:
From: Marek Olšák
Small decrease in draw call overhead.
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 6 ++
src/gallium/drivers/radeonsi/si_state_draw.c| 20 +---
src/gallium/drivers/radeonsi/si_state_shaders.c | 7 +++
4 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index c4f7a1c..55f8965 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -259,6 +259,7 @@ struct si_context {
struct si_vertex_element*vertex_elements;
unsignedsprite_coord_enable;
boolflatshade;
+ booldo_update_shaders;
/* shader descriptors */
struct si_descriptors vertex_buffers;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index c5b61e9..47fc7a0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -572,6 +572,7 @@ static void si_bind_blend_state(struct pipe_context *ctx,
void *state)
struct si_context *sctx = (struct si_context *)ctx;
si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ sctx->do_update_shaders = true;
}
static void si_delete_blend_state(struct pipe_context *ctx, void *state)
@@ -869,6 +870,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void
*state)
si_update_poly_offset_state(sctx);
si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ sctx->do_update_shaders = true;
}
static void si_delete_rs_state(struct pipe_context *ctx, void *state)
@@ -1018,6 +1020,7 @@ static void si_bind_dsa_state(struct pipe_context *ctx,
void *state)
sctx->stencil_ref.dsa_part = dsa->stencil_ref;
si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
}
+ sctx->do_update_shaders = true;
}
static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
@@ -2388,6 +2391,7 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
}
sctx->need_check_render_feedback = true;
+ sctx->do_update_shaders = true;
}
static void si_emit_framebuffer_state(struct si_context *sctx, struct
r600_atom *atom)
@@ -2628,6 +2632,7 @@ static void si_set_min_samples(struct pipe_context *ctx,
unsigned min_samples)
return;
sctx->ps_iter_samples = min_samples;
+ sctx->do_update_shaders = true;
if (sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, &sctx->msaa_config);
@@ -3267,6 +3272,7 @@ static void si_bind_vertex_elements(struct pipe_context
*ctx, void *state)
sctx->vertex_elements = v;
sctx->vertex_buffers_dirty = true;
+ sctx->do_update_shaders = true;
}
static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 2db2b0b..d743e22 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -867,7 +867,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
struct si_context *sctx = (struct si_context *)ctx;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
struct pipe_index_buffer ib = {};
- unsigned mask, dirty_fb_counter, dirty_tex_counter;
+ unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
if (!info->count && !info->indirect &&
(info->indexed || !info->count_from_stream_output))
@@ -911,15 +911,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
* draw_vbo recursively, and before si_update_shaders, which uses
* current_rast_prim for this draw_vbo call. */
if (sctx->gs_shader.cso)
- sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
+ rast_prim = sctx->gs_shader.cso->gs_output_prim;
else if (sctx->tes_shader.cso)
- sctx->current_rast_prim =
-
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
else
- sctx->current_rast_prim = info->mode;
+ rast_prim = info->mode;
- if (!si_update_shaders(sctx) ||
- !si_upload_graphics_shader_descriptors(sctx))
+ if (rast_prim != sctx->current_rast_prim) {
+ sctx->current_rast_prim = rast_prim;
+ sctx->do_update_shaders = true;
+ }
+
+ if (sctx->
Re: [Mesa-dev] [PATCH 3/3] radeonsi: print the command line to VM fault reports
Patch 2 & 3: Reviewed-by: Nicolai Hähnle On 30.07.2016 17:22, Marek Olšák wrote: From: Marek Olšák --- src/gallium/drivers/radeonsi/si_debug.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index e030f48..00a3b13 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -805,6 +805,7 @@ void si_check_vm_faults(struct r600_common_context *ctx, struct pipe_screen *screen = sctx->b.b.screen; FILE *f; uint32_t addr; + char cmd_line[4096]; if (!si_vm_fault_occured(sctx, &addr)) return; @@ -814,6 +815,8 @@ void si_check_vm_faults(struct r600_common_context *ctx, return; fprintf(f, "VM fault report.\n\n"); + if (os_get_process_cmd_line(cmd_line, sizeof(cmd_line))) + fprintf(f, "Command: %s\n", cmd_line); fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen)); fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen)); fprintf(f, "Device name: %s\n\n", screen->get_name(screen)); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] radeonsi: print the command line to VM fault reports (v2)
Obviously, the R-b applies to this rebased series as well. Nicolai On 01.08.2016 23:55, Marek Olšák wrote: From: Marek Olšák v2: rebase on top of Brian's commit --- src/gallium/drivers/radeonsi/si_debug.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index e030f48..ae11b2c 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -805,6 +805,7 @@ void si_check_vm_faults(struct r600_common_context *ctx, struct pipe_screen *screen = sctx->b.b.screen; FILE *f; uint32_t addr; + char cmd_line[4096]; if (!si_vm_fault_occured(sctx, &addr)) return; @@ -814,6 +815,8 @@ void si_check_vm_faults(struct r600_common_context *ctx, return; fprintf(f, "VM fault report.\n\n"); + if (os_get_command_line(cmd_line, sizeof(cmd_line))) + fprintf(f, "Command: %s\n", cmd_line); fprintf(f, "Driver vendor: %s\n", screen->get_vendor(screen)); fprintf(f, "Device vendor: %s\n", screen->get_device_vendor(screen)); fprintf(f, "Device name: %s\n\n", screen->get_name(screen)); ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] dri: use 'bool' instead 'int' for boolean variables
On 01.08.2016 15:21, Jan Ziak wrote:
Signed-off-by: Jan Ziak (http://atom-symbol.net) <0xe2.0x9a.0...@gmail.com>
---
src/egl/drivers/dri2/egl_dri2.h | 19 ++-
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 3 ++-
src/glx/dri3_priv.h | 5 +++--
src/loader/loader.c | 7 ---
src/loader/loader.h | 4 +++-
5 files changed, 22 insertions(+), 16 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 4577875..e406443 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -28,6 +28,7 @@
#ifndef EGL_DRI2_INCLUDED
#define EGL_DRI2_INCLUDED
+#include
#include
#ifdef HAVE_X11_PLATFORM
@@ -160,7 +161,7 @@ struct dri2_egl_display
int dri2_major;
int dri2_minor;
__DRIscreen *dri_screen;
- int own_dri_screen;
+ bool own_dri_screen;
const __DRIconfig **driver_configs;
void *driver;
const __DRIcoreExtension *core;
@@ -181,8 +182,8 @@ struct dri2_egl_display
* dri2_make_current (tracks if there are active contexts/surfaces). */
int ref_count;
- int own_device;
- int invalidate_available;
+ bool own_device;
+ bool invalidate_available;
int min_swap_interval;
int max_swap_interval;
int default_swap_interval;
@@ -201,7 +202,7 @@ struct dri2_egl_display
#ifdef HAVE_X11_PLATFORM
xcb_connection_t *conn;
int screen;
- int swap_available;
+ bool swap_available;
#ifdef HAVE_DRI3
struct loader_dri3_extensions loader_dri3_ext;
#endif
@@ -214,13 +215,13 @@ struct dri2_egl_display
struct wl_drm*wl_drm;
struct wl_shm*wl_shm;
struct wl_event_queue*wl_queue;
- int authenticated;
+ bool authenticated;
int formats;
uint32_t capabilities;
#endif
- int is_render_node;
- int is_different_gpu;
+ bool is_render_node;
+ bool is_different_gpu;
};
struct dri2_egl_context
@@ -244,7 +245,7 @@ struct dri2_egl_surface
__DRIdrawable *dri_drawable;
__DRIbuffer buffers[5];
int buffer_count;
- int have_fake_front;
+ bool have_fake_front;
#ifdef HAVE_X11_PLATFORM
xcb_drawable_t drawable;
@@ -282,7 +283,7 @@ struct dri2_egl_surface
#ifdef HAVE_DRM_PLATFORM
struct gbm_bo *bo;
#endif
- int locked;
+ boollocked;
int age;
} color_buffers[4], *back, *current;
#endif
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 493e645..7cb6c18 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -25,6 +25,7 @@
*
**/
+#include
#include
#include
@@ -627,7 +628,7 @@ vl_dri3_screen_create(Display *display, int screen)
xcb_dri3_open_reply_t *open_reply;
xcb_get_geometry_cookie_t geom_cookie;
xcb_get_geometry_reply_t *geom_reply;
- int is_different_gpu;
+ bool is_different_gpu;
int fd;
assert(display);
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 0822377..bfb0786 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -54,6 +54,7 @@
* Kristian Høgsberg (k...@redhat.com)
*/
+#include
#include
#include
#include
@@ -78,7 +79,7 @@ struct dri3_display
int dri3Minor;
/* Present bits */
- int hasPresent;
+ bool hasPresent;
int presentMajor;
int presentMinor;
};
@@ -101,7 +102,7 @@ struct dri3_screen {
void *driver;
int fd;
- int is_different_gpu;
+ bool is_different_gpu;
int show_fps_interval;
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 56ffc5d..a3b75c7 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -356,7 +356,7 @@ DRI_CONF_BEGIN
DRI_CONF_END;
#endif
-int loader_get_user_preferred_fd(int default_fd, int *different_device)
+int loader_get_user_preferred_fd(int default_fd, bool *different_device)
{
struct udev *udev;
#ifdef USE_DRICONF
@@ -365,7 +365,8 @@ int loader_get_user_preferred_fd(int default_fd, int
*different_device)
#endif
const char *dri_prime = getenv("DRI_PRIME");
char *prime = NULL;
- int is_different_device = 0, fd = default_fd;
+ bool is_different_device = 0;
It's a good change, but while you're at it, I'd change 0/1 to false/true
as well where the affected
Re: [Mesa-dev] [PATCH] ddebug: don't use fmemopen on non-Linux OS
Reviewed-by: Nicolai Hähnle
On 31.07.2016 22:57, Marek Olšák wrote:
From: Marek Olšák
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97140
---
src/gallium/drivers/ddebug/dd_draw.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/ddebug/dd_draw.c
b/src/gallium/drivers/ddebug/dd_draw.c
index 716208a..833454a 100644
--- a/src/gallium/drivers/ddebug/dd_draw.c
+++ b/src/gallium/drivers/ddebug/dd_draw.c
@@ -934,6 +934,7 @@ PIPE_THREAD_ROUTINE(dd_thread_pipelined_hang_detect, input)
static char *
dd_get_driver_shader_log(struct dd_context *dctx)
{
+#if defined(PIPE_OS_LINUX)
FILE *f;
char *buf;
int written_bytes;
@@ -970,6 +971,10 @@ dd_get_driver_shader_log(struct dd_context *dctx)
}
return buf;
+#else
+ /* Return an empty string. */
+ return (char*)calloc(1, 4);
+#endif
}
static void
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Re: [Mesa-dev] [PATCH 4/4] radeonsi: don't set the last parameter component of llvm.AMDGPU.cube
The series is
Reviewed-by: Nicolai Hähnle
On 31.07.2016 22:34, Marek Olšák wrote:
From: Marek Olšák
LLVM doesn't use it.
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index e7354de..d75311e 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -902,7 +902,7 @@ static void kil_emit(const struct lp_build_tgsi_action
*action,
}
static LLVMValueRef build_cube_intrinsic(struct gallivm_state *gallivm,
-LLVMValueRef in[4])
+LLVMValueRef in[3])
{
if (HAVE_LLVM >= 0x0309) {
LLVMTypeRef f32 = LLVMTypeOf(in[0]);
@@ -919,7 +919,13 @@ static LLVMValueRef build_cube_intrinsic(struct
gallivm_state *gallivm,
return lp_build_gather_values(gallivm, out, 4);
} else {
- LLVMValueRef vec = lp_build_gather_values(gallivm, in, 4);
+ LLVMValueRef c[4] = {
+ in[0],
+ in[1],
+ in[2],
+ LLVMGetUndef(LLVMTypeOf(in[0]))
+ };
+ LLVMValueRef vec = lp_build_gather_values(gallivm, c, 4);
return lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.cube",
LLVMTypeOf(vec), &vec, 1,
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Re: [Mesa-dev] [PATCH 0/3] RadeonSI GLSL "lit" tests
On 31.07.2016 22:29, Marek Olšák wrote: Inspired by LLVM, I created a small test suite that looks like "lit" tests, except that the input is GLSL and it verifies asm. The motivation was to verify that we generate optimal code when starting from GLSL. [PATCH 1/3] radeonsi: add environment variable SI_FORCE_FAMILY [PATCH 2/3] radeonsi: add a standalone compiler amdgcn_glslc [PATCH 3/3] radeonsi: add GLSL lit tests Good idea. Two comments: Please use .glsl or some such instead of .ll as a file extension. Those files are not LLVM IR. There's a `make check` in Mesa, which I readily admit to not using enough. There are r300_compiler_tests that are hooked up to it. Perhaps it's worth wiring that up? Apart from that, the series is Reviewed-by: Nicolai Hähnle Please review. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] nir: fix validation message
On Aug 2, 2016 2:46 AM, "Timothy Arceri"
wrote:
>
> Looks like a copy and paste error from f752effa087
Agreed. Rb
> Cc: Jason Ekstrand
> ---
> src/compiler/nir/nir_validate.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/compiler/nir/nir_validate.c
b/src/compiler/nir/nir_validate.c
> index 2d3f7a7..4182a68 100644
> --- a/src/compiler/nir/nir_validate.c
> +++ b/src/compiler/nir/nir_validate.c
> @@ -964,7 +964,7 @@ postvalidate_ssa_def(nir_ssa_def *def, void
*void_state)
> }
>
> if (def_state->uses->entries != 0) {
> - printf("extra entries in register uses:\n");
> + printf("extra entries in SSA def uses:\n");
>struct set_entry *entry;
>set_foreach(def_state->uses, entry)
> printf("%p\n", entry->key);
> @@ -979,7 +979,7 @@ postvalidate_ssa_def(nir_ssa_def *def, void
*void_state)
> }
>
> if (def_state->if_uses->entries != 0) {
> - printf("extra entries in register uses:\n");
> + printf("extra entries in SSA def uses:\n");
>struct set_entry *entry;
>set_foreach(def_state->if_uses, entry)
> printf("%p\n", entry->key);
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 12/12] gallium/radeon/winsyses: decrease max_alloc_size to 1/3 of largest heap
On Tue, Aug 2, 2016 at 4:55 AM, Marek Olšák wrote: > On Tue, Aug 2, 2016 at 3:13 AM, Michel Dänzer wrote: >> On 01.08.2016 16:35, Michel Dänzer wrote: >>> On 30.07.2016 06:42, Marek Olšák wrote: From: Marek Olšák This is controversial, but I don't see a better way out of this. Tonga has 2 GB of VRAM and 2 GB of GTT. amdgpu is not capable of submitting an IB referencing 1 GB of VRAM and 1 GB of GTT. The CS ioctl never succeeds even though it's far below the limits. Without this, "dEQP-GLES2.functional.color_clear.single_rgb" fails to submit an IB. With this, dEQP throws a framebuffer-incomplete exception and kills the process. IMO, failing the CS ioctl is worse for stability than failing big allocations. >>> >>> I can agree with that, but this change can't reliably prevent CS ioctl >>> failures: >>> >>> I believe the problem is mostly due to BOs which are pinned for scanout. >>> Since up to 6 CRTCs can scan out different buffers at any time, in the >>> worst case it may not be possible to place any BOs whose size is >= ~1/7 >>> of the VRAM size. >>> >>> At the end of the day, this needs to be solved in the kernel one way or >>> another. >> >> Or if you do want to avoid the problem in userspace for now, maybe use 1 >> / (number of CRTCs + 1) instead of hardcoding 1/3? > > I don't know. > > I could avoid the problem by splitting buffers into 128MB blocks > mapped into GPUVM consecutively, but that would prevent easy DMABUF > sharing and CPU mappings would not be consecutive. I think it could be fixed to a certain extent by handling migrations to/from vram iteratively rather than trying to move the whole buffer at once. E.g., we may have enough room in vram, but not enough contiguous gtt aperture or system pages to map the whole buffer to do the transfer in one shot. Alex ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 5/7] egl/android: Make get_fourcc() accept HAL formats
There are DRI_IMAGE_FOURCC macros, for which there are no corresponding
DRI_IMAGE_FORMAT macros. To support such formats we need to make the
lookup function take the native format directly. As a side effect, it
simplifies all existing calls to this function, because they all called
get_format() first to convert from native to DRI_IMAGE_FORMAT.
Signed-off-by: Tomasz Figa
---
src/egl/drivers/dri2/platform_android.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 5c35514..c8ea3ca 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -66,14 +66,15 @@ get_format_bpp(int native)
}
/* createImageFromFds requires fourcc format */
-static int get_fourcc(int format)
+static int get_fourcc(int native)
{
- switch(format) {
- case __DRI_IMAGE_FORMAT_RGB565: return __DRI_IMAGE_FOURCC_RGB565;
- case __DRI_IMAGE_FORMAT_ARGB: return __DRI_IMAGE_FOURCC_ARGB;
- case __DRI_IMAGE_FORMAT_XRGB: return __DRI_IMAGE_FOURCC_XRGB;
- case __DRI_IMAGE_FORMAT_ABGR: return __DRI_IMAGE_FOURCC_ABGR;
- case __DRI_IMAGE_FORMAT_XBGR: return __DRI_IMAGE_FOURCC_XBGR;
+ switch (native) {
+ case HAL_PIXEL_FORMAT_RGB_565: return __DRI_IMAGE_FOURCC_RGB565;
+ case HAL_PIXEL_FORMAT_BGRA_: return __DRI_IMAGE_FOURCC_ARGB;
+ case HAL_PIXEL_FORMAT_RGBA_: return __DRI_IMAGE_FOURCC_ABGR;
+ case HAL_PIXEL_FORMAT_RGBX_: return __DRI_IMAGE_FOURCC_XBGR;
+ default:
+ _eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", native);
}
return -1;
}
@@ -92,6 +93,7 @@ static int get_format(int format)
}
return -1;
}
+
static int
get_native_buffer_fd(struct ANativeWindowBuffer *buf)
{
@@ -424,7 +426,7 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
return -1;
}
- fourcc = get_fourcc(get_format(dri2_surf->buffer->format));
+ fourcc = get_fourcc(dri2_surf->buffer->format);
pitch = dri2_surf->buffer->stride *
get_format_bpp(dri2_surf->buffer->format);
@@ -510,7 +512,7 @@ static _EGLImage *
droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx,
struct ANativeWindowBuffer *buf, int fd)
{
- const int fourcc = get_fourcc(get_format(buf->format));
+ const int fourcc = get_fourcc(buf->format);
const int pitch = buf->stride * get_format_bpp(buf->format);
const EGLint attr_list[14] = {
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 4/7] egl/android: Refactor image creation to separate flink and prime paths (v2)
This patch splits current dri2_create_image_android_native_buffer() into
main entry point and two additional functions, one for creating an image
from flink name and one for handling prime FDs using the generic DMA-buf
path. This makes the code cleaner and also prepares for disabling flink
path more easily in the future.
v2: Split into separate patch.
Add error messages.
Signed-off-by: Tomasz Figa
---
src/egl/drivers/dri2/platform_android.c | 99 +++--
1 file changed, 57 insertions(+), 42 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 420436c..5c35514 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -507,53 +507,36 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp,
_EGLSurface *draw)
}
static _EGLImage *
-dri2_create_image_android_native_buffer(_EGLDisplay *disp,
-_EGLContext *ctx,
-struct ANativeWindowBuffer *buf)
+droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx,
+ struct ANativeWindowBuffer *buf, int fd)
{
- struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
- struct dri2_egl_image *dri2_img;
- int name, fd;
- int format;
-
- if (ctx != NULL) {
- /* From the EGL_ANDROID_image_native_buffer spec:
- *
- * * If is EGL_NATIVE_BUFFER_ANDROID and is not
- * EGL_NO_CONTEXT, the error EGL_BAD_CONTEXT is generated.
- */
- _eglError(EGL_BAD_CONTEXT, "eglCreateEGLImageKHR: for "
-"EGL_NATIVE_BUFFER_ANDROID, the context must be "
-"EGL_NO_CONTEXT");
- return NULL;
- }
+ const int fourcc = get_fourcc(get_format(buf->format));
+ const int pitch = buf->stride * get_format_bpp(buf->format);
+
+ const EGLint attr_list[14] = {
+ EGL_WIDTH, buf->width,
+ EGL_HEIGHT, buf->height,
+ EGL_LINUX_DRM_FOURCC_EXT, fourcc,
+ EGL_DMA_BUF_PLANE0_FD_EXT, fd,
+ EGL_DMA_BUF_PLANE0_PITCH_EXT, pitch,
+ EGL_DMA_BUF_PLANE0_OFFSET_EXT, 0,
+ EGL_NONE, 0
+ };
- if (!buf || buf->common.magic != ANDROID_NATIVE_BUFFER_MAGIC ||
- buf->common.version != sizeof(*buf)) {
- _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
+ if (fourcc == -1 || pitch == 0)
return NULL;
- }
- fd = get_native_buffer_fd(buf);
- if (fd >= 0) {
- const int fourcc = get_fourcc(get_format(buf->format));
- const int pitch = buf->stride * get_format_bpp(buf->format);
-
- const EGLint attr_list[14] = {
- EGL_WIDTH, buf->width,
- EGL_HEIGHT, buf->height,
- EGL_LINUX_DRM_FOURCC_EXT, fourcc,
- EGL_DMA_BUF_PLANE0_FD_EXT, fd,
- EGL_DMA_BUF_PLANE0_PITCH_EXT, pitch,
- EGL_DMA_BUF_PLANE0_OFFSET_EXT, 0,
- EGL_NONE, 0
- };
-
- if (fourcc == -1 || pitch == 0)
- return NULL;
+ return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
+}
- return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
- }
+static _EGLImage *
+droid_create_image_from_name(_EGLDisplay *disp, _EGLContext *ctx,
+ struct ANativeWindowBuffer *buf)
+{
+ struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
+ struct dri2_egl_image *dri2_img;
+ int name;
+ int format;
name = get_native_buffer_name(buf);
if (!name) {
@@ -594,6 +577,38 @@ dri2_create_image_android_native_buffer(_EGLDisplay *disp,
}
static _EGLImage *
+dri2_create_image_android_native_buffer(_EGLDisplay *disp,
+_EGLContext *ctx,
+struct ANativeWindowBuffer *buf)
+{
+ int fd;
+
+ if (ctx != NULL) {
+ /* From the EGL_ANDROID_image_native_buffer spec:
+ *
+ * * If is EGL_NATIVE_BUFFER_ANDROID and is not
+ * EGL_NO_CONTEXT, the error EGL_BAD_CONTEXT is generated.
+ */
+ _eglError(EGL_BAD_CONTEXT, "eglCreateEGLImageKHR: for "
+"EGL_NATIVE_BUFFER_ANDROID, the context must be "
+"EGL_NO_CONTEXT");
+ return NULL;
+ }
+
+ if (!buf || buf->common.magic != ANDROID_NATIVE_BUFFER_MAGIC ||
+ buf->common.version != sizeof(*buf)) {
+ _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
+ return NULL;
+ }
+
+ fd = get_native_buffer_fd(buf);
+ if (fd >= 0)
+ return droid_create_image_from_prime_fd(disp, ctx, buf, fd);
+
+ return droid_create_image_from_name(disp, ctx, buf);
+}
+
+static _EGLImage *
droid_create_image_khr(_EGLDriver *drv, _EGLDisplay *disp,
_EGLContext *ctx, EGLenum target,
EGLClientBuffer buffer, const EGLint *attr_list)
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 1/7] egl/android: Remove unused variables in droid_get_buffers_with_format()
Fix compilation warnings due to unused variables left after some earlier
code changes.
Signed-off-by: Tomasz Figa
---
src/egl/drivers/dri2/platform_android.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index e3d5f0b..124a30c 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -635,9 +635,6 @@ droid_get_buffers_with_format(__DRIdrawable * driDrawable,
int *out_count, void *loaderPrivate)
{
struct dri2_egl_surface *dri2_surf = loaderPrivate;
- struct dri2_egl_display *dri2_dpy =
- dri2_egl_display(dri2_surf->base.Resource.Display);
- int i;
if (update_buffers(dri2_surf) < 0)
return NULL;
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 3/7] egl/android: Fix support for pbuffers (v2)
From: Nicolas Boichat
Existing image loader code supports creating images only for window
surfaces. Moreover droid_create_surface() passes wrong surface type to
dri2_get_dri_config(), resulting in incorrect configs being returned for
pbuffers. This patch fixes these issues.
In addition, the config generation code is fixed to include single
buffered contexts required for pbuffers and make sure that generated
configs support only surfaces which can handle their supported buffering
modes.
v2: Return error only in case of real error condition and ignore requests
of unavailable buffers.
Improve coding style.
Signed-off-by: Nicolas Boichat
Signed-off-by: Tomasz Figa
---
src/egl/drivers/dri2/egl_dri2.h | 1 +
src/egl/drivers/dri2/platform_android.c | 64 +
2 files changed, 50 insertions(+), 15 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 4577875..3da6bef 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -291,6 +291,7 @@ struct dri2_egl_surface
struct ANativeWindow *window;
struct ANativeWindowBuffer *buffer;
__DRIimage *dri_image;
+ __DRIimage *dri_front_image;
/* EGL-owned buffers */
__DRIbuffer *local_buffers[__DRI_BUFFER_COUNT];
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index d78c06d..420436c 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -286,7 +286,7 @@ droid_create_surface(_EGLDriver *drv, _EGLDisplay *disp,
EGLint type,
window->query(window, NATIVE_WINDOW_HEIGHT, &dri2_surf->base.Height);
}
- config = dri2_get_dri_config(dri2_conf, EGL_WINDOW_BIT,
+ config = dri2_get_dri_config(dri2_conf, type,
dri2_surf->base.GLColorspace);
if (!config)
goto cleanup_surface;
@@ -347,6 +347,9 @@ droid_destroy_surface(_EGLDriver *drv, _EGLDisplay *disp,
_EGLSurface *surf)
dri2_surf->window->common.decRef(&dri2_surf->window->common);
}
+ if (dri2_surf->dri_front_image)
+ dri2_dpy->image->destroyImage(dri2_surf->dri_front_image);
+
(*dri2_dpy->core->destroyDrawable)(dri2_surf->dri_drawable);
free(dri2_surf);
@@ -378,6 +381,27 @@ update_buffers(struct dri2_egl_surface *dri2_surf)
}
static int
+get_front_bo(struct dri2_egl_surface *dri2_surf, unsigned int format)
+{
+ struct dri2_egl_display *dri2_dpy =
+ dri2_egl_display(dri2_surf->base.Resource.Display);
+
+ if (dri2_surf->base.Type == EGL_WINDOW_BIT)
+ return 0;
+
+ if (dri2_surf->dri_front_image)
+ return 0;
+
+ dri2_surf->dri_front_image =
+ dri2_dpy->image->createImage(dri2_dpy->dri_screen,
+ dri2_surf->base.Width,
+ dri2_surf->base.Height,
+ format, 0, dri2_surf);
+
+ return dri2_surf->dri_front_image ? 0 : -1;
+}
+
+static int
get_back_bo(struct dri2_egl_surface *dri2_surf)
{
struct dri2_egl_display *dri2_dpy =
@@ -385,6 +409,9 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
int fourcc, pitch;
int offset = 0, fd;
+ if (dri2_surf->base.Type != EGL_WINDOW_BIT)
+ return 0;
+
if (dri2_surf->dri_image)
return 0;
@@ -440,11 +467,12 @@ droid_image_get_buffers(__DRIdrawable *driDrawable,
return 0;
if (buffer_mask & __DRI_IMAGE_BUFFER_FRONT) {
- /*
- * We don't support front buffers and GLES doesn't require them for
- * window surfaces, but some DRI drivers will request them anyway.
- * We just ignore such request as other platforms backends do.
- */
+ if (get_front_bo(dri2_surf, format) < 0)
+ return 0;
+
+ images->front = dri2_surf->dri_front_image;
+ if (images->front)
+ images->image_mask |= __DRI_IMAGE_BUFFER_FRONT;
}
if (buffer_mask & __DRI_IMAGE_BUFFER_BACK) {
@@ -452,7 +480,8 @@ droid_image_get_buffers(__DRIdrawable *driDrawable,
return 0;
images->back = dri2_surf->dri_image;
- images->image_mask |= __DRI_IMAGE_BUFFER_BACK;
+ if (images->back)
+ images->image_mask |= __DRI_IMAGE_BUFFER_BACK;
}
return 1;
@@ -696,14 +725,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay
*dpy)
for (j = 0; dri2_dpy->driver_configs[j]; j++) {
const EGLint surface_type = EGL_WINDOW_BIT | EGL_PBUFFER_BIT;
struct dri2_egl_config *dri2_conf;
- unsigned int double_buffered = 0;
-
- dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[j],
-__DRI_ATTRIB_DOUBLE_BUFFER, &double_buffered);
-
- /* support only double buffered configs */
- if (!double_buffered)
-continue;
dri2_conf = dri2_add_config(dpy, dri2_dpy->driver_configs[j],
count + 1, surface_type, config_attrs, visuals[i].rgba_masks);
@@
[Mesa-dev] [PATCH v2 6/7] egl/android: Add support for YV12 pixel format (v2)
This patch adds support for YV12 pixel format to the Android platform
backend. Only creating EGL images is supported, it is not added to the
list of available visuals.
v2: Use const array defined just for YV12 instead of trying to be overly
generic.
Signed-off-by: Tomasz Figa
Signed-off-by: Kalyan Kondapally
---
src/egl/drivers/dri2/platform_android.c | 56 +
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index c8ea3ca..1768724 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -40,6 +40,8 @@
#include "egl_dri2_fallbacks.h"
#include "gralloc_drm.h"
+#define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1))
+
static int
get_format_bpp(int native)
{
@@ -57,6 +59,9 @@ get_format_bpp(int native)
case HAL_PIXEL_FORMAT_RGB_565:
bpp = 2;
break;
+ case HAL_PIXEL_FORMAT_YV12:
+ bpp = 1;
+ break;
default:
bpp = 0;
break;
@@ -73,6 +78,7 @@ static int get_fourcc(int native)
case HAL_PIXEL_FORMAT_BGRA_: return __DRI_IMAGE_FOURCC_ARGB;
case HAL_PIXEL_FORMAT_RGBA_: return __DRI_IMAGE_FOURCC_ABGR;
case HAL_PIXEL_FORMAT_RGBX_: return __DRI_IMAGE_FOURCC_XBGR;
+ case HAL_PIXEL_FORMAT_YV12: return __DRI_IMAGE_FOURCC_YVU420;
default:
_eglLog(_EGL_WARNING, "unsupported native buffer format 0x%x", native);
}
@@ -512,22 +518,60 @@ static _EGLImage *
droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx,
struct ANativeWindowBuffer *buf, int fd)
{
+ unsigned int offsets[3] = { 0, 0, 0 };
+ unsigned int pitches[3] = { 0, 0, 0 };
+
const int fourcc = get_fourcc(buf->format);
- const int pitch = buf->stride * get_format_bpp(buf->format);
+ if (fourcc == -1) {
+ _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
+ return NULL;
+ }
- const EGLint attr_list[14] = {
+ pitches[0] = buf->stride * get_format_bpp(buf->format);
+ if (pitches[0] == 0) {
+ _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR");
+ return NULL;
+ }
+
+ switch (buf->format) {
+ case HAL_PIXEL_FORMAT_YV12:
+ /* Y plane is assumed to be at offset 0. */
+ /* Cr plane is located after Y plane */
+ offsets[1] = offsets[0] + pitches[0] * buf->height;
+ pitches[1] = ALIGN(pitches[0] / 2, 16);
+ /* Cb plane is located after Cr plane */
+ offsets[2] = offsets[1] + pitches[1] * buf->height / 2;
+ pitches[2] = pitches[1];
+
+ const EGLint attr_list_yv12[] = {
+ EGL_WIDTH, buf->width,
+ EGL_HEIGHT, buf->height,
+ EGL_LINUX_DRM_FOURCC_EXT, fourcc,
+ EGL_DMA_BUF_PLANE0_FD_EXT, fd,
+ EGL_DMA_BUF_PLANE0_PITCH_EXT, pitches[0],
+ EGL_DMA_BUF_PLANE0_OFFSET_EXT, offsets[0],
+ EGL_DMA_BUF_PLANE1_FD_EXT, fd,
+ EGL_DMA_BUF_PLANE1_PITCH_EXT, pitches[1],
+ EGL_DMA_BUF_PLANE1_OFFSET_EXT, offsets[1],
+ EGL_DMA_BUF_PLANE2_FD_EXT, fd,
+ EGL_DMA_BUF_PLANE2_PITCH_EXT, pitches[2],
+ EGL_DMA_BUF_PLANE2_OFFSET_EXT, offsets[2],
+ EGL_NONE, 0
+ };
+
+ return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list_yv12);
+ }
+
+ const EGLint attr_list[] = {
EGL_WIDTH, buf->width,
EGL_HEIGHT, buf->height,
EGL_LINUX_DRM_FOURCC_EXT, fourcc,
EGL_DMA_BUF_PLANE0_FD_EXT, fd,
- EGL_DMA_BUF_PLANE0_PITCH_EXT, pitch,
+ EGL_DMA_BUF_PLANE0_PITCH_EXT, pitches[0],
EGL_DMA_BUF_PLANE0_OFFSET_EXT, 0,
EGL_NONE, 0
};
- if (fourcc == -1 || pitch == 0)
- return NULL;
-
return dri2_create_image_dma_buf(disp, ctx, NULL, attr_list);
}
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 7/7] egl/android: Make drm_gralloc headers optional (v2)
Make the code at least compile when being built without drm_gralloc
headers.
v2: Replaced #ifdefs with stubs for gralloc_drm_get_gem_handle()
and GRALLOC_MODULE_PERFORM_GET_DRM_FD.
Removed explicit render node probing code.
Signed-off-by: Tomasz Figa
---
src/egl/Android.mk | 1 +
src/egl/Makefile.am| 4 ++-
src/egl/drivers/dri2/egl_dri2.h| 2 +-
src/egl/drivers/dri2/platform_android.c| 2 +-
.../drivers/dri2/platform_android_gralloc_drm.h| 41 ++
5 files changed, 47 insertions(+), 3 deletions(-)
create mode 100644 src/egl/drivers/dri2/platform_android_gralloc_drm.h
diff --git a/src/egl/Android.mk b/src/egl/Android.mk
index bfd56a7..72ec02a 100644
--- a/src/egl/Android.mk
+++ b/src/egl/Android.mk
@@ -41,6 +41,7 @@ LOCAL_SRC_FILES := \
LOCAL_CFLAGS := \
-D_EGL_NATIVE_PLATFORM=_EGL_PLATFORM_ANDROID \
-D_EGL_BUILT_IN_DRIVER_DRI2 \
+ -DHAS_GRALLOC_DRM_HEADERS \
-DHAVE_ANDROID_PLATFORM
LOCAL_C_INCLUDES := \
diff --git a/src/egl/Makefile.am b/src/egl/Makefile.am
index 95ee6cc..e6ed8e6 100644
--- a/src/egl/Makefile.am
+++ b/src/egl/Makefile.am
@@ -86,7 +86,9 @@ endif
if HAVE_EGL_PLATFORM_ANDROID
AM_CFLAGS += -DHAVE_ANDROID_PLATFORM
-dri2_backend_FILES += drivers/dri2/platform_android.c
+dri2_backend_FILES += \
+ drivers/dri2/platform_android.c \
+ drivers/dri2/egl_dri2_drm_gralloc.h
endif
if HAVE_EGL_DRIVER_DRI2
diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 3da6bef..14c1e05 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -64,8 +64,8 @@
# include
#endif
+#include "platform_android_gralloc_drm.h"
#include
-#include
#include
#endif /* HAVE_ANDROID_PLATFORM */
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 1768724..49a9eb0 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -38,7 +38,7 @@
#include "loader.h"
#include "egl_dri2.h"
#include "egl_dri2_fallbacks.h"
-#include "gralloc_drm.h"
+#include "platform_android_gralloc_drm.h"
#define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1))
diff --git a/src/egl/drivers/dri2/platform_android_gralloc_drm.h
b/src/egl/drivers/dri2/platform_android_gralloc_drm.h
new file mode 100644
index 000..6757d1b
--- /dev/null
+++ b/src/egl/drivers/dri2/platform_android_gralloc_drm.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2016 Google Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#pragma once
+
+#ifdef HAS_GRALLOC_DRM_HEADERS
+
+#include
+#include
+
+#else
+
+#define GRALLOC_MODULE_PERFORM_GET_DRM_FD 0x0FD4DEAD
+
+static inline int gralloc_drm_get_gem_handle(buffer_handle_t handle)
+{
+ return 0; /* Not supported, return invalid handle. */
+}
+
+#endif
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 2/7] egl/android: Respect buffer mask in droid_image_get_buffers (v2)
Drivers can request different set of buffers depending on the buffer
mask they pass to the get_buffers callback. This patch makes
droid_image_get_buffers() respect this mask.
v2: Return error only in case of real error condition and ignore requests
of unavailable buffers.
Signed-off-by: Tomasz Figa
---
src/egl/drivers/dri2/platform_android.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 124a30c..d78c06d 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -434,16 +434,26 @@ droid_image_get_buffers(__DRIdrawable *driDrawable,
{
struct dri2_egl_surface *dri2_surf = loaderPrivate;
+ images->image_mask = 0;
+
if (update_buffers(dri2_surf) < 0)
return 0;
- if (get_back_bo(dri2_surf) < 0) {
- _eglError(EGL_BAD_PARAMETER, "get_back_bo");
- return 0;
+ if (buffer_mask & __DRI_IMAGE_BUFFER_FRONT) {
+ /*
+ * We don't support front buffers and GLES doesn't require them for
+ * window surfaces, but some DRI drivers will request them anyway.
+ * We just ignore such request as other platforms backends do.
+ */
}
- images->image_mask = __DRI_IMAGE_BUFFER_BACK;
- images->back = dri2_surf->dri_image;
+ if (buffer_mask & __DRI_IMAGE_BUFFER_BACK) {
+ if (get_back_bo(dri2_surf) < 0)
+ return 0;
+
+ images->back = dri2_surf->dri_image;
+ images->image_mask |= __DRI_IMAGE_BUFFER_BACK;
+ }
return 1;
}
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 0/7] egl/android: Improve the Android EGL backend
Hi, This series is a collection of various fixes and extensions we came up with during our attempt to use Mesa for Android. Fixes included in this series: - fixed multiple issues with handling pbuffers in the backend, - made the implementation of DRI image loader .getBuffers callback conform better to the extension semantics. New features added by this series: - possibility to build the Android EGL platform without drm_gralloc headers, - support for creating EGL images from Android native buffers with YV12 pixel format (prime-only). On top of that, a number of refactoring changes to clean things up a bit. Testing was done using classic i965 (gen 8) and gallium softpipe drivers on an internal build of Android, based on gralloc backed by a DRM render node and sharing buffers by PRIME FDs. v2: Dropped following already applied patches: egl/android: Check return value of dri2_get_dri_config() egl/android: Add some useful error messages egl/android: Stop leaking DRI images Dropped following patches, which need further discussion: egl/android: Set EGL_MAX_PBUFFER_WIDTH and EGL_MAX_PBUFFER_HEIGHT egl/android: Add fallback to kms_swrast driver Fixed handling of unavailable buffers in image loader. Removed explicit render node probing code. Addressed style problems. Split some refactoring changes into separate patches. Removed few more unused variables missed before. Nicolas Boichat (1): egl/android: Fix support for pbuffers Tomasz Figa (6): egl/android: Remove unused variables in droid_get_buffers_with_format() egl/android: Respect buffer mask in droid_image_get_buffers egl/android: Refactor image creation to separate flink and prime paths egl/android: Make get_fourcc() accept HAL formats egl/android: Add support for YV12 pixel format egl/android: Make drm_gralloc headers optional src/egl/Android.mk | 1 + src/egl/Makefile.am| 4 +- src/egl/drivers/dri2/egl_dri2.h| 3 +- src/egl/drivers/dri2/platform_android.c| 212 +++-- .../drivers/dri2/platform_android_gralloc_drm.h| 41 5 files changed, 204 insertions(+), 57 deletions(-) create mode 100644 src/egl/drivers/dri2/platform_android_gralloc_drm.h -- 2.8.0.rc3.226.g39d4020 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 1/4] gallium/winsys/kms: Fix double refcount when importing from prime FD (v2)
Currently the code creates a display target struct with refcount field
initialized to 1 and then the caller again increments it, leading to
a leaked reference. Let's remove the unnecessary increment.
v2: Split from one big patch into four fixing one thing at a time.
Signed-off-by: Tomasz Figa
CC:
---
src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
index 21ac0d7..0585fcc 100644
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -276,7 +276,6 @@ kms_sw_displaytarget_from_handle(struct sw_winsys *ws,
case DRM_API_HANDLE_TYPE_FD:
kms_sw_dt = kms_sw_displaytarget_add_from_prime(kms_sw, whandle->handle);
if (kms_sw_dt) {
- kms_sw_dt->ref_count++;
kms_sw_dt->width = templ->width0;
kms_sw_dt->height = templ->height0;
kms_sw_dt->stride = whandle->stride;
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 0/4] gallium/winsys/kms: Fix issues with prime import
Current prime import code in kms-dri Gallium winsys backend has several issues: - It leaks imported buffers, because of duplicate reference count increment at import time. - It does not check whether an already imported (or local) buffer is not being imported, which is problematic because prime import always returns the same GEM handle for the same buffer and we end up creating duplicate structs referencing the same handle. This series is an attempt to fix these problems. It originated from [PATCH] gallium/sw/kms: Fix multiple imports from PRIME FDs (https://patchwork.freedesktop.org/patch/98856/) and so they patches inside are considered to be v2. Tomasz Figa (4): gallium/winsys/kms: Fix double refcount when importing from prime FD (v2) gallium/winsys/kms: Fully initialize kms_sw_dt at prime import time (v2) gallium/winsys/kms: Move display target handle lookup to separate function (v2) gallium/winsys/kms: Look up the GEM handle after importing a prime FD (v2) src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 56 --- 1 file changed, 39 insertions(+), 17 deletions(-) -- 2.8.0.rc3.226.g39d4020 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 4/4] gallium/winsys/kms: Look up the GEM handle after importing a prime FD (v2)
drmPrimeHandleToFD() will return the same GEM handle every time the same buffer is imported, even from a different prime FD. Since GEM handles are not reference counted, we need to make sure that each GEM handle is referenced only by one display target struct, by looking it up in kms_sw->bo_list first and bumping the refcount of the found dt on hit and falling back to creating a new dt only on miss. v2: Split into separate function. Use helper function for lookup. Signed-off-by: Tomasz Figa CC: --- src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c index cb02b22..4ee2696 100644 --- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c +++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c @@ -244,6 +244,10 @@ kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys *kms_sw, int fd, if (ret) return NULL; + kms_sw_dt = kms_sw_displaytarget_lookup(kms_sw, handle); + if (kms_sw_dt) + return kms_sw_dt; + kms_sw_dt = CALLOC_STRUCT(kms_sw_displaytarget); if (!kms_sw_dt) return NULL; -- 2.8.0.rc3.226.g39d4020 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2 2/4] gallium/winsys/kms: Fully initialize kms_sw_dt at prime import time (v2)
Currently kms_sw_displaytarget_add_from_prime() allocates the struct and
fills in only some of the fields, resulting in a half-baked struct that
needs to be further completed by the caller. To make this a bit more
consistent, pass width, height and stride to this function and fill in
everything there, so that caller can take the returned struct as is.
v2: Split from one big patch into four fixing one thing at a time.
Signed-off-by: Tomasz Figa
CC:
---
src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
index 0585fcc..65dbf70 100644
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -211,7 +211,9 @@ kms_sw_displaytarget_map(struct sw_winsys *ws,
}
static struct kms_sw_displaytarget *
-kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys *kms_sw, int fd)
+kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys *kms_sw, int fd,
+unsigned width, unsigned height,
+unsigned stride)
{
uint32_t handle = -1;
struct kms_sw_displaytarget * kms_sw_dt;
@@ -229,6 +231,9 @@ kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys
*kms_sw, int fd)
kms_sw_dt->ref_count = 1;
kms_sw_dt->handle = handle;
kms_sw_dt->size = lseek(fd, 0, SEEK_END);
+ kms_sw_dt->width = width;
+ kms_sw_dt->height = height;
+ kms_sw_dt->stride = stride;
if (kms_sw_dt->size == (off_t)-1) {
FREE(kms_sw_dt);
@@ -274,13 +279,12 @@ kms_sw_displaytarget_from_handle(struct sw_winsys *ws,
switch(whandle->type) {
case DRM_API_HANDLE_TYPE_FD:
- kms_sw_dt = kms_sw_displaytarget_add_from_prime(kms_sw, whandle->handle);
- if (kms_sw_dt) {
- kms_sw_dt->width = templ->width0;
- kms_sw_dt->height = templ->height0;
- kms_sw_dt->stride = whandle->stride;
+ kms_sw_dt = kms_sw_displaytarget_add_from_prime(kms_sw, whandle->handle,
+ templ->width0,
+ templ->height0,
+ whandle->stride);
+ if (kms_sw_dt)
*stride = kms_sw_dt->stride;
- }
return (struct sw_displaytarget *)kms_sw_dt;
case DRM_API_HANDLE_TYPE_KMS:
LIST_FOR_EACH_ENTRY(kms_sw_dt, &kms_sw->bo_list, link) {
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH v2 3/4] gallium/winsys/kms: Move display target handle lookup to separate function (v2)
As a preparation to use the lookup in more than once place, move the
code that looks up given KMS/GEM handle to a separate function. This
change should not introduce any functional changes.
v2: Split into separate patch.
Move lookup code into separate function.
Signed-off-by: Tomasz Figa
CC:
---
src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 33 ---
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
index 65dbf70..cb02b22 100644
--- a/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
+++ b/src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c
@@ -211,6 +211,26 @@ kms_sw_displaytarget_map(struct sw_winsys *ws,
}
static struct kms_sw_displaytarget *
+kms_sw_displaytarget_lookup(struct kms_sw_winsys *kms_sw,
+unsigned int kms_handle)
+{
+ struct kms_sw_displaytarget *kms_sw_dt;
+
+ LIST_FOR_EACH_ENTRY(kms_sw_dt, &kms_sw->bo_list, link) {
+ if (kms_sw_dt->handle == kms_handle) {
+ kms_sw_dt->ref_count++;
+
+ DEBUG_PRINT("KMS-DEBUG: imported buffer %u (size %u)\n",
+ kms_sw_dt->handle, kms_sw_dt->size);
+
+ return kms_sw_dt;
+ }
+ }
+
+ return NULL;
+}
+
+static struct kms_sw_displaytarget *
kms_sw_displaytarget_add_from_prime(struct kms_sw_winsys *kms_sw, int fd,
unsigned width, unsigned height,
unsigned stride)
@@ -287,15 +307,10 @@ kms_sw_displaytarget_from_handle(struct sw_winsys *ws,
*stride = kms_sw_dt->stride;
return (struct sw_displaytarget *)kms_sw_dt;
case DRM_API_HANDLE_TYPE_KMS:
- LIST_FOR_EACH_ENTRY(kms_sw_dt, &kms_sw->bo_list, link) {
- if (kms_sw_dt->handle == whandle->handle) {
-kms_sw_dt->ref_count++;
-
-DEBUG_PRINT("KMS-DEBUG: imported buffer %u (size %u)\n",
kms_sw_dt->handle, kms_sw_dt->size);
-
-*stride = kms_sw_dt->stride;
-return (struct sw_displaytarget *)kms_sw_dt;
- }
+ kms_sw_dt = kms_sw_displaytarget_lookup(kms_sw, whandle->handle);
+ if (kms_sw_dt) {
+ *stride = kms_sw_dt->stride;
+ return (struct sw_displaytarget *)kms_sw_dt;
}
/* fallthrough */
default:
--
2.8.0.rc3.226.g39d4020
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[Mesa-dev] [PATCH] radeonsi: skip unnecessary si_update_shaders calls
From: Marek Olšák
Small decrease in draw call overhead.
---
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state.c | 6 ++
src/gallium/drivers/radeonsi/si_state_draw.c| 20 +---
src/gallium/drivers/radeonsi/si_state_shaders.c | 7 +++
4 files changed, 27 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index c4f7a1c..55f8965 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -259,6 +259,7 @@ struct si_context {
struct si_vertex_element*vertex_elements;
unsignedsprite_coord_enable;
boolflatshade;
+ booldo_update_shaders;
/* shader descriptors */
struct si_descriptors vertex_buffers;
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index c5b61e9..47fc7a0 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -572,6 +572,7 @@ static void si_bind_blend_state(struct pipe_context *ctx,
void *state)
struct si_context *sctx = (struct si_context *)ctx;
si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
si_mark_atom_dirty(sctx, &sctx->cb_render_state);
+ sctx->do_update_shaders = true;
}
static void si_delete_blend_state(struct pipe_context *ctx, void *state)
@@ -869,6 +870,7 @@ static void si_bind_rs_state(struct pipe_context *ctx, void
*state)
si_update_poly_offset_state(sctx);
si_mark_atom_dirty(sctx, &sctx->clip_regs);
+ sctx->do_update_shaders = true;
}
static void si_delete_rs_state(struct pipe_context *ctx, void *state)
@@ -1018,6 +1020,7 @@ static void si_bind_dsa_state(struct pipe_context *ctx,
void *state)
sctx->stencil_ref.dsa_part = dsa->stencil_ref;
si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
}
+ sctx->do_update_shaders = true;
}
static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
@@ -2388,6 +2391,7 @@ static void si_set_framebuffer_state(struct pipe_context
*ctx,
}
sctx->need_check_render_feedback = true;
+ sctx->do_update_shaders = true;
}
static void si_emit_framebuffer_state(struct si_context *sctx, struct
r600_atom *atom)
@@ -2628,6 +2632,7 @@ static void si_set_min_samples(struct pipe_context *ctx,
unsigned min_samples)
return;
sctx->ps_iter_samples = min_samples;
+ sctx->do_update_shaders = true;
if (sctx->framebuffer.nr_samples > 1)
si_mark_atom_dirty(sctx, &sctx->msaa_config);
@@ -3267,6 +3272,7 @@ static void si_bind_vertex_elements(struct pipe_context
*ctx, void *state)
sctx->vertex_elements = v;
sctx->vertex_buffers_dirty = true;
+ sctx->do_update_shaders = true;
}
static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 2db2b0b..d743e22 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -867,7 +867,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
struct si_context *sctx = (struct si_context *)ctx;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
struct pipe_index_buffer ib = {};
- unsigned mask, dirty_fb_counter, dirty_tex_counter;
+ unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
if (!info->count && !info->indirect &&
(info->indexed || !info->count_from_stream_output))
@@ -911,15 +911,21 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
* draw_vbo recursively, and before si_update_shaders, which uses
* current_rast_prim for this draw_vbo call. */
if (sctx->gs_shader.cso)
- sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
+ rast_prim = sctx->gs_shader.cso->gs_output_prim;
else if (sctx->tes_shader.cso)
- sctx->current_rast_prim =
-
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
else
- sctx->current_rast_prim = info->mode;
+ rast_prim = info->mode;
- if (!si_update_shaders(sctx) ||
- !si_upload_graphics_shader_descriptors(sctx))
+ if (rast_prim != sctx->current_rast_prim) {
+ sctx->current_rast_prim = rast_prim;
+ sctx->do_update_shaders = true;
+ }
+
+ if (sctx->do_update_shaders && !si_update_shaders(sctx))
+
Re: [Mesa-dev] [PATCH 0/8] RadeonSI: Unflushed fences for better Bioshock performance
On Tue, Aug 2, 2016 at 12:27 PM, Marek Olšák wrote: > Hi, > > Most interested people already know what this is, so I'm just gonna share the > performance numbers here. > > This series makes Bioshock Infinite 23% faster. Along with the CPU overhead > optimizations that are in the master branch already, the combined improvement > is more than 40%. BTW, 23% is for amdgpu. It's more than 23% on radeon because of how inefficiently it implements fences. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/8] gallium/radeon: add cs_get_next_fence winsys callback
From: Marek Olšák
---
src/gallium/drivers/radeon/radeon_winsys.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 3be4738..e7787d3 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -732,6 +732,13 @@ struct radeon_winsys {
struct pipe_fence_handle **fence);
/**
+ * Create a fence before the CS is flushed.
+ * The user must flush manually to complete the initializaton of the fence.
+ * The fence must not be used before the flush.
+ */
+struct pipe_fence_handle *(*cs_get_next_fence)(struct radeon_winsys_cs
*cs);
+
+/**
* Return true if a buffer is referenced by a command stream.
*
* \param csA command stream.
--
2.7.4
___
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