[Mesa-dev] [Bug 98245] GLES3.1 link negative dEQP "expected linking to fail, but passed."

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98245

--- Comment #2 from Iago Toral  ---
(In reply to Iago Toral from comment #1)
> These seem to be two different issues so I think it is probably best to
> create two different bug reports.
> 
> I have sent a patch for review that fixes the first one:
> https://lists.freedesktop.org/archives/mesa-dev/2016-October/132896.html

This patch is now in master:

commit 537dce06ec8e0fa4becd42d5e4b3d07cf722387f
Author: Iago Toral Quiroga 
Date:   Fri Oct 21 13:15:41 2016 +0200

glsl: add matrix layout information to interface block types

So far we have been checking that interface block definitions had matching
matrix layouts by comparing the definitions of their fields, however, this
does not cover the case where the interface blocks are defined with
mismatching matrix layouts but don't define any field with a matrix type.
In this case Mesa will not fail to link because none of the fields will
inherit the mismatching layout qualifier.

This patch fixes the problem in the same way we fixed it for packing layout
information: we add the the layout information to the interface type and
then
we check it matches during the uniform block linking process.

v2: Fix unit tests so they pass the new parameter to
glsl_type::get_interface_instance()

Fixes:
   
dEQP-GLES31.functional.shaders.linkage.uniform.block.layout_qualifier_mismatch_3

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98245
Reviewed-by: Nicolai Hähnle  (v1)

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[Mesa-dev] [Bug 98134] dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.draw_buffers wants a different GL error code

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98134

Tapani Pälli  changed:

   What|Removed |Added

 Status|ASSIGNED|RESOLVED
 Resolution|--- |FIXED

--- Comment #4 from Tapani Pälli  ---
commit a1652a059edc5a5f0f4b0836ba310a22e094bd85
Author: Tapani Pälli 
Date:   Fri Oct 7 10:08:21 2016 +0300

mesa: fix error handling in DrawBuffers

Patch rearranges error checking so that enum checking provided via
destmask happens before other checks. It needs to be done in this
order because other error checks do not work properly if there were
invalid enums passed.

Patch also refines one existing check and it's documentation to match
GLES 3.0 spec (also in later specs). This was somewhat mysteriously
referring to desktop GL but had a check for gles3.

Fixes following dEQP tests:

  
dEQP-GLES31.functional.debug.negative_coverage.get_error.buffer.draw_buffers

no CI regressions observed.

Signed-off-by: Tapani Pälli 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98134
Cc: "12.0 13.0" 
Reviewed-by: Emil Velikov 

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[Mesa-dev] [Bug 97524] Samplers referring to the same texture unit with different types should raise GL_INVALID_OPERATION

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=97524

--- Comment #11 from Tapani Pälli  ---
> All other GPU drivers I tested with handle this gracefully by raising a
> GL_INVALID_OPERATION error and continuing rendering the rest normally.

For which command in the sample program should GL_INVALID_OPERATION happen? I
remember the check for sampler conflict is done for glValidateProgram but TBH
I'm not quite sure where this error should happen in the supplied case.

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[Mesa-dev] [Bug 98345] dEQP EGL: negative test failed w/ invalid return

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98345

Tapani Pälli  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|ASSIGNED|RESOLVED

--- Comment #2 from Tapani Pälli  ---
commit 282b87dd03317ff39eb409b0ac2cbdc17d7e5aa3
Author: Tapani Pälli 
Date:   Thu Oct 20 13:51:40 2016 +0300

egl: fix type mismatch error type in _eglInitSurface

EGL spec defines EGL_BAD_MATCH for windows, pixmaps and pbuffers in
case where user creates a surface but config does not support rendering
to such surface type.

Following quotes are from EGL 1.5 spec 3.5 "Rendering Surfaces" :

for eglCreatePlatformWindowSurface, eglCreateWindowSurface:

   "If config does not support rendering to windows (the EGL_SURFACE_TYPE
   attribute does not contain EGL_WINDOW_BIT ), an EGL_BAD_MATCH error is
   generated."

for eglCreatePbufferSurface:

   "If config does not support pbuffers, an EGL_BAD_MATCH error is
   generated."

for eglCreatePlatformPixmapSurface, eglCreatePixmapSurface:

   "If config does not support rendering to pixmaps (the EGL_SURFACE_TYPE
   attribute does not contain EGL_PIXMAP_BIT ), an EGL_BAD_MATCH error is
   generated."

Fixes following dEQP test:

   dEQP-EGL.functional.negative_api.create_pbuffer_surface

Signed-off-by: Tapani Pälli 
Reviewed-by: Eric Engestrom 

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[Mesa-dev] [PATCH v2 4/6] i965/blit: Break blits into chunks in set_alpha_to_one

[Jason Ekstrand]

v2: Properly handle linear blit alignment restrictions

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 88 --
 1 file changed, 73 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index bc97e66..02a1fd9 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -179,6 +179,42 @@ intel_miptree_blit_compatible_formats(mesa_format src, 
mesa_format dst)
return false;
 }
 
+static void
+get_blit_intratile_offset_el(const struct brw_context *brw,
+ struct intel_mipmap_tree *mt,
+ uint32_t total_x_offset_el,
+ uint32_t total_y_offset_el,
+ uint32_t *base_address_offset,
+ uint32_t *x_offset_el,
+ uint32_t *y_offset_el)
+{
+   enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
+   isl_tiling_get_intratile_offset_el(>isl_dev,
+  tiling, mt->cpp, mt->pitch,
+  total_x_offset_el, total_y_offset_el,
+  base_address_offset,
+  x_offset_el, y_offset_el);
+   if (tiling == ISL_TILING_LINEAR) {
+  /* From the Broadwell PRM docs for XY_SRC_COPY_BLT::SourceBaseAddress:
+   *
+   *"Base address of the destination surface: X=0, Y=0. Lower 32bits
+   *of the 48bit addressing. When Src Tiling is enabled (Bit_15
+   *enabled), this address must be 4KB-aligned. When Tiling is not
+   *enabled, this address should be CL (64byte) aligned."
+   *
+   * The offsets we get from ISL in the tiled case are already aligned.
+   * In the linear case, we need to do some of our own aligning.
+   */
+  assert(mt->pitch % 64 == 0);
+  uint32_t delta = *base_address_offset & 63;
+  assert(delta % mt->cpp == 0);
+  *base_address_offset -= delta;
+  *x_offset_el += delta / mt->cpp;
+   } else {
+  assert(*base_address_offset % 4096 == 0);
+   }
+}
+
 /**
  * Implements a rectangular block transfer (blit) of pixels between two
  * miptrees.
@@ -804,22 +840,44 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
unsigned length = brw->gen >= 8 ? 7 : 6;
bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 
-   BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
-   OUT_BATCH(CMD | (length - 2));
-   OUT_BATCH(BR13);
-   OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
-   OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
-   if (brw->gen >= 8) {
-  OUT_RELOC64(mt->bo,
-  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-  0);
-   } else {
-  OUT_RELOC(mt->bo,
-I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-0);
+   /* We need to split the blit into chunks that each fit within the blitter's
+* restrictions.  We can't use a chunk size of 32768 because wee need to
+* ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
+* a nice round power of two, big enough that performance won't suffer, and
+* small enough to guarantee everything fits.
+*/
+   const uint32_t max_chunk_size = 16384;
+
+   for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
+  for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
+ const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
+ const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
+
+ uint32_t offset, tile_x, tile_y;
+ get_blit_intratile_offset_el(brw, mt,
+  x + chunk_x, y + chunk_y,
+  , _x, _y);
+
+ BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
+ OUT_BATCH(CMD | (length - 2));
+ OUT_BATCH(BR13);
+ OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
+   SET_FIELD(x + chunk_x, BLT_X));
+ OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
+   SET_FIELD(x + chunk_x + chunk_w, BLT_X));
+ if (brw->gen >= 8) {
+OUT_RELOC64(mt->bo,
+I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+offset);
+ } else {
+OUT_RELOC(mt->bo,
+  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+  offset);
+ }
+ OUT_BATCH(0x); /* white, but only alpha gets written */
+ ADVANCE_BATCH_TILED(dst_y_tiled, false);
+  }
}
-   OUT_BATCH(0x); /* white, but only alpha gets written */
-   ADVANCE_BATCH_TILED(dst_y_tiled, false);
 
brw_emit_mi_flush(brw);
 }
-- 
2.5.0.400.gff86faf

[Mesa-dev] [PATCH v2 5/6] i965/blit: Break blits into chunks in intel_miptree_blit

[Jason Ekstrand]

This allows us to blit much larger images than if we use the blitter
directly.  In particular, it gives us an almost infinite image height
compared to the fairly limiting 32k.  We do, however, still have a
restriction on stride of the image because handling larger strides, while
possible, is fairly difficult.

v2: Properly handle linear blit alignment restrictions

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 64 ++
 1 file changed, 41 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 02a1fd9..975eb39 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -313,31 +313,49 @@ intel_miptree_blit(struct brw_context *brw,
dst_x += dst_image_x;
dst_y += dst_image_y;
 
-   /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
-* value. The values we're working with are unsigned, so make sure we don't
-* overflow.
+   /* We need to split the blit into chunks that each fit within the blitter's
+* restrictions.  We can't use a chunk size of 32768 because wee need to
+* ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
+* a nice round power of two, big enough that performance won't suffer, and
+* small enough to guarantee everything fits.
 */
-   if (src_x >= 32768 || src_y >= 32768 || dst_x >= 32768 || dst_y >= 32768) {
-  perf_debug("Falling back due to >=32k offset [src(%d, %d) dst(%d, 
%d)]\n",
- src_x, src_y, dst_x, dst_y);
-  return false;
-   }
+   const uint32_t max_chunk_size = 16384;
 
-   if (!intelEmitCopyBlit(brw,
-  src_mt->cpp,
-  src_flip == dst_flip ? src_mt->pitch : 
-src_mt->pitch,
-  src_mt->bo, src_mt->offset,
-  src_mt->tiling,
-  src_mt->tr_mode,
-  dst_mt->pitch,
-  dst_mt->bo, dst_mt->offset,
-  dst_mt->tiling,
-  dst_mt->tr_mode,
-  src_x, src_y,
-  dst_x, dst_y,
-  width, height,
-  logicop)) {
-  return false;
+   for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
+  for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
+ const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
+ const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
+
+ uint32_t src_offset, src_tile_x, src_tile_y;
+ get_blit_intratile_offset_el(brw, src_mt,
+  src_x + chunk_x, src_y + chunk_y,
+  _offset, _tile_x, _tile_y);
+
+ uint32_t dst_offset, dst_tile_x, dst_tile_y;
+ get_blit_intratile_offset_el(brw, dst_mt,
+  dst_x + chunk_x, dst_y + chunk_y,
+  _offset, _tile_x, _tile_y);
+
+ if (!intelEmitCopyBlit(brw,
+src_mt->cpp,
+src_flip == dst_flip ? src_mt->pitch :
+   -src_mt->pitch,
+src_mt->bo, src_mt->offset + src_offset,
+src_mt->tiling,
+src_mt->tr_mode,
+dst_mt->pitch,
+dst_mt->bo, dst_mt->offset + dst_offset,
+dst_mt->tiling,
+dst_mt->tr_mode,
+src_tile_x, src_tile_y,
+dst_tile_x, dst_tile_y,
+chunk_w, chunk_h,
+logicop)) {
+/* If this is ever going to fail, it will fail on the first chunk 
*/
+assert(chunk_x == 0 && chunk_y == 0);
+return false;
+ }
+  }
}
 
/* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 2/6] i965/miptree: Break miptree -> ISL tiling conversion into a helper

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 ++
 2 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 866d61f..551df4d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3043,6 +3043,35 @@ get_isl_dim_layout(const struct gen_device_info 
*devinfo, uint32_t tiling,
unreachable("Invalid texture target");
 }
 
+enum isl_tiling
+intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
+{
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+  return ISL_TILING_W;
+   } else {
+  switch (mt->tiling) {
+  case I915_TILING_NONE:
+ return ISL_TILING_LINEAR;
+  case I915_TILING_X:
+ return ISL_TILING_X;
+  case I915_TILING_Y:
+ switch (mt->tr_mode) {
+ case INTEL_MIPTREE_TRMODE_NONE:
+return ISL_TILING_Y0;
+ case INTEL_MIPTREE_TRMODE_YF:
+return ISL_TILING_Yf;
+ case INTEL_MIPTREE_TRMODE_YS:
+return ISL_TILING_Ys;
+ default:
+unreachable("Invalid tiled resource mode");
+ }
+ break;
+  default:
+ unreachable("Invalid tiling mode");
+  }
+   }
+}
+
 void
 intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
@@ -3068,38 +3097,15 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
   surf->msaa_layout = ISL_MSAA_LAYOUT_NONE;
}
 
+   surf->tiling = intel_miptree_get_isl_tiling(mt);
+
if (mt->format == MESA_FORMAT_S_UINT8) {
-  surf->tiling = ISL_TILING_W;
   /* The ISL definition of row_pitch matches the surface state pitch field
* a bit better than intel_mipmap_tree.  In particular, ISL incorporates
* the factor of 2 for W-tiling in row_pitch.
*/
   surf->row_pitch = 2 * mt->pitch;
} else {
-  switch (mt->tiling) {
-  case I915_TILING_NONE:
- surf->tiling = ISL_TILING_LINEAR;
- break;
-  case I915_TILING_X:
- surf->tiling = ISL_TILING_X;
- break;
-  case I915_TILING_Y:
- switch (mt->tr_mode) {
- case INTEL_MIPTREE_TRMODE_NONE:
-surf->tiling = ISL_TILING_Y0;
-break;
- case INTEL_MIPTREE_TRMODE_YF:
-surf->tiling = ISL_TILING_Yf;
-break;
- case INTEL_MIPTREE_TRMODE_YS:
-surf->tiling = ISL_TILING_Ys;
-break;
- }
- break;
-  default:
- unreachable("Invalid tiling mode");
-  }
-
   surf->row_pitch = mt->pitch;
}
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f26a6b0..f69bd4a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -813,6 +813,9 @@ enum isl_dim_layout
 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
GLenum target);
 
+enum isl_tiling
+intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
+
 void
 intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 6/6] i965/miptree: Remove the width/height < 32768 restrictions

[Jason Ekstrand]

These restrictions existed because intel_miptree_blit couldn't handle
surfaces bigger than 32k.  How that we're chopping blits up into chunks, it
can handle any size we throw at it so we can get rid of this restriction.
This improves the terrain tests in synmark by 25-30% on my Sky Lake gt3.

Signed-off-by: Jason Ekstrand 
Reported-by: Ben Widawsky 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 3 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4618bc0..768f8a8 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -610,8 +610,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
if (minimum_pitch < 64)
   return I915_TILING_NONE;
 
-   if (ALIGN(minimum_pitch, 512) >= 32768 ||
-   mt->total_width >= 32768 || mt->total_height >= 32768) {
+   if (ALIGN(minimum_pitch, 512) >= 32768) {
   perf_debug("%dx%d miptree too large to blit, falling back to untiled",
  mt->total_width, mt->total_height);
   return I915_TILING_NONE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 551df4d..551812a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2838,12 +2838,6 @@ static bool
 can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
 {
-   uint32_t image_x;
-   uint32_t image_y;
-   intel_miptree_get_image_offset(mt, level, slice, _x, _y);
-   if (image_x >= 32768 || image_y >= 32768)
-  return false;
-
/* See intel_miptree_blit() for details on the 32k pitch limit. */
if (mt->pitch >= 32768)
   return false;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 3/6] i965/blit: Remove a bogus assertion

[Jason Ekstrand]

This assertion, while valid for linear buffers, doesn't work properly for
tiled memory.  It used to work most of the time because the offset provided
was always to the left-hand edge of the image.  However, if you use a byte
offset to get to the inside of the image, the height * stride calculation
may actually end up being too large.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 4 
 1 file changed, 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index b7a9cc9..bc97e66 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -585,10 +585,6 @@ intelEmitCopyBlit(struct brw_context *brw,
 
assert(dst_x < dst_x2);
assert(dst_y < dst_y2);
-   assert(src_offset + (src_y + h - 1) * abs(src_pitch) +
-  (w * cpp) <= src_buffer->size);
-   assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) +
-  (w * cpp) <= dst_buffer->size);
 
BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, src_y_tiled);
OUT_BATCH(CMD | (length - 2));
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH v2 1/6] i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offset

[Jason Ekstrand]

The only actual user of this parameter was blorp and, since the conversion
to ISL, it no longer uses this function.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  3 +--
 src/mesa/drivers/dri/i965/brw_misc_state.c|  6 ++
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |  6 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 +--
 5 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9484574..60ae840 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -123,8 +123,7 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
} else {
   *offset = intel_miptree_get_aligned_offset(mt,
  mt->level[lod].level_x,
- mt->level[lod].level_y,
- false);
+ mt->level[lod].level_y);
}
 
surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index cc62dab..6fce038 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -451,14 +451,12 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
   brw->depthstencil.depth_offset =
  intel_miptree_get_aligned_offset(depth_mt,
   depth_irb->draw_x & ~tile_mask_x,
-  depth_irb->draw_y & ~tile_mask_y,
-  false);
+  depth_irb->draw_y & ~tile_mask_y);
   if (intel_renderbuffer_has_hiz(depth_irb)) {
  brw->depthstencil.hiz_offset =
 intel_miptree_get_aligned_offset(depth_mt,
  depth_irb->draw_x & ~tile_mask_x,
- (depth_irb->draw_y & 
~tile_mask_y) / 2,
- false);
+ (depth_irb->draw_y & 
~tile_mask_y) / 2);
   }
}
if (stencil_irb) {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 1a29860..3f14006 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -168,8 +168,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 offset = intel_miptree_get_aligned_offset(
 hiz_mt,
 hiz_mt->level[lod].level_x,
-hiz_mt->level[lod].level_y,
-false);
+hiz_mt->level[lod].level_y);
  }
 
 BEGIN_BATCH(3);
@@ -204,8 +203,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
offset = intel_miptree_get_aligned_offset(
stencil_mt,
stencil_mt->level[lod].level_x,
-   stencil_mt->level[lod].level_y,
-   false);
+   stencil_mt->level[lod].level_y);
 }
  }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index aba203a..866d61f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1266,26 +1266,12 @@ intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, 
uint32_t cpp,
  */
 uint32_t
 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
- uint32_t x, uint32_t y,
- bool map_stencil_as_y_tiled)
+ uint32_t x, uint32_t y)
 {
int cpp = mt->cpp;
uint32_t pitch = mt->pitch;
uint32_t tiling = mt->tiling;
 
-   if (map_stencil_as_y_tiled) {
-  tiling = I915_TILING_Y;
-
-  /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
-   * gets transformed into a 32-high Y-tile.  Accordingly, the pitch of
-   * the resulting surface is twice the pitch of the original miptree,
-   * since each row in the Y-tiled view corresponds to two rows in the
-   * actual W-tiled surface.  So we need to correct the pitch before
-   * computing the offsets.
-   */
-  pitch *= 2;
-   }
-
switch (tiling) {
default:
   unreachable("not reached");
@@ -1327,7 +1313,7 @@ intel_miptree_get_tile_offsets(const struct 
intel_mipmap_tree *mt,
*tile_x = x & mask_x;
*tile_y = y & mask_y;
 
-   return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, 
false);
+ 

[Mesa-dev] [PATCH v2 0/6] i965: Remove width/height restrictions on tiled images

[Jason Ekstrand]

Sorry for the quick re-send, but I realized after sending that there were a
couple of issues (including a patch ordering problem) in the original
version.  Sadly, a full piglit run on Haswell (which makes pretty good use
of the blitter) didn't show any of these issues so it wasn't caught earlier.

Jason Ekstrand (6):
  i965/miptree: Remove the stencil_as_y_tiled parameter from
get_aligned_offset
  i965/miptree: Break miptree -> ISL tiling conversion into a helper
  i965/blit: Remove a bogus assertion
  i965/blit: Break blits into chunks in set_alpha_to_one
  i965/blit: Break blits into chunks in intel_miptree_blit
  i965/miptree: Remove the width/height < 32768 restrictions

 src/mesa/drivers/dri/i965/brw_blorp.c |   3 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c|   6 +-
 src/mesa/drivers/dri/i965/brw_tex_layout.c|   3 +-
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |   6 +-
 src/mesa/drivers/dri/i965/intel_blit.c| 158 +++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  80 ++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |   6 +-
 7 files changed, 158 insertions(+), 104 deletions(-)

-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] Proposal of date-based Mesa versioning for 2017

[Enrico Weigelt, metux IT consult]

folks,

are you looking for ways to make simple things complicated ?

date-based versioning (eg. -MM) only makes sense, when you
have an appropriate release schedule.

I'd really prefer semantic versioning - especially for stable distros
and embedded systems (here you dont wanna do arbitrary updates ...).

Anyways, retrieving the dates from tags should be pretty trivial,
And just takes a few lines of shellscript to generate a nice
html page ...


--mtx

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Re: [Mesa-dev] [PATCH] scons: Require libdrm >= 2.4.65 for DRM.

[Michel Dänzer]

On 25/10/16 11:01 AM, Michel Dänzer wrote:
> On 25/10/16 09:17 AM, Vedran Miletić wrote:
>> On 10/25/2016 01:41 AM, Vinson Lee wrote:
>>> Fix SCons build. drmDevicePtr is not available until libdrm 2.4.65.
>>>
>>>   Compiling src/loader/loader.c ...
>>> src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
>>>  static char *drm_construct_id_path_tag(drmDevicePtr device)
>>> ^
>>>
>>> Fixes: 4a183f4d06f8 ("scons: loader: use libdrm when available")
>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98421
>>> Signed-off-by: Vinson Lee 
>>> ---
>>>  scons/gallium.py | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/scons/gallium.py b/scons/gallium.py
>>> index 9f7555cf8bce..8cf6cc732cdc 100755
>>> --- a/scons/gallium.py
>>> +++ b/scons/gallium.py
>>> @@ -651,7 +651,7 @@ def generate(env):
>>>  env.PkgCheckModules('X11', ['x11', 'xext', 'xdamage', 'xfixes',
>>> 'glproto >= 1.4.13'])
>>>  env.PkgCheckModules('XCB', ['x11-xcb', 'xcb-glx >= 1.8.1',
>>> 'xcb-dri2 >= 1.8'])
>>>  env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
>>> -env.PkgCheckModules('DRM', ['libdrm >= 2.4.38'])
>>> +env.PkgCheckModules('DRM', ['libdrm >= 2.4.65'])
>>>
>>>  if env['x11']:
>>>  env.Append(CPPPATH = env['X11_CPPPATH'])
>>>
>>
>> That's a large bump and 2.4.65 is just over a year old. It would be nice
>> to support a couple more versions before.
>>
>> Is there an acceptable workaround?
> 
> Who / what requires current Mesa but can't update libdrm to >= 2.4.65?

Also, configure.ac already requires >= 2.4.66.


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Re: [Mesa-dev] [PATCH] scons: Require libdrm >= 2.4.65 for DRM.

[Michel Dänzer]

On 25/10/16 09:17 AM, Vedran Miletić wrote:
> On 10/25/2016 01:41 AM, Vinson Lee wrote:
>> Fix SCons build. drmDevicePtr is not available until libdrm 2.4.65.
>>
>>   Compiling src/loader/loader.c ...
>> src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
>>  static char *drm_construct_id_path_tag(drmDevicePtr device)
>> ^
>>
>> Fixes: 4a183f4d06f8 ("scons: loader: use libdrm when available")
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98421
>> Signed-off-by: Vinson Lee 
>> ---
>>  scons/gallium.py | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/scons/gallium.py b/scons/gallium.py
>> index 9f7555cf8bce..8cf6cc732cdc 100755
>> --- a/scons/gallium.py
>> +++ b/scons/gallium.py
>> @@ -651,7 +651,7 @@ def generate(env):
>>  env.PkgCheckModules('X11', ['x11', 'xext', 'xdamage', 'xfixes',
>> 'glproto >= 1.4.13'])
>>  env.PkgCheckModules('XCB', ['x11-xcb', 'xcb-glx >= 1.8.1',
>> 'xcb-dri2 >= 1.8'])
>>  env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
>> -env.PkgCheckModules('DRM', ['libdrm >= 2.4.38'])
>> +env.PkgCheckModules('DRM', ['libdrm >= 2.4.65'])
>>
>>  if env['x11']:
>>  env.Append(CPPPATH = env['X11_CPPPATH'])
>>
> 
> That's a large bump and 2.4.65 is just over a year old. It would be nice
> to support a couple more versions before.
> 
> Is there an acceptable workaround?

Who / what requires current Mesa but can't update libdrm to >= 2.4.65?


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[Mesa-dev] [Bug 98406] [vulkan, radv] with Intel iGPU and AMD dGPU coruptions on display

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98406

Mike Lothian  changed:

   What|Removed |Added

 CC||m...@fireburn.co.uk

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Re: [Mesa-dev] [PATCH] scons: Require libdrm >= 2.4.65 for DRM.

[Vedran Miletić]

On 10/25/2016 01:41 AM, Vinson Lee wrote:

Fix SCons build. drmDevicePtr is not available until libdrm 2.4.65.

  Compiling src/loader/loader.c ...
src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
 static char *drm_construct_id_path_tag(drmDevicePtr device)
^

Fixes: 4a183f4d06f8 ("scons: loader: use libdrm when available")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98421
Signed-off-by: Vinson Lee 
---
 scons/gallium.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scons/gallium.py b/scons/gallium.py
index 9f7555cf8bce..8cf6cc732cdc 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -651,7 +651,7 @@ def generate(env):
 env.PkgCheckModules('X11', ['x11', 'xext', 'xdamage', 'xfixes', 'glproto 
>= 1.4.13'])
 env.PkgCheckModules('XCB', ['x11-xcb', 'xcb-glx >= 1.8.1', 'xcb-dri2 >= 
1.8'])
 env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
-env.PkgCheckModules('DRM', ['libdrm >= 2.4.38'])
+env.PkgCheckModules('DRM', ['libdrm >= 2.4.65'])

 if env['x11']:
 env.Append(CPPPATH = env['X11_CPPPATH'])



That's a large bump and 2.4.65 is just over a year old. It would be nice 
to support a couple more versions before.


Is there an acceptable workaround?

Regards,
Vedran

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[Mesa-dev] [PATCH] nir: stop adjusting driver location for varying packing

[Timothy Arceri]

As of 59864e8e020 we just use the location assigned by the front-end and
no longer need this for i965.

Since there were some issues in the logic with assigning arrays the same
driver location if they didn't start at the same location just remove it
and let other drivers implement a solution if needed when they add
ARB_enhanced_layouts support.
---
 src/compiler/nir/nir.h|  1 -
 src/compiler/nir/nir_lower_io.c   | 48 ++-
 src/mesa/drivers/dri/i965/brw_nir.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_program.c   |  4 +--
 src/mesa/state_tracker/st_glsl_to_nir.cpp |  3 --
 5 files changed, 5 insertions(+), 53 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 54302f8..9264763 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2321,7 +2321,6 @@ void nir_lower_io_to_temporaries(nir_shader *shader,
 void nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint);
 
 void nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
-  unsigned base_offset,
   int (*type_size)(const struct glsl_type *));
 
 typedef enum {
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index d77cb13..25cca18 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -44,18 +44,10 @@ struct lower_io_state {
 
 void
 nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
- unsigned base_offset,
  int (*type_size)(const struct glsl_type *))
 {
unsigned location = 0;
 
-   /* There are 32 regular and 32 patch varyings allowed */
-   int locations[64][2];
-   for (unsigned i = 0; i < 64; i++) {
-  for (unsigned j = 0; j < 2; j++)
- locations[i][j] = -1;
-   }
-
nir_foreach_variable(var, var_list) {
   /*
* UBO's have their own address spaces, so don't count them towards the
@@ -65,44 +57,8 @@ nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
   var->interface_type != NULL)
  continue;
 
-  /* Make sure we give the same location to varyings packed with
-   * ARB_enhanced_layouts.
-   */
-  int idx = var->data.location - base_offset;
-  if (base_offset && idx >= 0) {
- assert(idx < ARRAY_SIZE(locations));
-
- if (locations[idx][var->data.index] == -1) {
-var->data.driver_location = location;
-locations[idx][var->data.index] = location;
-
-/* A dvec3 can be packed with a double we need special handling
- * for this as we are packing across two locations.
- */
-if (glsl_get_base_type(var->type) == GLSL_TYPE_DOUBLE &&
-glsl_get_vector_elements(var->type) == 3) {
-   /* Hack around type_size functions that expect vectors to be
-* padded out to vec4. If a float type is the same size as a
-* double then the type size is padded to vec4, otherwise
-* set the offset to two doubles which offsets the location
-* past the first two components in dvec3 which were stored at
-* the previous location.
-*/
-   unsigned dsize = type_size(glsl_double_type());
-   unsigned offset =
-  dsize == type_size(glsl_float_type()) ? dsize : dsize * 2;
-
-   locations[idx + 1][var->data.index] = location + offset;
-}
-
-location += type_size(var->type);
- } else {
-var->data.driver_location = locations[idx][var->data.index];
- }
-  } else {
- var->data.driver_location = location;
- location += type_size(var->type);
-  }
+  var->data.driver_location = location;
+  location += type_size(var->type);
}
 
*size = location;
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c 
b/src/mesa/drivers/dri/i965/brw_nir.c
index ec48da9..a93d825 100644
--- a/src/mesa/drivers/dri/i965/brw_nir.c
+++ b/src/mesa/drivers/dri/i965/brw_nir.c
@@ -380,7 +380,7 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
 void
 brw_nir_lower_cs_shared(nir_shader *nir)
 {
-   nir_assign_var_locations(>shared, >num_shared, 0,
+   nir_assign_var_locations(>shared, >num_shared,
 type_size_scalar_bytes);
nir_lower_io(nir, nir_var_shared, type_size_scalar_bytes, 0);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index e0a1287..8f01502 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -51,11 +51,11 @@ static void
 brw_nir_lower_uniforms(nir_shader *nir, bool is_scalar)
 {
if (is_scalar) {
-  nir_assign_var_locations(>uniforms, >num_uniforms, 0,
+  nir_assign_var_locations(>uniforms, >num_uniforms,

Re: [Mesa-dev] [PATCH mesa] egl/dri2: swap_buffers_with_damage falls back to swap_buffers

[Rob Herring]

On Mon, Oct 24, 2016 at 5:41 PM, Eric Engestrom  wrote:
> CC: Rob Herring 
> CC: Rob Clark 
> Suggested-by: Emil Velikov 
> Signed-off-by: Eric Engestrom 

Good, you beat me to it.

Reviewed-by: Rob Herring 

> ---
>  src/egl/drivers/dri2/egl_dri2_fallbacks.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h 
> b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> index e769af3..8dad271 100644
> --- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> +++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
> @@ -66,7 +66,8 @@ dri2_fallback_swap_buffers_with_damage(_EGLDriver *drv, 
> _EGLDisplay *dpy,
>_EGLSurface *surf,
>const EGLint *rects, EGLint n_rects)
>  {
> -   return EGL_FALSE;
> +   struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> +   return dri2_dpy->vtbl->swap_buffers(drv, dpy, surf);
>  }
>
>  static inline EGLBoolean
> --
> Cheers,
>   Eric
>
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Re: [Mesa-dev] [PATCH] scons: Require libdrm >= 2.4.65 for DRM.

[Edward O'Callaghan]

Reviewed-by: Edward O'Callaghan 

On 10/25/2016 10:41 AM, Vinson Lee wrote:
> Fix SCons build. drmDevicePtr is not available until libdrm 2.4.65.
> 
>   Compiling src/loader/loader.c ...
> src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
>  static char *drm_construct_id_path_tag(drmDevicePtr device)
> ^
> 
> Fixes: 4a183f4d06f8 ("scons: loader: use libdrm when available")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98421
> Signed-off-by: Vinson Lee 
> ---
>  scons/gallium.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/scons/gallium.py b/scons/gallium.py
> index 9f7555cf8bce..8cf6cc732cdc 100755
> --- a/scons/gallium.py
> +++ b/scons/gallium.py
> @@ -651,7 +651,7 @@ def generate(env):
>  env.PkgCheckModules('X11', ['x11', 'xext', 'xdamage', 'xfixes', 'glproto 
> >= 1.4.13'])
>  env.PkgCheckModules('XCB', ['x11-xcb', 'xcb-glx >= 1.8.1', 'xcb-dri2 >= 
> 1.8'])
>  env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
> -env.PkgCheckModules('DRM', ['libdrm >= 2.4.38'])
> +env.PkgCheckModules('DRM', ['libdrm >= 2.4.65'])
>  
>  if env['x11']:
>  env.Append(CPPPATH = env['X11_CPPPATH'])
> 



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[Mesa-dev] [PATCH] scons: Require libdrm >= 2.4.65 for DRM.

[Vinson Lee]

Fix SCons build. drmDevicePtr is not available until libdrm 2.4.65.

  Compiling src/loader/loader.c ...
src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
 static char *drm_construct_id_path_tag(drmDevicePtr device)
^

Fixes: 4a183f4d06f8 ("scons: loader: use libdrm when available")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98421
Signed-off-by: Vinson Lee 
---
 scons/gallium.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scons/gallium.py b/scons/gallium.py
index 9f7555cf8bce..8cf6cc732cdc 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -651,7 +651,7 @@ def generate(env):
 env.PkgCheckModules('X11', ['x11', 'xext', 'xdamage', 'xfixes', 'glproto 
>= 1.4.13'])
 env.PkgCheckModules('XCB', ['x11-xcb', 'xcb-glx >= 1.8.1', 'xcb-dri2 >= 
1.8'])
 env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
-env.PkgCheckModules('DRM', ['libdrm >= 2.4.38'])
+env.PkgCheckModules('DRM', ['libdrm >= 2.4.65'])
 
 if env['x11']:
 env.Append(CPPPATH = env['X11_CPPPATH'])
-- 
1.8.3.1

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Re: [Mesa-dev] [PATCH 6/6] i965/miptree: Remove the width/height < 32768 restrictions

[Ben Widawsky]

On 16-10-24 15:36:59, Jason Ekstrand wrote:

Even though this patch series is from-scratch, Ben deserves most of the
credit for tracking this down.  He had a series some time ago to fix the
issue for the terrain tests but it never ended up landing for a variety of
reasons (many of which were stupid).  Ben, would you like me to credit you
somehow?  Maybe a Reported-by?

--Jason



I don't care. I would have liked the have landed the patches way back when, but
that's how the cookie crumbles. I'm glad it's at least moving in the right
direction now.


On Mon, Oct 24, 2016 at 3:29 PM, Jason Ekstrand 
wrote:


These restrictions existed because intel_miptree_blit couldn't handle
surfaces bigger than 32k.  How that we're chopping blits up into chunks, it
can handle any size we throw at it so we can get rid of this restriction.
This improves the terrain tests in synmark by 25-30% on my Sky Lake gt3.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 3 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4618bc0..768f8a8 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -610,8 +610,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
if (minimum_pitch < 64)
   return I915_TILING_NONE;

-   if (ALIGN(minimum_pitch, 512) >= 32768 ||
-   mt->total_width >= 32768 || mt->total_height >= 32768) {
+   if (ALIGN(minimum_pitch, 512) >= 32768) {
   perf_debug("%dx%d miptree too large to blit, falling back to
untiled",
  mt->total_width, mt->total_height);
   return I915_TILING_NONE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 551df4d..551812a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2838,12 +2838,6 @@ static bool
 can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
 {
-   uint32_t image_x;
-   uint32_t image_y;
-   intel_miptree_get_image_offset(mt, level, slice, _x, _y);
-   if (image_x >= 32768 || image_y >= 32768)
-  return false;
-
/* See intel_miptree_blit() for details on the 32k pitch limit. */
if (mt->pitch >= 32768)
   return false;
--
2.5.0.400.gff86faf




--
Ben Widawsky, Intel Open Source Technology Center
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[Mesa-dev] [Bug 98421] src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=98421

Bug ID: 98421
   Summary: src/loader/loader.c:111:40: error: unknown type name
‘drmDevicePtr’
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: bisected, regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org
CC: davyax...@gmail.com, emil.l.veli...@gmail.com,
nhaeh...@gmail.com

mesa: 41034abfe63012784c9e9e36856d878928cecd99 (master 13.1.0-devel)

$ scons
[...]
  Compiling src/loader/loader.c ...
src/loader/loader.c:111:40: error: unknown type name ‘drmDevicePtr’
 static char *drm_construct_id_path_tag(drmDevicePtr device)
^

scons: building terminated because of errors.
4a183f4d06f800f44e8a679dc2ae60149105e1ce is the first bad commit
commit 4a183f4d06f800f44e8a679dc2ae60149105e1ce
Author: Emil Velikov 
Date:   Wed Sep 7 19:03:29 2016 +0100

scons: loader: use libdrm when available

Signed-off-by: Emil Velikov 
Reviewed-by: Axel Davy 
Reviewed-by: Nicolai Hähnle 

:04 04 00962395c62ef5998909b9085844f2cc4f3765ae
32167484a10b914d0a3c486ab8b9ee0a2518080b M  src
bisect run success

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[Mesa-dev] [PATCH] st/omx/enc Raise default encode level

[Andy Furniss]

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281

Signed-off-by: Andy Furniss 
---
 src/gallium/state_trackers/omx/vid_enc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/omx/vid_enc.c 
b/src/gallium/state_trackers/omx/vid_enc.c
index 0d7ab28..07f6799 100644
--- a/src/gallium/state_trackers/omx/vid_enc.c
+++ b/src/gallium/state_trackers/omx/vid_enc.c
@@ -246,7 +246,7 @@ static OMX_ERRORTYPE vid_enc_Constructor(OMX_COMPONENTTYPE 
*comp, OMX_STRING nam
priv->quant.nQpB = OMX_VID_ENC_QUANT_B_FRAMES_DEFAULT;
 
priv->profile_level.eProfile = OMX_VIDEO_AVCProfileBaseline;
-   priv->profile_level.eLevel = OMX_VIDEO_AVCLevel42;
+   priv->profile_level.eLevel = OMX_VIDEO_AVCLevel51;
 
priv->force_pic_type.IntraRefreshVOP = OMX_FALSE;
priv->frame_num = 0;
-- 
2.7.0

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Re: [Mesa-dev] [PATCH V3] i965: rewrite brw_setup_vue_interpolation()

[Jason Ekstrand]

On Fri, Oct 21, 2016 at 5:13 PM, Timothy Arceri <
timothy.arc...@collabora.com> wrote:

> Here brw_setup_vue_interpolation() is rewritten not to use the
> InterpQualifier
> array in gl_fragment_program which will allow us to remove it.
>
> This change also makes the code which is only used by gen4/5 more self
> contained
> as it now has its own gen5_fragment_program struct rather than storing the
> map
> in brw_context. This means the interpolation map will only get processed
> once
> and will get stored in the in memory cache rather than being processed
> everytime
> the fs changes.
>
> Also by calling this from the fs compile code rather than from the upload
> code
> and using the interpolation assigned there we can get rid of the
> BRW_NEW_INTERPOLATION_MAP flag.
>
> It might not seem ideal to add a gen5_fragment_program struct however by
> the end
> of this series we will have gotten rid of all the
> brw_{shader_stage}_program
> structs and replaced them with a generic brw_program struct so there will
> only
> be two program structs which is better than what we have now.
>
> V2: Don't remove BRW_NEW_INTERPOLATION_MAP from dirty_bit_map until the
> following
> patch to fix build error.
>
> V3 - Suggestions by Jason:
> - name struct gen4_fragment_program rather than gen5_fragment_program
> - don't use enum with memset()
> - create interp mode set helper and simplify logic to call it
> - add assert when calling function to show prog will never be NULL for
>  gen4/5 i.e. no Vulkan
>

V3 is

Reviewed-by: Jason Ekstrand 

However, I trust Ken's opinion far more when it comes to atoms and the
interactions between the different compile stages.  I'd like him to review
this one too.
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[Mesa-dev] [PATCH mesa] egl/dri2: swap_buffers_with_damage falls back to swap_buffers

[Eric Engestrom]

CC: Rob Herring 
CC: Rob Clark 
Suggested-by: Emil Velikov 
Signed-off-by: Eric Engestrom 
---
 src/egl/drivers/dri2/egl_dri2_fallbacks.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/egl/drivers/dri2/egl_dri2_fallbacks.h 
b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
index e769af3..8dad271 100644
--- a/src/egl/drivers/dri2/egl_dri2_fallbacks.h
+++ b/src/egl/drivers/dri2/egl_dri2_fallbacks.h
@@ -66,7 +66,8 @@ dri2_fallback_swap_buffers_with_damage(_EGLDriver *drv, 
_EGLDisplay *dpy,
   _EGLSurface *surf,
   const EGLint *rects, EGLint n_rects)
 {
-   return EGL_FALSE;
+   struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
+   return dri2_dpy->vtbl->swap_buffers(drv, dpy, surf);
 }
 
 static inline EGLBoolean
-- 
Cheers,
  Eric

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[Mesa-dev] [PATCH] radeon/vce Handle H.264 level 5.2

[Andy Furniss]

For gstreamer
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281

Signed-off-by: Andy Furniss 
---
 src/gallium/drivers/radeon/radeon_vce.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index ef93e46..6d6d414 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -178,13 +178,13 @@ static unsigned get_cpb_num(struct rvce_encoder *enc)
case 41:
dpb = 32768;
break;
-   default:
case 42:
dpb = 34816;
break;
case 50:
dpb = 110400;
break;
+   default:
case 51:
dpb = 184320;
break;
-- 
2.7.0

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Re: [Mesa-dev] [PATCH 6/6] i965/miptree: Remove the width/height < 32768 restrictions

[Jason Ekstrand]

Even though this patch series is from-scratch, Ben deserves most of the
credit for tracking this down.  He had a series some time ago to fix the
issue for the terrain tests but it never ended up landing for a variety of
reasons (many of which were stupid).  Ben, would you like me to credit you
somehow?  Maybe a Reported-by?

--Jason

On Mon, Oct 24, 2016 at 3:29 PM, Jason Ekstrand 
wrote:

> These restrictions existed because intel_miptree_blit couldn't handle
> surfaces bigger than 32k.  How that we're chopping blits up into chunks, it
> can handle any size we throw at it so we can get rid of this restriction.
> This improves the terrain tests in synmark by 25-30% on my Sky Lake gt3.
>
> Signed-off-by: Jason Ekstrand 
> ---
>  src/mesa/drivers/dri/i965/brw_tex_layout.c| 3 +--
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
>  2 files changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> index 4618bc0..768f8a8 100644
> --- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
> +++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
> @@ -610,8 +610,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
> if (minimum_pitch < 64)
>return I915_TILING_NONE;
>
> -   if (ALIGN(minimum_pitch, 512) >= 32768 ||
> -   mt->total_width >= 32768 || mt->total_height >= 32768) {
> +   if (ALIGN(minimum_pitch, 512) >= 32768) {
>perf_debug("%dx%d miptree too large to blit, falling back to
> untiled",
>   mt->total_width, mt->total_height);
>return I915_TILING_NONE;
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 551df4d..551812a 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -2838,12 +2838,6 @@ static bool
>  can_blit_slice(struct intel_mipmap_tree *mt,
> unsigned int level, unsigned int slice)
>  {
> -   uint32_t image_x;
> -   uint32_t image_y;
> -   intel_miptree_get_image_offset(mt, level, slice, _x, _y);
> -   if (image_x >= 32768 || image_y >= 32768)
> -  return false;
> -
> /* See intel_miptree_blit() for details on the 32k pitch limit. */
> if (mt->pitch >= 32768)
>return false;
> --
> 2.5.0.400.gff86faf
>
>
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[Mesa-dev] [PATCH 19/24] winsys/amdgpu: allocate FMASK properly

[Marek Olšák]

From: Marek Olšák 

I expect no change in behavior, because r600_texture.c forces the same
tile mode as the base texture has.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 27c425c..ff71bcb 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -380,36 +380,38 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
   AddrDccIn.bpp = AddrSurfInfoIn.bpp = bpe * 8;
}
 
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
   tex->nr_samples ? tex->nr_samples : 1;
AddrSurfInfoIn.tileIndex = -1;
 
/* Set the micro tile type. */
if (flags & RADEON_SURF_SCANOUT)
   AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
-   else if (flags & RADEON_SURF_Z_OR_SBUFFER)
+   else if (flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
   AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
else
   AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
 
AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
+   AddrSurfInfoIn.flags.fmask = (flags & RADEON_SURF_FMASK) != 0;
AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
AddrSurfInfoIn.flags.tcCompatible = (flags & 
RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 * requested, because TC-compatible HTILE requires 2D tiling.
 */
-   AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible;
+   AddrSurfInfoIn.flags.degrade4Space = !AddrSurfInfoIn.flags.tcCompatible &&
+!(flags & RADEON_SURF_FMASK);
 
/* DCC notes:
 * - If we add MSAA support, keep in mind that CB can't decompress 8bpp
 *   with samples >= 4.
 * - Mipmapped array textures have low performance (discovered by a closed
 *   driver team).
 */
AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
 !(flags & RADEON_SURF_Z_OR_SBUFFER) &&
 !(flags & RADEON_SURF_DISABLE_DCC) &&
-- 
2.7.4

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[Mesa-dev] [PATCH 04/24] gallium/radeon: fold radeon_winsys::surface_best into radeon/winsys

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c  |  6 ++
 src/gallium/drivers/radeon/radeon_winsys.h | 10 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  7 ---
 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 24 ++
 4 files changed, 9 insertions(+), 38 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 27035c0..c386549 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1289,24 +1289,21 @@ struct pipe_resource *r600_texture_create(struct 
pipe_screen *screen,
util_format_is_depth_or_stencil(templ->format);
 
int r;
 
r = r600_init_surface(rscreen, , templ,
  r600_choose_tiling(rscreen, templ),
  is_flushed_depth, tc_compatible_htile);
if (r) {
return NULL;
}
-   r = rscreen->ws->surface_best(rscreen->ws, );
-   if (r) {
-   return NULL;
-   }
+
return (struct pipe_resource *)r600_texture_create_object(screen, 
templ, 0,
  0, NULL, 
);
 }
 
 static struct pipe_resource *r600_texture_from_handle(struct pipe_screen 
*screen,
  const struct 
pipe_resource *templ,
  struct winsys_handle 
*whandle,
   unsigned usage)
 {
struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
@@ -1342,20 +1339,21 @@ static struct pipe_resource 
*r600_texture_from_handle(struct pipe_screen *screen
array_mode = RADEON_SURF_MODE_1D;
else
array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
 
r = r600_init_surface(rscreen, , templ, array_mode,
  false, false);
if (r) {
return NULL;
}
 
+   surface.flags |= RADEON_SURF_IMPORTED;
if (metadata.scanout)
surface.flags |= RADEON_SURF_SCANOUT;
 
rtex = r600_texture_create_object(screen, templ, stride,
  offset, buf, );
if (!rtex)
return NULL;
 
rtex->resource.is_shared = true;
rtex->resource.external_usage = usage;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 8946209..75badd0 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -272,20 +272,21 @@ enum radeon_feature_id {
 #define RADEON_SURF_MODE_2D 3
 #define RADEON_SURF_SCANOUT (1 << 16)
 #define RADEON_SURF_ZBUFFER (1 << 17)
 #define RADEON_SURF_SBUFFER (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER(RADEON_SURF_ZBUFFER | 
RADEON_SURF_SBUFFER)
 #define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
 #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
 #define RADEON_SURF_FMASK   (1 << 21)
 #define RADEON_SURF_DISABLE_DCC (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
+#define RADEON_SURF_IMPORTED(1 << 24)
 
 #define RADEON_SURF_GET(v, field)   (((v) >> RADEON_SURF_ ## field ## _SHIFT) 
& RADEON_SURF_ ## field ## _MASK)
 #define RADEON_SURF_SET(v, field)   (((v) & RADEON_SURF_ ## field ## _MASK) << 
RADEON_SURF_ ## field ## _SHIFT)
 #define RADEON_SURF_CLR(v, field)   ((v) & ~(RADEON_SURF_ ## field ## _MASK << 
RADEON_SURF_ ## field ## _SHIFT))
 
 struct radeon_surf_level {
 uint64_toffset;
 uint64_tslice_size;
 uint32_tnpix_x;
 uint32_tnpix_y;
@@ -737,29 +738,20 @@ struct radeon_winsys {
 
 /**
  * Initialize surface
  *
  * \param wsThe winsys this function is called from.
  * \param surf  Surface structure ptr
  */
 int (*surface_init)(struct radeon_winsys *ws,
 struct radeon_surf *surf);
 
-/**
- * Find best values for a surface
- *
- * \param wsThe winsys this function is called from.
- * \param surf  Surface structure ptr
- */
-int (*surface_best)(struct radeon_winsys *ws,
-struct radeon_surf *surf);
-
 uint64_t (*query_value)(struct radeon_winsys *ws,
 enum radeon_value_id value);
 
 bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset,
unsigned num_registers, uint32_t *out);
 };
 
 static inline bool radeon_emitted(struct radeon_winsys_cs *cs, unsigned num_dw)
 {
 return cs && (cs->prev_dw + 

[Mesa-dev] [PATCH 18/24] gallium/radeon: print tiling index when printing texture info

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index ca82a74..2f2c17c 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -949,48 +949,50 @@ void r600_print_texture_info(struct r600_texture *rtex, 
FILE *f)
fprintf(f, "  DCCLevel[%i]: enabled=%u, 
offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
i, rtex->surface.level[i].dcc_enabled,
rtex->surface.level[i].dcc_offset,
rtex->surface.level[i].dcc_fast_clear_size);
}
 
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, "  Level[%i]: offset=%"PRIu64", 
slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, 
"
-   "pitch_bytes=%u, mode=%u\n",
+   "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
rtex->surface.level[i].pitch_bytes,
-   rtex->surface.level[i].mode);
+   rtex->surface.level[i].mode,
+   rtex->surface.tiling_index[i]);
 
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
fprintf(f, "  StencilLayout: tilesplit=%u\n",
rtex->surface.stencil_tile_split);
for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
fprintf(f, "  StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
-   "pitch_bytes=%u, mode=%u\n",
+   "pitch_bytes=%u, mode=%u, tiling_index = %u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
rtex->surface.stencil_level[i].pitch_bytes,
-   rtex->surface.stencil_level[i].mode);
+   rtex->surface.stencil_level[i].mode,
+   rtex->surface.stencil_tiling_index[i]);
}
}
 }
 
 /* Common processing for r600_texture_create and r600_texture_from_handle */
 static struct r600_texture *
 r600_texture_create_object(struct pipe_screen *screen,
   const struct pipe_resource *base,
   struct pb_buffer *buf,
   struct radeon_surf *surface)
-- 
2.7.4

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[Mesa-dev] [PATCH 20/24] gallium/radeon: don't force the same tiling parameters for FMASK

[Marek Olšák]

From: Marek Olšák 

GCN can use a completely different tile mode for FMASK.

FMASK allocation now skips one unrelated amdgpu_surface_init codepath as
hinted by the assertion.
---
 src/gallium/drivers/radeon/r600_texture.c  | 18 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  2 ++
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 2f2c17c..f79eae2 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -586,33 +586,35 @@ void r600_texture_get_fmask_info(struct 
r600_common_screen *rscreen,
/* FMASK is allocated like an ordinary texture. */
struct pipe_resource templ = rtex->resource.b.b;
struct radeon_surf fmask = {};
unsigned flags, bpe;
 
memset(out, 0, sizeof(*out));
 
templ.nr_samples = 1;
flags = rtex->surface.flags | RADEON_SURF_FMASK;
 
-   /* Use the same parameters and tile mode. */
-   fmask.bankw = rtex->surface.bankw;
-   fmask.bankh = rtex->surface.bankh;
-   fmask.mtilea = rtex->surface.mtilea;
-   fmask.tile_split = rtex->surface.tile_split;
+   if (rscreen->chip_class <= CAYMAN) {
+   /* Use the same parameters and tile mode. */
+   fmask.bankw = rtex->surface.bankw;
+   fmask.bankh = rtex->surface.bankh;
+   fmask.mtilea = rtex->surface.mtilea;
+   fmask.tile_split = rtex->surface.tile_split;
+
+   if (nr_samples <= 4)
+   fmask.bankh = 4;
+   }
 
switch (nr_samples) {
case 2:
case 4:
bpe = 1;
-   if (rscreen->chip_class <= CAYMAN) {
-   fmask.bankh = 4;
-   }
break;
case 8:
bpe = 4;
break;
default:
R600_ERR("Invalid sample count for FMASK allocation.\n");
return;
}
 
/* Overallocate FMASK on R600-R700 to fix colorbuffer corruption.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index ff71bcb..45edcc2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -429,20 +429,22 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
 * TODO: update addrlib to a newer version, remove this, and
 * use flags.matchStencilTileCfg = 1 as an alternative fix.
 */
   if (tex->last_level > 0)
   AddrSurfInfoIn.flags.noStencil = 1;
 
/* Set preferred macrotile parameters. This is usually required
 * for shared resources. This is for 2D tiling only. */
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
+  assert(!(flags & RADEON_SURF_FMASK));
+
   /* If any of these parameters are incorrect, the calculation
* will fail. */
   AddrTileInfoIn.banks = surf->num_banks;
   AddrTileInfoIn.bankWidth = surf->bankw;
   AddrTileInfoIn.bankHeight = surf->bankh;
   AddrTileInfoIn.macroAspectRatio = surf->mtilea;
   AddrTileInfoIn.tileSplitBytes = surf->tile_split;
   AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to 
GB_TILE_MODE */
   AddrSurfInfoIn.flags.degrade4Space = 0;
   AddrSurfInfoIn.pTileInfo = 
-- 
2.7.4

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[Mesa-dev] [PATCH 05/24] winsys/amdgpu: remove unused definitions

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 95da4ac..94fe7d6 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -24,28 +24,20 @@
  * next paragraph) shall be included in all copies or substantial portions
  * of the Software.
  */
 
 /* Contact:
  * Marek Olšák 
  */
 
 #include "amdgpu_winsys.h"
 
-#ifndef NO_ENTRIES
-#define NO_ENTRIES 32
-#endif
-
-#ifndef NO_MACRO_ENTRIES
-#define NO_MACRO_ENTRIES 16
-#endif
-
 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x000A
 #endif
 
 
 static int amdgpu_surface_sanity(const struct radeon_surf *surf)
 {
unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
 
if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
-- 
2.7.4

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[Mesa-dev] [PATCH 23/24] gallium/radeon: stop using PIPE_BIND_CUSTOM

[Marek Olšák]

From: Marek Olšák 

it has no effect whatsoever
---
 src/gallium/drivers/r600/evergreen_compute.c| 6 ++
 src/gallium/drivers/r600/r600_shader.c  | 2 +-
 src/gallium/drivers/r600/r600_state_common.c| 4 ++--
 src/gallium/drivers/radeon/r600_query.c | 4 ++--
 src/gallium/drivers/radeon/r600_texture.c   | 3 +--
 src/gallium/drivers/radeon/radeon_video.c   | 2 +-
 src/gallium/drivers/radeonsi/si_hw_context.c| 2 +-
 src/gallium/drivers/radeonsi/si_pipe.c  | 5 ++---
 src/gallium/drivers/radeonsi/si_pipe.h  | 3 +--
 src/gallium/drivers/radeonsi/si_pm4.c   | 2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c | 9 -
 11 files changed, 18 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index fe43f37..f66c9f6 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -80,23 +80,21 @@ writable images will consume TEX slots, VTX slots too 
because of linear indexing
 
 */
 
 struct r600_resource *r600_compute_buffer_alloc_vram(struct r600_screen 
*screen,
 unsigned size)
 {
struct pipe_resource *buffer = NULL;
assert(size);
 
buffer = pipe_buffer_create((struct pipe_screen*) screen,
-   PIPE_BIND_CUSTOM,
-   PIPE_USAGE_IMMUTABLE,
-   size);
+   0, PIPE_USAGE_IMMUTABLE, size);
 
return (struct r600_resource *)buffer;
 }
 
 
 static void evergreen_set_rat(struct r600_pipe_compute *pipe,
  unsigned id,
  struct r600_resource *bo,
  int start,
  int size)
@@ -328,21 +326,21 @@ static void evergreen_compute_upload_input(struct 
pipe_context *ctx,
struct pipe_box box;
struct pipe_transfer *transfer = NULL;
 
if (shader->input_size == 0) {
return;
}
 
if (!shader->kernel_param) {
/* Add space for the grid dimensions */
shader->kernel_param = (struct r600_resource *)
-   pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM,
+   pipe_buffer_create(ctx->screen, 0,
PIPE_USAGE_IMMUTABLE, input_size);
}
 
u_box_1d(0, input_size, );
num_work_groups_start = ctx->transfer_map(ctx,
(struct pipe_resource*)shader->kernel_param,
0, PIPE_TRANSFER_WRITE | PIPE_TRANSFER_DISCARD_RANGE,
, );
global_size_start = num_work_groups_start + (3 * (sizeof(uint) /4));
local_size_start = global_size_start + (3 * (sizeof(uint)) / 4);
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 59a13ec..b5e7b7d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -130,21 +130,21 @@ static void r600_dump_streamout(struct 
pipe_stream_output_info *so)
 }
 
 static int store_shader(struct pipe_context *ctx,
struct r600_pipe_shader *shader)
 {
struct r600_context *rctx = (struct r600_context *)ctx;
uint32_t *ptr, i;
 
if (shader->bo == NULL) {
shader->bo = (struct r600_resource*)
-   pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, 
PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
+   pipe_buffer_create(ctx->screen, 0, 
PIPE_USAGE_IMMUTABLE, shader->shader.bc.ndw * 4);
if (shader->bo == NULL) {
return -ENOMEM;
}
ptr = r600_buffer_map_sync_with_rings(>b, shader->bo, 
PIPE_TRANSFER_WRITE);
if (R600_BIG_ENDIAN) {
for (i = 0; i < shader->shader.bc.ndw; ++i) {
ptr[i] = 
util_cpu_to_le32(shader->shader.bc.bytecode[i]);
}
} else {
memcpy(ptr, shader->shader.bc.bytecode, 
shader->shader.bc.ndw * sizeof(*ptr));
diff --git a/src/gallium/drivers/r600/r600_state_common.c 
b/src/gallium/drivers/r600/r600_state_common.c
index 48c5443..60490b0 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1319,28 +1319,28 @@ static void update_gs_block_state(struct r600_context 
*rctx, unsigned enable)
r600_mark_atom_dirty(rctx, >shader_stages.atom);
}
 
if (rctx->gs_rings.enable != enable) {
rctx->gs_rings.enable = enable;
r600_mark_atom_dirty(rctx, >gs_rings.atom);
 
if (enable && !rctx->gs_rings.esgs_ring.buffer) {
   

[Mesa-dev] [PATCH 21/24] gallium/radeon: remove unused r600_cmask_info members

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.h |  4 
 src/gallium/drivers/radeon/r600_texture.c | 15 +++
 2 files changed, 3 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7689054..d49f9d3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -225,24 +225,20 @@ struct r600_fmask_info {
unsigned pitch_in_pixels;
unsigned bank_height;
unsigned slice_tile_max;
unsigned tile_mode_index;
 };
 
 struct r600_cmask_info {
uint64_t offset;
uint64_t size;
unsigned alignment;
-   unsigned pitch;
-   unsigned height;
-   unsigned xalign;
-   unsigned yalign;
unsigned slice_tile_max;
unsigned base_address_reg;
 };
 
 struct r600_texture {
struct r600_resourceresource;
 
uint64_tsize;
unsignednum_level0_transfers;
enum pipe_formatdb_render_format;
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index f79eae2..db65cd9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -674,24 +674,20 @@ void r600_texture_get_cmask_info(struct 
r600_common_screen *rscreen,
unsigned pitch_elements = align(rtex->resource.b.b.width0, 
macro_tile_width);
unsigned height = align(rtex->resource.b.b.height0, macro_tile_height);
 
unsigned base_align = num_pipes * pipe_interleave_bytes;
unsigned slice_bytes =
((pitch_elements * height * element_bits + 7) / 8) / 
cmask_tile_elements;
 
assert(macro_tile_width % 128 == 0);
assert(macro_tile_height % 128 == 0);
 
-   out->pitch = pitch_elements;
-   out->height = height;
-   out->xalign = macro_tile_width;
-   out->yalign = macro_tile_height;
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
out->size = (util_max_layer(>resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
 }
 
 static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
  struct r600_texture *rtex,
  struct r600_cmask_info *out)
 {
@@ -723,24 +719,20 @@ static void si_texture_get_cmask_info(struct 
r600_common_screen *rscreen,
 
unsigned base_align = num_pipes * pipe_interleave_bytes;
 
unsigned width = align(rtex->resource.b.b.width0, cl_width*8);
unsigned height = align(rtex->resource.b.b.height0, cl_height*8);
unsigned slice_elements = (width * height) / (8*8);
 
/* Each element of CMASK is a nibble. */
unsigned slice_bytes = slice_elements / 2;
 
-   out->pitch = width;
-   out->height = height;
-   out->xalign = cl_width * 8;
-   out->yalign = cl_height * 8;
out->slice_tile_max = (width * height) / (128*128);
if (out->slice_tile_max)
out->slice_tile_max -= 1;
 
out->alignment = MAX2(256, base_align);
out->size = (util_max_layer(>resource.b.b, 0) + 1) *
align(slice_bytes, base_align);
 }
 
 static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -924,25 +916,24 @@ void r600_print_texture_info(struct r600_texture *rtex, 
FILE *f)
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
 
if (rtex->fmask.size)
fprintf(f, "  FMask: offset=%"PRIu64", size=%"PRIu64", 
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
rtex->fmask.offset, rtex->fmask.size, 
rtex->fmask.alignment,
rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
rtex->fmask.slice_tile_max, 
rtex->fmask.tile_mode_index);
 
if (rtex->cmask.size)
-   fprintf(f, "  CMask: offset=%"PRIu64", size=%"PRIu64", 
alignment=%u, pitch=%u, "
-   "height=%u, xalign=%u, yalign=%u, slice_tile_max=%u\n",
+   fprintf(f, "  CMask: offset=%"PRIu64", size=%"PRIu64", 
alignment=%u, "
+   "slice_tile_max=%u\n",
rtex->cmask.offset, rtex->cmask.size, 
rtex->cmask.alignment,
-   rtex->cmask.pitch, rtex->cmask.height, 
rtex->cmask.xalign,
-   rtex->cmask.yalign, rtex->cmask.slice_tile_max);
+   rtex->cmask.slice_tile_max);
 
if (rtex->htile_buffer)
fprintf(f, "  HTile: size=%u, alignment=%u, TC_compatible = 
%u\n",
rtex->htile_buffer->b.b.width0,

[Mesa-dev] [PATCH 12/24] gallium/radeon: remove unnecessary fields from radeon_surf_level

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/r600/evergreen_state.c |  8 
 src/gallium/drivers/r600/r600_state.c  |  8 
 src/gallium/drivers/radeon/r600_texture.c  | 10 --
 src/gallium/drivers/radeon/radeon_winsys.h |  4 
 src/gallium/drivers/radeonsi/si_dma.c  |  8 
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  7 ---
 src/gallium/winsys/radeon/drm/radeon_drm_surface.c |  8 
 7 files changed, 16 insertions(+), 37 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 6344c83..c137964 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3374,21 +3374,21 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
slice_tile_max = (rsrc->surface.level[src_level].nblk_x * 
rsrc->surface.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, 
it's ok even
 * if the linear destination/source have smaller heigh as the 
size of the
 * dma packet will be using the copy_height which is always 
smaller or equal
 * to the linear height
 */
-   height = rsrc->surface.level[src_level].npix_y;
+   height = u_minify(rsrc->resource.b.b.height0, src_level);
detile = 1;
x = src_x;
y = src_y;
z = src_z;
base = rsrc->surface.level[src_level].offset;
addr = rdst->surface.level[dst_level].offset;
addr += rdst->surface.level[dst_level].slice_size * dst_z;
addr += dst_y * pitch + dst_x * bpp;
bank_h = eg_bank_wh(rsrc->surface.bankh);
bank_w = eg_bank_wh(rsrc->surface.bankw);
@@ -3399,21 +3399,21 @@ static void evergreen_dma_copy_tile(struct r600_context 
*rctx,
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
slice_tile_max = (rdst->surface.level[dst_level].nblk_x * 
rdst->surface.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, 
it's ok even
 * if the linear destination/source have smaller heigh as the 
size of the
 * dma packet will be using the copy_height which is always 
smaller or equal
 * to the linear height
 */
-   height = rdst->surface.level[dst_level].npix_y;
+   height = u_minify(rdst->resource.b.b.height0, dst_level);
detile = 0;
x = dst_x;
y = dst_y;
z = dst_z;
base = rdst->surface.level[dst_level].offset;
addr = rsrc->surface.level[src_level].offset;
addr += rsrc->surface.level[src_level].slice_size * src_z;
addr += src_y * pitch + src_x * bpp;
bank_h = eg_bank_wh(rdst->surface.bankh);
bank_w = eg_bank_wh(rdst->surface.bankw);
@@ -3487,22 +3487,22 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
goto fallback;
 
src_x = util_format_get_nblocksx(src->format, src_box->x);
dst_x = util_format_get_nblocksx(src->format, dst_x);
src_y = util_format_get_nblocksy(src->format, src_box->y);
dst_y = util_format_get_nblocksy(src->format, dst_y);
 
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
-   src_w = rsrc->surface.level[src_level].npix_x;
-   dst_w = rdst->surface.level[dst_level].npix_x;
+   src_w = u_minify(rsrc->resource.b.b.width0, src_level);
+   dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
 
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
 
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* FIXME evergreen can do partial blit */
goto fallback;
}
/* the x test here are currently useless (because we don't support 
partial blit)
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 4a94a19..319db63 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2850,40 +2850,40 @@ static boolean 

[Mesa-dev] [PATCH 22/24] r600g: remove a redundant buffer_create helper

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/r600/r600_state.c | 31 ---
 1 file changed, 8 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index b00315d..737d770 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -795,40 +795,20 @@ static void r600_emit_clip_state(struct r600_context 
*rctx, struct r600_atom *at
 
radeon_set_context_reg_seq(cs, R_028E20_PA_CL_UCP0_X, 6*4);
radeon_emit_array(cs, (unsigned*)state, 6*4);
 }
 
 static void r600_set_polygon_stipple(struct pipe_context *ctx,
 const struct pipe_poly_stipple *state)
 {
 }
 
-static struct r600_resource *r600_buffer_create_helper(struct r600_screen 
*rscreen,
-  unsigned size, unsigned 
alignment)
-{
-   struct pipe_resource buffer;
-
-   memset(, 0, sizeof buffer);
-   buffer.target = PIPE_BUFFER;
-   buffer.format = PIPE_FORMAT_R8_UNORM;
-   buffer.bind = PIPE_BIND_CUSTOM;
-   buffer.usage = PIPE_USAGE_DEFAULT;
-   buffer.flags = 0;
-   buffer.width0 = size;
-   buffer.height0 = 1;
-   buffer.depth0 = 1;
-   buffer.array_size = 1;
-
-   return (struct r600_resource*)
-   r600_buffer_create(>b.b, , alignment);
-}
-
 static void r600_init_color_surface(struct r600_context *rctx,
struct r600_surface *surf,
bool force_cmask_fmask)
 {
struct r600_screen *rscreen = rctx->screen;
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
unsigned pitch, slice;
unsigned color_info;
unsigned color_view;
@@ -991,36 +971,41 @@ static void r600_init_color_surface(struct r600_context 
*rctx,
r600_texture_get_fmask_info(>b, rtex, 8, );
 
/* CMASK. */
if (!rctx->dummy_cmask ||
rctx->dummy_cmask->b.b.width0 < cmask.size ||
rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
struct pipe_transfer *transfer;
void *ptr;
 
r600_resource_reference(>dummy_cmask, NULL);
-   rctx->dummy_cmask = r600_buffer_create_helper(rscreen, 
cmask.size, cmask.alignment);
+   rctx->dummy_cmask = (struct r600_resource*)
+   r600_aligned_buffer_create(>b.b, 0,
+  PIPE_USAGE_DEFAULT,
+  cmask.size, 
cmask.alignment);
 
/* Set the contents to 0xCC. */
ptr = pipe_buffer_map(>b.b, 
>dummy_cmask->b.b, PIPE_TRANSFER_WRITE, );
memset(ptr, 0xCC, cmask.size);
pipe_buffer_unmap(>b.b, transfer);
}
r600_resource_reference(>cb_buffer_cmask, 
rctx->dummy_cmask);
 
/* FMASK. */
if (!rctx->dummy_fmask ||
rctx->dummy_fmask->b.b.width0 < fmask.size ||
rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
r600_resource_reference(>dummy_fmask, NULL);
-   rctx->dummy_fmask = r600_buffer_create_helper(rscreen, 
fmask.size, fmask.alignment);
-
+   rctx->dummy_fmask = (struct r600_resource*)
+   r600_aligned_buffer_create(>b.b, 0,
+  PIPE_USAGE_DEFAULT,
+  fmask.size, 
fmask.alignment);
}
r600_resource_reference(>cb_buffer_fmask, 
rctx->dummy_fmask);
 
/* Init the registers. */
color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
surf->cb_color_cmask = 0;
surf->cb_color_fmask = 0;
surf->cb_color_mask = 
S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
  
S_028100_FMASK_TILE_MAX(fmask.slice_tile_max);
}
-- 
2.7.4

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[Mesa-dev] [PATCH 13/24] gallium/radeon: remove r600_htile_info

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.h |  9 -
 src/gallium/drivers/radeon/r600_texture.c | 49 ---
 src/gallium/drivers/radeon/radeon_winsys.h|  1 -
 3 files changed, 21 insertions(+), 38 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1700371..7689054 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -233,28 +233,20 @@ struct r600_cmask_info {
uint64_t size;
unsigned alignment;
unsigned pitch;
unsigned height;
unsigned xalign;
unsigned yalign;
unsigned slice_tile_max;
unsigned base_address_reg;
 };
 
-struct r600_htile_info {
-   unsigned pitch;
-   unsigned height;
-   unsigned xalign;
-   unsigned yalign;
-   unsigned alignment;
-};
-
 struct r600_texture {
struct r600_resourceresource;
 
uint64_tsize;
unsignednum_level0_transfers;
enum pipe_formatdb_render_format;
boolis_depth;
booldb_compatible;
boolcan_sample_z;
boolcan_sample_s;
@@ -266,21 +258,20 @@ struct r600_texture {
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info  fmask;
struct r600_cmask_info  cmask;
struct r600_resource*cmask_buffer;
uint64_tdcc_offset; /* 0 = disabled */
unsignedcb_color_info; /* fast clear enable bit 
*/
unsignedcolor_clear_value[2];
unsignedlast_msaa_resolve_target_micro_mode;
 
/* Depth buffer compression and fast clear. */
-   struct r600_htile_info  htile;
struct r600_resource*htile_buffer;
booltc_compatible_htile;
booldepth_cleared; /* if it was cleared at 
least once */
float   depth_clear_value;
boolstencil_cleared; /* if it was cleared 
at least once */
uint8_t stencil_clear_value;
 
boolnon_disp_tiling; /* R600-Cayman only */
 
/* Whether the texture is a displayable back buffer and needs DCC
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 74977ea..4d4be97 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -796,42 +796,44 @@ static void r600_texture_alloc_cmask_separate(struct 
r600_common_screen *rscreen
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
 
if (rscreen->chip_class >= SI)
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
else
rtex->cb_color_info |= EG_S_028C70_FAST_CLEAR(1);
 
p_atomic_inc(>compressed_colortex_counter);
 }
 
-static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
-   struct r600_texture *rtex)
+static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
+   struct r600_texture *rtex)
 {
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
unsigned num_pipes = rscreen->info.num_tile_pipes;
 
+   rtex->surface.htile_size = 0;
+
if (rscreen->chip_class <= EVERGREEN &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
-   return 0;
+   return;
 
/* HW bug on R6xx. */
if (rscreen->chip_class == R600 &&
(rtex->resource.b.b.width0 > 7680 ||
 rtex->resource.b.b.height0 > 7680))
-   return 0;
+   return;
 
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
-   return 0;
+   return;
 
/* Overalign HTILE on P2 configs to work around GPU hangs in
 * piglit/depthstencil-render-miplevels 585.
 *
 * This has been confirmed to help Kabini & Stoney, where the hangs
 * are always reproducible. I think I have seen the test hang
 * on Carrizo too, though it was very rare there.
 */
if (rscreen->chip_class >= CIK && num_pipes < 4)
num_pipes = 4;
@@ -852,73 +854,66 @@ static 

[Mesa-dev] [PATCH 17/24] gallium/radeon: don't do (fmask.size && cmask.size)

[Marek Olšák]

From: Marek Olšák 

fmask implies that cmask is present too.
---
 src/gallium/drivers/r600/evergreen_state.c | 2 +-
 src/gallium/drivers/r600/r600_state.c  | 2 +-
 src/gallium/drivers/radeonsi/si_state.c| 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index c137964..2167e76 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1295,21 +1295,21 @@ static void evergreen_set_framebuffer_state(struct 
pipe_context *ctx,
r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
 
if (!surf->color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
 
if (!surf->export_16bpc) {
rctx->framebuffer.export_16bpc = false;
}
 
-   if (rtex->fmask.size && rtex->cmask.size) {
+   if (rtex->fmask.size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
 
/* Update alpha-test state dependencies.
 * Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
bool alphatest_bypass = false;
bool export_16bpc = true;
 
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 319db63..b00315d 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1129,21 +1129,21 @@ static void r600_set_framebuffer_state(struct 
pipe_context *ctx,
if (force_cmask_fmask) {
/* re-initialize later without compression */
surf->color_initialized = false;
}
}
 
if (!surf->export_16bpc) {
rctx->framebuffer.export_16bpc = false;
}
 
-   if (rtex->fmask.size && rtex->cmask.size) {
+   if (rtex->fmask.size) {
rctx->framebuffer.compressed_cb_mask |= 1 << i;
}
}
 
/* Update alpha-test state dependencies.
 * Alpha-test is done on the first colorbuffer only. */
if (state->nr_cbufs) {
bool alphatest_bypass = false;
 
surf = (struct r600_surface*)state->cbufs[0];
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 4ae14f7..42689da 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2349,21 +2349,21 @@ static void si_set_framebuffer_state(struct 
pipe_context *ctx,
sctx->framebuffer.spi_shader_col_format_alpha |=
surf->spi_shader_col_format_alpha << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend |=
surf->spi_shader_col_format_blend << (i * 4);
sctx->framebuffer.spi_shader_col_format_blend_alpha |=
surf->spi_shader_col_format_blend_alpha << (i * 4);
 
if (surf->color_is_int8)
sctx->framebuffer.color_is_int8 |= 1 << i;
 
-   if (rtex->fmask.size && rtex->cmask.size) {
+   if (rtex->fmask.size) {
sctx->framebuffer.compressed_cb_mask |= 1 << i;
}
 
if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
sctx->framebuffer.any_dst_linear = true;
 
r600_context_add_resource_size(ctx, surf->base.texture);
 
p_atomic_inc(>framebuffers_bound);
 
-- 
2.7.4

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[Mesa-dev] [PATCH 16/24] gallium/radeon: re-order radeon_surf::dcc and htile members

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/radeon_winsys.h | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index cec1274..2330cdd 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -291,21 +291,26 @@ struct radeon_surf {
 unsignedblk_w:4;
 unsignedblk_h:4;
 unsignedbpe:5;
 uint32_tflags;
 
 /* These are return values. Some of them can be set by the caller, but
  * they will be treated as hints (e.g. bankw, bankh) and might be
  * changed by the calculator.
  */
 uint64_tsurf_size;
+uint64_tdcc_size;
+uint64_thtile_size;
+
 uint32_tsurf_alignment;
+uint32_tdcc_alignment;
+uint32_thtile_alignment;
 
 /* This applies to EG and later. */
 unsignedbankw:4;  /* max 8 */
 unsignedbankh:4;  /* max 8 */
 unsignedmtilea:4; /* max 8 */
 unsignedtile_split:13; /* max 4K */
 unsignedstencil_tile_split:13; /* max 4K */
 unsignedpipe_config:5;  /* max 17 */
 unsignednum_banks:5;/* max 16 */
 unsignedmacro_tile_index:4; /* max 15 */
@@ -316,25 +321,20 @@ struct radeon_surf {
  * compatibility. If either is true, the corresponding plane cannot be
  * sampled from.
  */
 unsigneddepth_adjusted:1;
 unsignedstencil_adjusted:1;
 
 struct radeon_surf_levellevel[RADEON_SURF_MAX_LEVELS];
 struct radeon_surf_levelstencil_level[RADEON_SURF_MAX_LEVELS];
 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
-
-uint64_tdcc_size;
-uint32_tdcc_alignment;
-uint64_thtile_size;
-uint32_thtile_alignment;
 };
 
 struct radeon_bo_list_item {
 uint64_t bo_size;
 uint64_t vm_address;
 uint64_t priority_usage; /* mask of (1 << RADEON_PRIO_*) */
 };
 
 struct radeon_winsys {
 /**
-- 
2.7.4

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[Mesa-dev] [PATCH 09/24] radeon/vce: use nblk_y instead of npix_y

[Marek Olšák]

From: Marek Olšák 

npix_y will be removed. level[0].npix_y will be removed too. nblk_y should
be the same as npix_y if the block height == 1. However, nblk_y is aligned
to the tile size, so it can be greater than npix_y.

If that's a problem, we'll have to save the input height of surface_init
and use that.
---
 src/gallium/drivers/radeon/radeon_vce.c| 4 ++--
 src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 4 ++--
 src/gallium/drivers/radeon/radeon_vce_50.c | 2 +-
 src/gallium/drivers/radeon/radeon_vce_52.c | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce.c 
b/src/gallium/drivers/radeon/radeon_vce.c
index ef93e46..7e7bf2a 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -217,21 +217,21 @@ struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next, 
list);
 }
 
 /**
  * Calculate the offsets into the CPB
  */
 void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
   signed *luma_offset, signed *chroma_offset)
 {
unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
-   unsigned vpitch = align(enc->luma->npix_y, 16);
+   unsigned vpitch = align(enc->luma->level[0].nblk_y, 16);
unsigned fsize = pitch * (vpitch + vpitch / 2);
 
*luma_offset = slot->index * fsize;
*chroma_offset = *luma_offset + pitch * vpitch;
 }
 
 /**
  * destroy this video encoder
  */
 static void rvce_destroy(struct pipe_video_codec *encoder)
@@ -448,21 +448,21 @@ struct pipe_video_codec *rvce_create_encoder(struct 
pipe_context *context,
RVID_ERR("Can't create video buffer.\n");
goto error;
}
 
enc->cpb_num = get_cpb_num(enc);
if (!enc->cpb_num)
goto error;
 
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, 
_surf);
cpb_size = align(tmp_surf->level[0].pitch_bytes, 128);
-   cpb_size = cpb_size * align(tmp_surf->npix_y, 32);
+   cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
if (enc->dual_pipe)
cpb_size +=  RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
tmp_buf->destroy(tmp_buf);
if (!rvid_create_buffer(enc->screen, >cpb, cpb_size, 
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
goto error;
}
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c 
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index fe15ded..f194063 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -89,21 +89,21 @@ static void create(struct rvce_encoder *enc)
RVCE_BEGIN(0x0101); // create cmd
RVCE_CS(0x); // encUseCircularBuffer
RVCE_CS(profiles[enc->base.profile -
PIPE_VIDEO_PROFILE_MPEG4_AVC_BASELINE]); // encProfile
RVCE_CS(enc->base.level); // encLevel
RVCE_CS(0x); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
RVCE_CS(enc->luma->level[0].pitch_bytes); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encRefPicChromaPitch
-   RVCE_CS(align(enc->luma->npix_y, 16) / 8); // encRefYHeightInQw
+   RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(0x); // encRefPic(Addr|Array)Mode, 
encPicStructRestriction, disableRDO
RVCE_END();
 }
 
 static void rate_control(struct rvce_encoder *enc)
 {
RVCE_BEGIN(0x0405); // rate control
RVCE_CS(enc->pic.rate_ctrl.rate_ctrl_method); // encRateControlMethod
RVCE_CS(enc->pic.rate_ctrl.target_bitrate); // 
encRateControlTargetBitRate
RVCE_CS(enc->pic.rate_ctrl.peak_bitrate); // encRateControlPeakBitRate
@@ -316,21 +316,21 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(0x); // pictureStructure
RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
RVCE_CS(0x); // forceRefreshMap
RVCE_CS(0x); // insertAUD
RVCE_CS(0x); // endOfSequence
RVCE_CS(0x); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
  enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
  enc->chroma->level[0].offset); // 
inputPictureChromaAddressHi/Lo
-   RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
+   RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch

[Mesa-dev] [PATCH 03/24] gallium/radeon: use r600_gfx_write_event_eop everywhere

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.c |  4 +++-
 src/gallium/drivers/radeon/r600_query.c   | 17 -
 src/gallium/drivers/radeonsi/si_state_draw.c  | 12 +++-
 3 files changed, 10 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 8350083..1a7a712 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -115,21 +115,23 @@ void r600_gfx_write_event_eop(struct r600_common_context 
*ctx,
radeon_emit(cs, 0); /* unused */
}
 
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs, op);
radeon_emit(cs, va);
radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(data_sel));
radeon_emit(cs, new_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
 
-   r600_emit_reloc(ctx, >gfx, buf, RADEON_USAGE_WRITE, 
RADEON_PRIO_QUERY);
+   if (buf)
+   r600_emit_reloc(ctx, >gfx, buf, RADEON_USAGE_WRITE,
+   RADEON_PRIO_QUERY);
 }
 
 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
 {
unsigned dwords = 6;
 
if (screen->chip_class == CIK)
dwords *= 2;
 
if (!screen->info.has_virtual_memory)
diff --git a/src/gallium/drivers/radeon/r600_query.c 
b/src/gallium/drivers/radeon/r600_query.c
index ac71a43..a5c8595 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -550,26 +550,22 @@ static void r600_query_hw_do_emit_start(struct 
r600_common_context *ctx,
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_SO_STATISTICS:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | 
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0x);
break;
case PIPE_QUERY_TIME_ELAPSED:
-   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-   radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | 
EVENT_INDEX(5));
-   radeon_emit(cs, va);
-   radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0x));
-   radeon_emit(cs, 0);
-   radeon_emit(cs, 0);
+   r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+0, 3, NULL, va, 0, 0);
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | 
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0x);
break;
default:
assert(0);
}
@@ -636,27 +632,22 @@ static void r600_query_hw_do_emit_stop(struct 
r600_common_context *ctx,
va += query->result_size/2;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) | 
EVENT_INDEX(3));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0x);
break;
case PIPE_QUERY_TIME_ELAPSED:
va += 8;
/* fall through */
case PIPE_QUERY_TIMESTAMP:
-   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-   radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) | 
EVENT_INDEX(5));
-   radeon_emit(cs, va);
-   radeon_emit(cs, EOP_DATA_SEL(3) | ((va >> 32) & 0x));
-   radeon_emit(cs, 0);
-   radeon_emit(cs, 0);
-
+   r600_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS,
+0, 3, NULL, va, 0, 0);
fence_va = va + 8;
break;
case PIPE_QUERY_PIPELINE_STATISTICS: {
unsigned sample_size = (query->result_size - 8) / 2;
 
va += sample_size;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | 
EVENT_INDEX(2));
radeon_emit(cs, va);
radeon_emit(cs, (va >> 32) & 0x);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index d18137b..c0e2642 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -733,29 +733,23 @@ void si_emit_cache_flush(struct si_context *sctx)
 S_0085F0_CB0_DEST_BASE_ENA(1) |
 

[Mesa-dev] [PATCH 08/24] gallium/radeon: define RADEON_SURF_MODE_* as enums

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c  | 12 +++-
 src/gallium/drivers/radeon/radeon_winsys.h | 11 +++
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index ca67125..daa743e 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -30,22 +30,23 @@
 #include "util/u_format.h"
 #include "util/u_memory.h"
 #include "util/u_pack_color.h"
 #include "util/u_surface.h"
 #include "os/os_time.h"
 #include 
 #include 
 
 static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
   struct r600_texture *rtex);
-static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
-  const struct pipe_resource *templ);
+static enum radeon_surf_mode
+r600_choose_tiling(struct r600_common_screen *rscreen,
+  const struct pipe_resource *templ);
 
 
 bool r600_prepare_for_dma_blit(struct r600_common_context *rctx,
   struct r600_texture *rdst,
   unsigned dst_level, unsigned dstx,
   unsigned dsty, unsigned dstz,
   struct r600_texture *rsrc,
   unsigned src_level,
   const struct pipe_box *src_box)
 {
@@ -184,21 +185,21 @@ static unsigned r600_texture_get_offset(struct 
r600_texture *rtex, unsigned leve
 
return rtex->surface.level[level].offset +
   box->z * rtex->surface.level[level].slice_size +
   box->y / util_format_get_blockheight(format) * 
rtex->surface.level[level].pitch_bytes +
   box->x / util_format_get_blockwidth(format) * 
util_format_get_blocksize(format);
 }
 
 static int r600_init_surface(struct r600_common_screen *rscreen,
 struct radeon_surf *surface,
 const struct pipe_resource *ptex,
-unsigned array_mode,
+enum radeon_surf_mode array_mode,
 unsigned pitch_in_bytes_override,
 unsigned offset,
 bool is_imported,
 bool is_scanout,
 bool is_flushed_depth,
 bool tc_compatible_htile)
 {
const struct util_format_description *desc =
util_format_description(ptex->format);
bool is_depth, is_stencil;
@@ -1193,22 +1194,23 @@ r600_texture_create_object(struct pipe_screen *screen,
 
if (rscreen->debug_flags & DBG_TEX) {
puts("Texture:");
r600_print_texture_info(rtex, stdout);
fflush(stdout);
}
 
return rtex;
 }
 
-static unsigned r600_choose_tiling(struct r600_common_screen *rscreen,
-  const struct pipe_resource *templ)
+static enum radeon_surf_mode
+r600_choose_tiling(struct r600_common_screen *rscreen,
+  const struct pipe_resource *templ)
 {
const struct util_format_description *desc = 
util_format_description(templ->format);
bool force_tiling = templ->flags & R600_RESOURCE_FLAG_FORCE_TILING;
 
/* MSAA resources must be 2D tiled. */
if (templ->nr_samples > 1)
return RADEON_SURF_MODE_2D;
 
/* Transfer resources should be linear. */
if (templ->flags & R600_RESOURCE_FLAG_TRANSFER)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 75badd0..3bd141e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -250,33 +250,36 @@ struct radeon_bo_metadata {
 uint32_tmetadata[64];
 };
 
 enum radeon_feature_id {
 RADEON_FID_R300_HYPERZ_ACCESS, /* ZMask + HiZ */
 RADEON_FID_R300_CMASK_ACCESS,
 };
 
 #define RADEON_SURF_MAX_LEVEL   32
 
+enum radeon_surf_mode {
+RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
+RADEON_SURF_MODE_1D = 2,
+RADEON_SURF_MODE_2D = 3,
+};
+
 #define RADEON_SURF_TYPE_MASK   0xFF
 #define RADEON_SURF_TYPE_SHIFT  0
 #define RADEON_SURF_TYPE_1D 0
 #define RADEON_SURF_TYPE_2D 1
 #define RADEON_SURF_TYPE_3D 2
 #define RADEON_SURF_TYPE_CUBEMAP3
 #define RADEON_SURF_TYPE_1D_ARRAY   4
 #define RADEON_SURF_TYPE_2D_ARRAY   5
 #define RADEON_SURF_MODE_MASK   0xFF
 #define RADEON_SURF_MODE_SHIFT  8
-#define RADEON_SURF_MODE_LINEAR_ALIGNED 1
-#define RADEON_SURF_MODE_1D 2
-#define RADEON_SURF_MODE_2D 3
 

[Mesa-dev] [PATCH 15/24] gallium/radeon: rename bo_size -> surf_size, bo_alignment -> surf_alignment

[Marek Olšák]

From: Marek Olšák 

these names were misleading.
---
 src/gallium/drivers/radeon/r600_test_dma.c |  2 +-
 src/gallium/drivers/radeon/r600_texture.c  | 10 +-
 src/gallium/drivers/radeon/radeon_video.c  |  4 ++--
 src/gallium/drivers/radeon/radeon_winsys.h |  4 ++--
 src/gallium/drivers/radeonsi/cik_sdma.c|  2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 10 +-
 src/gallium/winsys/radeon/drm/radeon_drm_surface.c |  8 
 7 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_test_dma.c 
b/src/gallium/drivers/radeon/r600_test_dma.c
index 1e60f6a..7f4a8c0 100644
--- a/src/gallium/drivers/radeon/r600_test_dma.c
+++ b/src/gallium/drivers/radeon/r600_test_dma.c
@@ -294,21 +294,21 @@ void r600_test_dma(struct r600_common_screen *rscreen)
   i, tdst.width0, tdst.height0, tdst.array_size,
   array_mode_to_string(rdst->surface.level[0].mode),
   tsrc.width0, tsrc.height0, tsrc.array_size,
   array_mode_to_string(rsrc->surface.level[0].mode), bpp);
fflush(stdout);
 
/* set src pixels */
set_random_pixels(ctx, src, _cpu);
 
/* clear dst pixels */
-   rctx->clear_buffer(ctx, dst, 0, rdst->surface.bo_size, 0, true);
+   rctx->clear_buffer(ctx, dst, 0, rdst->surface.surf_size, 0, 
true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
 
/* preparation */
max_width = MIN2(tsrc.width0, tdst.width0);
max_height = MIN2(tsrc.height0, tdst.height0);
max_depth = MIN2(tsrc.array_size, tdst.array_size);
 
num = do_partial_copies ? num_partial_copies : 1;
for (j = 0; j < num; j++) {
int width, height, depth;
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index dcfa7cd..ca82a74 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -630,22 +630,22 @@ void r600_texture_get_fmask_info(struct 
r600_common_screen *rscreen,
 
assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
 
out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 
64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
 
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
-   out->alignment = MAX2(256, fmask.bo_alignment);
-   out->size = fmask.bo_size;
+   out->alignment = MAX2(256, fmask.surf_alignment);
+   out->size = fmask.surf_size;
 }
 
 static void r600_texture_allocate_fmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
 {
r600_texture_get_fmask_info(rscreen, rtex,
rtex->resource.b.b.nr_samples, 
>fmask);
 
rtex->fmask.offset = align64(rtex->size, rtex->fmask.alignment);
rtex->size = rtex->fmask.offset + rtex->fmask.size;
@@ -909,21 +909,21 @@ void r600_print_texture_info(struct r600_texture *rtex, 
FILE *f)
"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
rtex->resource.b.b.width0, rtex->resource.b.b.height0,
rtex->resource.b.b.depth0, rtex->surface.blk_w,
rtex->surface.blk_h,
rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
rtex->surface.bpe, rtex->resource.b.b.nr_samples,
rtex->surface.flags, 
util_format_short_name(rtex->resource.b.b.format));
 
fprintf(f, "  Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, 
scanout=%u\n",
-   rtex->surface.bo_size, rtex->surface.bo_alignment, 
rtex->surface.bankw,
+   rtex->surface.surf_size, rtex->surface.surf_alignment, 
rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks, 
rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
 
if (rtex->fmask.size)
fprintf(f, "  FMask: offset=%"PRIu64", size=%"PRIu64", 
alignment=%u, pitch_in_pixels=%u, "
"bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
rtex->fmask.offset, rtex->fmask.size, 
rtex->fmask.alignment,
rtex->fmask.pitch_in_pixels, rtex->fmask.bank_height,
rtex->fmask.slice_tile_max, 
rtex->fmask.tile_mode_index);
@@ -1007,21 +1007,21 @@ r600_texture_create_object(struct pipe_screen *screen,
resource->b.b = *base;
resource->b.b.next = NULL;
   

[Mesa-dev] [PATCH 14/24] gallium/radeon: remove flags specific to libdrm_radeon from winsys interface

[Marek Olšák]

From: Marek Olšák 

These just say whether libdrm can assume that the latest radeon_surface
definition is used by Mesa.
---
 src/gallium/drivers/radeon/r600_texture.c  | 14 ++
 src/gallium/drivers/radeon/radeon_winsys.h |  3 +--
 src/gallium/winsys/radeon/drm/radeon_drm_surface.c |  4 +++-
 3 files changed, 6 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 4d4be97..dcfa7cd 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -226,28 +226,22 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
if (tc_compatible_htile &&
array_mode == RADEON_SURF_MODE_2D) {
/* TC-compatible HTILE only supports Z32_FLOAT.
 * Promote Z16 to Z32. DB->CB copies will convert
 * the format for transfers.
 */
bpe = 4;
flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
 
-   if (is_stencil) {
-   flags |= RADEON_SURF_SBUFFER |
-RADEON_SURF_HAS_SBUFFER_MIPTREE;
-   }
-   }
-
-   if (rscreen->chip_class >= SI) {
-   flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
+   if (is_stencil)
+   flags |= RADEON_SURF_SBUFFER;
}
 
if (rscreen->chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
flags |= RADEON_SURF_DISABLE_DCC;
 
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
/* This should catch bugs in gallium users setting incorrect 
flags. */
assert(ptex->nr_samples <= 1 &&
@@ -598,24 +592,20 @@ void r600_texture_get_fmask_info(struct 
r600_common_screen *rscreen,
 
templ.nr_samples = 1;
flags = rtex->surface.flags | RADEON_SURF_FMASK;
 
/* Use the same parameters and tile mode. */
fmask.bankw = rtex->surface.bankw;
fmask.bankh = rtex->surface.bankh;
fmask.mtilea = rtex->surface.mtilea;
fmask.tile_split = rtex->surface.tile_split;
 
-   if (rscreen->chip_class >= SI) {
-   flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
-   }
-
switch (nr_samples) {
case 2:
case 4:
bpe = 1;
if (rscreen->chip_class <= CAYMAN) {
fmask.bankh = 4;
}
break;
case 8:
bpe = 4;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index bf4bb82..29b64c0 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -261,22 +261,21 @@ enum radeon_surf_mode {
 RADEON_SURF_MODE_LINEAR_ALIGNED = 1,
 RADEON_SURF_MODE_1D = 2,
 RADEON_SURF_MODE_2D = 3,
 };
 
 /* the first 16 bits are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_SCANOUT (1 << 16)
 #define RADEON_SURF_ZBUFFER (1 << 17)
 #define RADEON_SURF_SBUFFER (1 << 18)
 #define RADEON_SURF_Z_OR_SBUFFER(RADEON_SURF_ZBUFFER | 
RADEON_SURF_SBUFFER)
-#define RADEON_SURF_HAS_SBUFFER_MIPTREE (1 << 19)
-#define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20)
+/* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK   (1 << 21)
 #define RADEON_SURF_DISABLE_DCC (1 << 22)
 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
 #define RADEON_SURF_IMPORTED(1 << 24)
 
 struct radeon_surf_level {
 uint64_toffset;
 uint64_tslice_size;
 uint64_tdcc_offset;
 uint64_tdcc_fast_clear_size;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index ed61406..e35f8a4 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -105,21 +105,23 @@ static void surf_winsys_to_drm(struct radeon_surface 
*surf_drm,
 surf_drm->blk_h = util_format_get_blockheight(tex->format);
 surf_drm->blk_d = 1;
 surf_drm->array_size = 1;
 surf_drm->last_level = tex->last_level;
 surf_drm->bpe = bpe;
 surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
 
 surf_drm->flags = flags;
 surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
 surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
-surf_drm->flags |= RADEON_SURF_SET(mode, MODE);
+surf_drm->flags |= RADEON_SURF_SET(mode, MODE) |
+   

[Mesa-dev] [PATCH 07/24] gallium/radeon: stop using some input fields from radeon_surface

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/r600/evergreen_state.c |  2 +-
 src/gallium/drivers/r600/r600_state.c  |  2 +-
 src/gallium/drivers/radeon/r600_texture.c  | 32 +++---
 src/gallium/drivers/radeonsi/si_state.c|  4 ++--
 4 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index 58d98a9..6344c83 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1537,21 +1537,21 @@ static void evergreen_emit_framebuffer_state(struct 
r600_context *rctx, struct r
radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i 
* 0x3C,
   
S_028C70_FORMAT(V_028C70_COLOR_INVALID));
continue;
}
 
tex = (struct r600_texture *)cb->base.texture;
reloc = radeon_add_to_buffer_list(>b,
  >b.gfx,
  (struct 
r600_resource*)cb->base.texture,
  RADEON_USAGE_READWRITE,
- tex->surface.nsamples > 1 ?
+ tex->resource.b.b.nr_samples > 1 ?
  
RADEON_PRIO_COLOR_BUFFER_MSAA :
  RADEON_PRIO_COLOR_BUFFER);
 
if (tex->cmask_buffer && tex->cmask_buffer != >resource) {
cmask_reloc = radeon_add_to_buffer_list(>b, 
>b.gfx,
tex->cmask_buffer, RADEON_USAGE_READWRITE,
RADEON_PRIO_CMASK);
} else {
cmask_reloc = reloc;
}
diff --git a/src/gallium/drivers/r600/r600_state.c 
b/src/gallium/drivers/r600/r600_state.c
index 2b58d98..4a94a19 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -749,21 +749,21 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
view->tex_resource = >resource;
view->tex_resource_words[0] = 
(S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
   S_038000_TILE_MODE(array_mode) |
   S_038000_TILE_TYPE(tmp->non_disp_tiling) 
|
   S_038000_PITCH((pitch / 8) - 1) |
   S_038000_TEX_WIDTH(width - 1));
view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
   S_038004_TEX_DEPTH(depth - 1) |
   S_038004_DATA_FORMAT(format));
view->tex_resource_words[2] = tmp->surface.level[offset_level].offset 
>> 8;
-   if (offset_level >= tmp->surface.last_level) {
+   if (offset_level >= tmp->resource.b.b.last_level) {
view->tex_resource_words[3] = 
tmp->surface.level[offset_level].offset >> 8;
} else {
view->tex_resource_words[3] = tmp->surface.level[offset_level + 
1].offset >> 8;
}
view->tex_resource_words[4] = (word4 |
   S_038010_REQUEST_SIZE(1) |
   S_038010_ENDIAN_SWAP(endian) |
   S_038010_BASE_LEVEL(0));
view->tex_resource_words[5] = 
(S_038014_BASE_ARRAY(state->u.tex.first_layer) |
   
S_038014_LAST_ARRAY(state->u.tex.last_layer));
diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 1b1ea66..ca67125 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -282,24 +282,24 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}
 
if (rscreen->chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
surface->flags |= RADEON_SURF_DISABLE_DCC;
 
if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
/* This should catch bugs in gallium users setting incorrect 
flags. */
-   assert(surface->nsamples == 1 &&
-  surface->array_size == 1 &&
-  surface->npix_z == 1 &&
-  surface->last_level == 0 &&
+   assert(ptex->nr_samples <= 1 &&
+  ptex->array_size == 1 &&
+  ptex->depth0 == 1 &&
+  ptex->last_level == 0 &&
   !(surface->flags & RADEON_SURF_Z_OR_SBUFFER));
 
surface->flags |= RADEON_SURF_SCANOUT;
}

[Mesa-dev] [PATCH 02/24] gallium/radeon: make r600_gfx_write_fence more generic

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_pipe_common.c | 35 +++
 src/gallium/drivers/radeon/r600_pipe_common.h |  7 --
 src/gallium/drivers/radeon/r600_query.c   |  3 ++-
 src/gallium/drivers/radeonsi/si_perfcounter.c |  3 ++-
 4 files changed, 34 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index c4b70dc..8350083 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -73,45 +73,60 @@ void radeon_shader_binary_clean(struct radeon_shader_binary 
*b)
FREE(b->global_symbol_offsets);
FREE(b->relocs);
FREE(b->disasm_string);
FREE(b->llvm_ir_string);
 }
 
 /*
  * pipe_context
  */
 
-void r600_gfx_write_fence(struct r600_common_context *ctx, struct 
r600_resource *buf,
- uint64_t va, uint32_t old_value, uint32_t new_value)
+/**
+ * Write an EOP event.
+ *
+ * \param eventEVENT_TYPE_*
+ * \param event_flags  Optional cache flush flags (TC)
+ * \param data_sel 1 = fence, 3 = timestamp
+ * \param buf  Buffer
+ * \param va   GPU address
+ * \param old_valuePrevious fence value (for a bug workaround)
+ * \param new_valueFence value to write for this event.
+ */
+void r600_gfx_write_event_eop(struct r600_common_context *ctx,
+ unsigned event, unsigned event_flags,
+ unsigned data_sel,
+ struct r600_resource *buf, uint64_t va,
+ uint32_t old_fence, uint32_t new_fence)
 {
struct radeon_winsys_cs *cs = ctx->gfx.cs;
+   unsigned op = EVENT_TYPE(event) |
+ EVENT_INDEX(5) |
+ event_flags;
 
if (ctx->chip_class == CIK) {
/* Two EOP events are required to make all engines go idle
 * (and optional cache flushes executed) before the timestamp
 * is written.
 */
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-   radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
-   EVENT_INDEX(5));
+   radeon_emit(cs, op);
radeon_emit(cs, va);
-   radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(1));
-   radeon_emit(cs, old_value); /* immediate data */
+   radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(data_sel));
+   radeon_emit(cs, old_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
}
 
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-   radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
-   EVENT_INDEX(5));
+   radeon_emit(cs, op);
radeon_emit(cs, va);
-   radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(1));
-   radeon_emit(cs, new_value); /* immediate data */
+   radeon_emit(cs, ((va >> 32) & 0x) | EOP_DATA_SEL(data_sel));
+   radeon_emit(cs, new_fence); /* immediate data */
radeon_emit(cs, 0); /* unused */
 
r600_emit_reloc(ctx, >gfx, buf, RADEON_USAGE_WRITE, 
RADEON_PRIO_QUERY);
 }
 
 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen)
 {
unsigned dwords = 6;
 
if (screen->chip_class == CIK)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 5cfcad6..1700371 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -698,22 +698,25 @@ struct pipe_resource * r600_aligned_buffer_create(struct 
pipe_screen *screen,
  unsigned alignment);
 struct pipe_resource *
 r600_buffer_from_user_memory(struct pipe_screen *screen,
 const struct pipe_resource *templ,
 void *user_memory);
 void
 r600_invalidate_resource(struct pipe_context *ctx,
 struct pipe_resource *resource);
 
 /* r600_common_pipe.c */
-void r600_gfx_write_fence(struct r600_common_context *ctx, struct 
r600_resource *buf,
- uint64_t va, uint32_t old_value, uint32_t new_value);
+void r600_gfx_write_event_eop(struct r600_common_context *ctx,
+ unsigned event, unsigned event_flags,
+ unsigned data_sel,
+ struct r600_resource *buf, uint64_t va,
+ uint32_t old_fence, uint32_t new_fence);
 unsigned r600_gfx_write_fence_dwords(struct r600_common_screen *screen);
 void r600_gfx_wait_fence(struct r600_common_context *ctx,
 uint64_t va, uint32_t ref, uint32_t mask);
 void r600_draw_rectangle(struct blitter_context *blitter,
   

[Mesa-dev] [PATCH 00/24] RadeonSI: Massive radeon_surf winsys interface cleanup and more

[Marek Olšák]

Hi,

Most of this series cleans up the radeon_surf-based winsys interface,
and texture, fmask, and metadata (cmask, htile) allocation, and also
other code working with textures.

The series starts with EVENT_WRITE_EOP cleanups and ends with buffer_create
cleanups.

Please review.

Marek
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[Mesa-dev] [PATCH 06/24] gallium/radeon: fold r600_setup_surface into r600_init_surface

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeon/r600_texture.c | 62 ---
 1 file changed, 24 insertions(+), 38 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index c386549..1b1ea66 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -185,26 +185,31 @@ static unsigned r600_texture_get_offset(struct 
r600_texture *rtex, unsigned leve
return rtex->surface.level[level].offset +
   box->z * rtex->surface.level[level].slice_size +
   box->y / util_format_get_blockheight(format) * 
rtex->surface.level[level].pitch_bytes +
   box->x / util_format_get_blockwidth(format) * 
util_format_get_blocksize(format);
 }
 
 static int r600_init_surface(struct r600_common_screen *rscreen,
 struct radeon_surf *surface,
 const struct pipe_resource *ptex,
 unsigned array_mode,
+unsigned pitch_in_bytes_override,
+unsigned offset,
+bool is_imported,
+bool is_scanout,
 bool is_flushed_depth,
 bool tc_compatible_htile)
 {
const struct util_format_description *desc =
util_format_description(ptex->format);
bool is_depth, is_stencil;
+   int r, i;
 
is_depth = util_format_has_depth(desc);
is_stencil = util_format_has_stencil(desc);
 
surface->npix_x = ptex->width0;
surface->npix_y = ptex->height0;
surface->npix_z = ptex->depth0;
surface->blk_w = util_format_get_blockwidth(ptex->format);
surface->blk_h = util_format_get_blockheight(ptex->format);
surface->blk_d = 1;
@@ -275,61 +280,51 @@ static int r600_init_surface(struct r600_common_screen 
*rscreen,
 
if (rscreen->chip_class >= SI) {
surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
}
 
if (rscreen->chip_class >= VI &&
(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
 ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
surface->flags |= RADEON_SURF_DISABLE_DCC;
 
-   if (ptex->bind & PIPE_BIND_SCANOUT) {
+   if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
/* This should catch bugs in gallium users setting incorrect 
flags. */
assert(surface->nsamples == 1 &&
   surface->array_size == 1 &&
   surface->npix_z == 1 &&
   surface->last_level == 0 &&
   !(surface->flags & RADEON_SURF_Z_OR_SBUFFER));
 
surface->flags |= RADEON_SURF_SCANOUT;
}
-   return 0;
-}
 
-static int r600_setup_surface(struct pipe_screen *screen,
- struct r600_texture *rtex,
- unsigned pitch_in_bytes_override,
- unsigned offset)
-{
-   struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-   unsigned i;
-   int r;
+   if (is_imported)
+   surface->flags |= RADEON_SURF_IMPORTED;
 
-   r = rscreen->ws->surface_init(rscreen->ws, >surface);
+   r = rscreen->ws->surface_init(rscreen->ws, surface);
if (r) {
return r;
}
 
-   rtex->size = rtex->surface.bo_size;
-
-   if (pitch_in_bytes_override && pitch_in_bytes_override != 
rtex->surface.level[0].pitch_bytes) {
+   if (pitch_in_bytes_override && pitch_in_bytes_override != 
surface->level[0].pitch_bytes) {
/* old ddx on evergreen over estimate alignment for 1d, only 1 
level
 * for those
 */
-   rtex->surface.level[0].nblk_x = pitch_in_bytes_override / 
rtex->surface.bpe;
-   rtex->surface.level[0].pitch_bytes = pitch_in_bytes_override;
-   rtex->surface.level[0].slice_size = pitch_in_bytes_override * 
rtex->surface.level[0].nblk_y;
+   surface->level[0].nblk_x = pitch_in_bytes_override / 
surface->bpe;
+   surface->level[0].pitch_bytes = pitch_in_bytes_override;
+   surface->level[0].slice_size = pitch_in_bytes_override * 
surface->level[0].nblk_y;
}
 
if (offset) {
-   for (i = 0; i < ARRAY_SIZE(rtex->surface.level); ++i)
-   rtex->surface.level[i].offset += offset;
+   for (i = 0; i < ARRAY_SIZE(surface->level); ++i)
+   surface->level[i].offset += offset;
}
return 0;
 }
 
 static void r600_texture_init_metadata(struct r600_texture *rtex,
   struct radeon_bo_metadata *metadata)
 {
struct radeon_surf *surface = >surface;
 
memset(metadata, 0, 

[Mesa-dev] [PATCH 1/6] i965/miptree: Remove the stencil_as_y_tiled parameter from get_aligned_offset

[Jason Ekstrand]

The only actual user of this parameter was blorp and, since the conversion
to ISL, it no longer uses this function.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_blorp.c |  3 +--
 src/mesa/drivers/dri/i965/brw_misc_state.c|  6 ++
 src/mesa/drivers/dri/i965/gen6_depth_state.c  |  6 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 18 ++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 +--
 5 files changed, 8 insertions(+), 28 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 9484574..60ae840 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -123,8 +123,7 @@ apply_gen6_stencil_hiz_offset(struct isl_surf *surf,
} else {
   *offset = intel_miptree_get_aligned_offset(mt,
  mt->level[lod].level_x,
- mt->level[lod].level_y,
- false);
+ mt->level[lod].level_y);
}
 
surf->logical_level0_px.width = minify(surf->logical_level0_px.width, lod);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index cc62dab..6fce038 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -451,14 +451,12 @@ brw_workaround_depthstencil_alignment(struct brw_context 
*brw,
   brw->depthstencil.depth_offset =
  intel_miptree_get_aligned_offset(depth_mt,
   depth_irb->draw_x & ~tile_mask_x,
-  depth_irb->draw_y & ~tile_mask_y,
-  false);
+  depth_irb->draw_y & ~tile_mask_y);
   if (intel_renderbuffer_has_hiz(depth_irb)) {
  brw->depthstencil.hiz_offset =
 intel_miptree_get_aligned_offset(depth_mt,
  depth_irb->draw_x & ~tile_mask_x,
- (depth_irb->draw_y & 
~tile_mask_y) / 2,
- false);
+ (depth_irb->draw_y & 
~tile_mask_y) / 2);
   }
}
if (stencil_irb) {
diff --git a/src/mesa/drivers/dri/i965/gen6_depth_state.c 
b/src/mesa/drivers/dri/i965/gen6_depth_state.c
index 1a29860..3f14006 100644
--- a/src/mesa/drivers/dri/i965/gen6_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_depth_state.c
@@ -168,8 +168,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
 offset = intel_miptree_get_aligned_offset(
 hiz_mt,
 hiz_mt->level[lod].level_x,
-hiz_mt->level[lod].level_y,
-false);
+hiz_mt->level[lod].level_y);
  }
 
 BEGIN_BATCH(3);
@@ -204,8 +203,7 @@ gen6_emit_depth_stencil_hiz(struct brw_context *brw,
offset = intel_miptree_get_aligned_offset(
stencil_mt,
stencil_mt->level[lod].level_x,
-   stencil_mt->level[lod].level_y,
-   false);
+   stencil_mt->level[lod].level_y);
 }
  }
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index aba203a..866d61f 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -1266,26 +1266,12 @@ intel_get_tile_masks(uint32_t tiling, uint32_t tr_mode, 
uint32_t cpp,
  */
 uint32_t
 intel_miptree_get_aligned_offset(const struct intel_mipmap_tree *mt,
- uint32_t x, uint32_t y,
- bool map_stencil_as_y_tiled)
+ uint32_t x, uint32_t y)
 {
int cpp = mt->cpp;
uint32_t pitch = mt->pitch;
uint32_t tiling = mt->tiling;
 
-   if (map_stencil_as_y_tiled) {
-  tiling = I915_TILING_Y;
-
-  /* When mapping a W-tiled stencil buffer as Y-tiled, each 64-high W-tile
-   * gets transformed into a 32-high Y-tile.  Accordingly, the pitch of
-   * the resulting surface is twice the pitch of the original miptree,
-   * since each row in the Y-tiled view corresponds to two rows in the
-   * actual W-tiled surface.  So we need to correct the pitch before
-   * computing the offsets.
-   */
-  pitch *= 2;
-   }
-
switch (tiling) {
default:
   unreachable("not reached");
@@ -1327,7 +1313,7 @@ intel_miptree_get_tile_offsets(const struct 
intel_mipmap_tree *mt,
*tile_x = x & mask_x;
*tile_y = y & mask_y;
 
-   return intel_miptree_get_aligned_offset(mt, x & ~mask_x, y & ~mask_y, 
false);
+ 

[Mesa-dev] [PATCH 6/6] i965/miptree: Remove the width/height < 32768 restrictions

[Jason Ekstrand]

These restrictions existed because intel_miptree_blit couldn't handle
surfaces bigger than 32k.  How that we're chopping blits up into chunks, it
can handle any size we throw at it so we can get rid of this restriction.
This improves the terrain tests in synmark by 25-30% on my Sky Lake gt3.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/brw_tex_layout.c| 3 +--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 --
 2 files changed, 1 insertion(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c 
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 4618bc0..768f8a8 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -610,8 +610,7 @@ brw_miptree_choose_tiling(struct brw_context *brw,
if (minimum_pitch < 64)
   return I915_TILING_NONE;
 
-   if (ALIGN(minimum_pitch, 512) >= 32768 ||
-   mt->total_width >= 32768 || mt->total_height >= 32768) {
+   if (ALIGN(minimum_pitch, 512) >= 32768) {
   perf_debug("%dx%d miptree too large to blit, falling back to untiled",
  mt->total_width, mt->total_height);
   return I915_TILING_NONE;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 551df4d..551812a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2838,12 +2838,6 @@ static bool
 can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
 {
-   uint32_t image_x;
-   uint32_t image_y;
-   intel_miptree_get_image_offset(mt, level, slice, _x, _y);
-   if (image_x >= 32768 || image_y >= 32768)
-  return false;
-
/* See intel_miptree_blit() for details on the 32k pitch limit. */
if (mt->pitch >= 32768)
   return false;
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/6] i965/blit: Break blits into chunks in intel_miptree_blit

[Jason Ekstrand]

This allows us to blit much larger images than if we use the blitter
directly.  In particular, it gives us an almost infinite image height
compared to the fairly limiting 32k.  We do, however, still have a
restriction on stride of the image because handling larger strides, while
possible, is fairly difficult.

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 65 ++
 1 file changed, 50 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index bc97e66..95d00d3 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -287,21 +287,56 @@ intel_miptree_blit(struct brw_context *brw,
   return false;
}
 
-   if (!intelEmitCopyBlit(brw,
-  src_mt->cpp,
-  src_flip == dst_flip ? src_mt->pitch : 
-src_mt->pitch,
-  src_mt->bo, src_mt->offset,
-  src_mt->tiling,
-  src_mt->tr_mode,
-  dst_mt->pitch,
-  dst_mt->bo, dst_mt->offset,
-  dst_mt->tiling,
-  dst_mt->tr_mode,
-  src_x, src_y,
-  dst_x, dst_y,
-  width, height,
-  logicop)) {
-  return false;
+   const enum isl_tiling src_tiling = intel_miptree_get_isl_tiling(src_mt);
+   const enum isl_tiling dst_tiling = intel_miptree_get_isl_tiling(dst_mt);
+
+   /* We need to split the blit into chunks that each fit within the blitter's
+* restrictions.  We can't use a chunk size of 32768 because wee need to
+* ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
+* a nice round power of two, big enough that performance won't suffer, and
+* small enough to guarantee everything fits.
+*/
+   const uint32_t max_chunk_size = 16384;
+
+   for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
+  for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
+ const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
+ const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
+
+ uint32_t src_offset, src_tile_x, src_tile_y;
+ isl_tiling_get_intratile_offset_el(>isl_dev, src_tiling,
+src_mt->cpp, src_mt->pitch,
+src_x + chunk_x, src_y + chunk_y,
+_offset,
+_tile_x, _tile_y);
+
+ uint32_t dst_offset, dst_tile_x, dst_tile_y;
+ isl_tiling_get_intratile_offset_el(>isl_dev, dst_tiling,
+dst_mt->cpp, dst_mt->pitch,
+dst_x + chunk_x, dst_y + chunk_y,
+_offset,
+_tile_x, _tile_y);
+
+ if (!intelEmitCopyBlit(brw,
+src_mt->cpp,
+src_flip == dst_flip ? src_mt->pitch :
+   -src_mt->pitch,
+src_mt->bo, src_mt->offset + src_offset,
+src_mt->tiling,
+src_mt->tr_mode,
+dst_mt->pitch,
+dst_mt->bo, dst_mt->offset + dst_offset,
+dst_mt->tiling,
+dst_mt->tr_mode,
+src_tile_x, src_tile_y,
+dst_tile_x, dst_tile_y,
+chunk_w, chunk_h,
+logicop)) {
+/* If this is ever going to fail, it will fail on the first chunk 
*/
+assert(chunk_x == 0 && chunk_y == 0);
+return false;
+ }
+  }
}
 
/* XXX This could be done in a single pass using XY_FULL_MONO_PATTERN_BLT */
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 5/6] i965/blit: Break blits into chunks in set_alpha_to_one

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_blit.c | 56 +-
 1 file changed, 41 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c 
b/src/mesa/drivers/dri/i965/intel_blit.c
index 95d00d3..78c4578 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -839,22 +839,48 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
unsigned length = brw->gen >= 8 ? 7 : 6;
bool dst_y_tiled = mt->tiling == I915_TILING_Y;
 
-   BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
-   OUT_BATCH(CMD | (length - 2));
-   OUT_BATCH(BR13);
-   OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
-   OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
-   if (brw->gen >= 8) {
-  OUT_RELOC64(mt->bo,
-  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-  0);
-   } else {
-  OUT_RELOC(mt->bo,
-I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
-0);
+   const enum isl_tiling tiling = intel_miptree_get_isl_tiling(mt);
+
+   /* We need to split the blit into chunks that each fit within the blitter's
+* restrictions.  We can't use a chunk size of 32768 because wee need to
+* ensure that src_tile_x + chunk_size fits.  We choose 16384 because it's
+* a nice round power of two, big enough that performance won't suffer, and
+* small enough to guarantee everything fits.
+*/
+   const uint32_t max_chunk_size = 16384;
+
+   for (uint32_t chunk_x = 0; chunk_x < width; chunk_x += max_chunk_size) {
+  for (uint32_t chunk_y = 0; chunk_y < height; chunk_y += max_chunk_size) {
+ const uint32_t chunk_w = MIN2(max_chunk_size, width - chunk_x);
+ const uint32_t chunk_h = MIN2(max_chunk_size, height - chunk_y);
+
+ uint32_t offset, tile_x, tile_y;
+ isl_tiling_get_intratile_offset_el(>isl_dev, tiling,
+mt->cpp, mt->pitch,
+x + chunk_x, y + chunk_y,
+,
+_x, _y);
+
+ BEGIN_BATCH_BLT_TILED(length, dst_y_tiled, false);
+ OUT_BATCH(CMD | (length - 2));
+ OUT_BATCH(BR13);
+ OUT_BATCH(SET_FIELD(y + chunk_y, BLT_Y) |
+   SET_FIELD(x + chunk_x, BLT_X));
+ OUT_BATCH(SET_FIELD(y + chunk_y + chunk_h, BLT_Y) |
+   SET_FIELD(x + chunk_x + chunk_w, BLT_X));
+ if (brw->gen >= 8) {
+OUT_RELOC64(mt->bo,
+I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+offset);
+ } else {
+OUT_RELOC(mt->bo,
+  I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
+  offset);
+ }
+ OUT_BATCH(0x); /* white, but only alpha gets written */
+ ADVANCE_BATCH_TILED(dst_y_tiled, false);
+  }
}
-   OUT_BATCH(0x); /* white, but only alpha gets written */
-   ADVANCE_BATCH_TILED(dst_y_tiled, false);
 
brw_emit_mi_flush(brw);
 }
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/6] i965/miptree: Break miptree -> ISL tiling conversion into a helper

[Jason Ekstrand]

Signed-off-by: Jason Ekstrand 
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 56 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 ++
 2 files changed, 34 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 866d61f..551df4d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3043,6 +3043,35 @@ get_isl_dim_layout(const struct gen_device_info 
*devinfo, uint32_t tiling,
unreachable("Invalid texture target");
 }
 
+enum isl_tiling
+intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt)
+{
+   if (mt->format == MESA_FORMAT_S_UINT8) {
+  return ISL_TILING_W;
+   } else {
+  switch (mt->tiling) {
+  case I915_TILING_NONE:
+ return ISL_TILING_LINEAR;
+  case I915_TILING_X:
+ return ISL_TILING_X;
+  case I915_TILING_Y:
+ switch (mt->tr_mode) {
+ case INTEL_MIPTREE_TRMODE_NONE:
+return ISL_TILING_Y0;
+ case INTEL_MIPTREE_TRMODE_YF:
+return ISL_TILING_Yf;
+ case INTEL_MIPTREE_TRMODE_YS:
+return ISL_TILING_Ys;
+ default:
+unreachable("Invalid tiled resource mode");
+ }
+ break;
+  default:
+ unreachable("Invalid tiling mode");
+  }
+   }
+}
+
 void
 intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
@@ -3068,38 +3097,15 @@ intel_miptree_get_isl_surf(struct brw_context *brw,
   surf->msaa_layout = ISL_MSAA_LAYOUT_NONE;
}
 
+   surf->tiling = intel_miptree_get_isl_tiling(mt);
+
if (mt->format == MESA_FORMAT_S_UINT8) {
-  surf->tiling = ISL_TILING_W;
   /* The ISL definition of row_pitch matches the surface state pitch field
* a bit better than intel_mipmap_tree.  In particular, ISL incorporates
* the factor of 2 for W-tiling in row_pitch.
*/
   surf->row_pitch = 2 * mt->pitch;
} else {
-  switch (mt->tiling) {
-  case I915_TILING_NONE:
- surf->tiling = ISL_TILING_LINEAR;
- break;
-  case I915_TILING_X:
- surf->tiling = ISL_TILING_X;
- break;
-  case I915_TILING_Y:
- switch (mt->tr_mode) {
- case INTEL_MIPTREE_TRMODE_NONE:
-surf->tiling = ISL_TILING_Y0;
-break;
- case INTEL_MIPTREE_TRMODE_YF:
-surf->tiling = ISL_TILING_Yf;
-break;
- case INTEL_MIPTREE_TRMODE_YS:
-surf->tiling = ISL_TILING_Ys;
-break;
- }
- break;
-  default:
- unreachable("Invalid tiling mode");
-  }
-
   surf->row_pitch = mt->pitch;
}
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index f26a6b0..f69bd4a 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -813,6 +813,9 @@ enum isl_dim_layout
 get_isl_dim_layout(const struct gen_device_info *devinfo, uint32_t tiling,
GLenum target);
 
+enum isl_tiling
+intel_miptree_get_isl_tiling(const struct intel_mipmap_tree *mt);
+
 void
 intel_miptree_get_isl_surf(struct brw_context *brw,
const struct intel_mipmap_tree *mt,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/4] gallium/radeon: fix incorrect bpe use in si_set_optimal_micro_tile_mode

[Marek Olšák]

From: Marek Olšák 

Oh my god, I wonder what catastrophic issues this was causing on SI.

Cc: 13.0 
---
 src/gallium/drivers/radeon/r600_texture.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 625d091..b57cc92 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -2435,43 +2435,43 @@ static void si_set_optimal_micro_tile_mode(struct 
r600_common_screen *rscreen,
rtex->surface.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
} else { /* SI */
switch (rtex->last_msaa_resolve_target_micro_mode) {
case 0: /* displayable */
switch (rtex->surface.bpe) {
-   case 8:
+   case 1:
 rtex->surface.tiling_index[0] = 10;
 break;
-   case 16:
+   case 2:
 rtex->surface.tiling_index[0] = 11;
 break;
-   default: /* 32, 64 */
+   default: /* 4, 8 */
 rtex->surface.tiling_index[0] = 12;
 break;
}
break;
case 1: /* thin */
switch (rtex->surface.bpe) {
-   case 8:
+   case 1:
 rtex->surface.tiling_index[0] = 14;
 break;
-   case 16:
+   case 2:
 rtex->surface.tiling_index[0] = 15;
 break;
-   case 32:
+   case 4:
 rtex->surface.tiling_index[0] = 16;
 break;
-   default: /* 64, 128 */
+   default: /* 8, 16 */
 rtex->surface.tiling_index[0] = 17;
 break;
}
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
}
 
-- 
2.7.4

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[Mesa-dev] [PATCH 2/4] gallium/radeon: make sure the address of separate CMASK is aligned properly

[Marek Olšák]

From: Marek Olšák 

This should fix random GPU hangs on Hawaii and Fiji.

Cc: 11.2 12.0 13.0 
---
 src/gallium/drivers/radeon/r600_texture.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index b57cc92..27035c0 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -819,22 +819,23 @@ static void r600_texture_alloc_cmask_separate(struct 
r600_common_screen *rscreen
 
assert(rtex->cmask.size == 0);
 
if (rscreen->chip_class >= SI) {
si_texture_get_cmask_info(rscreen, rtex, >cmask);
} else {
r600_texture_get_cmask_info(rscreen, rtex, >cmask);
}
 
rtex->cmask_buffer = (struct r600_resource *)
-   pipe_buffer_create(>b, PIPE_BIND_CUSTOM,
-  PIPE_USAGE_DEFAULT, rtex->cmask.size);
+   r600_aligned_buffer_create(>b, 0, PIPE_USAGE_DEFAULT,
+  rtex->cmask.size,
+  rtex->cmask.alignment);
if (rtex->cmask_buffer == NULL) {
rtex->cmask.size = 0;
return;
}
 
/* update colorbuffer state bits */
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
 
if (rscreen->chip_class >= SI)
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1);
-- 
2.7.4

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[Mesa-dev] [PATCH 4/4] radeonsi: enable SDMA on Carrizo and all CIK chips again

[Marek Olšák]

From: Marek Olšák 

SDMA might be fixed by:
  "winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures"
---
 src/gallium/drivers/radeonsi/cik_sdma.c | 10 --
 1 file changed, 10 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c 
b/src/gallium/drivers/radeonsi/cik_sdma.c
index 141fb01..3a18118 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -155,24 +155,20 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 
assert(src_level <= src->last_level);
assert(dst_level <= dst->last_level);
assert(rdst->surface.level[dst_level].offset +
   dst_slice_pitch * bpp * (dstz + src_box->depth) <=
   rdst->resource.buf->size);
assert(rsrc->surface.level[src_level].offset +
   src_slice_pitch * bpp * (srcz + src_box->depth) <=
   rsrc->resource.buf->size);
 
-   /* Test CIK with radeon and amdgpu before enabling this. */
-   if (sctx->b.chip_class == CIK)
-   return false;
-
if (!r600_prepare_for_dma_blit(>b, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
return false;
 
dstx /= rdst->surface.blk_w;
dsty /= rdst->surface.blk_h;
 
if (srcx >= (1 << 14) ||
srcy >= (1 << 14) ||
srcz >= (1 << 11) ||
@@ -510,26 +506,20 @@ static void cik_sdma_copy(struct pipe_context *ctx,
struct si_context *sctx = (struct si_context *)ctx;
 
if (!sctx->b.dma.cs)
goto fallback;
 
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
cik_sdma_copy_buffer(sctx, dst, src, dstx, src_box->x, 
src_box->width);
return;
}
 
-   /* Carrizo SDMA texture copying is very broken for some users.
-* https://bugs.freedesktop.org/show_bug.cgi?id=97029
-*/
-   if (sctx->b.family == CHIP_CARRIZO)
-   goto fallback;
-
if (cik_sdma_copy_texture(sctx, dst, dst_level, dstx, dsty, dstz,
  src, src_level, src_box))
return;
 
 fallback:
si_resource_copy_region(ctx, dst, dst_level, dstx, dsty, dstz,
src, src_level, src_box);
 }
 
 void cik_init_sdma_functions(struct si_context *sctx)
-- 
2.7.4

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[Mesa-dev] [PATCH 0/4] RadeonSI: critical fixes

[Marek Olšák]

Patch 1: SI fix for MSAA for Mesa 13.0. I don't know the impact of that bug.
Patch 2: Possible GPU hang fix for Hawaii and Fiji when using separate CMASK.
Patch 3: Addrlib integration fix that hopefully resolves our SDMA issues.
Patch 4: Let's enable SDMA again.

Please review.

Marek
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[Mesa-dev] [PATCH 3/4] winsys/amdgpu: fix radeon_surf::macro_tile_index for imported textures

[Marek Olšák]

From: Marek Olšák 

Maybe this is why SDMA has been broken for many amdgpu users?

SDMA is the only block which is used with imported textures and relies
on this variable. DB also uses it, but it doesn't get imported textures,
so it's unaffected.

I do get SDMA failures on Tonga before this patch if R600_DEBUG=testdma
is changed to use imported textures.

Cc: 11.2 12.0 13.0 
---
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
index 1bf07a7..c5462bc 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
@@ -296,20 +296,34 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
 struct radeon_info *info)
 {
uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
 
if (info->chip_class >= CIK)
   surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
else
   surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
 }
 
+static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
+{
+   unsigned index, tileb;
+
+   tileb = 8 * 8 * surf->bpe;
+   tileb = MIN2(surf->tile_split, tileb);
+
+   for (index = 0; tileb > 64; index++)
+   tileb >>= 1;
+
+   assert(index < 16);
+   return index;
+}
+
 static int amdgpu_surface_init(struct radeon_winsys *rws,
struct radeon_surf *surf)
 {
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
unsigned level, mode, type;
bool compressed;
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
@@ -468,20 +482,23 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
 else
AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
  }
   } else {
  /* CIK - VI */
  if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
 AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
  else
 AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
+
+ /* Addrlib doesn't set this if tileIndex is forced like above. */
+ AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
   }
}
 
surf->bo_size = 0;
surf->dcc_size = 0;
surf->dcc_alignment = 1;
surf->htile_size = 0;
surf->htile_alignment = 1;
 
/* Calculate texture layout information. */
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] glsl: Skip invariant/precision linker checks for built-in variables.

[Brian Paul]

On 10/19/2016 02:17 PM, Brian Paul wrote:

On 10/19/2016 02:40 PM, Ian Romanick wrote:

On 10/19/2016 11:11 AM, Kenneth Graunke wrote:

Brian found a bug with my "inline built-ins immediately" code for
shaders
which use ftransform() and declare gl_Position invariant:

https://lists.freedesktop.org/archives/mesa-dev/2016-October/132452.html

Before my patch, things worked due to a specific order of operations:

1. link_intrastage_varyings imported the ftransform function into the VS
2. cross_validate_uniforms() ran and signed off that everything matched
3. do_common_optimization did both inlining and invariance propagation,
making the VS/FS versions of gl_ModelViewProjectionMatrix have
different invariant qualifiers...but after the check in step 2,
so we never raised an error.

After my patch, ftransform() is inlined right away, and at compile time,
do_common_optimization propagates the invariant qualifier to the
gl_ModelViewProjectionMatrix.  When the linker eventually happens, it
detects the mismatch.


Why are we marking a uniform as invariant in the first place?  That
sounds boats.


The shader author is marking the gl_Position VS output as invariant and
calling ftransform():

invariant gl_Position;
void main()
{
   gl_Position = ftransform();
}

ftransform() expands into gl_ModelviewProjectionMatrix * gl_Vertex.
Then, afaict, the propagation pass marks gl_ModelviewProjectionMatrix as
invariant, but that disagrees with the original declaration of the
matrix and linking fails.

That's my superficial understanding of it.

Do you want me to hold off on pushing the patch?  I'd really like to get
this or another fix in place.


Ping.  If a more elaborate fix is a ways off, I'd like to commit Ken's 
patch ASAP.


-Brian


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[Mesa-dev] [PATCH] radv/ac/llvm: shadow samplers only return one value.

[Dave Airlie]

From: Dave Airlie 

The intrinsic engine asserts in llvm due to this.

Reported-by: Christoph Haag 
Cc: "13.0" 
Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c3f3fe8..9edeec9 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3515,7 +3515,9 @@ static void visit_tex(struct nir_to_llvm_context *ctx, 
nir_tex_instr *instr)
 
result = build_tex_intrinsic(ctx, instr, );
 
-   if (instr->op == nir_texop_query_levels)
+   if (instr->is_shadow)
+   result = LLVMBuildExtractElement(ctx->builder, result, 
ctx->i32zero, "");
+   else if (instr->op == nir_texop_query_levels)
result = LLVMBuildExtractElement(ctx->builder, result, 
LLVMConstInt(ctx->i32, 3, false), "");
else if (instr->op == nir_texop_txs &&
 instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
-- 
2.5.5

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[Mesa-dev] [AppVeyor] mesa master #2515 completed

[AppVeyor]

Build mesa 2515 completed



Commit 88a618ce86 by Brian Paul on 10/24/2016 8:42 PM:

tgsi: trivial build fix for MSVC\n\nReviewed-by: Marek Olšák 


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Re: [Mesa-dev] [PATCH] tgsi: trivial build fix for MSVC

[Marek Olšák]

The warning can be fixed by using {{0}}. Either way:

Reviewed-by: Marek Olšák 

Marek

On Mon, Oct 24, 2016 at 10:45 PM, Brian Paul  wrote:
> Unfortunately, this fix causes a warning with some versions of gcc
> (such as 4.9.3):
>
> tgsi/tgsi_scan.c: In function 'scan_instruction':
> tgsi/tgsi_scan.c:373:17: warning: missing braces around initializer 
> [-Wmissing-braces]
>   struct tgsi_full_src_register src = {0};
>  ^
> tgsi/tgsi_scan.c:373:17: warning: (near initialization for 'src.Register') 
> [-Wmissing-braces]
> ---
>  src/gallium/auxiliary/tgsi/tgsi_scan.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
> b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> index cbb3eec..2565ab2 100644
> --- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
> +++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
> @@ -370,7 +370,7 @@ scan_instruction(struct tgsi_shader_info *info,
>
> if (fullinst->Instruction.Texture) {
>for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
> - struct tgsi_full_src_register src = {};
> + struct tgsi_full_src_register src = {0};
>
>   src.Register.File = fullinst->TexOffsets[i].File;
>   src.Register.Index = fullinst->TexOffsets[i].Index;
> --
> 1.9.1
>
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[Mesa-dev] [PATCH] tgsi: trivial build fix for MSVC

[Brian Paul]

Unfortunately, this fix causes a warning with some versions of gcc
(such as 4.9.3):

tgsi/tgsi_scan.c: In function 'scan_instruction':
tgsi/tgsi_scan.c:373:17: warning: missing braces around initializer 
[-Wmissing-braces]
  struct tgsi_full_src_register src = {0};
 ^
tgsi/tgsi_scan.c:373:17: warning: (near initialization for 'src.Register') 
[-Wmissing-braces]
---
 src/gallium/auxiliary/tgsi/tgsi_scan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c 
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index cbb3eec..2565ab2 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -370,7 +370,7 @@ scan_instruction(struct tgsi_shader_info *info,
 
if (fullinst->Instruction.Texture) {
   for (i = 0; i < fullinst->Texture.NumOffsets; i++) {
- struct tgsi_full_src_register src = {};
+ struct tgsi_full_src_register src = {0};
 
  src.Register.File = fullinst->TexOffsets[i].File;
  src.Register.Index = fullinst->TexOffsets[i].Index;
-- 
1.9.1

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Re: [Mesa-dev] [PATCH v2] nv50/ir: do not perform global membar for shared memory

[Ilia Mirkin]

Reviewed-by: Ilia Mirkin 

On Mon, Oct 24, 2016 at 3:41 PM, Samuel Pitoiset
 wrote:
> Shared memory is local to CTA, thus we should only wait for
> prior memory writes which are visible to other threads in
> the same CTA, and not at global level. This should speedup
> compute shaders which use shared memory.
>
> v2: - do not use ==
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index b47fc49..91cef81 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -3561,12 +3561,15 @@ Converter::handleInstruction(const struct 
> tgsi_full_instruction *insn)
>geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
>break;
> case TGSI_OPCODE_MEMBAR:
> +   {
> +  uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
>geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
>geni->fixed = 1;
> -  if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
> +  if (!(level & ~(TGSI_MEMBAR_THREAD_GROUP | TGSI_MEMBAR_SHARED)))
>   geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
>else
>   geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
> +   }
>break;
> case TGSI_OPCODE_ATOMUADD:
> case TGSI_OPCODE_ATOMXCHG:
> --
> 2.10.1
>
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Re: [Mesa-dev] [ANNOUNCE] mesa 13.0.0-rc2

[Emil Velikov]

On 24 October 2016 at 20:33, Jason Ekstrand  wrote:
> My three anv ICD patches were nominated but you didn't get them.
>

>> Jason Ekstrand (1):
>>   anv: Suffix the intel_icd file with the host CPU
>>
Here it is, squashed since it should have been way too messy otherwise.

Thanks
Emil
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[Mesa-dev] [AppVeyor] mesa master #2512 failed

[AppVeyor]

Build mesa 2512 failed


Commit f35b1d156b by Marek Olšák on 10/19/2016 11:22 PM:

tgsi/scan: scan texture offset operands\n\nThis seems important considering how much we depend on some of the flags.\n\nReviewed-by: Nicolai Hähnle 


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[Mesa-dev] [PATCH] Revert "wayland: Block for the frame callback in get_back_bo not dri2_swap_buffers"

[Daniel Stone]

This reverts commit 25cc889004aad6d1cab9edd76db898658e347b97, though
since the code has changed, it was applied manually.

The intent of moving blocking from SwapBuffers to get_back_bo, was to
avoid unnecessary triple-buffering by ensuring that the compositor had
fully processed the previous frame before we started rendering. This
means that the only time we would have to resort to triple-buffering
would be when the buffer is directly scanned out, thus saving an extra
buffer for composition anyway.

The 'repaint window' changes introduced in Weston since then, however,
have narrowed the window of time between the frame event being sent and
the repaint loop needing to conclude, to 7ms by default, in order to
reduce latency. This means however that blocking in get_back_bo gives a
maximum of 7ms for the entire GL submission to begin and complete.

Not only this, but if a client is using buffer_age to avoid full
repaints, the buffer-age request will stall in get_back_bo until the
frame callback completes, meaning that the client cannot even calculate
the repaint area before the 7ms window.

The combination of the two meant that WebKit-GTK+ was failing to
achieve full framerate on a Minnowboard, due to spending a great deal of
its time attempting to query the age of the next buffer before redraw.

Revert to the previous behaviour of allowing rendering to begin but
delaying SwapBuffers, unless and until we can find a more gentle
behaviour.

Signed-off-by: Daniel Stone 
Cc: Neil Roberts 
Cc: Kristian Høgsberg 
---
 src/egl/drivers/dri2/platform_wayland.c | 30 ++
 1 file changed, 14 insertions(+), 16 deletions(-)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index ccab192..ba74d33 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -324,14 +324,8 @@ get_back_bo(struct dri2_egl_surface *dri2_surf)
   return -1;
}
 
-   /* We always want to throttle to some event (either a frame callback or
-* a sync request) after the commit so that we can be sure the
-* compositor has had a chance to handle it and send us a release event
-* before we look for a free buffer */
-   while (dri2_surf->throttle_callback != NULL)
-  if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
-dri2_dpy->wl_queue) == -1)
- return -1;
+   /* There might be a buffer release already queued that wasn't processed */
+   wl_display_dispatch_queue_pending(dri2_dpy->wl_dpy, dri2_dpy->wl_queue);
 
if (dri2_surf->back == NULL) {
   for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
@@ -705,6 +699,11 @@ dri2_wl_swap_buffers_with_damage(_EGLDriver *drv,
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
int i;
 
+   while (dri2_surf->throttle_callback != NULL)
+  if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
+dri2_dpy->wl_queue) == -1)
+ return -1;
+
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
   if (dri2_surf->color_buffers[i].age > 0)
  dri2_surf->color_buffers[i].age++;
@@ -1464,14 +1463,8 @@ swrast_update_buffers(struct dri2_egl_surface *dri2_surf)
 
/* find back buffer */
 
-   /* We always want to throttle to some event (either a frame callback or
-* a sync request) after the commit so that we can be sure the
-* compositor has had a chance to handle it and send us a release event
-* before we look for a free buffer */
-   while (dri2_surf->throttle_callback != NULL)
-  if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
-dri2_dpy->wl_queue) == -1)
- return -1;
+   /* There might be a buffer release already queued that wasn't processed */
+   wl_display_dispatch_queue_pending(dri2_dpy->wl_dpy, dri2_dpy->wl_queue);
 
/* try get free buffer already created */
for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
@@ -1552,6 +1545,11 @@ dri2_wl_swrast_commit_backbuffer(struct dri2_egl_surface 
*dri2_surf)
 {
struct dri2_egl_display *dri2_dpy = 
dri2_egl_display(dri2_surf->base.Resource.Display);
 
+   while (dri2_surf->throttle_callback != NULL)
+  if (wl_display_dispatch_queue(dri2_dpy->wl_dpy,
+dri2_dpy->wl_queue) == -1)
+ return -1;
+
if (dri2_surf->base.SwapInterval > 0) {
   dri2_surf->throttle_callback =
  wl_surface_frame(dri2_surf->wl_win->surface);
-- 
2.9.3

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[Mesa-dev] [PATCH v2] nv50/ir: do not perform global membar for shared memory

[Samuel Pitoiset]

Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.

v2: - do not use ==

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index b47fc49..91cef81 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3561,12 +3561,15 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
   break;
case TGSI_OPCODE_MEMBAR:
+   {
+  uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
   geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
   geni->fixed = 1;
-  if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
+  if (!(level & ~(TGSI_MEMBAR_THREAD_GROUP | TGSI_MEMBAR_SHARED)))
  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
   else
  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
+   }
   break;
case TGSI_OPCODE_ATOMUADD:
case TGSI_OPCODE_ATOMXCHG:
-- 
2.10.1

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Re: [Mesa-dev] [PATCH] gallium/radeon: make sure HTILE address is aligned properly

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Mon, Oct 24, 2016 at 9:39 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> This should fix random GPU hangs on Hawaii and Fiji.
> It's already been fixed in 13.0 and later.
>
> Cc: 11.2 12.0 
> ---
>  src/gallium/drivers/radeon/r600_texture.c | 17 ++---
>  1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_texture.c 
> b/src/gallium/drivers/radeon/r600_texture.c
> index 23ddff4..b867f85 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -722,10 +722,11 @@ static void r600_texture_alloc_cmask_separate(struct 
> r600_common_screen *rscreen
>  }
>
>  static unsigned r600_texture_get_htile_size(struct r600_common_screen 
> *rscreen,
> -   struct r600_texture *rtex)
> +   struct r600_texture *rtex,
> +   unsigned *base_align)
>  {
> unsigned cl_width, cl_height, width, height;
> -   unsigned slice_elements, slice_bytes, pipe_interleave_bytes, 
> base_align;
> +   unsigned slice_elements, slice_bytes, pipe_interleave_bytes;
> unsigned num_pipes = rscreen->info.num_tile_pipes;
>
> if (rscreen->chip_class <= EVERGREEN &&
> @@ -787,7 +788,7 @@ static unsigned r600_texture_get_htile_size(struct 
> r600_common_screen *rscreen,
> slice_bytes = slice_elements * 4;
>
> pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
> -   base_align = num_pipes * pipe_interleave_bytes;
> +   *base_align = num_pipes * pipe_interleave_bytes;
>
> rtex->htile.pitch = width;
> rtex->htile.height = height;
> @@ -795,20 +796,22 @@ static unsigned r600_texture_get_htile_size(struct 
> r600_common_screen *rscreen,
> rtex->htile.yalign = cl_height * 8;
>
> return (util_max_layer(>resource.b.b, 0) + 1) *
> -   align(slice_bytes, base_align);
> +   align(slice_bytes, *base_align);
>  }
>
>  static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
> struct r600_texture *rtex)
>  {
> -   unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
> +   unsigned alignment = 0;
> +   unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex,
> + );
>
> if (!htile_size)
> return;
>
> rtex->htile_buffer = (struct r600_resource*)
> -pipe_buffer_create(>b, PIPE_BIND_CUSTOM,
> -   PIPE_USAGE_DEFAULT, 
> htile_size);
> +   r600_aligned_buffer_create(>b, 0, PIPE_USAGE_DEFAULT,
> +  htile_size, alignment);
> if (rtex->htile_buffer == NULL) {
> /* this is not a fatal error as we can still keep rendering
>  * without htile buffer */
> --
> 2.7.4
>
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[Mesa-dev] [PATCH] gallium/radeon: make sure HTILE address is aligned properly

[Marek Olšák]

From: Marek Olšák 

This should fix random GPU hangs on Hawaii and Fiji.
It's already been fixed in 13.0 and later.

Cc: 11.2 12.0 
---
 src/gallium/drivers/radeon/r600_texture.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index 23ddff4..b867f85 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -722,10 +722,11 @@ static void r600_texture_alloc_cmask_separate(struct 
r600_common_screen *rscreen
 }
 
 static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
-   struct r600_texture *rtex)
+   struct r600_texture *rtex,
+   unsigned *base_align)
 {
unsigned cl_width, cl_height, width, height;
-   unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
+   unsigned slice_elements, slice_bytes, pipe_interleave_bytes;
unsigned num_pipes = rscreen->info.num_tile_pipes;
 
if (rscreen->chip_class <= EVERGREEN &&
@@ -787,7 +788,7 @@ static unsigned r600_texture_get_htile_size(struct 
r600_common_screen *rscreen,
slice_bytes = slice_elements * 4;
 
pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
-   base_align = num_pipes * pipe_interleave_bytes;
+   *base_align = num_pipes * pipe_interleave_bytes;
 
rtex->htile.pitch = width;
rtex->htile.height = height;
@@ -795,20 +796,22 @@ static unsigned r600_texture_get_htile_size(struct 
r600_common_screen *rscreen,
rtex->htile.yalign = cl_height * 8;
 
return (util_max_layer(>resource.b.b, 0) + 1) *
-   align(slice_bytes, base_align);
+   align(slice_bytes, *base_align);
 }
 
 static void r600_texture_allocate_htile(struct r600_common_screen *rscreen,
struct r600_texture *rtex)
 {
-   unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex);
+   unsigned alignment = 0;
+   unsigned htile_size = r600_texture_get_htile_size(rscreen, rtex,
+ );
 
if (!htile_size)
return;
 
rtex->htile_buffer = (struct r600_resource*)
-pipe_buffer_create(>b, PIPE_BIND_CUSTOM,
-   PIPE_USAGE_DEFAULT, htile_size);
+   r600_aligned_buffer_create(>b, 0, PIPE_USAGE_DEFAULT,
+  htile_size, alignment);
if (rtex->htile_buffer == NULL) {
/* this is not a fatal error as we can still keep rendering
 * without htile buffer */
-- 
2.7.4

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Re: [Mesa-dev] [ANNOUNCE] mesa 13.0.0-rc2

[Jason Ekstrand]

My three anv ICD patches were nominated but you didn't get them.

On Mon, Oct 24, 2016 at 7:58 AM, Emil Velikov 
wrote:

> The second release candidate for Mesa 13.0.0 is now available.
>
>
> Dave Airlie (2):
>   radv: use emit_icmp for samples_identical
>   radv: allow cmask transitions without fast clear
>
> Emil Velikov (3):
>   automake: don't forget to pick wglext.h in the tarball
>   anv: automake: cleanup the generated json file during make clean
>   Update version to 13.0.0-rc2
>
> Eric Engestrom (1):
>   wsi/wayland: fix error path
>
> Francisco Jerez (2):
>   glapi: Move PrimitiveBoundingBox and BlendBarrier definitions
> into ES3.2 category.
>   Revert "Revert "mapi: export all GLES 3.2 functions in libGLESv2.so""
>
> Ilia Mirkin (2):
>   nv50,nvc0: avoid reading out of bounds when getting bogus so info
>   nv50/ir: process texture offset sources as regular sources
>
> Jason Ekstrand (1):
>   anv: Suffix the intel_icd file with the host CPU
>
> Jonathan Gray (1):
>   mapi: automake: set VISIBILITY_CFLAGS for shared glapi
>
> Nicolai Hähnle (5):
>   st/glsl_to_tgsi: fix block copies of arrays of doubles
>   st/glsl_to_tgsi: fix block copies of arrays of structs
>   st/glsl_to_tgsi: sort input and output decls by TGSI index
>   st/mesa: only set primitive_restart when the restart index is in
> range
>   radeonsi: fix 64-bit loads from LDS
>
> Samuel Pitoiset (1):
>   nvc0: do not break 3D state by pushing MS coordinates on Fermi
>
> Stencel, Joanna (1):
>   egl/wayland: add missing destroy_window callback
>
>
> git tag: mesa-13.0.0-rc2
>
> ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.gz
> MD5:  aa3f0652e0b1a7a8f07686cdea96d56e  mesa-13.0.0-rc2.tar.gz
> SHA1: 9998f5f6639169a18da558295addb3229f04a9c3  mesa-13.0.0-rc2.tar.gz
> SHA256: 82c96ef060d1dbbdb0ba52b25beaa0eabec85a5ddd9a8d49f6d9354b1faa78d7
> mesa-13.0.0-rc2.tar.gz
> PGP:  ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.gz.sig
>
> ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.xz
> MD5:  ac32eb49c8f5ba698013502a0aac79a5  mesa-13.0.0-rc2.tar.xz
> SHA1: e569062ec42ecbe40aa6df0c85f04c27416a378e  mesa-13.0.0-rc2.tar.xz
> SHA256: ef26031a79b915e1643b0ffe5354f8ae774cd445f12b342abac63438f9735a43
> mesa-13.0.0-rc2.tar.xz
> PGP:  ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.xz.sig
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Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers

[Leo Liu]

There are a couple of other issues from a brief test:

1. Compile warnings for presentation.c.

2. When window resized, it's showing corruption, and sometimes 
corruption will stay.


Regards,
Leo


On 10/24/2016 11:27 AM, Nayan Deshmukh wrote:



On Mon, Oct 24, 2016 at 8:48 PM, Christian König 
> wrote:


Nice work, have you been able to fix all the issues you mentioned
on your last mail?

Yes, it fixes all the known issues. But I have only tested it on my 
system.


Additional to that make sure that this set also keeps DRI2
working, in patch #2 it looks like you call the new function
without checking if it's available or not. 



Keep in mind that we possible compile both DRI2 and DRI3 into the
driver, but it can happen that we fallback to DRI2 on runtime.

I missed this case, it will won't work if we fallback to DRI2 on 
runtime I will send a v2 to take care of this.


Regards,
Nayan.

Regards,
Christian.


Am 24.10.2016 um 15:55 schrieb Nayan Deshmukh:

Suggested-by: Leo Liu >
Signed-off-by: Nayan Deshmukh >
---
  src/gallium/auxiliary/vl/vl_winsys.h  | 4 ++
  src/gallium/auxiliary/vl/vl_winsys_dri3.c | 89
+++
  2 files changed, 83 insertions(+), 10 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_winsys.h
b/src/gallium/auxiliary/vl/vl_winsys.h
index 26db9f2..7c56b48 100644
--- a/src/gallium/auxiliary/vl/vl_winsys.h
+++ b/src/gallium/auxiliary/vl/vl_winsys.h
@@ -59,6 +59,10 @@ struct vl_screen
 void *
 (*get_private)(struct vl_screen *vscreen);
  +   void
+   (*set_output_texture)(struct vl_screen *vscreen, struct
pipe_resource *buffer,
+ uint32_t width, uint32_t height);
+
 struct pipe_screen *pscreen;
 struct pipe_loader_device *dev;
  };
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 2929928..44d6f4c 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -56,6 +56,7 @@ struct vl_dri3_buffer
 struct xshmfence *shm_fence;
   bool busy;
+   bool is_external_texture;
 uint32_t width, height, pitch;
  };
  @@ -71,6 +72,9 @@ struct vl_dri3_screen
 xcb_special_event_t *special_event;
   struct pipe_context *pipe;
+   struct pipe_resource *output_texture;
+   uint32_t output_texture_width;
+   uint32_t output_texture_height;
   struct vl_dri3_buffer *back_buffers[BACK_BUFFER_NUM];
 int cur_back;
@@ -105,7 +109,8 @@ dri3_free_back_buffer(struct
vl_dri3_screen *scrn,
 xcb_free_pixmap(scrn->conn, buffer->pixmap);
 xcb_sync_destroy_fence(scrn->conn, buffer->sync_fence);
 xshmfence_unmap_shm(buffer->shm_fence);
-   pipe_resource_reference(>texture, NULL);
+   if (!buffer->is_external_texture)
+  pipe_resource_reference(>texture, NULL);
 if (buffer->linear_texture)
 pipe_resource_reference(>linear_texture, NULL);
 FREE(buffer);
@@ -236,13 +241,24 @@ dri3_alloc_back_buffer(struct
vl_dri3_screen *scrn)
 templ.format = PIPE_FORMAT_B8G8R8X8_UNORM;
 templ.target = PIPE_TEXTURE_2D;
 templ.last_level = 0;
-   templ.width0 = scrn->width;
-   templ.height0 = scrn->height;
+   if (scrn->output_texture) {
+  templ.width0 = (scrn->output_texture_width) ?
+ scrn->output_texture_width :
+  scrn->output_texture->width0;
+  templ.height0 = (scrn->output_texture_height) ?
+ scrn->output_texture_height :
+ scrn->output_texture->height0;
+   } else {
+   templ.width0 = scrn->width;
+   templ.height0 = scrn->height;
+   }
 templ.depth0 = 1;
 templ.array_size = 1;
   if (scrn->is_different_gpu) {
-  buffer->texture =
scrn->base.pscreen->resource_create(scrn->base.pscreen,
+  buffer->texture = (scrn->output_texture) ?
+scrn->output_texture :
+ scrn->base.pscreen->resource_create(scrn->base.pscreen,
  );
if (!buffer->texture)
   goto unmap_shm;
@@ -257,7 +273,9 @@ dri3_alloc_back_buffer(struct
vl_dri3_screen *scrn)
   goto no_linear_texture;
 } else {
templ.bind |= 

Re: [Mesa-dev] [PATCH 4/4] configure.ac: check for Glamor requirements only when needed

[Emil Velikov]

On 24 October 2016 at 19:28, Marek Olšák  wrote:
> On Mon, Oct 24, 2016 at 7:41 PM, Emil Velikov  
> wrote:
>> On 24 October 2016 at 18:21, Marek Olšák  wrote:
>>> On Mon, Oct 24, 2016 at 11:33 AM, Emil Velikov  
>>> wrote:
 On 19 October 2016 at 19:31, Marek Olšák  wrote:
> On Wed, Oct 19, 2016 at 2:40 PM, Emil Velikov  
> wrote:
>> On 18 October 2016 at 23:00, Marek Olšák  wrote:
>>> From: Marek Olšák 
>>>
>>> ---
>>>  configure.ac | 37 +++--
>>>  1 file changed, 27 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/configure.ac b/configure.ac
>>> index 12c8165..17dfafd 100644
>>> --- a/configure.ac
>>> +++ b/configure.ac
>>> @@ -2296,35 +2296,52 @@ dnl Gallium helper functions
>>>  dnl
>>>  gallium_require_llvm() {
>>>  if test "x$MESA_LLVM" = x0; then
>>>  case "$host" in *gnux32) return;; esac
>>>  case "$host_cpu" in
>>>  i*86|x86_64|amd64) AC_MSG_ERROR([LLVM is required to build $1 
>>> on x86 and x86_64]);;
>>>  esac
>>>  fi
>>>  }
>>>
>>> -dnl This is for Glamor. Skip this if OpenGL is disabled.
>>> -require_egl_drm() {
>>> +dnl If EGL/X11 or GLX is enabled, make sure they are usable.
>>> +check_glamor_requirements() {
>>
>> With the previous patches you no longer need this, due to the following:
>>  - The correct option is the default one
>>  - If one is missing libgbm.so, libglamoregl.so will fail to load
>> [with decent commit message]
>>  - With recent fix from Chad, we won't advertise the
>> EGL_MESA_platform_gbm extension when EGL is build w/o it.
>>  - The interface between DRI loaders and drivers is stable. So one
>> shouldn't need to rebuild EGL/gbm if they're only interested in the
>> latest fixes in the radeonsi driver.
>>
>> Either way, if you really want this please use something like the 
>> following:
>>
>> if test x$enable_egl = xyes; then
>>   case "$with_egl_platforms" in
>> *drm*)
>>   ;;
>> *)
>>   AC_MSG_ERROR([--with-egl-platforms=drm is required to build the
>> $1 driver.])
>>   ;;
>>   esac
>> fi
>>
>> One doesn't need any of the enable_opengl, enable_gbm or alike tests.
>> Furthermore glamor relies on the gbm/drm EGL platform so the x11 check
>> is superfluous.
>
> I think there is some misunderstanding.
>
> OpenGL X11/DRI acceleration is enabled by the build system:
> - for GLX by setting $enable_glx = dri
> - for EGL by setting $with_egl_platforms = *x11*
>
> The following code checks if OpenGL on X11/DRI is enabled:
>
> if test "x$enable_opengl" = xno; then
> return 0
> fi
>
> need_glamor=no
>
> if test "x$enable_glx" = xdri; then # GLX
> need_glamor=yes
> fi
>
> case "$with_egl_platforms" in # EGL
> *x11*)
> need_glamor=yes
> ;;
> esac
>
>
 IIRC glamor + glx isn't really an option.
>>>
>>> That's not what it means. It's not about Glamor. If I rename
>>> "need_glamor" to "need_opengl_in_X", will it make more sense? Glamor
>>> is a requirement for OpenGL in X (GLX), so in order to support GLX, we
>>> need Glamor, thus we need EGL/DRM. That's the dependency chain.
>>>
>>> To make it clear:
>>> - GLX depends on X acceleration.
>>> - EGL/X11 also depends on X acceleration.
>> Indeed, and people may want the swrast 'acceleration' for GLX and
>> radeon one for EGL/X11 and vice-versa.
>> Regardless, what gets build and shipped is packaging/distribution decision.
>>
>>> - X acceleration depends on Glamor.
>> Glamor is one way to provide X acceleration.
>
> It's the *only* way to provide X acceleration on radeonsi.
>
>>
>>> - Glamor depends on EGL/DRM and GBM.
>>>
>> Glamor may depend on GBM. Since radeons/mesa drivers rely on
>> Glamor/EGL to be GBM aware they need EGL/DRM. The latter already
>> depends on GBM so we can drop the enable_gbm check.
>
> BTW, xf86-video-amdgpu also depends on GBM. I think it's the only
> vendor-specific DDX that uses GBM. I can remove the check if EGL/DRM
> requires GBM already.
>
>>
>>> Thus, if you enable GLX or EGL/X11, you also need EGL/DRM and GBM.
>>>
>>> Is it clear now?
>>>
>> Guess it's the opposite way - I'm not clear enough :-\
>>
>> We're enforcing packaging/distribution decisions even if people don't
>> need them. We can devote our focus/energy to a) toggle things to sane
>> defaults (thanks for that) and b) have comprehensive messages as
>> people unintentionally, or not shoot themselves in the foot.
>>
>> Please ?
>
> OK, I'll give you an entirely different point of 

Re: [Mesa-dev] [PATCH] isl/format: Correct ASTC entries of format info table

[Nanley Chery]

On Fri, Oct 21, 2016 at 10:47:53PM -0700, Jason Ekstrand wrote:
> Are there separate formats for HDR?  I'm not seeing any.  I guess since the
> HDR is a strict superset of LDR, it doesn't make much sense to have
> separate enums.  In any case, thanks for fixing this!
> 

Correct.

> Reviewed-by: Jason Ekstrand 
> 

Thanks!

> Helper functions are so much better...
> 

Indeed.

> On Fri, Oct 21, 2016 at 3:50 PM, Nanley Chery  wrote:
> 
> > With the isl_format_supports* helpers, we can now conveniently
> > report support for this format on Cherry View.
> >
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92925
> > Signed-off-by: Nanley Chery 
> > ---
> >  src/intel/isl/isl_format.c | 70 +++---
> > 
> >  1 file changed, 42 insertions(+), 28 deletions(-)
> >
> > diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c
> > index daf2d81..98806f4 100644
> > --- a/src/intel/isl/isl_format.c
> > +++ b/src/intel/isl/isl_format.c
> > @@ -307,34 +307,34 @@ static const struct surface_format_info
> > format_info[] = {
> > SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ETC2_EAC_SRGB8_A8)
> > SF(90,  x,  x,  x,  x,  x, 75,  x,  x,x,   R8G8B8_UINT)
> > SF(90,  x,  x,  x,  x,  x, 75,  x,  x,x,   R8G8B8_SINT)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_4X4_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X4_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X5_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X5_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X6_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X5_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X6_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X8_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X5_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X6_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X8_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X10_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_12X10_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_12X12_FLT16)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_4X4_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X4_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X5_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X5_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X6_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X5_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X6_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X8_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X5_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X6_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X8_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,
> >  ASTC_LDR_2D_10X10_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,
> >  ASTC_LDR_2D_12X10_U8SRGB)
> > -   SF(80, 80,  x,  x,  x,  x,  x,  x,  x,x,
> >  ASTC_LDR_2D_12X12_U8SRGB)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_4X4_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X4_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X5_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X5_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_6X6_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X5_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X6_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_8X8_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X5_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X6_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X8_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_10X10_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_12X10_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_12X12_FLT16)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_4X4_U8SRGB)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X4_U8SRGB)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   ASTC_LDR_2D_5X5_U8SRGB)
> > +   SF(90, 90,  x,  x,  x,  x,  x,  x,  x,x,   

Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix mismatch between TGSI BFI/BFE and GLSL

[Roland Scheidegger]

On 10/24/2016 04:05 PM, Nicolai Hähnle wrote:

On 24.10.2016 15:49, Ilia Mirkin wrote:

On Mon, Oct 24, 2016 at 9:43 AM, Nicolai Hähnle 
wrote:

On 24.10.2016 15:38, Nicolai Hähnle wrote:


On 24.10.2016 15:34, Ilia Mirkin wrote:


These work properly on nvc0. I'd rather you work around it in your
backend.



That's not a good solution because of how the opcodes are defined. How
about TGSI_OPCODE_{BFI,[UI]BFE}_GLSL and an associated pipe cap that
gets enabled for nvc0?



Or we can declare that the semantics of BFI/BFE should just be in
line with
what GLSL wants. I don't know if there are other state trackers that
rely on
it, it seems that you were actually the one who introduced the
wording in
tgsi.rst...


Yeah, as part of the ARB_gpu_shader5 bringup. At the time, I believe I
specified them as the DX11 thing since I assumed it was identical to
the GLSL. I've since learned that not to be the case.

If you want to introduce new ops/caps to differentiate the GLSL way
and the DX11 way, that's fine by me. (And I'm not picky about which op
gets the original name...)


Okay. The question is whether anybody actually needs the DX11 way. Since
there's only a nine and not an eleven, I kind of suspect the answer is
'no', and then there's no need for a cap.



Having a solution which works for both would be nice, but I suppose we 
can deal with that once someone really needs to meet the dx11 
requirements. And, a dx11 state tracker could always use masks as 
workaround.


Roland
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[Mesa-dev] [PATCH 1/2] st/omx/dec: result buffers size should match codec decoder size

[Leo Liu]

Otherwise fails the check of matching between decoder size and buffers
size in kernel.

Signed-off-by: Leo Liu 
Cc: 13.0 
---
 src/gallium/state_trackers/omx/vid_dec.c  |  9 ++---
 src/gallium/state_trackers/omx/vid_dec_h264.c | 16 +---
 src/gallium/state_trackers/omx/vid_dec_h265.c | 12 +++-
 3 files changed, 18 insertions(+), 19 deletions(-)

diff --git a/src/gallium/state_trackers/omx/vid_dec.c 
b/src/gallium/state_trackers/omx/vid_dec.c
index 90f435b..e51a747 100644
--- a/src/gallium/state_trackers/omx/vid_dec.c
+++ b/src/gallium/state_trackers/omx/vid_dec.c
@@ -425,24 +425,19 @@ void vid_dec_NeedTarget(vid_dec_PrivateType *priv)
struct pipe_video_buffer templat = {};
struct vl_screen *omx_screen;
struct pipe_screen *pscreen;
-   omx_base_video_PortType *port;
 
omx_screen = priv->screen;
-   port = (omx_base_video_PortType 
*)priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
-
assert(omx_screen);
-   assert(port);
 
pscreen = omx_screen->pscreen;
-
assert(pscreen);
 
if (!priv->target) {
   memset(, 0, sizeof(templat));
 
   templat.chroma_format = PIPE_VIDEO_CHROMA_FORMAT_420;
-  templat.width = port->sPortParam.format.video.nFrameWidth;
-  templat.height = port->sPortParam.format.video.nFrameHeight;
+  templat.width = priv->codec->width;
+  templat.height = priv->codec->height;
   templat.buffer_format = pscreen->get_video_param(
 pscreen,
 PIPE_VIDEO_PROFILE_UNKNOWN,
diff --git a/src/gallium/state_trackers/omx/vid_dec_h264.c 
b/src/gallium/state_trackers/omx/vid_dec_h264.c
index 10f2959..a680844 100644
--- a/src/gallium/state_trackers/omx/vid_dec_h264.c
+++ b/src/gallium/state_trackers/omx/vid_dec_h264.c
@@ -105,13 +105,6 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType 
*priv)
if (priv->frame_started)
   return;
 
-   vid_dec_NeedTarget(priv);
-   if (priv->first_buf_in_frame)
-  priv->timestamp = priv->timestamps[0];
-   priv->first_buf_in_frame = false;
-
-   priv->picture.h264.num_ref_frames = 
priv->picture.h264.pps->sps->max_num_ref_frames;
-
if (!priv->codec) {
   struct pipe_video_codec templat = {};
   omx_base_video_PortType *port;
@@ -128,6 +121,15 @@ static void vid_dec_h264_BeginFrame(vid_dec_PrivateType 
*priv)
 
   priv->codec = priv->pipe->create_video_codec(priv->pipe, );
}
+
+   vid_dec_NeedTarget(priv);
+
+   if (priv->first_buf_in_frame)
+  priv->timestamp = priv->timestamps[0];
+   priv->first_buf_in_frame = false;
+
+   priv->picture.h264.num_ref_frames = 
priv->picture.h264.pps->sps->max_num_ref_frames;
+
priv->picture.h264.slice_count = 0;
priv->codec->begin_frame(priv->codec, priv->target, >picture.base);
priv->frame_started = true;
diff --git a/src/gallium/state_trackers/omx/vid_dec_h265.c 
b/src/gallium/state_trackers/omx/vid_dec_h265.c
index 6deae82..b9ac654 100644
--- a/src/gallium/state_trackers/omx/vid_dec_h265.c
+++ b/src/gallium/state_trackers/omx/vid_dec_h265.c
@@ -612,11 +612,6 @@ static void vid_dec_h265_BeginFrame(vid_dec_PrivateType 
*priv)
if (priv->frame_started)
   return;
 
-   vid_dec_NeedTarget(priv);
-   if (priv->first_buf_in_frame)
-  priv->timestamp = priv->timestamps[0];
-   priv->first_buf_in_frame = false;
-
if (!priv->codec) {
   struct pipe_video_codec templat = {};
 
@@ -629,6 +624,13 @@ static void vid_dec_h265_BeginFrame(vid_dec_PrivateType 
*priv)
   templat.level =  priv->codec_data.h265.level_idc;
   priv->codec = priv->pipe->create_video_codec(priv->pipe, );
}
+
+   vid_dec_NeedTarget(priv);
+
+   if (priv->first_buf_in_frame)
+  priv->timestamp = priv->timestamps[0];
+   priv->first_buf_in_frame = false;
+
priv->codec->begin_frame(priv->codec, priv->target, >picture.base);
priv->frame_started = true;
 }
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] st/omx/dec: disable tunnel for size different case

[Leo Liu]

When the video coded size is different from frame size, we need the result
buffers are same as coded size, which are not size compatible with encode
required size, so that simply use no tunnel for this case instead of frame
by frame converting.

Signed-off-by: Leo Liu 
Cc: 13.0 
---
 src/gallium/state_trackers/omx/vid_dec.c  | 2 +-
 src/gallium/state_trackers/omx/vid_dec.h  | 1 +
 src/gallium/state_trackers/omx/vid_dec_h265.c | 9 +
 3 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/omx/vid_dec.c 
b/src/gallium/state_trackers/omx/vid_dec.c
index e51a747..9a6efb8 100644
--- a/src/gallium/state_trackers/omx/vid_dec.c
+++ b/src/gallium/state_trackers/omx/vid_dec.c
@@ -621,7 +621,7 @@ static void vid_dec_FrameDecoded(OMX_COMPONENTTYPE *comp, 
OMX_BUFFERHEADERTYPE*
}
 
if (input->pInputPortPrivate) {
-  if (output->pInputPortPrivate) {
+  if (output->pInputPortPrivate && !priv->disable_tunnel) {
  struct pipe_video_buffer *tmp, *vbuf, *new_vbuf;
 
  tmp = output->pOutputPortPrivate;
diff --git a/src/gallium/state_trackers/omx/vid_dec.h 
b/src/gallium/state_trackers/omx/vid_dec.h
index 35a5758..90acf7b 100644
--- a/src/gallium/state_trackers/omx/vid_dec.h
+++ b/src/gallium/state_trackers/omx/vid_dec.h
@@ -129,6 +129,7 @@ DERIVEDCLASS(vid_dec_PrivateType, 
omx_base_filter_PrivateType)
bool frame_started; \
unsigned bytes_left; \
const void *slice; \
+   bool disable_tunnel; \
struct vl_compositor compositor; \
struct vl_compositor_state cstate;
 ENDCLASS(vid_dec_PrivateType)
diff --git a/src/gallium/state_trackers/omx/vid_dec_h265.c 
b/src/gallium/state_trackers/omx/vid_dec_h265.c
index b9ac654..3242dbe 100644
--- a/src/gallium/state_trackers/omx/vid_dec_h265.c
+++ b/src/gallium/state_trackers/omx/vid_dec_h265.c
@@ -614,6 +614,8 @@ static void vid_dec_h265_BeginFrame(vid_dec_PrivateType 
*priv)
 
if (!priv->codec) {
   struct pipe_video_codec templat = {};
+  omx_base_video_PortType *port = (omx_base_video_PortType *)
+ priv->ports[OMX_BASE_FILTER_INPUTPORT_INDEX];
 
   templat.profile = priv->profile;
   templat.entrypoint = PIPE_VIDEO_ENTRYPOINT_BITSTREAM;
@@ -623,6 +625,13 @@ static void vid_dec_h265_BeginFrame(vid_dec_PrivateType 
*priv)
   templat.height = priv->codec_data.h265.pic_height_in_luma_samples;
   templat.level =  priv->codec_data.h265.level_idc;
   priv->codec = priv->pipe->create_video_codec(priv->pipe, );
+
+  /* disable transcode tunnel if video size is different from coded size */
+  if (priv->codec_data.h265.pic_width_in_luma_samples !=
+  port->sPortParam.format.video.nFrameWidth ||
+  priv->codec_data.h265.pic_height_in_luma_samples !=
+  port->sPortParam.format.video.nFrameHeight)
+ priv->disable_tunnel = true;
}
 
vid_dec_NeedTarget(priv);
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 4/4] configure.ac: check for Glamor requirements only when needed

[Emil Velikov]

On 24 October 2016 at 18:21, Marek Olšák  wrote:
> On Mon, Oct 24, 2016 at 11:33 AM, Emil Velikov  
> wrote:
>> On 19 October 2016 at 19:31, Marek Olšák  wrote:
>>> On Wed, Oct 19, 2016 at 2:40 PM, Emil Velikov  
>>> wrote:
 On 18 October 2016 at 23:00, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  configure.ac | 37 +++--
>  1 file changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/configure.ac b/configure.ac
> index 12c8165..17dfafd 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -2296,35 +2296,52 @@ dnl Gallium helper functions
>  dnl
>  gallium_require_llvm() {
>  if test "x$MESA_LLVM" = x0; then
>  case "$host" in *gnux32) return;; esac
>  case "$host_cpu" in
>  i*86|x86_64|amd64) AC_MSG_ERROR([LLVM is required to build $1 on 
> x86 and x86_64]);;
>  esac
>  fi
>  }
>
> -dnl This is for Glamor. Skip this if OpenGL is disabled.
> -require_egl_drm() {
> +dnl If EGL/X11 or GLX is enabled, make sure they are usable.
> +check_glamor_requirements() {

 With the previous patches you no longer need this, due to the following:
  - The correct option is the default one
  - If one is missing libgbm.so, libglamoregl.so will fail to load
 [with decent commit message]
  - With recent fix from Chad, we won't advertise the
 EGL_MESA_platform_gbm extension when EGL is build w/o it.
  - The interface between DRI loaders and drivers is stable. So one
 shouldn't need to rebuild EGL/gbm if they're only interested in the
 latest fixes in the radeonsi driver.

 Either way, if you really want this please use something like the 
 following:

 if test x$enable_egl = xyes; then
   case "$with_egl_platforms" in
 *drm*)
   ;;
 *)
   AC_MSG_ERROR([--with-egl-platforms=drm is required to build the
 $1 driver.])
   ;;
   esac
 fi

 One doesn't need any of the enable_opengl, enable_gbm or alike tests.
 Furthermore glamor relies on the gbm/drm EGL platform so the x11 check
 is superfluous.
>>>
>>> I think there is some misunderstanding.
>>>
>>> OpenGL X11/DRI acceleration is enabled by the build system:
>>> - for GLX by setting $enable_glx = dri
>>> - for EGL by setting $with_egl_platforms = *x11*
>>>
>>> The following code checks if OpenGL on X11/DRI is enabled:
>>>
>>> if test "x$enable_opengl" = xno; then
>>> return 0
>>> fi
>>>
>>> need_glamor=no
>>>
>>> if test "x$enable_glx" = xdri; then # GLX
>>> need_glamor=yes
>>> fi
>>>
>>> case "$with_egl_platforms" in # EGL
>>> *x11*)
>>> need_glamor=yes
>>> ;;
>>> esac
>>>
>>>
>> IIRC glamor + glx isn't really an option.
>
> That's not what it means. It's not about Glamor. If I rename
> "need_glamor" to "need_opengl_in_X", will it make more sense? Glamor
> is a requirement for OpenGL in X (GLX), so in order to support GLX, we
> need Glamor, thus we need EGL/DRM. That's the dependency chain.
>
> To make it clear:
> - GLX depends on X acceleration.
> - EGL/X11 also depends on X acceleration.
Indeed, and people may want the swrast 'acceleration' for GLX and
radeon one for EGL/X11 and vice-versa.
Regardless, what gets build and shipped is packaging/distribution decision.

> - X acceleration depends on Glamor.
Glamor is one way to provide X acceleration.

> - Glamor depends on EGL/DRM and GBM.
>
Glamor may depend on GBM. Since radeons/mesa drivers rely on
Glamor/EGL to be GBM aware they need EGL/DRM. The latter already
depends on GBM so we can drop the enable_gbm check.

> Thus, if you enable GLX or EGL/X11, you also need EGL/DRM and GBM.
>
> Is it clear now?
>
Guess it's the opposite way - I'm not clear enough :-\

We're enforcing packaging/distribution decisions even if people don't
need them. We can devote our focus/energy to a) toggle things to sane
defaults (thanks for that) and b) have comprehensive messages as
people unintentionally, or not shoot themselves in the foot.

Please ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH 02/25] intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9

[Lionel Landwerlin]

On 24/10/16 18:02, Jason Ekstrand wrote:
On Mon, Oct 24, 2016 at 8:22 AM, Jason Ekstrand > wrote:


On Oct 24, 2016 2:58 AM, "Lionel Landwerlin"
> wrote:
>
> Reviewed-by: Lionel Landwerlin >
>
> Would adding the single register for gen6 makes sense?

It's not needed for this series but it wouldn't hurt.  I'll add it
to the patch.

 Upon further inspection, that register appears to not exist on gen6.


Sorry, got confused by Ken's response.


> On 22/10/16 18:50, Jason Ekstrand wrote:
>>
>> ---
>>   src/intel/genxml/gen7.xml  | 16 
>>   src/intel/genxml/gen75.xml | 16 
>>   src/intel/genxml/gen8.xml  | 16 
>>   src/intel/genxml/gen9.xml  | 16 
>>   4 files changed, 64 insertions(+)
>>
>> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
>> index a950603..8461bd0 100644
>> --- a/src/intel/genxml/gen7.xml
>> +++ b/src/intel/genxml/gen7.xml
>> @@ -2555,4 +2555,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen75.xml
b/src/intel/genxml/gen75.xml
>> index 2c522d5..168c5cc 100644
>> --- a/src/intel/genxml/gen75.xml
>> +++ b/src/intel/genxml/gen75.xml
>> @@ -2971,4 +2971,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
>> index 73c9265..07672ba 100644
>> --- a/src/intel/genxml/gen8.xml
>> +++ b/src/intel/genxml/gen8.xml
>> @@ -3175,4 +3175,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
>> index 0dfce3f..3ddf63d 100644
>> --- a/src/intel/genxml/gen9.xml
>> +++ b/src/intel/genxml/gen9.xml
>> @@ -3449,4 +3449,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>
>
>




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Re: [Mesa-dev] [PATCH 4/4] configure.ac: check for Glamor requirements only when needed

[Marek Olšák]

On Mon, Oct 24, 2016 at 11:33 AM, Emil Velikov  wrote:
> On 19 October 2016 at 19:31, Marek Olšák  wrote:
>> On Wed, Oct 19, 2016 at 2:40 PM, Emil Velikov  
>> wrote:
>>> On 18 October 2016 at 23:00, Marek Olšák  wrote:
 From: Marek Olšák 

 ---
  configure.ac | 37 +++--
  1 file changed, 27 insertions(+), 10 deletions(-)

 diff --git a/configure.ac b/configure.ac
 index 12c8165..17dfafd 100644
 --- a/configure.ac
 +++ b/configure.ac
 @@ -2296,35 +2296,52 @@ dnl Gallium helper functions
  dnl
  gallium_require_llvm() {
  if test "x$MESA_LLVM" = x0; then
  case "$host" in *gnux32) return;; esac
  case "$host_cpu" in
  i*86|x86_64|amd64) AC_MSG_ERROR([LLVM is required to build $1 on 
 x86 and x86_64]);;
  esac
  fi
  }

 -dnl This is for Glamor. Skip this if OpenGL is disabled.
 -require_egl_drm() {
 +dnl If EGL/X11 or GLX is enabled, make sure they are usable.
 +check_glamor_requirements() {
>>>
>>> With the previous patches you no longer need this, due to the following:
>>>  - The correct option is the default one
>>>  - If one is missing libgbm.so, libglamoregl.so will fail to load
>>> [with decent commit message]
>>>  - With recent fix from Chad, we won't advertise the
>>> EGL_MESA_platform_gbm extension when EGL is build w/o it.
>>>  - The interface between DRI loaders and drivers is stable. So one
>>> shouldn't need to rebuild EGL/gbm if they're only interested in the
>>> latest fixes in the radeonsi driver.
>>>
>>> Either way, if you really want this please use something like the following:
>>>
>>> if test x$enable_egl = xyes; then
>>>   case "$with_egl_platforms" in
>>> *drm*)
>>>   ;;
>>> *)
>>>   AC_MSG_ERROR([--with-egl-platforms=drm is required to build the
>>> $1 driver.])
>>>   ;;
>>>   esac
>>> fi
>>>
>>> One doesn't need any of the enable_opengl, enable_gbm or alike tests.
>>> Furthermore glamor relies on the gbm/drm EGL platform so the x11 check
>>> is superfluous.
>>
>> I think there is some misunderstanding.
>>
>> OpenGL X11/DRI acceleration is enabled by the build system:
>> - for GLX by setting $enable_glx = dri
>> - for EGL by setting $with_egl_platforms = *x11*
>>
>> The following code checks if OpenGL on X11/DRI is enabled:
>>
>> if test "x$enable_opengl" = xno; then
>> return 0
>> fi
>>
>> need_glamor=no
>>
>> if test "x$enable_glx" = xdri; then # GLX
>> need_glamor=yes
>> fi
>>
>> case "$with_egl_platforms" in # EGL
>> *x11*)
>> need_glamor=yes
>> ;;
>> esac
>>
>>
> IIRC glamor + glx isn't really an option.

That's not what it means. It's not about Glamor. If I rename
"need_glamor" to "need_opengl_in_X", will it make more sense? Glamor
is a requirement for OpenGL in X (GLX), so in order to support GLX, we
need Glamor, thus we need EGL/DRM. That's the dependency chain.

To make it clear:
- GLX depends on X acceleration.
- EGL/X11 also depends on X acceleration.
- X acceleration depends on Glamor.
- Glamor depends on EGL/DRM and GBM.

Thus, if you enable GLX or EGL/X11, you also need EGL/DRM and GBM.

Is it clear now?

Marek
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[Mesa-dev] [PATCH] configuire.ac: honour LLVM_LIBDIR when linking against LLVM

[Emil Velikov]

From: Emil Velikov 

Currently if one uses a non-default prefix, the path won't get
propagated and we'll fail at link-time.

A very quick and easy example is to install to /usr/local.
At this point, llvm-config will be picked even without the
--with-llvm-prefix, but regardless of the latter linking will fail.

Currently people can workaround that via LD_LIBRARY_PATH.

Cc: "12.0 13.0" 
Cc: Tom Stellard 
Signed-off-by: Emil Velikov 
---
Can a brave soul, familiar with llvm, help us stop the manual
llvm-config parsing and prep llvm.pc +
llvm-{$component-foo,$component-bar}.pc ?
---
 configure.ac | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index d215b63..7d988f5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1986,8 +1986,6 @@ AC_SUBST([LLVM_BINDIR])
 AC_SUBST([LLVM_CFLAGS])
 AC_SUBST([LLVM_CPPFLAGS])
 AC_SUBST([LLVM_CXXFLAGS])
-AC_SUBST([LLVM_LIBDIR])
-AC_SUBST([LLVM_LIBS])
 AC_SUBST([LLVM_LDFLAGS])
 AC_SUBST([LLVM_INCLUDEDIR])
 AC_SUBST([LLVM_VERSION])
@@ -2540,7 +2538,9 @@ if test "x$MESA_LLVM" != x0; then
 LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --system-libs`"
 fi
 fi
+LLVM_LIBS="$LLVM_LIBDIR $LLVM_LIBS"
 fi
+AC_SUBST([LLVM_LIBS])
 
 AM_CONDITIONAL(HAVE_GALLIUM_SVGA, test "x$HAVE_GALLIUM_SVGA" = xyes)
 AM_CONDITIONAL(HAVE_GALLIUM_I915, test "x$HAVE_GALLIUM_I915" = xyes)
-- 
2.10.0

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Re: [Mesa-dev] [PATCH 02/25] intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9

[Jason Ekstrand]

On Mon, Oct 24, 2016 at 8:22 AM, Jason Ekstrand 
wrote:

> On Oct 24, 2016 2:58 AM, "Lionel Landwerlin" <
> lionel.g.landwer...@intel.com> wrote:
> >
> > Reviewed-by: Lionel Landwerlin 
> >
> > Would adding the single register for gen6 makes sense?
>
> It's not needed for this series but it wouldn't hurt.  I'll add it to the
> patch.
>
 Upon further inspection, that register appears to not exist on gen6.

> > On 22/10/16 18:50, Jason Ekstrand wrote:
> >>
> >> ---
> >>   src/intel/genxml/gen7.xml  | 16 
> >>   src/intel/genxml/gen75.xml | 16 
> >>   src/intel/genxml/gen8.xml  | 16 
> >>   src/intel/genxml/gen9.xml  | 16 
> >>   4 files changed, 64 insertions(+)
> >>
> >> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
> >> index a950603..8461bd0 100644
> >> --- a/src/intel/genxml/gen7.xml
> >> +++ b/src/intel/genxml/gen7.xml
> >> @@ -2555,4 +2555,20 @@
> >>   
> >> 
> >>   +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >>   
> >> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> >> index 2c522d5..168c5cc 100644
> >> --- a/src/intel/genxml/gen75.xml
> >> +++ b/src/intel/genxml/gen75.xml
> >> @@ -2971,4 +2971,20 @@
> >>type="uint"/>
> >> 
> >>   +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >>   
> >> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> >> index 73c9265..07672ba 100644
> >> --- a/src/intel/genxml/gen8.xml
> >> +++ b/src/intel/genxml/gen8.xml
> >> @@ -3175,4 +3175,20 @@
> >>   
> >> 
> >>   +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >>   
> >> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
> >> index 0dfce3f..3ddf63d 100644
> >> --- a/src/intel/genxml/gen9.xml
> >> +++ b/src/intel/genxml/gen9.xml
> >> @@ -3449,4 +3449,20 @@
> >>   
> >> 
> >>   +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >> +  
> >> +
> >>   
> >
> >
> >
>
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix mismatch between TGSI BFI/BFE and GLSL

[Nicolai Hähnle]

On 24.10.2016 17:16, Ilia Mirkin wrote:

On Mon, Oct 24, 2016 at 11:12 AM, Nicolai Hähnle  wrote:

On 24.10.2016 16:44, Ilia Mirkin wrote:

In any case, the GLSL way is backwards-compatible with the DX11 way.
It just specifies some unspecified situations.


No, it isn't -- that's the whole problem :)

Both GLSL and SM5 specify clearly what should happen for the offset=0,
bits=32 case, but they disagree.


Oh. Interesting. Do we have tests for that? (Do they fail on nvc0?
Pretty sure they were passing last I checked...)

I find this very surprising BTW - please double-check.


For SM5: 
https://msdn.microsoft.com/en-us/library/windows/desktop/hh446837(v=vs.85).aspx 
is pretty clear that only the 5 LSBs matter, i.e. bits=32 should be the 
same as bits=0.


For GLSL, the quote is:

  Extracts bits [offset, offset + bits - 1] from value,
  returning them in the least significant bits of the result.
  [...]
  If bits is zero, the result will be zero. The result will
  be undefined if offset or bits is negative, or if the sum
  of offset and bits is _greater_than_ the number of bits used
  to store the operand.

None of this would be a problem if the spec said "greater than or equal 
to" instead.


We have piglit tests for that, which I realize now I forgot to mention 
in the commit message: 
arb_gpu_shader5/execution/built-in-functions/{fs,vs}-bitfield{extract,insert}.


There's also a GL CTS test that checks for this.

Cheers,
Nicolai
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[Mesa-dev] [Bug 97456] Detect wrong driver on AMD r4 graphic gpu

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=97456

Jeremy Huddleston Sequoia  changed:

   What|Removed |Added

 CC||japu...@gmail.com

--- Comment #3 from Jeremy Huddleston Sequoia  ---
*** Bug 98338 has been marked as a duplicate of this bug. ***

-- 
You are receiving this mail because:
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix mismatch between TGSI BFI/BFE and GLSL

[Ilia Mirkin]

On Mon, Oct 24, 2016 at 12:11 PM, Nicolai Hähnle  wrote:
> On 24.10.2016 17:16, Ilia Mirkin wrote:
>>
>> On Mon, Oct 24, 2016 at 11:12 AM, Nicolai Hähnle 
>> wrote:
>>>
>>> On 24.10.2016 16:44, Ilia Mirkin wrote:

 In any case, the GLSL way is backwards-compatible with the DX11 way.
 It just specifies some unspecified situations.
>>>
>>>
>>> No, it isn't -- that's the whole problem :)
>>>
>>> Both GLSL and SM5 specify clearly what should happen for the offset=0,
>>> bits=32 case, but they disagree.
>>
>>
>> Oh. Interesting. Do we have tests for that? (Do they fail on nvc0?
>> Pretty sure they were passing last I checked...)
>>
>> I find this very surprising BTW - please double-check.
>
>
> For SM5:
> https://msdn.microsoft.com/en-us/library/windows/desktop/hh446837(v=vs.85).aspx
> is pretty clear that only the 5 LSBs matter, i.e. bits=32 should be the same
> as bits=0.
>
> For GLSL, the quote is:
>
>   Extracts bits [offset, offset + bits - 1] from value,
>   returning them in the least significant bits of the result.
>   [...]
>   If bits is zero, the result will be zero. The result will
>   be undefined if offset or bits is negative, or if the sum
>   of offset and bits is _greater_than_ the number of bits used
>   to store the operand.
>
> None of this would be a problem if the spec said "greater than or equal to"
> instead.
>
> We have piglit tests for that, which I realize now I forgot to mention in
> the commit message:
> arb_gpu_shader5/execution/built-in-functions/{fs,vs}-bitfield{extract,insert}.
>
> There's also a GL CTS test that checks for this.

Oh. Very sad. So yeah - on NVIDIA hw it's easy to represent either
policy. So they must have made the underlying op work the "GLSL" way
for 32, and on DX11 they probably just take the lower 5 bits of the
offset. (The "BFI" op takes a combo bits/offset argument that has to
be composed first, and that composition is usually done with another
BFI op with fixed bits/offset.)

  -ilia
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Re: [Mesa-dev] [PATCH] egl/android: implement minimal swap_buffers_with_damage

[Emil Velikov]

On 21 October 2016 at 22:07, Rob Herring  wrote:
> Since commit 0a606a400fe3 ("egl: add eglSwapBuffersWithDamageKHR"),
> Android has been broken because the function eglSwapBuffersWithDamageKHR
> is provided regardless of the extension being present. Also, the Android
> meta-EGL always advertises the extension regardless of the underlying
> EGL implementation. As there doesn't seem to be a simple way
> conditionally make the EGL function ptr NULL, just implement a brain
> dead version for Android EGL.
>
Thanks for tracking this down Rob !

So both meta-EGL and users are busted, making a simple genuine patch
break things :-(

> Cc: Rob Clark 
> Cc: Eric Engestrom 
> Cc: Emil Velikov 
> Signed-off-by: Rob Herring 
> ---
>  src/egl/drivers/dri2/platform_android.c | 10 +-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/src/egl/drivers/dri2/platform_android.c 
> b/src/egl/drivers/dri2/platform_android.c
> index 142ef05bd1ea..2a6527a34407 100644
> --- a/src/egl/drivers/dri2/platform_android.c
> +++ b/src/egl/drivers/dri2/platform_android.c
> @@ -483,6 +483,14 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *draw)
> return EGL_TRUE;
>  }
>
> +static EGLBoolean
> +droid_swap_buffers_with_damage(_EGLDriver *drv, _EGLDisplay *disp,
> +   _EGLSurface *draw, const EGLint *rects,
> +   EGLint n_rects)
> +{
> +   return droid_swap_buffers(drv, disp, draw);
> +}
> +
Can we implement dri2_fallback_swap_buffers_with_damage as a wrapper
around .swap_buffers(). This way things will just work everywhere ?

Thanks
Emil
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Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers

[Nayan Deshmukh]

On Mon, Oct 24, 2016 at 8:48 PM, Christian König 
wrote:

> Nice work, have you been able to fix all the issues you mentioned on your
> last mail?
>
> Yes, it fixes all the known issues. But I have only tested it on my
system.

> Additional to that make sure that this set also keeps DRI2 working, in
> patch #2 it looks like you call the new function without checking if it's
> available or not.


>
Keep in mind that we possible compile both DRI2 and DRI3 into the driver,
> but it can happen that we fallback to DRI2 on runtime.
>
> I missed this case, it will won't work if we fallback to DRI2 on runtime I
will send a v2 to take care of this.

Regards,
Nayan.

> Regards,
> Christian.
>
>
> Am 24.10.2016 um 15:55 schrieb Nayan Deshmukh:
>
>> Suggested-by: Leo Liu 
>> Signed-off-by: Nayan Deshmukh 
>> ---
>>   src/gallium/auxiliary/vl/vl_winsys.h  |  4 ++
>>   src/gallium/auxiliary/vl/vl_winsys_dri3.c | 89
>> +++
>>   2 files changed, 83 insertions(+), 10 deletions(-)
>>
>> diff --git a/src/gallium/auxiliary/vl/vl_winsys.h
>> b/src/gallium/auxiliary/vl/vl_winsys.h
>> index 26db9f2..7c56b48 100644
>> --- a/src/gallium/auxiliary/vl/vl_winsys.h
>> +++ b/src/gallium/auxiliary/vl/vl_winsys.h
>> @@ -59,6 +59,10 @@ struct vl_screen
>>  void *
>>  (*get_private)(struct vl_screen *vscreen);
>>   +   void
>> +   (*set_output_texture)(struct vl_screen *vscreen, struct pipe_resource
>> *buffer,
>> + uint32_t width, uint32_t height);
>> +
>>  struct pipe_screen *pscreen;
>>  struct pipe_loader_device *dev;
>>   };
>> diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
>> b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
>> index 2929928..44d6f4c 100644
>> --- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
>> +++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
>> @@ -56,6 +56,7 @@ struct vl_dri3_buffer
>>  struct xshmfence *shm_fence;
>>bool busy;
>> +   bool is_external_texture;
>>  uint32_t width, height, pitch;
>>   };
>>   @@ -71,6 +72,9 @@ struct vl_dri3_screen
>>  xcb_special_event_t *special_event;
>>struct pipe_context *pipe;
>> +   struct pipe_resource *output_texture;
>> +   uint32_t output_texture_width;
>> +   uint32_t output_texture_height;
>>struct vl_dri3_buffer *back_buffers[BACK_BUFFER_NUM];
>>  int cur_back;
>> @@ -105,7 +109,8 @@ dri3_free_back_buffer(struct vl_dri3_screen *scrn,
>>  xcb_free_pixmap(scrn->conn, buffer->pixmap);
>>  xcb_sync_destroy_fence(scrn->conn, buffer->sync_fence);
>>  xshmfence_unmap_shm(buffer->shm_fence);
>> -   pipe_resource_reference(>texture, NULL);
>> +   if (!buffer->is_external_texture)
>> +  pipe_resource_reference(>texture, NULL);
>>  if (buffer->linear_texture)
>>  pipe_resource_reference(>linear_texture, NULL);
>>  FREE(buffer);
>> @@ -236,13 +241,24 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
>>  templ.format = PIPE_FORMAT_B8G8R8X8_UNORM;
>>  templ.target = PIPE_TEXTURE_2D;
>>  templ.last_level = 0;
>> -   templ.width0 = scrn->width;
>> -   templ.height0 = scrn->height;
>> +   if (scrn->output_texture) {
>> +  templ.width0 = (scrn->output_texture_width) ?
>> + scrn->output_texture_width :
>> + scrn->output_texture->width0;
>> +  templ.height0 = (scrn->output_texture_height) ?
>> +  scrn->output_texture_height :
>> +  scrn->output_texture->height0;
>> +   } else {
>> +   templ.width0 = scrn->width;
>> +   templ.height0 = scrn->height;
>> +   }
>>  templ.depth0 = 1;
>>  templ.array_size = 1;
>>if (scrn->is_different_gpu) {
>> -  buffer->texture = scrn->base.pscreen->resource_c
>> reate(scrn->base.pscreen,
>> +  buffer->texture = (scrn->output_texture) ?
>> +scrn->output_texture :
>> +scrn->base.pscreen->resource_c
>> reate(scrn->base.pscreen,
>>   );
>> if (!buffer->texture)
>>goto unmap_shm;
>> @@ -257,7 +273,9 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
>>goto no_linear_texture;
>>  } else {
>> templ.bind |= PIPE_BIND_SCANOUT | PIPE_BIND_SHARED;
>> -  buffer->texture = scrn->base.pscreen->resource_c
>> reate(scrn->base.pscreen,
>> +  buffer->texture = (scrn->output_texture) ?
>> +scrn->output_texture :
>> +scrn->base.pscreen->resource_c
>> reate(scrn->base.pscreen,
>>   );
>> if (!buffer->texture)
>>goto unmap_shm;
>> @@ -271,11 +289,20 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
>>  usage);
>>  buffer_fd = whandle.handle;
>>  buffer->pitch = whandle.stride;
>> +   

Re: [Mesa-dev] [PATCH 02/25] intel/genxml: Add SO_WRITE_OFFSET registers for gen7-9

[Jason Ekstrand]

On Oct 24, 2016 2:58 AM, "Lionel Landwerlin" 
wrote:
>
> Reviewed-by: Lionel Landwerlin 
>
> Would adding the single register for gen6 makes sense?

It's not needed for this series but it wouldn't hurt.  I'll add it to the
patch.

> On 22/10/16 18:50, Jason Ekstrand wrote:
>>
>> ---
>>   src/intel/genxml/gen7.xml  | 16 
>>   src/intel/genxml/gen75.xml | 16 
>>   src/intel/genxml/gen8.xml  | 16 
>>   src/intel/genxml/gen9.xml  | 16 
>>   4 files changed, 64 insertions(+)
>>
>> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
>> index a950603..8461bd0 100644
>> --- a/src/intel/genxml/gen7.xml
>> +++ b/src/intel/genxml/gen7.xml
>> @@ -2555,4 +2555,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
>> index 2c522d5..168c5cc 100644
>> --- a/src/intel/genxml/gen75.xml
>> +++ b/src/intel/genxml/gen75.xml
>> @@ -2971,4 +2971,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
>> index 73c9265..07672ba 100644
>> --- a/src/intel/genxml/gen8.xml
>> +++ b/src/intel/genxml/gen8.xml
>> @@ -3175,4 +3175,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
>> index 0dfce3f..3ddf63d 100644
>> --- a/src/intel/genxml/gen9.xml
>> +++ b/src/intel/genxml/gen9.xml
>> @@ -3449,4 +3449,20 @@
>>   
>> 
>>   +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>> +  
>> +
>>   
>
>
>
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Re: [Mesa-dev] [PATCH 1/3] vl/dri3: use external texture as back buffers

[Christian König]

Nice work, have you been able to fix all the issues you mentioned on 
your last mail?


Additional to that make sure that this set also keeps DRI2 working, in 
patch #2 it looks like you call the new function without checking if 
it's available or not.


Keep in mind that we possible compile both DRI2 and DRI3 into the 
driver, but it can happen that we fallback to DRI2 on runtime.


Regards,
Christian.

Am 24.10.2016 um 15:55 schrieb Nayan Deshmukh:

Suggested-by: Leo Liu 
Signed-off-by: Nayan Deshmukh 
---
  src/gallium/auxiliary/vl/vl_winsys.h  |  4 ++
  src/gallium/auxiliary/vl/vl_winsys_dri3.c | 89 +++
  2 files changed, 83 insertions(+), 10 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_winsys.h 
b/src/gallium/auxiliary/vl/vl_winsys.h
index 26db9f2..7c56b48 100644
--- a/src/gallium/auxiliary/vl/vl_winsys.h
+++ b/src/gallium/auxiliary/vl/vl_winsys.h
@@ -59,6 +59,10 @@ struct vl_screen
 void *
 (*get_private)(struct vl_screen *vscreen);
  
+   void

+   (*set_output_texture)(struct vl_screen *vscreen, struct pipe_resource 
*buffer,
+ uint32_t width, uint32_t height);
+
 struct pipe_screen *pscreen;
 struct pipe_loader_device *dev;
  };
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 2929928..44d6f4c 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -56,6 +56,7 @@ struct vl_dri3_buffer
 struct xshmfence *shm_fence;
  
 bool busy;

+   bool is_external_texture;
 uint32_t width, height, pitch;
  };
  
@@ -71,6 +72,9 @@ struct vl_dri3_screen

 xcb_special_event_t *special_event;
  
 struct pipe_context *pipe;

+   struct pipe_resource *output_texture;
+   uint32_t output_texture_width;
+   uint32_t output_texture_height;
  
 struct vl_dri3_buffer *back_buffers[BACK_BUFFER_NUM];

 int cur_back;
@@ -105,7 +109,8 @@ dri3_free_back_buffer(struct vl_dri3_screen *scrn,
 xcb_free_pixmap(scrn->conn, buffer->pixmap);
 xcb_sync_destroy_fence(scrn->conn, buffer->sync_fence);
 xshmfence_unmap_shm(buffer->shm_fence);
-   pipe_resource_reference(>texture, NULL);
+   if (!buffer->is_external_texture)
+  pipe_resource_reference(>texture, NULL);
 if (buffer->linear_texture)
 pipe_resource_reference(>linear_texture, NULL);
 FREE(buffer);
@@ -236,13 +241,24 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
 templ.format = PIPE_FORMAT_B8G8R8X8_UNORM;
 templ.target = PIPE_TEXTURE_2D;
 templ.last_level = 0;
-   templ.width0 = scrn->width;
-   templ.height0 = scrn->height;
+   if (scrn->output_texture) {
+  templ.width0 = (scrn->output_texture_width) ?
+ scrn->output_texture_width :
+ scrn->output_texture->width0;
+  templ.height0 = (scrn->output_texture_height) ?
+  scrn->output_texture_height :
+  scrn->output_texture->height0;
+   } else {
+   templ.width0 = scrn->width;
+   templ.height0 = scrn->height;
+   }
 templ.depth0 = 1;
 templ.array_size = 1;
  
 if (scrn->is_different_gpu) {

-  buffer->texture = scrn->base.pscreen->resource_create(scrn->base.pscreen,
+  buffer->texture = (scrn->output_texture) ?
+scrn->output_texture :
+scrn->base.pscreen->resource_create(scrn->base.pscreen,
  );
if (!buffer->texture)
   goto unmap_shm;
@@ -257,7 +273,9 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
   goto no_linear_texture;
 } else {
templ.bind |= PIPE_BIND_SCANOUT | PIPE_BIND_SHARED;
-  buffer->texture = scrn->base.pscreen->resource_create(scrn->base.pscreen,
+  buffer->texture = (scrn->output_texture) ?
+scrn->output_texture :
+scrn->base.pscreen->resource_create(scrn->base.pscreen,
  );
if (!buffer->texture)
   goto unmap_shm;
@@ -271,11 +289,20 @@ dri3_alloc_back_buffer(struct vl_dri3_screen *scrn)
 usage);
 buffer_fd = whandle.handle;
 buffer->pitch = whandle.stride;
+   buffer->width = templ.width0;
+   buffer->height = templ.height0;
+   buffer->is_external_texture = (scrn->output_texture) ?
+ true :
+ false;
+   scrn->output_texture = NULL;
+   scrn->output_texture_width = 0;
+   scrn->output_texture_height = 0;
+
 xcb_dri3_pixmap_from_buffer(scrn->conn,
 (pixmap = xcb_generate_id(scrn->conn)),
 scrn->drawable,
 0,
-   scrn->width, scrn->height, buffer->pitch,
+

Re: [Mesa-dev] [PATCH 4/4] configure.ac: check for Glamor requirements only when needed

[Emil Velikov]

On 24 October 2016 at 10:47, Michel Dänzer  wrote:
> On 24/10/16 06:33 PM, Emil Velikov wrote:
>>
>> IIRC glamor + glx isn't really an option.
>
> That's true for Xorg, because Xorg is the thing which provides GLX in
> the first place, so it cannot use GLX itself. (glamor on GLX works in
> Xephyr though)
>
>
>> So as we look the !glamor case (hmm does newer radeons have
>> acceleration in those cases ?)
>
> Not in X.
>
Precisely. So the x11 egl platform requirement seem artificial since
it has nothing to do with acceleration (making things run). To make it
even funnier - if one wants X-less setup, that won't be possible since
we explicitly require the X11 platform (and all its dependencies).

On the glx/dri/opengl side - I'm not claiming that the heuristics are
perfect, but if there's some issue (detection, dependencies and/or
other) in there we should fix it for everyone - just let me know
what's broken and I'll look into it. Please ?

>
>> Speaking of which - I cannot find any reports of people (mis)configuring
>> mesa, leading to lack of glamor/X11 acceleration.
>
> glamor failing to initialize in Xorg because Mesa was built without
> --with-egl-platforms=drm[,...] was a fairly common problem for radeonsi
> users until Marek made it basically impossible. Most of those reports
> might have been just on IRC though.
>
Ack. If anyone has a Xorg.0.log with a gbm-less libEGL handy that'll
be amazing. We could/should be able to make things clearer/easier to
track in such cases.

Thanks
Emil
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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix mismatch between TGSI BFI/BFE and GLSL

[Ilia Mirkin]

On Mon, Oct 24, 2016 at 11:12 AM, Nicolai Hähnle  wrote:
> On 24.10.2016 16:44, Ilia Mirkin wrote:
>> In any case, the GLSL way is backwards-compatible with the DX11 way.
>> It just specifies some unspecified situations.
>
> No, it isn't -- that's the whole problem :)
>
> Both GLSL and SM5 specify clearly what should happen for the offset=0,
> bits=32 case, but they disagree.

Oh. Interesting. Do we have tests for that? (Do they fail on nvc0?
Pretty sure they were passing last I checked...)

I find this very surprising BTW - please double-check.
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Re: [Mesa-dev] [PATCH] amd/addrlib: limit fastcall/regparm to i386

[Rob Herring]

On Sat, Oct 22, 2016 at 1:08 AM, Jason Ekstrand  wrote:
> On Fri, Oct 21, 2016 at 10:58 PM, Dave Airlie  wrote:
>>
>> On 22 Oct. 2016 15:51, "Jason Ekstrand"  wrote:
>> >
>> > Wait... Why are we building the AMD driver on ARM?  I know AMD has been
>> > talking about ARM-based servers, but are they actually strapping GPUs to
>> > them?
>>
>> PCIE on ARM somewhere.
>
> I suppose so.  I don't usually think of ARM devices as having PCIE, but I
> guess it's possible...  You learn something every day.

Pretty much all the server and networking chips have PCIe. Even the
mobile chips have PCIe now for WiFi.

I'm just build testing ATM, but I have heard that folks are plugging
in graphics cards on ARM dev boards.

Rob
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[Mesa-dev] [ANNOUNCE] mesa 13.0.0-rc2

[Emil Velikov]

The second release candidate for Mesa 13.0.0 is now available.


Dave Airlie (2):
  radv: use emit_icmp for samples_identical
  radv: allow cmask transitions without fast clear

Emil Velikov (3):
  automake: don't forget to pick wglext.h in the tarball
  anv: automake: cleanup the generated json file during make clean
  Update version to 13.0.0-rc2

Eric Engestrom (1):
  wsi/wayland: fix error path

Francisco Jerez (2):
  glapi: Move PrimitiveBoundingBox and BlendBarrier definitions
into ES3.2 category.
  Revert "Revert "mapi: export all GLES 3.2 functions in libGLESv2.so""

Ilia Mirkin (2):
  nv50,nvc0: avoid reading out of bounds when getting bogus so info
  nv50/ir: process texture offset sources as regular sources

Jason Ekstrand (1):
  anv: Suffix the intel_icd file with the host CPU

Jonathan Gray (1):
  mapi: automake: set VISIBILITY_CFLAGS for shared glapi

Nicolai Hähnle (5):
  st/glsl_to_tgsi: fix block copies of arrays of doubles
  st/glsl_to_tgsi: fix block copies of arrays of structs
  st/glsl_to_tgsi: sort input and output decls by TGSI index
  st/mesa: only set primitive_restart when the restart index is in range
  radeonsi: fix 64-bit loads from LDS

Samuel Pitoiset (1):
  nvc0: do not break 3D state by pushing MS coordinates on Fermi

Stencel, Joanna (1):
  egl/wayland: add missing destroy_window callback


git tag: mesa-13.0.0-rc2

ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.gz
MD5:  aa3f0652e0b1a7a8f07686cdea96d56e  mesa-13.0.0-rc2.tar.gz
SHA1: 9998f5f6639169a18da558295addb3229f04a9c3  mesa-13.0.0-rc2.tar.gz
SHA256: 82c96ef060d1dbbdb0ba52b25beaa0eabec85a5ddd9a8d49f6d9354b1faa78d7
mesa-13.0.0-rc2.tar.gz
PGP:  ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.gz.sig

ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.xz
MD5:  ac32eb49c8f5ba698013502a0aac79a5  mesa-13.0.0-rc2.tar.xz
SHA1: e569062ec42ecbe40aa6df0c85f04c27416a378e  mesa-13.0.0-rc2.tar.xz
SHA256: ef26031a79b915e1643b0ffe5354f8ae774cd445f12b342abac63438f9735a43
mesa-13.0.0-rc2.tar.xz
PGP:  ftp://ftp.freedesktop.org/pub/mesa/13.0.0/mesa-13.0.0-rc2.tar.xz.sig
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Re: [Mesa-dev] [PATCH] nv50/ir: display OP_BAR subops in debug mode

[Ilia Mirkin]

Reviewed-by: Ilia Mirkin 

On Mon, Oct 24, 2016 at 10:55 AM, Samuel Pitoiset
 wrote:
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> index 0c143e5..78c0757 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
> @@ -236,6 +236,11 @@ static const char *cctlOpStr[] =
> "", "", "", "", "", "iv", "ivall"
>  };
>
> +static const char *barOpStr[] =
> +{
> +   "sync", "arrive", "red and", "red or", "red popc"
> +};
> +
>  static const char *DataTypeStr[] =
>  {
> "-",
> @@ -611,6 +616,10 @@ void Instruction::print() const
>   if (subOp < ARRAY_SIZE(cctlOpStr))
>  PRINT("%s ", cctlOpStr[subOp]);
>   break;
> +  case OP_BAR:
> + if (subOp < ARRAY_SIZE(barOpStr))
> +PRINT("%s ", barOpStr[subOp]);
> + break;
>default:
>   if (subOp)
>  PRINT("(SUBOP:%u) ", subOp);
> --
> 2.10.1
>
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[Mesa-dev] [PATCH] nv50/ir: display OP_BAR subops in debug mode

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 0c143e5..78c0757 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -236,6 +236,11 @@ static const char *cctlOpStr[] =
"", "", "", "", "", "iv", "ivall"
 };
 
+static const char *barOpStr[] =
+{
+   "sync", "arrive", "red and", "red or", "red popc"
+};
+
 static const char *DataTypeStr[] =
 {
"-",
@@ -611,6 +616,10 @@ void Instruction::print() const
  if (subOp < ARRAY_SIZE(cctlOpStr))
 PRINT("%s ", cctlOpStr[subOp]);
  break;
+  case OP_BAR:
+ if (subOp < ARRAY_SIZE(barOpStr))
+PRINT("%s ", barOpStr[subOp]);
+ break;
   default:
  if (subOp)
 PRINT("(SUBOP:%u) ", subOp);
-- 
2.10.1

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Re: [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix mismatch between TGSI BFI/BFE and GLSL

[Ilia Mirkin]

On Mon, Oct 24, 2016 at 10:05 AM, Nicolai Hähnle  wrote:
> On 24.10.2016 15:49, Ilia Mirkin wrote:
>>
>> On Mon, Oct 24, 2016 at 9:43 AM, Nicolai Hähnle 
>> wrote:
>>>
>>> On 24.10.2016 15:38, Nicolai Hähnle wrote:


 On 24.10.2016 15:34, Ilia Mirkin wrote:
>
>
> These work properly on nvc0. I'd rather you work around it in your
> backend.



 That's not a good solution because of how the opcodes are defined. How
 about TGSI_OPCODE_{BFI,[UI]BFE}_GLSL and an associated pipe cap that
 gets enabled for nvc0?
>>>
>>>
>>>
>>> Or we can declare that the semantics of BFI/BFE should just be in line
>>> with
>>> what GLSL wants. I don't know if there are other state trackers that rely
>>> on
>>> it, it seems that you were actually the one who introduced the wording in
>>> tgsi.rst...
>>
>>
>> Yeah, as part of the ARB_gpu_shader5 bringup. At the time, I believe I
>> specified them as the DX11 thing since I assumed it was identical to
>> the GLSL. I've since learned that not to be the case.
>>
>> If you want to introduce new ops/caps to differentiate the GLSL way
>> and the DX11 way, that's fine by me. (And I'm not picky about which op
>> gets the original name...)
>
>
> Okay. The question is whether anybody actually needs the DX11 way. Since
> there's only a nine and not an eleven, I kind of suspect the answer is 'no',
> and then there's no need for a cap.

In any case, the GLSL way is backwards-compatible with the DX11 way.
It just specifies some unspecified situations.

I might also add that I added logic to the pack/unpack helpers to make
use of BFE/BFI in various cases. I'm pretty sure they don't need the
workaround logic either.
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Re: [Mesa-dev] [PATCH] nv50/ir: do not perform global membar for shared memory

[Samuel Pitoiset]

On 10/24/2016 04:35 PM, Ilia Mirkin wrote:

On Mon, Oct 24, 2016 at 10:29 AM, Samuel Pitoiset
 wrote:

Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index b47fc49..621a468 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3561,12 +3561,15 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
   break;
case TGSI_OPCODE_MEMBAR:
+   {
+  uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
   geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
   geni->fixed = 1;
-  if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
+  if ((level & TGSI_MEMBAR_THREAD_GROUP) || level == TGSI_MEMBAR_SHARED)


Probably just level & (A | B)


No, because TGSI_MEMBAR_SHARED is also defined for memoryBarrier() and 
we should perform a global synchronization for that one. We want to only 
do it for memoryBarrierShared().





  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
   else
  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
+   }
   break;
case TGSI_OPCODE_ATOMUADD:
case TGSI_OPCODE_ATOMXCHG:
--
2.10.1

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--
-Samuel
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Re: [Mesa-dev] [PATCH] nv50/ir: do not perform global membar for shared memory

[Ilia Mirkin]

On Mon, Oct 24, 2016 at 10:29 AM, Samuel Pitoiset
 wrote:
> Shared memory is local to CTA, thus we should only wait for
> prior memory writes which are visible to other threads in
> the same CTA, and not at global level. This should speedup
> compute shaders which use shared memory.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> index b47fc49..621a468 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -3561,12 +3561,15 @@ Converter::handleInstruction(const struct 
> tgsi_full_instruction *insn)
>geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
>break;
> case TGSI_OPCODE_MEMBAR:
> +   {
> +  uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
>geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
>geni->fixed = 1;
> -  if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
> +  if ((level & TGSI_MEMBAR_THREAD_GROUP) || level == TGSI_MEMBAR_SHARED)

Probably just level & (A | B)

>   geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
>else
>   geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
> +   }
>break;
> case TGSI_OPCODE_ATOMUADD:
> case TGSI_OPCODE_ATOMXCHG:
> --
> 2.10.1
>
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[Mesa-dev] [PATCH] nv50/ir: do not perform global membar for shared memory

[Samuel Pitoiset]

Shared memory is local to CTA, thus we should only wait for
prior memory writes which are visible to other threads in
the same CTA, and not at global level. This should speedup
compute shaders which use shared memory.

Signed-off-by: Samuel Pitoiset 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index b47fc49..621a468 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3561,12 +3561,15 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
   break;
case TGSI_OPCODE_MEMBAR:
+   {
+  uint32_t level = tgsi.getSrc(0).getValueU32(0, info);
   geni = mkOp(OP_MEMBAR, TYPE_NONE, NULL);
   geni->fixed = 1;
-  if (tgsi.getSrc(0).getValueU32(0, info) & TGSI_MEMBAR_THREAD_GROUP)
+  if ((level & TGSI_MEMBAR_THREAD_GROUP) || level == TGSI_MEMBAR_SHARED)
  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, CTA);
   else
  geni->subOp = NV50_IR_SUBOP_MEMBAR(M, GL);
+   }
   break;
case TGSI_OPCODE_ATOMUADD:
case TGSI_OPCODE_ATOMXCHG:
-- 
2.10.1

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[Mesa-dev] [PATCH 2/3] gallium/hud: close a previously opened handle

[Steven Toth]

We're missing the closedir() to the matching opendir().

Signed-off-by: Steven Toth 
---
 src/gallium/auxiliary/hud/hud_cpufreq.c  | 1 +
 src/gallium/auxiliary/hud/hud_diskstat.c | 5 -
 src/gallium/auxiliary/hud/hud_nic.c  | 1 +
 3 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/auxiliary/hud/hud_cpufreq.c 
b/src/gallium/auxiliary/hud/hud_cpufreq.c
index bfc748b..e66c3e4 100644
--- a/src/gallium/auxiliary/hud/hud_cpufreq.c
+++ b/src/gallium/auxiliary/hud/hud_cpufreq.c
@@ -225,6 +225,7 @@ hud_get_num_cpufreq(bool displayhelp)
   snprintf(fn, sizeof(fn), "%s/cpufreq/scaling_max_freq", basename);
   add_object(dp->d_name, fn, CPUFREQ_MAXIMUM, cpu_index);
}
+   closedir(dir);
 
if (displayhelp) {
   list_for_each_entry(struct cpufreq_info, cfi, _list, list) {
diff --git a/src/gallium/auxiliary/hud/hud_diskstat.c 
b/src/gallium/auxiliary/hud/hud_diskstat.c
index 7d4f500..d4306cd 100644
--- a/src/gallium/auxiliary/hud/hud_diskstat.c
+++ b/src/gallium/auxiliary/hud/hud_diskstat.c
@@ -277,8 +277,10 @@ hud_get_num_disks(bool displayhelp)
   /* Add any partitions */
   struct dirent *dpart;
   DIR *pdir = opendir(basename);
-  if (!pdir)
+  if (!pdir) {
+ closedir(dir);
  return 0;
+  }
 
   while ((dpart = readdir(pdir)) != NULL) {
  /* Avoid 'lo' and '..' and '.' */
@@ -298,6 +300,7 @@ hud_get_num_disks(bool displayhelp)
  add_object_part(basename, dpart->d_name, DISKSTAT_WR);
   }
}
+   closedir(dir);
 
if (displayhelp) {
   list_for_each_entry(struct diskstat_info, dsi, _list, list) {
diff --git a/src/gallium/auxiliary/hud/hud_nic.c 
b/src/gallium/auxiliary/hud/hud_nic.c
index 719dd04..2795c93 100644
--- a/src/gallium/auxiliary/hud/hud_nic.c
+++ b/src/gallium/auxiliary/hud/hud_nic.c
@@ -399,6 +399,7 @@ hud_get_num_nics(bool displayhelp)
   }
 
}
+   closedir(dir);
 
list_for_each_entry(struct nic_info, nic, _list, list) {
   char line[64];
-- 
2.7.4

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