[Mesa-dev] [Bug 111169] libmesa_util.a(u_queue.c.o): undefined reference to symbol 'pthread_setname_np@@GLIBC_2.12'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=69

Vinson Lee  changed:

   What|Removed |Added

 CC||e...@anholt.net
   Keywords||bisected

--- Comment #1 from Vinson Lee  ---
f8c27c277585141f2d2732732a8c64c7d40f0961 is the first bad commit
commit f8c27c277585141f2d2732732a8c64c7d40f0961
Author: Eric Anholt 
Date:   Mon Jul 1 13:06:09 2019 -0700

state_tracker: Move the format test out to be an actual unit test.

We want errors in the table to show up as unit test failures in MRs.
Also keeps unit test code out of the built drivers.

Reviewed-by: Thomas Helland 
Reviewed-by: Kristian H. Kristensen 

:04 04 97a04f178ee7547d3edd8bf12cfeb187b84f557b
a7de63dc1badfa11c5df3952e510ce0a8fe99421 M  src
bisect run success

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[Mesa-dev] [Bug 111169] libmesa_util.a(u_queue.c.o): undefined reference to symbol 'pthread_setname_np@@GLIBC_2.12'

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=69

Bug ID: 69
   Summary: libmesa_util.a(u_queue.c.o): undefined reference to
symbol 'pthread_setname_np@@GLIBC_2.12'
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Keywords: regression
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: v...@freedesktop.org
QA Contact: mesa-dev@lists.freedesktop.org

meson builddir -Ddri-drivers='' -Dbuild-tests=true -Dgallium-drivers=swrast
-Dplatforms=x11 -Dvulkan-drivers=''

FAILED: src/mesa/state_tracker/tests/st_format_test 
c++  -o src/mesa/state_tracker/tests/st_format_test
'src/mesa/state_tracker/tests/st_format_test@exe/st_format.c.o'
-Wl,--no-undefined -Wl,--as-needed -Wl,--start-group
src/mesa/state_tracker/tests/libmesa_st_test_common.a src/gtest/libgtest.a
src/mesa/libmesa_gallium.a src/compiler/glsl/libglsl.a
src/compiler/glsl/glcpp/libglcpp.a src/util/libmesa_util.a
src/compiler/nir/libnir.a src/compiler/libcompiler.a src/mesa/libmesa_sse41.a
src/mapi/shared-glapi/libglapi.so.0.0.0 src/gallium/auxiliary/libgallium.a -lz
-lm -Wl,--end-group -ldrm -L/usr/lib/llvm-6.0/lib -lLLVM-6.0 -ldl -lm -lz -lm
-lz -lm '-Wl,-rpath,$ORIGIN/../../../mapi/shared-glapi'
-Wl,-rpath-link,src/mapi/shared-glapi  
/usr/bin/ld: src/util/libmesa_util.a(u_queue.c.o): undefined reference to
symbol 'pthread_setname_np@@GLIBC_2.12'

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Re: [Mesa-dev] [AppVeyor] mesa master #11902 failed

[Rob Clark]

On Thu, Jul 18, 2019 at 4:34 PM Roland Scheidegger  wrote:
>
> Am 16.07.19 um 20:55 schrieb AppVeyor:
> >
> >   Build mesa 11902 failed
> > Commit 856e84083e by Rob Clark  on
> > 7/15/2019 4:05 PM:
> > mesa/st: add sampler uniforms\n\nAdd sampler uniforms for the UV
> > plane(s), so driver can count the\nuniforms and get the correct sampler
> > count.\n\nFixes lowered YUV on a6xx which actually wants to know # of
> > samplers.\n\nSigned-off-by: Rob Clark
> > \nReviewed-by: Kristian H. Kristensen
> > \nReviewed-by: Eric Anholt 
> >
>
> Apparently this commit broke windows builds...
>

Hmm, really no asprintf() on windows?

Is there some place we can add an asprintf() in mesa for windows builds?

BR,
-R
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Re: [Mesa-dev] [AppVeyor] mesa master #11902 failed

[Roland Scheidegger]

Am 16.07.19 um 20:55 schrieb AppVeyor:
> 
>   Build mesa 11902 failed
> Commit 856e84083e by Rob Clark  on
> 7/15/2019 4:05 PM:
> mesa/st: add sampler uniforms\n\nAdd sampler uniforms for the UV
> plane(s), so driver can count the\nuniforms and get the correct sampler
> count.\n\nFixes lowered YUV on a6xx which actually wants to know # of
> samplers.\n\nSigned-off-by: Rob Clark
> \nReviewed-by: Kristian H. Kristensen
> \nReviewed-by: Eric Anholt 
>

Apparently this commit broke windows builds...

Roland
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[Mesa-dev] [AppVeyor] mesa master #11947 failed

[AppVeyor]

Build mesa 11947 failed


Commit 0395b58c92 by Alyssa Rosenzweig on 7/18/2019 7:43 PM:

panfrost: Set rt_count\n\nThis doesn't quite work yet, but it illustrates how MRT is implemented\nin the MFBD: rt_count is set appropriately based on the number of render\ntargets, while additional render target descriptors are appended on with\nan index variable in them (not quite decoded since there's some aspects\nwe don't understand there, but conceptually this should be right).\n\nSigned-off-by: Alyssa Rosenzweig 


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[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=50

--- Comment #6 from Matías Zúñiga  ---
(In reply to Nanley Chery from comment #3)
> *** Bug 62 has been marked as a duplicate of this bug. ***

Sorry, i didn't find this bug before posting.

The merge request also fixes the problem for me

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Re: [Mesa-dev] [PATCH 2/2] meson: make "auto" only choose buildable drivers

[Dylan Baker]

Quoting Alyssa Ross (2019-07-18 10:29:45)
> > For virgl/svga: I'd be inclined not to build them automatically. They're not
> > useful outside of a VM, so most developers either will be exclusively 
> > building
> > one (not both) of those, or not be interested in them at all. And Distros 
> > don't
> > use auto options so we don't need to worry about them.
> 
> Interesting. I am in fact a developer for a distribution (NixOS) where a
> recent refactor of our package made it so we did use the auto options.
> Should we not, in your opinion?

It's up to you guys. Generally distro maintainers know exactly what they want
and want it. NixOS is a little different in that the Nix package manager runs on
basically every OS on the planet, so I guess you guys might be in a place to use
auto. My assumption for auto though was really end users who don't know what
they want or what the options even mean being able to run:

git clone ...
meson builddir
ninja -C builddir install

and get the driver they wanted.

Dylan


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Re: [Mesa-dev] [PATCH 2/2] meson: make "auto" only choose buildable drivers

[Alyssa Ross]

> For virgl/svga: I'd be inclined not to build them automatically. They're not
> useful outside of a VM, so most developers either will be exclusively building
> one (not both) of those, or not be interested in them at all. And Distros 
> don't
> use auto options so we don't need to worry about them.

Interesting. I am in fact a developer for a distribution (NixOS) where a
recent refactor of our package made it so we did use the auto options.
Should we not, in your opinion?


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[Mesa-dev] R: [PATCH 1/2] meson: require libdrm for gallium svga or virgl

[Francesco Ansanelli]

Dear Alyssa,

Sorry the bothering..

Your patch also added the check for freedreno, but it is not mentioned in
the commit message.
Is it actually what you wanted?

Cheers,
Francesco
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Re: [Mesa-dev] [PATCH v4] anv: fix alphaToCoverage when there is no color attachment

[Juan A. Suarez Romero]

On Mon, 2019-05-06 at 16:01 +0200, Iago Toral Quiroga wrote:
> From: Samuel Iglesias Gonsálvez 
> 
> There are tests in CTS for alpha to coverage without a color attachment
> that are failing. This happens because we remove the shader color
> outputs when we don't have a valid color attachment for them, but when
> alpha to coverage is enabled we still want to preserve the the output
> at location 0 since we need the alpha component. In that case we will
> also need to create a null render target for RT 0.
> 

I'm adding this commit to the 19.1 stable queue.


J.A.

> v2:
>   - We already create a null rt when we don't have any, so reuse that
> for this case (Jason)
>   - Simplify the code a bit (Iago)
> 
> v3:
>   - Take alpha to coverage from the key and don't tie this to depth-only
> rendering only, we want the same behavior if we have multiple render
> targets but the one at location 0 is not used. (Jason).
>   - Rewrite commit message (Iago)
> 
> v4:
>   - Make sure we take into account the array length of the shader outputs,
> which we were no handling correctly either and make sure we also
> create null render targets for any invalid array entries too. (Jason)
> 
> Fixes the following CTS tests:
> dEQP-VK.pipeline.multisample.alpha_to_coverage_no_color_attachment.*
> 
> Signed-off-by: Samuel Iglesias Gonsálvez 
> Signed-off-by: Iago Toral Quiroga 
> ---
>  src/intel/vulkan/anv_pipeline.c | 56 -
>  1 file changed, 42 insertions(+), 14 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
> index 20eab548fb2..f15f0896266 100644
> --- a/src/intel/vulkan/anv_pipeline.c
> +++ b/src/intel/vulkan/anv_pipeline.c
> @@ -823,14 +823,24 @@ anv_pipeline_link_fs(const struct brw_compiler 
> *compiler,
>   continue;
>  
>const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
> -  /* Unused or out-of-bounds */
> -  if (rt >= MAX_RTS || !(stage->key.wm.color_outputs_valid & (1 << rt)))
> +  /* Out-of-bounds */
> +  if (rt >= MAX_RTS)
>   continue;
>  
>const unsigned array_len =
>   glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
>assert(rt + array_len <= max_rt);
>  
> +  /* Unused */
> +  if (!(stage->key.wm.color_outputs_valid & BITFIELD_RANGE(rt, 
> array_len))) {
> + /* If this is the RT at location 0 and we have alpha to coverage
> +  * enabled we will have to create a null RT for it, so mark it as
> +  * used.
> +  */
> + if (rt > 0 || !stage->key.wm.alpha_to_coverage)
> +continue;
> +  }
> +
>for (unsigned i = 0; i < array_len; i++)
>   rt_used[rt + i] = true;
> }
> @@ -841,11 +851,22 @@ anv_pipeline_link_fs(const struct brw_compiler 
> *compiler,
>   continue;
>  
>rt_to_bindings[i] = num_rts;
> -  rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
> - .set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
> - .binding = 0,
> - .index = i,
> -  };
> +
> +  if (stage->key.wm.color_outputs_valid & (1 << i)) {
> + rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
> +.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
> +.binding = 0,
> +.index = i,
> + };
> +  } else {
> + /* Setup a null render target */
> + rt_bindings[rt_to_bindings[i]] = (struct anv_pipeline_binding) {
> +.set = ANV_DESCRIPTOR_SET_COLOR_ATTACHMENTS,
> +.binding = 0,
> +.index = UINT32_MAX,
> + };
> +  }
> +
>num_rts++;
> }
>  
> @@ -855,14 +876,21 @@ anv_pipeline_link_fs(const struct brw_compiler 
> *compiler,
>   continue;
>  
>const unsigned rt = var->data.location - FRAG_RESULT_DATA0;
> +  const unsigned array_len =
> + glsl_type_is_array(var->type) ? glsl_get_length(var->type) : 1;
> +
>if (rt >= MAX_RTS ||
> -  !(stage->key.wm.color_outputs_valid & (1 << rt))) {
> - /* Unused or out-of-bounds, throw it away */
> - deleted_output = true;
> - var->data.mode = nir_var_function_temp;
> - exec_node_remove(&var->node);
> - exec_list_push_tail(&impl->locals, &var->node);
> - continue;
> +  !(stage->key.wm.color_outputs_valid & BITFIELD_RANGE(rt, 
> array_len))) {
> + /* Unused or out-of-bounds, throw it away, unless it is the first
> +  * RT and we have alpha to coverage enabled.
> +  */
> + if (rt != 0 || !stage->key.wm.alpha_to_coverage) {
> +deleted_output = true;
> +var->data.mode = nir_var_function_temp;
> +exec_node_remove(&var->node);
> +exec_list_push_tail(&impl->locals, &var->node);
> +continue;
> + }
>}
>  
>/* Give it the new location */

__

Re: [Mesa-dev] [PATCH 1/2] meson: require libdrm for gallium svga or virgl

[Dylan Baker]

Quoting Alyssa Ross (2019-07-18 07:15:13)
> A build with svga or virgl, but without DRI or Vulkan, still requires
> libdrm, but this wasn't caught by meson.
> ---
>  meson.build | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/meson.build b/meson.build
> index 13b561f99de..52dd5be25e7 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -1185,7 +1185,7 @@ endforeach
>  with_gallium_drisw_kms = false
>  dep_libdrm = dependency(
>'libdrm', version : '>=' + _drm_ver,
> -  required : with_dri2 or with_dri3
> +  required : with_dri2 or with_dri3 or with_gallium_freedreno or 
> with_gallium_svga or with_gallium_virgl
>  )
>  if dep_libdrm.found()
>pre_args += '-DHAVE_LIBDRM'
> -- 
> 2.22.0
> 

for this patch:
Reviewed-by: Dylan Baker 


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Re: [Mesa-dev] [PATCH 2/2] meson: make "auto" only choose buildable drivers

[Dylan Baker]

Quoting Alyssa Ross (2019-07-18 07:15:14)
> "auto" pays attention to the OS and architecture of the target system,
> but not the available libraries. If, say, libdrm isn't available, "auto"
> won't work, and a manual list of drivers will be required anyway. It
> would also try building the virgl and svga gallium drivers, even when
> unsupported due to building with EGL and no compatible platform.
> 
> This wasn't a lot of code to implement, but it required moving around
> various parts of meson.build so that the necessary information was
> available in the right place.
> ---
>  meson.build | 183 
>  1 file changed, 113 insertions(+), 70 deletions(-)
> 
> diff --git a/meson.build b/meson.build
> index 52dd5be25e7..f25bbc92bfa 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -108,12 +108,30 @@ with_shared_glapi = get_option('shared-glapi') and 
> with_any_opengl
>  
>  system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'gnu/kfreebsd', 
> 'dragonfly', 'linux'].contains(host_machine.system())
>  
> +_drm_amdgpu_ver = '2.4.97'
> +_drm_radeon_ver = '2.4.71'
> +_drm_nouveau_ver = '2.4.66'
> +_drm_intel_ver = '2.4.75'
> +_drm_ver = '2.4.75'
> +
>  dri_drivers = get_option('dri-drivers')
>  if dri_drivers.contains('auto')
>if system_has_kms_drm
>  # TODO: PPC, Sparc
>  if ['x86', 'x86_64'].contains(host_machine.cpu_family())
> -  dri_drivers = ['i915', 'i965', 'r100', 'r200', 'nouveau']
> +  dri_drivers = []
> +  if dependency('libdrm_intel', version : '>=' + _drm_intel_ver, 
> required : false).found()
> +dri_drivers += 'i915'
> +  endif
> +  if dependency('libdrm', version : '>=' + _drm_ver, required : 
> false).found()
> +dri_drivers += 'i965'
> +  endif
> +  if dependency('libdrm_radeon', version : '>=' + _drm_radeon_ver, 
> required : false).found()
> +dri_drivers += ['r100', 'r200']
> +  endif
> +  if dependency('libdrm_nouveau', version : '>=' + _drm_nouveau_ver, 
> required : false).found()
> +dri_drivers += 'nouveau'
> +  endif
>  elif ['arm', 'aarch64'].contains(host_machine.cpu_family())

Newer versions of meson cache calls to dependency(), but older ones (which we
still support) don't, and I'm afraid that calling dependency() several times for
each libdrm library is going to stink for performance.

Would it work to just move the libdrm check before the drivers check, and
instead of erroring if libdrm_foo isn't found do that in the acutal drivers
checks, something like (pusdocode):

foreach d : ['intel', 'amdgpu', ...]
  dep_libdrm_$d = dependency(..., required : false)
endforeach

if dri_drivers.contains('auto')
  if system_has_kms_drm
dri_drivers = []
if ['x86', 'x86_64'].contains(host_machine.cpu_family())
  if dep_libdrm_intel.found()
dri_drivers += 'i915'
  endif
  ...
endif
  ...
  endif
else
  _checks = [['i915', dep_libdrm_intel], ...]
  foreach c : _checks
if dri_drivers.contains(c[0]) and not c[1].found()
  error(...)
endif
  endforeach
endif

if gallim_drivers.contains('auto')
  ...
else
  ...
endif

For virgl/svga: I'd be inclined not to build them automatically. They're not
useful outside of a VM, so most developers either will be exclusively building
one (not both) of those, or not be interested in them at all. And Distros don't
use auto options so we don't need to worry about them.

Dylan

>dri_drivers = []
>  else
> @@ -139,55 +157,6 @@ with_dri_swrast = dri_drivers.contains('swrast')
>  with_dri = dri_drivers.length() != 0 and dri_drivers != ['']
>  
>  gallium_drivers = get_option('gallium-drivers')
> -if gallium_drivers.contains('auto')
> -  if system_has_kms_drm
> -# TODO: PPC, Sparc
> -if ['x86', 'x86_64'].contains(host_machine.cpu_family())
> -  gallium_drivers = [
> -'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'swrast'
> -  ]
> -elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
> -  gallium_drivers = [
> -'kmsro', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau',
> -'tegra', 'virgl', 'lima', 'swrast'
> -  ]
> -else
> -  error('Unknown architecture @0@. Please pass -Dgallium-drivers to set 
> driver options. Patches gladly accepted to fix this.'.format(
> -host_machine.cpu_family()))
> -endif
> -  elif ['darwin', 'windows', 'cygwin', 
> 'haiku'].contains(host_machine.system())
> -gallium_drivers = ['swrast']
> -  else
> -error('Unknown OS @0@. Please pass -Dgallium-drivers to set driver 
> options. Patches gladly accepted to fix this.'.format(
> -  host_machine.system()))
> -  endif
> -endif
> -with_gallium_kmsro = gallium_drivers.contains('kmsro')
> -with_gallium_radeonsi = gallium_drivers.contains('radeonsi')
> -with_gallium_r300 = gallium_drivers.contains('r300')
> -with_gallium_r600 = gallium_drivers.contains('r600')
> -with_gallium_nouveau = gallium_drivers.con

[Mesa-dev] [PATCH 2/2] meson: make "auto" only choose buildable drivers

[Alyssa Ross]

"auto" pays attention to the OS and architecture of the target system,
but not the available libraries. If, say, libdrm isn't available, "auto"
won't work, and a manual list of drivers will be required anyway. It
would also try building the virgl and svga gallium drivers, even when
unsupported due to building with EGL and no compatible platform.

This wasn't a lot of code to implement, but it required moving around
various parts of meson.build so that the necessary information was
available in the right place.
---
 meson.build | 183 
 1 file changed, 113 insertions(+), 70 deletions(-)

diff --git a/meson.build b/meson.build
index 52dd5be25e7..f25bbc92bfa 100644
--- a/meson.build
+++ b/meson.build
@@ -108,12 +108,30 @@ with_shared_glapi = get_option('shared-glapi') and 
with_any_opengl
 
 system_has_kms_drm = ['openbsd', 'netbsd', 'freebsd', 'gnu/kfreebsd', 
'dragonfly', 'linux'].contains(host_machine.system())
 
+_drm_amdgpu_ver = '2.4.97'
+_drm_radeon_ver = '2.4.71'
+_drm_nouveau_ver = '2.4.66'
+_drm_intel_ver = '2.4.75'
+_drm_ver = '2.4.75'
+
 dri_drivers = get_option('dri-drivers')
 if dri_drivers.contains('auto')
   if system_has_kms_drm
 # TODO: PPC, Sparc
 if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  dri_drivers = ['i915', 'i965', 'r100', 'r200', 'nouveau']
+  dri_drivers = []
+  if dependency('libdrm_intel', version : '>=' + _drm_intel_ver, required 
: false).found()
+dri_drivers += 'i915'
+  endif
+  if dependency('libdrm', version : '>=' + _drm_ver, required : 
false).found()
+dri_drivers += 'i965'
+  endif
+  if dependency('libdrm_radeon', version : '>=' + _drm_radeon_ver, 
required : false).found()
+dri_drivers += ['r100', 'r200']
+  endif
+  if dependency('libdrm_nouveau', version : '>=' + _drm_nouveau_ver, 
required : false).found()
+dri_drivers += 'nouveau'
+  endif
 elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
   dri_drivers = []
 else
@@ -139,55 +157,6 @@ with_dri_swrast = dri_drivers.contains('swrast')
 with_dri = dri_drivers.length() != 0 and dri_drivers != ['']
 
 gallium_drivers = get_option('gallium-drivers')
-if gallium_drivers.contains('auto')
-  if system_has_kms_drm
-# TODO: PPC, Sparc
-if ['x86', 'x86_64'].contains(host_machine.cpu_family())
-  gallium_drivers = [
-'r300', 'r600', 'radeonsi', 'nouveau', 'virgl', 'svga', 'swrast'
-  ]
-elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
-  gallium_drivers = [
-'kmsro', 'v3d', 'vc4', 'freedreno', 'etnaviv', 'nouveau',
-'tegra', 'virgl', 'lima', 'swrast'
-  ]
-else
-  error('Unknown architecture @0@. Please pass -Dgallium-drivers to set 
driver options. Patches gladly accepted to fix this.'.format(
-host_machine.cpu_family()))
-endif
-  elif ['darwin', 'windows', 'cygwin', 'haiku'].contains(host_machine.system())
-gallium_drivers = ['swrast']
-  else
-error('Unknown OS @0@. Please pass -Dgallium-drivers to set driver 
options. Patches gladly accepted to fix this.'.format(
-  host_machine.system()))
-  endif
-endif
-with_gallium_kmsro = gallium_drivers.contains('kmsro')
-with_gallium_radeonsi = gallium_drivers.contains('radeonsi')
-with_gallium_r300 = gallium_drivers.contains('r300')
-with_gallium_r600 = gallium_drivers.contains('r600')
-with_gallium_nouveau = gallium_drivers.contains('nouveau')
-with_gallium_freedreno = gallium_drivers.contains('freedreno')
-with_gallium_softpipe = gallium_drivers.contains('swrast')
-with_gallium_vc4 = gallium_drivers.contains('vc4')
-with_gallium_v3d = gallium_drivers.contains('v3d')
-with_gallium_panfrost = gallium_drivers.contains('panfrost')
-with_gallium_etnaviv = gallium_drivers.contains('etnaviv')
-with_gallium_tegra = gallium_drivers.contains('tegra')
-with_gallium_iris = gallium_drivers.contains('iris')
-with_gallium_i915 = gallium_drivers.contains('i915')
-with_gallium_svga = gallium_drivers.contains('svga')
-with_gallium_virgl = gallium_drivers.contains('virgl')
-with_gallium_swr = gallium_drivers.contains('swr')
-with_gallium_lima = gallium_drivers.contains('lima')
-
-if cc.get_id() == 'intel'
-  if meson.version().version_compare('< 0.49.0')
-error('Meson does not have sufficient support of ICC before 0.49.0 to 
compile mesa')
-  elif with_gallium_swr and meson.version().version_compare('== 0.49.0')
-warning('Meson as of 0.49.0 is sufficient for compiling mesa with ICC, but 
there are some caveats with SWR. 0.49.1 should resolve all of these')
-  endif
-endif
 
 with_gallium = gallium_drivers.length() != 0 and gallium_drivers != ['']
 
@@ -203,7 +172,13 @@ _vulkan_drivers = get_option('vulkan-drivers')
 if _vulkan_drivers.contains('auto')
   if system_has_kms_drm
 if host_machine.cpu_family().startswith('x86')
-  _vulkan_drivers = ['amd', 'intel']
+  _vulkan_drivers = []
+  if dependency('libdrm

[Mesa-dev] [PATCH 1/2] meson: require libdrm for gallium svga or virgl

[Alyssa Ross]

A build with svga or virgl, but without DRI or Vulkan, still requires
libdrm, but this wasn't caught by meson.
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index 13b561f99de..52dd5be25e7 100644
--- a/meson.build
+++ b/meson.build
@@ -1185,7 +1185,7 @@ endforeach
 with_gallium_drisw_kms = false
 dep_libdrm = dependency(
   'libdrm', version : '>=' + _drm_ver,
-  required : with_dri2 or with_dri3
+  required : with_dri2 or with_dri3 or with_gallium_freedreno or 
with_gallium_svga or with_gallium_virgl
 )
 if dep_libdrm.found()
   pre_args += '-DHAVE_LIBDRM'
-- 
2.22.0

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[Mesa-dev] [PATCH 0/2] meson: improve configuration experience

[Alyssa Ross]

Two patches here to make configuring mesa with meson a bit nicer.

The first addresses some missing dependencies that weren't caught by
meson, and so would result in a compiler error due to missing headers.
The second makes the "auto" value for drivers quite a bit smarter in an
attempt to avoid ever choosing drivers that can't actually be built.

Alyssa Ross (2):
  meson: require libdrm for gallium svga or virgl
  meson: make "auto" only choose buildable drivers

 meson.build | 185 
 1 file changed, 114 insertions(+), 71 deletions(-)

--
2.22.0

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[Mesa-dev] [PATCH 4/7] radv/gfx10: do not set ELEMENT_SIZE for buffer descriptors

[Samuel Pitoiset]

This field doesn't exist.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 6e313aa9aa1..3c553cb93e7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2164,7 +2164,6 @@ fill_geom_tess_rings(struct radv_queue *queue,
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_ELEMENT_SIZE(1) |
  S_008F0C_INDEX_STRIDE(3) |
  S_008F0C_ADD_TID_ENABLE(1);
 
@@ -2174,7 +2173,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
   S_008F0C_RESOURCE_LEVEL(1);
} else {
desc[3] |= 
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-  
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+  
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
+  S_008F0C_ELEMENT_SIZE(1);
}
 
/* GS entry for ES->GS ring */
@@ -2234,7 +2234,6 @@ fill_geom_tess_rings(struct radv_queue *queue,
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_ELEMENT_SIZE(1) |
  S_008F0C_INDEX_STRIDE(1) |
  S_008F0C_ADD_TID_ENABLE(true);
 
@@ -2244,7 +2243,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
   S_008F0C_RESOURCE_LEVEL(1);
} else {
desc[7] |= 
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-  
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+  
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
+  S_008F0C_ELEMENT_SIZE(1);
}
 
}
-- 
2.22.0

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[Mesa-dev] [PATCH 6/7] radv/gfx10: emit the GS NGG prologue before the nested barrier

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 7e623414adc..6feb55e3916 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4453,6 +4453,7 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct 
ac_llvm_compiler *ac_llvm,
if (i) {
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
ctx.options->key.vs_common_out.as_ngg) {
+   gfx10_ngg_gs_emit_prologue(&ctx);
nested_barrier = false;
} else {
nested_barrier = true;
@@ -4495,12 +4496,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct 
ac_llvm_compiler *ac_llvm,
 
LLVMBasicBlockRef merge_block;
if (shader_count >= 2 || is_ngg) {
-
-   if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
-   ctx.options->key.vs_common_out.as_ngg) {
-   gfx10_ngg_gs_emit_prologue(&ctx);
-   }
-
LLVMValueRef fn = 
LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
LLVMBasicBlockRef then_block = 
LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
merge_block = 
LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
-- 
2.22.0

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[Mesa-dev] [PATCH 5/7] radv/gfx10: do not allocate space for the ZPASS_DONE bug

[Samuel Pitoiset]

GFX10 isn't affected.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b6ac14f63a9..84d627340e9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -364,12 +364,14 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
radv_buffer_get_va(cmd_buffer->upload.upload_bo);
cmd_buffer->gfx9_fence_va += fence_offset;
 
-   /* Allocate a buffer for the EOP bug on GFX9. */
-   radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
-&eop_bug_offset, &fence_ptr);
-   cmd_buffer->gfx9_eop_bug_va =
-   radv_buffer_get_va(cmd_buffer->upload.upload_bo);
-   cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
+   if (cmd_buffer->device->physical_device->rad_info.chip_class == 
GFX9) {
+   /* Allocate a buffer for the EOP bug on GFX9. */
+   radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, 8,
+&eop_bug_offset, 
&fence_ptr);
+   cmd_buffer->gfx9_eop_bug_va =
+   
radv_buffer_get_va(cmd_buffer->upload.upload_bo);
+   cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;
+   }
}
 
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;
-- 
2.22.0

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[Mesa-dev] [PATCH 2/7] radv: change a bunch of >= GFX9 to == GFX9

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_cmd_buffer.c |  6 +++---
 src/amd/vulkan/radv_device.c |  2 +-
 src/amd/vulkan/radv_image.c  | 10 +-
 src/amd/vulkan/si_cmd_buffer.c   | 12 ++--
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b4301c0da15..b6ac14f63a9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1294,7 +1294,7 @@ radv_emit_fb_color_state(struct radv_cmd_buffer 
*cmd_buffer,
   cb->cb_color_attrib2);
radeon_set_context_reg(cmd_buffer->cs, 
R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,
   cb->cb_color_attrib3);
-   } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
GFX9) {
+   } else if (cmd_buffer->device->physical_device->rad_info.chip_class == 
GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
radeon_emit(cmd_buffer->cs, 
S_028C64_BASE_256B(cb->cb_color_base >> 32));
@@ -1432,7 +1432,7 @@ radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);
radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);
-   } else if (cmd_buffer->device->physical_device->rad_info.chip_class >= 
GFX9) {
+   } else if (cmd_buffer->device->physical_device->rad_info.chip_class == 
GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, 
R_028014_DB_HTILE_DATA_BASE, 3);
radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);
radeon_emit(cmd_buffer->cs, 
S_028018_BASE_HI(ds->db_htile_data_base >> 32));
@@ -2508,7 +2508,7 @@ si_emit_ia_multi_vgt_param(struct radv_cmd_buffer 
*cmd_buffer,
  draw_vertex_count);
 
if (state->last_ia_multi_vgt_param != ia_multi_vgt_param) {
-   if (info->chip_class >= GFX9) {
+   if (info->chip_class == GFX9) {

radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device,
   cs,
   R_030960_IA_MULTI_VGT_PARAM,
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 8dd24cb8192..15bda6822e8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2502,7 +2502,7 @@ radv_emit_global_shader_pointers(struct radv_queue *queue,
radv_emit_shader_pointer(queue->device, cs, regs[i],
 va, true);
}
-   } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) 
{
+   } else if (queue->device->physical_device->rad_info.chip_class == GFX9) 
{
uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
   R_00B130_SPI_SHADER_USER_DATA_VS_0,
   R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 4d3ed71c23c..0941cbb 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -522,7 +522,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
}
 
state[7] = meta_va >> 16;
-   } else if (chip_class >= GFX9) {
+   } else if (chip_class == GFX9) {
state[3] &= C_008F1C_SW_MODE;
state[4] &= C_008F20_PITCH;
 
@@ -787,7 +787,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
 
/* S8 with either Z16 or Z32 HTILE need a special format. */
-   if (device->physical_device->rad_info.chip_class >= GFX9 &&
+   if (device->physical_device->rad_info.chip_class == GFX9 &&
vk_format == VK_FORMAT_S8_UINT &&
radv_image_is_tc_compat_htile(image)) {
if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
@@ -828,7 +828,7 @@ si_make_texture_descriptor(struct radv_device *device,
state[6] = 0;
state[7] = 0;
 
-   if (device->physical_device->rad_info.chip_class >= GFX9) {
+   if (device->physical_device->rad_info.chip_class == GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
 
/* Depth is the last accessible layer on Gfx9.
@@ -874,7 +874,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
va = gpu_address + image->offset + image->fmask.offset;
 
-   if (device->physical_device->rad_info.chip_class >= GFX9) {
+   if (device->physical_device->rad_info.chip_class == GFX9) {
fmask_for

[Mesa-dev] [PATCH 3/7] radv: clean up fill_geom_tess_rings()

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 34 +-
 1 file changed, 9 insertions(+), 25 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 15bda6822e8..6e313aa9aa1 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2158,7 +2158,6 @@ fill_geom_tess_rings(struct radv_queue *queue,
   index stride 64 */
desc[0] = esgs_va;
desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
- S_008F04_STRIDE(0) |
  S_008F04_SWIZZLE_ENABLE(true);
desc[2] = esgs_ring_size;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
@@ -2167,7 +2166,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
  S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
  S_008F0C_ELEMENT_SIZE(1) |
  S_008F0C_INDEX_STRIDE(3) |
- S_008F0C_ADD_TID_ENABLE(true);
+ S_008F0C_ADD_TID_ENABLE(1);
 
if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
desc[3] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2182,17 +2181,12 @@ fill_geom_tess_rings(struct radv_queue *queue,
/* stride 0, num records - size, elsize0,
   index stride 0 */
desc[4] = esgs_va;
-   desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
- S_008F04_STRIDE(0) |
- S_008F04_SWIZZLE_ENABLE(false);
+   desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
desc[6] = esgs_ring_size;
desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_ELEMENT_SIZE(0) |
- S_008F0C_INDEX_STRIDE(0) |
- S_008F0C_ADD_TID_ENABLE(false);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
 
if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
desc[7] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2213,17 +2207,12 @@ fill_geom_tess_rings(struct radv_queue *queue,
/* stride 0, num records - size, elsize0,
   index stride 0 */
desc[0] = gsvs_va;
-   desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
- S_008F04_STRIDE(0) |
- S_008F04_SWIZZLE_ENABLE(false);
+   desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
desc[2] = gsvs_ring_size;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
  S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
- S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
- S_008F0C_ELEMENT_SIZE(0) |
- S_008F0C_INDEX_STRIDE(0) |
- S_008F0C_ADD_TID_ENABLE(false);
+ S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
 
if (queue->device->physical_device->rad_info.chip_class >= 
GFX10) {
desc[3] |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
@@ -2238,9 +2227,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
   elsize 4, index stride 16 */
/* shader will patch stride and desc[2] */
desc[4] = gsvs_va;
-   desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
- S_008F04_STRIDE(0) |
- S_008F04_SWIZZLE_ENABLE(true);
+   desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
+ S_008F04_SWIZZLE_ENABLE(1);
desc[6] = 0;
desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
@@ -2268,9 +2256,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
 
desc[0] = tess_va;
-   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
- S_008F04_STRIDE(0) |
- S_008F04_SWIZZLE_ENABLE(false);
+   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
desc[2] = tess_factor_ring_size;
desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
  S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
@@ -2287,9 +2273,7 @@ fill_geom_tess_rings(struct radv_queue *queue,
}
 
desc[4] = tess_offchip_va;
-   desc[

[Mesa-dev] [PATCH 7/7] radv/gfx10: update descriptors for inline uniform blocks

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_nir_to_llvm.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 6feb55e3916..19dcae3a476 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1373,9 +1373,16 @@ radv_load_resource(struct ac_shader_abi *abi, 
LLVMValueRef index,
uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
-   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
-   S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
-   S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+   S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
+
+   if (ctx->ac.chip_class >= GFX10) {
+   desc_type |= 
S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
+S_008F0C_OOB_SELECT(3) |
+S_008F0C_RESOURCE_LEVEL(1);
+   } else {
+   desc_type |= 
S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
+
S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
+   }
 
LLVMValueRef desc_components[4] = {
LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, 
ctx->ac.intptr, ""),
-- 
2.22.0

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[Mesa-dev] [PATCH 1/7] ac/nir: do not clamp shadow reference on GFX10

[Samuel Pitoiset]

RadeonSI only uses Z32_FLOAT_CLAMP for upgraded depth textures
on GFX10 and RADV doesn't promotes Z16 or Z24.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_nir_to_llvm.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 96bf89a8bf9..75ee534eb3e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3805,12 +3805,16 @@ static void visit_tex(struct ac_nir_context *ctx, 
nir_tex_instr *instr)
 
/* TC-compatible HTILE on radeonsi promotes Z16 and Z24 to Z32_FLOAT,
 * so the depth comparison value isn't clamped for Z16 and
-* Z24 anymore. Do it manually here.
+* Z24 anymore. Do it manually here for GFX8-9; GFX10 has an explicitly
+* clamped 32-bit float format.
 *
 * It's unnecessary if the original texture format was
 * Z32_FLOAT, but we don't know that here.
 */
-   if (args.compare && ctx->ac.chip_class >= GFX8 && 
ctx->abi->clamp_shadow_reference)
+   if (args.compare &&
+   ctx->ac.chip_class >= GFX8 &&
+   ctx->ac.chip_class <= GFX9 &&
+   ctx->abi->clamp_shadow_reference)
args.compare = ac_build_clamp(&ctx->ac, ac_to_float(&ctx->ac, 
args.compare));
 
/* pack derivatives */
-- 
2.22.0

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[Mesa-dev] [AppVeyor] mesa master #11940 failed

[AppVeyor]

Build mesa 11940 failed


Commit b178fdf486 by Connor Abbott on 5/11/2019 4:43 PM:

lima/gp: Fix problem with complex moves\n\nWhen writing the scheduler, we forgot that you can't read the complex\nunit in certain sources because it gets overwritten to 0 or 1. Fixing\nthis turned out to be possible without giving up and reducing\nGPIR_VALUE_REG_NUM to 10, although it was difficult in a way I didn't\nexpect. There can be at most 4 next-max nodes that can't have moves\nscheduled in the complex slot, so it actually isn't a problem for\ngetting the number of next-max nodes at 5 or lower. However, it is a\nproblem for stores. If a given node is a next-max node whose move cannot\ngo in the complex slot *and* is used by a store that we decide to\nschedule, we have to reserve one of the non-complex slots for a move\ninstead of all the slots, or we can wind up in a situation where only\nthe complex slot is free and we fail the move. This means that we have\nto add another term to the reservation logic, for stores whose children\ncannot be in the complex slot.\n\nAcked-by: Qiang Yu 


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Re: [Mesa-dev] [PATCH] panfrost: Take into account a index_bias for glDrawElementsBaseVertex calls

[Alyssa Rosenzweig]

Thank you for the patch!

Could you add a comment to include/panfrost_job.h explaining why this
works?

Thanks,

Alyssa

On Thu, Jul 18, 2019 at 01:11:21PM +0200, Rohan Garg wrote:
> Make sure we adjust draw_start and vertex_count in order to
> take into account a index_bias as required by a glDrawElementsBaseVertex
> call
> 
> Signed-off-by: Rohan Garg 
> ---
>  src/gallium/drivers/panfrost/pan_context.c | 7 +++
>  1 file changed, 3 insertions(+), 4 deletions(-)
> 
> diff --git a/src/gallium/drivers/panfrost/pan_context.c 
> b/src/gallium/drivers/panfrost/pan_context.c
> index 4bbf5230c6c..6484401e472 100644
> --- a/src/gallium/drivers/panfrost/pan_context.c
> +++ b/src/gallium/drivers/panfrost/pan_context.c
> @@ -1637,7 +1637,7 @@ panfrost_draw_vbo(
>  
>  ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
>  
> -ctx->vertex_count = info->count;
> +ctx->vertex_count = info->count + info->index_bias;
>  ctx->instance_count = info->instance_count;
>  
>  /* For non-indexed draws, they're the same */
> @@ -1686,14 +1686,13 @@ panfrost_draw_vbo(
>  
>  /* Use the corresponding values */
>  vertex_count = max_index - min_index + 1;
> -ctx->payload_vertex.draw_start = min_index;
> -ctx->payload_tiler.draw_start = min_index;
> +ctx->payload_vertex.draw_start = min_index + 
> info->index_bias;
> +ctx->payload_tiler.draw_start = min_index + info->index_bias;
>  
>  ctx->payload_tiler.prefix.negative_start = -min_index;
>  ctx->payload_tiler.prefix.index_count = 
> MALI_POSITIVE(info->count);
>  
>  //assert(!info->restart_index); /* TODO: Research */
> -assert(!info->index_bias);
>  
>  draw_flags |= 
> panfrost_translate_index_size(info->index_size);
>  ctx->payload_tiler.prefix.indices = 
> panfrost_get_index_buffer_mapped(ctx, info);
> -- 
> 2.17.1
> 


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[Mesa-dev] [PATCH] panfrost: Take into account a index_bias for glDrawElementsBaseVertex calls

[Rohan Garg]

Make sure we adjust draw_start and vertex_count in order to
take into account a index_bias as required by a glDrawElementsBaseVertex
call

Signed-off-by: Rohan Garg 
---
 src/gallium/drivers/panfrost/pan_context.c | 7 +++
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_context.c 
b/src/gallium/drivers/panfrost/pan_context.c
index 4bbf5230c6c..6484401e472 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -1637,7 +1637,7 @@ panfrost_draw_vbo(
 
 ctx->payload_tiler.prefix.draw_mode = g2m_draw_mode(mode);
 
-ctx->vertex_count = info->count;
+ctx->vertex_count = info->count + info->index_bias;
 ctx->instance_count = info->instance_count;
 
 /* For non-indexed draws, they're the same */
@@ -1686,14 +1686,13 @@ panfrost_draw_vbo(
 
 /* Use the corresponding values */
 vertex_count = max_index - min_index + 1;
-ctx->payload_vertex.draw_start = min_index;
-ctx->payload_tiler.draw_start = min_index;
+ctx->payload_vertex.draw_start = min_index + info->index_bias;
+ctx->payload_tiler.draw_start = min_index + info->index_bias;
 
 ctx->payload_tiler.prefix.negative_start = -min_index;
 ctx->payload_tiler.prefix.index_count = 
MALI_POSITIVE(info->count);
 
 //assert(!info->restart_index); /* TODO: Research */
-assert(!info->index_bias);
 
 draw_flags |= panfrost_translate_index_size(info->index_size);
 ctx->payload_tiler.prefix.indices = 
panfrost_get_index_buffer_mapped(ctx, info);
-- 
2.17.1

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Re: [Mesa-dev] [PATCH] android: mesa: revert "Enable asm unconditionally"

[Chih-Wei Huang]

Mauro Rossi  於 2019年7月14日 週日 下午5:17寫道：
>
> This patch partially reverts 20294dc ("mesa: Enable asm unconditionally, ...")
>
> Android makefile build logic needs to disable assembler optimization
> in 32bit builds to avoid text relocations for libglapi.so shared
>
> Fixes the following build error with Android x86 32bit target:
>
> [  0% 4/477] target SharedLib: libglapi 
> (out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so)
> FAILED: 
> out/target/product/x86/obj/SHARED_LIBRARIES/libglapi_intermediates/LINKED/libglapi.so
> ...
> prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld:
>  warning: shared library text segment is not shareable
> prebuilts/gcc/linux-x86/x86/x86_64-linux-android-4.9/x86_64-linux-android/bin/ld:
>  error: treating warnings as errors
> clang-6.0: error: linker command failed with exit code 1 (use -v to see 
> invocation)
>
> Fixes: 20294dc ("mesa: Enable asm unconditionally, now that gen_matypes is 
> gone.")
> Signed-off-by: Mauro Rossi 
> ---
>  Android.common.mk   | 3 +++
>  Android.mk  | 7 +++
>  src/mesa/Android.libmesa_dricore.mk | 2 ++
>  src/mesa/Android.libmesa_st_mesa.mk | 2 ++
>  4 files changed, 14 insertions(+)
>
> diff --git a/Android.common.mk b/Android.common.mk
> index 8a1c734353..209654bb75 100644
> --- a/Android.common.mk
> +++ b/Android.common.mk
> @@ -106,9 +106,12 @@ ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 26 && 
> echo true),true)
>  LOCAL_CFLAGS += -DHAVE_SYS_SHM_H
>  endif
>
> +ifeq ($(strip $(MESA_ENABLE_ASM)),true)
>  ifeq ($(TARGET_ARCH),x86)
>  LOCAL_CFLAGS += \
> -DUSE_X86_ASM
> +
> +endif
>  endif
>  ifeq ($(ARCH_ARM_HAVE_NEON),true)
>  LOCAL_CFLAGS_arm += -DUSE_ARM_ASM
> diff --git a/Android.mk b/Android.mk
> index 57613eccfc..4a2a003ea3 100644
> --- a/Android.mk
> +++ b/Android.mk
> @@ -83,6 +83,13 @@ endif
>
>  $(foreach d, $(MESA_BUILD_CLASSIC) $(MESA_BUILD_GALLIUM), $(eval $(d) := 
> true))
>
> +# host and target must be the same arch to generate matypes.h
> +ifeq ($(TARGET_ARCH),$(HOST_ARCH))
> +MESA_ENABLE_ASM := true
> +else
> +MESA_ENABLE_ASM := false
> +endif
> +
>  ifneq ($(filter true, $(HAVE_GALLIUM_RADEONSI)),)
>  MESA_ENABLE_LLVM := true
>  endif
> diff --git a/src/mesa/Android.libmesa_dricore.mk 
> b/src/mesa/Android.libmesa_dricore.mk
> index 8eb6aabe83..792117767b 100644
> --- a/src/mesa/Android.libmesa_dricore.mk
> +++ b/src/mesa/Android.libmesa_dricore.mk
> @@ -39,9 +39,11 @@ LOCAL_MODULE_CLASS := STATIC_LIBRARIES
>  LOCAL_SRC_FILES := \
> $(MESA_FILES)
>
> +ifeq ($(strip $(MESA_ENABLE_ASM)),true)
>  ifeq ($(TARGET_ARCH),x86)
> LOCAL_SRC_FILES += $(X86_FILES)
>  endif # x86
> +endif # MESA_ENABLE_ASM
>
>  ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
>  LOCAL_WHOLE_STATIC_LIBRARIES := \
> diff --git a/src/mesa/Android.libmesa_st_mesa.mk 
> b/src/mesa/Android.libmesa_st_mesa.mk
> index 16153a3c5b..ddfd03059c 100644
> --- a/src/mesa/Android.libmesa_st_mesa.mk
> +++ b/src/mesa/Android.libmesa_st_mesa.mk
> @@ -42,9 +42,11 @@ LOCAL_GENERATED_SOURCES := \
> $(MESA_GEN_GLSL_H) \
> $(MESA_GEN_NIR_H)
>
> +ifeq ($(strip $(MESA_ENABLE_ASM)),true)
>  ifeq ($(TARGET_ARCH),x86)
> LOCAL_SRC_FILES += $(X86_FILES)
>  endif # x86
> +endif # MESA_ENABLE_ASM
>
>  ifeq ($(ARCH_X86_HAVE_SSE4_1),true)
>  LOCAL_WHOLE_STATIC_LIBRARIES := \
> --

Looks good to me.

Review-by: Chih-Wei Huang 
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[Mesa-dev] [Bug 111150] [BRW] WRC 5 asserts with gallium nine and iris.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=50

--- Comment #5 from Illia Iorin  ---
> I created a merge request for this issue here:
> https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1371
> 
> Please let me know if it fixes the issue.

This mr fixes the issue. I tried to put the flash exact after
nine_context_clear_render_target in NineSurface9_ctor and it fixes the issue
too.

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[Mesa-dev] [Bug 111141] [REGRESSION] [BISECTED] [DXVK] 1-bit booleans and Elite Dangerous shader mis-optimization

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=41

--- Comment #8 from Steven Newbury  ---
So presumably it's the optimization for AMD?

I had a good look through the code but I'm not sufficiently clear as to how it
all works to really know where the bug might be.

My current understanding, please correct me if I'm wrong:

The game is shipped with HLSL shaders compiled to DXBC

DXVK converts those DXBC -> SPIR-V [D3D int32_t booleans are converted to
SPIR-V boolean type] 

(At this point all must be okay since it worked before and still works with
Intel, except that Intel has a different internal representation...)

SPIR-V -> NIR [SPIR-V booleans are converted to int1_t]

NIR -> GPU HW Shader [AMD Scaler booleans; Intel 1+31bit booleans]

(What happens if the booleans are part of a struct and the code assumes they're
32-bit during the above passes?  Previously, NIR used D3D compatible booleans
so it would just work, Intel is 32bit so maybe it all falls back into place?)

Is the above nonsense?

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[Mesa-dev] [AppVeyor] mesa staging/19.1 #11939 completed

[AppVeyor]

Build mesa 11939 completed



Commit 0b1ee72bbc by Lionel Landwerlin on 7/17/2019 10:00 PM:

anv: fix format mapping for depth/stencil formats\n\nanv_format is supposed to have a pointer back to the associated\nVkFormat, we were missed this for depth/stencil formats.\n\nThis doesn't fix anything afaict, but will be needed for future\nchanges.\n\nSigned-off-by: Lionel Landwerlin \nFixes: 465de47bad70 ("anv: associate vulkan formats with aspects")\nAcked-by: Jason Ekstrand \n(cherry picked from commit 3adc32df922753363d964b637196157587d57565)


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Re: [Mesa-dev] [PATCH v2 2/3] radv/gfx10: do not emit VGT_GS_MODE

[Bas Nieuwenhuizen]

We might want to merge this into patch 1, as we now emit the
R_028A84_VGT_PRIMITIVEID_EN twice after only patch 1.

Either way r-b for the series

On Thu, Jul 18, 2019 at 10:14 AM Samuel Pitoiset
 wrote:
>
> Unnecessary.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_pipeline.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
> index bcb7ccc803d..b11d79f4811 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -3274,6 +3274,9 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf 
> *ctx_cs,
> unsigned vgt_primitiveid_en = 0;
> uint32_t vgt_gs_mode = 0;
>
> +   if (radv_pipeline_has_ngg(pipeline))
> +   return;
> +
> if (radv_pipeline_has_gs(pipeline)) {
> const struct radv_shader_variant *gs =
> pipeline->shaders[MESA_SHADER_GEOMETRY];
> --
> 2.22.0
>
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Re: [Mesa-dev] [PATCH 4/4] radv/gfx10: do not always execute a barrier before the second shader

[Bas Nieuwenhuizen]

r-b

On Thu, Jul 18, 2019 at 10:04 AM Samuel Pitoiset
 wrote:
>
>
> On 7/18/19 2:29 AM, Bas Nieuwenhuizen wrote:
> > On Wed, Jul 17, 2019 at 3:44 PM Samuel Pitoiset
> >  wrote:
> >> With NGG, empty waves may still be required to export data.
> >>
> >> This fixes dEQP-VK.ycbcr.format.*_unorm.geometry_*.
> >>
> >> Signed-off-by: Samuel Pitoiset 
> >> ---
> >>   src/amd/vulkan/radv_nir_to_llvm.c | 31 ++-
> >>   1 file changed, 30 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
> >> b/src/amd/vulkan/radv_nir_to_llvm.c
> >> index 3e18303879e..7e623414adc 100644
> >> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> >> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> >> @@ -4448,8 +4448,37 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct 
> >> ac_llvm_compiler *ac_llvm,
> >>  declare_esgs_ring(&ctx);
> >>  }
> >>
> >> -   if (i)
> >> +   bool nested_barrier = false;
> >> +
> >> +   if (i) {
> >> +   if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY 
> >> &&
> >> +   ctx.options->key.vs_common_out.as_ngg) {
> >> +   nested_barrier = false;
> >> +   } else {
> >> +   nested_barrier = true;
> >> +   }
> >> +   }
> > We can simplify this to
> >
> > nested_barrier = i && (shaders[i]->info.stage != MESA_SHADER_GEOMETRY
> > || !ctx.options->key.vs_common_out.as_ngg);
> >
> > Otherwise r-b, I'm just surprised an s_barrier is okay.
> I'm going to move the NGG GS prologue into that inner if, so I would
> prefer to keep this way.
> >> +
> >> +   if (nested_barrier) {
> >> +   /* Execute a barrier before the second shader in
> >> +* a merged shader.
> >> +*
> >> +* Execute the barrier inside the conditional 
> >> block,
> >> +* so that empty waves can jump directly to 
> >> s_endpgm,
> >> +* which will also signal the barrier.
> >> +*
> >> +* This is possible in gfx9, because an empty wave
> >> +* for the second shader does not participate in
> >> +* the epilogue. With NGG, empty waves may still
> >> +* be required to export data (e.g. GS output 
> >> vertices),
> >> +* so we cannot let them exit early.
> >> +*
> >> +* If the shader is TCS and the TCS epilog is 
> >> present
> >> +* and contains a barrier, it will wait there and 
> >> then
> >> +* reach s_endpgm.
> >> +   */
> >>  ac_emit_barrier(&ctx.ac, ctx.stage);
> >> +   }
> >>
> >>  nir_foreach_variable(variable, &shaders[i]->outputs)
> >>  scan_shader_output_decl(&ctx, variable, 
> >> shaders[i], shaders[i]->info.stage);
> >> --
> >> 2.22.0
> >>
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[Mesa-dev] [PATCH v2 1/3] radv/gfx10: move emitting VGT_PRIMITIVEID_EN into the NGG path

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 9338fcd550a..bcb7ccc803d 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3280,12 +3280,6 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf 
*ctx_cs,
 
vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
 
pipeline->device->physical_device->rad_info.chip_class);
-   } else if (radv_pipeline_has_ngg(pipeline)) {
-   bool enable_prim_id =
-   outinfo->export_prim_id || vs->info.info.uses_prim_id;
-
-   vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) |
- 
S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id);
} else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
@@ -3425,6 +3419,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf 
*ctx_cs,
uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
gl_shader_stage es_type =
radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : 
MESA_SHADER_VERTEX;
+   struct radv_shader_variant *es =
+   es_type == MESA_SHADER_TESS_EVAL ? 
pipeline->shaders[MESA_SHADER_TESS_EVAL] : 
pipeline->shaders[MESA_SHADER_VERTEX];
 
radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
radeon_emit(cs, va >> 8);
@@ -3441,6 +3437,8 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf 
*ctx_cs,
bool misc_vec_ena = outinfo->writes_pointsize ||
outinfo->writes_layer ||
outinfo->writes_viewport_index;
+   bool es_enable_prim_id = outinfo->export_prim_id ||
+(es && es->info.info.uses_prim_id);
bool break_wave_at_eoi = false;
unsigned nparams;
 
@@ -3479,6 +3477,10 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf 
*ctx_cs,
   cull_dist_mask << 8 |
   clip_dist_mask);
 
+   radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
+  S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
+  
S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
+
bool vgt_reuse_off = pipeline->device->physical_device->rad_info.family 
== CHIP_NAVI10 &&
 
pipeline->device->physical_device->rad_info.chip_external_rev == 0x1 &&
 es_type == MESA_SHADER_TESS_EVAL;
-- 
2.22.0

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[Mesa-dev] [PATCH v2 3/3] radv/gfx10: set BREAK_WAVE_AT_EOI if TES or GS enable the primitive ID

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index b11d79f4811..a7ff0e2d139 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3445,6 +3445,14 @@ radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf 
*ctx_cs,
bool break_wave_at_eoi = false;
unsigned nparams;
 
+   if (es_type == MESA_SHADER_TESS_EVAL) {
+   struct radv_shader_variant *gs =
+   pipeline->shaders[MESA_SHADER_GEOMETRY];
+
+   if (es_enable_prim_id || (gs && gs->info.info.uses_prim_id))
+   break_wave_at_eoi = true;
+   }
+
nparams = MAX2(outinfo->param_exports, 1);
radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
   S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
-- 
2.22.0

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[Mesa-dev] [PATCH v2 2/3] radv/gfx10: do not emit VGT_GS_MODE

[Samuel Pitoiset]

Unnecessary.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_pipeline.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index bcb7ccc803d..b11d79f4811 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3274,6 +3274,9 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf 
*ctx_cs,
unsigned vgt_primitiveid_en = 0;
uint32_t vgt_gs_mode = 0;
 
+   if (radv_pipeline_has_ngg(pipeline))
+   return;
+
if (radv_pipeline_has_gs(pipeline)) {
const struct radv_shader_variant *gs =
pipeline->shaders[MESA_SHADER_GEOMETRY];
-- 
2.22.0

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Re: [Mesa-dev] [PATCH 4/4] radv/gfx10: do not always execute a barrier before the second shader

[Samuel Pitoiset]

On 7/18/19 2:29 AM, Bas Nieuwenhuizen wrote:

On Wed, Jul 17, 2019 at 3:44 PM Samuel Pitoiset
 wrote:

With NGG, empty waves may still be required to export data.

This fixes dEQP-VK.ycbcr.format.*_unorm.geometry_*.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_nir_to_llvm.c | 31 ++-
  1 file changed, 30 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 3e18303879e..7e623414adc 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4448,8 +4448,37 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct 
ac_llvm_compiler *ac_llvm,
 declare_esgs_ring(&ctx);
 }

-   if (i)
+   bool nested_barrier = false;
+
+   if (i) {
+   if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
+   ctx.options->key.vs_common_out.as_ngg) {
+   nested_barrier = false;
+   } else {
+   nested_barrier = true;
+   }
+   }

We can simplify this to

nested_barrier = i && (shaders[i]->info.stage != MESA_SHADER_GEOMETRY
|| !ctx.options->key.vs_common_out.as_ngg);

Otherwise r-b, I'm just surprised an s_barrier is okay.
I'm going to move the NGG GS prologue into that inner if, so I would 
prefer to keep this way.

+
+   if (nested_barrier) {
+   /* Execute a barrier before the second shader in
+* a merged shader.
+*
+* Execute the barrier inside the conditional block,
+* so that empty waves can jump directly to s_endpgm,
+* which will also signal the barrier.
+*
+* This is possible in gfx9, because an empty wave
+* for the second shader does not participate in
+* the epilogue. With NGG, empty waves may still
+* be required to export data (e.g. GS output vertices),
+* so we cannot let them exit early.
+*
+* If the shader is TCS and the TCS epilog is present
+* and contains a barrier, it will wait there and then
+* reach s_endpgm.
+   */
 ac_emit_barrier(&ctx.ac, ctx.stage);
+   }

 nir_foreach_variable(variable, &shaders[i]->outputs)
 scan_shader_output_decl(&ctx, variable, shaders[i], 
shaders[i]->info.stage);
--
2.22.0

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Re: [Mesa-dev] [PATCH 1/4] radv: move emitting VGT_GS_MODE into the HW VS path

[Samuel Pitoiset]

On 7/18/19 2:10 AM, Bas Nieuwenhuizen wrote:

On Thu, Jul 18, 2019 at 2:05 AM Bas Nieuwenhuizen
 wrote:

On Wed, Jul 17, 2019 at 3:44 PM Samuel Pitoiset
 wrote:

It's useless for NGG anyways.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_pipeline.c | 43 ++
  1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index fdeb31c453e..686fd371f0f 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -3272,27 +3272,18 @@ radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf 
*ctx_cs,

Can you rename the function?

Actually now that I see your later patches, how about we keep this
function, return immediately if ngg, and then move the primitive id
stuff for ngg to ngg?

Yes, looks better.






 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
 pipeline->shaders[MESA_SHADER_VERTEX];
 unsigned vgt_primitiveid_en = 0;
-   uint32_t vgt_gs_mode = 0;

-   if (radv_pipeline_has_gs(pipeline)) {
-   const struct radv_shader_variant *gs =
-   pipeline->shaders[MESA_SHADER_GEOMETRY];
-
-   vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
-
pipeline->device->physical_device->rad_info.chip_class);
-   } else if (radv_pipeline_has_ngg(pipeline)) {
+   if (radv_pipeline_has_ngg(pipeline)) {
 bool enable_prim_id =
 outinfo->export_prim_id || vs->info.info.uses_prim_id;

 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(enable_prim_id) |
   
S_028A84_NGG_DISABLE_PROVOK_REUSE(enable_prim_id);
 } else if (outinfo->export_prim_id || vs->info.info.uses_prim_id) {
-   vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
 }

 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, 
vgt_primitiveid_en);
-   radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
  }

  static void
@@ -3370,6 +3361,38 @@ radv_pipeline_generate_hw_vs(struct radeon_cmdbuf 
*ctx_cs,
cull_dist_mask << 8 |
clip_dist_mask);

+   /* We always write VGT_GS_MODE in the VS state, because every switch
+* between different shader pipelines involving a different GS or no GS
+* at all involves a switch of the VS (different GS use different copy
+* shaders). On the other hand, when the API switches from a GS to no
+* GS and then back to the same GS used originally, the GS state is not
+* sent again.
+*/
+   unsigned vgt_gs_mode;
+   if (!radv_pipeline_has_gs(pipeline)) {
+   const struct radv_vs_output_info *outinfo =
+   get_vs_output_info(pipeline);
+   const struct radv_shader_variant *vs =
+   pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
+   pipeline->shaders[MESA_SHADER_TESS_EVAL] :
+   pipeline->shaders[MESA_SHADER_VERTEX];
+   unsigned mode = V_028A40_GS_OFF;
+
+   /* PrimID needs GS scenario A. */
+   if (outinfo->export_prim_id || vs->info.info.uses_prim_id)
+   mode = V_028A40_GS_SCENARIO_A;
+
+   vgt_gs_mode = S_028A40_MODE(mode);
+   } else {
+   const struct radv_shader_variant *gs =
+   pipeline->shaders[MESA_SHADER_GEOMETRY];
+
+   vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
+
pipeline->device->physical_device->rad_info.chip_class);
+   }
+
+   radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
+

Can you keep this in a separate function (possibly with the name
radv_pipeline_generate_vgt_gs_mode)?

 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
outinfo->writes_viewport_index);
--
2.22.0

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Re: [Mesa-dev] [PATCH] radv: fix crash in shader tracing.

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 7/18/19 2:51 AM, Dave Airlie wrote:

From: Dave Airlie 

Enabling tracing, and then having a vmfault, can leads to a segfault
before we print out the traces, as if a meta shader is executing
and we don't have the NIR for it.

Just pass the stage and give back a default.

Fixes: 9b9ccee4d64 ("radv: take LDS into account for compute shader occupancy 
stats")
---
  src/amd/vulkan/radv_nir_to_llvm.c | 8 ++--
  src/amd/vulkan/radv_private.h | 1 +
  src/amd/vulkan/radv_shader.c  | 2 +-
  3 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index 3e18303879e..c08789a4361 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4244,9 +4244,10 @@ ac_setup_rings(struct radv_shader_context *ctx)
  
  unsigned

  radv_nir_get_max_workgroup_size(enum chip_class chip_class,
+   gl_shader_stage stage,
const struct nir_shader *nir)
  {
-   switch (nir->info.stage) {
+   switch (stage) {
case MESA_SHADER_TESS_CTRL:
return chip_class >= GFX7 ? 128 : 64;
case MESA_SHADER_GEOMETRY:
@@ -4257,6 +4258,8 @@ radv_nir_get_max_workgroup_size(enum chip_class 
chip_class,
return 0;
}
  
+	if (!nir)

+   return chip_class >= GFX9 ? 128 : 64;
unsigned max_workgroup_size = nir->info.cs.local_size[0] *
nir->info.cs.local_size[1] *
nir->info.cs.local_size[2];
@@ -4340,7 +4343,8 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct 
ac_llvm_compiler *ac_llvm,
for (int i = 0; i < shader_count; ++i) {
ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
  
radv_nir_get_max_workgroup_size(ctx.options->chip_class,
-   
shaders[i]));
+ 
shaders[i]->info.stage,
+ 
shaders[i]));
}
  
  	if (ctx.ac.chip_class >= GFX10) {

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 931d4039397..f1f30887e01 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -2138,6 +2138,7 @@ void radv_compile_nir_shader(struct ac_llvm_compiler 
*ac_llvm,
 const struct radv_nir_compiler_options *options);
  
  unsigned radv_nir_get_max_workgroup_size(enum chip_class chip_class,

+gl_shader_stage stage,
 const struct nir_shader *nir);
  
  /* radv_shader_info.h */

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index bcc050a86cc..8f24a6d72b0 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -1232,7 +1232,7 @@ generate_shader_stats(struct radv_device *device,
 lds_increment);
} else if (stage == MESA_SHADER_COMPUTE) {
unsigned max_workgroup_size =
-   radv_nir_get_max_workgroup_size(chip_class, 
variant->nir);
+   radv_nir_get_max_workgroup_size(chip_class, stage, 
variant->nir);
lds_per_wave = (conf->lds_size * lds_increment) /
   DIV_ROUND_UP(max_workgroup_size, 64);
}

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Re: [Mesa-dev] [PATCH] radv: reset the window scissor with no clear state.

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 7/18/19 3:20 AM, Dave Airlie wrote:

From: Dave Airlie 

IF we don't have clear state (which gfx10 doesn't currently)
we will fix to reset the scissor. AMDVLK will leave it set
to something else.

Marek also has this fix for radeonsi pending.
---
  src/amd/vulkan/si_cmd_buffer.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
index 6fe447ef2e9..0efa169d674 100644
--- a/src/amd/vulkan/si_cmd_buffer.c
+++ b/src/amd/vulkan/si_cmd_buffer.c
@@ -202,7 +202,7 @@ si_emit_graphics(struct radv_physical_device 
*physical_device,
/* CLEAR_STATE doesn't clear these correctly on certain generations.
 * I don't know why. Deduced by trial and error.
 */
-   if (physical_device->rad_info.chip_class <= GFX7) {
+   if (physical_device->rad_info.chip_class <= GFX7 || 
!physical_device->has_clear_state) {
radeon_set_context_reg(cs, 
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
radeon_set_context_reg(cs, R_028204_PA_SC_WINDOW_SCISSOR_TL,
   S_028204_WINDOW_OFFSET_DISABLE(1));

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