Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Tue, Oct 23, 2018 at 12:04 PM Christian Gmeiner <
christian.gmei...@gmail.com> wrote:
> Am Di., 23. Okt. 2018 um 18:31 Uhr schrieb Ian Romanick <
> i...@freedesktop.org>:
> >
> > On 10/23/2018 08:33 AM, Connor Abbott wrote:
> > > On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand
> wrote:
> > >>
> > >> This should be useful for drivers that don't support real integers.
> > >>
> > >> Cc: Alyssa Rosenzweig
> > >> ---
> > >> src/compiler/Makefile.sources | 1 +
> > >> src/compiler/nir/meson.build | 1 +
> > >> src/compiler/nir/nir_lower_bool_to_float.c | 181
> +
> > >> 3 files changed, 183 insertions(+)
> > >> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> > >>
> > >> diff --git a/src/compiler/Makefile.sources
> b/src/compiler/Makefile.sources
> > >> index 8f65f974ab8..2ff12ff43cb 100644
> > >> --- a/src/compiler/Makefile.sources
> > >> +++ b/src/compiler/Makefile.sources
> > >> @@ -230,6 +230,7 @@ NIR_FILES = \
> > >> nir/nir_lower_atomics_to_ssbo.c \
> > >> nir/nir_lower_bitmap.c \
> > >> nir/nir_lower_bit_size.c \
> > >> + nir/nir_lower_bool_to_float.c \
> > >> nir/nir_lower_bool_to_int32.c \
> > >> nir/nir_lower_clamp_color_outputs.c \
> > >> nir/nir_lower_clip.c \
> > >> diff --git a/src/compiler/nir/meson.build
> b/src/compiler/nir/meson.build
> > >> index 5809551c9d4..f715668a03b 100644
> > >> --- a/src/compiler/nir/meson.build
> > >> +++ b/src/compiler/nir/meson.build
> > >> @@ -113,6 +113,7 @@ files_libnir = files(
> > >>'nir_lower_alpha_test.c',
> > >>'nir_lower_atomics_to_ssbo.c',
> > >>'nir_lower_bitmap.c',
> > >> + 'nir_lower_bool_to_float.c',
> > >>'nir_lower_bool_to_int32.c',
> > >>'nir_lower_clamp_color_outputs.c',
> > >>'nir_lower_clip.c',
> > >> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> b/src/compiler/nir/nir_lower_bool_to_float.c
> > >> new file mode 100644
> > >> index 000..7aa5efb5a2f
> > >> --- /dev/null
> > >> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> > >> @@ -0,0 +1,181 @@
> > >> +/*
> > >> + * Copyright © 2018 Intel Corporation
> > >> + *
> > >> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> > >> + * copy of this software and associated documentation files (the
> "Software"),
> > >> + * to deal in the Software without restriction, including without
> limitation
> > >> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> > >> + * and/or sell copies of the Software, and to permit persons to whom
> the
> > >> + * Software is furnished to do so, subject to the following
> conditions:
> > >> + *
> > >> + * The above copyright notice and this permission notice (including
> the next
> > >> + * paragraph) shall be included in all copies or substantial
> portions of the
> > >> + * Software.
> > >> + *
> > >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> > >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> > >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> > >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> > >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> > >> + * IN THE SOFTWARE.
> > >> + */
> > >> +
> > >> +#include "nir.h"
> > >> +#include "nir_builder.h"
> > >> +
> > >> +static bool
> > >> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> > >> +{
> > >> + assert(def->bit_size > 1);
> > >> + return true;
> > >> +}
> > >> +
> > >> +static bool
> > >> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> > >> +{
> > >> + bool *progress = _progress;
> > >> + if (def->bit_size == 1) {
> > >> + def->bit_size = 32;
> > >> + *progress = true;
> > >> + }
> > >> + return true;
> > >> +}
> > >> +
> > >> +static bool
> > >> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> > >> +{
> > >> + const nir_op_info *op_info = &nir_op_infos[alu->op];
> > >> +
> > >> + b->cursor = nir_before_instr(&alu->instr);
> > >> +
> > >> + /* Replacement SSA value */
> > >> + nir_ssa_def *rep = NULL;
> > >> + switch (alu->op) {
> > >> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> > >> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> > >> + case nir_op_f2b:
> > >> + case nir_op_i2b:
> > >> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> > >> + nir_imm_float(b, 0));
> > >> + break;
> > >> +
> > >> + case nir_op_flt: alu->op = nir_op_slt; break;
> > >> + case nir_op_fge: alu->op = nir_op_sge; break;
> > >> + case nir_op_feq: alu->op = nir_op_seq; break;
> > >> + case nir_op_fne: alu->op = nir_op_sne; break;
> > >> + case nir_op_ilt: alu->op = nir_op_slt; break;
> > >> + case nir_op_ige: alu
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
Am Di., 23. Okt. 2018 um 18:31 Uhr schrieb Ian Romanick :
>
> On 10/23/2018 08:33 AM, Connor Abbott wrote:
> > On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand
> > wrote:
> >>
> >> This should be useful for drivers that don't support real integers.
> >>
> >> Cc: Alyssa Rosenzweig
> >> ---
> >> src/compiler/Makefile.sources | 1 +
> >> src/compiler/nir/meson.build | 1 +
> >> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> >> 3 files changed, 183 insertions(+)
> >> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> >>
> >> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> >> index 8f65f974ab8..2ff12ff43cb 100644
> >> --- a/src/compiler/Makefile.sources
> >> +++ b/src/compiler/Makefile.sources
> >> @@ -230,6 +230,7 @@ NIR_FILES = \
> >> nir/nir_lower_atomics_to_ssbo.c \
> >> nir/nir_lower_bitmap.c \
> >> nir/nir_lower_bit_size.c \
> >> + nir/nir_lower_bool_to_float.c \
> >> nir/nir_lower_bool_to_int32.c \
> >> nir/nir_lower_clamp_color_outputs.c \
> >> nir/nir_lower_clip.c \
> >> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> >> index 5809551c9d4..f715668a03b 100644
> >> --- a/src/compiler/nir/meson.build
> >> +++ b/src/compiler/nir/meson.build
> >> @@ -113,6 +113,7 @@ files_libnir = files(
> >>'nir_lower_alpha_test.c',
> >>'nir_lower_atomics_to_ssbo.c',
> >>'nir_lower_bitmap.c',
> >> + 'nir_lower_bool_to_float.c',
> >>'nir_lower_bool_to_int32.c',
> >>'nir_lower_clamp_color_outputs.c',
> >>'nir_lower_clip.c',
> >> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> >> b/src/compiler/nir/nir_lower_bool_to_float.c
> >> new file mode 100644
> >> index 000..7aa5efb5a2f
> >> --- /dev/null
> >> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> >> @@ -0,0 +1,181 @@
> >> +/*
> >> + * Copyright © 2018 Intel Corporation
> >> + *
> >> + * Permission is hereby granted, free of charge, to any person obtaining a
> >> + * copy of this software and associated documentation files (the
> >> "Software"),
> >> + * to deal in the Software without restriction, including without
> >> limitation
> >> + * the rights to use, copy, modify, merge, publish, distribute,
> >> sublicense,
> >> + * and/or sell copies of the Software, and to permit persons to whom the
> >> + * Software is furnished to do so, subject to the following conditions:
> >> + *
> >> + * The above copyright notice and this permission notice (including the
> >> next
> >> + * paragraph) shall be included in all copies or substantial portions of
> >> the
> >> + * Software.
> >> + *
> >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> >> EXPRESS OR
> >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> >> MERCHANTABILITY,
> >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
> >> SHALL
> >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
> >> OTHER
> >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> >> DEALINGS
> >> + * IN THE SOFTWARE.
> >> + */
> >> +
> >> +#include "nir.h"
> >> +#include "nir_builder.h"
> >> +
> >> +static bool
> >> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> >> +{
> >> + assert(def->bit_size > 1);
> >> + return true;
> >> +}
> >> +
> >> +static bool
> >> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> >> +{
> >> + bool *progress = _progress;
> >> + if (def->bit_size == 1) {
> >> + def->bit_size = 32;
> >> + *progress = true;
> >> + }
> >> + return true;
> >> +}
> >> +
> >> +static bool
> >> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> >> +{
> >> + const nir_op_info *op_info = &nir_op_infos[alu->op];
> >> +
> >> + b->cursor = nir_before_instr(&alu->instr);
> >> +
> >> + /* Replacement SSA value */
> >> + nir_ssa_def *rep = NULL;
> >> + switch (alu->op) {
> >> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> >> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> >> + case nir_op_f2b:
> >> + case nir_op_i2b:
> >> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> >> + nir_imm_float(b, 0));
> >> + break;
> >> +
> >> + case nir_op_flt: alu->op = nir_op_slt; break;
> >> + case nir_op_fge: alu->op = nir_op_sge; break;
> >> + case nir_op_feq: alu->op = nir_op_seq; break;
> >> + case nir_op_fne: alu->op = nir_op_sne; break;
> >> + case nir_op_ilt: alu->op = nir_op_slt; break;
> >> + case nir_op_ige: alu->op = nir_op_sge; break;
> >> + case nir_op_ieq: alu->op = nir_op_seq; break;
> >> + case nir_op_ine: alu->op = nir_op_sne; break;
> >> + case nir_op_ult: alu->op = nir_op_slt; break;
> >> + case nir_op_uge: alu->op = nir_op_sge; break;
> >> +
> >> + case nir_op_ball_fequal2: alu->op = nir_op_fa
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On 10/23/2018 08:33 AM, Connor Abbott wrote:
> On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>>
>> This should be useful for drivers that don't support real integers.
>>
>> Cc: Alyssa Rosenzweig
>> ---
>> src/compiler/Makefile.sources | 1 +
>> src/compiler/nir/meson.build | 1 +
>> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
>> 3 files changed, 183 insertions(+)
>> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
>>
>> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
>> index 8f65f974ab8..2ff12ff43cb 100644
>> --- a/src/compiler/Makefile.sources
>> +++ b/src/compiler/Makefile.sources
>> @@ -230,6 +230,7 @@ NIR_FILES = \
>> nir/nir_lower_atomics_to_ssbo.c \
>> nir/nir_lower_bitmap.c \
>> nir/nir_lower_bit_size.c \
>> + nir/nir_lower_bool_to_float.c \
>> nir/nir_lower_bool_to_int32.c \
>> nir/nir_lower_clamp_color_outputs.c \
>> nir/nir_lower_clip.c \
>> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
>> index 5809551c9d4..f715668a03b 100644
>> --- a/src/compiler/nir/meson.build
>> +++ b/src/compiler/nir/meson.build
>> @@ -113,6 +113,7 @@ files_libnir = files(
>>'nir_lower_alpha_test.c',
>>'nir_lower_atomics_to_ssbo.c',
>>'nir_lower_bitmap.c',
>> + 'nir_lower_bool_to_float.c',
>>'nir_lower_bool_to_int32.c',
>>'nir_lower_clamp_color_outputs.c',
>>'nir_lower_clip.c',
>> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
>> b/src/compiler/nir/nir_lower_bool_to_float.c
>> new file mode 100644
>> index 000..7aa5efb5a2f
>> --- /dev/null
>> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
>> @@ -0,0 +1,181 @@
>> +/*
>> + * Copyright © 2018 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the
>> "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
>> DEALINGS
>> + * IN THE SOFTWARE.
>> + */
>> +
>> +#include "nir.h"
>> +#include "nir_builder.h"
>> +
>> +static bool
>> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
>> +{
>> + assert(def->bit_size > 1);
>> + return true;
>> +}
>> +
>> +static bool
>> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
>> +{
>> + bool *progress = _progress;
>> + if (def->bit_size == 1) {
>> + def->bit_size = 32;
>> + *progress = true;
>> + }
>> + return true;
>> +}
>> +
>> +static bool
>> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
>> +{
>> + const nir_op_info *op_info = &nir_op_infos[alu->op];
>> +
>> + b->cursor = nir_before_instr(&alu->instr);
>> +
>> + /* Replacement SSA value */
>> + nir_ssa_def *rep = NULL;
>> + switch (alu->op) {
>> + case nir_op_b2f: alu->op = nir_op_fmov; break;
>> + case nir_op_b2i: alu->op = nir_op_fmov; break;
>> + case nir_op_f2b:
>> + case nir_op_i2b:
>> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
>> + nir_imm_float(b, 0));
>> + break;
>> +
>> + case nir_op_flt: alu->op = nir_op_slt; break;
>> + case nir_op_fge: alu->op = nir_op_sge; break;
>> + case nir_op_feq: alu->op = nir_op_seq; break;
>> + case nir_op_fne: alu->op = nir_op_sne; break;
>> + case nir_op_ilt: alu->op = nir_op_slt; break;
>> + case nir_op_ige: alu->op = nir_op_sge; break;
>> + case nir_op_ieq: alu->op = nir_op_seq; break;
>> + case nir_op_ine: alu->op = nir_op_sne; break;
>> + case nir_op_ult: alu->op = nir_op_slt; break;
>> + case nir_op_uge: alu->op = nir_op_sge; break;
>> +
>> + case nir_op_ball_fequal2: alu->op = nir_op_fall_equal2; break;
>> + case nir_op_ball_fequal3: alu->op = nir_op_fall_equal3; break;
>> + case nir_op_ball_fequal4: alu->op = nir_op_fall_equal4; break;
>> + case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
>> + case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
>> + case nir_op_bany_fnequal4: alu->op
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Tue, Oct 23, 2018 at 12:16 AM Jason Ekstrand wrote:
>
> This should be useful for drivers that don't support real integers.
>
> Cc: Alyssa Rosenzweig
> ---
> src/compiler/Makefile.sources | 1 +
> src/compiler/nir/meson.build | 1 +
> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> 3 files changed, 183 insertions(+)
> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
>
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index 8f65f974ab8..2ff12ff43cb 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -230,6 +230,7 @@ NIR_FILES = \
> nir/nir_lower_atomics_to_ssbo.c \
> nir/nir_lower_bitmap.c \
> nir/nir_lower_bit_size.c \
> + nir/nir_lower_bool_to_float.c \
> nir/nir_lower_bool_to_int32.c \
> nir/nir_lower_clamp_color_outputs.c \
> nir/nir_lower_clip.c \
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index 5809551c9d4..f715668a03b 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -113,6 +113,7 @@ files_libnir = files(
>'nir_lower_alpha_test.c',
>'nir_lower_atomics_to_ssbo.c',
>'nir_lower_bitmap.c',
> + 'nir_lower_bool_to_float.c',
>'nir_lower_bool_to_int32.c',
>'nir_lower_clamp_color_outputs.c',
>'nir_lower_clip.c',
> diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
> b/src/compiler/nir/nir_lower_bool_to_float.c
> new file mode 100644
> index 000..7aa5efb5a2f
> --- /dev/null
> +++ b/src/compiler/nir/nir_lower_bool_to_float.c
> @@ -0,0 +1,181 @@
> +/*
> + * Copyright © 2018 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir.h"
> +#include "nir_builder.h"
> +
> +static bool
> +assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
> +{
> + assert(def->bit_size > 1);
> + return true;
> +}
> +
> +static bool
> +rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
> +{
> + bool *progress = _progress;
> + if (def->bit_size == 1) {
> + def->bit_size = 32;
> + *progress = true;
> + }
> + return true;
> +}
> +
> +static bool
> +lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
> +{
> + const nir_op_info *op_info = &nir_op_infos[alu->op];
> +
> + b->cursor = nir_before_instr(&alu->instr);
> +
> + /* Replacement SSA value */
> + nir_ssa_def *rep = NULL;
> + switch (alu->op) {
> + case nir_op_b2f: alu->op = nir_op_fmov; break;
> + case nir_op_b2i: alu->op = nir_op_fmov; break;
> + case nir_op_f2b:
> + case nir_op_i2b:
> + rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
> + nir_imm_float(b, 0));
> + break;
> +
> + case nir_op_flt: alu->op = nir_op_slt; break;
> + case nir_op_fge: alu->op = nir_op_sge; break;
> + case nir_op_feq: alu->op = nir_op_seq; break;
> + case nir_op_fne: alu->op = nir_op_sne; break;
> + case nir_op_ilt: alu->op = nir_op_slt; break;
> + case nir_op_ige: alu->op = nir_op_sge; break;
> + case nir_op_ieq: alu->op = nir_op_seq; break;
> + case nir_op_ine: alu->op = nir_op_sne; break;
> + case nir_op_ult: alu->op = nir_op_slt; break;
> + case nir_op_uge: alu->op = nir_op_sge; break;
> +
> + case nir_op_ball_fequal2: alu->op = nir_op_fall_equal2; break;
> + case nir_op_ball_fequal3: alu->op = nir_op_fall_equal3; break;
> + case nir_op_ball_fequal4: alu->op = nir_op_fall_equal4; break;
> + case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
> + case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
> + case nir_op_bany_fnequal4: alu->op = nir_op_fany_nequal4; break;
> + case nir_op_ball_iequal2: alu->op = nir_op_fall_equal2; break;
> + case nir_op_ball_iequal3: alu->op = nir_op_fall_equal3; break;
> + case
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
Am Di., 23. Okt. 2018 um 01:43 Uhr schrieb Jason Ekstrand : > > On Mon, Oct 22, 2018 at 6:20 PM Alyssa Rosenzweig > wrote: >> >> For what it's worth, Midgard has real integers (including int32 >> support), using hardware-level D3D10 boolean conventions. I'm trying to >> wrap my head around how this interacts with 5d85a0a. > > > Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia > can CC the right person. > I really love this pass and will help me/etnaviv to - reduce my hand crafted handling for such cases - make it easy to support vivante gpus with and without integer support I can give this pass a try over the weekend if you want. -- greets -- Christian Gmeiner, MSc https://christian-gmeiner.info ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
I think so? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On October 22, 2018 20:13:25 Alyssa Rosenzweig wrote: If you want to set me straight, that's probably the better patch to argue it out. :) No, I thought about it; you're right. I understand my hardware (and NIR) much better now than what I wrote the earlier patch; you have now shown me the error of my ways :) Nothing special should be needed for Midgard. Does that mean I should revise things to delete lower_b2f entirely? --Jason ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
> If you want to set me straight, that's probably the better patch to > argue it out. :) No, I thought about it; you're right. I understand my hardware (and NIR) much better now than what I wrote the earlier patch; you have now shown me the error of my ways :) Nothing special should be needed for Midgard. Thank you. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On 10/22/2018 05:09 PM, Alyssa Rosenzweig wrote: >> Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia >> can CC the right person. > > No worries at all! It may well have been me (I had touched the b2f code; > our hardware lacks a dedicated instruction and needs `iand 1.0` to do > the conversion). I'm not sure which hardware lacks native integers these > days. It does have an instruction. That instruction is just 'iand 1.0'. :) This is what we do in i965. I mentioned this in my review of patch 14. If you want to set me straight, that's probably the better patch to argue it out. :) > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
> Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia > can CC the right person. No worries at all! It may well have been me (I had touched the b2f code; our hardware lacks a dedicated instruction and needs `iand 1.0` to do the conversion). I'm not sure which hardware lacks native integers these days. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Mon, Oct 22, 2018 at 6:13 PM Ilia Mirkin wrote:
> On Mon, Oct 22, 2018 at 6:16 PM Jason Ekstrand
> wrote:
> >
> > This should be useful for drivers that don't support real integers.
> >
> > Cc: Alyssa Rosenzweig
> > ---
> > src/compiler/Makefile.sources | 1 +
> > src/compiler/nir/meson.build | 1 +
> > src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> > 3 files changed, 183 insertions(+)
> > create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> > + nir_foreach_block(block, impl) {
> > + nir_foreach_instr_safe(instr, block) {
> > + switch (instr->type) {
> > + case nir_instr_type_alu:
> > +progress |= lower_alu_instr(&b, nir_instr_as_alu(instr));
> > +break;
> > +
> > + case nir_instr_type_load_const: {
> > +nir_load_const_instr *load = nir_instr_as_load_const(instr);
> > +if (load->def.bit_size == 1) {
> > + nir_const_value value = load->value;
> > + for (unsigned i = 0; i < load->def.num_components; i++)
> > + load->value.u32[i] = value.b[i] ? NIR_TRUE :
> NIR_FALSE;
> > + load->def.bit_size = 32;
> > + progress = true;
> > +}
> > +break;
> > + }
>
> Should this instead rewrite the load_const to a 1.0f / 0.0f?
>
Yup. As you can tell, this is completely untested. However, I think it
does make the point that 1-bit bools aren't bad for float-only hardware
which is why I did it. I've fixed the bugs pointed out so far.
--Jason
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Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Mon, Oct 22, 2018 at 6:20 PM Alyssa Rosenzweig wrote: > For what it's worth, Midgard has real integers (including int32 > support), using hardware-level D3D10 boolean conventions. I'm trying to > wrap my head around how this interacts with 5d85a0a. > Right. Sorry. I forgot who's working on what chip these days. Maybe Ilia can CC the right person. --Jason > I'm tempted to think the standard lower_bool_to_int32 pass would work, > with an emulated b2f instruction in the backend IR level, rather than > burdening NIR with those details. > > I'll have to look at the patch set closer to understand the impact. > > --- > > > +nir_lower_bool_to_int32_impl(nir_function_impl *impl) > > +nir_lower_bool_to_int32(nir_shader *shader) > > + if (function->impl && > nir_lower_bool_to_int32_impl(function->impl)) > > I'm guessing these were intended to read float32? > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
For what it's worth, Midgard has real integers (including int32 support), using hardware-level D3D10 boolean conventions. I'm trying to wrap my head around how this interacts with 5d85a0a. I'm tempted to think the standard lower_bool_to_int32 pass would work, with an emulated b2f instruction in the backend IR level, rather than burdening NIR with those details. I'll have to look at the patch set closer to understand the impact. --- > +nir_lower_bool_to_int32_impl(nir_function_impl *impl) > +nir_lower_bool_to_int32(nir_shader *shader) > + if (function->impl && nir_lower_bool_to_int32_impl(function->impl)) I'm guessing these were intended to read float32? ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
On Mon, Oct 22, 2018 at 6:16 PM Jason Ekstrand wrote:
>
> This should be useful for drivers that don't support real integers.
>
> Cc: Alyssa Rosenzweig
> ---
> src/compiler/Makefile.sources | 1 +
> src/compiler/nir/meson.build | 1 +
> src/compiler/nir/nir_lower_bool_to_float.c | 181 +
> 3 files changed, 183 insertions(+)
> create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
> + nir_foreach_block(block, impl) {
> + nir_foreach_instr_safe(instr, block) {
> + switch (instr->type) {
> + case nir_instr_type_alu:
> +progress |= lower_alu_instr(&b, nir_instr_as_alu(instr));
> +break;
> +
> + case nir_instr_type_load_const: {
> +nir_load_const_instr *load = nir_instr_as_load_const(instr);
> +if (load->def.bit_size == 1) {
> + nir_const_value value = load->value;
> + for (unsigned i = 0; i < load->def.num_components; i++)
> + load->value.u32[i] = value.b[i] ? NIR_TRUE : NIR_FALSE;
> + load->def.bit_size = 32;
> + progress = true;
> +}
> +break;
> + }
Should this instead rewrite the load_const to a 1.0f / 0.0f?
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[Mesa-dev] [RFC 31/31] nir: Add a bool to float32 lowering pass
This should be useful for drivers that don't support real integers.
Cc: Alyssa Rosenzweig
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir_lower_bool_to_float.c | 181 +
3 files changed, 183 insertions(+)
create mode 100644 src/compiler/nir/nir_lower_bool_to_float.c
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 8f65f974ab8..2ff12ff43cb 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -230,6 +230,7 @@ NIR_FILES = \
nir/nir_lower_atomics_to_ssbo.c \
nir/nir_lower_bitmap.c \
nir/nir_lower_bit_size.c \
+ nir/nir_lower_bool_to_float.c \
nir/nir_lower_bool_to_int32.c \
nir/nir_lower_clamp_color_outputs.c \
nir/nir_lower_clip.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 5809551c9d4..f715668a03b 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -113,6 +113,7 @@ files_libnir = files(
'nir_lower_alpha_test.c',
'nir_lower_atomics_to_ssbo.c',
'nir_lower_bitmap.c',
+ 'nir_lower_bool_to_float.c',
'nir_lower_bool_to_int32.c',
'nir_lower_clamp_color_outputs.c',
'nir_lower_clip.c',
diff --git a/src/compiler/nir/nir_lower_bool_to_float.c
b/src/compiler/nir/nir_lower_bool_to_float.c
new file mode 100644
index 000..7aa5efb5a2f
--- /dev/null
+++ b/src/compiler/nir/nir_lower_bool_to_float.c
@@ -0,0 +1,181 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+
+static bool
+assert_ssa_def_is_not_1bit(nir_ssa_def *def, UNUSED void *unused)
+{
+ assert(def->bit_size > 1);
+ return true;
+}
+
+static bool
+rewrite_1bit_ssa_def_to_32bit(nir_ssa_def *def, void *_progress)
+{
+ bool *progress = _progress;
+ if (def->bit_size == 1) {
+ def->bit_size = 32;
+ *progress = true;
+ }
+ return true;
+}
+
+static bool
+lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
+{
+ const nir_op_info *op_info = &nir_op_infos[alu->op];
+
+ b->cursor = nir_before_instr(&alu->instr);
+
+ /* Replacement SSA value */
+ nir_ssa_def *rep = NULL;
+ switch (alu->op) {
+ case nir_op_b2f: alu->op = nir_op_fmov; break;
+ case nir_op_b2i: alu->op = nir_op_fmov; break;
+ case nir_op_f2b:
+ case nir_op_i2b:
+ rep = nir_sne(b, nir_ssa_for_alu_src(b, alu, 0),
+ nir_imm_float(b, 0));
+ break;
+
+ case nir_op_flt: alu->op = nir_op_slt; break;
+ case nir_op_fge: alu->op = nir_op_sge; break;
+ case nir_op_feq: alu->op = nir_op_seq; break;
+ case nir_op_fne: alu->op = nir_op_sne; break;
+ case nir_op_ilt: alu->op = nir_op_slt; break;
+ case nir_op_ige: alu->op = nir_op_sge; break;
+ case nir_op_ieq: alu->op = nir_op_seq; break;
+ case nir_op_ine: alu->op = nir_op_sne; break;
+ case nir_op_ult: alu->op = nir_op_slt; break;
+ case nir_op_uge: alu->op = nir_op_sge; break;
+
+ case nir_op_ball_fequal2: alu->op = nir_op_fall_equal2; break;
+ case nir_op_ball_fequal3: alu->op = nir_op_fall_equal3; break;
+ case nir_op_ball_fequal4: alu->op = nir_op_fall_equal4; break;
+ case nir_op_bany_fnequal2: alu->op = nir_op_fany_nequal2; break;
+ case nir_op_bany_fnequal3: alu->op = nir_op_fany_nequal3; break;
+ case nir_op_bany_fnequal4: alu->op = nir_op_fany_nequal4; break;
+ case nir_op_ball_iequal2: alu->op = nir_op_fall_equal2; break;
+ case nir_op_ball_iequal3: alu->op = nir_op_fall_equal3; break;
+ case nir_op_ball_iequal4: alu->op = nir_op_fall_equal4; break;
+ case nir_op_bany_inequal2: alu->op = nir_op_fany_nequal2; break;
+ case nir_op_bany_inequal3: alu->op = nir_op_fany_nequal3; break;
+ case nir_op_bany_inequal4: alu->op = nir_op_fany_nequal4; break;
+
+ case nir_op_bcsel: alu->op = nir
