[meta-xilinx] Device Tree mismatch in xilinx-v2017.3 (meta-xilinx vs meta-xilinx-tools)

[Kleve, Jesse R]

I’m building off of the Xilinx-v2017.3 branch. When I go to boot with the 
device tree and kernel I get a mismatch in zynqmp_plat_init for the power 
management API.

Kernel panic – not syncing: zynqmp_plat_init power management API version 
error. Expected: v0.3 – Found: v1.0

In Xilinx-v2017.3, the kernel is 4.9 which expects v0.3 yet meta-xilinx-tools 
is producing a device tree set for v1.0. Am I misconfiguring something here?

Thanks,
Jesse
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Re: [meta-xilinx] PicoZed 7030 again

[Thomas Goodwin]

The device tree in U-Boot and U-Boot-XLNX (which is different than the one
from that recipe) do not have the SD card set as the boot device (mmc0
points to sdhci1 vs. sdhci0) and then the block for sdhci0 needs to be
enabled (status = "okay") vs. disabling sdhci1.  I recall someone has put a
patch into the U-Boot mainline, but that's the gist.  The built-in one
seems to be eyeing if you were planning to boot from eMMC.

As I recall, the device tree is also missing a "chosen" block, like this:

chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
}

However I do not recall if that block is required or not.

Cheers,

Thomas

On Wed, Oct 3, 2018 at 2:35 PM Artjom Rjabov  wrote:

> For some reason, I can't boot the picozed-zynq7 image from an SD card on
> PicoZed+FMC Carrier Card Gen2. I worked with Zedboard previously and
> everything worked perfectly.
> I've read all the threads about Picozed here but didn't find anything
> helpful. Devicetree in "meta-xilinx-bsp/recipes-bsp/device-tree" looks fine
> at the moment.
> It has a console definition (chosen/stdout-path) in it and serial0 is
> enabled. I decompiled it to make sure that everything is there.
>
> Here what I did:
>
> 1. Compiled everything without my own recipes and bbappends. Uploaded
> boot.bin, uImage, picozed-zynq7.dtb, uEnv.txt, u-boot.img, and rootfs on
> the SD card and tried to boot.
> It didn't work. The D10 and D11 PS LEDs on the FMC carrier were blinking
> in sync indefinitely.
>
> 2. I generated my own ps7_init_gpl files in vivado (SD0 and SD1 enabled,
> UART1 on MIO48 and 49), created my own platform-init.bbappend file for
> replacing the init files. Enabled SD0 in the device tree. Bitbaked
> everything. Same result.
>
> 3. FSBL approach that worked with Zedboard. I copied u-boot.elf from the
> generated image folder, created FSBL in SDK and generated BOOT.bin with
> these two files. The result was different. The D10 and D11 blinked only
> once, but still no console output over the UART. It looks like it doesn't
> even get to the device tree because the result is the same even if there is
> no dtb file on the SD card.
>
> What am I missing here?
> --
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[meta-xilinx] PicoZed 7030 again

[Artjom Rjabov]

For some reason, I can't boot the picozed-zynq7 image from an SD card on 
PicoZed+FMC Carrier Card Gen2. I worked with Zedboard previously and everything 
worked perfectly.
I've read all the threads about Picozed here but didn't find anything helpful. 
Devicetree in "meta-xilinx-bsp/recipes-bsp/device-tree" looks fine at the 
moment.
It has a console definition (chosen/stdout-path) in it and serial0 is enabled. 
I decompiled it to make sure that everything is there.

Here what I did:

1. Compiled everything without my own recipes and bbappends. Uploaded  
boot.bin, uImage, picozed-zynq7.dtb, uEnv.txt, u-boot.img, and rootfs on the SD 
card and tried to boot.
It didn't work. The D10 and D11 PS LEDs on the FMC carrier were blinking in 
sync indefinitely.

2. I generated my own ps7_init_gpl files in vivado (SD0 and SD1 enabled, UART1 
on MIO48 and 49), created my own platform-init.bbappend file for replacing the 
init files. Enabled SD0 in the device tree. Bitbaked everything. Same result.

3. FSBL approach that worked with Zedboard. I copied u-boot.elf from the 
generated image folder, created FSBL in SDK and generated BOOT.bin with these 
two files. The result was different. The D10 and D11 blinked only once, but 
still no console output over the UART. It looks like it doesn't even get to the 
device tree because the result is the same even if there is no dtb file on the 
SD card.

What am I missing here?
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Re: [meta-xilinx] Ultra96 UART

[Manjukumar Harthikote Matha]

Hi Simon,

> -Original Message-
> From: meta-xilinx-boun...@yoctoproject.org [mailto:meta-xilinx-
> boun...@yoctoproject.org] On Behalf Of simon.g...@doulos.com
> Sent: Wednesday, October 03, 2018 1:19 AM
> To: tom.cur...@avnet.com
> Cc: meta-xil...@lists.yoctoproject.org
> Subject: Re: [meta-xilinx] Ultra96 UART
> 
> Hi Tom
> 
> 
> Thanks for the extra information. I was able to regenerate the HDF with (I 
> think) the
> appropriate changes in the PSU UART configuration (just changing UART1 to
> MIO[0..1], is that all that is required?). I then (eventually) managed to get 
> everything
> to build in Yocto using the new HDF by setting the HDF_PATH appropriately in 
> my
> local.conf.
> 
> 
> With the new boot.bin etc. I see the FSBL output now (a step forward) but 
> nothing
> more - I guess U-Boot is not loading properly from the boot.bin?
> 

Are you using rel-v2018.2 branches?

Is this used while building u-boot? 
https://github.com/Xilinx/meta-xilinx-tools/blob/rel-v2018.2/recipes-bsp/u-boot/u-boot-xlnx_%25.bbappend

> 
> I am slightly confused as to why this is necessary. Manju from Xilinx said 
> they have
> verified that it works but you are saying that the HDF provided by default in 
> meta-
> xilinx* is incorrect - have I missed something?
> 
> 

We use the mezzanine card for the UART, hence the need for EMIO. 

Thanks,
Manju

> Thanks in advance
> Simon
> 
> 
> ---
> Date: Fri, 28 Sep 2018 21:24:27 +
> From: "Curran, Tom (EM)"   >
> To: "meta-xil...@lists.yoctoproject.org 
> 
> "
>   >
> Subject: Re: [meta-xilinx] Ultra96 UART
> Message-ID:
> <0434c4d44760fb40aafb554c7c241caf10796...@cmx039usmb.avnet.com
>  COM> >
> Content-Type: text/plain; charset="utf-8"
> 
> Yes, the user STDIN/STDOUT UART is psu_uart_1 in the image that gets built via
> meta-xilinx, etc., BUT the UART is mapped out through EMIO to the low speed
> expansion header:
> 
> #HD_GPIO_5 on FPGA / Connector pin 13 / UART1_rxd set_property PACKAGE_PIN
> G5 [get_ports UART1_rxd]
> #HD_GPIO_4 on FPGA / Connector pin 11 / UART1_txd set_property PACKAGE_PIN
> F6 [get_ports UART1_txd]
> 
> You can get a look at the hardware platform by installing the posted 
> PetaLinux BSP
> for the Ultra96 board:
> https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-
> ultra96-reva-v2018.2-final.bsp
>  ultra96-reva-v2018.2-final.bsp>
> 
> See Xilinx UG1144 for the BSP install instructions:
> http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1144-
> petalinux-tools-reference-guide.pdf
>  -petalinux-tools-reference-guide.pdf>
> 
> To use the Avnet USB UART/JTAG adapter the UART needs to be changed from EMIO
> to MIO[0:1] in the PSU config of the Vivado design.  Then it should be 
> possible to
> regenerate the hdf file and drop it in the correct folder and run a new 
> bitbake build.
> 
> --Tom
> 
> 
> From: meta-xilinx-boun...@yoctoproject.org  boun...@yoctoproject.org>  [mailto:meta-xilinx-boun...@yoctoproject.org
>  ] On Behalf Of Manjukumar
> Harthikote Matha
> Sent: Wednesday, September 26, 2018 11:17 AM
> To: Tomas Thoresen mailto:tom...@xilinx.com> >;
> simon.g...@doulos.com  ; meta-
> xil...@lists.yoctoproject.org 
> Subject: Re: [meta-xilinx] Ultra96 UART
> 
> Hi,
> 
> Yes it should be psu_uart_1. Please use rel-v2018.3 branches from 
> github.com/xilinx
> tree, we have verified and it works.
> https://github.com/Xilinx/meta-xilinx-tools/blob/rel-
> v2018.2/classes/xsctyaml.bbclass#L15-L16 
>  tools/blob/rel-v2018.2/classes/xsctyaml.bbclass#L15-L16>
> 
> You can use repo command to get the release branches
> http://www.wiki.xilinx.com/How%20to%20build%20images%20through%20yocto
> 
> 
> Thanks,
> Manju
> 
> From: meta-xilinx-boun...@yoctoproject.org  boun...@yoctoproject.org>   > [mailto:meta-xilinx-
> boun...@yoctoproject.org  ] On
> Behalf Of Tomas Thoresen
> Sent: Wednesday, September 26, 2018 2:04 AM
> To: simon.g...@doulos.com 
>  >; meta-
> xil...@lists.yoctoproject.org 
>  xil...@lists.yoctoproject.org> >
> 

Re: [meta-xilinx] Ultra96 UART

[simon . goda]

Hi Tom

Thanks for the extra information. I was able to regenerate the HDF with (I 
think) the appropriate changes in the PSU UART configuration (just changing 
UART1 to MIO[0..1], is that all that is required?). I then (eventually) managed 
to get everything to build in Yocto using the new HDF by setting the HDF_PATH 
appropriately in my local.conf.

With the new boot.bin etc. I see the FSBL output now (a step forward) but 
nothing more - I guess U-Boot is not loading properly from the boot.bin? 

I am slightly confused as to why this is necessary. Manju from Xilinx said they 
have verified that it works but you are saying that the HDF provided by default 
in meta-xilinx* is incorrect - have I missed something?

Thanks in advance
Simon

---
Date: Fri, 28 Sep 2018 21:24:27 +
From: "Curran, Tom (EM)" 
To: "meta-xil...@lists.yoctoproject.org"

Subject: Re: [meta-xilinx] Ultra96 UART
Message-ID:
<0434c4d44760fb40aafb554c7c241caf10796...@cmx039usmb.avnet.com>
Content-Type: text/plain; charset="utf-8"

Yes, the user STDIN/STDOUT UART is psu_uart_1 in the image that gets built via 
meta-xilinx, etc., BUT the UART is mapped out through EMIO to the low speed 
expansion header:

#HD_GPIO_5 on FPGA / Connector pin 13 / UART1_rxd
set_property PACKAGE_PIN G5 [get_ports UART1_rxd]
#HD_GPIO_4 on FPGA / Connector pin 11 / UART1_txd
set_property PACKAGE_PIN F6 [get_ports UART1_txd]

You can get a look at the hardware platform by installing the posted PetaLinux 
BSP for the Ultra96 board:
https://www.xilinx.com/member/forms/download/xef.html?filename=xilinx-ultra96-reva-v2018.2-final.bsp

See Xilinx UG1144 for the BSP install instructions:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug1144-petalinux-tools-reference-guide.pdf

To use the Avnet USB UART/JTAG adapter the UART needs to be changed from EMIO 
to MIO[0:1] in the PSU config of the Vivado design.  Then it should be possible 
to regenerate the hdf file and drop it in the correct folder and run a new 
bitbake build.

--Tom


From: meta-xilinx-boun...@yoctoproject.org 
[mailto:meta-xilinx-boun...@yoctoproject.org] On Behalf Of Manjukumar 
Harthikote Matha
Sent: Wednesday, September 26, 2018 11:17 AM
To: Tomas Thoresen ; simon.g...@doulos.com; 
meta-xil...@lists.yoctoproject.org
Subject: Re: [meta-xilinx] Ultra96 UART

Hi,

Yes it should be psu_uart_1. Please use rel-v2018.3 branches from 
github.com/xilinx tree, we have verified and it works.
https://github.com/Xilinx/meta-xilinx-tools/blob/rel-v2018.2/classes/xsctyaml.bbclass#L15-L16

You can use repo command to get the release branches
http://www.wiki.xilinx.com/How%20to%20build%20images%20through%20yocto

Thanks,
Manju

From: 
meta-xilinx-boun...@yoctoproject.org
 [mailto:meta-xilinx-boun...@yoctoproject.org] On Behalf Of Tomas Thoresen
Sent: Wednesday, September 26, 2018 2:04 AM
To: simon.g...@doulos.com; 
meta-xil...@lists.yoctoproject.org
Subject: Re: [meta-xilinx] Ultra96 UART

Hi Simon,

If I?m not mistaking, I believe it uses uart1 instead of uart0...

So, something like this:

YAML_BSP_CONFIG[stdin]="set,psu_uart_1"
YAML_BSP_CONFIG[stdout]="set,psu_uart_1"


Hope this helps.

Cheers,

Tomas

From: 
meta-xilinx-boun...@yoctoproject.org
 [mailto:meta-xilinx-boun...@yoctoproject.org] On Behalf Of 
simon.g...@doulos.com
Sent: 26 September 2018 09:48
To: 
meta-xil...@lists.yoctoproject.org
Subject: [meta-xilinx] Ultra96 UART

Hi

I am trying to get a meta-xilinx/meta-xilinx-tools build (using versions Rocko 
& rel-v2018.2) to boot on an Ultra96 board. Following the various bits of 
guidance from this list I have successfully built, and have all the files I 
would expect in tmp/deploy/images/.

The files do not seem to boot - or at least I don't see anything on the serial 
(via the Avnet serial to USB dongle for the Ultra96).

I have read on another forum 
(http://zedboard.org/content/j6-serial-port-appears-not-be-working) that the 
default config of the FSBL for the Ultra96 board does not configure the UART 
properly and indeed using a 'hacked' boot.bin which has been 'fixed' from that 
forum entry I can boot the board and see output on the UART.

My questions are:

- Has anyone else successfully booted an Ultra96 using 
meta-xilinx/meta-xilinx-tools?
- If so, did you see anything on the UART? Were any changes made to the FSBL 
configuration to achieve this?

Any comments or guidance gratefully received!

Thanks & regards
Simon Goda


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