[Qemu-devel] [RFC qom-cpu v2 04/28] target-i386: Update X86CPU to QOM realizefn
Adapt the signature of x86_cpu_realize(), hook up to
DeviceClass::realize and set realized = true in cpu_x86_init().
The QOM realizefn cannot depend on errp being non-NULL as in
cpu_x86_init(), so use a local Error to preserve error handling behavior
on APIC initialization errors.
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Igor Mammedov imamm...@redhat.com
Cc: Eduardo Habkost ehabk...@redhat.com
---
target-i386/cpu-qom.h |5 ++---
target-i386/cpu.c | 19 +++
target-i386/helper.c |2 +-
3 Dateien geändert, 18 Zeilen hinzugefügt(+), 8 Zeilen entfernt(-)
diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
index 332916a..48e6b54 100644
--- a/target-i386/cpu-qom.h
+++ b/target-i386/cpu-qom.h
@@ -39,6 +39,7 @@
/**
* X86CPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An x86 CPU model or family.
@@ -48,6 +49,7 @@ typedef struct X86CPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} X86CPUClass;
@@ -72,8 +74,5 @@ static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
-/* TODO Drop once ObjectClass::realize is available */
-void x86_cpu_realize(Object *obj, Error **errp);
-
#endif
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 333745b..c988ac5 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2140,10 +2140,14 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
}
#endif
-void x86_cpu_realize(Object *obj, Error **errp)
+static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
{
-X86CPU *cpu = X86_CPU(obj);
+X86CPU *cpu = X86_CPU(dev);
+X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
CPUX86State *env = cpu-env;
+#ifndef CONFIG_USER_ONLY
+Error *local_err = NULL;
+#endif
if (env-cpuid_7_0_ebx_features env-cpuid_level 7) {
env-cpuid_level = 7;
@@ -2185,8 +2189,9 @@ void x86_cpu_realize(Object *obj, Error **errp)
qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu-env.cpuid_features CPUID_APIC || smp_cpus 1) {
-x86_cpu_apic_init(cpu, errp);
-if (error_is_set(errp)) {
+x86_cpu_apic_init(cpu, local_err);
+if (local_err != NULL) {
+error_propagate(errp, local_err);
return;
}
}
@@ -2195,6 +2200,8 @@ void x86_cpu_realize(Object *obj, Error **errp)
mce_init(cpu);
qemu_init_vcpu(cpu-env);
cpu_reset(CPU(cpu));
+
+xcc-parent_realize(dev, errp);
}
static void x86_cpu_initfn(Object *obj)
@@ -2247,6 +2254,10 @@ static void x86_cpu_common_class_init(ObjectClass *oc,
void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+xcc-parent_realize = dc-realize;
+dc-realize = x86_cpu_realizefn;
xcc-parent_reset = cc-reset;
cc-reset = x86_cpu_reset;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 547c25e..bf43d6a 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1280,7 +1280,7 @@ X86CPU *cpu_x86_init(const char *cpu_model)
return NULL;
}
-x86_cpu_realize(OBJECT(cpu), error);
+object_property_set_bool(OBJECT(cpu), true, realized, error);
if (error) {
error_free(error);
object_delete(OBJECT(cpu));
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 06/28] target-ppc: Update PowerPCCPU to QOM realizefn
Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set
realized = true in cpu_ppc_init().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-ppc/cpu-qom.h|2 ++
target-ppc/translate_init.c | 12 +---
2 Dateien geändert, 11 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)
diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h
index b338f8f..2b82cdb 100644
--- a/target-ppc/cpu-qom.h
+++ b/target-ppc/cpu-qom.h
@@ -40,6 +40,7 @@
/**
* PowerPCCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A PowerPC CPU model.
@@ -49,6 +50,7 @@ typedef struct PowerPCCPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
/* TODO inline fields here */
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 2d78529..63ba4a5 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10029,9 +10029,9 @@ static int ppc_fixup_cpu(PowerPCCPU *cpu)
return 0;
}
-static void ppc_cpu_realize(Object *obj, Error **errp)
+static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
{
-PowerPCCPU *cpu = POWERPC_CPU(obj);
+PowerPCCPU *cpu = POWERPC_CPU(dev);
CPUPPCState *env = cpu-env;
PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
ppc_def_t *def = pcc-info;
@@ -10071,6 +10071,8 @@ static void ppc_cpu_realize(Object *obj, Error **errp)
qemu_init_vcpu(env);
+pcc-parent_realize(dev, errp);
+
#if defined(PPC_DUMP_CPU)
{
const char *mmu_model, *excp_model, *bus_model;
@@ -10342,7 +10344,7 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
env-cpu_model_str = cpu_model;
-ppc_cpu_realize(OBJECT(cpu), err);
+object_property_set_bool(OBJECT(cpu), true, realized, err);
if (err != NULL) {
fprintf(stderr, %s\n, error_get_pretty(err));
error_free(err);
@@ -10563,6 +10565,10 @@ static void ppc_cpu_class_init(ObjectClass *oc, void
*data)
{
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+pcc-parent_realize = dc-realize;
+dc-realize = ppc_cpu_realizefn;
pcc-parent_reset = cc-reset;
cc-reset = ppc_cpu_reset;
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 07/28] target-cris: Introduce QOM realizefn for CRISCPU
Introduce realizefn and set realized = true from cpu_cris_init().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-cris/cpu-qom.h |2 ++
target-cris/cpu.c | 15 +++
target-cris/translate.c |3 +--
3 Dateien geändert, 18 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h
index 41ab9b2..7ad8398 100644
--- a/target-cris/cpu-qom.h
+++ b/target-cris/cpu-qom.h
@@ -33,6 +33,7 @@
/**
* CRISCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A CRIS CPU model.
@@ -42,6 +43,7 @@ typedef struct CRISCPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} CRISCPUClass;
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 3f64a57..34c4f75 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -55,6 +55,17 @@ static void cris_cpu_reset(CPUState *s)
#endif
}
+static void cris_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+CRISCPU *cpu = CRIS_CPU(dev);
+CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev);
+
+cpu_reset(CPU(cpu));
+qemu_init_vcpu(cpu-env);
+
+ccc-parent_realize(dev, errp);
+}
+
static void cris_cpu_initfn(Object *obj)
{
CRISCPU *cpu = CRIS_CPU(obj);
@@ -65,9 +76,13 @@ static void cris_cpu_initfn(Object *obj)
static void cris_cpu_class_init(ObjectClass *oc, void *data)
{
+DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
CRISCPUClass *ccc = CRIS_CPU_CLASS(oc);
+ccc-parent_realize = dc-realize;
+dc-realize = cris_cpu_realizefn;
+
ccc-parent_reset = cc-reset;
cc-reset = cris_cpu_reset;
}
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 09e6011..25ff490 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3558,8 +3558,7 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
env-pregs[PR_VR] = vr_by_name(cpu_model);
-cpu_reset(CPU(cpu));
-qemu_init_vcpu(env);
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
if (tcg_initialized) {
return cpu;
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 18/28] target-cris: Move TCG initialization to CRISCPU initfn
Split out TCG initialization from cpu_cris_init(). Avoid CPUCRISState
dependency for v10-specific initialization and for non-v10 by inlining
the decision into the initfn as well.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-cris/cpu.c | 10 ++
target-cris/cpu.h |3 +++
target-cris/translate.c | 19 +--
target-cris/translate_v10.c |5 +
4 Dateien geändert, 19 Zeilen hinzugefügt(+), 18 Zeilen entfernt(-)
diff --git a/target-cris/cpu.c b/target-cris/cpu.c
index 34c4f75..fedf641 100644
--- a/target-cris/cpu.c
+++ b/target-cris/cpu.c
@@ -70,8 +70,18 @@ static void cris_cpu_initfn(Object *obj)
{
CRISCPU *cpu = CRIS_CPU(obj);
CPUCRISState *env = cpu-env;
+static bool tcg_initialized;
cpu_exec_init(env);
+
+if (tcg_enabled() !tcg_initialized) {
+tcg_initialized = true;
+if (env-pregs[PR_VR] 32) {
+cris_initialize_crisv10_tcg();
+} else {
+cris_initialize_tcg();
+}
+}
}
static void cris_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 257cb52..ebf2d40 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -182,6 +182,9 @@ void do_interrupt(CPUCRISState *env);
int cpu_cris_signal_handler(int host_signum, void *pinfo,
void *puc);
+void cris_initialize_tcg(void);
+void cris_initialize_crisv10_tcg(void);
+
enum {
CC_OP_DYNAMIC, /* Use env-cc_op */
CC_OP_FLAGS,
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 25ff490..25a43fa 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3550,8 +3550,6 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
{
CRISCPU *cpu;
CPUCRISState *env;
-static int tcg_initialized = 0;
-int i;
cpu = CRIS_CPU(object_new(TYPE_CRIS_CPU));
env = cpu-env;
@@ -3560,21 +3558,16 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
-if (tcg_initialized) {
-return cpu;
-}
+return cpu;
+}
-tcg_initialized = 1;
+void cris_initialize_tcg(void)
+{
+int i;
#define GEN_HELPER 2
#include helper.h
-if (env-pregs[PR_VR] 32) {
-cpu_crisv10_init(env);
-return cpu;
-}
-
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, env);
cc_x = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUCRISState, cc_x), cc_x);
@@ -3614,8 +3607,6 @@ CRISCPU *cpu_cris_init(const char *cpu_model)
offsetof(CPUCRISState, pregs[i]),
pregnames[i]);
}
-
-return cpu;
}
void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-cris/translate_v10.c b/target-cris/translate_v10.c
index d2cca89..d6ef084 100644
--- a/target-cris/translate_v10.c
+++ b/target-cris/translate_v10.c
@@ -1257,7 +1257,7 @@ static unsigned int crisv10_decoder(CPUCRISState *env,
DisasContext *dc)
return insn_len;
}
-static CPUCRISState *cpu_crisv10_init (CPUCRISState *env)
+void cris_initialize_crisv10_tcg(void)
{
int i;
@@ -1300,7 +1300,4 @@ static CPUCRISState *cpu_crisv10_init (CPUCRISState *env)
offsetof(CPUCRISState, pregs[i]),
pregnames_v10[i]);
}
-
- return env;
}
-
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 24/28] target-s390x: Move TCG initialization to S390CPU initfn
Ensures that a QOM-created S390CPU is usable.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-s390x/cpu.c|6 ++
target-s390x/helper.c |7 ---
2 Dateien geändert, 6 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-)
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 60f71fc..109777e 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -112,6 +112,7 @@ static void s390_cpu_initfn(Object *obj)
{
S390CPU *cpu = S390_CPU(obj);
CPUS390XState *env = cpu-env;
+static bool inited;
static int cpu_num = 0;
#if !defined(CONFIG_USER_ONLY)
struct tm tm;
@@ -133,6 +134,11 @@ static void s390_cpu_initfn(Object *obj)
#endif
env-cpu_num = cpu_num++;
env-ext_index = -1;
+
+if (tcg_enabled() !inited) {
+inited = true;
+s390x_translate_init();
+}
}
static void s390_cpu_finalize(Object *obj)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 45020b2..bad0683 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -74,16 +74,9 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
{
S390CPU *cpu;
CPUS390XState *env;
-static int inited;
cpu = S390_CPU(object_new(TYPE_S390_CPU));
env = cpu-env;
-
-if (tcg_enabled() !inited) {
-inited = 1;
-s390x_translate_init();
-}
-
env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 08/28] target-lm32: Introduce QOM realizefn for LM32CPU
Introduce a realizefn and set realized = true in cpu_lm32_init().
Also move cpu_reset() call from initfn to realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-lm32/cpu-qom.h |2 ++
target-lm32/cpu.c | 18 --
target-lm32/helper.c |4 ++--
3 Dateien geändert, 20 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)
diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h
index 400cdbd..d7525b3 100644
--- a/target-lm32/cpu-qom.h
+++ b/target-lm32/cpu-qom.h
@@ -34,6 +34,7 @@
/**
* LM32CPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A LatticeMico32 CPU model.
@@ -43,6 +44,7 @@ typedef struct LM32CPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} LM32CPUClass;
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c
index eca2dca..6a84f51 100644
--- a/target-lm32/cpu.c
+++ b/target-lm32/cpu.c
@@ -42,6 +42,18 @@ static void lm32_cpu_reset(CPUState *s)
memset(env, 0, offsetof(CPULM32State, breakpoints));
}
+static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+LM32CPU *cpu = LM32_CPU(dev);
+LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
+
+cpu_reset(CPU(cpu));
+
+qemu_init_vcpu(cpu-env);
+
+lcc-parent_realize(dev, errp);
+}
+
static void lm32_cpu_initfn(Object *obj)
{
LM32CPU *cpu = LM32_CPU(obj);
@@ -50,14 +62,16 @@ static void lm32_cpu_initfn(Object *obj)
cpu_exec_init(env);
env-flags = 0;
-
-cpu_reset(CPU(cpu));
}
static void lm32_cpu_class_init(ObjectClass *oc, void *data)
{
LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+lcc-parent_realize = dc-realize;
+dc-realize = lm32_cpu_realizefn;
lcc-parent_reset = cc-reset;
cc-reset = lm32_cpu_reset;
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index d76ea3f..a6691ad 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -212,13 +212,13 @@ LM32CPU *cpu_lm32_init(const char *cpu_model)
env-num_wps = def-num_watchpoints;
env-cfg = cfg_by_def(def);
-qemu_init_vcpu(env);
-
if (tcg_enabled() !tcg_initialized) {
tcg_initialized = 1;
lm32_translate_init();
}
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
return cpu;
}
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 12/28] target-s390x: Introduce QOM realizefn for S390CPU
Introduce realizefn and set realized = true in cpu_s390x_init().
Defer CPU reset from initfn to realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-s390x/cpu-qom.h |2 ++
target-s390x/cpu.c | 17 +++--
target-s390x/helper.c |4 +++-
3 Dateien geändert, 20 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-)
diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h
index d54e4a2..237184f 100644
--- a/target-s390x/cpu-qom.h
+++ b/target-s390x/cpu-qom.h
@@ -34,6 +34,7 @@
/**
* S390CPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An S/390 CPU model.
@@ -43,6 +44,7 @@ typedef struct S390CPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} S390CPUClass;
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c
index 0b68db8..60f71fc 100644
--- a/target-s390x/cpu.c
+++ b/target-s390x/cpu.c
@@ -97,6 +97,17 @@ static void s390_cpu_machine_reset_cb(void *opaque)
}
#endif
+static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+S390CPU *cpu = S390_CPU(dev);
+S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
+
+qemu_init_vcpu(cpu-env);
+cpu_reset(CPU(cpu));
+
+scc-parent_realize(dev, errp);
+}
+
static void s390_cpu_initfn(Object *obj)
{
S390CPU *cpu = S390_CPU(obj);
@@ -122,8 +133,6 @@ static void s390_cpu_initfn(Object *obj)
#endif
env-cpu_num = cpu_num++;
env-ext_index = -1;
-
-cpu_reset(CPU(cpu));
}
static void s390_cpu_finalize(Object *obj)
@@ -139,6 +148,10 @@ static void s390_cpu_class_init(ObjectClass *oc, void
*data)
{
S390CPUClass *scc = S390_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(scc);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+scc-parent_realize = dc-realize;
+dc-realize = s390_cpu_realizefn;
scc-parent_reset = cc-reset;
cc-reset = s390_cpu_reset;
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 9a132e6..45020b2 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -85,7 +85,9 @@ S390CPU *cpu_s390x_init(const char *cpu_model)
}
env-cpu_model_str = cpu_model;
-qemu_init_vcpu(env);
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
return cpu;
}
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 16/28] target-xtensa: Introduce QOM realizefn for XtensaCPU
Introduce realizefn and set realized = true in cpu_xtensa_init().
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-xtensa/cpu-qom.h |2 ++
target-xtensa/cpu.c | 14 ++
target-xtensa/helper.c |4 +++-
3 Dateien geändert, 19 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h
index e344a9a..270de16 100644
--- a/target-xtensa/cpu-qom.h
+++ b/target-xtensa/cpu-qom.h
@@ -43,6 +43,7 @@
/**
* XtensaCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An Xtensa CPU model.
@@ -52,6 +53,7 @@ typedef struct XtensaCPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} XtensaCPUClass;
diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c
index 035b07c..ec99ae9 100644
--- a/target-xtensa/cpu.c
+++ b/target-xtensa/cpu.c
@@ -56,6 +56,16 @@ static void xtensa_cpu_reset(CPUState *s)
reset_mmu(env);
}
+static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+XtensaCPU *cpu = XTENSA_CPU(dev);
+XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
+
+qemu_init_vcpu(cpu-env);
+
+xcc-parent_realize(dev, errp);
+}
+
static void xtensa_cpu_initfn(Object *obj)
{
XtensaCPU *cpu = XTENSA_CPU(obj);
@@ -66,9 +76,13 @@ static void xtensa_cpu_initfn(Object *obj)
static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
{
+DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
+xcc-parent_realize = dc-realize;
+dc-realize = xtensa_cpu_realizefn;
+
xcc-parent_reset = cc-reset;
cc-reset = xtensa_cpu_reset;
}
diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c
index 94c03a1..14bcc7e 100644
--- a/target-xtensa/helper.c
+++ b/target-xtensa/helper.c
@@ -104,7 +104,9 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model)
}
xtensa_irq_init(env);
-qemu_init_vcpu(env);
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
return cpu;
}
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 22/28] target-mips: Move TCG initialization to MIPSCPU initfn
Make mips_tcg_init() non-static and add tcg_enabled() check to suppress
it for qtest.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-mips/cpu.c |4
target-mips/cpu.h |1 +
target-mips/translate.c |3 +--
3 Dateien geändert, 6 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)
diff --git a/target-mips/cpu.c b/target-mips/cpu.c
index 18895da..09d6172 100644
--- a/target-mips/cpu.c
+++ b/target-mips/cpu.c
@@ -59,6 +59,10 @@ static void mips_cpu_initfn(Object *obj)
CPUMIPSState *env = cpu-env;
cpu_exec_init(env);
+
+if (tcg_enabled()) {
+mips_tcg_init();
+}
}
static void mips_cpu_class_init(ObjectClass *c, void *data)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5963d62..0e198b1 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -629,6 +629,7 @@ enum {
#define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
int cpu_mips_exec(CPUMIPSState *s);
+void mips_tcg_init(void);
MIPSCPU *cpu_mips_init(const char *cpu_model);
int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9ea9354..373cfa7 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15791,7 +15791,7 @@ void cpu_dump_state (CPUMIPSState *env, FILE *f,
fprintf_function cpu_fprintf,
#endif
}
-static void mips_tcg_init(void)
+void mips_tcg_init(void)
{
int i;
static int inited;
@@ -15870,7 +15870,6 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
#endif
fpu_init(env, def);
mvp_init(env, def);
-mips_tcg_init();
object_property_set_bool(OBJECT(cpu), true, realized, NULL);
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 20/28] target-m68k: Move TCG initialization to M68kCPU initfn
Add a tcg_enabled() check to suppress it for qtest.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-m68k/cpu.c|6 ++
target-m68k/helper.c |7 ---
2 Dateien geändert, 6 Zeilen hinzugefügt(+), 7 Zeilen entfernt(-)
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index f6720ca..bbeae28 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -136,8 +136,14 @@ static void m68k_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
CPUM68KState *env = cpu-env;
+static bool inited;
cpu_exec_init(env);
+
+if (tcg_enabled() !inited) {
+inited = true;
+m68k_tcg_init();
+}
}
static void m68k_cpu_class_init(ObjectClass *c, void *data)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index f2d3059..920dfa9 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -97,19 +97,12 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
{
M68kCPU *cpu;
CPUM68KState *env;
-static int inited;
if (object_class_by_name(cpu_model) == NULL) {
return NULL;
}
cpu = M68K_CPU(object_new(cpu_model));
env = cpu-env;
-
-if (!inited) {
-inited = 1;
-m68k_tcg_init();
-}
-
env-cpu_model_str = cpu_model;
register_m68k_insns(env);
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 15/28] target-unicore32: Introduce QOM realizefn for UniCore32CPU
Introduce a realizefn and set realized = true in uc32_cpu_init().
Acked-by: Guan Xuetao g...@mprc.pku.edu.cn
[AF: Invoke the parent's realizefn]
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-unicore32/cpu-qom.h |3 +++
target-unicore32/cpu.c | 20
target-unicore32/helper.c |3 ++-
3 Dateien geändert, 25 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h
index fe40b2d..625c614 100644
--- a/target-unicore32/cpu-qom.h
+++ b/target-unicore32/cpu-qom.h
@@ -25,6 +25,7 @@
/**
* UniCore32CPUClass:
+ * @parent_realize: The parent class' realize handler.
*
* A UniCore32 CPU model.
*/
@@ -32,6 +33,8 @@ typedef struct UniCore32CPUClass {
/* private */
CPUClass parent_class;
/* public */
+
+DeviceRealize parent_realize;
} UniCore32CPUClass;
/**
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 884c101..bf33326 100644
--- a/target-unicore32/cpu.c
+++ b/target-unicore32/cpu.c
@@ -61,6 +61,16 @@ static const UniCore32CPUInfo uc32_cpus[] = {
{ .name = any,.instance_init = uc32_any_cpu_initfn },
};
+static void uc32_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+UniCore32CPU *cpu = UNICORE32_CPU(dev);
+UniCore32CPUClass *ucc = UNICORE32_CPU_GET_CLASS(dev);
+
+qemu_init_vcpu(cpu-env);
+
+ucc-parent_realize(dev, errp);
+}
+
static void uc32_cpu_initfn(Object *obj)
{
UniCore32CPU *cpu = UNICORE32_CPU(obj);
@@ -80,6 +90,15 @@ static void uc32_cpu_initfn(Object *obj)
tlb_flush(env, 1);
}
+static void uc32_cpu_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+UniCore32CPUClass *ucc = UNICORE32_CPU_CLASS(oc);
+
+ucc-parent_realize = dc-realize;
+dc-realize = uc32_cpu_realizefn;
+}
+
static void uc32_register_cpu_type(const UniCore32CPUInfo *info)
{
TypeInfo type_info = {
@@ -98,6 +117,7 @@ static const TypeInfo uc32_cpu_type_info = {
.instance_init = uc32_cpu_initfn,
.abstract = true,
.class_size = sizeof(UniCore32CPUClass),
+.class_init = uc32_cpu_class_init,
};
static void uc32_cpu_register_types(void)
diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c
index 5359538..173579a 100644
--- a/target-unicore32/helper.c
+++ b/target-unicore32/helper.c
@@ -42,7 +42,8 @@ CPUUniCore32State *uc32_cpu_init(const char *cpu_model)
uc32_translate_init();
}
-qemu_init_vcpu(env);
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
return env;
}
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 09/28] target-m68k: Introduce QOM realizefn for M68kCPU
Introduce realizefn and set realized = true in cpu_m68k_init().
Split off GDB registration to a new m68k_cpu_init_gdb() so that it can
be called from the realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-m68k/cpu-qom.h |2 ++
target-m68k/cpu.c | 17 +
target-m68k/cpu.h |1 +
target-m68k/helper.c | 14 ++
4 Dateien geändert, 30 Zeilen hinzugefügt(+), 4 Zeilen entfernt(-)
diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h
index 170daa7..20e5684 100644
--- a/target-m68k/cpu-qom.h
+++ b/target-m68k/cpu-qom.h
@@ -33,6 +33,7 @@
/**
* M68kCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A Motorola 68k CPU model.
@@ -42,6 +43,7 @@ typedef struct M68kCPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} M68kCPUClass;
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index ce89674..f6720ca 100644
--- a/target-m68k/cpu.c
+++ b/target-m68k/cpu.c
@@ -119,6 +119,19 @@ static const M68kCPUInfo m68k_cpus[] = {
{ .name = any, .instance_init = any_cpu_initfn },
};
+static void m68k_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+M68kCPU *cpu = M68K_CPU(dev);
+M68kCPUClass *mcc = M68K_CPU_GET_CLASS(dev);
+
+m68k_cpu_init_gdb(cpu);
+
+cpu_reset(CPU(cpu));
+qemu_init_vcpu(cpu-env);
+
+mcc-parent_realize(dev, errp);
+}
+
static void m68k_cpu_initfn(Object *obj)
{
M68kCPU *cpu = M68K_CPU(obj);
@@ -131,6 +144,10 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
{
M68kCPUClass *mcc = M68K_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
+DeviceClass *dc = DEVICE_CLASS(c);
+
+mcc-parent_realize = dc-realize;
+dc-realize = m68k_cpu_realizefn;
mcc-parent_reset = cc-reset;
cc-reset = m68k_cpu_reset;
diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
index adaf56c..94937c4 100644
--- a/target-m68k/cpu.h
+++ b/target-m68k/cpu.h
@@ -116,6 +116,7 @@ typedef struct CPUM68KState {
#include cpu-qom.h
void m68k_tcg_init(void);
+void m68k_cpu_init_gdb(M68kCPU *cpu);
CPUM68KState *cpu_m68k_init(const char *cpu_model);
int cpu_m68k_exec(CPUM68KState *s);
void do_interrupt(CPUM68KState *env1);
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 097fc78..f2d3059 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -113,15 +113,21 @@ CPUM68KState *cpu_m68k_init(const char *cpu_model)
env-cpu_model_str = cpu_model;
register_m68k_insns(env);
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
+return env;
+}
+
+void m68k_cpu_init_gdb(M68kCPU *cpu)
+{
+CPUM68KState *env = cpu-env;
+
if (m68k_feature(env, M68K_FEATURE_CF_FPU)) {
gdb_register_coprocessor(env, fpu_gdb_get_reg, fpu_gdb_set_reg,
11, cf-fp.xml, 18);
}
/* TODO: Add [E]MAC registers. */
-
-cpu_reset(ENV_GET_CPU(env));
-qemu_init_vcpu(env);
-return env;
}
void cpu_m68k_flush_flags(CPUM68KState *env, int cc_op)
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 23/28] target-ppc: Move TCG initialization to PowerPCCPU initfn
Ensures that a QOM-created PowerPCCPU is usable.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-ppc/translate_init.c |9 -
1 Datei geändert, 4 Zeilen hinzugefügt(+), 5 Zeilen entfernt(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 63ba4a5..786d871 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -10337,11 +10337,6 @@ PowerPCCPU *cpu_ppc_init(const char *cpu_model)
cpu = POWERPC_CPU(object_new(object_class_get_name(oc)));
env = cpu-env;
-
-if (tcg_enabled()) {
-ppc_translate_init();
-}
-
env-cpu_model_str = cpu_model;
object_property_set_bool(OBJECT(cpu), true, realized, err);
@@ -10559,6 +10554,10 @@ static void ppc_cpu_initfn(Object *obj)
env-sps = defsps;
}
#endif /* defined(TARGET_PPC64) */
+
+if (tcg_enabled()) {
+ppc_translate_init();
+}
}
static void ppc_cpu_class_init(ObjectClass *oc, void *data)
--
1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 03/28] target-arm: Update ARMCPU to QOM realizefn
Turn arm_cpu_realize() into a QOM realize function, no longer called
via cpu.h prototype. To maintain the semantics of cpu_init(), set
realized = true explicitly in cpu_arm_init().
Move GDB coprocessor registration, CPU reset and vCPU initialization
into the realizefn.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-arm/cpu-qom.h |3 ++-
target-arm/cpu.c | 21 ++---
target-arm/cpu.h |1 +
target-arm/helper.c | 14 ++
4 Dateien geändert, 27 Zeilen hinzugefügt(+), 12 Zeilen entfernt(-)
diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 0f455c4..aff7bf3 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -33,6 +33,7 @@
/**
* ARMCPUClass:
+ * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* An ARM CPU model.
@@ -42,6 +43,7 @@ typedef struct ARMCPUClass {
CPUClass parent_class;
/* public */
+DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} ARMCPUClass;
@@ -107,7 +109,6 @@ static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)
#define ENV_GET_CPU(e) CPU(arm_env_get_cpu(e))
-void arm_cpu_realize(ARMCPU *cpu);
void register_cp_regs_for_features(ARMCPU *cpu);
#endif
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 07588a1..19d5ae4 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -147,15 +147,12 @@ static void arm_cpu_finalizefn(Object *obj)
g_hash_table_destroy(cpu-cp_regs);
}
-void arm_cpu_realize(ARMCPU *cpu)
+static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
{
-/* This function is called by cpu_arm_init() because it
- * needs to do common actions based on feature bits, etc
- * that have been set by the subclass init functions.
- * When we have QOM realize support it should become
- * a true realize function instead.
- */
+ARMCPU *cpu = ARM_CPU(dev);
+ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
CPUARMState *env = cpu-env;
+
/* Some features automatically imply others: */
if (arm_feature(env, ARM_FEATURE_V7)) {
set_feature(env, ARM_FEATURE_VAPA);
@@ -197,6 +194,12 @@ void arm_cpu_realize(ARMCPU *cpu)
}
register_cp_regs_for_features(cpu);
+arm_cpu_register_gdb_regs_for_features(cpu);
+
+cpu_reset(CPU(cpu));
+qemu_init_vcpu(env);
+
+acc-parent_realize(dev, errp);
}
/* CPU models */
@@ -763,6 +766,10 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
{
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(acc);
+DeviceClass *dc = DEVICE_CLASS(oc);
+
+acc-parent_realize = dc-realize;
+dc-realize = arm_cpu_realizefn;
acc-parent_reset = cc-reset;
cc-reset = arm_cpu_reset;
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ffddfcb..2902ba5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -234,6 +234,7 @@ typedef struct CPUARMState {
ARMCPU *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
int cpu_arm_exec(CPUARMState *s);
void do_interrupt(CPUARMState *);
void switch_mode(CPUARMState *, int);
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 37c34a1..f412143 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1270,14 +1270,22 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
cpu = ARM_CPU(object_new(cpu_model));
env = cpu-env;
env-cpu_model_str = cpu_model;
-arm_cpu_realize(cpu);
+
+/* TODO this should be set centrally, once possible */
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
if (tcg_enabled() !inited) {
inited = 1;
arm_translate_init();
}
-cpu_reset(CPU(cpu));
+return cpu;
+}
+
+void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
+{
+CPUARMState *env = cpu-env;
+
if (arm_feature(env, ARM_FEATURE_NEON)) {
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
51, arm-neon.xml, 0);
@@ -1288,8 +1296,6 @@ ARMCPU *cpu_arm_init(const char *cpu_model)
gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
19, arm-vfp.xml, 0);
}
-qemu_init_vcpu(env);
-return cpu;
}
/* Sort alphabetically by type name, except for any. */
--
1.7.10.4
Re: [Qemu-devel] [PATCH for 1.4 0/4] Simplify Makefile.objs some more
Il 20/01/2013 00:22, Andreas Färber ha scritto: Am 19.01.2013 23:06, schrieb Paolo Bonzini: Il 19/01/2013 19:11, Andreas Färber ha scritto: The patches are mostly mechanical substitutions, and there is no user-visible change---neither in total build time, nor in the files that are linked into the executables. Without having tested this yet I want to remind that it is necessary for qom/cpu.c to be built twice Hmm, it's not anymore actually (since libuser was removed). It hasn't been built twice for a month and apparently nothing broke. I surely didn't ack that. At the time I did the move, there was no conditional CPUState field (commit 8e98e2e80b92e08e79e27a0c20a172906cfa12d2). The only difference between the user and softmmu qom/cpu.c was that the user version ended up in libuser. ISTR I asked around about libuser, and the conclusion was that it was only needed for --enable-user-pie. Have you actually tested linux-user to verify it works? It might lead to unexpected CPUState field accesses. As I said, at the time I did the move there was no difference between the two. Now, I am indeed quite surprised that it works, but yes---it does, at least trivial /bin/ls. You are judging based on master. I have some more code movements queued (qom-cpu-8) and I believe it was Anthony who insisted on suppressing those unneeded user-only fields even if they were unconditional in CPU_COMMON before. qom/cpu.c is not intended to remain so small forever - any cpu_* code that does not depend on CPUArchState can find a new home there. cpu_interrupt() is being moved to qom/cpu.h and cpu_reset_interrupt() to qom/cpu.c for instance. And I'm working on refactoring CPU VMState, that either requires #ifdef'ery or lots of new stubs beyond what Eduardo added. You can place those in a qom/cpu-softmmu.c. What I care about is having an understandable build system. At some point we had 12 recursive -obj-y variables and a few other non-recursive ones. The interactions and inclusions were completely impossible to understand. Paolo
[Qemu-devel] [RFC qom-cpu v3] target-ppc: Introduce unrealizefn for PowerPCCPU
Use it to clean up the opcode table, resolving a former TODO from Jocelyn.
Also switch from malloc() to g_malloc().
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: David Gibson da...@gibson.dropbear.id.au
Cc: Markus Armbruster arm...@redhat.com
---
Based on my CPUState QOM realizefn support series v2 (1.5 material).
From QOM'ify Power Architecture CPU v2:
* Implemented unrealizefn instead of finalizefn, to address rejection by dwg:
create_new_table() is not called from the instance initializer.
v1 - v2:
* Replace cpu_ppc_close() and its TODO with an implementation as a finalizefn.
target-ppc/translate_init.c | 16 +++-
1 Datei geändert, 15 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 786d871..2385571 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -9641,7 +9641,7 @@ static int create_new_table (opc_handler_t **table,
unsigned char idx)
{
opc_handler_t **tmp;
-tmp = malloc(0x20 * sizeof(opc_handler_t));
+tmp = g_malloc(0x20 * sizeof(opc_handler_t));
fill_new_table(tmp, 0x20);
table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
@@ -10236,6 +10236,19 @@ static void ppc_cpu_realizefn(DeviceState *dev, Error
**errp)
#endif
}
+static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
+{
+PowerPCCPU *cpu = POWERPC_CPU(dev);
+CPUPPCState *env = cpu-env;
+int i;
+
+for (i = 0; i 0x40; i++) {
+if (env-opcodes[i] != invalid_handler) {
+g_free(env-opcodes[i]);
+}
+}
+}
+
static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
{
ObjectClass *oc = (ObjectClass *)a;
@@ -10568,6 +10581,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void
*data)
pcc-parent_realize = dc-realize;
dc-realize = ppc_cpu_realizefn;
+dc-unrealize = ppc_cpu_unrealizefn;
pcc-parent_reset = cc-reset;
cc-reset = ppc_cpu_reset;
--
1.7.10.4
[Qemu-devel] [PATCH for-1.4] *-user: Don't reset X86CPU again
Since commit 65dee38052597b6285eb208125369f01b29ba6c1 (target-i386: move cpu_reset and reset callback to cpu.c) the x86 CPU is reset through cpu_init() but was still reset immediately after in linux-user and bsd-user. Similarly it was reset again in linux-user after cpu_copy(), defeating its very purpose. Clean this up. Fixing the ppc and sparc cases of cpu_copy() and overhauling its implementation is left for another day. Cc: Igor Mammedov imamm...@redhat.com Signed-off-by: Andreas Färber afaer...@suse.de Cc: Peter Maydell peter.mayd...@linaro.org --- bsd-user/main.c |2 +- linux-user/main.c|2 +- linux-user/syscall.c |2 +- 3 Dateien geändert, 3 Zeilen hinzugefügt(+), 3 Zeilen entfernt(-) diff --git a/bsd-user/main.c b/bsd-user/main.c index 1dc0330..ae24723 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -917,7 +917,7 @@ int main(int argc, char **argv) fprintf(stderr, Unable to find CPU definition\n); exit(1); } -#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) +#if defined(TARGET_SPARC) || defined(TARGET_PPC) cpu_reset(ENV_GET_CPU(env)); #endif thread_env = env; diff --git a/linux-user/main.c b/linux-user/main.c index 0181bc2..3df8aa2 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3540,7 +3540,7 @@ int main(int argc, char **argv, char **envp) fprintf(stderr, Unable to find CPU definition\n); exit(1); } -#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) +#if defined(TARGET_SPARC) || defined(TARGET_PPC) cpu_reset(ENV_GET_CPU(env)); #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 693e66f..7be6144 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4361,7 +4361,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, init_task_state(ts); /* we create a new CPU instance. */ new_env = cpu_copy(env); -#if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) +#if defined(TARGET_SPARC) || defined(TARGET_PPC) cpu_reset(ENV_GET_CPU(new_env)); #endif /* Init regs that differ from the parent. */ -- 1.7.10.4
Re: [Qemu-devel] [PATCH][v2] linux-user: correct semctl() and shmctl()
On 2 January 2013 20:38, Laurent Vivier laur...@vivier.eu wrote:
The parameter union semun of semctl() is not a value
but a pointer to the value.
Moreover, all fields of target_su must be swapped (if needed).
The third argument of shmctl is a pointer.
WITHOUT this patch:
$ ipcs
kernel not configured for shared memory
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
WITH this patch:
$ ipcs
-- Shared Memory Segments
keyshmid owner perms bytes nattch status
0x4e545030 0 root 60096 1
0x4e545031 32769 root 60096 1
0x4e545032 65538 root 66696 1
0x4e545033 98307 root 66696 1
0x47505344 131076 root 6668240 1
0x3c81b7f5 163845 laurent 6664096 0
0x 729513990 laurent 600393216 2 dest
0x 729546759 laurent 600393216 2 dest
0x 1879179273 laurent 600393216 2 dest
-- Semaphore Arrays
keysemid owner perms nsems
0x3c81b7f6 32768 laurent 6661
0x1c44ac47 6586369laurent 6001
-- Message Queues
keymsqid owner perms used-bytes messages
0x1c44ac45 458752 laurent60000
0x1c44ac46 491521 laurent60000
Signed-off-by: Laurent Vivier laur...@vivier.eu
---
[v2] move lock_user_struct() in do_semctl()
linux-user/syscall.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index e99adab..b2687e1 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -2637,8 +2637,9 @@ static inline abi_long host_to_target_semarray(int
semid, abi_ulong target_addr,
}
static inline abi_long do_semctl(int semid, int semnum, int cmd,
- union target_semun target_su)
+ abi_ulong ptr)
{
+union target_semun *target_su;
union semun arg;
struct semid_ds dsarg;
unsigned short *array = NULL;
@@ -2647,43 +2648,42 @@ static inline abi_long do_semctl(int semid, int
semnum, int cmd,
abi_long err;
cmd = 0xff;
+if (!lock_user_struct(VERIFY_READ, target_su, ptr, 1)) {
+return -TARGET_EFAULT;
+}
switch( cmd ) {
case GETVAL:
case SETVAL:
-arg.val = tswap32(target_su.val);
+arg.val = tswap32(target_su-val);
ret = get_errno(semctl(semid, semnum, cmd, arg));
-target_su.val = tswap32(arg.val);
+target_su-val = tswap32(arg.val);
break;
case GETALL:
case SETALL:
-err = target_to_host_semarray(semid, array, target_su.array);
+err = target_to_host_semarray(semid, array,
+ tswapal(target_su-array));
if (err)
-return err;
+break;
(1) Coding style demands braces
(2) More importantly, this is going to break the return value -- instead
of returning 'err' we will break out of the switch and then return 'ret'.
There are similar issues in other cases.
-- PMM
Re: [Qemu-devel] [PATCH 3/3] net/bitbang_mdio: Use bitbang core for smc91c111 network device
On 19 January 2013 22:28, Grant Likely grant.lik...@secretlab.ca wrote:
The smc91c111 device has bitbanged MDIO access, but the model doesn't
yet implement it. This patch uses the generalized bitbang MDIO support
pulled out of etraxfs Ethernet driver.
@@ -44,6 +45,13 @@ typedef struct {
uint8_t int_level;
uint8_t int_mask;
MemoryRegion mmio;
+
+/* MDIO bus. */
+struct qemu_mdio mdio_bus;
+unsigned int phyaddr;
+
+/* PHY. */
+struct qemu_phy phy;
} smc91c111_state;
This surely needs VMState additions so the extra state can be passed
across migrations. It looks like the MDIO/PHY stuff from the etraxfs code
doesn't have any kind of state save/restore support, so you probably need
to first implement that in your new mdio/phy source file, and then refer
to it here.
-- PMM
Re: [Qemu-devel] [PULL 0/6] Block patches
Pulled. Thanks. Regards, Anthony Liguori
[Qemu-devel] [Bug 1102027] [NEW] QED Time travel
Public bug reported: This night after a reboot of a VM, it was back to 8 Oct. 2012, i've lost all data between 8 Oct 2012 and now. I've check the QED file and mount on another VM, all seems OK. This QED has a raw backfile with the base OS (debian) shared with many others QED. It has NO snapshot. QEMU emulator version 1.1.2 Does anyone have a hint ? ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1102027 Title: QED Time travel Status in QEMU: New Bug description: This night after a reboot of a VM, it was back to 8 Oct. 2012, i've lost all data between 8 Oct 2012 and now. I've check the QED file and mount on another VM, all seems OK. This QED has a raw backfile with the base OS (debian) shared with many others QED. It has NO snapshot. QEMU emulator version 1.1.2 Does anyone have a hint ? To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1102027/+subscriptions
[Qemu-devel] [PATCH] Annotate questionable fallthroughs
Recent Clang compilers have preliminary support for finding
unannotated fallthrough cases in switch statements with
compiler flag -Wimplicit-fallthrough. The support is incomplete,
it's only possible to annotate the case in C++ but not in C, so it
wouldn't be useful to enable the flag for QEMU yet.
Mark cases which don't have a comment about fall through with
a comment. In legitimate fall through cases the comment can be
edited later to mark the case for future readers.
Signed-off-by: Blue Swirl blauwir...@gmail.com
---
audio/audio.c|3 ++
disas/cris.c |1 +
disas/m68k.c |1 +
disas/sh4.c |2 +
hw/arm_sysctl.c |2 +
hw/cadence_ttc.c |2 +
hw/cirrus_vga.c |1 +
hw/es1370.c | 20 +++
hw/hid.c |2 +
hw/highbank.c|2 +
hw/ide/core.c|8 ++
hw/jazz_led.c|1 +
hw/omap1.c |3 ++
hw/omap_dma.c| 12 +
hw/omap_spi.c| 24 ++
hw/pflash_cfi02.c|1 +
hw/ppc.c |1 +
hw/pxa2xx.c |2 +
hw/pxa2xx_timer.c| 47
hw/scsi-bus.c|2 +
hw/sh_timer.c|5
hw/smc91c111.c |1 +
hw/stellaris.c |2 +
hw/tcx.c |1 +
hw/twl92230.c| 17 +
hw/usb/hcd-ohci.c|2 +
linux-user/main.c|4 +++
linux-user/syscall.c |1 +
target-i386/translate.c |3 ++
target-mips/translate.c | 54 ++
target-ppc/mmu_helper.c |1 +
target-s390x/translate.c |1 +
target-sparc/ldst_helper.c |4 +++
target-unicore32/translate.c |2 +
target-xtensa/op_helper.c|2 +
tcg/optimize.c |3 ++
ui/sdl.c |1 +
37 files changed, 241 insertions(+), 0 deletions(-)
diff --git a/audio/audio.c b/audio/audio.c
index 02bb886..b42489b 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -617,11 +617,13 @@ void audio_pcm_init_info (struct audio_pcm_info *info,
struct audsettings *as)
switch (as-fmt) {
case AUD_FMT_S8:
sign = 1;
+/* XXX: questionable fallthrough */
case AUD_FMT_U8:
break;
case AUD_FMT_S16:
sign = 1;
+/* XXX: questionable fallthrough */
case AUD_FMT_U16:
bits = 16;
shift = 1;
@@ -629,6 +631,7 @@ void audio_pcm_init_info (struct audio_pcm_info *info,
struct audsettings *as)
case AUD_FMT_S32:
sign = 1;
+/* XXX: questionable fallthrough */
case AUD_FMT_U32:
bits = 32;
shift = 2;
diff --git a/disas/cris.c b/disas/cris.c
index 9dfb4e3..c2c08fa 100644
--- a/disas/cris.c
+++ b/disas/cris.c
@@ -1348,6 +1348,7 @@ spec_reg_info (unsigned int sreg, enum cris_disass_family
distype)
/* No ambiguous sizes or register names with CRISv32. */
if (cris_spec_regs[i].warning == NULL)
return cris_spec_regs[i];
+/* XXX: questionable fallthrough */
default:
;
}
diff --git a/disas/m68k.c b/disas/m68k.c
index c950241..7e82046 100644
--- a/disas/m68k.c
+++ b/disas/m68k.c
@@ -1626,6 +1626,7 @@ print_insn_arg (const char *d,
case 'X':
place = '8';
+ /* XXX: questionable fallthrough */
case 'Y':
case 'Z':
case 'W':
diff --git a/disas/sh4.c b/disas/sh4.c
index f6cadd5..0e94424 100644
--- a/disas/sh4.c
+++ b/disas/sh4.c
@@ -1969,6 +1969,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info
*info)
fprintf_fn (stream, xd%d, rn ~1);
break;
}
+ /* XXX: questionable fallthrough */
case D_REG_N:
fprintf_fn (stream, dr%d, rn);
break;
@@ -1978,6 +1979,7 @@ print_insn_sh (bfd_vma memaddr, struct disassemble_info
*info)
fprintf_fn (stream, xd%d, rm ~1);
break;
}
+ /* XXX: questionable fallthrough */
case D_REG_M:
fprintf_fn (stream, dr%d, rm);
break;
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index a196fcc..2066ef3 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -199,6 +199,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
switch (offset) {
case 0x08: /* LED */
s-leds = val;
+/* XXX: questionable fallthrough */
case 0x0c: /* OSC0 */
case 0x10: /* OSC1 */
case 0x14: /* OSC2 */
@@ -295,6 +296,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
/* On VExpress this register is unimplemented and
Re: [Qemu-devel] [PATCH v2 0/2] fix two revision related errors
On Thu, Jan 17, 2013 at 02:02:26PM +0100, Gerd Hoffmann wrote: On 01/16/13 18:59, Alon Levy wrote: Regarding orientation setting in windows 7 64 guest: Desktop, right click-Screen resolution - You can choose Orientation: Landscape, Portrait, Landscape (flipped), Portrait (flipped) - You can choose Resolution - You can click Advanced Settings, then List All Modes at the bottom, you get all the modes (i.e. four of each resolution, one for each orientation) Ah, ok. The driver seems to handle portrait and swap x+y when creating a displaysurface. At least I get a 600x800 display upright. I can't see a difference between Landscape + Landscape (flipped). Likewise Portrait + Portrait (flipped). Is there any? I can't actually get the (flipped) modes (both portrait and landscape) to work, I get an error message Unable to save display settings. How did you manage to get them to work? which driver, qemu command line, qemu version did you use? There are two changes after applying the change rom size to 8192 patch: - there is no longer an Orientation option - the modes listed under List All Modes reduce as expected Ok, so we loose the Portrait mode. Changes to the second patch: - no orientations except the normal Keeping orientation 0+1 (and dropping the flipped 2+3 versions) should make the mode list small enougth that it fits while maintaining support for the portrait mode. That's what I'm going to send. I think it would also be good to fix the driver to ignore everything with or How about that? - hard code 8192 bytes rom size - assert if the required size is larger Good. cheers, Gerd
Re: [Qemu-devel] [PATCH] Annotate questionable fallthroughs
On 20 January 2013 15:54, Blue Swirl blauwir...@gmail.com wrote:
This patch is a bit big to usefully review. A few comments on bits
I happened to notice:
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index a196fcc..2066ef3 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -199,6 +199,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
switch (offset) {
case 0x08: /* LED */
s-leds = val;
+/* XXX: questionable fallthrough */
Should have its own 'break' but it's safe currently as the following
case is just 'break' anyway.
case 0x0c: /* OSC0 */
case 0x10: /* OSC1 */
case 0x14: /* OSC2 */
@@ -295,6 +296,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
/* On VExpress this register is unimplemented and will RAZ/WI */
break;
}
+/* XXX: questionable fallthrough */
Ditto.
case 0x54: /* CLCDSER */
case 0x64: /* DMAPSR0 */
case 0x68: /* DMAPSR1 */
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -537,8 +537,10 @@ IO_WRITE_PROTO (es1370_writew)
case ES1370_REG_ADC_SCOUNT:
d++;
+/* XXX: questionable fallthrough */
case ES1370_REG_DAC2_SCOUNT:
d++;
+/* XXX: questionable fallthrough */
case ES1370_REG_DAC1_SCOUNT:
d-scount = (d-scount ~0x) | (val 0x);
break;
These fallthroughs are clearly intentional (similar cases
elsewhere in your patch).
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -182,8 +182,10 @@ static uint64_t gptm_read(void *opaque, hwaddr offset,
case 0x48: /* TAR */
if (s-control == 1)
return s-rtc;
+/* XXX: questionable fallthrough */
case 0x4c: /* TBR */
hw_error(TODO: Timer value read\n);
+/* XXX: questionable fallthrough */
This isn't a fallthrough at all, hw_error() never returns.
default:
hw_error(gptm_read: Bad offset 0x%x\n, (int)offset);
return 0;
(...so this return 0 is unreachable, but hey.)
I don't think there's much point adding tons of XXX comments
when a bunch of these aren't actually wrong code. If you want to fix
this I think a better approach would be more focused patches aimed
at adding 'break;' or /* fallthrough */ based on actual human
examination of the surrounding code.
-- PMM
Re: [Qemu-devel] [PATCH 0/3] Generalize bitbang MDIO and use for versatile-pb
Am 19.01.2013 23:28, schrieb Grant Likely: This series extracts the MDIO bitbang code from the etraxfs driver and makes it usable on targets using the smc9 Ethernet controller. I've tested this using u-boot on the versatile-pb model. net/bitbang_mdio: Generalize etraxfs MDIO bitbanging emulation net/bitbang_mdio: Never set PHY RST and ANEG_RST bits on register write net/bitbang_mdio: Use bitbang core for smc91c111 network device hw/Makefile.objs |2 +- hw/bitbang_mdio.c | 271 hw/bitbang_mdio.h | 72 + hw/cris/Makefile.objs |1 + hw/etraxfs_eth.c | 273 + hw/smc91c111.c| 29 +- 6 files changed, 371 insertions(+), 277 deletions(-) create mode 100644 hw/bitbang_mdio.c create mode 100644 hw/bitbang_mdio.h Neither of these files is actually in net/, so please fix that or name the subject less misleading bitbang_mdio: ... if you resend. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] Annotate questionable fallthroughs
On Sun, Jan 20, 2013 at 4:56 PM, Peter Maydell peter.mayd...@linaro.org wrote:
On 20 January 2013 15:54, Blue Swirl blauwir...@gmail.com wrote:
This patch is a bit big to usefully review. A few comments on bits
I happened to notice:
diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c
index a196fcc..2066ef3 100644
--- a/hw/arm_sysctl.c
+++ b/hw/arm_sysctl.c
@@ -199,6 +199,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
switch (offset) {
case 0x08: /* LED */
s-leds = val;
+/* XXX: questionable fallthrough */
Should have its own 'break' but it's safe currently as the following
case is just 'break' anyway.
case 0x0c: /* OSC0 */
case 0x10: /* OSC1 */
case 0x14: /* OSC2 */
@@ -295,6 +296,7 @@ static void arm_sysctl_write(void *opaque, hwaddr offset,
/* On VExpress this register is unimplemented and will RAZ/WI */
break;
}
+/* XXX: questionable fallthrough */
Ditto.
case 0x54: /* CLCDSER */
case 0x64: /* DMAPSR0 */
case 0x68: /* DMAPSR1 */
--- a/hw/es1370.c
+++ b/hw/es1370.c
@@ -537,8 +537,10 @@ IO_WRITE_PROTO (es1370_writew)
case ES1370_REG_ADC_SCOUNT:
d++;
+/* XXX: questionable fallthrough */
case ES1370_REG_DAC2_SCOUNT:
d++;
+/* XXX: questionable fallthrough */
case ES1370_REG_DAC1_SCOUNT:
d-scount = (d-scount ~0x) | (val 0x);
break;
These fallthroughs are clearly intentional (similar cases
elsewhere in your patch).
--- a/hw/stellaris.c
+++ b/hw/stellaris.c
@@ -182,8 +182,10 @@ static uint64_t gptm_read(void *opaque, hwaddr offset,
case 0x48: /* TAR */
if (s-control == 1)
return s-rtc;
+/* XXX: questionable fallthrough */
case 0x4c: /* TBR */
hw_error(TODO: Timer value read\n);
+/* XXX: questionable fallthrough */
This isn't a fallthrough at all, hw_error() never returns.
default:
hw_error(gptm_read: Bad offset 0x%x\n, (int)offset);
return 0;
(...so this return 0 is unreachable, but hey.)
I don't think there's much point adding tons of XXX comments
when a bunch of these aren't actually wrong code. If you want to fix
this I think a better approach would be more focused patches aimed
at adding 'break;' or /* fallthrough */ based on actual human
examination of the surrounding code.
The problem is that while some cases may be easy to decide, others are
not so clear.
My initial thought about the work flow was that this patch should be
succeeded by other patches which replace the comment with correct
action. These could be squashed to the original patch or committed
later. If no decision can be made for some comment, it could stay as
XXX.
Alternatively, I could split this patch per maintainer, architecture
or file even. Each maintainer could tune the patches as they see fit
and commit whatever they want later. Probably some areas would be
never fixed.
-- PMM
Re: [Qemu-devel] [PATCH 1/3] net/bitbang_mdio: Generalize etraxfs MDIO bitbanging emulation
Am 19.01.2013 23:28, schrieb Grant Likely: The etraxfs Ethernet model implements quite a nice bitbanging core. The change splits it out into a separate .c file. There are no functional changes here, just movement of code and reformatting to match qemu coding standards. Cc: Peter Maydell peter.mayd...@linaro.org Cc: Paul Brook p...@codesourcery.com Cc: Edgar E. Iglesias edgar.igles...@gmail.com Cc: Anthony Liguori aligu...@us.ibm.com Signed-off-by: Grant Likely grant.lik...@secretlab.ca --- hw/bitbang_mdio.c | 263 +++ hw/bitbang_mdio.h | 72 + hw/cris/Makefile.objs |1 + hw/etraxfs_eth.c | 273 + 4 files changed, 337 insertions(+), 272 deletions(-) create mode 100644 hw/bitbang_mdio.c create mode 100644 hw/bitbang_mdio.h If you fix coding style issues in the original file first this helps git's copy detection. Looks like either you have it disabled for patches or it's not detecting it at all... I would expect some similarity N% notice. Cheers, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] Annotate questionable fallthroughs
Am 20.01.2013 18:26, schrieb Blue Swirl: On Sun, Jan 20, 2013 at 4:56 PM, Peter Maydell peter.mayd...@linaro.org wrote: On 20 January 2013 15:54, Blue Swirl blauwir...@gmail.com wrote: This patch is a bit big to usefully review. A few comments on bits I happened to notice: [...] --- a/hw/stellaris.c +++ b/hw/stellaris.c @@ -182,8 +182,10 @@ static uint64_t gptm_read(void *opaque, hwaddr offset, case 0x48: /* TAR */ if (s-control == 1) return s-rtc; +/* XXX: questionable fallthrough */ case 0x4c: /* TBR */ hw_error(TODO: Timer value read\n); +/* XXX: questionable fallthrough */ This isn't a fallthrough at all, hw_error() never returns. Maybe hw_error() needs some annotation instead? I don't think there's much point adding tons of XXX comments when a bunch of these aren't actually wrong code. If you want to fix this I think a better approach would be more focused patches aimed at adding 'break;' or /* fallthrough */ based on actual human examination of the surrounding code. +1 The problem is that while some cases may be easy to decide, others are not so clear. My initial thought about the work flow was that this patch should be succeeded by other patches which replace the comment with correct action. These could be squashed to the original patch or committed later. If no decision can be made for some comment, it could stay as XXX. $ git grep XXX | wc --lines 75797 I don't think adding any more will help getting them addressed... Alternatively, I could split this patch per maintainer, architecture or file even. Each maintainer could tune the patches as they see fit and commit whatever they want later. Probably some areas would be never fixed. I would suggest to split per file and to propose either action rather than putting an XXX. I'm sure there would be static analysis volunteers to help review, CC'ing Stefan W. and Markus. :) Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
[Qemu-devel] [PATCH for-1.4?] isa: QOM'ify isa_bus_from_device()
DeviceState::parent_bus is document as private and should be accessed
through qdev_get_parent_bus(). Use a DEVICE() cast instead of accessing
ISADevice's qdev field directly. Use ISA_BUS() in place of DO_UPCAST().
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Anthony Liguori anth...@codemonkey.ws
---
hw/isa.h |2 +-
1 Datei geändert, 1 Zeile hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/hw/isa.h b/hw/isa.h
index 62e89d3..7a8874a 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -82,7 +82,7 @@ void isa_register_portio_list(ISADevice *dev, uint16_t start,
static inline ISABus *isa_bus_from_device(ISADevice *d)
{
-return DO_UPCAST(ISABus, qbus, d-qdev.parent_bus);
+return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
extern hwaddr isa_mem_base;
--
1.7.10.4
Re: [Qemu-devel] [PATCH] Annotate questionable fallthroughs
On 20 January 2013 17:38, Andreas Färber afaer...@suse.de wrote: Am 20.01.2013 18:26, schrieb Blue Swirl: On Sun, Jan 20, 2013 at 4:56 PM, Peter Maydell peter.mayd...@linaro.org wrote: case 0x4c: /* TBR */ hw_error(TODO: Timer value read\n); +/* XXX: questionable fallthrough */ This isn't a fallthrough at all, hw_error() never returns. Maybe hw_error() needs some annotation instead? It is already marked QEMU_NORETURN. Presumably whatever tool Blue is using doesn't pay attention to noreturn annotations. -- PMM
Re: [Qemu-devel] [PATCH for-1.4?] isa: QOM'ify isa_bus_from_device()
Am 20.01.2013 18:56, schrieb Andreas Färber:
DeviceState::parent_bus is document as private and should be accessed
documented - please fix when applying.
through qdev_get_parent_bus(). Use a DEVICE() cast instead of accessing
ISADevice's qdev field directly. Use ISA_BUS() in place of DO_UPCAST().
Signed-off-by: Andreas Färber afaer...@suse.de
Cc: Anthony Liguori anth...@codemonkey.ws
---
hw/isa.h |2 +-
1 Datei geändert, 1 Zeile hinzugefügt(+), 1 Zeile entfernt(-)
diff --git a/hw/isa.h b/hw/isa.h
index 62e89d3..7a8874a 100644
--- a/hw/isa.h
+++ b/hw/isa.h
@@ -82,7 +82,7 @@ void isa_register_portio_list(ISADevice *dev, uint16_t
start,
static inline ISABus *isa_bus_from_device(ISADevice *d)
{
-return DO_UPCAST(ISABus, qbus, d-qdev.parent_bus);
+return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
extern hwaddr isa_mem_base;
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH] Annotate questionable fallthroughs
I don't think there's much point adding tons of XXX comments when a bunch of these aren't actually wrong code. If you want to fix this I think a better approach would be more focused patches aimed at adding 'break;' or /* fallthrough */ based on actual human examination of the surrounding code. I agree. I encourage annotation of intentional fall through, but blindly pasting the output of an automated tool is liable to cause more harm than good. IMO running code analysis tools is easy. It's only when you take the time to manually inspect and fix the code that this really becomes valuable. Paul
[Qemu-devel] [PATCH] Ensure PCIR is aligned to 4 bytes
The PCI Firmware Specification apparently requires that the PCI Data Structure be DWORD-aligned. The implementation in OVMF also requires this, so vgabios ROMs don't work there. With this fixed, I can now initialise the VGA ROM from EFI, and EFI can display using INT 10h services. --- vgabios-0.6c/vgabios.c.orig 2013-01-20 11:33:36.138548472 -0600 +++ vgabios-0.6c/vgabios.c 2013-01-20 11:36:26.060270163 -0600 @@ -204,6 +204,7 @@ vgabios_website: .byte 0x00 #ifdef PCIBIOS +.align 4 // DWORD alignment required by PCI Firmware Specification vgabios_pci_data: .ascii PCIR #ifdef CIRRUS -- David WoodhouseOpen Source Technology Centre david.woodho...@intel.com Intel Corporation smime.p7s Description: S/MIME cryptographic signature
[Qemu-devel] [PATCH] target-mips: Fix accumulator selection for MIPS16 and microMIPS
Add accumulator arguments to gen_HILO and gen_muldiv, rather than
extracting the accumulator directly from ctx-opcode. The extraction
was only right for the standard encoding: MIPS16 doesn't have access
to the DSP registers, while microMIPS encodes the accumulator register
in a different field (bits 14 and 15).
Passing the accumulator register is probably an over-generalisation
for division and 64-bit multiplication, which never access anything
other than HI and LO, and which always pass 0 as the new argument.
Separating them felt a bit fussy though.
Signed-off-by: Richard Sandiford rdsandif...@googlemail.com
---
target-mips/translate.c | 135
1 file changed, 57 insertions(+), 78 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 206ba83..47528d7 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2571,10 +2571,9 @@ static void gen_shift (CPUMIPSState *env, DisasContext
*ctx, uint32_t opc,
}
/* Arithmetic on HI/LO registers */
-static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg)
+static void gen_HILO (DisasContext *ctx, uint32_t opc, int acc, int reg)
{
const char *opn = hilo;
-unsigned int acc;
if (reg == 0 (opc == OPC_MFHI || opc == OPC_MFLO)) {
/* Treat as NOP. */
@@ -2582,12 +2581,6 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc,
int reg)
return;
}
-if (opc == OPC_MFHI || opc == OPC_MFLO) {
-acc = ((ctx-opcode) 21) 0x03;
-} else {
-acc = ((ctx-opcode) 11) 0x03;
-}
-
if (acc != 0) {
check_dsp(ctx);
}
@@ -2651,11 +2644,10 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc,
int reg)
}
static void gen_muldiv (DisasContext *ctx, uint32_t opc,
-int rs, int rt)
+int acc, int rs, int rt)
{
const char *opn = mul/div;
TCGv t0, t1;
-unsigned int acc;
t0 = tcg_temp_new();
t1 = tcg_temp_new();
@@ -2663,6 +2655,9 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
gen_load_gpr(t0, rs);
gen_load_gpr(t1, rt);
+if (acc != 0)
+check_dsp(ctx);
+
switch (opc) {
case OPC_DIV:
{
@@ -2677,10 +2672,10 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_or_tl(t2, t2, t3);
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
-tcg_gen_div_tl(cpu_LO[0], t0, t1);
-tcg_gen_rem_tl(cpu_HI[0], t0, t1);
-tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
-tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
+tcg_gen_div_tl(cpu_LO[acc], t0, t1);
+tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
+tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
+tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
tcg_temp_free(t3);
tcg_temp_free(t2);
}
@@ -2693,10 +2688,10 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1);
-tcg_gen_divu_tl(cpu_LO[0], t0, t1);
-tcg_gen_remu_tl(cpu_HI[0], t0, t1);
-tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]);
-tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]);
+tcg_gen_divu_tl(cpu_LO[acc], t0, t1);
+tcg_gen_remu_tl(cpu_HI[acc], t0, t1);
+tcg_gen_ext32s_tl(cpu_LO[acc], cpu_LO[acc]);
+tcg_gen_ext32s_tl(cpu_HI[acc], cpu_HI[acc]);
tcg_temp_free(t3);
tcg_temp_free(t2);
}
@@ -2706,10 +2701,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
-acc = ((ctx-opcode) 11) 0x03;
-if (acc != 0) {
-check_dsp(ctx);
-}
tcg_gen_ext_tl_i64(t2, t0);
tcg_gen_ext_tl_i64(t3, t1);
@@ -2728,10 +2719,6 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
{
TCGv_i64 t2 = tcg_temp_new_i64();
TCGv_i64 t3 = tcg_temp_new_i64();
-acc = ((ctx-opcode) 11) 0x03;
-if (acc != 0) {
-check_dsp(ctx);
-}
tcg_gen_ext32u_tl(t0, t0);
tcg_gen_ext32u_tl(t1, t1);
@@ -2760,8 +2747,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
tcg_gen_or_tl(t2, t2, t3);
tcg_gen_movi_tl(t3, 0);
tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1);
-tcg_gen_div_tl(cpu_LO[0], t0, t1);
-tcg_gen_rem_tl(cpu_HI[0], t0, t1);
+tcg_gen_div_tl(cpu_LO[acc], t0, t1);
+tcg_gen_rem_tl(cpu_HI[acc], t0, t1);
tcg_temp_free(t3);
tcg_temp_free(t2);
}
@@ -2772,8 +2759,8 @@
[Qemu-devel] [PATCH] target-mips: Sign-extend the result of LWR
Sign-extend the result of LWR, as is already done for LWL. This is necessary in the case where LWR loads the full word (i.e. the address is actually aligned). In the other cases, it is implementation defined whether the upper 32 bits of the result are unchanged or a copy of bit 31. The latter seems easier to implement. Previously the code used: (oldval (0xfffe (31 - bitshift))) | (newval bitshift) which zeroed the upper bits of the register, losing any previous sign extension in the unaligned cases. Signed-off-by: Richard Sandiford rdsandif...@googlemail.com --- target-mips/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 623edd0..08e28f3 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1735,6 +1735,7 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, tcg_temp_free(t2); tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); +tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); opn = lwr; break; -- 1.7.11.7
[Qemu-devel] [PATCH] target-mips: Fix signedness of loads in MIPS16 RESTOREs
Make RESTORE use sign-extending rather than zero-extending loads.
Signed-off-by: Richard Sandiford rdsandif...@googlemail.com
---
target-mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 47528d7..623edd0 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -9409,7 +9409,7 @@ static void gen_mips16_restore (DisasContext *ctx,
#define DECR_AND_LOAD(reg) do { \
tcg_gen_subi_tl(t0, t0, 4); \
-tcg_gen_qemu_ld32u(t1, t0, ctx-mem_idx); \
+tcg_gen_qemu_ld32s(t1, t0, ctx-mem_idx); \
gen_store_gpr(t1, reg); \
} while (0)
--
1.7.11.7
Re: [Qemu-devel] [PATCH for-1.4] qom: Extend documentation on QOM method concepts
Applied. Thanks. Regards, Anthony Liguori
Re: [Qemu-devel] [PATCH] Makefile: drop recursive libcacard clean
Applied. Thanks. Regards, Anthony Liguori
Re: [Qemu-devel] [PATCH] bswap: improve gluing
Applied. Thanks. Regards, Anthony Liguori
Re: [Qemu-devel] [PULL for-1.4 0/8] Block patches
Pulled. Thanks. Regards, Anthony Liguori
Re: [Qemu-devel] [PATCH] virtio-pci: fix irqfd cleanup argument order
Applied. Thanks. Regards, Anthony Liguori
Re: [Qemu-devel] [PULL 0/5] QMP queue
Pulled. Thanks. Regards, Anthony Liguori
[Qemu-devel] [PATCH] linux-user: correct semctl() and shmctl()
The parameter union semun of semctl() is not a value
but a pointer to the value.
Moreover, all fields of target_su must be swapped (if needed).
The third argument of shmctl is a pointer.
WITHOUT this patch:
$ ipcs
kernel not configured for shared memory
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
WITH this patch:
$ ipcs
-- Shared Memory Segments
keyshmid owner perms bytes nattch status
0x4e545030 0 root 60096 1
0x4e545031 32769 root 60096 1
0x4e545032 65538 root 66696 1
0x4e545033 98307 root 66696 1
0x47505344 131076 root 6668240 1
0x3c81b7f5 163845 laurent 6664096 0
0x 729513990 laurent 600393216 2 dest
0x 729546759 laurent 600393216 2 dest
0x 1879179273 laurent 600393216 2 dest
-- Semaphore Arrays
keysemid owner perms nsems
0x3c81b7f6 32768 laurent 6661
0x1c44ac47 6586369laurent 6001
-- Message Queues
keymsqid owner perms used-bytes messages
0x1c44ac45 458752 laurent60000
0x1c44ac46 491521 laurent60000
Signed-off-by: Laurent Vivier laur...@vivier.eu
---
linux-user/syscall.c | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 693e66f..3c1bb3d 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -2635,8 +2635,9 @@ static inline abi_long host_to_target_semarray(int semid,
abi_ulong target_addr,
}
static inline abi_long do_semctl(int semid, int semnum, int cmd,
- union target_semun target_su)
+ abi_ulong ptr)
{
+union target_semun *target_su;
union semun arg;
struct semid_ds dsarg;
unsigned short *array = NULL;
@@ -2645,33 +2646,38 @@ static inline abi_long do_semctl(int semid, int semnum,
int cmd,
abi_long err;
cmd = 0xff;
+if (!lock_user_struct(VERIFY_READ, target_su, ptr, 1)) {
+return -TARGET_EFAULT;
+}
switch( cmd ) {
case GETVAL:
case SETVAL:
-arg.val = tswap32(target_su.val);
+arg.val = tswap32(target_su-val);
ret = get_errno(semctl(semid, semnum, cmd, arg));
-target_su.val = tswap32(arg.val);
+target_su-val = tswap32(arg.val);
break;
case GETALL:
case SETALL:
-err = target_to_host_semarray(semid, array, target_su.array);
+err = target_to_host_semarray(semid, array,
+ tswapal(target_su-array));
if (err)
return err;
arg.array = array;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_semarray(semid, target_su.array, array);
+err = host_to_target_semarray(semid, tswapal(target_su-array),
+ array);
if (err)
return err;
break;
case IPC_STAT:
case IPC_SET:
case SEM_STAT:
-err = target_to_host_semid_ds(dsarg, target_su.buf);
+err = target_to_host_semid_ds(dsarg, tswapal(target_su-buf));
if (err)
return err;
arg.buf = dsarg;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_semid_ds(target_su.buf, dsarg);
+err = host_to_target_semid_ds(tswapal(target_su-buf), dsarg);
if (err)
return err;
break;
@@ -2679,7 +2685,7 @@ static inline abi_long do_semctl(int semid, int semnum,
int cmd,
case SEM_INFO:
arg.__buf = seminfo;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_seminfo(target_su.__buf, seminfo);
+err = host_to_target_seminfo(tswapal(target_su-__buf), seminfo);
if (err)
return err;
break;
@@ -2690,6 +2696,7 @@ static inline abi_long do_semctl(int semid, int semnum,
int cmd,
ret = get_errno(semctl(semid, semnum, cmd, NULL));
break;
}
+unlock_user_struct(target_su, ptr, 0);
return ret;
}
@@ -3160,7 +3167,7 @@ static abi_long do_ipc(unsigned int call, int first,
break;
case IPCOP_semctl:
-ret = do_semctl(first, second, third, (union target_semun)(abi_ulong)
ptr);
+ret = do_semctl(first, second, third, ptr);
break;
case IPCOP_msgget:
@@ -3227,7 +3234,7 @@ static abi_long do_ipc(unsigned int call, int first,
/* IPC_* and SHM_* command values
Re: [Qemu-devel] [Qemu-trivial] [PATCH v2] configure: silence pkg-config's check for curses
Thank you! By the way (sorry if this was discussed before and is a strong decision) I'd say e-mail based workflow is of course very flexible - and very very novice-unfriendly. Dash, I had to learn git commands I'd never use in my usual workflow with local or Github repos. And, well, I was not very good with that. 10 ways with 10 options in each. You all saw my previous patch mail with fubar header and no signed-off-by string. Is there a reason you (team) don't use e.g. Github at least for trivial patches? Regards, Vadim
Re: [Qemu-devel] [PATCH] linux-user: correct semctl() and shmctl()
On 20 January 2013 21:12, Laurent Vivier laur...@vivier.eu wrote: case GETALL: case SETALL: -err = target_to_host_semarray(semid, array, target_su.array); +err = target_to_host_semarray(semid, array, + tswapal(target_su-array)); if (err) return err; This version is back to the same bug as before where the error case here skips unlocking the struct. PS: please include the version number (v2,v3,etc) in the [PATCH] subject tag so it's easier to distinguish which is the most recent version of a patch when you submit newer versions. thanks -- PMM
[Qemu-devel] [Bug 739785] Re: qemu-i386 user mode can't fork (bash: fork: Invalid argument)
I have just encountered this trying to emulate i386 on x86_64, which should dismiss any theories about ARM or MIPS. I've tried to apply the previous patch to QEMU 1.2.2 but it doesn't build. Currently trying to fix it. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/739785 Title: qemu-i386 user mode can't fork (bash: fork: Invalid argument) Status in QEMU: New Status in “qemu” package in Debian: Confirmed Bug description: Good time of day everybody, I have been trying to make usermode qemu on ARM with plugapps (archlinux) with archlinux i386 chroot to work. 1. I installed arch linux in a virtuabox and created a chroot for it with mkarchroot. Transferred it to my pogo plug into /i386/ 2. I comiled qemu-i386 static and put it into /i386/usr/bin/ ./configure --static --disable-blobs --disable-system --target-list=i386-linux-user make 3. I also compiled linux kernel 2.6.38 with CONFIG_BINFMT_MISC=y and installed it. uname -a Linux Plugbox 2.6.38 #4 PREEMPT Fri Mar 18 22:19:10 CDT 2011 armv5tel Feroceon 88FR131 rev 1 (v5l) Marvell SheevaPlug Reference Board GNU/Linux 4. Added the following options into /etc/rc.local /sbin/modprobe binfmt_misc /bin/mount binfmt_misc -t binfmt_misc /proc/sys/fs/binfmt_misc echo ':qemu-i386:M::\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00:\xff\xff\xff\xff\xff\xfe\xfe\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfb\xff\xff\xff:/usr/bin/qemu-i386:' /proc/sys/fs/binfmt_misc/register 5. Also copied ld-linux.so.3 (actually ld-2.13.so because ld- linux.so.3 is a link to that file) from /lib/ to /i386/lib/ 6.Now i chroot into /i386 and I get this: [root@Plugbox i386]# chroot . [II aI hnve ao n@P /]# pacman -Suy bash: fork: Invalid argument 7.I also downloaded linux-user-test-0.3 from qemu website and ran the test: [root@Plugbox linux-user-test-0.3]# make ./qemu-linux-user.sh [qemu-i386] ../qemu-0.14.0/i386-linux-user/qemu-i386 -L ./gnemul/qemu-i386 i386/ls -l dummyfile BUG IN DYNAMIC LINKER ld.so: dl-version.c: 210: _dl_check_map_versions: Assertion `needed != ((void *)0)' failed! make: *** [test] Error 127 To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/739785/+subscriptions
[Qemu-devel] [PATCH v2 0/3] sheepdog: unix domain socket support
This series adds support for a unix domain socket for a connection between qemu and local sheepdog server. The first two patches are cleanups for the third patch. Changes from v1: - split patch for easy review - move set_nodelay to lib/osdep.c - remove redundant error checks - add a bit more explanation to qemu-options.hx MORITA Kazutaka (3): move socket_set_nodelay to osdep.c sheepdog: use inet_connect to simplify connect code sheepdog: add support for connecting to unix domain socket block/sheepdog.c | 150 +--- gdbstub.c |5 +- include/qemu/sockets.h |1 + qemu-char.c|6 -- qemu-options.hx| 19 +++--- slirp/tcp_subr.c |3 +- util/osdep.c |6 ++ 7 files changed, 71 insertions(+), 119 deletions(-) -- 1.7.2.5
[Qemu-devel] [PATCH v2 1/3] move socket_set_nodelay to osdep.c
Signed-off-by: MORITA Kazutaka morita.kazut...@lab.ntt.co.jp
---
block/sheepdog.c | 11 +--
gdbstub.c |5 ++---
include/qemu/sockets.h |1 +
qemu-char.c|6 --
slirp/tcp_subr.c |3 +--
util/osdep.c |6 ++
6 files changed, 11 insertions(+), 21 deletions(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 3e49bb8..9746037 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -787,15 +787,6 @@ static int aio_flush_request(void *opaque)
!QLIST_EMPTY(s-pending_aio_head);
}
-static int set_nodelay(int fd)
-{
-int ret, opt;
-
-opt = 1;
-ret = setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)opt, sizeof(opt));
-return ret;
-}
-
/*
* Return a socket discriptor to read/write objects.
*
@@ -814,7 +805,7 @@ static int get_sheep_fd(BDRVSheepdogState *s)
socket_set_nonblock(fd);
-ret = set_nodelay(fd);
+ret = socket_set_nodelay(fd);
if (ret) {
error_report(%s, strerror(errno));
closesocket(fd);
diff --git a/gdbstub.c b/gdbstub.c
index 6cd26f1..4cc1812 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -2837,7 +2837,7 @@ static void gdb_accept(void)
GDBState *s;
struct sockaddr_in sockaddr;
socklen_t len;
-int val, fd;
+int fd;
for(;;) {
len = sizeof(sockaddr);
@@ -2854,8 +2854,7 @@ static void gdb_accept(void)
}
/* set short latency */
-val = 1;
-setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)val, sizeof(val));
+socket_set_nodelay(fd);
s = g_malloc0(sizeof(GDBState));
s-c_cpu = first_cpu;
diff --git a/include/qemu/sockets.h b/include/qemu/sockets.h
index 803ae17..6125bf7 100644
--- a/include/qemu/sockets.h
+++ b/include/qemu/sockets.h
@@ -34,6 +34,7 @@ int inet_aton(const char *cp, struct in_addr *ia);
int qemu_socket(int domain, int type, int protocol);
int qemu_accept(int s, struct sockaddr *addr, socklen_t *addrlen);
int socket_set_cork(int fd, int v);
+int socket_set_nodelay(int fd);
void socket_set_block(int fd);
void socket_set_nonblock(int fd);
int send_all(int fd, const void *buf, int len1);
diff --git a/qemu-char.c b/qemu-char.c
index 9ba0573..156164c 100644
--- a/qemu-char.c
+++ b/qemu-char.c
@@ -2365,12 +2365,6 @@ static void tcp_chr_telnet_init(int fd)
send(fd, (char *)buf, 3, 0);
}
-static void socket_set_nodelay(int fd)
-{
-int val = 1;
-setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)val, sizeof(val));
-}
-
static int tcp_chr_add_client(CharDriverState *chr, int fd)
{
TCPCharDriver *s = chr-opaque;
diff --git a/slirp/tcp_subr.c b/slirp/tcp_subr.c
index 1542e43..abc6662 100644
--- a/slirp/tcp_subr.c
+++ b/slirp/tcp_subr.c
@@ -429,8 +429,7 @@ tcp_connect(struct socket *inso)
setsockopt(s,SOL_SOCKET,SO_REUSEADDR,(char *)opt,sizeof(int));
opt = 1;
setsockopt(s,SOL_SOCKET,SO_OOBINLINE,(char *)opt,sizeof(int));
- opt = 1;
- setsockopt(s,IPPROTO_TCP,TCP_NODELAY,(char *)opt,sizeof(int));
+socket_set_nodelay(s);
so-so_fport = addr.sin_port;
so-so_faddr = addr.sin_addr;
diff --git a/util/osdep.c b/util/osdep.c
index 5b51a03..c408261 100644
--- a/util/osdep.c
+++ b/util/osdep.c
@@ -63,6 +63,12 @@ int socket_set_cork(int fd, int v)
#endif
}
+int socket_set_nodelay(int fd)
+{
+int v = 1;
+return setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, v, sizeof(v));
+}
+
int qemu_madvise(void *addr, size_t len, int advice)
{
if (advice == QEMU_MADV_INVALID) {
--
1.7.2.5
[Qemu-devel] [PATCH v2 3/3] sheepdog: add support for connecting to unix domain socket
This patch adds support for a unix domain socket for a connection
between qemu and local sheepdog server. You can use the unix domain
socket with the following syntax like NBD driver:
$ qemu sheepdog:unix:socket path:image name
Note that socket path must be an absolute path.
Signed-off-by: MORITA Kazutaka morita.kazut...@lab.ntt.co.jp
---
block/sheepdog.c | 37 +
qemu-options.hx | 19 +--
2 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index c287827..34685fd 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -296,7 +296,9 @@ typedef struct BDRVSheepdogState {
bool is_snapshot;
uint32_t cache_flags;
-/* It's a string of the form hostname:port */
+/* If it begins with 'unix:/', this is a UNIX domain socket. Otherwise,
+ * it's a string of the form hostname:port
+ */
char *host_spec;
int fd;
@@ -449,13 +451,25 @@ static SheepdogAIOCB *sd_aio_setup(BlockDriverState *bs,
QEMUIOVector *qiov,
static int connect_to_sdog(const char *host_spec)
{
int fd;
+const char *path;
Error *err = NULL;
if (host_spec == NULL) {
host_spec = SD_DEFAULT_ADDR_AND_PORT;
}
-fd = inet_connect(host_spec, err);
+if (strstart(host_spec, unix:, path) path[0] == '/') {
+fd = unix_connect(path, err);
+} else {
+fd = inet_connect(host_spec, err);
+
+if (err == NULL) {
+int ret = socket_set_nodelay(fd);
+if (ret 0) {
+error_report(%s, strerror(errno));
+}
+}
+}
if (err != NULL) {
qerror_report_err(err);
@@ -761,7 +775,7 @@ static int aio_flush_request(void *opaque)
*/
static int get_sheep_fd(BDRVSheepdogState *s)
{
-int ret, fd;
+int fd;
fd = connect_to_sdog(s-host_spec);
if (fd 0) {
@@ -770,13 +784,6 @@ static int get_sheep_fd(BDRVSheepdogState *s)
socket_set_nonblock(fd);
-ret = socket_set_nodelay(fd);
-if (ret) {
-error_report(%s, strerror(errno));
-closesocket(fd);
-return -errno;
-}
-
qemu_aio_set_fd_handler(fd, co_read_response, NULL, aio_flush_request, s);
return fd;
}
@@ -785,12 +792,10 @@ static int get_sheep_fd(BDRVSheepdogState *s)
* Parse a filename
*
* filename must be one of the following formats:
- * 1. [vdiname]
- * 2. [vdiname]:[snapid]
- * 3. [vdiname]:[tag]
- * 4. [hostname]:[port]:[vdiname]
- * 5. [hostname]:[port]:[vdiname]:[snapid]
- * 6. [hostname]:[port]:[vdiname]:[tag]
+ * - using TCP
+ * [hostname:port:]vdiname[:snapid or tag]
+ * - using Unix Domain Socket
+ * unix:domain-socket:vdiname[:snapid or tag]
*
* You can boot from the snapshot images by specifying `snapid` or
* `tag'.
diff --git a/qemu-options.hx b/qemu-options.hx
index 40cd683..0583b4a 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -2061,17 +2061,16 @@ devices.
Syntax for specifying a sheepdog device
@table @list
-``sheepdog:vdiname''
-
-``sheepdog:vdiname:snapid''
-
-``sheepdog:vdiname:tag''
-
-``sheepdog:host:port:vdiname''
-
-``sheepdog:host:port:vdiname:snapid''
+using TCP:
+@example
+sheepdog:[hostname:port:]vdiname[:snapid or tag]
+@end example
-``sheepdog:host:port:vdiname:tag''
+using Unix Domain Socket:
+@example
+sheepdog:unix:domain-socket:vdiname[:snapid or tag]
+@end example
+Note that domain-socket must be an absolute path.
@end table
Example
--
1.7.2.5
[Qemu-devel] [PATCH v2 2/3] sheepdog: use inet_connect to simplify connect code
This uses the form host:port for the representation of the
sheepdog server to use inet_connect.
Signed-off-by: MORITA Kazutaka morita.kazut...@lab.ntt.co.jp
---
block/sheepdog.c | 112 +-
1 files changed, 35 insertions(+), 77 deletions(-)
diff --git a/block/sheepdog.c b/block/sheepdog.c
index 9746037..c287827 100644
--- a/block/sheepdog.c
+++ b/block/sheepdog.c
@@ -20,8 +20,7 @@
#define SD_PROTO_VER 0x01
-#define SD_DEFAULT_ADDR localhost
-#define SD_DEFAULT_PORT 7000
+#define SD_DEFAULT_ADDR_AND_PORT localhost:7000
#define SD_OP_CREATE_AND_WRITE_OBJ 0x01
#define SD_OP_READ_OBJ 0x02
@@ -297,8 +296,9 @@ typedef struct BDRVSheepdogState {
bool is_snapshot;
uint32_t cache_flags;
-char *addr;
-char *port;
+/* It's a string of the form hostname:port */
+char *host_spec;
+
int fd;
CoMutex lock;
@@ -446,56 +446,22 @@ static SheepdogAIOCB *sd_aio_setup(BlockDriverState *bs,
QEMUIOVector *qiov,
return acb;
}
-static int connect_to_sdog(const char *addr, const char *port)
+static int connect_to_sdog(const char *host_spec)
{
-char hbuf[NI_MAXHOST], sbuf[NI_MAXSERV];
-int fd, ret;
-struct addrinfo hints, *res, *res0;
+int fd;
+Error *err = NULL;
-if (!addr) {
-addr = SD_DEFAULT_ADDR;
-port = SD_DEFAULT_PORT;
+if (host_spec == NULL) {
+host_spec = SD_DEFAULT_ADDR_AND_PORT;
}
-memset(hints, 0, sizeof(hints));
-hints.ai_socktype = SOCK_STREAM;
+fd = inet_connect(host_spec, err);
-ret = getaddrinfo(addr, port, hints, res0);
-if (ret) {
-error_report(unable to get address info %s, %s,
- addr, strerror(errno));
-return -errno;
+if (err != NULL) {
+qerror_report_err(err);
+error_free(err);
}
-for (res = res0; res; res = res-ai_next) {
-ret = getnameinfo(res-ai_addr, res-ai_addrlen, hbuf, sizeof(hbuf),
- sbuf, sizeof(sbuf), NI_NUMERICHOST | NI_NUMERICSERV);
-if (ret) {
-continue;
-}
-
-fd = socket(res-ai_family, res-ai_socktype, res-ai_protocol);
-if (fd 0) {
-continue;
-}
-
-reconnect:
-ret = connect(fd, res-ai_addr, res-ai_addrlen);
-if (ret 0) {
-if (errno == EINTR) {
-goto reconnect;
-}
-close(fd);
-break;
-}
-
-dprintf(connected to %s:%s\n, addr, port);
-goto success;
-}
-fd = -errno;
-error_report(failed connect to %s:%s, addr, port);
-success:
-freeaddrinfo(res0);
return fd;
}
@@ -797,9 +763,8 @@ static int get_sheep_fd(BDRVSheepdogState *s)
{
int ret, fd;
-fd = connect_to_sdog(s-addr, s-port);
+fd = connect_to_sdog(s-host_spec);
if (fd 0) {
-error_report(%s, strerror(errno));
return fd;
}
@@ -851,18 +816,15 @@ static int parse_vdiname(BDRVSheepdogState *s, const char
*filename,
}
p = q;
-/* use the first two tokens as hostname and port number. */
+/* use the first two tokens as host_spec. */
if (nr_sep = 2) {
-s-addr = p;
+s-host_spec = p;
p = strchr(p, ':');
-*p++ = '\0';
-
-s-port = p;
+p++;
p = strchr(p, ':');
*p++ = '\0';
} else {
-s-addr = NULL;
-s-port = 0;
+s-host_spec = NULL;
}
pstrcpy(vdi, SD_MAX_VDI_LEN, p);
@@ -878,7 +840,7 @@ static int parse_vdiname(BDRVSheepdogState *s, const char
*filename,
*snapid = CURRENT_VDI_ID; /* search current vdi */
}
-if (s-addr == NULL) {
+if (s-host_spec == NULL) {
g_free(q);
}
@@ -894,7 +856,7 @@ static int find_vdi_name(BDRVSheepdogState *s, char
*filename, uint32_t snapid,
unsigned int wlen, rlen = 0;
char buf[SD_MAX_VDI_LEN + SD_MAX_VDI_TAG_LEN];
-fd = connect_to_sdog(s-addr, s-port);
+fd = connect_to_sdog(s-host_spec);
if (fd 0) {
return fd;
}
@@ -1134,9 +1096,8 @@ static int sd_open(BlockDriverState *bs, const char
*filename, int flags)
s-is_snapshot = true;
}
-fd = connect_to_sdog(s-addr, s-port);
+fd = connect_to_sdog(s-host_spec);
if (fd 0) {
-error_report(failed to connect);
ret = fd;
goto out;
}
@@ -1171,7 +1132,7 @@ out:
static int do_sd_create(char *filename, int64_t vdi_size,
uint32_t base_vid, uint32_t *vdi_id, int snapshot,
-const char *addr, const char *port)
+const char *host_spec)
{
SheepdogVdiReq hdr;
SheepdogVdiRsp *rsp = (SheepdogVdiRsp *)hdr;
@@ -1179,7 +1140,7 @@ static int do_sd_create(char *filename, int64_t vdi_size,
unsigned int wlen, rlen = 0;
char buf[SD_MAX_VDI_LEN];
-fd = connect_to_sdog(addr, port);
+fd =
[Qemu-devel] [PATCH qom-cpu for-1.4 v2 1/2] target-i386: Simplify cpu_x86_find_by_name()
Catch NULL name argument early to avoid repeated checks.
Similarly, check for -cpu host early and untangle from iterating through
model definitions.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-i386/cpu.c | 22 --
1 Datei geändert, 12 Zeilen hinzugefügt(+), 10 Zeilen entfernt(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 333745b..a072712 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1321,20 +1321,22 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def,
const char *name)
{
x86_def_t *def;
-for (def = x86_defs; def; def = def-next) {
-if (name !strcmp(name, def-name)) {
-break;
-}
+if (name == NULL) {
+return -1;
}
-if (kvm_enabled() name strcmp(name, host) == 0) {
+if (kvm_enabled() strcmp(name, host) == 0) {
kvm_cpu_fill_host(x86_cpu_def);
-} else if (!def) {
-return -1;
-} else {
-memcpy(x86_cpu_def, def, sizeof(*def));
+return 0;
}
-return 0;
+for (def = x86_defs; def; def = def-next) {
+if (strcmp(name, def-name) == 0) {
+memcpy(x86_cpu_def, def, sizeof(*def));
+return 0;
+}
+}
+
+return -1;
}
/* Parse +feature,-feature,feature=foo CPU feature string
--
1.7.10.4
[Qemu-devel] [PATCH qom-cpu for-1.4 v2 0/2] target-i386: x86_defs cleanup
Hello, Here's a revamped mini-series doing cleanups of x86_defs for v1.4 before we proceed with X86CPU subclasses for v1.5. v2 leaves the cpudef hooks in place and refactors only within functions. Intended to catch this week's qom-cpu pull if there are no more objections. Regards, Andreas v1 - v2: * MAINTAINERS patch was applied already. * Redone on master. * Actually removed x86_def_t next pointer this time. * Instead of pulling -cpu host handling out of cpu_x86_find_by_name(), moved it to the front of that function. * Deferred cleanup of cpudef_setup() hooks. Cc: Eduardo Habkost ehabk...@redhat.com Cc: Igor Mammedov imamm...@redhat.com Andreas Färber (2): target-i386: Simplify cpu_x86_find_by_name() target-i386: Drop redundant list of CPU definitions target-i386/cpu.c | 42 +- 1 Datei geändert, 21 Zeilen hinzugefügt(+), 21 Zeilen entfernt(-) -- 1.7.10.4
[Qemu-devel] [PATCH qom-cpu for-1.4 v2 2/2] target-i386: Drop redundant list of CPU definitions
It is no longer needed since dropping cpudef config file support.
Cleaning this up removes knowledge about other models from x86_def_t,
in preparation for reusing x86_def_t as intermediate step towards pure
QOM X86CPU subclasses.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-i386/cpu.c | 22 ++
1 Datei geändert, 10 Zeilen hinzugefügt(+), 12 Zeilen entfernt(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index a072712..ddd7b98 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -338,7 +338,6 @@ static void add_flagname_to_bitmaps(const char *flagname,
}
typedef struct x86_def_t {
-struct x86_def_t *next;
const char *name;
uint32_t level;
uint32_t vendor1, vendor2, vendor3;
@@ -396,11 +395,7 @@ typedef struct x86_def_t {
#define TCG_SVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP)
-/* maintains list of cpu model definitions
- */
-static x86_def_t *x86_defs = {NULL};
-
-/* built-in cpu model definitions (deprecated)
+/* built-in CPU model definitions
*/
static x86_def_t builtin_x86_defs[] = {
{
@@ -1320,6 +1315,7 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visitor
*v, void *opaque,
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *name)
{
x86_def_t *def;
+int i;
if (name == NULL) {
return -1;
@@ -1329,7 +1325,8 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def,
const char *name)
return 0;
}
-for (def = x86_defs; def; def = def-next) {
+for (i = 0; i ARRAY_SIZE(builtin_x86_defs); i++) {
+def = builtin_x86_defs[i];
if (strcmp(name, def-name) == 0) {
memcpy(x86_cpu_def, def, sizeof(*def));
return 0;
@@ -1515,8 +1512,10 @@ void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
{
x86_def_t *def;
char buf[256];
+int i;
-for (def = x86_defs; def; def = def-next) {
+for (i = 0; i ARRAY_SIZE(builtin_x86_defs); i++) {
+def = builtin_x86_defs[i];
snprintf(buf, sizeof(buf), %s, def-name);
(*cpu_fprintf)(f, x86 %16s %-48s\n, buf, def-model_id);
}
@@ -1538,11 +1537,13 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error
**errp)
{
CpuDefinitionInfoList *cpu_list = NULL;
x86_def_t *def;
+int i;
-for (def = x86_defs; def; def = def-next) {
+for (i = 0; i ARRAY_SIZE(builtin_x86_defs); i++) {
CpuDefinitionInfoList *entry;
CpuDefinitionInfo *info;
+def = builtin_x86_defs[i];
info = g_malloc0(sizeof(*info));
info-name = g_strdup(def-name);
@@ -1663,7 +1664,6 @@ void x86_cpudef_setup(void)
for (i = 0; i ARRAY_SIZE(builtin_x86_defs); ++i) {
x86_def_t *def = builtin_x86_defs[i];
-def-next = x86_defs;
/* Look for specific cpudef models that */
/* have the QEMU version in .model_id */
@@ -1676,8 +1676,6 @@ void x86_cpudef_setup(void)
break;
}
}
-
-x86_defs = def;
}
}
--
1.7.10.4
Re: [Qemu-devel] [PATCH 16/18] hw: add QEMU model for Faraday RTCtimer
Hi Konrad:
Thanks for the information, I'm now studying the QOM.
And when I finished the reading. I'll send out new patches later.
Best Regards
Dante Su
-Original Message-
From: qemu-devel-bounces+dantesu=faraday-tech@nongnu.org
[mailto:qemu-devel-bounces+dantesu=faraday-tech@nongnu.org] On Behalf Of
KONRAD Frederic
Sent: Friday, January 18, 2013 4:44 PM
To: Dante Kuo-Jung Su(蘇國榮)
Cc: peter.mayd...@linaro.org; qemu-devel@nongnu.org; Andreas Färber;
p...@codesourcery.com
Subject: Re: [Qemu-devel] [PATCH 16/18] hw: add QEMU model for Faraday RTCtimer
On 18/01/2013 07:32, Dante wrote:
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/ftrtc011.c | 308
+
1 file changed, 308 insertions(+)
create mode 100644 hw/ftrtc011.c
diff --git a/hw/ftrtc011.c b/hw/ftrtc011.c new file mode 100644 index
000..466cbb6
--- /dev/null
+++ b/hw/ftrtc011.c
@@ -0,0 +1,308 @@
+/*
+ * QEMU model of the FTRTC011 RTC Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su dant...@faraday-tech.com
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a copy
+ * of this software and associated documentation files (the
+Software), to deal
+ * in the Software without restriction, including without limitation
+the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense,
+and/or sell
+ * copies of the Software, and to permit persons to whom the Software
+is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
+SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
+OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include sysbus.h
+#include sysemu/sysemu.h
+#include qemu/timer.h
+
+/* Hardware registers */
+#define REG_SEC0x00
+#define REG_MIN0x04
+#define REG_HOUR0x08
+#define REG_DAY0x0C
+
+#define REG_ALARM_SEC0x10
+#define REG_ALARM_MIN0x14
+#define REG_ALARM_HOUR0x18
+
+#define REG_CR0x20
+#define REG_WSEC0x24
+#define REG_WMIN0x28
+#define REG_WHOUR0x2C
+#define REG_WDAY0x30
+#define REG_ISR0x34
+
+#define REG_REV0x3C
+#define REG_CURRENT0x44
+
+enum ftrtc011_irqpin {
+IRQ_ALARM_LEVEL = 0,
+IRQ_ALARM_EDGE,
+IRQ_SEC,
+IRQ_MIN,
+IRQ_HOUR,
+IRQ_DAY,
+};
+
+typedef struct {
+SysBusDevice busdev;
+MemoryRegion mmio;
+
+qemu_irq irq[6];
+
+QEMUTimer *qtimer;
+
+uint8_t sec;
+uint8_t min;
+uint8_t hr;
+uint32_t day;
+
+uint8_t alarm_sec;
+uint8_t alarm_min;
+uint8_t alarm_hr;
+
+uint32_t cr;
+uint32_t isr;
+
+} ftrtc011_state;
+
+/* Update interrupts. */
+static inline void ftrtc011_update_irq(ftrtc011_state *s) {
+uint32_t mask = ((s-cr 1) 0x1f) s-isr;
+
+qemu_set_irq(s-irq[IRQ_ALARM_LEVEL], (mask 0x10) ? 1 : 0);
+
+if (mask) {
+if (mask 0x01)
+qemu_irq_pulse(s-irq[IRQ_SEC]);
+if (mask 0x02)
+qemu_irq_pulse(s-irq[IRQ_MIN]);
+if (mask 0x04)
+qemu_irq_pulse(s-irq[IRQ_HOUR]);
+if (mask 0x08)
+qemu_irq_pulse(s-irq[IRQ_DAY]);
+if (mask 0x10)
+qemu_irq_pulse(s-irq[IRQ_ALARM_EDGE]);
+}
+}
+
+static uint64_t ftrtc011_mem_read(void *opaque, hwaddr addr, unsigned
+int size) {
+ftrtc011_state *s = opaque;
+uint32_t rc = 0;
+
+switch (addr) {
+case REG_SEC:
+return s-sec;
+case REG_MIN:
+return s-min;
+case REG_HOUR:
+return s-hr;
+case REG_DAY:
+return s-day;
+case REG_ALARM_SEC:
+return s-alarm_sec;
+case REG_ALARM_MIN:
+return s-alarm_min;
+case REG_ALARM_HOUR:
+return s-alarm_hr;
+case REG_CR:
+return s-cr;
+case REG_ISR:
+return s-isr;
+case REG_REV:
+return 0x0001;
+case REG_CURRENT:
+return (s-day 17) | (s-hr 12) | (s-min 6) | (s-sec);
+default:
+break;
+}
+
+return rc;
+}
+
+static void ftrtc011_mem_write(void *opaque, hwaddr addr, uint64_t
+val, unsigned int size) {
+ftrtc011_state *s = opaque;
+
+switch (addr) {
+case REG_ALARM_SEC:
+s-alarm_sec =
Re: [Qemu-devel] [PATCH] target-arm: add Faraday ARMv5TE processors support
* ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE) All the single core RISC listed above are included in this patch. And there are two Faraday CP15 extensions (AUX and I/D-Scratchpad) have been implemented as NOP. Is a NOP appropriate? Should you at least read the value back? Not necessary, because 1. Auxiliary Control Register: It's used to alter the cache behaviors which is not important to QEMU. For example, it could: a) Turn-off the d-cache write allocations upon wirte missed. (By default, FA626TE is configured as Read/Write Allocation for D-Cache; which leads to a very poor memcpy speed while compared with general ARM processors which are Read-Allocation Only by default) 2. I/D-Scratchpad Configuration Register: It's used to setup a memory region for I/D-scratchpad memory; A I/D-scratchpad is a dedicated cache memory for a specific region of code/data(I/D), while I/D-caches work with random locality. And thus, it's also meaningless to QEMU. The reason why I add these two CP15 instructions to QEMU, is to prevent it hangs up without any notifications upon executing these instructions; I've seen such issue at QEMU-1.3.0, so I think it would be better if we could put these dummy registers into the helper.c Best Regards Dante Su -Original Message- From: Paul Brook [mailto:p...@codesourcery.com] Sent: Friday, January 18, 2013 5:45 PM To: Dante Kuo-Jung Su(蘇國榮) Cc: qemu-devel@nongnu.org; peter.mayd...@linaro.org Subject: Re: [PATCH] target-arm: add Faraday ARMv5TE processors support * ARMv5TE series (FA606TE, FA626TE, FA616TE, FA726TE) All the single core RISC listed above are included in this patch. And there are two Faraday CP15 extensions (AUX and I/D-Scratchpad) have been implemented as NOP. Is a NOP appropriate? Should you at least read the value back? * Confidentiality Notice This electronic message and any attachments may contain confidential and legally privileged information or information which is otherwise protected from disclosure. If you are not the intended recipient,please do not disclose the contents, either in whole or in part, to anyone,and immediately delete the message and any attachments from your computer system and destroy all hard copies. Thank you for your cooperation. ** * This sort of disclaimer is completely inappropriate for public mailing lists, and I'm unwilling to touch anything subject to these restrictions. As instructed I have deleted all your other email unread. Paul * Confidentiality Notice This electronic message and any attachments may contain confidential and legally privileged information or information which is otherwise protected from disclosure. If you are not the intended recipient,please do not disclose the contents, either in whole or in part, to anyone,and immediately delete the message and any attachments from your computer system and destroy all hard copies. Thank you for your cooperation. ***
Re: [Qemu-devel] [PATCH 16/18] hw: add QEMU model for Faraday RTCtimer
Sorry for the inconveniences, our e-mail server has a limitation on the rate of
sending mails.
It prevents the git-send-email to do that for me. I'll try to use gmail later
when I get the QOM issues fixed.
Best Regards
Dante Su
-Original Message-
From: qemu-devel-bounces+dantesu=faraday-tech@nongnu.org
[mailto:qemu-devel-bounces+dantesu=faraday-tech@nongnu.org] On Behalf Of
Andreas Farber
Sent: Friday, January 18, 2013 6:43 PM
To: Dante Kuo-Jung Su(蘇國榮)
Cc: peter.mayd...@linaro.org; p...@codesourcery.com; Paolo Bonzini;
qemu-devel@nongnu.org; KONRAD Frédéric
Subject: Re: [Qemu-devel] [PATCH 16/18] hw: add QEMU model for Faraday RTCtimer
Kuo-Jung, please thread your messages together (e.g., using
git-send-email) and prepend a cover letter, right now this is a badly
reviewable mess of individual patches on the list.
Am 18.01.2013 09:44, schrieb KONRAD Frédéric:
On 18/01/2013 07:32, Dante wrote:
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
---
hw/ftrtc011.c | 308
+
1 file changed, 308 insertions(+)
create mode 100644 hw/ftrtc011.c
diff --git a/hw/ftrtc011.c b/hw/ftrtc011.c new file mode 100644 index
000..466cbb6
--- /dev/null
+++ b/hw/ftrtc011.c
@@ -0,0 +1,308 @@
+/*
+ * QEMU model of the FTRTC011 RTC Timer
+ *
+ * Copyright (C) 2012 Faraday Technology
+ * Copyright (C) 2012 Dante Su dant...@faraday-tech.com
+ *
+ * Permission is hereby granted, free of charge, to any person
obtaining a copy
+ * of this software and associated documentation files (the
Software), to deal
+ * in the Software without restriction, including without limitation
the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell
+ * copies of the Software, and to permit persons to whom the
+ Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT
SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include sysbus.h
+#include sysemu/sysemu.h
+#include qemu/timer.h
+
+/* Hardware registers */
+#define REG_SEC0x00
+#define REG_MIN0x04
+#define REG_HOUR0x08
+#define REG_DAY0x0C
+
+#define REG_ALARM_SEC0x10
+#define REG_ALARM_MIN0x14
+#define REG_ALARM_HOUR0x18
+
+#define REG_CR0x20
+#define REG_WSEC0x24
+#define REG_WMIN0x28
+#define REG_WHOUR0x2C
+#define REG_WDAY0x30
+#define REG_ISR0x34
+
+#define REG_REV0x3C
+#define REG_CURRENT0x44
You would be well advised to put these constants into their own header file so
that they can be reused for qtest test cases. Please take a look at the
existing rtc code and test cases.
+
+enum ftrtc011_irqpin {
+IRQ_ALARM_LEVEL = 0,
+IRQ_ALARM_EDGE,
+IRQ_SEC,
+IRQ_MIN,
+IRQ_HOUR,
+IRQ_DAY,
+};
+
+typedef struct {
Please name the struct, usually like the typedef.
+SysBusDevice busdev;
parent_obj please and please separate from the remaining fields.
+MemoryRegion mmio;
+
+qemu_irq irq[6];
+
+QEMUTimer *qtimer;
+
+uint8_t sec;
+uint8_t min;
+uint8_t hr;
+uint32_t day;
+
+uint8_t alarm_sec;
+uint8_t alarm_min;
+uint8_t alarm_hr;
+
+uint32_t cr;
+uint32_t isr;
+
+} ftrtc011_state;
CamelCase please.
These comments may apply to other patches in the series as well, please check
on your own.
+
+/* Update interrupts. */
+static inline void ftrtc011_update_irq(ftrtc011_state *s) {
+uint32_t mask = ((s-cr 1) 0x1f) s-isr;
+
+qemu_set_irq(s-irq[IRQ_ALARM_LEVEL], (mask 0x10) ? 1 : 0);
+
+if (mask) {
+if (mask 0x01)
Please use scripts/checkpatch.pl, it will complain about missing braces for if
statements. You can automate this as a commit hook:
http://blog.vmsplice.net/2011/03/how-to-automatically-run-checkpatchpl.html
+qemu_irq_pulse(s-irq[IRQ_SEC]);
+if (mask 0x02)
+qemu_irq_pulse(s-irq[IRQ_MIN]);
+if (mask 0x04)
+qemu_irq_pulse(s-irq[IRQ_HOUR]);
+if (mask 0x08)
+qemu_irq_pulse(s-irq[IRQ_DAY]);
+if (mask 0x10)
+qemu_irq_pulse(s-irq[IRQ_ALARM_EDGE]);
+}
+}
+
+static uint64_t ftrtc011_mem_read(void *opaque, hwaddr addr,
+unsigned
int
[Qemu-devel] wrong argument to qemu_flush_queued_packets() in network frontends ?
While running qemu 1.3.0 with the following network-related flags:
-net nic -net tap,ifname=tap0,script=''
I encountered the same problem (should be common to several
frontends, e.g. e100, eepro100, virtio-net, xen_nic):
in net/tap.c :: tap_send(), if qemu_send_packet_async() returns 0
(e.g. because the NIC has no buffers available)
traffic stops, despite the fact that the frontend will try to pull
queued packets when the receive ring is updated.
Upon investigation, it turns out that the backend code does
size = qemu_send_packet_async(s-nc, buf, size, tap_send_completed);
if (size == 0) {
tap_read_poll(s, 0);
and the arguments are
s-nc.name = tap.0
s-nc.peer-name = hub0port1
s-nc.send_queue = 0x7f40b2f61e20
s-nc.peer-send_queue = 0x7f40b2f63690 --- enqueued here
whereis the frontend is trying to pull from a different queue
qemu_flush_queued_packets(s-nic-nc);
with arguments
s-nic-nc.name = e1000.0
s-nic-nc.peer-name = hub0port0 --- try to flush this
s-nic-nc.send_queue = 0x7f40b3008ae0
s-nic-nc.peer-send_queue = 0x7f40b2f63660
Note, regular traffic flows correctly across the hub,
but qemu_flush_queued_packets() seems to try and pull
from the wrong place.
Any idea how to fix this (other than the inefficient solution
of leaving read_poll=1 in the frontend)
cheers
luigi
Re: [Qemu-devel] [PATCH for-1.4 00/12] target-i386: Fix APIC-ID-based topology (v4)
在 2013-01-18五的 12:49 -0200，Eduardo Habkost写道： On Fri, Jan 18, 2013 at 02:54:41PM +0800, li guang wrote: 在 2013-01-17四的 18:59 -0200，Eduardo Habkost写道： I am hoping to get this bug fixed in 1.4. I didn't get much feedback on the RFC I sent last week, though. Igor argued that APIC ID should be set by the board and not by the CPU itself, per Intel's SPEC, seems APIC ID really based on design of board. (refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B 3C): System Programming Guide chapter 10.4.6) but, actually, it maybe meaningless for emulation. after go though your patches, I can't capture the purpose you do a topology map between APIC ID and cpu_index, (sorry for that) can you help to clear that? See the documents mentioned on PATCH 11/12: +/* This file implements the APIC-ID-based CPU topology enumeration logic, + * documented at the following document: + * Intel® 64 Architecture Processor Topology Enumeration + * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ + * + * This code should be compatible with AMD's Extended Method described at: + * AMD CPUID Specification (Publication #25481) + * Section 3: Multiple Core Calcuation + * as long as: + * nr_threads is set to 1; + * OFFSET_IDX is assumed to be 0; + * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). + */ If we don't generate the APIC IDs properly, identification of CPU sockets/cores/threads is broken. e.g. today -smp 12,cores=3,threads=2 currently ends up exposing 4 cores on the first socket, and 2 cores in the second one, because the APIC IDs are generated sequentially instead of being based on package/core/thread IDs. okay, Thanks! but I am not doing that because: - I want to keep the bug fix simple and isolated as we are past soft freeze - I believe the creator of the CPU object shouldn't be forced to provide the APIC ID, so the APIC ID is not unnecessarily exposed on the CPU hotplug device_add interface in the future - The APIC ID _is_ set by the CPU itself (because each CPU package may have multiple core/threads, and each core/thread has a different APIC ID). What needs to be provided by the board to the CPU package in the future is the package ID and the bit width of the core/thread IDs. Git tree for reference: git://github.com/ehabkost/qemu-hacks.git apicid-topology.v5 https://github.com/ehabkost/qemu-hacks/tree/apicid-topology.v5 Eduardo Habkost (12): kvm: Add fake KVM_FEATURE_CLOCKSOURCE_STABLE_BIT for builds withou KVM target-i386: Don't set any KVM flag by default if KVM is disabled pc: Reverse pc_init_pci() compatibility logic kvm: Create kvm_arch_vcpu_id() function target-i386: kvm: Set vcpu_id to APIC ID instead of CPU index fw_cfg: Remove FW_CFG_MAX_CPUS from fw_cfg_init() target-i386/cpu: Introduce apic_id_for_cpu() function cpus.h: Make constant smp_cores/smp_threads available on *-user pc: Set fw_cfg data based on APIC ID calculation tests: Support target-specific unit tests target-i386: Topology APIC ID utility functions pc: Generate APIC IDs according to CPU topology hw/fw_cfg.c| 1 - hw/pc.c| 44 +--- hw/pc_piix.c | 26 +++--- hw/ppc_newworld.c | 1 + hw/ppc_oldworld.c | 1 + hw/sun4m.c | 3 ++ hw/sun4u.c | 1 + include/sysemu/cpus.h | 7 +++ include/sysemu/kvm.h | 4 ++ kvm-all.c | 2 +- target-i386/cpu.c | 52 +++ target-i386/cpu.h | 5 +- target-i386/kvm.c | 6 +++ target-i386/topology.h | 133 + target-ppc/kvm.c | 5 ++ target-s390x/kvm.c | 5 ++ tests/.gitignore | 1 + tests/Makefile | 21 +++- tests/test-x86-cpuid.c | 101 + 19 files changed, 391 insertions(+), 28 deletions(-) create mode 100644 target-i386/topology.h create mode 100644 tests/test-x86-cpuid.c -- regards! li guang -- regards! li guang
Re: [Qemu-devel] [PATCH 2/5] target-i386: replace uint32_t vendor fields by vendor string in x86_def_t
在 2013-01-18五的 14:40 +0100，Igor Mammedov写道：
On Fri, 18 Jan 2013 15:12:36 +0800
li guang lig.f...@cn.fujitsu.com wrote:
在 2013-01-17四的 16:16 +0100，Igor Mammedov写道：
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index ce914da..ab80dbe 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -45,6 +45,18 @@
#include hw/apic_internal.h
#endif
+static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
+ uint32_t vendor2, uint32_t vendor3)
sorry, but I should say _vendor_words2str seems not so suitable,
it's mostly not a convertor, but a compactor, so I suggest to use
_vendor_str directly.
I think that _vendor_words2str describes more clearly what function does,
regardless whether it is conversion or compaction. _vendor_str seems more
ambiguous though. But if you insist, I can change to it.
No, _vendor_words2str is OK, though I still prefer _vendor_str
stubbornly :)
BTW: it's not just copying, it copies from little endinan words to string.
+{
+int i;
+for (i = 0; i 4; i++) {
+dst[i] = vendor1 (8 * i);
+dst[i + 4] = vendor2 (8 * i);
+dst[i + 8] = vendor3 (8 * i);
+}
+dst[CPUID_VENDOR_SZ] = '\0';
+}
+
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -537,14 +537,14 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_VENDOR_INTEL_1 0x756e6547 /* Genu */
#define CPUID_VENDOR_INTEL_2 0x49656e69 /* ineI */
#define CPUID_VENDOR_INTEL_3 0x6c65746e /* ntel */
+#define CPUID_VENDOR_INTEL GenuineIntel
you said the reason you did not remove _VENDOR_INTEL_{1,2,3}
is they're used somewhere, did you mean target-i386/translate.c
for sysenter instruction?
if it is, why can't we also remove them there?
That would imply conversion of CPUX86State to using string for cpuid_vendor
instead of currents words which would mean to do conversion every time cpuid
instruction is called in guest. I'd rather keep current cpuid_vendor{1,2,3}
in CPUX86State.
Purpose of this patch is to switch from direct field copying when initializing
CPU to using property setter.
If we ever decide to convert CPUX86State.cpuid_vendor{1,2,3} into string, it
could be done by a separate patch.
In addition, wouldn't strcmp() there be less effective performance wise,
versus just number comparison if we would convert
CPUX86State.cpuid_vendor{1,2,3} to string?
that's true.
Thanks!
#define CPUID_VENDOR_AMD_1 0x68747541 /* Auth */
#define CPUID_VENDOR_AMD_2 0x69746e65 /* enti */
#define CPUID_VENDOR_AMD_3 0x444d4163 /* cAMD */
+#define CPUID_VENDOR_AMD AuthenticAMD
-#define CPUID_VENDOR_VIA_1 0x746e6543 /* Cent */
-#define CPUID_VENDOR_VIA_2 0x48727561 /* aurH */
-#define CPUID_VENDOR_VIA_3 0x736c7561 /* auls */
+#define CPUID_VENDOR_VIA CentaurHauls
#define CPUID_MWAIT_IBE (1 1) /* Interrupts can exit capability */
#define CPUID_MWAIT_EMX (1 0) /* enumeration supported */
--
regards!
li guang
[Qemu-devel] [RFC qom-cpu v2 0/2] target-sh4: SuperHCPU subclasses
Hello, This series introduces SuperH CPU subclasses. The first conversion to QOM patch had used a declarative approach reusing sh4_def_t as SuperHCPUInfo. This approach now uses imperative instance_init functions. To preserve -cpu ? output and case-insensitivity, distinct name and type name are used, but allowing use of the type name as done for alpha. TODO: guard against abstract types (may apply to other targets as well) TODO: move class - name lookup to cpu.c? This series in context: + qom-cpu cleanups and bugfixes being queued for 1.4 + CPUState QOM realizefn and initfn RFC for 1.5 / qom-cpu-next ~ SuperHCPU subclasses (this series) - SH7750 QOM'ification (to be rebased) - cross-target refactoring of cpu_init() and realized behavior (TBD) Available for testing at: git://github.com/afaerber/qemu-cpu.git qom-cpu-sh4-classes.v2 https://github.com/afaerber/qemu-cpu/commits/qom-cpu-sh4-classes.v2 Regards, Andreas v2: * Fixed bug in class name comparison, spotted by Igor. * Refactored name - ObjectClass mapping into new function. * Moved realizefn patch into CPUState series, rebased. v1 - preview on GitHub: * Redone, using combination of initfn and class_init instead of SuperHCPUInfo. * Adopted naming scheme suggested by Eduardo. * Split out SuperHCPUClass field movements into separate patch. Cc: Aurélien Jarno aurel...@aurel32.net Cc: Igor Mammedov imamm...@redhat.com Cc: Eduardo Habkost ehabk...@redhat.com Andreas Färber (2): target-sh4: Introduce SuperHCPU subclasses target-sh4: Move PVR/PRR/CVR into SuperHCPUClass hw/sh7750.c| 10 ++-- target-sh4/cpu-qom.h | 13 + target-sh4/cpu.c | 124 +++- target-sh4/cpu.h |3 -- target-sh4/translate.c | 94 +--- 5 Dateien geändert, 175 Zeilen hinzugefügt(+), 69 Zeilen entfernt(-) -- 1.7.10.4
[Qemu-devel] [RFC qom-cpu v2 1/2] target-sh4: Introduce SuperHCPU subclasses
Store legacy name in SuperHCPUClass for -cpu ? and for case-insensitive
class lookup.
List CPUs by iterating over TYPE_SUPERH_CPU subclasses.
Signed-off-by: Andreas Färber afaer...@suse.de
---
target-sh4/cpu-qom.h |7 +++
target-sh4/cpu.c | 124 +++-
target-sh4/translate.c | 94 +---
3 Dateien geändert, 162 Zeilen hinzugefügt(+), 63 Zeilen entfernt(-)
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index d368db1..8326ceb 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -24,6 +24,10 @@
#define TYPE_SUPERH_CPU superh-cpu
+#define TYPE_SH7750R_CPU sh7750r- TYPE_SUPERH_CPU
+#define TYPE_SH7751R_CPU sh7751r- TYPE_SUPERH_CPU
+#define TYPE_SH7785_CPU sh7785- TYPE_SUPERH_CPU
+
#define SUPERH_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(SuperHCPUClass, (klass), TYPE_SUPERH_CPU)
#define SUPERH_CPU(obj) \
@@ -35,6 +39,7 @@
* SuperHCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
+ * @name: The name.
*
* A SuperH CPU model.
*/
@@ -45,6 +50,8 @@ typedef struct SuperHCPUClass {
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
+
+const char *name;
} SuperHCPUClass;
/**
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 223008a..80804ef 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -53,6 +53,125 @@ static void superh_cpu_reset(CPUState *s)
set_default_nan_mode(1, env-fp_status);
}
+typedef struct SuperHCPUListState {
+fprintf_function cpu_fprintf;
+FILE *file;
+} SuperHCPUListState;
+
+/* Sort alphabetically by type name. */
+static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
+{
+ObjectClass *class_a = (ObjectClass *)a;
+ObjectClass *class_b = (ObjectClass *)b;
+const char *name_a, *name_b;
+
+name_a = object_class_get_name(class_a);
+name_b = object_class_get_name(class_b);
+return strcmp(name_a, name_b);
+}
+
+static void superh_cpu_list_entry(gpointer data, gpointer user_data)
+{
+ObjectClass *oc = data;
+SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+SuperHCPUListState *s = user_data;
+
+(*s-cpu_fprintf)(s-file, %s\n,
+ scc-name);
+}
+
+void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
+{
+SuperHCPUListState s = {
+.cpu_fprintf = cpu_fprintf,
+.file = f,
+};
+GSList *list;
+
+list = object_class_get_list(TYPE_SUPERH_CPU, false);
+list = g_slist_sort(list, superh_cpu_list_compare);
+g_slist_foreach(list, superh_cpu_list_entry, s);
+g_slist_free(list);
+}
+
+static void sh7750r_cpu_initfn(Object *obj)
+{
+SuperHCPU *cpu = SUPERH_CPU(obj);
+CPUSH4State *env = cpu-env;
+
+env-id = SH_CPU_SH7750R;
+env-pvr = 0x0005;
+env-prr = 0x0100;
+env-cvr = 0x0011;
+env-features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7750r_class_init(ObjectClass *oc, void *data)
+{
+SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+scc-name = SH7750R;
+}
+
+static const TypeInfo sh7750r_type_info = {
+.name = TYPE_SH7750R_CPU,
+.parent = TYPE_SUPERH_CPU,
+.class_init = sh7750r_class_init,
+.instance_init = sh7750r_cpu_initfn,
+};
+
+static void sh7751r_cpu_initfn(Object *obj)
+{
+SuperHCPU *cpu = SUPERH_CPU(obj);
+CPUSH4State *env = cpu-env;
+
+env-id = SH_CPU_SH7751R;
+env-pvr = 0x04050005;
+env-prr = 0x0113;
+env-cvr = 0x0011; /* Neutered caches, should be 0x2048 */
+env-features = SH_FEATURE_BCR3_AND_BCR4;
+}
+
+static void sh7751r_class_init(ObjectClass *oc, void *data)
+{
+SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+scc-name = SH7751R;
+}
+
+static const TypeInfo sh7751r_type_info = {
+.name = TYPE_SH7751R_CPU,
+.parent = TYPE_SUPERH_CPU,
+.class_init = sh7751r_class_init,
+.instance_init = sh7751r_cpu_initfn,
+};
+
+static void sh7785_cpu_initfn(Object *obj)
+{
+SuperHCPU *cpu = SUPERH_CPU(obj);
+CPUSH4State *env = cpu-env;
+
+env-id = SH_CPU_SH7785;
+env-pvr = 0x10300700;
+env-prr = 0x0200;
+env-cvr = 0x71440211;
+env-features = SH_FEATURE_SH4A;
+}
+
+static void sh7785_class_init(ObjectClass *oc, void *data)
+{
+SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
+
+scc-name = SH7785;
+}
+
+static const TypeInfo sh7785_type_info = {
+.name = TYPE_SH7785_CPU,
+.parent = TYPE_SUPERH_CPU,
+.class_init = sh7785_class_init,
+.instance_init = sh7785_cpu_initfn,
+};
+
static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
{
SuperHCPU *cpu = SUPERH_CPU(dev);
@@ -96,7 +215,7 @@ static const TypeInfo superh_cpu_type_info = {
.parent = TYPE_CPU,
.instance_size = sizeof(SuperHCPU),
.instance_init = superh_cpu_initfn,
-.abstract = false,
+.abstract = true,
.class_size = sizeof(SuperHCPUClass),
.class_init = superh_cpu_class_init,
};
[Qemu-devel] [RFC qom-cpu v2 2/2] target-sh4: Move PVR/PRR/CVR into SuperHCPUClass
They are never changed once initialized, and moving them to the class
will allow to inspect them before instantiating.
Signed-off-by: Andreas Färber afaer...@suse.de
---
hw/sh7750.c | 10 +++---
target-sh4/cpu-qom.h |6 ++
target-sh4/cpu.c | 18 +-
target-sh4/cpu.h |3 ---
4 Dateien geändert, 22 Zeilen hinzugefügt(+), 15 Zeilen entfernt(-)
diff --git a/hw/sh7750.c b/hw/sh7750.c
index 666f865..2259b59 100644
--- a/hw/sh7750.c
+++ b/hw/sh7750.c
@@ -255,6 +255,7 @@ static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
{
SH7750State *s = opaque;
+SuperHCPUClass *scc;
switch (addr) {
case SH7750_BCR1_A7:
@@ -288,11 +289,14 @@ static uint32_t sh7750_mem_readl(void *opaque, hwaddr
addr)
case SH7750_CCR_A7:
return s-ccr;
case 0x1f30: /* Processor version */
- return s-cpu-pvr;
+scc = SUPERH_CPU_GET_CLASS(s-cpu);
+return scc-pvr;
case 0x1f40: /* Cache version */
- return s-cpu-cvr;
+scc = SUPERH_CPU_GET_CLASS(s-cpu);
+return scc-cvr;
case 0x1f44: /* Processor revision */
- return s-cpu-prr;
+scc = SUPERH_CPU_GET_CLASS(s-cpu);
+return scc-prr;
default:
error_access(long read, addr);
abort();
diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h
index 8326ceb..b264be7 100644
--- a/target-sh4/cpu-qom.h
+++ b/target-sh4/cpu-qom.h
@@ -40,6 +40,9 @@
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
* @name: The name.
+ * @pvr: Processor Version Register
+ * @prr: Processor Revision Register
+ * @cvr: Cache Version Register
*
* A SuperH CPU model.
*/
@@ -52,6 +55,9 @@ typedef struct SuperHCPUClass {
void (*parent_reset)(CPUState *cpu);
const char *name;
+uint32_t pvr;
+uint32_t prr;
+uint32_t cvr;
} SuperHCPUClass;
/**
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c
index 80804ef..d4ba957 100644
--- a/target-sh4/cpu.c
+++ b/target-sh4/cpu.c
@@ -100,9 +100,6 @@ static void sh7750r_cpu_initfn(Object *obj)
CPUSH4State *env = cpu-env;
env-id = SH_CPU_SH7750R;
-env-pvr = 0x0005;
-env-prr = 0x0100;
-env-cvr = 0x0011;
env-features = SH_FEATURE_BCR3_AND_BCR4;
}
@@ -111,6 +108,9 @@ static void sh7750r_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc-name = SH7750R;
+scc-pvr = 0x0005;
+scc-prr = 0x0100;
+scc-cvr = 0x0011;
}
static const TypeInfo sh7750r_type_info = {
@@ -126,9 +126,6 @@ static void sh7751r_cpu_initfn(Object *obj)
CPUSH4State *env = cpu-env;
env-id = SH_CPU_SH7751R;
-env-pvr = 0x04050005;
-env-prr = 0x0113;
-env-cvr = 0x0011; /* Neutered caches, should be 0x2048 */
env-features = SH_FEATURE_BCR3_AND_BCR4;
}
@@ -137,6 +134,9 @@ static void sh7751r_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc-name = SH7751R;
+scc-pvr = 0x04050005;
+scc-prr = 0x0113;
+scc-cvr = 0x0011; /* Neutered caches, should be 0x2048 */
}
static const TypeInfo sh7751r_type_info = {
@@ -152,9 +152,6 @@ static void sh7785_cpu_initfn(Object *obj)
CPUSH4State *env = cpu-env;
env-id = SH_CPU_SH7785;
-env-pvr = 0x10300700;
-env-prr = 0x0200;
-env-cvr = 0x71440211;
env-features = SH_FEATURE_SH4A;
}
@@ -163,6 +160,9 @@ static void sh7785_class_init(ObjectClass *oc, void *data)
SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
scc-name = SH7785;
+scc-pvr = 0x10300700;
+scc-prr = 0x0200;
+scc-cvr = 0x71440211;
}
static const TypeInfo sh7785_type_info = {
diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 49dcd9e..f805778 100644
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -179,9 +179,6 @@ typedef struct CPUSH4State {
CPU_COMMON
int id;/* CPU model */
-uint32_t pvr; /* Processor Version Register */
-uint32_t prr; /* Processor Revision Register */
-uint32_t cvr; /* Cache Version Register */
void *intc_handle;
int in_sleep; /* SR_BL ignored during sleep */
--
1.7.10.4
Re: [Qemu-devel] [PATCH for-1.4 03/12] pc: Reverse pc_init_pci() compatibility logic
Am 17.01.2013 21:59, schrieb Eduardo Habkost:
Currently, the pc-1.4 machine init function enables PV EOI and then
calls the pc-1.2 machine init function. The problem with this approach
is that now we can't enable any additional compatibility code inside the
pc-1.2 init function because it would end up enabling the compatibility
behavior on pc-1.3 and pc-1.4 as well.
This reverses the logic so that the pc-1.2 machine init function will
disable PV EOI, and then call the pc-1.4 machine init function.
This way we can change older machine-types to enable compatibility
behavior, and the newer machine-types (pc-1.3, pc-q35-1.4 and
pc-i440fx-1.4) would just use the default behavior.
(This means that one nice side-effect of this change is that pc-q35-1.4
will get PV EOI enabled by default, too)
It would be interesting to eventually change pc_init_pci_no_kvmclock()
and pc_init_isa() to reuse pc_init_pci_1_2() as well (so we don't need
to duplicate compatibility code on those two functions). But this will
be probably much easier to do after we create a PCInitArgs struct for
the PC initialization arguments, and/or after we use global-properties
to implement the compatibility modes present in pc_init_pci_1_2().
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
Cc: k...@vger.kernel.org
Cc: Michael S. Tsirkin m...@redhat.com
Cc: Gleb Natapov g...@redhat.com
Cc: Marcelo Tosatti mtosa...@redhat.com
Ping! mst, you handled a previous PC machine compatibility patch - can
you ack or nack?
Eduardo, which of the following patches depend on this one? Only 12/12?
Andreas
Signed-off-by: Eduardo Habkost ehabk...@redhat.com
---
hw/pc_piix.c | 22 +-
target-i386/cpu.c | 5 +++--
target-i386/cpu.h | 2 +-
3 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 0a6923d..f9cfe78 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -233,12 +233,14 @@ static void pc_init_pci(QEMUMachineInitArgs *args)
initrd_filename, cpu_model, 1, 1);
}
-static void pc_init_pci_1_3(QEMUMachineInitArgs *args)
+/* PC machine init function for pc-0.14 to pc-1.2 */
+static void pc_init_pci_1_2(QEMUMachineInitArgs *args)
{
-enable_kvm_pv_eoi();
+disable_kvm_pv_eoi();
pc_init_pci(args);
}
+/* PC init function for pc-0.10 to pc-0.13, and reused by xenfv */
static void pc_init_pci_no_kvmclock(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args-ram_size;
@@ -247,6 +249,7 @@ static void pc_init_pci_no_kvmclock(QEMUMachineInitArgs
*args)
const char *kernel_cmdline = args-kernel_cmdline;
const char *initrd_filename = args-initrd_filename;
const char *boot_device = args-boot_device;
+disable_kvm_pv_eoi();
pc_init1(get_system_memory(),
get_system_io(),
ram_size, boot_device,
@@ -264,6 +267,7 @@ static void pc_init_isa(QEMUMachineInitArgs *args)
const char *boot_device = args-boot_device;
if (cpu_model == NULL)
cpu_model = 486;
+disable_kvm_pv_eoi();
pc_init1(get_system_memory(),
get_system_io(),
ram_size, boot_device,
@@ -286,7 +290,7 @@ static QEMUMachine pc_i440fx_machine_v1_4 = {
.name = pc-i440fx-1.4,
.alias = pc,
.desc = Standard PC (i440FX + PIIX, 1996),
-.init = pc_init_pci_1_3,
+.init = pc_init_pci,
.max_cpus = 255,
.is_default = 1,
DEFAULT_MACHINE_OPTIONS,
@@ -302,7 +306,7 @@ static QEMUMachine pc_i440fx_machine_v1_4 = {
static QEMUMachine pc_machine_v1_3 = {
.name = pc-1.3,
.desc = Standard PC,
-.init = pc_init_pci_1_3,
+.init = pc_init_pci,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
PC_COMPAT_1_3,
@@ -342,7 +346,7 @@ static QEMUMachine pc_machine_v1_3 = {
static QEMUMachine pc_machine_v1_2 = {
.name = pc-1.2,
.desc = Standard PC,
-.init = pc_init_pci,
+.init = pc_init_pci_1_2,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
PC_COMPAT_1_2,
@@ -386,7 +390,7 @@ static QEMUMachine pc_machine_v1_2 = {
static QEMUMachine pc_machine_v1_1 = {
.name = pc-1.1,
.desc = Standard PC,
-.init = pc_init_pci,
+.init = pc_init_pci_1_2,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
PC_COMPAT_1_1,
@@ -422,7 +426,7 @@ static QEMUMachine pc_machine_v1_1 = {
static QEMUMachine pc_machine_v1_0 = {
.name = pc-1.0,
.desc = Standard PC,
-.init = pc_init_pci,
+.init = pc_init_pci_1_2,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
PC_COMPAT_1_0,
@@ -438,7 +442,7 @@ static QEMUMachine pc_machine_v1_0 = {
static QEMUMachine pc_machine_v0_15 = {
.name = pc-0.15,
.desc = Standard PC,
-.init = pc_init_pci,
+.init = pc_init_pci_1_2,
.max_cpus = 255,
.compat_props = (GlobalProperty[]) {
Re: [Qemu-devel] [RFC qom-cpu v2 0/2] target-sh4: SuperHCPU subclasses
Am 21.01.2013 04:28, schrieb Andreas Färber: Hello, This series introduces SuperH CPU subclasses. The first conversion to QOM patch had used a declarative approach reusing sh4_def_t as SuperHCPUInfo. This approach now uses imperative instance_init functions. To preserve -cpu ? output and case-insensitivity, distinct name and type name are used, but allowing use of the type name as done for alpha. TODO: guard against abstract types (may apply to other targets as well) TODO: move class - name lookup to cpu.c? This series in context: + qom-cpu cleanups and bugfixes being queued for 1.4 + CPUState QOM realizefn and initfn RFC for 1.5 / qom-cpu-next ~ SuperHCPU subclasses (this series) - SH7750 QOM'ification (to be rebased) - cross-target refactoring of cpu_init() and realized behavior (TBD) Available for testing at: git://github.com/afaerber/qemu-cpu.git qom-cpu-sh4-classes.v2 https://github.com/afaerber/qemu-cpu/commits/qom-cpu-sh4-classes.v2 Note that the default sh4 machine shix does not check the return value of cpu_init() and silently continues even without CPU. I've used -M r2d for testing and will try to post a fix for 1.4. Andreas v2: * Fixed bug in class name comparison, spotted by Igor. * Refactored name - ObjectClass mapping into new function. * Moved realizefn patch into CPUState series, rebased. v1 - preview on GitHub: * Redone, using combination of initfn and class_init instead of SuperHCPUInfo. * Adopted naming scheme suggested by Eduardo. * Split out SuperHCPUClass field movements into separate patch. Cc: Aurélien Jarno aurel...@aurel32.net Cc: Igor Mammedov imamm...@redhat.com Cc: Eduardo Habkost ehabk...@redhat.com Andreas Färber (2): target-sh4: Introduce SuperHCPU subclasses target-sh4: Move PVR/PRR/CVR into SuperHCPUClass hw/sh7750.c| 10 ++-- target-sh4/cpu-qom.h | 13 + target-sh4/cpu.c | 124 +++- target-sh4/cpu.h |3 -- target-sh4/translate.c | 94 +--- 5 Dateien geändert, 175 Zeilen hinzugefügt(+), 69 Zeilen entfernt(-) -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v4 2/3] net: split eth_mac_addr for better error handling
From: ak...@redhat.com Date: Sun, 20 Jan 2013 10:43:08 +0800 From: Stefan Hajnoczi stefa...@gmail.com When we set mac address, software mac address in system and hardware mac address all need to be updated. Current eth_mac_addr() doesn't allow callers to implement error handling nicely. This patch split eth_mac_addr() to prepare part and real commit part, then we can prepare first, and try to change hardware address, then do the real commit if hardware address is set successfully. Signed-off-by: Stefan Hajnoczi stefa...@gmail.com Signed-off-by: Amos Kong ak...@redhat.com This patch doesn't apply to net-next.
[Qemu-devel] [QEMU]Patch for QEMU errors
Hi all, We programmed a block storage(HLFS) patch for QEMU. Therefore, when i patched this driver for QEMU, it happened to me some errors. Could anyone give me some suggestions, thanks in advance ;-) You can see this issue i described in details from http://code.google.com/p/cloudxy/issues/detail?id=21 You can also see our patch for QEMU here. http://cloudxy.googlecode.com/svn/trunk/hlfs/patches/hlfs_driver_for_qemu.patch -- Thanks Harry Wei
Re: [Qemu-devel] wrong argument to qemu_flush_queued_packets() in network frontends ?
small correction:
On Sun, Jan 20, 2013 at 6:50 PM, Luigi Rizzo ri...@iet.unipi.it wrote:
While running qemu 1.3.0 with the following network-related flags:
-net nic -net tap,ifname=tap0,script=''
I encountered the same problem (should be common to several
frontends, e.g. e100, eepro100, virtio-net, xen_nic):
in net/tap.c :: tap_send(), if qemu_send_packet_async() returns 0
(e.g. because the NIC has no buffers available)
traffic stops, despite the fact that the frontend will try to pull
queued packets when the receive ring is updated.
Upon investigation, it turns out that the backend code does
size = qemu_send_packet_async(s-nc, buf, size, tap_send_completed);
if (size == 0) {
tap_read_poll(s, 0);
and the arguments are
s-nc.name = tap.0
s-nc.peer-name = hub0port1
s-nc.send_queue = 0x7f40b2f61e20
s-nc.peer-send_queue = 0x7f40b2f63690 --- enqueued here
whereis the frontend is trying to pull from a different queue
qemu_flush_queued_packets(s-nic-nc);
with arguments
s-nic-nc.name = e1000.0
s-nic-nc.peer-name = hub0port0 --- try to flush this
s-nic-nc.send_queue = 0x7f40b3008ae0
the queue that is actually flushed is s-nic-nc.send_queue or
0x7f40b3008ae0
s-nic-nc.peer-send_queue = 0x7f40b2f63660
Note, regular traffic flows correctly across the hub,
but qemu_flush_queued_packets() seems to try and pull
from the wrong place.
Any idea how to fix this (other than the inefficient solution
of leaving read_poll=1 in the frontend)
cheers
luigi
cheers
luigi
--
-+---
Prof. Luigi RIZZO, ri...@iet.unipi.it . Dip. di Ing. dell'Informazione
http://www.iet.unipi.it/~luigi/. Universita` di Pisa
TEL +39-050-2211611 . via Diotisalvi 2
Mobile +39-338-6809875 . 56122 PISA (Italy)
-+---
Re: [Qemu-devel] wrong argument to qemu_flush_queued_packets() in network frontends ?
... and upon closer inspection, the problem described below (frontend
blocks the backend, then tries to drain the wrong queue causing a stall)
occurs because the hub in the middle breaks the flow of events.
In the configuration below ( -net nic -net tap,ifname=tap0,... ) we have
e1000.0 -- hub0port0 [hub] hub0port1 -- tap.0
The hub0port1 reports as non-writable when all other ports
(just one in this case) are full, and the packet is queued
on hub0port1. However when the e1000 frontend tries to drain
the queue, it directly accesses the queue attached to hub0port0,
which is empty.
So it appears that the only fix is the following:
when a node is attached to a hub, instead of draining the
queue on the node one should drain all queues attached to the hub.
A new function qemu_flush_hub() would be handy, something like
QLIST_FOREACH(port, hub-ports, next) {
if (port != source_port)
qemu_flush_queued_packets(port-nc);
}
The other option (queueing on the output ports of the hub)
would require a bit more attention to make sure that
the callback is only executed once (and also, avoid exceeding
data replication). Not impossible, but it requires reference
counting the packet.
What do you think, which way do you prefer ?
cheers
luigi
On Sun, Jan 20, 2013 at 6:50 PM, Luigi Rizzo ri...@iet.unipi.it wrote:
While running qemu 1.3.0 with the following network-related flags:
-net nic -net tap,ifname=tap0,script=''
I encountered the same problem (should be common to several
frontends, e.g. e100, eepro100, virtio-net, xen_nic):
in net/tap.c :: tap_send(), if qemu_send_packet_async() returns 0
(e.g. because the NIC has no buffers available)
traffic stops, despite the fact that the frontend will try to pull
queued packets when the receive ring is updated.
Upon investigation, it turns out that the backend code does
size = qemu_send_packet_async(s-nc, buf, size, tap_send_completed);
if (size == 0) {
tap_read_poll(s, 0);
and the arguments are
s-nc.name = tap.0
s-nc.peer-name = hub0port1
s-nc.send_queue = 0x7f40b2f61e20
s-nc.peer-send_queue = 0x7f40b2f63690 --- enqueued here
whereis the frontend is trying to pull from a different queue
qemu_flush_queued_packets(s-nic-nc);
with arguments
s-nic-nc.name = e1000.0
s-nic-nc.peer-name = hub0port0 --- try to flush this
s-nic-nc.send_queue = 0x7f40b3008ae0
s-nic-nc.peer-send_queue = 0x7f40b2f63660
Note, regular traffic flows correctly across the hub,
but qemu_flush_queued_packets() seems to try and pull
from the wrong place.
Any idea how to fix this (other than the inefficient solution
of leaving read_poll=1 in the frontend)
cheers
luigi
--
-+---
Prof. Luigi RIZZO, ri...@iet.unipi.it . Dip. di Ing. dell'Informazione
http://www.iet.unipi.it/~luigi/. Universita` di Pisa
TEL +39-050-2211611 . via Diotisalvi 2
Mobile +39-338-6809875 . 56122 PISA (Italy)
-+---
[Qemu-devel] [PATCH][v3] linux-user: correct semctl() and shmctl()
The parameter union semun of semctl() is not a value
but a pointer to the value.
Moreover, all fields of target_su must be swapped (if needed).
The third argument of shmctl is a pointer.
WITHOUT this patch:
$ ipcs
kernel not configured for shared memory
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
WITH this patch:
$ ipcs
-- Shared Memory Segments
keyshmid owner perms bytes nattch status
0x4e545030 0 root 60096 1
0x4e545031 32769 root 60096 1
0x4e545032 65538 root 66696 1
0x4e545033 98307 root 66696 1
0x47505344 131076 root 6668240 1
0x3c81b7f5 163845 laurent 6664096 0
0x 729513990 laurent 600393216 2 dest
0x 729546759 laurent 600393216 2 dest
0x 1879179273 laurent 600393216 2 dest
-- Semaphore Arrays
keysemid owner perms nsems
0x3c81b7f6 32768 laurent 6661
0x1c44ac47 6586369laurent 6001
-- Message Queues
keymsqid owner perms used-bytes messages
0x1c44ac45 458752 laurent60000
0x1c44ac46 491521 laurent60000
Signed-off-by: Laurent Vivier laur...@vivier.eu
---
v2: move lock_user_struct() in do_semctl()
v3: correctly set the return value
linux-user/syscall.c | 49 +
1 file changed, 33 insertions(+), 16 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 693e66f..d44558d 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -2635,8 +2635,9 @@ static inline abi_long host_to_target_semarray(int semid,
abi_ulong target_addr,
}
static inline abi_long do_semctl(int semid, int semnum, int cmd,
- union target_semun target_su)
+ abi_ulong ptr)
{
+union target_semun *target_su;
union semun arg;
struct semid_ds dsarg;
unsigned short *array = NULL;
@@ -2645,43 +2646,58 @@ static inline abi_long do_semctl(int semid, int semnum,
int cmd,
abi_long err;
cmd = 0xff;
+if (!lock_user_struct(VERIFY_READ, target_su, ptr, 1)) {
+return -TARGET_EFAULT;
+}
switch( cmd ) {
case GETVAL:
case SETVAL:
-arg.val = tswap32(target_su.val);
+arg.val = tswap32(target_su-val);
ret = get_errno(semctl(semid, semnum, cmd, arg));
-target_su.val = tswap32(arg.val);
+target_su-val = tswap32(arg.val);
break;
case GETALL:
case SETALL:
-err = target_to_host_semarray(semid, array, target_su.array);
-if (err)
+err = target_to_host_semarray(semid, array,
+ tswapal(target_su-array));
+if (err) {
+unlock_user_struct(target_su, ptr, 0);
return err;
+}
arg.array = array;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_semarray(semid, target_su.array, array);
-if (err)
+err = host_to_target_semarray(semid, tswapal(target_su-array),
+ array);
+if (err) {
+unlock_user_struct(target_su, ptr, 0);
return err;
+}
break;
case IPC_STAT:
case IPC_SET:
case SEM_STAT:
-err = target_to_host_semid_ds(dsarg, target_su.buf);
-if (err)
+err = target_to_host_semid_ds(dsarg, tswapal(target_su-buf));
+if (err) {
+unlock_user_struct(target_su, ptr, 0);
return err;
+}
arg.buf = dsarg;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_semid_ds(target_su.buf, dsarg);
-if (err)
+err = host_to_target_semid_ds(tswapal(target_su-buf), dsarg);
+if (err) {
+unlock_user_struct(target_su, ptr, 0);
return err;
+}
break;
case IPC_INFO:
case SEM_INFO:
arg.__buf = seminfo;
ret = get_errno(semctl(semid, semnum, cmd, arg));
-err = host_to_target_seminfo(target_su.__buf, seminfo);
-if (err)
+err = host_to_target_seminfo(tswapal(target_su-__buf), seminfo);
+if (err) {
+unlock_user_struct(target_su, ptr, 0);
return err;
+}
break;
case IPC_RMID:
case GETPID:
@@ -2690,6 +2706,7 @@ static inline abi_long do_semctl(int semid, int semnum,
int cmd,
ret =
Re: [Qemu-devel] [PATCH v2 0/2] fix two revision related errors
Hi, I can't see a difference between Landscape + Landscape (flipped). Likewise Portrait + Portrait (flipped). Is there any? I can't actually get the (flipped) modes (both portrait and landscape) to work, I get an error message Unable to save display settings. How did you manage to get them to work? which driver, qemu command line, qemu version did you use? upstream qemu, qxl.rev set to 3, qxl driver 4.5.something (i.e. not the latest 5.x). cheers, Gerd
Re: [Qemu-devel] [PATCH V4 00/13] add qmp/hmp interfaces for snapshot info
于 2013-1-17 15:39, Wenchao Xia 写道: This serial of patches does two things: merge some info code in qemu-img, and add following interfaces: 1) qmp: query-images 2) qmp: query-snapshots 3) hmp: show snapshot info on a single block device These patches follows the rule that use qmp to retieve information, hmp layer just do a translation from qmp object it got, so almost every hmp interface may have a correlated qmp interface. To make code graceful, snapshot retrieving code in qemu and qemu-img are merged into block.c, and some function name was adjusted to make it tips better. Now it works as: qemu qemu-img dump_monitordump_stdout |--| | qmp | block Note: Last two patches need previous sent patches which extend hmp sub command, at: http://lists.nongnu.org/archive/html/qemu-devel/2012-12/msg03487.html v2: Rename and adjusted qmp interface according to comments from Eric. Spelling fix. Information retrieving function in block layer goes to seperated patch. Free qmp object after usage in hmp. Added counterpart in qmp-commands.hx. Better tips in qmp-schema.json. v3: Spelling fix in commit message, patch 03/11. Spelling fix in code, patch 06/11. Add comments that vm-state-size is in bytes, and change size of it in example to a reasonable number, patch 08/11. v4: 02/13: in bdrv_get_filename(), add const to parameter *bs. 03/13: new added, in which the function correct the behavior in info retrieving. 04/13: in bdrv_query_snapshot_infolist(), remove NULL check before call err_setg(), added TODO comments that let block layer function set error instead of this layer to tip better for errors, Split out patch about image info to patch 05/13. 05/13: new splitted, and it checks *bs by calling bdrv_can_read_snapshot() before collect internal snasphot info to avoid *err is set unexpectly now. 06/13: check if error happens after calling bdrv_query_image_info(). 08/13: rename info to image in DeviceImageInfo and make it optional, when device is not inserted it will be empty, added error handling code when met error in calling block layer API. 09/13: distinguish *id and *name in bdrv_find_snapshots(), caller can choose what to search with. id_wellformed() should be called in new snapshot creation interface above this function in the future. 10/13: now this interface have addtional parameter *device, which enable showing internal snapshots on a single device. Also use bdrv_can_read_snapshot() instead of bdrv_can_snapshot() now. 11/13: this function goes to hmp.c so hmp_handler_error is not exported any more, split out patch that switch snapshot info function to patch 12/13. 12/13: new splitted. 13/13: use qmp API instead of directly calling block layer API, now all hmp function have correspond qmp funtion in this serial. Wenchao Xia (13): 1 qemu-img: remove unused parameter in collect_image_info() 2 block: add bdrv_get_filename() function 3 block: add bdrv_can_read_snapshot() function 4 block: add snapshot info query function bdrv_query_snapshot_infolist() 5 block: add image info query function bdrv_query_image_info() 6 qemu-img: switch image retrieving function 7 block: rename bdrv_query_info to bdrv_query_block_info 8 qmp: add interface query-images. 9 block: export function bdrv_find_snapshot() 10 qmp: add interface query-snapshots 11 hmp: add function hmp_info_snapshots() 12 hmp: switch snapshot info function to qmp based one 13 hmp: show snapshots on single block device block.c | 274 - hmp.c | 47 + hmp.h |1 + include/block/block.h | 14 +++- monitor.c |8 +- qapi-schema.json | 46 qemu-img.c| 91 +--- qmp-commands.hx | 129 +++ savevm.c | 94 + 9 files changed, 522 insertions(+), 182 deletions(-) Hi all, any more comments for this serial? -- Best Regards Wenchao Xia
