Re: [Qemu-devel] [Bug 1180777] Re: Windows 7 VM freeze on Ubuntu 12.04 KVM
On Fri, Sep 13, 2013 at 07:29:49PM -, Vasile Dumitrescu wrote: > I also see these EXACT symptoms, using kvm (VM managed through livirt > virsh) on Debian x64 host, guest is Windows 8, RedHat VirtIo network > driver. > Can you trace KVM [1] when hang happens next time? [1] http://www.linux-kvm.org/page/Tracing > rgds > > ** Also affects: debian >Importance: Undecided >Status: New > > -- > You received this bug notification because you are a member of qemu- > devel-ml, which is subscribed to QEMU. > https://bugs.launchpad.net/bugs/1180777 > > Title: > Windows 7 VM freeze on Ubuntu 12.04 KVM > > Status in QEMU: > New > Status in “qemu-kvm” package in Ubuntu: > Confirmed > Status in Debian GNU/Linux: > New > > Bug description: > Hi, > > I have recently setup a Windows 7 VM on KVM and started using it > through remote desktop. > > What happens is that, after some hours of usage, the remote desktop > connection freezes. I thought it was a remmina bug, as the it was > enough to kill and restart it to successfully connect again to the VM. > > However, today I've switched to a different RDP client (2X Client > chromium app) and the freeze just happened again! > > Some information: > - the host and the VM are completely idle when the freeze occurs > - I've tried sniffing the network packets toward the RDP port during the > freeze and found that the client is sending packets but no packet is sent back > > Could this be a KVM issue? How can I further debug this one (I expect > the freeze to happen again...)? > > ProblemType: Bug > DistroRelease: Ubuntu 12.04 > Package: kvm 1:84+dfsg-0ubuntu16+1.0+noroms+0ubuntu14.8 > ProcVersionSignature: Ubuntu 3.2.0-41.66-generic 3.2.42 > Uname: Linux 3.2.0-41-generic x86_64 > ApportVersion: 2.0.1-0ubuntu17.2 > Architecture: amd64 > Date: Thu May 16 14:12:40 2013 > MachineType: Hewlett-Packard HP ProBook 4520s > MarkForUpload: True > ProcEnviron: > TERM=xterm > PATH=(custom, no user) > LANG=en_US.UTF-8 > SHELL=/bin/bash > ProcKernelCmdLine: BOOT_IMAGE=/boot/vmlinuz-3.2.0-41-generic > root=UUID=D2E20BC3E20BAAB5 loop=/hostname/disks/root.disk ro quiet splash > vt.handoff=7 > SourcePackage: qemu-kvm > UpgradeStatus: No upgrade log present (probably fresh install) > dmi.bios.date: 08/26/2010 > dmi.bios.vendor: Hewlett-Packard > dmi.bios.version: 68AZZ Ver. F.0A > dmi.board.name: 1411 > dmi.board.vendor: Hewlett-Packard > dmi.board.version: KBC Version 57.30 > dmi.chassis.type: 10 > dmi.chassis.vendor: Hewlett-Packard > dmi.modalias: > dmi:bvnHewlett-Packard:bvr68AZZVer.F.0A:bd08/26/2010:svnHewlett-Packard:pnHPProBook4520s:pvr:rvnHewlett-Packard:rn1411:rvrKBCVersion57.30:cvnHewlett-Packard:ct10:cvr: > dmi.product.name: HP ProBook 4520s > dmi.sys.vendor: Hewlett-Packard > > To manage notifications about this bug go to: > https://bugs.launchpad.net/qemu/+bug/1180777/+subscriptions -- Gleb.
Re: [Qemu-devel] [PATCH 3/8] target-m68k: Rename helpers.h to helper.h
Am 15.09.2013 02:03, schrieb Richard Henderson:
> This brings the m68k target in line with all other targets.
>
> Signed-off-by: Richard Henderson
> ---
> target-m68k/helper.c| 2 +-
> target-m68k/{helpers.h => helper.h} | 0
> target-m68k/op_helper.c | 2 +-
> target-m68k/translate.c | 6 +++---
> 4 files changed, 5 insertions(+), 5 deletions(-)
> rename target-m68k/{helpers.h => helper.h} (100%)
>
> diff --git a/target-m68k/helper.c b/target-m68k/helper.c
> index 00a7a08..a508896 100644
> --- a/target-m68k/helper.c
> +++ b/target-m68k/helper.c
> @@ -21,7 +21,7 @@
> #include "cpu.h"
> #include "exec/gdbstub.h"
>
> -#include "helpers.h"
> +#include "helper.h"
>
> #define SIGNBIT (1u << 31)
>
> diff --git a/target-m68k/helpers.h b/target-m68k/helper.h
> similarity index 100%
> rename from target-m68k/helpers.h
> rename to target-m68k/helper.h
> diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
> index 30f7d8b..bbbfd7f 100644
> --- a/target-m68k/op_helper.c
> +++ b/target-m68k/op_helper.c
> @@ -17,7 +17,7 @@
> * License along with this library; if not, see
>
Re: [Qemu-devel] [PATCH RFC v3 2/2] hw/pci: handle unassigned pci addresses
On Sun, 2013-09-15 at 00:08 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 09, 2013 at 02:21:36PM +0300, Marcel Apfelbaum wrote:
> > Created a MemoryRegion with negative priority that
> > spans over all the pci address space.
> > It "intercepts" the accesses to unassigned pci
> > address space and will follow the pci spec:
> > 1. returns -1 on read
> > 2. does nothing on write
> > 3. sets the RECEIVED MASTER ABORT bit in the STATUS register
> > of the device that initiated the transaction
> >
> > Note: This implementation assumes that all the reads/writes to
> > the pci address space are done by the cpu.
> >
> > Signed-off-by: Marcel Apfelbaum
> > ---
> > Changes from v1:
> > - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on
> > various Host Bridges
> > - "pci-unassgined-mem" does not have a ".valid.accept" field and
> > implements read write methods
> >
> > hw/pci/pci.c | 46
> > ++
> > include/hw/pci/pci_bus.h | 1 +
> > 2 files changed, 47 insertions(+)
> >
> > diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> > index d00682e..b6a8026 100644
> > --- a/hw/pci/pci.c
> > +++ b/hw/pci/pci.c
> > @@ -283,6 +283,43 @@ const char *pci_root_bus_path(PCIDevice *dev)
> > return rootbus->qbus.name;
> > }
> >
> > +static void unassigned_mem_access(PCIBus *bus)
> > +{
> > +/* FIXME assumption: memory access to the pci address
> > + * space is always initiated by the host bridge
> > + * (device 0 on the bus) */
> > +PCIDevice *d = bus->devices[0];
> > +if (!d) {
> > +return;
> > +}
> > +
> > +pci_word_test_and_set_mask(d->config + PCI_STATUS,
> > + PCI_STATUS_REC_MASTER_ABORT);
> > +}
> > +
> > +static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned
> > size)
> > +{
> > +PCIBus *bus = opaque;
> > +unassigned_mem_access(bus);
> > +
> > +return -1ULL;
> > +}
> > +
> > +static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val,
> > +unsigned size)
> > +{
> > +PCIBus *bus = opaque;
> > +unassigned_mem_access(bus);
> > +}
> > +
> > +static const MemoryRegionOps unassigned_mem_ops = {
> > +.read = unassigned_mem_read,
> > +.write = unassigned_mem_write,
> > +.endianness = DEVICE_NATIVE_ENDIAN,
> > +};
> > +
> > +#define UNASSIGNED_MEM_PRIORITY -1
> > +
>
> This really should be "lowest available priority" correct?
Yes, it should
>
> So how about making it INT_MIN then?
Seems right, thanks
Marcel
>
> > static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> > const char *name,
> > MemoryRegion *address_space_mem,
> > @@ -294,6 +331,15 @@ static void pci_bus_init(PCIBus *bus, DeviceState
> > *parent,
> > bus->address_space_mem = address_space_mem;
> > bus->address_space_io = address_space_io;
> >
> > +
> > +memory_region_init_io(&bus->unassigned_mem, OBJECT(bus),
> > + &unassigned_mem_ops, bus, "pci-unassigned",
> > + memory_region_size(bus->address_space_mem));
> > +memory_region_add_subregion_overlap(bus->address_space_mem,
> > +bus->address_space_mem->addr,
> > +&bus->unassigned_mem,
> > +UNASSIGNED_MEM_PRIORITY);
> > +
> > /* host bridge */
> > QLIST_INIT(&bus->child);
> >
> > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> > index 9df1788..4cc25a3 100644
> > --- a/include/hw/pci/pci_bus.h
> > +++ b/include/hw/pci/pci_bus.h
> > @@ -23,6 +23,7 @@ struct PCIBus {
> > PCIDevice *parent_dev;
> > MemoryRegion *address_space_mem;
> > MemoryRegion *address_space_io;
> > +MemoryRegion unassigned_mem;
> >
> > QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> > QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> > --
> > 1.8.3.1
Re: [Qemu-devel] [PATCH] pci: remove explicit check to 64K ioport size
On Fri, Sep 13, 2013 at 01:58:44PM +0200, Hervé Poussineau wrote:
> This check is useless, as bigger addresses will be ignored when
> added to 'io' MemoryRegion, which has a size of 64K.
>
> However, some architectures don't use the 'io' MemoryRegion, like
> the alpha and versatile platforms. They create a PCI I/O region
> bigger than 64K, so let them handle PCI I/O BARs in the higher range.
>
> Signed-off-by: Hervé Poussineau
> ---
> hw/pci/pci.c |3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index d00682e..a8e2b29 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -1028,8 +1028,7 @@ static pcibus_t pci_bar_address(PCIDevice *d,
> }
> new_addr = pci_get_long(d->config + bar) & ~(size - 1);
> last_addr = new_addr + size - 1;
> -/* NOTE: we have only 64K ioports on PC */
> -if (last_addr <= new_addr || new_addr == 0 || last_addr >
> UINT16_MAX) {
> +if (last_addr <= new_addr || new_addr == 0) {
> return PCI_BAR_UNMAPPED;
> }
> return new_addr;
> --
> 1.7.10.4
We still didn't fix the overlap for PCI BARs properly
so it looks like the following is needed on top.
Could you please check whether this works for you on versatile/alpha?
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index d452135..3118854 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1028,7 +1028,10 @@ static pcibus_t pci_bar_address(PCIDevice *d,
}
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
last_addr = new_addr + size - 1;
-if (last_addr <= new_addr || new_addr == 0) {
+/* Check if BAR is being sized explicitly.
+ * TODO: make priorities correct and remove this work around.
+ */
+if (last_addr <= new_addr || new_addr == 0 || last_addr >= UINT32_MAX)
{
return PCI_BAR_UNMAPPED;
}
return new_addr;
Re: [Qemu-devel] [PATCH 2/8] tcg: Use a GHashTable for tcg_find_helper
Am 15.09.2013 02:03, schrieb Richard Henderson:
> Slightly changes the interface, in that we now return name
> instead of a TCGHelperInfo structure, which goes away.
>
> Signed-off-by: Richard Henderson
> ---
> tcg/tcg.c | 74
> ---
> tcg/tcg.h | 10 +
> 2 files changed, 19 insertions(+), 65 deletions(-)
>
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index fd7fb6b..98b1c37 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -623,20 +623,15 @@ int tcg_check_temp_count(void)
> void tcg_register_helper(void *func, const char *name)
> {
> TCGContext *s = &tcg_ctx;
> -int n;
> -if ((s->nb_helpers + 1) > s->allocated_helpers) {
> -n = s->allocated_helpers;
> -if (n == 0) {
> -n = 4;
> -} else {
> -n *= 2;
> -}
> -s->helpers = realloc(s->helpers, n * sizeof(TCGHelperInfo));
> -s->allocated_helpers = n;
> +GHashTable *table = s->helpers;
> +
> +if (table == NULL) {
> +/* Use g_direct_hash/equal for direct pointer comparisons on func.
> */
> +table = g_hash_table_new(NULL, NULL);
> +s->helpers = table;
> }
> -s->helpers[s->nb_helpers].func = (uintptr_t)func;
> -s->helpers[s->nb_helpers].name = name;
> -s->nb_helpers++;
> +
> +g_hash_table_insert(table, (gpointer)func, (gpointer)name);
> }
>
> /* Note: we convert the 64 bit args to 32 bit and do some alignment
> @@ -851,47 +846,14 @@ char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int
> buf_size, TCGv_i64 arg)
> return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
> }
>
> -static int helper_cmp(const void *p1, const void *p2)
> +/* Find helper name. */
> +static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
> {
> -const TCGHelperInfo *th1 = p1;
> -const TCGHelperInfo *th2 = p2;
> -if (th1->func < th2->func)
> -return -1;
> -else if (th1->func == th2->func)
> -return 0;
> -else
> -return 1;
> -}
> -
> -/* find helper definition (Note: A hash table would be better) */
> -static TCGHelperInfo *tcg_find_helper(TCGContext *s, uintptr_t val)
> -{
> -int m, m_min, m_max;
> -TCGHelperInfo *th;
> -uintptr_t v;
> -
> -if (unlikely(!s->helpers_sorted)) {
> -qsort(s->helpers, s->nb_helpers, sizeof(TCGHelperInfo),
> - helper_cmp);
> -s->helpers_sorted = 1;
> -}
> -
> -/* binary search */
> -m_min = 0;
> -m_max = s->nb_helpers - 1;
> -while (m_min <= m_max) {
> -m = (m_min + m_max) >> 1;
> -th = &s->helpers[m];
> -v = th->func;
> -if (v == val)
> -return th;
> -else if (val < v) {
> -m_max = m - 1;
> -} else {
> -m_min = m + 1;
> -}
> +const char *ret = NULL;
> +if (s->helpers) {
> + ret = g_hash_table_lookup(s->helpers, (gpointer)val);
Please replace tab by spaces here.
> }
> -return NULL;
> +return ret;
> }
>
> static const char * const cond_name[] =
> @@ -976,7 +938,7 @@ void tcg_dump_ops(TCGContext *s)
> }
> } else if (c == INDEX_op_movi_i32 || c == INDEX_op_movi_i64) {
> tcg_target_ulong val;
> -TCGHelperInfo *th;
> +const char *name;
>
> nb_oargs = def->nb_oargs;
> nb_iargs = def->nb_iargs;
> @@ -984,9 +946,9 @@ void tcg_dump_ops(TCGContext *s)
> qemu_log(" %s %s,$", def->name,
> tcg_get_arg_str_idx(s, buf, sizeof(buf), args[0]));
> val = args[1];
> -th = tcg_find_helper(s, val);
> -if (th) {
> -qemu_log("%s", th->name);
> +name = tcg_find_helper(s, val);
> +if (name) {
> +qemu_log("%s", name);
> } else {
> if (c == INDEX_op_movi_i32) {
> qemu_log("0x%x", (uint32_t)val);
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 20543f6..8c5eb42 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -405,11 +405,6 @@ typedef struct TCGTemp {
> const char *name;
> } TCGTemp;
>
> -typedef struct TCGHelperInfo {
> -uintptr_t func;
> -const char *name;
> -} TCGHelperInfo;
> -
> typedef struct TCGContext TCGContext;
>
> struct TCGContext {
> @@ -447,10 +442,7 @@ struct TCGContext {
> uint8_t *code_ptr;
> TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
>
> -TCGHelperInfo *helpers;
> -int nb_helpers;
> -int allocated_helpers;
> -int helpers_sorted;
> +GHashTable *helpers;
>
> #ifdef CONFIG_PROFILER
> /* profiling info */
With fixed tab (see above):
Reviewed-by: Stefan Weil
Re: [Qemu-devel] [PATCH 1/8] tcg: Delete tcg_helper_get_name declaration
Am 15.09.2013 02:03, schrieb Richard Henderson: > The function was deleted in 4dc81f2822187f4503d4bdb76785cafa5b28db0b. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/tcg/tcg.h b/tcg/tcg.h > index 902c751..20543f6 100644 > --- a/tcg/tcg.h > +++ b/tcg/tcg.h > @@ -681,7 +681,6 @@ TCGArg *tcg_optimize(TCGContext *s, uint16_t > *tcg_opc_ptr, TCGArg *args, > > /* only used for debugging purposes */ > void tcg_register_helper(void *func, const char *name); > -const char *tcg_helper_get_name(TCGContext *s, void *func); > void tcg_dump_ops(TCGContext *s); > > void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf); Reviewed-by: Stefan Weil
[Qemu-devel] [PATCH 0/8] tcg: Tidy helpers registration
The subject came up in the contect of review of other patches
this weekend, and it was pretty easy to whip up.
r~
Richard Henderson (8):
tcg: Delete tcg_helper_get_name declaration
tcg: Use a GHashTable for tcg_find_helper
target-m68k: Rename helpers.h to helper.h
tcg: Move helper registration into tcg_context_init
tcg: Remove stray semi-colons from target-*/helper.h
tcg: Put target helper data into an array.
tcg: Add tcg-runtime.c helpers to all_helpers
tcg: Merge tcg_register_helper into tcg_context_init
include/exec/def-helper.h | 3 +-
target-alpha/helper.h | 2 +-
target-alpha/translate.c| 4 --
target-arm/helper.h | 8 +--
target-arm/translate.c | 3 -
target-cris/helper.h| 8 +--
target-cris/translate.c | 3 -
target-i386/translate.c | 4 --
target-m68k/helper.c| 2 +-
target-m68k/{helpers.h => helper.h} | 0
target-m68k/op_helper.c | 2 +-
target-m68k/translate.c | 7 +--
target-microblaze/translate.c | 2 -
target-mips/helper.h| 12 ++--
target-mips/translate.c | 4 --
target-openrisc/translate.c | 2 -
target-ppc/helper.h | 10 ++--
target-ppc/translate.c | 4 --
target-s390x/translate.c| 4 --
target-sh4/translate.c | 4 --
target-sparc/helper.h | 18 +++---
target-sparc/translate.c| 5 --
target-unicore32/translate.c| 3 -
target-xtensa/translate.c | 2 -
tcg/tcg.c | 114
tcg/tcg.h | 12 +---
26 files changed, 85 insertions(+), 157 deletions(-)
rename target-m68k/{helpers.h => helper.h} (100%)
--
1.8.1.4
[Qemu-devel] [PATCH 8/8] tcg: Merge tcg_register_helper into tcg_context_init
Eliminates the repeated checks for having created
the s->helpers hash table.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 21 ++---
tcg/tcg.h | 1 -
2 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bf4edfd..f401044 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -288,6 +288,7 @@ void tcg_context_init(TCGContext *s)
TCGOpDef *def;
TCGArgConstraint *args_ct;
int *sorted_args;
+GHashTable *helper_table;
memset(s, 0, sizeof(*s));
s->nb_globals = 0;
@@ -314,8 +315,12 @@ void tcg_context_init(TCGContext *s)
}
/* Register helpers. */
+/* Use g_direct_hash/equal for direct pointer comparisons on func. */
+s->helpers = helper_table = g_hash_table_new(NULL, NULL);
+
for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
-tcg_register_helper(all_helpers[i].func, all_helpers[i].name);
+g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
+(gpointer)all_helpers[i].name);
}
tcg_target_init(s);
@@ -653,20 +658,6 @@ int tcg_check_temp_count(void)
}
#endif
-void tcg_register_helper(void *func, const char *name)
-{
-TCGContext *s = &tcg_ctx;
-GHashTable *table = s->helpers;
-
-if (table == NULL) {
-/* Use g_direct_hash/equal for direct pointer comparisons on func. */
-table = g_hash_table_new(NULL, NULL);
-s->helpers = table;
-}
-
-g_hash_table_insert(table, (gpointer)func, (gpointer)name);
-}
-
/* Note: we convert the 64 bit args to 32 bit and do some alignment
and endian swap. Maybe it would be better to do the alignment
and endian swap in tcg_reg_alloc_call(). */
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 8c5eb42..f67fdb6 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -672,7 +672,6 @@ TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr,
TCGArg *args,
TCGOpDef *tcg_op_def);
/* only used for debugging purposes */
-void tcg_register_helper(void *func, const char *name);
void tcg_dump_ops(TCGContext *s);
void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
--
1.8.1.4
[Qemu-devel] [PATCH 7/8] tcg: Add tcg-runtime.c helpers to all_helpers
For the few targets that actually use these, we'd not report
them symbolicly in the tcg opcode logs.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 16
1 file changed, 16 insertions(+)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 9ace8fc..bf4edfd 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -264,6 +264,22 @@ typedef struct TCGHelperInfo {
static const TCGHelperInfo all_helpers[] = {
#define GEN_HELPER 2
#include "helper.h"
+
+/* Include tcg-runtime.c functions. */
+{ tcg_helper_div_i32, "div_i32" },
+{ tcg_helper_rem_i32, "rem_i32" },
+{ tcg_helper_divu_i32, "divu_i32" },
+{ tcg_helper_remu_i32, "remu_i32" },
+
+{ tcg_helper_shl_i64, "shl_i64" },
+{ tcg_helper_shr_i64, "shr_i64" },
+{ tcg_helper_sar_i64, "sar_i64" },
+{ tcg_helper_div_i64, "div_i64" },
+{ tcg_helper_rem_i64, "rem_i64" },
+{ tcg_helper_divu_i64, "divu_i64" },
+{ tcg_helper_remu_i64, "remu_i64" },
+{ tcg_helper_mulsh_i64, "mulsh_i64" },
+{ tcg_helper_muluh_i64, "muluh_i64" },
};
void tcg_context_init(TCGContext *s)
--
1.8.1.4
[Qemu-devel] [PATCH 4/8] tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson
---
target-alpha/translate.c | 4
target-arm/translate.c| 3 ---
target-cris/translate.c | 3 ---
target-i386/translate.c | 4
target-m68k/translate.c | 3 ---
target-microblaze/translate.c | 2 --
target-mips/translate.c | 4
target-openrisc/translate.c | 2 --
target-ppc/translate.c| 4
target-s390x/translate.c | 4
target-sh4/translate.c| 4
target-sparc/translate.c | 5 -
target-unicore32/translate.c | 3 ---
target-xtensa/translate.c | 2 --
tcg/tcg.c | 8 +++-
15 files changed, 7 insertions(+), 48 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 28ce436..9cb8084 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -140,10 +140,6 @@ void alpha_translate_init(void)
offsetof(CPUAlphaState, usp), "usp");
#endif
-/* register helpers */
-#define GEN_HELPER 2
-#include "helper.h"
-
done_init = 1;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 998bde2..5f003e7 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -115,9 +115,6 @@ void arm_translate_init(void)
#endif
a64_translate_init();
-
-#define GEN_HELPER 2
-#include "helper.h"
}
static inline TCGv_i32 load_cpu_offset(int offset)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 617e1b4..5faa44c 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3480,9 +3480,6 @@ void cris_initialize_tcg(void)
{
int i;
-#define GEN_HELPER 2
-#include "helper.h"
-
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cc_x = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUCRISState, cc_x), "cc_x");
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6d87900..439fc5a 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8242,10 +8242,6 @@ void optimize_flags_init(void)
cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUX86State,
regs[R_EDI]), "edi");
#endif
-
-/* register helpers */
-#define GEN_HELPER 2
-#include "helper.h"
}
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index f31e48d..f54b94a 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -108,9 +108,6 @@ void m68k_tcg_init(void)
NULL_QREG = tcg_global_mem_new(TCG_AREG0, -4, "NULL");
store_dummy = tcg_global_mem_new(TCG_AREG0, -8, "NULL");
-
-#define GEN_HELPER 2
-#include "helper.h"
}
static inline void qemu_assert(int cond, const char *msg)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 0673176..1b937b3 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -2024,8 +2024,6 @@ void mb_tcg_init(void)
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
}
-#define GEN_HELPER 2
-#include "helper.h"
}
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index ad43d59..0d8db66 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15886,10 +15886,6 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_fpu.fcr31),
"fcr31");
-/* register helpers */
-#define GEN_HELPER 2
-#include "helper.h"
-
inited = 1;
}
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 723b77d..8908a2e 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -110,8 +110,6 @@ void openrisc_translate_init(void)
offsetof(CPUOpenRISCState, gpr[i]),
regnames[i]);
}
-#define GEN_HELPER 2
-#include "helper.h"
}
/* Writeback SR_F transaltion-space to execution-space. */
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 2da7bc7..45ec840 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -175,10 +175,6 @@ void ppc_translate_init(void)
cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUPPCState,
access_type), "access_type");
-/* register helpers */
-#define GEN_HELPER 2
-#include "helper.h"
-
done_init = 1;
}
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index afe90eb..bc99a37 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -188,10 +188,6 @@ void s390x_translate_init(void)
offsetof(CPUS390XState, fregs[i].d),
cpu_re
[Qemu-devel] [PATCH 6/8] tcg: Put target helper data into an array.
One call inside of a loop to tcg_register_helper instead of hundreds
of sequential calls.
Presumably more icache and branch prediction friendly; resulting binary
size mostly unchanged on x86_64, as we're trading 32-bit rip-relative
references in .text for full 64-bit pointers in .rodata.
Signed-off-by: Richard Henderson
---
include/exec/def-helper.h | 3 +--
tcg/tcg.c | 17 ++---
2 files changed, 15 insertions(+), 5 deletions(-)
diff --git a/include/exec/def-helper.h b/include/exec/def-helper.h
index 022a9ce..73d51f9 100644
--- a/include/exec/def-helper.h
+++ b/include/exec/def-helper.h
@@ -240,8 +240,7 @@ static inline void glue(gen_helper_,
name)(dh_retvar_decl(ret) \
#elif GEN_HELPER == 2
/* Register helpers. */
-#define DEF_HELPER_FLAGS_0(name, flags, ret) \
-tcg_register_helper(HELPER(name), #name);
+#define DEF_HELPER_FLAGS_0(name, flags, ret) { HELPER(name), #name },
#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \
DEF_HELPER_FLAGS_0(name, flags, ret)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 59251c0..9ace8fc 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -256,9 +256,19 @@ void tcg_pool_reset(TCGContext *s)
#include "helper.h"
+typedef struct TCGHelperInfo {
+void *func;
+const char *name;
+} TCGHelperInfo;
+
+static const TCGHelperInfo all_helpers[] = {
+#define GEN_HELPER 2
+#include "helper.h"
+};
+
void tcg_context_init(TCGContext *s)
{
-int op, total_args, n;
+int op, total_args, n, i;
TCGOpDef *def;
TCGArgConstraint *args_ct;
int *sorted_args;
@@ -288,8 +298,9 @@ void tcg_context_init(TCGContext *s)
}
/* Register helpers. */
-#define GEN_HELPER 2
-#include "helper.h"
+for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
+tcg_register_helper(all_helpers[i].func, all_helpers[i].name);
+}
tcg_target_init(s);
}
--
1.8.1.4
[Qemu-devel] [PATCH 2/8] tcg: Use a GHashTable for tcg_find_helper
Slightly changes the interface, in that we now return name
instead of a TCGHelperInfo structure, which goes away.
Signed-off-by: Richard Henderson
---
tcg/tcg.c | 74 ---
tcg/tcg.h | 10 +
2 files changed, 19 insertions(+), 65 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index fd7fb6b..98b1c37 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -623,20 +623,15 @@ int tcg_check_temp_count(void)
void tcg_register_helper(void *func, const char *name)
{
TCGContext *s = &tcg_ctx;
-int n;
-if ((s->nb_helpers + 1) > s->allocated_helpers) {
-n = s->allocated_helpers;
-if (n == 0) {
-n = 4;
-} else {
-n *= 2;
-}
-s->helpers = realloc(s->helpers, n * sizeof(TCGHelperInfo));
-s->allocated_helpers = n;
+GHashTable *table = s->helpers;
+
+if (table == NULL) {
+/* Use g_direct_hash/equal for direct pointer comparisons on func. */
+table = g_hash_table_new(NULL, NULL);
+s->helpers = table;
}
-s->helpers[s->nb_helpers].func = (uintptr_t)func;
-s->helpers[s->nb_helpers].name = name;
-s->nb_helpers++;
+
+g_hash_table_insert(table, (gpointer)func, (gpointer)name);
}
/* Note: we convert the 64 bit args to 32 bit and do some alignment
@@ -851,47 +846,14 @@ char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int
buf_size, TCGv_i64 arg)
return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
}
-static int helper_cmp(const void *p1, const void *p2)
+/* Find helper name. */
+static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
{
-const TCGHelperInfo *th1 = p1;
-const TCGHelperInfo *th2 = p2;
-if (th1->func < th2->func)
-return -1;
-else if (th1->func == th2->func)
-return 0;
-else
-return 1;
-}
-
-/* find helper definition (Note: A hash table would be better) */
-static TCGHelperInfo *tcg_find_helper(TCGContext *s, uintptr_t val)
-{
-int m, m_min, m_max;
-TCGHelperInfo *th;
-uintptr_t v;
-
-if (unlikely(!s->helpers_sorted)) {
-qsort(s->helpers, s->nb_helpers, sizeof(TCGHelperInfo),
- helper_cmp);
-s->helpers_sorted = 1;
-}
-
-/* binary search */
-m_min = 0;
-m_max = s->nb_helpers - 1;
-while (m_min <= m_max) {
-m = (m_min + m_max) >> 1;
-th = &s->helpers[m];
-v = th->func;
-if (v == val)
-return th;
-else if (val < v) {
-m_max = m - 1;
-} else {
-m_min = m + 1;
-}
+const char *ret = NULL;
+if (s->helpers) {
+ ret = g_hash_table_lookup(s->helpers, (gpointer)val);
}
-return NULL;
+return ret;
}
static const char * const cond_name[] =
@@ -976,7 +938,7 @@ void tcg_dump_ops(TCGContext *s)
}
} else if (c == INDEX_op_movi_i32 || c == INDEX_op_movi_i64) {
tcg_target_ulong val;
-TCGHelperInfo *th;
+const char *name;
nb_oargs = def->nb_oargs;
nb_iargs = def->nb_iargs;
@@ -984,9 +946,9 @@ void tcg_dump_ops(TCGContext *s)
qemu_log(" %s %s,$", def->name,
tcg_get_arg_str_idx(s, buf, sizeof(buf), args[0]));
val = args[1];
-th = tcg_find_helper(s, val);
-if (th) {
-qemu_log("%s", th->name);
+name = tcg_find_helper(s, val);
+if (name) {
+qemu_log("%s", name);
} else {
if (c == INDEX_op_movi_i32) {
qemu_log("0x%x", (uint32_t)val);
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 20543f6..8c5eb42 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -405,11 +405,6 @@ typedef struct TCGTemp {
const char *name;
} TCGTemp;
-typedef struct TCGHelperInfo {
-uintptr_t func;
-const char *name;
-} TCGHelperInfo;
-
typedef struct TCGContext TCGContext;
struct TCGContext {
@@ -447,10 +442,7 @@ struct TCGContext {
uint8_t *code_ptr;
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
-TCGHelperInfo *helpers;
-int nb_helpers;
-int allocated_helpers;
-int helpers_sorted;
+GHashTable *helpers;
#ifdef CONFIG_PROFILER
/* profiling info */
--
1.8.1.4
[Qemu-devel] [PATCH 5/8] tcg: Remove stray semi-colons from target-*/helper.h
During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 2 +- target-arm/helper.h | 8 target-cris/helper.h | 8 target-mips/helper.h | 12 ++-- target-ppc/helper.h | 10 +- target-sparc/helper.h | 18 +- 6 files changed, 29 insertions(+), 29 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 732b701..5a0e78c 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -114,7 +114,7 @@ DEF_HELPER_FLAGS_1(tbia, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_2(tbis, TCG_CALL_NO_RWG, void, env, i64) DEF_HELPER_FLAGS_1(tb_flush, TCG_CALL_NO_RWG, void, env) -DEF_HELPER_1(halt, void, i64); +DEF_HELPER_1(halt, void, i64) DEF_HELPER_FLAGS_0(get_vmtime, TCG_CALL_NO_RWG, i64) DEF_HELPER_FLAGS_0(get_walltime, TCG_CALL_NO_RWG, i64) diff --git a/target-arm/helper.h b/target-arm/helper.h index 63ae13a..cac9564 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -247,10 +247,10 @@ DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32); -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32); -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32); -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64); +DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) diff --git a/target-cris/helper.h b/target-cris/helper.h index 8e8365c..0ac31f5 100644 --- a/target-cris/helper.h +++ b/target-cris/helper.h @@ -4,14 +4,14 @@ DEF_HELPER_2(raise_exception, void, env, i32) DEF_HELPER_2(tlb_flush_pid, void, env, i32) DEF_HELPER_2(spc_write, void, env, i32) DEF_HELPER_3(dump, void, i32, i32, i32) -DEF_HELPER_1(rfe, void, env); -DEF_HELPER_1(rfn, void, env); +DEF_HELPER_1(rfe, void, env) +DEF_HELPER_1(rfn, void, env) DEF_HELPER_3(movl_sreg_reg, void, env, i32, i32) DEF_HELPER_3(movl_reg_sreg, void, env, i32, i32) -DEF_HELPER_FLAGS_1(lz, TCG_CALL_NO_SE, i32, i32); -DEF_HELPER_FLAGS_4(btst, TCG_CALL_NO_SE, i32, env, i32, i32, i32); +DEF_HELPER_FLAGS_1(lz, TCG_CALL_NO_SE, i32, i32) +DEF_HELPER_FLAGS_4(btst, TCG_CALL_NO_SE, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(evaluate_flags_muls, TCG_CALL_NO_SE, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(evaluate_flags_mulu, TCG_CALL_NO_SE, i32, env, i32, i32, i32) diff --git a/target-mips/helper.h b/target-mips/helper.h index ed75e2c..1a8b86d 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -148,7 +148,7 @@ DEF_HELPER_2(mtc0_taghi, void, env, tl) DEF_HELPER_2(mtc0_datahi, void, env, tl) /* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32); +DEF_HELPER_2(mftgpr, tl, env, i32) DEF_HELPER_2(mftlo, tl, env, i32) DEF_HELPER_2(mfthi, tl, env, i32) DEF_HELPER_2(mftacx, tl, env, i32) @@ -165,11 +165,11 @@ DEF_HELPER_1(evpe, tl, env) #endif /* !CONFIG_USER_ONLY */ /* microMIPS functions */ -DEF_HELPER_4(lwm, void, env, tl, tl, i32); -DEF_HELPER_4(swm, void, env, tl, tl, i32); +DEF_HELPER_4(lwm, void, env, tl, tl, i32) +DEF_HELPER_4(swm, void, env, tl, tl, i32) #ifdef TARGET_MIPS64 -DEF_HELPER_4(ldm, void, env, tl, tl, i32); -DEF_HELPER_4(sdm, void, env, tl, tl, i32); +DEF_HELPER_4(ldm, void, env, tl, tl, i32) +DEF_HELPER_4(sdm, void, env, tl, tl, i32) #endif DEF_HELPER_2(fork, void, tl, tl) @@ -615,7 +615,7 @@ DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) #if defined(TARGET_MIPS64) -DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl); +DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl) #endif /* DSP Compare-Pick Sub-class insns */ diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 56814b5..6d282bb 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -168,8 +168,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr) DEF_HELPER_3(vsro, void, avr, avr, avr) DEF_HELPER_3(vaddcuw, void, avr, avr, avr) DEF_HELPER_3(vsubcuw, void, avr, avr, avr) -DEF_HELPER_2(lvsl, void, avr, tl); -DEF_HELPER_2(lvsr, void, avr, tl); +DEF_HELPER_2(lvsl, void, avr, tl) +DEF_HELPER_2(lvsr, void, avr, tl) DEF_HELPER_4(vaddsbs, void, env, avr, avr, avr) DEF_HELPER_4(vaddshs, void, env, avr, avr, avr) DEF_HE
[Qemu-devel] [PATCH 3/8] target-m68k: Rename helpers.h to helper.h
This brings the m68k target in line with all other targets.
Signed-off-by: Richard Henderson
---
target-m68k/helper.c| 2 +-
target-m68k/{helpers.h => helper.h} | 0
target-m68k/op_helper.c | 2 +-
target-m68k/translate.c | 6 +++---
4 files changed, 5 insertions(+), 5 deletions(-)
rename target-m68k/{helpers.h => helper.h} (100%)
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 00a7a08..a508896 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -21,7 +21,7 @@
#include "cpu.h"
#include "exec/gdbstub.h"
-#include "helpers.h"
+#include "helper.h"
#define SIGNBIT (1u << 31)
diff --git a/target-m68k/helpers.h b/target-m68k/helper.h
similarity index 100%
rename from target-m68k/helpers.h
rename to target-m68k/helper.h
diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c
index 30f7d8b..bbbfd7f 100644
--- a/target-m68k/op_helper.c
+++ b/target-m68k/op_helper.c
@@ -17,7 +17,7 @@
* License along with this library; if not, see
[Qemu-devel] [PATCH 1/8] tcg: Delete tcg_helper_get_name declaration
The function was deleted in 4dc81f2822187f4503d4bdb76785cafa5b28db0b. Signed-off-by: Richard Henderson --- tcg/tcg.h | 1 - 1 file changed, 1 deletion(-) diff --git a/tcg/tcg.h b/tcg/tcg.h index 902c751..20543f6 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -681,7 +681,6 @@ TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args, /* only used for debugging purposes */ void tcg_register_helper(void *func, const char *name); -const char *tcg_helper_get_name(TCGContext *s, void *func); void tcg_dump_ops(TCGContext *s); void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf); -- 1.8.1.4
[Qemu-devel] [PATCH v4 07/33] tcg-aarch64: Remove the shift_imm parameter from tcg_out_cmp
It was unused. Let's not overcomplicate things before we need them.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index be6d05a..cc56fe5 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -543,10 +543,10 @@ static inline void tcg_out_rotl(TCGContext *s, TCGType
ext,
}
static inline void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg rn,
- TCGReg rm, int shift_imm)
+ TCGReg rm)
{
/* Using CMP alias SUBS wzr, Wn, Wm */
-tcg_out_arith(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm, shift_imm);
+tcg_out_arith(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm, 0);
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -920,7 +920,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
(is_read ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write)));
/* Perform the address comparison. */
-tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
+tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3);
*label_ptr = s->code_ptr;
/* If not equal, we jump to the slow path. */
tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
@@ -1259,13 +1259,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_brcond_i64:
case INDEX_op_brcond_i32:
-tcg_out_cmp(s, ext, a0, a1, 0);
+tcg_out_cmp(s, ext, a0, a1);
tcg_out_goto_label_cond(s, a2, args[3]);
break;
case INDEX_op_setcond_i64:
case INDEX_op_setcond_i32:
-tcg_out_cmp(s, ext, a1, a2, 0);
+tcg_out_cmp(s, ext, a1, a2);
tcg_out_cset(s, 0, a0, args[3]);
break;
--
1.8.3.1
[Qemu-devel] [PATCH v4 29/33] tcg-aarch64: Use symbolic names for branches
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 48
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 3d1108c..335a5d0 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -327,6 +327,14 @@ typedef enum {
/* PC relative addressing instructions */
INSN_ADR = 0x1000,
INSN_ADRP = 0x9000,
+
+/* Branch instructions */
+INSN_B = 0x1400,
+INSN_BL= 0x9400,
+INSN_BR= 0xd61f,
+INSN_BLR = 0xd63f,
+INSN_RET = 0xd65f,
+INSN_B_C = 0x5400,
} AArch64Insn;
static inline enum aarch64_ldst_op_data
@@ -837,15 +845,14 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext,
TCGReg a,
static inline void tcg_out_goto(TCGContext *s, tcg_target_long target)
{
-tcg_target_long offset;
-offset = (target - (tcg_target_long)s->code_ptr) / 4;
+tcg_target_long offset = (target - (tcg_target_long)s->code_ptr) / 4;
if (offset < -0x0200 || offset >= 0x0200) {
/* out of 26bit range */
tcg_abort();
}
-tcg_out32(s, 0x1400 | (offset & 0x03ff));
+tcg_out32(s, INSN_B | (offset & 0x03ff));
}
static inline void tcg_out_goto_noaddr(TCGContext *s)
@@ -855,25 +862,21 @@ static inline void tcg_out_goto_noaddr(TCGContext *s)
kept coherent during retranslation.
Mask away possible garbage in the high bits for the first translation,
while keeping the offset bits for retranslation. */
-uint32_t insn;
-insn = (tcg_in32(s) & 0x03ff) | 0x1400;
-tcg_out32(s, insn);
+uint32_t old = tcg_in32(s) & 0x03ff;
+tcg_out32(s, INSN_B | old);
}
static inline void tcg_out_goto_cond_noaddr(TCGContext *s, TCGCond c)
{
-/* see comments in tcg_out_goto_noaddr */
-uint32_t insn;
-insn = tcg_in32(s) & (0x07 << 5);
-insn |= 0x5400 | tcg_cond_to_aarch64[c];
-tcg_out32(s, insn);
+/* See comments in tcg_out_goto_noaddr. */
+uint32_t old = tcg_in32(s) & (0x07 << 5);
+tcg_out32(s, INSN_B_C | tcg_cond_to_aarch64[c] | old);
}
static inline void tcg_out_goto_cond(TCGContext *s, TCGCond c,
tcg_target_long target)
{
-tcg_target_long offset;
-offset = (target - (tcg_target_long)s->code_ptr) / 4;
+tcg_target_long offset = (target - (tcg_target_long)s->code_ptr) / 4;
if (offset < -0x4 || offset >= 0x4) {
/* out of 19bit range */
@@ -881,37 +884,34 @@ static inline void tcg_out_goto_cond(TCGContext *s,
TCGCond c,
}
offset &= 0x7;
-tcg_out32(s, 0x5400 | tcg_cond_to_aarch64[c] | offset << 5);
+tcg_out32(s, INSN_B_C | tcg_cond_to_aarch64[c] | offset << 5);
}
static inline void tcg_out_callr(TCGContext *s, TCGReg reg)
{
-tcg_out32(s, 0xd63f | reg << 5);
+tcg_out32(s, INSN_BLR | reg << 5);
}
static inline void tcg_out_gotor(TCGContext *s, TCGReg reg)
{
-tcg_out32(s, 0xd61f | reg << 5);
+tcg_out32(s, INSN_BR | reg << 5);
}
static inline void tcg_out_call(TCGContext *s, tcg_target_long target)
{
-tcg_target_long offset;
-
-offset = (target - (tcg_target_long)s->code_ptr) / 4;
+tcg_target_long offset = (target - (tcg_target_long)s->code_ptr) / 4;
if (offset < -0x0200 || offset >= 0x0200) { /* out of 26bit rng */
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, target);
tcg_out_callr(s, TCG_REG_TMP);
} else {
-tcg_out32(s, 0x9400 | (offset & 0x03ff));
+tcg_out32(s, INSN_BL | (offset & 0x03ff));
}
}
-static inline void tcg_out_ret(TCGContext *s)
+static inline void tcg_out_ret(TCGContext *s, TCGReg rn)
{
-/* emit RET { LR } */
-tcg_out32(s, 0xd65f03c0);
+tcg_out32(s, INSN_RET | rn << 5);
}
void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
@@ -1993,5 +1993,5 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* pop (FP, LR), restore SP to previous frame, return */
tcg_out_pop_pair(s, TCG_REG_SP,
TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
-tcg_out_ret(s);
+tcg_out_ret(s, TCG_REG_LR);
}
--
1.8.3.1
[Qemu-devel] [PATCH v4 33/33] tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check
Removed from other targets in 56bbc2f967ce185fa1c5c39e1aeb5b68b26242e9.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 94f9ac1..a7d0785 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1852,12 +1852,6 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
static void tcg_target_init(TCGContext *s)
{
-#if !defined(CONFIG_USER_ONLY)
-/* fail safe */
-if ((1ULL << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) {
-tcg_abort();
-}
-#endif
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0x);
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0x);
--
1.8.3.1
[Qemu-devel] [PATCH v4 32/33] tcg-aarch64: Introduce tcg_out_ldst_pair
Combines 4 other inline functions and tidies the prologue.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 84
1 file changed, 27 insertions(+), 57 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index fa88e4b..94f9ac1 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -333,6 +333,10 @@ typedef enum {
INSN_BLR = 0xd63f,
INSN_RET = 0xd65f,
INSN_B_C = 0x5400,
+
+/* Load/store instructions */
+INSN_LDP = 0x2840,
+INSN_STP = 0x2800,
} AArch64Insn;
static inline enum aarch64_ldst_op_data
@@ -1331,56 +1335,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, int opc)
static uint8_t *tb_ret_addr;
-/* callee stack use example:
- stp x29, x30, [sp,#-32]!
- mov x29, sp
- stp x1, x2, [sp,#16]
- ...
- ldp x1, x2, [sp,#16]
- ldp x29, x30, [sp],#32
- ret
-*/
-
-/* push r1 and r2, and alloc stack space for a total of
- alloc_n elements (1 element=16 bytes, must be between 1 and 31. */
-static inline void tcg_out_push_pair(TCGContext *s, TCGReg addr,
- TCGReg r1, TCGReg r2, int alloc_n)
-{
-/* using indexed scaled simm7 STP 0x2880 | (ext) | 0x0100 (pre-idx)
- | alloc_n * (-1) << 16 | r2 << 10 | addr << 5 | r1 */
-assert(alloc_n > 0 && alloc_n < 0x20);
-alloc_n = (-alloc_n) & 0x3f;
-tcg_out32(s, 0xa980 | alloc_n << 16 | r2 << 10 | addr << 5 | r1);
-}
-
-/* dealloc stack space for a total of alloc_n elements and pop r1, r2. */
-static inline void tcg_out_pop_pair(TCGContext *s, TCGReg addr,
-TCGReg r1, TCGReg r2, int alloc_n)
-{
-/* using indexed scaled simm7 LDP 0x28c0 | (ext) | nothing (post-idx)
- | alloc_n << 16 | r2 << 10 | addr << 5 | r1 */
-assert(alloc_n > 0 && alloc_n < 0x20);
-tcg_out32(s, 0xa8c0 | alloc_n << 16 | r2 << 10 | addr << 5 | r1);
-}
-
-static inline void tcg_out_store_pair(TCGContext *s, TCGReg addr,
- TCGReg r1, TCGReg r2, int idx)
-{
-/* using register pair offset simm7 STP 0x2900 | (ext)
- | idx << 16 | r2 << 10 | addr << 5 | r1 */
-assert(idx > 0 && idx < 0x20);
-tcg_out32(s, 0xa900 | idx << 16 | r2 << 10 | addr << 5 | r1);
-}
-
-static inline void tcg_out_load_pair(TCGContext *s, TCGReg addr,
- TCGReg r1, TCGReg r2, int idx)
-{
-/* using register pair offset simm7 LDP 0x2940 | (ext)
- | idx << 16 | r2 << 10 | addr << 5 | r1 */
-assert(idx > 0 && idx < 0x20);
-tcg_out32(s, 0xa940 | idx << 16 | r2 << 10 | addr << 5 | r1);
-}
-
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS])
@@ -1937,17 +1891,32 @@ static void tcg_target_init(TCGContext *s)
+ TCG_TARGET_STACK_ALIGN - 1) \
& ~(TCG_TARGET_STACK_ALIGN - 1))
+static void tcg_out_ldst_pair(TCGContext *s, AArch64Insn insn,
+ TCGReg r1, TCGReg r2, TCGReg base,
+ tcg_target_long ofs, bool pre, bool w)
+{
+insn |= 1u << 31; /* ext */
+insn |= pre << 24;
+insn |= w << 23;
+
+assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0);
+insn |= (ofs & (0x7f << 3)) << (15 - 3);
+
+tcg_out32(s, insn | r2 << 10 | base << 5 | r1);
+}
+
static void tcg_target_qemu_prologue(TCGContext *s)
{
TCGReg r;
/* Push (FP, LR) and allocate space for all saved registers. */
-tcg_out_push_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16);
+tcg_out_ldst_pair(s, INSN_STP, TCG_REG_FP, TCG_REG_LR,
+ TCG_REG_SP, -PUSH_SIZE, 1, 1);
/* Store callee-preserved regs x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
-int idx = (r - TCG_REG_X19) / 2 + 1;
-tcg_out_store_pair(s, TCG_REG_SP, r, r + 1, idx);
+int ofs = (r - TCG_REG_X19 + 2) * 8;
+tcg_out_ldst_pair(s, INSN_STP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
}
/* Make stack space for TCG locals. */
@@ -1976,12 +1945,13 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* Restore callee-preserved registers x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
-int idx = (r - TCG_REG_X19) / 2 + 1;
-tcg_out_load_pair(s, TCG_REG_SP, r, r + 1, idx);
+int ofs = (r - TCG_REG_X19 + 2) * 8;
+tcg_out_ldst_pair(s, INSN_LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0);
}
-/* Pop (FP, LR), restore SP to previous frame, return. */
-tcg_out_pop_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16);
+/* Pop (FP, LR), restore SP to previous frame. */
+tcg_out_ldst_pair(s, INSN_LDP, TCG_REG_FP, TCG_REG_LR,
+ TCG_REG_SP, PUSH_SIZE, 0, 1)
[Qemu-devel] [PATCH v4 26/33] tcg-aarch64: Avoid add with zero in tlb load
Some guest env are small enough to reach the tlb with only a 12-bit addition.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 24 ++--
1 file changed, 18 insertions(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 5691cc3..1905271 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1136,46 +1136,58 @@ static void add_qemu_ldst_label(TCGContext *s, int
is_ld, int opc,
slow path for the failure case, which will be patched later when finalizing
the slow path. Generated code returns the host addend in X1,
clobbers X0,X2,X3,TMP. */
-static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
-int s_bits, uint8_t **label_ptr, int mem_index, int is_read)
+static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, int s_bits,
+ uint8_t **label_ptr, int mem_index, int is_read)
{
TCGReg base = TCG_AREG0;
int tlb_offset = is_read ?
offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
+
/* Extract the TLB index from the address into X0.
X0 =
addr_reg */
tcg_out_ubfm(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, addr_reg,
TARGET_PAGE_BITS, TARGET_PAGE_BITS + CPU_TLB_BITS);
+
/* Store the page mask part of the address and the low s_bits into X3.
Later this allows checking for equality and alignment at the same time.
X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */
tcg_fmt_Rdn_limm(s, INSN_ANDI, TARGET_LONG_BITS == 64, TCG_REG_X3,
addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
+
/* Add any "high bits" from the tlb offset to the env address into X2,
to take advantage of the LSL12 form of the ADDI instruction.
X2 = env + (tlb_offset & 0xfff000) */
-tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
+if (tlb_offset & 0xfff000) {
+tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_X2, base,
+ tlb_offset & 0xfff000);
+base = TCG_REG_X2;
+}
+
/* Merge the tlb index contribution into X2.
- X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
-tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2,
+ X2 = base + (X0 << CPU_TLB_ENTRY_BITS) */
+tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, base,
TCG_REG_X0, CPU_TLB_ENTRY_BITS);
+
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32,
LDST_LD, TCG_REG_X0, TCG_REG_X2,
(tlb_offset & 0xfff));
+
/* Load the tlb addend. Do that early to avoid stalling.
X1 = load [X2 + (tlb_offset & 0xfff) + offsetof(addend)] */
tcg_out_ldst(s, LDST_64, LDST_LD, TCG_REG_X1, TCG_REG_X2,
(tlb_offset & 0xfff) + (offsetof(CPUTLBEntry, addend)) -
(is_read ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write)));
+
/* Perform the address comparison. */
tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
-*label_ptr = s->code_ptr;
+
/* If not equal, we jump to the slow path. */
+*label_ptr = s->code_ptr;
tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
}
--
1.8.3.1
[Qemu-devel] [PATCH v4 23/33] tcg-aarch64: Use ORRI in tcg_out_movi
The subset of logical immediates that we support is quite quick to test,
and such constants are quite common to want to load.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index cecda05..9effee7 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -573,6 +573,15 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
type = TCG_TYPE_I32;
}
+/* Check for bitfield immediates. For the benefit of 32-bit quantities,
+ use the sign-extended value. That lets us match rotated values such
+ as 0xffff with the same 64-bit logic matching 0xffff.
+ The truncation happens inside tcg_fmt_Rdn_limm. */
+if (is_limm(svalue)) {
+tcg_fmt_Rdn_limm(s, INSN_ORRI, type, rd, TCG_REG_XZR, svalue);
+return;
+}
+
/* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. For the benefit
of 32-bit quantities, compare the zero-extended normal value vs the
--
1.8.3.1
[Qemu-devel] [PATCH v4 25/33] tcg-aarch64: Use adrp in tcg_out_movi
Loading an qemu pointer as an immediate happens often. E.g.
- exit_tb $0x7fa8140013
+ exit_tb $0x7f81ee0013
...
- : d2800260mov x0, #0x13
- : f2b50280movkx0, #0xa814, lsl #16
- : f2c00fe0movkx0, #0x7f, lsl #32
+ : 90ff1000adrpx0, 0x7f81ee
+ : 91004c00add x0, x0, #0x13
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index e50abcb..5691cc3 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -323,6 +323,10 @@ typedef enum {
/* Conditional select instructions */
INSN_CSEL = 0x1a80,
INSN_CSINC = 0x1a800400,
+
+/* PC relative addressing instructions */
+INSN_ADR = 0x1000,
+INSN_ADRP = 0x9000,
} AArch64Insn;
static inline enum aarch64_ldst_op_data
@@ -510,6 +514,12 @@ static inline void tcg_fmt_Rd_uimm(TCGContext *s,
AArch64Insn insn,
tcg_out32(s, insn | sf << 31 | shift << (21 - 4) | half << 5 | rd);
}
+static inline void tcg_fmt_Rd_disp21(TCGContext *s, AArch64Insn insn,
+ TCGReg rd, tcg_target_long disp)
+{
+tcg_out32(s, insn | (disp & 3) << 29 | (disp & 0x1c) << (5 - 2) | rd);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -561,7 +571,7 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
AArch64Insn insn;
int i, wantinv, shift;
tcg_target_long svalue = value;
-tcg_target_long ivalue, imask;
+tcg_target_long ivalue, imask, disp;
/* For 32-bit values, discard potential garbage in value. For 64-bit
values within [2**31, 2**32-1], we can create smaller sequences by
@@ -593,6 +603,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
return;
}
+/* Look for host pointer values within 4G of the PC. This happens
+ often when loading pointers to QEMU's own data structures. */
+disp = (value >> 12) - ((intptr_t)s->code_ptr >> 12);
+if (disp == sextract64(disp, 0, 21)) {
+tcg_fmt_Rd_disp21(s, INSN_ADRP, rd, disp);
+if (value & 0xfff) {
+tcg_fmt_Rdn_aimm(s, INSN_ADDI, type, rd, rd, value & 0xfff);
+}
+return;
+}
+
/* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. For the benefit
of 32-bit quantities, compare the zero-extended normal value vs the
--
1.8.3.1
[Qemu-devel] [PATCH v4 19/33] tcg-aarch64: Support muluh, mulsh
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 12
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index bc1ca84..b7f7fa5 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -300,6 +300,8 @@ typedef enum {
INSN_LSRV = 0x1ac02400,
INSN_ASRV = 0x1ac02800,
INSN_RORV = 0x1ac02c00,
+INSN_SMULH = 0x9b407c00,
+INSN_UMULH = 0x9bc07c00,
/* Bitfield instructions */
INSN_BFM = 0x3300,
@@ -1597,6 +1599,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[5], const_args[4], const_args[5], c2);
break;
+case INDEX_op_muluh_i64:
+tcg_fmt_Rdnm(s, INSN_UMULH, 1, a0, a1, a2);
+break;
+case INDEX_op_mulsh_i64:
+tcg_fmt_Rdnm(s, INSN_SMULH, 1, a0, a1, a2);
+break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1724,6 +1733,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+{ INDEX_op_muluh_i64, { "r", "r", "r" } },
+{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f311954..52c6c23 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -89,8 +89,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i640
#define TCG_TARGET_HAS_muls2_i640
-#define TCG_TARGET_HAS_muluh_i640
-#define TCG_TARGET_HAS_mulsh_i640
+#define TCG_TARGET_HAS_muluh_i641
+#define TCG_TARGET_HAS_mulsh_i641
enum {
TCG_AREG0 = TCG_REG_X19,
--
1.8.3.1
[Qemu-devel] [PATCH v4 17/33] tcg-aarch64: Support deposit
Also tidy the implementation of ubfm, sbfm, extr in order to share code.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 49 +++-
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 38 insertions(+), 15 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 5f2c437..894a1d9 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -290,6 +290,12 @@ typedef enum {
INSN_ASRV = 0x1ac02800,
INSN_RORV = 0x1ac02c00,
+/* Bitfield instructions */
+INSN_BFM = 0x3300,
+INSN_SBFM = 0x1300,
+INSN_UBFM = 0x5300,
+INSN_EXTR = 0x1380,
+
/* Conditional select instructions */
INSN_CSEL = 0x1a80,
INSN_CSINC = 0x1a800400,
@@ -610,28 +616,30 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext,
tcg_out32(s, base | rm << 16 | rn << 5 | rd);
}
+static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned int a, unsigned int b)
+{
+tcg_fmt_Rdn_nrs(s, INSN_BFM, ext, rd, rn, ext, a, b);
+}
+
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
-/* Using UBFM 0x5300 Wd, Wn, a, b */
-unsigned int base = ext ? 0xd340 : 0x5300;
-tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+tcg_fmt_Rdn_nrs(s, INSN_UBFM, ext, rd, rn, ext, a, b);
}
static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
-/* Using SBFM 0x1300 Wd, Wn, a, b */
-unsigned int base = ext ? 0x9340 : 0x1300;
-tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+tcg_fmt_Rdn_nrs(s, INSN_SBFM, ext, rd, rn, ext, a, b);
}
static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, TCGReg rm, unsigned int a)
{
-/* Using EXTR 0x1380 Wd, Wn, Wm, a */
-unsigned int base = ext ? 0x93c0 : 0x1380;
-tcg_out32(s, base | rm << 16 | a << 10 | rn << 5 | rd);
+/* ??? Abuse of the fmt function, but RM field is at the same location
+ as the IMMR field and we do still need to set N = SF for IMMS. */
+tcg_fmt_Rdn_nrs(s, INSN_EXTR, ext, rd, rn, ext, rm, a);
}
static inline void tcg_out_shl(TCGContext *s, TCGType ext,
@@ -673,6 +681,15 @@ static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
}
+static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned lsb, unsigned width)
+{
+unsigned size = ext ? 64 : 32;
+unsigned a = (size - lsb) & (size - 1);
+unsigned b = width - 1;
+tcg_out_bfm(s, ext, rd, rn, a, b);
+}
+
static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
tcg_target_long b, bool const_b)
{
@@ -828,8 +845,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGType ext,
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, int s_bits,
TCGReg rd, TCGReg rn)
{
-/* using ALIASes SXTB 0x13001c00, SXTH 0x13003c00, SXTW 0x93407c00
- of SBFM Xd, Xn, #0, #7|15|31 */
+/* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
int bits = 8 * (1 << s_bits) - 1;
tcg_out_sbfm(s, ext, rd, rn, 0, bits);
}
@@ -837,8 +853,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType ext,
int s_bits,
static inline void tcg_out_uxt(TCGContext *s, int s_bits,
TCGReg rd, TCGReg rn)
{
-/* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00
- of UBFM Wd, Wn, #0, #7|15 */
+/* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
int bits = 8 * (1 << s_bits) - 1;
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
@@ -1504,6 +1519,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_movr(s, 0, a0, a1);
break;
+case INDEX_op_deposit_i64:
+case INDEX_op_deposit_i32:
+tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
+break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1623,6 +1643,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_ext16u_i64, { "r", "r" } },
{ INDEX_op_ext32u_i64, { "r", "r" } },
+{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 85e9929..ac1c97d 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -55,7 +55,7 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_deposit_i32 0
+#define TC
[Qemu-devel] [PATCH v4 18/33] tcg-aarch64: Support add2, sub2
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 78
tcg/aarch64/tcg-target.h | 8 ++---
2 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 894a1d9..bc1ca84 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -115,6 +115,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_AIMM 0x200
#define TCG_CT_CONST_LIMM 0x400
#define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_MONE 0x1000
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -148,6 +149,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* Valid for logical immediate. */
ct->ct |= TCG_CT_CONST_LIMM;
break;
+case 'M': /* minus one */
+ct->ct |= TCG_CT_CONST_MONE;
+break;
case 'Z': /* zero */
ct->ct |= TCG_CT_CONST_ZERO;
break;
@@ -205,6 +209,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
+if ((ct & TCG_CT_CONST_MONE) && val == -1) {
+return 1;
+}
return 0;
}
@@ -284,6 +291,10 @@ typedef enum {
INSN_SUB = 0x4b00,
INSN_SUBS = 0x6b00,
+/* Add/subtract with carry instructions */
+INSN_ADC = 0x1a00,
+INSN_SBC = 0x5a00,
+
/* Data-processing (2 source) instructions */
INSN_LSLV = 0x1ac02000,
INSN_LSRV = 0x1ac02400,
@@ -869,6 +880,47 @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg
rd,
tcg_fmt_Rdn_aimm(s, insn, ext, rd, rn, aimm);
}
+static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
+ TCGReg rh, TCGReg al, TCGReg ah,
+ tcg_target_long bl, tcg_target_long bh,
+ bool const_bl, bool const_bh, bool sub)
+{
+TCGReg orig_rl = rl;
+AArch64Insn insn;
+
+if (rl == ah || (!const_bh && rl == bh)) {
+rl = TCG_REG_TMP;
+}
+
+if (const_bl) {
+insn = INSN_ADDSI;
+if ((bl < 0) ^ sub) {
+insn = INSN_SUBSI;
+bl = -bl;
+}
+tcg_fmt_Rdn_aimm(s, insn, ext, rl, al, bl);
+} else {
+tcg_fmt_Rdnm(s, sub ? INSN_SUBS : INSN_ADDS, ext, rl, al, bl);
+}
+
+insn = INSN_ADC;
+if (const_bh) {
+/* Note that the only two constants we support are 0 and -1, and
+ that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */
+if ((bh != 0) ^ sub) {
+insn = INSN_SBC;
+}
+bh = TCG_REG_XZR;
+} else if (sub) {
+insn = INSN_SBC;
+}
+tcg_fmt_Rdnm(s, insn, ext, rh, ah, bh);
+
+if (rl != orig_rl) {
+tcg_out_movr(s, ext, orig_rl, rl);
+}
+}
+
static inline void tcg_out_nop(TCGContext *s)
{
tcg_out32(s, 0xd503201f);
@@ -1524,6 +1576,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
break;
+case INDEX_op_add2_i32:
+a2 = (int32_t)args[4];
+c2 = false;
+goto do_addsub2;
+case INDEX_op_add2_i64:
+a2 = args[4];
+c2 = false;
+goto do_addsub2;
+case INDEX_op_sub2_i32:
+a2 = (int32_t)args[4];
+c2 = true;
+goto do_addsub2;
+case INDEX_op_sub2_i64:
+a2 = args[4];
+c2 = true;
+goto do_addsub2;
+do_addsub2:
+tcg_out_addsub2(s, ext, a0, a1, REG0(2), REG0(3), a2,
+args[5], const_args[4], const_args[5], c2);
+break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1646,6 +1719,11 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
+{ INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
+{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ac1c97d..f311954 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -57,8 +57,8 @@ typedef enum {
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_add2_i32 0
-#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i320
#define TCG_TARGET_HAS_muls2_i320
#define TCG_TARGET_HAS_muluh_i320
@@ -85,8 +85,8 @@ typedef enum {
#define TCG_TARGET_HAS_nor_i64 0
[Qemu-devel] [PATCH v4 15/33] tcg-aarch64: Support movcond
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 24 +++-
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 08a0cc4..e9a0f9b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -289,6 +289,10 @@ typedef enum {
INSN_LSRV = 0x1ac02400,
INSN_ASRV = 0x1ac02800,
INSN_RORV = 0x1ac02c00,
+
+/* Conditional select instructions */
+INSN_CSEL = 0x1a80,
+INSN_CSINC = 0x1a800400,
} AArch64Insn;
static inline enum aarch64_ldst_op_data
@@ -451,6 +455,14 @@ static void tcg_fmt_Rdn_limm(TCGContext *s, AArch64Insn
insn, TCGType sf,
tcg_fmt_Rdn_nrs(s, insn, sf, rd, rn, sf, r, c);
}
+static inline void tcg_fmt_Rdnm_cond(TCGContext *s, AArch64Insn insn,
+ TCGType sf, TCGReg rd, TCGReg rn,
+ TCGReg rm, TCGCond c)
+{
+tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd
+ | tcg_cond_to_aarch64[c] << 12);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -1414,7 +1426,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* FALLTHRU */
case INDEX_op_setcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
-tcg_out_cset(s, 0, a0, args[3]);
+tcg_out_cset(s, ext, a0, args[3]);
+break;
+
+case INDEX_op_movcond_i32:
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_movcond_i64:
+tcg_out_cmp(s, ext, a1, a2, c2);
+tcg_fmt_Rdnm_cond(s, INSN_CSEL, ext, a0, REG0(3), REG0(4), args[5]);
break;
case INDEX_op_qemu_ld8u:
@@ -1573,6 +1593,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_brcond_i64, { "r", "rA" } },
{ INDEX_op_setcond_i32, { "r", "r", "rwA" } },
{ INDEX_op_setcond_i64, { "r", "r", "rA" } },
+{ INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },
+{ INDEX_op_movcond_i64, { "r", "r", "rwA", "rZ", "rZ" } },
{ INDEX_op_qemu_ld8u, { "r", "l" } },
{ INDEX_op_qemu_ld8s, { "r", "l" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index efc506b..85e9929 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -56,7 +56,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i320
@@ -84,7 +84,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i640
--
1.8.3.1
[Qemu-devel] [PATCH v4 31/33] tcg-aarch64: Reuse FP and LR in translated code
We don't need the FP within translated code, and the LR is
otherwise unused.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 36 +++-
tcg/aarch64/tcg-target.h | 32 +---
2 files changed, 32 insertions(+), 36 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 7d2fd99..fa88e4b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -22,10 +22,7 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7",
"%x8", "%x9", "%x10", "%x11", "%x12", "%x13", "%x14", "%x15",
"%x16", "%x17", "%x18", "%x19", "%x20", "%x21", "%x22", "%x23",
-"%x24", "%x25", "%x26", "%x27", "%x28",
-"%fp", /* frame pointer */
-"%lr", /* link register */
-"%sp", /* stack pointer */
+"%x24", "%x25", "%x26", "%x27", "%x28", "%x29", "%x30", "%sp",
};
#endif /* NDEBUG */
@@ -38,18 +35,19 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
static const int tcg_target_reg_alloc_order[] = {
TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
-TCG_REG_X28, /* we will reserve this for GUEST_BASE if configured */
+TCG_REG_X28,
+TCG_REG_X29, /* maybe used for TCG_REG_GUEST_BASE */
-TCG_REG_X9, TCG_REG_X10, TCG_REG_X11, TCG_REG_X12,
-TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
+TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
+TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
TCG_REG_X16, TCG_REG_X17,
-TCG_REG_X18, TCG_REG_X19, /* will not use these, see tcg_target_init */
-
TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
-TCG_REG_X8, /* will not use, see tcg_target_init */
+/* X18 reserved by system */
+/* X19 reserved for AREG0 */
+/* X30 reserved as temporary */
};
static const int tcg_target_call_iarg_regs[8] = {
@@ -60,13 +58,13 @@ static const int tcg_target_call_oarg_regs[1] = {
TCG_REG_X0
};
-#define TCG_REG_TMP TCG_REG_X8
+#define TCG_REG_TMP TCG_REG_X30
#ifndef CONFIG_SOFTMMU
-# if defined(CONFIG_USE_GUEST_BASE)
-# define TCG_REG_GUEST_BASE TCG_REG_X28
+# ifdef CONFIG_USE_GUEST_BASE
+# define TCG_REG_GUEST_BASE TCG_REG_X29
# else
-# define TCG_REG_GUEST_BASE TCG_REG_XZR
+# define TCG_REG_GUEST_BASE TCG_REG_XZR
# endif
#endif
@@ -1919,11 +1917,10 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_X12) | (1 << TCG_REG_X13) |
(1 << TCG_REG_X14) | (1 << TCG_REG_X15) |
(1 << TCG_REG_X16) | (1 << TCG_REG_X17) |
- (1 << TCG_REG_X18));
+ (1 << TCG_REG_X18) | (1 << TCG_REG_X30));
tcg_regset_clear(s->reserved_regs);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
-tcg_regset_set_reg(s->reserved_regs, TCG_REG_FP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_X18); /* platform register */
@@ -1947,13 +1944,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* Push (FP, LR) and allocate space for all saved registers. */
tcg_out_push_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16);
-/* FP -> callee_saved */
-tcg_out_movr_sp(s, 1, TCG_REG_FP, TCG_REG_SP);
-
/* Store callee-preserved regs x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
int idx = (r - TCG_REG_X19) / 2 + 1;
-tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx);
+tcg_out_store_pair(s, TCG_REG_SP, r, r + 1, idx);
}
/* Make stack space for TCG locals. */
@@ -1983,7 +1977,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* Restore callee-preserved registers x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
int idx = (r - TCG_REG_X19) / 2 + 1;
-tcg_out_load_pair(s, TCG_REG_FP, r, r + 1, idx);
+tcg_out_load_pair(s, TCG_REG_SP, r, r + 1, idx);
}
/* Pop (FP, LR), restore SP to previous frame, return. */
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 8b55ff9..76810f1 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -17,17 +17,23 @@
#undef TCG_TARGET_STACK_GROWSUP
typedef enum {
-TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4,
-TCG_REG_X5, TCG_REG_X6, TCG_REG_X7, TCG_REG_X8, TCG_REG_X9,
-TCG_REG_X10, TCG_REG_X11, TCG_REG_X12, TCG_REG_X13, TCG_REG_X14,
-TCG_REG_X15, TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
-TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23, TCG_REG_X24,
-TCG_REG_X25, TCG_REG_X26, TCG_REG_X27, TCG_REG_X28,
-TCG_REG_FP, /* frame pointer */
-TCG_REG_LR, /* link register */
-TCG_REG_SP, /* stack pointer or zero register */
-TCG_REG_XZR = TCG_REG_SP /* same registe
[Qemu-devel] [PATCH v4 16/33] tcg-aarch64: Use tcg_fmt_Rdnm_cond for setcond
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 12 +++-
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index e9a0f9b..5f2c437 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -690,14 +690,6 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg
a,
}
}
-static inline void tcg_out_cset(TCGContext *s, TCGType ext,
-TCGReg rd, TCGCond c)
-{
-/* Using CSET alias of CSINC 0x1a800400 Xd, XZR, XZR, invert(cond) */
-unsigned int base = ext ? 0x9a9f07e0 : 0x1a9f07e0;
-tcg_out32(s, base | tcg_cond_to_aarch64[tcg_invert_cond(c)] << 12 | rd);
-}
-
static inline void tcg_out_goto(TCGContext *s, tcg_target_long target)
{
tcg_target_long offset;
@@ -1426,7 +1418,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* FALLTHRU */
case INDEX_op_setcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
-tcg_out_cset(s, ext, a0, args[3]);
+/* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
+tcg_fmt_Rdnm_cond(s, INSN_CSINC, 0, a0, TCG_REG_XZR, TCG_REG_XZR,
+ tcg_invert_cond(args[3]));
break;
case INDEX_op_movcond_i32:
--
1.8.3.1
[Qemu-devel] [PATCH v4 30/33] tcg-aarch64: Implement tcg_register_jit
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 93
1 file changed, 70 insertions(+), 23 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 335a5d0..7d2fd99 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1930,30 +1930,27 @@ static void tcg_target_init(TCGContext *s)
tcg_add_target_add_op_defs(aarch64_op_defs);
}
+/* Saving pairs: (X19, X20) .. (X27, X28), (X29(fp), X30(lr)). */
+#define PUSH_SIZE ((30 - 19 + 1) * 8)
+
+#define FRAME_SIZE \
+((PUSH_SIZE \
+ + TCG_STATIC_CALL_ARGS_SIZE \
+ + CPU_TEMP_BUF_NLONGS * sizeof(long) \
+ + TCG_TARGET_STACK_ALIGN - 1) \
+ & ~(TCG_TARGET_STACK_ALIGN - 1))
+
static void tcg_target_qemu_prologue(TCGContext *s)
{
-/* NB: frame sizes are in 16 byte stack units! */
-int frame_size_callee_saved, frame_size_tcg_locals;
TCGReg r;
-/* save pairs (FP, LR) and (X19, X20) .. (X27, X28) */
-frame_size_callee_saved = (1) + (TCG_REG_X28 - TCG_REG_X19) / 2 + 1;
-
-/* frame size requirement for TCG local variables */
-frame_size_tcg_locals = TCG_STATIC_CALL_ARGS_SIZE
-+ CPU_TEMP_BUF_NLONGS * sizeof(long)
-+ (TCG_TARGET_STACK_ALIGN - 1);
-frame_size_tcg_locals &= ~(TCG_TARGET_STACK_ALIGN - 1);
-frame_size_tcg_locals /= TCG_TARGET_STACK_ALIGN;
-
-/* push (FP, LR) and update sp */
-tcg_out_push_pair(s, TCG_REG_SP,
- TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
+/* Push (FP, LR) and allocate space for all saved registers. */
+tcg_out_push_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16);
/* FP -> callee_saved */
tcg_out_movr_sp(s, 1, TCG_REG_FP, TCG_REG_SP);
-/* store callee-preserved regs x19..x28 using FP -> callee_saved */
+/* Store callee-preserved regs x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
int idx = (r - TCG_REG_X19) / 2 + 1;
tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx);
@@ -1961,7 +1958,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* Make stack space for TCG locals. */
tcg_fmt_Rdn_aimm(s, INSN_SUBI, 1, TCG_REG_SP, TCG_REG_SP,
- frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
+ FRAME_SIZE - PUSH_SIZE);
/* inform TCG about how to find TCG locals with register, offset, size */
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
@@ -1981,17 +1978,67 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* Remove TCG locals stack space. */
tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_SP, TCG_REG_SP,
- frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
+ FRAME_SIZE - PUSH_SIZE);
-/* restore registers x19..x28.
- FP must be preserved, so it still points to callee_saved area */
+/* Restore callee-preserved registers x19..x28. */
for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) {
int idx = (r - TCG_REG_X19) / 2 + 1;
tcg_out_load_pair(s, TCG_REG_FP, r, r + 1, idx);
}
-/* pop (FP, LR), restore SP to previous frame, return */
-tcg_out_pop_pair(s, TCG_REG_SP,
- TCG_REG_FP, TCG_REG_LR, frame_size_callee_saved);
+/* Pop (FP, LR), restore SP to previous frame, return. */
+tcg_out_pop_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16);
tcg_out_ret(s, TCG_REG_LR);
}
+
+typedef struct {
+DebugFrameCIE cie;
+DebugFrameFDEHeader fde;
+uint8_t fde_def_cfa[4];
+uint8_t fde_reg_ofs[24];
+} DebugFrame;
+
+/* We're expecting a 2 byte uleb128 encoded value. */
+QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
+
+#define ELF_HOST_MACHINE EM_AARCH64
+
+static DebugFrame debug_frame = {
+.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
+.cie.id = -1,
+.cie.version = 1,
+.cie.code_align = 1,
+.cie.data_align = 0x78, /* sleb128 -8 */
+.cie.return_column = 16,
+
+/* Total FDE size does not include the "len" member. */
+.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
+
+.fde_def_cfa = {
+12, 7, /* DW_CFA_def_cfa %rsp, ... */
+(FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
+(FRAME_SIZE >> 7)
+},
+.fde_reg_ofs = {
+0x80 + 30, 1, /* DW_CFA_offset, lr, -8 */
+0x80 + 29, 2, /* DW_CFA_offset, fp, -16 */
+0x80 + 28, 3, /* DW_CFA_offset, x28, -24 */
+0x80 + 27, 4, /* DW_CFA_offset, x27, -32 */
+0x80 + 26, 5, /* DW_CFA_offset, x26, -40 */
+0x80 + 25, 6, /* DW_CFA_offset, x25, -48 */
+0x80 + 24, 7, /* DW_CFA_offset, x24, -56 */
+0x80 + 23, 8, /* DW_CFA_offset, x23, -64 */
+
[Qemu-devel] [PATCH v4 10/33] tcg-aarch64: Implement mov with tcg_fmt_* functions
Avoid the magic numbers in the current implementation.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 56625a9..93badfd 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -379,13 +379,18 @@ static inline void tcg_out_ldst_12(TCGContext *s,
| op_type << 20 | scaled_uimm << 10 | rn << 5 | rd);
}
+/* Register to register move using ORR (shifted register with no shift). */
static inline void tcg_out_movr(TCGContext *s, TCGType ext,
-TCGReg rd, TCGReg src)
+TCGReg rd, TCGReg rm)
{
-/* register to register move using MOV (shifted register with no shift) */
-/* using MOV 0x2a0003e0 | (shift).. */
-unsigned int base = ext ? 0xaa0003e0 : 0x2a0003e0;
-tcg_out32(s, base | src << 16 | rd);
+tcg_fmt_Rdnm(s, INSN_ORR, ext, rd, TCG_REG_XZR, rm);
+}
+
+/* Register to register move using ADDI (move to/from SP). */
+static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn)
+{
+tcg_fmt_Rdn_aimm(s, INSN_ADDI, ext, rd, rn, 0);
}
static inline void tcg_out_movi_aux(TCGContext *s,
@@ -460,15 +465,6 @@ static inline void tcg_out_ldst(TCGContext *s, enum
aarch64_ldst_op_data data,
tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP);
}
-/* mov alias implemented with add immediate, useful to move to/from SP */
-static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn)
-{
-/* using ADD 0x1100 | (ext) | rn << 5 | rd */
-unsigned int base = ext ? 0x9100 : 0x1100;
-tcg_out32(s, base | rn << 5 | rd);
-}
-
static inline void tcg_out_mov(TCGContext *s,
TCGType type, TCGReg ret, TCGReg arg)
{
--
1.8.3.1
[Qemu-devel] [PATCH v4 27/33] tcg-aarch64: Pass return address to load/store helpers directly.
Signed-off-by: Richard Henderson
---
include/exec/exec-all.h | 11 ---
tcg/aarch64/tcg-target.c | 44 ++--
2 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index beb4149..8b106f5 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -340,17 +340,6 @@ static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
ra += b;/* apply the displacement */
return ra;
}
-# elif defined(__aarch64__)
-# define GETRA_LDST(RA) tcg_getra_ldst(RA)
-static inline uintptr_t tcg_getra_ldst(uintptr_t ra)
-{
-int32_t b;
-ra += 4;/* skip one instruction */
-b = *(int32_t *)ra; /* load the branch insn */
-b = (b << 6) >> (6 - 2);/* extract the displacement */
-ra += b;/* apply the displacement */
-return ra;
-}
# endif
#endif /* CONFIG_QEMU_LDST_OPTIMIZATION */
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 1905271..ce3c17b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1038,39 +1038,46 @@ static inline void tcg_out_addsub2(TCGContext *s, int
ext, TCGReg rl,
}
}
-static inline void tcg_out_nop(TCGContext *s)
-{
-tcg_out32(s, 0xd503201f);
-}
-
#ifdef CONFIG_SOFTMMU
-/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
- int mmu_idx) */
+/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
+ * int mmu_idx, uintptr_t ra)
+ */
static const void * const qemu_ld_helpers[4] = {
-helper_ldb_mmu,
-helper_ldw_mmu,
-helper_ldl_mmu,
-helper_ldq_mmu,
+helper_ret_ldub_mmu,
+helper_ret_lduw_mmu,
+helper_ret_ldul_mmu,
+helper_ret_ldq_mmu,
};
-/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
- uintxx_t val, int mmu_idx) */
+/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr,
+ * uintxx_t val, int mmu_idx, uintptr_t ra)
+ */
static const void * const qemu_st_helpers[4] = {
-helper_stb_mmu,
-helper_stw_mmu,
-helper_stl_mmu,
-helper_stq_mmu,
+helper_ret_stb_mmu,
+helper_ret_stw_mmu,
+helper_ret_stl_mmu,
+helper_ret_stq_mmu,
};
+static inline void tcg_out_adr(TCGContext *s, TCGReg rd, tcg_target_long addr)
+{
+addr -= (tcg_target_long)s->code_ptr;
+assert(addr == sextract64(addr, 0, 21));
+tcg_fmt_Rd_disp21(s, INSN_ADR, rd, addr);
+}
+
static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
{
reloc_pc19(lb->label_ptr[0], (tcg_target_long)s->code_ptr);
tcg_out_movr(s, 1, TCG_REG_X0, TCG_AREG0);
tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
+tcg_out_adr(s, TCG_REG_X3, (uintptr_t)lb->raddr);
+
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
(tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
tcg_out_callr(s, TCG_REG_TMP);
+
if (lb->opc & 0x04) {
tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0);
} else {
@@ -1088,11 +1095,12 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_movr(s, (TARGET_LONG_BITS == 64), TCG_REG_X1, lb->addrlo_reg);
tcg_out_movr(s, 1, TCG_REG_X2, lb->datalo_reg);
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
+tcg_out_adr(s, TCG_REG_X4, (uintptr_t)lb->raddr);
+
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
(tcg_target_long)qemu_st_helpers[lb->opc & 3]);
tcg_out_callr(s, TCG_REG_TMP);
-tcg_out_nop(s);
tcg_out_goto(s, (tcg_target_long)lb->raddr);
}
--
1.8.3.1
[Qemu-devel] [PATCH v4 28/33] tcg-aarch64: Use tcg_out_call for qemu_ld/st
In some cases, a direct branch will be in range.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index ce3c17b..3d1108c 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1074,9 +1074,7 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X2, lb->mem_index);
tcg_out_adr(s, TCG_REG_X3, (uintptr_t)lb->raddr);
-tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
- (tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
-tcg_out_callr(s, TCG_REG_TMP);
+tcg_out_call(s, (tcg_target_long)qemu_ld_helpers[lb->opc & 3]);
if (lb->opc & 0x04) {
tcg_out_sxt(s, 1, lb->opc & 3, lb->datalo_reg, TCG_REG_X0);
@@ -1097,9 +1095,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s,
TCGLabelQemuLdst *lb)
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_X3, lb->mem_index);
tcg_out_adr(s, TCG_REG_X4, (uintptr_t)lb->raddr);
-tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP,
- (tcg_target_long)qemu_st_helpers[lb->opc & 3]);
-tcg_out_callr(s, TCG_REG_TMP);
+tcg_out_call(s, (tcg_target_long)qemu_st_helpers[lb->opc & 3]);
tcg_out_goto(s, (tcg_target_long)lb->raddr);
}
--
1.8.3.1
[Qemu-devel] [PATCH v4 08/33] tcg-aarch64: Introduce tcg_fmt_Rdnm and tcg_fmt_Rdnm_lsl
Now that we've converted opcode fields to pre-shifted insns, we
can merge the implementation of arithmetic and shift insns.
Simplify the left/right shift parameter to just the left shift
needed by tcg_out_tlb_read.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 78 +++-
1 file changed, 38 insertions(+), 40 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index cc56fe5..0e7b67b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -302,6 +302,30 @@ static inline uint32_t tcg_in32(TCGContext *s)
return v;
}
+/*
+ * Encode various formats.
+ */
+
+/* This function can be used for both Arithmetic and Logical (shifted register)
+ type insns. Since we don't actually use the other available shifts, we only
+ support LSL here. */
+static inline void tcg_fmt_Rdnm_lsl(TCGContext *s, AArch64Insn insn,
+TCGType sf, TCGReg rd, TCGReg rn,
+TCGReg rm, int imm6)
+{
+/* Note that LSL is bits {23,22} = 0. */
+tcg_out32(s, insn | sf << 31 | imm6 << 10 | rm << 16 | rn << 5 | rd);
+}
+
+/* This function can be used for most insns with 2 input registers and one
+ output register. This includes Arithmetic (shifted register, sans shift),
+ Logical, Shift, Multiply, Divide, and Bit operation. */
+static inline void tcg_fmt_Rdnm(TCGContext *s, AArch64Insn insn, TCGType sf,
+TCGReg rd, TCGReg rn, TCGReg rm)
+{
+tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -445,23 +469,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
arg, arg1, arg2);
}
-static inline void tcg_out_arith(TCGContext *s, AArch64Insn insn,
- TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm,
- int shift_imm)
-{
-/* Using shifted register arithmetic operations */
-/* if extended register operation (64bit) just OR with 0x80 << 24 */
-unsigned int shift, base = insn | (ext ? 0x8000 : 0);
-if (shift_imm == 0) {
-shift = 0;
-} else if (shift_imm > 0) {
-shift = shift_imm << 10 | 1 << 22;
-} else /* (shift_imm < 0) */ {
-shift = (-shift_imm) << 10;
-}
-tcg_out32(s, base | rm << 16 | shift | rn << 5 | rd);
-}
-
static inline void tcg_out_mul(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm)
{
@@ -470,15 +477,6 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext,
tcg_out32(s, base | rm << 16 | rn << 5 | rd);
}
-static inline void tcg_out_shiftrot_reg(TCGContext *s,
-AArch64Insn insn, TCGType ext,
-TCGReg rd, TCGReg rn, TCGReg rm)
-{
-/* using 2-source data processing instructions 0x1ac02000 */
-unsigned int base = insn | (ext ? 0x8000 : 0);
-tcg_out32(s, base | rm << 16 | rn << 5 | rd);
-}
-
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
@@ -546,7 +544,7 @@ static inline void tcg_out_cmp(TCGContext *s, TCGType ext,
TCGReg rn,
TCGReg rm)
{
/* Using CMP alias SUBS wzr, Wn, Wm */
-tcg_out_arith(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm, 0);
+tcg_fmt_Rdnm(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm);
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -906,8 +904,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
/* Merge the tlb index contribution into X2.
X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
-tcg_out_arith(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2,
- TCG_REG_X0, -CPU_TLB_ENTRY_BITS);
+tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2,
+ TCG_REG_X0, CPU_TLB_ENTRY_BITS);
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32,
@@ -1183,27 +1181,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_i64:
case INDEX_op_add_i32:
-tcg_out_arith(s, INSN_ADD, ext, a0, a1, a2, 0);
+tcg_fmt_Rdnm(s, INSN_ADD, ext, a0, a1, a2);
break;
case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
-tcg_out_arith(s, INSN_SUB, ext, a0, a1, a2, 0);
+tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, a1, a2);
break;
case INDEX_op_and_i64:
case INDEX_op_and_i32:
-tcg_out_arith(s, INSN_AND, ext, a0, a1, a2, 0);
+
[Qemu-devel] [PATCH v4 13/33] tcg-aarch64: Support andc, orc, eqv, not
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 65 ++--
tcg/aarch64/tcg-target.h | 16 ++--
2 files changed, 65 insertions(+), 16 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index bc651ac..5b4 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -258,10 +258,12 @@ typedef enum {
INSN_EORI = 0x5200,
/* Logical shifted register instructions */
-INSN_AND= 0x0a00,
-INSN_ORR= 0x2a00,
-INSN_EOR= 0x4a00,
-INSN_ANDS = 0x6a00,
+INSN_AND = 0x0a00,
+INSN_BIC = 0x0a20,
+INSN_ORR = 0x2a00,
+INSN_ORN = 0x2a20,
+INSN_EOR = 0x4a00,
+INSN_EON = 0x4a20,
/* Add/subtract immediate instructions */
INSN_ADDI = 0x1100,
@@ -270,10 +272,10 @@ typedef enum {
INSN_SUBSI = 0x7100,
/* Add/subtract shifted register instructions */
-INSN_ADD= 0x0b00,
-INSN_ADDS = 0x2b00,
-INSN_SUB= 0x4b00,
-INSN_SUBS = 0x6b00,
+INSN_ADD = 0x0b00,
+INSN_ADDS = 0x2b00,
+INSN_SUB = 0x4b00,
+INSN_SUBS = 0x6b00,
/* Data-processing (2 source) instructions */
INSN_LSLV = 0x1ac02000,
@@ -1270,6 +1272,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+case INDEX_op_andc_i32:
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_andc_i64:
+if (c2) {
+tcg_fmt_Rdn_limm(s, INSN_ANDI, ext, a0, a1, ~a2);
+} else {
+tcg_fmt_Rdnm(s, INSN_BIC, ext, a0, a1, a2);
+}
+break;
+
case INDEX_op_or_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1281,6 +1294,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+case INDEX_op_orc_i32:
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_orc_i64:
+if (c2) {
+tcg_fmt_Rdn_limm(s, INSN_ORRI, ext, a0, a1, ~a2);
+} else {
+tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, a1, a2);
+}
+break;
+
case INDEX_op_xor_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1292,6 +1316,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+case INDEX_op_eqv_i32:
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_eqv_i64:
+if (c2) {
+tcg_fmt_Rdn_limm(s, INSN_EORI, ext, a0, a1, ~a2);
+} else {
+tcg_fmt_Rdnm(s, INSN_EON, ext, a0, a1, a2);
+}
+break;
+
+case INDEX_op_not_i64:
+case INDEX_op_not_i32:
+tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, TCG_REG_XZR, a1);
+break;
+
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
tcg_out_mul(s, ext, a0, a1, a2);
@@ -1488,6 +1528,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_or_i64, { "r", "r", "rL" } },
{ INDEX_op_xor_i32, { "r", "r", "rwL" } },
{ INDEX_op_xor_i64, { "r", "r", "rL" } },
+{ INDEX_op_andc_i32, { "r", "r", "rwL" } },
+{ INDEX_op_andc_i64, { "r", "r", "rL" } },
+{ INDEX_op_orc_i32, { "r", "r", "rwL" } },
+{ INDEX_op_orc_i64, { "r", "r", "rL" } },
+{ INDEX_op_eqv_i32, { "r", "r", "rwL" } },
+{ INDEX_op_eqv_i64, { "r", "r", "rL" } },
+
+{ INDEX_op_not_i32, { "r", "r" } },
+{ INDEX_op_not_i64, { "r", "r" } },
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index d3a1bc2..efc506b 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -47,12 +47,12 @@ typedef enum {
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
-#define TCG_TARGET_HAS_not_i32 0
+#define TCG_TARGET_HAS_not_i32 1
#define TCG_TARGET_HAS_neg_i32 0
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_orc_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
+#define TCG_TARGET_HAS_orc_i32 1
+#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
@@ -75,12 +75,12 @@ typedef enum {
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
-#define TCG_TARGET_HAS_not_i64 0
+#define TCG_TARGET_HAS_not_i64 1
#define TCG_TARGET_HAS_neg_i64 0
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_
[Qemu-devel] [PATCH v4 24/33] tcg-aarch64: Special case small constants in tcg_out_movi
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9effee7..e50abcb 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -573,6 +573,17 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
type = TCG_TYPE_I32;
}
+/* Speed things up by handling the common case of small positive
+ and negative values specially. */
+if ((value & ~0xull) == 0) {
+tcg_fmt_Rd_uimm(s, INSN_MOVZ, type, rd, value, 0);
+return;
+}
+if ((~svalue & ~0xull) == 0) {
+tcg_fmt_Rd_uimm(s, INSN_MOVN, type, rd, ~svalue, 0);
+return;
+}
+
/* Check for bitfield immediates. For the benefit of 32-bit quantities,
use the sign-extended value. That lets us match rotated values such
as 0xffff with the same 64-bit logic matching 0xffff.
--
1.8.3.1
[Qemu-devel] [PATCH v4 22/33] tcg-aarch64: Use MOVN in tcg_out_movi
When profitable, initialize the register with MOVN instead of MOVZ,
before setting the remaining lanes with MOVK.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 88 +---
1 file changed, 75 insertions(+), 13 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index f9319ed..cecda05 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -559,24 +559,86 @@ static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg rd,
tcg_target_long value)
{
AArch64Insn insn;
-
-if (type == TCG_TYPE_I32) {
+int i, wantinv, shift;
+tcg_target_long svalue = value;
+tcg_target_long ivalue, imask;
+
+/* For 32-bit values, discard potential garbage in value. For 64-bit
+ values within [2**31, 2**32-1], we can create smaller sequences by
+ interpreting this as a negative 32-bit number, while ensuring that
+ the high 32 bits are cleared by setting SF=0. */
+if (type == TCG_TYPE_I32 || (value & ~0xull) == 0) {
+svalue = (int32_t)value;
value = (uint32_t)value;
+type = TCG_TYPE_I32;
+}
+
+/* Would it take fewer insns to begin with MOVN? For the value and its
+ inverse, count the number of 16-bit lanes that are 0. For the benefit
+ of 32-bit quantities, compare the zero-extended normal value vs the
+ sign-extended inverted value. For example,
+v = 0xf100, zeros = 2
+ ~v = 0x0eff, zeros = 1
+ ~sv = 0x0eff, zeros = 3
+ By using ~sv we see that 3 > 2, leading us to emit just a single insn
+ "movn ret, 0x0eff, lsl #16". */
+
+ivalue = ~svalue;
+imask = 0;
+wantinv = 0;
+
+/* ??? This can be done in the simd unit without a loop:
+// Move value and ivalue into V0 and V1 respectively.
+mov v0.d[0], value
+mov v1.d[0], ivalue
+// Compare each 16-bit lane vs 0, producing -1 for true.
+cmeqv0.4h, v0.4h, #0
+cmeqv1.4h, v1.4h, #0
+mov imask, v1.d[0]
+// Sum the comparisons, producing 0 to -4.
+addvh0, v0.4h
+addvh1, v1.4h
+// Subtract the two, forming a positive wantinv result.
+sub v0.4h, v0.4h, v1.4h
+smovwantinv, v0.h[0]
+ */
+for (i = 0; i < 64; i += 16) {
+tcg_target_long mask = 0xull << i;
+if ((value & mask) == 0) {
+wantinv -= 1;
+}
+if ((ivalue & mask) == 0) {
+wantinv += 1;
+imask |= mask;
+}
}
-/* count trailing zeros in 16 bit steps, mapping 64 to 0. Emit the
- first MOVZ with the half-word immediate skipping the zeros, with a shift
- (LSL) equal to this number. Then all next instructions use MOVKs.
- Zero the processed half-word in the value, continue until empty.
- We build the final result 16bits at a time with up to 4 instructions,
- but do not emit instructions for 16bit zero holes. */
+/* If we had more 0x than 0x, invert VALUE and use MOVN. */
insn = INSN_MOVZ;
-do {
-unsigned shift = ctz64(value) & (63 & -16);
-tcg_fmt_Rd_uimm(s, insn, shift >= 32, rd, value >> shift, shift);
+if (wantinv > 0) {
+value = ivalue;
+insn = INSN_MOVN;
+}
+
+/* Find the lowest lane that is not 0x. */
+shift = ctz64(value) & (63 & -16);
+tcg_fmt_Rd_uimm(s, insn, type, rd, value >> shift, shift);
+
+if (wantinv > 0) {
+/* Re-invert the value, so MOVK sees non-inverted bits. */
+value = ~value;
+/* Clear out all the 0x lanes. */
+value ^= imask;
+}
+/* Clear out the lane that we just set. */
+value &= ~(0xUL << shift);
+
+/* Iterate until all lanes have been set, and thus cleared from VALUE. */
+while (value) {
+shift = ctz64(value) & (63 & -16);
+tcg_fmt_Rd_uimm(s, INSN_MOVK, type, rd, value >> shift, shift);
value &= ~(0xUL << shift);
-insn = INSN_MOVK;
-} while (value);
+}
}
static inline void tcg_out_ldst_r(TCGContext *s,
--
1.8.3.1
[Qemu-devel] [PATCH v4 12/33] tcg-aarch64: Handle constant operands to and, or, xor
Handle a simplified set of logical immediates for the moment.
The way gcc and binutils do it, with 52k worth of tables, and
a binary search depth of log2(5334) = 13, seems slow for the
most common cases.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 155 ---
1 file changed, 106 insertions(+), 49 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 59499fd..bc651ac 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -113,6 +113,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_IS32 0x100
#define TCG_CT_CONST_AIMM 0x200
+#define TCG_CT_CONST_LIMM 0x400
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -143,6 +144,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'A': /* Valid for arithmetic immediate (positive or negative). */
ct->ct |= TCG_CT_CONST_AIMM;
break;
+case 'L': /* Valid for logical immediate. */
+ct->ct |= TCG_CT_CONST_LIMM;
+break;
default:
return -1;
}
@@ -157,6 +161,26 @@ static inline bool is_aimm(uint64_t val)
return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
}
+static inline bool is_limm(uint64_t val)
+{
+/* Taking a simplified view of the logical immediates for now, ignoring
+ the replication that can happen across the field. Match bit patterns
+ of the forms
+ 0011
+ 0..01..10..0
+ and their inverses. */
+
+/* Make things easier below, by testing the form with msb clear. */
+if ((int64_t)val < 0) {
+val = ~val;
+}
+if (val == 0) {
+return false;
+}
+val += val & -val;
+return (val & (val - 1)) == 0;
+}
+
static int tcg_target_const_match(tcg_target_long val,
const TCGArgConstraint *arg_ct)
{
@@ -171,6 +195,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
return 1;
}
+if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
+return 1;
+}
return 0;
}
@@ -225,6 +252,11 @@ enum aarch64_ldst_op_type { /* type of operation */
};
typedef enum {
+/* Logical immediate instructions */
+INSN_ANDI = 0x1200,
+INSN_ORRI = 0x3200,
+INSN_EORI = 0x5200,
+
/* Logical shifted register instructions */
INSN_AND= 0x0a00,
INSN_ORR= 0x2a00,
@@ -368,6 +400,48 @@ static inline void tcg_fmt_Rdn_aimm(TCGContext *s,
AArch64Insn insn,
tcg_out32(s, insn | sf << 31 | aimm << 10 | rn << 5 | rd);
}
+/* This function can be used for both Logical (immediate) and Bitfield
+ instruction groups, both of which have N, IMMR and IMMS fields, that
+ feed the DecodeBitMasks pseudo function in the reference manual. */
+static inline void tcg_fmt_Rdn_nrs(TCGContext *s, AArch64Insn insn,
+ TCGType sf, TCGReg rd, TCGReg rn,
+ int n, int immr, int imms)
+{
+tcg_out32(s, insn | sf << 31 | n << 22 | immr << 16 | imms << 10
+ | rn << 5 | rd);
+}
+
+/* This function is used for the Logical (immediate) instruction group.
+ The value of LIMM must satisfy IS_LIMM. See the comment above about
+ only supporting simplified logical immediates. */
+static void tcg_fmt_Rdn_limm(TCGContext *s, AArch64Insn insn, TCGType sf,
+ TCGReg rd, TCGReg rn, uint64_t limm)
+{
+unsigned h, l, r, c;
+
+assert(is_limm(limm));
+
+h = clz64(limm);
+l = ctz64(limm);
+if (l == 0) {
+r = 0; /* form 0011 */
+c = ctz64(~limm) - 1;
+if (h == 0) {
+r = clz64(~limm); /* form 1..10..01..1 */
+c += r;
+}
+} else {
+r = 64 - l; /* form 1100 or 0..01..10..0 */
+c = r - h - 1;
+}
+if (!sf) {
+r &= 31;
+c &= 31;
+}
+
+tcg_fmt_Rdn_nrs(s, insn, sf, rd, rn, sf, r, c);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -676,40 +750,6 @@ static inline void tcg_out_call(TCGContext *s,
tcg_target_long target)
}
}
-/* encode a logical immediate, mapping user parameter
- M=set bits pattern length to S=M-1 */
-static inline unsigned int
-aarch64_limm(unsigned int m, unsigned int r)
-{
-assert(m > 0);
-return r << 16 | (m - 1) << 10;
-}
-
-/* test a register against an immediate bit pattern made of
- M set bits rotated right by R.
- Examples:
- to test a 32/64 reg against 0x0007, pass M = 3, R = 0.
- to test a 32/64 reg against 0x00ff, pass M = 8, R = 0.
- to test a 32bit reg against 0xff00, pass M
[Qemu-devel] [PATCH v4 20/33] tcg-aarch64: Support div, rem
For remainder, generic code will produce mul+sub,
whereas we can implement with msub.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 51 +++-
tcg/aarch64/tcg-target.h | 8
2 files changed, 46 insertions(+), 13 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b7f7fa5..c44f404 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -302,6 +302,12 @@ typedef enum {
INSN_RORV = 0x1ac02c00,
INSN_SMULH = 0x9b407c00,
INSN_UMULH = 0x9bc07c00,
+INSN_UDIV = 0x1ac00800,
+INSN_SDIV = 0x1ac00c00,
+
+/* Data-processing (3 source) instructions */
+INSN_MADD = 0x1b00,
+INSN_MSUB = 0x1b008000,
/* Bitfield instructions */
INSN_BFM = 0x3300,
@@ -416,6 +422,13 @@ static inline void tcg_fmt_Rdnm(TCGContext *s, AArch64Insn
insn, TCGType sf,
tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd);
}
+/* This function is used for the Multiply instruction group. */
+static inline void tcg_fmt_Rdnma(TCGContext *s, AArch64Insn insn, TCGType sf,
+ TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
+{
+tcg_out32(s, insn | sf << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
+}
+
/* This function is used for the Arithmetic (immediate) instruction group.
The value of AIMM must be appropriate for encoding in the shift+imm12
fields. */
@@ -621,14 +634,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
arg, arg1, arg2);
}
-static inline void tcg_out_mul(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm)
-{
-/* Using MADD 0x1b00 with Ra = wzr alias MUL 0x1b007c00 */
-unsigned int base = ext ? 0x9b007c00 : 0x1b007c00;
-tcg_out32(s, base | rm << 16 | rn << 5 | rd);
-}
-
static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
@@ -1425,7 +1430,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
-tcg_out_mul(s, ext, a0, a1, a2);
+tcg_fmt_Rdnma(s, INSN_MADD, ext, a0, a1, a2, TCG_REG_XZR);
+break;
+
+case INDEX_op_div_i64:
+case INDEX_op_div_i32:
+tcg_fmt_Rdnm(s, INSN_SDIV, ext, a0, a1, a2);
+break;
+case INDEX_op_divu_i64:
+case INDEX_op_divu_i32:
+tcg_fmt_Rdnm(s, INSN_UDIV, ext, a0, a1, a2);
+break;
+
+case INDEX_op_rem_i64:
+case INDEX_op_rem_i32:
+tcg_fmt_Rdnm(s, INSN_SDIV, ext, TCG_REG_TMP, a1, a2);
+tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1);
+break;
+case INDEX_op_remu_i64:
+case INDEX_op_remu_i32:
+tcg_fmt_Rdnm(s, INSN_UDIV, ext, TCG_REG_TMP, a1, a2);
+tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1);
break;
case INDEX_op_shl_i64:
@@ -1658,6 +1683,14 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub_i64, { "r", "rZ", "rA" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
+{ INDEX_op_div_i32, { "r", "r", "r" } },
+{ INDEX_op_div_i64, { "r", "r", "r" } },
+{ INDEX_op_divu_i32, { "r", "r", "r" } },
+{ INDEX_op_divu_i64, { "r", "r", "r" } },
+{ INDEX_op_rem_i32, { "r", "r", "r" } },
+{ INDEX_op_rem_i64, { "r", "r", "r" } },
+{ INDEX_op_remu_i32, { "r", "r", "r" } },
+{ INDEX_op_remu_i64, { "r", "r", "r" } },
{ INDEX_op_and_i32, { "r", "r", "rwL" } },
{ INDEX_op_and_i64, { "r", "r", "rL" } },
{ INDEX_op_or_i32, { "r", "r", "rwL" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 52c6c23..8b55ff9 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -39,8 +39,8 @@ typedef enum {
#define TCG_TARGET_CALL_STACK_OFFSET0
/* optional instructions */
-#define TCG_TARGET_HAS_div_i32 0
-#define TCG_TARGET_HAS_rem_i32 0
+#define TCG_TARGET_HAS_div_i32 1
+#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_ext8s_i321
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i321
@@ -64,8 +64,8 @@ typedef enum {
#define TCG_TARGET_HAS_muluh_i320
#define TCG_TARGET_HAS_mulsh_i320
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_ext8s_i641
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
--
1.8.3.1
[Qemu-devel] [PATCH v4 06/33] tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn
And since we're no longer talking about opcodes, merge the 0x1ac02000
data2 primary opcode with the shift subcode to create the full insn.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 49
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 99d9884..be6d05a 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -216,14 +216,13 @@ typedef enum {
INSN_ADDS = 0x2b00,
INSN_SUB= 0x4b00,
INSN_SUBS = 0x6b00,
-} AArch64Insn;
-enum aarch64_srr_opc {
-SRR_SHL = 0x0,
-SRR_SHR = 0x4,
-SRR_SAR = 0x8,
-SRR_ROR = 0xc
-};
+/* Data-processing (2 source) instructions */
+INSN_LSLV = 0x1ac02000,
+INSN_LSRV = 0x1ac02400,
+INSN_ASRV = 0x1ac02800,
+INSN_RORV = 0x1ac02c00,
+} AArch64Insn;
static inline enum aarch64_ldst_op_data
aarch64_ldst_get_data(TCGOpcode tcg_op)
@@ -472,12 +471,12 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext,
}
static inline void tcg_out_shiftrot_reg(TCGContext *s,
-enum aarch64_srr_opc opc, TCGType ext,
+AArch64Insn insn, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm)
{
/* using 2-source data processing instructions 0x1ac02000 */
-unsigned int base = ext ? 0x9ac02000 : 0x1ac02000;
-tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd);
+unsigned int base = insn | (ext ? 0x8000 : 0);
+tcg_out32(s, base | rm << 16 | rn << 5 | rd);
}
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
@@ -1214,47 +1213,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_shl_i64:
case INDEX_op_shl_i32:
-if (c2) {/* LSL / UBFM Wd, Wn, (32 - m) */
+if (c2) {
tcg_out_shl(s, ext, a0, a1, a2);
-} else {/* LSL / LSLV */
-tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2);
+} else {
+tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
case INDEX_op_shr_i32:
-if (c2) {/* LSR / UBFM Wd, Wn, m, 31 */
+if (c2) {
tcg_out_shr(s, ext, a0, a1, a2);
-} else {/* LSR / LSRV */
-tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2);
+} else {
+tcg_out_shiftrot_reg(s, INSN_LSRV, ext, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
case INDEX_op_sar_i32:
-if (c2) {/* ASR / SBFM Wd, Wn, m, 31 */
+if (c2) {
tcg_out_sar(s, ext, a0, a1, a2);
-} else {/* ASR / ASRV */
-tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2);
+} else {
+tcg_out_shiftrot_reg(s, INSN_ASRV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotr_i64:
case INDEX_op_rotr_i32:
-if (c2) {/* ROR / EXTR Wd, Wm, Wm, m */
+if (c2) {
tcg_out_rotr(s, ext, a0, a1, a2);
-} else {/* ROR / RORV */
-tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2);
+} else {
+tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotl_i64:
-case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */
-if (c2) {/* ROR / EXTR Wd, Wm, Wm, 32 - m */
+case INDEX_op_rotl_i32:
+if (c2) {
tcg_out_rotl(s, ext, a0, a1, a2);
} else {
tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0);
-tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP);
+tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, TCG_REG_TMP);
}
break;
--
1.8.3.1
[Qemu-devel] [PATCH v4 11/33] tcg-aarch64: Handle constant operands to add, sub, and compare
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 103 ---
1 file changed, 80 insertions(+), 23 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 93badfd..59499fd 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -111,6 +111,9 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
}
}
+#define TCG_CT_CONST_IS32 0x100
+#define TCG_CT_CONST_AIMM 0x200
+
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
const char **pct_str)
@@ -134,6 +137,12 @@ static int target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
#endif
break;
+case 'w': /* The operand should be considered 32-bit. */
+ct->ct |= TCG_CT_CONST_IS32;
+break;
+case 'A': /* Valid for arithmetic immediate (positive or negative). */
+ct->ct |= TCG_CT_CONST_AIMM;
+break;
default:
return -1;
}
@@ -143,14 +152,25 @@ static int target_parse_constraint(TCGArgConstraint *ct,
return 0;
}
-static inline int tcg_target_const_match(tcg_target_long val,
- const TCGArgConstraint *arg_ct)
+static inline bool is_aimm(uint64_t val)
+{
+return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
+}
+
+static int tcg_target_const_match(tcg_target_long val,
+ const TCGArgConstraint *arg_ct)
{
int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
+if (ct & TCG_CT_CONST_IS32) {
+val = (int32_t)val;
+}
+if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
+return 1;
+}
return 0;
}
@@ -558,11 +578,21 @@ static inline void tcg_out_rotl(TCGContext *s, TCGType
ext,
tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
}
-static inline void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg rn,
- TCGReg rm)
+static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
+tcg_target_long b, bool const_b)
{
-/* Using CMP alias SUBS wzr, Wn, Wm */
-tcg_fmt_Rdnm(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm);
+if (const_b) {
+/* Using CMP or CMN aliases. */
+AArch64Insn insn = INSN_SUBSI;
+if (b < 0) {
+insn = INSN_ADDSI;
+b = -b;
+}
+tcg_fmt_Rdn_aimm(s, insn, ext, TCG_REG_XZR, a, b);
+} else {
+/* Using CMP alias SUBS wzr, Wn, Wm */
+tcg_fmt_Rdnm(s, INSN_SUBS, ext, TCG_REG_XZR, a, b);
+}
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -760,6 +790,17 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits,
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
+static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
+TCGReg rn, int aimm)
+{
+AArch64Insn insn = INSN_ADDI;
+if (aimm < 0) {
+insn = INSN_SUBI;
+aimm = -aimm;
+}
+tcg_fmt_Rdn_aimm(s, insn, ext, rd, rn, aimm);
+}
+
static inline void tcg_out_nop(TCGContext *s)
{
tcg_out32(s, 0xd503201f);
@@ -896,7 +937,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
(is_read ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write)));
/* Perform the address comparison. */
-tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3);
+tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
*label_ptr = s->code_ptr;
/* If not equal, we jump to the slow path. */
tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
@@ -1157,14 +1198,26 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
a0, a1, a2);
break;
-case INDEX_op_add_i64:
case INDEX_op_add_i32:
-tcg_fmt_Rdnm(s, INSN_ADD, ext, a0, a1, a2);
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_add_i64:
+if (c2) {
+tcg_out_addsubi(s, ext, a0, a1, a2);
+} else {
+tcg_fmt_Rdnm(s, INSN_ADD, ext, a0, a1, a2);
+}
break;
-case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
-tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, a1, a2);
+a2 = (int32_t)a2;
+/* FALLTHRU */
+case INDEX_op_sub_i64:
+if (c2) {
+tcg_out_addsubi(s, ext, a0, a1, -a2);
+} else {
+tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, a1, a2);
+}
break;
case INDEX_op_and_i64:
@@ -1233,15 +1286,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
-case INDEX_op_brcond_i64:
case INDEX_op_brcond_i32:
-tcg_out_cmp(s, ext, a0, a1);
+a1 = (int32_t)a1;
+/* FALLTHRU */
+case INDEX_op_brcond_i64:
+tcg_out_cmp(s, ext, a0, a1, const_args[1]);
[Qemu-devel] [PATCH v4 21/33] tcg-aarch64: Introduce tcg_fmt_Rd_uimm
Cleaning up the implementation of tcg_out_movi at the same time.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 49 +++-
1 file changed, 28 insertions(+), 21 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index c44f404..f9319ed 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -279,6 +279,11 @@ typedef enum {
INSN_EOR = 0x4a00,
INSN_EON = 0x4a20,
+/* Move wide immediate instructions */
+INSN_MOVN = 0x1280,
+INSN_MOVZ = 0x5280,
+INSN_MOVK = 0x7280,
+
/* Add/subtract immediate instructions */
INSN_ADDI = 0x1100,
INSN_ADDSI = 0x3100,
@@ -495,6 +500,16 @@ static inline void tcg_fmt_Rdnm_cond(TCGContext *s,
AArch64Insn insn,
| tcg_cond_to_aarch64[c] << 12);
}
+/* This function is used for the Move (wide immediate) instruction group.
+ Note that SHIFT is a full shift count, not the 2 bit HW field. */
+static inline void tcg_fmt_Rd_uimm(TCGContext *s, AArch64Insn insn,
+ TCGType sf, TCGReg rd, uint16_t half,
+ unsigned shift)
+{
+assert((shift & ~0x30) == 0);
+tcg_out32(s, insn | sf << 31 | shift << (21 - 4) | half << 5 | rd);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -540,38 +555,30 @@ static inline void tcg_out_movr_sp(TCGContext *s, TCGType
ext,
tcg_fmt_Rdn_aimm(s, INSN_ADDI, ext, rd, rn, 0);
}
-static inline void tcg_out_movi_aux(TCGContext *s,
-TCGReg rd, uint64_t value)
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long value)
{
-uint32_t half, base, shift, movk = 0;
-/* construct halfwords of the immediate with MOVZ/MOVK with LSL */
-/* using MOVZ 0x5280 | extended reg.. */
-base = (value > 0x) ? 0xd280 : 0x5280;
+AArch64Insn insn;
+
+if (type == TCG_TYPE_I32) {
+value = (uint32_t)value;
+}
+
/* count trailing zeros in 16 bit steps, mapping 64 to 0. Emit the
first MOVZ with the half-word immediate skipping the zeros, with a shift
- (LSL) equal to this number. Then morph all next instructions into MOVKs.
+ (LSL) equal to this number. Then all next instructions use MOVKs.
Zero the processed half-word in the value, continue until empty.
We build the final result 16bits at a time with up to 4 instructions,
but do not emit instructions for 16bit zero holes. */
+insn = INSN_MOVZ;
do {
-shift = ctz64(value) & (63 & -16);
-half = (value >> shift) & 0x;
-tcg_out32(s, base | movk | shift << 17 | half << 5 | rd);
-movk = 0x2000; /* morph next MOVZs into MOVKs */
+unsigned shift = ctz64(value) & (63 & -16);
+tcg_fmt_Rd_uimm(s, insn, shift >= 32, rd, value >> shift, shift);
value &= ~(0xUL << shift);
+insn = INSN_MOVK;
} while (value);
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
-TCGReg rd, tcg_target_long value)
-{
-if (type == TCG_TYPE_I64) {
-tcg_out_movi_aux(s, rd, value);
-} else {
-tcg_out_movi_aux(s, rd, value & 0x);
-}
-}
-
static inline void tcg_out_ldst_r(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
--
1.8.3.1
[Qemu-devel] [PATCH v4 14/33] tcg-aarch64: Handle zero as first argument to sub
In order to properly handle neg, as generated by TCG generic code.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 28
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 5b4..08a0cc4 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -114,6 +114,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_IS32 0x100
#define TCG_CT_CONST_AIMM 0x200
#define TCG_CT_CONST_LIMM 0x400
+#define TCG_CT_CONST_ZERO 0x800
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -147,6 +148,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* Valid for logical immediate. */
ct->ct |= TCG_CT_CONST_LIMM;
break;
+case 'Z': /* zero */
+ct->ct |= TCG_CT_CONST_ZERO;
+break;
default:
return -1;
}
@@ -198,6 +202,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
return 1;
}
+if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+return 1;
+}
return 0;
}
@@ -1186,6 +1193,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGArg a2 = args[2];
int c2 = const_args[2];
+/* Some operands are defined with "rZ" constraint, a register or
+ the zero register. These need not actually test args[I] == 0. */
+#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
+
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
@@ -1255,9 +1266,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* FALLTHRU */
case INDEX_op_sub_i64:
if (c2) {
-tcg_out_addsubi(s, ext, a0, a1, -a2);
+/* Arithmetic immediate instructions use Xn|sp, and thus
+ we cannot encode the zero register if tcg optimization
+ is turned off and both A1 and A2 are constants. */
+if (const_args[1]) {
+tcg_out_movi(s, ext ? TCG_TYPE_I64 : TCG_TYPE_I32, a0, -a2);
+} else {
+tcg_out_addsubi(s, ext, a0, a1, -a2);
+}
} else {
-tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, a1, a2);
+tcg_fmt_Rdnm(s, INSN_SUB, ext, a0, REG0(1), a2);
}
break;
@@ -1481,6 +1499,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* Opcode not implemented. */
tcg_abort();
}
+
+#undef REG0
}
static const TCGTargetOpDef aarch64_op_defs[] = {
@@ -1518,8 +1538,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_add_i32, { "r", "r", "rwA" } },
{ INDEX_op_add_i64, { "r", "r", "rA" } },
-{ INDEX_op_sub_i32, { "r", "r", "rwA" } },
-{ INDEX_op_sub_i64, { "r", "r", "rA" } },
+{ INDEX_op_sub_i32, { "r", "rZ", "rwA" } },
+{ INDEX_op_sub_i64, { "r", "rZ", "rA" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
{ INDEX_op_and_i32, { "r", "r", "rwL" } },
--
1.8.3.1
[Qemu-devel] [PATCH v4 09/33] tcg-aarch64: Introduce tcg_fmt_Rdn_aimm
This merges the implementation of tcg_out_addi and tcg_out_subi.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 79 +++-
1 file changed, 31 insertions(+), 48 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 0e7b67b..56625a9 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -211,6 +211,12 @@ typedef enum {
INSN_EOR= 0x4a00,
INSN_ANDS = 0x6a00,
+/* Add/subtract immediate instructions */
+INSN_ADDI = 0x1100,
+INSN_ADDSI = 0x3100,
+INSN_SUBI = 0x5100,
+INSN_SUBSI = 0x7100,
+
/* Add/subtract shifted register instructions */
INSN_ADD= 0x0b00,
INSN_ADDS = 0x2b00,
@@ -326,6 +332,22 @@ static inline void tcg_fmt_Rdnm(TCGContext *s, AArch64Insn
insn, TCGType sf,
tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd);
}
+/* This function is used for the Arithmetic (immediate) instruction group.
+ The value of AIMM must be appropriate for encoding in the shift+imm12
+ fields. */
+static inline void tcg_fmt_Rdn_aimm(TCGContext *s, AArch64Insn insn,
+TCGType sf, TCGReg rd, TCGReg rn,
+unsigned int aimm)
+{
+if (aimm > 0xfff) {
+assert((aimm & 0xfff) == 0);
+aimm >>= 12;
+assert(aimm <= 0xfff);
+aimm |= 1 << 12; /* apply LSL 12 */
+}
+tcg_out32(s, insn | sf << 31 | aimm << 10 | rn << 5 | rd);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -742,46 +764,6 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits,
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
-static inline void tcg_out_addi(TCGContext *s, TCGType ext,
-TCGReg rd, TCGReg rn, unsigned int aimm)
-{
-/* add immediate aimm unsigned 12bit value (with LSL 0 or 12) */
-/* using ADD 0x1100 | (ext) | (aimm << 10) | (rn << 5) | rd */
-unsigned int base = ext ? 0x9100 : 0x1100;
-
-if (aimm <= 0xfff) {
-aimm <<= 10;
-} else {
-/* we can only shift left by 12, on assert we cannot represent */
-assert(!(aimm & 0xfff));
-assert(aimm <= 0xfff000);
-base |= 1 << 22; /* apply LSL 12 */
-aimm >>= 2;
-}
-
-tcg_out32(s, base | aimm | (rn << 5) | rd);
-}
-
-static inline void tcg_out_subi(TCGContext *s, TCGType ext,
-TCGReg rd, TCGReg rn, unsigned int aimm)
-{
-/* sub immediate aimm unsigned 12bit value (with LSL 0 or 12) */
-/* using SUB 0x5100 | (ext) | (aimm << 10) | (rn << 5) | rd */
-unsigned int base = ext ? 0xd100 : 0x5100;
-
-if (aimm <= 0xfff) {
-aimm <<= 10;
-} else {
-/* we can only shift left by 12, on assert we cannot represent */
-assert(!(aimm & 0xfff));
-assert(aimm <= 0xfff000);
-base |= 1 << 22; /* apply LSL 12 */
-aimm >>= 2;
-}
-
-tcg_out32(s, base | aimm | (rn << 5) | rd);
-}
-
static inline void tcg_out_nop(TCGContext *s)
{
tcg_out32(s, 0xd503201f);
@@ -899,9 +881,9 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
(TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits,
(TARGET_LONG_BITS - TARGET_PAGE_BITS));
/* Add any "high bits" from the tlb offset to the env address into X2,
- to take advantage of the LSL12 form of the addi instruction.
+ to take advantage of the LSL12 form of the ADDI instruction.
X2 = env + (tlb_offset & 0xfff000) */
-tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
+tcg_fmt_Rdn_aimm(s, INSN_ADDI, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
/* Merge the tlb index contribution into X2.
X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
tcg_fmt_Rdnm_lsl(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2,
@@ -1510,9 +1492,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx);
}
-/* make stack space for TCG locals */
-tcg_out_subi(s, 1, TCG_REG_SP, TCG_REG_SP,
- frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
+/* Make stack space for TCG locals. */
+tcg_fmt_Rdn_aimm(s, INSN_SUBI, 1, TCG_REG_SP, TCG_REG_SP,
+ frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
+
/* inform TCG about how to find TCG locals with register, offset, size */
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
CPU_TEMP_BUF_NLONGS * sizeof(long));
@@ -1529,9 +1512,9 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tb_ret_addr = s->code_ptr;
-/* remove TCG locals stack space */
-tcg_out_addi(s, 1, TCG_REG_SP, TCG_REG_SP,
- frame_size_tcg_locals * TCG_TARGET_STACK
[Qemu-devel] [PATCH v4 03/33] tcg-aarch64: Don't handle mov/movi in tcg_out_op
Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 20 +++- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 983a74a..8f19b50 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -1172,18 +1172,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[0], args[1], args[2]); break; -case INDEX_op_mov_i64: -case INDEX_op_mov_i32: -tcg_out_movr(s, ext, args[0], args[1]); -break; - -case INDEX_op_movi_i64: -tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]); -break; -case INDEX_op_movi_i32: -tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); -break; - case INDEX_op_add_i64: case INDEX_op_add_i32: tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0); @@ -1347,8 +1335,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_movr(s, 0, args[0], args[1]); break; +case INDEX_op_mov_i64: +case INDEX_op_mov_i32: +case INDEX_op_movi_i64: +case INDEX_op_movi_i32: +/* Always implemented with tcg_out_mov/i, never with tcg_out_op. */ default: -tcg_abort(); /* opcode not implemented */ +/* Opcode not implemented. */ +tcg_abort(); } } -- 1.8.3.1
[Qemu-devel] [PATCH v4 00/33] tcg-aarch64 improvements
Changes since v3:
* Using TCGType instead of bool for the ext variables.
* Marginal tidying of the tcg_fmt_* functions to match fields names with the
architecture document now that it's released. In particular, the ext
variables incoming to them have been renamed "sf". I have not propagated
that change all the way back up the call chain.
* Split up the movi improvements into 3 separate patches. I also fixed the
bug therein that affected i386-softmmu booting. I've also significantly
improved the documentation in that function.
* I came up with a significantly faster way to actually perform the MOVN
check, although I didn't confuse the issue by actually implementing it,
since it requires using the neon unit, and probably real hardware to see
what kind of inter-unit slow down there is. It's left as a comment.
I actually suspect that the parallelism of the A57 is high enough to
support performing 3 tests at once, deciding which of the 3 alternatives
at once at the end.
* Split up the movcond addition and setcond cleanup. I did not find a
problem in either patch, as suggested during the previous review.
* Rebase vs head, 2d1fe18.
Tested bios boots of i386-softmmu, alpha-softmmu, sparc-softmmu.
Tested a full run of Paulo's sieve{32,64}.flat. Takes around an
hour to run under the Foundation model. Ouch.
r~
Richard Henderson (33):
tcg-aarch64: Change all ext variables to TCGType
tcg-aarch64: Set ext based on TCG_OPF_64BIT
tcg-aarch64: Don't handle mov/movi in tcg_out_op
tcg-aarch64: Hoist common argument loads in tcg_out_op
tcg-aarch64: Change enum aarch64_arith_opc to AArch64Insn
tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn
tcg-aarch64: Remove the shift_imm parameter from tcg_out_cmp
tcg-aarch64: Introduce tcg_fmt_Rdnm and tcg_fmt_Rdnm_lsl
tcg-aarch64: Introduce tcg_fmt_Rdn_aimm
tcg-aarch64: Implement mov with tcg_fmt_* functions
tcg-aarch64: Handle constant operands to add, sub, and compare
tcg-aarch64: Handle constant operands to and, or, xor
tcg-aarch64: Support andc, orc, eqv, not
tcg-aarch64: Handle zero as first argument to sub
tcg-aarch64: Support movcond
tcg-aarch64: Use tcg_fmt_Rdnm_cond for setcond
tcg-aarch64: Support deposit
tcg-aarch64: Support add2, sub2
tcg-aarch64: Support muluh, mulsh
tcg-aarch64: Support div, rem
tcg-aarch64: Introduce tcg_fmt_Rd_uimm
tcg-aarch64: Use MOVN in tcg_out_movi
tcg-aarch64: Use ORRI in tcg_out_movi
tcg-aarch64: Special case small constants in tcg_out_movi
tcg-aarch64: Use adrp in tcg_out_movi
tcg-aarch64: Avoid add with zero in tlb load
tcg-aarch64: Pass return address to load/store helpers directly.
tcg-aarch64: Use tcg_out_call for qemu_ld/st
tcg-aarch64: Use symbolic names for branches
tcg-aarch64: Implement tcg_register_jit
tcg-aarch64: Reuse FP and LR in translated code
tcg-aarch64: Introduce tcg_out_ldst_pair
tcg-aarch64: Remove redundant CPU_TLB_ENTRY_BITS check
include/exec/exec-all.h | 11 -
tcg/aarch64/tcg-target.c | 1352 ++
tcg/aarch64/tcg-target.h | 76 +--
3 files changed, 940 insertions(+), 499 deletions(-)
--
1.8.3.1
[Qemu-devel] [PATCH v4 04/33] tcg-aarch64: Hoist common argument loads in tcg_out_op
This reduces the code size of the function significantly.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 95 +---
1 file changed, 50 insertions(+), 45 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 8f19b50..8f5814d 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1113,15 +1113,22 @@ static inline void tcg_out_load_pair(TCGContext *s,
TCGReg addr,
}
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
- const TCGArg *args, const int *const_args)
+ const TCGArg args[TCG_MAX_OP_ARGS],
+ const int const_args[TCG_MAX_OP_ARGS])
{
/* 99% of the time, we can signal the use of extension registers
by looking to see if the opcode handles 64-bit data. */
TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
+/* Hoist the loads of the most common arguments. */
+TCGArg a0 = args[0];
+TCGArg a1 = args[1];
+TCGArg a2 = args[2];
+int c2 = const_args[2];
+
switch (opc) {
case INDEX_op_exit_tb:
-tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, args[0]);
+tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
tcg_out_goto(s, (tcg_target_long)tb_ret_addr);
break;
@@ -1130,23 +1137,23 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
#error "USE_DIRECT_JUMP required for aarch64"
#endif
assert(s->tb_jmp_offset != NULL); /* consistency for USE_DIRECT_JUMP */
-s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
+s->tb_jmp_offset[a0] = s->code_ptr - s->code_buf;
/* actual branch destination will be patched by
aarch64_tb_set_jmp_target later, beware retranslation. */
tcg_out_goto_noaddr(s);
-s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
+s->tb_next_offset[a0] = s->code_ptr - s->code_buf;
break;
case INDEX_op_call:
if (const_args[0]) {
-tcg_out_call(s, args[0]);
+tcg_out_call(s, a0);
} else {
-tcg_out_callr(s, args[0]);
+tcg_out_callr(s, a0);
}
break;
case INDEX_op_br:
-tcg_out_goto_label(s, args[0]);
+tcg_out_goto_label(s, a0);
break;
case INDEX_op_ld_i32:
@@ -1169,97 +1176,95 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st16_i64:
case INDEX_op_st32_i64:
tcg_out_ldst(s, aarch64_ldst_get_data(opc), aarch64_ldst_get_type(opc),
- args[0], args[1], args[2]);
+ a0, a1, a2);
break;
case INDEX_op_add_i64:
case INDEX_op_add_i32:
-tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0);
+tcg_out_arith(s, ARITH_ADD, ext, a0, a1, a2, 0);
break;
case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
-tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2], 0);
+tcg_out_arith(s, ARITH_SUB, ext, a0, a1, a2, 0);
break;
case INDEX_op_and_i64:
case INDEX_op_and_i32:
-tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2], 0);
+tcg_out_arith(s, ARITH_AND, ext, a0, a1, a2, 0);
break;
case INDEX_op_or_i64:
case INDEX_op_or_i32:
-tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2], 0);
+tcg_out_arith(s, ARITH_OR, ext, a0, a1, a2, 0);
break;
case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
-tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2], 0);
+tcg_out_arith(s, ARITH_XOR, ext, a0, a1, a2, 0);
break;
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
-tcg_out_mul(s, ext, args[0], args[1], args[2]);
+tcg_out_mul(s, ext, a0, a1, a2);
break;
case INDEX_op_shl_i64:
case INDEX_op_shl_i32:
-if (const_args[2]) {/* LSL / UBFM Wd, Wn, (32 - m) */
-tcg_out_shl(s, ext, args[0], args[1], args[2]);
+if (c2) {/* LSL / UBFM Wd, Wn, (32 - m) */
+tcg_out_shl(s, ext, a0, a1, a2);
} else {/* LSL / LSLV */
-tcg_out_shiftrot_reg(s, SRR_SHL, ext, args[0], args[1], args[2]);
+tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
case INDEX_op_shr_i32:
-if (const_args[2]) {/* LSR / UBFM Wd, Wn, m, 31 */
-tcg_out_shr(s, ext, args[0], args[1], args[2]);
+if (c2) {/* LSR / UBFM Wd, Wn, m, 31 */
+tcg_out_shr(s, ext, a0, a1, a2);
} else {/* LSR / LSRV */
-tcg_out_shiftrot_reg(s, SRR_SHR, ext, args[0], args[1], args[2]);
+tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
case INDEX_op_sar_i32:
-if (const_args[2]) {/* ASR / SBFM Wd
[Qemu-devel] [PATCH v4 01/33] tcg-aarch64: Change all ext variables to TCGType
We assert that the values for _I32 and _I64 are 0 and 1 respectively.
This will make a couple of functions declared by tcg.c cleaner.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 64
1 file changed, 37 insertions(+), 27 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 6379df1..cf36551 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -12,6 +12,11 @@
#include "qemu/bitops.h"
+/* We're going to re-use TCGType in setting of the SF bit, which controls
+ the size of the operation performed. If we know the values match, it
+ makes things much cleaner. */
+QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
+
#ifndef NDEBUG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"%x0", "%x1", "%x2", "%x3", "%x4", "%x5", "%x6", "%x7",
@@ -326,7 +331,8 @@ static inline void tcg_out_ldst_12(TCGContext *s,
| op_type << 20 | scaled_uimm << 10 | rn << 5 | rd);
}
-static inline void tcg_out_movr(TCGContext *s, int ext, TCGReg rd, TCGReg src)
+static inline void tcg_out_movr(TCGContext *s, TCGType ext,
+TCGReg rd, TCGReg src)
{
/* register to register move using MOV (shifted register with no shift) */
/* using MOV 0x2a0003e0 | (shift).. */
@@ -407,7 +413,8 @@ static inline void tcg_out_ldst(TCGContext *s, enum
aarch64_ldst_op_data data,
}
/* mov alias implemented with add immediate, useful to move to/from SP */
-static inline void tcg_out_movr_sp(TCGContext *s, int ext, TCGReg rd, TCGReg
rn)
+static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
+ TCGReg rd, TCGReg rn)
{
/* using ADD 0x1100 | (ext) | rn << 5 | rd */
unsigned int base = ext ? 0x9100 : 0x1100;
@@ -437,7 +444,7 @@ static inline void tcg_out_st(TCGContext *s, TCGType type,
TCGReg arg,
}
static inline void tcg_out_arith(TCGContext *s, enum aarch64_arith_opc opc,
- int ext, TCGReg rd, TCGReg rn, TCGReg rm,
+ TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm,
int shift_imm)
{
/* Using shifted register arithmetic operations */
@@ -453,7 +460,7 @@ static inline void tcg_out_arith(TCGContext *s, enum
aarch64_arith_opc opc,
tcg_out32(s, base | rm << 16 | shift | rn << 5 | rd);
}
-static inline void tcg_out_mul(TCGContext *s, int ext,
+static inline void tcg_out_mul(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm)
{
/* Using MADD 0x1b00 with Ra = wzr alias MUL 0x1b007c00 */
@@ -462,7 +469,7 @@ static inline void tcg_out_mul(TCGContext *s, int ext,
}
static inline void tcg_out_shiftrot_reg(TCGContext *s,
-enum aarch64_srr_opc opc, int ext,
+enum aarch64_srr_opc opc, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm)
{
/* using 2-source data processing instructions 0x1ac02000 */
@@ -470,23 +477,23 @@ static inline void tcg_out_shiftrot_reg(TCGContext *s,
tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd);
}
-static inline void tcg_out_ubfm(TCGContext *s, int ext, TCGReg rd, TCGReg rn,
-unsigned int a, unsigned int b)
+static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
+TCGReg rn, unsigned int a, unsigned int b)
{
/* Using UBFM 0x5300 Wd, Wn, a, b */
unsigned int base = ext ? 0xd340 : 0x5300;
tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
}
-static inline void tcg_out_sbfm(TCGContext *s, int ext, TCGReg rd, TCGReg rn,
-unsigned int a, unsigned int b)
+static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
+TCGReg rn, unsigned int a, unsigned int b)
{
/* Using SBFM 0x1300 Wd, Wn, a, b */
unsigned int base = ext ? 0x9340 : 0x1300;
tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
}
-static inline void tcg_out_extr(TCGContext *s, int ext, TCGReg rd,
+static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, TCGReg rm, unsigned int a)
{
/* Using EXTR 0x1380 Wd, Wn, Wm, a */
@@ -494,7 +501,7 @@ static inline void tcg_out_extr(TCGContext *s, int ext,
TCGReg rd,
tcg_out32(s, base | rm << 16 | a << 10 | rn << 5 | rd);
}
-static inline void tcg_out_shl(TCGContext *s, int ext,
+static inline void tcg_out_shl(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, unsigned int m)
{
int bits, max;
@@ -503,28 +510,28 @@ static inline void tcg_out_shl(TCGContext *s, int ext,
tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max));
}
[Qemu-devel] [PATCH v4 05/33] tcg-aarch64: Change enum aarch64_arith_opc to AArch64Insn
And since we're no longer talking about opcodes, change the
values to be shifted into the opcode field, avoiding a shift
at runtime.
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 43 +++
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 8f5814d..99d9884 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -204,16 +204,19 @@ enum aarch64_ldst_op_type { /* type of operation */
LDST_LD_S_W = 0xc, /* load and sign-extend into Wt */
};
-enum aarch64_arith_opc {
-ARITH_AND = 0x0a,
-ARITH_ADD = 0x0b,
-ARITH_OR = 0x2a,
-ARITH_ADDS = 0x2b,
-ARITH_XOR = 0x4a,
-ARITH_SUB = 0x4b,
-ARITH_ANDS = 0x6a,
-ARITH_SUBS = 0x6b,
-};
+typedef enum {
+/* Logical shifted register instructions */
+INSN_AND= 0x0a00,
+INSN_ORR= 0x2a00,
+INSN_EOR= 0x4a00,
+INSN_ANDS = 0x6a00,
+
+/* Add/subtract shifted register instructions */
+INSN_ADD= 0x0b00,
+INSN_ADDS = 0x2b00,
+INSN_SUB= 0x4b00,
+INSN_SUBS = 0x6b00,
+} AArch64Insn;
enum aarch64_srr_opc {
SRR_SHL = 0x0,
@@ -443,13 +446,13 @@ static inline void tcg_out_st(TCGContext *s, TCGType
type, TCGReg arg,
arg, arg1, arg2);
}
-static inline void tcg_out_arith(TCGContext *s, enum aarch64_arith_opc opc,
+static inline void tcg_out_arith(TCGContext *s, AArch64Insn insn,
TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm,
int shift_imm)
{
/* Using shifted register arithmetic operations */
/* if extended register operation (64bit) just OR with 0x80 << 24 */
-unsigned int shift, base = ext ? (0x80 | opc) << 24 : opc << 24;
+unsigned int shift, base = insn | (ext ? 0x8000 : 0);
if (shift_imm == 0) {
shift = 0;
} else if (shift_imm > 0) {
@@ -544,7 +547,7 @@ static inline void tcg_out_cmp(TCGContext *s, TCGType ext,
TCGReg rn,
TCGReg rm, int shift_imm)
{
/* Using CMP alias SUBS wzr, Wn, Wm */
-tcg_out_arith(s, ARITH_SUBS, ext, TCG_REG_XZR, rn, rm, shift_imm);
+tcg_out_arith(s, INSN_SUBS, ext, TCG_REG_XZR, rn, rm, shift_imm);
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -904,7 +907,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
/* Merge the tlb index contribution into X2.
X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
-tcg_out_arith(s, ARITH_ADD, 1, TCG_REG_X2, TCG_REG_X2,
+tcg_out_arith(s, INSN_ADD, 1, TCG_REG_X2, TCG_REG_X2,
TCG_REG_X0, -CPU_TLB_ENTRY_BITS);
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
@@ -1181,27 +1184,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_i64:
case INDEX_op_add_i32:
-tcg_out_arith(s, ARITH_ADD, ext, a0, a1, a2, 0);
+tcg_out_arith(s, INSN_ADD, ext, a0, a1, a2, 0);
break;
case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
-tcg_out_arith(s, ARITH_SUB, ext, a0, a1, a2, 0);
+tcg_out_arith(s, INSN_SUB, ext, a0, a1, a2, 0);
break;
case INDEX_op_and_i64:
case INDEX_op_and_i32:
-tcg_out_arith(s, ARITH_AND, ext, a0, a1, a2, 0);
+tcg_out_arith(s, INSN_AND, ext, a0, a1, a2, 0);
break;
case INDEX_op_or_i64:
case INDEX_op_or_i32:
-tcg_out_arith(s, ARITH_OR, ext, a0, a1, a2, 0);
+tcg_out_arith(s, INSN_ORR, ext, a0, a1, a2, 0);
break;
case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
-tcg_out_arith(s, ARITH_XOR, ext, a0, a1, a2, 0);
+tcg_out_arith(s, INSN_EOR, ext, a0, a1, a2, 0);
break;
case INDEX_op_mul_i64:
@@ -1250,7 +1253,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (c2) {/* ROR / EXTR Wd, Wm, Wm, 32 - m */
tcg_out_rotl(s, ext, a0, a1, a2);
} else {
-tcg_out_arith(s, ARITH_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0);
+tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0);
tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP);
}
break;
--
1.8.3.1
[Qemu-devel] [PATCH v4 02/33] tcg-aarch64: Set ext based on TCG_OPF_64BIT
Signed-off-by: Richard Henderson
---
tcg/aarch64/tcg-target.c | 28 +++-
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index cf36551..983a74a 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1115,9 +1115,9 @@ static inline void tcg_out_load_pair(TCGContext *s,
TCGReg addr,
static void tcg_out_op(TCGContext *s, TCGOpcode opc,
const TCGArg *args, const int *const_args)
{
-/* ext will be set in the switch below, which will fall through to the
- common code. It triggers the use of extended regs where appropriate. */
-TCGType ext = 0;
+/* 99% of the time, we can signal the use of extension registers
+ by looking to see if the opcode handles 64-bit data. */
+TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
switch (opc) {
case INDEX_op_exit_tb:
@@ -1173,7 +1173,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_mov_i64:
-ext = 1; /* fall through */
case INDEX_op_mov_i32:
tcg_out_movr(s, ext, args[0], args[1]);
break;
@@ -1186,43 +1185,36 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_add_i64:
-ext = 1; /* fall through */
case INDEX_op_add_i32:
tcg_out_arith(s, ARITH_ADD, ext, args[0], args[1], args[2], 0);
break;
case INDEX_op_sub_i64:
-ext = 1; /* fall through */
case INDEX_op_sub_i32:
tcg_out_arith(s, ARITH_SUB, ext, args[0], args[1], args[2], 0);
break;
case INDEX_op_and_i64:
-ext = 1; /* fall through */
case INDEX_op_and_i32:
tcg_out_arith(s, ARITH_AND, ext, args[0], args[1], args[2], 0);
break;
case INDEX_op_or_i64:
-ext = 1; /* fall through */
case INDEX_op_or_i32:
tcg_out_arith(s, ARITH_OR, ext, args[0], args[1], args[2], 0);
break;
case INDEX_op_xor_i64:
-ext = 1; /* fall through */
case INDEX_op_xor_i32:
tcg_out_arith(s, ARITH_XOR, ext, args[0], args[1], args[2], 0);
break;
case INDEX_op_mul_i64:
-ext = 1; /* fall through */
case INDEX_op_mul_i32:
tcg_out_mul(s, ext, args[0], args[1], args[2]);
break;
case INDEX_op_shl_i64:
-ext = 1; /* fall through */
case INDEX_op_shl_i32:
if (const_args[2]) {/* LSL / UBFM Wd, Wn, (32 - m) */
tcg_out_shl(s, ext, args[0], args[1], args[2]);
@@ -1232,7 +1224,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_shr_i64:
-ext = 1; /* fall through */
case INDEX_op_shr_i32:
if (const_args[2]) {/* LSR / UBFM Wd, Wn, m, 31 */
tcg_out_shr(s, ext, args[0], args[1], args[2]);
@@ -1242,7 +1233,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_sar_i64:
-ext = 1; /* fall through */
case INDEX_op_sar_i32:
if (const_args[2]) {/* ASR / SBFM Wd, Wn, m, 31 */
tcg_out_sar(s, ext, args[0], args[1], args[2]);
@@ -1252,7 +1242,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_rotr_i64:
-ext = 1; /* fall through */
case INDEX_op_rotr_i32:
if (const_args[2]) {/* ROR / EXTR Wd, Wm, Wm, m */
tcg_out_rotr(s, ext, args[0], args[1], args[2]);
@@ -1262,7 +1251,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_rotl_i64:
-ext = 1; /* fall through */
case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */
if (const_args[2]) {/* ROR / EXTR Wd, Wm, Wm, 32 - m */
tcg_out_rotl(s, ext, args[0], args[1], args[2]);
@@ -1275,14 +1263,12 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_brcond_i64:
-ext = 1; /* fall through */
case INDEX_op_brcond_i32: /* CMP 0, 1, cond(2), label 3 */
tcg_out_cmp(s, ext, args[0], args[1], 0);
tcg_out_goto_label_cond(s, args[2], args[3]);
break;
case INDEX_op_setcond_i64:
-ext = 1; /* fall through */
case INDEX_op_setcond_i32:
tcg_out_cmp(s, ext, args[1], args[2], 0);
tcg_out_cset(s, 0, args[0], args[3]);
@@ -1325,9 +1311,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_qemu_st(s, args, 3);
break;
-case INDEX_op_bswap64_i64:
-ext = 1; /* fall through */
case INDEX_op_bswap32_i64:
+/* Despite the _i64, this is a 32-bit bswap. */
+ext = 0;
+/* FALLTHRU */
+case INDEX_op_bswap64_i64:
case INDEX_op_bswap32_i32:
tcg_out_rev(s, ext, args[0], args[1]);
break;
@@ -1337,12 +1325,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break
[Qemu-devel] subregion collisions
Enabling the print in memory.c shows quite a lot of these: warning: subregion collision fec0/1000 (ioapic) vs 800/f800 (pci-hole) warning: subregion collision fed0/400 (hpet) vs 800/f800 (pci-hole) warning: subregion collision 0/80 (ich9-pm) vs 8/8 (dma-cont) warning: subregion collision 0/80 (ich9-pm) vs 0/8 (dma-chan) warning: subregion collision 0/80 (ich9-pm) vs 64/1 (i8042-cmd) warning: subregion collision 0/80 (ich9-pm) vs 60/1 (i8042-data) warning: subregion collision 0/80 (ich9-pm) vs 61/1 (elcr) warning: subregion collision 0/80 (ich9-pm) vs 40/4 (pit) warning: subregion collision 0/80 (ich9-pm) vs 70/2 (rtc) warning: subregion collision 0/80 (ich9-pm) vs 20/2 (pic) warning: subregion collision 0/80 (ich9-pm) vs 7e/2 (kvmvapic) warning: subregion collision b000/1000 (pcie-mmcfg) vs 800/f800 (pci-hole) They likely work fine because the initialization order happens to give priority to regions which are registered later. But we really should fix these, should we not?
Re: [Qemu-devel] [PATCH RFC v3 2/2] hw/pci: handle unassigned pci addresses
On Mon, Sep 09, 2013 at 02:21:36PM +0300, Marcel Apfelbaum wrote:
> Created a MemoryRegion with negative priority that
> spans over all the pci address space.
> It "intercepts" the accesses to unassigned pci
> address space and will follow the pci spec:
> 1. returns -1 on read
> 2. does nothing on write
> 3. sets the RECEIVED MASTER ABORT bit in the STATUS register
> of the device that initiated the transaction
>
> Note: This implementation assumes that all the reads/writes to
> the pci address space are done by the cpu.
>
> Signed-off-by: Marcel Apfelbaum
> ---
> Changes from v1:
> - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on
> various Host Bridges
> - "pci-unassgined-mem" does not have a ".valid.accept" field and
> implements read write methods
>
> hw/pci/pci.c | 46 ++
> include/hw/pci/pci_bus.h | 1 +
> 2 files changed, 47 insertions(+)
>
> diff --git a/hw/pci/pci.c b/hw/pci/pci.c
> index d00682e..b6a8026 100644
> --- a/hw/pci/pci.c
> +++ b/hw/pci/pci.c
> @@ -283,6 +283,43 @@ const char *pci_root_bus_path(PCIDevice *dev)
> return rootbus->qbus.name;
> }
>
> +static void unassigned_mem_access(PCIBus *bus)
> +{
> +/* FIXME assumption: memory access to the pci address
> + * space is always initiated by the host bridge
> + * (device 0 on the bus) */
> +PCIDevice *d = bus->devices[0];
> +if (!d) {
> +return;
> +}
> +
> +pci_word_test_and_set_mask(d->config + PCI_STATUS,
> + PCI_STATUS_REC_MASTER_ABORT);
> +}
> +
> +static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +PCIBus *bus = opaque;
> +unassigned_mem_access(bus);
> +
> +return -1ULL;
> +}
> +
> +static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val,
> +unsigned size)
> +{
> +PCIBus *bus = opaque;
> +unassigned_mem_access(bus);
> +}
> +
> +static const MemoryRegionOps unassigned_mem_ops = {
> +.read = unassigned_mem_read,
> +.write = unassigned_mem_write,
> +.endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +#define UNASSIGNED_MEM_PRIORITY -1
> +
This really should be "lowest available priority" correct?
So how about making it INT_MIN then?
> static void pci_bus_init(PCIBus *bus, DeviceState *parent,
> const char *name,
> MemoryRegion *address_space_mem,
> @@ -294,6 +331,15 @@ static void pci_bus_init(PCIBus *bus, DeviceState
> *parent,
> bus->address_space_mem = address_space_mem;
> bus->address_space_io = address_space_io;
>
> +
> +memory_region_init_io(&bus->unassigned_mem, OBJECT(bus),
> + &unassigned_mem_ops, bus, "pci-unassigned",
> + memory_region_size(bus->address_space_mem));
> +memory_region_add_subregion_overlap(bus->address_space_mem,
> +bus->address_space_mem->addr,
> +&bus->unassigned_mem,
> +UNASSIGNED_MEM_PRIORITY);
> +
> /* host bridge */
> QLIST_INIT(&bus->child);
>
> diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
> index 9df1788..4cc25a3 100644
> --- a/include/hw/pci/pci_bus.h
> +++ b/include/hw/pci/pci_bus.h
> @@ -23,6 +23,7 @@ struct PCIBus {
> PCIDevice *parent_dev;
> MemoryRegion *address_space_mem;
> MemoryRegion *address_space_io;
> +MemoryRegion unassigned_mem;
>
> QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
> QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
> --
> 1.8.3.1
Re: [Qemu-devel] [PATCH] tci: Detect function argument alignment
Michael Walle and Jia Liu, see below wrt minor lm32 and openrisc mistakes. On 09/14/2013 02:51 AM, Peter Maydell wrote: >> I had a look on libffi now and don't see how it could solve my problem. >> As far as I could see, libffi must be ported to new architectures, so >> its use would restrict the portability of TCI. > > Yes, but it's somebody else's problem to port it, not ours. > I present it mostly as an alternative to doing it the hard way. In particular, libffi is used by gcc within its libjava implementation. Which tends to mean that every (non-embedded) target to which gcc is ported also gets a port of libffi. It is tempting to want to avoid the extra external build dependency, but we have so many now that working too hard to avoid another seems silly. >> There is a drawback of that solution: it needs modifications in the TCG >> opcode generation which would no longer be identical to all other TCG >> targets (or I'd have to search the given address of the helper function >> in a lookup table which would cost too much time). > > Nobody's running TCI for the performance benefit :-) Use a hash > table, there's one in glib and it won't have much overhead at all for lookups. Indeed. And one can minimize that lookup cost by doing that when building the TB, as opposed to when we interpret it. As far as actually interfacing with libffi, one builds ffi_cif structures that describe the arguments and return value. Given the contents of the target-foo/helper.h file, we ought to be able to statically build data structures of the ffi_type* inputs, and use those to generate all of the ffi_cif structures within tcg_target_init. We probably need to clean up the interface from target-foo to tcg.c a bit to facilitate this. In the process, we'd be able to reduce some startup overhead wrt cpu_translate_init. We currently use /* register helpers */ #define GEN_HELPER 2 #include "helper.h" which expands to, in the case of i386, 514 calls to tcg_register_helper. We ought to be able to build a static table within tcg.o instead. It also means that one wouldn't be able to *forget* to register helpers on the target side. The lm32 and openrisc target have forgotten that. That's not to say that we don't still need changes to tcg.c to allow ffi_call to actually be used. In particular, getting the data into the avalue array is non-trivial. As is getting the results out of rvalue. One needs to store the argument data such that one knows where the argument boundaries are. I.e., at minimum one still needs to know the sizes of each argument. That minimum could be passing along the "sizemask" value used during tcg_gen_callN. Currently we discard that value there in tcg_gen_callN, but that's not to say we couldn't store it in the INDEX_op_call opcode. And pass it along to tcg_gen_opc as args[1]. Actually, with just that last change we wouldn't necessarily have to clean up the target-foo/helper.h interface first. We'd have just enough info to build the ffi_cif on demand during translation of the INDEX_op_call. r~
[Qemu-devel] [PULL 04/15] *-user: Fix typo in comment (ulocking -> unlocking)
From: Stefan Weil Signed-off-by: Stefan Weil Reviewed-by: Peter Maydell Signed-off-by: Michael Tokarev --- bsd-user/qemu.h |2 +- linux-user/qemu.h |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 325f564..1f8ec6e 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -381,7 +381,7 @@ static inline void *lock_user_string(abi_ulong guest_addr) return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); } -/* Helper macros for locking/ulocking a target struct. */ +/* Helper macros for locking/unlocking a target struct. */ #define lock_user_struct(type, host_ptr, guest_addr, copy) \ (host_ptr = lock_user(type, guest_addr, sizeof(*host_ptr), copy)) #define unlock_user_struct(host_ptr, guest_addr, copy) \ diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 6ffe5a2..4422dfc 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -438,7 +438,7 @@ static inline void *lock_user_string(abi_ulong guest_addr) return lock_user(VERIFY_READ, guest_addr, (long)(len + 1), 1); } -/* Helper macros for locking/ulocking a target struct. */ +/* Helper macros for locking/unlocking a target struct. */ #define lock_user_struct(type, host_ptr, guest_addr, copy) \ (host_ptr = lock_user(type, guest_addr, sizeof(*host_ptr), copy)) #define unlock_user_struct(host_ptr, guest_addr, copy) \ -- 1.7.10.4
[Qemu-devel] [PULL 15/15] configure: Enable extra compiler warnings
From: Stefan Weil
Compiler option -Wextra enables an additional set of compiler warnings.
Some of these warnings were already enabled explicitly in QEMU:
-Wold-style-declaration, -Wtype-limits, -Wignored-qualifiers and
-Wempty-body are now redundant and can be removed.
Others don't work with the current code and must be disabled to
avoid warnings: -Wno-missing-field-initializers, -Wno-override-init,
-Wno-sign-compare and -Wno-unused-parameter.
Signed-off-by: Stefan Weil
Signed-off-by: Michael Tokarev
---
configure | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/configure b/configure
index 21451ba..a17cac7 100755
--- a/configure
+++ b/configure
@@ -310,7 +310,7 @@ sdl_config="${SDL_CONFIG-${cross_prefix}sdl-config}"
# default flags for all hosts
QEMU_CFLAGS="-fno-strict-aliasing $QEMU_CFLAGS"
-QEMU_CFLAGS="-Wall -Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS"
+QEMU_CFLAGS="-Wall -Wextra -Wundef -Wwrite-strings -Wmissing-prototypes
$QEMU_CFLAGS"
QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS"
QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE
$QEMU_CFLAGS"
QEMU_INCLUDES="-I. -I\$(SRC_PATH) -I\$(SRC_PATH)/include"
@@ -1236,12 +1236,16 @@ if test -z "$werror" ; then
fi
fi
-gcc_flags="-Wold-style-declaration -Wold-style-definition -Wtype-limits"
-gcc_flags="-Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers
$gcc_flags"
-gcc_flags="-Wmissing-include-dirs -Wempty-body -Wnested-externs $gcc_flags"
+gcc_flags="-Wold-style-definition"
+gcc_flags="-Wformat-security -Wformat-y2k -Winit-self $gcc_flags"
+gcc_flags="-Wmissing-include-dirs -Wnested-externs $gcc_flags"
gcc_flags="-Wendif-labels $gcc_flags"
gcc_flags="-Wno-initializer-overrides $gcc_flags"
+gcc_flags="-Wno-missing-field-initializers $gcc_flags"
+gcc_flags="-Wno-override-init $gcc_flags"
+gcc_flags="-Wno-sign-compare $gcc_flags"
gcc_flags="-Wno-string-plus-int $gcc_flags"
+gcc_flags="-Wno-unused-parameter $gcc_flags"
# Note that we do not add -Werror to gcc_flags here, because that would
# enable it for all configure tests. If a configure test failed due
# to -Werror this would just silently disable some features,
--
1.7.10.4
[Qemu-devel] [PULL 08/15] tci: Fix qemu-alpha on 32 bit hosts (wrong assertions)
From: Stefan Weil Debian busybox-static for alpha has a load address of 0x00012000 which is mapped to 0x2000 for 32 bit hosts. qemu-alpha uses the TCG opcodes qemu_ld32, qemu_ld64, qemu_st32 and qemu_st64 which all raise the assertion (taddr == host_addr). Remove all assertions of this type because they are either wrong or unnecessary (when sizeof(tcg_target_ulong) >= sizeof(target_ulong)). Cc: qemu-stable Signed-off-by: Stefan Weil Reviewed-by: Richard Henderson Signed-off-by: Michael Tokarev --- tci.c | 12 1 file changed, 12 deletions(-) diff --git a/tci.c b/tci.c index 18c888e..6d64891 100644 --- a/tci.c +++ b/tci.c @@ -1085,7 +1085,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp8 = *(uint8_t *)(host_addr + GUEST_BASE); #endif tci_write_reg8(t0, tmp8); @@ -1097,7 +1096,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp8 = *(uint8_t *)(host_addr + GUEST_BASE); #endif tci_write_reg8s(t0, tmp8); @@ -1109,7 +1107,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg16(t0, tmp16); @@ -1121,7 +1118,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg16s(t0, tmp16); @@ -1134,7 +1130,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg32(t0, tmp32); @@ -1146,7 +1141,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg32s(t0, tmp32); @@ -1159,7 +1153,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg32(t0, tmp32); @@ -1174,7 +1167,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr)); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE)); #endif tci_write_reg(t0, tmp64); @@ -1190,7 +1182,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) helper_stb_mmu(env, taddr, t0, t2); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); *(uint8_t *)(host_addr + GUEST_BASE) = t0; #endif break; @@ -1202,7 +1193,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) helper_stw_mmu(env, taddr, t0, t2); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); *(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0); #endif break; @@ -1214,7 +1204,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) helper_stl_mmu(env, taddr, t0, t2); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); *(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0); #endif break; @@ -1226,7 +1215,6 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) helper_stq_mmu(env, taddr, tmp64, t2); #else host_addr = (tcg_target_ulong)taddr; -assert(taddr == host_addr); *(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64); #endif break; -- 1.7.10.4
[Qemu-devel] [PULL 12/15] target-i386: Fix segment cache dump
From: Tobias Markus
When in Long Mode, cpu_x86_seg_cache() logs "DS16" because the Default
operation size bit (D/B bit) is not set for Long Mode Data Segments since
there are only Data Segments in Long Mode and no explicit 16/32/64-bit
Descriptors.
This patch fixes this by checking the Long Mode Active bit of the hidden
flags variable and logging "DS" if it is set. (I.e. in Long Mode all Data
Segments are logged as "DS")
Signed-off-by: Tobias Markus
Reviewed-by: Richard Henderson
Signed-off-by: Michael Tokarev
---
target-i386/helper.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 7c58e27..eef3334 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -147,7 +147,9 @@ cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
fprintf_function cpu_fprintf,
cpu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
(sc->flags & DESC_R_MASK) ? 'R' : '-');
} else {
-cpu_fprintf(f, (sc->flags & DESC_B_MASK) ? "DS " : "DS16");
+cpu_fprintf(f,
+(sc->flags & DESC_B_MASK || env->hflags & HF_LMA_MASK)
+? "DS " : "DS16");
cpu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
(sc->flags & DESC_W_MASK) ? 'W' : '-');
}
--
1.7.10.4
[Qemu-devel] [PULL 06/15] MAINTAINERS: Add missing entry to filelist for TCI target
From: Stefan Weil tci.c is also a maintained part of the TCI implementation. Signed-off-by: Stefan Weil Reviewed-by: Richard Henderson Signed-off-by: Michael Tokarev --- MAINTAINERS |1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index d128ed0..4d634f2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -842,6 +842,7 @@ TCI target M: Stefan Weil S: Maintained F: tcg/tci/ +F: tci.c Stable branches --- -- 1.7.10.4
[Qemu-devel] [PULL 11/15] iov: avoid "orig_len may be used unitialized" warning
Signed-off-by: Wenchao Xia
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Michael Tokarev
---
util/iov.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/util/iov.c b/util/iov.c
index f705586..bb46c04 100644
--- a/util/iov.c
+++ b/util/iov.c
@@ -181,13 +181,11 @@ ssize_t iov_send_recv(int sockfd, struct iovec *iov,
unsigned iov_cnt,
assert(iov[niov].iov_len > tail);
orig_len = iov[niov].iov_len;
iov[niov++].iov_len = tail;
-}
-
-ret = do_send_recv(sockfd, iov, niov, do_send);
-
-/* Undo the changes above before checking for errors */
-if (tail) {
+ret = do_send_recv(sockfd, iov, niov, do_send);
+/* Undo the changes above before checking for errors */
iov[niov-1].iov_len = orig_len;
+} else {
+ret = do_send_recv(sockfd, iov, niov, do_send);
}
if (offset) {
iov[0].iov_base -= offset;
--
1.7.10.4
[Qemu-devel] [PULL 14/15] tcg-sparc: Fix parenthesis warning
From: Richard Henderson
error: suggest parentheses around comparison in operand of ‘&’
[-Werror=parentheses]
Signed-off-by: Richard Henderson
Signed-off-by: Michael Tokarev
---
tcg/sparc/tcg-target.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 2edf858..1ff2922 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -153,7 +153,7 @@ typedef enum {
static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{
uintptr_t p;
-for (p = start & -8; p < (stop + 7) & -8; p += 8) {
+for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
__asm__ __volatile__("flush\t%0" : : "r" (p));
}
}
--
1.7.10.4
[Qemu-devel] [PULL 13/15] Makefile: Remove some more files when cleaning
From: Stefan Weil
Signed-off-by: Stefan Weil
Signed-off-by: Michael Tokarev
---
Makefile |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 362fe3e..f6da5fe 100644
--- a/Makefile
+++ b/Makefile
@@ -236,7 +236,8 @@ clean:
find . -name '*.[oda]' -type f -exec rm -f {} +
find . -name '*.l[oa]' -type f -exec rm -f {} +
rm -f $(filter-out %.tlb,$(TOOLS)) $(HELPERS-y) qemu-ga TAGS cscope.*
*.pod *~ */*~
- rm -Rf .libs
+ rm -f fsdev/*.pod
+ rm -rf .libs */.libs
rm -f qemu-img-cmds.h
@# May not be present in GENERATED_HEADERS
rm -f trace/generated-tracers-dtrace.dtrace*
@@ -261,6 +262,7 @@ qemu-%.tar.bz2:
distclean: clean
rm -f config-host.mak config-host.h* config-host.ld $(DOCS)
qemu-options.texi qemu-img-cmds.texi qemu-monitor.texi
rm -f config-all-devices.mak config-all-disas.mak
+ rm -f po/*.mo
rm -f roms/seabios/config.mak roms/vgabios/config.mak
rm -f qemu-doc.info qemu-doc.aux qemu-doc.cp qemu-doc.cps qemu-doc.dvi
rm -f qemu-doc.fn qemu-doc.fns qemu-doc.info qemu-doc.ky qemu-doc.kys
--
1.7.10.4
[Qemu-devel] [PULL 10/15] vscclient: remove unnecessary use of uninitialized variable
Signed-off-by: Wenchao Xia
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Michael Tokarev
---
libcacard/vscclient.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/libcacard/vscclient.c b/libcacard/vscclient.c
index 5180d29..a3cb776 100644
--- a/libcacard/vscclient.c
+++ b/libcacard/vscclient.c
@@ -645,7 +645,6 @@ main(
GIOChannel *channel_stdin;
char *qemu_host;
char *qemu_port;
-VSCMsgHeader mhHeader;
VCardEmulOptions *command_line_options = NULL;
@@ -754,7 +753,7 @@ main(
.magic = VSCARD_MAGIC,
.capabilities = {0}
};
-send_msg(VSC_Init, mhHeader.reader_id, &init, sizeof(init));
+send_msg(VSC_Init, 0, &init, sizeof(init));
g_main_loop_run(loop);
g_main_loop_unref(loop);
--
1.7.10.4
[Qemu-devel] [PULL 09/15] trace-events: Clean up with scripts/cleanup-trace-events.pl again
From: Markus Armbruster Event qxl_render_blit_guest_primary_initialized is unused since commit c58c7b9, drop it. Commit 42e5b4c moved hw/ppc/xics.c to hw/intc/xics.c without updating the comment in trace-events. "scripts/cleanup-trace-events.pl trace-events | diff trace-events" is now clean again. Signed-off-by: Markus Armbruster Signed-off-by: Michael Tokarev --- trace-events |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/trace-events b/trace-events index d4dba24..9a1347b 100644 --- a/trace-events +++ b/trace-events @@ -1109,7 +1109,6 @@ qemu_spice_wakeup(uint32_t qid) "%d" qemu_spice_create_update(uint32_t left, uint32_t right, uint32_t top, uint32_t bottom) "lr %d -> %d, tb -> %d -> %d" # hw/display/qxl-render.c -qxl_render_blit_guest_primary_initialized(void) "" qxl_render_blit(int32_t stride, int32_t left, int32_t right, int32_t top, int32_t bottom) "stride=%d [%d, %d, %d, %d]" qxl_render_guest_primary_resized(int32_t width, int32_t height, int32_t stride, int32_t bytes_pp, int32_t bits_pp) "%dx%d, stride %d, bpp %d, depth %d" qxl_render_update_area_done(void *cookie) "%p" @@ -1122,7 +1121,7 @@ spapr_pci_rtas_ibm_query_interrupt_source_number(unsigned ioa, unsigned intr) "q spapr_pci_msi_write(uint64_t addr, uint64_t data, uint32_t dt_irq) "@%"PRIx64"<=%"PRIx64" IRQ %u" spapr_pci_lsi_set(const char *busname, int pin, uint32_t irq) "%s PIN%d IRQ %u" -# hw/ppc/xics.c +# hw/intc/xics.c xics_icp_check_ipi(int server, uint8_t mfrr) "CPU %d can take IPI mfrr=%#x" xics_icp_accept(uint32_t old_xirr, uint32_t new_xirr) "icp_accept: XIRR %#"PRIx32"->%#"PRIx32 xics_icp_eoi(int server, uint32_t xirr, uint32_t new_xirr) "icp_eoi: server %d given XIRR %#"PRIx32" new XIRR %#"PRIx32 -- 1.7.10.4
[Qemu-devel] [PULL 01/15] configure: Undefine _FORTIFY_SOURCE prior using it
From: Michal Privoznik Currently, we are enforcing the _FORTIFY_SOURCE=2 without any previous detection if the macro has been already defined, e.g. by environment, or is just enabled by compiler by default. Signed-off-by: Michal Privoznik Signed-off-by: Jan Vesely Reviewed-by: Peter Maydell Signed-off-by: Michael Tokarev --- configure |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure b/configure index 2b83936..21451ba 100755 --- a/configure +++ b/configure @@ -3502,7 +3502,7 @@ if test "$gcov" = "yes" ; then CFLAGS="-fprofile-arcs -ftest-coverage -g $CFLAGS" LDFLAGS="-fprofile-arcs -ftest-coverage $LDFLAGS" elif test "$debug" = "no" ; then - CFLAGS="-O2 -D_FORTIFY_SOURCE=2 $CFLAGS" + CFLAGS="-O2 -U_FORTIFY_SOURCE -D_FORTIFY_SOURCE=2 $CFLAGS" fi -- 1.7.10.4
[Qemu-devel] [PULL 07/15] *-user: Improve documentation for lock_user function
From: Stefan Weil Add a missing "function" and replace "and" by "any". BSD and Linux use the same documentation here, so fix both. Signed-off-by: Stefan Weil Reviewed-by: Peter Maydell Signed-off-by: Michael Tokarev --- bsd-user/qemu.h |4 ++-- linux-user/qemu.h |4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 1f8ec6e..ddc74ed 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -323,9 +323,9 @@ abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); /* Functions for accessing guest memory. The tget and tput functions - read/write single values, byteswapping as necessary. The lock_user + read/write single values, byteswapping as necessary. The lock_user function gets a pointer to a contiguous area of guest memory, but does not perform - and byteswapping. lock_user may return either a pointer to the guest + any byteswapping. lock_user may return either a pointer to the guest memory, or a temporary buffer. */ /* Lock an area of guest memory into the host. If copy is true then the diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 4422dfc..617cac1 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -380,9 +380,9 @@ abi_long copy_from_user(void *hptr, abi_ulong gaddr, size_t len); abi_long copy_to_user(abi_ulong gaddr, void *hptr, size_t len); /* Functions for accessing guest memory. The tget and tput functions - read/write single values, byteswapping as necessary. The lock_user + read/write single values, byteswapping as necessary. The lock_user function gets a pointer to a contiguous area of guest memory, but does not perform - and byteswapping. lock_user may return either a pointer to the guest + any byteswapping. lock_user may return either a pointer to the guest memory, or a temporary buffer. */ /* Lock an area of guest memory into the host. If copy is true then the -- 1.7.10.4
[Qemu-devel] [PULL 05/15] translate-all: Fix formatting of dump output
From: Stefan Weil
The page dump writes a table with 3 abi_ulong values in each row.
These values take 8 or 16 characters (depending on sizeof abi_ulong).
Fix the table headings to be aligned with the table columns.
old:
startend size prot
00012000-00012021e000 0021e000 rwx
0040-00402000 2000 ---
00402000-004000802000 0080 rw-
new:
startend size prot
00012000-00012021e000 0021e000 rwx
0040-00402000 2000 ---
00402000-004000802000 0080 rw-
Signed-off-by: Stefan Weil
Signed-off-by: Michael Tokarev
---
translate-all.c |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/translate-all.c b/translate-all.c
index 2c923c6..3b97c66 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1679,8 +1679,9 @@ static int dump_region(void *priv, abi_ulong start,
/* dump memory mappings */
void page_dump(FILE *f)
{
-(void) fprintf(f, "%-8s %-8s %-8s %s\n",
-"start", "end", "size", "prot");
+const size_t length = sizeof(abi_ulong) * 2;
+(void) fprintf(f, "%-*s %-*s %-*s %s\n",
+length, "start", length, "end", length, "size", "prot");
walk_memory_regions(f, dump_region);
}
--
1.7.10.4
[Qemu-devel] [PULL 02/15] q35: Fix typo in constant DEFUALT -> DEFAULT.
From: "Richard W.M. Jones"
Signed-off-by: Richard W.M. Jones
Signed-off-by: Michael Tokarev
---
hw/pci-host/q35.c |2 +-
include/hw/pci-host/q35.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 5473504..0cb652d 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -372,7 +372,7 @@ static void mch_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_mch;
k->vendor_id = PCI_VENDOR_ID_INTEL;
k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
-k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT;
+k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT;
k->class_id = PCI_CLASS_BRIDGE_HOST;
}
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 6eb7ab6..56de92e 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -85,7 +85,7 @@ typedef struct Q35PCIHost {
#define MCH_HOST_BRIDGE_CONFIG_DATA0xcfc
/* D0:F0 configuration space */
-#define MCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
+#define MCH_HOST_BRIDGE_REVISION_DEFAULT 0x0
#define MCH_HOST_BRIDGE_PCIEXBAR 0x60/* 64bit register */
#define MCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
--
1.7.10.4
[Qemu-devel] [PULL 03/15] docs: Fix IO port number for CPU present bitmap.
From: Anthony PERARD Signed-off-by: Anthony PERARD Reviewd-By: Igor Mammedov Signed-off-by: Michael Tokarev --- docs/specs/acpi_cpu_hotplug.txt |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/specs/acpi_cpu_hotplug.txt b/docs/specs/acpi_cpu_hotplug.txt index 5dec0c5..f6f5774 100644 --- a/docs/specs/acpi_cpu_hotplug.txt +++ b/docs/specs/acpi_cpu_hotplug.txt @@ -10,7 +10,7 @@ ACPI GPE block (IO ports 0xafe0-0xafe3, byte access): Generic ACPI GPE block. Bit 2 (GPE.2) used to notify CPU hot-add/remove event to ACPI BIOS, via SCI interrupt. -CPU present bitmap (IO port 0xaf00-0xae1f, 1-byte access): +CPU present bitmap (IO port 0xaf00-0xaf1f, 1-byte access): --- One bit per CPU. Bit position reflects corresponding CPU APIC ID. Read-only. -- 1.7.10.4
[Qemu-devel] [PULL 00/15] trivial patches for 2013-09-14
Just a bit late but here's the next trivial-patches pull request. Thanks, /mjt The following changes since commit 2d1fe1873a984d1c2c89ffa3d12949cafc718551: Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20130910' into staging (2013-09-11 14:46:52 -0500) are available in the git repository at: git://git.corpit.ru/qemu.git trivial-patches for you to fetch changes up to f47873f7d5a67ec8c5411abec9786beb8f691a46: configure: Enable extra compiler warnings (2013-09-14 23:42:44 +0400) Anthony PERARD (1): docs: Fix IO port number for CPU present bitmap. Markus Armbruster (1): trace-events: Clean up with scripts/cleanup-trace-events.pl again Michael Tokarev (2): vscclient: remove unnecessary use of uninitialized variable iov: avoid "orig_len may be used unitialized" warning Michal Privoznik (1): configure: Undefine _FORTIFY_SOURCE prior using it Richard Henderson (1): tcg-sparc: Fix parenthesis warning Richard W.M. Jones (1): q35: Fix typo in constant DEFUALT -> DEFAULT. Stefan Weil (7): *-user: Fix typo in comment (ulocking -> unlocking) translate-all: Fix formatting of dump output MAINTAINERS: Add missing entry to filelist for TCI target *-user: Improve documentation for lock_user function tci: Fix qemu-alpha on 32 bit hosts (wrong assertions) Makefile: Remove some more files when cleaning configure: Enable extra compiler warnings Tobias Markus (1): target-i386: Fix segment cache dump MAINTAINERS |1 + Makefile|4 +++- bsd-user/qemu.h |6 +++--- configure | 14 +- docs/specs/acpi_cpu_hotplug.txt |2 +- hw/pci-host/q35.c |2 +- include/hw/pci-host/q35.h |2 +- libcacard/vscclient.c |3 +-- linux-user/qemu.h |6 +++--- target-i386/helper.c|4 +++- tcg/sparc/tcg-target.h |2 +- tci.c | 12 trace-events|3 +-- translate-all.c |5 +++-- util/iov.c | 10 -- 15 files changed, 35 insertions(+), 41 deletions(-)
Re: [Qemu-devel] [PATCH v2] configure: Enable extra compiler warnings
14.09.2013 19:55, Stefan Weil wrote: Compiler option -Wextra enables an additional set of compiler warnings. Some of these warnings were already enabled explicitly in QEMU: -Wold-style-declaration, -Wtype-limits, -Wignored-qualifiers and -Wempty-body are now redundant and can be removed. Others don't work with the current code and must be disabled to avoid warnings: -Wno-missing-field-initializers, -Wno-override-init, -Wno-sign-compare and -Wno-unused-parameter. Thanks, applied to the trivial-patches queue, and (minimally) verified that the result builds on FreeBSD 9. /mjt
Re: [Qemu-devel] [PATCH] pci: remove explicit check to 64K ioport size
On 09/13/2013 04:58 AM, Hervé Poussineau wrote: > This check is useless, as bigger addresses will be ignored when > added to 'io' MemoryRegion, which has a size of 64K. > > However, some architectures don't use the 'io' MemoryRegion, like > the alpha and versatile platforms. They create a PCI I/O region > bigger than 64K, so let them handle PCI I/O BARs in the higher range. > > Signed-off-by: Hervé Poussineau > --- > hw/pci/pci.c |3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) Reviewed-by: Richard Henderson r~
Re: [Qemu-devel] [RFC v3 0/2] use sizes.h macros for power-of-two sizes
On 09/13/2013 12:33 AM, Antony Pavlov wrote: > Changes since v2: > * commit messages: drop ALL 'Reviewed-by' tags. > Drop Aurelien Jarno's tag because the patchseries > was completely reworked, so it need additional review. > > Changes since v1: > > * include/sizes.h -> include/qemu/sizes.h > * fix copyright header; > * fix formatting: drop tabs; > * use the BIT() macro, so it's easy-to-read the constants column; > also the BIT() macro casts constant to UL; > * rebase on updated master; > * take into account the "mips_malta: support up to 2GiB RAM" commit. > > [RFC v3 1/2] include/qemu: introduce sizes.h > [RFC v3 2/2] hw/mips: use sizes.h macros > > The sizes.h macros is a easy-to-read method of > power-of-two memory sizes representation. The sizes.h > macros are actively used in linux kernel and other > projects, so let's use them in QEMU too. > Seems reasonable. I'd have said why bother with some of the multiples, except for the crossover with the linux kernel. Reviewed-by: Richard Henderson r~
Re: [Qemu-devel] [Qemu-trivial] [PATCH] configure: Enable extra compiler warnings
Am 14.09.2013 19:38, schrieb Michael Tokarev: > 14.09.2013 19:30, Stefan Weil wrote: >> Am 14.09.2013 14:18, schrieb Michael Tokarev: > [] >>> Well. I see at least one hidden flag here which is not covered by the >>> description: >>> >>> -gcc_flags="-Wendif-labels $gcc_flags" >>> +gcc_flags="-fstack-protector-all -Wendif-labels $gcc_flags" >>> >>> Is it intentional? >> >> No, -fstack-protector-all should not be there. It might be a relict of >> a previous patch rebase: I added -Wextra in my local branch a long >> time ago, and -fstack-protector-all was obviously moved to another >> location in configure during that time. >> >> I can send an updated patch later, or you can just remove it from >> my original patch. > > Please take a look at the resulting patch at > http://git.corpit.ru/?p=qemu.git;a=shortlog;h=refs/heads/trivial-patches-next > > and see if this is the patch you want to be applied. > > I verified it compiles on FreeBSD 9.1, but I tried only minimal set > of optional dependencies so things might still break, but I think > we can fix it later. > > If it looks okay, I'll send a pull request today. > > Thanks, > > /mjt It looks good, but I'd prefer my v2: http://patchwork.ozlabs.org/patch/274928/. It's nearly identical to your version, but sorts some options alphabetically. Thanks for your work. Stefan
Re: [Qemu-devel] [Qemu-trivial] [PATCH] configure: Enable extra compiler warnings
14.09.2013 19:30, Stefan Weil wrote: Am 14.09.2013 14:18, schrieb Michael Tokarev: [] Well. I see at least one hidden flag here which is not covered by the description: -gcc_flags="-Wendif-labels $gcc_flags" +gcc_flags="-fstack-protector-all -Wendif-labels $gcc_flags" Is it intentional? No, -fstack-protector-all should not be there. It might be a relict of a previous patch rebase: I added -Wextra in my local branch a long time ago, and -fstack-protector-all was obviously moved to another location in configure during that time. I can send an updated patch later, or you can just remove it from my original patch. Please take a look at the resulting patch at http://git.corpit.ru/?p=qemu.git;a=shortlog;h=refs/heads/trivial-patches-next and see if this is the patch you want to be applied. I verified it compiles on FreeBSD 9.1, but I tried only minimal set of optional dependencies so things might still break, but I think we can fix it later. If it looks okay, I'll send a pull request today. Thanks, /mjt
[Qemu-devel] [Bug] qemu-alpha broken on 32 bit hosts
All (?) syscalls fail to handle addresses larger than 32 bit correctly.
See "Bad address" in the strace ouput below.
Tested on arm and on i686 hosts with Debian's busybox-static.
$ alpha-linux-user/qemu-alpha -d unimp,guest_errors -strace
/usr/gnemul/qemu-alpha/bin/busybox ls -l block.c
host mmap_min_addr=0x1000
Reserved 0x21e000 bytes of guest address space
Relocating guest address space from 0x2000 to 0x2000
guest_base 0x0
startend size prot
2000-20218000 00218000 rwx
4000-40002000 2000 ---
40002000-40802000 0080 rw-
20216000-00012021e000 00018000 rwx
start_brk 0x
end_code0x0001202179bd
start_code 0x00012000
start_data 0x00012000
end_data0x0001202179bd
start_stack 0x40801590
brk 0x00012021dcb0
entry 0x0001200d3fe0
15764 uname(0x408012d0) = 0
15764 brk(NULL) = 0x2021e000
15764 brk(0x2021ef8e) = 0x2021ef8e
15764 osf_getsysinfo(45,1082135520,1082136000,0,1082136475,4834034616) = 0
15764 osf_setsysinfo(14,1082135520,1082136000,0,1082136475,4834034616) = 0
15764 brk(0x20240f8e) = 0x20240f8e
15764 brk(0x20242000) = 0x20242000
15764
getxuid(1082136491,3399988123389603631,1082136000,0,1082136475,4834034616)
= 1000
15764 stat64(0x0001201cea90,0x40801290) = -1 errno=14 (Bad
address)
15764 getxgid(1082136529,1082135968,213,1,4832709268,4834034616) = 1000
15764 setgid(1000,1000,213,0,1000,4834034616) = 0
15764 setuid(1000,1000,213,0,1000,4834034616) = 0
15764 gettimeofday(1082135216,0,213,0,1000,4834034616) = 0
15764 ioctl(0,1074295912,1082135220,0,1000,4834034616) = 0
15764 lstat64("block.c",0x40801220) = 0
15764 fstat64(1611596608,0x408008c0) = 0
15764
mmap(NULL,1611596608,PROT_READ|PROT_WRITE,MAP_PRIVATE|MAP_ANONYMOUS,1611596608,0x600f0340)
= 0x40802000
15764 open(0x0001201cedfe,O_RDONLY) = -1 errno=14 (Bad address)
15764 open(0x0001201cedf3,O_RDONLY) = -1 errno=14 (Bad address)
15764 open(0x0001201e0edf,O_RDONLY) = -1 errno=14 (Bad address)
-rw-r--r--1 1000 1000128079 Sep 12 07:23 block.c
15764 write(1,0,1082138624) = 65
15764 exit_group(0)
[Qemu-devel] [PATCH v2] configure: Enable extra compiler warnings
Compiler option -Wextra enables an additional set of compiler warnings.
Some of these warnings were already enabled explicitly in QEMU:
-Wold-style-declaration, -Wtype-limits, -Wignored-qualifiers and
-Wempty-body are now redundant and can be removed.
Others don't work with the current code and must be disabled to
avoid warnings: -Wno-missing-field-initializers, -Wno-override-init,
-Wno-sign-compare and -Wno-unused-parameter.
Signed-off-by: Stefan Weil
---
v2: Removed unintentional change which added -fstack-protector-all
and rebased for latest QEMU.
configure | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/configure b/configure
index 2b83936..ff89d60 100755
--- a/configure
+++ b/configure
@@ -310,7 +310,7 @@ sdl_config="${SDL_CONFIG-${cross_prefix}sdl-config}"
# default flags for all hosts
QEMU_CFLAGS="-fno-strict-aliasing $QEMU_CFLAGS"
-QEMU_CFLAGS="-Wall -Wundef -Wwrite-strings -Wmissing-prototypes $QEMU_CFLAGS"
+QEMU_CFLAGS="-Wall -Wextra -Wundef -Wwrite-strings -Wmissing-prototypes
$QEMU_CFLAGS"
QEMU_CFLAGS="-Wstrict-prototypes -Wredundant-decls $QEMU_CFLAGS"
QEMU_CFLAGS="-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE
$QEMU_CFLAGS"
QEMU_INCLUDES="-I. -I\$(SRC_PATH) -I\$(SRC_PATH)/include"
@@ -1236,12 +1236,16 @@ if test -z "$werror" ; then
fi
fi
-gcc_flags="-Wold-style-declaration -Wold-style-definition -Wtype-limits"
-gcc_flags="-Wformat-security -Wformat-y2k -Winit-self -Wignored-qualifiers
$gcc_flags"
-gcc_flags="-Wmissing-include-dirs -Wempty-body -Wnested-externs $gcc_flags"
+gcc_flags="-Wold-style-definition"
+gcc_flags="-Wformat-security -Wformat-y2k -Winit-self $gcc_flags"
+gcc_flags="-Wmissing-include-dirs -Wnested-externs $gcc_flags"
gcc_flags="-Wendif-labels $gcc_flags"
gcc_flags="-Wno-initializer-overrides $gcc_flags"
+gcc_flags="-Wno-missing-field-initializers $gcc_flags"
+gcc_flags="-Wno-override-init $gcc_flags"
+gcc_flags="-Wno-sign-compare $gcc_flags"
gcc_flags="-Wno-string-plus-int $gcc_flags"
+gcc_flags="-Wno-unused-parameter $gcc_flags"
# Note that we do not add -Werror to gcc_flags here, because that would
# enable it for all configure tests. If a configure test failed due
# to -Werror this would just silently disable some features,
--
1.7.10.4
[Qemu-devel] [PATCH v2 3/5] lsi: ignore write accesses to CTEST0 registers
53C895A datasheet says that this register is read/write, and that the value returned on read access is dependant of DMA FIFO state. However, nothing is said for written value. 53C810A datasheet gives more insight about this register: "This was a general purpose read/write register in previous SYM53C8XX family chips. Although it is still a read/write register, Symbios reserves the right to use these bits for future 53C8XX family enhancements." This prevents going to the default case, which prints an error message. Signed-off-by: Hervé Poussineau --- hw/scsi/lsi53c895a.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 764feaa..a9a9eca 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -1749,6 +1749,9 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val) case 0x17: /* MBOX1 */ s->mbox1 = val; break; +case 0x18: /* CTEST0 */ +/* nothing to do */ +break; case 0x1a: /* CTEST2 */ s->ctest2 = val & LSI_CTEST2_PCICIE; break; -- 1.7.10.4
[Qemu-devel] [PATCH v2 1/5] lsi: use constant name instead of its value
Signed-off-by: Hervé Poussineau --- hw/scsi/lsi53c895a.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c index 0c36842..ca01e86 100644 --- a/hw/scsi/lsi53c895a.c +++ b/hw/scsi/lsi53c895a.c @@ -1521,7 +1521,7 @@ static uint8_t lsi_reg_readb(LSIState *s, int offset) used for diagnostics, so should be ok. */ return 0; case 0xc: /* DSTAT */ -tmp = s->dstat | 0x80; +tmp = s->dstat | LSI_DSTAT_DFE; if ((s->istat0 & LSI_ISTAT0_INTF) == 0) s->dstat = 0; lsi_update_irq(s); @@ -2113,7 +2113,7 @@ static int lsi_scsi_init(PCIDevice *dev) "lsi-io", 256); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_io); -pci_register_bar(dev, 1, 0, &s->mmio_io); +pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio_io); pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->ram_io); QTAILQ_INIT(&s->queue); -- 1.7.10.4
[Qemu-devel] [PATCH v2 5/5] lsi: add 53C810 variant
Currently, treat it exactly as a 53C895A.
53C895A is a 53C810 with more capabilities, so this should work.
However, this lets us test different code paths on Linux, which
don't use lastest features if it detect a 810, or on some OSes
which only support 810 and not 895A (like very old Windows NT
versions).
Signed-off-by: Hervé Poussineau
---
hw/scsi/lsi53c895a.c | 21 +
include/hw/pci/pci_ids.h |1 +
2 files changed, 22 insertions(+)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index 47e4680..1e75e5b 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -7,6 +7,12 @@
* This code is licensed under the LGPL.
*/
+/* Note:
+ * LSI53C810 emulation is incorrect, in the sense that it supports
+ * features added in later evolutions. This should not be a problem,
+ * as well-behaved operating systems will not try to use them.
+ */
+
#include
#include "hw/hw.h"
@@ -275,6 +281,7 @@ typedef struct {
uint32_t script_ram[2048];
} LSIState;
+#define TYPE_LSI53C810 "lsi53c810"
#define TYPE_LSI53C895A "lsi53c895a"
#define LSI53C895A(obj) \
@@ -2152,9 +2159,23 @@ static const TypeInfo lsi_info = {
.class_init= lsi_class_init,
};
+static void lsi53c810_class_init(ObjectClass *klass, void *data)
+{
+PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+k->device_id = PCI_DEVICE_ID_LSI_53C810;
+}
+
+static TypeInfo lsi53c810_info = {
+.name = TYPE_LSI53C810,
+.parent= TYPE_LSI53C895A,
+.class_init= lsi53c810_class_init,
+};
+
static void lsi53c895a_register_types(void)
{
type_register_static(&lsi_info);
+type_register_static(&lsi53c810_info);
}
type_init(lsi53c895a_register_types)
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
index 3ddaf6a..4c0002b 100644
--- a/include/hw/pci/pci_ids.h
+++ b/include/hw/pci/pci_ids.h
@@ -53,6 +53,7 @@
/* Vendors and devices. Sort key: vendor first, device next. */
#define PCI_VENDOR_ID_LSI_LOGIC 0x1000
+#define PCI_DEVICE_ID_LSI_53C810 0x0001
#define PCI_DEVICE_ID_LSI_53C895A0x0012
#define PCI_DEVICE_ID_LSI_SAS10780x0060
--
1.7.10.4
[Qemu-devel] [PATCH v2 4/5] lsi: remove todo
LSI emulation has been tested with Linux on PPC platform.
Signed-off-by: Hervé Poussineau
---
hw/scsi/lsi53c895a.c |3 ---
1 file changed, 3 deletions(-)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index a9a9eca..47e4680 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -7,9 +7,6 @@
* This code is licensed under the LGPL.
*/
-/* ??? Need to check if the {read,write}[wl] routines work properly on
- big-endian targets. */
-
#include
#include "hw/hw.h"
--
1.7.10.4
[Qemu-devel] [PATCH v2 0/5] lsi: small cleanup and add 53C810 variant
Hi, This small patchset fixes a few issues I encountered while trying to add support for the IBM RS/6000 40p. Patches 1 to 4 are small cleanups. Patch 5 may be more controversial, as it adds support for an older (albeit compatible) SCSI adapter, without removing emulation of newer features. Changes since v1: - added patch 4 (lsi emulation has been tested on big-endian guest) - added a comment in patch 5 (remark from Paolo Bonzini) Hervé Poussineau (5): lsi: use constant name instead of its value lsi: check ssid versus sdid only if ssid is valid lsi: ignore write accesses to CTEST0 registers lsi: remove todo lsi: add 53C810 variant hw/scsi/lsi53c895a.c | 32 +++- include/hw/pci/pci_ids.h |1 + 2 files changed, 28 insertions(+), 5 deletions(-) -- 1.7.10.4
[Qemu-devel] [PATCH v2 2/5] lsi: check ssid versus sdid only if ssid is valid
This prevents some (invalid) error messages on console.
Signed-off-by: Hervé Poussineau
---
hw/scsi/lsi53c895a.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index ca01e86..764feaa 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -1705,8 +1705,9 @@ static void lsi_reg_writeb(LSIState *s, int offset,
uint8_t val)
s->sxfer = val;
break;
case 0x06: /* SDID */
-if ((val & 0xf) != (s->ssid & 0xf))
+if ((s->ssid & 0x80) && (val & 0xf) != (s->ssid & 0xf)) {
BADF("Destination ID does not match SSID\n");
+}
s->sdid = val & 0xf;
break;
case 0x07: /* GPREG0 */
--
1.7.10.4
Re: [Qemu-devel] [Qemu-trivial] [PATCH] configure: Enable extra compiler warnings
Am 14.09.2013 14:18, schrieb Michael Tokarev: > 03.09.2013 22:28, Stefan Weil wrote: >> Am 21.08.2013 07:44, schrieb Stefan Weil: >>> Compiler option -Wextra enables an additional set of compiler warnings. >>> >>> Some of these warnings were already enabled explicitly in QEMU: >>> -Wold-style-declaration, -Wtype-limits, -Wignored-qualifiers and >>> -Wempty-body are now redundant and can be removed. >>> >>> Others don't work with the current code and must be disabled to >>> avoid warnings: -Wno-missing-field-initializers, -Wno-override-init, >>> -Wno-sign-compare and -Wno-unused-parameter. >>> >>> Signed-off-by: Stefan Weil >>> --- >>> This is a rather old and long tested patch: I use -Wextra in my >>> QEMU builds for more than a year now. At least one bug was found >>> by using this warning level (see commit >>> b22dd1243f38286263d40496ce5298a8a7d96eea). >>> >>> My tests include Linux and Windows hosts (gcc), but not BSD based >>> hosts, >>> so maybe those hosts might need additional code fixes. >>> clang reports lots of -Wunused-value warnings. > [] >> Ping? I'd appreciate getting this patch committed. >> Is it trivial enough for qemu-trivial? >> >> Stefan >> >> See also http://patchwork.ozlabs.org/patch/268687/ > > Well. I see at least one hidden flag here which is not covered by the > description: > > -gcc_flags="-Wendif-labels $gcc_flags" > +gcc_flags="-fstack-protector-all -Wendif-labels $gcc_flags" > > Is it intentional? No, -fstack-protector-all should not be there. It might be a relict of a previous patch rebase: I added -Wextra in my local branch a long time ago, and -fstack-protector-all was obviously moved to another location in configure during that time. I can send an updated patch later, or you can just remove it from my original patch. > > As for the rest, I think it may go to -trivial just fine. The patch > does not apply to current git, but is easy to fix. > > I'll fire a FreeBSD compile test with it applied. > > Thanks, > > /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] configure: Enable extra compiler warnings
03.09.2013 22:28, Stefan Weil wrote: Am 21.08.2013 07:44, schrieb Stefan Weil: Compiler option -Wextra enables an additional set of compiler warnings. Some of these warnings were already enabled explicitly in QEMU: -Wold-style-declaration, -Wtype-limits, -Wignored-qualifiers and -Wempty-body are now redundant and can be removed. Others don't work with the current code and must be disabled to avoid warnings: -Wno-missing-field-initializers, -Wno-override-init, -Wno-sign-compare and -Wno-unused-parameter. Signed-off-by: Stefan Weil --- This is a rather old and long tested patch: I use -Wextra in my QEMU builds for more than a year now. At least one bug was found by using this warning level (see commit b22dd1243f38286263d40496ce5298a8a7d96eea). My tests include Linux and Windows hosts (gcc), but not BSD based hosts, so maybe those hosts might need additional code fixes. clang reports lots of -Wunused-value warnings. [] Ping? I'd appreciate getting this patch committed. Is it trivial enough for qemu-trivial? Stefan See also http://patchwork.ozlabs.org/patch/268687/ Well. I see at least one hidden flag here which is not covered by the description: -gcc_flags="-Wendif-labels $gcc_flags" +gcc_flags="-fstack-protector-all -Wendif-labels $gcc_flags" Is it intentional? As for the rest, I think it may go to -trivial just fine. The patch does not apply to current git, but is easy to fix. I'll fire a FreeBSD compile test with it applied. Thanks, /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] ivshmem: allow the sharing of hugepages
On 09/14/2013 11:36 AM, Michael Tokarev wrote: > That to say, this is not a _definition_ of a shared memory object, it > is just > a suggested name syntax, suggested purely for portability. In other > words, > there may be other acceptable syntaxes for it. You are right, the definition can be found in shm_open(P), and reads: If name does not begin with the slash character, the effect is implementation-defined. The interpretation of slash characters other than the leading slash character in name is implementation-defined. The "implementation-defined" found in glibc is as follow: The leading '/', if present, is removed. and '/dev/shm/' is prepended to the resulting name before calling open(). (found in sysdeps/posix/shm_open.c around line 57 depending on the version). Note that a workaround in my case is to give a name in the form: /../../path/to/file" ... > So as the result, I'm not sure this approach is valid. Maybe we should > always try shared first and create-new second? I dunno. This is probably a better approach, yes. cf next paragraph. > Note that whole thing - using shared memory object like this - may lead > to surprizes at least, -- users who previously expected one behavour now > see different behavour. Most likely the old behavour wasn't correct. By first trying to open with shm_open, and only when it fails with open, the behavior should stay the same. Because according to glibc implementation, if "folder" exists in /dev/shm, a name like "/folder/shared_mem" should work, but will trigger a false positive with the checks I added. Note that I am not sure anyone uses this syntax, but still, this is a false positive. I'll change that. > At least this should be documented somewhere in user-visible part of > ivshmem, so users will have an ides when objects will be shared and > when truncated. I will add a paragraph in docs/specs/ivshmem_device_spec.txt for that. Thanks for mentioning it. > It is a somewhat minor nitpick, but it'd be not nice to spread such tests > (for NULLness) where the object can't be NULL and to confuse readers. agreed. > Thanks, Thanks for your review, that was helpful. I'll send a reworked patch, probably on Monday. -- Damien Millescamps
Re: [Qemu-devel] [PATCH] tci: Detect function argument alignment
On 14 September 2013 08:18, Stefan Weil wrote: > Am 12.09.2013 22:35, schrieb Peter Maydell: >> You're not a native assembly backend, you can't rely on this >> to be sufficient. Use libffi or call the target function with >> the exact correct prototype. > I had a look on libffi now and don't see how it could solve my problem. > As far as I could see, libffi must be ported to new architectures, so > its use would restrict the portability of TCI. Yes, but it's somebody else's problem to port it, not ours. I present it mostly as an alternative to doing it the hard way. > Calling the helper function with the correct prototype seems to be the > solution with the best portability and would also make TCI a little bit > faster. > There is a drawback of that solution: it needs modifications in the TCG > opcode generation which would no longer be identical to all other TCG > targets (or I'd have to search the given address of the helper function > in a lookup table which would cost too much time). Nobody's running TCI for the performance benefit :-) Use a hash table, there's one in glib and it won't have much overhead at all for lookups. > Therefore I'd like to implement that solution as a configure time option: > either TCI calls helpers with the correct prototype, or it uses the macros > TCG_TARGET_CALL_ALIGN_ARGS and TCG_TARGET_EXTEND_ARGS. > > This means that we still need some way to determine the call alignment > and whether 32 bit arguments are extended to 64 bit values on 64 bit hosts > for the solution with unmodified TCG opcode generator. Any test for this > requires native compilation. Of course I can add the known values for > the common architectures, so these architectures would not require the > test. This is worse -- it means the common cases (where there's probably an ffi port anyhow) won't take the same code paths as the obscure architectures which are the cases where you might care about TCI being portable where QEMU otherwise isn't. -- PMM
Re: [Qemu-devel] [PATCH 4/5] hw: arm_gic: Support setting/getting binary point reg
On 14 September 2013 02:52, Christoffer Dall wrote: > On Fri, Sep 06, 2013 at 03:41:04PM +0100, Peter Maydell wrote: >> The TCG QEMU GIC model is currently adopting the >> "GIC without Security Extensions" model, which implies >> that we should be implementing GIC_ABPR too. What >> model does KVM's in-kernel vGIC use? (ie what state >> does it put into binary_point[0] and [1] on save/load)? >> > We put whatever the guest writes into the GICV_BPR and GICV_ABPR, but > the in-kernel distributor does not care about priorities at all and > considers all interrupts to be group 0 interrupts, which just happens to > work for Linux. > > So yes, we should implement the GIC_ABPR, but there's no need for it > yet. But, if I don't add these fields the guest will (by reading the > GICC_[A]BPR registers) be able to tell it was migrated, but it will not > influence anything on the distributor level. Therefore, by adding these > fields we support the kernel's limited model fully without adding a > bunch of code that we can't really test in real life anyhow, and it > doesn't prevent us from adding full grouping support later on. I agree we should have the fields for KVM's benefit. I think we should also add simple reads-as-written code in the TCG side so they're both accessible. State that the TCG implementation can't access is a bit weird. We should probably also call the fields bpr[NCPU] and abpr[NCPU] or something, so they're a little more self-documenting about what they represent. -- PMM
Re: [Qemu-devel] [Qemu-trivial] [PATCH] tcg-sparc: Fix parenthesis warning
07.09.2013 00:24, Richard Henderson wrote: error: suggest parentheses around comparison in operand of ‘&’ [-Werror=parentheses] Thanks, applied to the trivial-patches queue. Cc'ing the SPARC code maintainer for possible NAK. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] Makefile: Remove some more files when cleaning
Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] ivshmem: allow the sharing of hugepages
12.09.2013 22:23, Damien Millescamps wrote:
According to shm_open specifications:
A shared memory object should be identified by a name of the form /somename;
that is, a null-terminated string of up to NAME_MAX (i.e., 255) characters
consisting of an initial slash, followed by one or more characters, none of
which are slashes.
This patch permits to share memory areas that do not specifically belong to
/dev/shmem.
A use case for this patch is sharing huge pages available through a
hugetlbfs mountpoint.
Signed-off-by: Damien Millescamps
---
hw/misc/ivshmem.c | 16 +++-
1 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 2838866..9020bb2 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -751,9 +751,23 @@ static int pci_ivshmem_init(PCIDevice *dev)
IVSHMEM_DPRINTF("using shm_open (shm object = %s)\n", s->shmobj);
+/*
+ * A shared memory object should be identified by a name of the form
/somename;
+ * that is, a null-terminated string of up to NAME_MAX (i.e., 255)
characters
+ * consisting of an initial slash, followed by one or more characters,
none of
+ * which are slashes.
It'd be nice to give a hint about where this definition comes from.
And once you look at shm_open(3), you'll notice that this paragraph
is prefixed with "For portable use", and reads:
For portable use, a shared memory object should be identified by a name of the
form /somename; that is, a null-terminated string of up to NAME_MAX (i.e.,
255)
characters consisting of an initial slash, followed by one or more characters,
none of which are slashes.
That to say, this is not a _definition_ of a shared memory object, it is just
a suggested name syntax, suggested purely for portability. In other words,
there may be other acceptable syntaxes for it.
So as the result, I'm not sure this approach is valid. Maybe we should
always try shared first and create-new second? I dunno.
Note that whole thing - using shared memory object like this - may lead
to surprizes at least, -- users who previously expected one behavour now
see different behavour. Most likely the old behavour wasn't correct.
At least this should be documented somewhere in user-visible part of
ivshmem, so users will have an ides when objects will be shared and
when truncated.
+ */
+if (s->shmobj && s->shmobj[0] == '/' && strstr(&s->shmobj[1], "/")) {
Here you're testing for s->shmobj, but before, the code were referencing
it directly as an argument for shm_open(). Can it be NULL in this place?
It is a somewhat minor nitpick, but it'd be not nice to spread such tests
(for NULLness) where the object can't be NULL and to confuse readers.
+/* This can't be a shared memory object. */
+fd = open(s->shmobj, O_RDWR);
+if (fd < 0) {
+perror("ivshmem - open");
+exit(-1);
+}
+}
/* try opening with O_EXCL and if it succeeds zero the memory
* by truncating to 0 */
-if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR|O_EXCL,
+else if ((fd = shm_open(s->shmobj, O_CREAT|O_RDWR|O_EXCL,
S_IRWXU|S_IRWXG|S_IRWXO)) > 0) {
/* truncate file to length PCI device's memory */
if (ftruncate(fd, s->ivshmem_size) != 0) {
Thanks,
/mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] trace-events: Clean up with scripts/cleanup-trace-events.pl again
13.09.2013 12:49, arm...@redhat.com пишет: From: Markus Armbruster Event qxl_render_blit_guest_primary_initialized is unused since commit c58c7b9, drop it. Commit 42e5b4c moved hw/ppc/xics.c to hw/intc/xics.c without updating the comment in trace-events. "scripts/cleanup-trace-events.pl trace-events | diff trace-events" is now clean again. Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] *-user: Fix typo in comment (ulocking -> unlocking)
Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] MAINTAINERS: Add missing entry to filelist for TCI target
12.09.2013 22:24, Stefan Weil wrote: tci.c is also a maintained part of the TCI implementation. Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] q35: Fix typo in constant DEFUALT -> DEFAULT.
02.09.2013 17:43, Richard W.M. Jones wrote: From: "Richard W.M. Jones" Signed-off-by: Richard W.M. Jones Thanks, applied to the trivial-patches queue. /mjt
[Qemu-devel] ACPI enabled => qemu process exits when guest shuts down
Hi all, I tried a guest OS that is ACPI capable with enabled ACPI in qemu (+kvm) and qemu quits when the guest OS was shut down (and the "guest PC" should be powered off). Well, from the guest point of view, this behavior seems to be okay, but I would like to keep qemu running to have e.g. a qemu console possibility to restart (power on) the guest again. Is there a possiblity to configure this behavior? Thanks in advance. Best regards, Erik
Re: [Qemu-devel] [Qemu-trivial] PING Re: [PATCH v3] target-i386: Fix segment cache dump
13.09.2013 18:05, Tobias Markus wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 On 08/25/2013 12:20 PM, Tobias Markus wrote: When in Long Mode, cpu_x86_seg_cache() logs "DS16" because the Default operation size bit (D/B bit) is not set for Long Mode Data Segments since there are only Data Segments in Long Mode and no explicit 16/32/64-bit Descriptors. This patch fixes this by checking the Long Mode Active bit of the hidden flags variable and logging "DS" if it is set. (I.e. in Long Mode all Data Segments are logged as "DS") Thanks, applied to the trivial-patches queue. Andreas: if you think it should go to i386 queue instead please just reply to this email saying so, before I'll send a pull request to Anthony. Before a pull request it is really trivial to remove one patch from a queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] *-user: Improve documentation for lock_user function
12.09.2013 21:57, Stefan Weil wrote: Add a missing "function" and replace "and" by "any". BSD und Linux use the same documentation here, so fix both. Thanks, applied to the trivial-patches queue (with the commit comment fixup). /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] tci: Fix qemu-alpha on 32 bit hosts (wrong assertions)
12.09.2013 22:17, Stefan Weil wrote: Debian busybox-static for alpha has a load address of 0x00012000 which is mapped to 0x2000 for 32 bit hosts. qemu-alpha uses the TCG opcodes qemu_ld32, qemu_ld64, qemu_st32 and qemu_st64 which all raise the assertion (taddr == host_addr). Remove all assertions of this type because they are either wrong or unnecessary (when sizeof(tcg_target_ulong) >= sizeof(target_ulong)). Thanks, applied to the trivial-patches queue. I'm not sure why this needs to go there, as you're a maintainer of TCI, but since you sent it especially to -trivial I'm applying it. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] q35: Fix typo in constant DEFUALT -> DEFAULT.
On Sat, Sep 14, 2013 at 12:47:47PM +0400, Michael Tokarev wrote: > 02.09.2013 17:43, Richard W.M. Jones wrote: > >From: "Richard W.M. Jones" > > > >Signed-off-by: Richard W.M. Jones > > Thanks, applied to the trivial-patches queue. Thanks :-) I case you were wondering, the substring "FUA" was hindering my searches for SCSI force-unit-access code ... Rich. -- Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones virt-p2v converts physical machines to virtual machines. Boot with a live CD or over the network (PXE) and turn machines into KVM guests. http://libguestfs.org/virt-v2v
Re: [Qemu-devel] [Qemu-trivial] Ping http://patchwork.ozlabs.org/patch/251410/
12.09.2013 12:51, Stefan Hajnoczi пишет: On Wed, Sep 11, 2013 at 04:08:01PM -0700, Richard Henderson wrote: There have been two patches posted for this uninitialized warning, outstanding since June 14. I still encounter this daily... I'm still happy with the patch. Michael: Do you want to take this through the trivial patches tree? Yes it looks like a trivial patch, but it has at least 2 issues: 1) it does 2 different things in one patch (one for vscclient and one for iov) 2) the subject line is too generic. On the other hand, asking for a V4 for such a trivial thing is a bit too much, in my opinion. So - since by applying to -trivial I'm adding my S-o-b anyway - I'll split it into two patches and fix $subject. Thanks, applied to the trivial-patches queue. /mjt
Re: [Qemu-devel] [Qemu-trivial] [PATCH] translate-all: Fix formatting of dump output
12.09.2013 22:09, Stefan Weil wrote: The page dump writes a table with 3 abi_ulong values in each row. These values take 8 or 16 characters (depending on sizeof abi_ulong). Fix the table headings to be aligned with the table columns. Thanks, applied to the trivial-patches queue. /mjt
