Re: [Qemu-devel] [PATCH 13/25] audio: remove hw->samples, buffer_size_in/out pcm_ops
On Sun, Aug 25, 2019 at 08:46:15PM +0200, Kővágó, Zoltán wrote: > This patch removes the samples member from HWVoiceIn and HWVoiceOut. > Backends can specify buffer size via the newly added buffer_size_in and > buffer_size_out functions in audio_pcm_ops. They are optional, if not > defined qemu will fall back to some built-in constant. > > Signed-off-by: Kővágó, Zoltán > --- > > Notes: > Not sure if this is necessary. At first it seemed like a good idea to > have a function so that backends can compute the size on demand when > needed and things like that, but currently it's just a burden. If none of the backends actually uses this, then drop it. cheers, Gerd
Re: [Qemu-devel] [PATCH 01/25] audio: api for mixeng code free backends
More verbose commit message would be nice here. thanks, Gerd
Re: [Qemu-devel] [PATCH v2 4/4] audio: paaudio: ability to specify stream name
On Mon, Aug 26, 2019 at 09:59:04PM +0200, Kővágó, Zoltán wrote: > This can be used to identify stream in tools like pavucontrol when one > creates multiple -audiodevs or runs multiple qemu instances. Hmm, can we create an useful name automatically, without yet another config option? Useful choices could be the device name (usb-audio, ...) or the device id (whatever -device id=xxx was specified on the command line). cheers, Gerd
Re: [Qemu-devel] [PATCH v2 3/4] audio: paaudio: fix client name
On Mon, Aug 26, 2019 at 09:59:03PM +0200, Kővágó, Zoltán wrote: > pa_context_new expects a client name, not a server socket path. > > Signed-off-by: Kővágó, Zoltán > Reviewed-by: Maxim Levitsky > --- > audio/paaudio.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/audio/paaudio.c b/audio/paaudio.c > index bfef9acaad..777b8e4718 100644 > --- a/audio/paaudio.c > +++ b/audio/paaudio.c > @@ -866,7 +866,7 @@ static void *qpa_conn_init(const char *server) > } > > c->context = pa_context_new(pa_threaded_mainloop_get_api(c->mainloop), > -server); > +"qemu"); qemu_get_vm_name() would be a better default (returns the name set by the user using "qemu -name $whatever", can be NULL if unset). cheers, Gerd
Re: [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers
On 8/26/19 9:36 PM, Stafford Horne wrote: >> /* Fields from here on are preserved across CPU reset. */ >> uint32_t vr; /* Version register */ >> +uint32_t vr2; /* Version register 2 */ >> +uint32_t avr; /* Architecture version register */ > > Do you need to update the serialization in machine.c? I don't think so, because these are invariant for the cpu type. It is not valid to migrate state to a different cpu. The VR, DMMUCFGR, IMMUCFGR entries that you pointed out wrt the previous patch wouldn't need to be in the serialization if they weren't already there. r~
[Qemu-devel] [QEMU-PPC] [PATCH V4] powerpc/spapr: Add host threads parameter to ibm, get_system_parameter
The ibm,get_system_parameter rtas call is used by the guest to retrieve
data relating to certain parameters of the system. The SPLPAR
characteristics option (token 20) is used to determine characteristics of
the environment in which the lpar will run.
It may be useful for a guest to know the number of physical host threads
present on the underlying system where it is being run. Add the
characteristic "HostThrs" to the SPLPAR Characteristics
ibm,get_system_parameter rtas call to expose this information to a
guest. Add a n_host_threads property to the processor class which is
then used to retrieve this information and define it for POWER8 and
POWER9. Other processors will default to 0 and the charateristic won't
be added.
Signed-off-by: Suraj Jitindar Singh
---
V1 -> V2:
- Take into account that the core may be operating in split core mode
meaning a single core may be split into multiple subcores.
V2 -> V3:
- Add curly braces for single line if statements
V3 -> V4;
- Add a host threads property to the processor class and use this to
derive the information rather than the device tree.
---
hw/ppc/spapr_rtas.c | 15 +++
target/ppc/cpu-qom.h| 1 +
target/ppc/translate_init.inc.c | 2 ++
3 files changed, 18 insertions(+)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index 526b489297..bee3835214 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -266,6 +266,7 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
target_ulong args,
uint32_t nret, target_ulong rets)
{
+PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
MachineState *ms = MACHINE(qdev_get_machine());
unsigned int max_cpus = ms->smp.max_cpus;
target_ulong parameter = rtas_ld(args, 0);
@@ -283,6 +284,20 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
current_machine->ram_size / MiB,
ms->smp.cpus,
max_cpus);
+if (pcc->n_host_threads > 0) {
+char *hostthr_val, *old = param_val;
+
+/*
+ * Add HostThrs property. This property is not present in PAPR but
+ * is expected by some guests to communicate the number of physical
+ * host threads per core on the system so that they can scale
+ * information which varies based on the thread configuration.
+ */
+hostthr_val = g_strdup_printf(",HostThrs=%d", pcc->n_host_threads);
+param_val = g_strconcat(param_val, hostthr_val, NULL);
+g_free(hostthr_val);
+g_free(old);
+}
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
g_free(param_val);
break;
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index 7ffdb0a706..e499575dc8 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -191,6 +191,7 @@ typedef struct PowerPCCPUClass {
const PPCHash64Options *hash64_opts;
struct ppc_radix_page_info *radix_page_info;
uint32_t lrg_decr_bits;
+int n_host_threads;
void (*init_proc)(CPUPPCState *env);
int (*check_pow)(CPUPPCState *env);
int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int
mmu_idx);
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 4a21ed7289..41f77b7ef8 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -8770,6 +8770,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->lrg_decr_bits = 32;
+pcc->n_host_threads = 8;
#endif
pcc->excp_model = POWERPC_EXCP_POWER8;
pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
@@ -8981,6 +8982,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
pcc->hash64_opts = _hash64_opts_POWER7;
pcc->radix_page_info = _radix_page_info;
pcc->lrg_decr_bits = 56;
+pcc->n_host_threads = 4;
#endif
pcc->excp_model = POWERPC_EXCP_POWER9;
pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
--
2.13.6
Re: [Qemu-devel] [PATCH 00/13] target/openrisc updates
On Mon, Aug 26, 2019 at 05:07:32PM -0700, Richard Henderson wrote: > The first three fix an MTTCG race on cpu_R[0], now that > we do code generation in parallel. > > Then some updates to the SPRs, cpuid checks for existing > float insns, adding the new v1.3 instructions. > > I've run this through the gcc testsuite as > > make check-gcc \ > RUNTESTFLAGS='--target_board=or1k-qemu/-mhard-float/-mdouble-float > execute.exp' > > === gcc Summary === > > # of expected passes103979 > # of unexpected failures26 > # of expected failures 400 > # of unresolved testcases 1 > # of unsupported tests 2539 > > Of the 26, none are obviously floating-point related. > Hi Richard, Thanks for all of that. I assume you will be taking care of upstreaming this? FYI, I have been working on getting an old [glibc port][0] ready for upstreaming. There still is a lot of testing and cleanup to be done. But so far the work has uncovered 2 bugs in OpenRISC binutils and gcc. I cced you on both of those, did you see them? - binutils (*) : https://sourceware.org/ml/binutils/2019-08/msg00214.html - gcc : https://gcc.gnu.org/ml/gcc-patches/2019-08/msg01549.html * the binutils patch is already pushed upstream. [0] https://github.com/stffrdhrn/or1k-glibc/tree/upstream-rebase Sorry for hijacking this thread. -Stafford
Re: [Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp
On Mon, Aug 26, 2019 at 05:07:44PM -0700, Richard Henderson wrote: > This was added to the 1.3 spec. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3
On Mon, Aug 26, 2019 at 05:07:45PM -0700, Richard Henderson wrote: > Now that the two updates from v3.1 are implemented, > update the "any" cpu to enable it. It should say 1.3 not 3.1 above. > Signed-off-by: Richard Henderson Other than that. Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR
On Mon, Aug 26, 2019 at 05:07:43PM -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons
On Mon, Aug 26, 2019 at 05:07:42PM -0700, Richard Henderson wrote: > These were added to the 1.3 spec. For OF32S, validate AVR. > But OF64A32 is itself new to 1.3 so no extra check needed. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32
On Mon, Aug 26, 2019 at 05:07:41PM -0700, Richard Henderson wrote: > This is hardware support for double-precision floating-point > using pairs of 32-bit registers. Fix a latent bug in the > heretofore unused helper_itofd. Include the bit for cpu "any". > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s
On Mon, Aug 26, 2019 at 05:07:39PM -0700, Richard Henderson wrote:
> The specification of this insn is round-to-zero.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Stafford Horne
> ---
> target/openrisc/fpu_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
> index b9d2ebbb8c..4cc5b297c5 100644
> --- a/target/openrisc/fpu_helper.c
> +++ b/target/openrisc/fpu_helper.c
> @@ -78,7 +78,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
>
> uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
> {
> -return float32_to_int32(val, >fp_status);
> +return float32_to_int32_round_to_zero(val, >fp_status);
> }
>
> #define FLOAT_CALC(name) \
> --
> 2.17.1
>
Re: [Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns
On Mon, Aug 26, 2019 at 05:07:40PM -0700, Richard Henderson wrote: > Make sure the OF32S insns are enabled before allowing execution. > Include the missing bit for cpu "any". > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
[Qemu-devel] [Bug 1841491] Re: floating point emulation can fail to set FE_UNDERFLOW
The float test failure is part of a larger problem for target/powerpc in which all float routines are implemented incorrectly. They are all implemented as double operations with rounding to float as a second step. Which not only produces incorrect exceptions, as in this case, but incorrect numerical results from the double rounding. This should probably be split to a separate bug... ** Changed in: qemu Status: New => Confirmed -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841491 Title: floating point emulation can fail to set FE_UNDERFLOW Status in QEMU: Confirmed Bug description: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841491/+subscriptions
Re: [Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only
On Mon, Aug 26, 2019 at 05:07:36PM -0700, Richard Henderson wrote: > These SPRs are read-only. The writes can simply be ignored, > as we already do for other read-only (or missing) registers. > There is no reason to mask the value in env->vr. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers
On Mon, Aug 26, 2019 at 05:07:38PM -0700, Richard Henderson wrote:
> Update the CPUCFG bits to arch v1.3.
> Include support for AVRP for cpu "any".
>
> Signed-off-by: Richard Henderson
> ---
> target/openrisc/cpu.h| 11 +++
> target/openrisc/cpu.c| 8 ++--
> target/openrisc/sys_helper.c | 6 ++
> 3 files changed, 19 insertions(+), 6 deletions(-)
>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 18d7445e74..71c5959828 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -96,11 +96,12 @@ enum {
> CPUCFGR_OF32S = (1 << 7),
> CPUCFGR_OF64S = (1 << 8),
> CPUCFGR_OV64S = (1 << 9),
> -/* CPUCFGR_ND = (1 << 10), */
> -/* CPUCFGR_AVRP = (1 << 11), */
> +CPUCFGR_ND = (1 << 10),
> +CPUCFGR_AVRP = (1 << 11),
> CPUCFGR_EVBARP = (1 << 12),
> -/* CPUCFGR_ISRP = (1 << 13), */
> -/* CPUCFGR_AECSRP = (1 << 14), */
> +CPUCFGR_ISRP = (1 << 13),
> +CPUCFGR_AECSRP = (1 << 14),
> +CPUCFGR_OF64A32S = (1 << 15),
> };
>
> /* DMMU configure register */
> @@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState {
>
> /* Fields from here on are preserved across CPU reset. */
> uint32_t vr; /* Version register */
> +uint32_t vr2; /* Version register 2 */
> +uint32_t avr; /* Architecture version register */
Do you need to update the serialization in machine.c?
Re: [Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
On Mon, Aug 26, 2019 at 05:07:37PM -0700, Richard Henderson wrote:
> These registers are read-only and implementation specific.
> Initiailize VR for the first time; take the OR1200 values
> from the verilog source.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Stafford Horne
> ---
> target/openrisc/cpu.h| 8
> target/openrisc/cpu.c| 23 ---
> target/openrisc/sys_helper.c | 4 ++--
> 3 files changed, 22 insertions(+), 13 deletions(-)
>
> diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
> index 755282f95d..18d7445e74 100644
> --- a/target/openrisc/cpu.h
> +++ b/target/openrisc/cpu.h
> @@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState {
> target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
> target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
> uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
> -uint32_t vr; /* Version register */
> -uint32_t upr; /* Unit presence register */
> -uint32_t dmmucfgr;/* DMMU configure register */
> -uint32_t immucfgr;/* IMMU configure register */
> uint32_t esr; /* Exception supervisor register */
> uint32_t evbar; /* Exception vector base address register */
> uint32_t pmr; /* Power Management Register */
> @@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState {
> struct {} end_reset_fields;
>
> /* Fields from here on are preserved across CPU reset. */
> +uint32_t vr; /* Version register */
> +uint32_t upr; /* Unit presence register */
> uint32_t cpucfgr; /* CPU configure register */
> +uint32_t dmmucfgr;/* DMMU configure register */
> +uint32_t immucfgr;/* IMMU configure register */
Note for me, others, just moving these doesn't require updating the machine
serialization.
Re: [Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function
On Mon, Aug 26, 2019 at 05:07:34PM -0700, Richard Henderson wrote: > The writes to cpu_R[0] are now a race across threads, now that we > do code generation in parallel. Stage the change by introducing > a function to return the temp for R0. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext
On Mon, Aug 26, 2019 at 05:07:35PM -0700, Richard Henderson wrote: > Finish the race condition fix from the previous patch. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write
On Mon, Aug 26, 2019 at 05:07:33PM -0700, Richard Henderson wrote: > We will need this context in the next patch. > > Signed-off-by: Richard Henderson Reviewed-by: Stafford Horne
Re: [Qemu-devel] [PATCH 1/1] target/ppc: Fix do_float_check_status vs inexact
On Mon, Aug 26, 2019 at 09:54:34AM -0700, Richard Henderson wrote:
> The underflow and inexact exceptions are not mutually exclusive.
> Check for both of them. Tidy the reset of FPSCR[FI].
>
> Fixes: https://bugs.launchpad.net/bugs/1841442
> Reported-by: Paul Clarke
> Signed-off-by: Richard Henderson
Applied to ppc-for-4.2, thanks.
> ---
> target/ppc/fpu_helper.c | 10 +++---
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index 07bc9051b0..2e023c5204 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -630,19 +630,15 @@ static void do_float_check_status(CPUPPCState *env,
> uintptr_t raddr)
> {
> CPUState *cs = env_cpu(env);
> int status = get_float_exception_flags(>fp_status);
> -bool inexact_happened = false;
>
> if (status & float_flag_overflow) {
> float_overflow_excp(env);
> } else if (status & float_flag_underflow) {
> float_underflow_excp(env);
> -} else if (status & float_flag_inexact) {
> -float_inexact_excp(env);
> -inexact_happened = true;
> }
> -
> -/* if the inexact flag was not set */
> -if (inexact_happened == false) {
> +if (status & float_flag_inexact) {
> +float_inexact_excp(env);
> +} else {
> env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
> }
>
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Description: PGP signature
Re: [Qemu-devel] [PATCH] target/ppc: Set float_tininess_before_rounding at cpu reset
On Mon, Aug 26, 2019 at 07:00:13PM -0700, Richard Henderson wrote:
> As defined in Power 3.0 section 4.4.4 "Underflow Exception",
> a tiny result is detected before rounding.
>
> Fixes: https://bugs.launchpad.net/qemu/+bug/1841491
> Reported-by: Paul Clarke
> Signed-off-by: Richard Henderson
Applied to ppc-for-4.2, thanks.
> ---
> target/ppc/translate_init.inc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 4a21ed7289..023138c2f9 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -10461,6 +10461,10 @@ static void ppc_cpu_reset(CPUState *s)
> s->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
>
> +/* tininess for underflow is detected before rounding */
> +set_float_detect_tininess(float_tininess_before_rounding,
> + >fp_status);
> +
> for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
> ppc_spr_t *spr = >spr_cb[i];
>
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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Description: PGP signature
Re: [Qemu-devel] [PATCH] pseries: Fix compat_pvr on reset
On Mon, Aug 26, 2019 at 11:08:12AM +0200, Laurent Vivier wrote:
> If we a migrate P8 machine to a P9 machine, the migration fails on
> destination with:
>
> error while loading state for instance 0x1 of device 'cpu'
> load of migration failed: Operation not permitted
>
> This is caused because the compat_pvr field is only present for the first
> CPU.
> Originally, spapr_machine_reset() calls ppc_set_compat() to set the value
> max_compat_pvr for the first cpu and this was propagated to all CPUs by
> spapr_cpu_reset(). Now, as spapr_cpu_reset() is called before that, the
> value is not propagated to all CPUs and the migration fails.
>
> To fix that, propagate the new value to all CPUs in spapr_machine_reset().
>
> Fixes: 25c9780d38d4 ("spapr: Reset CAS & IRQ subsystem after devices")
> Signed-off-by: Laurent Vivier
Applied to ppc-for-4.2, thanks.
> ---
> hw/ppc/spapr.c | 8 +++-
> hw/ppc/spapr_cpu_core.c | 2 ++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index baedadf20b8c..d063312a3b2a 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1752,7 +1752,13 @@ static void spapr_machine_reset(MachineState *machine)
> spapr_ovec_cleanup(spapr->ov5_cas);
> spapr->ov5_cas = spapr_ovec_new();
>
> -ppc_set_compat(first_ppc_cpu, spapr->max_compat_pvr, _fatal);
> +/*
> + * reset compat_pvr for all CPUs
> + * as qemu_devices_reset() is called before this,
> + * it can't be propagated by spapr_cpu_reset()
> + * from the first CPU to all the others
> + */
> +ppc_set_compat_all(spapr->max_compat_pvr, _fatal);
> }
>
> /*
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
> index bf47fbdf6f7f..45e2f2747ffc 100644
> --- a/hw/ppc/spapr_cpu_core.c
> +++ b/hw/ppc/spapr_cpu_core.c
> @@ -43,6 +43,8 @@ static void spapr_cpu_reset(void *opaque)
>
> /* Set compatibility mode to match the boot CPU, which was either set
> * by the machine reset code or by CAS. This should never fail.
> + * At startup the value is already set for all the CPUs
> + * but we need this when we hotplug a new CPU
> */
> ppc_set_compat(cpu, POWERPC_CPU(first_cpu)->compat_pvr, _abort);
>
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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[Qemu-devel] [Bug 1841491] Re: floating point emulation can fail to set FE_UNDERFLOW
Responding to the patch https://lists.nongnu.org/archive/html/qemu- ppc/2019-08/msg00404.html, it seems to work for "double", but not for "float". Test case attached. ** Attachment added: "float testcase" https://bugs.launchpad.net/qemu/+bug/1841491/+attachment/5284810/+files/test-ffma.c -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841491 Title: floating point emulation can fail to set FE_UNDERFLOW Status in QEMU: New Bug description: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841491/+subscriptions
[Qemu-devel] [Bug 1841491] Re: floating point emulation can fail to set FE_UNDERFLOW
** Attachment added: "2nd file of float testcase" https://bugs.launchpad.net/qemu/+bug/1841491/+attachment/5284821/+files/ffma.c -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841491 Title: floating point emulation can fail to set FE_UNDERFLOW Status in QEMU: New Bug description: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841491/+subscriptions
Re: [Qemu-devel] [PATCH] target/ppc: Set float_tininess_before_rounding at cpu reset
On 8/26/19 9:00 PM, Richard Henderson wrote:
> As defined in Power 3.0 section 4.4.4 "Underflow Exception",
> a tiny result is detected before rounding.
Responded in the bug:
https://bugs.launchpad.net/qemu/+bug/1841491/comments/3
In my testing, this works for "double", but not "float".
> Fixes: https://bugs.launchpad.net/qemu/+bug/1841491
> Reported-by: Paul Clarke
> Signed-off-by: Richard Henderson
> ---
> target/ppc/translate_init.inc.c | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 4a21ed7289..023138c2f9 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -10461,6 +10461,10 @@ static void ppc_cpu_reset(CPUState *s)
> s->exception_index = POWERPC_EXCP_NONE;
> env->error_code = 0;
>
> +/* tininess for underflow is detected before rounding */
> +set_float_detect_tininess(float_tininess_before_rounding,
> + >fp_status);
> +
> for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
> ppc_spr_t *spr = >spr_cb[i];
PC
[Qemu-devel] [PATCH v6 2/3] aspeed: add a GPIO controller to the SoC
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_soc.c | 17 +
2 files changed, 20 insertions(+)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index cef605ad6b..fa04abddd8 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -22,6 +22,7 @@
#include "hw/ssi/aspeed_smc.h"
#include "hw/watchdog/wdt_aspeed.h"
#include "hw/net/ftgmac100.h"
+#include "hw/gpio/aspeed_gpio.h"
#define ASPEED_SPIS_NUM 2
#define ASPEED_WDTS_NUM 3
@@ -47,6 +48,7 @@ typedef struct AspeedSoCState {
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
+AspeedGPIOState gpio;
} AspeedSoCState;
#define TYPE_ASPEED_SOC "aspeed-soc"
@@ -60,6 +62,7 @@ typedef struct AspeedSoCInfo {
int spis_num;
const char *fmc_typename;
const char **spi_typename;
+const char *gpio_typename;
int wdts_num;
const int *irqmap;
const hwaddr *memmap;
diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c
index c6fb3700f2..ff422c8ad1 100644
--- a/hw/arm/aspeed_soc.c
+++ b/hw/arm/aspeed_soc.c
@@ -124,6 +124,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spis_num = 1,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+.gpio_typename = "aspeed.gpio-ast2400",
.wdts_num = 2,
.irqmap = aspeed_soc_ast2400_irqmap,
.memmap = aspeed_soc_ast2400_memmap,
@@ -136,6 +137,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spis_num = 1,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+.gpio_typename = "aspeed.gpio-ast2400",
.wdts_num = 2,
.irqmap = aspeed_soc_ast2400_irqmap,
.memmap = aspeed_soc_ast2400_memmap,
@@ -148,6 +150,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spis_num = 1,
.fmc_typename = "aspeed.smc.fmc",
.spi_typename = aspeed_soc_ast2400_typenames,
+.gpio_typename = "aspeed.gpio-ast2400",
.wdts_num = 2,
.irqmap = aspeed_soc_ast2400_irqmap,
.memmap = aspeed_soc_ast2400_memmap,
@@ -160,6 +163,7 @@ static const AspeedSoCInfo aspeed_socs[] = {
.spis_num = 2,
.fmc_typename = "aspeed.smc.ast2500-fmc",
.spi_typename = aspeed_soc_ast2500_typenames,
+.gpio_typename = "aspeed.gpio-ast2500",
.wdts_num = 3,
.irqmap = aspeed_soc_ast2500_irqmap,
.memmap = aspeed_soc_ast2500_memmap,
@@ -246,6 +250,9 @@ static void aspeed_soc_init(Object *obj)
sysbus_init_child_obj(obj, "xdma", OBJECT(>xdma), sizeof(s->xdma),
TYPE_ASPEED_XDMA);
+
+sysbus_init_child_obj(obj, "gpio", OBJECT(>gpio), sizeof(s->gpio),
+ sc->info->gpio_typename);
}
static void aspeed_soc_realize(DeviceState *dev, Error **errp)
@@ -425,6 +432,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error
**errp)
sc->info->memmap[ASPEED_XDMA]);
sysbus_connect_irq(SYS_BUS_DEVICE(>xdma), 0,
aspeed_soc_get_irq(s, ASPEED_XDMA));
+
+/* GPIO */
+object_property_set_bool(OBJECT(>gpio), true, "realized", );
+if (err) {
+error_propagate(errp, err);
+return;
+}
+sysbus_mmio_map(SYS_BUS_DEVICE(>gpio), 0,
sc->info->memmap[ASPEED_GPIO]);
+sysbus_connect_irq(SYS_BUS_DEVICE(>gpio), 0,
+ aspeed_soc_get_irq(s, ASPEED_GPIO));
}
static Property aspeed_soc_properties[] = {
DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0),
--
2.20.1
[Qemu-devel] [PATCH v6 1/3] hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500
GPIO pins are arranged in groups of 8 pins labeled A,B,..,Y,Z,AA,AB,AC.
(Note that the ast2400 controller only goes up to group AB).
A set has four groups (except set AC which only has one) and is
referred to by the groups it is composed of (eg ABCD,EFGH,...,YZAAAB).
Each set is accessed and controlled by a bank of 14 registers.
These registers operate on a per pin level where each bit in the register
corresponds to a pin, except for the command source registers. The command
source registers operate on a per group level where bits 24, 16, 8 and 0
correspond to each group in the set.
eg. registers for set ABCD:
|D7...D0|C7...C0|B7...B0|A7...A0| <- GPIOs
|31...24|23...16|158|7.0| <- bit position
Note that there are a couple of groups that only have 4 pins.
There are two ways that this model deviates from the behaviour of the
actual controller:
(1) The only control source driving the GPIO pins in the model is the ARM
model (as there currently aren't models for the LPC or Coprocessor).
(2) None of the registers in the model are reset tolerant (needs
integration with the watchdog).
Signed-off-by: Rashmica Gupta
Tested-by: Andrew Jeffery
Reviewed-by: Cédric Le Goater
---
include/hw/gpio/aspeed_gpio.h | 100
hw/gpio/aspeed_gpio.c | 882 ++
hw/gpio/Makefile.objs | 1 +
3 files changed, 983 insertions(+)
create mode 100644 include/hw/gpio/aspeed_gpio.h
create mode 100644 hw/gpio/aspeed_gpio.c
diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h
new file mode 100644
index 00..a2deac046a
--- /dev/null
+++ b/include/hw/gpio/aspeed_gpio.h
@@ -0,0 +1,100 @@
+/*
+ * ASPEED GPIO Controller
+ *
+ * Copyright (C) 2017-2018 IBM Corp.
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#ifndef ASPEED_GPIO_H
+#define ASPEED_GPIO_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ASPEED_GPIO "aspeed.gpio"
+#define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO)
+#define ASPEED_GPIO_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO)
+#define ASPEED_GPIO_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO)
+
+#define ASPEED_GPIO_MAX_NR_SETS 8
+#define ASPEED_REGS_PER_BANK 14
+#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK *
ASPEED_GPIO_MAX_NR_SETS)
+#define ASPEED_GPIO_NR_PINS 228
+#define ASPEED_GROUPS_PER_SET 4
+#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3
+#define ASPEED_CHARS_PER_GROUP_LABEL 4
+
+typedef struct GPIOSets GPIOSets;
+
+typedef struct GPIOSetProperties {
+uint32_t input;
+uint32_t output;
+char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL];
+} GPIOSetProperties;
+
+enum GPIORegType {
+gpio_not_a_reg,
+gpio_reg_data_value,
+gpio_reg_direction,
+gpio_reg_int_enable,
+gpio_reg_int_sens_0,
+gpio_reg_int_sens_1,
+gpio_reg_int_sens_2,
+gpio_reg_int_status,
+gpio_reg_reset_tolerant,
+gpio_reg_debounce_1,
+gpio_reg_debounce_2,
+gpio_reg_cmd_source_0,
+gpio_reg_cmd_source_1,
+gpio_reg_data_read,
+gpio_reg_input_mask,
+};
+
+typedef struct AspeedGPIOReg {
+uint16_t set_idx;
+enum GPIORegType type;
+ } AspeedGPIOReg;
+
+typedef struct AspeedGPIOClass {
+SysBusDevice parent_obj;
+const GPIOSetProperties *props;
+uint32_t nr_gpio_pins;
+uint32_t nr_gpio_sets;
+uint32_t gap;
+const AspeedGPIOReg *reg_table;
+} AspeedGPIOClass;
+
+typedef struct AspeedGPIOState {
+/* */
+SysBusDevice parent;
+
+/*< public >*/
+MemoryRegion iomem;
+int pending;
+qemu_irq irq;
+qemu_irq gpios[ASPEED_GPIO_NR_PINS];
+
+/* Parallel GPIO Registers */
+uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS];
+struct GPIOSets {
+uint32_t data_value; /* Reflects pin values */
+uint32_t data_read; /* Contains last value written to data value */
+uint32_t direction;
+uint32_t int_enable;
+uint32_t int_sens_0;
+uint32_t int_sens_1;
+uint32_t int_sens_2;
+uint32_t int_status;
+uint32_t reset_tol;
+uint32_t cmd_source_0;
+uint32_t cmd_source_1;
+uint32_t debounce_1;
+uint32_t debounce_2;
+uint32_t input_mask;
+} sets[ASPEED_GPIO_MAX_NR_SETS];
+} AspeedGPIOState;
+
+#endif /* _ASPEED_GPIO_H_ */
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
new file mode 100644
index 00..d9e92f0a67
--- /dev/null
+++ b/hw/gpio/aspeed_gpio.c
@@ -0,0 +1,882 @@
+/*
+ * ASPEED GPIO Controller
+ *
+ * Copyright (C) 2017-2019 IBM Corp.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+#include "qemu/log.h"
+#include "hw/gpio/aspeed_gpio.h"
+#include "include/hw/misc/aspeed_scu.h"
+#include "qapi/error.h"
+#include "qapi/visitor.h"
+
+#define GPIOS_PER_REG
[Qemu-devel] [PATCH v6 3/3] hw/gpio: Add in AST2600 specific implementation
The AST2600 has the same sets of 3.6v gpios as the AST2400 plus an
addtional two sets of 1.8V gpios.
Signed-off-by: Rashmica Gupta
Reviewed-by: Cédric Le Goater
---
hw/gpio/aspeed_gpio.c | 142 --
1 file changed, 137 insertions(+), 5 deletions(-)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index d9e92f0a67..dd21065d4e 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -167,6 +167,48 @@
#define GPIO_3_6V_MEM_SIZE 0x1F0
#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2)
+/* AST2600 only - 1.8V gpios */
+/*
+ * The AST2600 has same 3.6V gpios as the AST2400 (memory offsets 0x0-0x198)
+ * and addtional 1.8V gpios (memory offsets 0x800-0x9D4).
+ */
+#define GPIO_1_8V_REG_OFFSET 0x800
+#define GPIO_1_8V_ABCD_DATA_VALUE ((0x800 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DIRECTION ((0x804 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_ENABLE ((0x808 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_0 ((0x80C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_1 ((0x810 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_SENS_2 ((0x814 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INT_STATUS ((0x818 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_RESET_TOLERANT ((0x81C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DATA_VALUE((0x820 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DIRECTION ((0x824 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_ENABLE((0x828 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_0((0x82C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_1((0x830 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_SENS_2((0x834 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INT_STATUS((0x838 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_RESET_TOLERANT((0x83C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_1 ((0x840 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DEBOUNCE_2 ((0x844 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_1((0x848 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DEBOUNCE_2((0x84C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_1 ((0x850 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_2 ((0x854 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_DEBOUNCE_TIME_3 ((0x858 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_0 ((0x860 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_COMMAND_SRC_1 ((0x864 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_0 ((0x868 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_COMMAND_SRC_1 ((0x86C - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_DATA_READ ((0x8C0 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_DATA_READ ((0x8C4 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_ABCD_INPUT_MASK ((0x9D0 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_E_INPUT_MASK((0x9D4 - GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_1_8V_MEM_SIZE0x9D8
+#define GPIO_1_8V_REG_ARRAY_SIZE ((GPIO_1_8V_MEM_SIZE - \
+ GPIO_1_8V_REG_OFFSET) >> 2)
+#define GPIO_MAX_MEM_SIZE MAX(GPIO_3_6V_MEM_SIZE, GPIO_1_8V_MEM_SIZE)
+
static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio)
{
uint32_t falling_edge = 0, rising_edge = 0;
@@ -463,6 +505,39 @@ static const AspeedGPIOReg
aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = {
[GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask },
};
+static const AspeedGPIOReg aspeed_1_8v_gpios[GPIO_1_8V_REG_ARRAY_SIZE] = {
+/* 1.8V Set ABCD */
+[GPIO_1_8V_ABCD_DATA_VALUE] = {0, gpio_reg_data_value},
+[GPIO_1_8V_ABCD_DIRECTION] = {0, gpio_reg_direction},
+[GPIO_1_8V_ABCD_INT_ENABLE] = {0, gpio_reg_int_enable},
+[GPIO_1_8V_ABCD_INT_SENS_0] = {0, gpio_reg_int_sens_0},
+[GPIO_1_8V_ABCD_INT_SENS_1] = {0, gpio_reg_int_sens_1},
+[GPIO_1_8V_ABCD_INT_SENS_2] = {0, gpio_reg_int_sens_2},
+[GPIO_1_8V_ABCD_INT_STATUS] = {0, gpio_reg_int_status},
+[GPIO_1_8V_ABCD_RESET_TOLERANT] = {0, gpio_reg_reset_tolerant},
+[GPIO_1_8V_ABCD_DEBOUNCE_1] = {0, gpio_reg_debounce_1},
+[GPIO_1_8V_ABCD_DEBOUNCE_2] = {0, gpio_reg_debounce_2},
+[GPIO_1_8V_ABCD_COMMAND_SRC_0] = {0, gpio_reg_cmd_source_0},
+[GPIO_1_8V_ABCD_COMMAND_SRC_1] = {0, gpio_reg_cmd_source_1},
+[GPIO_1_8V_ABCD_DATA_READ] = {0, gpio_reg_data_read},
+[GPIO_1_8V_ABCD_INPUT_MASK] = {0, gpio_reg_input_mask},
+/* 1.8V Set E */
+[GPIO_1_8V_E_DATA_VALUE] = {1, gpio_reg_data_value},
+[GPIO_1_8V_E_DIRECTION] = {1, gpio_reg_direction},
+[GPIO_1_8V_E_INT_ENABLE] = {1, gpio_reg_int_enable},
+[GPIO_1_8V_E_INT_SENS_0] =
[Qemu-devel] [PATCH v6 0/3] Add Aspeed GPIO controller model
v6: - fixed bug in get/set pin - added error checking that Cédric suggested v5: - integrated AspeedGPIOController fields into AspeedGPIOClass - separated ast2600_3_6v and ast2600_1_8v into two classes v4: - proper interupt handling thanks to Andrew - switch statements for reading and writing suggested by Peter - some small cleanups suggested by Alexey v3: - didn't have each gpio set up as an irq - now can't access set AC on ast2400 (only exists on ast2500) - added ast2600 implementation (patch 3) - renamed a couple of variables for clarity v2: Addressed Andrew's feedback, added debounce regs, renamed get/set to read/write to minimise confusion with a 'set' of registers. Rashmica Gupta (3): hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 aspeed: add a GPIO controller to the SoC hw/gpio: Add in AST2600 specific implementation include/hw/arm/aspeed_soc.h |3 + include/hw/gpio/aspeed_gpio.h | 100 hw/arm/aspeed_soc.c | 17 + hw/gpio/aspeed_gpio.c | 1014 + hw/gpio/Makefile.objs |1 + 5 files changed, 1135 insertions(+) create mode 100644 include/hw/gpio/aspeed_gpio.h create mode 100644 hw/gpio/aspeed_gpio.c -- 2.20.1
Re: [Qemu-devel] [Virtio-fs] [PATCH v2 1/2] virtio: add vhost-user-fs base device
On 2019/8/24 1:56, Dr. David Alan Gilbert (git) wrote:
> From: "Dr. David Alan Gilbert"
>
> The virtio-fs virtio device provides shared file system access using
> the FUSE protocol carried ovew virtio.
typo? ovew->over
> The actual file server is implemented in an external vhost-user-fs device
> backend process.
>
> Signed-off-by: Stefan Hajnoczi
> Signed-off-by: Sebastien Boeuf
> Signed-off-by: Dr. David Alan Gilbert
> ---
> configure | 13 +
> hw/virtio/Makefile.objs | 1 +
> hw/virtio/vhost-user-fs.c | 297
> include/hw/virtio/vhost-user-fs.h | 45 +++
> include/standard-headers/linux/virtio_fs.h | 41 +++
> include/standard-headers/linux/virtio_ids.h | 1 +
> 6 files changed, 398 insertions(+)
> create mode 100644 hw/virtio/vhost-user-fs.c
> create mode 100644 include/hw/virtio/vhost-user-fs.h
> create mode 100644 include/standard-headers/linux/virtio_fs.h
>
> diff --git a/configure b/configure
> index 0173db5d9f..d77996dd24 100755
> --- a/configure
> +++ b/configure
> @@ -382,6 +382,7 @@ vhost_crypto=""
> vhost_scsi=""
> vhost_vsock=""
> vhost_user=""
> +vhost_user_fs=""
> kvm="no"
> hax="no"
> hvf="no"
> @@ -1316,6 +1317,10 @@ for opt do
>;;
>--enable-vhost-vsock) vhost_vsock="yes"
>;;
> + --disable-vhost-user-fs) vhost_user_fs="no"
> + ;;
> + --enable-vhost-user-fs) vhost_user_fs="yes"
> + ;;
>--disable-opengl) opengl="no"
>;;
>--enable-opengl) opengl="yes"
> @@ -2269,6 +2274,10 @@ test "$vhost_crypto" = "" && vhost_crypto=$vhost_user
> if test "$vhost_crypto" = "yes" && test "$vhost_user" = "no"; then
>error_exit "--enable-vhost-crypto requires --enable-vhost-user"
> fi
> +test "$vhost_user_fs" = "" && vhost_user_fs=$vhost_user
> +if test "$vhost_user_fs" = "yes" && test "$vhost_user" = "no"; then
> + error_exit "--enable-vhost-user-fs requires --enable-vhost-user"
> +fi
>
> # OR the vhost-kernel and vhost-user values for simplicity
> if test "$vhost_net" = ""; then
> @@ -6422,6 +6431,7 @@ echo "vhost-crypto support $vhost_crypto"
> echo "vhost-scsi support $vhost_scsi"
> echo "vhost-vsock support $vhost_vsock"
> echo "vhost-user support $vhost_user"
> +echo "vhost-user-fs support $vhost_user_fs"
> echo "Trace backends$trace_backends"
> if have_backend "simple"; then
> echo "Trace output file $trace_file-"
> @@ -6918,6 +6928,9 @@ fi
> if test "$vhost_user" = "yes" ; then
>echo "CONFIG_VHOST_USER=y" >> $config_host_mak
> fi
> +if test "$vhost_user_fs" = "yes" ; then
> + echo "CONFIG_VHOST_USER_FS=y" >> $config_host_mak
> +fi
> if test "$blobs" = "yes" ; then
>echo "INSTALL_BLOBS=yes" >> $config_host_mak
> fi
> diff --git a/hw/virtio/Makefile.objs b/hw/virtio/Makefile.objs
> index 964ce78607..47ffbf22c4 100644
> --- a/hw/virtio/Makefile.objs
> +++ b/hw/virtio/Makefile.objs
> @@ -11,6 +11,7 @@ common-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
> common-obj-$(CONFIG_VIRTIO_MMIO) += virtio-mmio.o
> obj-$(CONFIG_VIRTIO_BALLOON) += virtio-balloon.o
> obj-$(CONFIG_VIRTIO_CRYPTO) += virtio-crypto.o
> +obj-$(CONFIG_VHOST_USER_FS) += vhost-user-fs.o
> obj-$(call land,$(CONFIG_VIRTIO_CRYPTO),$(CONFIG_VIRTIO_PCI)) +=
> virtio-crypto-pci.o
> obj-$(CONFIG_VIRTIO_PMEM) += virtio-pmem.o
> common-obj-$(call land,$(CONFIG_VIRTIO_PMEM),$(CONFIG_VIRTIO_PCI)) +=
> virtio-pmem-pci.o
> diff --git a/hw/virtio/vhost-user-fs.c b/hw/virtio/vhost-user-fs.c
> new file mode 100644
> index 00..72e270d869
> --- /dev/null
> +++ b/hw/virtio/vhost-user-fs.c
> @@ -0,0 +1,297 @@
> +/*
> + * Vhost-user filesystem virtio device
> + *
> + * Copyright 2018 Red Hat, Inc.
> + *
> + * Authors:
> + * Stefan Hajnoczi
> + *
> + * This work is licensed under the terms of the GNU GPL, version 2 or
> + * (at your option) any later version. See the COPYING file in the
> + * top-level directory.
> + */
> +
> +#include "qemu/osdep.h"
> +#include
> +#include "standard-headers/linux/virtio_fs.h"
> +#include "qapi/error.h"
> +#include "hw/qdev-properties.h"
> +#include "hw/virtio/virtio-bus.h"
> +#include "hw/virtio/virtio-access.h"
> +#include "qemu/error-report.h"
> +#include "hw/virtio/vhost-user-fs.h"
> +#include "monitor/monitor.h"
> +
> +static void vuf_get_config(VirtIODevice *vdev, uint8_t *config)
> +{
> +VHostUserFS *fs = VHOST_USER_FS(vdev);
> +struct virtio_fs_config fscfg = {};
> +
> +memcpy((char *)fscfg.tag, fs->conf.tag,
> + MIN(strlen(fs->conf.tag) + 1, sizeof(fscfg.tag)));
> +
> +virtio_stl_p(vdev, _request_queues,
> fs->conf.num_request_queues);
> +
> +memcpy(config, , sizeof(fscfg));
> +}
> +
> +static void vuf_start(VirtIODevice *vdev)
> +{
> +VHostUserFS *fs = VHOST_USER_FS(vdev);
> +BusState *qbus = BUS(qdev_get_parent_bus(DEVICE(vdev)));
> +VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus);
> +int ret;
> +int i;
> +
> +if (!k->set_guest_notifiers) {
> +
[Qemu-devel] [PATCH] target/ppc: Set float_tininess_before_rounding at cpu reset
As defined in Power 3.0 section 4.4.4 "Underflow Exception",
a tiny result is detected before rounding.
Fixes: https://bugs.launchpad.net/qemu/+bug/1841491
Reported-by: Paul Clarke
Signed-off-by: Richard Henderson
---
target/ppc/translate_init.inc.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 4a21ed7289..023138c2f9 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -10461,6 +10461,10 @@ static void ppc_cpu_reset(CPUState *s)
s->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
+/* tininess for underflow is detected before rounding */
+set_float_detect_tininess(float_tininess_before_rounding,
+ >fp_status);
+
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
ppc_spr_t *spr = >spr_cb[i];
--
2.17.1
Re: [Qemu-devel] [PATCH qemu] spapr: Render full FDT on ibm, client-architecture-support
On 26/08/2019 17:44, David Gibson wrote: On Mon, Aug 26, 2019 at 02:31:26PM +1000, Alexey Kardashevskiy wrote: The ibm,client-architecture-support call is a way for the guest to negotiate capabilities with a hypervisor. It is implemented as: - the guest calls SLOF via client interface; - SLOF calls QEMU (H_CAS hypercall) with an options vector from the guest; - QEMU returns a device tree diff (which uses FDT format with an additional header before it); - SLOF walks through the partial diff tree and updates its internal tree with the values from the diff. This changes QEMU to simply re-render the entire tree and send it as an update. SLOF can handle this already mostly, [1] is needed before this can be applied. The benefit is reduced code size as there is no need for another set of DT rendering helpers such as spapr_fixup_cpu_dt(). The downside is that the updates are bigger now (as they include all nodes and properties) but the difference on a '-smp 256,threads=1' system before/after is 2.35s vs. 2.5s. While at this, add a missing g_free(fdt) if the resulting tree is bigger than the space allocated by SLOF. Also, store the resulting tree in the spapr machine to have the latest valid FDT copy possible (this should not matter much as H_UPDATE_DT happens right after that but nevertheless). [1] https://patchwork.ozlabs.org/patch/1152915/ Signed-off-by: Alexey Kardashevskiy Reviewed-by: David Gibson Can you wrap that up with the SLOF update in a pull request for me? Yup, I'll just wait a little bit more for replies about the RTAS log extension patch. Cheers, -- Alexey
Re: [Qemu-devel] [PATCH v4 0/3] Add Aspeed GPIO controller model
On Fri, 2019-08-16 at 18:21 +0200, Cédric Le Goater wrote: > On 16/08/2019 09:32, Rashmica Gupta wrote: > > v5: > > - integrated AspeedGPIOController fields into AspeedGPIOClass > > - separated ast2600_3_6v and ast2600_1_8v into two classes > > Rashmica, > > This looks much nicer ! > > Please take a look at branch aspeed-4.2 in which I have merged your > v5 and modified slightly the ast2600 part. > > > https://github.com/legoater/qemu/commit/02b3df3f1a380eec4df7c49e88fa7ba27f75a610 > > I introduced a gpio_1_8v controller with its specific MMIO and IRQ > definitions. Tell me what you think of it. The principal motivation > behind these adjustments is that I don't know yet how we are going > to instantiate/realize the specific models of the AST2600 SoC. the > GPIO 1.8v is one of these extra controllers. This looks like a much better way to do this! > > Thanks, > > C. > > > v4: > > - proper interupt handling thanks to Andrew > > - switch statements for reading and writing suggested by Peter > > - some small cleanups suggested by Alexey > > > > v3: > > - didn't have each gpio set up as an irq > > - now can't access set AC on ast2400 (only exists on ast2500) > > - added ast2600 implementation (patch 3) > > - renamed a couple of variables for clarity > > > > v2: Addressed Andrew's feedback, added debounce regs, renamed > > get/set to > > read/write to minimise confusion with a 'set' of registers. > > > > Rashmica Gupta (3): > > hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500 > > aspeed: add a GPIO controller to the SoC > > hw/gpio: Add in AST2600 specific implementation > > > > include/hw/arm/aspeed_soc.h |3 + > > include/hw/gpio/aspeed_gpio.h | 100 > > hw/arm/aspeed_soc.c | 17 + > > hw/gpio/aspeed_gpio.c | 1006 > > + > > hw/gpio/Makefile.objs |1 + > > 5 files changed, 1127 insertions(+) > > create mode 100644 include/hw/gpio/aspeed_gpio.h > > create mode 100644 hw/gpio/aspeed_gpio.c > >
Re: [Qemu-devel] [POC Seabios PATCH] seabios: use isolated SMM address space for relocation
On 8/26/19 9:57 AM, Igor Mammedov wrote: > >> I most likely don't understand how this is supposed to work but aren't >> we here successfully reading SMRAM from non-SMM context, something we >> are not supposed to be able to do? > We are aren't reading SMRAM at 0x3 base directly, > "RAM" marked log lines are non-SMM context reads using as base > BUILD_SMM_INIT_ADDR 0x3 > and as you see, it isn't showing anything from SMRAM > > For mgmt/demo purposes SMRAM (which is at 0x3 in SMM address space) > is also aliased at > BUILD_SMM_ADDR0xa > into non-SMM address space to allow us to initialize SMM entry point > (log entries are marked as "SMRAM"). OK, I then misunderstood the purpose of this demo. I thought you were not supposed to be able to read it from either location in non-SMM mode. Thanks for the explanation. -boris > > Aliased SMRAM also allows us to check that relocation worked > (i.e. smm_base was relocated from default "handle_smi cmd=0 smbase=0x0003" > to a new one "smm_relocate: SMRAM cpu.i64.smm_base a"). > > > It's similar to what we do with TSEG where QEMU steals RAM from > normal address space and puts MMIO region 'tseg_blackhole' over it > so non-SMM context reads 0xFF from TSEG window, while SMM context > accesses RAM hidden below tseg_blackhole. > > These patches show that we can have normal usable RAM at 0x3 > which doesn't overlap with SMRAM at the same address and each can > be made accessible only from its own mode (no-SMM and SMM). > Preventing non-SMM mode from injecting attack on SMRAM via CPU > that hasn't been initialized yet once firmware locked down SMRAM. > > >> >> -boris >>
[Qemu-devel] [Bug 1841491] Re: floating point emulation can fail to set FE_UNDERFLOW
** Attachment added: "2nd file of testcase" https://bugs.launchpad.net/qemu/+bug/1841491/+attachment/5284809/+files/fma.c -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841491 Title: floating point emulation can fail to set FE_UNDERFLOW Status in QEMU: New Bug description: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841491/+subscriptions
[Qemu-devel] [Bug 1841491] [NEW] floating point emulation can fail to set FE_UNDERFLOW
Public bug reported: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. ** Affects: qemu Importance: Undecided Status: New ** Attachment added: "testcase reporting exceptions set by simple floating point multiply-add" https://bugs.launchpad.net/bugs/1841491/+attachment/5284808/+files/test-fma.c -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1841491 Title: floating point emulation can fail to set FE_UNDERFLOW Status in QEMU: New Bug description: Floating point emulation can fail to set FE_UNDERFLOW in some circumstances. This shows up often in glibc's "math" tests. A similar test is attached. This is similar to bug #1841442, but not the same problem, and I don't think the fix will be in the same code. On ppc64le native: -- $ gcc -c -O2 fma.c $ gcc -O2 test-fma.c fma.o -lm -o test-fma $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0xa00 FE_INEXACT FE_UNDERFLOW 0x1p-1022 -- On qemu-system-ppc64: -- $ ./test-fma $(./test-fma) fma(0x1.cp-1022, 0x1.1p-1, 0x0.1p-1022) 0x0 0x200 FE_INEXACT 0x1p-1022 -- QEMU versions vary, but not too much, and are pretty close to git HEAD: - 586f3dced9 (HEAD -> master, origin/master, origin/HEAD) Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190822' into staging - 864ab31 Update version for v4.1.0-rc4 release There are worse symptoms on qemu-x86_64, but this is apparently not surprising per https://bugs.launchpad.net/qemu/+bug/1841442/comments/6. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1841491/+subscriptions
[Qemu-devel] [PATCH v3 1/2] block: posix: Always allocate the first block
When creating an image with preallocation "off" or "falloc", the first
block of the image is typically not allocated. When using Gluster
storage backed by XFS filesystem, reading this block using direct I/O
succeeds regardless of request length, fooling alignment detection.
In this case we fallback to a safe value (4096) instead of the optimal
value (512), which may lead to unneeded data copying when aligning
requests. Allocating the first block avoids the fallback.
Since we allocate the first block even with preallocation=off, we no
longer create images with zero disk size:
$ ./qemu-img create -f raw test.raw 1g
Formatting 'test.raw', fmt=raw size=1073741824
$ ls -lhs test.raw
4.0K -rw-r--r--. 1 nsoffer nsoffer 1.0G Aug 16 23:48 test.raw
And converting the image requires additional cluster:
$ ./qemu-img measure -f raw -O qcow2 test.raw
required size: 458752
fully allocated size: 1074135040
When using format like vmdk with multiple files per image, we allocate
one block per file:
$ ./qemu-img create -f vmdk -o subformat=twoGbMaxExtentFlat test.vmdk 4g
Formatting 'test.vmdk', fmt=vmdk size=4294967296 compat6=off
hwversion=undefined subformat=twoGbMaxExtentFlat
$ ls -lhs test*.vmdk
4.0K -rw-r--r--. 1 nsoffer nsoffer 2.0G Aug 27 03:23 test-f001.vmdk
4.0K -rw-r--r--. 1 nsoffer nsoffer 2.0G Aug 27 03:23 test-f002.vmdk
4.0K -rw-r--r--. 1 nsoffer nsoffer 353 Aug 27 03:23 test.vmdk
I did quick performance test for copying disks with qemu-img convert to
new raw target image to Gluster storage with sector size of 512 bytes:
for i in $(seq 10); do
rm -f dst.raw
sleep 10
time ./qemu-img convert -f raw -O raw -t none -T none src.raw dst.raw
done
Here is a table comparing the total time spent:
TypeBefore(s) After(s)Diff(%)
---
real 530.028469.123 -11.4
user 17.204 10.768 -37.4
sys17.881 7.011 -60.7
We can see very clear improvement in CPU usage.
Signed-off-by: Nir Soffer
---
block/file-posix.c| 51 +++
tests/qemu-iotests/059.out| 2 +-
tests/qemu-iotests/{150.out => 150.out.qcow2} | 0
tests/qemu-iotests/150.out.raw| 12 +
tests/qemu-iotests/175| 19 ---
tests/qemu-iotests/175.out| 8 +--
tests/qemu-iotests/178.out.qcow2 | 4 +-
tests/qemu-iotests/221.out| 12 +++--
tests/qemu-iotests/253.out| 12 +++--
9 files changed, 99 insertions(+), 21 deletions(-)
rename tests/qemu-iotests/{150.out => 150.out.qcow2} (100%)
create mode 100644 tests/qemu-iotests/150.out.raw
diff --git a/block/file-posix.c b/block/file-posix.c
index fbeb0068db..447f937aa1 100644
--- a/block/file-posix.c
+++ b/block/file-posix.c
@@ -1749,6 +1749,43 @@ static int handle_aiocb_discard(void *opaque)
return ret;
}
+/*
+ * Help alignment probing by allocating the first block.
+ *
+ * When reading with direct I/O from unallocated area on Gluster backed by XFS,
+ * reading succeeds regardless of request length. In this case we fallback to
+ * safe alignment which is not optimal. Allocating the first block avoids this
+ * fallback.
+ *
+ * fd may be opened with O_DIRECT, but we don't know the buffer alignment or
+ * request alignment, so we use safe values.
+ *
+ * Returns: 0 on success, -errno on failure. Since this is an optimization,
+ * caller may ignore failures.
+ */
+static int allocate_first_block(int fd, size_t max_size)
+{
+size_t write_size = (max_size < MAX_BLOCKSIZE)
+? BDRV_SECTOR_SIZE
+: MAX_BLOCKSIZE;
+size_t max_align = MAX(MAX_BLOCKSIZE, getpagesize());
+void *buf;
+ssize_t n;
+int ret;
+
+buf = qemu_memalign(max_align, write_size);
+memset(buf, 0, write_size);
+
+do {
+n = pwrite(fd, buf, write_size, 0);
+} while (n == -1 && errno == EINTR);
+
+ret = (n == -1) ? -errno : 0;
+
+qemu_vfree(buf);
+return ret;
+}
+
static int handle_aiocb_truncate(void *opaque)
{
RawPosixAIOData *aiocb = opaque;
@@ -1788,6 +1825,17 @@ static int handle_aiocb_truncate(void *opaque)
/* posix_fallocate() doesn't set errno. */
error_setg_errno(errp, -result,
"Could not preallocate new data");
+} else if (current_length == 0) {
+/*
+ * posix_fallocate() uses fallocate() if the filesystem
+ * supports it, or fallback to manually writing zeroes. If
+ * fallocate() was used, unaligned reads from the fallocated
+ * area in raw_probe_alignment() will succeed, hence we need to
+ * allocate the first block.
+ *
+ * Optimize future alignment probing; ignore failures.
+ */
+
[Qemu-devel] [PATCH v3 2/2] iotests: Test allocate_first_block() with O_DIRECT
Using block_resize we can test allocate_first_block() with file
descriptor opened with O_DIRECT, ensuring that it works for any size
larger than 4096 bytes.
Testing smaller sizes is tricky as the result depends on the filesystem
used for testing. For example on NFS any size will work since O_DIRECT
does not require any alignment.
Signed-off-by: Nir Soffer
Reviewed-by: Max Reitz
---
tests/qemu-iotests/175 | 28
tests/qemu-iotests/175.out | 8
2 files changed, 36 insertions(+)
diff --git a/tests/qemu-iotests/175 b/tests/qemu-iotests/175
index 7ba28b3c1b..55db2803ed 100755
--- a/tests/qemu-iotests/175
+++ b/tests/qemu-iotests/175
@@ -49,6 +49,23 @@ _filter_blocks()
-e "s/blocks=$((extra_blocks + img_size / 512))\\(\$\\|[^0-9]\\)/max
allocation/"
}
+# Resize image using block_resize.
+# Parameter 1: image path
+# Parameter 2: new size
+_block_resize()
+{
+local path=$1
+local size=$2
+
+$QEMU -qmp stdio -nographic -nodefaults \
+-blockdev file,node-name=file,filename=$path,cache.direct=on \
+<
[Qemu-devel] [PATCH v3 0/2] Optimize alignment probing
When probing unallocated area on remote XFS filesystem we cannot detect request
alignment and we fallback to safe value which may not be optimal. Avoid this
fallback by always allocating the first block when creating a new image or
resizing empty image.
Tested with all formats:
for fmt in raw bochs cloop parallels qcow qcow2 qed vdi vpc vhdx vmdk luks
dmg; do
./check -$fmt
done
Changes in v3:
- Allocating first block works now when 512 <= size < 4096, storage sector size
is 512 bytes, and using block_resize with O_DIRECT (Max)
- Fix return value on errors if qemu_vfree() modified errno (Eric)
- Improve comment about using allocate_first_block in FALLOC mode (Max)
- Remove unneeded $(()) in _filter_block (Max)
- Add _default_cache_mode and _supported_cache_mode to new test (Max)
- Fix disk size in vmdk tests
v2 was here:
https://lists.nongnu.org/archive/html/qemu-block/2019-08/msg01265.html
Changes in v2:
- Support file descriptor opened with O_DIRECT (e.g. in block_resize) (Max)
- Remove unneeded change in 160 (Max)
- Fix block filter in 175 on filesystem allocating extra blocks (Max)
- Comment why we ignore errors in allocte_first_block() (Max)
- Comment why allocate_first_block() is needed in FALLOC mode (Max)
- Clarify commit message about user visible changes (Maxim)
- Fix 178.out.qcow2
- Fix 150.out with -qcow2 by splitting to 150.out.{raw,qcow2}
- Add test for allocate_first_block() with block_resize (Max)
- Drop provisioning tests results since I ran them only once
v1 was here:
https://lists.nongnu.org/archive/html/qemu-block/2019-08/msg00821.html
Nir Soffer (2):
block: posix: Always allocate the first block
iotests: Test allocate_first_block() with O_DIRECT
block/file-posix.c| 51 +++
tests/qemu-iotests/059.out| 2 +-
tests/qemu-iotests/{150.out => 150.out.qcow2} | 0
tests/qemu-iotests/150.out.raw| 12 +
tests/qemu-iotests/175| 47 ++---
tests/qemu-iotests/175.out| 16 --
tests/qemu-iotests/178.out.qcow2 | 4 +-
tests/qemu-iotests/221.out| 12 +++--
tests/qemu-iotests/253.out| 12 +++--
9 files changed, 135 insertions(+), 21 deletions(-)
rename tests/qemu-iotests/{150.out => 150.out.qcow2} (100%)
create mode 100644 tests/qemu-iotests/150.out.raw
--
2.20.1
Re: [Qemu-devel] [PATCH v2] configure: more resilient Python version capture
On Mon, Aug 26, 2019 at 11:58:32AM -0400, Cleber Rosa wrote:
> The current approach to capture the Python version is fragile, as it
> was demonstrated by a very specific build of Python 3 on Fedora 29
> that, under non-interactive shells would print multiline version
> information.
>
> The (badly) stripped version output would be sent to config-host.mak,
> producing bad syntax and rendering the makefiles unusable. Now, the
> Python versions is printed by configure, but only a simple (and better
> controlled variable) indicating whether the build system is using
> Python 2 is kept on config-host.mak.
>
> Signed-off-by: Cleber Rosa
>
> ---
> v2: Use python from '$python' variable instead of hardcoded 'python2'
> ---
> configure | 5 +++--
> tests/Makefile.include | 2 +-
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/configure b/configure
> index e44e454c43..95134c0180 100755
> --- a/configure
> +++ b/configure
> @@ -1864,7 +1864,7 @@ if ! $python -c 'import sys; sys.exit(sys.version_info
> < (2,7))'; then
> fi
>
> # Preserve python version since some functionality is dependent on it
> -python_version=$($python -V 2>&1 | sed -e 's/Python\ //')
> +python_version=$($python -c 'import sys; print("%d.%d.%d" %
> (sys.version_info[0], sys.version_info[1], sys.version_info[2]))' 2>/dev/null)
>
> # Suppress writing compiled files
> python="$python -B"
> @@ -6511,6 +6511,7 @@ if ! $python -c 'import sys; sys.exit(sys.version_info
> < (3,0))'; then
>echo
>echo "warning: Python 2 support is deprecated" >&2
>echo "warning: Python 3 will be required for building future versions of
> QEMU" >&2
> + python2="y"
> fi
>
> config_host_mak="config-host.mak"
> @@ -7333,7 +7334,7 @@ echo "INSTALL_DATA=$install -c -m 0644" >>
> $config_host_mak
> echo "INSTALL_PROG=$install -c -m 0755" >> $config_host_mak
> echo "INSTALL_LIB=$install -c -m 0644" >> $config_host_mak
> echo "PYTHON=$python" >> $config_host_mak
> -echo "PYTHON_VERSION=$python_version" >> $config_host_mak
> +echo "PYTHON2=$python2" >> $config_host_mak
> echo "CC=$cc" >> $config_host_mak
> if $iasl -h > /dev/null 2>&1; then
>echo "IASL=$iasl" >> $config_host_mak
> diff --git a/tests/Makefile.include b/tests/Makefile.include
> index 49684fd4f4..f5ac09549c 100644
> --- a/tests/Makefile.include
> +++ b/tests/Makefile.include
> @@ -1135,7 +1135,7 @@ TESTS_RESULTS_DIR=$(BUILD_DIR)/tests/results
> AVOCADO_SHOW=app
> AVOCADO_TAGS=$(patsubst %-softmmu,-t arch:%, $(filter
> %-softmmu,$(TARGET_DIRS)))
>
> -ifneq ($(findstring v2,"v$(PYTHON_VERSION)"),v2)
> +ifneq ($(PYTHON2),y)
> $(TESTS_VENV_DIR): $(TESTS_VENV_REQ)
> $(call quiet-command, \
> $(PYTHON) -m venv --system-site-packages $@, \
> --
> 2.21.0
>
>
Reviewed-by: Tony Nguyen
[Qemu-devel] [PATCH 13/13] target/openrisc: Update cpu "any" to v1.3
Now that the two updates from v3.1 are implemented, update the "any" cpu to enable it. Signed-off-by: Richard Henderson --- target/openrisc/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index f96a69e278..506aec6bfb 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -129,7 +129,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.vr = 0x1340; /* Obsolete VER + UVRP for new SPRs */ cpu->env.vr2 = 0; /* No version specific id */ -cpu->env.avr = 0x0101; /* Architecture v1.1 */ +cpu->env.avr = 0x0103; /* Architecture v1.3 */ cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | -- 2.17.1
[Qemu-devel] [PATCH 11/13] target/openrisc: Implement move to/from FPCSR
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 2 ++
target/openrisc/cpu.c| 1 +
target/openrisc/fpu_helper.c | 13 +
target/openrisc/machine.c| 11 +++
target/openrisc/sys_helper.c | 18 --
5 files changed, 39 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 71c5959828..0ad02eab79 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -413,6 +413,8 @@ static inline void cpu_set_sr(CPUOpenRISCState *env,
uint32_t val)
env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
}
+void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val);
+
#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
#endif /* OPENRISC_CPU_H */
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b931605e62..f96a69e278 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -55,6 +55,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.sr = SR_FO | SR_SM;
cpu->env.lock_addr = -1;
s->exception_index = -1;
+cpu_set_fpcsr(>env, 0);
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x;
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 7bcef9dc53..59e1413279 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -61,6 +61,19 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
}
}
+void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
+{
+static const int rm_to_sf[] = {
+float_round_nearest_even,
+float_round_to_zero,
+float_round_up,
+float_round_down
+};
+
+env->fpcsr = val & 0x7ff;
+set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], >fp_status);
+}
+
uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
{
return int64_to_float64(val, >fp_status);
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 0a96404dc6..b92985d99b 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -121,10 +121,21 @@ static const VMStateDescription vmstate_env = {
}
};
+static int cpu_post_load(void *opaque, int version_id)
+{
+OpenRISCCPU *cpu = opaque;
+CPUOpenRISCState *env = >env;
+
+/* Update env->fp_status to match env->fpcsr. */
+cpu_set_fpcsr(env, env->fpcsr);
+return 0;
+}
+
const VMStateDescription vmstate_openrisc_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
+.post_load = cpu_post_load,
.fields = (VMStateField[]) {
VMSTATE_CPU(),
VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index cf8e637b08..d9fe6c5948 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -37,8 +37,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
CPUState *cs = env_cpu(env);
target_ulong mr;
int idx;
+#endif
switch (spr) {
+#ifndef CONFIG_USER_ONLY
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -179,10 +181,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong
spr, target_ulong rb)
}
cpu_openrisc_timer_update(cpu);
break;
-default:
+#endif
+
+case TO_SPR(0, 20): /* FPCSR */
+cpu_set_fpcsr(env, rb);
break;
}
-#endif
}
target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
@@ -193,8 +197,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
OpenRISCCPU *cpu = env_archcpu(env);
CPUState *cs = env_cpu(env);
int idx;
+#endif
switch (spr) {
+#ifndef CONFIG_USER_ONLY
case TO_SPR(0, 0): /* VR */
return env->vr;
@@ -303,12 +309,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
case TO_SPR(10, 1): /* TTCR */
cpu_openrisc_count_update(cpu);
return cpu_openrisc_count_get(cpu);
-
-default:
-break;
-}
#endif
+case TO_SPR(0, 20): /* FPCSR */
+return env->fpcsr;
+}
+
/* for rd is passed in, if rd unchanged, just keep it back. */
return rd;
}
--
2.17.1
[Qemu-devel] [PATCH 09/13] target/openrisc: Add support for ORFPX64A32
This is hardware support for double-precision floating-point
using pairs of 32-bit registers. Fix a latent bug in the
heretofore unused helper_itofd. Include the bit for cpu "any".
Signed-off-by: Richard Henderson
---
linux-user/openrisc/target_elf.h | 2 +-
target/openrisc/helper.h | 2 +
target/openrisc/cpu.c| 2 +-
target/openrisc/disas.c | 56
target/openrisc/fpu_helper.c | 14 +-
target/openrisc/translate.c | 230 +++
target/openrisc/insns.decode | 31 +
7 files changed, 333 insertions(+), 4 deletions(-)
diff --git a/linux-user/openrisc/target_elf.h b/linux-user/openrisc/target_elf.h
index 40ceb025c9..265ecd3079 100644
--- a/linux-user/openrisc/target_elf.h
+++ b/linux-user/openrisc/target_elf.h
@@ -9,6 +9,6 @@
#define OPENRISC_TARGET_ELF_H
static inline const char *cpu_get_model(uint32_t eflags)
{
-return "or1200";
+return "any";
}
#endif
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index 96d79a8113..94b823580e 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -30,6 +30,8 @@ DEF_HELPER_FLAGS_2(itofd, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(itofs, TCG_CALL_NO_RWG, i32, env, i32)
DEF_HELPER_FLAGS_2(ftoid, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_2(ftois, TCG_CALL_NO_RWG, i32, env, i32)
+DEF_HELPER_FLAGS_2(stod, TCG_CALL_NO_RWG, i64, env, i32)
+DEF_HELPER_FLAGS_2(dtos, TCG_CALL_NO_RWG, i32, env, i64)
DEF_HELPER_FLAGS_4(float_madd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32)
DEF_HELPER_FLAGS_4(float_madd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f3c8134531..b931605e62 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -132,7 +132,7 @@ static void openrisc_any_initfn(Object *obj)
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
- CPUCFGR_AVRP | CPUCFGR_EVBARP;
+ CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S;
/* 1Way, TLB_SIZE entries. */
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index 7091832347..4de5c632de 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -166,3 +166,59 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
+
+FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sub, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(mul, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(div, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(rem, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(madd, d, "r%d,r%d, r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+
+FP_INSN(itof, d, "r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1)
+FP_INSN(ftoi, d, "r%d,r%d, r%d,r%d",
+a->d, a->d + a->dp + 1,
+a->a, a->a + a->ap + 1)
+
+FP_INSN(stod, d, "r%d,r%d, r%d",
+a->d, a->d + a->dp + 1, a->a)
+FP_INSN(dtos, d, "r%d r%d,r%d",
+a->d, a->a, a->a + a->ap + 1)
+
+FP_INSN(sfeq, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfne, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfgt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfge, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 4cc5b297c5..9d7dfc0fb9 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -63,7 +63,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
{
-return int32_to_float64(val, >fp_status);
+return int64_to_float64(val, >fp_status);
}
uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
@@ -73,7 +73,7 @@ uint32_t HELPER(itofs)(CPUOpenRISCState *env, uint32_t val)
[Qemu-devel] [PATCH 06/13] target/openrisc: Add VR2 and AVR special processor registers
Update the CPUCFG bits to arch v1.3.
Include support for AVRP for cpu "any".
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 11 +++
target/openrisc/cpu.c| 8 ++--
target/openrisc/sys_helper.c | 6 ++
3 files changed, 19 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 18d7445e74..71c5959828 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -96,11 +96,12 @@ enum {
CPUCFGR_OF32S = (1 << 7),
CPUCFGR_OF64S = (1 << 8),
CPUCFGR_OV64S = (1 << 9),
-/* CPUCFGR_ND = (1 << 10), */
-/* CPUCFGR_AVRP = (1 << 11), */
+CPUCFGR_ND = (1 << 10),
+CPUCFGR_AVRP = (1 << 11),
CPUCFGR_EVBARP = (1 << 12),
-/* CPUCFGR_ISRP = (1 << 13), */
-/* CPUCFGR_AECSRP = (1 << 14), */
+CPUCFGR_ISRP = (1 << 13),
+CPUCFGR_AECSRP = (1 << 14),
+CPUCFGR_OF64A32S = (1 << 15),
};
/* DMMU configure register */
@@ -280,6 +281,8 @@ typedef struct CPUOpenRISCState {
/* Fields from here on are preserved across CPU reset. */
uint32_t vr; /* Version register */
+uint32_t vr2; /* Version register 2 */
+uint32_t avr; /* Architecture version register */
uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
uint32_t dmmucfgr;/* DMMU configure register */
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index d9f447e90c..9f566ad883 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -126,9 +126,13 @@ static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
-cpu->env.vr = 0x1300;
+cpu->env.vr = 0x1340; /* Obsolete VER + UVRP for new SPRs */
+cpu->env.vr2 = 0; /* No version specific id */
+cpu->env.avr = 0x0101; /* Architecture v1.1 */
+
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
-cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
+cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S |
+ CPUCFGR_AVRP | CPUCFGR_EVBARP;
/* 1Way, TLB_SIZE entries. */
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index a2b1f52294..cf8e637b08 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -210,6 +210,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
case TO_SPR(0, 4): /* IMMUCFGR */
return env->immucfgr;
+case TO_SPR(0, 9): /* VR2 */
+return env->vr2;
+
+case TO_SPR(0, 10): /* AVR */
+return env->avr;
+
case TO_SPR(0, 11): /* EVBAR */
return env->evbar;
--
2.17.1
[Qemu-devel] [PATCH 07/13] target/openrisc: Fix lf.ftoi.s
The specification of this insn is round-to-zero.
Signed-off-by: Richard Henderson
---
target/openrisc/fpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index b9d2ebbb8c..4cc5b297c5 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -78,7 +78,7 @@ uint64_t HELPER(ftoid)(CPUOpenRISCState *env, uint64_t val)
uint32_t HELPER(ftois)(CPUOpenRISCState *env, uint32_t val)
{
-return float32_to_int32(val, >fp_status);
+return float32_to_int32_round_to_zero(val, >fp_status);
}
#define FLOAT_CALC(name) \
--
2.17.1
[Qemu-devel] [PATCH 10/13] target/openrisc: Implement unordered fp comparisons
These were added to the 1.3 spec. For OF32S, validate AVR.
But OF64A32 is itself new to 1.3 so no extra check needed.
Signed-off-by: Richard Henderson
---
target/openrisc/helper.h | 4 ++
target/openrisc/disas.c | 24 ++
target/openrisc/fpu_helper.c | 20 +
target/openrisc/translate.c | 85
target/openrisc/insns.decode | 12 +
5 files changed, 145 insertions(+)
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index 94b823580e..d847814a28 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -52,6 +52,10 @@ DEF_HELPER_FLAGS_3(float_ ## op ## _d, TCG_CALL_NO_RWG, tl,
env, i64, i64)
FOP_CMP(eq)
FOP_CMP(lt)
FOP_CMP(le)
+FOP_CMP(un)
+FOP_CMP(ueq)
+FOP_CMP(ule)
+FOP_CMP(ult)
#undef FOP_CMP
/* interrupt */
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index 4de5c632de..e51cbb24c6 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -166,6 +166,12 @@ FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfun, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfueq, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfuge, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfugt, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfule, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfult, s, "r%d, r%d", a->a, a->b)
FP_INSN(add, d, "r%d,r%d, r%d,r%d, r%d,r%d",
a->d, a->d + a->dp + 1,
@@ -222,3 +228,21 @@ FP_INSN(sflt, d, "r%d,r%d, r%d,r%d",
FP_INSN(sfle, d, "r%d,r%d, r%d,r%d",
a->a, a->a + a->ap + 1,
a->b, a->b + a->bp + 1)
+FP_INSN(sfun, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfueq, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfuge, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfugt, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfule, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
+FP_INSN(sfult, d, "r%d,r%d, r%d,r%d",
+a->a, a->a + a->ap + 1,
+a->b, a->b + a->bp + 1)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index 9d7dfc0fb9..7bcef9dc53 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -135,4 +135,24 @@ target_ulong helper_float_ ## name ## _s(CPUOpenRISCState
*env, \
FLOAT_CMP(le, le)
FLOAT_CMP(lt, lt)
FLOAT_CMP(eq, eq_quiet)
+FLOAT_CMP(un, unordered_quiet)
#undef FLOAT_CMP
+
+#define FLOAT_UCMP(name, expr) \
+target_ulong helper_float_ ## name ## _d(CPUOpenRISCState *env, \
+ uint64_t fdt0, uint64_t fdt1)\
+{ \
+int r = float64_compare_quiet(fdt0, fdt1, >fp_status); \
+return expr; \
+} \
+target_ulong helper_float_ ## name ## _s(CPUOpenRISCState *env, \
+ uint32_t fdt0, uint32_t fdt1)\
+{ \
+int r = float32_compare_quiet(fdt0, fdt1, >fp_status); \
+return expr; \
+}
+
+FLOAT_UCMP(ueq, r == float_relation_equal || r == float_relation_unordered)
+FLOAT_UCMP(ult, r == float_relation_less || r == float_relation_unordered)
+FLOAT_UCMP(ule, r != float_relation_greater)
+#undef FLOAT_UCMP
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index fcf73cbf8f..024218ebeb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -46,6 +46,7 @@ typedef struct DisasContext {
uint32_t tb_flags;
uint32_t delayed_branch;
uint32_t cpucfgr;
+uint32_t avr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
@@ -141,6 +142,11 @@ static void gen_illegal_exception(DisasContext *dc)
dc->base.is_jmp = DISAS_NORETURN;
}
+static bool check_v1_3(DisasContext *dc)
+{
+return dc->avr >= 0x0103;
+}
+
static bool check_of32s(DisasContext *dc)
{
return dc->cpucfgr & CPUCFGR_OF32S;
@@ -1265,6 +1271,54 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a)
return do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
}
+static bool trans_lf_sfueq_s(DisasContext *dc, arg_ab *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+return do_fpcmp(dc, a, gen_helper_float_ueq_s, false, false);
+}
+
+static bool trans_lf_sfult_s(DisasContext *dc, arg_ab *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+return do_fpcmp(dc, a,
[Qemu-devel] [PATCH 08/13] target/openrisc: Check CPUCFG_OF32S for float insns
Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.c | 2 +-
target/openrisc/translate.c | 84 -
2 files changed, 36 insertions(+), 50 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index 9f566ad883..f3c8134531 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -131,7 +131,7 @@ static void openrisc_any_initfn(Object *obj)
cpu->env.avr = 0x0101; /* Architecture v1.1 */
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
-cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S |
+cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
CPUCFGR_AVRP | CPUCFGR_EVBARP;
/* 1Way, TLB_SIZE entries. */
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 37e8098023..faae979ae3 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -45,6 +45,7 @@ typedef struct DisasContext {
uint32_t mem_idx;
uint32_t tb_flags;
uint32_t delayed_branch;
+uint32_t cpucfgr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
@@ -140,30 +141,11 @@ static void gen_illegal_exception(DisasContext *dc)
dc->base.is_jmp = DISAS_NORETURN;
}
-/* not used yet, open it when we need or64. */
-/*#ifdef TARGET_OPENRISC64
-static void check_ob64s(DisasContext *dc)
+static bool check_of32s(DisasContext *dc)
{
-if (!(dc->flags & CPUCFGR_OB64S)) {
-gen_illegal_exception(dc);
-}
+return dc->cpucfgr & CPUCFGR_OF32S;
}
-static void check_of64s(DisasContext *dc)
-{
-if (!(dc->flags & CPUCFGR_OF64S)) {
-gen_illegal_exception(dc);
-}
-}
-
-static void check_ov64s(DisasContext *dc)
-{
-if (!(dc->flags & CPUCFGR_OV64S)) {
-gen_illegal_exception(dc);
-}
-}
-#endif*/
-
static TCGv cpu_R(DisasContext *dc, int reg)
{
if (reg == 0) {
@@ -1157,26 +1139,37 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
return true;
}
-static void do_fp2(DisasContext *dc, arg_da *a,
+static bool do_fp2(DisasContext *dc, arg_da *a,
void (*fn)(TCGv, TCGv_env, TCGv))
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a));
gen_helper_update_fpcsr(cpu_env);
+return true;
}
-static void do_fp3(DisasContext *dc, arg_dab *a,
+static bool do_fp3(DisasContext *dc, arg_dab *a,
void (*fn)(TCGv, TCGv_env, TCGv, TCGv))
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
fn(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->a), cpu_R(dc, a->b));
gen_helper_update_fpcsr(cpu_env);
+return true;
}
-static void do_fpcmp(DisasContext *dc, arg_ab *a,
+static bool do_fpcmp(DisasContext *dc, arg_ab *a,
void (*fn)(TCGv, TCGv_env, TCGv, TCGv),
bool inv, bool swap)
{
+if (!check_of32s(dc)) {
+return false;
+}
if (swap) {
fn(cpu_sr_f, cpu_env, cpu_R(dc, a->b), cpu_R(dc, a->a));
} else {
@@ -1186,52 +1179,50 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a,
tcg_gen_xori_tl(cpu_sr_f, cpu_sr_f, 1);
}
gen_helper_update_fpcsr(cpu_env);
+return true;
}
static bool trans_lf_add_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_add_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_add_s);
}
static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_sub_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_sub_s);
}
static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_mul_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_mul_s);
}
static bool trans_lf_div_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_div_s);
-return true;
+return do_fp3(dc, a, gen_helper_float_div_s);
}
static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a)
{
-do_fp3(dc, a, gen_helper_float_rem_s);
+return do_fp3(dc, a, gen_helper_float_rem_s);
return true;
}
static bool trans_lf_itof_s(DisasContext *dc, arg_da *a)
{
-do_fp2(dc, a, gen_helper_itofs);
-return true;
+return do_fp2(dc, a, gen_helper_itofs);
}
static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a)
{
-do_fp2(dc, a, gen_helper_ftois);
-return true;
+return do_fp2(dc, a, gen_helper_ftois);
}
static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a)
{
+if (!check_of32s(dc)) {
+return false;
+}
check_r0_write(dc, a->d);
gen_helper_float_madd_s(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d),
cpu_R(dc, a->a), cpu_R(dc, a->b));
@@
[Qemu-devel] [PATCH 02/13] target/openrisc: Replace cpu register array with a function
The writes to cpu_R[0] are now a race across threads, now that we
do code generation in parallel. Stage the change by introducing
a function to return the temp for R0.
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 213
1 file changed, 116 insertions(+), 97 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index ed2197c371..3812dc4427 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -63,7 +63,7 @@ static inline bool is_user(DisasContext *dc)
#include "decode.inc.c"
static TCGv cpu_sr;
-static TCGv cpu_R[32];
+static TCGv cpu_regs[32];
static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
@@ -117,12 +117,12 @@ void openrisc_translate_init(void)
offsetof(CPUOpenRISCState, mac),
"mac");
for (i = 0; i < 32; i++) {
-cpu_R[i] = tcg_global_mem_new(cpu_env,
- offsetof(CPUOpenRISCState,
- shadow_gpr[0][i]),
- regnames[i]);
+cpu_regs[i] = tcg_global_mem_new(cpu_env,
+ offsetof(CPUOpenRISCState,
+ shadow_gpr[0][i]),
+ regnames[i]);
}
-cpu_R0 = cpu_R[0];
+cpu_R0 = cpu_regs[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
@@ -163,6 +163,11 @@ static void check_ov64s(DisasContext *dc)
}
#endif*/
+static TCGv cpu_R(DisasContext *dc, int reg)
+{
+return cpu_regs[reg];
+}
+
/*
* We're about to write to REG. On the off-chance that the user is
* writing to R0, re-instate the architectural register.
@@ -170,7 +175,7 @@ static void check_ov64s(DisasContext *dc)
static void check_r0_write(DisasContext *dc, int reg)
{
if (unlikely(reg == 0)) {
-cpu_R[0] = cpu_R0;
+cpu_regs[0] = cpu_R0;
}
}
@@ -439,98 +444,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv
srcb)
static bool trans_l_add(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_add(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_addc(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_addc(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sub(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+gen_sub(dc, cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_and(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_and_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_or(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_or_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_xor(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_xor_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sll(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_shl_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_srl(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_shr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_sra(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_sar_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_ror(DisasContext *dc, arg_dab *a)
{
check_r0_write(dc, a->d);
-tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
+tcg_gen_rotr_tl(cpu_R(dc, a->d), cpu_R(dc, a->a), cpu_R(dc, a->b));
return true;
}
static bool trans_l_exths(DisasContext *dc, arg_da *a)
{
check_r0_write(dc, a->d);
-tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
+tcg_gen_ext16s_tl(cpu_R(dc, a->d), cpu_R(dc, a->a));
return true;
}
static bool trans_l_extbs(DisasContext *dc, arg_da *a)
{
check_r0_write(dc, a->d);
-tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
+tcg_gen_ext8s_tl(cpu_R(dc,
[Qemu-devel] [PATCH 01/13] target/openrisc: Add DisasContext parameter to check_r0_write
We will need this context in the next patch.
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 96 +++--
1 file changed, 49 insertions(+), 47 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 4360ce4045..ed2197c371 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -163,14 +163,16 @@ static void check_ov64s(DisasContext *dc)
}
#endif*/
-/* We're about to write to REG. On the off-chance that the user is
- writing to R0, re-instate the architectural register. */
-#define check_r0_write(reg) \
-do {\
-if (unlikely(reg == 0)) { \
-cpu_R[0] = cpu_R0; \
-} \
-} while (0)
+/*
+ * We're about to write to REG. On the off-chance that the user is
+ * writing to R0, re-instate the architectural register.
+ */
+static void check_r0_write(DisasContext *dc, int reg)
+{
+if (unlikely(reg == 0)) {
+cpu_R[0] = cpu_R0;
+}
+}
static void gen_ove_cy(DisasContext *dc)
{
@@ -436,98 +438,98 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv
srcb)
static bool trans_l_add(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_addc(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sub(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_and(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_or(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_xor(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sll(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_srl(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sra(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_ror(DisasContext *dc, arg_dab *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_exths(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_extbs(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_exthz(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
static bool trans_l_extbz(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
}
@@ -536,7 +538,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
{
TCGv zero;
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
zero = tcg_const_tl(0);
tcg_gen_movcond_tl(TCG_COND_NE, cpu_R[a->d], cpu_sr_f, zero,
cpu_R[a->a], cpu_R[a->b]);
@@ -546,7 +548,7 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a)
static bool trans_l_ff1(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1);
tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1);
return true;
@@ -554,7 +556,7 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a)
static bool trans_l_fl1(DisasContext *dc, arg_da *a)
{
-check_r0_write(a->d);
+check_r0_write(dc, a->d);
tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS);
tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]);
return true;
@@ -562,28 +564,28 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a)
static
[Qemu-devel] [PATCH 12/13] target/openrisc: Implement l.adrp
This was added to the 1.3 spec.
Signed-off-by: Richard Henderson
---
target/openrisc/disas.c | 1 +
target/openrisc/translate.c | 13 +
target/openrisc/insns.decode | 2 ++
3 files changed, 16 insertions(+)
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index e51cbb24c6..ce112640b9 100644
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -98,6 +98,7 @@ INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b)
INSN(nop,"")
+INSN(adrp, "r%d, %d", a->d, a->i)
INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i)
INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i)
INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 024218ebeb..bd2f29e272 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -799,6 +799,19 @@ static bool trans_l_nop(DisasContext *dc, arg_l_nop *a)
return true;
}
+static bool trans_l_adrp(DisasContext *dc, arg_l_adrp *a)
+{
+if (!check_v1_3(dc)) {
+return false;
+}
+check_r0_write(dc, a->d);
+
+tcg_gen_movi_i32(cpu_R(dc, a->d),
+ (dc->base.pc_next & TARGET_PAGE_MASK) +
+ ((target_long)a->i << TARGET_PAGE_BITS));
+return true;
+}
+
static bool trans_l_addi(DisasContext *dc, arg_rri *a)
{
TCGv t0;
diff --git a/target/openrisc/insns.decode b/target/openrisc/insns.decode
index 71e0d740db..0d6f7c29f8 100644
--- a/target/openrisc/insns.decode
+++ b/target/openrisc/insns.decode
@@ -102,6 +102,8 @@ l_maci 010011 - a:5 i:s16
l_movhi 000110 d:5 0 k:16
l_macrc 000110 d:5 1
+l_adrp 10 d:5 i:s21
+
# Arithmetic Instructions
--
2.17.1
[Qemu-devel] [PATCH 03/13] target/openrisc: Cache R0 in DisasContext
Finish the race condition fix from the previous patch.
Signed-off-by: Richard Henderson
---
target/openrisc/translate.c | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 3812dc4427..37e8098023 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -48,6 +48,9 @@ typedef struct DisasContext {
/* If not -1, jmp_pc contains this value and so is a direct jump. */
target_ulong jmp_pc_imm;
+
+/* The temporary corresponding to register 0 for this compilation. */
+TCGv R0;
} DisasContext;
static inline bool is_user(DisasContext *dc)
@@ -64,7 +67,6 @@ static inline bool is_user(DisasContext *dc)
static TCGv cpu_sr;
static TCGv cpu_regs[32];
-static TCGv cpu_R0;
static TCGv cpu_pc;
static TCGv jmp_pc;/* l.jr/l.jalr temp pc */
static TCGv cpu_ppc;
@@ -122,7 +124,6 @@ void openrisc_translate_init(void)
shadow_gpr[0][i]),
regnames[i]);
}
-cpu_R0 = cpu_regs[0];
}
static void gen_exception(DisasContext *dc, unsigned int excp)
@@ -165,7 +166,11 @@ static void check_ov64s(DisasContext *dc)
static TCGv cpu_R(DisasContext *dc, int reg)
{
-return cpu_regs[reg];
+if (reg == 0) {
+return dc->R0;
+} else {
+return cpu_regs[reg];
+}
}
/*
@@ -175,7 +180,7 @@ static TCGv cpu_R(DisasContext *dc, int reg)
static void check_r0_write(DisasContext *dc, int reg)
{
if (unlikely(reg == 0)) {
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
}
}
@@ -747,7 +752,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
to cpu_regs[0]. Since l.swa is quite often immediately followed by a
branch, don't bother reallocating; finish the TB using the "real" R0.
This also takes care of RB input across the branch. */
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
lab_fail = gen_new_label();
lab_done = gen_new_label();
@@ -1292,9 +1297,9 @@ static void openrisc_tr_tb_start(DisasContextBase *db,
CPUState *cs)
/* Allow the TCG optimizer to see that R0 == 0,
when it's true, which is the common case. */
if (dc->tb_flags & TB_FLAGS_R0_0) {
-cpu_regs[0] = tcg_const_tl(0);
+dc->R0 = tcg_const_tl(0);
} else {
-cpu_regs[0] = cpu_R0;
+dc->R0 = cpu_regs[0];
}
}
--
2.17.1
[Qemu-devel] [PATCH 05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 8
target/openrisc/cpu.c| 23 ---
target/openrisc/sys_helper.c | 4 ++--
3 files changed, 22 insertions(+), 13 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 755282f95d..18d7445e74 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState {
target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */
target_long sr_ov; /* the SR_OV bit (in the sign bit only) */
uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */
-uint32_t vr; /* Version register */
-uint32_t upr; /* Unit presence register */
-uint32_t dmmucfgr;/* DMMU configure register */
-uint32_t immucfgr;/* IMMU configure register */
uint32_t esr; /* Exception supervisor register */
uint32_t evbar; /* Exception vector base address register */
uint32_t pmr; /* Power Management Register */
@@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState {
struct {} end_reset_fields;
/* Fields from here on are preserved across CPU reset. */
+uint32_t vr; /* Version register */
+uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
+uint32_t dmmucfgr;/* DMMU configure register */
+uint32_t immucfgr;/* IMMU configure register */
#ifndef CONFIG_USER_ONLY
QEMUTimer *timer;
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f19e482a55..d9f447e90c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -56,13 +56,6 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.lock_addr = -1;
s->exception_index = -1;
-cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
- UPR_PMP;
-cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
- | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
-cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
- | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
-
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x;
cpu->env.picsr = 0x;
@@ -117,15 +110,31 @@ static void or1200_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+cpu->env.vr = 0x1308;
+cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |
CPUCFGR_EVBARP;
+
+/* 1Way, TLB_SIZE entries. */
+cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
static void openrisc_any_initfn(Object *obj)
{
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
+cpu->env.vr = 0x1300;
+cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;
+
+/* 1Way, TLB_SIZE entries. */
+cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
}
static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index d20f48b659..a2b1f52294 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
return env->vr;
case TO_SPR(0, 1): /* UPR */
-return env->upr;/* TT, DM, IM, UP present */
+return env->upr;
case TO_SPR(0, 2): /* CPUCFGR */
return env->cpucfgr;
case TO_SPR(0, 3): /* DMMUCFGR */
-return env->dmmucfgr;/* 1Way, 64 entries */
+return env->dmmucfgr;
case TO_SPR(0, 4): /* IMMUCFGR */
return env->immucfgr;
--
2.17.1
[Qemu-devel] [PATCH 04/13] target/openrisc: Make VR and PPC read-only
These SPRs are read-only. The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.
Signed-off-by: Richard Henderson
---
target/openrisc/cpu.h| 3 ---
target/openrisc/sys_helper.c | 10 +-
2 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 561f0f7fad..755282f95d 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -68,9 +68,6 @@ enum {
(reg) |= ((v & 0x1f) << 2);\
} while (0)
-/* Version Register */
-#define SPR_VR 0x003F
-
/* Interrupt */
#define NR_IRQS 32
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 1053409a04..d20f48b659 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
int idx;
switch (spr) {
-case TO_SPR(0, 0): /* VR */
-env->vr = rb;
-break;
-
case TO_SPR(0, 11): /* EVBAR */
env->evbar = rb;
break;
@@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr,
target_ulong rb)
cpu_set_sr(env, rb);
break;
-case TO_SPR(0, 18): /* PPC */
-env->ppc = rb;
-break;
-
case TO_SPR(0, 32): /* EPCR */
env->epcr = rb;
break;
@@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
target_ulong rd,
switch (spr) {
case TO_SPR(0, 0): /* VR */
-return env->vr & SPR_VR;
+return env->vr;
case TO_SPR(0, 1): /* UPR */
return env->upr;/* TT, DM, IM, UP present */
--
2.17.1
[Qemu-devel] [PATCH 00/13] target/openrisc updates
The first three fix an MTTCG race on cpu_R[0], now that we do code generation in parallel. Then some updates to the SPRs, cpuid checks for existing float insns, adding the new v1.3 instructions. I've run this through the gcc testsuite as make check-gcc \ RUNTESTFLAGS='--target_board=or1k-qemu/-mhard-float/-mdouble-float execute.exp' === gcc Summary === # of expected passes103979 # of unexpected failures26 # of expected failures 400 # of unresolved testcases 1 # of unsupported tests 2539 Of the 26, none are obviously floating-point related. r~ Richard Henderson (13): target/openrisc: Add DisasContext parameter to check_r0_write target/openrisc: Replace cpu register array with a function target/openrisc: Cache R0 in DisasContext target/openrisc: Make VR and PPC read-only target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init target/openrisc: Add VR2 and AVR special processor registers target/openrisc: Fix lf.ftoi.s target/openrisc: Check CPUCFG_OF32S for float insns target/openrisc: Add support for ORFPX64A32 target/openrisc: Implement unordered fp comparisons target/openrisc: Implement move to/from FPCSR target/openrisc: Implement l.adrp target/openrisc: Update cpu "any" to v1.3 linux-user/openrisc/target_elf.h | 2 +- target/openrisc/cpu.h| 24 +- target/openrisc/helper.h | 6 + target/openrisc/cpu.c| 30 +- target/openrisc/disas.c | 81 target/openrisc/fpu_helper.c | 49 ++- target/openrisc/machine.c| 11 + target/openrisc/sys_helper.c | 38 +- target/openrisc/translate.c | 716 +++ target/openrisc/insns.decode | 45 ++ 10 files changed, 774 insertions(+), 228 deletions(-) -- 2.17.1
Re: [Qemu-devel] [PATCH 0/2] riscv: Fix "-L" not working for bios image search path
On Fri, 16 Aug 2019 06:09:34 PDT (-0700), bmeng...@gmail.com wrote: Currently when QEMU is given a bios image with only a file name and its file path passed in "-L", it still reports file not found. This series fixes the issue. This is especially helpful for creating distro QEMU packages. Bin Meng (2): riscv: Add a helper routine for finding firmware riscv: Resolve full path of the given bios image hw/riscv/boot.c | 26 +- include/hw/riscv/boot.h | 1 + 2 files changed, 18 insertions(+), 9 deletions(-) Thanks, I've put these two in the patch queue with Alistair's review.
Re: [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions
On 8/26/19 1:38 PM, Peter Maydell wrote: >> + IT1011 ... imm:5 cond=%it_cond > > This is correct (same behaviour as the old decoder, but > it looks a bit odd here because it's not the same as > the fields defined by the architecture (in particular the > 'cond' field is not the same set of bits as the 'firstcond' > field). We could maybe comment it: > > # Bits 7:0 in IT are architecturally simply the > # new PSTATE.IT bits (despite the instruction description > # splitting them into 'firstcond' and 'mask' fields). > # In QEMU during translation we track the IT bits using > # the DisasContext fields condexec_cond and condexec_mask, > # so here we massage the bits from the insn into the form > # that that optimization requires. > > (Or equivalently we could just pass a single 8 bit immediate > to the trans_IT function and split it out there, I dunno.) I think I'll just go with this latter and do everything in trans_IT. >> +%imm6_9_3 9:1 3:5 !function=times_2 > > Would it be worth adding support to the decodetree script > for letting you specify fixed bits in this kind of field-decode, > so we could write '9:1 3:5 0' rather than having to specify > a multiply-by-2 function to put the 0 bit in ? Or is it > not likely to be common enough to be worth bothering with? > (Not something for this series, anyway.) I hadn't thought about that. Adding 1, 2, or -1 also appears, but that's 3 of the 60 instances currently in the tree whereas shifts make up 33 of 60. r~
Re: [Qemu-devel] [PATCH v2 0/4] Audio: misc fixes for "Audio 20190821 patches"
On Mon, 2019-08-26 at 21:59 +0200, Kővágó, Zoltán wrote: > Hi, > > This is the second iteration of my "random fixes" patchset. Compared to > v1, this has a new patch, fixing the memory error caused by an invalid > malloc. > > Regards, > Zoltan > > Kővágó, Zoltán (4): > audio: fix invalid malloc size in audio_create_pdos > audio: omitting audiodev= parameter is only deprecated > audio: paaudio: fix client name > audio: paaudio: ability to specify stream name > > qemu-deprecated.texi | 7 +++ > qapi/audio.json | 6 ++ > audio/audio.c| 10 +- > audio/paaudio.c | 6 +++--- > 4 files changed, 21 insertions(+), 8 deletions(-) > With that patch series everything works as expected. No more heap corruption when I don't use audiodev. Thanks! Best regards, Maxim Levitsky
Re: [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
On Fri, Aug 23, 2019 at 10:08 PM Bin Meng wrote: > > Hi Alistair, > > On Sat, Aug 24, 2019 at 1:29 AM Alistair Francis wrote: > > > > On Thu, Aug 22, 2019 at 10:15 PM Bin Meng wrote: > > > > > > As of today, the QEMU 'sifive_u' machine is a special target that does > > > not boot the upstream OpenSBI/U-Boot firmware images built for the real > > > SiFive HiFive Unleashed board. Hence OpenSBI supports a special platform > > > "qemu/sifive_u". For U-Boot, the sifive_fu540_defconfig is referenced > > > in the OpenSBI doc as its payload, but that does not boot at all due > > > to various issues in current QEMU 'sifive_u' machine codes. > > > > > > This series aims to improve the emulation fidelity of sifive_u machine, > > > so that the upstream OpenSBI, U-Boot and kernel images built for the > > > SiFive HiFive Unleashed board can be used out of the box without any > > > special hack. > > > > > > The major changes include: > > > - Heterogeneous harts creation supported, so that we can create a CPU > > > that exactly mirrors the real hardware: 1 E51 + 4 U54. > > > - Implemented a PRCI model for FU540 > > > - Implemented an OTP model for FU540, primarily used for storing serial > > > number of the board > > > - Fixed GEM support that was seriously broken on sifive_u > > > - Synced device tree with upstream Linux kernel on sifive_u > > > > > > OpenSBI v0.4 image built for sifive/fu540 is included as the default > > > bios image for 'sifive_u' machine. > > > > > > The series is tested against OpenSBI v0.4 image for sifive/fu540 > > > paltform, U-Boot v2019.10-rc1 image for sifive_fu540_defconfig, > > > and Linux kernel v5.3-rc3 image with the following patch: > > > > > > macb: Update compatibility string for SiFive FU540-C000 [1] > > > > > > OpenSBI + U-Boot, ping/tftpboot with U-Boot MACB driver works well. > > > Boot Linux 64-bit defconfig image, verified that system console on > > > the serial 0 and ping host work pretty well. > > > > > > An OpenSBI patch [2] was sent to drop the special "qemu/sifive_u" platform > > > support in OpenSBI. The original plan was to get the drop patch applied > > > after this QEMU series is merged. However after discussion in the OpenSBI > > > mailing list, it seems the best option for us is to let OpenSBI continue > > > shipping the special "qemu/sifive_u" platform support to work with QEMU > > > version <= 4.1 and deprecate the support sometime in the future. A patch > > > will need to be sent to OpenSBI mailing list to update its document. > > > > > > v4 is now rebased on Palmer's QEMU RISC-V repo "for-master" branch. > > > Dropped the following v3 patch that was already done by someone else. > > > - riscv: sifive_u: Generate an aliases node in the device tree > > > - riscv: sifive_u: Support loading initramfs > > > > > > The following v3 patch was dropped too due to a different cluster approach > > > suggested by Richard Henderson is used in v4: > > > - riscv: hart: Support heterogeneous harts population > > > > > > [1]: https://patchwork.kernel.org/patch/11050003/ > > > [2]: http://lists.infradead.org/pipermail/opensbi/2019-August/000335.html > > > > > > Changes in v5: > > > - new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...) instead > > > in various sifive models > > > - new patch to remove the unnecessary include of target/riscv/cpu.h > > > - change to use defines instead of enums > > > - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_prci > > > - creating a 32-bit val variable and using that instead of casting > > > everywhere in sifive_u_prci_write() > > > - move all register initialization to sifive_u_prci_reset() function > > > - drop sifive_u_prci_create() > > > - s/codes that worked/code that works/g > > > - create sifive_u_prci block directly in the machine codes, instead > > > of calling sifive_u_prci_create() > > > - change to use defines instead of enums > > > - change to use qemu_log_mask(LOG_GUEST_ERROR,...) in sifive_u_otp > > > - creating a 32-bit val variable and using that instead of casting > > > everywhere in sifive_u_otp_write() > > > - move all register initialization to sifive_u_otp_reset() function > > > - drop sifive_u_otp_create() > > > - create sifive_u_otp block directly in the machine codes, instead > > > of calling sifive_u_otp_create() > > > - add the missing "local-mac-address" property in the ethernet node > > > > > > Changes in v4: > > > - remove 2 more "linux,phandle" instances in sifive_u.c and spike.c > > > after rebasing on Palmer's QEMU RISC-V tree > > > - change create_fdt() to return void in sifive_u.c too, after rebasing > > > on Palmer's QEMU RISC-V tree > > > - new patch to remove executable attribute of opensbi images > > > - prefix all macros/variables/functions with SIFIVE_E/sifive_e > > > in the sifive_e_prci driver > > > - new patch to add a "hartid-base" property to RISC-V hart array > > > - changed to create clusters for each cpu type > > > - prefix all
Re: [Qemu-devel] [PATCH v5 12/30] riscv: sifive_e: Drop sifive_mmio_emulate()
On Thu, 2019-08-22 at 22:10 -0700, Bin Meng wrote:
> Use create_unimplemented_device() instead.
>
> Signed-off-by: Bin Meng
Reviewed-by: Alistair Francis
Alistair
>
> ---
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - drop patch "riscv: sifive: Move sifive_mmio_emulate() to a common
> place"
> - new patch "riscv: sifive_e: Drop sifive_mmio_emulate()"
>
> hw/riscv/sifive_e.c | 23 ---
> 1 file changed, 8 insertions(+), 15 deletions(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 2d67670..040d59f 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -37,6 +37,7 @@
> #include "hw/loader.h"
> #include "hw/sysbus.h"
> #include "hw/char/serial.h"
> +#include "hw/misc/unimp.h"
> #include "target/riscv/cpu.h"
> #include "hw/riscv/riscv_hart.h"
> #include "hw/riscv/sifive_plic.h"
> @@ -74,14 +75,6 @@ static const struct MemmapEntry {
> [SIFIVE_E_DTIM] = { 0x8000, 0x4000 }
> };
>
> -static void sifive_mmio_emulate(MemoryRegion *parent, const char
> *name,
> - uintptr_t offset, uintptr_t length)
> -{
> -MemoryRegion *mock_mmio = g_new(MemoryRegion, 1);
> -memory_region_init_ram(mock_mmio, NULL, name, length,
> _fatal);
> -memory_region_add_subregion(parent, offset, mock_mmio);
> -}
> -
> static void riscv_sifive_e_init(MachineState *machine)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> @@ -172,7 +165,7 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
> memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
> SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE);
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> +create_unimplemented_device("riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
>
> @@ -199,19 +192,19 @@ static void
> riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
>
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
> serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART0_IRQ));
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0",
> +create_unimplemented_device("riscv.sifive.e.qspi0",
> memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0",
> +create_unimplemented_device("riscv.sifive.e.pwm0",
> memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
> sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
> serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic),
> SIFIVE_E_UART1_IRQ));
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1",
> +create_unimplemented_device("riscv.sifive.e.qspi1",
> memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1",
> +create_unimplemented_device("riscv.sifive.e.pwm1",
> memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2",
> +create_unimplemented_device("riscv.sifive.e.qspi2",
> memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
> -sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2",
> +create_unimplemented_device("riscv.sifive.e.pwm2",
> memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
>
> /* Flash memory */
Re: [Qemu-devel] patch to swap SIGRTMIN + 1 and SIGRTMAX - 1
On Wed, Aug 21, 2019 at 2:28 AM Laurent Vivier wrote: > Le 19/08/2019 à 23:46, Josh Kunz via Qemu-devel a écrit : > > Hi all, > > > > I have also experienced issues with SIGRTMIN + 1, and am interested in > > moving this patch forwards. Anything I can do here to help? Would the > > maintainers prefer myself or Marli re-submit the patch? > > > > The Go issue here seems particularly sticky. Even if we update the Go > > runtime, users may try and run older binaries built with older versions > of > > Go for quite some time (months? years?). Would it be better to hide this > > behind some kind of build-time flag (`--enable-sigrtmin-plus-one-proxy` > or > > something), so that some users can opt-in, but older binaries still work > as > > expected? > > > > Also, here is a link to the original thread this message is in reply to > > in-case my mail-client doesn't set up the reply properly: > > https://lists.nongnu.org/archive/html/qemu-devel/2019-07/msg01303.html > > The problem here is we break something to fix something else. > > I'm wondering if the series from Aleksandar Markovic, "linux-user: > Support signal passing for targets having more signals than host" [1] > can fix the problem in a better way? > That patch[1] (which I'll refer to as the MUX patch to avoid confusion) does not directly fix the issue addressed by this patch (re-wiring SIGRTMIN+1), but since it basically implements generic signal multiplexing, it could be re-worked to address this case as well. The way it handles `si_code` spooks me a little bit. It could easily be broken by a kernel version change, and such a breakage could be hard to detect or lead to surprising results. Other than that, it looks like a reasonable implementation. That said, overall, fixing the SIGRTMIN+1 issue using a more-generic signal-multiplexing mechanism doesn't seem *that* much better to me. It adds a lot of complexity, and only saves a single signal (assuming glibc doesn't add more reserved signals). The "big win" is additional emulation features, like those introduced in MUX patch (being able to utilize signals outside of the host range). If having those features in QEMU warrants the additional complexity, then re-working this patch on-top of that infrastructure seems like a good idea. If the maintainers want to go down that route, then I would be happy to re-work this patch utilizing the infrastructure from the MUX patch. Unfortunately it will require non-trivial changes, so it may be best to wait until that patch is merged. I could also provide a patch "on top of" the MUX patch, if that's desired/more convenient. Just one last note, if you do decide to merge the MUX patch, then it would be best to use SIGRTMAX (instead of SIGRTMAX-1) as the multiplexing signal if possible, to avoid breaking go binaries. Thanks again for taking a look at this issue. Cheers, Josh Kunz [1] http://patchwork.ozlabs.org/cover/1103565/
Re: [Qemu-devel] [PATCH 2/3] audio: paaudio: fix client name
On Mon, 2019-08-26 at 21:28 +0200, Zoltán Kővágó wrote:
> On 2019-08-26 10:21, Maxim Levitsky wrote:
> > On Mon, 2019-08-26 at 02:29 +0200, Kővágó, Zoltán wrote:
> > > pa_context_new expects a client name, not a server socket path.
> > >
> > > Signed-off-by: Kővágó, Zoltán
> > > ---
> > > audio/paaudio.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/audio/paaudio.c b/audio/paaudio.c
> > > index bfef9acaad..777b8e4718 100644
> > > --- a/audio/paaudio.c
> > > +++ b/audio/paaudio.c
> > > @@ -866,7 +866,7 @@ static void *qpa_conn_init(const char *server)
> > > }
> > >
> > > c->context =
> > > pa_context_new(pa_threaded_mainloop_get_api(c->mainloop),
> > > -server);
> > > +"qemu");
> > > if (!c->context) {
> > > goto fail;
> > > }
> >
> > Also tested, and this works.
> >
> > May I suggest though to make this configurable as well, for the sake of
> > usability since gnome sound settings show only the client name, and it
> > is per each sound card.
> > Although on the other thing the client name is qemu.
>
> There is a small problem with that. Currently we only open one
> connection to pa, even with multiple -audiodevs (they will just create
> different streams), which means we can only use a single client name per
> qemu process. Because of that, I wouldn't turn this into an audiodev
> property. Some other kind of global setting could work, but I'm not
> sure whether it's worth it or not.
>
> Regards,
> Zoltan
All right.
We could use the VM name for that though, so that at least multiple VMs
would show up as different client.
Best regards,
Maxim Levitsky
Re: [Qemu-devel] [PATCH 1/1] target/ppc: Fix do_float_check_status vs inexact
On 8/26/19 11:54 AM, Richard Henderson wrote:
> The underflow and inexact exceptions are not mutually exclusive.
> Check for both of them. Tidy the reset of FPSCR[FI].
>
> Fixes: https://bugs.launchpad.net/bugs/1841442
> Reported-by: Paul Clarke
> Signed-off-by: Richard Henderson
Tested-by: Paul Clarke
Thanks, Richard!
There seems to be a similar problem with underflow. I'll narrow down a test
case, and I guess I'll just open a new bug report.
PC
> ---
> target/ppc/fpu_helper.c | 10 +++---
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
> index 07bc9051b0..2e023c5204 100644
> --- a/target/ppc/fpu_helper.c
> +++ b/target/ppc/fpu_helper.c
> @@ -630,19 +630,15 @@ static void do_float_check_status(CPUPPCState *env,
> uintptr_t raddr)
> {
> CPUState *cs = env_cpu(env);
> int status = get_float_exception_flags(>fp_status);
> -bool inexact_happened = false;
>
> if (status & float_flag_overflow) {
> float_overflow_excp(env);
> } else if (status & float_flag_underflow) {
> float_underflow_excp(env);
> -} else if (status & float_flag_inexact) {
> -float_inexact_excp(env);
> -inexact_happened = true;
> }
> -
> -/* if the inexact flag was not set */
> -if (inexact_happened == false) {
> +if (status & float_flag_inexact) {
> +float_inexact_excp(env);
> +} else {
> env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
> }
>
>
Re: [Qemu-devel] [PATCH v2 62/68] target/arm: Convert T16, Miscellaneous 16-bit instructions
On Mon, 19 Aug 2019 at 22:39, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> diff --git a/target/arm/t16.decode b/target/arm/t16.decode
> index 98d60952a1..4ecbabd364 100644
> --- a/target/arm/t16.decode
> +++ b/target/arm/t16.decode
> @@ -210,20 +210,33 @@ REVSH 1011 1010 11 ... ...@rdm
>
> # Hints
>
> +%it_cond5:3 !function=times_2
> +
> {
> - YIELD 1011 0001
> - WFE 1011 0010
> - WFI 1011 0011
> + {
> +YIELD 1011 0001
> +WFE 1011 0010
> +WFI 1011 0011
>
> - # TODO: Implement SEV, SEVL; may help SMP performance.
> - # SEV 1011 0100
> - # SEVL1011 0101
> +# TODO: Implement SEV, SEVL; may help SMP performance.
> +# SEV 1011 0100
> +# SEVL 1011 0101
>
> - # The canonical nop has the second nibble as , but the whole of the
> - # rest of the space is a reserved hint, behaves as nop.
> - NOP 1011
> +# The canonical nop has the second nibble as , but the whole of the
> +# rest of the space is a reserved hint, behaves as nop.
> +NOP 1011
> + }
> + IT1011 ... imm:5 cond=%it_cond
This is correct (same behaviour as the old decoder, but
it looks a bit odd here because it's not the same as
the fields defined by the architecture (in particular the
'cond' field is not the same set of bits as the 'firstcond'
field). We could maybe comment it:
# Bits 7:0 in IT are architecturally simply the
# new PSTATE.IT bits (despite the instruction description
# splitting them into 'firstcond' and 'mask' fields).
# In QEMU during translation we track the IT bits using
# the DisasContext fields condexec_cond and condexec_mask,
# so here we massage the bits from the insn into the form
# that that optimization requires.
(Or equivalently we could just pass a single 8 bit immediate
to the trans_IT function and split it out there, I dunno.)
> }
>
> +# Miscellaneous 16-bit instructions
> +
> +%imm6_9_3 9:1 3:5 !function=times_2
Would it be worth adding support to the decodetree script
for letting you specify fixed bits in this kind of field-decode,
so we could write '9:1 3:5 0' rather than having to specify
a multiply-by-2 function to put the 0 bit in ? Or is it
not likely to be common enough to be worth bothering with?
(Not something for this series, anyway.)
> +
> +HLT 1011 1010 10 imm:6
> +BKPT1011 1110 imm:8
> +CBZ 1011 nz:1 0.1 . rn:3imm=%imm6_9_3
> +
> # Push and Pop
>
> %push_list 0:9 !function=t16_push_list
> --
In any case
Reviewed-by: Peter Maydell
thanks
-- PMM
Re: [Qemu-devel] [PATCH 16/25] audio: add mixeng option (documentation)
On 2019-08-26 15:35, Eric Blake wrote:
> On 8/25/19 1:46 PM, Kővágó, Zoltán wrote:
>> This will allow us to disable mixeng when we use a decent backend.
>>
>> Disabling mixeng have a few advantages:
>> * we no longer convert the audio output from one format to another, when
>> the underlying audio system would just convert it to a third format.
>> We no longer convert, only the underlying system, when needed.
>> * the underlying system probably has better resampling and sample format
>> converting methods anyway...
>> * we may support formats that the mixeng currently does not support (S24
>> or float samples, more than two channels)
>> * when using an audio server (like pulseaudio) different sound card
>> outputs will show up as separate streams, even if we use only one
>> backend
>>
>> Disadvantages:
>> * audio capturing no longer works (wavcapture, and vnc audio extension)
>> * some backends only support a single playback stream or very picky
>> about the audio format. In this case we can't disable mixeng.
>>
>> However mixeng is not removed, only made optional, so this shouldn't be
>> a big concern.
>>
>> Signed-off-by: Kővágó, Zoltán
>> ---
>> qapi/audio.json | 5 +
>> qemu-options.hx | 6 ++
>> 2 files changed, 11 insertions(+)
>>
>> diff --git a/qapi/audio.json b/qapi/audio.json
>> index 9fefdf5186..dc7f9cb1e2 100644
>> --- a/qapi/audio.json
>> +++ b/qapi/audio.json
>> @@ -11,6 +11,10 @@
>> # General audio backend options that are used for both playback and
>> # recording.
>> #
>> +# @mixeng: use QEMU's mixing engine to mix all streams inside QEMU. When
>> set to
>> +# off, fixed-settings must be also off. Not every backend
>> compatible
>> +# with the off setting (default on, since 4.2)
>> +#
>
> 'mixeng' looks like an accidental typo, when 3 words later is 'mixing'.
> Would 'mix-eng' or 'mix-engine' be more obvious?
I used the spelling used in audio/mixeng.c, if we treat it as a name
then it should be simply 'mixeng'. However I agree that it might not be
too meaningful for users, so 'mixing-engine' would make more sense, even
though it's a bit longer.
>
>
>> ##
>> { 'struct': 'AudiodevPerDirectionOptions',
>>'data': {
>> +'*mixeng': 'bool',
>> '*fixed-settings': 'bool',
>
> And the very next member is an example that QAPI doesn't have to use
> abbreviations.
>
Regards,
Zoltan
[Qemu-devel] [PATCH v2 3/4] audio: paaudio: fix client name
pa_context_new expects a client name, not a server socket path.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Maxim Levitsky
---
audio/paaudio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/audio/paaudio.c b/audio/paaudio.c
index bfef9acaad..777b8e4718 100644
--- a/audio/paaudio.c
+++ b/audio/paaudio.c
@@ -866,7 +866,7 @@ static void *qpa_conn_init(const char *server)
}
c->context = pa_context_new(pa_threaded_mainloop_get_api(c->mainloop),
-server);
+"qemu");
if (!c->context) {
goto fail;
}
--
2.22.0
[Qemu-devel] [PATCH v2 1/4] audio: fix invalid malloc size in audio_create_pdos
The code used sizeof(AudiodevAlsaPerDirectionOptions) instead of the
appropriate per direction options for the audio backend. If the size of
the actual audiodev's per direction options are larger than alsa's, it
could cause a buffer overflow.
However, alsa has three fields in per direction options: a string, an
uint32 and a bool. Oss has the same fields, coreaudio has a single
uint32, paaudio has a string and an uint32, all other backends only use
the common options, so currently no per direction options struct should
be larger than alsa's.
Signed-off-by: Kővágó, Zoltán
---
audio/audio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/audio/audio.c b/audio/audio.c
index 7d715332c9..ae335dbebb 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -1685,7 +1685,7 @@ void audio_create_pdos(Audiodev *dev)
} \
if (!dev->u.driver.has_out) { \
dev->u.driver.out = g_malloc0( \
-sizeof(AudiodevAlsaPerDirectionOptions)); \
+sizeof(Audiodev##pdo_name##PerDirectionOptions)); \
dev->u.driver.has_out = true; \
} \
break
--
2.22.0
[Qemu-devel] [PATCH v2 4/4] audio: paaudio: ability to specify stream name
This can be used to identify stream in tools like pavucontrol when one
creates multiple -audiodevs or runs multiple qemu instances.
Signed-off-by: Kővágó, Zoltán
Reviewed-by: Maxim Levitsky
---
qapi/audio.json | 6 ++
audio/paaudio.c | 4 ++--
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/qapi/audio.json b/qapi/audio.json
index 9fefdf5186..a433b3c9d7 100644
--- a/qapi/audio.json
+++ b/qapi/audio.json
@@ -206,6 +206,11 @@
#
# @name: name of the sink/source to use
#
+# @stream-name: name of the PulseAudio stream created by qemu. Can be
+# used to identify the stream in PulseAudio when you
+# create multiple PulseAudio devices or run multiple qemu
+# instances (default "qemu", since 4.2)
+#
# @latency: latency you want PulseAudio to achieve in microseconds
# (default 15000)
#
@@ -215,6 +220,7 @@
'base': 'AudiodevPerDirectionOptions',
'data': {
'*name': 'str',
+'*stream-name': 'str',
'*latency': 'uint32' } }
##
diff --git a/audio/paaudio.c b/audio/paaudio.c
index 777b8e4718..827f442b6e 100644
--- a/audio/paaudio.c
+++ b/audio/paaudio.c
@@ -562,7 +562,7 @@ static int qpa_init_out(HWVoiceOut *hw, struct audsettings
*as,
pa->stream = qpa_simple_new (
c,
-"qemu",
+ppdo->has_stream_name ? ppdo->stream_name : "qemu",
PA_STREAM_PLAYBACK,
ppdo->has_name ? ppdo->name : NULL,
,
@@ -630,7 +630,7 @@ static int qpa_init_in(HWVoiceIn *hw, struct audsettings
*as, void *drv_opaque)
pa->stream = qpa_simple_new (
c,
-"qemu",
+ppdo->has_stream_name ? ppdo->stream_name : "qemu",
PA_STREAM_RECORD,
ppdo->has_name ? ppdo->name : NULL,
,
--
2.22.0
[Qemu-devel] [PATCH v2 2/4] audio: omitting audiodev= parameter is only deprecated
Unfortunately, changes introduced in af2041ed2d "audio: audiodev=
parameters no longer optional when -audiodev present" breaks backward
compatibility. This patch changes the error into a deprecation warning.
Signed-off-by: Kővágó, Zoltán
---
qemu-deprecated.texi | 7 +++
audio/audio.c| 8
2 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi
index 00a4b6f350..9d74a1cfc0 100644
--- a/qemu-deprecated.texi
+++ b/qemu-deprecated.texi
@@ -72,6 +72,13 @@ backend settings instead of environment variables. To ease
migration to
the new format, the ``-audiodev-help'' option can be used to convert
the current values of the environment variables to ``-audiodev'' options.
+@subsection Creating sound card devices and vnc without audiodev= property
(since 4.2)
+
+When not using the deprecated legacy audio config, each sound card
+should specify an @code{audiodev=} property. Additionally, when using
+vnc, you should specify an @code{audiodev=} propery if you plan to
+transmit audio through the VNC protocol.
+
@subsection -mon ...,control=readline,pretty=on|off (since 4.1)
The @code{pretty=on|off} switch has no effect for HMP monitors, but is
diff --git a/audio/audio.c b/audio/audio.c
index ae335dbebb..e99fcd0694 100644
--- a/audio/audio.c
+++ b/audio/audio.c
@@ -1412,8 +1412,9 @@ static AudioState *audio_init(Audiodev *dev, const char
*name)
drvname = AudiodevDriver_str(dev->driver);
} else if (!QTAILQ_EMPTY(_states)) {
if (!legacy_config) {
-dolog("You must specify an audiodev= for the device %s\n", name);
-exit(1);
+dolog("Device %s: audiodev default parameter is deprecated, please
"
+ "specify audiodev=%s\n", name,
+ QTAILQ_FIRST(_states)->dev->id);
}
return QTAILQ_FIRST(_states);
} else {
@@ -1548,8 +1549,7 @@ CaptureVoiceOut *AUD_add_capture(
if (!s) {
if (!legacy_config) {
-dolog("You must specify audiodev when trying to capture\n");
-return NULL;
+dolog("Capturing without setting an audiodev is deprecated\n");
}
s = audio_init(NULL, NULL);
}
--
2.22.0
[Qemu-devel] [PATCH v2 0/4] Audio: misc fixes for "Audio 20190821 patches"
Hi, This is the second iteration of my "random fixes" patchset. Compared to v1, this has a new patch, fixing the memory error caused by an invalid malloc. Regards, Zoltan Kővágó, Zoltán (4): audio: fix invalid malloc size in audio_create_pdos audio: omitting audiodev= parameter is only deprecated audio: paaudio: fix client name audio: paaudio: ability to specify stream name qemu-deprecated.texi | 7 +++ qapi/audio.json | 6 ++ audio/audio.c| 10 +- audio/paaudio.c | 6 +++--- 4 files changed, 21 insertions(+), 8 deletions(-) -- 2.22.0
[Qemu-devel] [PATCH v3] target/xtensa: linux-user: add call0 ABI support
Xtensa binaries built for call0 ABI don't rotate register window on
function calls and returns. Invocation of signal handlers from the
kernel is therefore different in windowed and call0 ABIs.
There's currently no way to determine xtensa ELF binary ABI from the
binary itself. Add handler for the -xtensa-abi-call0 command line
parameter/QEMU_XTENSA_ABI_CALL0 envitonment variable to the qemu-user
and record ABI choice. Use it to initialize PS.WOE in xtensa_cpu_reset.
Check PS.WOE in setup_rt_frame to determine how a signal should be
delivered.
Signed-off-by: Max Filippov
---
Changes v2->v3:
- revert to checking PS.WOE in the setup_rt_frame
Changes v1->v2:
- move handling of QEMU_XTENSA_ABI_CALL0 to linux-user/main.c
- check xtensa_abi_call0 instead of PS.WOE in the setup_rt_frame
linux-user/main.c | 17 +
linux-user/xtensa/signal.c | 25 +
target/xtensa/cpu.c| 24
target/xtensa/cpu.h| 3 +++
4 files changed, 57 insertions(+), 12 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index 47917bbb20fc..9e50b2d2a92f 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -393,6 +393,13 @@ static void handle_arg_trace(const char *arg)
trace_file = trace_opt_parse(arg);
}
+#if defined(TARGET_XTENSA)
+static void handle_arg_abi_call0(const char *arg)
+{
+xtensa_set_abi_call0();
+}
+#endif
+
struct qemu_argument {
const char *argv;
const char *env;
@@ -446,6 +453,10 @@ static const struct qemu_argument arg_table[] = {
"", "[[enable=]][,events=][,file=]"},
{"version","QEMU_VERSION", false, handle_arg_version,
"", "display version information and exit"},
+#if defined(TARGET_XTENSA)
+{"xtensa-abi-call0", "QEMU_XTENSA_ABI_CALL0", false, handle_arg_abi_call0,
+ "", "assume CALL0 Xtensa ABI"},
+#endif
{NULL, NULL, false, NULL, NULL, NULL}
};
@@ -710,6 +721,12 @@ int main(int argc, char **argv, char **envp)
}
}
+#if defined(TARGET_XTENSA)
+if (getenv("QEMU_XTENSA_ABI_CALL0")) {
+xtensa_set_abi_call0();
+}
+#endif
+
target_environ = envlist_to_environ(envlist, NULL);
envlist_free(envlist);
diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c
index 8d54ef3ae34b..590f0313ffe9 100644
--- a/linux-user/xtensa/signal.c
+++ b/linux-user/xtensa/signal.c
@@ -134,6 +134,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
abi_ulong frame_addr;
struct target_rt_sigframe *frame;
uint32_t ra;
+bool abi_call0;
+unsigned base;
int i;
frame_addr = get_sigframe(ka, env, sizeof(*frame));
@@ -182,20 +184,27 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
__put_user(0x00, >retcode[5]);
#endif
}
-env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
-if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER)) {
-env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT);
-}
memset(env->regs, 0, sizeof(env->regs));
env->pc = ka->_sa_handler;
env->regs[1] = frame_addr;
env->sregs[WINDOW_BASE] = 0;
env->sregs[WINDOW_START] = 1;
-env->regs[4] = (ra & 0x3fff) | 0x4000;
-env->regs[6] = sig;
-env->regs[7] = frame_addr + offsetof(struct target_rt_sigframe, info);
-env->regs[8] = frame_addr + offsetof(struct target_rt_sigframe, uc);
+abi_call0 = (env->sregs[PS] & PS_WOE) == 0;
+env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
+
+if (abi_call0) {
+base = 0;
+env->regs[base] = ra;
+} else {
+env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT);
+base = 4;
+env->regs[base] = (ra & 0x3fff) | 0x4000;
+}
+env->regs[base + 2] = sig;
+env->regs[base + 3] = frame_addr + offsetof(struct target_rt_sigframe,
+info);
+env->regs[base + 4] = frame_addr + offsetof(struct target_rt_sigframe, uc);
unlock_user_struct(frame, frame_addr, 1);
return;
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
index 76db1741a796..c65dcf9dd782 100644
--- a/target/xtensa/cpu.c
+++ b/target/xtensa/cpu.c
@@ -53,6 +53,20 @@ static bool xtensa_cpu_has_work(CPUState *cs)
#endif
}
+#ifdef CONFIG_USER_ONLY
+static bool abi_call0;
+
+void xtensa_set_abi_call0(void)
+{
+abi_call0 = true;
+}
+
+bool xtensa_abi_call0(void)
+{
+return abi_call0;
+}
+#endif
+
/* CPUClass::reset() */
static void xtensa_cpu_reset(CPUState *s)
{
@@ -70,10 +84,12 @@ static void xtensa_cpu_reset(CPUState *s)
XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
env->pending_irq_level = 0;
#else
-env->sregs[PS] =
-(xtensa_option_enabled(env->config,
- XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) |
-PS_UM | (3 << PS_RING_SHIFT);
+env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
+if
Re: [Qemu-devel] [PATCH v2 61/68] target/arm: Convert T16, Conditional branches, Supervisor call
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 26 +++--- > target/arm/t16.decode | 12 > 2 files changed, 15 insertions(+), 23 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM
Re: [Qemu-devel] [PATCH v2] target/xtensa: linux-user: add call0 ABI support
On Mon, Aug 26, 2019 at 11:17 AM Max Filippov wrote: > > Xtensa binaries built for call0 ABI don't rotate register window on > function calls and returns. Invocation of signal handlers from the > kernel is therefore different in windowed and call0 ABIs. > There's currently no way to determine xtensa ELF binary ABI from the > binary itself. Add handler for the --xtensa-abi-call0 command line > parameter/QEMU_XTENSA_ABI_CALL0 envitonment variable to the qemu-user > and record ABI choice. Use it to initialize PS.WOE in xtensa_cpu_reset > and in setup_rt_frame to determine how a signal should be delivered. > > Signed-off-by: Max Filippov > --- > Changes v1->v2: > > - move handling of QEMU_XTENSA_ABI_CALL0 to linux-user/main.c > - check xtensa_abi_call0 instead of PS.WOE in the setup_rt_frame Thought about it some more and decided that checking PS.WOE was a better choice. Will send v3. -- Thanks. -- Max
Re: [Qemu-devel] [PATCH 0/2] tests/acceptance: Update MIPS Malta ssh test
ping 22.08.2019. 19.59, "Aleksandar Markovic" је написао/ла: > > > 22.08.2019. 05.15, "Aleksandar Markovic" је написао/ла: > > > > > > 21.08.2019. 23.00, "Eduardo Habkost" је написао/ла: > > > > > > On Wed, Aug 21, 2019 at 10:27:11PM +0200, Aleksandar Markovic wrote: > > > > 02.08.2019. 17.37, "Aleksandar Markovic" < aleksandar.marko...@rt-rk.com> је > > > > написао/ла: > > > > > > > > > > From: Aleksandar Markovic > > > > > > > > > > This little series improves linux_ssh_mips_malta.py, both in the sense > > > > > of code organization and in the sense of quantity of executed tests. > > > > > > > > > > > > > Hello, all. > > > > > > > > I am going to send a new version in few days, and I have a question for > > > > test team: > > > > > > > > Currently, the outcome of the script execition is either PASS:1 FAIL:0 or > > > > PASS:0 FAIL:1. But the test actually consists of several subtests. Is there > > > > any way that this single Python script considers these subtests as separate > > > > tests (test cases), reporting something like PASS:12 FAIL:7? If yes, what > > > > would be the best way to achieve that? > > > > > > If you are talking about each test_*() method, they are already > > > treated like separate tests. If you mean treating each > > > ssh_command_output_contains() call as a separate test, this might > > > be difficult. > > > > > > > Yes, I meant the latter one, individual code segments involving an invocation of ssh_command_output_contains() instance being treated as separate tests. > > > > Hello, Cleber, > > I am willing to rewamp python file structure if needed. > > The only thing I feel a little unconfortable is if I need to reboot the virtual machine for each case of ssh_command_output_contains(). > > Grateful in advance, > Aleksandar > > > > Cleber, is there something already available in the Avocado API > > > that would help us report more fine-grained results inside each > > > test case? > > > > > > > Thanks, that would be a better way of expressing my question. > > > > > > > > > > > > > Thanks in advance, > > > > Aleksandar > > > > > > > > > Aleksandar Markovic (2): > > > > > tests/acceptance: Refactor and improve reporting in > > > > > linux_ssh_mips_malta.py > > > > > tests/acceptance: Add new test cases in linux_ssh_mips_malta.py > > > > > > > > > > tests/acceptance/linux_ssh_mips_malta.py | 81 > > > > ++-- > > > > > 1 file changed, 66 insertions(+), 15 deletions(-) > > > > > > > > > > -- > > > > > 2.7.4 > > > > > > > > > > > > > > > > -- > > > Eduardo
Re: [Qemu-devel] [PATCH v8 00/13] Add migration support for VFIO device
Patchew URL:
https://patchew.org/QEMU/1566845753-18993-1-git-send-email-kwankh...@nvidia.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 1566845753-18993-1-git-send-email-kwankh...@nvidia.com
Subject: [Qemu-devel] [PATCH v8 00/13] Add migration support for VFIO device
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
0aeba38 vfio: Make vfio-pci device migration capable.
acc0d2b vfio: Add vfio_listener_log_sync to mark dirty pages
cb11cd6 vfio: Add function to get dirty page list
6d46042 vfio: Add load state functions to SaveVMHandlers
1f88428 vfio: Add save state functions to SaveVMHandlers
d0fbf18 vfio: Register SaveVMHandlers for VFIO device
04097e1 vfio: Add migration state change notifier
c3b9857 vfio: Add VM state change handler to know state of VM
a712a3a vfio: Add migration region initialization and finalize function
78b6920 vfio: Add save and load functions for VFIO PCI devices
032d272 vfio: Add vfio_get_object callback to VFIODeviceOps
95817ed vfio: Add function to unmap VFIO region
eaf5be5 vfio: KABI for migration interface
=== OUTPUT BEGIN ===
1/13 Checking commit eaf5be5b94f3 (vfio: KABI for migration interface)
2/13 Checking commit 95817edc42f9 (vfio: Add function to unmap VFIO region)
3/13 Checking commit 032d272ca311 (vfio: Add vfio_get_object callback to
VFIODeviceOps)
4/13 Checking commit 78b692082884 (vfio: Add save and load functions for VFIO
PCI devices)
5/13 Checking commit a712a3a74713 (vfio: Add migration region initialization
and finalize function)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#29:
new file mode 100644
ERROR: g_free(NULL) is safe this check is probably not required
#171: FILE: hw/vfio/migration.c:138:
+if (vbasedev->migration) {
+g_free(vbasedev->migration);
total: 1 errors, 1 warnings, 178 lines checked
Patch 5/13 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/13 Checking commit c3b98575e39b (vfio: Add VM state change handler to know
state of VM)
7/13 Checking commit 04097e167c8b (vfio: Add migration state change notifier)
8/13 Checking commit d0fbf181b9db (vfio: Register SaveVMHandlers for VFIO
device)
9/13 Checking commit 1f88428a8340 (vfio: Add save state functions to
SaveVMHandlers)
10/13 Checking commit 6d46042143b9 (vfio: Add load state functions to
SaveVMHandlers)
11/13 Checking commit cb11cd6229f8 (vfio: Add function to get dirty page list)
12/13 Checking commit acc0d2baac7d (vfio: Add vfio_listener_log_sync to mark
dirty pages)
13/13 Checking commit 0aeba384447b (vfio: Make vfio-pci device migration
capable.)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1566845753-18993-1-git-send-email-kwankh...@nvidia.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-de...@redhat.com
Re: [Qemu-devel] [PATCH v2 60/68] target/arm: Convert T16, push and pop
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 83 ++ > target/arm/t16.decode | 10 + > 2 files changed, 22 insertions(+), 71 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM
Re: [Qemu-devel] [PATCH v2 59/68] target/arm: Split gen_nop_hint
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Now that there all callers pass a constant value, split the switch > statement into the individual trans_* functions. s/there//. Otherwise Reviewed-by: Peter Maydell thanks -- PMM
Re: [Qemu-devel] [PATCH 2/3] audio: paaudio: fix client name
On 2019-08-26 10:21, Maxim Levitsky wrote:
> On Mon, 2019-08-26 at 02:29 +0200, Kővágó, Zoltán wrote:
>> pa_context_new expects a client name, not a server socket path.
>>
>> Signed-off-by: Kővágó, Zoltán
>> ---
>> audio/paaudio.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/audio/paaudio.c b/audio/paaudio.c
>> index bfef9acaad..777b8e4718 100644
>> --- a/audio/paaudio.c
>> +++ b/audio/paaudio.c
>> @@ -866,7 +866,7 @@ static void *qpa_conn_init(const char *server)
>> }
>>
>> c->context = pa_context_new(pa_threaded_mainloop_get_api(c->mainloop),
>> -server);
>> +"qemu");
>> if (!c->context) {
>> goto fail;
>> }
>
> Also tested, and this works.
>
> May I suggest though to make this configurable as well, for the sake of
> usability since gnome sound settings show only the client name, and it
> is per each sound card.
> Although on the other thing the client name is qemu.
There is a small problem with that. Currently we only open one
connection to pa, even with multiple -audiodevs (they will just create
different streams), which means we can only use a single client name per
qemu process. Because of that, I wouldn't turn this into an audiodev
property. Some other kind of global setting could work, but I'm not
sure whether it's worth it or not.
Regards,
Zoltan
>
> Reviewed-by: Maxim Levitsky
>
> Best regards,
> Maxim Levitsky
>
>
Re: [Qemu-devel] [PATCH v2 58/68] target/arm: Convert T16, nop hints
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 3 +-- > target/arm/t16.decode | 17 + > 2 files changed, 18 insertions(+), 2 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM
[Qemu-devel] [PATCH v8 10/13] vfio: Add load state functions to SaveVMHandlers
Sequence during _RESUMING device state:
While data for this device is available, repeat below steps:
a. read data_offset from where user application should write data.
b. write data of data_size to migration region from data_offset.
c. write data_size which indicates vendor driver that data is written in
staging buffer.
For user, data is opaque. User should write data in the same order as
received.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 170 +++
hw/vfio/trace-events | 3 +
2 files changed, 173 insertions(+)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index 3b81c1d6f5b3..765015fdc2dd 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -249,6 +249,33 @@ static int vfio_save_device_config_state(QEMUFile *f, void
*opaque)
return qemu_file_get_error(f);
}
+static int vfio_load_device_config_state(QEMUFile *f, void *opaque)
+{
+VFIODevice *vbasedev = opaque;
+uint64_t data;
+
+if (vbasedev->ops && vbasedev->ops->vfio_load_config) {
+int ret;
+
+ret = vbasedev->ops->vfio_load_config(vbasedev, f);
+if (ret) {
+error_report("%s: Failed to load device config space",
+ vbasedev->name);
+return ret;
+}
+}
+
+data = qemu_get_be64(f);
+if (data != VFIO_MIG_FLAG_END_OF_STATE) {
+error_report("%s: Failed loading device config space, "
+ "end flag incorrect 0x%"PRIx64, vbasedev->name, data);
+return -EINVAL;
+}
+
+trace_vfio_load_device_config_state(vbasedev->name);
+return qemu_file_get_error(f);
+}
+
/* -- */
static int vfio_save_setup(QEMUFile *f, void *opaque)
@@ -411,12 +438,155 @@ static int vfio_save_complete_precopy(QEMUFile *f, void
*opaque)
return ret;
}
+static int vfio_load_setup(QEMUFile *f, void *opaque)
+{
+VFIODevice *vbasedev = opaque;
+VFIOMigration *migration = vbasedev->migration;
+int ret = 0;
+
+if (migration->region.mmaps) {
+ret = vfio_region_mmap(>region);
+if (ret) {
+error_report("%s: Failed to mmap VFIO migration region %d: %s",
+ vbasedev->name, migration->region.nr,
+ strerror(-ret));
+return ret;
+}
+}
+
+ret = vfio_migration_set_state(vbasedev, VFIO_DEVICE_STATE_RESUMING, 0);
+if (ret) {
+error_report("%s: Failed to set state RESUMING", vbasedev->name);
+}
+return ret;
+}
+
+static int vfio_load_cleanup(void *opaque)
+{
+vfio_save_cleanup(opaque);
+return 0;
+}
+
+static int vfio_load_state(QEMUFile *f, void *opaque, int version_id)
+{
+VFIODevice *vbasedev = opaque;
+VFIOMigration *migration = vbasedev->migration;
+int ret = 0;
+uint64_t data, data_size;
+
+data = qemu_get_be64(f);
+while (data != VFIO_MIG_FLAG_END_OF_STATE) {
+
+trace_vfio_load_state(vbasedev->name, data);
+
+switch (data) {
+case VFIO_MIG_FLAG_DEV_CONFIG_STATE:
+{
+ret = vfio_load_device_config_state(f, opaque);
+if (ret) {
+return ret;
+}
+break;
+}
+case VFIO_MIG_FLAG_DEV_SETUP_STATE:
+{
+data = qemu_get_be64(f);
+if (data == VFIO_MIG_FLAG_END_OF_STATE) {
+return ret;
+} else {
+error_report("%s: SETUP STATE: EOS not found 0x%"PRIx64,
+ vbasedev->name, data);
+return -EINVAL;
+}
+break;
+}
+case VFIO_MIG_FLAG_DEV_DATA_STATE:
+{
+VFIORegion *region = >region;
+void *buf = NULL;
+bool buffer_mmaped = false;
+uint64_t data_offset = 0;
+
+data_size = qemu_get_be64(f);
+if (data_size == 0) {
+break;
+}
+
+ret = pread(vbasedev->fd, _offset, sizeof(data_offset),
+region->fd_offset +
+offsetof(struct vfio_device_migration_info,
+data_offset));
+if (ret != sizeof(data_offset)) {
+error_report("%s:Failed to get migration buffer data offset
%d",
+ vbasedev->name, ret);
+return -EINVAL;
+}
+
+if (region->mmaps) {
+buf = find_data_region(region, data_offset, data_size);
+}
+
+buffer_mmaped = (buf != NULL) ? true : false;
+
+if (!buffer_mmaped) {
+buf = g_try_malloc0(data_size);
+if (!buf) {
+error_report("%s: Error allocating buffer ", __func__);
+return -ENOMEM;
+}
+}
+
+qemu_get_buffer(f, buf,
Re: [Qemu-devel] [PATCH v2 57/68] target/arm: Convert T16, Reverse bytes
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 18 +++--- > target/arm/t16.decode | 9 + > 2 files changed, 12 insertions(+), 15 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM
[Qemu-devel] [PATCH v8 08/13] vfio: Register SaveVMHandlers for VFIO device
Define flags to be used as delimeter in migration file stream.
Added .save_setup and .save_cleanup functions. Mapped & unmapped migration
region from these functions at source during saving or pre-copy phase.
Set VFIO device state depending on VM's state. During live migration, VM is
running when .save_setup is called, _SAVING | _RUNNING state is set for VFIO
device. During save-restore, VM is paused, _SAVING state is set for VFIO device.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 71
hw/vfio/trace-events | 2 ++
2 files changed, 73 insertions(+)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index e97f1b0fe803..1910a913cde2 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -8,6 +8,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
#include
#include "sysemu/runstate.h"
@@ -24,6 +25,17 @@
#include "pci.h"
#include "trace.h"
+/*
+ * Flags used as delimiter:
+ * 0x => MSB 32-bit all 1s
+ * 0xef10 => emulated (virtual) function IO
+ * 0x => 16-bits reserved for flags
+ */
+#define VFIO_MIG_FLAG_END_OF_STATE (0xef11ULL)
+#define VFIO_MIG_FLAG_DEV_CONFIG_STATE (0xef12ULL)
+#define VFIO_MIG_FLAG_DEV_SETUP_STATE (0xef13ULL)
+#define VFIO_MIG_FLAG_DEV_DATA_STATE(0xef14ULL)
+
static void vfio_migration_region_exit(VFIODevice *vbasedev)
{
VFIOMigration *migration = vbasedev->migration;
@@ -106,6 +118,63 @@ static int vfio_migration_set_state(VFIODevice *vbasedev,
uint32_t set_flags,
return 0;
}
+/* -- */
+
+static int vfio_save_setup(QEMUFile *f, void *opaque)
+{
+VFIODevice *vbasedev = opaque;
+VFIOMigration *migration = vbasedev->migration;
+int ret;
+
+qemu_put_be64(f, VFIO_MIG_FLAG_DEV_SETUP_STATE);
+
+if (migration->region.mmaps) {
+qemu_mutex_lock_iothread();
+ret = vfio_region_mmap(>region);
+qemu_mutex_unlock_iothread();
+if (ret) {
+error_report("%s: Failed to mmap VFIO migration region %d: %s",
+ vbasedev->name, migration->region.index,
+ strerror(-ret));
+return ret;
+}
+}
+
+ret = vfio_migration_set_state(vbasedev, VFIO_DEVICE_STATE_SAVING, 0);
+if (ret) {
+error_report("%s: Failed to set state SAVING", vbasedev->name);
+return ret;
+}
+
+qemu_put_be64(f, VFIO_MIG_FLAG_END_OF_STATE);
+
+ret = qemu_file_get_error(f);
+if (ret) {
+return ret;
+}
+
+trace_vfio_save_setup(vbasedev->name);
+return 0;
+}
+
+static void vfio_save_cleanup(void *opaque)
+{
+VFIODevice *vbasedev = opaque;
+VFIOMigration *migration = vbasedev->migration;
+
+if (migration->region.mmaps) {
+vfio_region_unmap(>region);
+}
+trace_vfio_save_cleanup(vbasedev->name);
+}
+
+static SaveVMHandlers savevm_vfio_handlers = {
+.save_setup = vfio_save_setup,
+.save_cleanup = vfio_save_cleanup,
+};
+
+/* -- */
+
static void vfio_vmstate_change(void *opaque, int running, RunState state)
{
VFIODevice *vbasedev = opaque;
@@ -169,6 +238,8 @@ static int vfio_migration_init(VFIODevice *vbasedev,
return ret;
}
+register_savevm_live(vbasedev->dev, "vfio", -1, 1, _vfio_handlers,
+ vbasedev);
vbasedev->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change,
vbasedev);
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 69503228f20e..4bb43f18f315 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -149,3 +149,5 @@ vfio_migration_probe(char *name, uint32_t index) " (%s)
Region %d"
vfio_migration_set_state(char *name, uint32_t state) " (%s) state %d"
vfio_vmstate_change(char *name, int running, const char *reason, uint32_t
dev_state) " (%s) running %d reason %s device state %d"
vfio_migration_state_notifier(char *name, int state) " (%s) state %d"
+vfio_save_setup(char *name) " (%s)"
+vfio_save_cleanup(char *name) " (%s)"
--
2.7.0
[Qemu-devel] [PATCH v8 07/13] vfio: Add migration state change notifier
Added migration state change notifier to get notification on migration state
change. These states are translated to VFIO device state and conveyed to vendor
driver.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 28
hw/vfio/trace-events | 1 +
include/hw/vfio/vfio-common.h | 1 +
3 files changed, 30 insertions(+)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index 83057d909d49..e97f1b0fe803 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -134,6 +134,26 @@ static void vfio_vmstate_change(void *opaque, int running,
RunState state)
}
}
+static void vfio_migration_state_notifier(Notifier *notifier, void *data)
+{
+MigrationState *s = data;
+VFIODevice *vbasedev = container_of(notifier, VFIODevice, migration_state);
+int ret;
+
+trace_vfio_migration_state_notifier(vbasedev->name, s->state);
+
+switch (s->state) {
+case MIGRATION_STATUS_CANCELLING:
+case MIGRATION_STATUS_CANCELLED:
+case MIGRATION_STATUS_FAILED:
+ret = vfio_migration_set_state(vbasedev, VFIO_DEVICE_STATE_RUNNING,
+ VFIO_DEVICE_STATE_SAVING | VFIO_DEVICE_STATE_RESUMING);
+if (ret) {
+error_report("%s: Failed to set state RUNNING", vbasedev->name);
+}
+}
+}
+
static int vfio_migration_init(VFIODevice *vbasedev,
struct vfio_region_info *info)
{
@@ -152,6 +172,9 @@ static int vfio_migration_init(VFIODevice *vbasedev,
vbasedev->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change,
vbasedev);
+vbasedev->migration_state.notify = vfio_migration_state_notifier;
+add_migration_state_change_notifier(>migration_state);
+
return 0;
}
@@ -190,6 +213,11 @@ add_blocker:
void vfio_migration_finalize(VFIODevice *vbasedev)
{
+
+if (vbasedev->migration_state.notify) {
+remove_migration_state_change_notifier(>migration_state);
+}
+
if (vbasedev->vm_state) {
qemu_del_vm_change_state_handler(vbasedev->vm_state);
}
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 3d15bacd031a..69503228f20e 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -148,3 +148,4 @@ vfio_display_edid_write_error(void) ""
vfio_migration_probe(char *name, uint32_t index) " (%s) Region %d"
vfio_migration_set_state(char *name, uint32_t state) " (%s) state %d"
vfio_vmstate_change(char *name, int running, const char *reason, uint32_t
dev_state) " (%s) running %d reason %s device state %d"
+vfio_migration_state_notifier(char *name, int state) " (%s) state %d"
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 15be0358845b..dcab8a4ae0f9 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -125,6 +125,7 @@ typedef struct VFIODevice {
uint32_t device_state;
VMChangeStateEntry *vm_state;
int vm_running;
+Notifier migration_state;
} VFIODevice;
struct VFIODeviceOps {
--
2.7.0
Re: [Qemu-devel] [PATCH v2 56/68] target/arm: Convert T16, Change processor state
On Mon, 19 Aug 2019 at 22:39, Richard Henderson
wrote:
>
> Signed-off-by: Richard Henderson
> ---
> target/arm/translate.c | 85 --
> target/arm/t16.decode | 12 ++
> 2 files changed, 52 insertions(+), 45 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 414c562fb3..368f0ab147 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7474,6 +7474,11 @@ static int negate(DisasContext *s, int x)
> return -x;
> }
>
> +static int plus_2(DisasContext *s, int x)
> +{
> +return x + 2;
> +}
> +
> static int times_2(DisasContext *s, int x)
> {
> return x * 2;
> @@ -10152,6 +10157,9 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
> {
> uint32_t mask, val;
>
> +if (ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M)) {
> +return false;
> +}
I don't think this condition is quite right. We want to
do two things:
(1) this is the A/R-profile CPS, so it shouldn't
be decoded for any ARM_FEATURE_M CPU
(2) for A/R-profile, all the CPS instructions are v6-or-better
(All M-profile CPUs are at v6-or-better, which is why the
legacy decoder gets away with doing its ARCH(6) check
up front rather than only in the A/R-profile arm of its
if statement.)
> if (IS_USER(s)) {> /* Implemented as NOP in user mode. */
> return true;
> @@ -10182,6 +10190,36 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
> return true;
> }
>
> +static bool trans_CPS_v6m(DisasContext *s, arg_CPS_v6m *a)
> +{
> +TCGv_i32 tmp, addr;
> +
> +if (!(ENABLE_ARCH_6 && arm_dc_feature(s, ARM_FEATURE_M))) {
> +return false;
> +}
Similarly, this one need not check ENABLE_ARCH_6.
That is, this is the generic M-profile CPS, it's
not specific to v6M, and FEATURE_M always implies
ARCH_6 anyway. Usually we name M-profile specific
functions _v7m, not _v6m, for mostly historical
reasons relating to our having implemented v7m first,
so maybe we should follow that here. I have made
a bit of an inconsistent hash of this with the v8M
support, where sometimes I use _v8m because the
function is only in v8M and not v7M, and sometimes
_v7m because it's an M-profile function even if it
happens that it only kicks in or is called for
v8M CPUs. But we do not curretly have any functions
with a _v6m suffix so we should probably go with _v7m here.
> +if (IS_USER(s)) {
> +/* Implemented as NOP in user mode. */
> +return true;
> +}
> +
> +tmp = tcg_const_i32(a->im);
> +/* FAULTMASK */
> +if (a->F) {
> +addr = tcg_const_i32(19);
> +gen_helper_v7m_msr(cpu_env, addr, tmp);
> +tcg_temp_free_i32(addr);
> +}
> +/* PRIMASK */
> +if (a->I) {
> +addr = tcg_const_i32(16);
> +gen_helper_v7m_msr(cpu_env, addr, tmp);
> +tcg_temp_free_i32(addr);
> +}
> +tcg_temp_free_i32(tmp);
> +gen_lookup_tb(s);
> +return true;
> +}
thanks
-- PMM
[Qemu-devel] [PATCH v8 05/13] vfio: Add migration region initialization and finalize function
- Migration functions are implemented for VFIO_DEVICE_TYPE_PCI device in this
patch series.
- VFIO device supports migration or not is decided based of migration region
query. If migration region query is successful and migration region
initialization is successful then migration is supported else migration is
blocked.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/Makefile.objs | 2 +-
hw/vfio/migration.c | 140 ++
hw/vfio/trace-events | 3 +
include/hw/vfio/vfio-common.h | 11
4 files changed, 155 insertions(+), 1 deletion(-)
create mode 100644 hw/vfio/migration.c
diff --git a/hw/vfio/Makefile.objs b/hw/vfio/Makefile.objs
index abad8b818c9b..36033d1437c5 100644
--- a/hw/vfio/Makefile.objs
+++ b/hw/vfio/Makefile.objs
@@ -1,4 +1,4 @@
-obj-y += common.o spapr.o
+obj-y += common.o spapr.o migration.o
obj-$(CONFIG_VFIO_PCI) += pci.o pci-quirks.o display.o
obj-$(CONFIG_VFIO_CCW) += ccw.o
obj-$(CONFIG_VFIO_PLATFORM) += platform.o
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
new file mode 100644
index ..a1feeb7e1a5a
--- /dev/null
+++ b/hw/vfio/migration.c
@@ -0,0 +1,140 @@
+/*
+ * Migration support for VFIO devices
+ *
+ * Copyright NVIDIA, Inc. 2019
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include
+
+#include "hw/vfio/vfio-common.h"
+#include "cpu.h"
+#include "migration/migration.h"
+#include "migration/qemu-file.h"
+#include "migration/register.h"
+#include "migration/blocker.h"
+#include "migration/misc.h"
+#include "qapi/error.h"
+#include "exec/ramlist.h"
+#include "exec/ram_addr.h"
+#include "pci.h"
+#include "trace.h"
+
+static void vfio_migration_region_exit(VFIODevice *vbasedev)
+{
+VFIOMigration *migration = vbasedev->migration;
+
+if (!migration) {
+return;
+}
+
+if (migration->region.size) {
+vfio_region_exit(>region);
+vfio_region_finalize(>region);
+}
+}
+
+static int vfio_migration_region_init(VFIODevice *vbasedev, int index)
+{
+VFIOMigration *migration = vbasedev->migration;
+Object *obj = NULL;
+int ret = -EINVAL;
+
+if (!vbasedev->ops || !vbasedev->ops->vfio_get_object) {
+return ret;
+}
+
+obj = vbasedev->ops->vfio_get_object(vbasedev);
+if (!obj) {
+return ret;
+}
+
+ret = vfio_region_setup(obj, vbasedev, >region, index,
+"migration");
+if (ret) {
+error_report("%s: Failed to setup VFIO migration region %d: %s",
+ vbasedev->name, index, strerror(-ret));
+goto err;
+}
+
+if (!migration->region.size) {
+ret = -EINVAL;
+error_report("%s: Invalid region size of VFIO migration region %d: %s",
+ vbasedev->name, index, strerror(-ret));
+goto err;
+}
+
+return 0;
+
+err:
+vfio_migration_region_exit(vbasedev);
+return ret;
+}
+
+static int vfio_migration_init(VFIODevice *vbasedev,
+ struct vfio_region_info *info)
+{
+int ret;
+
+vbasedev->migration = g_new0(VFIOMigration, 1);
+
+ret = vfio_migration_region_init(vbasedev, info->index);
+if (ret) {
+error_report("%s: Failed to initialise migration region",
+ vbasedev->name);
+g_free(vbasedev->migration);
+return ret;
+}
+
+return 0;
+}
+
+/* -- */
+
+int vfio_migration_probe(VFIODevice *vbasedev, Error **errp)
+{
+struct vfio_region_info *info;
+Error *local_err = NULL;
+int ret;
+
+ret = vfio_get_dev_region_info(vbasedev, VFIO_REGION_TYPE_MIGRATION,
+ VFIO_REGION_SUBTYPE_MIGRATION, );
+if (ret) {
+goto add_blocker;
+}
+
+ret = vfio_migration_init(vbasedev, info);
+if (ret) {
+goto add_blocker;
+}
+
+trace_vfio_migration_probe(vbasedev->name, info->index);
+return 0;
+
+add_blocker:
+error_setg(>migration_blocker,
+ "VFIO device doesn't support migration");
+ret = migrate_add_blocker(vbasedev->migration_blocker, _err);
+if (local_err) {
+error_propagate(errp, local_err);
+error_free(vbasedev->migration_blocker);
+}
+return ret;
+}
+
+void vfio_migration_finalize(VFIODevice *vbasedev)
+{
+if (vbasedev->migration_blocker) {
+migrate_del_blocker(vbasedev->migration_blocker);
+error_free(vbasedev->migration_blocker);
+}
+
+vfio_migration_region_exit(vbasedev);
+
+if (vbasedev->migration) {
+g_free(vbasedev->migration);
+}
+}
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 8cdc27946cb8..191a726a1312 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -143,3 +143,6 @@ vfio_display_edid_link_up(void) ""
[Qemu-devel] [PATCH v8 11/13] vfio: Add function to get dirty page list
Dirty page tracking (.log_sync) is part of RAM copying state, where
vendor driver provides the bitmap of pages which are dirtied by vendor
driver through migration region and as part of RAM copy, those pages
gets copied to file stream.
To get dirty page bitmap:
- write start address, page_size and pfn count.
- read count of pfns copied. Vendor driver should take one of the below action:
- Vendor driver should return VFIO_DEVICE_DIRTY_PFNS_NONE if driver
doesn't have any page to report dirty in given range or rest of the range
- Vendor driver should return VFIO_DEVICE_DIRTY_PFNS_ALL to mark all pages
dirty for given range or rest of the range.
- Vendor driver should return copied_pfns and provide bitmap for copied_pfn
in migration region.
- read data_offset, where vendor driver has written bitmap.
- read bitmap from from the migration region from data_offset.
- Iterate above steps till page bitmap for all requested pfns are copied.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 123 ++
hw/vfio/trace-events | 1 +
include/hw/vfio/vfio-common.h | 2 +
3 files changed, 126 insertions(+)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index 765015fdc2dd..eff4b2a4a6e8 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -276,6 +276,129 @@ static int vfio_load_device_config_state(QEMUFile *f,
void *opaque)
return qemu_file_get_error(f);
}
+void vfio_get_dirty_page_list(VFIODevice *vbasedev,
+ uint64_t start_pfn,
+ uint64_t pfn_count,
+ uint64_t page_size)
+{
+VFIOMigration *migration = vbasedev->migration;
+VFIORegion *region = >region;
+uint64_t count = 0;
+int64_t copied_pfns = 0;
+int64_t total_pfns = pfn_count;
+int ret;
+
+qemu_mutex_lock(>lock);
+
+while (total_pfns > 0) {
+uint64_t bitmap_size, data_offset = 0;
+uint64_t start = start_pfn + count;
+void *buf = NULL;
+bool buffer_mmaped = false;
+
+ret = pwrite(vbasedev->fd, , sizeof(start),
+ region->fd_offset + offsetof(struct
vfio_device_migration_info,
+ start_pfn));
+if (ret < 0) {
+error_report("%s: Failed to set dirty pages start address %d %s",
+ vbasedev->name, ret, strerror(errno));
+goto dpl_unlock;
+}
+
+ret = pwrite(vbasedev->fd, _size, sizeof(page_size),
+ region->fd_offset + offsetof(struct
vfio_device_migration_info,
+ page_size));
+if (ret < 0) {
+error_report("%s: Failed to set dirty page size %d %s",
+ vbasedev->name, ret, strerror(errno));
+goto dpl_unlock;
+}
+
+ret = pwrite(vbasedev->fd, _pfns, sizeof(total_pfns),
+ region->fd_offset + offsetof(struct
vfio_device_migration_info,
+ total_pfns));
+if (ret < 0) {
+error_report("%s: Failed to set dirty page total pfns %d %s",
+ vbasedev->name, ret, strerror(errno));
+goto dpl_unlock;
+}
+
+/* Read copied dirty pfns */
+ret = pread(vbasedev->fd, _pfns, sizeof(copied_pfns),
+region->fd_offset + offsetof(struct vfio_device_migration_info,
+ copied_pfns));
+if (ret < 0) {
+error_report("%s: Failed to get dirty pages bitmap count %d %s",
+ vbasedev->name, ret, strerror(errno));
+goto dpl_unlock;
+}
+
+if (copied_pfns == VFIO_DEVICE_DIRTY_PFNS_NONE) {
+/*
+ * copied_pfns could be 0 if driver doesn't have any page to
+ * report dirty in given range
+ */
+break;
+} else if (copied_pfns == VFIO_DEVICE_DIRTY_PFNS_ALL) {
+/* Mark all pages dirty for this range */
+cpu_physical_memory_set_dirty_range(start * page_size,
+total_pfns * page_size,
+DIRTY_MEMORY_MIGRATION);
+break;
+}
+
+bitmap_size = BITS_TO_LONGS(copied_pfns) * sizeof(unsigned long);
+
+ret = pread(vbasedev->fd, _offset, sizeof(data_offset),
+region->fd_offset + offsetof(struct vfio_device_migration_info,
+ data_offset));
+if (ret != sizeof(data_offset)) {
+error_report("%s: Failed to get migration buffer data offset %d",
+ vbasedev->name, ret);
+goto dpl_unlock;
+}
+
+if (region->mmaps) {
+buf = find_data_region(region, data_offset,
[Qemu-devel] [PATCH v8 04/13] vfio: Add save and load functions for VFIO PCI devices
These functions save and restore PCI device specific data - config
space of PCI device.
Tested save and restore with MSI and MSIX type.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/pci.c | 168 ++
include/hw/vfio/vfio-common.h | 2 +
2 files changed, 170 insertions(+)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 56166cae824f..161068286592 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -40,6 +40,7 @@
#include "pci.h"
#include "trace.h"
#include "qapi/error.h"
+#include "migration/qemu-file.h"
#define TYPE_VFIO_PCI "vfio-pci"
#define PCI_VFIO(obj)OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI)
@@ -1618,6 +1619,55 @@ static void vfio_bars_prepare(VFIOPCIDevice *vdev)
}
}
+static int vfio_bar_validate(VFIOPCIDevice *vdev, int nr)
+{
+PCIDevice *pdev = >pdev;
+VFIOBAR *bar = >bars[nr];
+uint64_t addr;
+uint32_t addr_lo, addr_hi = 0;
+
+/* Skip unimplemented BARs and the upper half of 64bit BARS. */
+if (!bar->size) {
+return 0;
+}
+
+/* skip IO BAR */
+if (bar->ioport) {
+return 0;
+}
+
+addr_lo = pci_default_read_config(pdev, PCI_BASE_ADDRESS_0 + nr * 4, 4);
+
+addr_lo = addr_lo & (bar->ioport ? PCI_BASE_ADDRESS_IO_MASK :
+ PCI_BASE_ADDRESS_MEM_MASK);
+if (bar->type == PCI_BASE_ADDRESS_MEM_TYPE_64) {
+addr_hi = pci_default_read_config(pdev,
+ PCI_BASE_ADDRESS_0 + (nr + 1) * 4, 4);
+}
+
+addr = ((uint64_t)addr_hi << 32) | addr_lo;
+
+if (!QEMU_IS_ALIGNED(addr, bar->size)) {
+return -EINVAL;
+}
+
+return 0;
+}
+
+static int vfio_bars_validate(VFIOPCIDevice *vdev)
+{
+int i, ret;
+
+for (i = 0; i < PCI_ROM_SLOT; i++) {
+ret = vfio_bar_validate(vdev, i);
+if (ret) {
+error_report("vfio: BAR address %d validation failed", i);
+return ret;
+}
+}
+return 0;
+}
+
static void vfio_bar_register(VFIOPCIDevice *vdev, int nr)
{
VFIOBAR *bar = >bars[nr];
@@ -2400,11 +2450,129 @@ static Object *vfio_pci_get_object(VFIODevice
*vbasedev)
return OBJECT(vdev);
}
+static void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f)
+{
+VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
+PCIDevice *pdev = >pdev;
+uint16_t pci_cmd;
+int i;
+
+for (i = 0; i < PCI_ROM_SLOT; i++) {
+uint32_t bar;
+
+bar = pci_default_read_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, 4);
+qemu_put_be32(f, bar);
+}
+
+qemu_put_be32(f, vdev->interrupt);
+if (vdev->interrupt == VFIO_INT_MSI) {
+uint32_t msi_flags, msi_addr_lo, msi_addr_hi = 0, msi_data;
+bool msi_64bit;
+
+msi_flags = pci_default_read_config(pdev, pdev->msi_cap +
PCI_MSI_FLAGS,
+2);
+msi_64bit = (msi_flags & PCI_MSI_FLAGS_64BIT);
+
+msi_addr_lo = pci_default_read_config(pdev,
+ pdev->msi_cap + PCI_MSI_ADDRESS_LO,
4);
+qemu_put_be32(f, msi_addr_lo);
+
+if (msi_64bit) {
+msi_addr_hi = pci_default_read_config(pdev,
+ pdev->msi_cap +
PCI_MSI_ADDRESS_HI,
+ 4);
+}
+qemu_put_be32(f, msi_addr_hi);
+
+msi_data = pci_default_read_config(pdev,
+pdev->msi_cap + (msi_64bit ? PCI_MSI_DATA_64 :
PCI_MSI_DATA_32),
+2);
+qemu_put_be32(f, msi_data);
+} else if (vdev->interrupt == VFIO_INT_MSIX) {
+uint16_t offset;
+
+/* save enable bit and maskall bit */
+offset = pci_default_read_config(pdev,
+ pdev->msix_cap + PCI_MSIX_FLAGS + 1, 2);
+qemu_put_be16(f, offset);
+msix_save(pdev, f);
+}
+pci_cmd = pci_default_read_config(pdev, PCI_COMMAND, 2);
+qemu_put_be16(f, pci_cmd);
+}
+
+static int vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f)
+{
+VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
+PCIDevice *pdev = >pdev;
+uint32_t interrupt_type;
+uint32_t msi_flags, msi_addr_lo, msi_addr_hi = 0, msi_data;
+uint16_t pci_cmd;
+bool msi_64bit;
+int i, ret;
+
+/* retore pci bar configuration */
+pci_cmd = pci_default_read_config(pdev, PCI_COMMAND, 2);
+vfio_pci_write_config(pdev, PCI_COMMAND,
+pci_cmd & (!(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)), 2);
+for (i = 0; i < PCI_ROM_SLOT; i++) {
+uint32_t bar = qemu_get_be32(f);
+
+vfio_pci_write_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, bar, 4);
+}
+
+ret = vfio_bars_validate(vdev);
+if (ret) {
+return ret;
+}
+
+interrupt_type = qemu_get_be32(f);
+
+if (interrupt_type == VFIO_INT_MSI) {
+/* restore
[Qemu-devel] [PATCH v8 09/13] vfio: Add save state functions to SaveVMHandlers
Added .save_live_pending, .save_live_iterate and .save_live_complete_precopy
functions. These functions handles pre-copy and stop-and-copy phase.
In _SAVING|_RUNNING device state or pre-copy phase:
- read pending_bytes. If pending_bytes > 0, go through below steps.
- read data_offset - indicates kernel driver to write data to staging
buffer.
- read data_size - amount of data in bytes written by vendor driver in
migration region.
- read data_size bytes of data from data_offset in the migration region.
- Write data packet to file stream as below:
{VFIO_MIG_FLAG_DEV_DATA_STATE, data_size, actual data,
VFIO_MIG_FLAG_END_OF_STATE }
In _SAVING device state or stop-and-copy phase
a. read config space of device and save to migration file stream. This
doesn't need to be from vendor driver. Any other special config state
from driver can be saved as data in following iteration.
b. read pending_bytes. If pending_bytes > 0, go through below steps.
c. read data_offset - indicates kernel driver to write data to staging
buffer.
d. read data_size - amount of data in bytes written by vendor driver in
migration region.
e. read data_size bytes of data from data_offset in the migration region.
f. Write data packet as below:
{VFIO_MIG_FLAG_DEV_DATA_STATE, data_size, actual data}
g. iterate through steps b to f while (pending_bytes > 0)
h. Write {VFIO_MIG_FLAG_END_OF_STATE}
When data region is mapped, its user's responsibility to read data from
data_offset of data_size before moving to next steps.
.save_live_iterate runs outside the iothread lock in the migration case, which
could race with asynchronous call to get dirty page list causing data corruption
in mapped migration region. Mutex added here to serial migration buffer read
operation.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 251 ++-
hw/vfio/trace-events | 6 ++
2 files changed, 256 insertions(+), 1 deletion(-)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index 1910a913cde2..3b81c1d6f5b3 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -118,6 +118,137 @@ static int vfio_migration_set_state(VFIODevice *vbasedev,
uint32_t set_flags,
return 0;
}
+static void *find_data_region(VFIORegion *region,
+ uint64_t data_offset,
+ uint64_t data_size)
+{
+void *ptr = NULL;
+int i;
+
+for (i = 0; i < region->nr_mmaps; i++) {
+if ((data_offset >= region->mmaps[i].offset) &&
+(data_offset < region->mmaps[i].offset + region->mmaps[i].size) &&
+(data_size <= region->mmaps[i].size)) {
+ptr = region->mmaps[i].mmap + (data_offset -
+ region->mmaps[i].offset);
+break;
+}
+}
+return ptr;
+}
+
+static int vfio_save_buffer(QEMUFile *f, VFIODevice *vbasedev)
+{
+VFIOMigration *migration = vbasedev->migration;
+VFIORegion *region = >region;
+uint64_t data_offset = 0, data_size = 0;
+int ret;
+
+ret = pread(vbasedev->fd, _offset, sizeof(data_offset),
+region->fd_offset + offsetof(struct vfio_device_migration_info,
+ data_offset));
+if (ret != sizeof(data_offset)) {
+error_report("%s: Failed to get migration buffer data offset %d",
+ vbasedev->name, ret);
+return -EINVAL;
+}
+
+ret = pread(vbasedev->fd, _size, sizeof(data_size),
+region->fd_offset + offsetof(struct vfio_device_migration_info,
+ data_size));
+if (ret != sizeof(data_size)) {
+error_report("%s: Failed to get migration buffer data size %d",
+ vbasedev->name, ret);
+return -EINVAL;
+}
+
+if (data_size > 0) {
+void *buf = NULL;
+bool buffer_mmaped;
+
+if (region->mmaps) {
+buf = find_data_region(region, data_offset, data_size);
+}
+
+buffer_mmaped = (buf != NULL) ? true : false;
+
+if (!buffer_mmaped) {
+buf = g_try_malloc0(data_size);
+if (!buf) {
+error_report("%s: Error allocating buffer ", __func__);
+return -ENOMEM;
+}
+
+ret = pread(vbasedev->fd, buf, data_size,
+region->fd_offset + data_offset);
+if (ret != data_size) {
+error_report("%s: Failed to get migration data %d",
+ vbasedev->name, ret);
+g_free(buf);
+return -EINVAL;
+}
+}
+
+qemu_put_be64(f, data_size);
+qemu_put_buffer(f, buf, data_size);
+
+if (!buffer_mmaped) {
+g_free(buf);
+}
+} else {
+qemu_put_be64(f, data_size);
+}
+
+trace_vfio_save_buffer(vbasedev->name, data_offset, data_size,
[Qemu-devel] [PATCH v8 12/13] vfio: Add vfio_listener_log_sync to mark dirty pages
vfio_listener_log_sync gets list of dirty pages from vendor driver and mark
those pages dirty when in _SAVING state.
Return early for the RAM block section of mapped MMIO region.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/common.c | 35 +++
1 file changed, 35 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index c33c6684c06f..23f3d3c7c46a 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -38,6 +38,7 @@
#include "sysemu/reset.h"
#include "trace.h"
#include "qapi/error.h"
+#include "migration/migration.h"
VFIOGroupList vfio_group_list =
QLIST_HEAD_INITIALIZER(vfio_group_list);
@@ -796,9 +797,43 @@ static void vfio_listener_region_del(MemoryListener
*listener,
}
}
+static void vfio_listerner_log_sync(MemoryListener *listener,
+MemoryRegionSection *section)
+{
+uint64_t start_addr, size, pfn_count;
+VFIOGroup *group;
+VFIODevice *vbasedev;
+
+if (memory_region_is_ram_device(section->mr)) {
+return;
+}
+
+QLIST_FOREACH(group, _group_list, next) {
+QLIST_FOREACH(vbasedev, >device_list, next) {
+if (vbasedev->device_state & VFIO_DEVICE_STATE_SAVING) {
+continue;
+} else {
+return;
+}
+}
+}
+
+start_addr = TARGET_PAGE_ALIGN(section->offset_within_address_space);
+size = int128_get64(section->size);
+pfn_count = size >> TARGET_PAGE_BITS;
+
+QLIST_FOREACH(group, _group_list, next) {
+QLIST_FOREACH(vbasedev, >device_list, next) {
+vfio_get_dirty_page_list(vbasedev, start_addr >> TARGET_PAGE_BITS,
+ pfn_count, TARGET_PAGE_SIZE);
+}
+}
+}
+
static const MemoryListener vfio_memory_listener = {
.region_add = vfio_listener_region_add,
.region_del = vfio_listener_region_del,
+.log_sync = vfio_listerner_log_sync,
};
static void vfio_listener_release(VFIOContainer *container)
--
2.7.0
[Qemu-devel] [PATCH v8 02/13] vfio: Add function to unmap VFIO region
This function will be used for migration region.
Migration region is mmaped when migration starts and will be unmapped when
migration is complete.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
Reviewed-by: Cornelia Huck
---
hw/vfio/common.c | 20
hw/vfio/trace-events | 1 +
include/hw/vfio/vfio-common.h | 1 +
3 files changed, 22 insertions(+)
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 3e03c495d868..c33c6684c06f 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -966,6 +966,26 @@ int vfio_region_mmap(VFIORegion *region)
return 0;
}
+void vfio_region_unmap(VFIORegion *region)
+{
+int i;
+
+if (!region->mem) {
+return;
+}
+
+for (i = 0; i < region->nr_mmaps; i++) {
+trace_vfio_region_unmap(memory_region_name(>mmaps[i].mem),
+region->mmaps[i].offset,
+region->mmaps[i].offset +
+region->mmaps[i].size - 1);
+memory_region_del_subregion(region->mem, >mmaps[i].mem);
+munmap(region->mmaps[i].mmap, region->mmaps[i].size);
+object_unparent(OBJECT(>mmaps[i].mem));
+region->mmaps[i].mmap = NULL;
+}
+}
+
void vfio_region_exit(VFIORegion *region)
{
int i;
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index b1ef55a33ffd..8cdc27946cb8 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -111,6 +111,7 @@ vfio_region_mmap(const char *name, unsigned long offset,
unsigned long end) "Reg
vfio_region_exit(const char *name, int index) "Device %s, region %d"
vfio_region_finalize(const char *name, int index) "Device %s, region %d"
vfio_region_mmaps_set_enabled(const char *name, bool enabled) "Region %s mmaps
enabled: %d"
+vfio_region_unmap(const char *name, unsigned long offset, unsigned long end)
"Region %s unmap [0x%lx - 0x%lx]"
vfio_region_sparse_mmap_header(const char *name, int index, int nr_areas)
"Device %s region %d: %d sparse mmap entries"
vfio_region_sparse_mmap_entry(int i, unsigned long start, unsigned long end)
"sparse entry %d [0x%lx - 0x%lx]"
vfio_get_dev_region(const char *name, int index, uint32_t type, uint32_t
subtype) "%s index %d, %08x/%0x8"
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 9107bd41c030..93493891ba40 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -171,6 +171,7 @@ int vfio_region_setup(Object *obj, VFIODevice *vbasedev,
VFIORegion *region,
int index, const char *name);
int vfio_region_mmap(VFIORegion *region);
void vfio_region_mmaps_set_enabled(VFIORegion *region, bool enabled);
+void vfio_region_unmap(VFIORegion *region);
void vfio_region_exit(VFIORegion *region);
void vfio_region_finalize(VFIORegion *region);
void vfio_reset_handler(void *opaque);
--
2.7.0
[Qemu-devel] [PATCH v8 06/13] vfio: Add VM state change handler to know state of VM
VM state change handler gets called on change in VM's state. This is used to set
VFIO device state to _RUNNING.
VM state change handler, migration state change handler and log_sync listener
are called asynchronously, which sometimes lead to data corruption in migration
region. Initialised mutex that is used to serialize operations on migration data
region during saving state.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/migration.c | 67 +++
hw/vfio/trace-events | 2 ++
include/hw/vfio/vfio-common.h | 4 +++
3 files changed, 73 insertions(+)
diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c
index a1feeb7e1a5a..83057d909d49 100644
--- a/hw/vfio/migration.c
+++ b/hw/vfio/migration.c
@@ -10,6 +10,7 @@
#include "qemu/osdep.h"
#include
+#include "sysemu/runstate.h"
#include "hw/vfio/vfio-common.h"
#include "cpu.h"
#include "migration/migration.h"
@@ -74,6 +75,65 @@ err:
return ret;
}
+static int vfio_migration_set_state(VFIODevice *vbasedev, uint32_t set_flags,
+uint32_t clear_flags)
+{
+VFIOMigration *migration = vbasedev->migration;
+VFIORegion *region = >region;
+uint32_t device_state;
+int ret = 0;
+
+/* same flags should not be set or clear */
+assert(!(set_flags & clear_flags));
+
+device_state = (vbasedev->device_state | set_flags) & ~clear_flags;
+
+if ((device_state & VFIO_DEVICE_STATE_MASK) == VFIO_DEVICE_STATE_INVALID) {
+return -EINVAL;
+}
+
+ret = pwrite(vbasedev->fd, _state, sizeof(device_state),
+ region->fd_offset + offsetof(struct
vfio_device_migration_info,
+ device_state));
+if (ret < 0) {
+error_report("%s: Failed to set device state %d %s",
+ vbasedev->name, ret, strerror(errno));
+return ret;
+}
+
+vbasedev->device_state = device_state;
+trace_vfio_migration_set_state(vbasedev->name, device_state);
+return 0;
+}
+
+static void vfio_vmstate_change(void *opaque, int running, RunState state)
+{
+VFIODevice *vbasedev = opaque;
+
+if ((vbasedev->vm_running != running)) {
+int ret;
+uint32_t set_flags = 0, clear_flags = 0;
+
+if (running) {
+set_flags = VFIO_DEVICE_STATE_RUNNING;
+if (vbasedev->device_state & VFIO_DEVICE_STATE_RESUMING) {
+clear_flags = VFIO_DEVICE_STATE_RESUMING;
+}
+} else {
+clear_flags = VFIO_DEVICE_STATE_RUNNING;
+}
+
+ret = vfio_migration_set_state(vbasedev, set_flags, clear_flags);
+if (ret) {
+error_report("%s: Failed to set device state 0x%x",
+ vbasedev->name, set_flags & ~clear_flags);
+}
+vbasedev->vm_running = running;
+trace_vfio_vmstate_change(vbasedev->name, running, RunState_str(state),
+ set_flags & ~clear_flags);
+}
+}
+
static int vfio_migration_init(VFIODevice *vbasedev,
struct vfio_region_info *info)
{
@@ -89,6 +149,9 @@ static int vfio_migration_init(VFIODevice *vbasedev,
return ret;
}
+vbasedev->vm_state = qemu_add_vm_change_state_handler(vfio_vmstate_change,
+ vbasedev);
+
return 0;
}
@@ -127,6 +190,10 @@ add_blocker:
void vfio_migration_finalize(VFIODevice *vbasedev)
{
+if (vbasedev->vm_state) {
+qemu_del_vm_change_state_handler(vbasedev->vm_state);
+}
+
if (vbasedev->migration_blocker) {
migrate_del_blocker(vbasedev->migration_blocker);
error_free(vbasedev->migration_blocker);
diff --git a/hw/vfio/trace-events b/hw/vfio/trace-events
index 191a726a1312..3d15bacd031a 100644
--- a/hw/vfio/trace-events
+++ b/hw/vfio/trace-events
@@ -146,3 +146,5 @@ vfio_display_edid_write_error(void) ""
# migration.c
vfio_migration_probe(char *name, uint32_t index) " (%s) Region %d"
+vfio_migration_set_state(char *name, uint32_t state) " (%s) state %d"
+vfio_vmstate_change(char *name, int running, const char *reason, uint32_t
dev_state) " (%s) running %d reason %s device state %d"
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index f80e04e26e1f..15be0358845b 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -29,6 +29,7 @@
#ifdef CONFIG_LINUX
#include
#endif
+#include "sysemu/sysemu.h"
#define VFIO_MSG_PREFIX "vfio %s: "
@@ -121,6 +122,9 @@ typedef struct VFIODevice {
unsigned int flags;
VFIOMigration *migration;
Error *migration_blocker;
+uint32_t device_state;
+VMChangeStateEntry *vm_state;
+int vm_running;
} VFIODevice;
struct VFIODeviceOps {
--
2.7.0
[Qemu-devel] [PATCH v8 03/13] vfio: Add vfio_get_object callback to VFIODeviceOps
Hook vfio_get_object callback for PCI devices.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
Suggested-by: Cornelia Huck
Reviewed-by: Cornelia Huck
---
hw/vfio/pci.c | 8
include/hw/vfio/vfio-common.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index dc3479c374e3..56166cae824f 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -2393,10 +2393,18 @@ static void vfio_pci_compute_needs_reset(VFIODevice
*vbasedev)
}
}
+static Object *vfio_pci_get_object(VFIODevice *vbasedev)
+{
+VFIOPCIDevice *vdev = container_of(vbasedev, VFIOPCIDevice, vbasedev);
+
+return OBJECT(vdev);
+}
+
static VFIODeviceOps vfio_pci_ops = {
.vfio_compute_needs_reset = vfio_pci_compute_needs_reset,
.vfio_hot_reset_multi = vfio_pci_hot_reset_multi,
.vfio_eoi = vfio_intx_eoi,
+.vfio_get_object = vfio_pci_get_object,
};
int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp)
diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h
index 93493891ba40..771b6d59a3db 100644
--- a/include/hw/vfio/vfio-common.h
+++ b/include/hw/vfio/vfio-common.h
@@ -119,6 +119,7 @@ struct VFIODeviceOps {
void (*vfio_compute_needs_reset)(VFIODevice *vdev);
int (*vfio_hot_reset_multi)(VFIODevice *vdev);
void (*vfio_eoi)(VFIODevice *vdev);
+Object *(*vfio_get_object)(VFIODevice *vdev);
};
typedef struct VFIOGroup {
--
2.7.0
[Qemu-devel] [PATCH v8 13/13] vfio: Make vfio-pci device migration capable.
Call vfio_migration_probe() and vfio_migration_finalize() functions for
vfio-pci device to enable migration for vfio PCI device.
Removed vfio_pci_vmstate structure.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
hw/vfio/pci.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 161068286592..514cf1b0ce16 100644
--- a/hw/vfio/pci.c
+++ b/hw/vfio/pci.c
@@ -2911,6 +2911,7 @@ static void vfio_realize(PCIDevice *pdev, Error **errp)
vdev->vbasedev.ops = _pci_ops;
vdev->vbasedev.type = VFIO_DEVICE_TYPE_PCI;
vdev->vbasedev.dev = DEVICE(vdev);
+vdev->vbasedev.device_state = 0;
tmp = g_strdup_printf("%s/iommu_group", vdev->vbasedev.sysfsdev);
len = readlink(tmp, group_path, sizeof(group_path));
@@ -3171,6 +3172,12 @@ static void vfio_realize(PCIDevice *pdev, Error **errp)
}
}
+ret = vfio_migration_probe(>vbasedev, errp);
+if (ret) {
+error_report("%s: Failed to setup for migration",
+ vdev->vbasedev.name);
+}
+
vfio_register_err_notifier(vdev);
vfio_register_req_notifier(vdev);
vfio_setup_resetfn_quirk(vdev);
@@ -3190,6 +3197,7 @@ static void vfio_instance_finalize(Object *obj)
VFIOPCIDevice *vdev = PCI_VFIO(obj);
VFIOGroup *group = vdev->vbasedev.group;
+vdev->vbasedev.device_state = 0;
vfio_display_finalize(vdev);
vfio_bars_finalize(vdev);
g_free(vdev->emulated_config_bits);
@@ -3218,6 +3226,7 @@ static void vfio_exitfn(PCIDevice *pdev)
}
vfio_teardown_msi(vdev);
vfio_bars_exit(vdev);
+vfio_migration_finalize(>vbasedev);
}
static void vfio_pci_reset(DeviceState *dev)
@@ -3326,11 +3335,6 @@ static Property vfio_pci_dev_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
-static const VMStateDescription vfio_pci_vmstate = {
-.name = "vfio-pci",
-.unmigratable = 1,
-};
-
static void vfio_pci_dev_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -3338,7 +3342,6 @@ static void vfio_pci_dev_class_init(ObjectClass *klass,
void *data)
dc->reset = vfio_pci_reset;
dc->props = vfio_pci_dev_properties;
-dc->vmsd = _pci_vmstate;
dc->desc = "VFIO-based PCI device assignment";
set_bit(DEVICE_CATEGORY_MISC, dc->categories);
pdc->realize = vfio_realize;
--
2.7.0
[Qemu-devel] [PATCH v8 01/13] vfio: KABI for migration interface
- Defined MIGRATION region type and sub-type.
- Used 3 bits to define VFIO device states.
Bit 0 => _RUNNING
Bit 1 => _SAVING
Bit 2 => _RESUMING
Combination of these bits defines VFIO device's state during migration
_STOPPED => All bits 0 indicates VFIO device stopped.
_RUNNING => Normal VFIO device running state.
_SAVING | _RUNNING => vCPUs are running, VFIO device is running but start
saving state of device i.e. pre-copy state
_SAVING => vCPUs are stoppped, VFIO device should be stopped, and
save device state,i.e. stop-n-copy state
_RESUMING => VFIO device resuming state.
_SAVING | _RESUMING => Invalid state if _SAVING and _RESUMING bits are set
Bits 3 - 31 are reserved for future use. User should perform
read-modify-write operation on this field.
- Defined vfio_device_migration_info structure which will be placed at 0th
offset of migration region to get/set VFIO device related information.
Defined members of structure and usage on read/write access:
* device_state: (read/write)
To convey VFIO device state to be transitioned to. Only 3 bits are used
as of now, Bits 3 - 31 are reserved for future use.
* pending bytes: (read only)
To get pending bytes yet to be migrated for VFIO device.
* data_offset: (read only)
To get data offset in migration region from where data exist during
_SAVING, from where data should be written by user space application
during _RESUMING state and while read dirty pages bitmap.
* data_size: (read/write)
To get and set size of data copied in migration region during _SAVING
and _RESUMING state.
* start_pfn, page_size, total_pfns: (write only)
To get bitmap of dirty pages from vendor driver from given
start address for total_pfns.
* copied_pfns: (read only)
To get number of pfns bitmap copied in migration region.
Vendor driver should copy the bitmap with bits set only for
pages to be marked dirty in migration region. Vendor driver
should return VFIO_DEVICE_DIRTY_PFNS_NONE if there are 0 pages dirty in
requested range. Vendor driver should return VFIO_DEVICE_DIRTY_PFNS_ALL
to mark all pages in the section as dirty.
Migration region looks like:
--
|vfio_device_migration_info|data section |
| | /// |
--
^ ^ ^
offset 0-trapped partdata_offset data_size
Data section is always followed by vfio_device_migration_info
structure in the region, so data_offset will always be non-0.
Offset from where data is copied is decided by kernel driver, data
section can be trapped or mapped depending on how kernel driver
defines data section. If mmapped, then data_offset should be page
aligned, where as initial section which contain vfio_device_migration_info
structure might not end at offset which is page aligned.
Data_offset can be same or different for device data and dirty pages bitmap.
Vendor driver should decide whether to partition data section and how to
partition the data section. Vendor driver should return data_offset
accordingly.
For user application, data is opaque. User should write data in the same
order as received.
Signed-off-by: Kirti Wankhede
Reviewed-by: Neo Jia
---
linux-headers/linux/vfio.h | 148 +
1 file changed, 148 insertions(+)
diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h
index 24f505199f83..4bc0236b0898 100644
--- a/linux-headers/linux/vfio.h
+++ b/linux-headers/linux/vfio.h
@@ -372,6 +372,154 @@ struct vfio_region_gfx_edid {
*/
#define VFIO_REGION_SUBTYPE_IBM_NVLINK2_ATSD (1)
+/* Migration region type and sub-type */
+#define VFIO_REGION_TYPE_MIGRATION (3)
+#define VFIO_REGION_SUBTYPE_MIGRATION (1)
+
+/**
+ * Structure vfio_device_migration_info is placed at 0th offset of
+ * VFIO_REGION_SUBTYPE_MIGRATION region to get/set VFIO device related
migration
+ * information. Field accesses from this structure are only supported at their
+ * native width and alignment, otherwise the result is undefined and vendor
+ * drivers should return an error.
+ *
+ * device_state: (read/write)
+ * To indicate vendor driver the state VFIO device should be transitioned
+ * to. If device state transition fails, write on this field return error.
+ * It consists of 3 bits:
+ * - If bit 0 set, indicates _RUNNING state. When its reset, that
indicates
+ *_STOPPED state. When device is changed to _STOPPED, driver should
stop
+ *device before write() returns.
+ * - If bit 1 set, indicates _SAVING state.
+ * -
[Qemu-devel] [PATCH v8 00/13] Add migration support for VFIO device
Add migration support for VFIO device This Patch set include patches as below: - Define KABI for VFIO device for migration support. - Added save and restore functions for PCI configuration space - Generic migration functionality for VFIO device. * This patch set adds functionality only for PCI devices, but can be extended to other VFIO devices. * Added all the basic functions required for pre-copy, stop-and-copy and resume phases of migration. * Added state change notifier and from that notifier function, VFIO device's state changed is conveyed to VFIO device driver. * During save setup phase and resume/load setup phase, migration region is queried and is used to read/write VFIO device data. * .save_live_pending and .save_live_iterate are implemented to use QEMU's functionality of iteration during pre-copy phase. * In .save_live_complete_precopy, that is in stop-and-copy phase, iteration to read data from VFIO device driver is implemented till pending bytes returned by driver are not zero. * Added function to get dirty pages bitmap for the pages which are used by driver. - Add vfio_listerner_log_sync to mark dirty pages. - Make VFIO PCI device migration capable. If migration region is not provided by driver, migration is blocked. Below is the flow of state change for live migration where states in brackets represent VM state, migration state and VFIO device state as: (VM state, MIGRATION_STATUS, VFIO_DEVICE_STATE) Live migration save path: QEMU normal running state (RUNNING, _NONE, _RUNNING) | migrate_init spawns migration_thread. (RUNNING, _SETUP, _RUNNING|_SAVING) Migration thread then calls each device's .save_setup() | (RUNNING, _ACTIVE, _RUNNING|_SAVING) If device is active, get pending bytes by .save_live_pending() if pending bytes >= threshold_size, call save_live_iterate() Data of VFIO device for pre-copy phase is copied. Iterate till pending bytes converge and are less than threshold | On migration completion, vCPUs stops and calls .save_live_complete_precopy for each active device. VFIO device is then transitioned in _SAVING state. (FINISH_MIGRATE, _DEVICE, _SAVING) For VFIO device, iterate in .save_live_complete_precopy until pending data is 0. (FINISH_MIGRATE, _DEVICE, _STOPPED) | (FINISH_MIGRATE, _COMPLETED, STOPPED) Migraton thread schedule cleanup bottom half and exit Live migration resume path: Incomming migration calls .load_setup for each device (RESTORE_VM, _ACTIVE, STOPPED) | For each device, .load_state is called for that device section data | At the end, called .load_cleanup for each device and vCPUs are started. | (RUNNING, _NONE, _RUNNING) Note that: - Migration post copy is not supported. v7 -> v8: - Updated comments for KABI - Added BAR address validation check during PCI device's config space load as suggested by Dr. David Alan Gilbert. - Changed vfio_migration_set_state() to set or clear device state flags. - Some nit fixes. v6 -> v7: - Fix build failures. v5 -> v6: - Fix build failure. v4 -> v5: - Added decriptive comment about the sequence of access of members of structure vfio_device_migration_info to be followed based on Alex's suggestion - Updated get dirty pages sequence. - As per Cornelia Huck's suggestion, added callbacks to VFIODeviceOps to get_object, save_config and load_config. - Fixed multiple nit picks. - Tested live migration with multiple vfio device assigned to a VM. v3 -> v4: - Added one more bit for _RESUMING flag to be set explicitly. - data_offset field is read-only for user space application. - data_size is read for every iteration before reading data from migration, that is removed assumption that data will be till end of migration region. - If vendor driver supports mappable sparsed region, map those region during setup state of save/load, similarly unmap those from cleanup routines. - Handles race condition that causes data corruption in migration region during save device state by adding mutex and serialiaing save_buffer and get_dirty_pages routines. - Skip called get_dirty_pages routine for mapped MMIO region of device. - Added trace events. - Splitted into multiple functional patches. v2 -> v3: - Removed enum of VFIO device states. Defined VFIO device state with 2 bits. - Re-structured vfio_device_migration_info to keep it minimal and defined action on read and write access on its members. v1 -> v2: - Defined MIGRATION region type and sub-type which should be used with region type capability. - Re-structured vfio_device_migration_info. This structure will be placed at 0th offset of migration region. - Replaced ioctl with read/write for trapped part of migration region. - Added both type of
[Qemu-devel] [Bug 1839060] Re: HDA device non functional in Windows 10 1903
Created Windows feedback as instructed by Andre: https://aka.ms/AA5wlk7 Please upvote this to get attention by Microsoft. -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1839060 Title: HDA device non functional in Windows 10 1903 Status in QEMU: New Bug description: I made the update to 1903, and the HDA device stopped working. The driver says the device is working correctly, but it does not. When I try to open the Windows sound configuration, the dialog hangs and never shows it's content. Several people reported this back in May: https://windowsreport.com/windows-10-v1903-ich6-ich9-virtio/ I can confirm I have exactly the same problem. Host is Arch Linux, current (5.2.5) kernel, QEMU 4.0. I enabled HDA debug output and compared an older, working Windows version to 1903, but could not see the difference. The driver seems to issue the same verbs. I am happy to provide additional information if needed. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1839060/+subscriptions
Re: [Qemu-devel] [PATCH v2 55/68] target/arm: Convert T16, extract
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 14 +- > target/arm/t16.decode | 10 ++ > 2 files changed, 11 insertions(+), 13 deletions(-) Reviewed-by: Peter Maydell thanks -- PMM
Re: [Qemu-devel] [PATCH v2 54/68] target/arm: Convert T16 adjust sp (immediate)
On Mon, 19 Aug 2019 at 22:39, Richard Henderson wrote: > > Signed-off-by: Richard Henderson > --- > target/arm/translate.c | 15 ++- > target/arm/t16.decode | 9 + > 2 files changed, 11 insertions(+), 13 deletions(-) > Reviewed-by: Peter Maydell thanks -- PMM
[Qemu-devel] GSoC project: API Documentation Generation links and comments
I've uploaded to my github repository¹ the work done so far. Using Peter's patches as a starting point, we were able to generate kernel-docs documentation for some of QEMU's APIs. After studying the available options, we found a nice solution to publish the documentation online and keep it updated, using Github Pages and Travis CI. The idea is to use QEMU's Github mirror, updating the documentation (located on a gh-pages branch) with every push done to the master branch. I've implemented this and it's available at a Github Page² on a gh-pages branch managed by travis jobs. The default theme needs better structure, but a search in existing documentation is possible as an out-of-the-box feature. My work is not done yet, as I still need to rebase my commits to obtain a proper format for RFCs and figure out a better alternative to deal with the massive number of warnings that happen when generating the documentation. I'll keep working on it and welcome any feedback from you. I'm available to answer all questions you might have. [1] https://github.com/gsb16/qemu [2] https://gsb16.github.io/qemu/ Kind Regards, Gabriel Barreto
