Re: [Qemu-devel] [Consult] tilegx: About floating point instructions
On 8/4/15 00:40, Richard Henderson wrote: On 08/01/2015 02:47 AM, Chen Gang wrote: I am just adding floating point instructions (e.g. fsingle_add1), but for me, I can not find any details about them (the ISA documents only give a summary description, but not details), e.g. The tilegx splits the four/six cycle arithmetic into multiple black-box instructions. You need only really implement one of the four, with the rest of them being implemented as nops or moves. Looking at what gcc produces gives the hints: fdouble_unpack_minmin, srca, srcb fdouble_unpack_max max, srca, srcb fdouble_add_flagsflg, srca, srcb fdouble_addsub max, min, flg fdouble_pack1 dst, max, flg fdouble_pack2 dst, max, zero The unpack, addsub, and pack2 insns can be ignored, the add_flags insn can perform the whole operation, the pack1 insn performs a move from flg to dst. Similarly for the single-precision: fsingle_add1 tmp, srca, srcb fsingle_addsub2 tmp, srca, srcb fsingle_pack1 flg, tmp fsingle_pack2 dst, tmp, flg The add1 insn performs the whole operation, the addsub2 and pack1 insns are ignored, and the pack2 insn is a move from tmp to dst. Thank you very much. I am just analyzing the template file (tilegx.md) and testsuite executable file (2603-1.exe) for it. Your information is really valuable to me! :-) And still welcome any additional information for it: especially related details documentations which should be more 'standard' than the third- party's implementation (e.g. gcc implementation). I shall try to let qemu tilegx support gcc testsuite successfully within this month. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [Consult] tilegx: About floating point instructions
Hello All: I am just adding floating point instructions (e.g. fsingle_add1), but for me, I can not find any details about them (the ISA documents only give a summary description, but not details), e.g. fsingle_add1 Floating Point Single Precision Add Part 1 Syntax fsingle_add1 Dest, SrcA, SrcB Example fsingle_add1 r5, r6, r7 Description Performs the first part of a floating point single precision add. This instruction also sets the floating point comparison flags in the destination register (see Table 7-2 on page 135). Functional Description rf[Dest] = fsingle_addsub1 (rf[SrcA], rf[SrcB], false); (there is no additional information for fsingle_addsub1, and Table 7-2 will set 'Dest', is 'Dest' only for the comparison flags?). At present, for me, the only way for finding the related details are gcc source. But I am just testing gcc (when testing gcc, I found I have to implement floating point instructions), so it is not a quite well way. Welcome any additional information, ideas or suggestions. (By the way, I have implemented 'iret' instruction, for me, we can just skip it for linux user. Also welcome any additional ideas, suggestions, and completions for it). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH] xen: Drop net_rx_ok
On 7/27/15 21:16, Stefan Hajnoczi wrote:
On Mon, Jul 20, 2015 at 06:12:09PM +0100, Stefan Hajnoczi wrote:
On Thu, Jul 02, 2015 at 01:39:16PM +0100, Stefan Hajnoczi wrote:
On Tue, Jun 30, 2015 at 10:42:37AM +0800, Fam Zheng wrote:
This is necessary because once we return false from .can_receive, we
need to flush the queue when the .can_receive conditions become true
again, (for example when more buffer is available).
We can rely on net_rx_packet (which checks the same conditions) to drop
the packet if the device is not ready, so drop net_xen_info.can_receive.
This patch changes behavior:
Previously can_receive() false meant packets are queued.
Now those same conditions result in net_rx_packet() returning -1, so
packets are discarded.
In order to keep the spirit of the queuing mechanism - where we tell a
sender to hold off until more rx buffers become available - I think the
following line in net_rx_packet() needs to be changed:
if (rc == rp || RING_REQUEST_CONS_OVERFLOW(netdev-rx_ring, rc)) {
xen_be_printf(netdev-xendev, 2, no buffer, drop packet\n);
return -1; -- this should be changed to return 0
}
That change assumes that net_event()'s flush is always called when the
rx ring gets more free space.
Any thoughts from Xen folks?
Ping?
Need input from Xen developers.
Ping?
In fact, I am not Xen folks. But I shall provide my idea for it, since
Cc to me.
For me, it is reasonable to use return 0 instead of return -1.
- It completes the current API and keep compatible with the original
usage. As return size, it needs to consider about all numbers (zero,
negative, and positive numbers, like e.g. standard read/write API).
- Comparing with all the other NetClientInfo.receive providers, some of
them consider about it (e.g. virtio), others not (maybe each of them
have their own reasons -- e.g. hardware will never generate 0 size).
Welcome any other members' ideas, suggestions and completions.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v12] target-tilegx: Generate tcg instructions to finish Hello world
On 6/13/15 21:21, Chen Gang wrote:
+static void gen_st_add(struct DisasContext *dc,
+ uint8_t rsrc, uint8_t rsrcb, uint8_t imm8,
It needs int8_t instead of uint8_t for imm8, or it will cause memmove()
of glibc generates incorrect result with -O1/2/s optimization.
And tilegx linux-user still has another issues (at least 1 another bug),
I shall continue analyzing, hope I can finish them within this month.
Thanks.
+ TCGMemOp ops, const char *code)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, %s r%d, r%d, %d\n,
+ code, rsrc, rsrcb, imm8);
+tcg_gen_qemu_st_i64(load_gr(dc, rsrcb), load_gr(dc, rsrc),
+MMU_USER_IDX, ops);
+tcg_gen_addi_i64(dest_gr(dc, rsrc), load_gr(dc, rsrc), imm8);
+}
+
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v12] target-tilegx: Generate tcg instructions to finish Hello world
On 6/13/15 21:21, Chen Gang wrote:
+
+static void decode_x1(struct DisasContext *dc, tilegx_bundle_bits bundle)
+{
+unsigned int opcode = get_Opcode_X1(bundle);
+uint8_t rsrc = (uint8_t)get_SrcA_X1(bundle);
+uint8_t rdst = (uint8_t)get_Dest_X1(bundle);
+int16_t imm16 = (int16_t)get_Imm16_X1(bundle);
+
These type cast should be removed.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v12] target-tilegx: Generate tcg instructions to finish Hello world
On 7/19/15 17:42, Chen Gang wrote:
On 6/13/15 21:21, Chen Gang wrote:
+static void gen_st_add(struct DisasContext *dc,
+ uint8_t rsrc, uint8_t rsrcb, uint8_t imm8,
It needs int8_t instead of uint8_t for imm8, or it will cause memmove()
of glibc generates incorrect result with -O1/2/s optimization.
This bug causes many various issues: after fix this bug, vi is OK.
Now, I am analyzing another issue, it is about stat64 failure issue.
Thanks
And tilegx linux-user still has another issues (at least 1 another bug),
I shall continue analyzing, hope I can finish them within this month.
Thanks.
+ TCGMemOp ops, const char *code)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, %s r%d, r%d, %d\n,
+ code, rsrc, rsrcb, imm8);
+tcg_gen_qemu_st_i64(load_gr(dc, rsrcb), load_gr(dc, rsrc),
+MMU_USER_IDX, ops);
+tcg_gen_addi_i64(dest_gr(dc, rsrc), load_gr(dc, rsrc), imm8);
+}
+
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v12] linux-user: Support tilegx architecture in linux-user
On 6/13/15 21:10, Chen Gang wrote:
+
+void cpu_loop(CPUTLGState *env)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+int trapnr;
+
+while (1) {
+cpu_exec_start(cs);
+trapnr = cpu_tilegx_exec(env);
+cpu_exec_end(cs);
+switch (trapnr) {
+case TILEGX_EXCP_SYSCALL:
+env-regs[TILEGX_R_RE] = do_syscall(env, env-regs[TILEGX_R_NR],
+env-regs[0], env-regs[1],
+env-regs[2], env-regs[3],
+env-regs[4], env-regs[5],
+env-regs[6], env-regs[7]);
+env-regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env-regs[TILEGX_R_RE])
+ ?
env-regs[TILEGX_R_RE]
It needs - env-regs[TILEGX_R_RE] instead of env-regs[TILEGX_R_RE].
For stat64, when return ENOENT, qemu will mark it as -ENOENT, so syscall
should revert it again.
+ : 0;
+break;
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v12] linux-user: Support tilegx architecture in linux-user
On 7/19/15 19:31, Chen Gang wrote:
On 6/13/15 21:10, Chen Gang wrote:
+
+void cpu_loop(CPUTLGState *env)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+int trapnr;
+
+while (1) {
+cpu_exec_start(cs);
+trapnr = cpu_tilegx_exec(env);
+cpu_exec_end(cs);
+switch (trapnr) {
+case TILEGX_EXCP_SYSCALL:
+env-regs[TILEGX_R_RE] = do_syscall(env, env-regs[TILEGX_R_NR],
+env-regs[0], env-regs[1],
+env-regs[2], env-regs[3],
+env-regs[4], env-regs[5],
+env-regs[6], env-regs[7]);
+env-regs[TILEGX_R_ERR] =
TILEGX_IS_ERRNO(env-regs[TILEGX_R_RE])
+ ?
env-regs[TILEGX_R_RE]
It needs - env-regs[TILEGX_R_RE] instead of env-regs[TILEGX_R_RE].
For stat64, when return ENOENT, qemu will mark it as -ENOENT, so syscall
should revert it again.
After this fix, the tilegx linux-user can let busybox pass simple test
(manually using sh, ls, cp, mv, and vi are OK).
Next, I shall start gcc testsuite with tilegx linux-user. :-)
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 07/07/2015 08:19 AM, Chris Metcalf wrote: I will be posting more hardware documents on Wednesday when I'm back in the office. That is good news! Thanks. And at present, I am just analyzing the issue about the vi of busybox with the static glibc (displaying and modifying contents through vi under tilegx qemu have bugs). Hope I can finish within this month (I also have to do some kernel and gcc related things in my free time during this month). Thanks. On Jun 4, 2015, at 5:33 AM, Chen Gang xili_gchen_5...@hotmail.com wrote: On 06/03/2015 11:47 PM, Richard Henderson wrote: On 06/03/2015 05:34 AM, Peter Maydell wrote: You must do something. You can't allow guest code (even broken guest code) to make QEMU assert. You need to find out what the hardware does here, and do that. These are I/O registers for IPC. I believe that the best thing to do is assume protection is enabled at the kernel level, and thus raise the appropriate exception: SN_ACCESS, IDN_ACCESS, UDN_ACCESS. OK, thanks That said, I don't have the system architecture manual handy to check the full details. Fortunately, Chris knows more about it, and provide more valuable details for it. And welcome any members to provide related pdf documents, if possible. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 07/07/2015 08:19 AM, Chris Metcalf wrote: I will be posting more hardware documents on Wednesday when I'm back in the office. That is good news! Thanks. And at present, I am just analyzing the issue about the vi of busybox with the static glibc (displaying and modifying contents through vi under tilegx qemu have bugs). Hope I can finish within this month (I also have to do some kernel and gcc related things in my free time during this month). Thanks. On Jun 4, 2015, at 5:33 AM, Chen Gang xili_gchen_5...@hotmail.com wrote: On 06/03/2015 11:47 PM, Richard Henderson wrote: On 06/03/2015 05:34 AM, Peter Maydell wrote: You must do something. You can't allow guest code (even broken guest code) to make QEMU assert. You need to find out what the hardware does here, and do that. These are I/O registers for IPC. I believe that the best thing to do is assume protection is enabled at the kernel level, and thus raise the appropriate exception: SN_ACCESS, IDN_ACCESS, UDN_ACCESS. OK, thanks That said, I don't have the system architecture manual handy to check the full details. Fortunately, Chris knows more about it, and provide more valuable details for it. And welcome any members to provide related pdf documents, if possible. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 00/10 v12] tilegx: Firstly add tilegx target for linux-user
Today, I shall continue to try the test for qemu linux-user, and try to finish gcc testsuite within this month. Welcome any ideas, suggestions, and completions. Thanks. On 06/19/2015 09:12 AM, Chen Gang wrote: On 06/19/2015 06:02 AM, Peter Maydell wrote: On 13 June 2015 at 14:07, Chen Gang xili_gchen_5...@hotmail.com wrote: It can finish running Hello world elf64 binary, and the related test cases: - with --enable-debug, enable assertion with -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/a.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/b.log - without --enable-debug, disable assertion with -O2 -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/c.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/d.log Chen Gang (10): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Generate tcg instructions to finish Hello world target-tilegx: Add TILE-Gx building files I gave some of these my reviewed-by: tag in v11. Please don't just drop that, it wastes my time when I end up re-looking at patches I've already reviewed. OK, thanks. I shall notice next time (Add reviewer's Reviewed-by in the already reviewed patches in the re-send patches). Anyway, you can add my Reviewed-by: tag to patches 1-7 and 10. I'll let rth do patches 8 and 9. OK, thanks. And excuse me, I am not quite familiar with the related working flow: - Shall I apply these patches (with the Reviewed-by tags)? or anyone else help to do it? - If I shall be the maintainer of tilegx, what shall I do next (e.g. add an item to MAINTAINER, the working flow as an maintainer, next) For me, next (after current patches are applied): - Give a common test (may send bug fix patches): Let busybox work (e.g. sh, ls, cp, mv, vi) Finish DejaGNU gcc testsuite for tilegx (which is my original goal). - Finish all instructions of tilegx (then send the new patches). - Try qemu system mode for tilegx (hope I can finish within this year). Opinions on whether we should put this series into master now (assuming 8 and 9 are good), or delay until after 2.4 release? OK, thanks. And welcome any other members' ideas, suggestions and completions. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 00/10 v12] tilegx: Firstly add tilegx target for linux-user
On 06/19/2015 06:02 AM, Peter Maydell wrote: On 13 June 2015 at 14:07, Chen Gang xili_gchen_5...@hotmail.com wrote: It can finish running Hello world elf64 binary, and the related test cases: - with --enable-debug, enable assertion with -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/a.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/b.log - without --enable-debug, disable assertion with -O2 -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/c.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/d.log Chen Gang (10): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Generate tcg instructions to finish Hello world target-tilegx: Add TILE-Gx building files I gave some of these my reviewed-by: tag in v11. Please don't just drop that, it wastes my time when I end up re-looking at patches I've already reviewed. OK, thanks. I shall notice next time (Add reviewer's Reviewed-by in the already reviewed patches in the re-send patches). Anyway, you can add my Reviewed-by: tag to patches 1-7 and 10. I'll let rth do patches 8 and 9. OK, thanks. And excuse me, I am not quite familiar with the related working flow: - Shall I apply these patches (with the Reviewed-by tags)? or anyone else help to do it? - If I shall be the maintainer of tilegx, what shall I do next (e.g. add an item to MAINTAINER, the working flow as an maintainer, next) For me, next (after current patches are applied): - Give a common test (may send bug fix patches): Let busybox work (e.g. sh, ls, cp, mv, vi) Finish DejaGNU gcc testsuite for tilegx (which is my original goal). - Finish all instructions of tilegx (then send the new patches). - Try qemu system mode for tilegx (hope I can finish within this year). Opinions on whether we should put this series into master now (assuming 8 and 9 are good), or delay until after 2.4 release? OK, thanks. And welcome any other members' ideas, suggestions and completions. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH 01/10 v12] linux-user: tilegx: Firstly add architecture related features
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/tilegx/syscall.h| 40 +
linux-user/tilegx/syscall_nr.h | 324 +
linux-user/tilegx/target_cpu.h | 35
linux-user/tilegx/target_signal.h | 28
linux-user/tilegx/target_structs.h | 46 ++
linux-user/tilegx/termbits.h | 274 +++
6 files changed, 747 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 000..653ece1
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,40 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE tilegx
+#define UNAME_MINIMUM_RELEASE 3.19
+
+#define MMAP_SHIFT TARGET_PAGE_BITS
+
+#define TILEGX_IS_ERRNO(ret) \
+ ((ret) 0xf000ULL) /* errno is 0 -- 4096 */
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+union {
+/* Saved main processor registers; 56..63 are special. */
+tilegx_reg_t regs[56];
+struct {
+tilegx_reg_t __regs[53];
+tilegx_reg_t tp;/* aliases regs[TREG_TP] */
+tilegx_reg_t sp;/* aliases regs[TREG_SP] */
+tilegx_reg_t lr;/* aliases regs[TREG_LR] */
+};
+};
+
+/* Saved special registers. */
+tilegx_reg_t pc;/* stored in EX_CONTEXT_K_0 */
+tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+tilegx_reg_t flags; /* flags (see below) */
+tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+#endif
diff --git a/linux-user/tilegx/syscall_nr.h b/linux-user/tilegx/syscall_nr.h
new file mode 100644
index 000..1dca348
--- /dev/null
+++ b/linux-user/tilegx/syscall_nr.h
@@ -0,0 +1,324 @@
+#ifndef TILEGX_SYSCALL_NR
+#define TILEGX_SYSCALL_NR
+
+/*
+ * Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr12
+#define TARGET_NR_flistxattr13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd17
+#define TARGET_NR_lookup_dcookie18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set30
+#define TARGET_NR_ioprio_get31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root41
+#define TARGET_NR_nfsservctl42
+#define TARGET_NR_statfs43
[Qemu-devel] [PATCH 05/10 v12] target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
unsigned long long
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/opcode_tilegx.h | 220 +-
1 file changed, 110 insertions(+), 110 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index d76ff2d..33b71a9 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -23,7 +23,7 @@
#ifndef __ASSEMBLER__
-typedef unsigned long long tilegx_bundle_bits;
+typedef uint64_t tilegx_bundle_bits;
/* These are the bits that determine if a bundle is in the X encoding. */
#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
@@ -66,360 +66,360 @@ typedef tilegx_bundle_bits tile_bundle_bits;
/* 64-bit pattern for a { bpt ; nop } bundle. */
#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-static __inline unsigned int
+static inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 24)) 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 18)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x0001ffc0);
}
-static __inline unsigned int
+static inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 54)) 0x1f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 43)) 0x00c0);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 20)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 51)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x7ff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 58)) 0x1);
}
-static __inline unsigned int
+static inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 37)) 0x3fff);
}
-static __inline unsigned int
+static inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x3fc0);
}
-static __inline unsigned int
+static inline unsigned int
get_Mode(tilegx_bundle_bits n)
{
return (((unsigned int)(n 62)) 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 28)) 0x7);
}
-static __inline unsigned int
+static inline unsigned int
[Qemu-devel] [PATCH 06/10 v12] target-tilegx: Add special register information from Tilera Corporation
The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h diff --git a/target-tilegx/spr_def_64.h b/target-tilegx/spr_def_64.h new file mode 100644 index 000..67a6c17 --- /dev/null +++ b/target-tilegx/spr_def_64.h @@ -0,0 +1,216 @@ +/* + * Copyright 2011 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#ifndef __DOXYGEN__ + +#ifndef __ARCH_SPR_DEF_64_H__ +#define __ARCH_SPR_DEF_64_H__ + +#define SPR_AUX_PERF_COUNT_0 0x2105 +#define SPR_AUX_PERF_COUNT_1 0x2106 +#define SPR_AUX_PERF_COUNT_CTL 0x2107 +#define SPR_AUX_PERF_COUNT_STS 0x2108 +#define SPR_CMPEXCH_VALUE 0x2780 +#define SPR_CYCLE 0x2781 +#define SPR_DONE 0x2705 +#define SPR_DSTREAM_PF 0x2706 +#define SPR_EVENT_BEGIN 0x2782 +#define SPR_EVENT_END 0x2783 +#define SPR_EX_CONTEXT_0_0 0x2580 +#define SPR_EX_CONTEXT_0_1 0x2581 +#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_1_0 0x2480 +#define SPR_EX_CONTEXT_1_1 0x2481 +#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_2_0 0x2380 +#define SPR_EX_CONTEXT_2_1 0x2381 +#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 +#define SPR_FAIL 0x2707 +#define SPR_IDN_AVAIL_EN 0x1a05 +#define SPR_IDN_DATA_AVAIL 0x0a80 +#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 +#define SPR_IDN_DEMUX_COUNT_0 0x0a05 +#define SPR_IDN_DEMUX_COUNT_1 0x0a06 +#define SPR_IDN_DIRECTION_PROTECT 0x1405 +#define SPR_IDN_PENDING 0x0a08 +#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 +#define SPR_INTCTRL_0_STATUS 0x2505 +#define SPR_INTCTRL_1_STATUS 0x2405 +#define SPR_INTCTRL_2_STATUS 0x2305 +#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 +#define SPR_INTERRUPT_MASK_0 0x2506 +#define SPR_INTERRUPT_MASK_1 0x2406 +#define SPR_INTERRUPT_MASK_2 0x2306 +#define SPR_INTERRUPT_MASK_RESET_0 0x2507 +#define SPR_INTERRUPT_MASK_RESET_1 0x2407 +#define SPR_INTERRUPT_MASK_RESET_2 0x2307 +#define SPR_INTERRUPT_MASK_SET_0 0x2508 +#define SPR_INTERRUPT_MASK_SET_1 0x2408 +#define SPR_INTERRUPT_MASK_SET_2 0x2308 +#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 +#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 +#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 +#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 +#define SPR_IPI_EVENT_0 0x1f05 +#define SPR_IPI_EVENT_1 0x1e05 +#define SPR_IPI_EVENT_2 0x1d05 +#define SPR_IPI_EVENT_RESET_0 0x1f06 +#define SPR_IPI_EVENT_RESET_1 0x1e06 +#define SPR_IPI_EVENT_RESET_2 0x1d06 +#define SPR_IPI_EVENT_SET_0 0x1f07 +#define SPR_IPI_EVENT_SET_1 0x1e07 +#define SPR_IPI_EVENT_SET_2 0x1d07 +#define SPR_IPI_MASK_0 0x1f08 +#define SPR_IPI_MASK_1 0x1e08 +#define SPR_IPI_MASK_2 0x1d08 +#define SPR_IPI_MASK_RESET_0 0x1f09 +#define SPR_IPI_MASK_RESET_1 0x1e09 +#define SPR_IPI_MASK_RESET_2 0x1d09 +#define SPR_IPI_MASK_SET_0 0x1f0a +#define SPR_IPI_MASK_SET_1 0x1e0a +#define SPR_IPI_MASK_SET_2 0x1d0a +#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 +#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 +#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 +#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 +#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 +#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 +#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 +#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 +#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 +#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 +#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 +#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 +#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 +#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 +#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 +#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 +#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 +#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 +#define SPR_MPL_IDN_TIMER_SET_0 0x1800 +#define SPR_MPL_IDN_TIMER_SET_1 0x1801 +#define SPR_MPL_IDN_TIMER_SET_2 0x1802 +#define
[Qemu-devel] [PATCH 07/10 v12] target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu.c | 143 ++
target-tilegx/cpu.h | 175
2 files changed, 318 insertions(+)
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
new file mode 100644
index 000..663fcb6
--- /dev/null
+++ b/target-tilegx/cpu.c
@@ -0,0 +1,143 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include hw/qdev-properties.h
+#include migration/vmstate.h
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model)
+{
+TileGXCPU *cpu;
+
+cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
+return cpu;
+}
+
+static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+TileGXCPU *cpu = TILEGX_CPU(cs);
+
+cpu-env.pc = value;
+}
+
+static bool tilegx_cpu_has_work(CPUState *cs)
+{
+return true;
+}
+
+static void tilegx_cpu_reset(CPUState *s)
+{
+TileGXCPU *cpu = TILEGX_CPU(s);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
+CPUTLGState *env = cpu-env;
+
+tcc-parent_reset(s);
+
+memset(env, 0, sizeof(CPUTLGState));
+tlb_flush(s, 1);
+}
+
+static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+CPUState *cs = CPU(dev);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
+
+cpu_reset(cs);
+qemu_init_vcpu(cs);
+
+tcc-parent_realize(dev, errp);
+}
+
+static void tilegx_cpu_initfn(Object *obj)
+{
+CPUState *cs = CPU(obj);
+TileGXCPU *cpu = TILEGX_CPU(obj);
+CPUTLGState *env = cpu-env;
+static bool tcg_initialized;
+
+cs-env_ptr = env;
+cpu_exec_init(env);
+
+if (tcg_enabled() !tcg_initialized) {
+tcg_initialized = true;
+tilegx_tcg_init();
+}
+}
+
+static void tilegx_cpu_do_interrupt(CPUState *cs)
+{
+cs-exception_index = -1;
+}
+
+static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
+{
+cpu_dump_state(cs, stderr, fprintf, 0);
+return 1;
+}
+
+static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+if (interrupt_request CPU_INTERRUPT_HARD) {
+tilegx_cpu_do_interrupt(cs);
+return true;
+}
+return false;
+}
+
+static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+CPUClass *cc = CPU_CLASS(oc);
+TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
+
+tcc-parent_realize = dc-realize;
+dc-realize = tilegx_cpu_realizefn;
+
+tcc-parent_reset = cc-reset;
+cc-reset = tilegx_cpu_reset;
+
+cc-has_work = tilegx_cpu_has_work;
+cc-do_interrupt = tilegx_cpu_do_interrupt;
+cc-cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+cc-set_pc = tilegx_cpu_set_pc;
+cc-handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
+cc-gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tilegx_cpu_type_info = {
+.name = TYPE_TILEGX_CPU,
+.parent = TYPE_CPU,
+.instance_size = sizeof(TileGXCPU),
+.instance_init = tilegx_cpu_initfn,
+.class_size = sizeof(TileGXCPUClass),
+.class_init = tilegx_cpu_class_init,
+};
+
+static void tilegx_cpu_register_types(void)
+{
+type_register_static(tilegx_cpu_type_info);
+}
+
+type_init(tilegx_cpu_register_types)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
new file mode 100644
index 000..e404025
--- /dev/null
+++ b/target-tilegx/cpu.h
@@ -0,0 +1,175 @@
+/*
+ * TILE-Gx virtual CPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You
[Qemu-devel] [PATCH 08/10 v12] target-tilegx: Add several helpers for instructions translation
The related instructions are exception, cntlz, cnttz, shufflebytes, and
add_saturate.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c | 83 ++
target-tilegx/helper.h | 5 +++
2 files changed, 88 insertions(+)
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
new file mode 100644
index 000..5ab41cd
--- /dev/null
+++ b/target-tilegx/helper.c
@@ -0,0 +1,83 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include exec/helper-proto.h
+
+#define SIGNBIT32 0x8000
+
+int64_t helper_add_saturate(CPUTLGState *env, uint64_t rsrc, uint64_t rsrcb)
+{
+uint32_t rdst = rsrc + rsrcb;
+
+if (((rdst ^ rsrc) SIGNBIT32) !((rsrc ^ rsrcb) SIGNBIT32)) {
+rdst = ~(((int32_t)rsrc 31) ^ SIGNBIT32);
+}
+
+return (int64_t)rdst;
+}
+
+void helper_exception(CPUTLGState *env, uint32_t excp)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+
+cs-exception_index = excp;
+cpu_loop_exit(cs);
+}
+
+uint64_t helper_cntlz(uint64_t arg)
+{
+return clz64(arg);
+}
+
+uint64_t helper_cnttz(uint64_t arg)
+{
+return ctz64(arg);
+}
+
+/*
+ * Functional Description
+ * uint64_t a = rf[SrcA];
+ * uint64_t b = rf[SrcB];
+ * uint64_t d = rf[Dest];
+ * uint64_t output = 0;
+ * unsigned int counter;
+ * for (counter = 0; counter (WORD_SIZE / BYTE_SIZE); counter++)
+ * {
+ * int sel = getByte (b, counter) 0xf;
+ * uint8_t byte = (sel 8) ? getByte (d, sel) : getByte (a, (sel -
8));
+ * output = setByte (output, counter, byte);
+ * }
+ * rf[Dest] = output;
+ */
+uint64_t helper_shufflebytes(uint64_t rdst, uint64_t rsrc, uint64_t rsrcb)
+{
+uint64_t vdst = 0;
+int count;
+
+for (count = 0; count 64; count += 8) {
+uint64_t sel = rsrcb count;
+uint64_t src = (sel 8) ? rsrc : rdst;
+vdst |= ((src ((sel 7) * 8)) 0xff) count;
+}
+
+return vdst;
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
new file mode 100644
index 000..1411c19
--- /dev/null
+++ b/target-tilegx/helper.h
@@ -0,0 +1,5 @@
+DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
+DEF_HELPER_3(add_saturate, s64, env, i64, i64)
--
1.9.3
[Qemu-devel] [PATCH 02/10 v12] linux-user: Support tilegx architecture in linux-user
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
include/elf.h | 2 +
linux-user/elfload.c | 23
linux-user/main.c | 295 ++
linux-user/syscall_defs.h | 14 ++-
4 files changed, 329 insertions(+), 5 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 4afd474..79859f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
+#define EM_TILEGX 191 /* TILE-Gx */
+
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL0
#define DT_NEEDED 1
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index b71e866..12d79f1 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1218,6 +1218,29 @@ static inline void init_thread(struct target_pt_regs
*regs, struct image_info *i
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+/* 42 bits real used address, a half for user mode */
+#define ELF_START_MMAP (0x00200ULL)
+
+#define elf_check_arch(x) ((x) == EM_TILEGX)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+regs-pc = infop-entry;
+regs-sp = infop-start_stack;
+
+}
+
+#define ELF_EXEC_PAGESIZE65536 /* TILE-Gx page size is 64KB */
+
+#endif /* TARGET_TILEGX */
+
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index a0d3e58..0a44b38 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3412,6 +3412,290 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+static void gen_sigsegv_mapper(CPUTLGState *env, target_ulong addr)
+{
+target_siginfo_t info;
+
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+info.si_code = TARGET_SEGV_MAPERR;
+info._sifields._sigfault._addr = addr;
+queue_signal(env, info.si_signo, info);
+}
+
+static void gen_sigill_reg(CPUTLGState *env)
+{
+target_siginfo_t info;
+
+info.si_signo = TARGET_SIGILL;
+info.si_errno = 0;
+info.si_code = TARGET_ILL_PRVREG;
+info._sifields._sigfault._addr = env-pc;
+queue_signal(env, info.si_signo, info);
+}
+
+static int get_regval(CPUTLGState *env, uint8_t reg, target_ulong *val)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+*val = env-regs[reg];
+return 0;
+}
+
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+*val = 0;
+return 0;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+return -1;
+default:
+g_assert_not_reached();
+}
+}
+
+static int set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
+{
+if (unlikely(reg = TILEGX_R_COUNT)) {
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+return 0;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+return -1;
+default:
+g_assert_not_reached();
+}
+}
+
+env-regs[reg] = val;
+return 0;
+}
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values are
+ * not equal, then no memory operation is performed. If the values are equal,
+ * the 8-byte quantity from the second source register is written into memory
+ * at the address held in the first source register. In either case, the result
+ * of the instruction is the value read from memory. The compare and write to
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * This function also processes exch and exch4 which need not process SPR.
+ */
+static void do_exch(CPUTLGState *env, bool quad, bool cmp)
+{
+uint8_t rdst, rsrc, rsrcb;
+target_ulong addr
[Qemu-devel] [PATCH 09/10 v12] target-tilegx: Generate tcg instructions to finish Hello world
Generate related tcg instructions, and qemu tilegx can finish running
Hello world. The elf64 binary can be static or shared.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/translate.c | 2966 +
1 file changed, 2966 insertions(+)
create mode 100644 target-tilegx/translate.c
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
new file mode 100644
index 000..1dd3a43
--- /dev/null
+++ b/target-tilegx/translate.c
@@ -0,0 +1,2966 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu/log.h
+#include disas/disas.h
+#include tcg-op.h
+#include exec/cpu_ldst.h
+#include opcode_tilegx.h
+#include spr_def_64.h
+
+#define FMT64X %016 PRIx64
+#define TILEGX_TMP_REGS(TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE + 1)
+
+static TCGv_ptr cpu_env;
+static TCGv cpu_pc;
+static TCGv cpu_regs[TILEGX_R_COUNT];
+static TCGv cpu_spregs[TILEGX_SPR_COUNT];
+#if defined(CONFIG_USER_ONLY)
+static TCGv_i32 cpu_excparam;
+#endif
+
+static const char * const reg_names[] = {
+ r0, r1, r2, r3, r4, r5, r6, r7,
+ r8, r9, r10, r11, r12, r13, r14, r15,
+r16, r17, r18, r19, r20, r21, r22, r23,
+r24, r25, r26, r27, r28, r29, r30, r31,
+r32, r33, r34, r35, r36, r37, r38, r39,
+r40, r41, r42, r43, r44, r45, r46, r47,
+r48, r49, r50, r51, bp, tp, sp, lr
+};
+
+static const char * const spreg_names[] = {
+cmpexch, criticalsec, simcontrol
+};
+
+/* It is for temporary registers */
+typedef struct DisasContextTemp {
+uint8_t idx; /* index */
+TCGv val; /* value */
+} DisasContextTemp;
+
+/* This is the state at translation time. */
+typedef struct DisasContext {
+uint64_t pc; /* Current pc */
+int exception; /* Current exception */
+
+TCGv zero; /* For zero register */
+
+DisasContextTemp *tmp_regcur; /* Current temporary registers */
+DisasContextTemp tmp_regs[TILEGX_TMP_REGS]; /* All temporary registers */
+struct {
+TCGCond cond; /* Branch condition */
+TCGv dest; /* pc jump destination, if will jump */
+TCGv val1; /* Firt value for condition comparing */
+TCGv val2; /* Second value for condition comparing */
+} jmp; /* Jump object, only once in each TB block
*/
+} DisasContext;
+
+#include exec/gen-icount.h
+
+static void gen_exception(DisasContext *dc, int num)
+{
+TCGv_i32 tmp = tcg_const_i32(num);
+
+gen_helper_exception(cpu_env, tmp);
+tcg_temp_free_i32(tmp);
+}
+
+/*
+ * All exceptions which can still let working flow continue are all in pipe x1,
+ * which is the last pipe of a bundle. So it is OK to only process the first
+ * exception within a bundle.
+ */
+static void set_exception(DisasContext *dc, int num)
+{
+if (dc-exception == TILEGX_EXCP_NONE) {
+dc-exception = num;
+}
+}
+
+static bool check_gr(DisasContext *dc, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return true;
+}
+
+switch (reg) {
+case TILEGX_R_SN:
+case TILEGX_R_ZERO:
+break;
+case TILEGX_R_IDN0:
+case TILEGX_R_IDN1:
+set_exception(dc, TILEGX_EXCP_REG_IDN_ACCESS);
+break;
+case TILEGX_R_UDN0:
+case TILEGX_R_UDN1:
+case TILEGX_R_UDN2:
+case TILEGX_R_UDN3:
+set_exception(dc, TILEGX_EXCP_REG_UDN_ACCESS);
+break;
+default:
+g_assert_not_reached();
+}
+return false;
+}
+
+static TCGv load_zero(DisasContext *dc)
+{
+if (TCGV_IS_UNUSED_I64(dc-zero)) {
+dc-zero = tcg_const_i64(0);
+}
+return dc-zero;
+}
+
+static TCGv load_gr(DisasContext *dc, uint8_t reg)
+{
+if (check_gr(dc, reg)) {
+return cpu_regs[reg];
+}
+return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, uint8_t rdst)
+{
+DisasContextTemp *tmp = dc-tmp_regcur++;
+
+/* Skip the result, mark the exception if necessary, and continue */
+check_gr(dc, rdst);
+assert((dc-tmp_regcur - dc-tmp_regs) TILEGX_TMP_REGS);
+tmp-idx = rdst;
+tmp-val = tcg_temp_new_i64();
+return
[Qemu-devel] [PATCH 00/10 v12] tilegx: Firstly add tilegx target for linux-user
It can finish running Hello world elf64 binary, and the related test cases: - with --enable-debug, enable assertion with -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/a.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/b.log - without --enable-debug, disable assertion with -O2 -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/c.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/d.log Chen Gang (10): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx/opcode_tilegx.h: Modify it to fit QEMU usage target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Generate tcg instructions to finish Hello world target-tilegx: Add TILE-Gx building files configure |2 + default-configs/tilegx-linux-user.mak |1 + include/elf.h |2 + linux-user/elfload.c | 23 + linux-user/main.c | 295 linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 40 + linux-user/tilegx/syscall_nr.h| 324 linux-user/tilegx/target_cpu.h| 35 + linux-user/tilegx/target_signal.h | 28 + linux-user/tilegx/target_structs.h| 46 + linux-user/tilegx/termbits.h | 274 +++ target-tilegx/Makefile.objs |1 + target-tilegx/cpu.c | 143 ++ target-tilegx/cpu.h | 175 ++ target-tilegx/helper.c| 83 + target-tilegx/helper.h|5 + target-tilegx/opcode_tilegx.h | 1406 target-tilegx/spr_def_64.h| 216 +++ target-tilegx/translate.c | 2966 + 21 files changed, 6123 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- 1.9.3
[Qemu-devel] [PATCH 04/10 v12] target-tilegx: Add opcode basic implementation from Tilera Corporation
It is copied from Linux kernel arch/tile/include/uapi/arch/
opcode_tilegx.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
new file mode 100644
index 000..d76ff2d
--- /dev/null
+++ b/target-tilegx/opcode_tilegx.h
@@ -0,0 +1,1406 @@
+/* TILE-Gx opcode information.
+ *
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __ARCH_OPCODE_H__
+#define __ARCH_OPCODE_H__
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long long tilegx_bundle_bits;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
+
+enum
+{
+ /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+ /* Instructions take this many bytes. */
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+ /* Bundles should be aligned modulo this number of bytes. */
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+(1 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+ /* Number of registers (some are magic, such as network I/O). */
+ TILEGX_NUM_REGISTERS = 64,
+};
+
+/* Make a few tile_ variables to simplify common code between
+ architectures. */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 24)) 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 18)) 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 37)) 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 54)) 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 43)) 0x00c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0x);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 20)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 51)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0xff);
+}
+
+static
[Qemu-devel] [PATCH 03/10 v12] linux-user/syscall.c: conditionally define syscalls which are not defined in tilegx
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/syscall.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 1622ad6..a503673 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
-#ifdef __NR_getdents
+#if defined(TARGET_NR_getdents) defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint,
count);
#endif
#if !defined(__NR_getdents) || \
@@ -5581,6 +5581,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
+#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -5589,6 +5590,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@@ -5603,9 +5605,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
+#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
+#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@@ -5640,6 +5644,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
+#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@@ -5653,6 +5658,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@@ -5670,12 +5676,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@@ -5792,12 +5800,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@@ -5806,12 +5816,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@@ -5946,6 +5958,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@@ -5964,6 +5977,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@@ -5992,12 +6006,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
+#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_faccessat) defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@@ -6022,6 +6038,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
+#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@@ -6035,6 +6052,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@@ -6050,12 +6068,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break
[Qemu-devel] [PATCH 10/10 v12] target-tilegx: Add TILE-Gx building files
Add related configuration, make files for tilegx. Now, qemu tilegx can pass building, and finish running Hello world static/shared elf64 binary. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- configure | 2 ++ default-configs/tilegx-linux-user.mak | 1 + target-tilegx/Makefile.objs | 1 + 3 files changed, 4 insertions(+) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 target-tilegx/Makefile.objs diff --git a/configure b/configure index 409edf9..befd461 100755 --- a/configure +++ b/configure @@ -5296,6 +5296,8 @@ case $target_name in s390x) gdb_xml_files=s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml ;; + tilegx) + ;; tricore) ;; unicore32) diff --git a/default-configs/tilegx-linux-user.mak b/default-configs/tilegx-linux-user.mak new file mode 100644 index 000..3e47493 --- /dev/null +++ b/default-configs/tilegx-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for tilegx-linux-user diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs new file mode 100644 index 000..8b3dc76 --- /dev/null +++ b/target-tilegx/Makefile.objs @@ -0,0 +1 @@ +obj-y += cpu.o translate.o helper.o -- 1.9.3
Re: [Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish Hello world
After thinking of again, for me, I still prefer to keep gen_cntlz() and
others, the reason is below:
- gen_* (include gen_cntlz) are used in multiple areas, and most gen_*
are not single statement. For each gen_*, printing insns is easy (and
may be helpful).
- decode* is for switch opcode (as branch), not for implementation (as
leaf).
- After we use individual functions for all unary opcode extensions, we
can let decode* very simple (although they may have long code), if we
let decode* printing insns, it will let them seem a little complex.
Thanks.
On 6/2/15 04:54, Chen Gang wrote:
I can't help thinking, as I read all of these decode functions, that it would
be better if the output disassembly, i.e. qemu_log_mask(CPU_LOG_TB_IN_ASM,
*),
were to happen here, instead of being spread across 99 other functions.
This has a side effect of reducing many of your functions to a single
statement, invoking another tcg generator, at which point it's worth
inlining them.
OK, thanks.
For example:
static void decode_rrr_1_unary_y0(struct DisasContext *dc,
tilegx_bundle_bits bundle,
uint8_t rdst, uint8_t rsrc)
{
unsigned ext = get_UnaryOpcodeExtension_Y0(bundle);
const char *mnemonic;
TCGv vdst, vsrc;
if (ext == NOP_UNARY_OPCODE_Y0 || ext == FNOP_UNARY_OPCODE_Y0) {
if (rsrc != 0 || rdst != 0) {
goto unimplemented;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, (f)nop\n);
return;
}
vdst = dest_gr(dc, rdst);
vsrc = load_gr(dc, rsrc);
switch (ext) {
case CNTLZ_UNARY_OPCODE_Y0:
gen_helper_cntlz(vdst, vsrc);
mnemonic = cntlz;
break;
case CNTTZ_UNARY_OPCODE_Y0:
gen_helper_cnttz(vdst, vsrc);
mnemonic = cnttz;
break;
case FSINGLE_PACK1_UNARY_OPCODE_Y0:
case PCNT_UNARY_OPCODE_Y0:
case REVBITS_UNARY_OPCODE_Y0:
case REVBYTES_UNARY_OPCODE_Y0:
case TBLIDXB0_UNARY_OPCODE_Y0:
case TBLIDXB1_UNARY_OPCODE_Y0:
case TBLIDXB2_UNARY_OPCODE_Y0:
case TBLIDXB3_UNARY_OPCODE_Y0:
default:
unimplemented:
qemu_log_mask(LOG_UNIMP, UNIMP rrr_1_unary_y0, [ FMT64X ]\n,
bundle);
dc-exception = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
return;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, %s r%d,r%d\n,
mnemonic, rdst, rsrc);
}
static void decode_rrr_1_opcode_y0(struct DisasContext *dc,
tilegx_bundle_bits bundle)
{
unsigned ext = get_RRROpcodeExtension_Y0(bundle);
uint8_t rsrca = get_SrcA_Y0(bundle);
uint8_t rsrcb = get_SrcB_Y0(bundle);
uint8_t rdst = get_Dest_Y0(bundle);
const char *mnemonic;
TCGv vdst, vsrca, vsrcb;
if (ext == UNARY_RRR_1_OPCODE_Y0) {
decode_rrr_1_unary_y0(dc, bundle, rdst, rsrc);
return;
}
vdst = dest_gr(dc, rdst);
vsrca = load_gr(dc, rsrca);
vsrcb = load_gr(dc, rsrcb);
switch (ext) {
case SHL1ADD_RRR_1_OPCODE_Y0:
gen_shladd(vdst, vsrca, vsrcb, 1, 0);
mnemonic = shl1add;
break;
case SHL2ADD_RRR_1_OPCODE_Y0:
gen_shladd(vdst, vsrca, vsrcb, 2, 0);
mnemonic = shl2add;
break;
case SHL3ADD_RRR_1_OPCODE_Y0:
gen_shladd(vdst, vsrca, vsrcb, 3, 0);
mnemonic = shl3add;
break;
default:
qemu_log_mask(LOG_UNIMP, UNIMP rrr_1_opcode_y0, [ FMT64X ]\n,
bundle);
dc-exception = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
return;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, %s r%d,r%d,r%d\n,
mnemonic, rdst, rsrca, rsrcb);
}
OK, thank you very much.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 06/03/2015 11:20 PM, Chris Metcalf wrote: On 06/03/2015 11:19 AM, Peter Maydell wrote: On 3 June 2015 at 16:10, Chris Metcalf cmetc...@ezchip.com wrote: On 06/03/2015 08:47 AM, Chen Gang wrote: On 06/03/2015 08:34 PM, Peter Maydell wrote: You must do something. You can't allow guest code (even broken guest code) to make QEMU assert. You need to find out what the hardware does here, and do that. OK, what you said sounds reasonable to me. I will check what to do next for the 56..62 registers (at present, I guess, we need generate a hardware exception, and its default handler will do nothing). The registers in question are mapped directly to the on-chip networks. 56 - sn (static network) 57 - idn0 (internal dynamic network, demux 0) 58 - idn1 (internal dynamic network, demux 1) 59 - udn0 (user dynamic network, demux 0) 60 - udn1 (user dynamic network, demux 1) 61 - udn2 (user dynamic network, demux 2) 62 - udn3 (user dynamic network, demux 3) The sn is obsoleted in tilegx so acts just like zero. Accessing idn0 or idn1 will generate an IDN_ACCESS exception, and accessing udn0..udn3 will generate a UDN_ACCESS exception; either of those becomes a SIGILL to a userspace application with code ILL_PRVREG. OK, thank you very much for your details. I will implement it according to the details above. Presumably this applies for all register accesses, not just atomic instructions? Excuse me, I do not quite understand what it is meaning, welcome any more details for it. Correct. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 06/03/2015 11:47 PM, Richard Henderson wrote: On 06/03/2015 05:34 AM, Peter Maydell wrote: You must do something. You can't allow guest code (even broken guest code) to make QEMU assert. You need to find out what the hardware does here, and do that. These are I/O registers for IPC. I believe that the best thing to do is assume protection is enabled at the kernel level, and thus raise the appropriate exception: SN_ACCESS, IDN_ACCESS, UDN_ACCESS. OK, thanks That said, I don't have the system architecture manual handy to check the full details. Fortunately, Chris knows more about it, and provide more valuable details for it. And welcome any members to provide related pdf documents, if possible. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 06/04/2015 08:29 PM, Peter Maydell wrote: On 4 June 2015 at 13:25, Chen Gang xili_gchen_5...@hotmail.com wrote: On 06/03/2015 11:20 PM, Chris Metcalf wrote: On 06/03/2015 11:19 AM, Peter Maydell wrote: On 3 June 2015 at 16:10, Chris Metcalf cmetc...@ezchip.com wrote: On 06/03/2015 08:47 AM, Chen Gang wrote: On 06/03/2015 08:34 PM, Peter Maydell wrote: You must do something. You can't allow guest code (even broken guest code) to make QEMU assert. You need to find out what the hardware does here, and do that. OK, what you said sounds reasonable to me. I will check what to do next for the 56..62 registers (at present, I guess, we need generate a hardware exception, and its default handler will do nothing). The registers in question are mapped directly to the on-chip networks. 56 - sn (static network) 57 - idn0 (internal dynamic network, demux 0) 58 - idn1 (internal dynamic network, demux 1) 59 - udn0 (user dynamic network, demux 0) 60 - udn1 (user dynamic network, demux 1) 61 - udn2 (user dynamic network, demux 2) 62 - udn3 (user dynamic network, demux 3) The sn is obsoleted in tilegx so acts just like zero. Accessing idn0 or idn1 will generate an IDN_ACCESS exception, and accessing udn0..udn3 will generate a UDN_ACCESS exception; either of those becomes a SIGILL to a userspace application with code ILL_PRVREG. OK, thank you very much for your details. I will implement it according to the details above. Presumably this applies for all register accesses, not just atomic instructions? Excuse me, I do not quite understand what it is meaning, welcome any more details for it. Chris says that all instructions that use these registers generate an exception. Atomic instructions are not special. This means you should handle these registers in translate.c (in the same place you handle their use in all other kinds of instruction). If you do that then it's OK to assert in main.c, because you know that translate.c has already made sure those cases are handled and won't generate the do an atomic operation exception for them. OK, Thanks. And I shall try to send patch v12 within next week (2015-06-14). -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v11] arget-tilegx/opcode_tilegx.h: Modify it to fit qemu using
On 06/03/2015 07:39 AM, Andreas Färber wrote: Am 03.06.2015 um 02:43 schrieb Peter Maydell: On 30 May 2015 at 22:14, Chen Gang xili_gchen_5...@hotmail.com wrote: Use 'inline' instead of '__inline', and also use 'uint64_t' instead of unsigned long long Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/opcode_tilegx.h | 220 +- 1 file changed, 110 insertions(+), 110 deletions(-) Reviewed-by: Peter Maydell peter.mayd...@linaro.org There's a t missing in the subject and the grammar is wrong - usage? Also QEMU. OK, thank you very much. Deserves a mention in the commit message why this is not being squashed. Excuse me, my English is not quite well, I do not know about what you said above, could you provide more details for it? Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 06/03/2015 08:34 PM, Peter Maydell wrote:
On 3 June 2015 at 13:30, Chen Gang xili_gchen_5...@hotmail.com wrote:
On 06/03/2015 01:40 AM, Peter Maydell wrote:
On 30 May 2015 at 22:10, Chen Gang xili_gchen_5...@hotmail.com wrote:
+#ifdef TARGET_TILEGX
+
+static uint64_t get_regval(CPUTLGState *env, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return env-regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for reading.\n, reg);
+g_assert_not_reached();
You don't appear to be guaranteeing that the register value
is TILEGX_R_COUNT anywhere: get_SrcA_X1() and friends
mask with 0x3f, but that only means you're guaranteed the
value is between 0 and 63, wherease TILEGX_R_COUNT is 56.
What does real hardware do if the encoded register value
is 56..63 ?
At present, it will g_assert_not_reached() too.
No, it is not possible for hardware to assert!
56..62 are hidden to
outside. So I did not implement them, either. Need we still implement
them?
You must do something. You can't allow guest code (even
broken guest code) to make QEMU assert. You need to find
out what the hardware does here, and do that.
OK, what you said sounds reasonable to me. I will check what to do next
for the 56..62 registers (at present, I guess, we need generate a
hardware exception, and its default handler will do nothing).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 01/10 v11] linux-user: tilegx: Firstly add architecture related features
On 06/03/2015 01:06 AM, Peter Maydell wrote:
On 30 May 2015 at 22:10, Chen Gang xili_gchen_5...@hotmail.com wrote:
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
+typedef struct target_sigaltstack {
+abi_ulong ss_sp;
+abi_int ss_flags;
+abi_int dummy;
+abi_ulong ss_size;
+} target_stack_t;
Drop the 'dummy' field; you don't need it. The point of the abi_*
types is to have the same struct layout requirements as the target,
and the target doesn't have a 'dummy' field.
OK, thanks.
+struct target_ipc_perm {
+abi_int __key; /* Key. */
+abi_uint uid; /* Owner's user ID. */
+abi_uint gid; /* Owner's group ID. */
+abi_uint cuid; /* Creator's user ID. */
+abi_uint cgid; /* Creator's group ID. */
+abi_uint mode; /* Read/write permission. */
+abi_ushort __seq; /* Sequence number. */
+abi_ushort __pad2;
+abi_ulong __unused1;
+abi_ulong __unused2;
I still think these pad and unused fields are wrong; they're not
in the kernel. Do you have a test program that is incorrectly
handled if we don't have these fields in the QEMU struct?
OK, thanks, I will try to test it without pad and unused fields.
For me, I also think they are useless (wrong). But I don't understand
why all the other targets add them (may they also need remove pad or
unused? -- I guess yes).
+};
+
+struct target_shmid_ds {
+struct target_ipc_perm shm_perm;/* operation permission struct */
...in particular the way this struct is embedded means that
if we have the wrong size for target_ipc_perm then we will
have wrong offsets for all these following fields.
We really need analyze why it still works. I will try to analyze it (it
seems most of the other targets face to the same issue).
+abi_long shm_segsz; /* size of segment in bytes */
+abi_ulong shm_atime;/* time of last shmat() */
+abi_ulong shm_dtime;/* time of last shmdt() */
+abi_ulong shm_ctime;/* time of last change by shmctl()
*/
+abi_int shm_cpid; /* pid of creator */
+abi_int shm_lpid; /* pid of last shmop */
+abi_ulong shm_nattch; /* number of current attaches */
The kernel has an unsigned short here, with a following
unsigned short shm_unused for padding.
OK, thanks.
+abi_ulong __unused4;
+abi_ulong __unused5;
+};
+
+#endif
diff --git a/linux-user/tilegx/termbits.h b/linux-user/tilegx/termbits.h
new file mode 100644
index 000..39bc8ac
--- /dev/null
+++ b/linux-user/tilegx/termbits.h
@@ -0,0 +1,285 @@
+#ifndef TILEGX_TERMBITS_H
+#define TILEGX_TERMBITS_H
+
+/* From asm-generic/termbits.h, which is used by tilegx */
+
+#define TARGET_NCCS 19
+struct target_termios {
+unsigned int c_iflag; /* input mode flags */
+unsigned int c_oflag; /* output mode flags */
+unsigned int c_cflag; /* control mode flags */
+unsigned int c_lflag; /* local mode flags */
+unsigned char c_line; /* line discipline */
+unsigned char c_cc[TARGET_NCCS]; /* control characters */
+};
+
+struct target_termios2 {
+unsigned int c_iflag; /* input mode flags */
+unsigned int c_oflag; /* output mode flags */
+unsigned int c_cflag; /* control mode flags */
+unsigned int c_lflag; /* local mode flags */
+unsigned char c_line; /* line discipline */
+unsigned char c_cc[TARGET_NCCS]; /* control characters */
+unsigned int c_ispeed;/* input speed */
+unsigned int c_ospeed;/* output speed */
+};
+
+struct target_ktermios {
+unsigned int c_iflag; /* input mode flags */
+unsigned int c_oflag; /* output mode flags */
+unsigned int c_cflag; /* control mode flags */
+unsigned int c_lflag; /* local mode flags */
+unsigned char c_line; /* line discipline */
+unsigned char c_cc[TARGET_NCCS]; /* control characters */
+unsigned int c_ispeed;/* input speed */
+unsigned int c_ospeed;/* output speed */
+};
Why have you defined target_ktermios? It's not used anywhere in QEMU.
OK, thanks. I will remove it.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
On 06/03/2015 01:40 AM, Peter Maydell wrote:
On 30 May 2015 at 22:10, Chen Gang xili_gchen_5...@hotmail.com wrote:
+#ifdef TARGET_TILEGX
+
+static uint64_t get_regval(CPUTLGState *env, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return env-regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for reading.\n, reg);
+g_assert_not_reached();
You don't appear to be guaranteeing that the register value
is TILEGX_R_COUNT anywhere: get_SrcA_X1() and friends
mask with 0x3f, but that only means you're guaranteed the
value is between 0 and 63, wherease TILEGX_R_COUNT is 56.
What does real hardware do if the encoded register value
is 56..63 ?
At present, it will g_assert_not_reached() too. 56..62 are hidden to
outside. So I did not implement them, either. Need we still implement
them?
For 63, it is zero register, we need do nothing for it.
Also, if (something) {
g_assert_not_reached();
}
is an awkward way to write
g_assert(!something);
OK, thanks. The code above is fine to me.
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values
are
+ * not equal, then no memory operation is performed. If the values are
equal,
+ * the 8-byte quantity from the second source register is written into
memory
+ * at the address held in the first source register. In either case, the
result
+ * of the instruc- tion is the value read from memory. The compare and
write to
stray - .
OK, thanks.
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * For exch(4), will no cmp spr.
Not sure what this sentence means?
This function also process exch and exch4 which need not process SPR.
I guess, the comments needs to be improved (provide more details).
+ */
+static void do_exch(CPUTLGState *env, int8_t quad, int8_t cmp)
quad and cmp are just booleans, right? Why int8_t not bool?
OK, thanks. I will change to bool in qemu. I often use char or int
instead of bool. For the latest C, bool is better.
+{
+uint8_t rdst, rsrc, rsrcb;
+target_ulong addr, tmp;
+target_long val, sprval;
+target_siginfo_t info;
+
+start_exclusive();
+
+rdst = (env-excparam 16) 0xff;
+rsrc = (env-excparam 8) 0xff;
+rsrcb = env-excparam 0xff;
Consider extract32().
OK, thanks. It sounds good.
+
+addr = get_regval(env, rsrc);
+if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+goto do_sigsegv;
+}
+tmp = (target_ulong)val; /* rdst may be the same to rsrcb, so buffer
it */
Why do this, when we could just use a different variable
rather than trashing val below?
OK, thanks, the code need rewrite a little, just like you said below.
+
+if (cmp) {
+if (quad) {
+sprval = (target_long)env-spregs[TILEGX_SPR_CMPEXCH];
Pointless cast.
OK, thanks.
+} else {
+sprval = (int32_t)(env-spregs[TILEGX_SPR_CMPEXCH]
0x);
Clearer as
sprval = sextract64(env-spregs[TILEGX_SPR_CMPEXCH], 0, 32);
OK, thanks.
+}
+}
+
+if (!cmp || val == sprval) {
+val = get_regval(env, rsrcb);
If you say target_long srcbval = ... you don't trash val.
OK, thanks.
+if (quad ? put_user_u64(val, addr) : put_user_u32(val, addr)) {
+goto do_sigsegv;
+}
+}
+
+set_regval(env, rdst, tmp);
+
+end_exclusive();
+return;
+
+do_sigsegv:
+end_exclusive();
+
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+info.si_code = TARGET_SEGV_MAPERR;
+info._sifields._sigfault._addr = addr;
+queue_signal(env, TARGET_SIGSEGV, info);
+}
+
+static void do_fetch(CPUTLGState *env, int trapnr, int8_t quad)
+{
+uint8_t rdst, rsrc, rsrcb;
+int8_t write = 1;
+target_ulong addr;
+target_long val, tmp;
+target_siginfo_t info;
+
+start_exclusive();
+
+rdst = (env-excparam 16) 0xff;
+rsrc = (env-excparam 8) 0xff;
+rsrcb = env-excparam 0xff;
+
+addr = get_regval(env, rsrc);
+if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+goto
Re: [Qemu-devel] [PATCH 10/10 v11] target-tilegx: Add TILE-Gx building files
On 6/3/15 01:52, Peter Maydell wrote: On 30 May 2015 at 22:19, Chen Gang xili_gchen_5...@hotmail.com wrote: Add related configuration, make files for tilegx. Now, qemu tilegx can pass building, and finish running Hello world static/shared elf64 binary. Signed-off-by: Chen Gang gang.chen.5...@gmail.com Reviewed-by: Peter Maydell peter.mayd...@linaro.org OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 06/10 v11] target-tilegx: Add special register information from Tilera Corporation
On 6/3/15 01:44, Peter Maydell wrote: On 30 May 2015 at 22:15, Chen Gang xili_gchen_5...@hotmail.com wrote: The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h I'd care more about the possibility of conflicts with the actual user header if we supported building QEMU on a tilegx host. But since we don't this is OK. it contents #ifndef __ARCH_SPR_DEF_64_H__, and belongs to UAPI which should be no changes (at least should be compitable with old version), so for me, it should be no conflicts on a tilegx host. Reviewed-by: Peter Maydell peter.mayd...@linaro.org OK Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish Hello world
On 6/3/15 01:54, Peter Maydell wrote: On 30 May 2015 at 22:18, Chen Gang xili_gchen_5...@hotmail.com wrote: Generate related tcg instructions, and qemu tilegx can finish running Hello world. The elf64 binary can be static or shared. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/translate.c | 2787 + 1 file changed, 2787 insertions(+) create mode 100644 target-tilegx/translate.c For me, this patch is just too long to review sensibly. (Simply trying to deal with replying to this email in my mail client was a pain.) But Richard is going to review this so I'll let him make that decision. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 07/10 v11] target-tilegx: Add cpu basic features for linux-user
Firstly, thank you very much for your valuable work for all patches. On 6/3/15 01:51, Peter Maydell wrote: On 30 May 2015 at 22:15, Chen Gang xili_gchen_5...@hotmail.com wrote: + +#define TILEGX_IS_ERRNO(ret) \ + ((ret) 0xf000ULL) /* errno is 0 -- 4096 */ TILEGX_IS_ERRNO is specific to the Linux syscall ABI; it belongs in linux-user/ somewhere, not here. OK, thanks. I shall move it to linux-user/tilegx/syscall.h. +#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e)) + +#define ENV_OFFSET offsetof(TileGXCPU, env) + +/* TILE-Gx memory attributes */ +#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */ +#define MMAP_SHIFT TARGET_PAGE_BITS MMAP_SHIFT is linux ABI specific and doesn't belong in this file. OK, thanks. I shall move it to linux-user/tilegx/syscall.h (although all the other targets still put it in target-*/cpu.h). +#define TARGET_PHYS_ADDR_SPACE_BITS 42 /* It has 42 bit physical addresses */ +#define TARGET_VIRT_ADDR_SPACE_BITS 64 /* It has 64 bit virtual addresses */ These comments are stating the obvious and can be deleted. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 06/10 v11] target-tilegx: Add special register information from Tilera Corporation
On 6/3/15 01:44, Peter Maydell wrote: On 30 May 2015 at 22:15, Chen Gang xili_gchen_5...@hotmail.com wrote: The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h I'd care more about the possibility of conflicts with the actual user header if we supported building QEMU on a tilegx host. But since we don't this is OK. it contents #ifndef __ARCH_SPR_DEF_64_H__, and belongs to UAPI which should be no changes (at least should be compatible with old version), so for me, it should be no conflicts on a tilegx host. Reviewed-by: Peter Maydell peter.mayd...@linaro.org OK Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish Hello world
On 6/3/15 00:32, Richard Henderson wrote:
On 06/01/2015 01:54 PM, Chen Gang wrote:
Further, the TILEGX_R_COUNT restriction is also incorrect. True, you
don't
actually implement the top 7 special registers, but that doesn't matter, you
should still be incrementing them.
We did not implement them, so can not increment them, either.
They are hidden to outside, or we have to define and implement them.
So for me, the current code is correct.
It isn't correct, it's simply functional. These registers may eventually be
implemented, and at that point this code will fail. You'll note that your
store_add functions don't have the same problem, because they don't have this
R_COUNT check. It would be better to increase the number of buffer slots and
do the right thing here in load_add.
For me, it is about 2 discussions:
- Whether need implement additional 7 registers.
I guess not. But if we will really implement them in future, we need
only let TILEGX_R_COUNT = TILEGX_R_ZERO, and all things should still
be OK.
- Whether need 2 or more tmp variables for one pipe.
It is not necessary, but it will let the code simplier.
My suggestion is to expand tmp_regs to 4, drop tmp_regcur, and have dest_gr
manage all of the indexing. I.e.
static TCGv dest_gr(DisasContext *dc, uint8_t rdst)
{
int n = dc-n_tmp_regs++;
assert(n ARRAY_SIZE(dc-tmp_regs));
dc-tmp_regs[n].idx = rdst;
return dc-tmp_regs[n].val = tcg_temp_new_i64();
}
In this way you can in fact call dest_gr twice within load_add and everything
will Just Work.
For me, the code is fine (and reset dc-n_tmp_regs for each bundle).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 08/10 v11] target-tilegx: Add several helpers for instructions translation
On 6/2/15 00:02, Richard Henderson wrote:
On 05/30/2015 02:17 PM, Chen Gang wrote:
+for (count = 0; count 8; count++) {
+sel = (rsrcb (count * 8)) 0xf;
+if (sel 8) {
+vdst |= ((rdst (8 * sel)) 0xff) (count * 8);
+} else {
+vdst |= ((rsrc (8 * (8 - sel))) 0xff) (count * 8);
8 - sel is wrong; you wanted sel - 8.
OK, thank you very much.
That said, you can do better with masking operations. And for brevity, let
count increment by 8. E.g.
uint64_t vdst = 0;
int count;
for (count = 0; count 64; count += 8) {
uint64_t sel = rsrcb count;
uint64_t src = (sel 8 ? rsrc : rdst);
vdst |= ((src ((sel 7) * 8)) 0xff) count;
}
OK, thank.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/27/15 05:39, Chen Gang wrote:
On 5/12/15 05:26, Chen Gang wrote:
+}
+
+/*
+ * Functional Description
+ *
+ *uint64_t output = 0;
+ *uint32_t counter;
+ *for (counter = 0; counter (WORD_SIZE / 32); counter++)
+ *{
+ *bool asel = ((counter 1) == 1);
+ *int in_sel = 0 + counter / 2;
+ *int32_t srca = get4Byte (rf[SrcA], in_sel);
+ *int32_t srcb = get4Byte (rf[SrcB], in_sel);
+ *output = set4Byte (output, counter, (asel ? srca : srcb));
+ *}
+ *rf[Dest] = output;
+*/
+
+static void gen_v4int_l(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+TCGv vdst = dest_gr(dc, rdst);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v4int_l r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+
+tcg_gen_andi_i64(vdst, load_gr(dc, rsrc), 0x);
+tcg_gen_shli_i64(vdst, vdst, 8);
+tcg_gen_andi_i64(tmp, load_gr(dc, rsrcb), 0x);
+tcg_gen_or_i64(vdst, vdst, tmp);
And herein is a bug, that I'd hope using the helper functions would avoid:
you
shift by 8 instead of 32. This function simplifies to
OK, thank you very much.
tcg_gen_deposit_i64(vdst, load_gr(dc, rsrc), load_gr(dc, rsrcb),
32, 32);
Oh, it should be:
tcg_gen_deposit_i64(vdst, load_gr(dc, rsrcb), load_gr(dc, rsrc),
32, 32);
Oh, it is:
tcg_gen_deposit_i64(vdst, load_gr(dc, rsrc), load_gr(dc, rsrcb),
0, 32);
OK, thanks.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish Hello world
Firstly, thank you very much for your valuable work and quick response.
On 6/2/15 02:40, Richard Henderson wrote:
First, what happened to the decoding skeleton patch? You seem to have merged
it with patch 9 here. That said, see the bottom of this message.
Yes, I merged them together. For me, it would be easier for reading and
discussing (they are in one c file within 3K, related with each other,
and sent together).
On 05/30/2015 02:18 PM, Chen Gang wrote:
+/* mfspr can be only in X1 pipe, so it doesn't need to be bufferd */
+static void gen_mfspr(struct DisasContext *dc, uint8_t rdst, uint16_t imm14)
I'm not keen on this as a comment. Clearly it could be buffered, with what is
implemented here now. But there are plenty of SPRs for which produce side
effects, and *cannot* be buffered.
Adjust the comment to
/* Many SPR reads have side effects and cannot be buffered. However, they are
all in the X1 pipe, which we are executing last, therefore we need not do
additional buffering. */
+/* mtspr can be only in X1 pipe, so it doesn't need to be bufferd */
Same, but s/reads/writes/.
OK, thanks.
+#if 1
Do not include this.
OK, thanks.
+/*
+ * uint64_t output = 0;
+ * uint32_t counter;
+ * for (counter = 0; counter (WORD_SIZE / BYTE_SIZE); counter++)
+ * {
+ * int8_t srca = getByte (rf[SrcA], counter);
+ * int8_t srcb = signExtend8 (Imm8);
+ * output = setByte (output, counter, ((srca == srcb) ? 1 : 0));
+ * }
+ * rf[Dest] = output;
+ */
+static void gen_v1cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, int8_t imm8)
Pass in the condition to use, since you'll eventually need to implement
v1cmpltsi, v1cmpltui.
+static void gen_v1cmpeq(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
Likewise for v1cmples, v1cmpleu, v1cmplts, v1cmpltu, v1cmpne.
OK, thanks.
+tcg_gen_movi_i64(vdst, 0); /* or Assertion `ts-val_type ==
TEMP_VAL_REG' */
These comments are unnecessary. Of course it's illegal to use an
uninitialized
temporary.
OK, thanks.
+static void gen_v4int_l(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v4int_l r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+tcg_gen_deposit_i64(dest_gr(dc, rdst), load_gr(dc, rsrc),
+load_gr(dc, rsrcb), 0, 32);
This is incorrect. This produces { A1, B0 }, not { A0, B0 }.
As I said, you did want 32, 32 as the field insert, but you have the source
operands in the wrong order.
OK, thank you very much.
+static void gen_addx(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+TCGv vdst = dest_gr(dc, rdst);
+
+/* High bits have no effect with low bits, so addx and addxsc are
merged. */
+qemu_log_mask(CPU_LOG_TB_IN_ASM, addx(sc) r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
Um, no, addxsc does signed saturation before sign extension.
OK, thank you very much. I shall fix it reference to add_saturate of arm
helper function.
+static void gen_mul_u_u(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb,
+int8 high, int8 highb, int8 add, const char *code)
A better name for this function is warranted, since it does much more than
mul_u_u. The add parameter should be type bool.
Given the existence of mul_hs_hs, mul_hu_ls, etc, you're probably better off
passing in extraction functions. E.g.
static void ext32s_high(TCGv d, TCGv s)
{
tcg_gen_sari_i64(d, s, 32);
}
static void ext32u_high(TCGv d, TCGv s)
{
tcg_gen_shri_i64(d, s, 32);
}
gen_mul(dc, rdst, rsrc, rsrcb, ext32s_high, ext32s_high,
false, mul_hs_hs);
gen_mul(dc, rdst, rsrc, rsrcb, ext32s_high, ext32u_high,
false, mul_hs_hu);
gen_mul(dc, rdst, rsrc, rsrcb, ext32s_high, tcg_gen_ext32s_i64,
false, mul_hs_ls);
gen_mul(dc, rdst, rsrc, rsrcb, ext32s_high, tcg_gen_ext32u_i64,
false, mul_hs_lu);
gen_mul(dc, rdst, rsrc, rsrcb, ext32u_high, ext32u_high,
false, mul_hu_hu);
gen_mul(dc, rdst, rsrc, rsrcb, ext32u_high, tcg_gen_ext32s_i64,
false, mul_hu_ls);
gen_mul(dc, rdst, rsrc, rsrcb, ext32u_high, tcg_gen_ext32u_i64,
false, mul_hu_lu);
gen_mul(dc, rdst, rsrc, rsrcb, tcg_gen_ext32s_i64, tcg_gen_ext32s_i64,
false, mul_ls_ls);
gen_mul(dc, rdst, rsrc, rsrcb, tcg_gen_ext32s_i64, tcg_gen_ext32u_i64,
false, mul_ls_lu);
gen_mul(dc, rdst, rsrc, rsrcb, tcg_gen_ext32u_i64, tcg_gen_ext32u_i64,
false, mul_lu_lu);
and of course the same for the mula insns with true instead of false for the
add parameter.
OK, thanks.
+static void gen_shladd(struct DisasContext *dc,
+ uint8_t rdst
[Qemu-devel] [PATCH 00/10 v11] tilegx: Firstly add tilegx target for linux-user
It can finish running Hello world elf64 binary, and the related test cases: - with --enable-debug, enable assertion with -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/a.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/b.log - without --enable-debug, disable asserion with -O2 -g: ./tilegx-linux-user/qemu-tilegx -L /upstream/release-tile /upstream/release-tile/test/test_shared ./tilegx-linux-user/qemu-tilegx -d all -L /upstream/release-tile /upstream/release-tile/test/test_shared /tmp/c.log ./tilegx-linux-user/qemu-tilegx /upstream/release-tile/test/test_static ./tilegx-linux-user/qemu-tilegx -d all /upstream/release-tile/test/test_static /tmp/d.log Chen Gang (10): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation arget-tilegx/opcode_tilegx.h: Modify it to fit qemu using target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add several helpers for instructions translation target-tilegx: Generate tcg instructions to finish Hello world target-tilegx: Add TILE-Gx building files configure |2 + default-configs/tilegx-linux-user.mak |1 + include/elf.h |2 + linux-user/elfload.c | 23 + linux-user/main.c | 236 +++ linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 35 + linux-user/tilegx/syscall_nr.h| 324 linux-user/tilegx/target_cpu.h| 35 + linux-user/tilegx/target_signal.h | 29 + linux-user/tilegx/target_structs.h| 48 + linux-user/tilegx/termbits.h | 285 target-tilegx/Makefile.objs |1 + target-tilegx/cpu.c | 143 ++ target-tilegx/cpu.h | 171 ++ target-tilegx/helper.c| 73 + target-tilegx/helper.h|4 + target-tilegx/opcode_tilegx.h | 1406 + target-tilegx/spr_def_64.h| 216 +++ target-tilegx/translate.c | 2787 + 21 files changed, 5879 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- 1.9.3
[Qemu-devel] [PATCH 08/10 v11] target-tilegx: Add several helpers for instructions translation
The related instructions are exception, cntlz, cnttz, and shufflebytes.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c | 73 ++
target-tilegx/helper.h | 4 +++
2 files changed, 77 insertions(+)
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
new file mode 100644
index 000..f125dc8
--- /dev/null
+++ b/target-tilegx/helper.c
@@ -0,0 +1,73 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include exec/helper-proto.h
+
+void helper_exception(CPUTLGState *env, uint32_t excp)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+
+cs-exception_index = excp;
+cpu_loop_exit(cs);
+}
+
+uint64_t helper_cntlz(uint64_t arg)
+{
+return clz64(arg);
+}
+
+uint64_t helper_cnttz(uint64_t arg)
+{
+return ctz64(arg);
+}
+
+/*
+ Functional Description
+ uint64_t a = rf[SrcA];
+ uint64_t b = rf[SrcB];
+ uint64_t d = rf[Dest];
+ uint64_t output = 0;
+ unsigned int counter;
+ for (counter = 0; counter (WORD_SIZE / BYTE_SIZE); counter++)
+ {
+ int sel = getByte (b, counter) 0xf;
+ uint8_t byte = (sel 8) ? getByte (d, sel) : getByte (a, (sel -
8));
+ output = setByte (output, counter, byte);
+ }
+ rf[Dest] = output;
+ */
+uint64_t helper_shufflebytes(uint64_t rdst, uint64_t rsrc, uint64_t rsrcb)
+{
+uint64_t vdst = 0;
+int count, sel;
+
+for (count = 0; count 8; count++) {
+sel = (rsrcb (count * 8)) 0xf;
+if (sel 8) {
+vdst |= ((rdst (8 * sel)) 0xff) (count * 8);
+} else {
+vdst |= ((rsrc (8 * (8 - sel))) 0xff) (count * 8);
+}
+}
+
+return vdst;
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
new file mode 100644
index 000..fd5517e
--- /dev/null
+++ b/target-tilegx/helper.h
@@ -0,0 +1,4 @@
+DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
--
1.9.3
[Qemu-devel] [PATCH 01/10 v11] linux-user: tilegx: Firstly add architecture related features
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/tilegx/syscall.h| 35
linux-user/tilegx/syscall_nr.h | 324 +
linux-user/tilegx/target_cpu.h | 35
linux-user/tilegx/target_signal.h | 29
linux-user/tilegx/target_structs.h | 48 ++
linux-user/tilegx/termbits.h | 285
6 files changed, 756 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 000..df55ec7
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,35 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE tilegx
+#define UNAME_MINIMUM_RELEASE 3.19
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+union {
+/* Saved main processor registers; 56..63 are special. */
+tilegx_reg_t regs[56];
+struct {
+tilegx_reg_t __regs[53];
+tilegx_reg_t tp;/* aliases regs[TREG_TP] */
+tilegx_reg_t sp;/* aliases regs[TREG_SP] */
+tilegx_reg_t lr;/* aliases regs[TREG_LR] */
+};
+};
+
+/* Saved special registers. */
+tilegx_reg_t pc;/* stored in EX_CONTEXT_K_0 */
+tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+tilegx_reg_t flags; /* flags (see below) */
+tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+#endif
diff --git a/linux-user/tilegx/syscall_nr.h b/linux-user/tilegx/syscall_nr.h
new file mode 100644
index 000..1dca348
--- /dev/null
+++ b/linux-user/tilegx/syscall_nr.h
@@ -0,0 +1,324 @@
+#ifndef TILEGX_SYSCALL_NR
+#define TILEGX_SYSCALL_NR
+
+/*
+ * Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr12
+#define TARGET_NR_flistxattr13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd17
+#define TARGET_NR_lookup_dcookie18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set30
+#define TARGET_NR_ioprio_get31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root41
+#define TARGET_NR_nfsservctl42
+#define TARGET_NR_statfs43
+#define TARGET_NR_fstatfs 44
+#define TARGET_NR_truncate 45
+#define TARGET_NR_ftruncate 46
[Qemu-devel] [PATCH 09/10 v11] target-tilegx: Generate tcg instructions to finish Hello world
Generate related tcg instructions, and qemu tilegx can finish running
Hello world. The elf64 binary can be static or shared.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/translate.c | 2787 +
1 file changed, 2787 insertions(+)
create mode 100644 target-tilegx/translate.c
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
new file mode 100644
index 000..7e45118
--- /dev/null
+++ b/target-tilegx/translate.c
@@ -0,0 +1,2787 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu/log.h
+#include disas/disas.h
+#include tcg-op.h
+#include exec/cpu_ldst.h
+#include opcode_tilegx.h
+#include spr_def_64.h
+
+#define FMT64X %016 PRIx64
+
+static TCGv_ptr cpu_env;
+static TCGv cpu_pc;
+static TCGv cpu_regs[TILEGX_R_COUNT];
+static TCGv cpu_spregs[TILEGX_SPR_COUNT];
+#if defined(CONFIG_USER_ONLY)
+static TCGv_i32 cpu_excparam;
+#endif
+
+static const char * const reg_names[] = {
+ r0, r1, r2, r3, r4, r5, r6, r7,
+ r8, r9, r10, r11, r12, r13, r14, r15,
+r16, r17, r18, r19, r20, r21, r22, r23,
+r24, r25, r26, r27, r28, r29, r30, r31,
+r32, r33, r34, r35, r36, r37, r38, r39,
+r40, r41, r42, r43, r44, r45, r46, r47,
+r48, r49, r50, r51, bp, tp, sp, lr
+};
+
+static const char * const spreg_names[] = {
+cmpexch, criticalsec, simcontrol
+};
+
+/* It is for temporary registers */
+typedef struct DisasContextTemp {
+uint8_t idx; /* index */
+TCGv val; /* value */
+} DisasContextTemp;
+
+/* This is the state at translation time. */
+typedef struct DisasContext {
+uint64_t pc; /* Current pc */
+uint64_t exception;/* Current exception */
+
+TCGv zero; /* For zero register */
+
+DisasContextTemp *tmp_regcur; /* Current temporary registers */
+DisasContextTemp tmp_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
+ /* All temporary registers */
+struct {
+TCGCond cond; /* Branch condition */
+TCGv dest; /* pc jump destination, if will jump */
+TCGv val1; /* Firt value for condition comparing */
+TCGv val2; /* Second value for condition comparing */
+} jmp; /* Jump object, only once in each TB block
*/
+} DisasContext;
+
+#include exec/gen-icount.h
+
+static TCGv load_zero(DisasContext *dc)
+{
+if (TCGV_IS_UNUSED_I64(dc-zero)) {
+dc-zero = tcg_const_i64(0);
+}
+return dc-zero;
+}
+
+static TCGv load_gr(DisasContext *dc, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return cpu_regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+dc-exception = TILEGX_EXCP_REG_UNSUPPORTED;
+}
+return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, uint8_t rdst)
+{
+DisasContextTemp *tmp = dc-tmp_regcur;
+tmp-idx = rdst;
+tmp-val = tcg_temp_new_i64();
+return tmp-val;
+}
+
+static void gen_exception(DisasContext *dc, int num)
+{
+TCGv_i32 tmp = tcg_const_i32(num);
+
+gen_helper_exception(cpu_env, tmp);
+tcg_temp_free_i32(tmp);
+}
+
+/* mfspr can be only in X1 pipe, so it doesn't need to be bufferd */
+static void gen_mfspr(struct DisasContext *dc, uint8_t rdst, uint16_t imm14)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, mfspr r%d, 0x%x\n, rdst, imm14);
+
+if (rdst = TILEGX_R_COUNT) {
+if (rdst != TILEGX_R_ZERO) {
+dc-exception = TILEGX_EXCP_REG_UNSUPPORTED;
+}
+return;
+}
+
+switch (imm14) {
+case SPR_CMPEXCH_VALUE:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_CMPEXCH]);
+return;
+case SPR_INTERRUPT_CRITICAL_SECTION:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_CRITICAL_SEC]);
+return;
+case SPR_SIM_CONTROL:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_SIM_CONTROL]);
+return;
+default:
+qemu_log_mask(LOG_UNIMP, UNIMP mfspr 0x%x.\n, imm14);
+}
+dc-exception = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+}
+
+/* mtspr can be only in X1 pipe, so it doesn't need
[Qemu-devel] [PATCH 10/10 v11] target-tilegx: Add TILE-Gx building files
Add related configuration, make files for tilegx. Now, qemu tilegx can pass building, and finish running Hello world static/shared elf64 binary. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- configure | 2 ++ default-configs/tilegx-linux-user.mak | 1 + target-tilegx/Makefile.objs | 1 + 3 files changed, 4 insertions(+) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 target-tilegx/Makefile.objs diff --git a/configure b/configure index 4e2f78a..92729eb 100755 --- a/configure +++ b/configure @@ -5294,6 +5294,8 @@ case $target_name in s390x) gdb_xml_files=s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml ;; + tilegx) + ;; tricore) ;; unicore32) diff --git a/default-configs/tilegx-linux-user.mak b/default-configs/tilegx-linux-user.mak new file mode 100644 index 000..3e47493 --- /dev/null +++ b/default-configs/tilegx-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for tilegx-linux-user diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs new file mode 100644 index 000..8b3dc76 --- /dev/null +++ b/target-tilegx/Makefile.objs @@ -0,0 +1 @@ +obj-y += cpu.o translate.o helper.o -- 1.9.3
[Qemu-devel] [PATCH 04/10 v11] target-tilegx: Add opcode basic implementation from Tilera Corporation
It is copied from Linux kernel arch/tile/include/uapi/arch/
opcode_tilegx.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
new file mode 100644
index 000..d76ff2d
--- /dev/null
+++ b/target-tilegx/opcode_tilegx.h
@@ -0,0 +1,1406 @@
+/* TILE-Gx opcode information.
+ *
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __ARCH_OPCODE_H__
+#define __ARCH_OPCODE_H__
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long long tilegx_bundle_bits;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
+
+enum
+{
+ /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+ /* Instructions take this many bytes. */
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+ /* Bundles should be aligned modulo this number of bytes. */
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+(1 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+ /* Number of registers (some are magic, such as network I/O). */
+ TILEGX_NUM_REGISTERS = 64,
+};
+
+/* Make a few tile_ variables to simplify common code between
+ architectures. */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 24)) 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 18)) 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 37)) 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 54)) 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 43)) 0x00c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0x);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 20)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 51)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0xff);
+}
+
+static
[Qemu-devel] [PATCH 06/10 v11] target-tilegx: Add special register information from Tilera Corporation
The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h diff --git a/target-tilegx/spr_def_64.h b/target-tilegx/spr_def_64.h new file mode 100644 index 000..67a6c17 --- /dev/null +++ b/target-tilegx/spr_def_64.h @@ -0,0 +1,216 @@ +/* + * Copyright 2011 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#ifndef __DOXYGEN__ + +#ifndef __ARCH_SPR_DEF_64_H__ +#define __ARCH_SPR_DEF_64_H__ + +#define SPR_AUX_PERF_COUNT_0 0x2105 +#define SPR_AUX_PERF_COUNT_1 0x2106 +#define SPR_AUX_PERF_COUNT_CTL 0x2107 +#define SPR_AUX_PERF_COUNT_STS 0x2108 +#define SPR_CMPEXCH_VALUE 0x2780 +#define SPR_CYCLE 0x2781 +#define SPR_DONE 0x2705 +#define SPR_DSTREAM_PF 0x2706 +#define SPR_EVENT_BEGIN 0x2782 +#define SPR_EVENT_END 0x2783 +#define SPR_EX_CONTEXT_0_0 0x2580 +#define SPR_EX_CONTEXT_0_1 0x2581 +#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_1_0 0x2480 +#define SPR_EX_CONTEXT_1_1 0x2481 +#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_2_0 0x2380 +#define SPR_EX_CONTEXT_2_1 0x2381 +#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 +#define SPR_FAIL 0x2707 +#define SPR_IDN_AVAIL_EN 0x1a05 +#define SPR_IDN_DATA_AVAIL 0x0a80 +#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 +#define SPR_IDN_DEMUX_COUNT_0 0x0a05 +#define SPR_IDN_DEMUX_COUNT_1 0x0a06 +#define SPR_IDN_DIRECTION_PROTECT 0x1405 +#define SPR_IDN_PENDING 0x0a08 +#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 +#define SPR_INTCTRL_0_STATUS 0x2505 +#define SPR_INTCTRL_1_STATUS 0x2405 +#define SPR_INTCTRL_2_STATUS 0x2305 +#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 +#define SPR_INTERRUPT_MASK_0 0x2506 +#define SPR_INTERRUPT_MASK_1 0x2406 +#define SPR_INTERRUPT_MASK_2 0x2306 +#define SPR_INTERRUPT_MASK_RESET_0 0x2507 +#define SPR_INTERRUPT_MASK_RESET_1 0x2407 +#define SPR_INTERRUPT_MASK_RESET_2 0x2307 +#define SPR_INTERRUPT_MASK_SET_0 0x2508 +#define SPR_INTERRUPT_MASK_SET_1 0x2408 +#define SPR_INTERRUPT_MASK_SET_2 0x2308 +#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 +#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 +#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 +#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 +#define SPR_IPI_EVENT_0 0x1f05 +#define SPR_IPI_EVENT_1 0x1e05 +#define SPR_IPI_EVENT_2 0x1d05 +#define SPR_IPI_EVENT_RESET_0 0x1f06 +#define SPR_IPI_EVENT_RESET_1 0x1e06 +#define SPR_IPI_EVENT_RESET_2 0x1d06 +#define SPR_IPI_EVENT_SET_0 0x1f07 +#define SPR_IPI_EVENT_SET_1 0x1e07 +#define SPR_IPI_EVENT_SET_2 0x1d07 +#define SPR_IPI_MASK_0 0x1f08 +#define SPR_IPI_MASK_1 0x1e08 +#define SPR_IPI_MASK_2 0x1d08 +#define SPR_IPI_MASK_RESET_0 0x1f09 +#define SPR_IPI_MASK_RESET_1 0x1e09 +#define SPR_IPI_MASK_RESET_2 0x1d09 +#define SPR_IPI_MASK_SET_0 0x1f0a +#define SPR_IPI_MASK_SET_1 0x1e0a +#define SPR_IPI_MASK_SET_2 0x1d0a +#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 +#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 +#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 +#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 +#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 +#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 +#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 +#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 +#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 +#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 +#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 +#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 +#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 +#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 +#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 +#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 +#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 +#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 +#define SPR_MPL_IDN_TIMER_SET_0 0x1800 +#define SPR_MPL_IDN_TIMER_SET_1 0x1801 +#define SPR_MPL_IDN_TIMER_SET_2 0x1802 +#define
[Qemu-devel] [PATCH 05/10 v11] arget-tilegx/opcode_tilegx.h: Modify it to fit qemu using
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of
unsigned long long
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/opcode_tilegx.h | 220 +-
1 file changed, 110 insertions(+), 110 deletions(-)
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
index d76ff2d..33b71a9 100644
--- a/target-tilegx/opcode_tilegx.h
+++ b/target-tilegx/opcode_tilegx.h
@@ -23,7 +23,7 @@
#ifndef __ASSEMBLER__
-typedef unsigned long long tilegx_bundle_bits;
+typedef uint64_t tilegx_bundle_bits;
/* These are the bits that determine if a bundle is in the X encoding. */
#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
@@ -66,360 +66,360 @@ typedef tilegx_bundle_bits tile_bundle_bits;
/* 64-bit pattern for a { bpt ; nop } bundle. */
#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-static __inline unsigned int
+static inline unsigned int
get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 24)) 0xf);
}
-static __inline unsigned int
+static inline unsigned int
get_BFStart_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 18)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_BrOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x0001ffc0);
}
-static __inline unsigned int
+static inline unsigned int
get_BrType_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 54)) 0x1f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 43)) 0x00c0);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 0)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x3f);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0x);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 20)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 51)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 12)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 43)) 0xff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOff_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x7ff);
}
-static __inline unsigned int
+static inline unsigned int
get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 58)) 0x1);
}
-static __inline unsigned int
+static inline unsigned int
get_MF_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 37)) 0x3fff);
}
-static __inline unsigned int
+static inline unsigned int
get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n 31)) 0x003f) |
(((unsigned int)(n 37)) 0x3fc0);
}
-static __inline unsigned int
+static inline unsigned int
get_Mode(tilegx_bundle_bits n)
{
return (((unsigned int)(n 62)) 0x3);
}
-static __inline unsigned int
+static inline unsigned int
get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n 28)) 0x7);
}
-static __inline unsigned int
+static inline unsigned int
[Qemu-devel] [PATCH 07/10 v11] target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu.c | 143 +++
target-tilegx/cpu.h | 171
2 files changed, 314 insertions(+)
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
new file mode 100644
index 000..663fcb6
--- /dev/null
+++ b/target-tilegx/cpu.c
@@ -0,0 +1,143 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include hw/qdev-properties.h
+#include migration/vmstate.h
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model)
+{
+TileGXCPU *cpu;
+
+cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
+return cpu;
+}
+
+static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+TileGXCPU *cpu = TILEGX_CPU(cs);
+
+cpu-env.pc = value;
+}
+
+static bool tilegx_cpu_has_work(CPUState *cs)
+{
+return true;
+}
+
+static void tilegx_cpu_reset(CPUState *s)
+{
+TileGXCPU *cpu = TILEGX_CPU(s);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
+CPUTLGState *env = cpu-env;
+
+tcc-parent_reset(s);
+
+memset(env, 0, sizeof(CPUTLGState));
+tlb_flush(s, 1);
+}
+
+static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+CPUState *cs = CPU(dev);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
+
+cpu_reset(cs);
+qemu_init_vcpu(cs);
+
+tcc-parent_realize(dev, errp);
+}
+
+static void tilegx_cpu_initfn(Object *obj)
+{
+CPUState *cs = CPU(obj);
+TileGXCPU *cpu = TILEGX_CPU(obj);
+CPUTLGState *env = cpu-env;
+static bool tcg_initialized;
+
+cs-env_ptr = env;
+cpu_exec_init(env);
+
+if (tcg_enabled() !tcg_initialized) {
+tcg_initialized = true;
+tilegx_tcg_init();
+}
+}
+
+static void tilegx_cpu_do_interrupt(CPUState *cs)
+{
+cs-exception_index = -1;
+}
+
+static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
+{
+cpu_dump_state(cs, stderr, fprintf, 0);
+return 1;
+}
+
+static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+if (interrupt_request CPU_INTERRUPT_HARD) {
+tilegx_cpu_do_interrupt(cs);
+return true;
+}
+return false;
+}
+
+static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+CPUClass *cc = CPU_CLASS(oc);
+TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
+
+tcc-parent_realize = dc-realize;
+dc-realize = tilegx_cpu_realizefn;
+
+tcc-parent_reset = cc-reset;
+cc-reset = tilegx_cpu_reset;
+
+cc-has_work = tilegx_cpu_has_work;
+cc-do_interrupt = tilegx_cpu_do_interrupt;
+cc-cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+cc-set_pc = tilegx_cpu_set_pc;
+cc-handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
+cc-gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tilegx_cpu_type_info = {
+.name = TYPE_TILEGX_CPU,
+.parent = TYPE_CPU,
+.instance_size = sizeof(TileGXCPU),
+.instance_init = tilegx_cpu_initfn,
+.class_size = sizeof(TileGXCPUClass),
+.class_init = tilegx_cpu_class_init,
+};
+
+static void tilegx_cpu_register_types(void)
+{
+type_register_static(tilegx_cpu_type_info);
+}
+
+type_init(tilegx_cpu_register_types)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
new file mode 100644
index 000..a0f4c6f
--- /dev/null
+++ b/target-tilegx/cpu.h
@@ -0,0 +1,171 @@
+/*
+ * TILE-Gx virtual CPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You
[Qemu-devel] [PATCH 02/10 v11] linux-user: Support tilegx architecture in linux-user
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
include/elf.h | 2 +
linux-user/elfload.c | 23 +
linux-user/main.c | 236 ++
linux-user/syscall_defs.h | 14 ++-
4 files changed, 270 insertions(+), 5 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 4afd474..79859f0 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
+#define EM_TILEGX 191 /* TILE-Gx */
+
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL0
#define DT_NEEDED 1
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 0ba9706..fbf9212 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1189,6 +1189,29 @@ static inline void init_thread(struct target_pt_regs
*regs, struct image_info *i
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+/* 42 bits real used address, a half for user mode */
+#define ELF_START_MMAP (0x00200ULL)
+
+#define elf_check_arch(x) ((x) == EM_TILEGX)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+regs-pc = infop-entry;
+regs-sp = infop-start_stack;
+
+}
+
+#define ELF_EXEC_PAGESIZE65536 /* TILE-Gx page size is 64KB */
+
+#endif /* TARGET_TILEGX */
+
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index 3f32db0..8e7fe86 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3416,6 +3416,231 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+static uint64_t get_regval(CPUTLGState *env, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return env-regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for reading.\n, reg);
+g_assert_not_reached();
+}
+return 0;
+}
+
+static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+env-regs[reg] = val;
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for writing.\n, reg);
+g_assert_not_reached();
+}
+}
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values are
+ * not equal, then no memory operation is performed. If the values are equal,
+ * the 8-byte quantity from the second source register is written into memory
+ * at the address held in the first source register. In either case, the result
+ * of the instruc- tion is the value read from memory. The compare and write to
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * For exch(4), will no cmp spr.
+ */
+static void do_exch(CPUTLGState *env, int8_t quad, int8_t cmp)
+{
+uint8_t rdst, rsrc, rsrcb;
+target_ulong addr, tmp;
+target_long val, sprval;
+target_siginfo_t info;
+
+start_exclusive();
+
+rdst = (env-excparam 16) 0xff;
+rsrc = (env-excparam 8) 0xff;
+rsrcb = env-excparam 0xff;
+
+addr = get_regval(env, rsrc);
+if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+goto do_sigsegv;
+}
+tmp = (target_ulong)val; /* rdst may be the same to rsrcb, so buffer it */
+
+if (cmp) {
+if (quad) {
+sprval = (target_long)env-spregs[TILEGX_SPR_CMPEXCH];
+} else {
+sprval = (int32_t)(env-spregs[TILEGX_SPR_CMPEXCH] 0x);
+}
+}
+
+if (!cmp || val == sprval) {
+val = get_regval(env, rsrcb);
+if (quad ? put_user_u64(val, addr) : put_user_u32(val, addr)) {
+goto do_sigsegv;
+}
+}
+
+set_regval(env, rdst, tmp);
+
+end_exclusive();
+return;
+
+do_sigsegv:
+end_exclusive();
+
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+info.si_code = TARGET_SEGV_MAPERR;
+info._sifields
[Qemu-devel] [PATCH 03/10 v11] linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/syscall.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 1622ad6..a503673 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
-#ifdef __NR_getdents
+#if defined(TARGET_NR_getdents) defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint,
count);
#endif
#if !defined(__NR_getdents) || \
@@ -5581,6 +5581,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
+#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -5589,6 +5590,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@@ -5603,9 +5605,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
+#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
+#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@@ -5640,6 +5644,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
+#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@@ -5653,6 +5658,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@@ -5670,12 +5676,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@@ -5792,12 +5800,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@@ -5806,12 +5816,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@@ -5946,6 +5958,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@@ -5964,6 +5977,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@@ -5992,12 +6006,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
+#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_faccessat) defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@@ -6022,6 +6038,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
+#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@@ -6035,6 +6052,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@@ -6050,12 +6068,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 00:55, Richard Henderson wrote:
+static void gen_v1cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v1cmpeqi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+
+tcg_gen_movi_i64(vdst, 0);
+
+for (count = 0; count 8; count++) {
+tcg_gen_shri_i64(tmp, load_gr(dc, rsrc), (8 - count - 1) * 8);
+tcg_gen_andi_i64(tmp, tmp, 0xff);
+tcg_gen_setcondi_i64(TCG_COND_EQ, tmp, tmp, imm8);
+tcg_gen_or_i64(vdst, vdst, tmp);
+tcg_gen_shli_i64(vdst, vdst, 8);
For all of these vector instructions, I would encourage you to use helpers to
extract and insert values. Extraction has little choice but to use a shift
and
a mask, as you use here. But insertion can use tcg_gen_deposit_i64. I think
that is a lot easier to reason with than your construction here which
sequentially shifts vdst.
E.g.
static inline void
extract_v1(TCGv out, TCGv in, unsigned byte)
{
tcg_gen_shri_i64(out, in, byte * 8);
tcg_gen_ext8u_i64(out, out);
}
static inline void
insert_v1(TCGv out, TCGv in, unsigned byte)
{
tcg_gen_deposit_i64(out, out, in, byte * 8, 8);
}
This loop then becomes
TCGv vsrc = load_gr(dc, src);
for (count = 0; count 8; ++count) {
extract_v1(tmp, vsrc, count);
tcg_gen_setcondi_i64(TCG_COND_EQ, tmp, tmp, imm8);
insert_v1(vdst, tmp, count);
}
It also needs tcg_gen_movi_i64(vdst, 0); or will generate assertion
`ts-val_type == TEMP_VAL_REG' in debug mode.
And I shall try to send patch within one day (sorry for a little late).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 05:26, Chen Gang wrote:
+}
+
+/*
+ * Functional Description
+ *
+ *uint64_t output = 0;
+ *uint32_t counter;
+ *for (counter = 0; counter (WORD_SIZE / 32); counter++)
+ *{
+ *bool asel = ((counter 1) == 1);
+ *int in_sel = 0 + counter / 2;
+ *int32_t srca = get4Byte (rf[SrcA], in_sel);
+ *int32_t srcb = get4Byte (rf[SrcB], in_sel);
+ *output = set4Byte (output, counter, (asel ? srca : srcb));
+ *}
+ *rf[Dest] = output;
+*/
+
+static void gen_v4int_l(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+TCGv vdst = dest_gr(dc, rdst);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v4int_l r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+
+tcg_gen_andi_i64(vdst, load_gr(dc, rsrc), 0x);
+tcg_gen_shli_i64(vdst, vdst, 8);
+tcg_gen_andi_i64(tmp, load_gr(dc, rsrcb), 0x);
+tcg_gen_or_i64(vdst, vdst, tmp);
And herein is a bug, that I'd hope using the helper functions would avoid:
you
shift by 8 instead of 32. This function simplifies to
OK, thank you very much.
tcg_gen_deposit_i64(vdst, load_gr(dc, rsrc), load_gr(dc, rsrcb),
32, 32);
Oh, it is:
tcg_gen_deposit_i64(vdst, load_gr(dc, rsrc), load_gr(dc, rsrcb),
0, 32);
OK, thanks.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
Also additional bug: when a block finishes with no branch insn (e.g. the insns are too much to be in a block), we need to modify pc and exit_tb. I found this bug when mark -d all for Hello world with shared glibc. At present, I finished all Hello world related test cases which I can find, and begin make patches for tilegx, next. Welcome any ideas, suggestions and completions (e.g. for test cases). If no additional reply, I shall send patches for tilegx within 4 days. Thanks. On 5/25/15 06:03, Chen Gang wrote: For Hello world with shared glibc, it needs to implement additional instructions and fix one additional bug (it is about syscall_nr.h: need stat64 and fstatat64). I shall send patch v11 within this month. :-) Thanks. On 5/22/15 09:48, Chen Gang wrote: On 05/22/2015 07:40 AM, Chris Metcalf wrote: Congratulations! Again, really thank all of you very much!! :-) On May 21, 2015, at 4:58 PM, Chen Gang xili_gchen_5...@hotmail.com wrote: After fix additional 3 bugs (one for mnz, one for mz, one for v1cmpeqi), at present, tilegx linux user can print Hello World! :-) I shall reconstruct/prepare the code and send patch v11 for review within this month. Thanks. On 5/19/15 10:47, Chen Gang wrote: Hello All: I also found another bug: I did not set the system call error number to r1 register, which will cause new_heap() fail although mmap64 succeed. Hope it is my last bug for printing Hello world executable binary. Thanks. On 05/12/2015 07:16 PM, Chen Gang wrote: On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
For Hello world with shared glibc, it needs to implement additional instructions and fix one additional bug (it is about syscall_nr.h: need stat64 and fstatat64). I shall send patch v11 within this month. :-) Thanks. On 5/22/15 09:48, Chen Gang wrote: On 05/22/2015 07:40 AM, Chris Metcalf wrote: Congratulations! Again, really thank all of you very much!! :-) On May 21, 2015, at 4:58 PM, Chen Gang xili_gchen_5...@hotmail.com wrote: After fix additional 3 bugs (one for mnz, one for mz, one for v1cmpeqi), at present, tilegx linux user can print Hello World! :-) I shall reconstruct/prepare the code and send patch v11 for review within this month. Thanks. On 5/19/15 10:47, Chen Gang wrote: Hello All: I also found another bug: I did not set the system call error number to r1 register, which will cause new_heap() fail although mmap64 succeed. Hope it is my last bug for printing Hello world executable binary. Thanks. On 05/12/2015 07:16 PM, Chen Gang wrote: On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
After fix additional 3 bugs (one for mnz, one for mz, one for v1cmpeqi), at present, tilegx linux user can print Hello World! :-) I shall reconstruct/prepare the code and send patch v11 for review within this month. Thanks. On 5/19/15 10:47, Chen Gang wrote: Hello All: I also found another bug: I did not set the system call error number to r1 register, which will cause new_heap() fail although mmap64 succeed. Hope it is my last bug for printing Hello world executable binary. Thanks. On 05/12/2015 07:16 PM, Chen Gang wrote: On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
On 05/22/2015 07:40 AM, Chris Metcalf wrote: Congratulations! Again, really thank all of you very much!! :-) On May 21, 2015, at 4:58 PM, Chen Gang xili_gchen_5...@hotmail.com wrote: After fix additional 3 bugs (one for mnz, one for mz, one for v1cmpeqi), at present, tilegx linux user can print Hello World! :-) I shall reconstruct/prepare the code and send patch v11 for review within this month. Thanks. On 5/19/15 10:47, Chen Gang wrote: Hello All: I also found another bug: I did not set the system call error number to r1 register, which will cause new_heap() fail although mmap64 succeed. Hope it is my last bug for printing Hello world executable binary. Thanks. On 05/12/2015 07:16 PM, Chen Gang wrote: On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
Hello All: I also found another bug: I did not set the system call error number to r1 register, which will cause new_heap() fail although mmap64 succeed. Hope it is my last bug for printing Hello world executable binary. Thanks. On 05/12/2015 07:16 PM, Chen Gang wrote: On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 00:55, Richard Henderson wrote:
On 05/10/2015 03:45 PM, Chen Gang wrote:
+static void gen_cmpltsi(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltsi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+ (int64_t)imm8);
It is another bug (which the root cause to lead current _init_malloc to
assert). Need use TCG_COND_LT instead of TCG_COND_LTU.
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
Merge these.
Thank you again for your reviewing. Next, I shall continue for printing
Hello world.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 00:55, Richard Henderson wrote:
On 05/10/2015 03:45 PM, Chen Gang wrote:
+static void gen_cmpltsi(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltsi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+ (int64_t)imm8);
+}
It is another bug: need to use TCG_COND_LT instead of TCG_COND_LTU.
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t imm8)
For imm8, its type needs to be int8_t.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
For imm8, its type needs to be int8_t.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
Merge these.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 00:55, Richard Henderson wrote:
On 05/10/2015 03:45 PM, Chen Gang wrote:
+static void gen_cmpltsi(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltsi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+ (int64_t)imm8);
It is another bug (which the root cause to lead current _init_malloc to
assert). Need use TCG_COND_LT instead of TCG_COND_LTU.
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
Merge these.
Next, I shall continue for printing Hello world.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
On 5/12/15 00:55, Richard Henderson wrote:
On 05/10/2015 03:45 PM, Chen Gang wrote:
+static void gen_cmpltsi(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltsi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+ (int64_t)imm8);
It is another bug (which the root cause to lead current _init_malloc to
assert). Need use TCG_COND_LT instead of TCG_COND_LTU.
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
Need to be int8_t for imm8.
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
Merge these.
Thank you again for your reviewing. Next, I shall continue to print
Hello world.
Thanks.
-- Chen Gang Open, share, and attitude like air, water, and life which God
blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). Thanks. On 05/12/2015 08:43 AM, gchen gchen wrote: For me, I still stick to uint8_t, since all callers and callee always treat it as uint8_t. It will make the code more clearer for readers. Date: Mon, 11 May 2015 15:06:48 -0700 From: r...@twiddle.net To: xili_gchen_5...@hotmail.com; peter.mayd...@linaro.org; afaer...@suse.de; cmetc...@ezchip.com CC: riku.voi...@iki.fi; w...@tilera.com; qemu-devel@nongnu.org Subject: Re: [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using On 05/11/2015 02:06 PM, Chen Gang wrote: On 5/12/15 00:01, Richard Henderson wrote: On 05/10/2015 03:42 PM, Chen Gang wrote: -static __inline unsigned int +static inline uint8_t get_BFEnd_X0(tilegx_bundle_bits num) Do not change these casts to uint8_t. It's unnecessary churn. For me, it is enough to return uint8_t, and the caller really treats it as uint8_t. So for the function declaration, uint8_t is more precise than unsigned int for return type. I don't want to argue about this anymore. Drop all the uint8_t and uint16_t. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
On 05/12/2015 07:08 PM, Peter Maydell wrote: On 12 May 2015 at 11:56, Chen Gang xili_gchen_5...@hotmail.com wrote: Welcome any other members' ideas, suggestions or completions for it. If one of another members also suggests to drop all uint8_t and uint16_t, I shall drop them (more explanations for dropping them will be better). I agree with Richard on this one. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
Firstly, thank you very much for your response quickly!
On 5/12/15 00:55, Richard Henderson wrote:
On 05/10/2015 03:45 PM, Chen Gang wrote:
+static void gen_cmpltsi(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltsi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc, rsrc),
+ (int64_t)imm8);
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ,
+ dest_gr(dc, rdst), load_gr(dc, rsrc), imm8);
+}
Merge these.
OK, thanks.
+
+static void gen_cmp(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb, TCGCond cond)
+{
+const char *prefix;
+
+switch (cond) {
+case TCG_COND_EQ:
+prefix = eq;
+break;
+case TCG_COND_LE:
+prefix = les;
+break;
+case TCG_COND_LEU:
+prefix = leu;
+break;
+case TCG_COND_LT:
+prefix = lts;
+break;
+case TCG_COND_LTU:
+prefix = ltu;
+break;
+case TCG_COND_NE:
+prefix = ne;
+break;
+default:
+dc-exception = TILEGX_EXCP_OPCODE_UNKNOWN;
+return;
+}
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmp%s r%d, r%d, r%d\n,
+ prefix, rdst, rsrc, rsrcb);
Better to just pass down the opcode name with the TCGCond rather than trying
to
recreate it. Then there's no need for a switch, nor a need for a confusing
TILEGX_EXCP_OPCODE_UNKNOWN path.
+static void gen_exch(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t rsrcb, int excp)
+{
+const char *prefix, *width;
+
+switch (excp) {
+case TILEGX_EXCP_OPCODE_EXCH4:
+prefix = ;
+width = 4;
+break;
+case TILEGX_EXCP_OPCODE_EXCH:
+prefix = ;
+width = ;
+break;
+case TILEGX_EXCP_OPCODE_CMPEXCH4:
+prefix = cmp;
+width = 4;
+break;
+case TILEGX_EXCP_OPCODE_CMPEXCH:
+prefix = cmp;
+width = ;
+break;
+default:
+dc-exception = TILEGX_EXCP_OPCODE_UNKNOWN;
+return;
+}
Likewise.
OK, thanks.
+static void gen_v1cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t imm8)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v1cmpeqi r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+
+tcg_gen_movi_i64(vdst, 0);
+
+for (count = 0; count 8; count++) {
+tcg_gen_shri_i64(tmp, load_gr(dc, rsrc), (8 - count - 1) * 8);
+tcg_gen_andi_i64(tmp, tmp, 0xff);
+tcg_gen_setcondi_i64(TCG_COND_EQ, tmp, tmp, imm8);
+tcg_gen_or_i64(vdst, vdst, tmp);
+tcg_gen_shli_i64(vdst, vdst, 8);
For all of these vector instructions, I would encourage you to use helpers to
extract and insert values. Extraction has little choice but to use a shift
and
a mask, as you use here. But insertion can use tcg_gen_deposit_i64. I think
that is a lot easier to reason with than your construction here which
sequentially shifts vdst.
E.g.
static inline void
extract_v1(TCGv out, TCGv in, unsigned byte)
{
tcg_gen_shri_i64(out, in, byte * 8);
tcg_gen_ext8u_i64(out, out);
}
static inline void
insert_v1(TCGv out, TCGv in, unsigned byte)
{
tcg_gen_deposit_i64(out, out, in, byte * 8, 8);
}
This loop then becomes
TCGv vsrc = load_gr(dc, src);
for (count = 0; count 8; ++count) {
extract_v1(tmp, vsrc, count);
tcg_gen_setcondi_i64(TCG_COND_EQ, tmp, tmp, imm8);
insert_v1(vdst, tmp, count);
}
+static void gen_v1int_l(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+int count;
+TCGv vdst = dest_gr(dc, rdst);
+TCGv tmp = tcg_temp_new_i64();
+
+qemu_log_mask(CPU_LOG_TB_IN_ASM, v1int_l r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+
+tcg_gen_movi_i64(vdst, 0);
+for (count = 0; count 4; count++) {
+
+tcg_gen_shli_i64(vdst, vdst, 8);
+
+tcg_gen_shri_i64(tmp, load_gr(dc, rsrc), (4 - count - 1) * 8);
+tcg_gen_andi_i64(tmp, tmp, 0xff
Re: [Qemu-devel] [PATCH 05/10 v10] target-tilegx/opcode_tilegx.h: Modify it to fit qemu using
On 5/12/15 00:01, Richard Henderson wrote: On 05/10/2015 03:42 PM, Chen Gang wrote: -static __inline unsigned int +static inline uint8_t get_BFEnd_X0(tilegx_bundle_bits num) Do not change these casts to uint8_t. It's unnecessary churn. For me, it is enough to return uint8_t, and the caller really treats it as uint8_t. So for the function declaration, uint8_t is more precise than unsigned int for return type. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [PATCH 09/10 v10] target-tilegx: Generate tcg instructions to execute to _init_malloc in glib
Generate related tcg instructions, and qemu tilegx runs to _init_malloc,
but causes assert in _init_malloc.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/translate.c | 2889 +
1 file changed, 2889 insertions(+)
create mode 100644 target-tilegx/translate.c
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
new file mode 100644
index 000..3d7d327
--- /dev/null
+++ b/target-tilegx/translate.c
@@ -0,0 +1,2889 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu/log.h
+#include disas/disas.h
+#include tcg-op.h
+#include exec/cpu_ldst.h
+#include opcode_tilegx.h
+#include spr_def_64.h
+
+#define FMT64X %016 PRIx64
+
+#define TILEGX_OPCODE_MAX_X0164 /* include 164 */
+#define TILEGX_OPCODE_MAX_X1107 /* include 107 */
+#define TILEGX_OPCODE_MAX_Y0 15 /* include 15 */
+#define TILEGX_OPCODE_MAX_Y1 15 /* include 15 */
+#define TILEGX_OPCODE_MAX_Y2 3 /* include 3 */
+
+static TCGv_ptr cpu_env;
+static TCGv cpu_pc;
+static TCGv cpu_regs[TILEGX_R_COUNT];
+static TCGv cpu_spregs[TILEGX_SPR_COUNT];
+#if defined(CONFIG_USER_ONLY)
+static TCGv_i32 cpu_cmpexch;
+#endif
+
+static const char * const reg_names[] = {
+ r0, r1, r2, r3, r4, r5, r6, r7,
+ r8, r9, r10, r11, r12, r13, r14, r15,
+r16, r17, r18, r19, r20, r21, r22, r23,
+r24, r25, r26, r27, r28, r29, r30, r31,
+r32, r33, r34, r35, r36, r37, r38, r39,
+r40, r41, r42, r43, r44, r45, r46, r47,
+r48, r49, r50, r51, bp, tp, sp, lr
+};
+
+static const char * const spreg_names[] = {
+cmpexch
+};
+
+/* It is for temporary registers */
+typedef struct DisasContextTemp {
+uint8_t idx; /* index */
+TCGv val; /* value */
+} DisasContextTemp;
+
+/* This is the state at translation time. */
+typedef struct DisasContext {
+uint64_t pc; /* Current pc */
+uint64_t exception;/* Current exception */
+
+TCGv zero; /* For zero register */
+
+DisasContextTemp *tmp_regcur; /* Current temporary registers */
+DisasContextTemp tmp_regs[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE];
+ /* All temporary registers */
+struct {
+TCGCond cond; /* Branch condition */
+TCGv dest; /* pc jump destination, if will jump */
+TCGv val1; /* Firt value for condition comparing */
+TCGv val2; /* Second value for condition comparing */
+} jmp; /* Jump object, only once in each TB block
*/
+} DisasContext;
+
+#include exec/gen-icount.h
+
+static TCGv load_zero(DisasContext *dc)
+{
+if (TCGV_IS_UNUSED_I64(dc-zero)) {
+dc-zero = tcg_const_local_i64(0);
+}
+return dc-zero;
+}
+
+static TCGv load_gr(DisasContext *dc, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return cpu_regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+dc-exception = TILEGX_EXCP_REG_UNSUPPORTED;
+}
+return load_zero(dc);
+}
+
+static TCGv dest_gr(DisasContext *dc, uint8_t rdst)
+{
+DisasContextTemp *tmp = dc-tmp_regcur;
+tmp-idx = rdst;
+tmp-val = tcg_temp_new_i64();
+return tmp-val;
+}
+
+static void gen_exception(DisasContext *dc, int num)
+{
+TCGv_i32 tmp = tcg_const_i32(num);
+
+gen_helper_exception(cpu_env, tmp);
+tcg_temp_free_i32(tmp);
+}
+
+/* mfspr can be only in X1 pipe, so it doesn't need to be bufferd */
+static void gen_mfspr(struct DisasContext *dc, uint8_t rdst, uint16_t imm14)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, mfspr r%d, 0x%x\n, rdst, imm14);
+
+if (rdst = TILEGX_R_COUNT) {
+if (rdst != TILEGX_R_ZERO) {
+dc-exception = TILEGX_EXCP_REG_UNSUPPORTED;
+}
+return;
+}
+
+switch (imm14) {
+case SPR_CMPEXCH_VALUE:
+tcg_gen_mov_i64(cpu_regs[rdst], cpu_spregs[TILEGX_SPR_CMPEXCH]);
+return;
+default:
+qemu_log_mask(LOG_UNIMP, UNIMP mfspr 0x%x.\n, imm14);
+}
+dc-exception = TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
+}
+
+/* mtspr can be only in X1 pipe
[Qemu-devel] [PATCH 10/10 v10] target-tilegx: Add TILE-Gx building files
Add related configuration, make files for tilegx. Now, qemu tilegx can pass building. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- configure | 2 ++ default-configs/tilegx-linux-user.mak | 1 + target-tilegx/Makefile.objs | 1 + 3 files changed, 4 insertions(+) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 target-tilegx/Makefile.objs diff --git a/configure b/configure index b18aa9e..0a32741 100755 --- a/configure +++ b/configure @@ -5243,6 +5243,8 @@ case $target_name in s390x) gdb_xml_files=s390x-core64.xml s390-acr.xml s390-fpr.xml ;; + tilegx) + ;; tricore) ;; unicore32) diff --git a/default-configs/tilegx-linux-user.mak b/default-configs/tilegx-linux-user.mak new file mode 100644 index 000..3e47493 --- /dev/null +++ b/default-configs/tilegx-linux-user.mak @@ -0,0 +1 @@ +# Default configuration for tilegx-linux-user diff --git a/target-tilegx/Makefile.objs b/target-tilegx/Makefile.objs new file mode 100644 index 000..8b3dc76 --- /dev/null +++ b/target-tilegx/Makefile.objs @@ -0,0 +1 @@ +obj-y += cpu.o translate.o helper.o -- 1.9.3
[Qemu-devel] [PATCH 06/10 v10] target-tilegx: Add special register information from Tilera Corporation
The related copy is from Linux kernel arch/tile/include/uapi/arch/ spr_def_64.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com --- target-tilegx/spr_def_64.h | 216 + 1 file changed, 216 insertions(+) create mode 100644 target-tilegx/spr_def_64.h diff --git a/target-tilegx/spr_def_64.h b/target-tilegx/spr_def_64.h new file mode 100644 index 000..67a6c17 --- /dev/null +++ b/target-tilegx/spr_def_64.h @@ -0,0 +1,216 @@ +/* + * Copyright 2011 Tilera Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, version 2. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or + * NON INFRINGEMENT. See the GNU General Public License for + * more details. + */ + +#ifndef __DOXYGEN__ + +#ifndef __ARCH_SPR_DEF_64_H__ +#define __ARCH_SPR_DEF_64_H__ + +#define SPR_AUX_PERF_COUNT_0 0x2105 +#define SPR_AUX_PERF_COUNT_1 0x2106 +#define SPR_AUX_PERF_COUNT_CTL 0x2107 +#define SPR_AUX_PERF_COUNT_STS 0x2108 +#define SPR_CMPEXCH_VALUE 0x2780 +#define SPR_CYCLE 0x2781 +#define SPR_DONE 0x2705 +#define SPR_DSTREAM_PF 0x2706 +#define SPR_EVENT_BEGIN 0x2782 +#define SPR_EVENT_END 0x2783 +#define SPR_EX_CONTEXT_0_0 0x2580 +#define SPR_EX_CONTEXT_0_1 0x2581 +#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_1_0 0x2480 +#define SPR_EX_CONTEXT_1_1 0x2481 +#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4 +#define SPR_EX_CONTEXT_2_0 0x2380 +#define SPR_EX_CONTEXT_2_1 0x2381 +#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0 +#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3 +#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3 +#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2 +#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1 +#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4 +#define SPR_FAIL 0x2707 +#define SPR_IDN_AVAIL_EN 0x1a05 +#define SPR_IDN_DATA_AVAIL 0x0a80 +#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806 +#define SPR_IDN_DEMUX_COUNT_0 0x0a05 +#define SPR_IDN_DEMUX_COUNT_1 0x0a06 +#define SPR_IDN_DIRECTION_PROTECT 0x1405 +#define SPR_IDN_PENDING 0x0a08 +#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1 +#define SPR_INTCTRL_0_STATUS 0x2505 +#define SPR_INTCTRL_1_STATUS 0x2405 +#define SPR_INTCTRL_2_STATUS 0x2305 +#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708 +#define SPR_INTERRUPT_MASK_0 0x2506 +#define SPR_INTERRUPT_MASK_1 0x2406 +#define SPR_INTERRUPT_MASK_2 0x2306 +#define SPR_INTERRUPT_MASK_RESET_0 0x2507 +#define SPR_INTERRUPT_MASK_RESET_1 0x2407 +#define SPR_INTERRUPT_MASK_RESET_2 0x2307 +#define SPR_INTERRUPT_MASK_SET_0 0x2508 +#define SPR_INTERRUPT_MASK_SET_1 0x2408 +#define SPR_INTERRUPT_MASK_SET_2 0x2308 +#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509 +#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409 +#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309 +#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209 +#define SPR_IPI_EVENT_0 0x1f05 +#define SPR_IPI_EVENT_1 0x1e05 +#define SPR_IPI_EVENT_2 0x1d05 +#define SPR_IPI_EVENT_RESET_0 0x1f06 +#define SPR_IPI_EVENT_RESET_1 0x1e06 +#define SPR_IPI_EVENT_RESET_2 0x1d06 +#define SPR_IPI_EVENT_SET_0 0x1f07 +#define SPR_IPI_EVENT_SET_1 0x1e07 +#define SPR_IPI_EVENT_SET_2 0x1d07 +#define SPR_IPI_MASK_0 0x1f08 +#define SPR_IPI_MASK_1 0x1e08 +#define SPR_IPI_MASK_2 0x1d08 +#define SPR_IPI_MASK_RESET_0 0x1f09 +#define SPR_IPI_MASK_RESET_1 0x1e09 +#define SPR_IPI_MASK_RESET_2 0x1d09 +#define SPR_IPI_MASK_SET_0 0x1f0a +#define SPR_IPI_MASK_SET_1 0x1e0a +#define SPR_IPI_MASK_SET_2 0x1d0a +#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100 +#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101 +#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102 +#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700 +#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701 +#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702 +#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00 +#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01 +#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02 +#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00 +#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01 +#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02 +#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500 +#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501 +#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502 +#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400 +#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401 +#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402 +#define SPR_MPL_IDN_TIMER_SET_0 0x1800 +#define SPR_MPL_IDN_TIMER_SET_1 0x1801 +#define SPR_MPL_IDN_TIMER_SET_2 0x1802 +#define
[Qemu-devel] [PATCH 07/10 v10] target-tilegx: Add cpu basic features for linux-user
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu.c | 143 +++
target-tilegx/cpu.h | 156
2 files changed, 299 insertions(+)
create mode 100644 target-tilegx/cpu.c
create mode 100644 target-tilegx/cpu.h
diff --git a/target-tilegx/cpu.c b/target-tilegx/cpu.c
new file mode 100644
index 000..663fcb6
--- /dev/null
+++ b/target-tilegx/cpu.c
@@ -0,0 +1,143 @@
+/*
+ * QEMU TILE-Gx CPU
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include hw/qdev-properties.h
+#include migration/vmstate.h
+
+TileGXCPU *cpu_tilegx_init(const char *cpu_model)
+{
+TileGXCPU *cpu;
+
+cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
+
+object_property_set_bool(OBJECT(cpu), true, realized, NULL);
+
+return cpu;
+}
+
+static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
+{
+TileGXCPU *cpu = TILEGX_CPU(cs);
+
+cpu-env.pc = value;
+}
+
+static bool tilegx_cpu_has_work(CPUState *cs)
+{
+return true;
+}
+
+static void tilegx_cpu_reset(CPUState *s)
+{
+TileGXCPU *cpu = TILEGX_CPU(s);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
+CPUTLGState *env = cpu-env;
+
+tcc-parent_reset(s);
+
+memset(env, 0, sizeof(CPUTLGState));
+tlb_flush(s, 1);
+}
+
+static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
+{
+CPUState *cs = CPU(dev);
+TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
+
+cpu_reset(cs);
+qemu_init_vcpu(cs);
+
+tcc-parent_realize(dev, errp);
+}
+
+static void tilegx_cpu_initfn(Object *obj)
+{
+CPUState *cs = CPU(obj);
+TileGXCPU *cpu = TILEGX_CPU(obj);
+CPUTLGState *env = cpu-env;
+static bool tcg_initialized;
+
+cs-env_ptr = env;
+cpu_exec_init(env);
+
+if (tcg_enabled() !tcg_initialized) {
+tcg_initialized = true;
+tilegx_tcg_init();
+}
+}
+
+static void tilegx_cpu_do_interrupt(CPUState *cs)
+{
+cs-exception_index = -1;
+}
+
+static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
+ int mmu_idx)
+{
+cpu_dump_state(cs, stderr, fprintf, 0);
+return 1;
+}
+
+static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
+{
+if (interrupt_request CPU_INTERRUPT_HARD) {
+tilegx_cpu_do_interrupt(cs);
+return true;
+}
+return false;
+}
+
+static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
+{
+DeviceClass *dc = DEVICE_CLASS(oc);
+CPUClass *cc = CPU_CLASS(oc);
+TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
+
+tcc-parent_realize = dc-realize;
+dc-realize = tilegx_cpu_realizefn;
+
+tcc-parent_reset = cc-reset;
+cc-reset = tilegx_cpu_reset;
+
+cc-has_work = tilegx_cpu_has_work;
+cc-do_interrupt = tilegx_cpu_do_interrupt;
+cc-cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
+cc-set_pc = tilegx_cpu_set_pc;
+cc-handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
+cc-gdb_num_core_regs = 0;
+}
+
+static const TypeInfo tilegx_cpu_type_info = {
+.name = TYPE_TILEGX_CPU,
+.parent = TYPE_CPU,
+.instance_size = sizeof(TileGXCPU),
+.instance_init = tilegx_cpu_initfn,
+.class_size = sizeof(TileGXCPUClass),
+.class_init = tilegx_cpu_class_init,
+};
+
+static void tilegx_cpu_register_types(void)
+{
+type_register_static(tilegx_cpu_type_info);
+}
+
+type_init(tilegx_cpu_register_types)
diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h
new file mode 100644
index 000..30f1828
--- /dev/null
+++ b/target-tilegx/cpu.h
@@ -0,0 +1,156 @@
+/*
+ * TILE-Gx virtual CPU header
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details
[Qemu-devel] [PATCH 08/10 v10] target-tilegx: Add helper features for linux-user
Add several helpers for translation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/helper.c | 41 +
target-tilegx/helper.h | 3 +++
2 files changed, 44 insertions(+)
create mode 100644 target-tilegx/helper.c
create mode 100644 target-tilegx/helper.h
diff --git a/target-tilegx/helper.c b/target-tilegx/helper.c
new file mode 100644
index 000..5fc53a8
--- /dev/null
+++ b/target-tilegx/helper.c
@@ -0,0 +1,41 @@
+/*
+ * QEMU TILE-Gx helpers
+ *
+ * Copyright (c) 2015 Chen Gang
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * http://www.gnu.org/licenses/lgpl-2.1.html
+ */
+
+#include cpu.h
+#include qemu-common.h
+#include exec/helper-proto.h
+
+void helper_exception(CPUTLGState *env, uint32_t excp)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+
+cs-exception_index = excp;
+cpu_loop_exit(cs);
+}
+
+uint64_t helper_cntlz(uint64_t arg)
+{
+return clz64(arg);
+}
+
+uint64_t helper_cnttz(uint64_t arg)
+{
+return ctz64(arg);
+}
diff --git a/target-tilegx/helper.h b/target-tilegx/helper.h
new file mode 100644
index 000..15f841f
--- /dev/null
+++ b/target-tilegx/helper.h
@@ -0,0 +1,3 @@
+DEF_HELPER_2(exception, noreturn, env, i32)
+DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
+DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
--
1.9.3
[Qemu-devel] [PATCH 04/10 v10] target-tilegx: Add opcode basic implementation from Tilera Corporation
It is copied from Linux kernel arch/tile/include/uapi/arch/
opcode_tilegx.h.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/opcode_tilegx.h | 1406 +
1 file changed, 1406 insertions(+)
create mode 100644 target-tilegx/opcode_tilegx.h
diff --git a/target-tilegx/opcode_tilegx.h b/target-tilegx/opcode_tilegx.h
new file mode 100644
index 000..d76ff2d
--- /dev/null
+++ b/target-tilegx/opcode_tilegx.h
@@ -0,0 +1,1406 @@
+/* TILE-Gx opcode information.
+ *
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ *
+ *
+ *
+ *
+ */
+
+#ifndef __ARCH_OPCODE_H__
+#define __ARCH_OPCODE_H__
+
+#ifndef __ASSEMBLER__
+
+typedef unsigned long long tilegx_bundle_bits;
+
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 62)
+
+enum
+{
+ /* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+
+ /* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
+
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+
+ /* Instructions take this many bytes. */
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
+
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+
+ /* Bundles should be aligned modulo this number of bytes. */
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+(1 TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
+
+ /* Number of registers (some are magic, such as network I/O). */
+ TILEGX_NUM_REGISTERS = 64,
+};
+
+/* Make a few tile_ variables to simplify common code between
+ architectures. */
+
+typedef tilegx_bundle_bits tile_bundle_bits;
+#define TILE_BUNDLE_SIZE_IN_BYTES TILEGX_BUNDLE_SIZE_IN_BYTES
+#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES \
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES
+#define TILE_BPT_BUNDLE TILEGX_BPT_BUNDLE
+
+/* 64-bit pattern for a { bpt ; nop } bundle. */
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
+
+static __inline unsigned int
+get_BFEnd_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x3f);
+}
+
+static __inline unsigned int
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 24)) 0xf);
+}
+
+static __inline unsigned int
+get_BFStart_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 18)) 0x3f);
+}
+
+static __inline unsigned int
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 37)) 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 54)) 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x003f) |
+ (((unsigned int)(n 43)) 0x00c0);
+}
+
+static __inline unsigned int
+get_Dest_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 0)) 0x3f);
+}
+
+static __inline unsigned int
+get_Dest_Y1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 31)) 0x3f);
+}
+
+static __inline unsigned int
+get_Imm16_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0x);
+}
+
+static __inline unsigned int
+get_Imm16_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0x);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 20)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 51)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((n 12)) 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n 43)) 0xff);
+}
+
+static
[Qemu-devel] [PATCH 00/10 v10] tilegx: Firstly add tilegx target for linux-user
At present, it can run into glibc _init_malloc(), but cause assertion, which should be fixed, next. Since it already has quite a few of code, so send patches firstly, and next, continue fixing the issue. Chen Gang (10): linux-user: tilegx: Firstly add architecture related features linux-user: Support tilegx architecture in linux-user linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx target-tilegx: Add opcode basic implementation from Tilera Corporation target-tilegx/opcode_tilegx.h: Modify it to fit qemu using target-tilegx: Add special register information from Tilera Corporation target-tilegx: Add cpu basic features for linux-user target-tilegx: Add helper features for linux-user target-tilegx: Generate tcg instructions to execute to _init_malloc in glib target-tilegx: Add TILE-Gx building files configure |2 + default-configs/tilegx-linux-user.mak |1 + include/elf.h |2 + linux-user/elfload.c | 23 + linux-user/main.c | 148 ++ linux-user/syscall.c | 50 +- linux-user/syscall_defs.h | 14 +- linux-user/tilegx/syscall.h | 35 + linux-user/tilegx/syscall_nr.h| 278 linux-user/tilegx/target_cpu.h| 35 + linux-user/tilegx/target_signal.h | 29 + linux-user/tilegx/target_structs.h| 48 + linux-user/tilegx/termbits.h | 285 target-tilegx/Makefile.objs |1 + target-tilegx/cpu.c | 143 ++ target-tilegx/cpu.h | 156 ++ target-tilegx/helper.c| 41 + target-tilegx/helper.h|3 + target-tilegx/opcode_tilegx.h | 1405 target-tilegx/spr_def_64.h| 216 +++ target-tilegx/translate.c | 2889 + 21 files changed, 5798 insertions(+), 6 deletions(-) create mode 100644 default-configs/tilegx-linux-user.mak create mode 100644 linux-user/tilegx/syscall.h create mode 100644 linux-user/tilegx/syscall_nr.h create mode 100644 linux-user/tilegx/target_cpu.h create mode 100644 linux-user/tilegx/target_signal.h create mode 100644 linux-user/tilegx/target_structs.h create mode 100644 linux-user/tilegx/termbits.h create mode 100644 target-tilegx/Makefile.objs create mode 100644 target-tilegx/cpu.c create mode 100644 target-tilegx/cpu.h create mode 100644 target-tilegx/helper.c create mode 100644 target-tilegx/helper.h create mode 100644 target-tilegx/opcode_tilegx.h create mode 100644 target-tilegx/spr_def_64.h create mode 100644 target-tilegx/translate.c -- 1.9.3
[Qemu-devel] [PATCH 01/10 v10] linux-user: tilegx: Firstly add architecture related features
They are based on Linux kernel tilegx architecture for 64 bit binary,
and also based on tilegx ABI reference document, and also reference from
other targets implementations.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/tilegx/syscall.h| 35 +
linux-user/tilegx/syscall_nr.h | 278
linux-user/tilegx/target_cpu.h | 35 +
linux-user/tilegx/target_signal.h | 29
linux-user/tilegx/target_structs.h | 48 +++
linux-user/tilegx/termbits.h | 285 +
6 files changed, 710 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/target_cpu.h
create mode 100644 linux-user/tilegx/target_signal.h
create mode 100644 linux-user/tilegx/target_structs.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 000..df55ec7
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,35 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE tilegx
+#define UNAME_MINIMUM_RELEASE 3.19
+
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+union {
+/* Saved main processor registers; 56..63 are special. */
+tilegx_reg_t regs[56];
+struct {
+tilegx_reg_t __regs[53];
+tilegx_reg_t tp;/* aliases regs[TREG_TP] */
+tilegx_reg_t sp;/* aliases regs[TREG_SP] */
+tilegx_reg_t lr;/* aliases regs[TREG_LR] */
+};
+};
+
+/* Saved special registers. */
+tilegx_reg_t pc;/* stored in EX_CONTEXT_K_0 */
+tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
+tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
+tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
+tilegx_reg_t flags; /* flags (see below) */
+tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
+tilegx_reg_t pad[2];
+};
+
+#define TARGET_MLOCKALL_MCL_CURRENT 1
+#define TARGET_MLOCKALL_MCL_FUTURE 2
+
+#endif
diff --git a/linux-user/tilegx/syscall_nr.h b/linux-user/tilegx/syscall_nr.h
new file mode 100644
index 000..8121154
--- /dev/null
+++ b/linux-user/tilegx/syscall_nr.h
@@ -0,0 +1,278 @@
+#ifndef TILEGX_SYSCALL_NR
+#define TILEGX_SYSCALL_NR
+
+/*
+ * Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
+ */
+#define TARGET_NR_io_setup 0
+#define TARGET_NR_io_destroy1
+#define TARGET_NR_io_submit 2
+#define TARGET_NR_io_cancel 3
+#define TARGET_NR_io_getevents 4
+#define TARGET_NR_setxattr 5
+#define TARGET_NR_lsetxattr 6
+#define TARGET_NR_fsetxattr 7
+#define TARGET_NR_getxattr 8
+#define TARGET_NR_lgetxattr 9
+#define TARGET_NR_fgetxattr 10
+#define TARGET_NR_listxattr 11
+#define TARGET_NR_llistxattr12
+#define TARGET_NR_flistxattr13
+#define TARGET_NR_removexattr 14
+#define TARGET_NR_lremovexattr 15
+#define TARGET_NR_fremovexattr 16
+#define TARGET_NR_getcwd17
+#define TARGET_NR_lookup_dcookie18
+#define TARGET_NR_eventfd2 19
+#define TARGET_NR_epoll_create1 20
+#define TARGET_NR_epoll_ctl 21
+#define TARGET_NR_epoll_pwait 22
+#define TARGET_NR_dup 23
+#define TARGET_NR_dup3 24
+#define TARGET_NR_fcntl 25
+#define TARGET_NR_inotify_init1 26
+#define TARGET_NR_inotify_add_watch 27
+#define TARGET_NR_inotify_rm_watch 28
+#define TARGET_NR_ioctl 29
+#define TARGET_NR_ioprio_set30
+#define TARGET_NR_ioprio_get31
+#define TARGET_NR_flock 32
+#define TARGET_NR_mknodat 33
+#define TARGET_NR_mkdirat 34
+#define TARGET_NR_unlinkat 35
+#define TARGET_NR_symlinkat 36
+#define TARGET_NR_linkat37
+#define TARGET_NR_renameat 38
+#define TARGET_NR_umount2 39
+#define TARGET_NR_mount 40
+#define TARGET_NR_pivot_root41
+#define TARGET_NR_nfsservctl42
+#define TARGET_NR_statfs43
+#define TARGET_NR_fstatfs 44
+#define TARGET_NR_truncate 45
+#define TARGET_NR_ftruncate
[Qemu-devel] [PATCH 02/10 v10] linux-user: Support tilegx architecture in linux-user
Add main working flow feature, system call processing feature, and elf64
tilegx binary loading feature, based on Linux kernel tilegx 64-bit
implementation.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
include/elf.h | 2 +
linux-user/elfload.c | 23 +++
linux-user/main.c | 148 ++
linux-user/syscall_defs.h | 14 +++--
4 files changed, 182 insertions(+), 5 deletions(-)
diff --git a/include/elf.h b/include/elf.h
index 3e75f05..154144e 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
+#define EM_TILEGX 191 /* TILE-Gx */
+
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL0
#define DT_NEEDED 1
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 0ba9706..fbf9212 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1189,6 +1189,29 @@ static inline void init_thread(struct target_pt_regs
*regs, struct image_info *i
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+/* 42 bits real used address, a half for user mode */
+#define ELF_START_MMAP (0x00200ULL)
+
+#define elf_check_arch(x) ((x) == EM_TILEGX)
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+regs-pc = infop-entry;
+regs-sp = infop-start_stack;
+
+}
+
+#define ELF_EXEC_PAGESIZE65536 /* TILE-Gx page size is 64KB */
+
+#endif /* TARGET_TILEGX */
+
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif
diff --git a/linux-user/main.c b/linux-user/main.c
index 3f32db0..38fa01c 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -3416,6 +3416,143 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
+#ifdef TARGET_TILEGX
+
+static uint64_t get_regval(CPUTLGState *env, uint8_t reg)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+return env-regs[reg];
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for reading.\n, reg);
+g_assert_not_reached();
+}
+return 0;
+}
+
+static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
+{
+if (likely(reg TILEGX_R_COUNT)) {
+env-regs[reg] = val;
+} else if (reg != TILEGX_R_ZERO) {
+fprintf(stderr, invalid register r%d for writing.\n, reg);
+g_assert_not_reached();
+}
+}
+
+/*
+ * Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
+ * memory at the address held in the first source register. If the values are
+ * not equal, then no memory operation is performed. If the values are equal,
+ * the 8-byte quantity from the second source register is written into memory
+ * at the address held in the first source register. In either case, the result
+ * of the instruc- tion is the value read from memory. The compare and write to
+ * memory are atomic and thus can be used for synchronization purposes. This
+ * instruction only operates for addresses aligned to a 8-byte boundary.
+ * Unaligned memory access causes an Unaligned Data Reference interrupt.
+ *
+ * Functional Description (64-bit)
+ * uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
+ * rf[Dest] = memVal;
+ * if (memVal == SPR[CmpValueSPR])
+ * memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
+ *
+ * Functional Description (32-bit)
+ * uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
+ * rf[Dest] = memVal;
+ * if (memVal == signExtend32 (SPR[CmpValueSPR]))
+ * memoryWriteWord (rf[SrcA], rf[SrcB]);
+ *
+ *
+ * For exch(4), will no cmp spr.
+ */
+static void do_exch(CPUTLGState *env, int8_t quad, int8_t cmp)
+{
+uint8_t rdst, rsrc, rsrcb;
+target_ulong addr, tmp;
+target_long val, sprval;
+target_siginfo_t info;
+
+start_exclusive();
+
+rdst = (env-cmpexch 16) 0xff;
+rsrc = (env-cmpexch 8) 0xff;
+rsrcb = env-cmpexch 0xff;
+
+addr = get_regval(env, rsrc);
+if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
+goto do_sigsegv;
+}
+tmp = (target_ulong)val; /* rdst may be the same to rsrcb, so buffer it */
+
+if (cmp) {
+if (quad) {
+sprval = (target_long)env-spregs[TILEGX_SPR_CMPEXCH];
+} else {
+sprval = (int32_t)(env-spregs[TILEGX_SPR_CMPEXCH] 0x);
+}
+}
+
+if (!cmp || val == sprval) {
+val = get_regval(env, rsrcb);
+if (quad ? put_user_u64(val, addr) : put_user_u32(val, addr)) {
+goto do_sigsegv;
+}
+}
+
+set_regval(env, rdst, tmp);
+
+end_exclusive();
+return;
+
+do_sigsegv:
+end_exclusive();
+
+info.si_signo = TARGET_SIGSEGV;
+info.si_errno = 0;
+info.si_code = TARGET_SEGV_MAPERR;
+info._sifields
[Qemu-devel] [PATCH 03/10 v10] linux-user/syscall.c: Conditionalize syscalls which are not defined in tilegx
Some of architectures (e.g. tilegx), several syscall macros are not
supported, so switch them.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/syscall.c | 50 +-
1 file changed, 49 insertions(+), 1 deletion(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 1622ad6..a503673 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
-#ifdef __NR_getdents
+#if defined(TARGET_NR_getdents) defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint,
count);
#endif
#if !defined(__NR_getdents) || \
@@ -5581,6 +5581,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
+#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@@ -5589,6 +5590,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
+#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@@ -5603,9 +5605,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
+#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
+#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@@ -5640,6 +5644,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
+#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@@ -5653,6 +5658,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@@ -5670,12 +5676,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@@ -5792,12 +5800,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break;
#endif
+#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@@ -5806,12 +5816,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
unlock_user(p, arg2, 0);
break;
#endif
+#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@@ -5946,6 +5958,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
+#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@@ -5964,6 +5977,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@@ -5992,12 +6006,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
+#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
+#endif
#if defined(TARGET_NR_faccessat) defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@@ -6022,6 +6038,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
+#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@@ -6035,6 +6052,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
+#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@@ -6050,12 +6068,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long
arg1,
}
break
Re: [Qemu-devel] [PATCH 06/12 v9] target-tilegx: Add cpu basic features for linux-user
After have a check again, for me, I'd like to simply remove it firstly,
since it is only for system mode.
- At present, we are only focus on user mode, and which I haven't done
quite well.
- After we finish user mode, and start system mode, then can add it.
- In this way, this feature will have no any negative effect with our
current coding/reviewing, either no any negative effect for our next
coding/reviewing.
Thanks.
On 4/11/15 05:04, Chen Gang wrote:
+static const VMStateDescription vmstate_tilegx_cpu = {
+.name = cpu,
+.unmigratable = 1,
+};
I'd prefer to see a correct VMState from the start -- it's
not very difficult. Migration/snapshotting is much easier
to enforce at the point where we let code in to the tree
than if we let in non-migratable devices and CPUs and then
have to fix them up later...
OK, thanks. I shall try.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
On 5/8/15 11:14, Peter Maydell wrote: On 7 May 2015 at 22:05, Chen Gang xili_gchen_5...@hotmail.com wrote: Since no response, I assume that it is not suitable to send patches before finish printing hello world successfully (when sending patches, we should be sure of the patches are valuable enough). Er, I said you should send patches earlier rather than later. The longer you hold on to them without sending them the bigger the patchset will get and the more rework you may need to do if there are review comments that suggest significant refactoring. OK, I shall send patches within 2 days (2015-05-10), and continue. At present, it still has bug (it will cause assert in _init_malloc, then quit). It doesn't seem quite difficult for me to fix it, but it really needs additional time resources. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
Since no response, I assume that it is not suitable to send patches before finish printing hello world successfully (when sending patches, we should be sure of the patches are valuable enough). And sorry, I delayed too much for developing tilegx qemu, next I shall try to print hello world successfully and send patches within this month. Thanks. On 5/3/15 22:30, Chen Gang wrote: After spend two days, I fix the issue below: I misunderstood v4int_l instruction, so cause this issue. At present, I met mf (memory fence), I guess, we can just skip it, but I am not quite sure, welcome any ideas, suggestions and completions for it. And I almost re-constructed the code (it doesn't change quite much), if suitable, I shall try to send patches to upstream for reviewing. Welcome any ideas, suggestions and completions for it. Thanks. On 5/2/15 12:09, Chen Gang wrote: Hello all: At present, I met an issue (I guess, it should be my code bug), I am analyzing it which may spend quite a few time resources (checking and reconstructing the code is helpful for analyzing this issue): - It is about invalid memory access for ld operation. The related tilegx code is ld r48, r12, the related x86_64 code is mov (%rbx),%rbx. - The related invalid address is 0x128020 which is near (but a little upper) tilegx rsp. - I have ways for analyzing it: we have the related libc source code, and the working flow is not quite complex. But it really needs to spend me quite a few time resources on it. At present, for me, I plan to send the reconstructed code to upstream within 2 days, and continue analyzing (so that other members can also have a check), but I am not quite sure whether it is suitable. Welcome any ideas, suggestions and completions. Thanks. On 5/2/15 10:42, Chen Gang wrote: On 4/29/15 21:32, Chen Gang wrote: On 4/29/15 05:43, Peter Maydell wrote: On 28 April 2015 at 22:32, Chen Gang xili_gchen_5...@hotmail.com wrote: The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. I suggest you look at how existing CPUs handle this kind of atomic operation. I finished cmpexch(), referenced to store_exclusive() in arm and alpha. Hope what I have done is correct (I guess, it should be). - Save information about cmpexch (add additional variable in CPUState). - Generate an exception for it. - Process the related exception in main.c with start/end_exclusive() just like what alpha or arm has done. Thanks. OK, thanks. I also suggest you stop adding implementations of *new* instructions and concentrate on getting a basic set into shape for inclusion. The more stuff you keep adding the bigger your patchset is going to get and the harder it is going to get to review. Reconstruction the code is really very useful, cmp*, shl?add*, V?int_?. That will not only simplify reading, but also speed up coding. Thank you for your valuable suggestions again. For me, current code is not quite much, and really easy enough. At present I am still going smoothly (the issues are mainly about understanding new instructions which I shall meet). I still want to reach display hello world successfully (it does not seem quite difficult to me), then reconstruct current code, and send patch to upstream. But sorry, it seems I can not finish it within this month (and I shall try to finish within next month). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
After spend two days, I fix the issue below: I misunderstood v4int_l instruction, so cause this issue. At present, I met mf (memory fence), I guess, we can just skip it, but I am not quite sure, welcome any ideas, suggestions and completions for it. And I almost re-constructed the code (it doesn't change quite much), if suitable, I shall try to send patches to upstream for reviewing. Welcome any ideas, suggestions and completions for it. Thanks. On 5/2/15 12:09, Chen Gang wrote: Hello all: At present, I met an issue (I guess, it should be my code bug), I am analyzing it which may spend quite a few time resources (checking and reconstructing the code is helpful for analyzing this issue): - It is about invalid memory access for ld operation. The related tilegx code is ld r48, r12, the related x86_64 code is mov (%rbx),%rbx. - The related invalid address is 0x128020 which is near (but a little upper) tilegx rsp. - I have ways for analyzing it: we have the related libc source code, and the working flow is not quite complex. But it really needs to spend me quite a few time resources on it. At present, for me, I plan to send the reconstructed code to upstream within 2 days, and continue analyzing (so that other members can also have a check), but I am not quite sure whether it is suitable. Welcome any ideas, suggestions and completions. Thanks. On 5/2/15 10:42, Chen Gang wrote: On 4/29/15 21:32, Chen Gang wrote: On 4/29/15 05:43, Peter Maydell wrote: On 28 April 2015 at 22:32, Chen Gang xili_gchen_5...@hotmail.com wrote: The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. I suggest you look at how existing CPUs handle this kind of atomic operation. I finished cmpexch(), referenced to store_exclusive() in arm and alpha. Hope what I have done is correct (I guess, it should be). - Save information about cmpexch (add additional variable in CPUState). - Generate an exception for it. - Process the related exception in main.c with start/end_exclusive() just like what alpha or arm has done. Thanks. OK, thanks. I also suggest you stop adding implementations of *new* instructions and concentrate on getting a basic set into shape for inclusion. The more stuff you keep adding the bigger your patchset is going to get and the harder it is going to get to review. Reconstruction the code is really very useful, cmp*, shl?add*, V?int_?. That will not only simplify reading, but also speed up coding. Thank you for your valuable suggestions again. For me, current code is not quite much, and really easy enough. At present I am still going smoothly (the issues are mainly about understanding new instructions which I shall meet). I still want to reach display hello world successfully (it does not seem quite difficult to me), then reconstruct current code, and send patch to upstream. But sorry, it seems I can not finish it within this month (and I shall try to finish within next month). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
Hello all: At present, I met an issue (I guess, it should be my code bug), I am analyzing it which may spend quite a few time resources (checking and reconstructing the code is helpful for analyzing this issue): - It is about invalid memory access for ld operation. The related tilegx code is ld r48, r12, the related x86_64 code is mov (%rbx),%rbx. - The related invalid address is 0x128020 which is near (but a little upper) tilegx rsp. - I have ways for analyzing it: we have the related libc source code, and the working flow is not quite complex. But it really needs to spend me quite a few time resources on it. At present, for me, I plan to send the reconstructed code to upstream within 2 days, and continue analyzing (so that other members can also have a check), but I am not quite sure whether it is suitable. Welcome any ideas, suggestions and completions. Thanks. On 5/2/15 10:42, Chen Gang wrote: On 4/29/15 21:32, Chen Gang wrote: On 4/29/15 05:43, Peter Maydell wrote: On 28 April 2015 at 22:32, Chen Gang xili_gchen_5...@hotmail.com wrote: The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. I suggest you look at how existing CPUs handle this kind of atomic operation. I finished cmpexch(), referenced to store_exclusive() in arm and alpha. Hope what I have done is correct (I guess, it should be). - Save information about cmpexch (add additional variable in CPUState). - Generate an exception for it. - Process the related exception in main.c with start/end_exclusive() just like what alpha or arm has done. Thanks. OK, thanks. I also suggest you stop adding implementations of *new* instructions and concentrate on getting a basic set into shape for inclusion. The more stuff you keep adding the bigger your patchset is going to get and the harder it is going to get to review. Reconstruction the code is really very useful, cmp*, shl?add*, V?int_?. That will not only simplify reading, but also speed up coding. Thank you for your valuable suggestions again. For me, current code is not quite much, and really easy enough. At present I am still going smoothly (the issues are mainly about understanding new instructions which I shall meet). I still want to reach display hello world successfully (it does not seem quite difficult to me), then reconstruct current code, and send patch to upstream. But sorry, it seems I can not finish it within this month (and I shall try to finish within next month). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
On 4/29/15 21:32, Chen Gang wrote: On 4/29/15 05:43, Peter Maydell wrote: On 28 April 2015 at 22:32, Chen Gang xili_gchen_5...@hotmail.com wrote: The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. I suggest you look at how existing CPUs handle this kind of atomic operation. I finished cmpexch(), referenced to store_exclusive() in arm and alpha. Hope what I have done is correct (I guess, it should be). - Save information about cmpexch (add additional variable in CPUState). - Generate an exception for it. - Process the related exception in main.c with start/end_exclusive() just like what alpha or arm has done. Thanks. OK, thanks. I also suggest you stop adding implementations of *new* instructions and concentrate on getting a basic set into shape for inclusion. The more stuff you keep adding the bigger your patchset is going to get and the harder it is going to get to review. Reconstruction the code is really very useful, cmp*, shl?add*, V?int_?. That will not only simplify reading, but also speed up coding. Thank you for your valuable suggestions again. For me, current code is not quite much, and really easy enough. At present I am still going smoothly (the issues are mainly about understanding new instructions which I shall meet). I still want to reach display hello world successfully (it does not seem quite difficult to me), then reconstruct current code, and send patch to upstream. But sorry, it seems I can not finish it within this month (and I shall try to finish within next month). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
On 4/29/15 05:43, Peter Maydell wrote: On 28 April 2015 at 22:32, Chen Gang xili_gchen_5...@hotmail.com wrote: The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. I suggest you look at how existing CPUs handle this kind of atomic operation. OK, thanks. I also suggest you stop adding implementations of *new* instructions and concentrate on getting a basic set into shape for inclusion. The more stuff you keep adding the bigger your patchset is going to get and the harder it is going to get to review. For me, current code is not quite much, and really easy enough. At present I am still going smoothly (the issues are mainly about understanding new instructions which I shall meet). I still want to reach display hello world successfully (it does not seem quite difficult to me), then reconstruct current code, and send patch to upstream. But sorry, it seems I can not finish it within this month (and I shall try to finish within next month). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
On 4/28/15 06:04, Richard Henderson wrote: On 04/27/2015 02:12 PM, Chen Gang wrote: Now, I am blocked at SPRs: mtspr SPR_CMPEXCH_VALUE %r12, and trying to solve it. SPR_CMPEXCH_VALUE should be present in your cpu structure, should be a TCGv like all of your other registers, and this expands to a simple move. You will probably need to dispatch on the SPR number. Some of these will be normal moves to special register slots. Some of these may require a function call in order to handle the side effects. OK, thank you very much. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] About SPRs information
On 4/29/15 04:19, Chen Gang wrote: On 4/28/15 06:04, Richard Henderson wrote: On 04/27/2015 02:12 PM, Chen Gang wrote: Now, I am blocked at SPRs: mtspr SPR_CMPEXCH_VALUE %r12, and trying to solve it. SPR_CMPEXCH_VALUE should be present in your cpu structure, should be a TCGv like all of your other registers, and this expands to a simple move. You will probably need to dispatch on the SPR number. Some of these will be normal moves to special register slots. Some of these may require a function call in order to handle the side effects. After check the next instruction cmpexch which uses SPR_CMPEXCH_VALUE: - Do we need a lock for cmpexch spr? (I guess not) - Do we need the same lock within cmpexch instruction for reading cmpexch spr? (I guess not) - When each spr occurs, do we need end the current block just like branch/call instruction occurs? (I guess we need) The related information for cmpexch instruction: Description Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in memory at the address held in the first source register. If the values are not equal, then no memory operation is performed. If the values are equal, the 8-byte quantity from the second source register is written into memory at the address held in the first source register. In either case, the result of the instruc- tion is the value read from memory. The compare and write to memory are atomic and thus can be used for synchronization purposes. This instruction only operates for addresses aligned to a 8-byte boundary. Unaligned memory access causes an Unaligned Data Reference interrupt. Functional Description uint64_t memVal = memoryReadDoubleWord (rf[SrcA]); rf[Dest] = memVal; if (memVal == SPR[CmpValueSPR]) memoryWriteDoubleWord (rf[SrcA], rf[SrcB]); OK, thank you very much. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [Consult] About SPRs information
On 2/17/15 08:29, Chris Metcalf wrote: Yes, I think there is a bit less documentation on tilegx SPRs available. If this becomes a blocker for you, let me know and I will see if there is anything we can do about it. Probably best to wait until you have made more progress on qemu before trying to make a case for it internally, though. Hello all: Now, I am blocked at SPRs: mtspr SPR_CMPEXCH_VALUE %r12, and trying to solve it. And welcome any ideas, suggestions and completions for it. Thanks. On 2/15/2015 10:40 PM, Chen Gang S wrote: Excuse me, I want to consult the related information about SPR. For SPRs (Special Purpose Register) under tilegx, I can not get related documents (I only got the tilepro related document for SPR). After read through the source code of Linux kernel for tile, I guess: - SPRs are in arch/tile/include/uapi/arch/spr_def_64.h. - SPRs are all 64-bit registers (I referenced the 'interrupt_mask' and CHIP_HAS_SPLIT_INTR_MASK to know about it). If what I guess is incorrect, please let me know. And welcome to provide tilegx SPR related documents, too. Thanks. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [Consult] tilegx: Is it a qemu's system bug?
On 4/26/15 03:30, Richard Henderson wrote: On 04/25/2015 05:12 AM, Chen Gang wrote: Hello All: I want to consult an issue I met below for the latest master branch, is it a qemu's bug? (it is about ctz/cnttz instruction for tilegx) OP: ld_i32 tmp0,env,$0xfffc movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,ne,$L0 movi_i64 tmp3,$0x0/* Initialize tmp3 */ set_label $L1 shr_i64 tmp2,r2,tmp3 You can't keep temporaries live across basic blocks. That is, across set_label, br, or brcond. In that case you'd have to use tcg_new_local_temp() instead. That said, you shouldn't open-code ctz but instead use a helper function and use ctz64(). Thank you very much for your valuable reply! It will save my much time resources for analyzing. And I shall try to let tilegx print hello world within this month (although it seems really difficult to me, at present). Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
[Qemu-devel] [Consult] tilegx: Is it a qemu's system bug?
Hello All: I want to consult an issue I met below for the latest master branch, is it a qemu's bug? (it is about ctz/cnttz instruction for tilegx) OP: ld_i32 tmp0,env,$0xfffc movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,ne,$L0 movi_i64 tmp3,$0x0/* Initialize tmp3 */ set_label $L1 shr_i64 tmp2,r2,tmp3 movi_i64 tmp4,$0x1 and_i64 tmp2,tmp2,tmp4 movi_i64 tmp4,$0x1 brcond_i64 tmp2,tmp4,eq,$L2 movi_i64 tmp4,$0x1 add_i64 tmp3,tmp3,tmp4 movi_i64 tmp4,$0x40 brcond_i64 tmp3,tmp4,ne,$L1 set_label $L2 mov_i64 tmp4,tmp3 set_label $L0 exit_tb $0x72690013 OP after optimization and liveness analysis: ld_i32 tmp0,env,$0xfffc movi_i32 tmp1,$0x0 brcond_i32 tmp0,tmp1,ne,$L0 set_label $L1 /* Skip tmp3 initialization */ shr_i64 tmp2,r2,tmp3 /* So I guess, qemu can not find tmp3 in shr_i64, so report assertion */ movi_i64 tmp4,$0x1 and_i64 tmp2,tmp2,tmp4 movi_i64 tmp4,$0x1 brcond_i64 tmp2,tmp4,eq,$L2 movi_i64 tmp4,$0x1 add_i64 tmp3,tmp3,tmp4 movi_i64 tmp4,$0x40 brcond_i64 tmp3,tmp4,ne,$L1 set_label $L2 set_label $L0 exit_tb $0x72690013 /* begin: I add related printing log in tcg_reg_alloc_op() before assertion */ opc == 12 /* ld_i32 */ ===ts-val_type: 1. opc == 5 /* movi_i32 */ opc == 34 /* brcond_i32 */ ===ts-val_type: 1. ===ts-val_type: 3. opc == 1 /* set_label */ opc == 84 /* shr_i64 */ opc = INDEX_op_shr_i64 ===ts-val_type: 2. ===ts-val_type: 0. /* end: I add related printing log in tcg_reg_alloc_op() before assertion */ qemu-tilegx: /upstream/qemu/tcg/tcg.c:1982: tcg_reg_alloc_op: Assertion `ts-val_type == 1' failed. Welcome any ideas, suggestions and completions. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 12/12 v9] target-tilegx: Generate tcg instructions to execute to 1st system call
On 4/22/15 05:31, Peter Maydell wrote: On 21 April 2015 at 22:23, Chen Gang xili_gchen_5...@hotmail.com wrote: On 4/22/15 05:15, Peter Maydell wrote: will work in place of both of the above (and does this CPU really only have two kinds of compare-immediate? Some of the case labels suggest not, so it would be better to just implement all the compare-immediates together in one patch.) You can probably use a function to do the sub-opcode-to-TCGCond lookup too. Having dozens of two line functions that all look incredibly similar is a really strong sign that you haven't taken advantage of the commonality between them. CPU instruction sets are usually pretty regular if they're well designed and the resulting translate.c should also look pretty regular. I guess what you said is correct, but at present, I did not think of all gen_cmp* (but it should really be done at last). So for me, at present, we can leave it as current implementation (Add FIXME comment). And at last (when almost finish all opcode decoding), I shall rewrite it again. If you rewrite it all at the end then we get twice the code review work to do. Please just do it right the first time. OK, I shall try. Thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 12/12 v9] target-tilegx: Generate tcg instructions to execute to 1st system call
On 4/11/15 05:28, Chen Gang wrote:
On 4/10/15 06:19, Peter Maydell wrote:
On 27 March 2015 at 11:07, Chen Gang xili_gchen_5...@hotmail.com wrote:
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+(uint64_t)imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst, rsrc,
imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ, dest_gr(dc, rdst), load_gr(dc, rsrc),
+(uint64_t)imm8);
+}
+
+static void gen_cmpne(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpne r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+tcg_gen_setcond_i64(TCG_COND_NE, dest_gr(dc, rdst), load_gr(dc, rsrc),
+load_gr(dc, rsrcb));
+}
+
+static void gen_cmoveqz(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmoveqz r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+tcg_gen_movcond_i64(TCG_COND_EQ, dest_gr(dc, rdst), load_gr(dc, rsrc),
+load_zero(dc), load_gr(dc, rsrcb), load_gr(dc,
rdst));
+}
+
+static void gen_cmovnez(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, uint8_t rsrcb)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmovnez r%d, r%d, r%d\n,
+ rdst, rsrc, rsrcb);
+tcg_gen_movcond_i64(TCG_COND_NE, dest_gr(dc, rdst), load_gr(dc, rsrc),
+load_zero(dc), load_gr(dc, rsrcb), load_gr(dc,
rdst));
+}
This is hugely repetitive. Write a common function that takes a
TCG_COND_* as a parameter.
OK, thanks.
Oh, after check again, for me, the original implementation is OK:
- We need print disassembly code for tracing, and all related functions
are meaningful and match the whole function naming way in this file.
- All related functions are too simple to simplified (only 2 lines each).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 12/12 v9] target-tilegx: Generate tcg instructions to execute to 1st system call
On 4/22/15 05:15, Peter Maydell wrote:
On 21 April 2015 at 22:01, Chen Gang xili_gchen_5...@hotmail.com wrote:
On 4/11/15 05:28, Chen Gang wrote:
On 4/10/15 06:19, Peter Maydell wrote:
On 27 March 2015 at 11:07, Chen Gang xili_gchen_5...@hotmail.com wrote:
+}
+
+static void gen_cmpltui(struct DisasContext *dc,
+uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpltui r%d, r%d, %d\n,
+ rdst, rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_LTU, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+(uint64_t)imm8);
+}
+
+static void gen_cmpeqi(struct DisasContext *dc,
+ uint8_t rdst, uint8_t rsrc, int8_t imm8)
+{
+qemu_log_mask(CPU_LOG_TB_IN_ASM, cmpeqi r%d, r%d, %d\n, rdst,
rsrc, imm8);
+tcg_gen_setcondi_i64(TCG_COND_EQ, dest_gr(dc, rdst), load_gr(dc,
rsrc),
+(uint64_t)imm8);
+}
Oh, after check again, for me, the original implementation is OK:
- We need print disassembly code for tracing, and all related functions
are meaningful and match the whole function naming way in this file.
- All related functions are too simple to simplified (only 2 lines each).
But you don't need all these functions! Something like:
static void gen_cmpi(struct DisasContext *dc, TCGCond cond,
uint8_t rdst, uint8_t rsrc, int8_t imm8)
{
qemu_log_mask(CPU_LOG_TB_IN_ASM, cmp%si r%d, r%d, %d\n,
condname[cond], dest_gr(dc, rdst), load_gr(dc, rsrc),
imm8);
tcg_gen_setcondi_i64(cond, dest_gr(dc, rdst), load_gr(dc, rsrc),
(uint64_t)imm8);
}
will work in place of both of the above (and does this CPU
really only have two kinds of compare-immediate? Some of the
case labels suggest not, so it would be better to just implement
all the compare-immediates together in one patch.)
You can probably use a function to do the sub-opcode-to-TCGCond
lookup too.
Having dozens of two line functions that all look incredibly
similar is a really strong sign that you haven't taken
advantage of the commonality between them. CPU instruction
sets are usually pretty regular if they're well designed and
the resulting translate.c should also look pretty regular.
I guess what you said is correct, but at present, I did not think of all
gen_cmp* (but it should really be done at last).
So for me, at present, we can leave it as current implementation (Add
FIXME comment). And at last (when almost finish all opcode decoding), I
shall rewrite it again.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 02/12 v9] linux-user: tilegx: Add target features support within qemu
On 4/11/15 05:51, Peter Maydell wrote:
On 10 April 2015 at 21:41, Chen Gang xili_gchen_5...@hotmail.com wrote:
On 4/10/15 05:31, Peter Maydell wrote:
On 27 March 2015 at 10:49, Chen Gang xili_gchen_5...@hotmail.com wrote:
+typedef struct target_sigaltstack {
+abi_ulong ss_sp;
+abi_ulong ss_size;
+abi_long ss_flags;
+} target_stack_t;
Where does this come from? It doesn't match the kernel's
generic-headers struct layout.
Oh, sorry, originally, I guess, I only copied it from microblaze, did
not check kernel.
These structures are all user-guest-facing ABI, so they must
match the kernel's structures for your target architecture.
I shall use generic-headers which tilegx will use (the result will like
alpha has done):
typedef struct target_sigaltstack {
abi_ulong ss_sp;
int32_t ss_flags;
int32_t dummy;
abi_ulong ss_size;
} target_stack_t;
This doesn't match the kernel either.
http://lxr.free-electrons.com/source/include/uapi/asm-generic/signal.h#L111
You have a pointer, an int and a size_t, so you want
abi_ulong ss_sp;
abi_int ss_flags;
abi_ulong ss_size;
like aarch64.
For me, for tilegx which is always 64-bit, add 'dummy' is more clearer
(but need to use abi_int instead of original int32_t).
And does it pragma packed ()? As far as I know, it doesn't.
[...]
+
+struct target_ipc_perm {
+abi_int __key; /* Key. */
+abi_uint uid; /* Owner's user ID. */
+abi_uint gid; /* Owner's group ID. */
+abi_uint cuid; /* Creator's user ID. */
+abi_uint cgid; /* Creator's group ID. */
+abi_uint mode;/* Read/write permission. */
+abi_ushort __seq; /* Sequence number. */
+abi_ushort __pad2;
+abi_ulong __unused1;
+abi_ulong __unused2;
+};
Again, doesn't seem to match kernel?
For me, it matches kernel. mode is abi_uint (__kernel_mode_t is 32-bit).
I'm looking at
http://lxr.free-electrons.com/source/include/uapi/linux/ipc.h#L9
which doesn't have that padding and unused fields at the end.
However the ipc structs are pretty confusing so maybe that's
the wrong one -- which one are you looking at?
I check the linux-next tree next-20150401 in include/uapi/linux/ipc.h,
the __kernel_mode_t is unsigned int for tile (and also most of 64-bit
targets in qemu, mode is 32-bit), please check again.
it really has no __pad2 and __unused?, but after check all the other
targets within qemu, they all have __pad2 and __unused?. May qemu
itself need them? I am not quite sure, but for me, appending them is OK.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 01/12 v9] linux-user: tilegx: Firstly add architecture related features
Firstly, thank you very much for your patient work for all related
patches.
And I shall try to send patch v10 within this month, and let linux-user
run Hello world completely (finish emulate a demo executable binary
successfully).
The related reply is below:
On 4/10/15 05:21, Peter Maydell wrote:
On 27 March 2015 at 10:48, Chen Gang xili_gchen_5...@hotmail.com wrote:
They are based on Linux kernel tilegx architecture for 64 bit binary,
also based on tilegx ABI reference document.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
linux-user/tilegx/syscall.h| 80
linux-user/tilegx/syscall_nr.h | 278
linux-user/tilegx/termbits.h | 285
+
3 files changed, 643 insertions(+)
create mode 100644 linux-user/tilegx/syscall.h
create mode 100644 linux-user/tilegx/syscall_nr.h
create mode 100644 linux-user/tilegx/termbits.h
diff --git a/linux-user/tilegx/syscall.h b/linux-user/tilegx/syscall.h
new file mode 100644
index 000..561e158
--- /dev/null
+++ b/linux-user/tilegx/syscall.h
@@ -0,0 +1,80 @@
+#ifndef TILEGX_SYSCALLS_H
+#define TILEGX_SYSCALLS_H
+
+#define UNAME_MACHINE tilegx
+#define UNAME_MINIMUM_RELEASE 3.19
+
+/* We use tilegx to keep things similar to the kernel sources. */
This is true but a slightly odd place to say so.
OK, thanks, I shall remove it.
+typedef uint64_t tilegx_reg_t;
+
+struct target_pt_regs {
+
+/* Can be as parameters */
+tilegx_reg_t r0; /* Also for return value, both function and system
call */
+tilegx_reg_t r1;
+tilegx_reg_t r2;
+tilegx_reg_t r3;
+tilegx_reg_t r4;
+tilegx_reg_t r5;
+tilegx_reg_t r6;
+tilegx_reg_t r7;
+tilegx_reg_t r8;
+tilegx_reg_t r9;
+
+/* Normal using, caller saved */
+tilegx_reg_t r10; /* Also for system call */
+tilegx_reg_t r11;
+tilegx_reg_t r12;
+tilegx_reg_t r13;
+tilegx_reg_t r14;
+tilegx_reg_t r15;
+tilegx_reg_t r16;
+tilegx_reg_t r17;
+tilegx_reg_t r18;
+tilegx_reg_t r19;
+tilegx_reg_t r20;
+tilegx_reg_t r21;
+tilegx_reg_t r22;
+tilegx_reg_t r23;
+tilegx_reg_t r24;
+tilegx_reg_t r25;
+tilegx_reg_t r26;
+tilegx_reg_t r27;
+tilegx_reg_t r28;
+tilegx_reg_t r29;
+
+/* Normal using, callee saved */
+tilegx_reg_t r30;
+tilegx_reg_t r31;
+tilegx_reg_t r32;
+tilegx_reg_t r33;
+tilegx_reg_t r34;
+tilegx_reg_t r35;
+tilegx_reg_t r36;
+tilegx_reg_t r37;
+tilegx_reg_t r38;
+tilegx_reg_t r39;
+tilegx_reg_t r40;
+tilegx_reg_t r41;
+tilegx_reg_t r42;
+tilegx_reg_t r43;
+tilegx_reg_t r44;
+tilegx_reg_t r45;
+tilegx_reg_t r46;
+tilegx_reg_t r47;
+tilegx_reg_t r48;
+tilegx_reg_t r49;
+tilegx_reg_t r50;
+tilegx_reg_t r51;
+
+/* Control using */
+tilegx_reg_t r52;/* optional frame pointer */
Why aren't we using an array, the way the kernel does?
OK, thanks. I shall do it like pt_reg have done.
+tilegx_reg_t tp; /* thread-local data */
+tilegx_reg_t sp; /* stack pointer */
+tilegx_reg_t lr; /* lr pointer */
This is missing a bunch of stuff from the kernel uapi
pt_regs type, which is bad because this struct is part
of the user-facing ABI (it gets used in signal handling).
OK, thanks. And I guess, sigcontext is a little betther than pt_regs.
diff --git a/linux-user/tilegx/termbits.h b/linux-user/tilegx/termbits.h
new file mode 100644
index 000..c11ce3e
--- /dev/null
+++ b/linux-user/tilegx/termbits.h
+#define TARGET_TIOCNOTTY0x5422
+#define TARGET_TIOCSETD 0x5423
+#define TARGET_TIOCGETD 0x5424
+#define TARGET_TCSBRKP 0x5425
+#define TARGET_TIOCSBRK 0x5427
+#define TARGET_TIOCCBRK 0x5428
+#define TARGET_TIOCGSID 0x5429
+#define TARGET_TCGETS2 _IOR('T', 0x2A, struct termios2)
You probably mean TARGET_IOR/TARGET_IOW here and below.
OK, thanks. I shall use TARGET_IOR/TARGET_IOW instead of _IOR/_IOW.
+#define TARGET_TCSETS2 _IOW('T', 0x2B, struct termios2)
+#define TARGET_TCSETSW2 _IOW('T', 0x2C, struct termios2)
+#define TARGET_TCSETSF2 _IOW('T', 0x2D, struct termios2)
+#define TARGET_TIOCGRS485 0x542E
+#define TARGET_TIOCSRS485 0x542F
+#define TARGET_TIOCGPTN _IOR('T', 0x30, unsigned int)
+#define TARGET_TIOCSPTLCK _IOW('T', 0x31, int)
+#define TARGET_TIOCGDEV _IOR('T', 0x32, unsigned int)
+#define TARGET_TCGETX 0x5432
+#define TARGET_TCSETX 0x5433
+#define TARGET_TCSETXF 0x5434
+#define TARGET_TCSETXW 0x5435
+#define TARGET_TIOCSIG
Re: [Qemu-devel] [PATCH 02/12 v9] linux-user: tilegx: Add target features support within qemu
On 4/10/15 05:31, Peter Maydell wrote:
On 27 March 2015 at 10:49, Chen Gang xili_gchen_5...@hotmail.com wrote:
[...]
+static inline void cpu_clone_regs(CPUTLGState *env, target_ulong newsp)
+{
+if (newsp) {
+env-regs[TILEGX_R_SP] = newsp;
+}
+env-regs[TILEGX_R_RE] = 0;
This is slightly confusing, because the kernel code we're matching here
doesn't call this register RE, it just uses 0:
childregs-regs[0] = 0; /* return value is zero */
TILEGX_R_RE is just 0, I define a macro instead the hardcode number in
cpu.h with the comment for it.
[...]
+
+/* this struct defines a stack used during syscall handling */
+
+typedef struct target_sigaltstack {
+abi_ulong ss_sp;
+abi_ulong ss_size;
+abi_long ss_flags;
+} target_stack_t;
Where does this come from? It doesn't match the kernel's
generic-headers struct layout.
Oh, sorry, originally, I guess, I only copied it from microblaze, did
not check kernel.
I shall use generic-headers which tilegx will use (the result will like
alpha has done):
typedef struct target_sigaltstack {
abi_ulong ss_sp;
int32_t ss_flags;
int32_t dummy;
abi_ulong ss_size;
} target_stack_t;
[...]
+
+struct target_ipc_perm {
+abi_int __key; /* Key. */
+abi_uint uid; /* Owner's user ID. */
+abi_uint gid; /* Owner's group ID. */
+abi_uint cuid; /* Creator's user ID. */
+abi_uint cgid; /* Creator's group ID. */
+abi_uint mode;/* Read/write permission. */
+abi_ushort __seq; /* Sequence number. */
+abi_ushort __pad2;
+abi_ulong __unused1;
+abi_ulong __unused2;
+};
Again, doesn't seem to match kernel?
For me, it matches kernel. mode is abi_uint (__kernel_mode_t is 32-bit).
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 03/12 v9] linux-user: Support tilegx architecture in syscall
On 4/10/15 05:38, Peter Maydell wrote:
On 27 March 2015 at 10:50, Chen Gang xili_gchen_5...@hotmail.com wrote:
[...]
+#elif defined(TARGET_TILEGX)
+
+/* Copy from Linux kernel uapi/asm-generic/stat.h */
+struct target_stat {
+abi_ulong st_dev; /* Device. */
+abi_ulong st_ino; /* File serial number. */
+unsigned int st_mode; /* File mode. */
+unsigned int st_nlink; /* Link count. */
+unsigned int st_uid;/* User ID of the file's owner. */
+unsigned int st_gid;/* Group ID of the file's group. */
+abi_ulong st_rdev; /* Device number, if device. */
+abi_ulong __pad1;
+abi_long st_size; /* Size of file, in bytes. */
+int st_blksize; /* Optimal block size for I/O. */
+int __pad2;
+abi_long st_blocks; /* Number 512-byte blocks
allocated. */
+abi_long target_st_atime; /* Time of last access. */
+abi_ulong target_st_atime_nsec;
+abi_long target_st_mtime; /* Time of last modification. */
+abi_ulong target_st_mtime_nsec;
+abi_long target_st_ctime; /* Time of last status change. */
+abi_ulong target_st_ctime_nsec;
+unsigned int __unused4;
+unsigned int __unused5;
+};
We already have the generic stat struct for TARGET_OPENRISC,
so you should just add TILEGX to the #if for that. (Pretty
sure you want the stat64 struct too, or at least that it
won't hurt.)
OK, thanks, it sounds a good idea to me.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 04/12 v9] linux-user: Support tilegx architecture in linux-user
On 4/10/15 05:44, Peter Maydell wrote:
On 27 March 2015 at 10:52, Chen Gang xili_gchen_5...@hotmail.com wrote:
[...]
+
+#define ELF_CLASS ELFCLASS64
+#define ELF_DATAELFDATA2LSB
+#define ELF_ARCHEM_TILEGX
+
+static inline void init_thread(struct target_pt_regs *regs,
+ struct image_info *infop)
+{
+regs-lr = infop-entry;
This is wrong (see later).
+regs-sp = infop-start_stack;
+
+}
+
[...]
+#ifdef TARGET_TILEGX
+void cpu_loop(CPUTLGState *env)
+{
+CPUState *cs = CPU(tilegx_env_get_cpu(env));
+int trapnr;
+
+while (1) {
+cpu_exec_start(cs);
+trapnr = cpu_tilegx_exec(env);
+cpu_exec_end(cs);
+switch (trapnr) {
+case TILEGX_EXCP_SYSCALL:
+env-regs[TILEGX_R_RE] = do_syscall(env, env-regs[TILEGX_R_NR],
+env-regs[0], env-regs[1],
+env-regs[2], env-regs[3],
+env-regs[4], env-regs[5],
+env-regs[6], env-regs[7]);
+break;
+default:
+exit(-1);
Calling exit() with negative values is never right (exit codes
are always positive), and in any case this is the wrong way to
handle a can't happen case in code. If we can never get here
then you want
g_assert_not_reached();
OK, thanks.
[...]
+#elif defined(TARGET_TILEGX)
+{
+env-regs[0] = regs-r0;
+env-regs[1] = regs-r1;
+env-regs[2] = regs-r2;
+env-regs[3] = regs-r3;
+env-regs[4] = regs-r4;
+env-regs[5] = regs-r5;
+env-regs[6] = regs-r6;
+env-regs[7] = regs-r7;
+env-regs[8] = regs-r8;
+env-regs[9] = regs-r9;
+env-regs[10] = regs-r10;
+env-regs[11] = regs-r11;
+env-regs[12] = regs-r12;
+env-regs[13] = regs-r13;
+env-regs[14] = regs-r14;
+env-regs[15] = regs-r15;
+env-regs[16] = regs-r16;
+env-regs[17] = regs-r17;
+env-regs[18] = regs-r18;
+env-regs[19] = regs-r19;
+env-regs[20] = regs-r20;
+env-regs[21] = regs-r21;
+env-regs[22] = regs-r22;
+env-regs[23] = regs-r23;
+env-regs[24] = regs-r24;
+env-regs[25] = regs-r25;
+env-regs[26] = regs-r26;
+env-regs[27] = regs-r27;
+env-regs[28] = regs-r28;
+env-regs[29] = regs-r29;
+env-regs[30] = regs-r30;
+env-regs[31] = regs-r31;
+env-regs[32] = regs-r32;
+env-regs[33] = regs-r33;
+env-regs[34] = regs-r34;
+env-regs[35] = regs-r35;
+env-regs[36] = regs-r36;
+env-regs[37] = regs-r37;
+env-regs[38] = regs-r38;
+env-regs[39] = regs-r39;
+env-regs[40] = regs-r40;
+env-regs[41] = regs-r41;
+env-regs[42] = regs-r42;
+env-regs[43] = regs-r43;
+env-regs[44] = regs-r44;
+env-regs[45] = regs-r45;
+env-regs[46] = regs-r46;
+env-regs[47] = regs-r47;
+env-regs[48] = regs-r48;
+env-regs[49] = regs-r49;
+env-regs[50] = regs-r50;
+env-regs[51] = regs-r51;
+env-regs[52] = regs-r52; /* TILEGX_R_BP */
This is why you should have declared target_pt_regs
with an array, because then you can use a loop to
do this initialization.
OK, thanks.
+env-regs[53] = regs-tp; /* TILEGX_R_TP */
+env-regs[54] = regs-sp; /* TILEGX_R_SP */
+env-regs[55] = regs-lr; /* TILEGX_R_LR */
+env-pc = regs-lr;
Er, what? You should set the env-pc from the entry
in target_pt_regs that corresponds to the PC, not the LR.
(Which in turn means you need to set that field, not LR,
in init_thread().)
OK, thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 05/12 v9] linux-user/syscall.c: conditionalize syscalls which are not defined in tilegx
On 4/10/15 05:46, Peter Maydell wrote: On 27 March 2015 at 10:53, Chen Gang xili_gchen_5...@hotmail.com wrote: For tilegx, several syscall macros are not supported, so switch them to avoid building break. Signed-off-by: Chen Gang gang.chen.5...@gmail.com +#ifdef TARGET_NR_getpgrp case TARGET_NR_getpgrp: ret = get_errno(getpgrp()); break; case TARGET_NR_setsid: ret = get_errno(setsid()); break; +#endif This looks wrong -- your ifdef for NR_getpgrp is covering the setsid syscall too. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 06/12 v9] target-tilegx: Add cpu basic features for linux-user
On 4/10/15 05:55, Peter Maydell wrote:
On 27 March 2015 at 10:54, Chen Gang xili_gchen_5...@hotmail.com wrote:
It implements minimized cpu features for linux-user.
Signed-off-by: Chen Gang gang.chen.5...@gmail.com
---
target-tilegx/cpu-qom.h | 73
target-tilegx/cpu.c | 149
target-tilegx/cpu.h | 94 ++
You don't really need a separate cpu-qom.h and cpu.h -- that's
just the way we've ended up with for the older targets which
got converted to QOM for legacy reasons. See target-moxie/
for an example which combines the two headers.
OK, thanks.
+static const VMStateDescription vmstate_tilegx_cpu = {
+.name = cpu,
+.unmigratable = 1,
+};
I'd prefer to see a correct VMState from the start -- it's
not very difficult. Migration/snapshotting is much easier
to enforce at the point where we let code in to the tree
than if we let in non-migratable devices and CPUs and then
have to fix them up later...
OK, thanks. I shall try.
[...]
+
+#include exec/cpu-defs.h
+#include fpu/softfloat.h
What's the softfloat include for?
OK, thanks. I shall remove it.
[...]
+
+/* TILE-Gx memory attributes */
+#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
+#define MMAP_SHIFT TARGET_PAGE_BITS
+#define TARGET_PHYS_ADDR_SPACE_BITS 42 /* TILE-Gx is 42 bit physical
address */
+#define TARGET_VIRT_ADDR_SPACE_BITS 64 /* TILE-Gx has 64 bit virtual
address */
nitpick: has [...] addresses is the correct grammar in both these comments.
OK, thanks.
+#define MMU_USER_IDX0 /* independent from both qemu and architecture */
Not sure what you mean with this comment?
OK, thanks. I shall remove the comment.
Thanks.
--
Chen Gang
Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 08/12 v9] target-tilegx: Add opcode basic implementation for tilegx
On 4/10/15 06:03, Peter Maydell wrote: On 27 March 2015 at 10:56, Chen Gang xili_gchen_5...@hotmail.com wrote: It is from Tilera Corporation, and copied from Linux kernel arch/tile/ include/uapi/arch/opcode_tilegx.h. Signed-off-by: Chen Gang gang.chen.5...@gmail.com It's good to have this import as a single this is the upstream kernel header with no changes at all patch, but you then need a following patch that fixes it up so it will work with QEMU. Specifically, all the uses of __inline need to be changed to inline. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
Re: [Qemu-devel] [PATCH 09/12 v9] target-tilegx: Finish processing bundle and preparing decoding pipes
On 4/10/15 06:08, Peter Maydell wrote: On 27 March 2015 at 10:57, Chen Gang xili_gchen_5...@hotmail.com wrote: Finish processing tilegx bundle, and reach to related pipes. +qemu_log_mask(LOG_UNIMP, + UNIMP y0, opcode %d, bundle [ FMT64X ]\n, + opcode, (uint64_t)bundle); I feel like we should change the typedef of tilegx_bundle_bits to uint64_t, then you could avoid all these casts. OK, thanks. -- Chen Gang Open, share, and attitude like air, water, and life which God blessed
