[Qemu-devel] Email address change for Eric Johnson

[Johnson, Eric]

My email address is changing from:
er...@mips.com
to
eric.john...@imgtec.com

I've already subscribed the new email address to the list.  Emails to the 
previous address will forward to my new address for an unspecified amount of 
time.

The MIPS Technologies website (http://www.mips.com) announces the acquisition 
by Imagination Technologies.

Eric Johnson

Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO and SHILOV

[Johnson, Eric]

Sorry mail wrap issue.

> -Original Message-
> From: Jovanovic, Petar
> Sent: Wednesday, December 05, 2012 3:31 PM
> To: Johnson, Eric; qemu-devel@nongnu.org
> Cc: blauwir...@gmail.com; rth7...@gmail.com; afaer...@suse.de;
> aurel...@aurel32.net
> Subject: RE: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> SHILO and SHILOV
> 
> hey Eric,
> 
> the patch does not have to be rebased since no changes have been made to
> these files since I created the patch.
> 
> You can try it on clean master with:
> 
> wget -O shilo.diff http://patchwork.ozlabs.org/patch/203744/mbox
> git am ./shilo.diff
> 
> You probably have the previous (not yet committed) INSV patch on your
> branch
> that creates an issue for you when you run 'git am'.
> 
> Petar
> 
> From: Johnson, Eric
> Sent: Wednesday, December 05, 2012 10:36 PM
> To: Jovanovic, Petar; qemu-devel@nongnu.org
> Cc: blauwir...@gmail.com; rth7...@gmail.com; afaer...@suse.de;
> aurel...@aurel32.net
> Subject: RE: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> SHILO and SHILOV
> 
> Oops, I forgot.  The contents are OK but 'git am' didn't like the patch.
> patch had to use fuzz.  This may need to be rebased to latest master.
> 
> -Eric
> 
> > -Original Message-
> > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> > bounces+ericj=mips@nongnu.org] On Behalf Of Johnson, Eric
> > Sent: Wednesday, December 05, 2012 12:42 PM
> > To: Jovanovic, Petar; qemu-devel@nongnu.org
> > Cc: blauwir...@gmail.com; rth7...@gmail.com; afaer...@suse.de;
> > aurel...@aurel32.net
> > Subject: Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift
> for
> > SHILO and SHILOV
> >
> > > -Original Message-
> > > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> > > bounces+ericj=mips@nongnu.org] On Behalf Of Petar Jovanovic
> > > Sent: Tuesday, December 04, 2012 3:29 PM
> > > To: qemu-devel@nongnu.org
> > > Cc: blauwir...@gmail.com; Jovanovic, Petar; rth7...@gmail.com;
> > > afaer...@suse.de; aurel...@aurel32.net
> > > Subject: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> > > SHILO and SHILOV
> > >
> > > From: Petar Jovanovic 
> > >
> > > helper_shilo has not been shifting an accumulator value correctly for
> > > negative
> > > values in 'shift' field. Minor optimization for shift=0 case.
> > > This change also adds tests that will trigger issue and check for
> > > regressions.
> > >
> > > Signed-off-by: Petar Jovanovic 
> > > ---
> > >  target-mips/dsp_helper.c   |   17 +
> > >  tests/tcg/mips/mips32-dsp/shilo.c  |   18 ++
> > >  tests/tcg/mips/mips32-dsp/shilov.c |   20 
> > >  3 files changed, 47 insertions(+), 8 deletions(-)
> > >
> > > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> > > index e7949c2..44f6dc7 100644
> > > --- a/target-mips/dsp_helper.c
> > > +++ b/target-mips/dsp_helper.c
> > > @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac,
> target_ulong
> > > rs, CPUMIPSState *env)
> > >
> > >  rs5_0 = rs & 0x3F;
> > >  rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
> > > -rs5_0 = MIPSDSP_ABS(rs5_0);
> > > +
> > > +if (unlikely(rs5_0 == 0)) {
> > > +return;
> > > +}
> > > +
> > >  acc   = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
> > >  ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
> > > -if (rs5_0 == 0) {
> > > -temp = acc;
> > > +
> > > +if (rs5_0 > 0) {
> > > +temp = acc >> rs5_0;
> > >  } else {
> > > -if (rs5_0 > 0) {
> > > -temp = acc >> rs5_0;
> > > -} else {
> > > -temp = acc << rs5_0;
> > > -}
> > > +temp = acc << -rs5_0;
> > >  }
> > >
> > >  env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp &
> > MIPSDSP_LHI)
> > > >> 32);
> > > diff --git a/tests/tcg/mips/mips32-dsp/shilo.c
> b/tests/tcg/mips/mips32-
> > > dsp/shilo.c
> > > index b686616..ce8ebc6 100644
> > > --- a/tests/tcg/mips/mips32-dsp/shilo.c
> > > +++ b/tests/tcg/

Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO and SHILOV

[Johnson, Eric]

Oops, I forgot.  The contents are OK but 'git am' didn't like the patch.  patch 
had to use fuzz.  This may need to be rebased to latest master.

-Eric

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Johnson, Eric
> Sent: Wednesday, December 05, 2012 12:42 PM
> To: Jovanovic, Petar; qemu-devel@nongnu.org
> Cc: blauwir...@gmail.com; rth7...@gmail.com; afaer...@suse.de;
> aurel...@aurel32.net
> Subject: Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> SHILO and SHILOV
> 
> > -Original Message-
> > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> > bounces+ericj=mips@nongnu.org] On Behalf Of Petar Jovanovic
> > Sent: Tuesday, December 04, 2012 3:29 PM
> > To: qemu-devel@nongnu.org
> > Cc: blauwir...@gmail.com; Jovanovic, Petar; rth7...@gmail.com;
> > afaer...@suse.de; aurel...@aurel32.net
> > Subject: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> > SHILO and SHILOV
> >
> > From: Petar Jovanovic 
> >
> > helper_shilo has not been shifting an accumulator value correctly for
> > negative
> > values in 'shift' field. Minor optimization for shift=0 case.
> > This change also adds tests that will trigger issue and check for
> > regressions.
> >
> > Signed-off-by: Petar Jovanovic 
> > ---
> >  target-mips/dsp_helper.c   |   17 +
> >  tests/tcg/mips/mips32-dsp/shilo.c  |   18 ++
> >  tests/tcg/mips/mips32-dsp/shilov.c |   20 
> >  3 files changed, 47 insertions(+), 8 deletions(-)
> >
> > diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> > index e7949c2..44f6dc7 100644
> > --- a/target-mips/dsp_helper.c
> > +++ b/target-mips/dsp_helper.c
> > @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong
> > rs, CPUMIPSState *env)
> >
> >  rs5_0 = rs & 0x3F;
> >  rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
> > -rs5_0 = MIPSDSP_ABS(rs5_0);
> > +
> > +if (unlikely(rs5_0 == 0)) {
> > +return;
> > +}
> > +
> >  acc   = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
> >  ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
> > -if (rs5_0 == 0) {
> > -temp = acc;
> > +
> > +if (rs5_0 > 0) {
> > +temp = acc >> rs5_0;
> >  } else {
> > -if (rs5_0 > 0) {
> > -temp = acc >> rs5_0;
> > -} else {
> > -temp = acc << rs5_0;
> > -}
> > +temp = acc << -rs5_0;
> >  }
> >
> >  env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp &
> MIPSDSP_LHI)
> > >> 32);
> > diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-
> > dsp/shilo.c
> > index b686616..ce8ebc6 100644
> > --- a/tests/tcg/mips/mips32-dsp/shilo.c
> > +++ b/tests/tcg/mips/mips32-dsp/shilo.c
> > @@ -23,5 +23,23 @@ int main()
> >  assert(ach == resulth);
> >  assert(acl == resultl);
> >
> > +
> > +ach = 0x1;
> > +acl = 0x8000;
> > +
> > +resulth = 0x3;
> > +resultl = 0x0;
> > +
> > +__asm
> > +("mthi %0, $ac1\n\t"
> > + "mtlo %1, $ac1\n\t"
> > + "shilo $ac1, -1\n\t"
> > + "mfhi %0, $ac1\n\t"
> > + "mflo %1, $ac1\n\t"
> > + : "+r"(ach), "+r"(acl)
> > +);
> > +assert(ach == resulth);
> > +assert(acl == resultl);
> > +
> >  return 0;
> >  }
> > diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-
> > dsp/shilov.c
> > index f186032..e1d6cea 100644
> > --- a/tests/tcg/mips/mips32-dsp/shilov.c
> > +++ b/tests/tcg/mips/mips32-dsp/shilov.c
> > @@ -25,5 +25,25 @@ int main()
> >  assert(ach == resulth);
> >  assert(acl == resultl);
> >
> > +
> > +rs  = 0x;
> > +ach = 0x1;
> > +acl = 0x8000;
> > +
> > +resulth = 0x3;
> > +resultl = 0x0;
> > +
> > +__asm
> > +("mthi %0, $ac1\n\t"
> > + "mtlo %1, $ac1\n\t"
> > + "shilov $ac1, %2\n\t"
> > + "mfhi %0, $ac1\n\t"
> > + "mflo %1, $ac1\n\t"
> > + : "+r"(ach), "+r"(acl)
> > + : "r"(rs)
> > +);
> > +assert(ach == resulth);
> > +assert(acl == resultl);
> > +
> >  return 0;
> >  }
> > --
> > 1.7.5.4
> >
> 
> Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for SHILO and SHILOV

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Petar Jovanovic
> Sent: Tuesday, December 04, 2012 3:29 PM
> To: qemu-devel@nongnu.org
> Cc: blauwir...@gmail.com; Jovanovic, Petar; rth7...@gmail.com;
> afaer...@suse.de; aurel...@aurel32.net
> Subject: [Qemu-devel] [PATCH v2] target-mips: Fix incorrect shift for
> SHILO and SHILOV
> 
> From: Petar Jovanovic 
> 
> helper_shilo has not been shifting an accumulator value correctly for
> negative
> values in 'shift' field. Minor optimization for shift=0 case.
> This change also adds tests that will trigger issue and check for
> regressions.
> 
> Signed-off-by: Petar Jovanovic 
> ---
>  target-mips/dsp_helper.c   |   17 +
>  tests/tcg/mips/mips32-dsp/shilo.c  |   18 ++
>  tests/tcg/mips/mips32-dsp/shilov.c |   20 
>  3 files changed, 47 insertions(+), 8 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..44f6dc7 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong
> rs, CPUMIPSState *env)
> 
>  rs5_0 = rs & 0x3F;
>  rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
> -rs5_0 = MIPSDSP_ABS(rs5_0);
> +
> +if (unlikely(rs5_0 == 0)) {
> +return;
> +}
> +
>  acc   = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
>  ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
> -if (rs5_0 == 0) {
> -temp = acc;
> +
> +if (rs5_0 > 0) {
> +temp = acc >> rs5_0;
>  } else {
> -if (rs5_0 > 0) {
> -temp = acc >> rs5_0;
> -} else {
> -temp = acc << rs5_0;
> -}
> +temp = acc << -rs5_0;
>  }
> 
>  env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI)
> >> 32);
> diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-
> dsp/shilo.c
> index b686616..ce8ebc6 100644
> --- a/tests/tcg/mips/mips32-dsp/shilo.c
> +++ b/tests/tcg/mips/mips32-dsp/shilo.c
> @@ -23,5 +23,23 @@ int main()
>  assert(ach == resulth);
>  assert(acl == resultl);
> 
> +
> +ach = 0x1;
> +acl = 0x8000;
> +
> +resulth = 0x3;
> +resultl = 0x0;
> +
> +__asm
> +("mthi %0, $ac1\n\t"
> + "mtlo %1, $ac1\n\t"
> + "shilo $ac1, -1\n\t"
> + "mfhi %0, $ac1\n\t"
> + "mflo %1, $ac1\n\t"
> + : "+r"(ach), "+r"(acl)
> +);
> +assert(ach == resulth);
> +assert(acl == resultl);
> +
>  return 0;
>  }
> diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-
> dsp/shilov.c
> index f186032..e1d6cea 100644
> --- a/tests/tcg/mips/mips32-dsp/shilov.c
> +++ b/tests/tcg/mips/mips32-dsp/shilov.c
> @@ -25,5 +25,25 @@ int main()
>  assert(ach == resulth);
>  assert(acl == resultl);
> 
> +
> +rs  = 0x;
> +ach = 0x1;
> +acl = 0x8000;
> +
> +resulth = 0x3;
> +resultl = 0x0;
> +
> +__asm
> +("mthi %0, $ac1\n\t"
> + "mtlo %1, $ac1\n\t"
> + "shilov $ac1, %2\n\t"
> + "mfhi %0, $ac1\n\t"
> + "mflo %1, $ac1\n\t"
> + : "+r"(ach), "+r"(acl)
> + : "r"(rs)
> +);
> +assert(ach == resulth);
> +assert(acl == resultl);
> +
>  return 0;
>  }
> --
> 1.7.5.4
> 

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for INSV

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Petar Jovanovic
> Sent: Monday, November 26, 2012 7:13 AM
> To: qemu-devel@nongnu.org
> Cc: Jovanovic, Petar; aurel...@aurel32.net
> Subject: [Qemu-devel] [PATCH] target-mips: Fix incorrect code and test for
> INSV
> 
> From: Petar Jovanovic 
> 
> Content of register rs should be shifted for pos before applying a mask.
> This change contains both fix for the instruction and to the existing
> test.
> 
> Signed-off-by: Petar Jovanovic 
> ---
>  target-mips/dsp_helper.c |2 +-
>  tests/tcg/mips/mips32-dsp/insv.c |2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..fda5f04 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env,
> target_ulong rs,  \
>  \
>  filter = ((int32_t)0x01 << size) - 1;   \
>  filter = filter << pos; \
> -temprs = rs & filter;   \
> +temprs = (rs << pos) & filter;  \
>  temprt = rt & ~filter;  \
>  temp = temprs | temprt; \
>  \
> diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-
> dsp/insv.c
> index 7e3b047..243b007 100644
> --- a/tests/tcg/mips/mips32-dsp/insv.c
> +++ b/tests/tcg/mips/mips32-dsp/insv.c
> @@ -10,7 +10,7 @@ int main()
>  dsp= 0x305;
>  rt = 0x12345678;
>  rs = 0x87654321;
> -result = 0x12345338;
> +result = 0x12345438;
>  __asm
>  ("wrdsp %2, 0x03\n\t"
>   "insv  %0, %1\n\t"
> --
> 1.7.5.4
> 

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH 5/7] target-mips: use DSP unions for unary DSP operators

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 5/7] target-mips: use DSP unions for unary
> DSP operators
> 
> This allow to reduce the number of macros.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/dsp_helper.c |  124 -
> -
>  1 file changed, 42 insertions(+), 82 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 931ca70..3bd2d35 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -1139,6 +1139,48 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a,
> uint32_t b)
>  #endif
> 
>  /** DSP Arithmetic Sub-class insns **/
> +#define MIPSDSP32_UNOP_ENV(name, func, element)
> \
> +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env)
> \
> +{
> \
> +DSP32Value dt;
> \
> +unsigned int i, n;
> \
> +
> \
> +n = sizeof(DSP32Value) / sizeof(dt.element[0]);
> \
> +dt.sw[0] = rt;
> \
> +
> \
> +for (i = 0 ; i < n ; i++) {
> \
> +dt.element[i] = mipsdsp_##func(dt.element[i], env);
> \
> +}
> \
> +
> \
> +return (int32_t)dt.sw[0];
> \
> +}
> +MIPSDSP32_UNOP_ENV(absq_s_ph, sat_abs16, sh)
> +MIPSDSP32_UNOP_ENV(absq_s_qb, sat_abs8, sb)
> +MIPSDSP32_UNOP_ENV(absq_s_w, sat_abs32, sw)
> +#undef MIPSDSP32_UNOP_ENV
> +
> +#if defined(TARGET_MIPS64)
> +#define MIPSDSP64_UNOP_ENV(name, func, element)
> \
> +target_ulong helper_##name(target_ulong rt, CPUMIPSState *env)
> \
> +{
> \
> +DSP64Value dt;
> \
> +unsigned int i, n;
> \
> +
> \
> +n = sizeof(DSP64Value) / sizeof(dt.element[0]);
> \
> +dt.sl[0] = rt;
> \
> +
> \
> +for (i = 0 ; i < n ; i++) {
> \
> +dt.element[i] = mipsdsp_##func(dt.element[i], env);
> \
> +}
> \
> +
> \
> +return dt.sl[0];
> \
> +}
> +MIPSDSP64_UNOP_ENV(absq_s_ob, sat_abs8, sb)
> +MIPSDSP64_UNOP_ENV(absq_s_qh, sat_abs16, sh)
> +MIPSDSP64_UNOP_ENV(absq_s_pw, sat_abs32, sw)
> +#undef MIPSDSP64_UNOP_ENV
> +#endif
> +
>  #define MIPSDSP32_BINOP(name, func, element)
> \
>  target_ulong helper_##name(target_ulong rs, target_ulong rt)
> \
>  {
> \
> @@ -1260,16 +1302,6 @@ MIPSDSP64_BINOP_ENV(subu_s_qh, satu16_sub_u16_u16,
> uh);
> 
>  #endif
> 
> -target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env)
> -{
> -uint32_t rd;
> -
> -rd = mipsdsp_sat_abs32(rt, env);
> -
> -return (target_ulong)rd;
> -}
> -
> -
>  #define SUBUH_QB(name, var) \
>  target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \
>  { \
> @@ -1377,78 +1409,6 @@ target_ulong helper_raddu_l_ob(target_ulong rs)
>  }
>  #endif
> 
> -target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env)
> -{
> -uint8_t tempD, tempC, tempB, tempA;
> -
> -MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA);
> -
> -tempD = mipsdsp_sat_abs8(tempD, env);
> -tempC = mipsdsp_sat_abs8(tempC, env);
> -tempB = mipsdsp_sat_abs8(tempB, env);
> -tempA = mipsdsp_sat_abs8(tempA, env);
> -
> -return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA);
> -}
> -
> -target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env)
> -{
> -uint16_t tempB, tempA;
> -
> -MIPSDSP_SPLIT32_16(rt, tempB, tempA);
> -
> -tempB = mipsdsp_sat_abs16 (tempB, env);
> -tempA = mipsdsp_sat_abs16 (tempA, env);
> -
> -return MIPSDSP_RETURN32_16(tempB, tempA);
> -}
> -
> -#if defined(TARGET_MIPS64)
> -target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env)
> -{
> -int i;
> -int8_t temp[8];
> -uint64_t result;
> -
> -for (i = 0; i < 8; i++) {
> -temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0;
> -temp[i] = mipsdsp_sat_abs8(temp[i], env);
> -}
> -
> -for (i = 0; i < 8; i++) {
> -result = (uint64_t)(uint8_t)temp[i] << (8 * i);
> -}
> -
> -return result;
> -}
> -
> -target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env)
> -{
> -int16_t tempD, tempC, tempB, tempA;
> -
> -MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA);
> -
> -tempD = mipsdsp_sat_abs16(tempD, env);
> -tempC = mipsdsp_sat_abs16(tempC, env);
> -tempB = mipsdsp_sat_abs16(tempB, env);
> -tempA = mipsdsp_sat_abs16(tempA, env);
> -
> -return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA);
> -}
> -
> -target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env)
> -{
> -int32_t tempB, tempA;
> -
> -MIPSDSP_SPLIT64_32(rt, tempB, tempA);
> -
> -tempB = mipsdsp_sat_abs32(tempB, env);
> -tempA = mipsdsp_sat_abs32(tempA, env);
> -
> -return MIPSDSP_RETURN64_32(tempB, tempA);
> -}
> -#endif
> -
>  #define PRECR_QB_PH(name, a, b)\
>  target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \
>  { 

Re: [Qemu-devel] [PATCH 7/7] target-mips: implement DSP (d)append sub-class with TCG

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 7/7] target-mips: implement DSP (d)append
> sub-class with TCG
> 
> DSP instruction from the (d)append sub-class can be implemented with
> TCG. Use a different function for these instructions are they are quite
> different from compare-pick sub-class.
> 
> Fix BALIGN instruction for negative value, where the value should be
> zero-extended before being shift to the right.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/dsp_helper.c |   67 ---
>  target-mips/helper.h |   13 -
>  target-mips/translate.c  |  133 ++---
> -
>  3 files changed, 87 insertions(+), 126 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 474c249..22bbfa1 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -3140,73 +3140,6 @@ PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0);
>  #endif
>  #undef PICK_INSN
> 
> -#define APPEND_INSN(name, ret_32) \
> -target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa)
> \
> -{
> \
> -target_ulong temp;
> \
> -
> \
> -if (ret_32) {
> \
> -temp = ((rt & MIPSDSP_LLO) << sa) |
> \
> -   ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1));
> \
> -temp = (target_long)(int32_t)(temp & MIPSDSP_LLO);
> \
> -} else {
> \
> -temp = (rt << sa) | (rs & ((0x01 << sa) - 1));
> \
> -}
> \
> -
> \
> -return temp;
> \
> -}
> -
> -APPEND_INSN(append, 1);
> -#ifdef TARGET_MIPS64
> -APPEND_INSN(dappend, 0);
> -#endif
> -#undef APPEND_INSN
> -
> -#define PREPEND_INSN(name, or_val, ret_32)\
> -target_ulong helper_##name(target_ulong rs, target_ulong rt,  \
> -   uint32_t sa)   \
> -{ \
> -sa |= or_val; \
> -  \
> -if (1) {  \
> -return (target_long)(int32_t)(uint32_t)   \
> -(((rs & MIPSDSP_LLO) << (32 - sa)) |  \
> - ((rt & MIPSDSP_LLO) >> sa)); \
> -} else {  \
> -return (rs << (64 - sa)) | (rt >> sa);\
> -} \
> -}
> -
> -PREPEND_INSN(prepend, 0, 1);
> -#ifdef TARGET_MIPS64
> -PREPEND_INSN(prependw, 0, 0);
> -PREPEND_INSN(prependd, 0x20, 0);
> -#endif
> -#undef PREPEND_INSN
> -
> -#define BALIGN_INSN(name, filter, ret32) \
> -target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp)
> \
> -{
> \
> -bp = bp & 0x03;
> \
> -
> \
> -if ((bp & 1) == 0) {
> \
> -return rt;
> \
> -} else {
> \
> -if (ret32) {
> \
> -return (target_long)(int32_t)((rt << (8 * bp)) |
> \
> -  (rs >> (8 * (4 - bp;
> \
> -} else {
> \
> -return (rt << (8 * bp)) | (rs >> (8 * (8 - bp)));
> \
> -}
> \
> -}
> \
> -}
> -
> -BALIGN_INSN(balign, 0x03, 1);
> -#if defined(TARGET_MIPS64)
> -BALIGN_INSN(dbalign, 0x07, 0);
> -#endif
> -#undef BALIGN_INSN
> -
>  target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt)
>  {
>  uint32_t rsl, rth;
> diff --git a/target-mips/helper.h b/target-mips/helper.h
> index acf9ebd..4373ac5 100644
> --- a/target-mips/helper.h
> +++ b/target-mips/helper.h
> @@ -654,19 +654,6 @@ DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env)
>  DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env)
>  DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env)
>  #endif
> -DEF_HELPER_FLAGS_3(append, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#if defined(TARGET_MIPS64)
> -DEF_HELPER_FLAGS_3(dappend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#endif
> -DEF_HELPER_FLAGS_3(prepend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#if defined(TARGET_MIPS64)
> -DEF_HELPER_FLAGS_3(prependd, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -DEF_HELPER_FLAGS_3(prependw, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#endif
> -DEF_HELPER_FLAGS_3(balign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#if defined(TARGET_MIPS64)
> -DEF_HELPER_FLAGS_3(dbalign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32)
> -#endif
>  DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl)
>  #if defined(TARGET_MIPS64)
>  DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 910dd16..624d5a5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -336,7 +336,7 @@ enum {
>  /* DSP Bit/Manipulation Sub-class */
>  OPC_IN

Re: [Qemu-devel] [PATCH 4/7] target-mips: use DSP unions for binary DSP operators

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 4/7] target-mips: use DSP unions for binary
> DSP operators
> 
> This allow to reduce the number of macros.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/dsp_helper.c |  384 ++---
> -
>  1 file changed, 116 insertions(+), 268 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 8015d8d..931ca70 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -1107,7 +1107,6 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a,
> uint32_t b)
>  b = num & MIPSDSP_LO;   \
>  } while (0)
> 
> -#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a)
>  #define MIPSDSP_RETURN32_8(a, b, c, d)  ((target_long)(int32_t) \
>   (((uint32_t)a << 24) | \
>   (((uint32_t)b << 16) | \
> @@ -1140,119 +1139,127 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t
> a, uint32_t b)
>  #endif
> 
>  /** DSP Arithmetic Sub-class insns **/
> -#define ARITH_PH(name, func)  \
> -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \
> -{ \
> -uint16_t  rsh, rsl, rth, rtl, temph, templ;   \
> -  \
> -MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
> -MIPSDSP_SPLIT32_16(rt, rth, rtl); \
> -  \
> -temph = mipsdsp_##func(rsh, rth); \
> -templ = mipsdsp_##func(rsl, rtl); \
> -  \
> -return MIPSDSP_RETURN32_16(temph, templ); \
> -}
> -
> -#define ARITH_PH_ENV(name, func)  \
> -target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \
> -CPUMIPSState *env)\
> -{ \
> -uint16_t  rsh, rsl, rth, rtl, temph, templ;   \
> -  \
> -MIPSDSP_SPLIT32_16(rs, rsh, rsl); \
> -MIPSDSP_SPLIT32_16(rt, rth, rtl); \
> -  \
> -temph = mipsdsp_##func(rsh, rth, env);\
> -templ = mipsdsp_##func(rsl, rtl, env);\
> -  \
> -return MIPSDSP_RETURN32_16(temph, templ); \
> -}
> -
> -
> -ARITH_PH_ENV(addq, add_i16);
> -ARITH_PH_ENV(addq_s, sat_add_i16);
> -ARITH_PH_ENV(addu, add_u16);
> -ARITH_PH_ENV(addu_s, sat_add_u16);
> -
> -ARITH_PH(addqh, rshift1_add_q16);
> -ARITH_PH(addqh_r, rrshift1_add_q16);
> -
> -ARITH_PH_ENV(subq, sub_i16);
> -ARITH_PH_ENV(subq_s, sat16_sub);
> -ARITH_PH_ENV(subu, sub_u16_u16);
> -ARITH_PH_ENV(subu_s, satu16_sub_u16_u16);
> -
> -ARITH_PH(subqh, rshift1_sub_q16);
> -ARITH_PH(subqh_r, rrshift1_sub_q16);
> -
> -#undef ARITH_PH
> -#undef ARITH_PH_ENV
> +#define MIPSDSP32_BINOP(name, func, element)
> \
> +target_ulong helper_##name(target_ulong rs, target_ulong rt)
> \
> +{
> \
> +DSP32Value ds, dt;
> \
> +unsigned int i, n;
> \
> +
> \
> +n = sizeof(DSP32Value) / sizeof(ds.element[0]);
> \
> +ds.sw[0] = rs;
> \
> +dt.sw[0] = rt;
> \
> +
> \
> +for (i = 0 ; i < n ; i++) {
> \
> +ds.element[i] = mipsdsp_##func(ds.element[i], dt.element[i]);
> \
> +}
> \
> +
> \
> +return (int32_t)ds.sw[0];
> \
> +}
> +MIPSDSP32_BINOP(addqh_ph, rshift1_add_q16, sh);
> +MIPSDSP32_BINOP(addqh_r_ph, rrshift1_add_q16, sh);
> +MIPSDSP32_BINOP(addqh_r_w, rrshift1_add_q32, sw);
> +MIPSDSP32_BINOP(addqh_w, rshift1_add_q32, sw);
> +MIPSDSP32_BINOP(adduh_qb, rshift1_add_u8, ub);
> +MIPSDSP32_BINOP(adduh_r_qb, rrshift1_add_u8, ub);
> +MIPSDSP32_BINOP(subqh_ph, rshift1_sub_q16, sh);
> +MIPSDSP32_BINOP(subqh_r_ph, rrshift1_sub_q16, sh);
> +MIPSDSP32_BINOP(subqh_r_w, rrshift1_sub_q32, sw);
> +MIPSDSP32_BINOP(subqh_w, rshift1_sub_q32, sw);
> +#undef MIPSDSP32_BINOP
> +
> +#define MIPSDSP32_BINOP_ENV(name, func, element)
> \
> +target_ulong helper_##name(target_ulong rs, target_ulong rt,
> \
> +   CPUMIPSState *env)
> \
> +{
> \
> +DSP32Value ds, dt;
> \
> +unsigned int i, n;
> \
> +
> \
> +n = sizeof(DSP32Value) / sizeof(ds.element[0]);
> \
> +ds.sw[0]

Re: [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for reduction add instructions

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 6/7] target-mips: use DSP unions for
> reduction add instructions
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/dsp_helper.c |   32 +++-
>  1 file changed, 15 insertions(+), 17 deletions(-)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index 3bd2d35..474c249 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -1381,31 +1381,29 @@ target_ulong helper_modsub(target_ulong rs,
> target_ulong rt)
> 
>  target_ulong helper_raddu_w_qb(target_ulong rs)
>  {
> -uint8_t  rs3, rs2, rs1, rs0;
> -uint16_t temp;
> -
> -MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0);
> -
> -temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0;
> +target_ulong ret = 0;
> +DSP32Value ds;
> +unsigned int i;
> 
> -return (target_ulong)temp;
> +ds.uw[0] = rs;
> +for (i = 0 ; i < 4 ; i++) {
> +ret += ds.ub[i];
> +}
> +return ret;
>  }
> 
>  #if defined(TARGET_MIPS64)
>  target_ulong helper_raddu_l_ob(target_ulong rs)
>  {
> -int i;
> -uint16_t rs_t[8];
> -uint64_t temp;
> -
> -temp = 0;
> +target_ulong ret = 0;
> +DSP64Value ds;
> +unsigned int i;
> 
> -for (i = 0; i < 8; i++) {
> -rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0;
> -temp += (uint64_t)rs_t[i];
> +ds.ul[0] = rs;
> +for (i = 0 ; i < 8 ; i++) {
> +ret += ds.ub[i];
>  }
> -
> -return temp;
> +return ret;
>  }
>  #endif
> 
> --
> 1.7.10.4
> 

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [RFC] 1.4 release schedule

[Johnson, Eric]

I think you meant to change the 1.3.0 to 1.4.0 for the milestones on the Wiki. 
;-)

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Anthony Liguori
> Sent: Monday, December 03, 2012 1:30 PM
> To: qemu-devel@nongnu.org
> Subject: [Qemu-devel] [RFC] 1.4 release schedule
> 
> 
> Hi,
> 
> Based on popular demand, I'd like to continue with a 3-month release
> cycle for the foreseeable future.  One thing I'd like to "fix" though is
> to avoid major holidays during the -rc cycles.
> 
> The best cycle I can figure is:
> 
> Feb 15th
> May 15th
> Aug 15th
> Nov 15th
> 
> To get us onto this schedule, we'll need to make 1.4 a short release but
> I still think there's ample time to ge stuff done.
> 
> I've put up a strawman schedule on the wiki:
> 
> http://wiki.qemu.org/Planning/1.4
> 
> Regards,
> 
> Anthony Liguori
> 

Re: [Qemu-devel] MIPS exception number limits?

[Johnson, Eric]

> -Original Message-
> From: Richard Henderson [mailto:rth7...@gmail.com] On Behalf Of Richard
> Henderson
> Sent: Tuesday, November 27, 2012 1:19 PM
> To: Johnson, Eric
> Cc: "陳韋任 (Wei-Ren Chen)"; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] MIPS exception number limits?
> 
> On 11/26/2012 09:25 PM, Johnson, Eric wrote:
> > So basically the SC and SCD instructions for user-mode QEMU are
> implemented with a "dummy" exception.  Since it is not a real exception,
> it is not reported in the QEMU log file as an exception.
> 
> I'm not certain that's a helpful distinction to make when it comes to
> debugging qemu.
> 
> 
> r~

It may not be a helpful distinction.

The under 0x100 check has been there since 2005 which is long before I looked 
at any QEMU code.  I was describing the code as it exists based on deductions 
from looking at the code.  I should have made that clear that my summary.

My first draft of a response I described the steps I did (I.E. vim op_helper.c, 
grep EXCP *.h, gitk op_helper.c, grep EXCP_SC *, vim translate.c) to get to the 
conclusions I made.  When I read it seemed like it might be interpreted as 
condescending which was not my intent.

In the original reply I also meant to say "removing the '#if 1' is fine with 
me."

/If/ the under 0x100 check remains, I would advocate using EXCP_SC instead of a 
magic constant.

-Eric

Re: [Qemu-devel] MIPS exception number limits?

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of ??? (Wei-Ren Chen)
> Sent: Thursday, November 22, 2012 11:34 AM
> To: qemu-devel@nongnu.org
> Subject: [Qemu-devel] MIPS exception number limits?
> 
> Hi all,
> 
>   Wondering why MIPS limits exception number less then 0x100,
> you can see such example in function do_raise_exception_err
> (target-mips/op_helper.c). See below,
> 
> static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
> ...
> {
>   ...
> 
> #if 1
> if (exception < 0x100)
> qemu_log("%s: %d %d\n", __func__, exception, error_code);
> #endif
> 
>   ...
> }
> 
>   Anyone can help confirm this, stated in what spec? Also, do we
> need "#if 1 .. #endif"? Thanks for help. =]
> 
> Regards,
> chenwj
> 
> --
> Wei-Ren Chen (陳韋任)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> Homepage: http://people.cs.nctu.edu.tw/~chenwj

The 0x100 is an arbitrary value known to be larger than the maximum possible 
CP0.Cause.ExcCode value.

From target-mips/cpu.h:
/* Dummy exception for conditional stores.  */
#define EXCP_SC 0x100

From target-mips/translate.c:
gen_helper_0e0i(raise_exception, EXCP_SC); \

It can be seen the only use of EXCP_SC is for the macro OP_ST_ATOMIC when 
CONFIG_USER_ONLY is defined.

So basically the SC and SCD instructions for user-mode QEMU are implemented 
with a "dummy" exception.  Since it is not a real exception, it is not reported 
in the QEMU log file as an exception.

-Eric

Re: [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP elements

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 3/7] target-mips: add unions to access DSP
> elements
> 
> Instead of playing with bit shifting, add two unions (one for 32-bit
> values, one for 64-bit ones) to access all the DSP elements with the
> correct type.
> 
> This make the code easier to read and less error prone, and allow GCC
> to vectorize the code in some cases.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/dsp_helper.c |   22 ++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
> index e7949c2..8015d8d 100644
> --- a/target-mips/dsp_helper.c
> +++ b/target-mips/dsp_helper.c
> @@ -20,6 +20,28 @@
>  #include "cpu.h"
>  #include "helper.h"
> 
> +/* As the byte ordering doesn't matter, i.e. all columns are treated
> +   identically, these unions can be used directly.  */
> +typedef union {
> +uint8_t  ub[4];
> +int8_t   sb[4];
> +uint16_t uh[2];
> +int16_t  sh[2];
> +uint32_t uw[1];
> +int32_t  sw[1];
> +} DSP32Value;
> +
> +typedef union {
> +uint8_t  ub[8];
> +int8_t   sb[8];
> +uint16_t uh[4];
> +int16_t  sh[4];
> +uint32_t uw[2];
> +int32_t  sw[2];
> +uint64_t ul[1];
> +int64_t  sl[1];
> +} DSP64Value;
> +
>  /*** MIPS DSP internal functions begin ***/
>  #define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x)
>  #define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d)))
> --
> 1.7.10.4
> 

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved instruction exception on CPU without DSP

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Richard Henderson
> Sent: Friday, November 16, 2012 2:03 PM
> To: Aurelien Jarno
> Cc: qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH 2/7] target-mips: generate a reserved
> instruction exception on CPU without DSP
> 
> On 11/16/2012 03:04 AM, Aurelien Jarno wrote:
> > +static inline void check_dsp(CPUMIPSState *env, DisasContext *ctx)
> >  {
> >  if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) {
> > -generate_exception(ctx, EXCP_DSPDIS);
> > +if (env->insn_flags & ASE_DSP) {
> > +generate_exception(ctx, EXCP_DSPDIS);
> > +} else {
> > +generate_exception(ctx, EXCP_RI);
> > +}
> 
> Perhaps it would make more sense to copy env->insn_flags into
> a new field in DisasContext at the start of translation, rather
> than modify 300 instances to pass around a second pointer?
> 
> 
> r~

I agree copying insn_flags to a new field is probably a cleaner way to go.

Also minor complaints from checkpatch.pl:
$ upstream/scripts/checkpatch.pl 'patches/dsp-ase-aurelien/Qemu-devel PATCH 27 
target-mips generate a reservedinstruction exception on CPU without DSP.txt'
WARNING: line over 80 characters
#54: FILE: target-mips/translate.c:2582:
+static void gen_HILO (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int 
reg)

WARNING: space prohibited between function name and open parenthesis '('
#54: FILE: target-mips/translate.c:2582:
+static void gen_HILO (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int 
reg)

WARNING: space prohibited between function name and open parenthesis '('
#73: FILE: target-mips/translate.c:2661:
+static void gen_muldiv (CPUMIPSState *env, DisasContext *ctx,

total: 0 errors, 3 warnings, 1825 lines checked

patches/dsp-ase-aurelien/Qemu-devel PATCH 27 target-mips generate a 
reservedinstruction exception on CPU without DSP.txt has style problems, please 
review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

-Eric

Re: [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Friday, November 16, 2012 3:04 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0
> 
> When rd is 0, which still need to do the actually load to possibly
> generate a TLB exception.
> 
> Signed-off-by: Aurelien Jarno 
> ---
>  target-mips/translate.c |5 -
>  1 file changed, 5 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 01b48fa..c3e00c5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12631,11 +12631,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env,
> DisasContext *ctx, uint32_t opc,
>  const char *opn = "ldx";
>  TCGv t0;
> 
> -if (rd == 0) {
> -MIPS_DEBUG("NOP");
> -return;
> -}
> -
>  check_dsp(ctx);
>  t0 = tcg_temp_new();
> 
> --
> 1.7.10.4
> 

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH v3] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

> -Original Message-
> From: 陳韋任 (Wei-Ren Chen) [mailto:che...@iis.sinica.edu.tw]
> Sent: Tuesday, November 20, 2012 10:05 PM
> To: qemu-devel@nongnu.org
> Cc: Johnson, Eric; Aurelien Jarno; Jia Liu
> Subject: [PATCH v3] target-mips: Clean up microMIPS32 major opcode
> 
>   I check MIPS microMIPS manual [1], and found the major opcode might
> be wrong. I add a comment to explicitly indicate what manual I am refering
> to, and according that manual I remove microMIPS32 major opcodes 0x1f.
> As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order
> MIPS ISA level or new revision of this microMIPS architecture. Quote
> from Johnson, they are belong MIPS64 [2].
> 
> [1] http://www.mips.com/products/architectures/micromips/#specifications
> 
> MIPS Architecture for Programmers Volume II-B:
>   The microMIPS32 Instruction Set (Revision 3.05)
> 
> MD00582-2B-microMIPS-AFP-03.05.pdf
> 
> [2] http://www.mips.com/products/architectures/mips64/
> 
> MIPS Architecture For Programmers
>   Volume II-A: The MIPS64 Instruction Set
> 
> MD00087-2B-MIPS64BIS-AFP-03.51.pdf
> 
> Signed-off-by: Chen Wei-Ren 
> ---
> 
> v3: Correct commit message formatting.
> 
> v2: Remove POOL48A only. The other three opcode are belong MIPS64.
> 
>  target-mips/translate.c | 24 +---
>  1 file changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 8b438f8..7fe8d83 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env,
> DisasContext *ctx,
>  return n_bytes;
>  }
> 
> -/* microMIPS extension to MIPS32 */
> +/* microMIPS extension to MIPS32/MIPS64 */
> 
> -/* microMIPS32 major opcodes */
> +/*
> + * microMIPS32/microMIPS64 major opcodes
> + *
> + * 1. MIPS Architecture for Programmers Volume II-B:
> + *  The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + *Table 6.2 microMIPS32 Encoding of Major Opcode Field
> + *
> + * 2. MIPS Architecture For Programmers Volume II-A:
> + *  The MIPS64 Instruction Set (Revision 3.51)
> + */
> 
>  enum {
>  POOL32A = 0x00,
> @@ -10268,9 +10278,10 @@ enum {
>  POOL16D = 0x13,
>  ORI32 = 0x14,
>  POOL32F = 0x15,
> -POOL32S = 0x16,
> -DADDIU32 = 0x17,
> +POOL32S = 0x16,  /* MIPS64 */
> +DADDIU32 = 0x17, /* MIPS64 */
> 
> +/* 0x1f is reserved */
>  POOL32C = 0x18,
>  LWGP16 = 0x19,
>  LW16 = 0x1a,
> @@ -10278,7 +10289,6 @@ enum {
>  XORI32 = 0x1c,
>  JALS32 = 0x1d,
>  ADDIUPC = 0x1e,
> -POOL48A = 0x1f,
> 
>  /* 0x20 is reserved */
>  RES_20 = 0x20,
> @@ -10307,8 +10317,8 @@ enum {
>  B16 = 0x33,
>  ANDI32 = 0x34,
>  J32 = 0x35,
> -SD32 = 0x36,
> -LD32 = 0x37,
> +SD32 = 0x36, /* MIPS64 */
> +LD32 = 0x37, /* MIPS64 */
> 
>  /* 0x38 and 0x39 are reserved */
>  RES_38 = 0x38,
> --
> 1.7.12.3

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH v2] target-mips: Add comments on POOL32Axf encoding

[Johnson, Eric]

> -Original Message-
> From: 陳韋任 (Wei-Ren Chen) [mailto:che...@iis.sinica.edu.tw]
> Sent: Tuesday, November 20, 2012 9:51 PM
> To: qemu-devel@nongnu.org
> Cc: Johnson, Eric; Aurelien Jarno; Jia Liu
> Subject: [PATCH v2] target-mips: Add comments on POOL32Axf encoding
> 
>   Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
> and microMIPS32 DSP. Add comment here to help reading.
> 
> Signed-off-by: Chen Wei-Ren 
> ---
> 
> v2: Correct commit message formatting
> 
>  target-mips/translate.c | 17 +
>  1 file changed, 17 insertions(+)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 8b438f8..e453d9e 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10359,6 +10359,19 @@ enum {
> 
>  /* POOL32AXF encoding of minor opcode field extension */
> 
> +/*
> + * 1. MIPS Architecture for Programmers Volume II-B:
> + *  The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + *Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
> + *
> + * 2. MIPS Architecture for Programmers VolumeIV-e:
> + *  The MIPS DSP Application-Specific Extension
> + *to the microMIPS32 Architecture (Revision 2.34)
> + *
> + *Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
> + */
> +
>  enum {
>  /* bits 11..6 */
>  TEQ = 0x00,
> @@ -10371,6 +10384,8 @@ enum {
>  MFC0 = 0x03,
>  MTC0 = 0x0b,
> 
> +/* begin of microMIPS32 DSP */
> +
>  /* bits 13..12 for 0x01 */
>  MFHI_ACC = 0x0,
>  MFLO_ACC = 0x1,
> @@ -10387,6 +10402,8 @@ enum {
>  MULT_ACC = 0x0,
>  MULTU_ACC = 0x1,
> 
> +/* end of microMIPS32 DSP */
> +
>  /* bits 15..12 for 0x2c */
>  SEB = 0x2,
>  SEH = 0x3,
> --
> 1.7.12.3

Reviewed-by: Eric Johnson 

Re: [Qemu-devel] [PATCH v2] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

Hi Chen,

Again the format is incorrect.

Please review the "SubmittingPatches 1.12" link on the 
http://wiki.qemu.org/Contribute/SubmitAPatch page.

-Eric

> -Original Message-
> From: 陳韋任 (Wei-Ren Chen) [mailto:che...@iis.sinica.edu.tw]
> Sent: Thursday, November 15, 2012 6:06 PM
> To: qemu-devel@nongnu.org; qemu-triv...@nongnu.org
> Cc: Johnson, Eric; Jia Liu; Aurelien Jarno
> Subject: [PATCH v2] target-mips: Clean up microMIPS32 major opcode
> 
> Hi all,
> 
>   I check MIPS microMIPS manual [1], and found the major opcode might be
> wrong. I add a comment to explicitly indicate what manual I am refering
> to, and according that manual I remove microMIPS32 major opcodes 0x1f.
> As for others, like 0x16, 0x17, 0x36 and 0x37, they are for higher-order
> MIPS ISA level or new revision of this microMIPS architecture. Quote
> from Johnson, they are belong MIPS64 [2].
> 
>   Please review, thanks.
> 
> [1] http://www.mips.com/products/architectures/micromips/#specifications
> 
> MIPS Architecture for Programmers Volume II-B:
>   The microMIPS32 Instruction Set (Revision 3.05)
> 
> MD00582-2B-microMIPS-AFP-03.05.pdf
> 
> [2] http://www.mips.com/products/architectures/mips64/
> 
> MIPS Architecture For Programmers
>   Volume II-A: The MIPS64 Instruction Set
> 
> MD00087-2B-MIPS64BIS-AFP-03.51.pdf
> 
> Signed-off-by: Chen Wei-Ren 
> ---
>  target-mips/translate.c |   24 +---
>  1 files changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 01b48fa..1c0ff65 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10239,9 +10239,19 @@ static int decode_mips16_opc (CPUMIPSState *env,
> DisasContext *ctx,
>  return n_bytes;
>  }
> 
> -/* microMIPS extension to MIPS32 */
> +/* microMIPS extension to MIPS32/MIPS64 */
> 
> -/* microMIPS32 major opcodes */
> +/*
> + * microMIPS32/microMIPS64 major opcodes
> + *
> + *  1. MIPS Architecture for Programmers Volume II-B:
> + *   The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + * Table 6.2 microMIPS32 Encoding of Major Opcode Field
> + *
> + *  2. MIPS Architecture For Programmers Volume II-A:
> + *   The MIPS64 Instruction Set (Revision 3.51)
> + */
> 
>  enum {
>  POOL32A = 0x00,
> @@ -10268,9 +10278,10 @@ enum {
>  POOL16D = 0x13,
>  ORI32 = 0x14,
>  POOL32F = 0x15,
> -POOL32S = 0x16,
> -DADDIU32 = 0x17,
> +POOL32S = 0x16,  /* MIPS64 */
> +DADDIU32 = 0x17, /* MIPS64 */
> 
> +/* 0x1f is reserved */
>  POOL32C = 0x18,
>  LWGP16 = 0x19,
>  LW16 = 0x1a,
> @@ -10278,7 +10289,6 @@ enum {
>  XORI32 = 0x1c,
>  JALS32 = 0x1d,
>  ADDIUPC = 0x1e,
> -POOL48A = 0x1f,
> 
>  /* 0x20 is reserved */
>  RES_20 = 0x20,
> @@ -10307,8 +10317,8 @@ enum {
>  B16 = 0x33,
>  ANDI32 = 0x34,
>  J32 = 0x35,
> -SD32 = 0x36,
> -LD32 = 0x37,
> +SD32 = 0x36, /* MIPS64 */
> +LD32 = 0x37, /* MPIS64 */
> 
>  /* 0x38 and 0x39 are reserved */
>  RES_38 = 0x38,
> --
> 1.7.3.4

Re: [Qemu-devel] [PATCH] target-mips: Add comments on POOL32Axf encoding

[Johnson, Eric]

Hi Chen,

The contents of the patch are OK.

The formatting of the message is incorrect.  Anything before the first '---' 
will be used as the comment for the commit.  It should not have "Hi all," 
"Please review, thanks.  Regards, checnwj"

If you want to include these additional comments, put them after the first 
'---' and before changed file summary.

> ---
[Additional comments here]
>  target-mips/translate.c |   17 +

Please review the "SubmittingPatches 1.12" link on the 
http://wiki.qemu.org/Contribute/SubmitAPatch page.

-Eric

> -Original Message-
> From: 陳韋任 (Wei-Ren Chen) [mailto:che...@iis.sinica.edu.tw]
> Sent: Thursday, November 15, 2012 6:30 PM
> To: qemu-devel@nongnu.org; qemu-triv...@nongnu.org
> Cc: Johnson, Eric; Aurelien Jarno; Jia Liu
> Subject: [PATCH] target-mips: Add comments on POOL32Axf encoding
> 
> Hi all,
> 
>   Current QEMU MIPS POOL32AXF encoding comes from microMIPS32
> and microMIPS32 DSP. Add comment here to help reading.
> 
>   Please review, thanks.
> 
> Regards,
> chenwj
> 
> Signed-off-by: Chen Wei-Ren 
> ---
>  target-mips/translate.c |   17 +
>  1 files changed, 17 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 01b48fa..9d4b2c3 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10359,6 +10359,19 @@ enum {
> 
>  /* POOL32AXF encoding of minor opcode field extension */
> 
> +/*
> + *  1. MIPS Architecture for Programmers Volume II-B:
> + *   The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + * Table 6.5 POOL32Axf Encoding of Minor Opcode Extension Field
> + *
> + *  2. MIPS Architecture for Programmers VolumeIV-e:
> + *   The MIPS DSP Application-Specific Extension
> + * to the microMIPS32 Architecture (Revision 2.34)
> + *
> + * Table 5.5 POOL32Axf Encoding of Minor Opcode Extension Field
> + */
> +
>  enum {
>  /* bits 11..6 */
>  TEQ = 0x00,
> @@ -10371,6 +10384,8 @@ enum {
>  MFC0 = 0x03,
>  MTC0 = 0x0b,
> 
> +/* begin of microMIPS32 DSP */
> +
>  /* bits 13..12 for 0x01 */
>  MFHI_ACC = 0x0,
>  MFLO_ACC = 0x1,
> @@ -10387,6 +10402,8 @@ enum {
>  MULT_ACC = 0x0,
>  MULTU_ACC = 0x1,
> 
> +/* end of microMIPS32 DSP */
> +
>  /* bits 15..12 for 0x2c */
>  SEB = 0x2,
>  SEH = 0x3,
> --
> 1.7.3.4

Re: [Qemu-devel] Question about comment on MIPS POOL32AXF encoding

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of ??? (Wei-Ren Chen)
> Sent: Thursday, November 15, 2012 1:03 AM
> To: qemu-devel@nongnu.org
> Cc: Jia Liu
> Subject: [Qemu-devel] Question about comment on MIPS POOL32AXF encoding
> 
> Hi all,
> 
>   I am reading POOL32AXF encoding in target-mips/translate.c,
> and can't understand what the comment says. For example,
> 
> /* bits 13..12 for 0x01 */
> MFHI_ACC = 0x0,
> MFLO_ACC = 0x1,
> MTHI_ACC = 0x2,
> MTLO_ACC = 0x3,
> 
> I compare this with microMIPS32 manual [1] Table 6.5, but I still
> don't understand why they're encoded in such way. The comment says
> "bits 13..12 for 0x01", I can roughly understand the enum list
> bits 13..12 here, but what "for 0x01" exactly means?

Please refer to the following document.

MIPS® Architecture for Programmers VolumeIV-e: The MIPS® DSP 
Application-Specific Extension to the microMIPS32™ Architecture

http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00764-2B-microMIPS32DSP-AFP-02.34.pdf

-Eric

Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

> -Original Message-
> From: 陳韋任 (Wei-Ren Chen) [mailto:che...@iis.sinica.edu.tw]
> Sent: Wednesday, November 14, 2012 9:51 PM
> To: Johnson, Eric
> Cc: qemu-devel@nongnu.org; qemu-triv...@nongnu.org; Jia Liu; Aurelien
> Jarno
> Subject: Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major
> opcode
> 
> On Thu, Nov 15, 2012 at 04:01:32AM +, Johnson, Eric wrote:
> > Hi Chen,
> >
> > Sorry I must have made a copy paste error.  I access the documents
> internally. I'll double check the link tomorrow.
> >
> > The document I referenced is the MIPS64 not the microMIPS64.
> >
> > Do not change the names. The LD32 and SD32 are microMIPS specific. The
> assembler LD and SD opcodes work for either MIPS64 or microMIPS64.
> 
>   O.K., thanks for the help. :)
> 
>   How about DADDIU32, should I keep the 32 suffix, too?
> I still can't find where POOL32S is.
> 
> Regards,
> chenwj

The only opcode on the list that is incorrect is the POOL48A opcode.  It should 
be removed.  If the others are removed or renamed, I or someone else would just 
have to fix them at some point in the future.

It seems the microMIPS64 Instruction Set manual is not one the external 
website.  I'll ask about that.

-Eric

Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

> -Original Message-
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> Sent: Thursday, November 15, 2012 6:04 AM
> To: Johnson, Eric
> Cc: 陳韋任 (Wei-Ren Chen); qemu-devel@nongnu.org; qemu-triv...@nongnu.org;
> che...@cs.nctu.edu.tw; Jia Liu
> Subject: Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major
> opcode
> 
> On Thu, Nov 15, 2012 at 02:34:31AM +, Johnson, Eric wrote:
> > Hi Chen,
> >
> > Please only remove the POOL48A opcode.
> >
> > The others are documented in the microMIPS64 Instruction Set manual (
> http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00087-
> 2B-MIPS64BIS-AFP-03.51.pdf ).  See
> http://www.mips.com/products/architectures/mips64/ for other relavent
> docs.
> >
> > Instead of removing them please surround the POOL32S, DADDIU32, SD32,
> and LD32 opcodes with
> > #if defined(TARGET_MIPS64)
> >
> 
> I don't think a #if is necessary there, this makes the code more
> difficult to read, while it doesn't change anything on the generated
> code.

Agreed.

-Eric

Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

Hi Chen,

Sorry I must have made a copy paste error.  I access the documents internally. 
I'll double check the link tomorrow.

The document I referenced is the MIPS64 not the microMIPS64.

Do not change the names. The LD32 and SD32 are microMIPS specific. The 
assembler LD and SD opcodes work for either MIPS64 or microMIPS64.

Eric

On Nov 14, 2012, at 7:27 PM, "陳韋任 (Wei-Ren Chen)"  
wrote:

> On Thu, Nov 15, 2012 at 02:34:31AM +0000, Johnson, Eric wrote:
>> Hi Chen,
>> 
>> Please only remove the POOL48A opcode.
>> 
>> The others are documented in the microMIPS64 Instruction Set manual ( 
>> http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00087-2B-MIPS64BIS-AFP-03.51.pdf
>>  ).  See http://www.mips.com/products/architectures/mips64/ for other 
>> relavent docs.
>> 
>> Instead of removing them please surround the POOL32S, DADDIU32, SD32, and 
>> LD32 opcodes with
>> #if defined(TARGET_MIPS64)
> 
>  Just want to make sure I am reading the right manual, are you refering
> to [1] or [2]? The link you gave me is about MIPS64 not microMIPS64, I 
> am not sure which one I should look into. I can find DADDIU, SD, and LD
> in [1] and [2], all *without* 32 suffix. Should I change their name?
> I cannot find POOL32S in both document, would you like to point it out?
> Thanks.
> 
> Regards,
> chenwj
> 
> [1] MIPS Architecture For Programmers
>  Volume I-B: Introduction to the microMIPS64 Architecture
> 
>MD00743-2B-microMIPS64INT-AFP-03.02.pdf
> 
> [2] MIPS Architecture For Programmers
>  Volume II-A: The MIPS64 Instruction Set
> 
>MD00087-2B-MIPS64BIS-AFP-03.51.pdf
> 
> -- 
> Wei-Ren Chen (陳韋任)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> Homepage: http://people.cs.nctu.edu.tw/~chenwj

Re: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major opcode

[Johnson, Eric]

Hi Chen,

Please only remove the POOL48A opcode.

The others are documented in the microMIPS64 Instruction Set manual ( 
http://www.mips.com/secure-download/index.dot?product_name=/auth/MD00087-2B-MIPS64BIS-AFP-03.51.pdf
 ).  See http://www.mips.com/products/architectures/mips64/ for other relavent 
docs.

Instead of removing them please surround the POOL32S, DADDIU32, SD32, and LD32 
opcodes with
#if defined(TARGET_MIPS64)

-Eric

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of ??? (Wei-Ren Chen)
> Sent: Wednesday, November 14, 2012 6:15 PM
> To: qemu-devel@nongnu.org; qemu-triv...@nongnu.org
> Cc: che...@cs.nctu.edu.tw; Jia Liu; Aurelien Jarno
> Subject: [Qemu-devel] [PATCH] target-mips: Clean up microMIPS32 major
> opcode
> 
> Hi all,
> 
>   I check MIPS microMIPS manual [1], and found the major opcode might be
> wrong. I add a comment to explicitly indicate what manual I am refering
> to, and according that manual I remove some microMIPS32 major opcodes.
> Major opcode 0x1f is reserved, so I just remove it. As for others, like
> 0x16, 0x17, 0x36 and 0x37, they are for higher-order MIPS ISA level or
> new revision of this microMIPS architecture. Since they are not appear
> in the manual I refer to, I just remove them as well.
> 
>   Please review, thanks.
> 
> [1] http://www.mips.com/products/architectures/micromips/#specifications
> 
> MIPS Architecture for Programmers Volume II-B:
>   The microMIPS32 Instruction Set (Revision 3.05)
> 
> MD00582-2B-microMIPS-AFP-03.05.pdf
> 
> Signed-off-by: Chen Wei-Ren 
> ---
>  target-mips/translate.c |   16 ++--
>  1 files changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index f6fc0c2..b57da24 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -10241,7 +10241,15 @@ static int decode_mips16_opc (CPUMIPSState *env,
> DisasContext *ctx,
> 
>  /* microMIPS extension to MIPS32 */
> 
> -/* microMIPS32 major opcodes */
> +/*
> + * microMIPS32 major opcodes
> + *
> + * MIPS Architecture for Programmers Volume II-B:
> + *   The microMIPS32 Instruction Set (Revision 3.05)
> + *
> + * Table 6.2 microMIPS32 Encoding of Major Opcode Field
> + *
> + */
> 
>  enum {
>  POOL32A = 0x00,
> @@ -10268,9 +10276,8 @@ enum {
>  POOL16D = 0x13,
>  ORI32 = 0x14,
>  POOL32F = 0x15,
> -POOL32S = 0x16,
> -DADDIU32 = 0x17,
> 
> +/* 0x1f is reserved */
>  POOL32C = 0x18,
>  LWGP16 = 0x19,
>  LW16 = 0x1a,
> @@ -10278,7 +10285,6 @@ enum {
>  XORI32 = 0x1c,
>  JALS32 = 0x1d,
>  ADDIUPC = 0x1e,
> -POOL48A = 0x1f,
> 
>  /* 0x20 is reserved */
>  RES_20 = 0x20,
> @@ -10307,8 +10313,6 @@ enum {
>  B16 = 0x33,
>  ANDI32 = 0x34,
>  J32 = 0x35,
> -SD32 = 0x36,
> -LD32 = 0x37,
> 
>  /* 0x38 and 0x39 are reserved */
>  RES_38 = 0x38,
> --
> 1.7.3.4

Re: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Wednesday, November 14, 2012 6:38 AM
> To: qemu-devel@nongnu.org
> Cc: Aurelien Jarno
> Subject: [Qemu-devel] [PATCH] mips/malta: fix CBUS UART interrupt pin
> 
> According to the MIPS Malta Developement Platform User's Manual, the
> i8259 interrupt controller is supposed to be connected to the hardware
> IRQ0, and the CBUS UART to the hardware interrupt 2.
> 
> In QEMU they are both connected to hardware interrupt 0, the CBUS UART
> interrupt being wrong. This patch fixes that. It should be noted that
> the irq array in QEMU includes the software interrupts, hence
> env->irq[2] is the first hardware interrupt.
> 
> Cc: Ralf Baechle 
> Signed-off-by: Aurelien Jarno 
> ---
>  hw/mips_malta.c |3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/mips_malta.c b/hw/mips_malta.c
> index 0571d58..4d2464a 100644
> --- a/hw/mips_malta.c
> +++ b/hw/mips_malta.c
> @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args)
>  be = 0;
>  #endif
>  /* FPGA */
> -malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2],
> serial_hds[2]);
> +/* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4
> */
> +malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4],
> serial_hds[2]);
> 
>  /* Load firmware in flash / BIOS. */
>  dinfo = drive_get(IF_PFLASH, 0, fl_idx);
> --
> 1.7.10.4
> 

I double checked with a Malta expert here.  He verified that the CBUS UART is 
connected to the HW2 interrupt pin.

Reviewed-by: Eric Johnson 

-Eric

Re: [Qemu-devel] [PATCH 5/6] pixman: build internal version early

[Johnson, Eric]

> -Original Message-
> From: Gerd Hoffmann [mailto:kra...@redhat.com]
> Sent: Wednesday, November 14, 2012 4:42 AM
[...]
> On 11/13/12 19:41, Johnson, Eric wrote:
[...]
> > I wasn't sure how to submit a patch to an unsubmitted patch.
> 
> As usual: "git commit -s" + "git format-patch" + "git send-email",
> especially as this one stands on its own and has no dependency on the
> unsubmitted patch, but it is fine for incremental fixes too.

Thanks.

I found portability issues with my simple sed replacement that I could not 
resolve to my satisfaction.  The patch you made to deal with \$(BUILD_DIR) and 
\$(SRC_PATH) is cleaner and simpler anyway.

-Eric

Re: [Qemu-devel] [PATCH 5/6] pixman: build internal version early

[Johnson, Eric]

It's OK to add.
Signed-off-by: Eric Johnson 

I wasn't sure how to submit a patch to an unsubmitted patch.  I haven't had a 
chance to review the patch submission doc to see if that is covered.  It would 
still be useful info.  I intend to recreate and supply my local sed replacement 
of $(BUILD_DIR) and $(SRC_PATH) in $(QEMU_CFLAGS) patch to configure for patch 
1 in this series to address Stefan's feedback.  I had done that patch locally 
prior to noticing Blue's and Gerd's patches on the list.  And discarded since 
trying Gerd's patch.  It is trivial to recreate.
 
-Eric

> -Original Message-
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> Sent: Tuesday, November 13, 2012 10:30 AM
> To: Gerd Hoffmann
> Cc: qemu-devel@nongnu.org; Johnson, Eric
> Subject: Re: [Qemu-devel] [PATCH 5/6] pixman: build internal version early
> 
> On 13 November 2012 08:42, Gerd Hoffmann  wrote:
> > Patch by Eric Johnson.
> >
> > Signed-off-by: Gerd Hoffmann 
> 
> Does this need a Signed-off-by: from Eric? It's a pretty
> trivial patch but I guess it would be nice...
> 
> thanks
> -- PMM
> 
> > ---
> >  configure |7 ---
> >  1 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/configure b/configure
> > index e7ca78b..fb5f002 100755
> > --- a/configure
> > +++ b/configure
> > @@ -3953,9 +3953,6 @@ if test "$target_softmmu" = "yes" ; then
> >if test "$smartcard_nss" = "yes" ; then
> >  echo "subdir-$target: subdir-libcacard" >> $config_host_mak
> >fi
> > -  if test "$pixman" = "internal" ; then
> > -echo "subdir-$target: subdir-pixman" >> $config_host_mak
> > -  fi
> >case "$target_arch2" in
> >  i386|x86_64)
> >echo "CONFIG_HAVE_CORE_DUMP=y" >> $config_target_mak
> > @@ -4153,6 +4150,10 @@ echo "QEMU_INCLUDES+=$includes" >>
> $config_target_mak
> >
> >  done # for target in $targets
> >
> > +if [ "$pixman" = "internal" ]; then
> > +  echo "config-host.h: subdir-pixman" >> $config_host_mak
> > +fi
> > +
> >  # build tree in object directory in case the source is not in the
> current directory
> >  DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
> >  DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas"
> > --
> > 1.7.1
> >
> >

Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds for pixman

[Johnson, Eric]

Sorry, I didn’t let the make finish but I think there will be linking errors 
with the previous because libpixman-1.a may not be built.

The following changes to Gerd's rebase/pixman branch will completely build 
(except s390x).
On RHEL 5.7 (no pixman on system):
$ ../kraxel.org/configure --without-system-pixman
$ make -k -j8

diff --git a/configure b/configure
index f0bc726..d946937 100755
--- a/configure
+++ b/configure
@@ -3955,9 +3955,6 @@ if test "$target_softmmu" = "yes" ; then
   if test "$smartcard_nss" = "yes" ; then
 echo "subdir-$target: subdir-libcacard" >> $config_host_mak
   fi
-  if test "$pixman" = "internal" ; then
-echo "subdir-$target: subdir-pixman" >> $config_host_mak
-  fi
   case "$target_arch2" in
 i386|x86_64)
   echo "CONFIG_HAVE_CORE_DUMP=y" >> $config_target_mak
@@ -4154,6 +4151,10 @@ echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak
 echo "QEMU_INCLUDES+=$includes" >> $config_target_mak

 done # for target in $targets
+ 
+if [ "$pixman" = "internal" ]; then
+  echo "config-host.h: subdir-pixman" >> $config_host_mak
+fi

 # build tree in object directory in case the source is not in the current 
directory
 DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"

cc1: warnings being treated as errors
/home/ericj/work/qemu/kraxel.org/hw/s390x/event-facility.c: In function 
'command_handler':
/home/ericj/work/qemu/kraxel.org/hw/s390x/event-facility.c:110: warning: 'rc' 
may be used uninitialized in this function
make[1]: *** [hw/s390x/event-facility.o] Error 1

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Johnson, Eric
> Sent: Wednesday, November 07, 2012 12:07 PM
> To: Gerd Hoffmann; Blue Swirl
> Cc: Peter Maydell; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds
> for pixman
> 
> This may not be the prettiest fix for the pixman dependency but it seems
> to work.
> 
> diff --git a/configure b/configure
> index f0bc726..fcb744e 100755
> --- a/configure
> +++ b/configure
> @@ -4154,6 +4154,10 @@ echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak
>  echo "QEMU_INCLUDES+=$includes" >> $config_target_mak
> 
>  done # for target in $targets
> +
> +if [ "$pixman" = "internal" ]; then
> +  echo "config-host.h: pixman/Makefile" >> $config_host_mak
> +fi
> 
>  # build tree in object directory in case the source is not in the current
> directory
>  DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"
> 
> > -Original Message-
> > From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> > bounces+ericj=mips@nongnu.org] On Behalf Of Gerd Hoffmann
> > Sent: Wednesday, November 07, 2012 3:43 AM
> > To: Blue Swirl
> > Cc: Peter Maydell; qemu-devel@nongnu.org
> > Subject: Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile
> builds
> > for pixman
> >
> > On 11/03/12 21:15, Blue Swirl wrote:
> > > On Sat, Nov 3, 2012 at 7:02 PM, Peter Maydell
> 
> > wrote:
> > >> On 3 November 2012 19:47, Blue Swirl  wrote:
> > >>> --- a/Makefile
> > >>> +++ b/Makefile
> > >>> @@ -122,7 +122,7 @@ subdir-pixman: pixman/Makefile
> > >>> $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C pixman
> > V="$(V)" all,)
> > >>>
> > >>>  pixman/Makefile: $(SRC_PATH)/pixman/configure
> > >>> -   (cd pixman; $(SRC_PATH)/pixman/configure --disable-shared --
> > enable-static)
> > >>> +   (cd pixman; CC=$(CC) LD=$(LD) AR=$(AR) NM=$(NM)
> > RANLIB=$(RANLIB) $(SRC_PATH)/pixman/configure --disable-shared --enable-
> > static)
> > >>
> > >> Not tested, but aren't there quoting issues here if you're
> > >> building with --cc='ccache gcc' ?
> > >
> > > Yes. Also configure fails because the variables are not expanded and
> > > directory pixman/pixman does not exist. Funny how it worked earlier.
> >
> > Turned out part of the issue is that having pixman-devel installed
> > masked some of the build issues of the internal pixman even when
> > building --without-pixman-system, so my build testing was incomplete.
> >
> > Pushed test branch:
> >   git://git.kraxel.org/qemu rebase/pixman
> >
> > Dependency issue isn't tackled yet, but non-parallel builds are working
> > fine for me.  Feedback is welcome.
> >
> > cheers,
> >   Gerd
> >

Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds for pixman

[Johnson, Eric]

This may not be the prettiest fix for the pixman dependency but it seems to 
work.

diff --git a/configure b/configure
index f0bc726..fcb744e 100755
--- a/configure
+++ b/configure
@@ -4154,6 +4154,10 @@ echo "QEMU_CFLAGS+=$cflags" >> $config_target_mak
 echo "QEMU_INCLUDES+=$includes" >> $config_target_mak
 
 done # for target in $targets
+ 
+if [ "$pixman" = "internal" ]; then
+  echo "config-host.h: pixman/Makefile" >> $config_host_mak
+fi
 
 # build tree in object directory in case the source is not in the current 
directory
 DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32"

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Gerd Hoffmann
> Sent: Wednesday, November 07, 2012 3:43 AM
> To: Blue Swirl
> Cc: Peter Maydell; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds
> for pixman
> 
> On 11/03/12 21:15, Blue Swirl wrote:
> > On Sat, Nov 3, 2012 at 7:02 PM, Peter Maydell 
> wrote:
> >> On 3 November 2012 19:47, Blue Swirl  wrote:
> >>> --- a/Makefile
> >>> +++ b/Makefile
> >>> @@ -122,7 +122,7 @@ subdir-pixman: pixman/Makefile
> >>> $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C pixman
> V="$(V)" all,)
> >>>
> >>>  pixman/Makefile: $(SRC_PATH)/pixman/configure
> >>> -   (cd pixman; $(SRC_PATH)/pixman/configure --disable-shared --
> enable-static)
> >>> +   (cd pixman; CC=$(CC) LD=$(LD) AR=$(AR) NM=$(NM)
> RANLIB=$(RANLIB) $(SRC_PATH)/pixman/configure --disable-shared --enable-
> static)
> >>
> >> Not tested, but aren't there quoting issues here if you're
> >> building with --cc='ccache gcc' ?
> >
> > Yes. Also configure fails because the variables are not expanded and
> > directory pixman/pixman does not exist. Funny how it worked earlier.
> 
> Turned out part of the issue is that having pixman-devel installed
> masked some of the build issues of the internal pixman even when
> building --without-pixman-system, so my build testing was incomplete.
> 
> Pushed test branch:
>   git://git.kraxel.org/qemu rebase/pixman
> 
> Dependency issue isn't tackled yet, but non-parallel builds are working
> fine for me.  Feedback is welcome.
> 
> cheers,
>   Gerd
> 

Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds for pixman

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Stefan Weil
> Sent: Sunday, November 04, 2012 4:11 AM
> To: Blue Swirl
> Cc: Peter Maydell; qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH] Fix out-of-tree and cross compile builds
> for pixman
> 
> Am 03.11.2012 21:15, schrieb Blue Swirl:
> > On Sat, Nov 3, 2012 at 7:02 PM, Peter Maydell 
> wrote:
> >> On 3 November 2012 19:47, Blue Swirl  wrote:
> >>> --- a/Makefile
> >>> +++ b/Makefile
> >>> @@ -122,7 +122,7 @@ subdir-pixman: pixman/Makefile
> >>>  $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C pixman
> V="$(V)" all,)
> >>>
> >>>   pixman/Makefile: $(SRC_PATH)/pixman/configure
> >>> -   (cd pixman; $(SRC_PATH)/pixman/configure --disable-shared --
> enable-static)
> >>> +   (cd pixman; CC=$(CC) LD=$(LD) AR=$(AR) NM=$(NM)
> RANLIB=$(RANLIB) $(SRC_PATH)/pixman/configure --disable-shared --enable-
> static)
> >> Not tested, but aren't there quoting issues here if you're
> >> building with --cc='ccache gcc' ?
> > Yes. Also configure fails because the variables are not expanded and
> > directory pixman/pixman does not exist. Funny how it worked earlier.
> 
> I struggle with the same issue, and there are more problems caused
> by the internal pixman code.
> 
> The dependencies are wrong because pixman is built too late:
> $(TOOLS) also depends on it. It is not trivial to model them correctly.
> IMHO it would be better to build the internal pixman immediately when
> QEMU's configure is called. Then QEMU's make can always rely on an
> existing pixman.
> 
> The internal pixman code is also too old for cross compilations with
> MinGW-w64. It already fails when running configure.
> 
> Newer versions of pixman compile after a trivial modification which
> is needed to avoid redefined symbols:
> 
> diff --git a/pixman/pixman-mmx.c b/pixman/pixman-mmx.c
> index 1a014fd..723c245 100644
> --- a/pixman/pixman-mmx.c
> +++ b/pixman/pixman-mmx.c
> @@ -61,7 +61,7 @@ _mm_empty (void)
>   #endif
> 
>   #ifdef USE_X86_MMX
> -# if (defined(__SUNPRO_C) || defined(_MSC_VER))
> +# if (defined(__SUNPRO_C) || defined(_MSC_VER) || defined(__WIN64))
>   #  include 
>   # else
>   /* We have to compile with -msse to use xmmintrin.h, but that causes SSE
> 
> More changes are needed to avoid typical MinGW-w64 compiler warnings
> (pointer to int conversions without uintptr_t).
> 
> Up to now, I did not test the resulting code, so maybe there will be more
> surprises.
> 
> Regards
> Stefan
> 

I was able to get a parallel out-of-tree build to work with the following 
changes.  I'm not sure if it violates any rules about make features or 
configure processing.

Unless order only dependencies are not allowed the following should fix the 
build order for pixman and the tools.

diff --git a/Makefile b/Makefile
index ca14a21..42dcf92 100644
--- a/Makefile
+++ b/Makefile
@@ -118,6 +118,8 @@ endif
 
 subdir-libcacard: $(oslib-obj-y) $(trace-obj-y) qemu-timer-common.o
 
+$(TOOLS): | subdir-pixman
+
 subdir-pixman: pixman/Makefile
$(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C pixman V="$(V)" 
all,)

The following change does the internal pixman configuration during the QEMU 
configuration.

The upside is that the environment variables get passed to the sub-configure.  
Probably still need the Makefile fixes for CC="$(CC)", etc. just in case the 
pixman configuration dependencies are updated.

The down side is that \$(BUILD_DIR) and \$(SRC_PATH) cannot be used.  Instead I 
used `pwd` and ${source_path}.  Maybe with some more work the pixman 
configuration would work using the make variables.

diff --git a/configure b/configure
index 7290f50..97c7d15 100755
--- a/configure
+++ b/configure
@@ -2121,8 +2121,19 @@ else
 echo "  git submodule update --init pixman"
 exit 1
   fi
-  pixman_cflags="-I${source_path}/pixman/pixman"
-  pixman_libs="-Lpixman/pixman/.libs -lpixman-1"
+
+  if [ "$source_path" != `pwd` ]; then
+pixman_cflags="-I$source_path/pixman/pixman -I`pwd`/pixman/pixman"
+pixman_libs="-L`pwd`/pixman/pixman/.libs -lpixman-1"
+mkdir -p pixman
+  else
+pixman_cflags="-I$source_path/pixman/pixman"
+pixman_libs="-Lpixman/pixman/.libs -lpixman-1"
+  fi
+  if test ! -f ${source_path}/pixman/configure; then
+(cd ${source_path}/pixman; autoreconf -v --install)
+  fi
+  (cd pixman; ${source_path}/pixman/configure --disable-shared --enable-static)
 fi
 QEMU_CFLAGS="$QEMU_CFLAGS $pixman_cflags"
 libs_softmmu="$libs_softmmu $pixman_libs"

There are some dependencies issues that cause unneeded rebuilds and links but I 
think those exist despite these changes.

For example libcacard/cutils.d is being included for the top-level make but has 
relative dependencies ../config-host.h and ../qapi-types.h.  Those dependencies 
work when the PWD is $(BUILD_DIR)/libcacard but not at the top level 
$(BUILD_DIR).

The objects that are being

Re: [Qemu-devel] MIPS DSP for Qemu

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Peter Maydell
> Sent: Friday, October 05, 2012 8:07 AM
> To: Kotler, Reed
> Cc: Lau, David; Fuhler, Rich; Gilmore, Douglas; qemu-devel@nongnu.org; Jia
> Liu
> Subject: Re: [Qemu-devel] MIPS DSP for Qemu
> 
> On 3 October 2012 22:37, reed kotler  wrote:
> > A year and half ago, I did a complete implementation  for Mips DSP in
> Qemu.
> > My port has passed all the MIPS AVPs (Architectural Verification
> Programs)
> > for DSP, which is something not available to the public but is what all
> > architectural licenses and internal groups are required to pass.
> 
> > It was about to get finally pushed upstream and then this new port
> appeared.
> 
> ...you could have mentioned this back in March when Jia first sent
> his DSP related patches...

Reed only recently became aware of Jia's patches.  Reed's implementation had 
gone through a few rounds of cleanup based on feedback from a third party.  
That work was not completed.  There is still more cleanup that needs to be 
done.  Unfortunately the resources which might have worked on it were and still 
are involved in higher priority tasks.

At this point it probably makes sense to just address an issues with Jia's 
patches for the MIPS32 and MIPS64 architecture encodings.  microMIPS 
instruction encodings will need to be added.

> > I would like to still submit our patches .
> >
> > Please advise.
> 
> Well, if your patches are in what you believe to be a clean and
> ready-for-upstream state anyway, you might as well submit them to
> the mailing list so we can look at them. (you might want to read
> http://wiki.qemu.org/Contribute/SubmitAPatch if you haven't already.)
> 
> I also note that target-mips/ is currently in the "Odd Fixes"
> maintenance state -- is anybody at MIPS in a position to step
> up and help with bug fixing and patch review of that area?

MIPS has been considering several options to address the issue of a MIPS target 
maintainer for QEMU.

Since the topic has come up, what is the process for vetting a maintainer?

-Eric

Re: [Qemu-devel] [PATCH v10 14/14] target-mips-ase-dsp: Change TODO file

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Jia Liu
> Sent: Monday, October 08, 2012 1:51 AM
> To: qemu-devel@nongnu.org
> Cc: aurel...@aurel32.net
> Subject: [Qemu-devel] [PATCH v10 14/14] target-mips-ase-dsp: Change TODO
> file
> 
> Delete DSP r1 & DSP r2 from TODO file.
> 
> Signed-off-by: Jia Liu 
> ---
>  target-mips/TODO |2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/target-mips/TODO b/target-mips/TODO
> index 2a3546f..15d67cd 100644
> --- a/target-mips/TODO
> +++ b/target-mips/TODO
> @@ -6,8 +6,6 @@ General
>  - Unimplemented ASEs:
>- MDMX
>- SmartMIPS
> -  - DSP r1
> -  - DSP r2
>  - MT ASE only partially implemented and not functional
>  - Shadow register support only partially implemented,
>lacks set switching on interrupt/exception.
> --
> 1.7.10.2 (Apple Git-33)
> 

As I stated in a prior email, there are microMIPS instruction encodings for the 
DSP instructions.  Should we change this to "microMIPS DSP r1 & r2 encodings" 
instead of deleting?

-Eric

Re: [Qemu-devel] [PATCH v7 04/14] target-mips-ase-dsp: Add branch instructions

[Johnson, Eric]

> -Original Message-
> From: qemu-devel-bounces+ericj=mips@nongnu.org [mailto:qemu-devel-
> bounces+ericj=mips@nongnu.org] On Behalf Of Aurelien Jarno
> Sent: Thursday, September 06, 2012 2:11 AM
> To: Jia Liu
> Cc: qemu-devel@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH v7 04/14] target-mips-ase-dsp: Add branch
> instructions
> 
> On Tue, Aug 28, 2012 at 02:36:15PM +0800, Jia Liu wrote:
> > Add MIPS ASE DSP Branch instructions.
> >
> > Signed-off-by: Jia Liu 
> > ---
> >  target-mips/translate.c |   50
> +++
> >  1 file changed, 46 insertions(+), 4 deletions(-)
> >
> > diff --git a/target-mips/translate.c b/target-mips/translate.c
> > index e1ea9c1..18d827d 100644
> > --- a/target-mips/translate.c
> > +++ b/target-mips/translate.c
> > @@ -332,6 +332,14 @@ enum {
> >  OPC_DSHD = (0x05 << 6) | OPC_DBSHFL,
> >  };
> >
> > +/* MIPS DSP REGIMM opcodes */
> > +enum {
> > +OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM,
> > +#if defined(TARGET_MIPS64)
> > +OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM,
> > +#endif
> > +};
> > +
> >  /* Coprocessor 0 (rs field) */
> >  #define MASK_CP0(op)   MASK_OP_MAJOR(op) | (op & (0x1F << 21))
> >
> > @@ -2841,6 +2849,22 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
> >  }
> >  btgt = ctx->pc + insn_bytes + offset;
> >  break;
> > +case OPC_BPOSGE32:
> > +#if defined(TARGET_MIPS64)
> > +tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> > +#else
> > +tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
> > +#endif
> > +bcond_compute = 1;
> > +btgt = ctx->pc + insn_bytes + offset;
> > +break;
> > +#if defined(TARGET_MIPS64)
> > +case OPC_BPOSGE64:
> > +tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> > +bcond_compute = 1;
> > +btgt = ctx->pc + insn_bytes + offset;
> > +break;
> > +#endif
> 
> For this part of the code, BPOSGE32 is basically the same than BPOSGE64.
> Therefore this can be written the following way:
> 
> | case OPC_BPOSGE32:
> | #if defined(TARGET_MIPS64)
> | case OPC_BPOSGE64:
> | tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F);
> | #else
> | tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F);
> | #endif
> | bcond_compute = 1;
> | btgt = ctx->pc + insn_bytes + offset;
> | break;
> 
> >  case OPC_J:
> >  case OPC_JAL:
> >  case OPC_JALX:
> > @@ -3029,6 +3053,16 @@ static void gen_compute_branch (DisasContext *ctx,
> uint32_t opc,
> >  tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0);
> >  MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt);
> >  goto likely;
> > +case OPC_BPOSGE32:
> > +tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32);
> > +MIPS_DEBUG("bposge32 %s, " TARGET_FMT_lx, t0, btgt);
> > +goto not_likely;
> > +#if defined(TARGET_MIPS64)
> > +case OPC_BPOSGE64:
> > +tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64);
> > +MIPS_DEBUG("bposge64 %s, " TARGET_FMT_lx, t0, btgt);
> > +goto not_likely;
> > +#endif
> >  case OPC_BLTZALS:
> >  case OPC_BLTZAL:
> >  ctx->hflags |= (opc == OPC_BLTZALS
> > @@ -11284,10 +11318,6 @@ static void decode_micromips32_opc (CPUMIPSState
> *env, DisasContext *ctx,
> >  (ctx->opcode >> 18) & 0x7, imm << 1);
> >  *is_branch = 1;
> >  break;
> > -case BPOSGE64:
> > -case BPOSGE32:
> > -/* MIPS DSP: not implemented */
> > -/* Fall through */
> 
> I don't think this is correct. These are for microMIPS, and AFAIK, DSP
> ASE instructions can be encoded using microMIPS.

Yes, the MIPS DSP ASE instructions have microMIPS encodings.  They are 
available on the microAptiv processors.

> 
> >  default:
> >  MIPS_INVAL("pool32i");
> >  generate_exception(ctx, EXCP_RI);
> > @@ -12196,6 +12226,18 @@ static void decode_opc (CPUMIPSState *env,
> DisasContext *ctx, int *is_branch)
> >  check_insn(env, ctx, ISA_MIPS32R2);
> >  /* Treat as NOP. */
> >  break;
> > +case OPC_BPOSGE32:/* MIPS DSP branch */
> > +check_dsp(ctx);
> > +gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> > +*is_branch = 1;
> > +break;
> > +#if defined(TARGET_MIPS64)
> > +case OPC_BPOSGE64:
> > +check_dsp(ctx);
> > +gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> > +*is_branch = 1;
> > +break;
> > +#endif
> 
> Same here, this can be written
> 
> | case OPC_BPOSGE32:/* MIPS DSP branch */
> | #if defined(TARGET_MIPS64)
> | case OPC_BPOSGE64:
> | #endif
> | check_dsp(ctx);
> | gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2);
> | *is_branch = 1;
> |   

Re: [Qemu-devel] r4k doesn't support movz

[Johnson, Eric]

Hi Zhi-zhou Zhang,

You are correct.  This should not be a reserved instruction exception on MIPS64 
(nor should MOVN).

-Eric

From: qemu-devel-bounces+ericj=mips@nongnu.org 
[mailto:qemu-devel-bounces+ericj=mips@nongnu.org] On Behalf Of Zhi-zhou 
Zhang
Sent: Friday, May 18, 2012 4:39 AM
To: qemu-devel@nongnu.org
Cc: aurel...@aurel32.net
Subject: [Qemu-devel] r4k doesn't support movz

Hi Aurelien,

I found that when qemu-system-mips64el executed 'movz' with -M mips, it would 
raise a reserved instruction exception.
The mips spec describes movz as below:

Mnemonic   Instructio  Defined in MIPS ISA
MOVZMove Conditional on Zero   MIPS32

I think ISA-64 should support MIPS32 instructions for compatible. am I right?

--
Regards,
Zhizhou Zhang

Re: [Qemu-devel] [PATCH 09/15] target-mips: Clean includes

[Johnson, Eric]

You may want to just put those includes inside an '#ifdef MIPS_DEBUG_DISAS' 
instead of removing them.

Although I suppose we could just add back the minimum needed along with the 
patches to fix the compile when MIPS_DEBUG_DISAS is defined.

-Original Message-
From: qemu-devel-bounces+ericj=mips@nongnu.org 
[mailto:qemu-devel-bounces+ericj=mips@nongnu.org] On Behalf Of Stefan Weil
Sent: Tuesday, February 28, 2012 1:47 PM
To: Anthony Liguori
Cc: Stefan Weil; qemu-devel@nongnu.org; Aurelien Jarno
Subject: [Qemu-devel] [PATCH 09/15] target-mips: Clean includes

Remove some include statements which are not needed.

Cc: Aurelien Jarno 
Signed-off-by: Stefan Weil 
---
 target-mips/translate.c |7 ---
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c index 
d5b1c76..8361d88 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20,16 +20,9 @@
  * License along with this library; if not, see .
  */
 
-#include 
-#include 
-#include 
-#include 
-#include 
-
 #include "cpu.h"
 #include "disas.h"
 #include "tcg-op.h"
-#include "qemu-common.h"
 
 #include "helper.h"
 #define GEN_HELPER 1
--
1.7.9

Re: [Qemu-devel] [PATCH] Add privilege level check to several Cop0 instructions.

[Johnson, Eric]

The patch applies to a8467c7a0e8b024a18608ff7db31ca2f2297e641.

-Original Message-
From: qemu-devel-bounces+ericj=mips@nongnu.org 
[mailto:qemu-devel-bounces+ericj=mips@nongnu.org] On Behalf Of Eric Johnson
Sent: Saturday, September 17, 2011 5:06 PM
To: qemu-devel@nongnu.org; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH] Add privilege level check to several Cop0 
instructions.

The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level.  These changes are needed
to pass the AVP suite.

Signed-off-by: Eric Johnson 
---
 target-mips/translate.c |   10 ++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..d99a716 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5940,6 +5940,8 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, 
uint32_t opc, int rt, int
 {
 const char *opn = "ldst";
 
+check_cp0_enabled(ctx);
+
 switch (opc) {
 case OPC_MFC0:
 if (rt == 0) {
@@ -10125,6 +10127,7 @@ static void gen_pool32axf (CPUState *env, DisasContext 
*ctx, int rt, int rs,
 #ifndef CONFIG_USER_ONLY
 case MFC0:
 case MFC0 + 32:
+check_cp0_enabled(ctx);
 if (rt == 0) {
 /* Treat as NOP. */
 break;
@@ -10136,6 +10139,7 @@ static void gen_pool32axf (CPUState *env, DisasContext 
*ctx, int rt, int rs,
 {
 TCGv t0 = tcg_temp_new();
 
+check_cp0_enabled(ctx);
 gen_load_gpr(t0, rt);
 gen_mtc0(env, ctx, t0, rs, (ctx->opcode >> 11) & 0x7);
 tcg_temp_free(t0);
@@ -10230,10 +10234,12 @@ static void gen_pool32axf (CPUState *env, 
DisasContext *ctx, int rt, int rs,
 switch (minor) {
 case RDPGPR:
 check_insn(env, ctx, ISA_MIPS32R2);
+check_cp0_enabled(ctx);
 gen_load_srsgpr(rt, rs);
 break;
 case WRPGPR:
 check_insn(env, ctx, ISA_MIPS32R2);
+check_cp0_enabled(ctx);
 gen_store_srsgpr(rt, rs);
 break;
 default:
@@ -10276,6 +10282,7 @@ static void gen_pool32axf (CPUState *env, DisasContext 
*ctx, int rt, int rs,
 {
 TCGv t0 = tcg_temp_new();
 
+check_cp0_enabled(ctx);
 save_cpu_state(ctx, 1);
 gen_helper_di(t0);
 gen_store_gpr(t0, rs);
@@ -10288,6 +10295,7 @@ static void gen_pool32axf (CPUState *env, DisasContext 
*ctx, int rt, int rs,
 {
 TCGv t0 = tcg_temp_new();
 
+check_cp0_enabled(ctx);
 save_cpu_state(ctx, 1);
 gen_helper_ei(t0);
 gen_store_gpr(t0, rs);
@@ -10765,6 +10773,7 @@ static void decode_micromips32_opc (CPUState *env, 
DisasContext *ctx,
 minor = (ctx->opcode >> 12) & 0xf;
 switch (minor) {
 case CACHE:
+check_cp0_enabled(ctx);
 /* Treat as no-op. */
 break;
 case LWC2:
@@ -12216,6 +12225,7 @@ static void decode_opc (CPUState *env, DisasContext 
*ctx, int *is_branch)
  break;
 case OPC_CACHE:
 check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32);
+check_cp0_enabled(ctx);
 /* Treat as NOP. */
 break;
 case OPC_PREF: