subject:"\[Qemu\-devel\] \[PATCH v5 00\/35\] target\/riscv\: Convert to decodetree"

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-02-01 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
1271fb3 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e577171 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b38 target/riscv: Convert @cs_2 insns to share translation functions
ae50456 target/riscv: Remove decode_RV32_64G()
689db53 target/riscv: Remove gen_system()
ba19bbe target/riscv: Rename trans_arith to gen_arith
4821480 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b target/riscv: Remove shift and slt insn manual decoding
b24202e target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8 target/riscv: Remove manual decoding from gen_store()
2717536 target/riscv: Remove manual decoding from gen_load()
ce1206d target/riscv: Remove manual decoding from gen_branch()
35a81db target/riscv: Remove gen_jalr()
8d3033d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f939 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c6 target/riscv: Convert RV priv insns to decodetree
801dbbd target/riscv: Convert RV64D insns to decodetree
5669654 target/riscv: Convert RV32D insns to decodetree
e2646f4 target/riscv: Convert RV64F insns to decodetree
188a6e6 target/riscv: Convert RV32F insns to decodetree
c39a5a5 target/riscv: Convert RV64A insns to decodetree
74169b8 target/riscv: Convert RV32A insns to decodetree
f0db8bc target/riscv: Convert RVXM insns to decodetree
2db8b9a target/riscv: Convert RVXI csr insns to decodetree
abf36db target/riscv: Convert RVXI fence insns to decodetree
437709e target/riscv: Convert RVXI arithmetic insns to decodetree
201f108 target/riscv: Convert RV64I load/store insns to decodetree
7c6f475 target/riscv: Convert RV32I load/store insns to decodetree
9e5332d target/riscv: Convert RVXI branch insns to decodetree
dc69d0a target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e4978 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 74169b8e3825 (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
 * [new tag] patchew/20190131210851.9842-1-richard.hender...@linaro.org 
-> patchew/20190131210851.9842-1-richard.hender...@linaro.org
Switched to a new branch 'test'
8fbe349 target/riscv: Remaining rvc insn reuse 32 bit translators
24ac6df target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
a872fb0 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
b15e98a target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
8620f8c target/riscv: Convert @cs_2 insns to share translation functions
34fdff0 target/riscv: Remove decode_RV32_64G()
18fef41 target/riscv: Remove gen_system()
0c7096a target/riscv: Rename trans_arith to gen_arith
11b4396 target/riscv: Remove manual decoding of RV32/64M insn
03ea617 target/riscv: Remove shift and slt insn manual decoding
b9d345c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f9f6281 target/riscv: Move gen_arith_imm() decoding into trans_* functions
28988be target/riscv: Remove manual decoding from gen_store()
b227163 target/riscv: Remove manual decoding from gen_load()
2d9466d target/riscv: Remove manual decoding from gen_branch()
389dfb1 target/riscv: Remove gen_jalr()
015e21b target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f7599be target/riscv: Convert quadrant 1 of RVXC insns to decodetree
b43b908 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
9def3a0 target/riscv: Convert RV priv insns to decodetree
cb6a85c target/riscv: Convert RV64D insns to decodetree
de12358 target/riscv: Convert RV32D insns to decodetree
3637746 target/riscv: Convert RV64F insns to decodetree
f7f1cee target/riscv: Convert RV32F insns to decodetree
ff48f82 target/riscv: Convert RV64A insns to decodetree
59216b4 target/riscv: Convert RV32A insns to decodetree
ecd3e26 target/riscv: Convert RVXM insns to decodetree
f925ddf target/riscv: Convert RVXI csr insns to decodetree
0521076 target/riscv: Convert RVXI fence insns to decodetree
96ef5df target/riscv: Convert RVXI arithmetic insns to decodetree
720d36f target/riscv: Convert RV64I load/store insns to decodetree
4ca2a53 target/riscv: Convert RV32I load/store insns to decodetree
797e17e target/riscv: Convert RVXI branch insns to decodetree
5fe471c target/riscv: Activate decodetree and implemnt LUI & AUIPC
2f6484f target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2f6484fc8b40 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 5fe471c8d889 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 797e17e309d8 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 4ca2a533ae0f (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 720d36fcb482 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 96ef5df64035 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 052107679d38 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit f925ddff48df (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit ecd3e263f4d3 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are f

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   aefcd28366..e8977901b7  master -> master
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
84d9232271 target/riscv: Remaining rvc insn reuse 32 bit translators
d914ca8ad6 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
d91d36a5a5 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
96a7dd7cc4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
4be75db113 target/riscv: Convert @cs_2 insns to share translation functions
5df6fa908b target/riscv: Remove decode_RV32_64G()
9e15d220cb target/riscv: Remove gen_system()
569b624066 target/riscv: Rename trans_arith to gen_arith
ab8fe35848 target/riscv: Remove manual decoding of RV32/64M insn
35c8b7cf65 target/riscv: Remove shift and slt insn manual decoding
aa1fcbc0b2 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
09af9d97eb target/riscv: Move gen_arith_imm() decoding into trans_* functions
2b6c72f3da target/riscv: Remove manual decoding from gen_store()
1d3a7b5cb7 target/riscv: Remove manual decoding from gen_load()
0551b57210 target/riscv: Remove manual decoding from gen_branch()
129eb0e041 target/riscv: Remove gen_jalr()
65a653d84d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
faca63ff69 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
0e9ac5bbcb target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8871e9f09a target/riscv: Convert RV priv insns to decodetree
4ffcac38e7 target/riscv: Convert RV64D insns to decodetree
8b13dafd4a target/riscv: Convert RV32D insns to decodetree
f59e9b8655 target/riscv: Convert RV64F insns to decodetree
8cd874a0eb target/riscv: Convert RV32F insns to decodetree
4f9f53aa9e target/riscv: Convert RV64A insns to decodetree
17aee59b02 target/riscv: Convert RV32A insns to decodetree
e93a947b94 target/riscv: Convert RVXM insns to decodetree
87454d7d1d target/riscv: Convert RVXI csr insns to decodetree
11f83510fd target/riscv: Convert RVXI fence insns to decodetree
40bf83abf8 target/riscv: Convert RVXI arithmetic insns to decodetree
6f109f635b target/riscv: Convert RV64I load/store insns to decodetree
1bdc022b7c target/riscv: Convert RV32I load/store insns to decodetree
ad3f70396f target/riscv: Convert RVXI branch insns to decodetree
693a52f261 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b098fdaf40 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit b098fdaf40da (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 693a52f261fd (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit ad3f70396f2e (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 1bdc022b7ca3 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 6f109f635b03 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 40bf83abf814 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 11f83510fd16 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 87454d7d1d12 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit e93a947b945f (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these er

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
 * [new tag] patchew/20190131211931.16216-1-sv...@stackframe.org -> 
patchew/20190131211931.16216-1-sv...@stackframe.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb3378a target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a301 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
16680b13d8 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631fd4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de935 target/riscv: Convert @cs_2 insns to share translation functions
24f04339fe target/riscv: Remove decode_RV32_64G()
8e284b2972 target/riscv: Remove gen_system()
7fdd5f104c target/riscv: Rename trans_arith to gen_arith
696cd56967 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbfad9 target/riscv: Remove shift and slt insn manual decoding
69947ae047 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444c18 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f830c target/riscv: Remove manual decoding from gen_store()
b9e24ac0d5 target/riscv: Remove manual decoding from gen_load()
543c238dc7 target/riscv: Remove manual decoding from gen_branch()
1ecefc4283 target/riscv: Remove gen_jalr()
4251a010bd target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627ae71 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107593 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d537b5 target/riscv: Convert RV priv insns to decodetree
28b613a932 target/riscv: Convert RV64D insns to decodetree
02b797edd5 target/riscv: Convert RV32D insns to decodetree
27cc348b3b target/riscv: Convert RV64F insns to decodetree
b0857e0983 target/riscv: Convert RV32F insns to decodetree
b578a96842 target/riscv: Convert RV64A insns to decodetree
26ca8f5631 target/riscv: Convert RV32A insns to decodetree
0ef195feef target/riscv: Convert RVXM insns to decodetree
d22f711d7d target/riscv: Convert RVXI csr insns to decodetree
34de7f7504 target/riscv: Convert RVXI fence insns to decodetree
da5403e39d target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548e2d target/riscv: Convert RV64I load/store insns to decodetree
7f40538802 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4501 target/riscv: Convert RVXI branch insns to decodetree
26e2990ada target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010a7d target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
291fb33 target/riscv: Remaining rvc insn reuse 32 bit translators
f234c9a target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
16680b1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8c27631 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
d2bb2de target/riscv: Convert @cs_2 insns to share translation functions
24f0433 target/riscv: Remove decode_RV32_64G()
8e284b2 target/riscv: Remove gen_system()
7fdd5f1 target/riscv: Rename trans_arith to gen_arith
696cd56 target/riscv: Remove manual decoding of RV32/64M insn
81c0dbf target/riscv: Remove shift and slt insn manual decoding
69947ae target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
b162444 target/riscv: Move gen_arith_imm() decoding into trans_* functions
9d189f8 target/riscv: Remove manual decoding from gen_store()
b9e24ac target/riscv: Remove manual decoding from gen_load()
543c238 target/riscv: Remove manual decoding from gen_branch()
1ecefc4 target/riscv: Remove gen_jalr()
4251a01 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
3a0627a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
135f107 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8833d53 target/riscv: Convert RV priv insns to decodetree
28b613a target/riscv: Convert RV64D insns to decodetree
02b797e target/riscv: Convert RV32D insns to decodetree
27cc348 target/riscv: Convert RV64F insns to decodetree
b0857e0 target/riscv: Convert RV32F insns to decodetree
b578a96 target/riscv: Convert RV64A insns to decodetree
26ca8f5 target/riscv: Convert RV32A insns to decodetree
0ef195f target/riscv: Convert RVXM insns to decodetree
d22f711 target/riscv: Convert RVXI csr insns to decodetree
34de7f7 target/riscv: Convert RVXI fence insns to decodetree
da5403e target/riscv: Convert RVXI arithmetic insns to decodetree
f8d0548 target/riscv: Convert RV64I load/store insns to decodetree
7f40538 target/riscv: Convert RV32I load/store insns to decodetree
d5b10e4 target/riscv: Convert RVXI branch insns to decodetree
26e2990 target/riscv: Activate decodetree and implemnt LUI & AUIPC
2d78010 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 2d78010a7d7b (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 26e2990adad9 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit d5b10e450153 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 7f40538802f9 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit f8d0548e2da9 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit da5403e39dfc (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 34de7f750472 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit d22f711d7ddb (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit 0ef195feef49 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 26ca8f56316d (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161ee9 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3c49 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
4f6990dd63 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13fad target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276f0b target/riscv: Convert @cs_2 insns to share translation functions
6800d2f774 target/riscv: Remove decode_RV32_64G()
52e9366cfe target/riscv: Remove gen_system()
ae15272edc target/riscv: Rename trans_arith to gen_arith
44cb4f52be target/riscv: Remove manual decoding of RV32/64M insn
061c8f4edb target/riscv: Remove shift and slt insn manual decoding
38903407bb target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69edcc target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b751d target/riscv: Remove manual decoding from gen_store()
9724ef941d target/riscv: Remove manual decoding from gen_load()
8b7259ecd2 target/riscv: Remove manual decoding from gen_branch()
e1a89f8fa3 target/riscv: Remove gen_jalr()
3997202158 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0633 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb662db target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e0d7 target/riscv: Convert RV priv insns to decodetree
3936560c24 target/riscv: Convert RV64D insns to decodetree
b2cfe9c051 target/riscv: Convert RV32D insns to decodetree
ef187b9c6f target/riscv: Convert RV64F insns to decodetree
549ce3e937 target/riscv: Convert RV32F insns to decodetree
f12ae436a4 target/riscv: Convert RV64A insns to decodetree
d2d3a0129f target/riscv: Convert RV32A insns to decodetree
f2a1e72600 target/riscv: Convert RVXM insns to decodetree
123c4ce4d6 target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b951 target/riscv: Convert RVXI fence insns to decodetree
23c598c7e8 target/riscv: Convert RVXI arithmetic insns to decodetree
251bd0658a target/riscv: Convert RV64I load/store insns to decodetree
b950690c00 target/riscv: Convert RV32I load/store insns to decodetree
c7c44352c5 target/riscv: Convert RVXI branch insns to decodetree
b9b322714c target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc589a target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
4f6990d target/riscv: Splice fsw_sd and flw

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
 * [new tag] patchew/20190131210851.9842-1-richard.hender...@linaro.org 
-> patchew/20190131210851.9842-1-richard.hender...@linaro.org
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
 * [new tag] patchew/20190131211931.16216-1-sv...@stackframe.org -> 
patchew/20190131211931.16216-1-sv...@stackframe.org
Switched to a new branch 'test'
9e8165d target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
efb9740 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478 target/riscv: Convert @cs_2 insns to share translation functions
110406e target/riscv: Remove decode_RV32_64G()
976eb72 target/riscv: Remove gen_system()
0edf15c target/riscv: Rename trans_arith to gen_arith
dfa6dc2 target/riscv: Remove manual decoding of RV32/64M insn
5a6623c target/riscv: Remove shift and slt insn manual decoding
42aa254 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da target/riscv: Remove manual decoding from gen_store()
2e18729 target/riscv: Remove manual decoding from gen_load()
308b594 target/riscv: Remove manual decoding from gen_branch()
12f3dae target/riscv: Remove gen_jalr()
663d608 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932 target/riscv: Convert RV priv insns to decodetree
57d7252 target/riscv: Convert RV64D insns to decodetree
85126a6 target/riscv: Convert RV32D insns to decodetree
4b1f8c6 target/riscv: Convert RV64F insns to decodetree
ca3cfe3 target/riscv: Convert RV32F insns to decodetree
70fd254 target/riscv: Convert RV64A insns to decodetree
d05a7c9 target/riscv: Convert RV32A insns to decodetree
f56b79a target/riscv: Convert RVXM insns to decodetree
f5805d1 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0 target/riscv: Convert RVXI fence insns to decodetree
197e9af target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8 target/riscv: Convert RV64I load/store insns to decodetree
c44be19 target/riscv: Convert RV32I load/store insns to decodetree
944c287 target/riscv: Convert RVXI branch insns to decodetree
2b11f0f target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eaf target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positiv

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
9e8165dd94 target/riscv: Remaining rvc insn reuse 32 bit translators
e66c95c9bc target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
efb9740ab1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
3c31768d81 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
795b478c4c target/riscv: Convert @cs_2 insns to share translation functions
110406e271 target/riscv: Remove decode_RV32_64G()
976eb72944 target/riscv: Remove gen_system()
0edf15c5d8 target/riscv: Rename trans_arith to gen_arith
dfa6dc21c3 target/riscv: Remove manual decoding of RV32/64M insn
5a6623cc6d target/riscv: Remove shift and slt insn manual decoding
42aa2541a4 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f6ead4a8ee target/riscv: Move gen_arith_imm() decoding into trans_* functions
132f8da29f target/riscv: Remove manual decoding from gen_store()
2e18729d25 target/riscv: Remove manual decoding from gen_load()
308b594c3a target/riscv: Remove manual decoding from gen_branch()
12f3dae1bf target/riscv: Remove gen_jalr()
663d608c7e target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f689ec99ed target/riscv: Convert quadrant 1 of RVXC insns to decodetree
baba3b6b99 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
222b932a1c target/riscv: Convert RV priv insns to decodetree
57d7252133 target/riscv: Convert RV64D insns to decodetree
85126a61bc target/riscv: Convert RV32D insns to decodetree
4b1f8c614b target/riscv: Convert RV64F insns to decodetree
ca3cfe3dd9 target/riscv: Convert RV32F insns to decodetree
70fd2547e6 target/riscv: Convert RV64A insns to decodetree
d05a7c9118 target/riscv: Convert RV32A insns to decodetree
f56b79ac87 target/riscv: Convert RVXM insns to decodetree
f5805d1ea7 target/riscv: Convert RVXI csr insns to decodetree
0d45dd0abf target/riscv: Convert RVXI fence insns to decodetree
197e9af126 target/riscv: Convert RVXI arithmetic insns to decodetree
f4195b8860 target/riscv: Convert RV64I load/store insns to decodetree
c44be19b1c target/riscv: Convert RV32I load/store insns to decodetree
944c2876b3 target/riscv: Convert RVXI branch insns to decodetree
2b11f0fa7d target/riscv: Activate decodetree and implemnt LUI & AUIPC
a377eafc54 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit a377eafc5405 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 2b11f0fa7dd5 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 944c2876b315 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit c44be19b1c8f (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit f4195b886030 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 197e9af1264b (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 0d45dd0abfc6 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit f5805d1ea703 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f56b79ac87ee (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
9b963a1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48 target/riscv: Convert @cs_2 insns to share translation functions
8499159 target/riscv: Remove decode_RV32_64G()
3ac75b0 target/riscv: Remove gen_system()
28b7019 target/riscv: Rename trans_arith to gen_arith
c69cef8 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7 target/riscv: Remove shift and slt insn manual decoding
3e8a05f target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f72 target/riscv: Remove manual decoding from gen_store()
bba5eb0 target/riscv: Remove manual decoding from gen_load()
2382078 target/riscv: Remove manual decoding from gen_branch()
51720e7 target/riscv: Remove gen_jalr()
76fe773 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f88 target/riscv: Convert RV priv insns to decodetree
a45dc64 target/riscv: Convert RV64D insns to decodetree
81d433a target/riscv: Convert RV32D insns to decodetree
a2817b8 target/riscv: Convert RV64F insns to decodetree
a4b3aa5 target/riscv: Convert RV32F insns to decodetree
f571c73 target/riscv: Convert RV64A insns to decodetree
3099ed9 target/riscv: Convert RV32A insns to decodetree
e5cff57 target/riscv: Convert RVXM insns to decodetree
3e87961 target/riscv: Convert RVXI csr insns to decodetree
a9ff2a1 target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4 target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746 target/riscv: Convert RV64I load/store insns to decodetree
18be721 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f2 target/riscv: Convert RVXI branch insns to decodetree
b44b4cc target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3099ed9f2afe (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179aad0 target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce033 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
2a407bf78c target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081bebf6 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd909d2 target/riscv: Convert @cs_2 insns to share translation functions
39402d7cf2 target/riscv: Remove decode_RV32_64G()
e168704ef0 target/riscv: Remove gen_system()
925f796a5d target/riscv: Rename trans_arith to gen_arith
ce11a2d977 target/riscv: Remove manual decoding of RV32/64M insn
819cbda0d1 target/riscv: Remove shift and slt insn manual decoding
6de3ea8220 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8507 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d70f0 target/riscv: Remove manual decoding from gen_store()
6e32a22cc2 target/riscv: Remove manual decoding from gen_load()
fc2febc2de target/riscv: Remove manual decoding from gen_branch()
24ffd31f26 target/riscv: Remove gen_jalr()
ecb0b58ef2 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53aae target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e25d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285826 target/riscv: Convert RV priv insns to decodetree
9c31e4fb05 target/riscv: Convert RV64D insns to decodetree
5e73a245d4 target/riscv: Convert RV32D insns to decodetree
62b38c11f0 target/riscv: Convert RV64F insns to decodetree
4a7251e72d target/riscv: Convert RV32F insns to decodetree
cff510f04b target/riscv: Convert RV64A insns to decodetree
180d186fed target/riscv: Convert RV32A insns to decodetree
bf2294 target/riscv: Convert RVXM insns to decodetree
a3244685ea target/riscv: Convert RVXI csr insns to decodetree
e4cb753f66 target/riscv: Convert RVXI fence insns to decodetree
851fff88fc target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20de2 target/riscv: Convert RV64I load/store insns to decodetree
ca745cbfa1 target/riscv: Convert RV32I load/store insns to decodetree
850511d47c target/riscv: Convert RVXI branch insns to decodetree
812f4fb0e1 target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d802c target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit bf229406 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
ed5d29b4e2 target/riscv: Remaining rvc insn reuse 32 bit translators
b54031a6e1 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
9b963a191d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
eb5cc3d89f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
f31df48270 target/riscv: Convert @cs_2 insns to share translation functions
84991598cd target/riscv: Remove decode_RV32_64G()
3ac75b04e9 target/riscv: Remove gen_system()
28b70192fe target/riscv: Rename trans_arith to gen_arith
c69cef8906 target/riscv: Remove manual decoding of RV32/64M insn
0fee6c7778 target/riscv: Remove shift and slt insn manual decoding
3e8a05f65c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
2805954f69 target/riscv: Move gen_arith_imm() decoding into trans_* functions
4ca0f7208f target/riscv: Remove manual decoding from gen_store()
bba5eb03d7 target/riscv: Remove manual decoding from gen_load()
2382078c37 target/riscv: Remove manual decoding from gen_branch()
51720e7871 target/riscv: Remove gen_jalr()
76fe77374a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
cbdbfe4ce6 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
a845ad9167 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
4757f887d3 target/riscv: Convert RV priv insns to decodetree
a45dc64b14 target/riscv: Convert RV64D insns to decodetree
81d433a355 target/riscv: Convert RV32D insns to decodetree
a2817b828e target/riscv: Convert RV64F insns to decodetree
a4b3aa5113 target/riscv: Convert RV32F insns to decodetree
f571c731a1 target/riscv: Convert RV64A insns to decodetree
3099ed9f2a target/riscv: Convert RV32A insns to decodetree
e5cff571cf target/riscv: Convert RVXM insns to decodetree
3e8796163e target/riscv: Convert RVXI csr insns to decodetree
a9ff2a19cb target/riscv: Convert RVXI fence insns to decodetree
fc1d4e4b6f target/riscv: Convert RVXI arithmetic insns to decodetree
40eb746234 target/riscv: Convert RV64I load/store insns to decodetree
18be721131 target/riscv: Convert RV32I load/store insns to decodetree
3a4a0f26ab target/riscv: Convert RVXI branch insns to decodetree
b44b4cc800 target/riscv: Activate decodetree and implemnt LUI & AUIPC
257d7a3545 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 257d7a3545e4 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit b44b4cc80078 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 3a4a0f26abd1 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 18be72113172 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 40eb746234ae (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit fc1d4e4b6fdc (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit a9ff2a19cbb4 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 3e8796163e96 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit e5cff571cf52 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
5d3e748344 target/riscv: Remaining rvc insn reuse 32 bit translators
4ebbf1dcb0 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
d254063f14 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa3dbf3a29 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
a3eff7f3ed target/riscv: Convert @cs_2 insns to share translation functions
f7b24d5062 target/riscv: Remove decode_RV32_64G()
cbb2c77bce target/riscv: Remove gen_system()
3bbe000ac1 target/riscv: Rename trans_arith to gen_arith
41b7b724e1 target/riscv: Remove manual decoding of RV32/64M insn
8c5199bde1 target/riscv: Remove shift and slt insn manual decoding
3f525d4302 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
8949ae2959 target/riscv: Move gen_arith_imm() decoding into trans_* functions
0269cfffef target/riscv: Remove manual decoding from gen_store()
98e5879319 target/riscv: Remove manual decoding from gen_load()
a02ae5f469 target/riscv: Remove manual decoding from gen_branch()
fefcf6d2fb target/riscv: Remove gen_jalr()
01532a82e7 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
d232ba560a target/riscv: Convert quadrant 1 of RVXC insns to decodetree
165d8337fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
25c307af64 target/riscv: Convert RV priv insns to decodetree
511cb46131 target/riscv: Convert RV64D insns to decodetree
62ffbad8f1 target/riscv: Convert RV32D insns to decodetree
8caabe5e65 target/riscv: Convert RV64F insns to decodetree
20004c0268 target/riscv: Convert RV32F insns to decodetree
38300733ef target/riscv: Convert RV64A insns to decodetree
bde575d56d target/riscv: Convert RV32A insns to decodetree
d37bad2de8 target/riscv: Convert RVXM insns to decodetree
0c9508a7ec target/riscv: Convert RVXI csr insns to decodetree
a6b3d65e3e target/riscv: Convert RVXI fence insns to decodetree
1e1292029e target/riscv: Convert RVXI arithmetic insns to decodetree
de7f337b02 target/riscv: Convert RV64I load/store insns to decodetree
2a2ed84b3c target/riscv: Convert RV32I load/store insns to decodetree
eb157fbcca target/riscv: Convert RVXI branch insns to decodetree
56bb22ad3e target/riscv: Activate decodetree and implemnt LUI & AUIPC
b6c4484f90 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit b6c4484f903d (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 56bb22ad3e17 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit eb157fbccad3 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 2a2ed84b3ca7 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit de7f337b0271 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 1e1292029e37 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit a6b3d65e3e38 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 0c9508a7ec9b (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit d37bad2de864 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
b5d179a target/riscv: Remaining rvc insn reuse 32 bit translators
89632ce target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
2a407bf target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
82081be target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
e17dd90 target/riscv: Convert @cs_2 insns to share translation functions
39402d7 target/riscv: Remove decode_RV32_64G()
e168704 target/riscv: Remove gen_system()
925f796 target/riscv: Rename trans_arith to gen_arith
ce11a2d target/riscv: Remove manual decoding of RV32/64M insn
819cbda target/riscv: Remove shift and slt insn manual decoding
6de3ea8 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
ac209c8 target/riscv: Move gen_arith_imm() decoding into trans_* functions
e6c57d7 target/riscv: Remove manual decoding from gen_store()
6e32a22 target/riscv: Remove manual decoding from gen_load()
fc2febc target/riscv: Remove manual decoding from gen_branch()
24ffd31 target/riscv: Remove gen_jalr()
ecb0b58 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7ce9e53 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
2cf65e2 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
ae6f285 target/riscv: Convert RV priv insns to decodetree
9c31e4f target/riscv: Convert RV64D insns to decodetree
5e73a24 target/riscv: Convert RV32D insns to decodetree
62b38c1 target/riscv: Convert RV64F insns to decodetree
4a7251e target/riscv: Convert RV32F insns to decodetree
cff510f target/riscv: Convert RV64A insns to decodetree
180d186 target/riscv: Convert RV32A insns to decodetree
bf22444 target/riscv: Convert RVXM insns to decodetree
a324468 target/riscv: Convert RVXI csr insns to decodetree
e4cb753 target/riscv: Convert RVXI fence insns to decodetree
851fff8 target/riscv: Convert RVXI arithmetic insns to decodetree
b806b20 target/riscv: Convert RV64I load/store insns to decodetree
ca745cb target/riscv: Convert RV32I load/store insns to decodetree
850511d target/riscv: Convert RVXI branch insns to decodetree
812f4fb target/riscv: Activate decodetree and implemnt LUI & AUIPC
40371d8 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 40371d802c19 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 812f4fb0e12e (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 850511d47ca4 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit ca745cbfa171 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit b806b20de230 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 851fff88fc5c (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit e4cb753f663e (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit a3244685ea17 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit bf229406 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 180d186fed80 (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
0b8b161 target/riscv: Remaining rvc insn reuse 32 bit translators
c572ee3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
4f6990d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
978ba13 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
6950276 target/riscv: Convert @cs_2 insns to share translation functions
6800d2f target/riscv: Remove decode_RV32_64G()
52e9366 target/riscv: Remove gen_system()
ae15272 target/riscv: Rename trans_arith to gen_arith
44cb4f5 target/riscv: Remove manual decoding of RV32/64M insn
061c8f4 target/riscv: Remove shift and slt insn manual decoding
3890340 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
0e4b69e target/riscv: Move gen_arith_imm() decoding into trans_* functions
68786b7 target/riscv: Remove manual decoding from gen_store()
9724ef9 target/riscv: Remove manual decoding from gen_load()
8b7259e target/riscv: Remove manual decoding from gen_branch()
e1a89f8 target/riscv: Remove gen_jalr()
3997202 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
ef701a0 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
ffedb66 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
80efd9e target/riscv: Convert RV priv insns to decodetree
3936560 target/riscv: Convert RV64D insns to decodetree
b2cfe9c target/riscv: Convert RV32D insns to decodetree
ef187b9 target/riscv: Convert RV64F insns to decodetree
549ce3e target/riscv: Convert RV32F insns to decodetree
f12ae43 target/riscv: Convert RV64A insns to decodetree
d2d3a01 target/riscv: Convert RV32A insns to decodetree
f2a1e72 target/riscv: Convert RVXM insns to decodetree
123c4ce target/riscv: Convert RVXI csr insns to decodetree
0a7cb7b target/riscv: Convert RVXI fence insns to decodetree
23c598c target/riscv: Convert RVXI arithmetic insns to decodetree
251bd06 target/riscv: Convert RV64I load/store insns to decodetree
b950690 target/riscv: Convert RV32I load/store insns to decodetree
c7c4435 target/riscv: Convert RVXI branch insns to decodetree
b9b3227 target/riscv: Activate decodetree and implemnt LUI & AUIPC
0b8dcc5 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 0b8dcc589a0b (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit b9b322714c83 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit c7c44352c524 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit b950690c000c (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 251bd0658ab8 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 23c598c7e86f (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 0a7cb7b951af (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 123c4ce4d6bc (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f2a1e72600c7 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit d2d3a0129f2c (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
b915423 target/riscv: Splice fsw_sd and flw

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
a3cbe72 target/riscv: Remaining rvc insn reuse 32 bit translators
9afdd3e target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
b915423 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
4e79caa target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
0121b65 target/riscv: Convert @cs_2 insns to share translation functions
b7a4ef9 target/riscv: Remove decode_RV32_64G()
510bbe8 target/riscv: Remove gen_system()
f1331f5 target/riscv: Rename trans_arith to gen_arith
b276b8c target/riscv: Remove manual decoding of RV32/64M insn
d445e37 target/riscv: Remove shift and slt insn manual decoding
46bfc39 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
9db1077 target/riscv: Move gen_arith_imm() decoding into trans_* functions
72b35f4 target/riscv: Remove manual decoding from gen_store()
84c26d7 target/riscv: Remove manual decoding from gen_load()
4779d13 target/riscv: Remove manual decoding from gen_branch()
5870468 target/riscv: Remove gen_jalr()
fb02c0c target/riscv: Convert quadrant 2 of RVXC insns to decodetree
64793c9 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
5e210d0 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
8d3d945 target/riscv: Convert RV priv insns to decodetree
d3a238f target/riscv: Convert RV64D insns to decodetree
982f175 target/riscv: Convert RV32D insns to decodetree
3fe1356 target/riscv: Convert RV64F insns to decodetree
d231c90 target/riscv: Convert RV32F insns to decodetree
82b118b target/riscv: Convert RV64A insns to decodetree
32b39a2 target/riscv: Convert RV32A insns to decodetree
d6f6f2b target/riscv: Convert RVXM insns to decodetree
34094a1 target/riscv: Convert RVXI csr insns to decodetree
6995f94 target/riscv: Convert RVXI fence insns to decodetree
0a445ed target/riscv: Convert RVXI arithmetic insns to decodetree
3566ff3 target/riscv: Convert RV64I load/store insns to decodetree
9f47cca target/riscv: Convert RV32I load/store insns to decodetree
b28fd8e target/riscv: Convert RVXI branch insns to decodetree
dde69a0 target/riscv: Activate decodetree and implemnt LUI & AUIPC
3e3b3d7 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 3e3b3d7bd110 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit dde69a04bec7 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit b28fd8eb6190 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 9f47cca20003 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 3566ff341f1c (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 0a445ed42134 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 6995f940028d (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 34094a1d0d03 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit d6f6f2bb7f86 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 32b39a20f7d1 (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
b2503c4 target/riscv: Splice fsw_sd and flw

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
b2503c4 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff522 target/riscv: Convert @cs_2 insns to share translation functions
6bd1806 target/riscv: Remove decode_RV32_64G()
5d84869 target/riscv: Remove gen_system()
9398d22 target/riscv: Rename trans_arith to gen_arith
f46f9d3 target/riscv: Remove manual decoding of RV32/64M insn
4f99b16 target/riscv: Remove shift and slt insn manual decoding
4b7a37b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5b target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5 target/riscv: Remove manual decoding from gen_store()
0266236 target/riscv: Remove manual decoding from gen_load()
bd16560 target/riscv: Remove manual decoding from gen_branch()
38dd044 target/riscv: Remove gen_jalr()
f60b6e5 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2 target/riscv: Convert RV priv insns to decodetree
1f1f8c9 target/riscv: Convert RV64D insns to decodetree
d1c0ab7 target/riscv: Convert RV32D insns to decodetree
c6e274a target/riscv: Convert RV64F insns to decodetree
6c51fee target/riscv: Convert RV32F insns to decodetree
577e399 target/riscv: Convert RV64A insns to decodetree
c4fef55 target/riscv: Convert RV32A insns to decodetree
fdbec6c target/riscv: Convert RVXM insns to decodetree
d9ed27a target/riscv: Convert RVXI csr insns to decodetree
591b4a3 target/riscv: Convert RVXI fence insns to decodetree
3fcba6a target/riscv: Convert RVXI arithmetic insns to decodetree
de26410 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7 target/riscv: Convert RV32I load/store insns to decodetree
aedd230 target/riscv: Convert RVXI branch insns to decodetree
52f4c24 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit c4fef55a8df1 (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
b0d91d5c95 target/riscv: Remaining rvc insn reuse 32 bit translators
7206dcc84c target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
b2503c4a5d target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
8a29c8d73f target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
dfff5221bb target/riscv: Convert @cs_2 insns to share translation functions
6bd1806e46 target/riscv: Remove decode_RV32_64G()
5d8486984d target/riscv: Remove gen_system()
9398d224da target/riscv: Rename trans_arith to gen_arith
f46f9d3b7e target/riscv: Remove manual decoding of RV32/64M insn
4f99b16403 target/riscv: Remove shift and slt insn manual decoding
4b7a37bf50 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
d5dff5bb4f target/riscv: Move gen_arith_imm() decoding into trans_* functions
cdd18b5fd3 target/riscv: Remove manual decoding from gen_store()
02662360b2 target/riscv: Remove manual decoding from gen_load()
bd16560117 target/riscv: Remove manual decoding from gen_branch()
38dd04479d target/riscv: Remove gen_jalr()
f60b6e585d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
6696503c0b target/riscv: Convert quadrant 1 of RVXC insns to decodetree
798ef76c96 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
5a39fc2a0e target/riscv: Convert RV priv insns to decodetree
1f1f8c9bc3 target/riscv: Convert RV64D insns to decodetree
d1c0ab7fe1 target/riscv: Convert RV32D insns to decodetree
c6e274a4d5 target/riscv: Convert RV64F insns to decodetree
6c51feecdd target/riscv: Convert RV32F insns to decodetree
577e399bd4 target/riscv: Convert RV64A insns to decodetree
c4fef55a8d target/riscv: Convert RV32A insns to decodetree
fdbec6cffa target/riscv: Convert RVXM insns to decodetree
d9ed27a651 target/riscv: Convert RVXI csr insns to decodetree
591b4a364c target/riscv: Convert RVXI fence insns to decodetree
3fcba6a869 target/riscv: Convert RVXI arithmetic insns to decodetree
de26410380 target/riscv: Convert RV64I load/store insns to decodetree
15edfa7b53 target/riscv: Convert RV32I load/store insns to decodetree
aedd230ba2 target/riscv: Convert RVXI branch insns to decodetree
52f4c244c6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
669f7c2086 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 669f7c2086d5 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 52f4c244c6bb (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit aedd230ba257 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 15edfa7b53d2 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit de26410380cd (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 3fcba6a869c8 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 591b4a364c72 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit d9ed27a651b0 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit fdbec6cffaa5 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
b7781a7 target/riscv: Remaining rvc insn reuse 32 bit translators
1ab9d8e target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
0fa8b2e target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
c244577 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
543f794 target/riscv: Convert @cs_2 insns to share translation functions
aa10284 target/riscv: Remove decode_RV32_64G()
722467d target/riscv: Remove gen_system()
7282e3f target/riscv: Rename trans_arith to gen_arith
740da2a target/riscv: Remove manual decoding of RV32/64M insn
82b3b82 target/riscv: Remove shift and slt insn manual decoding
888303c target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
f43fc38 target/riscv: Move gen_arith_imm() decoding into trans_* functions
675475d target/riscv: Remove manual decoding from gen_store()
18e9f9c target/riscv: Remove manual decoding from gen_load()
a4b5ccf target/riscv: Remove manual decoding from gen_branch()
2bcd11b target/riscv: Remove gen_jalr()
09af5a0 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
f0cd394 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7f0870a target/riscv: Convert quadrant 0 of RVXC insns to decodetree
0b9d6d2 target/riscv: Convert RV priv insns to decodetree
9c6e329 target/riscv: Convert RV64D insns to decodetree
e955fce target/riscv: Convert RV32D insns to decodetree
13e93c0 target/riscv: Convert RV64F insns to decodetree
12184ac target/riscv: Convert RV32F insns to decodetree
a3bcf32 target/riscv: Convert RV64A insns to decodetree
5c47e6b target/riscv: Convert RV32A insns to decodetree
b0f1dae target/riscv: Convert RVXM insns to decodetree
a58a706 target/riscv: Convert RVXI csr insns to decodetree
d47d9c8 target/riscv: Convert RVXI fence insns to decodetree
7a89aec target/riscv: Convert RVXI arithmetic insns to decodetree
a71f6e8 target/riscv: Convert RV64I load/store insns to decodetree
ca43510 target/riscv: Convert RV32I load/store insns to decodetree
e1f0ea1 target/riscv: Convert RVXI branch insns to decodetree
c7218af target/riscv: Activate decodetree and implemnt LUI & AUIPC
9c5a0c8 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 9c5a0c8e56d9 (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit c7218af8df45 (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit e1f0ea1e116d (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit ca43510d59be (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit a71f6e8504f8 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 7a89aecc1174 (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit d47d9c887001 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit a58a706b3359 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit b0f1dae534f9 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 5c47e6b13010 (target/riscv: Convert RV32A insns to

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   aefcd28..e897790  master -> master
 - [tag update]  patchew/20190121170731.2500692-1-stef...@linux.ibm.com -> 
patchew/20190121170731.2500692-1-stef...@linux.ibm.com
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
 - [tag update]  patchew/20190130132214.25493-1-laur...@vivier.eu -> 
patchew/20190130132214.25493-1-laur...@vivier.eu
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submod

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Switched to a new branch 'test'
707ba25e6a target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd801 target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
1271fb32d1 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
e57717196e target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9a48b3870f target/riscv: Convert @cs_2 insns to share translation functions
ae50456b4a target/riscv: Remove decode_RV32_64G()
689db535fa target/riscv: Remove gen_system()
ba19bbe72c target/riscv: Rename trans_arith to gen_arith
4821480397 target/riscv: Remove manual decoding of RV32/64M insn
bc78e8b198 target/riscv: Remove shift and slt insn manual decoding
b24202ed1b target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
c4655ea1af target/riscv: Move gen_arith_imm() decoding into trans_* functions
f4b51a8879 target/riscv: Remove manual decoding from gen_store()
271753698f target/riscv: Remove manual decoding from gen_load()
ce1206dbc3 target/riscv: Remove manual decoding from gen_branch()
35a81db796 target/riscv: Remove gen_jalr()
8d3033de1a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
7f04cc7343 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a1f9394fa target/riscv: Convert quadrant 0 of RVXC insns to decodetree
84311c64b5 target/riscv: Convert RV priv insns to decodetree
801dbbdb4c target/riscv: Convert RV64D insns to decodetree
566965419e target/riscv: Convert RV32D insns to decodetree
e2646f4afe target/riscv: Convert RV64F insns to decodetree
188a6e6678 target/riscv: Convert RV32F insns to decodetree
c39a5a597a target/riscv: Convert RV64A insns to decodetree
74169b8e38 target/riscv: Convert RV32A insns to decodetree
f0db8bcb9c target/riscv: Convert RVXM insns to decodetree
2db8b9a367 target/riscv: Convert RVXI csr insns to decodetree
abf36dbe82 target/riscv: Convert RVXI fence insns to decodetree
437709e78b target/riscv: Convert RVXI arithmetic insns to decodetree
201f108c71 target/riscv: Convert RV64I load/store insns to decodetree
7c6f47530c target/riscv: Convert RV32I load/store insns to decodetree
9e5332de20 target/riscv: Convert RVXI branch insns to decodetree
dc69d0a085 target/riscv: Activate decodetree and implemnt LUI & AUIPC
b4e49789dd target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit b4e49789dd4a (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit dc69d0a0852a (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 9e5332de20d5 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit 7c6f47530cd9 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 201f108c71a8 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 437709e78b8c (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit abf36dbe8296 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 2db8b9a36725 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit f0db8bcb9cb8 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the main

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]  
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de -> 
patchew/20190122092909.5341-1-kbast...@mail.uni-paderborn.de
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for 
path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) 
registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 
'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 
'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered 
for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) 
registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) 
registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for 
path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) 
registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for 
path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for 
path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for 
path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) 
registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' 
(https://github.com/cota/berkeley-softfloat-3) registered for path 
'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' 
(https://github.com/cota/berkeley-testfloat-3) registered for path 
'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) 
registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out 
'22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 
'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out 
'9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 
'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out 
'441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 
'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out 
'51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 
'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out 
'1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 
'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 
'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 
'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out 
'60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 
'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out 
'5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
707ba25 target/riscv: Remaining rvc insn reuse 32 bit translators
e8e3fdd target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
1271fb3 target/riscv: Splice fsw_sd and flw

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-31 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20190122092909.5341-1-kbast...@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190122092909.5341-1-kbast...@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
8fff3fc6a2 target/riscv: Remaining rvc insn reuse 32 bit translators
c563ab1ecb target/riscv: Splice remaining compressed insn pairs for riscv32 vs 
riscv64
e2d25e9d55 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
aa0f8ada63 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
c57a581714 target/riscv: Convert @cs_2 insns to share translation functions
0a0a43441c target/riscv: Remove decode_RV32_64G()
30f9d142a0 target/riscv: Remove gen_system()
5710f6d871 target/riscv: Rename trans_arith to gen_arith
3f07a91951 target/riscv: Remove manual decoding of RV32/64M insn
0fc287193b target/riscv: Remove shift and slt insn manual decoding
236a600baf target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
a4fde90aab target/riscv: Move gen_arith_imm() decoding into trans_* functions
efebe9125f target/riscv: Remove manual decoding from gen_store()
30bef8034b target/riscv: Remove manual decoding from gen_load()
ea82022814 target/riscv: Remove manual decoding from gen_branch()
047f3d2ee4 target/riscv: Remove gen_jalr()
7ea527626d target/riscv: Convert quadrant 2 of RVXC insns to decodetree
27b3303efa target/riscv: Convert quadrant 1 of RVXC insns to decodetree
6a90487077 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
2d8731dad1 target/riscv: Convert RV priv insns to decodetree
b78a5409c2 target/riscv: Convert RV64D insns to decodetree
7181a4f946 target/riscv: Convert RV32D insns to decodetree
dbb77cd4df target/riscv: Convert RV64F insns to decodetree
6ff19f1f62 target/riscv: Convert RV32F insns to decodetree
101b3708d7 target/riscv: Convert RV64A insns to decodetree
18db9d7cbe target/riscv: Convert RV32A insns to decodetree
c2032943b6 target/riscv: Convert RVXM insns to decodetree
80b7b0b6e0 target/riscv: Convert RVXI csr insns to decodetree
35ca21d90a target/riscv: Convert RVXI fence insns to decodetree
a974405bbb target/riscv: Convert RVXI arithmetic insns to decodetree
3ea0060942 target/riscv: Convert RV64I load/store insns to decodetree
c1b9e8b927 target/riscv: Convert RV32I load/store insns to decodetree
109a6de64b target/riscv: Convert RVXI branch insns to decodetree
492967f3a6 target/riscv: Activate decodetree and implemnt LUI & AUIPC
7f257b74de target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 7f257b74decd (target/riscv: Move CPURISCVState pointer to 
DisasContext)
2/35 Checking commit 492967f3a6ae (target/riscv: Activate decodetree and 
implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#34: 
new file mode 100644

ERROR: externs should be avoided in .c files
#125: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 109a6de64b62 (target/riscv: Convert RVXI branch insns to 
decodetree)
4/35 Checking commit c1b9e8b927b1 (target/riscv: Convert RV32I load/store insns 
to decodetree)
5/35 Checking commit 3ea006094257 (target/riscv: Convert RV64I load/store insns 
to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit a974405bbbae (target/riscv: Convert RVXI arithmetic insns 
to decodetree)
7/35 Checking commit 35ca21d90a96 (target/riscv: Convert RVXI fence insns to 
decodetree)
8/35 Checking commit 80b7b0b6e041 (target/riscv: Convert RVXI csr insns to 
decodetree)
9/35 Checking commit c2032943b671 (target/riscv: Convert RVXM insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#48: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 18db9d7cbe2a (target/riscv: Convert RV32A insns to 
decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#54:

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-30 Thread Palmer Dabbelt


On Wed, 30 Jan 2019 01:08:33 PST (-0800), Bastian Koppelmann wrote:

Hi Palmer,

On 1/29/19 8:22 PM, Palmer Dabbelt wrote:

[..]
Well, that pretty much exhausts my testing scheme :).  I think
Alistair might have a setup for booting a 32-bit Yocto-based distro in
QEMU.  Assuming he has the flow set up and it boots then I don't see
any reason not to merge it.

Thanks for pulling this all together, it's really great to have a
cleaner decoder!

Alistair: if that's true, can you give this a shot?

Bastian: do you mind collecting the relevant tags (Reviwed-by, etc)
and putting them in a v6?



I already did (see
http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)


Sorry, my mail latency got a bit high.  So I'm good here, just pending any 
other testing we might have floating around.  I just sent up a PR with a 
handful of little things so we can avoid mixing too much stuff together, but I 
don't see any reason not to include this in the next round.


Thanks!

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-30 Thread Bastian Koppelmann


Hi Palmer,

On 1/29/19 8:22 PM, Palmer Dabbelt wrote:

[..]
Well, that pretty much exhausts my testing scheme :).  I think 
Alistair might have a setup for booting a 32-bit Yocto-based distro in 
QEMU.  Assuming he has the flow set up and it boots then I don't see 
any reason not to merge it.


Thanks for pulling this all together, it's really great to have a 
cleaner decoder!


Alistair: if that's true, can you give this a shot?

Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) 
and putting them in a v6?



I already did (see 
http://lists.gnu.org/archive/html/qemu-riscv/2019-01/msg00147.html) :)


Cheers,

Bastian

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-29 Thread Alistair Francis

On Tue, Jan 29, 2019 at 11:31 AM Palmer Dabbelt  wrote:
>
> On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:
> > On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> >> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.hender...@linaro.org 
> >> wrote:
> >>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>  Hi,
> 
>  this patchset converts the RISC-V decoder to decodetree in four major 
>  steps:
> 
>  1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>  Many of the gen_* functions are called by the decode functions for 
>  16-bit
>  and 32-bit functions. If we move translation code from the gen_*
>  functions to the generated trans_* functions of decode-tree, we get 
>  a lot of
>  duplication. Therefore, we mostly generate calls to the old gen_* 
>  function
>  which are properly replaced after step 2).
> 
>  Each of the trans_ functions are grouped into files corresponding to 
>  their
>  ISA extension, e.g. addi which is in RV32I is translated in the file
>  'trans_rvi.inc.c'.
> 
>  2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>  All 16 bit instructions have a direct mapping to a 32 bit 
>  instruction. Thus,
>  we convert the arguments in the 16 bit trans_ function to the 
>  arguments of
>  the corresponding 32 bit instruction and call the 32 bit trans_ 
>  function.
> 
>  3) Remove old manual decoding in gen_* function [Patch 20-30]:
>  this move all manual translation code into the trans_* instructions 
>  of
>  decode tree, such that we can remove the old decode_* functions.
> 
>  4) Simplify RVC by reusing as much as possible from the RVG decoder as 
>  suggested
> by Richard. [Patch 31-35]
> 
>  full tree available at
>  https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> 
>  Cheers,
>  Bastian
> 
>  v4 -> v5:
>  - fixed rebase error
>  - moved TARGET_LONG_BITS check of shift instructions before rd == 0 
>  check
>  - removed extra sign extension of sraiw
>  - removed rs2 == 0 special cases in sraw/srlw
> >>>
> >>> All looks good to me now.  Thanks for persevering.
> >>
> >> Thanks for reviewing this.
> >>
> >> Bastian: what sort of testing have you done here?  This is a pretty big 
> >> change,
> >> and while it's been fairly extensively reviewed I'm just generally 
> >> paranoid.
> >>
> >
> > I ran riscv-test as well as booting the newest fedora.
>
> Well, that pretty much exhausts my testing scheme :).  I think Alistair might
> have a setup for booting a 32-bit Yocto-based distro in QEMU.  Assuming he has
> the flow set up and it boots then I don't see any reason not to merge it.

I just tested it and 32-bit images boot the same before and after this
patchset. So the 4.19 (with patches ontop) kernel boots, but the 5.0
(with patches ontop) crashes at init.

>
> Thanks for pulling this all together, it's really great to have a cleaner
> decoder!
>
> Alistair: if that's true, can you give this a shot?

Yep, I have been using this in my daily use and haven't seen any
problems. That isn't exhaustive testing but should cover a bit.

Tested-by: Alistair Francis 

Alistair

>
> Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and 
> putting
> them in a v6?
>

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-29 Thread Palmer Dabbelt


On Sat, 26 Jan 2019 00:51:23 PST (-0800), Bastian Koppelmann wrote:

On 1/26/19 12:54 AM, Palmer Dabbelt wrote:

On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.hender...@linaro.org wrote:

On 1/22/19 1:28 AM, Bastian Koppelmann wrote:

Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5

Cheers,
Bastian

v4 -> v5:
    - fixed rebase error
    - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
    - removed extra sign extension of sraiw
    - removed rs2 == 0 special cases in sraw/srlw


All looks good to me now.  Thanks for persevering.


Thanks for reviewing this.

Bastian: what sort of testing have you done here?  This is a pretty big change,
and while it's been fairly extensively reviewed I'm just generally paranoid.



I ran riscv-test as well as booting the newest fedora.


Well, that pretty much exhausts my testing scheme :).  I think Alistair might 
have a setup for booting a 32-bit Yocto-based distro in QEMU.  Assuming he has 
the flow set up and it boots then I don't see any reason not to merge it.


Thanks for pulling this all together, it's really great to have a cleaner 
decoder!


Alistair: if that's true, can you give this a shot?

Bastian: do you mind collecting the relevant tags (Reviwed-by, etc) and putting 
them in a v6?

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-26 Thread Bastian Koppelmann

On 1/26/19 12:54 AM, Palmer Dabbelt wrote:
> On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.hender...@linaro.org wrote:
>> On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
>>> Hi,
>>>
>>> this patchset converts the RISC-V decoder to decodetree in four major steps:
>>>
>>> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>>>     Many of the gen_* functions are called by the decode functions for 
>>> 16-bit
>>>     and 32-bit functions. If we move translation code from the gen_*
>>>     functions to the generated trans_* functions of decode-tree, we get a 
>>> lot of
>>>     duplication. Therefore, we mostly generate calls to the old gen_* 
>>> function
>>>     which are properly replaced after step 2).
>>>
>>>     Each of the trans_ functions are grouped into files corresponding to 
>>> their
>>>     ISA extension, e.g. addi which is in RV32I is translated in the file
>>>     'trans_rvi.inc.c'.
>>>
>>> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>>>     All 16 bit instructions have a direct mapping to a 32 bit instruction. 
>>> Thus,
>>>     we convert the arguments in the 16 bit trans_ function to the arguments 
>>> of
>>>     the corresponding 32 bit instruction and call the 32 bit trans_ 
>>> function.
>>>
>>> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>>>     this move all manual translation code into the trans_* instructions of
>>>     decode tree, such that we can remove the old decode_* functions.
>>>
>>> 4) Simplify RVC by reusing as much as possible from the RVG decoder as 
>>> suggested
>>>    by Richard. [Patch 31-35]
>>>
>>> full tree available at
>>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
>>>
>>> Cheers,
>>> Bastian
>>>
>>> v4 -> v5:
>>>     - fixed rebase error
>>>     - moved TARGET_LONG_BITS check of shift instructions before rd == 0 
>>> check
>>>     - removed extra sign extension of sraiw
>>>     - removed rs2 == 0 special cases in sraw/srlw
>>
>> All looks good to me now.  Thanks for persevering.
> 
> Thanks for reviewing this.
> 
> Bastian: what sort of testing have you done here?  This is a pretty big 
> change,
> and while it's been fairly extensively reviewed I'm just generally paranoid.
> 

I ran riscv-test as well as booting the newest fedora.

Cheers,
Bastian

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-25 Thread Palmer Dabbelt


On Tue, 22 Jan 2019 13:38:52 PST (-0800), richard.hender...@linaro.org wrote:

On 1/22/19 1:28 AM, Bastian Koppelmann wrote:

Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).

Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5

Cheers,
Bastian

v4 -> v5:
- fixed rebase error
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
- removed rs2 == 0 special cases in sraw/srlw


All looks good to me now.  Thanks for persevering.


Thanks for reviewing this.

Bastian: what sort of testing have you done here?  This is a pretty big change, 
and while it's been fairly extensively reviewed I'm just generally paranoid.

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-23 Thread Alistair Francis

On Wed, Jan 23, 2019 at 1:15 AM Bastian Koppelmann
 wrote:
>
>
> On 1/22/19 10:38 PM, Richard Henderson wrote:
> > On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> >> Hi,
> >>
> >> this patchset converts the RISC-V decoder to decodetree in four major 
> >> steps:
> >>
> >> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >>  Many of the gen_* functions are called by the decode functions for 
> >> 16-bit
> >>  and 32-bit functions. If we move translation code from the gen_*
> >>  functions to the generated trans_* functions of decode-tree, we get a 
> >> lot of
> >>  duplication. Therefore, we mostly generate calls to the old gen_* 
> >> function
> >>  which are properly replaced after step 2).
> >>
> >>  Each of the trans_ functions are grouped into files corresponding to 
> >> their
> >>  ISA extension, e.g. addi which is in RV32I is translated in the file
> >>  'trans_rvi.inc.c'.
> >>
> >> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >>  All 16 bit instructions have a direct mapping to a 32 bit 
> >> instruction. Thus,
> >>  we convert the arguments in the 16 bit trans_ function to the 
> >> arguments of
> >>  the corresponding 32 bit instruction and call the 32 bit trans_ 
> >> function.
> >>
> >> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >>  this move all manual translation code into the trans_* instructions of
> >>  decode tree, such that we can remove the old decode_* functions.
> >>
> >> 4) Simplify RVC by reusing as much as possible from the RVG decoder as 
> >> suggested
> >> by Richard. [Patch 31-35]
> >>
> >> full tree available at
> >> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> >>
> >> Cheers,
> >> Bastian
> >>
> >> v4 -> v5:
> >>  - fixed rebase error
> >>  - moved TARGET_LONG_BITS check of shift instructions before rd == 0 
> >> check
> >>  - removed extra sign extension of sraiw
> >>  - removed rs2 == 0 special cases in sraw/srlw
> > All looks good to me now.  Thanks for persevering.
>
>
> Thanks for your great reviews. I'll do a final respin to fix the funky
> indentations. Alistair do you want to pick up the series?

Thanks, the series looks good :)

Palmer is in charge of pull requests for RISC-V QEMU. So it will have
to go through him.

Alistair

>
> Cheers,
>
> Bastian
>
>

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-23 Thread Bastian Koppelmann




On 1/22/19 10:38 PM, Richard Henderson wrote:

On 1/22/19 1:28 AM, Bastian Koppelmann wrote:

Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
 Many of the gen_* functions are called by the decode functions for 16-bit
 and 32-bit functions. If we move translation code from the gen_*
 functions to the generated trans_* functions of decode-tree, we get a lot 
of
 duplication. Therefore, we mostly generate calls to the old gen_* function
 which are properly replaced after step 2).

 Each of the trans_ functions are grouped into files corresponding to their
 ISA extension, e.g. addi which is in RV32I is translated in the file
 'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
 All 16 bit instructions have a direct mapping to a 32 bit instruction. 
Thus,
 we convert the arguments in the 16 bit trans_ function to the arguments of
 the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
 this move all manual translation code into the trans_* instructions of
 decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5

Cheers,
Bastian

v4 -> v5:
 - fixed rebase error
 - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
 - removed extra sign extension of sraiw
 - removed rs2 == 0 special cases in sraw/srlw

All looks good to me now.  Thanks for persevering.



Thanks for your great reviews. I'll do a final respin to fix the funky 
indentations. Alistair do you want to pick up the series?


Cheers,

Bastian

Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-22 Thread Richard Henderson

On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
> Hi,
> 
> this patchset converts the RISC-V decoder to decodetree in four major steps:
> 
> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> Many of the gen_* functions are called by the decode functions for 16-bit
> and 32-bit functions. If we move translation code from the gen_*
> functions to the generated trans_* functions of decode-tree, we get a lot 
> of
> duplication. Therefore, we mostly generate calls to the old gen_* function
> which are properly replaced after step 2).
> 
> Each of the trans_ functions are grouped into files corresponding to their
> ISA extension, e.g. addi which is in RV32I is translated in the file
> 'trans_rvi.inc.c'.
> 
> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> All 16 bit instructions have a direct mapping to a 32 bit instruction. 
> Thus,
> we convert the arguments in the 16 bit trans_ function to the arguments of
> the corresponding 32 bit instruction and call the 32 bit trans_ function.
> 
> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> this move all manual translation code into the trans_* instructions of
> decode tree, such that we can remove the old decode_* functions.
> 
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as 
> suggested
>by Richard. [Patch 31-35]
> 
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5
> 
> Cheers,
> Bastian
> 
> v4 -> v5:
> - fixed rebase error
> - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
> - removed extra sign extension of sraiw
> - removed rs2 == 0 special cases in sraw/srlw

All looks good to me now.  Thanks for persevering.


r~

[Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

2019-01-22 Thread Bastian Koppelmann

Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
Many of the gen_* functions are called by the decode functions for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we get a lot of
duplication. Therefore, we mostly generate calls to the old gen_* function
which are properly replaced after step 2).

Each of the trans_ functions are grouped into files corresponding to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the arguments of
the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
this move all manual translation code into the trans_* instructions of
decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5

Cheers,
Bastian

v4 -> v5:
- fixed rebase error
- moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
- removed extra sign extension of sraiw
- removed rs2 == 0 special cases in sraw/srlw

Bastian Koppelmann (35):
  target/riscv: Move CPURISCVState pointer to DisasContext
  target/riscv: Activate decodetree and implemnt LUI & AUIPC
  target/riscv: Convert RVXI branch insns to decodetree
  target/riscv: Convert RV32I load/store insns to decodetree
  target/riscv: Convert RV64I load/store insns to decodetree
  target/riscv: Convert RVXI arithmetic insns to decodetree
  target/riscv: Convert RVXI fence insns to decodetree
  target/riscv: Convert RVXI csr insns to decodetree
  target/riscv: Convert RVXM insns to decodetree
  target/riscv: Convert RV32A insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Remove gen_jalr()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove gen_system()
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Convert @cs_2 insns to share translation functions
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
  target/riscv: Splice remaining compressed insn pairs for riscv32 vs
riscv64
  target/riscv: Remaining rvc insn reuse 32 bit translators

 target/riscv/Makefile.objs|   22 +
 target/riscv/insn16-32.decode |   31 +
 target/riscv/insn16-64.decode |   33 +
 target/riscv/insn16.decode|  114 ++
 target/riscv/insn32-64.decode |   72 +
 target/riscv/insn32.decode|  203 ++
 .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
 target/riscv/insn_trans/trans_rva.inc.c   |  207 ++
 target/riscv/insn_trans/trans_rvc.inc.c   |  149 ++
 target/riscv/insn_trans/trans_rvd.inc.c   |  388 
 target/riscv/insn_trans/trans_rvf.inc.c   |  388 
 target/riscv/insn_trans/trans_rvi.inc.c   |  568 ++
 target/riscv/insn_trans/trans_rvm.inc.c   |  107 +
 target/riscv/translate.c  | 1781 ++---
 14 files changed, 2611 insertions(+), 1562 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn32-64.decode
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c

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