CVS commit: src/common/lib/libc/arch/x86_64/atomic
Module Name:src Committed By: riastradh Date: Tue Jul 16 22:45:10 UTC 2024 Modified Files: src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: amd64: Fix performance regression in uniprocessor atomics/membars. Back in 2022, I eliminated the MFENCE hotpatch in membar_sync because it's essentially always more expensive than LOCK ADD with no benefit for CPU/CPU store-before-load ordering. (It is relevant only for non-temporal stores or write-combining memory.) https://mail-index.netbsd.org/source-changes/2022/07/30/msg140047.html But in that change, I made a mistake and _also_ eliminated the LOCK hotpatch on uniprocessor amd64. And our assembler gas helpfully interprets uppercase LOCK just like lowercase lock and assembles them the same way, so I didn't notice. This change restores the LOCK hotpatch, so that when booting on a uniprocessor system (or a uniprocessor guest on a multicore host), the LOCK prefix is replaced by NOP for a cheaper instruction. Found by puzzling over how my explanation for PR kern/57199 could possibly be correct when (on an amd64 guest) ddb x/i membar_sync kept showing the lock prefix even in uniprocessor boots. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/x86_64/atomic
Module Name:src Committed By: riastradh Date: Tue Jul 16 22:45:10 UTC 2024 Modified Files: src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: amd64: Fix performance regression in uniprocessor atomics/membars. Back in 2022, I eliminated the MFENCE hotpatch in membar_sync because it's essentially always more expensive than LOCK ADD with no benefit for CPU/CPU store-before-load ordering. (It is relevant only for non-temporal stores or write-combining memory.) https://mail-index.netbsd.org/source-changes/2022/07/30/msg140047.html But in that change, I made a mistake and _also_ eliminated the LOCK hotpatch on uniprocessor amd64. And our assembler gas helpfully interprets uppercase LOCK just like lowercase lock and assembles them the same way, so I didn't notice. This change restores the LOCK hotpatch, so that when booting on a uniprocessor system (or a uniprocessor guest on a multicore host), the LOCK prefix is replaced by NOP for a cheaper instruction. Found by puzzling over how my explanation for PR kern/57199 could possibly be correct when (on an amd64 guest) ddb x/i membar_sync kept showing the lock prefix even in uniprocessor boots. To generate a diff of this commit: cvs rdiff -u -r1.30 -r1.31 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/x86_64/atomic/atomic.S diff -u src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.30 src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.31 --- src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.30 Tue Jul 16 22:44:38 2024 +++ src/common/lib/libc/arch/x86_64/atomic/atomic.S Tue Jul 16 22:45:10 2024 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.30 2024/07/16 22:44:38 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.31 2024/07/16 22:45:10 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -38,6 +38,13 @@ #define ALIAS(f, t) WEAK_ALIAS(f,t) #endif +#ifdef _HARDKERNEL +#include +#define LOCK HOTPATCH(HP_NAME_NOLOCK, 1); lock +#else +#define LOCK lock +#endif + .text /* 32-bit */
CVS commit: src/common/lib/libc/arch
Module Name:src
Committed By: andvar
Date: Sat Mar 30 22:03:39 UTC 2024
Modified Files:
src/common/lib/libc/arch/i386/string: strlen.S
src/common/lib/libc/arch/x86_64/string: strlen.S
Log Message:
s/Westley/Wesley/ in a book reference (in comments).
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/common/lib/libc/arch/i386/string/strlen.S
cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/x86_64/string/strlen.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/i386/string/strlen.S
diff -u src/common/lib/libc/arch/i386/string/strlen.S:1.4 src/common/lib/libc/arch/i386/string/strlen.S:1.5
--- src/common/lib/libc/arch/i386/string/strlen.S:1.4 Wed Dec 8 20:11:54 2021
+++ src/common/lib/libc/arch/i386/string/strlen.S Sat Mar 30 22:03:39 2024
@@ -6,7 +6,7 @@
#include
#if defined(LIBC_SCCS)
- RCSID("$NetBSD: strlen.S,v 1.4 2021/12/08 20:11:54 andvar Exp $")
+ RCSID("$NetBSD: strlen.S,v 1.5 2024/03/30 22:03:39 andvar Exp $")
#endif
ENTRY(strlen)
@@ -89,7 +89,7 @@ ENTRY(strlen)
* to load constants.
*
*
- * [1] Henry S. Warren Jr., "Hacker's Delight", Addison-Westley 2003
+ * [1] Henry S. Warren Jr., "Hacker's Delight", Addison-Wesley 2003
*
* [2] International Business Machines, "The PowerPC Compiler Writer's
* Guide", Warthman Associates, 1996
Index: src/common/lib/libc/arch/x86_64/string/strlen.S
diff -u src/common/lib/libc/arch/x86_64/string/strlen.S:1.7 src/common/lib/libc/arch/x86_64/string/strlen.S:1.8
--- src/common/lib/libc/arch/x86_64/string/strlen.S:1.7 Wed Dec 8 20:11:54 2021
+++ src/common/lib/libc/arch/x86_64/string/strlen.S Sat Mar 30 22:03:39 2024
@@ -1,4 +1,4 @@
-/* $NetBSD: strlen.S,v 1.7 2021/12/08 20:11:54 andvar Exp $ */
+/* $NetBSD: strlen.S,v 1.8 2024/03/30 22:03:39 andvar Exp $ */
/*-
* Copyright (c) 2009 The NetBSD Foundation, Inc.
@@ -37,7 +37,7 @@
#include
#if defined(LIBC_SCCS)
- RCSID("$NetBSD: strlen.S,v 1.7 2021/12/08 20:11:54 andvar Exp $")
+ RCSID("$NetBSD: strlen.S,v 1.8 2024/03/30 22:03:39 andvar Exp $")
#endif
/*
@@ -108,7 +108,7 @@
* to load constants.
*
*
- * [1] Henry S. Warren Jr., "Hacker's Delight", Addison-Westley 2003
+ * [1] Henry S. Warren Jr., "Hacker's Delight", Addison-Wesley 2003
*
* [2] International Business Machines, "The PowerPC Compiler Writer's
* Guide", Warthman Associates, 1996
CVS commit: src/common/lib/libc/arch
Module Name:src Committed By: andvar Date: Sat Mar 30 22:03:39 UTC 2024 Modified Files: src/common/lib/libc/arch/i386/string: strlen.S src/common/lib/libc/arch/x86_64/string: strlen.S Log Message: s/Westley/Wesley/ in a book reference (in comments). To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/common/lib/libc/arch/i386/string/strlen.S cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/x86_64/string/strlen.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/hppa/atomic
Module Name:src
Committed By: skrll
Date: Sun Oct 29 08:04:19 UTC 2023
Modified Files:
src/common/lib/libc/arch/hppa/atomic: Makefile.inc
Log Message:
Define __HAVE_ATOMIC_CAS_64_UP and provide __sync_val_compare_and_swap_8
The new santizer code in gcc12 needs this.
To generate a diff of this commit:
cvs rdiff -u -r1.15 -r1.16 src/common/lib/libc/arch/hppa/atomic/Makefile.inc
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/hppa/atomic/Makefile.inc
diff -u src/common/lib/libc/arch/hppa/atomic/Makefile.inc:1.15 src/common/lib/libc/arch/hppa/atomic/Makefile.inc:1.16
--- src/common/lib/libc/arch/hppa/atomic/Makefile.inc:1.15 Thu Mar 30 15:03:35 2023
+++ src/common/lib/libc/arch/hppa/atomic/Makefile.inc Sun Oct 29 08:04:18 2023
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.15 2023/03/30 15:03:35 riastradh Exp $
+# $NetBSD: Makefile.inc,v 1.16 2023/10/29 08:04:18 skrll Exp $
.if defined(LIB)
@@ -18,6 +18,7 @@ SRCS+= atomic_add_32_cas.c atomic_add_32
. if (${LIB} == "c" || ${LIB} == "pthread")
SRCS+= atomic_init_testset.c
+CPPFLAGS+= -D__HAVE_ATOMIC_CAS_64_UP
SRCS+= atomic_cas_up.S
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_UP
CPPFLAGS+= -D__HAVE_ASM_ATOMIC_CAS_16_UP
CVS commit: src/common/lib/libc/arch/hppa/atomic
Module Name:src Committed By: skrll Date: Sun Oct 29 08:04:19 UTC 2023 Modified Files: src/common/lib/libc/arch/hppa/atomic: Makefile.inc Log Message: Define __HAVE_ATOMIC_CAS_64_UP and provide __sync_val_compare_and_swap_8 The new santizer code in gcc12 needs this. To generate a diff of this commit: cvs rdiff -u -r1.15 -r1.16 src/common/lib/libc/arch/hppa/atomic/Makefile.inc Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/string
Module Name:src
Committed By: skrll
Date: Sun Jul 23 07:54:37 UTC 2023
Modified Files:
src/common/lib/libc/arch/aarch64/string: bcopy.S
Log Message:
port-arm/57388: Minor bug fix in bcopy.S
Use correct register to check alignment of destination in backwards copy.
Patch from Antoni Pokusinski. Thanks.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/aarch64/string/bcopy.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/aarch64/string/bcopy.S
diff -u src/common/lib/libc/arch/aarch64/string/bcopy.S:1.2 src/common/lib/libc/arch/aarch64/string/bcopy.S:1.3
--- src/common/lib/libc/arch/aarch64/string/bcopy.S:1.2 Sat Apr 11 05:12:52 2020
+++ src/common/lib/libc/arch/aarch64/string/bcopy.S Sun Jul 23 07:54:37 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: bcopy.S,v 1.2 2020/04/11 05:12:52 ryo Exp $ */
+/* $NetBSD: bcopy.S,v 1.3 2023/07/23 07:54:37 skrll Exp $ */
/*
* Copyright (c) 2018 Ryo Shimizu
@@ -29,7 +29,7 @@
#include
#if defined(LIBC_SCCS)
-RCSID("$NetBSD: bcopy.S,v 1.2 2020/04/11 05:12:52 ryo Exp $")
+RCSID("$NetBSD: bcopy.S,v 1.3 2023/07/23 07:54:37 skrll Exp $")
#endif
#if defined(MEMCOPY)
@@ -306,7 +306,7 @@ backward_tiny:
ret
9:
/* length is small(<32), and src or dst may be unaligned */
- eor TMP_X, SRC0, DST0
+ eor TMP_X, SRC0, DST
ands TMP_X, TMP_X, #7
bne notaligned_backward_small
CVS commit: src/common/lib/libc/arch/aarch64/string
Module Name:src Committed By: skrll Date: Sun Jul 23 07:54:37 UTC 2023 Modified Files: src/common/lib/libc/arch/aarch64/string: bcopy.S Log Message: port-arm/57388: Minor bug fix in bcopy.S Use correct register to check alignment of destination in backwards copy. Patch from Antoni Pokusinski. Thanks. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/aarch64/string/bcopy.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src
Committed By: mlelstv
Date: Tue Jan 24 07:04:27 UTC 2023
Modified Files:
src/common/lib/libc/arch/arm/string: memcpy_arm.S
Log Message:
Fix two signed comparisons that were missed in the last patch.
Found be rillig@
To generate a diff of this commit:
cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/arm/string/memcpy_arm.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/string/memcpy_arm.S
diff -u src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.6 src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.7
--- src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.6 Thu Jan 19 18:03:03 2023
+++ src/common/lib/libc/arch/arm/string/memcpy_arm.S Tue Jan 24 07:04:27 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: memcpy_arm.S,v 1.6 2023/01/19 18:03:03 mlelstv Exp $ */
+/* $NetBSD: memcpy_arm.S,v 1.7 2023/01/24 07:04:27 mlelstv Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -111,8 +111,8 @@ ENTRY(memcpy)
blo .Lmemcpy_l4
subs r2, r2, #4
- ldrlt r3, [r1], #4
- strlt r3, [r0], #4
+ ldrlo r3, [r1], #4
+ strlo r3, [r0], #4
ldmiahs r1!, {r3, r12}
stmiahs r0!, {r3, r12}
subhs r2, r2, #4
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src Committed By: mlelstv Date: Tue Jan 24 07:04:27 UTC 2023 Modified Files: src/common/lib/libc/arch/arm/string: memcpy_arm.S Log Message: Fix two signed comparisons that were missed in the last patch. Found be rillig@ To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/arm/string/memcpy_arm.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src Committed By: mlelstv Date: Thu Jan 19 18:03:03 UTC 2023 Modified Files: src/common/lib/libc/arch/arm/string: memcpy_arm.S memcpy_neon.S memcpy_xscale.S memmove.S memset.S memset_naive.S strlen_neon.S Log Message: Use unsigned comparisons for pointers and size_t values. To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/arm/string/memcpy_arm.S \ src/common/lib/libc/arch/arm/string/memcpy_xscale.S cvs rdiff -u -r1.1 -r1.2 src/common/lib/libc/arch/arm/string/memcpy_neon.S \ src/common/lib/libc/arch/arm/string/memset_naive.S cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/string/memmove.S cvs rdiff -u -r1.8 -r1.9 src/common/lib/libc/arch/arm/string/memset.S cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/arm/string/strlen_neon.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src
Committed By: mlelstv
Date: Thu Jan 19 18:03:03 UTC 2023
Modified Files:
src/common/lib/libc/arch/arm/string: memcpy_arm.S memcpy_neon.S
memcpy_xscale.S memmove.S memset.S memset_naive.S strlen_neon.S
Log Message:
Use unsigned comparisons for pointers and size_t values.
To generate a diff of this commit:
cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/arm/string/memcpy_arm.S \
src/common/lib/libc/arch/arm/string/memcpy_xscale.S
cvs rdiff -u -r1.1 -r1.2 src/common/lib/libc/arch/arm/string/memcpy_neon.S \
src/common/lib/libc/arch/arm/string/memset_naive.S
cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/string/memmove.S
cvs rdiff -u -r1.8 -r1.9 src/common/lib/libc/arch/arm/string/memset.S
cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/arm/string/strlen_neon.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/string/memcpy_arm.S
diff -u src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.5 src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.6
--- src/common/lib/libc/arch/arm/string/memcpy_arm.S:1.5 Mon Dec 2 21:21:33 2013
+++ src/common/lib/libc/arch/arm/string/memcpy_arm.S Thu Jan 19 18:03:03 2023
@@ -1,4 +1,4 @@
-/* $NetBSD: memcpy_arm.S,v 1.5 2013/12/02 21:21:33 joerg Exp $ */
+/* $NetBSD: memcpy_arm.S,v 1.6 2023/01/19 18:03:03 mlelstv Exp $ */
/*-
* Copyright (c) 1997 The NetBSD Foundation, Inc.
@@ -66,7 +66,7 @@ ENTRY(memcpy)
push {r0, lr} /* memcpy() returns dest addr */
subs r2, r2, #4
- blt .Lmemcpy_l4 /* less than 4 bytes */
+ blo .Lmemcpy_l4 /* less than 4 bytes */
ands r12, r0, #3
bne .Lmemcpy_destul /* oh unaligned destination addr */
ands r12, r1, #3
@@ -75,9 +75,9 @@ ENTRY(memcpy)
.Lmemcpy_t8:
/* We have aligned source and destination */
subs r2, r2, #8
- blt .Lmemcpy_l12 /* less than 12 bytes (4 from above) */
+ blo .Lmemcpy_l12 /* less than 12 bytes (4 from above) */
subs r2, r2, #0x14
- blt .Lmemcpy_l32 /* less than 32 bytes (12 from above) */
+ blo .Lmemcpy_l32 /* less than 32 bytes (12 from above) */
push {r4} /* borrow r4 */
/* blat 32 bytes at a time */
@@ -88,12 +88,12 @@ ENTRY(memcpy)
ldmia r1!, {r3, r4, r12, lr}
stmia r0!, {r3, r4, r12, lr}
subs r2, r2, #0x20
- bge .Lmemcpy_loop32
+ bhs .Lmemcpy_loop32
cmn r2, #0x10
- ldmiage r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
- stmiage r0!, {r3, r4, r12, lr}
- subge r2, r2, #0x10
+ ldmiahs r1!, {r3, r4, r12, lr} /* blat a remaining 16 bytes */
+ stmiahs r0!, {r3, r4, r12, lr}
+ subhs r2, r2, #0x10
pop {r4} /* return r4 */
.Lmemcpy_l32:
@@ -101,21 +101,21 @@ ENTRY(memcpy)
/* blat 12 bytes at a time */
.Lmemcpy_loop12:
- ldmiage r1!, {r3, r12, lr}
- stmiage r0!, {r3, r12, lr}
- subsge r2, r2, #0x0c
- bge .Lmemcpy_loop12
+ ldmiahs r1!, {r3, r12, lr}
+ stmiahs r0!, {r3, r12, lr}
+ subshs r2, r2, #0x0c
+ bhs .Lmemcpy_loop12
.Lmemcpy_l12:
adds r2, r2, #8
- blt .Lmemcpy_l4
+ blo .Lmemcpy_l4
subs r2, r2, #4
ldrlt r3, [r1], #4
strlt r3, [r0], #4
- ldmiage r1!, {r3, r12}
- stmiage r0!, {r3, r12}
- subge r2, r2, #4
+ ldmiahs r1!, {r3, r12}
+ stmiahs r0!, {r3, r12}
+ subhs r2, r2, #4
.Lmemcpy_l4:
/* less than 4 bytes to go */
@@ -129,10 +129,10 @@ ENTRY(memcpy)
cmp r2, #2
ldrb r3, [r1], #1
strb r3, [r0], #1
- ldrbge r3, [r1], #1
- strbge r3, [r0], #1
- ldrbgt r3, [r1], #1
- strbgt r3, [r0], #1
+ ldrbhs r3, [r1], #1
+ strbhs r3, [r0], #1
+ ldrbhi r3, [r1], #1
+ strbhi r3, [r0], #1
pop {r0, pc}
/* erg - unaligned destination */
@@ -143,12 +143,12 @@ ENTRY(memcpy)
/* align destination with byte copies */
ldrb r3, [r1], #1
strb r3, [r0], #1
- ldrbge r3, [r1], #1
- strbge r3, [r0], #1
- ldrbgt r3, [r1], #1
- strbgt r3, [r0], #1
+ ldrbhs r3, [r1], #1
+ strbhs r3, [r0], #1
+ ldrbhi r3, [r1], #1
+ strbhi r3, [r0], #1
subs r2, r2, r12
- blt .Lmemcpy_l4 /* less the 4 bytes */
+ blo .Lmemcpy_l4 /* less the 4 bytes */
ands r12, r1, #3
beq .Lmemcpy_t8 /* we have an aligned source */
@@ -159,10 +159,10 @@ ENTRY(memcpy)
bic r1, r1, #3
ldr lr, [r1], #4
cmp r12, #2
- bgt .Lmemcpy_srcul3
+ bhi .Lmemcpy_srcul3
beq .Lmemcpy_srcul2
cmp r2, #0x0c
- blt .Lmemcpy_srcul1loop4
+ blo .Lmemcpy_srcul1loop4
sub r2, r2, #0x0c
push {r4, r5}
@@ -192,10 +192,10 @@ ENTRY(memcpy)
#endif
stmia r0!, {r3-r5, r12}
subs r2, r2, #0x10
- bge .Lmemcpy_srcul1loop16
+ bhs .Lmemcpy_srcul1loop16
pop {r4, r5}
adds r2, r2, #0x0c
- blt .Lmemcpy_srcul1l4
+ blo .Lmemcpy_srcul1l4
.Lmemcpy_srcul1loop4:
#ifdef __ARMEB__
@@ -211,7 +211,7 @@ ENTRY(memcpy)
#endif
str r12, [r0], #4
subs r2, r2, #4
- bge .Lmemcpy_srcul1loop4
+ bhs .Lmemcpy_srcul1loop4
.Lmemcpy_srcul1l4:
sub r1, r1, #3
@@ -219,7 +219,7 @@ ENTRY(memcpy)
.Lmemcpy_srcul2:
cmp r2, #0x0c
- blt .Lmemcpy_srcul2loop4
+ blo .Lmemcpy_srcul2loop4
sub r2, r2, #0x0c
push {r4, r5}
@@ -249,10 +249,10 @@ ENTRY(m
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src
Committed By: skrll
Date: Sun Jan 15 08:43:04 UTC 2023
Modified Files:
src/common/lib/libc/arch/arm/string: strlen_arm.S
Log Message:
Fix strnlen with a large maxlen argument by using unsigned comparison
conditions - from mlelstv.
I had a similar, but not quite as good patch.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/string/strlen_arm.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/string/strlen_arm.S
diff -u src/common/lib/libc/arch/arm/string/strlen_arm.S:1.10 src/common/lib/libc/arch/arm/string/strlen_arm.S:1.11
--- src/common/lib/libc/arch/arm/string/strlen_arm.S:1.10 Sat Dec 3 11:34:38 2022
+++ src/common/lib/libc/arch/arm/string/strlen_arm.S Sun Jan 15 08:43:03 2023
@@ -29,7 +29,7 @@
#include
-RCSID("$NetBSD: strlen_arm.S,v 1.10 2022/12/03 11:34:38 skrll Exp $")
+RCSID("$NetBSD: strlen_arm.S,v 1.11 2023/01/15 08:43:03 skrll Exp $")
#if defined(__thumb__) && !defined(_ARM_ARCH_T2)
#error Only Thumb2 or ARM supported
@@ -102,7 +102,7 @@ ENTRY(FUNCNAME)
.Lmain_loop:
#ifdef STRNLEN
cmp r0, r5 /* gone too far? */
- bge .Lmaxed_out /* yes, return maxlen */
+ bhs .Lmaxed_out /* yes, return maxlen */
#endif
ldr r3, [r0], #4 /* load next word */
#if defined(_ARM_ARCH_6)
@@ -164,9 +164,9 @@ ENTRY(FUNCNAME)
#ifdef STRNLEN
cmp r0, r4 /* is it larger than maxlen? */
#ifdef __thumb__
- it gt
+ it hi
#endif
- movgt r0, r4 /* yes, return maxlen */
+ movhi r0, r4 /* yes, return maxlen */
pop {r4, r5} /* restore registers */
#endif
RET/* return */
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src Committed By: skrll Date: Sun Jan 15 08:43:04 UTC 2023 Modified Files: src/common/lib/libc/arch/arm/string: strlen_arm.S Log Message: Fix strnlen with a large maxlen argument by using unsigned comparison conditions - from mlelstv. I had a similar, but not quite as good patch. To generate a diff of this commit: cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/string/strlen_arm.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src
Committed By: skrll
Date: Sat Dec 3 11:34:38 UTC 2022
Modified Files:
src/common/lib/libc/arch/arm/string: strlen_arm.S
Log Message:
Fix some comments
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/common/lib/libc/arch/arm/string/strlen_arm.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/string/strlen_arm.S
diff -u src/common/lib/libc/arch/arm/string/strlen_arm.S:1.9 src/common/lib/libc/arch/arm/string/strlen_arm.S:1.10
--- src/common/lib/libc/arch/arm/string/strlen_arm.S:1.9 Tue May 6 16:02:11 2014
+++ src/common/lib/libc/arch/arm/string/strlen_arm.S Sat Dec 3 11:34:38 2022
@@ -29,7 +29,7 @@
#include
-RCSID("$NetBSD: strlen_arm.S,v 1.9 2014/05/06 16:02:11 joerg Exp $")
+RCSID("$NetBSD: strlen_arm.S,v 1.10 2022/12/03 11:34:38 skrll Exp $")
#if defined(__thumb__) && !defined(_ARM_ARCH_T2)
#error Only Thumb2 or ARM supported
@@ -121,9 +121,9 @@ ENTRY(FUNCNAME)
* (other tests for NULs in a word take more instructions/cycles).
*/
tst r3, #BYTE0 /* is this byte 0? */
- tstne r3, #BYTE1 /* no, is this byte 0? */
- tstne r3, #BYTE2 /* no, is this byte 0? */
- tstne r3, #BYTE3 /* no, is this byte 0? */
+ tstne r3, #BYTE1 /* no, is this byte 1? */
+ tstne r3, #BYTE2 /* no, is this byte 2? */
+ tstne r3, #BYTE3 /* no, is this byte 3? */
bne .Lmain_loop /* no, then get next word */
#endif
#if defined(_ARM_ARCH_6)
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src Committed By: skrll Date: Sat Dec 3 11:34:38 UTC 2022 Modified Files: src/common/lib/libc/arch/arm/string: strlen_arm.S Log Message: Fix some comments To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/common/lib/libc/arch/arm/string/strlen_arm.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src
Committed By: skrll
Date: Sat Dec 3 11:30:24 UTC 2022
Modified Files:
src/common/lib/libc/arch/arm/string: strlen_naive.S
Log Message:
improve a comment
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/common/lib/libc/arch/arm/string/strlen_naive.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/string/strlen_naive.S
diff -u src/common/lib/libc/arch/arm/string/strlen_naive.S:1.8 src/common/lib/libc/arch/arm/string/strlen_naive.S:1.9
--- src/common/lib/libc/arch/arm/string/strlen_naive.S:1.8 Mon Aug 19 17:02:25 2013
+++ src/common/lib/libc/arch/arm/string/strlen_naive.S Sat Dec 3 11:30:24 2022
@@ -28,7 +28,7 @@
*/
#include
-RCSID("$NetBSD: strlen_naive.S,v 1.8 2013/08/19 17:02:25 matt Exp $")
+RCSID("$NetBSD: strlen_naive.S,v 1.9 2022/12/03 11:30:24 skrll Exp $")
#ifdef STRNLEN
/* LINTSTUB: size_t strnlen(const char *, size_t) */
@@ -40,7 +40,7 @@ ENTRY(strnlen)
#else
adds ip, r0, r1 /* &src[maxlen] */
#endif
-1: cmp r0, ip /* is this of string? */
+1: cmp r0, ip /* is this the end of string? */
beq 2f /* yes it is */
#ifdef __thumb__
ldrb r2, [r0] /* read a byte */
CVS commit: src/common/lib/libc/arch/arm/string
Module Name:src Committed By: skrll Date: Sat Dec 3 11:30:24 UTC 2022 Modified Files: src/common/lib/libc/arch/arm/string: strlen_naive.S Log Message: improve a comment To generate a diff of this commit: cvs rdiff -u -r1.8 -r1.9 src/common/lib/libc/arch/arm/string/strlen_naive.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src
Committed By: riastradh
Date: Sat Aug 6 21:31:33 UTC 2022
Modified Files:
src/common/lib/libc/arch/aarch64/atomic: Makefile.inc __aarch64_lse.S
Log Message:
aarch64: Implement __aarch64_casN_sync.
gcc generates calls to this symbol in programs that use
__sync_*_compare_and_swap, which require full sequential consistency
barriers, including store-before-load ordering on both sides of the
atomic; none of the release/acquire operations guarantee that, so we
have to insert explicit DMB instructions.
Note: gcc's own definition omits some of the DMB instructions, but I
can't prove that it's correct that way -- stores preceding the CAS
must complete before the load part of the CAS, and the store part of
the CAS must complete before loads following the CAS. Maybe there's
some way to prove that one of these orderings is guaranteed some
other way than a DMB but I'm not seeing it, and store-before-load
ordering is hard to understand.
Patch by skrll@ based on a patch by mrg@, soliloquy in commit message
by me.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/common/lib/libc/arch/aarch64/atomic/Makefile.inc
cvs rdiff -u -r1.6 -r1.7 \
src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/aarch64/atomic/Makefile.inc
diff -u src/common/lib/libc/arch/aarch64/atomic/Makefile.inc:1.4 src/common/lib/libc/arch/aarch64/atomic/Makefile.inc:1.5
--- src/common/lib/libc/arch/aarch64/atomic/Makefile.inc:1.4 Tue Apr 27 09:14:24 2021
+++ src/common/lib/libc/arch/aarch64/atomic/Makefile.inc Sat Aug 6 21:31:33 2022
@@ -1,4 +1,4 @@
-# $NetBSD: Makefile.inc,v 1.4 2021/04/27 09:14:24 skrll Exp $
+# $NetBSD: Makefile.inc,v 1.5 2022/08/06 21:31:33 riastradh Exp $
.if defined(LIB) && (${LIB} == "kern" || ${LIB} == "c" || ${LIB} == "pthread" \
|| ${LIB} == "rump")
@@ -14,7 +14,7 @@ SRCS.atomic+= membar_ops.S
#and cas nand or sub swap xor
.for op in swp cas clr set eor add
.for sz in 1 2 4 8
-.for ar in _relax _acq _rel _acq_rel
+.for ar in _relax _acq _rel _acq_rel _sync
__aarch64_${op}${sz}${ar}.S: __aarch64_lse.S
${_MKTARGET_CREATE}
printf '#define OP ${op}\n#define OP_${op}\n#define SZ ${sz}\n#define AR ${ar}\n#define AR${ar}\n#include "__aarch64_lse.S"\n' > ${.TARGET}
@@ -23,7 +23,7 @@ SRCS.gen+= __aarch64_${op}${sz}${ar}.S
.endfor
.endfor
.for op in casp
-.for ar in _relax _acq _rel _acq_rel
+.for ar in _relax _acq _rel _acq_rel _sync
__aarch64_${op}${ar}.S: __aarch64_lse.S
${_MKTARGET_CREATE}
printf '#define OP ${op}\n#define OP_${op}\n#define AR ${ar}\n#define AR${ar}\n#include "__aarch64_lse.S"\n' > ${.TARGET}
Index: src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S
diff -u src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.6 src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.7
--- src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.6 Sat Jul 23 13:30:15 2022
+++ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Sat Aug 6 21:31:33 2022
@@ -1,4 +1,4 @@
-/* $NetBSD: __aarch64_lse.S,v 1.6 2022/07/23 13:30:15 skrll Exp $ */
+/* $NetBSD: __aarch64_lse.S,v 1.7 2022/08/06 21:31:33 riastradh Exp $ */
/*-
* Copyright (c) 2021 The NetBSD Foundation, Inc.
@@ -64,21 +64,31 @@
#if defined(AR_relax)
#define ACQ
#define REL
+#define DMB
#endif
#if defined(AR_acq)
#define ACQ a
#define REL
+#define DMB
#endif
#if defined(AR_rel)
#define ACQ
#define REL l
+#define DMB
#endif
#if defined(AR_acq_rel)
#define ACQ a
#define REL l
+#define DMB
+#endif
+
+#if defined(AR_sync)
+#define ACQ
+#define REL
+#define DMB dmb ish
#endif
#if defined(OP_clr)
@@ -134,14 +144,18 @@
ENTRY_NP(SWP_FUNC)
#ifdef _HAVE_LSE
DO_LSE_INSN_IF_SUPPORTED(99f)
+ DMB
SWP R0, R0, [x1]
+ DMB
ret
99:
#endif
mov x4, x0 /* need x0 for return value */
+ DMB/* potential barrier */
1: LDXR R0, [x1] /* load old value */
STXR w3, R4, [x1] /* store new value */
cbnz w3, 2f /* succeed?? no, try again */
+ DMB/* potential barrier */
ret/* return old value */
2: b 1b
END(SWP_FUNC)
@@ -151,16 +165,20 @@ END(SWP_FUNC)
ENTRY_NP(CAS_FUNC)
#ifdef _HAVE_LSE
DO_LSE_INSN_IF_SUPPORTED(99f)
+ DMB
CAS R0, R1, [x2]
+ DMB
ret
99:
#endif
mov x4, x0 /* need x0 for return value */
+ DMB/* potential barrier */
1: LDXR R0, [x2] /* load old value */
cmp R0, R4 /* compare */
b.ne 2f /* not equal? return */
STXR w3, R1, [x2] /* store new value */
cbnz w3, 3f /* succeed? nope, try again. */
+ DMB/* potential barrier */
2: ret/* return. */
3: b 1b
END(CAS_FUNC)
@@ -170,12 +188,15 @@ END(CAS_FUNC)
ENTRY_NP(CASP_FUNC)
#ifdef _HAVE_LSE
DO_LSE_INSN_IF_SUPPORTED(99f)
+ DMB
CASP x0, x1, x2, x3, [x4]
+ DMB
ret
99:
#endif
mov x5, x0 /* need x0 for return value */
mov x6, x1 /* need x1 for return
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: riastradh Date: Sat Aug 6 21:31:33 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: Makefile.inc __aarch64_lse.S Log Message: aarch64: Implement __aarch64_casN_sync. gcc generates calls to this symbol in programs that use __sync_*_compare_and_swap, which require full sequential consistency barriers, including store-before-load ordering on both sides of the atomic; none of the release/acquire operations guarantee that, so we have to insert explicit DMB instructions. Note: gcc's own definition omits some of the DMB instructions, but I can't prove that it's correct that way -- stores preceding the CAS must complete before the load part of the CAS, and the store part of the CAS must complete before loads following the CAS. Maybe there's some way to prove that one of these orderings is guaranteed some other way than a DMB but I'm not seeing it, and store-before-load ordering is hard to understand. Patch by skrll@ based on a patch by mrg@, soliloquy in commit message by me. To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 src/common/lib/libc/arch/aarch64/atomic/Makefile.inc cvs rdiff -u -r1.6 -r1.7 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jul 23 13:30:15 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: whitespace To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S diff -u src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.5 src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.6 --- src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.5 Sat Jun 18 08:01:56 2022 +++ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Sat Jul 23 13:30:15 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: __aarch64_lse.S,v 1.5 2022/06/18 08:01:56 skrll Exp $ */ +/* $NetBSD: __aarch64_lse.S,v 1.6 2022/07/23 13:30:15 skrll Exp $ */ /*- * Copyright (c) 2021 The NetBSD Foundation, Inc. @@ -138,11 +138,11 @@ ENTRY_NP(SWP_FUNC) ret 99: #endif - mov x4, x0 /* need x0 for return value */ -1: LDXR R0, [x1] /* load old value */ - STXR w3, R4, [x1] /* store new value */ - cbnz w3, 2f /* succeed?? no, try again */ - ret/* return old value */ + mov x4, x0 /* need x0 for return value */ +1: LDXR R0, [x1] /* load old value */ + STXR w3, R4, [x1] /* store new value */ + cbnz w3, 2f /* succeed?? no, try again */ + ret/* return old value */ 2: b 1b END(SWP_FUNC) #endif @@ -196,12 +196,12 @@ ENTRY_NP(INSN_FUNC) ret 99: #endif - mov x4, x0 /* need x0 for return value */ -1: LDXR R0, [x1] /* load old value */ + mov x4, x0 /* need x0 for return value */ +1: LDXR R0, [x1] /* load old value */ INSNOP R4, R0, R4 - STXR w3, R4, [x1] /* store new value */ - cbnz w3, 2f /* succeed?? no, try again */ - ret/* return old value */ + STXR w3, R4, [x1] /* store new value */ + cbnz w3, 2f /* succeed?? no, try again */ + ret/* return old value */ 2: b 1b END(INSN_FUNC) #endif
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jul 23 13:30:15 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: whitespace To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jun 18 08:01:56 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: be consistent about comparing loaded value against expected old value register ordering To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S diff -u src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.4 src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.5 --- src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.4 Sat Jun 18 07:55:19 2022 +++ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Sat Jun 18 08:01:56 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: __aarch64_lse.S,v 1.4 2022/06/18 07:55:19 skrll Exp $ */ +/* $NetBSD: __aarch64_lse.S,v 1.5 2022/06/18 08:01:56 skrll Exp $ */ /*- * Copyright (c) 2021 The NetBSD Foundation, Inc. @@ -177,9 +177,9 @@ ENTRY_NP(CASP_FUNC) mov x5, x0 /* need x0 for return value */ mov x6, x1 /* need x1 for return value */ 1: LDXP x0, x1, [x4] /* load old value */ - cmp x5, x0 /* compare */ + cmp x0, x5 /* compare */ b.ne 2f /* not equal? return */ - cmp x6, x1 + cmp x1, x6 b.ne 2f /* not equal? return */ STXP w7, x2, x3, [x4] /* store new value */ cbnz w7, 3f /* succeed? nope, try again. */
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jun 18 08:01:56 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: be consistent about comparing loaded value against expected old value register ordering To generate a diff of this commit: cvs rdiff -u -r1.4 -r1.5 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jun 18 07:55:19 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: Fix some register usage To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S diff -u src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.3 src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.4 --- src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.3 Thu Jun 16 08:21:57 2022 +++ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Sat Jun 18 07:55:19 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: __aarch64_lse.S,v 1.3 2022/06/16 08:21:57 skrll Exp $ */ +/* $NetBSD: __aarch64_lse.S,v 1.4 2022/06/18 07:55:19 skrll Exp $ */ /*- * Copyright (c) 2021 The NetBSD Foundation, Inc. @@ -174,8 +174,9 @@ ENTRY_NP(CASP_FUNC) ret 99: #endif - mov x4, x0 /* need x0 for return value */ -1: LDXP x5, x6, [x4] /* load old value */ + mov x5, x0 /* need x0 for return value */ + mov x6, x1 /* need x1 for return value */ +1: LDXP x0, x1, [x4] /* load old value */ cmp x5, x0 /* compare */ b.ne 2f /* not equal? return */ cmp x6, x1
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sat Jun 18 07:55:19 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: Fix some register usage To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Thu Jun 16 08:21:57 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: remove stray 'w' To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S diff -u src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.2 src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.3 --- src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S:1.2 Sun Aug 8 07:17:18 2021 +++ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Thu Jun 16 08:21:57 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: __aarch64_lse.S,v 1.2 2021/08/08 07:17:18 skrll Exp $ */ +/* $NetBSD: __aarch64_lse.S,v 1.3 2022/06/16 08:21:57 skrll Exp $ */ /*- * Copyright (c) 2021 The NetBSD Foundation, Inc. @@ -6,7 +6,7 @@ * * This code is derived from software contributed to The NetBSD Foundation * by Nick Hudson. -w * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met:
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Thu Jun 16 08:21:57 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: __aarch64_lse.S Log Message: remove stray 'w' To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 \ src/common/lib/libc/arch/aarch64/atomic/__aarch64_lse.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/riscv/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:53 UTC 2022 Modified Files: src/common/lib/libc/arch/riscv/atomic: membar_ops.S Log Message: riscv/membar_ops: Upgrade membar_enter from W/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/riscv/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/riscv/atomic/membar_ops.S diff -u src/common/lib/libc/arch/riscv/atomic/membar_ops.S:1.2 src/common/lib/libc/arch/riscv/atomic/membar_ops.S:1.3 --- src/common/lib/libc/arch/riscv/atomic/membar_ops.S:1.2 Wed Apr 6 22:47:56 2022 +++ src/common/lib/libc/arch/riscv/atomic/membar_ops.S Sat Apr 9 22:53:53 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.2 2022/04/06 22:47:56 riastradh Exp $ */ +/* $NetBSD: membar_ops.S,v 1.3 2022/04/09 22:53:53 riastradh Exp $ */ /*- * Copyright (c) 2006, 2007 The NetBSD Foundation, Inc. @@ -39,7 +39,7 @@ ATOMIC_OP_ALIAS(membar_sync,_membar_sync CRT_ALIAS(__sync_synchronize,_membar_sync) ENTRY_NP(_membar_enter) - fence w,rw + fence rw,rw ret END(_membar_enter) ATOMIC_OP_ALIAS(membar_enter,_membar_enter)
CVS commit: src/common/lib/libc/arch/riscv/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:53 UTC 2022 Modified Files: src/common/lib/libc/arch/riscv/atomic: membar_ops.S Log Message: riscv/membar_ops: Upgrade membar_enter from W/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/riscv/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/x86_64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:45 UTC 2022 Modified Files: src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86_64/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/x86_64/atomic/atomic.S diff -u src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.26 src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.27 --- src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.26 Sat Apr 9 12:07:29 2022 +++ src/common/lib/libc/arch/x86_64/atomic/atomic.S Sat Apr 9 22:53:45 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.26 2022/04/09 12:07:29 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.27 2022/04/09 22:53:45 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -365,7 +365,7 @@ ALIAS(atomic_cas_ptr_ni,_atomic_cas_64_n ALIAS(membar_consumer,_membar_consumer) ALIAS(membar_producer,_membar_producer) -ALIAS(membar_enter,_membar_consumer) +ALIAS(membar_enter,_membar_sync) ALIAS(membar_exit,_membar_producer) ALIAS(membar_sync,_membar_sync) @@ -421,7 +421,7 @@ STRONG_ALIAS(_atomic_cas_uint_ni,_atomic STRONG_ALIAS(_atomic_cas_ulong_ni,_atomic_cas_64_ni) STRONG_ALIAS(_atomic_cas_ptr_ni,_atomic_cas_64_ni) -STRONG_ALIAS(_membar_enter,_membar_consumer) +STRONG_ALIAS(_membar_enter,_membar_sync) STRONG_ALIAS(_membar_exit,_membar_producer) #ifdef _HARDKERNEL
CVS commit: src/common/lib/libc/arch/x86_64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:45 UTC 2022 Modified Files: src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86_64/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.26 -r1.27 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/i386/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:36 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S Log Message: i386/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/common/lib/libc/arch/i386/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/i386/atomic/atomic.S diff -u src/common/lib/libc/arch/i386/atomic/atomic.S:1.33 src/common/lib/libc/arch/i386/atomic/atomic.S:1.34 --- src/common/lib/libc/arch/i386/atomic/atomic.S:1.33 Sat Apr 9 12:07:29 2022 +++ src/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 9 22:53:36 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.33 2022/04/09 12:07:29 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.34 2022/04/09 22:53:36 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -342,7 +342,7 @@ ALIAS(__sync_val_compare_and_swap_8,_ato ALIAS(membar_consumer,_membar_consumer) ALIAS(membar_producer,_membar_producer) -ALIAS(membar_enter,_membar_consumer) +ALIAS(membar_enter,_membar_sync) ALIAS(membar_exit,_membar_producer) ALIAS(membar_sync,_membar_sync) @@ -398,7 +398,7 @@ STRONG_ALIAS(_atomic_cas_uint_ni,_atomic STRONG_ALIAS(_atomic_cas_ulong_ni,_atomic_cas_32_ni) STRONG_ALIAS(_atomic_cas_ptr_ni,_atomic_cas_32_ni) -STRONG_ALIAS(_membar_enter,_membar_consumer) +STRONG_ALIAS(_membar_enter,_membar_sync) STRONG_ALIAS(_membar_exit,_membar_producer) #ifdef _HARDKERNEL
CVS commit: src/common/lib/libc/arch/i386/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:36 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S Log Message: i386/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.33 -r1.34 src/common/lib/libc/arch/i386/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/sparc64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:25 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc64/atomic: membar_ops.S Log Message: sparc64/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/sparc64/atomic/membar_ops.S diff -u src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.7 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.8 --- src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.7 Sat Apr 9 12:06:47 2022 +++ src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Sat Apr 9 22:53:25 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.7 2022/04/09 12:06:47 riastradh Exp $ */ +/* $NetBSD: membar_ops.S,v 1.8 2022/04/09 22:53:25 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -35,8 +35,9 @@ /* * These assume Total Store Order (TSO), which may reorder - * store-before-load but nothing else. Hence, only membar_sync must - * issue anything -- namely, membar #StoreLoad. + * store-before-load but nothing else. Hence, only membar_sync (and + * its deprecated alias membar_enter) must issue anything -- namely, + * membar #StoreLoad. * * If we ran with Partial Store Order (PSO), we would also need to * issue membar #StoreStore for membar_exit (load/store-before-store) @@ -73,8 +74,8 @@ END(_membar_sync) ATOMIC_OP_ALIAS(membar_producer,_membar_consumer) STRONG_ALIAS(_membar_producer,_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) -ATOMIC_OP_ALIAS(membar_enter,_membar_consumer) -STRONG_ALIAS(_membar_enter,_membar_consumer) +ATOMIC_OP_ALIAS(membar_enter,_membar_sync) +STRONG_ALIAS(_membar_enter,_membar_sync) ATOMIC_OP_ALIAS(membar_exit,_membar_consumer) STRONG_ALIAS(_membar_exit,_membar_consumer) ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
CVS commit: src/common/lib/libc/arch/sparc64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:25 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc64/atomic: membar_ops.S Log Message: sparc64/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/sparc/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:17 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc/atomic: membar_ops.S Log Message: sparc/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/sparc/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/sparc/atomic/membar_ops.S diff -u src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.6 src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.7 --- src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.6 Sat Apr 9 12:06:39 2022 +++ src/common/lib/libc/arch/sparc/atomic/membar_ops.S Sat Apr 9 22:53:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.6 2022/04/09 12:06:39 riastradh Exp $ */ +/* $NetBSD: membar_ops.S,v 1.7 2022/04/09 22:53:17 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -39,10 +39,10 @@ /* * These assume Total Store Order (TSO), which may reorder - * store-before-load but nothing else. Hence, only membar_sync must - * issue anything -- specifically, an LDSTUB, which (along with SWAP) - * is the only instruction that implies a sequential consistency - * barrier. + * store-before-load but nothing else. Hence, only membar_sync (and + * its deprecated alias membar_enter) must issue anything -- + * specifically, an LDSTUB, which (along with SWAP) is the only + * instruction that implies a sequential consistency barrier. * * If we ran with Partial Store Order (PSO), we would also need to * issue STBAR for membar_exit (load/store-before-store) and @@ -66,8 +66,8 @@ END(_membar_sync) ATOMIC_OP_ALIAS(membar_producer,_membar_consumer) STRONG_ALIAS(_membar_producer,_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) -ATOMIC_OP_ALIAS(membar_enter,_membar_consumer) -STRONG_ALIAS(_membar_enter,_membar_consumer) +ATOMIC_OP_ALIAS(membar_enter,_membar_sync) +STRONG_ALIAS(_membar_enter,_membar_sync) ATOMIC_OP_ALIAS(membar_exit,_membar_consumer) STRONG_ALIAS(_membar_exit,_membar_consumer) ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
CVS commit: src/common/lib/libc/arch/sparc/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 22:53:17 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc/atomic: membar_ops.S Log Message: sparc/membar_ops: Upgrade membar_enter from R/RW to RW/RW. This will be deprecated soon but let's avoid leaving rakes to trip on with it arising from disagreement over the documentation (W/RW) and implementation and usage (R/RW). To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/sparc/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:37 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: membar_ops.S Log Message: aarch64/membar_ops: Fix wrong symbol end. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/aarch64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/membar_ops.S diff -u src/common/lib/libc/arch/aarch64/atomic/membar_ops.S:1.2 src/common/lib/libc/arch/aarch64/atomic/membar_ops.S:1.3 --- src/common/lib/libc/arch/aarch64/atomic/membar_ops.S:1.2 Tue Oct 13 21:22:12 2020 +++ src/common/lib/libc/arch/aarch64/atomic/membar_ops.S Sat Apr 9 12:07:37 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.2 2020/10/13 21:22:12 skrll Exp $ */ +/* $NetBSD: membar_ops.S,v 1.3 2022/04/09 12:07:37 riastradh Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -42,7 +42,7 @@ STRONG_ALIAS(_membar_write,_membar_produ ENTRY_NP(_membar_consumer) dmb ishld ret -END(_membar_producer) +END(_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) ATOMIC_OP_ALIAS(membar_read,_membar_consumer) STRONG_ALIAS(_membar_read,_membar_consumer)
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:37 UTC 2022 Modified Files: src/common/lib/libc/arch/aarch64/atomic: membar_ops.S Log Message: aarch64/membar_ops: Fix wrong symbol end. To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/common/lib/libc/arch/aarch64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:29 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86: Add a note on membar_sync and mfence. To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/common/lib/libc/arch/i386/atomic/atomic.S cvs rdiff -u -r1.25 -r1.26 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/i386/atomic/atomic.S diff -u src/common/lib/libc/arch/i386/atomic/atomic.S:1.32 src/common/lib/libc/arch/i386/atomic/atomic.S:1.33 --- src/common/lib/libc/arch/i386/atomic/atomic.S:1.32 Sat Apr 9 12:07:17 2022 +++ src/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 9 12:07:29 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.32 2022/04/09 12:07:17 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.33 2022/04/09 12:07:29 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -197,6 +197,12 @@ ENTRY(_membar_producer) END(_membar_producer) ENTRY(_membar_sync) + /* + * MFENCE, or a serializing instruction like a locked addq, + * is necessary to order store-before-load. Every other + * ordering -- load-before-anything, anything-before-store -- + * is already guaranteed without explicit barriers. + */ HOTPATCH_SSE2_MFENCE /* 7 bytes of instructions */ LOCK Index: src/common/lib/libc/arch/x86_64/atomic/atomic.S diff -u src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.25 src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.26 --- src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.25 Sat Apr 9 12:07:17 2022 +++ src/common/lib/libc/arch/x86_64/atomic/atomic.S Sat Apr 9 12:07:29 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.25 2022/04/09 12:07:17 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.26 2022/04/09 12:07:29 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -272,6 +272,12 @@ ENTRY(_membar_producer) END(_membar_producer) ENTRY(_membar_sync) + /* + * MFENCE, or a serializing instruction like a locked addq, + * is necessary to order store-before-load. Every other + * ordering -- load-before-anything, anything-before-store -- + * is already guaranteed without explicit barriers. + */ HOTPATCH_SSE2_MFENCE /* 8 bytes of instructions */ LOCK
CVS commit: src/common/lib/libc/arch
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:29 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86: Add a note on membar_sync and mfence. To generate a diff of this commit: cvs rdiff -u -r1.32 -r1.33 src/common/lib/libc/arch/i386/atomic/atomic.S cvs rdiff -u -r1.25 -r1.26 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:18 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86: Omit needless store in membar_producer/exit. On x86, every store is a store-release, so there is no need for any barrier. But this wasn't a barrier anyway; it was just a store, which was redundant with the store of the return address to the stack implied by CALL even if issuing a store made a difference. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/common/lib/libc/arch/i386/atomic/atomic.S cvs rdiff -u -r1.24 -r1.25 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/i386/atomic/atomic.S diff -u src/common/lib/libc/arch/i386/atomic/atomic.S:1.31 src/common/lib/libc/arch/i386/atomic/atomic.S:1.32 --- src/common/lib/libc/arch/i386/atomic/atomic.S:1.31 Sat Apr 9 12:07:00 2022 +++ src/common/lib/libc/arch/i386/atomic/atomic.S Sat Apr 9 12:07:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.31 2022/04/09 12:07:00 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.32 2022/04/09 12:07:17 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -188,8 +188,11 @@ ENTRY(_membar_consumer) END(_membar_consumer) ENTRY(_membar_producer) - /* A store is enough */ - movl $0, -4(%esp) + /* + * Every store to normal memory is a store-release on x86, so + * there is never any need for explicit barriers to order + * anything-before-store. + */ ret END(_membar_producer) Index: src/common/lib/libc/arch/x86_64/atomic/atomic.S diff -u src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.24 src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.25 --- src/common/lib/libc/arch/x86_64/atomic/atomic.S:1.24 Sat Apr 9 12:07:00 2022 +++ src/common/lib/libc/arch/x86_64/atomic/atomic.S Sat Apr 9 12:07:17 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic.S,v 1.24 2022/04/09 12:07:00 riastradh Exp $ */ +/* $NetBSD: atomic.S,v 1.25 2022/04/09 12:07:17 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -263,8 +263,11 @@ ENTRY(_membar_consumer) END(_membar_consumer) ENTRY(_membar_producer) - /* A store is enough */ - movq $0, -8(%rsp) + /* + * Every store to normal memory is a store-release on x86, so + * there is never any need for explicit barriers to order + * anything-before-store. + */ ret END(_membar_producer)
CVS commit: src/common/lib/libc/arch
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:07:18 UTC 2022 Modified Files: src/common/lib/libc/arch/i386/atomic: atomic.S src/common/lib/libc/arch/x86_64/atomic: atomic.S Log Message: x86: Omit needless store in membar_producer/exit. On x86, every store is a store-release, so there is no need for any barrier. But this wasn't a barrier anyway; it was just a store, which was redundant with the store of the return address to the stack implied by CALL even if issuing a store made a difference. To generate a diff of this commit: cvs rdiff -u -r1.31 -r1.32 src/common/lib/libc/arch/i386/atomic/atomic.S cvs rdiff -u -r1.24 -r1.25 src/common/lib/libc/arch/x86_64/atomic/atomic.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/sparc64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:06:48 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc64/atomic: membar_ops.S Log Message: sparc64: Fix membar_sync by issuing membar #StoreLoad. In TSO this is the only memory barrier ever needed, and somehow we got this wrong and instead issued an unnecessary membar #LoadLoad -- not needed even in PSO let alone in TSO. XXX Apparently we may run userland programs with PSO or RMO, in which case all of these membars need fixing: PSO RMO membar_consumer nop membar #LoadLoad membar_producer membar #StoreStore membar #StoreStore membar_enternop membar #LoadLoad|LoadStore membar_exit membar #StoreStore membar #LoadStore|StoreStore membar_sync membar #StoreLoad|StoreStore membar #...everything... But at least this fixes the TSO case in which we run the kernel. Also I'm not sure there's any non-TSO hardware out there in practice. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/sparc64/atomic/membar_ops.S diff -u src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.6 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.7 --- src/common/lib/libc/arch/sparc64/atomic/membar_ops.S:1.6 Wed Apr 6 22:47:57 2022 +++ src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Sat Apr 9 12:06:47 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.6 2022/04/06 22:47:57 riastradh Exp $ */ +/* $NetBSD: membar_ops.S,v 1.7 2022/04/09 12:06:47 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -33,22 +33,48 @@ .text -/* These assume Total Store Order (TSO) */ +/* + * These assume Total Store Order (TSO), which may reorder + * store-before-load but nothing else. Hence, only membar_sync must + * issue anything -- namely, membar #StoreLoad. + * + * If we ran with Partial Store Order (PSO), we would also need to + * issue membar #StoreStore for membar_exit (load/store-before-store) + * and membar_producer (store-before-store). + */ -ENTRY(_membar_producer) +ENTRY(_membar_consumer) retl nop +END(_membar_consumer) -ENTRY(_membar_consumer) - membar #LoadLoad +ENTRY(_membar_sync) + /* + * Some SPARC CPUs have errata with MEMBAR in the delay slot of + * a branch, such as the UltraSPARC-IIi: + * + * `Apparently, the deadlock is most easily caused if the + * delay slot of the JMPL is a MEMBAR #Sync, or any + * instruction that synchronizes on the load or store + * buffers being empty.' + * + * UltraSPARC-IIi User's Manual, Part No. 805-0087-01, Sun + * Microsystems, October 1997, Appendix K.2 `Errata + * Created by UltraSPARC-I', Erratum 51, p. 476. + * https://www.oracle.com/technetwork/server-storage/sun-sparc-enterprise/documentation/sparc-2i-usersmanual-2516677.pdf#page=518 + * + * So let's avoid doing that. + */ + membar #StoreLoad retl nop +END(_membar_sync) -ATOMIC_OP_ALIAS(membar_producer,_membar_producer) +ATOMIC_OP_ALIAS(membar_producer,_membar_consumer) +STRONG_ALIAS(_membar_producer,_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) ATOMIC_OP_ALIAS(membar_enter,_membar_consumer) STRONG_ALIAS(_membar_enter,_membar_consumer) ATOMIC_OP_ALIAS(membar_exit,_membar_consumer) STRONG_ALIAS(_membar_exit,_membar_consumer) -ATOMIC_OP_ALIAS(membar_sync,_membar_consumer) -STRONG_ALIAS(_membar_sync,_membar_consumer) +ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
CVS commit: src/common/lib/libc/arch/sparc64/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:06:48 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc64/atomic: membar_ops.S Log Message: sparc64: Fix membar_sync by issuing membar #StoreLoad. In TSO this is the only memory barrier ever needed, and somehow we got this wrong and instead issued an unnecessary membar #LoadLoad -- not needed even in PSO let alone in TSO. XXX Apparently we may run userland programs with PSO or RMO, in which case all of these membars need fixing: PSO RMO membar_consumer nop membar #LoadLoad membar_producer membar #StoreStore membar #StoreStore membar_enternop membar #LoadLoad|LoadStore membar_exit membar #StoreStore membar #LoadStore|StoreStore membar_sync membar #StoreLoad|StoreStore membar #...everything... But at least this fixes the TSO case in which we run the kernel. Also I'm not sure there's any non-TSO hardware out there in practice. To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/sparc64/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/sparc/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:06:39 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc/atomic: membar_ops.S Log Message: sparc: Fix membar_sync with LDSTUB. membar_sync is required to be a full sequential consistency barrier, equivalent to MEMBAR #StoreStore|LoadStore|StoreLoad|LoadLoad on sparcv9. LDSTUB and SWAP are the only pre-v9 instructions that do this and SWAP doesn't exist on all v7 hardware, so use LDSTUB. Note: I'm having a hard time nailing down a reference for the ordering implied by LDSTUB and SWAP. I'm _pretty sure_ SWAP has to imply store-load ordering since the SPARCv8 manual recommends it for Dekker's algorithm (which notoriously requires store-load ordering), and the formal memory model treats LDSTUB and SWAP the same for ordering. But the v8 and v9 manuals aren't clear. GCC issues STBAR and LDSTUB, but (a) I don't see why STBAR is necessary here, (b) STBAR doesn't exist on v7 so it'd be a pain to use, and (c) from what I've heard (although again it's hard to nail down authoritative references here) all actual SPARC hardware is TSO or SC anyway so STBAR is a noop in all the silicon anyway. Either way, certainly this is better than what we had before, which was nothing implying ordering at all, just a store! To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/sparc/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/sparc/atomic
Module Name:src Committed By: riastradh Date: Sat Apr 9 12:06:39 UTC 2022 Modified Files: src/common/lib/libc/arch/sparc/atomic: membar_ops.S Log Message: sparc: Fix membar_sync with LDSTUB. membar_sync is required to be a full sequential consistency barrier, equivalent to MEMBAR #StoreStore|LoadStore|StoreLoad|LoadLoad on sparcv9. LDSTUB and SWAP are the only pre-v9 instructions that do this and SWAP doesn't exist on all v7 hardware, so use LDSTUB. Note: I'm having a hard time nailing down a reference for the ordering implied by LDSTUB and SWAP. I'm _pretty sure_ SWAP has to imply store-load ordering since the SPARCv8 manual recommends it for Dekker's algorithm (which notoriously requires store-load ordering), and the formal memory model treats LDSTUB and SWAP the same for ordering. But the v8 and v9 manuals aren't clear. GCC issues STBAR and LDSTUB, but (a) I don't see why STBAR is necessary here, (b) STBAR doesn't exist on v7 so it'd be a pain to use, and (c) from what I've heard (although again it's hard to nail down authoritative references here) all actual SPARC hardware is TSO or SC anyway so STBAR is a noop in all the silicon anyway. Either way, certainly this is better than what we had before, which was nothing implying ordering at all, just a store! To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/common/lib/libc/arch/sparc/atomic/membar_ops.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/sparc/atomic/membar_ops.S diff -u src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.5 src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.6 --- src/common/lib/libc/arch/sparc/atomic/membar_ops.S:1.5 Wed Apr 6 22:47:56 2022 +++ src/common/lib/libc/arch/sparc/atomic/membar_ops.S Sat Apr 9 12:06:39 2022 @@ -1,4 +1,4 @@ -/* $NetBSD: membar_ops.S,v 1.5 2022/04/06 22:47:56 riastradh Exp $ */ +/* $NetBSD: membar_ops.S,v 1.6 2022/04/09 12:06:39 riastradh Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -31,25 +31,43 @@ #include "atomic_op_asm.h" +#ifdef _KERNEL_OPT +#include "opt_multiprocessor.h" +#endif + .text -/* These assume Total Store Order (TSO) */ +/* + * These assume Total Store Order (TSO), which may reorder + * store-before-load but nothing else. Hence, only membar_sync must + * issue anything -- specifically, an LDSTUB, which (along with SWAP) + * is the only instruction that implies a sequential consistency + * barrier. + * + * If we ran with Partial Store Order (PSO), we would also need to + * issue STBAR for membar_exit (load/store-before-store) and + * membar_producer (store-before-store). + */ -ENTRY(_membar_producer) +ENTRY(_membar_consumer) retl nop +END(_membar_consumer) -ENTRY(_membar_consumer) - add %sp, -112, %sp - st %g0, [%sp+100] +ENTRY(_membar_sync) retl - sub %sp, -112, %sp +#if !defined(_KERNEL) || defined(MULTIPROCESSOR) + ldstub [%sp - 4], %g0 +#else + nop +#endif +END(_membar_sync) -ATOMIC_OP_ALIAS(membar_producer,_membar_producer) +ATOMIC_OP_ALIAS(membar_producer,_membar_consumer) +STRONG_ALIAS(_membar_producer,_membar_consumer) ATOMIC_OP_ALIAS(membar_consumer,_membar_consumer) ATOMIC_OP_ALIAS(membar_enter,_membar_consumer) STRONG_ALIAS(_membar_enter,_membar_consumer) ATOMIC_OP_ALIAS(membar_exit,_membar_consumer) STRONG_ALIAS(_membar_exit,_membar_consumer) -ATOMIC_OP_ALIAS(membar_sync,_membar_consumer) -STRONG_ALIAS(_membar_sync,_membar_consumer) +ATOMIC_OP_ALIAS(membar_sync,_membar_sync)
Re: CVS commit: src/common/lib/libc/arch/aarch64/atomic
On 04/07/2021 23:11, Joerg Sonnenberger wrote:
On Sun, Jul 04, 2021 at 06:55:47AM +, Nick Hudson wrote:
Module Name:src
Committed By: skrll
Date: Sun Jul 4 06:55:47 UTC 2021
Modified Files:
src/common/lib/libc/arch/aarch64/atomic: atomic_nand_16.S
atomic_nand_32.S atomic_nand_64.S atomic_nand_8.S
Log Message:
Fix the logic operation for atomic_nand_{8,16,32,64}
From the gcc docs the operations are as follows
{ tmp = *ptr; *ptr = ~(tmp & value); return tmp; } // nand
{ tmp = ~(*ptr & value); *ptr = tmp; return *ptr; } // nand
yes, this is really rather strange.
This depends on which GCC version you are looking at. They changed it
sometime in the early GCC 4 days.
Right... gcc 4.4 which is well before NetBSD had an arm64/aarch64 port.
Nick
Re: CVS commit: src/common/lib/libc/arch/aarch64/atomic
On Sun, Jul 04, 2021 at 06:55:47AM +, Nick Hudson wrote:
> Module Name: src
> Committed By: skrll
> Date: Sun Jul 4 06:55:47 UTC 2021
>
> Modified Files:
> src/common/lib/libc/arch/aarch64/atomic: atomic_nand_16.S
> atomic_nand_32.S atomic_nand_64.S atomic_nand_8.S
>
> Log Message:
> Fix the logic operation for atomic_nand_{8,16,32,64}
>
> From the gcc docs the operations are as follows
>
> { tmp = *ptr; *ptr = ~(tmp & value); return tmp; } // nand
> { tmp = ~(*ptr & value); *ptr = tmp; return *ptr; } // nand
>
> yes, this is really rather strange.
This depends on which GCC version you are looking at. They changed it
sometime in the early GCC 4 days.
Joerg
Re: CVS commit: src/common/lib/libc/arch
On Sat, Feb 01, 2020 at 03:02:02PM +, m...@netbsd.org wrote: > On Mon, Jan 27, 2020 at 10:09:21PM +, Andrew Doran wrote: > > Module Name:src > > Committed By: ad > > Date: Mon Jan 27 22:09:21 UTC 2020 > > > > Removed Files: > > src/common/lib/libc/arch/i386/string: memcmp.S > > src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S > > > > Log Message: > > x86 uses the C versions of bcmp() and memcmp() now. > > > > Why? REP CMPS is very slow on the modern CPUs I have access to. The updated C version is 1.5-10x faster in the configurations I have tried, from tiny strings up to N-megabyte strings. MOVS and STOS are very good though. Andrew
Re: CVS commit: src/common/lib/libc/arch
On Mon, Jan 27, 2020 at 10:09:21PM +, Andrew Doran wrote: > Module Name: src > Committed By: ad > Date: Mon Jan 27 22:09:21 UTC 2020 > > Removed Files: > src/common/lib/libc/arch/i386/string: memcmp.S > src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S > > Log Message: > x86 uses the C versions of bcmp() and memcmp() now. > Why?
Re: CVS commit: src/common/lib/libc/arch/x86_64/string
Sorry for answering out of thread, but the message is long gone.
I just remembered very old x86 code of mine.
More than fifteen years ago it was still faster to go for 32-bit
wide testing when more than 20 bytes had to be compared, and to
redo a short byte loop to work around the fact that the carry flag
stats the wrong byteorder for the matching slot.
Maybe of interest.
|Andrew Doran writes:
|> Hi,
|>
|> Change backed out. Sorry about the disruption.
/// MEMCMP - sir (*)(const void *_ba, const void *_bb, uir _bytes)
#undef FUN
#undef FUN_STR
#define FUN __XX_mem_Compare
#define FUN_STR "sir XXX::Mem::Utils::Compare(const void*,const void*,uir)"
ASSERT_FUNVARS_STR()
NYD_FUNVARS_STR()
.global G(FUN)
.type G(FUN), @function
G(FUN):
pushl %edi
pushl %esi
.if __ALL
GET_GOT()
NYDIN()
.endif
.if SF_DEBUG
movl PICSO(12)(%esp), %eax // _ba
testl %eax, %eax
jnz 1f
ASSERT_CRASH("_ba != NIL")
1:
movl PICSO(16)(%esp), %eax // _bb
testl %eax, %eax
jnz 2f
ASSERT_CRASH("_bb != NIL")
2:
.endif
// load args (_ba, _bb, _bytes)
movl __PICSO(12)(%esp), %esi
movl __PICSO(16)(%esp), %edi
movl __PICSO(20)(%esp), %ecx
cld // forward cried the man from the rear
xorl %edx, %edx // default return
cmpl $20, %ecx // byte loop?
jle 7f
1: // align at least one on ui4 boundary; use a bytewise loop for that
testl $3, %esi
jz 2f
cmpsb
jne 8f // query result (CF)
decl %ecx
jmp 1b
2: // perform a uir loop; does not help us much due to the little endian
// byte order, but gives us at least an equality indication..
// (and is much faster than the byteloop ...)
movl %ecx, %eax // save bytecount
shrl $2, %ecx // >> Register::shift
repz cmpsl
jne 3f
movb %al, %cl // restore rem. bytecount
andl $3, %ecx // max. two bits remain (<= 3)
jz 9f
jmp 7f // to the byte loop please
3: // we have found an unequal slot, but CF aka the result is based on
// the "wrong" byte order. this is not easy to solve, thus simply
// adjust the pointers and the count and restart the byte loop.
// doing so is easier than the other thinkable approaches?
movl $4, %eax // avoid immediate ops..
subl %eax, %esi
subl %eax, %edi
addl %eax, %ecx
7: // byte loop
repz cmpsb
je 9f
8: // have result, calculate it accordingly (edx is still 0)
sbbl %edx, %edx // a -= b+CF --> 0 || -1 (borrow sub)
orb $1, %dl // 1 or still -1
9: // and finalize
movl %edx, %eax // overtake result into eax
.if __ALL
NYDOUT()
UNGET_GOT()
.endif
popl %esi
popl %edi
ret
.size G(FUN), .-G(FUN)
.align 16
// /__XX_mem_Compare
--steffen
|
|Der Kragenbaer,The moon bear,
|der holt sich munter he cheerfully and one by one
|einen nach dem anderen runter wa.ks himself off
|(By Robert Gernhardt)
Re: CVS commit: src/common/lib/libc/arch/x86_64/string
Hi, Andrew Doran writes: > Hi, > > Change backed out. Sorry about the disruption. Thank you. The back-out works fine for me. > Andrew > > On Thu, Jan 16, 2020 at 05:30:20PM +0900, Ryo ONODERA wrote: >> Hi, >> >> pkgsrc/www/firefox and mail/notmuch are also >> broken after this commit. >> >> >> On January 16, 2020 5:23:47 PM GMT+09:00, Kamil Rytarowski >> wrote: >> >On 15.01.2020 11:56, Andrew Doran wrote: >> >> Module Name: src >> >> Committed By: ad >> >> Date: Wed Jan 15 10:56:49 UTC 2020 >> >> >> >> Modified Files: >> >> src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S >> >> >> >> Log Message: >> >> Rewrite bcmp() & memcmp() to not use REP CMPS. Seems about 5-10x >> >faster for >> >> small strings on modern hardware. >> >> >> >> >> >> To generate a diff of this commit: >> >> cvs rdiff -u -r1.3 -r1.4 >> >src/common/lib/libc/arch/x86_64/string/bcmp.S \ >> >> src/common/lib/libc/arch/x86_64/string/memcmp.S >> >> >> >> Please note that diffs are not public domain; they are subject to the >> >> copyright notices on the relevant files. >> >> >> > >> >This exact change broke git: >> > >> >$ git clone g...@github.com:anphsw/memtest86.git >> >Cloning into 'memtest86'... >> >remote: Enumerating objects: 3, done. >> >remote: Counting objects: 100% (3/3), done. >> >remote: Compressing objects: 100% (3/3), done. >> >remote: Total 477 (delta 0), reused 1 (delta 0), pack-reused 474 >> >Receiving objects: 100% (477/477), 312.55 KiB | 984.00 KiB/s, done. >> >Resolving deltas: 100% (290/290), done. >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >error: wrong index v2 file size in >> >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >> >fatal: bad object 9da11d5d7eaa9f1a6a26c04c22b5422c886699a0 >> >fatal: remote did not send all necessary objects >> > >> >Userland is now broken. >> > >> >Please fix. >> >> -- >> Ryo ONODERA // r...@tetera.org >> PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3 -- Ryo ONODERA // r...@tetera.org PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: CVS commit: src/common/lib/libc/arch/x86_64/string
Hi, Change backed out. Sorry about the disruption. Andrew On Thu, Jan 16, 2020 at 05:30:20PM +0900, Ryo ONODERA wrote: > Hi, > > pkgsrc/www/firefox and mail/notmuch are also > broken after this commit. > > > On January 16, 2020 5:23:47 PM GMT+09:00, Kamil Rytarowski > wrote: > >On 15.01.2020 11:56, Andrew Doran wrote: > >> Module Name: src > >> Committed By: ad > >> Date: Wed Jan 15 10:56:49 UTC 2020 > >> > >> Modified Files: > >>src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S > >> > >> Log Message: > >> Rewrite bcmp() & memcmp() to not use REP CMPS. Seems about 5-10x > >faster for > >> small strings on modern hardware. > >> > >> > >> To generate a diff of this commit: > >> cvs rdiff -u -r1.3 -r1.4 > >src/common/lib/libc/arch/x86_64/string/bcmp.S \ > >> src/common/lib/libc/arch/x86_64/string/memcmp.S > >> > >> Please note that diffs are not public domain; they are subject to the > >> copyright notices on the relevant files. > >> > > > >This exact change broke git: > > > >$ git clone g...@github.com:anphsw/memtest86.git > >Cloning into 'memtest86'... > >remote: Enumerating objects: 3, done. > >remote: Counting objects: 100% (3/3), done. > >remote: Compressing objects: 100% (3/3), done. > >remote: Total 477 (delta 0), reused 1 (delta 0), pack-reused 474 > >Receiving objects: 100% (477/477), 312.55 KiB | 984.00 KiB/s, done. > >Resolving deltas: 100% (290/290), done. > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >error: wrong index v2 file size in > >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx > >fatal: bad object 9da11d5d7eaa9f1a6a26c04c22b5422c886699a0 > >fatal: remote did not send all necessary objects > > > >Userland is now broken. > > > >Please fix. > > -- > Ryo ONODERA // r...@tetera.org > PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: CVS commit: src/common/lib/libc/arch/x86_64/string
Hi, pkgsrc/www/firefox and mail/notmuch are also broken after this commit. On January 16, 2020 5:23:47 PM GMT+09:00, Kamil Rytarowski wrote: >On 15.01.2020 11:56, Andrew Doran wrote: >> Module Name: src >> Committed By:ad >> Date:Wed Jan 15 10:56:49 UTC 2020 >> >> Modified Files: >> src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S >> >> Log Message: >> Rewrite bcmp() & memcmp() to not use REP CMPS. Seems about 5-10x >faster for >> small strings on modern hardware. >> >> >> To generate a diff of this commit: >> cvs rdiff -u -r1.3 -r1.4 >src/common/lib/libc/arch/x86_64/string/bcmp.S \ >> src/common/lib/libc/arch/x86_64/string/memcmp.S >> >> Please note that diffs are not public domain; they are subject to the >> copyright notices on the relevant files. >> > >This exact change broke git: > >$ git clone g...@github.com:anphsw/memtest86.git >Cloning into 'memtest86'... >remote: Enumerating objects: 3, done. >remote: Counting objects: 100% (3/3), done. >remote: Compressing objects: 100% (3/3), done. >remote: Total 477 (delta 0), reused 1 (delta 0), pack-reused 474 >Receiving objects: 100% (477/477), 312.55 KiB | 984.00 KiB/s, done. >Resolving deltas: 100% (290/290), done. >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >error: wrong index v2 file size in >/public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx >fatal: bad object 9da11d5d7eaa9f1a6a26c04c22b5422c886699a0 >fatal: remote did not send all necessary objects > >Userland is now broken. > >Please fix. -- Ryo ONODERA // r...@tetera.org PGP fingerprint = 82A2 DC91 76E0 A10A 8ABB FD1B F404 27FA C7D1 15F3
Re: CVS commit: src/common/lib/libc/arch/x86_64/string
On 15.01.2020 11:56, Andrew Doran wrote: > Module Name: src > Committed By: ad > Date: Wed Jan 15 10:56:49 UTC 2020 > > Modified Files: > src/common/lib/libc/arch/x86_64/string: bcmp.S memcmp.S > > Log Message: > Rewrite bcmp() & memcmp() to not use REP CMPS. Seems about 5-10x faster for > small strings on modern hardware. > > > To generate a diff of this commit: > cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/x86_64/string/bcmp.S \ > src/common/lib/libc/arch/x86_64/string/memcmp.S > > Please note that diffs are not public domain; they are subject to the > copyright notices on the relevant files. > This exact change broke git: $ git clone g...@github.com:anphsw/memtest86.git Cloning into 'memtest86'... remote: Enumerating objects: 3, done. remote: Counting objects: 100% (3/3), done. remote: Compressing objects: 100% (3/3), done. remote: Total 477 (delta 0), reused 1 (delta 0), pack-reused 474 Receiving objects: 100% (477/477), 312.55 KiB | 984.00 KiB/s, done. Resolving deltas: 100% (290/290), done. error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx error: wrong index v2 file size in /public/memtest86/.git/objects/pack/pack-3baed7d30e4536c1173b6c083d81de217e9c829a.idx fatal: bad object 9da11d5d7eaa9f1a6a26c04c22b5422c886699a0 fatal: remote did not send all necessary objects Userland is now broken. Please fix. signature.asc Description: OpenPGP digital signature
CVS commit: src/common/lib/libc/arch/aarch64/gen
Module Name:src Committed By: maya Date: Sat Oct 12 09:22:36 UTC 2019 Modified Files: src/common/lib/libc/arch/aarch64/gen: byte_swap_8.S Log Message: Remove htonll and ntohll as symbols from aarch64 libc. Other architectures do not define them, and so we don't provide a function declaration in any header. This means a package may detect it with a link-test and then fail due to the missing declaration, like sysutils/collectd currently does. Done this way as aarch64 has not had a release yet. Discussed with releng. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/gen
Module Name:src Committed By: maya Date: Sat Oct 12 09:22:36 UTC 2019 Modified Files: src/common/lib/libc/arch/aarch64/gen: byte_swap_8.S Log Message: Remove htonll and ntohll as symbols from aarch64 libc. Other architectures do not define them, and so we don't provide a function declaration in any header. This means a package may detect it with a link-test and then fail due to the missing declaration, like sysutils/collectd currently does. Done this way as aarch64 has not had a release yet. Discussed with releng. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S diff -u src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S:1.1 src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S:1.2 --- src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S:1.1 Sun Aug 10 05:47:35 2014 +++ src/common/lib/libc/arch/aarch64/gen/byte_swap_8.S Sat Oct 12 09:22:36 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: byte_swap_8.S,v 1.1 2014/08/10 05:47:35 matt Exp $ */ +/* $NetBSD: byte_swap_8.S,v 1.2 2019/10/12 09:22:36 maya Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -41,7 +41,3 @@ ENTRY(FUNC) rev x0, x0 ret END(FUNC) -#if BYTE_ORDER == LITTLE_ENDIAN -STRONG_ALIAS(_C_LABEL(ntohll), FUNC) -STRONG_ALIAS(_C_LABEL(htonll), FUNC) -#endif
CVS commit: src/common/lib/libc/arch/arm/atomic
Module Name:src Committed By: skrll Date: Mon Sep 16 12:40:40 UTC 2019 Modified Files: src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h Log Message: Traiing whitespace. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h diff -u src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.7 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.8 --- src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h:1.7 Sun May 17 20:57:11 2015 +++ src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h Mon Sep 16 12:40:40 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic_op_asm.h,v 1.7 2015/05/17 20:57:11 justin Exp $ */ +/* $NetBSD: atomic_op_asm.h,v 1.8 2019/09/16 12:40:40 skrll Exp $ */ /*- * Copyright (c) 2007 The NetBSD Foundation, Inc. @@ -22,7 +22,7 @@ * 4. Neither the name of The NetBSD Foundation nor the names of its *contributors may be used to endorse or promote products derived *from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
CVS commit: src/common/lib/libc/arch/arm/atomic
Module Name:src Committed By: skrll Date: Mon Sep 16 12:40:40 UTC 2019 Modified Files: src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h Log Message: Traiing whitespace. To generate a diff of this commit: cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/atomic
Module Name:src
Committed By: skrll
Date: Sun Sep 15 14:55:04 UTC 2019
Modified Files:
src/common/lib/libc/arch/arm/atomic: atomic_or_64.S atomic_xor_64.S
Log Message:
__sync_{,x}or_and_fetch_8 should return new value... make it so.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/atomic/atomic_or_64.S
cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/arm/atomic
Module Name:src
Committed By: skrll
Date: Sun Sep 15 14:55:04 UTC 2019
Modified Files:
src/common/lib/libc/arch/arm/atomic: atomic_or_64.S atomic_xor_64.S
Log Message:
__sync_{,x}or_and_fetch_8 should return new value... make it so.
To generate a diff of this commit:
cvs rdiff -u -r1.10 -r1.11 src/common/lib/libc/arch/arm/atomic/atomic_or_64.S
cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/common/lib/libc/arch/arm/atomic/atomic_or_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.10 src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.11
--- src/common/lib/libc/arch/arm/atomic/atomic_or_64.S:1.10 Tue Mar 4 16:15:28 2014
+++ src/common/lib/libc/arch/arm/atomic/atomic_or_64.S Sun Sep 15 14:55:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_or_64.S,v 1.10 2014/03/04 16:15:28 matt Exp $ */
+/* $NetBSD: atomic_or_64.S,v 1.11 2019/09/15 14:55:04 skrll Exp $ */
/*-
* Copyright (c) 2012 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -57,6 +57,6 @@ END(_atomic_or_64_nv)
STRONG_ALIAS(_atomic_or_64,_atomic_or_64_nv)
ATOMIC_OP_ALIAS(atomic_or_64_nv,_atomic_or_64_nv)
ATOMIC_OP_ALIAS(atomic_or_64,_atomic_or_64)
-CRT_ALIAS(__sync_or_and_fetch_8,_atomic_or_64)
+CRT_ALIAS(__sync_or_and_fetch_8,_atomic_or_64_nv)
#endif /* _ARM_ARCH_6 */
Index: src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S
diff -u src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.3 src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.4
--- src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S:1.3 Tue Mar 4 16:15:28 2014
+++ src/common/lib/libc/arch/arm/atomic/atomic_xor_64.S Sun Sep 15 14:55:04 2019
@@ -1,4 +1,4 @@
-/* $NetBSD: atomic_xor_64.S,v 1.3 2014/03/04 16:15:28 matt Exp $ */
+/* $NetBSD: atomic_xor_64.S,v 1.4 2019/09/15 14:55:04 skrll Exp $ */
/*-
* Copyright (c) 2013 The NetBSD Foundation, Inc.
* All rights reserved.
@@ -57,6 +57,6 @@ END(_atomic_xor_64_nv)
STRONG_ALIAS(_atomic_xor_64,_atomic_xor_64_nv)
ATOMIC_OP_ALIAS(atomic_xor_64_nv,_atomic_xor_64_nv)
ATOMIC_OP_ALIAS(atomic_xor_64,_atomic_xor_64)
-CRT_ALIAS(__sync_xor_and_fetch_8,_atomic_xor_64)
+CRT_ALIAS(__sync_xor_and_fetch_8,_atomic_xor_64_nv)
#endif /* _ARM_ARCH_6 */
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sun Sep 15 11:14:15 UTC 2019 Modified Files: src/common/lib/libc/arch/aarch64/atomic: atomic_or_64.S Log Message: __sync_or_and_fetch_8 should return new value... make it do that. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 \ src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files.
CVS commit: src/common/lib/libc/arch/aarch64/atomic
Module Name:src Committed By: skrll Date: Sun Sep 15 11:14:15 UTC 2019 Modified Files: src/common/lib/libc/arch/aarch64/atomic: atomic_or_64.S Log Message: __sync_or_and_fetch_8 should return new value... make it do that. To generate a diff of this commit: cvs rdiff -u -r1.1 -r1.2 \ src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S diff -u src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S:1.1 src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S:1.2 --- src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S:1.1 Sun Aug 10 05:47:35 2014 +++ src/common/lib/libc/arch/aarch64/atomic/atomic_or_64.S Sun Sep 15 11:14:15 2019 @@ -1,4 +1,4 @@ -/* $NetBSD: atomic_or_64.S,v 1.1 2014/08/10 05:47:35 matt Exp $ */ +/* $NetBSD: atomic_or_64.S,v 1.2 2019/09/15 11:14:15 skrll Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -43,4 +43,4 @@ ATOMIC_OP64_NV(or, orr) STRONG_ALIAS(_atomic_or_ulong_nv,_atomic_or_64_nv) ATOMIC_OP_ALIAS(atomic_or_64_nv,_atomic_or_64_nv) ATOMIC_OP_ALIAS(atomic_or_ulong_nv,_atomic_or_64_nv) -STRONG_ALIAS(__sync_or_and_fetch_8,_atomic_or_64) +STRONG_ALIAS(__sync_or_and_fetch_8,_atomic_or_64_nv)
Re: CVS commit: src/common/lib/libc/arch/arm
On 17 May 2015 at 22:19, Justin Cormack wrote: > On 17 May 2015 at 22:02, Matt Thomas wrote: >> >>> On May 17, 2015, at 1:57 PM, Justin Cormack wrote: >>> >>> Module Name: src >>> Committed By: justin >>> Date: Sun May 17 20:57:12 UTC 2015 >>> >>> Modified Files: >>> src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h atomic_swap.S >>> atomic_swap_16.S atomic_swap_64.S sync_bool_compare_and_swap_1.S >>> sync_bool_compare_and_swap_2.S sync_bool_compare_and_swap_4.S >>> sync_bool_compare_and_swap_8.S sync_fetch_and_add_8.S >>> sync_fetch_and_and_8.S sync_fetch_and_nand_8.S >>> sync_fetch_and_or_8.S sync_fetch_and_sub_8.S >>> sync_fetch_and_xor_8.S >>> src/common/lib/libc/arch/arm/string: ffs.S > >> >> Most of these changes should have been in Makefile.inc, not in the sources >> themselves. Ok fixed now, sorry about that. justin
Re: CVS commit: src/common/lib/libc/arch/arm
On 17 May 2015 at 22:02, Matt Thomas wrote: > >> On May 17, 2015, at 1:57 PM, Justin Cormack wrote: >> >> Module Name: src >> Committed By: justin >> Date: Sun May 17 20:57:12 UTC 2015 >> >> Modified Files: >> src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h atomic_swap.S >> atomic_swap_16.S atomic_swap_64.S sync_bool_compare_and_swap_1.S >> sync_bool_compare_and_swap_2.S sync_bool_compare_and_swap_4.S >> sync_bool_compare_and_swap_8.S sync_fetch_and_add_8.S >> sync_fetch_and_and_8.S sync_fetch_and_nand_8.S >> sync_fetch_and_or_8.S sync_fetch_and_sub_8.S sync_fetch_and_xor_8.S >> src/common/lib/libc/arch/arm/string: ffs.S > > Most of these changes should have been in Makefile.inc, not in the sources > themselves. Ok, will rework those ones. Justin
Re: CVS commit: src/common/lib/libc/arch/arm
> On May 17, 2015, at 1:57 PM, Justin Cormack wrote: > > Module Name: src > Committed By: justin > Date: Sun May 17 20:57:12 UTC 2015 > > Modified Files: > src/common/lib/libc/arch/arm/atomic: atomic_op_asm.h atomic_swap.S > atomic_swap_16.S atomic_swap_64.S sync_bool_compare_and_swap_1.S > sync_bool_compare_and_swap_2.S sync_bool_compare_and_swap_4.S > sync_bool_compare_and_swap_8.S sync_fetch_and_add_8.S > sync_fetch_and_and_8.S sync_fetch_and_nand_8.S > sync_fetch_and_or_8.S sync_fetch_and_sub_8.S sync_fetch_and_xor_8.S > src/common/lib/libc/arch/arm/string: ffs.S > > Log Message: > Do not build arm toolchain symbols in the rump kernel > > These symbols will be provided at link time and will be > duplicate symbols in rump kernel and libc if defined. > > Many have been fixed previously, but these were missed > as did not have a test. > > > To generate a diff of this commit: > cvs rdiff -u -r1.6 -r1.7 src/common/lib/libc/arch/arm/atomic/atomic_op_asm.h > cvs rdiff -u -r1.13 -r1.14 src/common/lib/libc/arch/arm/atomic/atomic_swap.S > cvs rdiff -u -r1.3 -r1.4 src/common/lib/libc/arch/arm/atomic/atomic_swap_16.S > \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_add_8.S \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_and_8.S \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_or_8.S \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_sub_8.S \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_xor_8.S > cvs rdiff -u -r1.9 -r1.10 \ > src/common/lib/libc/arch/arm/atomic/atomic_swap_64.S > cvs rdiff -u -r1.1 -r1.2 \ > src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_1.S \ > src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_2.S \ > src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_4.S > cvs rdiff -u -r1.2 -r1.3 \ > src/common/lib/libc/arch/arm/atomic/sync_bool_compare_and_swap_8.S \ > src/common/lib/libc/arch/arm/atomic/sync_fetch_and_nand_8.S > cvs rdiff -u -r1.7 -r1.8 src/common/lib/libc/arch/arm/string/ffs.S > > Please note that diffs are not public domain; they are subject to the > copyright notices on the relevant files. Most of these changes should have been in Makefile.inc, not in the sources themselves.
Re: CVS commit: src/common/lib/libc/arch/i386/string/small
On Mon, Sep 22, 2014 at 08:31:56PM +, Pierre Pronchery wrote: > Module Name: src > Committed By: khorben > Date: Mon Sep 22 20:31:56 UTC 2014 > > Modified Files: > src/common/lib/libc/arch/i386/string/small: strchr.S > > Log Message: > Look for the character to locate before checking for the NUL character > > As documented in PR port-i386/49208, this fixes strchr(s, '\0'), as used by > the FAT first-stage bootloader on x86 (bootxx_msdos). > strchr(s, '\0') is otherwise equivalent to strlen(string), which would > probably look nicer in the original file, dosfs.c from libsa. FWIW 'strchr(s, 0)' is actually 's + strlen(s)' David -- David Laight: da...@l8s.co.uk
Re: CVS commit: src/common/lib/libc/arch/arm/atomic
On 11/09/13 08:29, Jukka Ruohonen wrote: On Fri, Nov 08, 2013 at 10:42:52PM +, Matt Thomas wrote: Log Message: Add support for the gcc __sync builtins. A stupid but important question: what is __sync? - Jukka. http://gcc.gnu.org/onlinedocs/gcc-4.8.2/gcc/_005f_005fsync-Builtins.html#g_t_005f_005fsync-Builtins hmm Nick
Re: CVS commit: src/common/lib/libc/arch/arm/atomic
On Fri, Nov 08, 2013 at 10:42:52PM +, Matt Thomas wrote: > Log Message: > Add support for the gcc __sync builtins. A stupid but important question: what is __sync? - Jukka.
Re: CVS commit: src/common/lib/libc/arch/m68k
> Module Name: src > Committed By: matt > Date: Thu Jul 18 22:42:51 UTC 2013 > > Modified Files: > src/common/lib/libc/arch/m68k/gen: bswap16.S bswap32.S bswap64.S > src/common/lib/libc/arch/m68k/string: bcmp.S bcopy.S bzero.S ffs.S > memcmp.S memset.S strcmp.S strncmp.S strncpy.S > > Log Message: > Adjust for Coldfire These changes break traditional m68k ports. (struct uvm seems corrupted probably memset etc and kernel doesn't boot) Please revert and create a branch for coldfire if you can't debug your changes on m68k. --- Izumi Tsutsui
Re: CVS commit: src/common/lib/libc/arch/m68k/string
> Module Name: src > Committed By: matt > Date: Fri Jul 19 16:42:12 UTC 2013 > > Modified Files: > src/common/lib/libc/arch/m68k/string: memset.S strcmp.S strncmp.S > > Log Message: > With these changes, they now produce identical binary as before the coldfire > changes. ... and please post proper announcements if you have fixed dumb but fatal bugs per reports on public lists. It's so annoying for users to track problems without descriptions. Thanks, --- Izumi Tsutsui
Re: CVS commit: src/common/lib/libc/arch/arm/string
On Jan 15, 2013, at 12:10 AM, David Laight wrote: > On Tue, Jan 15, 2013 at 02:03:31AM +, Matt Thomas wrote: >> Module Name: src >> Committed By:matt >> Date:Tue Jan 15 02:03:31 UTC 2013 >> >> Added Files: >> src/common/lib/libc/arch/arm/string: strchr_naive.S strrchr_naive.S >> >> Log Message: >> Add simple/small versions of strchr/strrchr for ARM. > > If you use 'preindex with writeback' you can remove an instruction > from the loop (in strchr at least). I pretty much already do that. > I'm also intrigued that these are the very simple/small versions > whereas the memcpy() (I think) was one that did all the alignment > and double-word copies! As I said in its commit, the stupid version was very very slow.
Re: CVS commit: src/common/lib/libc/arch/arm/string
On Tue, Jan 15, 2013 at 02:03:31AM +, Matt Thomas wrote: > Module Name: src > Committed By: matt > Date: Tue Jan 15 02:03:31 UTC 2013 > > Added Files: > src/common/lib/libc/arch/arm/string: strchr_naive.S strrchr_naive.S > > Log Message: > Add simple/small versions of strchr/strrchr for ARM. If you use 'preindex with writeback' you can remove an instruction from the loop (in strchr at least). I'm also intrigued that these are the very simple/small versions whereas the memcpy() (I think) was one that did all the alignment and double-word copies! David -- David Laight: da...@l8s.co.uk
