CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Fri Jan 2 23:23:17 UTC 2015
Modified Files:
src/sys/arch/arm/rockchip: obio.c
Log Message:
back out r1.8, its fine (and preferred) to write value before direction reg
To generate a diff of this commit:
cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/rockchip/obio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.9 src/sys/arch/arm/rockchip/obio.c:1.10
--- src/sys/arch/arm/rockchip/obio.c:1.9 Fri Jan 2 21:59:29 2015
+++ src/sys/arch/arm/rockchip/obio.c Fri Jan 2 23:23:17 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.9 2015/01/02 21:59:29 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.10 2015/01/02 23:23:17 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -38,7 +38,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.9 2015/01/02 21:59:29 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.10 2015/01/02 23:23:17 jmcneill Exp $);
#include sys/param.h
#include sys/systm.h
@@ -237,22 +237,22 @@ void obio_init_gpio(void)
{
#if 1
/* Radxa Rock */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
- obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
/* IT66121 HDMI */
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(10));
obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(10));
+ obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(10));
#else
/* ChipSPARK Rayeager PX2 */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(5));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(6));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(5));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(6));
- obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(6));
obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
#endif
}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Thu Jan 1 15:18:45 UTC 2015
Modified Files:
src/sys/arch/arm/rockchip: rockchip_i2c.c
Log Message:
drop clk rate to 100kHz, explicit register initialization, shift slave addr
left 1, add some more debugging, now this works
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_i2c.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_i2c.c
diff -u src/sys/arch/arm/rockchip/rockchip_i2c.c:1.3 src/sys/arch/arm/rockchip/rockchip_i2c.c:1.4
--- src/sys/arch/arm/rockchip/rockchip_i2c.c:1.3 Tue Dec 30 18:57:36 2014
+++ src/sys/arch/arm/rockchip/rockchip_i2c.c Thu Jan 1 15:18:45 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_i2c.c,v 1.3 2014/12/30 18:57:36 jmcneill Exp $ */
+/* $NetBSD: rockchip_i2c.c,v 1.4 2015/01/01 15:18:45 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -30,7 +30,7 @@
#include opt_rkiic.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.3 2014/12/30 18:57:36 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.4 2015/01/01 15:18:45 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -48,7 +48,7 @@ __KERNEL_RCSID(0, $NetBSD: rockchip_i2c
#include dev/i2c/i2cvar.h
-#define RKIIC_CLOCK_RATE 40
+#define RKIIC_CLOCK_RATE 10
struct rkiic_softc {
device_t sc_dev;
@@ -129,6 +129,14 @@ rkiic_attach(device_t parent, device_t s
}
}
+ if (rkiic_set_rate(sc, RKIIC_CLOCK_RATE) != 0) {
+ aprint_error_dev(sc-sc_dev, couldn't set clock rate\n);
+ return;
+ }
+
+ I2C_WRITE(sc, I2C_CON_REG, 0);
+ I2C_WRITE(sc, I2C_IEN_REG, 0);
+
sc-sc_ic.ic_cookie = sc;
sc-sc_ic.ic_acquire_bus = rkiic_acquire_bus;
sc-sc_ic.ic_release_bus = rkiic_release_bus;
@@ -151,6 +159,10 @@ rkiic_intr(void *priv)
I2C_WRITE(sc, I2C_IPD_REG, ipd);
+#ifdef RKIIC_INTR
+ device_printf(sc-sc_dev, %s: ipd %#x\n, __func__, ipd);
+#endif
+
mutex_enter(sc-sc_lock);
sc-sc_intr_ipd |= ipd;
cv_broadcast(sc-sc_cv);
@@ -183,12 +195,12 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
{
struct rkiic_softc *sc = priv;
uint32_t con, ien;
- u_int mode;
+ u_int mode, sraddr;
int error;
KASSERT(mutex_owned(sc-sc_lock));
- if (sc-sc_ih == NULL) {
+ if (sc-sc_ih == NULL || cold) {
flags |= I2C_F_POLL;
}
@@ -199,30 +211,27 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
if (error)
return error;
- I2C_WRITE(sc, I2C_MRXADDR_REG, I2C_MRXADDR_ADDLVLD |
- __SHIFTIN(addr, I2C_MRXADDR_SADDR));
-
if (cmdlen == 1) {
- const uint8_t reg = *(const uint8_t *)cmdbuf;
if (I2C_OP_READ_P(op)) {
mode = I2C_CON_MODE_TRX;
} else {
mode = I2C_CON_MODE_TX;
}
- I2C_WRITE(sc, I2C_MRXRADDR_REG, I2C_MRXRADDR_SRADDLVLD |
- __SHIFTIN(reg, I2C_MRXRADDR_SRADDR));
+ sraddr = *(const uint8_t *)cmdbuf;
} else {
if (I2C_OP_READ_P(op)) {
mode = I2C_CON_MODE_RX;
} else {
mode = I2C_CON_MODE_TX;
}
- I2C_WRITE(sc, I2C_MRXRADDR_REG, 0);
+ sraddr = 0;
}
sc-sc_intr_ipd = 0;
+ I2C_WRITE(sc, I2C_IPD_REG, I2C_READ(sc, I2C_IPD_REG));
- ien = I2C_INT_START | (I2C_OP_READ_P(op) ? I2C_INT_MBRF : I2C_INT_MBTF);
+ ien = I2C_OP_READ_P(op) ? I2C_INT_MBRF : I2C_INT_MBTF;
+ ien |= I2C_INT_START | I2C_INT_STOP | I2C_INT_NAKRCV;
I2C_WRITE(sc, I2C_IEN_REG, ien);
con = I2C_CON_START | I2C_CON_EN | I2C_CON_ACK |
@@ -236,6 +245,13 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
#endif
goto done;
}
+ con = ~I2C_CON_START;
+ I2C_WRITE(sc, I2C_CON_REG, con);
+
+ I2C_WRITE(sc, I2C_MRXADDR_REG, I2C_MRXADDR_ADDLVLD |
+ __SHIFTIN((addr 1), I2C_MRXADDR_SADDR));
+ I2C_WRITE(sc, I2C_MRXRADDR_REG, I2C_MRXRADDR_SRADDLVLD |
+ __SHIFTIN(sraddr, I2C_MRXRADDR_SRADDR));
if (I2C_OP_READ_P(op)) {
error = rkiic_read(sc, addr, buf, len, flags);
@@ -244,10 +260,22 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
}
if (I2C_OP_STOP_P(op)) {
- I2C_WRITE(sc, I2C_CON_REG, I2C_CON_STOP);
+ con = I2C_READ(sc, I2C_CON_REG);
+ con |= I2C_CON_STOP;
+ I2C_WRITE(sc, I2C_CON_REG, con);
+ if (rkiic_wait(sc, I2C_INT_STOP, hz, flags) != 0) {
+#ifdef RKIIC_DEBUG
+ device_printf(sc-sc_dev, timeout waiting for stop\n);
+#endif
+ error = ETIMEDOUT;
+ goto done;
+ }
+ con = ~I2C_CON_STOP;
+ I2C_WRITE(sc, I2C_CON_REG, con);
}
done:
+ I2C_WRITE(sc, I2C_CON_REG, 0);
I2C_WRITE(sc, I2C_IEN_REG, 0);
return error;
}
@@ -283,6 +311,9 @@ rkiic_wait(struct rkiic_softc *sc, uint3
}
}
+#ifdef RKIIC_DEBUG
+ device_printf(sc-sc_dev, %s: ipd %#x\n, __func__, sc-sc_intr_ipd);
+#endif
return ETIMEDOUT;
}
@@ -307,6 +338,13 @@ rkiic_read(struct rkiic_softc *sc, i2c_a
return error;
}
+ if (sc-sc_intr_ipd I2C_INT_NAKRCV) {
+#ifdef RKIIC_DEBUG
+ device_printf(sc-sc_dev, nak received\n);
+#endif
+ return EIO;
+ }
+
for (off = 0, resid = buflen; off 8 resid 0; off++) {
const
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Thu Jan 1 13:32:24 UTC 2015 Modified Files: src/sys/arch/arm/rockchip: obio.c Log Message: RK3188 I2C iomux init To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/obio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/obio.c diff -u src/sys/arch/arm/rockchip/obio.c:1.5 src/sys/arch/arm/rockchip/obio.c:1.6 --- src/sys/arch/arm/rockchip/obio.c:1.5 Tue Dec 30 17:15:31 2014 +++ src/sys/arch/arm/rockchip/obio.c Thu Jan 1 13:32:24 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: obio.c,v 1.5 2014/12/30 17:15:31 jmcneill Exp $ */ +/* $NetBSD: obio.c,v 1.6 2015/01/01 13:32:24 jmcneill Exp $ */ /* * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. @@ -38,7 +38,7 @@ #include opt_rockchip.h #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.5 2014/12/30 17:15:31 jmcneill Exp $); +__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.6 2015/01/01 13:32:24 jmcneill Exp $); #include sys/param.h #include sys/systm.h @@ -169,11 +169,29 @@ obio_search(device_t parent, cfdata_t cf return 0; } +#define RK3188_GRF_GPIO0C_IOMUX_OFFSET 0x0068 +#define RK3188_GRF_GPIO0D_IOMUX_OFFSET 0x006C + +#define RK3188_GRF_GPIO1A_IOMUX_OFFSET 0x0070 +#define RK3188_GRF_GPIO1B_IOMUX_OFFSET 0x0074 +#define RK3188_GRF_GPIO1C_IOMUX_OFFSET 0x0078 +#define RK3188_GRF_GPIO1D_IOMUX_OFFSET 0x007C + +#define RK3188_GRF_GPIO2A_IOMUX_OFFSET 0x0080 +#define RK3188_GRF_GPIO2B_IOMUX_OFFSET 0x0084 +#define RK3188_GRF_GPIO2C_IOMUX_OFFSET 0x0088 +#define RK3188_GRF_GPIO2D_IOMUX_OFFSET 0x008C + #define RK3188_GRF_GPIO3A_IOMUX_OFFSET 0x0090 #define RK3188_GRF_GPIO3B_IOMUX_OFFSET 0x0094 #define RK3188_GRF_GPIO3C_IOMUX_OFFSET 0x0098 #define RK3188_GRF_GPIO3D_IOMUX_OFFSET 0x009C +#define RK3188_GRF_SOC_CON0_OFFSET 0x00A0 +#define RK3188_GRF_SOC_CON1_OFFSET 0x00A4 +#define RK3188_GRF_SOC_CON2_OFFSET 0x00A8 +#define RK3188_GRF_SOC_STATUS_OFFSET 0x00AC + #define GRF_GPIO0A_IOMUX_OFFSET 0x00a8 #define GRF_GPIO3A_IOMUX_OFFSET 0x00d8 #define GRF_GPIO3B_IOMUX_OFFSET 0x00dc @@ -185,6 +203,9 @@ void obio_init_grf(void) obio_iomux(RK3188_GRF_GPIO3A_IOMUX_OFFSET, 0x5554); /* MMC0 */ obio_iomux(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0x00050001); /* MMC0 */ obio_iomux(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x3c00); /* VBUS */ + obio_iomux(RK3188_GRF_GPIO1D_IOMUX_OFFSET, 0x); /* I2C[0124] */ + obio_iomux(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0xa000a000); /* I2C3 */ + obio_iomux(RK3188_GRF_SOC_CON1_OFFSET, 0xf800f800); /* I2C[01234] */ #else /* ChipSPARK Rayeager PX2 */ obio_iomux(GRF_GPIO0A_IOMUX_OFFSET, 0x1400); /* VBUS */
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Thu Jan 1 22:15:40 UTC 2015
Modified Files:
src/sys/arch/arm/rockchip: rockchip_i2c.c
Log Message:
Include addr and reg in data sent with rkiic_write, now writes work too.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rockchip_i2c.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_i2c.c
diff -u src/sys/arch/arm/rockchip/rockchip_i2c.c:1.4 src/sys/arch/arm/rockchip/rockchip_i2c.c:1.5
--- src/sys/arch/arm/rockchip/rockchip_i2c.c:1.4 Thu Jan 1 15:18:45 2015
+++ src/sys/arch/arm/rockchip/rockchip_i2c.c Thu Jan 1 22:15:40 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_i2c.c,v 1.4 2015/01/01 15:18:45 jmcneill Exp $ */
+/* $NetBSD: rockchip_i2c.c,v 1.5 2015/01/01 22:15:40 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -30,7 +30,7 @@
#include opt_rkiic.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.4 2015/01/01 15:18:45 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.5 2015/01/01 22:15:40 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -207,6 +207,14 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
if (cmdlen != 0 cmdlen != 1)
return EINVAL;
+ if (I2C_OP_READ_P(op)) {
+ if (len 32)
+ return EINVAL;
+ } else {
+ if (len 30)
+ return EINVAL;
+ }
+
error = rkiic_set_rate(sc, RKIIC_CLOCK_RATE);
if (error)
return error;
@@ -256,7 +264,15 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
if (I2C_OP_READ_P(op)) {
error = rkiic_read(sc, addr, buf, len, flags);
} else {
- error = rkiic_write(sc, addr, buf, len, flags);
+ uint8_t tmp_buf[32];
+ tmp_buf[0] = addr 1;
+ if (cmdlen == 1) {
+ tmp_buf[1] = sraddr;
+ memcpy(tmp_buf[2], buf, len);
+ } else {
+ memcpy(tmp_buf[1], buf, len);
+ }
+ error = rkiic_write(sc, addr, tmp_buf, len + cmdlen + 1, flags);
}
if (I2C_OP_STOP_P(op)) {
@@ -369,7 +385,7 @@ rkiic_write(struct rkiic_softc *sc, i2c_
for (off = 0, resid = buflen; off 8 resid 0; off++) {
uint32_t data = 0;
for (byte = 0; byte 4 resid 0; byte++, resid--) {
- data |= buf[off * 4 + byte] (byte * 8);
+ data |= (uint32_t)buf[off * 4 + byte] (byte * 8);
}
I2C_WRITE(sc, I2C_TXDATA_REG(off), data);
}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Thu Jan 1 18:59:03 UTC 2015
Modified Files:
src/sys/arch/arm/rockchip: obio.c
Log Message:
obio_init_gpio: set pin direction to output before writing data
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/obio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.7 src/sys/arch/arm/rockchip/obio.c:1.8
--- src/sys/arch/arm/rockchip/obio.c:1.7 Thu Jan 1 18:25:52 2015
+++ src/sys/arch/arm/rockchip/obio.c Thu Jan 1 18:59:03 2015
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.7 2015/01/01 18:25:52 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.8 2015/01/01 18:59:03 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -38,7 +38,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.7 2015/01/01 18:25:52 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.8 2015/01/01 18:59:03 jmcneill Exp $);
#include sys/param.h
#include sys/systm.h
@@ -237,22 +237,22 @@ void obio_init_gpio(void)
{
#if 1
/* Radxa Rock */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
- obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
/* IT66121 HDMI */
- obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(10));
obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(10));
+ obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(10));
#else
/* ChipSPARK Rayeager PX2 */
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(5));
- obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(6));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(6));
- obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(6));
obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
#endif
}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Thu Jan 1 18:25:52 UTC 2015 Modified Files: src/sys/arch/arm/rockchip: obio.c Log Message: IT66121 HDMI transmitter GPIO setup To generate a diff of this commit: cvs rdiff -u -r1.6 -r1.7 src/sys/arch/arm/rockchip/obio.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/obio.c diff -u src/sys/arch/arm/rockchip/obio.c:1.6 src/sys/arch/arm/rockchip/obio.c:1.7 --- src/sys/arch/arm/rockchip/obio.c:1.6 Thu Jan 1 13:32:24 2015 +++ src/sys/arch/arm/rockchip/obio.c Thu Jan 1 18:25:52 2015 @@ -1,4 +1,4 @@ -/* $NetBSD: obio.c,v 1.6 2015/01/01 13:32:24 jmcneill Exp $ */ +/* $NetBSD: obio.c,v 1.7 2015/01/01 18:25:52 jmcneill Exp $ */ /* * Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc. @@ -38,7 +38,7 @@ #include opt_rockchip.h #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.6 2015/01/01 13:32:24 jmcneill Exp $); +__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.7 2015/01/01 18:25:52 jmcneill Exp $); #include sys/param.h #include sys/systm.h @@ -241,6 +241,10 @@ void obio_init_gpio(void) obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3)); obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31)); obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31)); + + /* IT66121 HDMI */ + obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(10)); + obio_swporta(ROCKCHIP_GPIO3_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(10)); #else /* ChipSPARK Rayeager PX2 */ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Wed Dec 31 18:09:06 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_board.c
Log Message:
Cleanup freq setting a bit. Add a table of supported rates in ~200MHz steps
from 600MHz to 1608MHz, and let the cpu.frequency parameter match the
closest available freq (without going over +50MHz).
After updating APLL, wait for PLL lock.
Do APLL changes with PLL mode set to slow, rather than the previous
(and more complex) APLL/GPLL dance.
To generate a diff of this commit:
cvs rdiff -u -r1.8 -r1.9 src/sys/arch/arm/rockchip/rockchip_board.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.8 src/sys/arch/arm/rockchip/rockchip_board.c:1.9
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.8 Wed Dec 31 16:16:35 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Wed Dec 31 18:09:05 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -29,7 +29,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -83,6 +83,13 @@ rockchip_get_cru_bsh(bus_space_handle_t
ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, pbsh);
}
+static void
+rockchip_get_grf_bsh(bus_space_handle_t *pbsh)
+{
+ bus_space_subregion(rockchip_bs_tag, rockchip_core1_bsh,
+ ROCKCHIP_GRF_OFFSET, ROCKCHIP_GRF_SIZE, pbsh);
+}
+
static u_int
rockchip_pll_get_rate(bus_size_t con0_reg, bus_size_t con1_reg)
{
@@ -127,80 +134,68 @@ rockchip_apll_get_rate(void)
return rockchip_pll_get_rate(CRU_APLL_CON0_REG, CRU_APLL_CON1_REG);
}
+struct rk3188_apll_rate {
+ u_int rate;
+ u_int nr, nf, no;
+ u_int core_div, core_periph_div, core_axi_div;
+ u_int aclk_div, hclk_div, pclk_div, ahb2apb_div;
+};
+
+#define RK3188_RATE(_r, _nf, _no, _p, _a, _aclk, _hclk, _pclk, _ahb2apb) \
+ { .rate = (_r) * 100, .nr = 1, .nf = (_nf), .no = (_no), \
+ .core_div = 1, .core_periph_div = (_p), .core_axi_div = (_a), \
+ .aclk_div = (_aclk), .hclk_div = (_hclk), .pclk_div = (_pclk), \
+ .ahb2apb_div = (_ahb2apb) }
+
+static const struct rk3188_apll_rate rk3188_apll_rates[] = {
+ RK3188_RATE(1608, 67, 1, 8, 4, 4, 2, 4, 2),
+ RK3188_RATE(1416, 59, 1, 8, 4, 4, 2, 4, 2),
+ RK3188_RATE(1200, 50, 1, 8, 4, 4, 2, 4, 2),
+ RK3188_RATE(1008, 42, 1, 8, 3, 3, 2, 4, 2),
+ RK3188_RATE( 816, 68, 2, 8, 4, 3, 2, 4, 2),
+ RK3188_RATE( 600, 50, 2, 4, 4, 3, 2, 4, 2),
+};
+
+#define RK3188_GRF_STATUS0_REG 0x00ac
+#define RK3188_GRF_STATUS0_APLL_LOCK __BIT(6)
+
static u_int
rk3188_apll_set_rate(u_int rate)
{
+ const struct rk3188_apll_rate *r = NULL;
bus_space_tag_t bst = rockchip_bs_tag;
- bus_space_handle_t bsh;
+ bus_space_handle_t bsh, grf_bsh;
uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
uint32_t reset_mask, reset;
- u_int no, nr, nf, core_div, core_periph_div, core_axi_div,
- aclk_div, hclk_div, pclk_div, ahb2apb_div;
u_int cpu_aclk_div_con;
const bool rk3188plus_p = rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS);
rockchip_get_cru_bsh(bsh);
+ rockchip_get_grf_bsh(grf_bsh);
#ifdef ROCKCHIP_CLOCK_DEBUG
printf(%s: rate=%u rk3188plus_p=%d\n, __func__, rate, rk3188plus_p);
#endif
- switch (rate) {
- case 160800:
- nr = 1;
- nf = 67;
- no = 1;
- core_div = 1;
- core_periph_div = 8;
- core_axi_div = 4;
- aclk_div = 4;
- hclk_div = 2;
- pclk_div = 4;
- ahb2apb_div = 2;
- break;
- case 141600:
- nr = 1;
- nf = 59;
- no = 1;
- core_div = 1;
- core_periph_div = 8;
- core_axi_div = 4;
- aclk_div = 4;
- hclk_div = 2;
- pclk_div = 4;
- ahb2apb_div = 2;
- break;
- case 100800:
- nr = 1;
- nf = 42;
- no = 1;
- core_div = 1;
- core_periph_div = 8;
- core_axi_div = 3;
- aclk_div = 3;
- hclk_div = 2;
- pclk_div = 4;
- ahb2apb_div = 2;
- break;
- case 6:
- nr = 1;
- nf = 50;
- no = 2;
- core_div = 1;
- core_periph_div = 4;
- core_axi_div = 4;
- aclk_div = 3;
- hclk_div = 2;
- pclk_div = 4;
- ahb2apb_div = 2;
- break;
- default:
+ /* Pick the closest rate (nearest 100MHz increment) */
+ for (int i = 0; i __arraycount(rk3188_apll_rates); i++) {
+ u_int trate = rate / 100;
+ u_int arate = ((rk3188_apll_rates[i].rate / 100) + 50)
+ / 100 * 100;
+ if (arate = trate) {
+ r = rk3188_apll_rates[i];
+ break;
+ }
+ }
+ if (r == NULL) {
#ifdef ROCKCHIP_CLOCK_DEBUG
- printf(%s: unsupported rate %u\n, __func__, rate);
+ printf(CPU: No matching rate found for %u MHz\n, rate);
#endif
- return EINVAL;
+ return
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Wed Dec 31 18:08:58 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_crureg.h Log Message: add some more bits To generate a diff of this commit: cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/rockchip_crureg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_crureg.h diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.5 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.6 --- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.5 Tue Dec 30 03:53:52 2014 +++ src/sys/arch/arm/rockchip/rockchip_crureg.h Wed Dec 31 18:08:58 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_crureg.h,v 1.5 2014/12/30 03:53:52 jmcneill Exp $ */ +/* $NetBSD: rockchip_crureg.h,v 1.6 2014/12/31 18:08:58 jmcneill Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca @@ -62,7 +62,12 @@ #define CRU_PLL_CON1_CLKF_MASK __BITS(31,16) #define CRU_PLL_CON1_CLKF __BITS(15,0) +#define CRU_PLL_CON2_BWADJ_MASK __BITS(27,16) +#define CRU_PLL_CON2_BWADJ __BITS(11,0) + +#define CRU_PLL_CON3_RESET_MASK __BIT(21) #define CRU_PLL_CON3_POWER_DOWN_MASK __BIT(17) +#define CRU_PLL_CON3_RESET __BIT(5) #define CRU_PLL_CON3_POWER_DOWN __BIT(1) #define CRU_MODE_CON_APLL_WORK_MODE_MASK __BITS(17,16) @@ -105,6 +110,11 @@ #define CRU_CLKSEL_CON11_MMC0_PLL_SEL __BIT(6) #define CRU_CLKSEL_CON11_MMC0_DIV_CON __BITS(5,0) +#define CRU_CLKSEL_CON13_UART0_CLK_SEL_MASK __BITS(25,24) +#define CRU_CLKSEL_CON13_UART0_DIV_CON_MASK __BITS(22,16) +#define CRU_CLKSEL_CON13_UART0_CLK_SEL __BITS(9,8) +#define CRU_CLKSEL_CON13_UART0_DIV_CON __BITS(6,0) + #define CRU_GLB_SRST_FST_MAGIC 0xfdb9 #endif /* !_ROCKCHIP_CRUREG_H */
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Wed Dec 31 16:16:35 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_board.c
Log Message:
add RK3188plus freq scaling, and a 1.4GHz mode. anything above 1GHz with all 4
cores enabled seems to have trouble locking apll, needs more work
To generate a diff of this commit:
cvs rdiff -u -r1.7 -r1.8 src/sys/arch/arm/rockchip/rockchip_board.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.7 src/sys/arch/arm/rockchip/rockchip_board.c:1.8
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.7 Tue Dec 30 17:15:31 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Wed Dec 31 16:16:35 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.7 2014/12/30 17:15:31 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -29,7 +29,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.7 2014/12/30 17:15:31 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.8 2014/12/31 16:16:35 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -37,6 +37,7 @@ __KERNEL_RCSID(0, $NetBSD: rockchip_boa
#include sys/device.h
#include arm/bootconfig.h
+#include arm/cpufunc.h
#include arm/rockchip/rockchip_reg.h
#include arm/rockchip/rockchip_crureg.h
@@ -131,15 +132,17 @@ rk3188_apll_set_rate(u_int rate)
{
bus_space_tag_t bst = rockchip_bs_tag;
bus_space_handle_t bsh;
- uint32_t apll_con0, apll_con1, clksel0_con, clksel1_con;
+ uint32_t apll_con0, apll_con1, apll_con2, clksel0_con, clksel1_con;
+ uint32_t reset_mask, reset;
u_int no, nr, nf, core_div, core_periph_div, core_axi_div,
aclk_div, hclk_div, pclk_div, ahb2apb_div;
u_int cpu_aclk_div_con;
+ const bool rk3188plus_p = rockchip_is_chip(ROCKCHIP_CHIPVER_RK3188PLUS);
rockchip_get_cru_bsh(bsh);
#ifdef ROCKCHIP_CLOCK_DEBUG
- printf(%s: rate=%u\n, __func__, rate);
+ printf(%s: rate=%u rk3188plus_p=%d\n, __func__, rate, rk3188plus_p);
#endif
switch (rate) {
@@ -155,6 +158,18 @@ rk3188_apll_set_rate(u_int rate)
pclk_div = 4;
ahb2apb_div = 2;
break;
+ case 141600:
+ nr = 1;
+ nf = 59;
+ no = 1;
+ core_div = 1;
+ core_periph_div = 8;
+ core_axi_div = 4;
+ aclk_div = 4;
+ hclk_div = 2;
+ pclk_div = 4;
+ ahb2apb_div = 2;
+ break;
case 100800:
nr = 1;
nf = 42;
@@ -186,6 +201,14 @@ rk3188_apll_set_rate(u_int rate)
return EINVAL;
}
+ if (rk3188plus_p) {
+ reset_mask = CRU_PLL_CON3_RESET_MASK;
+ reset = CRU_PLL_CON3_RESET;
+ } else {
+ reset_mask = CRU_PLL_CON3_POWER_DOWN_MASK;
+ reset = CRU_PLL_CON3_POWER_DOWN;
+ }
+
apll_con0 = CRU_PLL_CON0_CLKR_MASK | CRU_PLL_CON0_CLKOD_MASK;
apll_con0 |= __SHIFTIN(no - 1, CRU_PLL_CON0_CLKOD);
apll_con0 |= __SHIFTIN(nr - 1, CRU_PLL_CON0_CLKR);
@@ -193,10 +216,16 @@ rk3188_apll_set_rate(u_int rate)
apll_con1 = CRU_PLL_CON1_CLKF_MASK;
apll_con1 |= __SHIFTIN(nf - 1, CRU_PLL_CON1_CLKF);
+ if (rk3188plus_p) {
+ apll_con2 = CRU_PLL_CON2_BWADJ_MASK;
+ apll_con2 |= __SHIFTIN(nf 1, CRU_PLL_CON2_BWADJ);
+ } else {
+ apll_con2 = 0;
+ }
+
clksel0_con = RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK |
- CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK |
- CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL;
+ CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK;
clksel0_con |= __SHIFTIN(core_div - 1,
RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
clksel0_con |= __SHIFTIN(ffs(core_periph_div) - 2,
@@ -204,11 +233,10 @@ rk3188_apll_set_rate(u_int rate)
clksel0_con |= __SHIFTIN(aclk_div - 1,
CRU_CLKSEL_CON0_A9_CORE_DIV_CON);
- clksel1_con = RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON_MASK |
- CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
+ clksel1_con = CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_PCLK_DIV_CON_MASK |
CRU_CLKSEL_CON1_CPU_HCLK_DIV_CON_MASK;
-
+
switch (core_axi_div) {
case 1: cpu_aclk_div_con = 0; break;
case 2: cpu_aclk_div_con = 1; break;
@@ -217,8 +245,6 @@ rk3188_apll_set_rate(u_int rate)
case 8: cpu_aclk_div_con = 4; break;
default: panic(bad core_axi_div);
}
- clksel1_con |= __SHIFTIN(cpu_aclk_div_con,
- RK3188_CRU_CLKSEL_CON1_CPU_ACLK_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(ahb2apb_div) - 1,
CRU_CLKSEL_CON1_AHB2APB_PCLKEN_DIV_CON);
clksel1_con |= __SHIFTIN(ffs(hclk_div) - 1,
@@ -237,40 +263,48 @@ rk3188_apll_set_rate(u_int rate)
bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(1)));
#endif
- /* Change from normal to slow mode */
- bus_space_write_4(bst, bsh, CRU_MODE_CON_REG,
- CRU_MODE_CON_APLL_WORK_MODE_MASK |
- __SHIFTIN(CRU_MODE_CON_APLL_WORK_MODE_SLOW,
- CRU_MODE_CON_APLL_WORK_MODE));
+
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Wed Dec 31 18:14:15 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_board.c Log Message: fix typo in 1008MHz rate definition for rk3188 To generate a diff of this commit: cvs rdiff -u -r1.9 -r1.10 src/sys/arch/arm/rockchip/rockchip_board.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_board.c diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.9 src/sys/arch/arm/rockchip/rockchip_board.c:1.10 --- src/sys/arch/arm/rockchip/rockchip_board.c:1.9 Wed Dec 31 18:09:05 2014 +++ src/sys/arch/arm/rockchip/rockchip_board.c Wed Dec 31 18:14:14 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $ */ +/* $NetBSD: rockchip_board.c,v 1.10 2014/12/31 18:14:14 jmcneill Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca @@ -29,7 +29,7 @@ #include opt_rockchip.h #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.9 2014/12/31 18:09:05 jmcneill Exp $); +__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.10 2014/12/31 18:14:14 jmcneill Exp $); #include sys/param.h #include sys/bus.h @@ -151,7 +151,7 @@ static const struct rk3188_apll_rate rk3 RK3188_RATE(1608, 67, 1, 8, 4, 4, 2, 4, 2), RK3188_RATE(1416, 59, 1, 8, 4, 4, 2, 4, 2), RK3188_RATE(1200, 50, 1, 8, 4, 4, 2, 4, 2), - RK3188_RATE(1008, 42, 1, 8, 3, 3, 2, 4, 2), + RK3188_RATE(1008, 42, 1, 8, 4, 3, 2, 4, 2), RK3188_RATE( 816, 68, 2, 8, 4, 3, 2, 4, 2), RK3188_RATE( 600, 50, 2, 4, 4, 3, 2, 4, 2), };
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Tue Dec 30 12:38:20 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: obio.c
Log Message:
MMC0/VBUS GPIO changes for Radxa Rock, from FUKAUMI Naoki f...@naobsd.org.
XXX Need to find a way to handle board-specific configurations.
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/obio.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.3 src/sys/arch/arm/rockchip/obio.c:1.4
--- src/sys/arch/arm/rockchip/obio.c:1.3 Sat Dec 27 16:18:50 2014
+++ src/sys/arch/arm/rockchip/obio.c Tue Dec 30 12:38:20 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.3 2014/12/27 16:18:50 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.4 2014/12/30 12:38:20 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -38,7 +38,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.3 2014/12/27 16:18:50 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.4 2014/12/30 12:38:20 jmcneill Exp $);
#include sys/param.h
#include sys/systm.h
@@ -166,16 +166,28 @@ obio_search(device_t parent, cfdata_t cf
return 0;
}
-#define GRF_GPIO3A_IOMUX_OFFSET 0x0090
-#define GRF_GPIO3B_IOMUX_OFFSET 0x0094
-#define GRF_GPIO3C_IOMUX_OFFSET 0x0098
-#define GRF_GPIO3D_IOMUX_OFFSET 0x009C
+#define RK3188_GRF_GPIO3A_IOMUX_OFFSET 0x0090
+#define RK3188_GRF_GPIO3B_IOMUX_OFFSET 0x0094
+#define RK3188_GRF_GPIO3C_IOMUX_OFFSET 0x0098
+#define RK3188_GRF_GPIO3D_IOMUX_OFFSET 0x009C
+
+#define GRF_GPIO0A_IOMUX_OFFSET 0x00a8
+#define GRF_GPIO3A_IOMUX_OFFSET 0x00d8
+#define GRF_GPIO3B_IOMUX_OFFSET 0x00dc
void obio_init_grf(void)
{
- obio_iomux(GRF_GPIO3A_IOMUX_OFFSET, 0x);
- obio_iomux(GRF_GPIO3B_IOMUX_OFFSET, 0x0004);
- obio_iomux(GRF_GPIO3D_IOMUX_OFFSET, 0x1400);
+#if 1
+ /* Radxa Rock */
+ obio_iomux(RK3188_GRF_GPIO3A_IOMUX_OFFSET, 0x5554); /* MMC0 */
+ obio_iomux(RK3188_GRF_GPIO3B_IOMUX_OFFSET, 0x00050001); /* MMC0 */
+ obio_iomux(RK3188_GRF_GPIO3D_IOMUX_OFFSET, 0x3c00); /* VBUS */
+#else
+ /* ChipSPARK Rayeager PX2 */
+ obio_iomux(GRF_GPIO0A_IOMUX_OFFSET, 0x1400); /* VBUS */
+ obio_iomux(GRF_GPIO3A_IOMUX_OFFSET, 0x50004000); /* MMC0 */
+ obio_iomux(GRF_GPIO3B_IOMUX_OFFSET, 0x1555); /* MMC0 */
+#endif
}
void obio_iomux(int offset, int new)
@@ -188,7 +200,7 @@ void obio_iomux(int offset, int new)
ROCKCHIP_GRF_SIZE, bh);
old = bus_space_read_4(bt, bh, offset);
- bus_space_write_4(bt, bh, offset, (old | new | 0x));
+ bus_space_write_4(bt, bh, offset, new);
renew = bus_space_read_4(bt, bh, offset);
printf(grf iomux: old %08x, new %08x, renew %08x\n, old, new, renew);
@@ -199,8 +211,21 @@ void obio_iomux(int offset, int new)
void obio_init_gpio(void)
{
+#if 1
+ /* Radxa Rock */
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(3));
obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(3));
+ obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO2_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+#else
+ /* ChipSPARK Rayeager PX2 */
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(5));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(5));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(6));
+ obio_swporta(ROCKCHIP_GPIO0_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(6));
+ obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DR_OFFSET, __BIT(31));
+ obio_swporta(ROCKCHIP_GPIO1_OFFSET, GPIO_SWPORTA_DD_OFFSET, __BIT(31));
+#endif
}
void obio_swporta(int gpio_base, int offset, int new)
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Tue Dec 30 17:28:11 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_i2c.c
Log Message:
drop clock rate to 400kHz
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_i2c.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_i2c.c
diff -u src/sys/arch/arm/rockchip/rockchip_i2c.c:1.1 src/sys/arch/arm/rockchip/rockchip_i2c.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_i2c.c:1.1 Tue Dec 30 17:15:31 2014
+++ src/sys/arch/arm/rockchip/rockchip_i2c.c Tue Dec 30 17:28:11 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_i2c.c,v 1.1 2014/12/30 17:15:31 jmcneill Exp $ */
+/* $NetBSD: rockchip_i2c.c,v 1.2 2014/12/30 17:28:11 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -29,7 +29,7 @@
#include locators.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.1 2014/12/30 17:15:31 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.2 2014/12/30 17:28:11 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -47,7 +47,7 @@ __KERNEL_RCSID(0, $NetBSD: rockchip_i2c
#include dev/i2c/i2cvar.h
-#define RKIIC_CLOCK_RATE 100
+#define RKIIC_CLOCK_RATE 40
struct rkiic_softc {
device_t sc_dev;
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Tue Dec 30 18:57:36 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: files.rockchip rockchip_i2c.c
rockchip_i2creg.h
Log Message:
Actually set slave addr / reg. Wait for start irq after sending start before
transferring data. Add RKIIC_DEBUG kernel option.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/files.rockchip
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rockchip_i2c.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_i2creg.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u src/sys/arch/arm/rockchip/files.rockchip:1.4 src/sys/arch/arm/rockchip/files.rockchip:1.5
--- src/sys/arch/arm/rockchip/files.rockchip:1.4 Tue Dec 30 17:15:31 2014
+++ src/sys/arch/arm/rockchip/files.rockchip Tue Dec 30 18:57:36 2014
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.4 2014/12/30 17:15:31 jmcneill Exp $
+# $NetBSD: files.rockchip,v 1.5 2014/12/30 18:57:36 jmcneill Exp $
#
# Configuration info for Rockchip ARM Peripherals
#
@@ -49,3 +49,4 @@ defparam opt_rockchip.h MEMSIZE
# Debugging parameters
defflag opt_rockchip.h ROCKCHIP_CLOCK_DEBUG
+defflag opt_rkiic.h RKIIC_DEBUG
Index: src/sys/arch/arm/rockchip/rockchip_i2c.c
diff -u src/sys/arch/arm/rockchip/rockchip_i2c.c:1.2 src/sys/arch/arm/rockchip/rockchip_i2c.c:1.3
--- src/sys/arch/arm/rockchip/rockchip_i2c.c:1.2 Tue Dec 30 17:28:11 2014
+++ src/sys/arch/arm/rockchip/rockchip_i2c.c Tue Dec 30 18:57:36 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_i2c.c,v 1.2 2014/12/30 17:28:11 jmcneill Exp $ */
+/* $NetBSD: rockchip_i2c.c,v 1.3 2014/12/30 18:57:36 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -27,9 +27,10 @@
*/
#include locators.h
+#include opt_rkiic.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.2 2014/12/30 17:28:11 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_i2c.c,v 1.3 2014/12/30 18:57:36 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -181,7 +182,7 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
const void *cmdbuf, size_t cmdlen, void *buf, size_t len, int flags)
{
struct rkiic_softc *sc = priv;
- uint32_t con;
+ uint32_t con, ien;
u_int mode;
int error;
@@ -191,32 +192,49 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
flags |= I2C_F_POLL;
}
+ if (cmdlen != 0 cmdlen != 1)
+ return EINVAL;
+
error = rkiic_set_rate(sc, RKIIC_CLOCK_RATE);
if (error)
return error;
- if (cmdlen 0) {
+ I2C_WRITE(sc, I2C_MRXADDR_REG, I2C_MRXADDR_ADDLVLD |
+ __SHIFTIN(addr, I2C_MRXADDR_SADDR));
+
+ if (cmdlen == 1) {
+ const uint8_t reg = *(const uint8_t *)cmdbuf;
if (I2C_OP_READ_P(op)) {
- mode = I2C_CON_MODE_RRX;
- } else {
mode = I2C_CON_MODE_TRX;
+ } else {
+ mode = I2C_CON_MODE_TX;
}
+ I2C_WRITE(sc, I2C_MRXRADDR_REG, I2C_MRXRADDR_SRADDLVLD |
+ __SHIFTIN(reg, I2C_MRXRADDR_SRADDR));
} else {
if (I2C_OP_READ_P(op)) {
mode = I2C_CON_MODE_RX;
} else {
mode = I2C_CON_MODE_TX;
}
+ I2C_WRITE(sc, I2C_MRXRADDR_REG, 0);
}
- con = I2C_CON_START | I2C_CON_EN | __SHIFTIN(mode, I2C_CON_MODE);
+ sc-sc_intr_ipd = 0;
+
+ ien = I2C_INT_START | (I2C_OP_READ_P(op) ? I2C_INT_MBRF : I2C_INT_MBTF);
+ I2C_WRITE(sc, I2C_IEN_REG, ien);
+
+ con = I2C_CON_START | I2C_CON_EN | I2C_CON_ACK |
+ __SHIFTIN(mode, I2C_CON_MODE);
I2C_WRITE(sc, I2C_CON_REG, con);
- if (cmdlen 0) {
- error = rkiic_write(sc, addr, cmdbuf, cmdlen, flags);
- if (error) {
- goto done;
- }
+ error = rkiic_wait(sc, I2C_INT_START, hz, flags);
+ if (error) {
+#ifdef RKIIC_DEBUG
+ device_printf(sc-sc_dev, timeout waiting for start\n);
+#endif
+ goto done;
}
if (I2C_OP_READ_P(op)) {
@@ -225,11 +243,12 @@ rkiic_exec(void *priv, i2c_op_t op, i2c_
error = rkiic_write(sc, addr, buf, len, flags);
}
-done:
if (I2C_OP_STOP_P(op)) {
I2C_WRITE(sc, I2C_CON_REG, I2C_CON_STOP);
}
+done:
+ I2C_WRITE(sc, I2C_IEN_REG, 0);
return error;
}
@@ -246,14 +265,14 @@ rkiic_wait(struct rkiic_softc *sc, uint3
if (flags I2C_F_POLL) {
retry = (timeout / hz) * 100;
while (retry 0) {
- if (I2C_READ(sc, I2C_IPD_REG) mask)
+ sc-sc_intr_ipd |= I2C_READ(sc, I2C_IPD_REG);
+ if (sc-sc_intr_ipd mask)
return 0;
delay(1);
--retry;
}
} else {
retry = timeout / hz;
-
while (retry 0) {
error = cv_timedwait(sc-sc_cv, sc-sc_lock, hz);
if (error error != EWOULDBLOCK)
@@ -278,17 +297,15 @@ rkiic_read(struct rkiic_softc *sc, i2c_a
if (buflen 32)
return EINVAL;
- sc-sc_intr_ipd = 0;
-
- if (!(flags I2C_F_POLL)) {
- I2C_WRITE(sc, I2C_IEN_REG, I2C_INT_MBRF);
- }
-
I2C_WRITE(sc, I2C_MRXCNT_REG, __SHIFTIN(buflen, I2C_MRXCNT_COUNT));
error = rkiic_wait(sc, I2C_INT_MBRF, hz, flags);
- if (error)
- goto done;
+ if (error) {
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Mon Dec 29 23:59:52 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_dwcmmc.c
Log Message:
- Set DWC_MMC_F_FORCE_CLK
- Force max sdmmc clk to 24MHz
- Update for simpler dwcmmc clock setup
To generate a diff of this commit:
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
diff -u src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.3 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.4
--- src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.3 Sun Dec 28 16:27:14 2014
+++ src/sys/arch/arm/rockchip/rockchip_dwcmmc.c Mon Dec 29 23:59:52 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_dwcmmc.c,v 1.3 2014/12/28 16:27:14 jmcneill Exp $ */
+/* $NetBSD: rockchip_dwcmmc.c,v 1.4 2014/12/29 23:59:52 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.3 2014/12/28 16:27:14 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.4 2014/12/29 23:59:52 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -48,8 +48,6 @@ static void rk_dwcmmc_attach(device_t, d
static void rk_dwcmmc_attach_i(device_t);
-static int rk_dwcmmc_set_clkdiv(struct dwc_mmc_softc *, int);
-
CFATTACH_DECL_NEW(rkdwcmmc, sizeof(struct dwc_mmc_softc),
rk_dwcmmc_match, rk_dwcmmc_attach, NULL, NULL);
@@ -65,13 +63,16 @@ rk_dwcmmc_attach(device_t parent, device
struct dwc_mmc_softc *sc = device_private(self);
struct obio_attach_args * const obio = aux;
+ rockchip_mmc0_set_div(1);
+
sc-sc_dev = self;
sc-sc_bst = obio-obio_bst;
sc-sc_dmat = obio-obio_dmat;
- sc-sc_flags = DWC_MMC_F_USE_HOLD_REG | DWC_MMC_F_PWREN_CLEAR;
- sc-sc_clock_freq = rockchip_ahb_get_rate();
- sc-sc_fifo_depth = 256;
- sc-sc_set_clkdiv = rk_dwcmmc_set_clkdiv;
+ sc-sc_flags = DWC_MMC_F_USE_HOLD_REG | DWC_MMC_F_PWREN_CLEAR |
+ DWC_MMC_F_FORCE_CLK;
+ sc-sc_clock_freq = rockchip_mmc0_get_rate();
+ sc-sc_clock_max = 24000;
+ sc-sc_fifo_depth = 32;
bus_space_subregion(obio-obio_bst, obio-obio_bsh, obio-obio_offset,
obio-obio_size, sc-sc_bsh);
@@ -97,9 +98,3 @@ rk_dwcmmc_attach_i(device_t self)
dwc_mmc_init(sc);
}
-
-static int
-rk_dwcmmc_set_clkdiv(struct dwc_mmc_softc *sc, int div)
-{
- return rockchip_mmc0_set_div(div);
-}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sun Dec 28 16:03:09 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_reg.h Log Message: add SRAM, SCU, PMU offsets To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_reg.h diff -u src/sys/arch/arm/rockchip/rockchip_reg.h:1.3 src/sys/arch/arm/rockchip/rockchip_reg.h:1.4 --- src/sys/arch/arm/rockchip/rockchip_reg.h:1.3 Sun Dec 28 01:50:39 2014 +++ src/sys/arch/arm/rockchip/rockchip_reg.h Sun Dec 28 16:03:09 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_reg.h,v 1.3 2014/12/28 01:50:39 jmcneill Exp $ */ +/* $NetBSD: rockchip_reg.h,v 1.4 2014/12/28 16:03:09 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -43,6 +43,10 @@ #define ROCKCHIP_CORE0_SIZE 0x0030 /* CORE0 */ +#define ROCKCHIP_SRAM_OFFSET 0x0008 +#define ROCKCHIP_SRAM_SIZE 0x8000 +#define ROCKCHIP_SCU_OFFSET 0x0013C000 +#define ROCKCHIP_SCU_SIZE 0x100 #define ROCKCHIP_OTG_OFFSET 0x0018 #define ROCKCHIP_OTG_SIZE 0x4 #define ROCKCHIP_USB_OFFSET 0x001C @@ -69,6 +73,8 @@ /* CORE1 */ #define ROCKCHIP_CRU_OFFSET 0x #define ROCKCHIP_CRU_SIZE 0x4000 +#define ROCKCHIP_PMU_OFFSET 0x4000 +#define ROCKCHIP_PMU_SIZE 0x4000 #define ROCKCHIP_GRF_OFFSET 0x8000 #define ROCKCHIP_GRF_SIZE 0x2000 #define ROCKCHIP_UART2_OFFSET 0x00064000
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sun Dec 28 16:27:15 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_dwcmmc.c Log Message: remove redundant irq print To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_dwcmmc.c diff -u src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.2 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.3 --- src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.2 Sat Dec 27 19:18:35 2014 +++ src/sys/arch/arm/rockchip/rockchip_dwcmmc.c Sun Dec 28 16:27:14 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_dwcmmc.c,v 1.2 2014/12/27 19:18:35 jmcneill Exp $ */ +/* $NetBSD: rockchip_dwcmmc.c,v 1.3 2014/12/28 16:27:14 jmcneill Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca @@ -27,7 +27,7 @@ */ #include sys/cdefs.h -__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.2 2014/12/27 19:18:35 jmcneill Exp $); +__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.3 2014/12/28 16:27:14 jmcneill Exp $); #include sys/param.h #include sys/bus.h @@ -86,7 +86,6 @@ rk_dwcmmc_attach(device_t parent, device obio-obio_intr); return; } - aprint_normal_dev(self, interrupting on irq %d\n, obio-obio_intr); config_interrupts(self, rk_dwcmmc_attach_i); }
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 16:18:50 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: files.rockchip obio.c rockchip_board.c
rockchip_crureg.h rockchip_var.h
Log Message:
More clock fixes, debugging.
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/files.rockchip \
src/sys/arch/arm/rockchip/obio.c \
src/sys/arch/arm/rockchip/rockchip_crureg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rockchip_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/files.rockchip
diff -u src/sys/arch/arm/rockchip/files.rockchip:1.2 src/sys/arch/arm/rockchip/files.rockchip:1.3
--- src/sys/arch/arm/rockchip/files.rockchip:1.2 Fri Dec 26 19:44:48 2014
+++ src/sys/arch/arm/rockchip/files.rockchip Sat Dec 27 16:18:50 2014
@@ -1,4 +1,4 @@
-# $NetBSD: files.rockchip,v 1.2 2014/12/26 19:44:48 jmcneill Exp $
+# $NetBSD: files.rockchip,v 1.3 2014/12/27 16:18:50 jmcneill Exp $
#
# Configuration info for Rockchip ARM Peripherals
#
@@ -41,3 +41,6 @@ defparam opt_rockchip.h CONMODE
# Memory parameters
defparam opt_rockchip.h MEMSIZE
+
+# Debugging parameters
+defflag opt_rockchip.h ROCKCHIP_CLOCK_DEBUG
Index: src/sys/arch/arm/rockchip/obio.c
diff -u src/sys/arch/arm/rockchip/obio.c:1.2 src/sys/arch/arm/rockchip/obio.c:1.3
--- src/sys/arch/arm/rockchip/obio.c:1.2 Fri Dec 26 19:44:48 2014
+++ src/sys/arch/arm/rockchip/obio.c Sat Dec 27 16:18:50 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
+/* $NetBSD: obio.c,v 1.3 2014/12/27 16:18:50 jmcneill Exp $ */
/*
* Copyright (c) 2001, 2002, 2003 Wasabi Systems, Inc.
@@ -35,8 +35,10 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
+#include opt_rockchip.h
+
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.2 2014/12/26 19:44:48 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: obio.c,v 1.3 2014/12/27 16:18:50 jmcneill Exp $);
#include sys/param.h
#include sys/systm.h
@@ -66,6 +68,10 @@ void obio_iomux(int, int);
void obio_init_gpio(void);
void obio_swporta(int, int, int);
+#ifdef ROCKCHIP_CLOCK_DEBUG
+static void obio_dump_clocks(void);
+#endif
+
/* there can be only one */
bool obio_found;
@@ -86,6 +92,10 @@ obio_attach(device_t parent, device_t se
aprint_naive(\n);
aprint_normal(: On-board I/O\n);
+#ifdef ROCKCHIP_CLOCK_DEBUG
+ obio_dump_clocks();
+#endif
+
obio_init_grf();
obio_init_gpio();
@@ -208,3 +218,16 @@ void obio_swporta(int gpio_base, int off
printf(gpio: 0x%08x 0x%08x - 0x%08x\n, gpio_base + offset, old, renew);
}
+
+#ifdef ROCKCHIP_CLOCK_DEBUG
+static void
+obio_dump_clocks(void)
+{
+ printf(APLL: %u Hz\n, rockchip_apll_get_rate());
+ printf(GPLL: %u Hz\n, rockchip_gpll_get_rate());
+ printf(CPU: %u Hz\n, rockchip_cpu_get_rate());
+ printf(AHB: %u Hz\n, rockchip_ahb_get_rate());
+ printf(A9PERIPH: %u Hz\n, rockchip_a9periph_get_rate());
+ printf(MMC0: %u Hz\n, rockchip_mmc0_get_rate());
+}
+#endif
Index: src/sys/arch/arm/rockchip/rockchip_crureg.h
diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.2 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.3
--- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.2 Sat Dec 27 02:12:29 2014
+++ src/sys/arch/arm/rockchip/rockchip_crureg.h Sat Dec 27 16:18:50 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_crureg.h,v 1.2 2014/12/27 02:12:29 jmcneill Exp $ */
+/* $NetBSD: rockchip_crureg.h,v 1.3 2014/12/27 16:18:50 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -55,12 +55,12 @@
#define CRU_GLB_CNT_TH_REG 0x0140
#define CRU_PLL_CON0_CLKR_MASK __BITS(29,24)
-#define CRU_PLL_CON0_CLKOD_MASK __BITS(19,16)
+#define CRU_PLL_CON0_CLKOD_MASK __BITS(21,16)
#define CRU_PLL_CON0_CLKR __BITS(13,8)
-#define CRU_PLL_CON0_CLKOD __BITS(3,0)
+#define CRU_PLL_CON0_CLKOD __BITS(5,0)
-#define CRU_PLL_CON1_CLKF_MASK __BITS(28,16)
-#define CRU_PLL_CON1_CLKF __BITS(12,0)
+#define CRU_PLL_CON1_CLKF_MASK __BITS(31,16)
+#define CRU_PLL_CON1_CLKF __BITS(15,0)
#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK __BIT(24)
#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK __BITS(23,22)
@@ -68,6 +68,7 @@
#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL __BIT(8)
#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON __BITS(7,6)
#define CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(4,0)
+#define RK3188_CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(13,9)
#define CRU_CLKSEL_CON10_PERI_PLL_SEL_MASK __BIT(31)
#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON_MASK __BITS(29,28)
@@ -78,6 +79,9 @@
#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(9,8)
#define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON __BITS(4,0)
+#define CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK __BITS(21,16)
+#define CRU_CLKSEL_CON11_MMC0_DIV_CON __BITS(5,0)
+
#define CRU_GLB_SRST_FST_MAGIC 0xfdb9
#endif /* !_ROCKCHIP_CRUREG_H */
Index:
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 19:14:05 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_board.c rockchip_var.h
Log Message:
mmc0 on rk3188 is based on ahb clk, not gpll. add a function to control mmc0
clock as well.
To generate a diff of this commit:
cvs rdiff -u -r1.4 -r1.5 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.5 -r1.6 src/sys/arch/arm/rockchip/rockchip_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.4 src/sys/arch/arm/rockchip/rockchip_board.c:1.5
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.4 Sat Dec 27 16:18:50 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Sat Dec 27 19:14:05 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.4 2014/12/27 16:18:50 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.5 2014/12/27 19:14:05 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -29,7 +29,7 @@
#include opt_rockchip.h
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.4 2014/12/27 16:18:50 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.5 2014/12/27 19:14:05 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -199,5 +199,41 @@ rockchip_mmc0_get_rate(void)
mmc0_div_con = __SHIFTOUT(clksel_con11,
CRU_CLKSEL_CON11_MMC0_DIV_CON);
- return rockchip_gpll_get_rate() / (mmc0_div_con + 1);
+ return rockchip_ahb_get_rate() / (mmc0_div_con + 1);
+}
+
+u_int
+rockchip_mmc0_set_div(u_int div)
+{
+ bus_space_tag_t bst = rockchip_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t clksel_con11;
+
+ if (div == 0 || div 0x40)
+ return EINVAL;
+
+ rockchip_get_cru_bsh(bsh);
+
+ clksel_con11 = CRU_CLKSEL_CON11_MMC0_PLL_SEL_MASK |
+ CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK;
+ //clksel_con11 |= CRU_CLKSEL_CON11_MMC0_PLL_SEL; /* GPLL */
+ clksel_con11 |= __SHIFTIN(div - 1, CRU_CLKSEL_CON11_MMC0_DIV_CON);
+
+#ifdef ROCKCHIP_CLOCK_DEBUG
+ const u_int old_rate = rockchip_mmc0_get_rate();
+#endif
+
+ bus_space_write_4(bst, bsh, CRU_CLKSEL_CON_REG(11), clksel_con11);
+
+#ifdef ROCKCHIP_CLOCK_DEBUG
+ const u_int new_rate = rockchip_mmc0_get_rate();
+
+ printf(%s: update %u Hz - %u Hz\n, __func__, old_rate, new_rate);
+
+ const uint32_t clkgate2 = bus_space_read_4(bst, bsh,
+ CRU_CLKGATE_CON_REG(2));
+ printf(%s: clkgate2 = %#x\n, __func__, clkgate2);
+#endif
+
+ return 0;
}
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u src/sys/arch/arm/rockchip/rockchip_var.h:1.5 src/sys/arch/arm/rockchip/rockchip_var.h:1.6
--- src/sys/arch/arm/rockchip/rockchip_var.h:1.5 Sat Dec 27 16:18:50 2014
+++ src/sys/arch/arm/rockchip/rockchip_var.h Sat Dec 27 19:14:05 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_var.h,v 1.5 2014/12/27 16:18:50 jmcneill Exp $ */
+/* $NetBSD: rockchip_var.h,v 1.6 2014/12/27 19:14:05 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -64,5 +64,6 @@ u_int rockchip_cpu_get_rate(void);
u_int rockchip_ahb_get_rate(void);
u_int rockchip_a9periph_get_rate(void);
u_int rockchip_mmc0_get_rate(void);
+u_int rockchip_mmc0_set_div(u_int);
#endif /* _ARM_ROCKCHIP_ROCKCHIP_VAR_H_ */
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Dec 27 19:14:34 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_crureg.h Log Message: update some bits for rk3188 To generate a diff of this commit: cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_crureg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_crureg.h diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.3 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.4 --- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.3 Sat Dec 27 16:18:50 2014 +++ src/sys/arch/arm/rockchip/rockchip_crureg.h Sat Dec 27 19:14:34 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_crureg.h,v 1.3 2014/12/27 16:18:50 jmcneill Exp $ */ +/* $NetBSD: rockchip_crureg.h,v 1.4 2014/12/27 19:14:34 jmcneill Exp $ */ /*- * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca @@ -72,14 +72,16 @@ #define CRU_CLKSEL_CON10_PERI_PLL_SEL_MASK __BIT(31) #define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON_MASK __BITS(29,28) -#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(25,24) +#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(26,24) #define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON_MASK __BITS(20,16) #define CRU_CLKSEL_CON10_PERI_PLL_SEL __BIT(15) #define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON __BITS(13,12) -#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(9,8) +#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(10,8) #define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON __BITS(4,0) +#define CRU_CLKSEL_CON11_MMC0_PLL_SEL_MASK __BIT(22) #define CRU_CLKSEL_CON11_MMC0_DIV_CON_MASK __BITS(21,16) +#define CRU_CLKSEL_CON11_MMC0_PLL_SEL __BIT(6) #define CRU_CLKSEL_CON11_MMC0_DIV_CON __BITS(5,0) #define CRU_GLB_SRST_FST_MAGIC 0xfdb9
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 19:18:35 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_dwcmmc.c
Log Message:
set DWC_MMC_F_PWREN_CLEAR, implement set_clkdiv callback; now this works
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
diff -u src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.1 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.1 Sat Dec 27 01:22:07 2014
+++ src/sys/arch/arm/rockchip/rockchip_dwcmmc.c Sat Dec 27 19:18:35 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_dwcmmc.c,v 1.1 2014/12/27 01:22:07 jmcneill Exp $ */
+/* $NetBSD: rockchip_dwcmmc.c,v 1.2 2014/12/27 19:18:35 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.1 2014/12/27 01:22:07 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.2 2014/12/27 19:18:35 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -48,6 +48,8 @@ static void rk_dwcmmc_attach(device_t, d
static void rk_dwcmmc_attach_i(device_t);
+static int rk_dwcmmc_set_clkdiv(struct dwc_mmc_softc *, int);
+
CFATTACH_DECL_NEW(rkdwcmmc, sizeof(struct dwc_mmc_softc),
rk_dwcmmc_match, rk_dwcmmc_attach, NULL, NULL);
@@ -66,9 +68,10 @@ rk_dwcmmc_attach(device_t parent, device
sc-sc_dev = self;
sc-sc_bst = obio-obio_bst;
sc-sc_dmat = obio-obio_dmat;
- sc-sc_flags = DWC_MMC_F_USE_HOLD_REG;
+ sc-sc_flags = DWC_MMC_F_USE_HOLD_REG | DWC_MMC_F_PWREN_CLEAR;
sc-sc_clock_freq = rockchip_ahb_get_rate();
sc-sc_fifo_depth = 256;
+ sc-sc_set_clkdiv = rk_dwcmmc_set_clkdiv;
bus_space_subregion(obio-obio_bst, obio-obio_bsh, obio-obio_offset,
obio-obio_size, sc-sc_bsh);
@@ -95,3 +98,9 @@ rk_dwcmmc_attach_i(device_t self)
dwc_mmc_init(sc);
}
+
+static int
+rk_dwcmmc_set_clkdiv(struct dwc_mmc_softc *sc, int div)
+{
+ return rockchip_mmc0_set_div(div);
+}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sun Dec 28 01:50:39 UTC 2014 Modified Files: src/sys/arch/arm/rockchip: rockchip_reg.h Log Message: add DDR offsets To generate a diff of this commit: cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rockchip_reg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Modified files: Index: src/sys/arch/arm/rockchip/rockchip_reg.h diff -u src/sys/arch/arm/rockchip/rockchip_reg.h:1.2 src/sys/arch/arm/rockchip/rockchip_reg.h:1.3 --- src/sys/arch/arm/rockchip/rockchip_reg.h:1.2 Fri Dec 26 19:44:48 2014 +++ src/sys/arch/arm/rockchip/rockchip_reg.h Sun Dec 28 01:50:39 2014 @@ -1,4 +1,4 @@ -/* $NetBSD: rockchip_reg.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */ +/* $NetBSD: rockchip_reg.h,v 1.3 2014/12/28 01:50:39 jmcneill Exp $ */ /*- * Copyright (c) 2014 The NetBSD Foundation, Inc. @@ -77,10 +77,14 @@ #define ROCKCHIP_UART3_SIZE 0x400 #define ROCKCHIP_GPIO0_OFFSET 0xA000 #define ROCKCHIP_GPIO0_SIZE 0x100 +#define ROCKCHIP_DDR_PCTL_OFFSET 0x0002 +#define ROCKCHIP_DDR_PCTL_SIZE 0x4000 #define ROCKCHIP_GPIO1_OFFSET 0x0003C000 #define ROCKCHIP_GPIO1_SIZE 0x100 #define ROCKCHIP_GPIO2_OFFSET 0x0003E000 #define ROCKCHIP_GPIO2_SIZE 0x100 +#define ROCKCHIP_DDR_PUBL_OFFSET 0x0004 +#define ROCKCHIP_DDR_PUBL_SIZE 0x4000 #define ROCKCHIP_GPIO3_OFFSET 0x0008 #define ROCKCHIP_GPIO3_SIZE 0x100
CVS commit: src/sys/arch/arm/rockchip
Module Name:src Committed By: jmcneill Date: Sat Dec 27 01:20:31 UTC 2014 Added Files: src/sys/arch/arm/rockchip: rockchip_crureg.h Log Message: add CRU reg definitions To generate a diff of this commit: cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/rockchip_crureg.h Please note that diffs are not public domain; they are subject to the copyright notices on the relevant files. Added files: Index: src/sys/arch/arm/rockchip/rockchip_crureg.h diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_crureg.h:1.1 --- /dev/null Sat Dec 27 01:20:31 2014 +++ src/sys/arch/arm/rockchip/rockchip_crureg.h Sat Dec 27 01:20:31 2014 @@ -0,0 +1,76 @@ +/* $NetBSD: rockchip_crureg.h,v 1.1 2014/12/27 01:20:31 jmcneill Exp $ */ + +/*- + * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + *notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + *notice, this list of conditions and the following disclaimer in the + *documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ROCKCHIP_CRUREG_H +#define _ROCKCHIP_CRUREG_H + +#define CRU_APLL_CON0_REG 0x +#define CRU_APLL_CON1_REG 0x0004 +#define CRU_APLL_CON2_REG 0x0008 +#define CRU_APLL_CON3_REG 0x000c +#define CRU_DPLL_CON0_REG 0x0010 +#define CRU_DPLL_CON1_REG 0x0014 +#define CRU_DPLL_CON2_REG 0x0018 +#define CRU_DPLL_CON3_REG 0x001c +#define CRU_CPLL_CON0_REG 0x0020 +#define CRU_CPLL_CON1_REG 0x0024 +#define CRU_CPLL_CON2_REG 0x0028 +#define CRU_CPLL_CON3_REG 0x002c +#define CRU_GPLL_CON0_REG 0x0030 +#define CRU_GPLL_CON1_REG 0x0034 +#define CRU_GPLL_CON2_REG 0x0038 +#define CRU_GPLL_CON3_REG 0x003c +#define CRU_MODE_CON_REG 0x0040 +#define CRU_CLKSEL_CON_REG(n) (0x0044 + (n) * 4) +#define CRU_CLKGATE_CON_REG(n) (0x00d0 + (n) * 4) +#define CRU_GLB_SRST_FST_REG 0x0100 +#define CRU_GLB_SRST_SND_REG 0x0104 +#define CRU_SOFTRST_REG(n) (0x0110 + (n) * 4) +#define CRU_MISC_CON_REG 0x0134 +#define CRU_GLB_CNT_TH_REG 0x0140 + +#define CRU_PLL_CON0_CLKR_MASK __BITS(29,24) +#define CRU_PLL_CON0_CLKOD_MASK __BITS(19,16) +#define CRU_PLL_CON0_CLKR __BITS(13,8) +#define CRU_PLL_CON0_CLKOD __BITS(3,0) + +#define CRU_PLL_CON1_CLKF_MASK __BITS(28,16) +#define CRU_PLL_CON1_CLKF __BITS(12,0) + +#define CRU_CLKSEL_CON10_PERI_PLL_SEL_MASK __BIT(31) +#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON_MASK __BITS(29,28) +#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(25,24) +#define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON_MASK __BITS(20,16) +#define CRU_CLKSEL_CON10_PERI_PLL_SEL __BIT(15) +#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON __BITS(13,12) +#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON __BITS(9,8) +#define CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON __BITS(4,0) + +#define CRU_GLB_SRST_FST_MAGIC 0xfdb9 + +#endif /* !_ROCKCHIP_CRUREG_H */
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 01:21:21 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_board.c rockchip_var.h
Log Message:
add helpers to get gpll and ahb clock rates
To generate a diff of this commit:
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rockchip_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.1 src/sys/arch/arm/rockchip/rockchip_board.c:1.2
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.1 Fri Dec 26 19:44:48 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Sat Dec 27 01:21:21 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.2 2014/12/27 01:21:21 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.1 2014/12/26 19:44:48 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.2 2014/12/27 01:21:21 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -35,6 +35,7 @@ __KERNEL_RCSID(0, $NetBSD: rockchip_boa
#include sys/device.h
#include arm/rockchip/rockchip_reg.h
+#include arm/rockchip/rockchip_crureg.h
#include arm/rockchip/rockchip_var.h
bus_space_handle_t rockchip_core0_bsh;
@@ -55,3 +56,50 @@ rockchip_bootstrap(void)
if (error)
panic(%s: failed to map CORE1 registers: %d, __func__, error);
}
+
+static void
+rockchip_get_cru_bsh(bus_space_handle_t *pbsh)
+{
+ bus_space_subregion(rockchip_bs_tag, rockchip_core1_bsh,
+ ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, pbsh);
+}
+
+u_int
+rockchip_gpll_get_rate(void)
+{
+ bus_space_tag_t bst = rockchip_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t gpll_con0, gpll_con1;
+ uint32_t nr, nf, no;
+
+ rockchip_get_cru_bsh(bsh);
+
+ gpll_con0 = bus_space_read_4(bst, bsh, CRU_GPLL_CON0_REG);
+ gpll_con1 = bus_space_read_4(bst, bsh, CRU_GPLL_CON1_REG);
+
+ nr = __SHIFTOUT(gpll_con0, CRU_PLL_CON0_CLKR) + 1;
+ no = __SHIFTOUT(gpll_con0, CRU_PLL_CON0_CLKOD) + 1;
+ nf = __SHIFTOUT(gpll_con1, CRU_PLL_CON1_CLKF) + 1;
+
+ return ROCKCHIP_REF_FREQ * nf / (nr * no);
+}
+
+u_int
+rockchip_ahb_get_rate(void)
+{
+ bus_space_tag_t bst = rockchip_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t clksel_con10;
+ uint32_t hclk_div, aclk_div;
+
+ rockchip_get_cru_bsh(bsh);
+
+ clksel_con10 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(10));
+
+ hclk_div = __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON) + 1;
+ aclk_div = 1 __SHIFTOUT(clksel_con10,
+ CRU_CLKSEL_CON10_PERI_ACLK_DIV_CON);
+
+ return rockchip_gpll_get_rate() / (hclk_div * aclk_div);
+}
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u src/sys/arch/arm/rockchip/rockchip_var.h:1.2 src/sys/arch/arm/rockchip/rockchip_var.h:1.3
--- src/sys/arch/arm/rockchip/rockchip_var.h:1.2 Fri Dec 26 19:44:48 2014
+++ src/sys/arch/arm/rockchip/rockchip_var.h Sat Dec 27 01:21:21 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_var.h,v 1.2 2014/12/26 19:44:48 jmcneill Exp $ */
+/* $NetBSD: rockchip_var.h,v 1.3 2014/12/27 01:21:21 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -56,4 +56,7 @@ extern bus_space_handle_t rockchip_core1
void rockchip_bootstrap(void);
+u_int rockchip_gpll_get_rate(void);
+u_int rockchip_ahb_get_rate(void);
+
#endif /* _ARM_ROCKCHIP_ROCKCHIP_VAR_H_ */
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 01:22:07 UTC 2014
Added Files:
src/sys/arch/arm/rockchip: rockchip_dwcmmc.c
Log Message:
add dwcmmc glue, doesnt work yet
To generate a diff of this commit:
cvs rdiff -u -r0 -r1.1 src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Added files:
Index: src/sys/arch/arm/rockchip/rockchip_dwcmmc.c
diff -u /dev/null src/sys/arch/arm/rockchip/rockchip_dwcmmc.c:1.1
--- /dev/null Sat Dec 27 01:22:07 2014
+++ src/sys/arch/arm/rockchip/rockchip_dwcmmc.c Sat Dec 27 01:22:07 2014
@@ -0,0 +1,97 @@
+/* $NetBSD: rockchip_dwcmmc.c,v 1.1 2014/12/27 01:22:07 jmcneill Exp $ */
+
+/*-
+ * Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include sys/cdefs.h
+__KERNEL_RCSID(0, $NetBSD: rockchip_dwcmmc.c,v 1.1 2014/12/27 01:22:07 jmcneill Exp $);
+
+#include sys/param.h
+#include sys/bus.h
+#include sys/device.h
+#include sys/intr.h
+#include sys/systm.h
+#include sys/kernel.h
+#include sys/mutex.h
+#include sys/condvar.h
+
+#include arm/rockchip/rockchip_reg.h
+#include arm/rockchip/rockchip_var.h
+
+#include dev/ic/dwc_mmc_var.h
+
+static int rk_dwcmmc_match(device_t, cfdata_t, void *);
+static void rk_dwcmmc_attach(device_t, device_t, void *);
+
+static void rk_dwcmmc_attach_i(device_t);
+
+CFATTACH_DECL_NEW(rkdwcmmc, sizeof(struct dwc_mmc_softc),
+ rk_dwcmmc_match, rk_dwcmmc_attach, NULL, NULL);
+
+static int
+rk_dwcmmc_match(device_t parent, cfdata_t cf, void *aux)
+{
+ return 1;
+}
+
+static void
+rk_dwcmmc_attach(device_t parent, device_t self, void *aux)
+{
+ struct dwc_mmc_softc *sc = device_private(self);
+ struct obio_attach_args * const obio = aux;
+
+ sc-sc_dev = self;
+ sc-sc_bst = obio-obio_bst;
+ sc-sc_dmat = obio-obio_dmat;
+ sc-sc_flags = DWC_MMC_F_USE_HOLD_REG;
+ sc-sc_clock_freq = rockchip_ahb_get_rate();
+ sc-sc_fifo_depth = 256;
+
+ bus_space_subregion(obio-obio_bst, obio-obio_bsh, obio-obio_offset,
+ obio-obio_size, sc-sc_bsh);
+
+ aprint_naive(\n);
+ aprint_normal(: SD/MMC controller\n);
+
+ sc-sc_ih = intr_establish(obio-obio_intr, IPL_BIO, IST_LEVEL,
+ dwc_mmc_intr, sc);
+ if (sc-sc_ih == NULL) {
+ aprint_error_dev(self, couldn't establish interrupt %d\n,
+ obio-obio_intr);
+ return;
+ }
+ aprint_normal_dev(self, interrupting on irq %d\n, obio-obio_intr);
+
+ config_interrupts(self, rk_dwcmmc_attach_i);
+}
+
+static void
+rk_dwcmmc_attach_i(device_t self)
+{
+ struct dwc_mmc_softc *sc = device_private(self);
+
+ dwc_mmc_init(sc);
+}
CVS commit: src/sys/arch/arm/rockchip
Module Name:src
Committed By: jmcneill
Date: Sat Dec 27 02:12:30 UTC 2014
Modified Files:
src/sys/arch/arm/rockchip: rockchip_board.c rockchip_crureg.h
rockchip_var.h
Log Message:
add functions to get apll and cpu rates
To generate a diff of this commit:
cvs rdiff -u -r1.2 -r1.3 src/sys/arch/arm/rockchip/rockchip_board.c
cvs rdiff -u -r1.1 -r1.2 src/sys/arch/arm/rockchip/rockchip_crureg.h
cvs rdiff -u -r1.3 -r1.4 src/sys/arch/arm/rockchip/rockchip_var.h
Please note that diffs are not public domain; they are subject to the
copyright notices on the relevant files.
Modified files:
Index: src/sys/arch/arm/rockchip/rockchip_board.c
diff -u src/sys/arch/arm/rockchip/rockchip_board.c:1.2 src/sys/arch/arm/rockchip/rockchip_board.c:1.3
--- src/sys/arch/arm/rockchip/rockchip_board.c:1.2 Sat Dec 27 01:21:21 2014
+++ src/sys/arch/arm/rockchip/rockchip_board.c Sat Dec 27 02:12:29 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_board.c,v 1.2 2014/12/27 01:21:21 jmcneill Exp $ */
+/* $NetBSD: rockchip_board.c,v 1.3 2014/12/27 02:12:29 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -27,7 +27,7 @@
*/
#include sys/cdefs.h
-__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.2 2014/12/27 01:21:21 jmcneill Exp $);
+__KERNEL_RCSID(0, $NetBSD: rockchip_board.c,v 1.3 2014/12/27 02:12:29 jmcneill Exp $);
#include sys/param.h
#include sys/bus.h
@@ -64,27 +64,56 @@ rockchip_get_cru_bsh(bus_space_handle_t
ROCKCHIP_CRU_OFFSET, ROCKCHIP_CRU_SIZE, pbsh);
}
-u_int
-rockchip_gpll_get_rate(void)
+static u_int
+rockchip_pll_get_rate(bus_size_t con0_reg, bus_size_t con1_reg)
{
bus_space_tag_t bst = rockchip_bs_tag;
bus_space_handle_t bsh;
- uint32_t gpll_con0, gpll_con1;
+ uint32_t pll_con0, pll_con1;
uint32_t nr, nf, no;
rockchip_get_cru_bsh(bsh);
- gpll_con0 = bus_space_read_4(bst, bsh, CRU_GPLL_CON0_REG);
- gpll_con1 = bus_space_read_4(bst, bsh, CRU_GPLL_CON1_REG);
+ pll_con0 = bus_space_read_4(bst, bsh, con0_reg);
+ pll_con1 = bus_space_read_4(bst, bsh, con1_reg);
- nr = __SHIFTOUT(gpll_con0, CRU_PLL_CON0_CLKR) + 1;
- no = __SHIFTOUT(gpll_con0, CRU_PLL_CON0_CLKOD) + 1;
- nf = __SHIFTOUT(gpll_con1, CRU_PLL_CON1_CLKF) + 1;
+ nr = __SHIFTOUT(pll_con0, CRU_PLL_CON0_CLKR) + 1;
+ no = __SHIFTOUT(pll_con0, CRU_PLL_CON0_CLKOD) + 1;
+ nf = __SHIFTOUT(pll_con1, CRU_PLL_CON1_CLKF) + 1;
return ROCKCHIP_REF_FREQ * nf / (nr * no);
}
u_int
+rockchip_gpll_get_rate(void)
+{
+ return rockchip_pll_get_rate(CRU_GPLL_CON0_REG, CRU_GPLL_CON1_REG);
+}
+
+u_int
+rockchip_apll_get_rate(void)
+{
+ return rockchip_pll_get_rate(CRU_APLL_CON0_REG, CRU_APLL_CON1_REG);
+}
+
+u_int
+rockchip_cpu_get_rate(void)
+{
+ bus_space_tag_t bst = rockchip_bs_tag;
+ bus_space_handle_t bsh;
+ uint32_t clksel_con0;
+
+ rockchip_get_cru_bsh(bsh);
+
+ clksel_con0 = bus_space_read_4(bst, bsh, CRU_CLKSEL_CON_REG(0));
+ if (clksel_con0 CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL) {
+ return rockchip_gpll_get_rate();
+ } else {
+ return rockchip_apll_get_rate();
+ }
+}
+
+u_int
rockchip_ahb_get_rate(void)
{
bus_space_tag_t bst = rockchip_bs_tag;
Index: src/sys/arch/arm/rockchip/rockchip_crureg.h
diff -u src/sys/arch/arm/rockchip/rockchip_crureg.h:1.1 src/sys/arch/arm/rockchip/rockchip_crureg.h:1.2
--- src/sys/arch/arm/rockchip/rockchip_crureg.h:1.1 Sat Dec 27 01:20:31 2014
+++ src/sys/arch/arm/rockchip/rockchip_crureg.h Sat Dec 27 02:12:29 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_crureg.h,v 1.1 2014/12/27 01:20:31 jmcneill Exp $ */
+/* $NetBSD: rockchip_crureg.h,v 1.2 2014/12/27 02:12:29 jmcneill Exp $ */
/*-
* Copyright (c) 2014 Jared D. McNeill jmcne...@invisible.ca
@@ -62,6 +62,13 @@
#define CRU_PLL_CON1_CLKF_MASK __BITS(28,16)
#define CRU_PLL_CON1_CLKF __BITS(12,0)
+#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL_MASK __BIT(24)
+#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON_MASK __BITS(23,22)
+#define CRU_CLKSEL_CON0_A9_CORE_DIV_CON_MASK __BITS(20,16)
+#define CRU_CLKSEL_CON0_CPU_CLK_PLL_SEL __BIT(8)
+#define CRU_CLKSEL_CON0_CORE_PERI_DIV_CON __BITS(7,6)
+#define CRU_CLKSEL_CON0_A9_CORE_DIV_CON __BITS(4,0)
+
#define CRU_CLKSEL_CON10_PERI_PLL_SEL_MASK __BIT(31)
#define CRU_CLKSEL_CON10_PERI_PCLK_DIV_CON_MASK __BITS(29,28)
#define CRU_CLKSEL_CON10_PERI_HCLK_DIV_CON_MASK __BITS(25,24)
Index: src/sys/arch/arm/rockchip/rockchip_var.h
diff -u src/sys/arch/arm/rockchip/rockchip_var.h:1.3 src/sys/arch/arm/rockchip/rockchip_var.h:1.4
--- src/sys/arch/arm/rockchip/rockchip_var.h:1.3 Sat Dec 27 01:21:21 2014
+++ src/sys/arch/arm/rockchip/rockchip_var.h Sat Dec 27 02:12:29 2014
@@ -1,4 +1,4 @@
-/* $NetBSD: rockchip_var.h,v 1.3 2014/12/27 01:21:21 jmcneill Exp $ */
+/* $NetBSD: rockchip_var.h,v 1.4 2014/12/27 02:12:29 jmcneill Exp $ */
/*-
* Copyright (c) 2014 The NetBSD Foundation, Inc.
@@ -56,7 +56,9 @@ extern bus_space_handle_t rockchip_core1
void rockchip_bootstrap(void);
+u_int rockchip_apll_get_rate(void);
u_int rockchip_gpll_get_rate(void);
+u_int
