Re: [time-nuts] Microsemi up for sale?

[Anders Wallin]

>
> rich...@karlquist.com said:
> > 2.  Magnetic state selection, as used in the 5071A, would be replaced by
> > optical pumping.  Len Cutler was heartbroken that HP/Agilent management
> > wouldn't fund this effort.
>
> > It turns out that, even now in 2018, optical pumping is not ready for
> prime
> > time in a working standard because the lasers drift over time.
>
> Is there something fundamental in there, or is the lack of products because
> nobody has made the big investment required to figure out how to do it.
>

FWIW, OSA has been giving at leat one talk per year on their optical Cs
work, and as others have noted it's been coming "real soon" for a couple of
years now.
Here are some links:
2015 November:
http://www.chronos.co.uk/files/pdfs/itsf/2015/day2/1410_High_performance_optically-pumped_cesium_beam_clock-PBerthoud-Oscilloquartz.pdf

2017 April:
https://www.atis.org/wsts/library/2017/5-03_Oscilloquartz_Berthoud_Michaud_Optical%20Cs%20Beam%20clock%20for%20ePRTC%20applications_revision20170327.pdf
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Re: [time-nuts] Microsemi up for sale?

[Anders Wallin]

Just a change to the last part of the name then ;)
https://www.ft.com/content/10192a2a-1d99-11e8-956a-43db76e69936
"semi" -> "chip"


On Sat, Jan 27, 2018 at 1:27 AM, Clint Jay  wrote:

> Perhaps of interest to the list
>
> https://www.theregister.co.uk/2018/01/25/microsemi/
>
> --
> Clint.
>
> *No trees were harmed in the sending of this mail. However, a large number
> of electrons were greatly inconvenienced.*
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Re: [time-nuts] Phase noise in stable 32

[Anders Wallin]

For AllanTools and other testing I have tried the FFT plots in Stable32.
It seems to use a fairly simple FFT which has problems for divergent
noise-types. The Welch algorithm is better for these.
The x-axis should end at the Nyquist frequency, i.e. half of your data rate.
For meaningful phase-noise analysis you'd want phase observations at 100
kHz or more, e.g. from an SDR or similar.


On Thu, Jan 25, 2018 at 12:47 AM, slawek dabrowski  wrote:

> Hello to the group,
>
> Have you ever used frequency/phase data to estimate phase noise of your
> O's using Stable32? I probably do something wrong in conversions when using
> Power button because my plot starts on 10e-7 Hz and ends on 10e0 Hz
>
>
>
>
>
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Re: [time-nuts] On the IETF leap-seconds.list SHA1

[Anders Wallin]

>
> > For the Paris Observatory and USNO files my program agrees with the SHA1s
> > in the files.
> > For the IETF file there seems to be one byte, a "0" at the start of the
> > third group of 8 hex characters missing.
>
>This is not a bug but a « feature ». From the ntpd leap hash checking
> code:
>
>  * The NIST code creating the hash writes them out as 5 hex integers
>  * without leading zeros.
>
>Still, it a little unorthodox and complicates the code.
>

Ha! Thanks for explaining this.
Indeed I find writing out the SHA-1 in groups of 8 characters without
leading zeroes quite surprising and undocumented.
The comments in leap-seconds.list about the SHA-1 refer to a /sha or
/pub/sha folder - is that generic information on the SHA-1 or is there any
inidication of the 8-char/leading-zeroes convention there?
I quickly looked at FIPS-180 but didn't find anything about leading zeros
there.

I am still unable to access the NIST ftp-site linked earlier in this thread.

Anders
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Re: [time-nuts] On the IETF leap-seconds.list SHA1

[Anders Wallin]

Thanks,
I added the IANA URL to my list, and sent them an e-mail.
I can't seem to reach the nist ftp-server - does it work for anyone?

I re-named the output.txt so the link in my previous e-mail won't work.
The output now shows on the github repo frontpage:
https://github.com/aewallin/leap-seconds.list_sha1_check

Anders



On Wed, Dec 20, 2017 at 2:18 PM, John Hawkinson <jh...@mit.edu> wrote:

> Umm, the presence of a copy of the IANA TZ distribution at
> https://www.ietf.org/timezones/ is not evidence of an "IETF leap-seconds
> list." This is bizarre, and probably a web server configuration error that
> even exists. The IETF is not involved in this list. I guess this shows why
> Google is an unreliable indicator of authority.
>
> https://www.ietf.org/timezones/data/leap-seconds.list
> is not a URL anyone should be depending on.
>
> https://data.iana.org/time-zones/code/leap-seconds.list
> is perhaps a better URL for the file in the tz distribution, but I'd
> hestitate to call it canonical. Start at https://www.iana.org/time-zones.
>
> But then the tz database isn't an authorative source, either. Per the NEWS
> file:
>
> The 'leapseconds' file is now generated automatically from a
> new file 'leap-seconds.list', which is a copy of
> <ftp://time.nist.gov/pub/leap-seconds.list>.
> A new source file 'leapseconds.awk' implements this.
> The goal is simplification of the future maintenance of 'leapseconds'.
>
> That is, it's just a copy of NIST's file.
>
> Your email would make a lot more sense if you had included the URLs
> directly rather than referring to your source code and output file that
> happen to contain them.
>
> --jh...@mit.edu
>   John Hawkinson
>
> Anders Wallin <anders.e.e.wal...@gmail.com> wrote on Wed, 20 Dec 2017
> at 13:51:21 +0200 in 

[time-nuts] On the IETF leap-seconds.list SHA1

[Anders Wallin]

Hi all,
So I'm doing the typical Wednesday thing you might do, that is writing a
small script for checking the SHA1 checksum in leap-seconds.list files.
I came up with [1] which produces output [2].

For the Paris Observatory and USNO files my program agrees with the SHA1s
in the files.
For the IETF file there seems to be one byte, a "0" at the start of the
third group of 8 hex characters missing.

This is somewhat funny/alarming, since the IETF leap-seconds.list is the
first thing that shows up (at least for me) on google when looking for
leap-seocnds.list.

Please do add to and improve on my code on github - if this is your sort of
thing ;)

happy holidays!
Anders

[1]
https://github.com/aewallin/leap-seconds.list_sha1_check/blob/master/leap_sha.py
[2]
https://github.com/aewallin/leap-seconds.list_sha1_check/blob/master/output.txt
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Re: [time-nuts] Favorite counters (current production)?

[Anders Wallin]

The CNT-90/91 an 53230 both have graphical presentation, which is very
> beneficial. The SR-620 still have better performance even being older than
> everything else.
>

Magnus can you elaborate on the SR-620 performance?
In my hands the 53230A with a spec of 20ps single-shot does about 11-13 ps
RMS for a 1PPS TI-measurement between CH1 and CH2 - so in theory a single
channel is 1/sqrt(2) better than that.
In what measurements would an SR-620 be better?

The 53230A does have a design-flaw where one of the input BNCs has a very
narrow PCB-trace which tends to break. I think I've fixed 2 or 3 counters
with that same fault.

Anders
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Re: [time-nuts] Spice simulation of PSRR and phase noise

[Anders Wallin]

FWIW I recently took a peek inside a commercial distribution-amplifier and
it seems to use two LMH6702 op-amps in parallel.
There are two of these dual-LMH6702 stages with a 1:2 splitter after the
first, and then a 1:4 splitter after the second stage. 8 outputs in total,
with an additional op-amp driving each output.
A simulation that shows the difference in PN between a single LMH6702 and
the dual-op-amp idea would be nice.
For far-out (>100Hz from carrier?) PN only SNR might matter, so a SPICE
noise-simulation giving noise PSD at relevant (5-10MHz) frequencies might
give something?

Anders
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Re: [time-nuts] Distribution amplifier (again!) - now mostly ok but has gain peaking

[Anders Wallin]

On Sat, Jan 28, 2017 at 5:53 PM, Mattia Rizzi 
wrote:

> Have you tried to use clock distribution components like 5PB1108? You could
> use that to distribute the LT1711 output to the output stages
> *independently*. You could use also 5PB1108 as output stage as well (but
> this depends on your output voltage level), I got like >3V/ns on a 50ohm
> with 6 outputs tied together. For fine alignment a variable capacitor (or
> RC filter) at the output stage's input pin may do the job.
>

Hi Mattia, everyone,

I now had time to assemble a few distribution amplifiers using IDT5PB1108
(see [1], left side).
With my skills in length matching the traces (using Kicad) I still get
around 200ps peak-to-peak output skew between channels.
The chip datasheet spec is <50 ps pin-to-pin skew.

So now I tried adding a trimmer-cap on the input of the output-buffer.
I tried both 50pF and 10pF, but it seems 10pF gives a 500ps delay-tuning
range which is sufficient.
When tuning all channels to within 20ps P-P one day, I then got 50 ps P-P
when verifying this the next day.
Using BNC-cables and an SMA-BNC adapter on the output might not be the
greatest choice for picosecond repeatability...

I did the measurements with a 53230A and the reported values are the
average of 30-60 s of 1PPS pulses.
Some images with the board and results here:
http://www.anderswallin.net/2017/09/delay-tuning-with-trimmer-caps/

I also opened up a commercial pulse-distributor, and it has the same kind
of trimmer-caps before the output-stages.
It measured 28 ps peak-to-peak among 16 output channels.

I will incorporate a trimmer-cap into the next version of the "PDA" design
and publish on ohwr - when I have time..

Anders
[1] https://www.ohwr.org/attachments/5339
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[time-nuts] Isolated 1PPS-input for distribution-amp?

[Anders Wallin]

Hi all,
I'm looking for a solution for galvanic isolation of a 1PPS signal-input to
a distribution amplifier.

We have an old box using HCPL-2411 at the input followed by 74LS04, but the
degraded rise-time (from below 3ns out of a clock, to >12 ns out of the
box) and increased jitter (from below TIC-resolution of 20ps out of the
clock to 700ps std.dev at 100s out of the box) are now limiting our
measurements.

Does anyone have experience with a circuit with good rise-time and low
jitter?
Should I look for better optoisolators, or pulse-transformers, or something
else?

thanks for your input!
Anders

PS. I started on publishing my distribution-amplifier (non isolated) on the
ohwr.org site, see https://www.ohwr.org/projects/pda-8ch-fda-8ch/wiki/wiki
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Re: [time-nuts] gLAB PPP noisy clock residuals

[Anders Wallin]

> I have not been able to get a copy of the nrcan-ppp softwarepackage, so I
> am looking elsewhere. ESA gLAB looks like it might fit the bill. The
> problem, in short, is that the data I get from  postprocessing with gLAB is
> much, _much_ noisier than the results I get from submitting the RINEX files
> to NrCAN-PPP online service.
>

Hi Ole!
I did a comparison of a few PPP results some years ago, maybe you saw it
already
http://www.anderswallin.net/2013/12/comparing-gps-ppp-solutions/

For the web-service running NrCAN, there was an URL API that allows running
the filter/algorithm forward and backward ("filtfilt" in matlab or numpy),
to get rid of the initial transient in only the forward solution. You could
ask the maintainers, or I can try to dig in my archives (I should have
python code that submits RINEX to the service and retrieves the results).

>From my link above it looks like the troposphere-models are quite
different.
Here is a recent ".sum" summary file from a NrCAN run:
https://pastebin.ca/3816315
in section 2.7 it has the troposhpere model type, and in section 3.1 a
parameter "TZD random walk   (mm/hr):5.000"
if you dig in the ESA gLAB settings, can you set the ZTD-model identically
and see what happens?

If you post your RINEX:es and other relevant data I can try processing also
and see what I get.

cheers,
Anders
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Re: [time-nuts] Measuring coax temperature coefficient with a TICC

[Anders Wallin]

The recent supplement to Microwave journal has a piece on phase stability
of cables (predictably - written by a vendor of said cables..):
http://www.microwavejournal.com/publications/1/editions/223

maybe you can recalculate your results in PPM and plot against temperature,
to compare with the mw-journal plots?

Anders

On Sat, Apr 15, 2017 at 4:34 AM, Mark Sims  wrote:

> I finally got around to using a TICC to measure the temperature
> coefficient of 100 feet of generic RG-58 coax using a TICC.   The TICC was
> clocked by a HP 5071A 10 MHz output.  The 1PPS output was connected to the
> input of the coax and the TICC chB input.  The TICC chA input was connected
> to the coax output via an inline terminator.   The TICC was set to "debug"
> mode  and Lady Heather plotted the chB-chA timestamp difference (hence the
> negative cable delay values).
>
> The coax had been chilled down for 2 hours in a 5 degrees F in a freezer,
> connected to the TICC, and left to warm up in a 75 degree F room.   Over
> the 10F to 70F temperature range (measured with an IR thermometer) the coax
> delay spanned around 300 ps... so figure around 5 ps per degree F (10 ps
> per degree C) for 100 feet of cable.
>
> I'm adding currently adding the ability for Heather to use an external
> temperature sensor...
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Re: [time-nuts] RFDO - Experience and questions

[Anders Wallin]

FWIW, for fun I measured the LF stations MSF, DCF, and TDF just a few days
ago. The signals look like this from our site:
http://www.anderswallin.net/wp-content/uploads/2017/02/MSF.jpg
http://www.anderswallin.net/wp-content/uploads/2017/02/DCF.jpg
http://www.anderswallin.net/wp-content/uploads/2017/02/TDF.jpg

I guess the +/- 40 Hz side-bands on TDF are by design?

I have an SDR set up also, so the gnu-radio demodulators could run in
parallel on each of these, and the sdr sampling clock could come from a
local clock. One more project on the to-do list...

Anders


On Mon, Mar 6, 2017 at 12:42 AM, Iain Young  wrote:

> On 05/03/17 20:23, paul swed wrote:
>
> Gilles what signal is that at 162KHz. A European station? Nice thats its C
>> controlled.
>>
>
> That's TDF from France. Their equivalent of WWV/MSF/DCF. Used to carry
> the AM Station France Inter as well, but that went when France turned
> off all LW, MW, and LORAN stations at the end of 2016.
>
> The Time Signal is Phase Modulated (I have a gnuradio decoder which
> works very well if anyone is interested)
>
> See https://en.wikipedia.org/wiki/TDF_time_signal and
> https://en.wikipedia.org/wiki/Allouis_longwave_transmitter
>
> With no AM modulation, there are obvious benefits with regards to using
> it as a frequency reference. Average phase and frequency deviation is
> zero over 200msec (see link above for details)
>
>
> Iain
>
> PS, The signal is used by the French railways SNCF, the electricity
> distributor ENEDIS, airports, hospitals according to the Allouis link
> above
>
>
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[time-nuts] Distribution amplifier (again!) - now mostly ok but has gain peaking

[Anders Wallin]

Hi all,
I've been tinkering with another distribution amplifier design and made
some measurements earlier this week.
The goal is roughly 1:8 fan-out, gain of 0 dB, for good quality (Cs, maser,
OCXO) 5 or 10 MHz signals in the range of maybe +0 dBm to +15 dBm - in a 1U
form-factor.

Earlier I made an SMD version of the TADD-1 design [1] which showed about
-156 dBc/Hz far-out phase-noise but was quite sensitive to external noise
and required 12VDC power from a lead-acid battery as well as shielding in
aluminium foil for a 'quiet' PN-spectrum.
I then did some SPICE simulations [2] (never trust them without testing ;)
which indicated ADA4899 would be a good op-amp. In practice the
slew-rate/distortion was limiting and the AD4899 version didn't show better
PN.

This new version is inspired by looking inside a 6502[3] - and in the
mean-time I also measured and Ettus Octoclock [4] - but its performance
isn't so exciting..

My current design is now here: https://goo.gl/photos/WB8fYd4jzba7nXH18
So far my observations are:
- phase noise around -162 dBc/Hz at 10 MHz
- nice quiet PN-spectrum when unshielded and powered from lab-supplies
- this probably means the supply-section with common-mode choke, BNX025
filter and LT1963/LT3015 is working OK. I should probably build a
10Hz-100kHz LNA (e.g. [5]) to verify. I've used 2k@100MHz ferrites a lot
and an RC-filter on all supply pins - maybe overkill?
- an undesired feature is gain-peaking which increases from output ch1 to
ch8, shown here: https://goo.gl/photos/6QkoKakSPDdT7Acj7
I tried to improve it a bit by adding a 100pF cap at the start of the long
trace that feeds the output stages, but some gain-peaking still remains:
https://goo.gl/photos/qrkLzZ21ptcHxFsw6
- reverse isolation around 120 dB
- channel-to-channel isolation around 80 dB
- at 10MHz 1dB compression between +14 and +15 dBm
- IP3 perhaps +27dBm to +30 dBm.

Any ideas on how to deal with the long 'feeder-trace' that seems to be the
cause of the gain-peaking?
Anyway if not used at 100MHz perhaps my next version will have reduced BW
where the feeder-trace is not an issue..
Another issue is that the voltage regulators get quite hot when fed at
+/-12V and producing +/-6V. They should probably be positioned as far away
from the input/output amps and thermally disconnected if possible. I have a
+/-12V AC/DC brick on order - but a DIY linear PSU producing e.g. +/-8VDC
for the regulators might be better.

The picture gallery also shows a pulse distribution amp for 1PPS. It has an
LT1711 comparator feeding an 74AC14 buffer with length-matched traces to
74AC04's at the outputs. So far my length-matching didn't give zero
output-skew between the outputs - I see around 150-200ps skew which I tried
to tune a bit with wires and 0R resistors - without very much success.. any
ideas for improving this - or just leave it at 200ps skew?

cheers,
Anders

[1]
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-first-tests/
[2]
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-v2-simulations/
[3]
http://www.anderswallin.net/2016/02/symmetricom-6502-distribution-amplifier/
[4]
http://www.anderswallin.net/2016/09/ettus-octoclock-distribution-amplifier/
[5] http://cds.linear.com/docs/en/application-note/an83f.pdf
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Re: [time-nuts] PN/AM and 1.5Hz spur from frequency doubling?

[Anders Wallin]

I made some progress with this issue today.
It turns I was using a 75Ohm cable at some point (doh!) which caused a
'forest' of spurs far out. Possibly our other maser has a faulty/cut cable
which behaves similarly.
The final fix was to turn off our 25 MHz radio time-code transmitter which
was causing the strong close-in spur at around 1.5 Hz. It uses a modified
DCF77 code where it transmits full power AM-modulated 25MHz carrier for 0,
100ms or 200ms at the start of each second.

Here are PN plots of the 5MHz maser signal, same signal through 75ohm
reflective cable to the doubler, and through a 50ohm cable
 to the doubler which solves the far-out spurs, and finally turning off the
radio transmitter. The result is now close to the +6dBc/Hz expected for a
doubler.
https://goo.gl/photos/qKKvg3SfE1XKxtq17
as a time-series of residual phase the switchoff of the time-code
transmitter looks like so:
https://goo.gl/photos/jNVJK2kj1kGUkSVd9

Finally I tried it with the transmitter on, but reduced coupling into the
lab by disconnecting a few monitoring-cables. Strangely this shifts the
spur even closer in (close to 1Hz now) and reduces the amplitude as expected
https://goo.gl/photos/jG6rxfuC8R2QKchM6

What makes frequency doublers especially sensitive to this kind of
interference? The 25MHz carrier is phase-locked to better than 1e-12 to our
masers, so there can't reasonably be a 1-1.5Hz offset in the carrier
frequency. What is the interaction? (5th harmonic of 5Mhz mixes with 25MHz?)

Anders


On Fri, Jan 20, 2017 at 11:06 AM, Anders Wallin <anders.e.e.wal...@gmail.com
> wrote:

> Thanks for all the comments so far.
> I will try the doubler with another quieter source, and try removing
> various potential noise-sources and exchanging cables...
>
> I have now uploaded a few more images of the same data to the shared album
> linked in my earlier post.
>
> Anders
>
> On Thu, Jan 19, 2017 at 10:39 PM, Bill Byrom <t...@radio.sent.com> wrote:
>
>> I see spurs at 50 Hz and harmonics, which I assume are from the power
>> line at your location. This might be due to an oscillation in the power
>> supply regulator, leading to nonlinear regulator operation and
>> feedthrough of power line ripple. For example, low dropout regulators
>> can sometimes oscillate when an additional ceramic bypass capacitor is
>> added due to decreased phase margin in the feedback loop. It's also
>> possible that there is too much ripple before the regulator and you are
>> exceeding the dropout voltage, or that the regulator is going in and out
>> of an overcurrent condition. Many odd things may happen if the power
>> supply regular isn't working properly.
>>
>>
>> --
>>
>> Bill Byrom N5BB
>>
>>
>>
>>
>>
>> > _
>>
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>>
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>>
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>>
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>>
>>
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Re: [time-nuts] PN/AM and 1.5Hz spur from frequency doubling?

[Anders Wallin]

Thanks for all the comments so far.
I will try the doubler with another quieter source, and try removing
various potential noise-sources and exchanging cables...

I have now uploaded a few more images of the same data to the shared album
linked in my earlier post.

Anders

On Thu, Jan 19, 2017 at 10:39 PM, Bill Byrom  wrote:

> I see spurs at 50 Hz and harmonics, which I assume are from the power
> line at your location. This might be due to an oscillation in the power
> supply regulator, leading to nonlinear regulator operation and
> feedthrough of power line ripple. For example, low dropout regulators
> can sometimes oscillate when an additional ceramic bypass capacitor is
> added due to decreased phase margin in the feedback loop. It's also
> possible that there is too much ripple before the regulator and you are
> exceeding the dropout voltage, or that the regulator is going in and out
> of an overcurrent condition. Many odd things may happen if the power
> supply regular isn't working properly.
>
>
> --
>
> Bill Byrom N5BB
>
>
>
>
>
> > _
>
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>
> > To unsubscribe, go to
>
> > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
>
> > and follow the instructions there.
>
>
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[time-nuts] PN/AM and 1.5Hz spur from frequency doubling?

[Anders Wallin]

I'm seeing +20-30 dBc/Hz of excess AM/PN, as well as a strong 1.5 Hz spur
created by frequency doubling from 5 MHz to 10 MHz.
https://goo.gl/photos/GFx9tQoxrSmyzUQo8
The input amplitude to the doubler should be just above the recommended 11
dBm.
What's going on??

thanks!
Anders
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[time-nuts] Measuring sidereal/solar time? Re: A Leap Second is coming

[Anders Wallin]

out of curiosity, are there any amateur/semi-pro experiments that can
measure the length of the solar or sidereal day to sub-millisecond
resolution?
To reproduce data like this:
https://upload.wikimedia.org/wikipedia/commons/5/5b/Deviation_of_day_length_from_SI_day.svg

Something in the sky that goes "ping" every day - detected with a pointing
accuracy of < 1ms/24h or <0.01 arc-seconds (!?). Or perhaps two
satellite-dishes pointed at the sun and noise-correlation/interferometry??

Anders
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Re: [time-nuts] New Timestamping / Time Interval Counter: the TICC

[Anders Wallin]

Nice work!
On the website in the introduction you mention 22ps single-shot
time-stamping on the 5370A/B.
I think it's well established that the 53230A does about 11-12 ps for
time-intervals, which corresponds to about 9 ps single-channel. see for
example:
http://www.anderswallin.net/wp-content/uploads/2015/04/53230A_PPS_skew.png

Anders


On Wed, Nov 23, 2016 at 11:13 PM, Peter Vince 
wrote:

> Fantastic John - well done!  Yes, I'll definitely put an order in as soon
> as possible.
>
>  Regards,
>
>  Peter  (G8ZZR, London)
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Re: [time-nuts] Thinking outside the box a super reference

[Anders Wallin]

>
> > Just for the heck of it, I'd go laser instead of the old UHF lamp.
> >
> > With respect to precision machining, that space has changed a lot
> > over the last five years, with precision CNC machines, factory
> > or home-built, dropping dramatically in price.
> Yes, the laser technique is doable even if one has to build an ECDL.
> What would be nice would be a scheme that allows the same Rb filled bulb
> to be used to both lock the laser to the right wavelength and to detect
> that the microwave signal is also locked to the Rb microwave transition.
>

FWIW we have the remains of this experiment somewhere in the basement - but
no time or resources to really play with it...
http://lib.tkk.fi/Diss/2010/isbn9789526035024/article4.pdf
Fig 3 is a fairly clear overview of the two cells and loops, one for
stabilizing the laser wavelength, and one for the 3 GHz
sidebands/clock-transition.
For hobby tinkering I would expect the Rb-cells and the optical isolator to
be hard/expensive to source. Otherwise the electronics needed looks
DIY-able.

Anders
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Re: [time-nuts] theoretical Allan Variance question

[Anders Wallin]

FWIW this example in AllanTools generates white pm and compares to the
IEEE1139 ADEV formula:
https://github.com/aewallin/allantools/blob/master/examples/ieee1139_white_pm.py

two comments:
1. Theoretical white noise has infinite power, so limiting the RMS to some
value already implies you have limited the measurement bandwidth (f_h in
the formulas)
2. Interestingly my understanding of the phase-meters (Timepod/3120A and/or
DIY USRP SDR) is that they don't measure raw phase of the signal much
better than a 20ps counter. The trick is to measure the phase between
REF/DUT at a high sample-rate, and then dramatically reduce the bandwidth
by low-pass filtering numerically. So an ADEV(1s)<1e-13 (100-fold better
than a typical counter) is not done via some "magic" 100fs
phase-measurement, but instead by doing plain old ~20 ps phase measurements
at a high rate and averaging lots of them together.
I've been playing with an USRP phase-meter and hope to release some
software/results soonish.

Anders
(ITSF2016/Prague next week)


Hi Stu,
> If you have white phase noise with standard deviation of 1 then the ADEV
> will be sqrt(3). This is because each term in the ADEV formula is based on
> the addition/subtraction of 3 phase samples. And the variance of normally
> distributed random variables is the sum of the variances. So if your
> standard deviation is 0.5 ns, then the AVAR should be 1.5 ns and the ADEV
> should be 0.87 ns, which is sqrt(3)/2 ns. You can check this with a quick
> simulation [1].
>
> Note this assumes that 1 ns quantization error has a normal distribution
> with standard deviation of +/- 0.5 ns. Someone who's actually measured the
> hp 5334B quantization noise can correct this assumption.
>
> /tvb
>
> [1] Simulation:
>
> C:\tvb> rand 10 0.5e-9 0 | adev4 /at 1
> rand 10(count) 5e-010(sdev) 0(mean)
> ** tau from 1 to 1 step 1
>1 a 8.676237e-010 8 t 5.009227e-010 8
>
> In this 100k sample simulation we see ADEV is close to sqrt(3)/2 ns. The
> TDEV is 0.5 ns. This is because TDEV is based on tau * MDEV / sqrt(3). In
> other words, the sqrt(3) is eliminated in definition of TDEV.
>
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Re: [time-nuts] disappearance of NIST UT1 time service

[Anders Wallin]

somewhat related: if someone has NTP service distributing TAI, that could
be useful for monitoring how the leap second is added to UTC-distributing
normal NTP servers come December 31st?
might have to set one up myself if there are none in Europe?

AW

On Thu, Oct 27, 2016 at 1:50 PM, Mike Cook  wrote:

> Hi,
>
>   Does anyone know what happened to the NIST UT1 time service managed by
> Dr. Judah Levine?
>
> I lost contact with the server ut1-time.colorado.edu on the 24th this
> month at 20:15 UTC and there has been no response to NTP requests  since.
> I mailed Judah to find out what happened but have not as yet got anything
> back.
>
> Regards,
> Mike
>
> "The power of accurate observation is commonly called cynicism by those
> who have not got it. »
> George Bernard Shaw
>
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[time-nuts] Phase-noise through mixer?

[Anders Wallin]

Hi group!

Can someone help me with how phase-noise through a mixer is calculated?

Let's say I connect a 1 GHz signal with -80 dBc/Hz PN (wrt. 1GHz carrier)
at some offset to the RF port.
I then connect a 900 MHz signal with also -80dBc/Hz PN (wrt. 900MHz
carrier) at the same offset.
I'm interested in the 100 MHz IF signal (naively, will it have -77 dBc/Hz
PN wrt 100MHz? carrier?)

(ofcourse there might be a noise-figure through the mixer also)

thanks!
Anders
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Re: [time-nuts] Ettus OctoClock measurements

[Anders Wallin]

>
> > The results are decent but not stellar:
> > http://www.anderswallin.net/2016/09/ettus-octoclock-
> distribution-amplifier/
> > In particular the AM noise on the 10MHz looks high. Any
> thoughts/comments?
>
> I am not surprised. They used a digital clock distribution chip. The chip
> is not designed for lowest phase noise, neither is the surrounding
> electronics.
> And selling that whole thing, which is nothing more than the example
> circuit
> in the datasheet, for 1700 is a bit of a rip-off, IMHO.
>

In fairness my link was to the version also containing a GPSDO.
The price I see on the web for only the distribution amplifier is 960 eur.
Timetech and/or Microsemi are probably better - at a higher cost.


> IIRC your design beats theirs already in performance, doesn't it?
>

Yes, my prototype of the TADD-1 design with an AD8055 op-amp, powered from
a +12VDC battery, and wrapped in alu-foil to shield, looked quite good:
http://www.anderswallin.net/wp-content/uploads/2015/12/alufoil_and_battery.png
The 6502 is better and I opened it up to find it has an LMH6702 input stage
and LMH6609 output stages.
I will try that at some point.

Anders
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[time-nuts] Ettus OctoClock measurements

[Anders Wallin]

Hi all,
I measured an Ettus OctoClock with a 3120A phase-noise probe (for the
10MHz) and the 1PPS channel skew with a 53230A TIC.

The results are decent but not stellar:
http://www.anderswallin.net/2016/09/ettus-octoclock-distribution-amplifier/

In particular the AM noise on the 10MHz looks high. Any thoughts/comments?

For 1PPS a 200ps skew between fastest and slowest channel is not the end of
the world, but I would be interested in the cause. To produce 200ps skew
both a 4cm trace-length-difference and/or 200 mV of DC-offset (for a 1V/ns
slewrate signal) seem large?

Anders
(will build better distribution amp as soon as I getroundtoit..)
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Re: [time-nuts] NCOCXO anyone?

[Anders Wallin]

> rich...@karlquist.com said:
> > Also in 1996, phase microsteppers were already legacy technology and
> didn't
> > have a good reputation for spectral purity.  Another non-panacea.
>
> What is a phase microstepper and/or how does it compare to a DDS?
>
> (Google gets lots of hits, but they all refer to motors.)
>


H-maser aging is typically compensated by something like
spectratime femto-stepper
http://www.spectratime.com/products/itest/clock-instruments/FemtoStepper/
microsemi AOG
http://www.microsemi.com/products/timing-synchronization-systems/time-frequency-references/active-hydrogen-maser/aog-110
(there are probably others, please post if you know about them!)

afaik they contain a OCXO/BVA that is steered based on a DMTD measurement
against the input reference.


AW
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Re: [time-nuts] Quartz Crystal Motional Movement

[Anders Wallin]

> Indeed there is an physical limitation for the Q of piezoelectric
> resonators, which is given by phonon interactions etc. For quartz this
> limit is given approximately by Q*f = 15E12. See attached graph (sorry, in
> German).


NIce figure! Here's a similar one for MEMS resonators (mostly Si I think)
in a paper by Ghaffari et al. from 2013:
http://www.nature.com/articles/srep03244
>From the figure it looks like the MEMS resonator for on a line Q*f = 5e12

Anders
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Re: [time-nuts] Timelab and the 53220A - getting best results

[Anders Wallin]

A time-interval measurement between 1-PPS outputs of your two clocks is the
most straightforward to interpret.
With the 20ps 53230A I get a noise-floor of about 1.8e-11/tau(s) for this
measurement.
I haven't tried the 100ps version, I suspect the hardware is identical and
HPAK just de-rates the spec/firmware to 100ps in order to 'segment the
market'.

In frequency counting mode things are tricky because it does some sort of
omega-counting in default (CONT) mode.
This makes the effective bandwidth depend on the gate-time. (see 2nd image
of 2nd link).
The pi-counting mode is called RCON and is undocumented AFAIK. I got
3e-11/tau(s) with a 1s gate time and here I would expect noise-floor
measurements to fall on this same line independent of gate time (I haven't
verified this).

http://www.anderswallin.net/2015/06/cont-vs-rcon-mode-on-the-53230a-frequency-counter/
http://www.anderswallin.net/2015/04/keysight-53230a-noise-floor-test/

Anders


On Sat, May 28, 2016 at 7:11 PM, Nick Sayer via time-nuts <
time-nuts@febo.com> wrote:

> So far, I’ve been configuring my 53220A for frequency measurements with a
> 500 msec gate time, and using the external reference and one input.
>
> If instead I send the two devices into inputs A and B, and ask for the
> time interval between the two and give that to Timelab, my results look
> quite a bit worse.
>
> At the moment, I’m doing that with a pair of 5680As. The ADEV at 100s is
> reasonably close to the spec at 1.83E-12, but the tau at 10s is what it’s
> *supposed* to be at 1s: 1.43E-11. At 1s, it’s 1.42E-10. The line is quite
> linear between those points, but the slope is way off the spec. The
> frequency difference graph supports this view - it shows a ±2E-10 “haze.”
>
> I don’t have any reason to believe either oscillator is misbehaving to an
> extent that would explain this. I’m fairly sure I’m making some kind of
> fundamental newbie mistake and the test setup is introducing some sort of
> error, or I’m inside of the uncertainty of the 53220A and that’s why it’s
> showing poorly at low tau. My money is on the former. :)
>
> The behavior I see suggests that how Timelab works with the 53220A is that
> it sends a command to obtain a single measurement over and over again.
> Thus, the network latency figures into the measurement timespan, I think.
> I’m sure there’s a way to record measurements in the 53220A internally and
> then export that file into Timelab, but I haven’t figured that out yet.
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Re: [time-nuts] Capturing a 1PPS signal with a Keysight 53230A

[Anders Wallin]

4.
With 1PPS you probably want to run it in time-interval mode and measure the
phase difference of  two clocks: have it start on CH1 with (say) the 1PPS
from your microsemi, and stop on CH2 with your uBlox.
You should still have it on ext-REF with 10MHz from the Rb-clock.

gate time refers to measurements in frequency counter mode, usually not
used with 1PPS signals.

On Mon, May 2, 2016 at 2:09 PM, Peter Membrey  wrote:

> Hi guys,
>
> I'm looking to measure and characterize the 1PPS output of a uBlox MAX M6Q
> using a Keysight 53230A. Specifically, I'm mostly interested in the period
> of the signal, how close it is to exactly 1Hz and how that signal changes
> over time.
>
> The Keysight is using the 10Mhz output of a SRS FS-725 Rubidium Frequency
> Reference (which is being disciplined by a PPS from a microsemi S600 GPS)
> as an external reference.
>
> I've currently got the channel configured as follows:
>
> * DC
> * 50Ohm
> * Bandwidth filter enabled
>
> The default gate time is 100ms, which if I leave it configured for that,
> it will never show a reading. I can get it to start giving a reading if I
> set the gate time to 3 seconds but for reliable readings, I need to set it
> to at least 5 seconds.
>
> So, here's my questions:
>
> 1. I would like to capture the period of each pulse - is this doable with
> my set up?
> 2. What does gate time actually mean? I've read a number of descriptions,
> but I'm still not 100% clear on what it means in this context and what
> impact it has
> 3. How exactly does the gate time work in this case? I mean if it captures
> data over 5 seconds and gives one reading - what actually is that reading?
> An average? One of the samples?
> 4. Should I be doing anything differently?
>
> Ideally, what I'd like to do is capture the period of each pulse
> individually so that I can do an Allan variance on the data over a period
> of time.
>
> I've googled around and I've read numerous guides, but they mostly seem to
> cover faster signals (like 10Mhz sine wave) rather than the much slower
> PPS. I asked a very similar question on the EEVBlog forum, and the
> suggestion was to use time-stamp capture with the rise time, but
> unfortunately, it never seems to see the signal, even though the gate
> indicator flashes every second.
>
> Thanks in advance for any advice or guidance!
>
> Kind Regards,
>
> Peter Membrey
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[time-nuts] PICDIV build

[Anders Wallin]

hi all, I wrote down some notes on a recent PICDIV build and measurements:
http://www.anderswallin.net/2016/04/picdiv-frequency-divider/

If/when I make v2 of this board:
- any suggestions for boosting the output amplitude of both 1PPS and 10MHz
CMOS? Something that drives 3.3Vpp into 50R with ~few ns rise time?
- any obvious mistakes that cause the phase-noise observed? Mostly I think
50/100Hz and harmonics would be nice to suppress..

thanks!
Anders
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Re: [time-nuts] [Announce] Simulation software for powerlaw noise and PTP clock synchronization

[Anders Wallin]

>
> I would like to announce the public availabilty of two software projects
> which I have been working on for my master thesis:
>
> * LibPLN: a portable C++ library for the efficient simulation of Powerlaw
> Noise (PLN)
>

Do you get agreement between PLN time-series and calcluated ADEVs, as per
IEEE1139-2008 table B.2 ?

I tried [3] using python libraries colorednoise [1] (also based on
Kasdin) and allantools [2], but it gives ADEVs that are
systematically higher than predicted by theory. OTOH the calculated MDEVs
seem to fall on the line that theory predicts. Image here:
http://www.anderswallin.net/wp-content/uploads/2016/04/colorednoise-1.png

On your libPLN page the time-series graph is called 'time deviation' which
could be a bit confusing as there is also an ADEV-like statistic called
time deviation. Perhaps time-series or 'phase observations' or similar is
better?


Anders
[1] https://github.com/jleute/colorednoise
[2] https://github.com/aewallin/allantools
[3]
https://github.com/jleute/colorednoise/blob/master/example_noise_slopes.py
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Re: [time-nuts] Unix software to generate nice looking *DEV plots

[Anders Wallin]

allantools has functions for most of the xDEV statistics, and it is tested
against Stable32
https://github.com/aewallin/allantools
or
https://pypi.python.org/pypi/AllanTools

matplotlib works for plotting, but there are probably many alternatives.

Anders


On Thu, Mar 17, 2016 at 7:35 PM, Didier Juges  wrote:

>
>
> Here is what my tool looks like:
> www.eds-fl.com/misc/graph/index.php
>
> You need to download a data file first, I added a link to download a small
> file 9kB.
>
> Again, this is not an ADEV tool, the file format is binary (came out of an
> old DOS tool that could not plot to save its life...) but it's an example.
> Some advantages are that you do not need to install anything on your
> computer and it is by default multiplatform :)
>
>
> On March 17, 2016 7:25:08 AM CDT, John Ackermann N8UR 
> wrote:
> >Hi Attila --
> >
> >I have some stuff that does ADEV and similar calculations and shoves
> >the
> >results into plots using the Grace plotting tool.  It's basically a
> >perl
> >script using some document formatting templates and a couple of shell
> >scripts for control.  I use it to automagically create web pages such
> >as
> >those at
> >
> >http://www.febo.com/pages/plots/chronos/
> >
> >Let me know off list if you're interested and I can package up the
> >latest version; I'm working on an update now.
> >
> >John
> >
> >
> >On 3/17/2016 6:29 AM, Attila Kinali wrote:
> >> Moin,
> >>
> >> I'm looking for some non-GUI software to generate the different *DEV
> >> plots we generally use to asses oscillators with. Timelab is nice,
> >> but if you are evaluating two dozen measurements using different
> >> parameters, it becomes very tedious to generate the plots. Not
> >> to talk about the problem that the plots are not really reproducable,
> >> which is a very important property, when publishing results.
> >>
> >> I could for sure write myself wrappers around
> >gnuplot/ploticus/mathplotlib/..
> >> to generate the *DEV plots, but I'm not keen on reinventing the
> >wheel.
> >>
> >> Thus I'd like to ask whether someone has any hints on what to use.
> >>
> >>  Attila Kinali
> >>
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> --
> Sent from my Moto-X wireless tracker while I do other things.
> --
> Sent from my Moto-X wireless tracker while I do other things.
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Re: [time-nuts] MV89A / MTI-260 / HP10811 carrier board

[Anders Wallin]

Hi, looks quite useful!
What's the benefit of the Xilinx CPLD (2-3 dollars/euro) over a PICDIV (<1
dollar/euro) ?
Sync-input for the PPS-output would be useful. Also a PPS LED that blinks.
If the PPS-divider is directly under the OCXO it will get more or less warm
- could that be a problem?

What's the idea with the mixer/DIY-PLL? Did you look at PLL-chips instead?
Would it make sense to have the time-constant for the PLL-loop adjustable
with jumpers or a pot? Lock-indicator LED?

Could the board be 100mm wide with all the connections on one 100mm side,
to allow vertical rack-mounting ('plug-in' unit) in a 3U enclosure?

here's a link to a similar-ish board, for comparison/inspiration:
http://www.qsl.net/bi7lnq/distribution_amp/v1.5/10M_distributor.pdf

cheers,

Anders
PS. use Kicad for your next OSHW design! ;)


On Thu, Feb 25, 2016 at 5:25 PM, Gerhard Hoffmann  wrote:

> HI,
>
> I have made some progress on my crystal oven carrier board.
>
> It will offer a home for one of these:
>
> - MTI-260
>
> - Morion MV89A
>
> - HP 10811-611
>
>
> It provides regulated voltages for either of them, and the needed
> electronics.
>
> It will be possible to lock the resident oscillator to an external
> reference frequency,
>
> tune it a few Hz using a 10-turn-pot or an external tuning voltage from 0
> to 5 volts.
>
> The 10811 oscillator does not have a stable tuning reference voltage
> output, it will be
>
> provided.
>
> There is a Xilinx Coolrunner 2C64 CPLD that generates a 1pps output from
> the
>
> resident oscillator with the usual 20 us pulsewidth.
>
> The squarer that feeds the CPLD is either a LT6759-4 or my implementation
> of
>
> C.Steinmetz's interpretation of C.Wenzel's version of the standard
> differential limiter.
>
> The 1PPS can drive 3V3 CMOS, terminated with 50 Ohms. The output of the
> CPLD
>
> is re-clocked in a 74LVC74 Flipflop directly from the limiting amplifier.
>
> There is a 1 stage common base isolation amplifier between the output of
> the oscillator
>
> and the output of the board. It can be configured to work as a push-pull
> active frequency
> doubler without attenuation instead. There are 2 or 3 crystal notches to
> remove the
> closest (sub-)harmonics without affecting carrier phase stability.
>
>
> Board size is abt. 100 * 110 square mm.
>
> The design is modular from predefined macros. You can cut it into pieces
> and get:
>
>
> 3 positive voltage regulators, LM317 style
>
> 1 negative voltage regulator, LM337 style
>
> 2 current feedback amplifiers using LMH6702 / AD8009 etc
>
> 1 ring mixer using a low 1/f noise Avago diode ring
>
> 1 PLL-regulator
>
> 1 isolation or frequency doubler amplifier
>
> 1 LT6759-4 limiter
>
> 1 Wenzel limiter
>
> 1 Xilinx 2C64 Coolrunner with pins on 100 mil grid
>
> 1 3V3-CMOS reclocked driver for 50 Ohm load.
>
> 1 input power meter
>
>
> Connections to the modules are on a 100 mil grid, so one can
>
> rearrange/recycle everything on Vector board or such.
>
> This is open source hardware under BSD rules.
> I do not intend to sell boards on a commercial base,
>
> maybe there will be some samples to get things started.
> All parts are available from Digikey/Mouser.
>
> I'm currently doing the layout and will be trough with it in a week or so.
> proposals, spotted errors, what to do with the empty space etc. are
> welcome.
> (but not on parts values, that will be taken care of later)
>
> circuits can be found under
>
> <
> http://www.hoffmann-hochfrequenz.de/downloads/CrystalOvenCarrierBoard.pdf
> >
>
> This is no product documentation but a quick snapshot as of this afternoon.
> One thing that is missing is sync'ing on a 1PPs instead of the external
> frequency reference.
>
> regards, Gerhard, DK4XP
>
>
>
>
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[time-nuts] Distribution Amplifier: a look inside the 6502B

[Anders Wallin]

Hi all,
I'm continuing with my distribution amplifier project described here:
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-first-tests/
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-v2-simulations/

The conclusion from those v1 board tests were that the AD8055-based
amplifier phase noise floor is at around -156 dBc/Hz while an old
Symmetricom 6502B I have in the lab is at -163 dBc/Hz. It would be nice if
the new design was at least as good as the 6502B ;)

On the v2 board I improved the power-supply with more filtering (BNX025)
and changed the layout to take SO-8 op-amps with an analog-devices style
feedback pin-1 and exposed bottom/GND pad.
With an AD4899-1 the results are in principle OK with small amplitude
input, but I think the limited slew-rate of (310V/us) causes
compression/distortion quite quickly and the phase noise is actually worse
(-150 dBc/Hz) at +7 dBm output compared to +4 dBm signal level ( ca -155
dBc/Hz). Contrary to simulations I didn't get 12 dB better phase noise out
of the AD4899-1 - beware of simulations I guess is the lesson! ;)
I also tried an AD8000, but this op-amp is not stable on my layout
(oscillates at 470 MHz).

Yesterday I opened up the 6502B to reveal a LMH6702-based input-stage and
an LMH6609-based output stage.
The files are on dropbox:
https://www.dropbox.com/sh/3vxyu87ax5cqjyf/AACQWDG3lN5lpnvTAqRXKW9ia?dl=0
Maybe someone in the group already has a schematic, home made or official,
for the 6502B?

To me the signal path looks like:
R1 is 50 ohm (switchable) termination to GND. When in hi-Z mode the input
impedance is R2=2k.
The input stage LMH6702 looks like an inverting amplifier with gain -RF1/R
= -133/100.
The distribution to output stages is via a small resistor R7=10R, and then
there is (small?) loading of the input-stage by the level-detector/alarm.
The output stage looks like a non-inverting circuit with a 1k/1k R21/R22
divider on the input and gain of 1+R23/R19 = 2.

Any comments/ideas of why they use a different op-amp for the output stage?

The powersupply is nothing fancy at all: LM317 and LM337, two devices in
parallel I think.

What are the parts "Dale 100" and "Dale R27"? Someone suggested resistor
networks to me. "Dale 100" is used as the R in the first of two RC-filter
stages on all power-supply pins. What is the benefit of 2 (or 3?) resistors
in parallel?
"Dale R27" is used on the output, just after a 51R1 output-impedance
resistor and before a (very small?) capacitor C15 to ground.

Almost half of the components deal with the alarm-signal, which to me looks
like a level detector built around the dual-opamp LM358, where input and
10x outputs possibly share a common single alarm-trace?

For the next version I will either try to make a stable schematic/layout
for the AD8000 or try the LMH6702/LMH6609. I will skip the alarm-circuit of
the 6502B, and perhaps also change to bipolar simpler supplies as compared
to the unipolar TADD-1/v1/v2 design.

If anyone wants the kicad-schematic I threw together just email me.

Anders
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[time-nuts] Distribution amplifier, v2 simulation+design

[Anders Wallin]

Hi all,
Based on the response to my distribution amplifier prototype I
ran a few SPICE simulations with the old AD8055 design and an improved
design.

The changes are:
- better op-amp
- improved DC-bias "T" circuit
- lower resistance values (esp. gain-setting resistors)

results & discussion in my blog:
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-v2-simulations/

The simulations would indicate a 12 to 13 dB improvement in noise floor is
possible. I could not find a good ADA4899-1 spice model. One has realistic
AC gain response but unrealistic 1/f noise. The other model I found has a
realistic 1/f noise but infinite AC gain bandwidth :(

again suggestions are welcome, I'll probably order boards and parts for the
next prototype in a few days.

I will look at Bruce's suggestion for the BNX002 (SMD equivalent
available?) on the powersupply. There is already a common-mode choke (TDK
ZJYS) and an NFE61P before the regulator, as well as ferrites before the
bypass-caps and vcc-pin of each output amplifier.

thanks!
Anders
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Re: [time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

[Anders Wallin]

> > AD8055 in non-inverting circuit with 1+2k7/2k7 gain has 9.6 nV/sqrt(Hz)
> > input-referred voltage noise PSD (if I calculated correctly..)
>
> With +10dBm input the corresponding SSB PN floor should be  around
> -163dBc/Hz.
>

HI,
How is that calculated? I only get this far:
9.6nV/sqrt(Hz) into a 50R load is 1.8e-18 W/Hz or -147.3 dBm/Hz

what then? split half-and-half into AM and PN, and how to relate that to
the carrier power +10dBm?

thanks,
Anders
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Re: [time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

[Anders Wallin]

Thanks for all the useful comments!
Things improved quite a bit just by wrapping the (insulated) board in
aluminium foil:
http://www.anderswallin.net/wp-content/uploads/2015/12/alufoil_and_battery.png

Op-Amps:
Maybe it wasn't clear enough on schematic, but I used the AD8055 (as in
TADD-1). The TL071 is there just because it comes standard with KiCad -
sorry for the confusion.
OPA827 doesn't have the slew-rate for +10 or +20 dBm at 10 MHz.
I was looking at ADA4899-1, but with the exposed pad it's not a direct
replacement and might require a new board.

Biasing:
I didn't understand why a "T" of resistors is better than a simple voltage
divider? The extra resistor is R3 in Bruce's second attachment.
What is the noise contribution of the biasing resistors?

Battery:
The lead acid battery was only used as a convenient DC source in the lab. I
would need to find a quiet SMPS or linear supply for permanent
installation.
Additional filtering on the 12VDC input might be still be required. Results
with the battery are good, so does that 'prove' the schematic is OK after
the linear regulator?

Isolation measurements:
Not done yet. I want to get one good channel first ;)
Would this be done by feeding a known amplitude RF (at 10.1 MHz or
something?) to an output-channel, and looking at the feedthrough to an
another output-channel or to the amplifier input with e.g. a spectrum
analyzer?

Far-out PN/AM is still 7dB short of the 6502!
Looks like an SNR issue to me, rather than some issue with the linear
regulator noise feeding through?!
AD8055 in non-inverting circuit with 1+2k7/2k7 gain has 9.6 nV/sqrt(Hz)
input-referred voltage noise PSD (if I calculated correctly..)
With an ADA4899-1 and lower value resistors I get about -4.5 dB improvement
to 3.4 nV/sqrt(Hz) input-referred
Could they run two or more amplifiers in parallel on the 6502 to get
1/sqrt(N) type improvements - or are there still cheap gains to be made
with my circuit?

thanks,
Anders


On Fri, Dec 18, 2015 at 6:32 PM, Pete Lancashire <p...@petelancashire.com>
wrote:

> When I used a Lead acid battery as a low noise and isolated power source I
> raided the kitchen. Put the batter inside
> a polyethylene container they type with a 'snap tight' lid. Then found in
> my junk a nylon barb to threaded fitting and
> some Tygon tubing to create an external vent. In another junk box a sealed
> MS socket and its mating plug.
>
> It solved three things venting to where it didn't matter, sealed becoming
> not sealed and puking and solving
> shorting from touching things.
>
>
>
>
>
> On Fri, Dec 18, 2015 at 7:22 AM, Chuck Harris <cfhar...@erols.com> wrote:
>
> > One of my other hats involves advising electronics scrap and
> > recycling companies, and the repair of all manner of electronics
> > equipment.
> >
> > In all of the equipment I have rummaged through I can state the
> > following without reservation:
> >
> > I have never seen any sign of damage caused by properly float charged
> > sealed lead acid batteries.
> >
> > I have seen lots of serious damage caused by trickle charged nicads.
> >
> > I have seen some very serious damage caused by lithium iodide pacemaker
> > cells at end-of-life.
> >
> > I have seen lots of damage caused by carbon-zinc, and alkaline cells.
> >
> > Lithium ion cells behave like electrolytic capacitors.  They want to
> > have their initial inrush current limited to about 1C, and they must
> > have their final charge voltage limited to 4.2V.  They will tolerate
> > being floated at 4.2V for quite a while, but that will ultimately lead
> > to their capacity being compromised.
> >
> > A simple backup charger for a LiIon cell would be a constant voltage,
> > current roll back supply that is controlled by a timer that charges
> > the cell every time power is restored, and several times a year if
> > power doesn't fail.
> >
> > Discharge must be abruptly stopped when the cell voltage drops below
> > around 2V... the exact value varies by the manufacturer.
> >
> > -Chuck Harris
> >
> >
> > Dr. David Kirkby (Kirkby Microwave Ltd) wrote:
> >
> >> On 17 Dec 2015 21:00, "Anders Wallin" <anders.e.e.wal...@gmail.com>
> >> wrote:
> >>
> >>>
> >>> First prototype assembled today, tested with 12 VDC SMPS wall-wart
> supply
> >>> and with 12 V lead-acid battery.
> >>>
> >>
> >> Anders
> >>>
> >>
> >> Is the lead acid battery supposed to be there so the unit continues to
> >> function if power is removed?
> >>
> >> If do, I believe that the choice of a lead acid battery is a poor one.
> 

Re: [time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

[Anders Wallin]

First prototype assembled today, tested with 12 VDC SMPS wall-wart supply
and with 12 V lead-acid battery.
Compared against a SRS FS710 and a Symmetricom 6502 and John Ackermann's
2007 plot:
http://www.anderswallin.net/2015/12/frequency-distribution-amplifier-first-tests/

What does the 6502 do differently? It is maybe 5 to 8 dBc/Hz better both in
PN and AM from around 1 kHz and out.

My 'ultra-low-noise DC-supply' in the form of a lead-acid battery improves
things somewhat, but some spurs still remain:
http://www.anderswallin.net/wp-content/uploads/2015/12/2015-12-17_fda_spurs_and_comments.png
interpretations and explanations are welcome!
The board was not enclosed in a metal can for these tests.

The regulator is an LP38798
http://www.ti.com/lit/ds/symlink/lp38798.pdf


Anders


On Tue, Dec 1, 2015 at 12:54 AM, Bruce Griffiths <bruce.griffi...@xtra.co.nz
> wrote:

> Anders
> U101 only needs to have a gain of 1 at dc so replace R104 and R105 with a
> capacitor connected to ground.
> Adjust the other components of the gain determining network
> accordingly.Also the junction of the power supply divider R102 and R103
> should be heavily capacitively bypassed to ground and a resistor placed
> between this junction and U101's noninverting input.
>
> Excess Sub Hz PN is usually due power supply noise or thermal fluctuations
> due to air currents/ convection.
> Most of the so called super regulator circuits  should be more than quiet
> enough with an LM329 reference.A damped LCR filter at the input will
> improve the PSRR at switchmode output frequencies.
>
> Bruce
>
>
>
> On Tuesday, 1 December 2015 9:02 AM, Anders Wallin <
> anders.e.e.wal...@gmail.com> wrote:
>
>
>  HI all,
> I need to build a few distribution amplifiers (>90% for 10MHz, sometimes
> maybe 5MHz) and instead of reinventing the wheel I decided to try to
> modernize the TADD-1 into an all (almost) SMD design. Here are some draft
> sketches:
>
> http://www.anderswallin.net/2015/11/frequency-distribution-amplifier-plans-a-k-a-smd-tadd-1/
>
> Does this sound/look reasonable or crazy?
> Any suggestions for op-amps to try and/or compare to the AD8055?
> What causes the extra phase-noise below 1 Hz offset in John A's result:
> https://www.febo.com/pages/amplifier_phase_noise/amplifier_phase_noise.png
>
> Suggestions for a low noise DC-regulator circuit? The 12-24VDC supplied to
> this board will most likely come from a switched-mode PSU, so filtering of
> common-mode noise is mandatory.
> I found the TI LP38798 shown in the schematic by googling - if someone has
> a proven a measured design that would be a safer choice. In any case more
> filtering (e.g. ferriites) is probably a good idea.
>
> This design will be available on my blog or on github when it is done - if
> anyone is interested.
>
> Thanks,
> Anders
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>
>
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Re: [time-nuts] Phase noise from Allan Deviation ?

[Anders Wallin]

>From PN to ADEV you integrate under the PN-curve with a certain
weighting-function. This paper shows the weighting function:
https://www.researchgate.net/publication/6308454_Considerations_on_the_measurement_of_the_stability_of_oscillators_with_frequency_counters

to go the other way around you would indeed have to assume the shape of the
PN-curve, such as the Leeson model or similar. This is quite an assumption
and probably best avoided.

What you want to do is rather than mix down to 1Hz instead mix down to
maybe 1 kHz...200 kHz or so - stream all those phase-samples to the
computer, and compute the PN as the PSD of the phase data.
As an aside I've found that FFT (e.g. Stable32 uses this) sometimes gives
funny PSD results, and the Welch-method (periodogram) is more robust.

Anders


On Mon, Dec 14, 2015 at 5:15 AM, Tom McDermott  wrote:

> I've constructed a homebrew setup to measure time intervals using a
> software defined radio.  Basically a single-channel downconversion to
> about one hertz, then count samples from the SDR clock to time stamp
> the zero crossings.  This is done in gnuradio and saved to a file for
> post processing. The resolution is theoretically good, but the accuracy
> is unknown.
>
> The result produces ADEV vs. Tau charts with reasonably sane looking
> results.
> The 'unknown' is a Rubidium oscillator locked to CDMA pilot (TS2700),
> and the internal crystal oscillator in the SDR radio as the reference.
> Thus, ADEV probably is mostly measuring that internal crystal rather than
> the TS2700.  Later on a GPSDO will be tried as the reference clock to
> see if the Adev results are better.
>
> It brings up a question:  Is it possible to estimate the phase noise of
> that
> internal crystal from the ADEV measurements?  There are a bunch of
> papers that go the other way:  from Phase Noise to Adev.   Searching
> brings up only one paper that goes from ADEV to Phase Noise but it's text
> does not seem to be readily available.  It apparently models the oscillator
> as a couple of well known error models.
>
> -- Tom, N5EG
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Re: [time-nuts] Data collection from 5115A phase noise test set?

[Anders Wallin]

Thanks for these useful comments!

It seems there is no way to estimate frequency from looking at the phase
data then?
Does TimeLab have automated collection for the frequency-counter data on
the control port?

Anders


On Fri, Dec 11, 2015 at 2:51 AM, John Miles  wrote:

> > Hi all,
> >
> > A 5115A phase noise test set landed in our lab and I am wondering about
> the
> > data collection.
> > It has two telnet ports one for commands and one for phase data.
> > When issuing "start" on the command-port it starts spitting out
> > phase-difference values on the data port.
> >
> > However it seems to me that the phase data alone (REF-DUT phase, in units
> > of the REF period) is almost useless without knowing the internal
> workings
> > of the device.
> > The phase values are clearly not the true phase difference, which would
> > quickly accumulate to a huge number with e.g. REF=10MHz and DUT=11MHz.
> > My
> > understanding is that digital downconversion (DDC) is performed on both
> REF
> > and DUT signals, and without knowing the LO frequencies for the DDC the
> raw
> > phase data alone is almost useless.
> >
> > The command prompt does have commands for displaying the internally
> > calculated ADEV, L(f), frequency-counter readings, etc. and these seem to
> > show correct and OK values, but there seems to be no way to reproduce
> e.g.
> > the ADEV or frequency-counter values/statistics from the raw phase values
> > on the data port??
> > Is this correct? Any other experiences with the 5115A or higher end
> 5120A?
>
> The shorter-term ADEV values on the 5120A/5125A test sets are
> mathematically backed out of the phase noise data.  They will never
> perfectly match the ADEV values you get from plotting the phase data stream
> in my experience.
>
> I don't actually know what they do on the 5115A, though -- since it
> doesn't do cross-correlated PN, there's presumably no reason to derive the
> short-term ADEV plot from the PN data pipeline.  I'd expect the plots to
> match in that case, apart from any errors due to different measurement
> bandwidths and ADEV bin distributions.
>
> It's also true that there will always be an arbitrary phase slope error
> due to the mismatch between the frequency estimate used to tune the
> internal DDCs and the "real" frequency of the incoming data.  Knowledge of
> the actual DDC core frequencies would not be enough to correct for this
> behavior, because you would also need to know how far off they are.  The
> true frequency offset can't be measured ahead of time with perfect
> certainty, so it has to be estimated, and the resulting error will often
> dominate the slope of the phase-difference graph.
>
> The TimePod and 3120A test sets allow you to specify the input and
> reference frequencies explicitly to obtain a valid phase slope in residual
> measurements and other cases where the exact frequencies are known by the
> user.  But this is something you have to remember to do prior to the
> measurement, and you still don't get a calibrated absolute offset.
>
> (Also, note that TimeLab can read both phase and PN data from 51xx test
> sets without the need to use a Telnet client.  Not that it helps with this
> particular issue, of course.)
>
> -- john, KE5FX
> Miles Design LLC
>
>
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[time-nuts] Data collection from 5115A phase noise test set?

[Anders Wallin]

Hi all,

A 5115A phase noise test set landed in our lab and I am wondering about the
data collection.
It has two telnet ports one for commands and one for phase data.
When issuing "start" on the command-port it starts spitting out
phase-difference values on the data port.

However it seems to me that the phase data alone (REF-DUT phase, in units
of the REF period) is almost useless without knowing the internal workings
of the device.
The phase values are clearly not the true phase difference, which would
quickly accumulate to a huge number with e.g. REF=10MHz and DUT=11MHz. My
understanding is that digital downconversion (DDC) is performed on both REF
and DUT signals, and without knowing the LO frequencies for the DDC the raw
phase data alone is almost useless.

The command prompt does have commands for displaying the internally
calculated ADEV, L(f), frequency-counter readings, etc. and these seem to
show correct and OK values, but there seems to be no way to reproduce e.g.
the ADEV or frequency-counter values/statistics from the raw phase values
on the data port??
Is this correct? Any other experiences with the 5115A or higher end 5120A?

thanks,
Anders
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Re: [time-nuts] Phase microstepper designs?

[Anders Wallin]

Do you mean delay-generators for 1PPS? Or a finely-tunable frequency
synthesizer?

For 1PPS, the fine-delay FMC card might be worth a look:
http://www.ohwr.org/projects/fmc-delay-1ns-8cha/wiki

afaik it works by first time-stamping the input pulse, then delaying the
output with an integer number of clock cycles on the FPGA, and for
sub-cycle fine delay it uses programmable hardware delay-lines (these run
quite hot on the board),
If you need only 1PPS that is synchronous to some input 10MHz signal then
the design is much simpler since you don't need to time-stamp an
asynchronous input pulse first.

SRS DG645 and similar might be worth a look too.

Anders

On Wed, Dec 9, 2015 at 12:26 PM, Attila Kinali  wrote:

> Moin,
>
> I just tried to figure out how phase microsteppers are usually build,
> but, beside the time-nuts discussion from 10 years ago and US patents
> US4358741 and US4417352 my search turned out empty. I am pretty sure
> that I used the wrong search terms and there should be lots of
> documentation
> out there. Can someone give me a hint what to look for?
>
> Attila Kinali
>
> --
> It is upon moral qualities that a society is ultimately founded. All
> the prosperity and technological sophistication in the world is of no
> use without that foundation.
>  -- Miss Matheson, The Diamond Age, Neil Stephenson
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[time-nuts] SMD TADD-1 distribution amplifier - seeking comments and suggestions?

[Anders Wallin]

HI all,
I need to build a few distribution amplifiers (>90% for 10MHz, sometimes
maybe 5MHz) and instead of reinventing the wheel I decided to try to
modernize the TADD-1 into an all (almost) SMD design. Here are some draft
sketches:
http://www.anderswallin.net/2015/11/frequency-distribution-amplifier-plans-a-k-a-smd-tadd-1/

Does this sound/look reasonable or crazy?
Any suggestions for op-amps to try and/or compare to the AD8055?
What causes the extra phase-noise below 1 Hz offset in John A's result:
https://www.febo.com/pages/amplifier_phase_noise/amplifier_phase_noise.png

Suggestions for a low noise DC-regulator circuit? The 12-24VDC supplied to
this board will most likely come from a switched-mode PSU, so filtering of
common-mode noise is mandatory.
I found the TI LP38798 shown in the schematic by googling - if someone has
a proven a measured design that would be a safer choice. In any case more
filtering (e.g. ferriites) is probably a good idea.

This design will be available on my blog or on github when it is done - if
anyone is interested.

Thanks,
Anders
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Re: [time-nuts] SRS FS710 spurs at 50Hz and harmonics?

[Anders Wallin]

Hi all, thanks for all the suggestions.
I am starting to think this is a feature not a bug.
I tinkered with the FS710 a bit today. It shows about 600mVpp 100Hz
sawtooth on the +/-13.9VDC input to the voltage regulators.
I changed the big electrolytic caps and the smaller tantalum caps around
the 7805/7905 regulators - but no change to the sawtooth.
With a 1M 10x probe and a cheap scope there is no visible 100Hz ripple on
the +/-5V regulator outputs.
some new pictures in my blog:
http://www.anderswallin.net/2015/09/srs-fs710-noise-measurement/

Maybe my earlier result with strong spurs was a result of a ground loop
between REF-distribution-amp, 3120A, and this F710-distribution amp. They
were probably plugged in to different AC outlets...

Anders


On Thu, Oct 1, 2015 at 1:52 PM, Bob Camp <kb...@n1k.org> wrote:

> Hi
>
> It can also be a blown diode in the bridge. When that happens the ripple
> goes
> way up. A quick check with a scope should tell you what’s happened. 50 Hz
> triangle
> wave = blown diode. 100 Hz triangle wave = blown cap.
>
> Bob
>
> > On Oct 1, 2015, at 4:04 AM, Esa Heikkinen <tn1...@nic.fi> wrote:
> >
> > Anders Wallin kirjoitti:
> >
> >> I seem to get very strong spurs at 50Hz and harmonics with an old
> >> second-hand SRS FS710:
> >> http://www.anderswallin.net/2015/09/srs-fs710-noise-measurement/
> >> feature or bug? Anyone looked at the powersupply and figured out what
> parts
> >> to change?
> >
> > If you live in a country with 50 Hz mains network then this sounds like
> a dead capacitor in the power supply. Usually this means that it has old
> fashioned linear power supply (with classic iron transformer). In that
> case, replace the secondary capacitors after the rectifier bridge(s). Check
> voltages with oscilloscope if you wanna see which ones, but it might be
> good idea to replace them all (there should't be many of them).
> >
> > Should be very easy to fix.
> >
> > --
> > 73s!
> > Esa
> > OH4KJU
> > ___
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[time-nuts] SRS FS710 spurs at 50Hz and harmonics?

[Anders Wallin]

I seem to get very strong spurs at 50Hz and harmonics with an old
second-hand SRS FS710:
http://www.anderswallin.net/2015/09/srs-fs710-noise-measurement/

feature or bug? Anyone looked at the powersupply and figured out what parts
to change?

Anders
(going crazy measuring all things in sight with a loaner Microsemi 3120A :)
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Re: [time-nuts] Symmetricom experts?

[Anders Wallin]

FWIW our SyncServer S250 has a PSU with an electrolytic cap that has failed
at least twice over the years:
http://www.anderswallin.net/2015/08/psu-electrolytic-cap-fix/

Anders

On Thu, Sep 24, 2015 at 10:21 AM, G1FEF  wrote:

> Do we have any Symmetricom experts on this list?
>
> I've had a Symmetricom Syncserver S200 GPS+PPS with rubidium clock running
> for several years until we had a power cut and the UPS battery failed, on
> powering back up it won't boot at all.
>
> I suspect the flash is corrupt but they protect it in some way, so one
> can't just copy the o/s onto a new card, and the company want 's to fix
> it for me!
>
> Thanks in advance,
> Chris
>
>
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Re: [time-nuts] measuring os latency for pps

[Anders Wallin]

Back in 2012 while playing with LinuxCNC, a program for real-time control
of CNC machines, I made a few graphs on the real-time vs. normal kernel
performance:
http://www.anderswallin.net/?s=latency
These are purely software generated and measured events (i.e. we set a
thread to run at 1 ms intervals and in software measure when it actually
runs).

It would be interesting to hear what (if any?) real-time kernels are used
on NTP servers and if that is one way to measure/generate 1PPS input/output.

Anders


On Wed, Aug 26, 2015 at 3:04 AM, Chris Albertson albertson.ch...@gmail.com
wrote:

 What are you measuring?  Seriously.  What is it you need to know, is it?

 1) The time between the raising edge of the PPS and when the OS samples
 the time

 2) The time it takes between the PPS edge and when a user land process
 is notified.

 There are other things you can measure but if you want to see #1 above
 you can't use a TIC.  And you can't have the user space process set s
 GPIO bit.   The reason is that the PPS interrupt handler dramatically
 shortens the time removing ALL of the kernel process or latency.
 Look at the interrupt code.  The clock is sampled there.  The edge
 triggers the interrupt then while inside the handler the internal
 clock is sampled and stored and a flag is set to indicate the PPS was
 received.  Som tie MUCH later the flag is checked and the user-land
 process is told the PPS has detected   The delay does not matter
 because the clock was sampled with very low latency even if the user
 process was not notified right away.

 I think the details are platform dependent, hardware on a PC is not
 the same as a Raspberry Pi.  So you need to look at the source.

 On Tue, Aug 25, 2015 at 10:53 AM, Andrew Symington
 andrew.c.syming...@gmail.com wrote:
  Hi Folkert
 
  If you have a board with a hardware timer that supports
 load/match/compare
  then you can schedule an external interrupt to be generated at a
  predetermined point in the hardware count. Thus, if you know the
 transform
  between your disciplined clock and the hardware counter of the timer that
  drives it, then you should be able to do this. I have spent some time
  working with the (pretty neat) timers on board a beaglebone black, and
 I've
  written some code to setup input capture and compare on up to 4 timers:
 
 https://bitbucket.org/rose-line/roseline/src/35d551bf29e4bfec80f8ba667b199c8aa333b87f/core/modules/roseline.c?at=master
 
  Cheers
  Andrew
 
 
  On Tue, Aug 25, 2015 at 8:24 AM, folkert folk...@vanheusden.com wrote:
 
  Hi,
 
  Not sure if it is interesting for you guys but I wrote a simple program
  for e.g. Linux (or any other system with the pps api implemented) that
  listens on a pps source waiting for a pulse and then toggles a gpio
  pin. That way you can measure the latency introduced by the the kernel
  when listening from userspace. Note that there's a little extra latency
  due to the gpio-pin handling.
 
  It is on github: https://github.com/flok99/pps2gpio
 
 
  Folkert van Heusden
 
  --
  MultiTail cok yonlu kullanimli bir program, loglari okumak, verilen
  kommandolari yerine getirebilen. Filter, renk verme, merge, 'diff-
  view', vs.  http://www.vanheusden.com/multitail/
  --
  Phone: +31-6-41278122, PGP-key: 1F28D8AE, www.vanheusden.com
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 --

 Chris Albertson
 Redondo Beach, California
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[time-nuts] monitoring NTP servers?

[Anders Wallin]

Hi all,
Is there a ready made set of scripts for monitoring a bunch of NTP servers?
Preferably for generic unix/linux like ubuntu.

I imagine it would look something like:
1. measure data with a test machine, either use output of ntpq -p or
perhaps python and ntplib. Variable measurement interval, perhaps 60s or so.
2. store relevant data into RRDTool database (offsets, delay, jitter, etc)
3. produce graphs with RRDGraph, and possibly Alarms (e-mail?) if a server
goes offline or way out of sync.

thanks,
Anders
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Re: [time-nuts] 53230A noise floor

[Anders Wallin]

I finally had time to  compare the 53230A CONT (resolution-enhanced, aka
lambda-counting) and RCON (undocumented! reciprocal continuous counting,
aka pi-counting) modes, and wrote down some notes:
http://www.anderswallin.net/2015/06/cont-vs-rcon-mode-on-the-53230a-frequency-counter/
comments on my notes, here or in the blog, are welcome.

enjoy!
Anders

On Tue, Apr 7, 2015 at 9:42 PM, Mod Mix mod...@t-online.de wrote:

 Ole Petter Ronningen:

 Tangetially relevant; I made a patch for TimeLab to use the gap-free
 frequency measurement-mode for the 53230A, if anyone is interested.

 Thanks for this great support!
 Ulli

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Re: [time-nuts] Nature: Hyper-precise atomic clocks face off to redefine time

[Anders Wallin]

Here are some details on the gravity measurements:
http://projects.npl.co.uk/itoc/project-structure/reg/gravity-observations/

AFAIK this campaign is done with GPS-PPP and TWSTFT for frequency
comparison. The troposphere makes it hard to reach 1e-17 level for the
satellite links - even with a week of averaging time.
The next step is coherent frequency transfer over optical fibers, where
they claim down to maybe 1e-18 or 1e-19 ADEVs for the link itself for a day
of averaging.

Anders


On Sat, Jun 6, 2015 at 3:19 AM, Richard (Rick) Karlquist 
rich...@karlquist.com wrote:

 Can someone explain to me how this is going to work in
 light of the fact that each clock is in a different
 gravitational field?  Or is accuracy not the measurement,
 but rather stability?  No, that can't be because any
 lab that wants to measure stability merely needs to build
 two or three copies of their favorite clock and insure
 against synchronization.  They in principle shouldn't
 need to compare against a dissimilar type of clock.
 Therefore, we are back to the gravity issue.

 When we worked on the 5071A, we barely had enough sensitivity
 to notice a few parts in 10^13 between Santa Clara and
 Boulder (~5000 feet).

 Rick Karlquist N6RK

 On 6/3/2015 12:18 AM, Hal Murray wrote:

 Nice picture: A strontium-ion optical clock housed at the National
 Physical
 Laboratory in Teddington, UK.

 Over the past decade, various laboratories have created prototype optical
 atomic clocks, which use different elements such as strontium and
 ytterbium
 that emit and absorb higher-frequency photons in the visible spectrum.
 This
 finer slicing of time should, in principle, make them more accurate: it is
 claimed that the best of these clocks gain or lose no more than one second
 every 15 billion years (1E18 seconds) -- longer than the current age of
 the
 Universe -- making them 100 times more precise than their caesium
 counterparts. Optical clocks are claimed to be the best timekeepers in
 existence, but the only way to verify this in practice is to compare
 different models against each other and see whether they agree.

 Starting on 4 June, four European laboratories will kick off this testing
 process -- the National Physical Laboratory (NPL) in Teddington, UK; the
 department of Time-Space Reference Systems at the Paris Observatory; the
 German National Metrology Institute (PTB) in Braunschweig, Germany; and
 Italy's National Institute of Metrology Research in Turin. Between them,
 the
 labs host a variety of optical clocks that harness different elements in
 different experimental set-ups.


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[time-nuts] 53230A noise floor

[Anders Wallin]

Hi all,

I ran some tests on a new 53230A counter that just arrived:
http://www.anderswallin.net/2015/04/keysight-53230a-noise-floor-test/

The time-interval single-shot noise and resulting ADEV seems easy enough to
explain.

I didn't yet have time to look closely at Enrico Rubiola's notes over here:
http://rubiola.org/pdf-slides/2012T-IFCS-Counters.pdf
There is probably a good explanation for the ADEV-level in standard
(pi-counting?) reciprocal frequency counter mode as well as the roughly
1/sqrt(10) enhancement in ADEV when increasing the gate-time 10-fold.

on another note:
The discussion on phase-noise - ADEV calculations earlier was
interesting. Datasets (synthetic or real) with known correct ADEVs and
phase-noise-spectra would be a good addition to allantools and a motivation
to add code for the phase-noise - ADEV conversion.

cheers,
Anders
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Re: [time-nuts] 53230A noise floor

[Anders Wallin]

 See the part the end that shows why averaging breaks ADEV:
 http://leapsecond.com/pages/adev-avg/


Hi Tom, thanks for reminding me of that page. I did no averaging of the
data myself, and I think it's logical that the counter noise floor goes
down with increasing gate time - I just haven't had time to read and think
about the counter specs enough to write down some reasonable formula that
predicts the noise floor for different gate times.
PHK's comment about trying something different than exactly 10MHz is worth
testing.

Reading your page above I am confused by the graph where you add noise.
If I create a synthetic phase dataset with 1 ns of RMS noise (i.e. you
histogram the data and it looks like a gaussian with standard deviation
1ns) and then calculate ADEV I get ADEV(1s) = sqrt(3)*1e-9  (tried with
both stable32 and allantools)
Your page says add 1ns noise and shows ADEV(1s)=1e-9. Can you clarify
what add 1ns noise means - or am I doing something wrong?

Anders
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Re: [time-nuts] Need advice for multilateration setup

[Anders Wallin]

What's your budget?
Put a white-rabbit switch (3.5keur) in the middle, and install a mile of
single-mode fiber to each rx-station. Then use TDC or FDEL SPEC-cards
(1.5keur each) at the RX-stations to time-stamp the incoming pulse. 1 ns
systematic and 50 ps RMS random error should be doable. The systematic
constant error in time-stamp for each rx-station can maybe be calibrated
out in the TDOA-algorithm? The FDEL-card can time-stamp up to 100 kEdges/s
(that results in a ca  4 Mb/s datastream).

Anders


On Thu, Mar 26, 2015 at 4:27 AM, Robert Watzlavick roc...@watzlavick.com
wrote:

 I'm working on a project that I could use some advice on and also might be
 of interest to the list.   If it's not appropriate for the list, my
 apologies.

 I want to develop a tracking system for an amateur rocket that can allow
 me to track the rocket even if onboard GPS is lost (as is typical during
 ascent and sometimes during descent) or if telemetry is lost.  The idea is
 to use a transmitter in the rocket and have 4 or more ground stations about
 a mile apart each receive the signal. Multilateration based on TDOA (time
 difference of arrival) measurements would then be used to determine x, y,
 z, and t.  With at least 4 ground stations, you don't need to know the time
 the pulse was transmitted.  The main problem I'm running into is that most
 of the algorithms I've come across are very sensitive to the expected
 uncertainty in the time measurements.  I had thought 100 ns of timing
 accuracy in the received signals would be good enough but I think I need to
 get down less than 40 ns to keep the algorithms from blowing up.  My
 desired position accuracy is around 100 ft up to a range of 100k ft.

 There were two different methods I thought of.  The first method would
 transmit a pulse from the rocket and then use a counter or TDC on the
 ground to measure the time difference between a GPS PPS and the pulse
 arrival.  This is the most straightforward method but I'm worried about the
 timing accuracy of the pulse measurement.  I should be able to find a
 timing GPS that has a PPS output with about +/- 30-40 ns of jitter (2
 sigma) so that portion is in the ballpark.  There also seem to be TDCs that
 have accuracy and resolution in the tens of picosecond range but they also
 have a maximum interval in the millisecond range.   I'm not sure I can
 ensure the pulse sent from the rocket will be within a few miilliseconds of
 the 1 PPS value on the ground.  I will have onboard GPS before launch so in
 theory I could initialize a counter to align the transmit pulse within a
 millisecond or so to the onboard PPS. But, once GPS is lost on ascent,
 unless I put an OCXO onboard that pulse may drift too far away (due to
 temperature, acceleration, etc.) for the TDC on the ground to pick it up.
 Plus an OCXO will add weight and require extra power for the heater.
 Another idea would be to send pulses at a very fast rate, say 1 kHz to stay
 within the TDC window.  But then I need to worry about what happens if the
 pulses get too close to the edge of the TDC window.  One other variable is
 the delay through the RF chain on the receive end but I figure I could
 calibrate that out.

 The other idea, and I'm not sure exactly how to implement it, would be to
 transmit a continuous tone (1 kHz for example) and perform some kind of
 phase measurement at each ground station against a reference.  I could use
 a GPSDO to divide down the 10 MHz to 1 kHz to compare with the received
 signal but how can I assure the divided down 1 kHz clocks are synchronized
 between ground stations?  Are the 10 MHz outputs from GPSDOs necessarily
 aligned to each other?  I let two Thunderbolts sit for a couple of hours
 and the 10 MHz outputs seemed to stabilize with an offset of about 1/4 of a
 cycle, too much for this application.  Another related idea would be to use
 the 10 MHz output to clock an ADC and then sample several thousand points
 using curve fitting, interpolation, and averaging to get a more accurate
 zero crossing than you could get based on the sample rate alone.  Adding a
 TDC would allow the use of RIS (random interleaved sampling) for repetitive
 signals which could generate an effective sample rate of 1 GS/s.

 Does anybody have advice or practical experience on which method would
 work better?

 Thanks,
 -Bob
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Re: [time-nuts] Time tagging fpga

[Anders Wallin]

 Anders,
 The counter runs on a Pipistrello.  I looked at the information on the web
 about time taggers before starting.  I decided to try an oversampling
 scheme described by a group of  Italian? physicists for a multichannel time
 tagging instrument.  They used 4x oversampling.  My version is crude; it
 uses the 50 MHz on-board clock but of course could use an external clock
 source.  The clock is multiplied to 1 GHz and then divided into four 125 Hz
 clocks phased 45 degrees apart.  There is a fifth 125 MHz clock at 0 phase
 for the main counter and external interface.
 There are four channels, each with 3 bits for value and a forth bit
 indicating an event.  The sixteen bits are followed by a 48 bit counter
 value.


what, if any, signal conditioning do you have between the DMTD output and
the FPGA? I was thinking about copying the CERN DIO design which looks like
this:
http://ibin.co/1iEwLuAUQYJ4
it has a fuse, a resistor to set the input impedance, protection diodes,
and an ADCMP604 that outputs an LVDS pair to the FPGA.

The CERN design is for a 125 MHz clock. What would be the preferred way to
generate this for the Pipistrello, with an optional 10MHz reference input?
OCXO at 10MHz and a ADF4351 PLL+VCO up to 125MHz? Does someone have a
tested circuit that autodetects the external 10MHz and can switch between
the OCXO and ext-ref?



 This yields 1 ns resolution (bin size) but the bins sizes are certainly
 not all equal.  I have few means to check the accuracy but for my purposes
 (logging 100 Hz to 1 Hz zero crossings of a DMTD) it is certainly more
 accurate than I need.  I have experimented with .5 ns bin sizes, also using
 the 8x oversampling with a 250 MHz clock.  To keep the backend 125 MHz
 structure I used a two phase multiplexer to combine two successive samples.
 This runs but is not reliable and needs further work before it's useful.


Did you post the schematic for your DMTD?
Many of the time-to-digital papers calibrate the bin-width by collecting
time-stamps from an asynchronous pulse-source. If the bins are equal you
should get a flat histogram. Some use a ring-oscillator on the fpga for
generating the asynchronous hits.


Anders
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Re: [time-nuts] Time tagging fpga

[Anders Wallin]

On Sat, Nov 22, 2014 at 5:37 AM, Robert Darby bobda...@triad.rr.com wrote:

 I finally got the time tagging fpga I was playing with to a semi-usable
 state.  I mentioned in an earlier post that I was unable to compile or link
 the FTDI library but Magnus Karlsson very kindly rewrote a program of his
 to provide me with a utility to set up the USB asynchronous parallel
 interface characteristics on the PC.  Only bad thing is you're running
 blind so it pays to do a short run to make sure all's well before
 committing to a long capture.


Interesting! How do you generate a clock (what frequency) for the FPGA?
Are you using a coarse-counter + interpolator (delay-line?) approach?

I'm planning to explore this with a Pipistrello (sparta6 LX45) board, which
has the same fpga used in this work:
http://arxiv.org/abs/1303.6840
the VHDL is available on ohwr:
http://www.ohwr.org/projects/tdc-core/wiki


Anders
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[time-nuts] 53230A input channel fault?

[Anders Wallin]

Hi all,

I have a 53230A that behaves differently on ch1 and ch2.

With ch2 at DC/1Mohm/postive-slope/1V it triggers ok on my PPS signal and
shows e.g. a pusle-width measurement etc.
The same signal connected to ch1 fails to trigger.

I noticed the Vpp and Vmax/Vmin voltage readings are not correct for PPS
signals - i.e. on a scope my signals are from 0V to 4V, but the counter
shows -5 mV to +5 mV or similar. But perhaps that is because of the low
duty-cycle of a PPS signal.

We were measuring RF frequencies with the counter a few weeks back - it
says max 1W input... it is possible that this was exceeded (does 50Ohm vs.
1MOhm setting matter for input-protection?).
Any ideas on what breaks first on the input stage? :) (are there schematics
online?)


thanks,
Anders
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Re: [time-nuts] 53230A input channel fault?

[Anders Wallin]

A colleague of mine had seen this exact same behavior on another 53230A.
The problem is a narrow trace right after the CH1 BNC input.
http://www.anderswallin.net/2014/11/53230a-counter-input-channel-fix/

There might be some chemical corrosion going on, since the other counter
that experienced this problem had definitely not been subjected to
overvoltage or other abuse. Or perhaps it's a mechanical issue where the
BNC-connector over time bends the PCB+trace. The BNCs don't appear
mechanically anchored to the front-panel, they are just soldered to the PCB
and stick out through holes in the front panel.

We have one of the 100ps models and probably a third 20ps model also - time
will tell if these will break in the same way...

Agilent/Keysight - are you listening?!? fix it please :)

Anders


 Hi all,
 
  I have a 53230A that behaves differently on ch1 and ch2.
 
  With ch2 at DC/1Mohm/postive-slope/1V it triggers ok on my PPS signal and
  shows e.g. a pusle-width measurement etc.
  The same signal connected to ch1 fails to trigger.

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Re: [time-nuts] Measuring ADEV for a beginner

[Anders Wallin]

what you want to measure is a time-series of either frequency data or phase
data.
the simplest possible case for a beginner would be to have two clocks with
1-PPS (one pulse per second) outputs, and connect one clock to the
start-input and the other to the stop-input of a time-interval counter. If
you measure phase, keep the time-interval number to a 5...6 digit number
and you don't have to worry too much about the internal time-base of the
counter.


On Sat, Nov 1, 2014 at 3:29 PM, Anthony Roby ar...@antamy.com wrote:

 I've been reading a lot about ADEV and following the threads on the list,
 particularly Karen's in-flight thread. What I haven't come across is a
 simple explanation of the basic setup required to go about collecting the
 data.  John Miles referenced this page http://www.ke5fx.com/tpll.htm, and
 the simple setup at the bottom of the page looks like a reasonable place to
 start.  Seems that I'd need to acquire a phase detector and build or buy
 some filters and the amp.  I can probably figure that out, but how do I get
 the data into a PC?  Is there a basic hardware and software setup that
 someone could point me to or recommend?

 Thanks

 Anthony
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Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop

[Anders Wallin]

two D-flops in series make a synchronizer!? (see the input-channels on
Nutt-type time interval counters)
http://chipdesignmag.com/print.php?articleId=32?issueId=5
you've lost all your noise - but you've also got rid of all the signal - so
not great for improving SNR.

On Tue, Oct 14, 2014 at 6:32 PM, Simon Marsh subscripti...@burble.com
wrote:

 I now have the 2 D-flops in a 74AC74 wired in series so that one does the
 sampling and the other acts as a shift register before the output is sent
 on to the BBB.
 I got so far with this before realising that one of the D-flops was being
 much more noisy than the other and indeed it was only a single output that
 was particularly noisy. Switching to the inverted output reduced the noise
 considerably.
 After a bit of head scratching I swapped the part with the result that
 _all_ the glitches vanished. Completely. Even at small beat frequencies
 (5hz).

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Re: [time-nuts] Digital Mixing with a BeagleBone Black and D Flip Flop

[Anders Wallin]

Interesting 2008 discussion on using a sound-card ADC for a DMTD system!
Did anyone build a DMTD-system and measure the performance using a 24-bit
soundcard?
Does it matter that the ADC in the sound-card is probably clocked by a
crystal clock that is 50ppm off and has bad ADEV?

Anders

On Sun, Oct 12, 2014 at 7:27 AM, Bruce Griffiths bruce.griffi...@xtra.co.nz
 wrote:

 Original thread on DDMTD in 2008:
 https://www.febo.com/pipermail/time-nuts/2008-December/034955.html

 Later comment on using a shift register to
 minimise metastability issues:
 https://www.febo.com/pipermail/time-nuts/2011-August/058648.html

 Bruce



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Re: [time-nuts] fast switching quiet synthesizer

[Anders Wallin]

On Tue, Oct 7, 2014 at 8:32 PM, Magnus Danielson mag...@rubidium.dyndns.org
 wrote:



 Some of the modern DDSes can take 10 MHz directly and step it up
 internally before hitting the DDS core, but it may be that you need to
 synthesize a higher clock from the 10 MHz first.


We've been using/testing an AD9912 eval-kit board. It can take 10MHz input
and has an internal 66x PLL and VCO for a 660MHz DDS sample-clock (just out
of spec actually, vco is min 700MHz if I read the datasheet correctly).
Output looks like so:
http://www.anderswallin.net/wp-content/uploads/2013/12/Fout100M_Span400M.bmp
DDS output is 0 to 2-400MHz with a resolution of ~few uHz since it has a
48-bit tuning word. We're programming it with an arduino+eth-shield using
modbus-ethernet. Changing frequency over ethernet takes about 60ms, but it
could be much much faster directly over SPI if you know the desired
frequencies beforehand and store them on the arduino.
zoom-in shows spurs at 50kHz
http://www.anderswallin.net/wp-content/uploads/2013/12/Fout100M_Span500k.bmp

The spurs improve when using the DDS with an external 1GHz sample-clock
(internal PLL+VCO on the DDS-chip disabled). We produced it from 10MHz with
an ADF4350 eval-board:
http://www.anderswallin.net/wp-content/uploads/2014/03/100MHz_AD9912_internal_vs_external_PLL.jpg
AD must use some niceexpensive spectrum-analyzer to produce that figure
with a -100 dBm noise floor! :)

even with the eval-boards there's a fair bit of building: multiple
powersupplies, cables, enclosure, etc.

Anders
PS. I could be tempted to join in if someone wants to make a PCB for these
chips - would save significantly compared to eval-boards..
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Re: [time-nuts] New TIC test run

[Anders Wallin]

Do you have the schematic for this online somewhere?
what is the range of the interpolator?
which TIC is the red/blue points? the blue data looks like it is aliased
somehow, perhaps a number that is truncated/rounded badly?


On Sat, Mar 8, 2014 at 9:46 PM, Bob Stewart b...@evoria.net wrote:

 I put my TIC to hardware, and have started testing it.  Here is a sample
 run comparing it against the 5334B with an off frequency OCXO.  I've scaled
 and rotated to tried to cancel out the length of the cables to the 5334B.
 Still early days with it, yet.


 http://www.evoria.net/AE6RV/TIC/TICvs5334B.png

 Bob - AE6RV
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Re: [time-nuts] ADEV from phase or frequency measurement

[Anders Wallin]

Here is python code for the most common deviations
https://github.com/aewallin/allantools/blob/master/allantools/allantools.py

each statistic (ADEV, MDEV, TDEV, and so on) has two functions. one takes
fractional frequency data, the other phase data. frequency2phase() and
phase2freqeuncy() show how the conversions are done.

Your patches are welcome!

Anders




On Sat, Mar 1, 2014 at 1:37 PM, Tom Van Baak t...@leapsecond.com wrote:

 Hi Volker,

 Either phase or frequency raw data can be used to generate an ADEV plot,
 but you have to use different methods depending on the data type.

 See the two formulas for Allan Variance in:
 http://www.wriley.com/paper2ht.htm

 Usually we use the x form of the formula, where x is an array of phase
 samples. But if you have frequency samples then use the y form instead,
 where y is an array of frequency samples.

 Note you can also convert phase data to frequency data (by
 differentiating) and use the y form. Or convert frequency data to phase
 data (by integrating) and use the x form.

 /tvb

 - Original Message -
 From: Volker Esper ail...@t-online.de
 To: Discussion of precise time and frequency measurement 
 time-nuts@febo.com
 Sent: Saturday, March 01, 2014 3:15 AM
 Subject: [time-nuts] ADEV from phase or frequency measurement


  Hello dear fellow time-nuts,
 
  I stumbled over a question that may sound stupid to you:
 
  Is the usual ADEV plot the result of a phase or a frequency measurement?
 
  I get totally different results when comparing a phase and a frequency
  measurement of the same source. Or am I doing something totally wrong?
 
  Thanks a lot
 
  Volker


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Re: [time-nuts] Sample R script for ADEV under Linux wanted

[Anders Wallin]

I recently copy/pasted/googled together this Python library:
https://github.com/aewallin/allantools
patches, sample datasets, and new tests are welcome!

Anders



On Mon, Feb 3, 2014 at 2:02 AM, Bob Stewart b...@evoria.net wrote:

 Subject says it all.  Does anyone have a script I could use as a starting
 point to calculate/plot the ADEV for my GPSDO?

 Bob - AE6RV
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Re: [time-nuts] high (spacial) precision GPS in Kickstarter

[Anders Wallin]

AFAIK 'normal' RTK does not provide a clock solution. There's something
called 4D RTK which does:
http://saegnss1.curtin.edu.au/Publications/2010/Feng2010Four.pdf
apparently the results can be very good - but I think the errors quoted are
for time-transfer between two RTK receivers (?).

If there are papers comparing time-transfer with dual-frequency PPP to this
4D RTK I'd be interested..

AW



On Sat, Jan 25, 2014 at 4:10 AM, John C. Westmoreland, P.E. 
j...@westmorelandengineering.com wrote:

 Hello Daniel,

 Appears that is precision for position - not necessarily time.  I think
 NIST had a write-up on something very similar.

 Regards,
 John Westmoreland


 On Fri, Jan 24, 2014 at 5:40 PM, Daniel Mendes dmend...@gmail.com wrote:

 
  http://www.kickstarter.com/projects/swiftnav/piksi-the-rtk-gps-receiver
 
  Has anyone seen this? Any time-nuts utility?
 
  Daniel
 
 
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Re: [time-nuts] PICPET- was Affordable (cheap) COTS (etc)

[Anders Wallin]

Given that Arduinos are now sold in (almost) every super-market, and the
programming IDE is free/open-source, and the C/C++ code is familiar to
many, I would have thought the logical evolution of the pictic is to
become an Arduino shield?

One drawback (AFAIK) is that e.g. Arduino Due doesn't have a dedicated
counter/encoder input, like the dsPICs made for motor-control have.
On the other hand the Due has 12-bit analog inputs (and DACs) that might
work for interpolation.

How fast can the QEI (quadrature encoder interface) on a dsPIC clocked at
140MHz count? Were you planning on using a dsPIC with two QEIs, for TIC
startstop coarse counting?
For 1ns or 2ns resolution an analog (or fpga?) interpolator is required
anyway?

AW


On Thu, Jan 23, 2014 at 4:10 AM, Tom Van Baak (lab) t...@leapsecond.comwrote:

 Hi Bob,

 It's pretty easy to get a tiny PIC or AVR down to 50 ns, so to me the next
 sweet spot would be 1 or 2 ns. A couple of us are trying. Contact me
 off-list re the dsPIC33.

 /tvb (i5s)

  On Jan 22, 2014, at 5:53 PM, Bob Stewart b...@evoria.net wrote:
 
  Tom,
 
  Do you know of any other PIC projects that get a greater resolution?  I
 was thinking of doing something with a dsPIC33 running at 140MHz or
 greater, but I'm not sure I want to devote the time to if it's it's been
 done.
 
  Bob
 
 
 
 
  
  From: Tom Van Baak (lab) t...@leapsecond.com
  To: Robert Atkinson robert8...@yahoo.co.uk; Discussion of precise
 time and frequency measurement time-nuts@febo.com
  Sent: Wednesday, January 22, 2014 7:39 PM
  Subject: Re: [time-nuts] Affordable (cheap) COTS / eBay kit for TIE /
 1PPS phase comparison
 
 
  As much as I'm fond of my picPET it has 400 ns resolution and not
 intended to replace a 5 or 10 or 50 ns TIC (which is what the OP asked for).
 
  /tvb (i5s)
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Re: [time-nuts] L1/L2 GPS Receiver

[Anders Wallin]

Looking at this graph:
http://www.thinksrs.com/assets/instr/PRS10/PRS10diag2LG.gif
If you have a good PRS10, it only needs adjusting on the many-hours
timescale?
How much better is a dual-frequency receiver going to be for this, compared
to a single frequency receiver?

The real benefit of dual-frequency is you can do post-processing with PPP.
Javad has some modules but they start at 3 kUSD - if anyone knows of hobby
level priced L1/L2 receivers that can produce rinex-files for PPP
processing that would be interesting!

AW




On Thu, Jan 16, 2014 at 6:03 AM, davidh dho...@gmail.com wrote:

 Folks,

 I've stumbled across a Novatel 720L, so would like a new receiver module
 which supports L1/L2.

 The main goal is to start learning about GPS/Galileo/Beidou. I may use the
 derived 1pps as input to my PRS10/10811D reference (or may continue using
 the 58503A). My budget is quite limited.

 Thanks,

 david

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Re: [time-nuts] sysclock source for AD9912 DDS?

[Anders Wallin]

Some more testing today. It turns out that AD's schematic for the
evaluation board doesn't match with reality - and so I had not connected
the PLL filter components at all previously! Now they are 'in the loop' and
I get reasonable results without the 2x reference clock setting. With 2x
activated there are still very strong spurs. I have updated my blog with
pictures from today:
http://www.anderswallin.net/2013/12/ad9912-dds-test/

Could the remaining -60 dBc spurs at +/- 50 kHz be due to my 10MHz clock
source, an Agilent 33120A?

Next I will try cooking up some Arduino code for controlling the DDS over
3-wire bit-banged SPI (hardware SPI port is already in use on my arduino).

Anders


On Mon, Dec 30, 2013 at 5:56 PM, Anders Wallin
anders.e.e.wal...@gmail.comwrote:

 I've tested the AD9912 evaluation board:

 http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png

 I want to use it with a 10MHz external input clock, but it looks like the
 on-board PLL that generates a 1200MHz sample clock from my input isn't that
 great, since I get strong side-bands on the output that are only 18-20 dB
 down from the fundamental.

 So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
 get a clean output. Any ideas/suggestions for generating this from a 10 MHz
 sine?
 Driving the DDS system clock from an expensive RF generator (e.g. HP
 8648A) would be possible but I'd prefer a PLL from 10MHz if it's doable
 simply/cheaply.

 Anders

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[time-nuts] sysclock source for AD9912 DDS?

[Anders Wallin]

I've tested the AD9912 evaluation board:
http://www.anderswallin.net/wp-content/uploads/2013/12/dds_test_2013-12-30.png

I want to use it with a 10MHz external input clock, but it looks like the
on-board PLL that generates a 1200MHz sample clock from my input isn't that
great, since I get strong side-bands on the output that are only 18-20 dB
down from the fundamental.

So it looks like I need to supply a clean 800-1000MHz clock to the DDS to
get a clean output. Any ideas/suggestions for generating this from a 10 MHz
sine?
Driving the DDS system clock from an expensive RF generator (e.g. HP 8648A)
would be possible but I'd prefer a PLL from 10MHz if it's doable
simply/cheaply.

Anders
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Re: [time-nuts] sysclock source for AD9912 DDS?

[Anders Wallin]

Thanks for all replies so far!

It looks like I will play around with the evaluation board some more, and
see if I can get the on-chip PLL to behave better.
The settings with 2x edge-detector and 60x PLL were the only ones I could
find where the output frequency setting in the software corresponded to the
actual output frequency - hence I tested only with 10MHz x120 = 1200 MHz
sysclock. I have asked about this on the AD forum, but no replies yet.

If that doesn't work the suggested ADF4351 (or similar) evaluation board
looks like the most straightforward option.

thanks,
Anders
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Re: [time-nuts] PPP with RTKLib?

[Anders Wallin]

I made some progress with this, but there still remains a ~4ns offset
between the clock solutions of RTKLib and CSRS.
On the other hand CSRS and gLAB agree quite well. See:
http://www.anderswallin.net/2013/12/comparing-gps-ppp-solutions/

I've tried adjusting a lot of the RTKLib options, but the 4ns offset
remains. strange.

Anders



On Fri, Dec 20, 2013 at 2:04 PM, Anders Wallin
anders.e.e.wal...@gmail.comwrote:

 Hi all,

 I want to use PPP for post-processing of RINEX 2.10 files from a Dicom
 GTR50/51 GPS receiver. The GTR50 references the time-stamps in the RINEX
 file to an external PPS input, so this is a way of remotely monitoring a
 clock.

 Does anyone know how to run PPP-Static calculations with RTKLib?
 I have an example RINEX file which I ran through two online web-based PPP
 services:
 CSRS-PPP over here:
 http://webapp.geod.nrcan.gc.ca/geod/tools-outils/ppp.php
 and JPL-APPS over here:
 http://apps.gdgps.net/apps_file_upload.php

 Then I try to do the same calculation with RTKLib with a number of input
 files and I get:
 http://imagebin.org/283130
 The two online services differ by about 3 ns, but the overall shape of the
 solutions is very similar.
 My RTKLib solution is very noisy and I doubt if the PPP-calculation is
 working at all.

 Here's what I am feeding into RTKPOST:
 my own RINEX 2.10 Observation data file. This 24h of data from 17th of
 October.
 and then a lot of files fetched from IGS with RTKGET
 igsXXX.clk (clock data)
 igsXXX.sp3 (orbit data)
 brdcYYY.13n (ephemerides or nav data?)


 thanks for any input,
 Anders

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[time-nuts] PPP with RTKLib?

[Anders Wallin]

Hi all,

I want to use PPP for post-processing of RINEX 2.10 files from a Dicom
GTR50/51 GPS receiver. The GTR50 references the time-stamps in the RINEX
file to an external PPS input, so this is a way of remotely monitoring a
clock.

Does anyone know how to run PPP-Static calculations with RTKLib?
I have an example RINEX file which I ran through two online web-based PPP
services:
CSRS-PPP over here:
http://webapp.geod.nrcan.gc.ca/geod/tools-outils/ppp.php
and JPL-APPS over here:
http://apps.gdgps.net/apps_file_upload.php

Then I try to do the same calculation with RTKLib with a number of input
files and I get:
http://imagebin.org/283130
The two online services differ by about 3 ns, but the overall shape of the
solutions is very similar.
My RTKLib solution is very noisy and I doubt if the PPP-calculation is
working at all.

Here's what I am feeding into RTKPOST:
my own RINEX 2.10 Observation data file. This 24h of data from 17th of
October.
and then a lot of files fetched from IGS with RTKGET
igsXXX.clk (clock data)
igsXXX.sp3 (orbit data)
brdcYYY.13n (ephemerides or nav data?)


thanks for any input,
Anders
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Re: [time-nuts] refclock - NTP server settings/tuning?

[Anders Wallin]

On Mon, Sep 30, 2013 at 1:17 AM, Hal Murray hmur...@megapathdsl.net wrote:


 anders.e.e.wal...@gmail.com said:
  The refclock driver is a userspace C-program (daemon) that essentially
 does:
  while(1) {
  gettimeofday(tv,NULL) // system time, for NTP  receiveTimeStamp
  get_wr_time(wr_tv); // WR time, for NTP clockTimeStamp
  // write tv and wr_tv to shared memory where NTP expects to see them
  sleep(8);
   }

 Where did you get the 8 from?
 Each ntpd refclock has a 64 slot FIFO.  Every polling interval, ntpd
 processes the data in the buffer and turns it into a sample feed to the
 main
 algorithm.  That processing discards 1/3 of the samples as (potential)
 outliers and averages the rest.
 You had min/max poll set to 4 (16 seconds) so you are only giving ntpd 2
 samples to work with.
 So the first thing I would do is change the 8 to 1.  Then I'd fiddle with
 min/max poll to see what worked best.


Thanks! I did not know this and thought with maxpoll 4 NTP will only read
the timestamps from memory every 16s, so updating them more often is not
useful. Apparently updating the timestamps with the SHM driver every second
(or even every 0.5 s?) is indeed useful. This is easy to change in my code.


 The next source of noise that I see is that time it takes to execute the
 time-reads may vary due to cache faults and may get interrupted.  Plan one
 would be:
 gettimeofday(tv0,NULL)
 get_wr_time(wr_tv);
 gettimeofday(tv1,NULL)
 if (tv1-tv0  xxx) try again
 You can get xxx from a calibration run.

 Plan two would be
 gettimeofday(tv,NULL)
 get_wr_time(wr_tv);
 gettimeofday(tv,NULL)
 get_wr_time(wr_tv);
 The first two will warm up the cache.  You will still get occasional
 interrupts, but ntp should filter them out.


again thanks for these tips. I guess NTP will not panic if I use the first
strategy and discard a few timestamp readings. There would then be a gap of
1 s or 2 s in the timestamp history. No new data is better than new noisy
data?



 
 Go back to the big picture.  What are you trying to do?  What sort of
 accuracy do you need?
 Is this a one-off project or do you need to run code on many systems using
 different hardware?
 Can you modify the code that needs accurate time to call get_wr_time rather
 than gettimeofday?  (Or patch the library so gettimeofday uses WR rather
 than
 calling the system?)


We are experimenting with using WR for time-distribution. WR is designed
for max 10km fiber-links but we are experimenting with a 1000km link :)
WR requires dedicated (open-source!) hardware and software and switches, as
well as a dedicated fiber or light-path in a CWDM or DWDM fiber network.
Infrastructure for NTP on the otherhand is 'everywhere'. Since a lot of
users don't need the precision (100ps) or accuracy (1ns) of WR, the
refclock driver is just a simple way to bridge WR-NTP. It allows
GPS-independent NTP-servers to run wherever we have WR-network. I don't
have any particular accuracy spec for the NTP-server as a goal, I am just
experimenting - apprently getting within 50us of the refclock is already
quite good for NTP.

PTP over copper ethernet is another lower accuracy option for
re-distributing WR-time. But as mentioned it requires dedicated
network-cards and switches. We could bring WR-time into a switch that takes
10MHz and 1PPS inputs. Or Meinberg and the other PTP-hardware makers might
start to support WR directly.

Anders
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Re: [time-nuts] refclock - NTP server settings/tuning?

[Anders Wallin]

Thanks for all replies,

I can try changing maxpoll to a larger value and see if the trace is
smoother.

The refclock driver is a userspace C-program (daemon) that essentially does:
while(1) {
gettimeofday(tv,NULL) // system time, for NTP  receiveTimeStamp
get_wr_time(wr_tv); // WR time, for NTP clockTimeStamp
// write tv and wr_tv to shared memory where NTP expects to see them
sleep(8);
}

This may be the cause of a constant negative offset I see, since one
time-stamp is always read before the other. Perhaps this could be improved
by reading system time both before and after get_wr_time() and reporting
the average of the two readings as receiveTimeStamp? Or measure the offset
and put it as a time1 offset-value in ntp.conf
If the driver was written as a kernel module, would that run with higher
priority and less variable delay?

I use the same piece of code to log how well system time tracks WR-time.
Here I sometimes see sudden spikes of 100s of microseconds. Could this be
caused by the OS context switching in the middle of my program between the
two timestamp-reading functions? Again, would this improve if the
time-logger was written as a kernel module, or is there some other way of
coding it that avoids context switches and keeps the two time-stamp reading
functions atomic?

Standard Ubuntu nowadays has a pre-packaged lowlatency kernel which I
think is RT-Preempt with some modifications. But I assume both the
refclock-driver and the logger would need a re-write to take advantage of
the RT-kernel. Does anyone have experienced with that?

thanks,
Anders
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Re: [time-nuts] refclock - NTP server settings/tuning?

[Anders Wallin]

 [1] http://en.wikipedia.org/wiki/White_Rabbit


Sorry the correct link is
http://en.wikipedia.org/wiki/The_White_Rabbit_Project
:)
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[time-nuts] refclock - NTP server settings/tuning?

[Anders Wallin]

Hi all,

If I have an NTP server with a refclock that is assumed very accurate (~few
nanoseconds/day drift at most, with  1 ns jitter), how well should NTP be
able to keep the system clock on time?

I'm using a White Rabbit (WR) [1] SPEC PCI-card that receives accurate time
over WR, and I wrote a shared-memory refclock driver [2] for it. I added it
to ntp.conf with
server 127.127.28.0 minpoll 4 maxpoll 4

and I get the following graph. The error is system time compared to
WR-time, where we can assume that WR-time is very accurate.
http://www.anderswallin.net/wp-content/uploads/2013/09/ntp_graph.png

Are the minpoll and maxpoll parameters the only way to tune how NTP locks
onto a refclock? To me the trace (blue in the graph) looks quite noisy and
I would guess it could be improved by PID-tuning inside NTP?
As a comparison the red trace shows another computer using standard NTP
without a refclock and the trace is much smoother.
If it matters I measured the free running system clock on this computer to
have an error of about 40 ppm [3].


thanks,
Anders

[1] http://en.wikipedia.org/wiki/White_Rabbit
[2] https://github.com/aewallin/ptp2ntpd
[3]
http://www.anderswallin.net/wp-content/uploads/2013/07/freerunning_vs_ntp_2013jul26.png
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Re: [time-nuts] Generate 1 PPS signal on serial port

[Anders Wallin]

On Tue, Aug 6, 2013 at 4:07 PM, Mark C. Stephens ma...@non-stop.com.auwrote:

 However if you are hell bent on generating PPS in software somehow (please
 let me know you plan? - curious)


FWIW:
Over in the hobby-CNC world where it is common to use the parallel port for
driving machine tools (mills, lathes, 3d printers) pulses with good timing
are output by LinuxCNC which sits on top of a real-time kernel (RTAI,
Xenomai, or RT-Preempt). With a well-behaving bios/cpu/motherboard
combination it is possible to achieve around 10-20 us maximum jitter - in
good cases down to 5 us. The same program run on a non-realtime kernel will
easily show 3-5 milliseconds or more of jitter.
This is relative to a clock that the real-time kernel uses for internal
timing - I am not sure if that clock can be NTP-disciplined.

Anders
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[time-nuts] Typical NTP performance? Monitoring multiple NTP servers?

[Anders Wallin]

Hi all, I have two NTP-related questions:

1.
We are setting up a White-Rabbit[1] network for time-distribution. We
'seed' the WR-network with 10MHz and PPS signals form atomic clocks. This
means on each computer in the network there's a very accurate PTP-server
running on the WR-card, as well as the normal system time on the computer.
For fun I logged both the system-time (kept on time using NTP) as well as
the PTP time and plotted the error:
http://www.anderswallin.net/wp-content/uploads/2013/07/NTP_time_2013jul26.png
I was wondering if this plot is typical for a (good?) NTP-disciplined
computer clock?
Without NTP the free-running clock shows 40 ppm error:
http://www.anderswallin.net/wp-content/uploads/2013/07/freerunning_vs_ntp_2013jul26.png

The -16ms offset in this graph is probably due to my naive program where we
first call a simple function that asks the NTP time, and then over a serial
link ask for the PTP time. In reality the two time-stamps might be better
synchronized - I don't know. The slow variation I see should be real
however and completely due to drift in the NTP time, since the WR-time is
much more accurate.

2.
Is it possible to run several NTP-clients on one machine? That means I'd
have multiple system-times each synchronized to its own NTP server.
If this is possible I'd like to monitor several NTP-servers at once and log
their time-stamps against our WR-time which is known to be good.

thanks,

Anders
[1] http://en.wikipedia.org/wiki/The_White_Rabbit_Project
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Re: [time-nuts] NIST Optical lattice clocks

[Anders Wallin]

According to Wikipedia, The optical clock based on it is exact to 17 digits
 after the decimal point!
 I hope that doesn't mean it is time to trade my HP 5370B in shortly...
 How do they measure down to these resolutions?


Short answer: instead of a few GHz (Cs clock or H-maser), go to 500 THz or
so.

Long answer:

You can think of these optical clocks as an exercise in laser
stabilization. A laser with the correct wavelength for the atomic species
chosen (Yb, Sr, Ca, and so on) is stabilized to a fabry-perot resonator
(two mirrors separated by a glass or silicon spacer). If the resonator
(mirrors+spacer) is kept in vacuum, temperature stabilized well, and
isolated from vibrations (seismic/acoustic), the mirror-separation (which
determines the resonance frequency) is stable to (roughly) 1 part in 10^16
or so for short time scales (100s maybe).
If the resonator would be absolutely stable this alone would make a clock.
But there is ageing/creep in the spacer material, as well as thermal noise
in the spacer/mirrors that limits performance.

To get rid of the long-term drift of the reference-resonator these lasers
(oscillating at say 500 THz)  which are stable to 1Hz are locked to the
clock transition (an optical absorption resonance) of the atomic species
chosen.
If the atoms are cooled  and isolated from the environment (electric,
magnetic fields etc) a narrow absorption line can show a linewidth of one
or a few Hz.
Keep the 500 THz local-oscillator locked to the atomic reference with ~1 Hz
or better for a few hours/days and you have an optical clock!

The clockwork that converts laser light at 500 THz down to a reasonable
RF frequency is a femtosecond frequency comb - which is fairly standard
technology by now.


 http://tf.nist.gov/ofm/calcium/ybhome.htm
 I thought they are already able to capture an atom in its own well?


There are two approaches:
- ion-clocks that trap a single ion in an RF trap. It's easier to cool and
control a single atom/ion, but the signal for locking is weak.
- lattice-clocks trap neutral atoms in an optical standing-wave trap. SNR
scales with the number of atoms, so more is better, as long as you can cool
them all and ensure they experience the exact same environment so they all
show an identical clock-transition.

AFAIK the lattice-clocks trap maybe 100s or 1000s of atoms in one well, and
have a 1D lattice with many wells in order to get up to maybe 1e6 atoms in
total which are probed by the clock laser.

hope this helps :)
Anders
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