Re: [time-nuts] Commercial software defined radio for clock metrology
On Jul 29, 2016, at 5:14 PM, Kevin Rosenberg wrote: I had a question about your experience. You mentioned using a input signal near the maximum of the USRP’s ADC to get the best SNR. I reviewed the schematics and application notes. I found a maximum Vpp mentioned of 3.3V. I was wondering what voltage you were using to drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal distortions and not much increase in the amplitude. The absolute limit is not the 3.3V supply but a voltage reference embedded in the ADC (ADS62P44): 2V peak-to-peak. For the studies in the paper, the RF power input to the BasicRX board (which features a transformer-coupling into the differential ADC inputs) was kept below 0 dBm; more often approximately -3 dBm. I noticed distortion first in the harmonic content of signals after down-conversion beyond about half-scale on the ADC. The "gain" setting in the firmware will have an impact as well; I believe I set the gain to 0 (i.e. no gain) for all the published data. N.B. the ADC is not a 50-ohm device; the daughterboard does the impedance matching. Best wishes, Jeff Sherman National Institute of Standards & Technology Time and Frequency Division (688) 325 Broadway / Boulder, CO 80305 / 303-497-3511 ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi There are a *lot* of papers out there on downsampling and ADEV. Just about any / every technique known has been tried and evaluated. The only “correct” answer is to throw away the samples (decimation). Anything else you do will give you subtle (or not so subtle) issues. That said, there are standard filtering approaches that impact the first point, but don’t do much past that. Sam Stein published a few papers on the why and the how of the conventional approach (if you are going to filter). It has an impact, but at least you know what it is likely to do. Bob > On Jul 29, 2016, at 11:44 PM, Kevin Rosenberg wrote: > > Hi Bob, > > You have a good point. That leads to the question is what is the “best” > measurement technique when you are sampling at a more smaller interval than > the desired tau? > > SDRs sample at high rates. The slowest the USRP N2x0 can sample is just under > 200Ksps. For easy math, let’s assume we sample at 1Msps but we want to record > only 1sps for a long-term measurement. What’s best way to handle the 1e6 to 1 > ratio of available samples to desired samples? One method is to discard > 999,999 samples and just record the phase difference with a true tau of 1 > sec. The other is to take a window of 1e6 samples and output the average > phase difference over that 1 second window. Is your point that averaging > samples that are more frequent than the tau will overestimate stability at > the tau? If using averaged data, would it be “less lying” to multiply the > ADEV by the sqrt of the length of the averaging window? > > I’d appreciate your thoughts on the subject, > > Kevin > >> On Jul 29, 2016, at 6:51 PM, Bob Camp wrote: >> >> HI >> >> Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you …. >> >> Bob >> >>> On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote: >>> >>> Jeff, >>> >>> Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I >>> created a C++ program and checked residuals using a 10 MHz clock split >>> to the A and B channels of a LFRX and BasicRX boards and sampled at 1 >>> Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed >>> by the low noise floor approaching that of my Timepod which was >>> several times the cost. I included the Allan Deviation without >>> averaging showing the sqrt(1000) increase in noise floor without the >>> averaging[2]. >>> >>> I had a question about your experience. You mentioned using a input >>> signal near the maximum of the USRP’s ADC to get the best SNR. I >>> reviewed the schematics and application notes. I found a maximum Vpp >>> mentioned of 3.3V. I was wondering what voltage you were using to >>> drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal >>> distortions and not much increase in the amplitude. >>> >>> Many thanks for publishing your work in this area. >>> >>> Kevin >>> >>> [1] >>> https://arxiv.org/abs/1605.03505 >>> >>> [2] >>> ___ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi The simple answer is a filter at the highest sample rate (say 1 second) that impacts the 1 second data. You then decimate from there. If you want 1 second data that “looks right” you start at something higher (say 0.1 second) and filter there. The data set is filtered once (if at all) and decimated from there. Bob > On Jul 30, 2016, at 12:04 PM, Kevin Rosenberg wrote: > > Hmm, I might have answered my own question: filter to the fast samples to the > equivalent noise bandwidth (ENBW) of the lower desired sampling rate and then > decimate. > >> On Jul 29, 2016, at 9:44 PM, Kevin Rosenberg wrote: >> >> Hi Bob, >> >> You have a good point. That leads to the question is what is the “best” >> measurement technique when you are sampling at a more smaller interval than >> the desired tau? >> >> SDRs sample at high rates. The slowest the USRP N2x0 can sample is just >> under 200Ksps. For easy math, let’s assume we sample at 1Msps but we want to >> record only 1sps for a long-term measurement. What’s best way to handle the >> 1e6 to 1 ratio of available samples to desired samples? One method is to >> discard 999,999 samples and just record the phase difference with a true tau >> of 1 sec. The other is to take a window of 1e6 samples and output the >> average phase difference over that 1 second window. Is your point that >> averaging samples that are more frequent than the tau will overestimate >> stability at the tau? If using averaged data, would it be “less lying” to >> multiply the ADEV by the sqrt of the length of the averaging window? >> >> I’d appreciate your thoughts on the subject, >> >> Kevin >> >>> On Jul 29, 2016, at 6:51 PM, Bob Camp wrote: >>> >>> HI >>> >>> Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you >>> …. >>> >>> Bob >>> On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote: Jeff, Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I created a C++ program and checked residuals using a 10 MHz clock split to the A and B channels of a LFRX and BasicRX boards and sampled at 1 Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed by the low noise floor approaching that of my Timepod which was several times the cost. I included the Allan Deviation without averaging showing the sqrt(1000) increase in noise floor without the averaging[2]. I had a question about your experience. You mentioned using a input signal near the maximum of the USRP’s ADC to get the best SNR. I reviewed the schematics and application notes. I found a maximum Vpp mentioned of 3.3V. I was wondering what voltage you were using to drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal distortions and not much increase in the amplitude. Many thanks for publishing your work in this area. Kevin [1] https://arxiv.org/abs/1605.03505 [2] ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. >>> >>> ___ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >>> >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hmm, I might have answered my own question: filter to the fast samples to the equivalent noise bandwidth (ENBW) of the lower desired sampling rate and then decimate. > On Jul 29, 2016, at 9:44 PM, Kevin Rosenberg wrote: > > Hi Bob, > > You have a good point. That leads to the question is what is the “best” > measurement technique when you are sampling at a more smaller interval than > the desired tau? > > SDRs sample at high rates. The slowest the USRP N2x0 can sample is just under > 200Ksps. For easy math, let’s assume we sample at 1Msps but we want to record > only 1sps for a long-term measurement. What’s best way to handle the 1e6 to 1 > ratio of available samples to desired samples? One method is to discard > 999,999 samples and just record the phase difference with a true tau of 1 > sec. The other is to take a window of 1e6 samples and output the average > phase difference over that 1 second window. Is your point that averaging > samples that are more frequent than the tau will overestimate stability at > the tau? If using averaged data, would it be “less lying” to multiply the > ADEV by the sqrt of the length of the averaging window? > > I’d appreciate your thoughts on the subject, > > Kevin > >> On Jul 29, 2016, at 6:51 PM, Bob Camp wrote: >> >> HI >> >> Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you …. >> >> Bob >> >>> On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote: >>> >>> Jeff, >>> >>> Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I >>> created a C++ program and checked residuals using a 10 MHz clock split >>> to the A and B channels of a LFRX and BasicRX boards and sampled at 1 >>> Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed >>> by the low noise floor approaching that of my Timepod which was >>> several times the cost. I included the Allan Deviation without >>> averaging showing the sqrt(1000) increase in noise floor without the >>> averaging[2]. >>> >>> I had a question about your experience. You mentioned using a input >>> signal near the maximum of the USRP’s ADC to get the best SNR. I >>> reviewed the schematics and application notes. I found a maximum Vpp >>> mentioned of 3.3V. I was wondering what voltage you were using to >>> drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal >>> distortions and not much increase in the amplitude. >>> >>> Many thanks for publishing your work in this area. >>> >>> Kevin >>> >>> [1] >>> https://arxiv.org/abs/1605.03505 >>> >>> [2] >>> ___ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >>> and follow the instructions there. >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. >> > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi Bob, You have a good point. That leads to the question is what is the “best” measurement technique when you are sampling at a more smaller interval than the desired tau? SDRs sample at high rates. The slowest the USRP N2x0 can sample is just under 200Ksps. For easy math, let’s assume we sample at 1Msps but we want to record only 1sps for a long-term measurement. What’s best way to handle the 1e6 to 1 ratio of available samples to desired samples? One method is to discard 999,999 samples and just record the phase difference with a true tau of 1 sec. The other is to take a window of 1e6 samples and output the average phase difference over that 1 second window. Is your point that averaging samples that are more frequent than the tau will overestimate stability at the tau? If using averaged data, would it be “less lying” to multiply the ADEV by the sqrt of the length of the averaging window? I’d appreciate your thoughts on the subject, Kevin > On Jul 29, 2016, at 6:51 PM, Bob Camp wrote: > > HI > > Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you …. > > Bob > >> On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote: >> >> Jeff, >> >> Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I >> created a C++ program and checked residuals using a 10 MHz clock split >> to the A and B channels of a LFRX and BasicRX boards and sampled at 1 >> Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed >> by the low noise floor approaching that of my Timepod which was >> several times the cost. I included the Allan Deviation without >> averaging showing the sqrt(1000) increase in noise floor without the >> averaging[2]. >> >> I had a question about your experience. You mentioned using a input >> signal near the maximum of the USRP’s ADC to get the best SNR. I >> reviewed the schematics and application notes. I found a maximum Vpp >> mentioned of 3.3V. I was wondering what voltage you were using to >> drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal >> distortions and not much increase in the amplitude. >> >> Many thanks for publishing your work in this area. >> >> Kevin >> >> [1] >> https://arxiv.org/abs/1605.03505 >> >> [2] >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts >> and follow the instructions there. > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
HI Keep in mind that if you apply pre-filtering, an ADEV plot is lying to you …. Bob > On Jul 29, 2016, at 6:58 PM, Kevin Rosenberg wrote: > > Jeff, > > Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I > created a C++ program and checked residuals using a 10 MHz clock split > to the A and B channels of a LFRX and BasicRX boards and sampled at 1 > Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed > by the low noise floor approaching that of my Timepod which was > several times the cost. I included the Allan Deviation without > averaging showing the sqrt(1000) increase in noise floor without the > averaging[2]. > > I had a question about your experience. You mentioned using a input > signal near the maximum of the USRP’s ADC to get the best SNR. I > reviewed the schematics and application notes. I found a maximum Vpp > mentioned of 3.3V. I was wondering what voltage you were using to > drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal > distortions and not much increase in the amplitude. > > Many thanks for publishing your work in this area. > > Kevin > > [1] > https://arxiv.org/abs/1605.03505 > > [2] > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Jeff, Thanks for your very useful paper Oscillator Metrology with SDRs[1]. I created a C++ program and checked residuals using a 10 MHz clock split to the A and B channels of a LFRX and BasicRX boards and sampled at 1 Mhz. Using boxcar averaging of 1000 samples at 1 kHz, I was impressed by the low noise floor approaching that of my Timepod which was several times the cost. I included the Allan Deviation without averaging showing the sqrt(1000) increase in noise floor without the averaging[2]. I had a question about your experience. You mentioned using a input signal near the maximum of the USRP’s ADC to get the best SNR. I reviewed the schematics and application notes. I found a maximum Vpp mentioned of 3.3V. I was wondering what voltage you were using to drive the USRPs. When I go above 1.5-2 Vpp, I start getting signal distortions and not much increase in the amplitude. Many thanks for publishing your work in this area. Kevin [1] https://arxiv.org/abs/1605.03505 [2] ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Wed, 1 Jun 2016 16:00:39 + "Sherman, Jeffrey A. (Fed)" wrote: > I'm not sure exact which ~15dB you're contemplating, but I'll hazard > a guess. You measured an ADC noise floor of -140dBc/Hz. The TimePod has a spec'ed noise floor of -170dBc/Hz(typ). That's a difference of ~30dB. The different specs of the ADCs and the signal level account for a difference of about ~14dB. There is still a ~16dB difference that I cannot explain. > We observe some non-idealities in the SDR (or our noise environment), > the effect of which scales with decimation factor. In principle, reducing > the bandwidth through low-pass decimation---suppose by a factor of 100-- >-should increase the signal-to-noise by 20 dB. This result relies on a > completely white-noise spectrum, ideal filters, and no round-off or > quantization noise. For a decimation factor of 100, we observed an SNR > improvement of about 11 dB instead of 20 dB. This deficit in "process gain" > was another 3 dB worse at a decimation factor of 500. Some additional > details are in Appendix B of the paper. I would have guessed, that the TimePod is plagued by the same effects. But maybe it has less spurs and thus can achieve a higher SNR gain during decimation. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On 6/1/16 8:45 AM, Sherman, Jeffrey A. (Fed) wrote: Jim Lux: If you pick the right USRP models, you can lock the sampling clocks together or distribute the clock. I don't know if that distribution is sufficiently high quality for time-nuts kinds of applications. A bit of extra detail related to this but not reported in print... The N210 has two means of locking the sampling clocks of two SDR units together. First, a 10 MHz reference signal can be split and input into the two units' reference ports. Second, a "MIMO link" can be made between the two units with a SFP-style "direct-attach" cable. I don't know the details of this digital link, but it supports data transfer (so only one of the two SDR units requires an Ethernet connection) and reference frequency/time transfer. Is the digital MIMO-link method any worse than the analog splitter method? Over short averaging intervals (1 us through ~30 us), we resolved no degradation in a 1-channel measurement. This is consistent with the advertised bandwidth of the PLL ~3 kHz. Over intervals 1 ms through 10 ms, the MIMO-link reference method resulted in about a factor-of-2 worse time deviation (in this test, the NCO was turned for a heterodyne frequency of approximately 8 Hz, which also leads to an oscillation peak in this range). Beyond 10 ms, both methods showed the same ~150 fs flicker floor that we've attributed to the ADC aperture jitter. Finally, the SDR also has a PPS input, which can be used to "name" a 100 MHz master clock edge as an epoch (with 10 ns resolution). Although I didn't test this, I think this epoch can be synchronized over the MIMO link. Interesting.. We were doing some work with the earlier USRPs and wanted to actually run the ADC tied to an external clock at a peculiar rate - which it turns out the USRP doesn't support: you can lock the internal clock to an external reference (or to a signal from another USRP), but there's that PLL in the mix, so you have the usual issues. I think the MIMO link actually transfers the same clock around (so you can guarantee synchronous sampling). But ultimately, we wound up going another direction - we needed the "external clock" input. I think the MIMO transfer doesn't go through the PLL ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Jim Lux: If you pick the right USRP models, you can lock the sampling clocks together or distribute the clock. I don't know if that distribution is sufficiently high quality for time-nuts kinds of applications. A bit of extra detail related to this but not reported in print... The N210 has two means of locking the sampling clocks of two SDR units together. First, a 10 MHz reference signal can be split and input into the two units' reference ports. Second, a "MIMO link" can be made between the two units with a SFP-style "direct-attach" cable. I don't know the details of this digital link, but it supports data transfer (so only one of the two SDR units requires an Ethernet connection) and reference frequency/time transfer. Is the digital MIMO-link method any worse than the analog splitter method? Over short averaging intervals (1 us through ~30 us), we resolved no degradation in a 1-channel measurement. This is consistent with the advertised bandwidth of the PLL ~3 kHz. Over intervals 1 ms through 10 ms, the MIMO-link reference method resulted in about a factor-of-2 worse time deviation (in this test, the NCO was turned for a heterodyne frequency of approximately 8 Hz, which also leads to an oscillation peak in this range). Beyond 10 ms, both methods showed the same ~150 fs flicker floor that we've attributed to the ADC aperture jitter. Finally, the SDR also has a PPS input, which can be used to "name" a 100 MHz master clock edge as an epoch (with 10 ns resolution). Although I didn't test this, I think this epoch can be synchronized over the MIMO link. Best wishes, -js ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Atilla Kinali: Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216 is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in Sherman and Jördens experiments were kept around half scale, which is another -6dB in SNR. There is another ~15dB in difference, but I currently don't see where it comes from. I'm not sure exact which ~15dB you're contemplating, but I'll hazard a guess. We observe some non-idealities in the SDR (or our noise environment), the effect of which scales with decimation factor. In principle, reducing the bandwidth through low-pass decimation---suppose by a factor of 100---should increase the signal-to-noise by 20 dB. This result relies on a completely white-noise spectrum, ideal filters, and no round-off or quantization noise. For a decimation factor of 100, we observed an SNR improvement of about 11 dB instead of 20 dB. This deficit in "process gain" was another 3 dB worse at a decimation factor of 500. Some additional details are in Appendix B of the paper. Best wishes, -js ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Wed, 25 May 2016 16:01:51 + "Sherman, Jeffrey A. (Fed)" wrote: > We found that in the studied units the limiting non-stationary noise > source was likely the aperture jitter of the ADC (the instability of the > delay between an idealized sample trigger and actuation of the sample/hold > circuitry). However, the ADC's aperture jitter appears highly common-mode in > chips with a second "simultaneously-sampled" input channel, allowing for an > order-of-magnitue improvement after channel-to-channel subtraction. For > example, at 5 MHz, the SDR showed a time deviation floor of ~20 fs after > just 10 ms of averaging; the aperture jitter specification was 150 fs. We > also describe tests with maser signals lasting several days. I tried to understand where the aperture jitter comes from and why it has such a huge common-mode. I asked a professor from Stanford doing research on ADCs a couple of questions in this regard, especialy whether he had any good references to read. Apparently, most of the noise in ADCs is internally generated. The two biggest contributors to aperture jitter seem to be thermal noise in the clock path and power supply noise. Interestingly, power supply noise comes mostly from the ADC itself and not from the external power source. I've been told the voltage drop on the power grid due to current spiking on chip can reach several tens of mV. Beside that, most research on jitter induced ADC noise only considers the clock jitter as source. There are very few that consider supply induced jitter as well, but no numbers are given. A few also mention substrate coupled noise, but according to the professor that is negligible in reality. The professor was surprised at how much of the aperture jitter is common-mode. He asked whether there was any explanation given by Jeffrey or Roberts in the paper, which I had to deny. His best guess was that the common-mode came either from external supply or internal supply issues common to both channels. He also remarked that the phase noise spectrum could give hints. I personally do not think that the phase noise spectrum reviles anything. There is just too much going on to say anything. I think it would be interesting to try a board designed for low noise operation and see what that would show (partially working on that already for other reasons). I also found out that the sample-and-hold circuits have a input voltage dependent delay component. So there is potentially a phase shift dependent change in the noise floor. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Bob Camp: > In many DMTD (and single mixer) systems, a lowpass and high pass filter are > applied to the signal coming out of the mixer. > This is done to improve the zero crossing detection. It also effectively > reduces the “pre detection” bandwidth. My understanding > of the setup in your paper does not do this sort of filtering. It simply > operated directly on the downconverter signal. Is this correct? > I may have missed something really obvious in a quick read of the paper….. Yes. After the filtering and down-conversion in the FPGA, we applied no further filtering in software (except in very long data runs we averaged the phase in 1 second "chunks" of samples before recording). ADC zero offset (or slow fluctuations) is removed with a high-pass filter implemented in the FPGA. Following down-conversion, a series of decimating low-pass filters in hardware reduces the data rate (typically by a factor of ~100) and the bandwidth. Both of these have the same effect of reducing the "pre-detection" bandwidth with the trade-offs of a) reducing the noise bandwidth (but not the noise density floor), and b) reducing the data throughput. Best wishes, -js ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
No it has 4 x LTC2216 (single 16bit ADCs). Bruce On Sunday, 29 May 2016 4:06 AM, Bob Camp wrote: HI It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in it? You can select which way you route the signals into the ADEV process. Bob > On May 28, 2016, at 11:04 AM, Bruce Griffiths > wrote: > > One can just measure the TDEV performance.I can measure the TDEV performance > at 10MHz later today if that's useful.It should be somewhat similar to the > single channel SDR instrument given there is no cancellation of most of the > internal ADC clock conditioning system noise. > Bruce > > > On Sunday, 29 May 2016 2:04 AM, Attila Kinali wrote: > > > On Sat, 28 May 2016 08:47:45 + (UTC) > Bruce Griffiths wrote: > >> This SDR setup appears to have a higher PN (at least 2 ADC's per signal >> are required to achieve lower PN ) than a Timepod, however it appears >> to be better at measuring ADEV than a Timepod. > > Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216 > is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in > Sherman and Jördens experiments were kept around half scale, which is > another -6dB in SNR. There is another ~15dB in difference, but I currently > don't see where it comes from. > > > What I wonder is, what the TDEV performance of the TimePod is, given > that it uses single channel ADCs. Unfortunately, there is nothing in the spec. > > Guestimating from the ADEV specs, it looks like that the TimePod has about > the performance of the single channel setup. Which approximately makes sense. > > Attila Kinali > > -- > Reading can seriously damage your ignorance. > -- unknown > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
HI It’s been a while since I dug into a TimePod. Doesn’t it have two dual ADC’s in it? You can select which way you route the signals into the ADEV process. Bob > On May 28, 2016, at 11:04 AM, Bruce Griffiths > wrote: > > One can just measure the TDEV performance.I can measure the TDEV performance > at 10MHz later today if that's useful.It should be somewhat similar to the > single channel SDR instrument given there is no cancellation of most of the > internal ADC clock conditioning system noise. > Bruce > > >On Sunday, 29 May 2016 2:04 AM, Attila Kinali wrote: > > > On Sat, 28 May 2016 08:47:45 + (UTC) > Bruce Griffiths wrote: > >> This SDR setup appears to have a higher PN (at least 2 ADC's per signal >> are required to achieve lower PN ) than a Timepod, however it appears >> to be better at measuring ADEV than a Timepod. > > Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216 > is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in > Sherman and Jördens experiments were kept around half scale, which is > another -6dB in SNR. There is another ~15dB in difference, but I currently > don't see where it comes from. > > > What I wonder is, what the TDEV performance of the TimePod is, given > that it uses single channel ADCs. Unfortunately, there is nothing in the spec. > > Guestimating from the ADEV specs, it looks like that the TimePod has about > the performance of the single channel setup. Which approximately makes sense. > > Attila Kinali > > -- > Reading can seriously damage your ignorance. > -- unknown > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
One can just measure the TDEV performance.I can measure the TDEV performance at 10MHz later today if that's useful.It should be somewhat similar to the single channel SDR instrument given there is no cancellation of most of the internal ADC clock conditioning system noise. Bruce On Sunday, 29 May 2016 2:04 AM, Attila Kinali wrote: On Sat, 28 May 2016 08:47:45 + (UTC) Bruce Griffiths wrote: > This SDR setup appears to have a higher PN (at least 2 ADC's per signal > are required to achieve lower PN ) than a Timepod, however it appears > to be better at measuring ADEV than a Timepod. Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216 is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in Sherman and Jördens experiments were kept around half scale, which is another -6dB in SNR. There is another ~15dB in difference, but I currently don't see where it comes from. What I wonder is, what the TDEV performance of the TimePod is, given that it uses single channel ADCs. Unfortunately, there is nothing in the spec. Guestimating from the ADEV specs, it looks like that the TimePod has about the performance of the single channel setup. Which approximately makes sense. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Sat, 28 May 2016 08:47:45 + (UTC) Bruce Griffiths wrote: > This SDR setup appears to have a higher PN (at least 2 ADC's per signal > are required to achieve lower PN ) than a Timepod, however it appears > to be better at measuring ADEV than a Timepod. Yes, the spec'ed SNR of the ADS62P44 is 74dBFS (typ) while the LTC2216 is spec'ed with 81dBFS (typ). Additionally, the input amplitudes in Sherman and Jördens experiments were kept around half scale, which is another -6dB in SNR. There is another ~15dB in difference, but I currently don't see where it comes from. What I wonder is, what the TDEV performance of the TimePod is, given that it uses single channel ADCs. Unfortunately, there is nothing in the spec. Guestimating from the ADEV specs, it looks like that the TimePod has about the performance of the single channel setup. Which approximately makes sense. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On 5/27/16 6:58 PM, Hal Murray wrote: bruce.griffi...@xtra.co.nz said: All the filtering and down mixing is done in the digital domain. Anitialiasing filters in front of the ADCs are also be required. What sort of bandwidth is expected? The usual trick with audio ADCs is to have a low cost analog filter that does't have a sharp corner but lets everything you want through, sample at a high rate - say 16x, run that through a digital filter with a sharp cutoff, then decimate down to the desired sample rate. The USRP uses fast ADCs intended for the wireless market. Sample rates are >50MSPS. You can get daughter cards which have an analog PLL and mixer to tune over a wider band - as you can imagine, 2.5 and 5.8 GHz are popular. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On 5/27/16 5:17 PM, Bruce Griffiths wrote: On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: Hi Very interesting paper, thanks for sharing !! One question: In many DMTD (and single mixer) systems, a lowpass and high pass filter are applied to the signal coming out of the mixer. This is done to improve the zero crossing detection. It also effectively reduces the “pre detection” bandwidth. My understanding of the setup in your paper does not do this sort of filtering. It simply operated directly on the downconverter signal. Is this correct? I may have missed something really obvious in a quick read of the paper….. Thanks! Bob All the filtering and down mixing is done in the digital domain. Anitialiasing filters in front of the ADCs are also be required. A 2 (or more) receive channel SDR board would be a nice tool to use for this provided the FPGA is large enough. Most of the off the shelf SDR units (like the USRP) have more than enough FPGA. The "standard" software in the USRP is a digital down converter with an "IF" filter used as a front end for gnuradio. It streams the downconverted and bandlimited samples to a back-end PC via USB or Ethernet. If you pick the right USRP models, you can lock the sampling clocks together or distribute the clock. I don't know if that distribution is sufficiently high quality for time-nuts kinds of applications. My experience with the USRP has been that the detailed documentation on this sort of thing tends to be kind of light, if not non-existent. You might be digging into the source code to figure out what the interface is and how it's implemented. The other thing is that the USRP is made as a "radio" and more particularly, one target market is people like grad students developing wireless comm software, things like MIMO algorithms, etc. In general, the oscillator and sampler quality isn't at "gnat's eyelash" kind of performance. If your primary market is developing multimegabit/second phy layer wireless comms, you tend not to be worried about phase noise at 10 Hz from the carrier. The NIST paper discusses this aspect. Bruce On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) wrote: Hello, A recently published paper might be of interest to the time-nuts community. We studied how well an unmodified commercial software defined radio (SDR) device/firmware could serve in comparing high-performance oscillators and atomic clocks. Though we chose to study the USRP platform, the discussion easily generalizes to many other SDRs. I understand that for one month, the journal allows for free electronic downloads of the manuscript at: http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 (Review of Scientific Instruments 87, 054711 (2016)) Perhaps the biggest worry about the SDR approach is that fast ADCs are in general much noisier than the analog processing components in DMTD. However, quantization noise is at least amenable to averaging. As you all likely appreciate, what really limits high precision clock comparison is instrument stability. In this regard, the SDR's digital signal processing steps (frequency translation, sample rate decimation, and low-pass filtering) are at least perfectly stable and can be made sufficiently accurate. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On 5/27/16 6:15 PM, Bob Camp wrote: Hi On May 27, 2016, at 8:17 PM, Bruce Griffiths wrote: On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: Hi Very interesting paper, thanks for sharing !! One question: In many DMTD (and single mixer) systems, a lowpass and high pass filter are applied to the signal coming out of the mixer. This is done to improve the zero crossing detection. It also effectively reduces the “pre detection” bandwidth. My understanding of the setup in your paper does not do this sort of filtering. It simply operated directly on the downconverter signal. Is this correct? I may have missed something really obvious in a quick read of the paper….. Thanks! Bob All the filtering and down mixing is done in the digital domain. Anitialiasing filters in front of the ADCs are also be required. A 2 (or more) receive channel SDR board would be a nice tool to use for this provided the FPGA is large enough. So … is there an explicit high pass in the FPGA other than the dc offset elimination high pass? There is obviously a lowpass function in the decimating FIR’s and the CIC. That appears to be optimized simply for sample rate rather than for noise. Thus the same question applies to low pass as well. If they are using the stock USRP load, it's a digital down converter: NCO mixes with input samples, CIC decimator and bandpass filter (actually low pass I/Q), followed by a couple FIR filters. Then, you can implement whatever further filtering and processing you want in software, most commonly done in gnuradio (by far most common) or simulink/Matlab. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi The Max V FPGA on the Bemicro card is pretty impressive. The gotcha is with the Quartus side of things. Altera is not willing to let you have the DSP stuff (NCO’s, CIC’s, FIR’s) for free the way Xilinx is. Bob > On May 28, 2016, at 4:47 AM, Bruce Griffiths > wrote: > > A low pass filter will reduce the source broadband noise aliased into the ADC > output signal. > > Using the LVDS ADC outputs rather than the CMOS outputs may help in reducing > noise generated on the board. NB the ADC performance is specified when the > LVDS outputs are used. > > This SDR setup appears to have a higher PN (at least 2 ADC's per signal are > required to achieve lower PN ) than a Timepod, however it appears to be > better at measuring ADEV than a Timepod. > Bruce > >On Saturday, 28 May 2016 6:02 PM, Attila Kinali wrote: > > > On Fri, 27 May 2016 18:58:35 -0700 > Hal Murray wrote: > >> bruce.griffi...@xtra.co.nz said: >>> All the filtering and down mixing is done in the digital domain. >>> Anitialiasing filters in front of the ADCs are also be required. >> >> What sort of bandwidth is expected? >> >> The usual trick with audio ADCs is to have a low cost analog filter that >> does't have a sharp corner but lets everything you want through, sample at a >> high rate - say 16x, run that through a digital filter with a sharp cutoff, >> then decimate down to the desired sample rate. > > The daughterboards for the USRP N210 that allow direct access to the > ADC inputs do not contain any filters. They kind of expect band limited > signals at the input. > > Given that they used 10MHz signals from H-masers and used 100Msps, > I would say that the Niquist condition does hold. One might probably > increase the noise performance a little bit by using a low pass filter. > > Attila Kinali > > -- > Reading can seriously damage your ignorance. > -- unknown > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi The normal process with a 10 Hz beat note in a DMTD is to have something like a 6 Hz two pole high pass and a 15 Hz two pole lowpass after the mixer and before any zero crossing stuff. This is after down conversion, but before any demodulation. This of course is based on the fundamental assumption in a DMTD that the inputs are within a fraction of a Hertz of the target at all times. In a system that has one input offset 12 to 121 Hz and the other at 80 to 9,000 Hz, the approach isn’t going to work as well. Bob > On May 27, 2016, at 9:58 PM, Hal Murray wrote: > > > bruce.griffi...@xtra.co.nz said: >> All the filtering and down mixing is done in the digital domain. >> Anitialiasing filters in front of the ADCs are also be required. > > What sort of bandwidth is expected? > > The usual trick with audio ADCs is to have a low cost analog filter that > does't have a sharp corner but lets everything you want through, sample at a > high rate - say 16x, run that through a digital filter with a sharp cutoff, > then decimate down to the desired sample rate. > > -- > These are my opinions. I hate spam. > > > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
A low pass filter will reduce the source broadband noise aliased into the ADC output signal. Using the LVDS ADC outputs rather than the CMOS outputs may help in reducing noise generated on the board. NB the ADC performance is specified when the LVDS outputs are used. This SDR setup appears to have a higher PN (at least 2 ADC's per signal are required to achieve lower PN ) than a Timepod, however it appears to be better at measuring ADEV than a Timepod. Bruce On Saturday, 28 May 2016 6:02 PM, Attila Kinali wrote: On Fri, 27 May 2016 18:58:35 -0700 Hal Murray wrote: > bruce.griffi...@xtra.co.nz said: > > All the filtering and down mixing is done in the digital domain. > > Anitialiasing filters in front of the ADCs are also be required. > > What sort of bandwidth is expected? > > The usual trick with audio ADCs is to have a low cost analog filter that > does't have a sharp corner but lets everything you want through, sample at a > high rate - say 16x, run that through a digital filter with a sharp cutoff, > then decimate down to the desired sample rate. The daughterboards for the USRP N210 that allow direct access to the ADC inputs do not contain any filters. They kind of expect band limited signals at the input. Given that they used 10MHz signals from H-masers and used 100Msps, I would say that the Niquist condition does hold. One might probably increase the noise performance a little bit by using a low pass filter. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
> As we are doing a similar desgin > also using a Zynq 7010 I would appreciate if you could elaborate > a bit what made the FPGA too small for your application. It wasn't too small, I just had to think about just how much filtering I was using. "It was a struggle" probably overstated the situation. The main limitation is number of DSP slices (80 for the Zynq7010) rather than general FPGA resources. Most of these are used by the CIC+FIR decimation and this is largely because I am working with 64 bit data so that each filter stage needs twice as many DSP resources as you would for say 32 bit data (where the 48 bits each MAC has might be enough to get by with). This may be overkill in some applications. The original application for this was in tracking phase in a laser heterodyne interferometer where phase rollovers during long measurement times were undesirable. So for other applications eg a 10 MHz phase comparison where frequency differences are quite small, the data width could be dropped significantly. Cheers Michael On Sat, May 28, 2016 at 3:11 PM, Attila Kinali wrote: > On Sat, 28 May 2016 12:08:18 +1000 > Michael Wouters wrote: > >> I also have been looking at low-cost SDR hardware for T&F measurements >> and have made an RF phase meter based on the Red Pitaya. The >> performance of this was not as good as I was hoping for: the >> fractional frequency resolution of this is about 10E-12 at 1 second >> averaging time. An earlier implementation on fairly ordinary NI >> hardware (14 bit 100 MHz ADCs) did better than 10E-13. Part of the >> problem seems to be that although the RP ADC is 14 bits, the effective >> number of bits is really only 10, according to a study I read (ENOB >> for the NI ADCs is specified as 12). The RP is a bit constrained for >> DSP resources too - it was a struggle to squeeze in the decimation >> filters. > > This does not really surprise me. The Red Pitaya has not been done > by someone who knows how to do a low noise design. > > Unfortunately, there are no schematics of the board available > (why someone would keep these secret when everything else is > open source is beyond me), but from what is known: > A dual 14bit 125Msps ADC (LT2145) that are fed by an Opamp > (seems to be an LTC6403) to get a differential signal out of > the signle ended input. There is an quite high impedance input > divider stage (500k to 1M resistors!). > > But the biggest problem of the board is, that the ADC is right > next (as in ~2mm distance) from the Zynq FPGA+CPU SoC. > No matter how well you "shield" the ADC, this alone will eat up > quite a bit of the ADC's performance. > > As for the FPGA size, it's supposed to be a 17k LUT type. It's not > the biggest FPGA on the market, but that should be quite a bit of > resources. So I am a little bit surprised that you had trouble to > fit in the decimation filters. As we are doing a similar desgin > also using a Zynq 7010 I would appreciate if you could elaborate > a bit what made the FPGA too small for your application. As this > would mean that we have to potentially redesign the board. > > > Attila Kinali > > "schematics" (aka extended block diagram) of the red pitaya prototype: > https://dl.dropboxusercontent.com/s/jkdy0p05a2vfcba/Red_Pitaya_Schematics_v1.0.1.pdf > > Close up pictures: > http://imgur.com/a/AuYWf > > > -- > Reading can seriously damage your ignorance. > -- unknown > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Sat, 28 May 2016 12:08:18 +1000 Michael Wouters wrote: > I also have been looking at low-cost SDR hardware for T&F measurements > and have made an RF phase meter based on the Red Pitaya. The > performance of this was not as good as I was hoping for: the > fractional frequency resolution of this is about 10E-12 at 1 second > averaging time. An earlier implementation on fairly ordinary NI > hardware (14 bit 100 MHz ADCs) did better than 10E-13. Part of the > problem seems to be that although the RP ADC is 14 bits, the effective > number of bits is really only 10, according to a study I read (ENOB > for the NI ADCs is specified as 12). The RP is a bit constrained for > DSP resources too - it was a struggle to squeeze in the decimation > filters. This does not really surprise me. The Red Pitaya has not been done by someone who knows how to do a low noise design. Unfortunately, there are no schematics of the board available (why someone would keep these secret when everything else is open source is beyond me), but from what is known: A dual 14bit 125Msps ADC (LT2145) that are fed by an Opamp (seems to be an LTC6403) to get a differential signal out of the signle ended input. There is an quite high impedance input divider stage (500k to 1M resistors!). But the biggest problem of the board is, that the ADC is right next (as in ~2mm distance) from the Zynq FPGA+CPU SoC. No matter how well you "shield" the ADC, this alone will eat up quite a bit of the ADC's performance. As for the FPGA size, it's supposed to be a 17k LUT type. It's not the biggest FPGA on the market, but that should be quite a bit of resources. So I am a little bit surprised that you had trouble to fit in the decimation filters. As we are doing a similar desgin also using a Zynq 7010 I would appreciate if you could elaborate a bit what made the FPGA too small for your application. As this would mean that we have to potentially redesign the board. Attila Kinali "schematics" (aka extended block diagram) of the red pitaya prototype: https://dl.dropboxusercontent.com/s/jkdy0p05a2vfcba/Red_Pitaya_Schematics_v1.0.1.pdf Close up pictures: http://imgur.com/a/AuYWf -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Fri, 27 May 2016 18:58:35 -0700 Hal Murray wrote: > bruce.griffi...@xtra.co.nz said: > > All the filtering and down mixing is done in the digital domain. > > Anitialiasing filters in front of the ADCs are also be required. > > What sort of bandwidth is expected? > > The usual trick with audio ADCs is to have a low cost analog filter that > does't have a sharp corner but lets everything you want through, sample at a > high rate - say 16x, run that through a digital filter with a sharp cutoff, > then decimate down to the desired sample rate. The daughterboards for the USRP N210 that allow direct access to the ADC inputs do not contain any filters. They kind of expect band limited signals at the input. Given that they used 10MHz signals from H-masers and used 100Msps, I would say that the Niquist condition does hold. One might probably increase the noise performance a little bit by using a low pass filter. Attila Kinali -- Reading can seriously damage your ignorance. -- unknown ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi Bruce, What about the BeMicroCV-A9 that Scotty Cowling has been recommending in QEX? It has a Cyclone V SoC FPGA running at 800MHz. Installments to his series have been slow coming, but I've been wondering if this could be the basis for a Timepod type of unit. Bob On Fri, 5/27/16, Bruce Griffiths wrote: Subject: Re: [time-nuts] Commercial software defined radio for clock metrology To: "Discussion of precise time and frequency measurement" Date: Friday, May 27, 2016, 10:08 PM The Red Pitaya FPGA may be a little too small.Its not clear if a single chip ADC is used.If not, the performance will suffer.Dc coupled inputs will degrade the performance somewhat compared to transformer coupled inputs. Input bandwidth would be around 40MHz or so for the Nyquist band of interest.The output bandwidth used was something like 100 kHz. Bruce On Saturday, 28 May 2016 2:01 PM, Hal Murray wrote: bruce.griffi...@xtra.co.nz said: > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. What sort of bandwidth is expected? The usual trick with audio ADCs is to have a low cost analog filter that does't have a sharp corner but lets everything you want through, sample at a high rate - say 16x, run that through a digital filter with a sharp cutoff, then decimate down to the desired sample rate. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
For anyone thinking of rolling their own: The results in the paper were achieved using an ADC pair with no input buffers. The TI ADCs with sample rates much greater than 100MHz or so use input buffer amps that drive sets of interleaved ADCs. The more complex clock conditioning and distribution circuitry may degrade the performance compared to that achieved with lower maximum sampling rate ADC pairs. Bruce On Saturday, 28 May 2016 4:01 PM, Bob Camp wrote: Hi > On May 27, 2016, at 8:17 PM, Bruce Griffiths > wrote: > > On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: >> Hi >> >> Very interesting paper, thanks for sharing !! >> >> One question: >> >> In many DMTD (and single mixer) systems, a lowpass and high pass filter are >> applied to the signal coming out of the mixer. This is done to improve the >> zero crossing detection. It also effectively reduces the “pre detection” >> bandwidth. My understanding of the setup in your paper does not do this >> sort of filtering. It simply operated directly on the downconverter signal. >> Is this correct? I may have missed something really obvious in a quick >> read of the paper….. >> >> Thanks! >> >> Bob > > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. > > A 2 (or more) receive channel SDR board would be a nice tool to use for this > provided the FPGA is large enough. So … is there an explicit high pass in the FPGA other than the dc offset elimination high pass? There is obviously a lowpass function in the decimating FIR’s and the CIC. That appears to be optimized simply for sample rate rather than for noise. Thus the same question applies to low pass as well. Bob > > Bruce > >> >>> On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) >>> wrote: >>> >>> Hello, >>> >>> A recently published paper might be of interest to the time-nuts >>> community. We studied how well an unmodified commercial software defined >>> radio (SDR) device/firmware could serve in comparing high-performance >>> oscillators and atomic clocks. Though we chose to study the USRP >>> platform, the discussion easily generalizes to many other SDRs. >>> >>> I understand that for one month, the journal allows for free electronic >>> downloads of the manuscript at: >>> http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 >>> (Review of Scientific Instruments 87, 054711 (2016)) >>> >>> Afterwards, a preprint will remain available at: >>> http://arxiv.org/abs/1605.03505 >>> >>> There are commercial instruments available with SDR architecture >>> under-the-hood, but they often cost many thousands of dollars per >>> measurement channel. In contrast, commercial general-purpose SDRs scale >>> horizontally and can cost <= $1k per channel. Unlike the classic >>> dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The >>> carrier-acceptance range is limited not by the sample clock rate but by >>> the ADC's input bandwidth (assuming one allows for aliasing), which can >>> be many times greater. This property is an important feature in >>> considering the future measurement of optical clocks, often accomplished >>> through a heterodyne beatnote (often at "practically any" frequency >>> between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At >>> typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock >>> SDR outperforms a purpose-built DMTD instrument. >>> >>> Perhaps the biggest worry about the SDR approach is that fast ADCs are in >>> general much noisier than the analog processing components in DMTD. >>> However, quantization noise is at least amenable to averaging. As you all >>> likely appreciate, what really limits high precision clock comparison is >>> instrument stability. In this regard, the SDR's digital signal processing >>> steps (frequency translation, sample rate decimation, and low-pass >>> filtering) are at least perfectly stable and can be made sufficiently >>> accurate. >>> >>> We found that in the studied units the limiting non-stationary noise >>> source was likely the aperture jitter of the ADC (the instability of the >>> delay between an idealized sample trigger and actuation of the >>> sample/hold circuitry). However, the ADC's aperture jitter appears highly >>> common-mode in chips with a second "simultaneously-sampled" input >>> channel, allowing for an order-of-magnitue improvement after >>> channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a >>> time deviation floor of ~20 fs after just 10 ms of averaging; the >>> aperture jitter specification was 150 fs. We also describe tests with >>> maser signals lasting several days. >>> >>> Best wishes, >>> Jeff Sherman, Ph.D. >>> >>> National Institute of Standards & Technology >>> Time and Frequency Division (688) >>> 325 Broadway / Boulder, CO 80
Re: [time-nuts] Commercial software defined radio for clock metrology
The first version of the Red Pitaya apparently used an LTC2145 dual input 14 bit ADC with an SNR of around 72dB (11.6 bits) or so. Various claims of 10 bits effective implies that poor layout, and/or a noisy sampling clock, and/or the analog front end degrade the performance somewhat. For this particular application a noisy sampling clock may be less of an issue as it is common to both ADC channels. The Red Pitaya FPGA has about 1/2 the number of logic cells of the FPGA used in the Ettus 210 used in the paper. The internal sampling jitter of the Ltc2145 appears to be somewhat lower than that of the TI ADC used in the ETTUS 210 SDR. Bruce On Saturday, 28 May 2016 3:08 PM, Bruce Griffiths wrote: The Red Pitaya FPGA may be a little too small.Its not clear if a single chip ADC is used.If not, the performance will suffer.Dc coupled inputs will degrade the performance somewhat compared to transformer coupled inputs. Input bandwidth would be around 40MHz or so for the Nyquist band of interest.The output bandwidth used was something like 100 kHz. Bruce On Saturday, 28 May 2016 2:01 PM, Hal Murray wrote: bruce.griffi...@xtra.co.nz said: > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. What sort of bandwidth is expected? The usual trick with audio ADCs is to have a low cost analog filter that does't have a sharp corner but lets everything you want through, sample at a high rate - say 16x, run that through a digital filter with a sharp cutoff, then decimate down to the desired sample rate. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi > On May 27, 2016, at 8:17 PM, Bruce Griffiths > wrote: > > On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: >> Hi >> >> Very interesting paper, thanks for sharing !! >> >> One question: >> >> In many DMTD (and single mixer) systems, a lowpass and high pass filter are >> applied to the signal coming out of the mixer. This is done to improve the >> zero crossing detection. It also effectively reduces the “pre detection” >> bandwidth. My understanding of the setup in your paper does not do this >> sort of filtering. It simply operated directly on the downconverter signal. >> Is this correct? I may have missed something really obvious in a quick >> read of the paper….. >> >> Thanks! >> >> Bob > > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. > > A 2 (or more) receive channel SDR board would be a nice tool to use for this > provided the FPGA is large enough. So … is there an explicit high pass in the FPGA other than the dc offset elimination high pass? There is obviously a lowpass function in the decimating FIR’s and the CIC. That appears to be optimized simply for sample rate rather than for noise. Thus the same question applies to low pass as well. Bob > > Bruce > >> >>> On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) >>> wrote: >>> >>> Hello, >>> >>> A recently published paper might be of interest to the time-nuts >>> community. We studied how well an unmodified commercial software defined >>> radio (SDR) device/firmware could serve in comparing high-performance >>> oscillators and atomic clocks. Though we chose to study the USRP >>> platform, the discussion easily generalizes to many other SDRs. >>> >>> I understand that for one month, the journal allows for free electronic >>> downloads of the manuscript at: >>> http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 >>> (Review of Scientific Instruments 87, 054711 (2016)) >>> >>> Afterwards, a preprint will remain available at: >>> http://arxiv.org/abs/1605.03505 >>> >>> There are commercial instruments available with SDR architecture >>> under-the-hood, but they often cost many thousands of dollars per >>> measurement channel. In contrast, commercial general-purpose SDRs scale >>> horizontally and can cost <= $1k per channel. Unlike the classic >>> dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The >>> carrier-acceptance range is limited not by the sample clock rate but by >>> the ADC's input bandwidth (assuming one allows for aliasing), which can >>> be many times greater. This property is an important feature in >>> considering the future measurement of optical clocks, often accomplished >>> through a heterodyne beatnote (often at "practically any" frequency >>> between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At >>> typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock >>> SDR outperforms a purpose-built DMTD instrument. >>> >>> Perhaps the biggest worry about the SDR approach is that fast ADCs are in >>> general much noisier than the analog processing components in DMTD. >>> However, quantization noise is at least amenable to averaging. As you all >>> likely appreciate, what really limits high precision clock comparison is >>> instrument stability. In this regard, the SDR's digital signal processing >>> steps (frequency translation, sample rate decimation, and low-pass >>> filtering) are at least perfectly stable and can be made sufficiently >>> accurate. >>> >>> We found that in the studied units the limiting non-stationary noise >>> source was likely the aperture jitter of the ADC (the instability of the >>> delay between an idealized sample trigger and actuation of the >>> sample/hold circuitry). However, the ADC's aperture jitter appears highly >>> common-mode in chips with a second "simultaneously-sampled" input >>> channel, allowing for an order-of-magnitue improvement after >>> channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a >>> time deviation floor of ~20 fs after just 10 ms of averaging; the >>> aperture jitter specification was 150 fs. We also describe tests with >>> maser signals lasting several days. >>> >>> Best wishes, >>> Jeff Sherman, Ph.D. >>> >>> National Institute of Standards & Technology >>> Time and Frequency Division (688) >>> 325 Broadway / Boulder, CO 80305 / 303-497-3511 >>> ___ >>> time-nuts mailing list -- time-nuts@febo.com >>> To unsubscribe, go to >>> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the >>> instructions there. >> >> ___ >> time-nuts mailing list -- time-nuts@febo.com >> To unsubscribe, go to >> https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the >> instructions there. > >
Re: [time-nuts] Commercial software defined radio for clock metrology
The following may be of interest to those playing with low-cost SDR hardware: I also have been looking at low-cost SDR hardware for T&F measurements and have made an RF phase meter based on the Red Pitaya. The performance of this was not as good as I was hoping for: the fractional frequency resolution of this is about 10E-12 at 1 second averaging time. An earlier implementation on fairly ordinary NI hardware (14 bit 100 MHz ADCs) did better than 10E-13. Part of the problem seems to be that although the RP ADC is 14 bits, the effective number of bits is really only 10, according to a study I read (ENOB for the NI ADCs is specified as 12). The RP is a bit constrained for DSP resources too - it was a struggle to squeeze in the decimation filters. Cheers Michael On Sat, May 28, 2016 at 10:17 AM, Bruce Griffiths wrote: > On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: >> Hi >> >> Very interesting paper, thanks for sharing !! >> >> One question: >> >> In many DMTD (and single mixer) systems, a lowpass and high pass filter are >> applied to the signal coming out of the mixer. This is done to improve the >> zero crossing detection. It also effectively reduces the “pre detection” >> bandwidth. My understanding of the setup in your paper does not do this >> sort of filtering. It simply operated directly on the downconverter signal. >> Is this correct? I may have missed something really obvious in a quick >> read of the paper….. >> >> Thanks! >> >> Bob > > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. > > A 2 (or more) receive channel SDR board would be a nice tool to use for this > provided the FPGA is large enough. > > Bruce > >> >> > On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) >> > wrote: >> > >> > Hello, >> > >> > A recently published paper might be of interest to the time-nuts >> > community. We studied how well an unmodified commercial software defined >> > radio (SDR) device/firmware could serve in comparing high-performance >> > oscillators and atomic clocks. Though we chose to study the USRP >> > platform, the discussion easily generalizes to many other SDRs. >> > >> > I understand that for one month, the journal allows for free electronic >> > downloads of the manuscript at: >> > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 >> > (Review of Scientific Instruments 87, 054711 (2016)) >> > >> > Afterwards, a preprint will remain available at: >> > http://arxiv.org/abs/1605.03505 >> > >> > There are commercial instruments available with SDR architecture >> > under-the-hood, but they often cost many thousands of dollars per >> > measurement channel. In contrast, commercial general-purpose SDRs scale >> > horizontally and can cost <= $1k per channel. Unlike the classic >> > dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The >> > carrier-acceptance range is limited not by the sample clock rate but by >> > the ADC's input bandwidth (assuming one allows for aliasing), which can >> > be many times greater. This property is an important feature in >> > considering the future measurement of optical clocks, often accomplished >> > through a heterodyne beatnote (often at "practically any" frequency >> > between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At >> > typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock >> > SDR outperforms a purpose-built DMTD instrument. >> > >> > Perhaps the biggest worry about the SDR approach is that fast ADCs are in >> > general much noisier than the analog processing components in DMTD. >> > However, quantization noise is at least amenable to averaging. As you all >> > likely appreciate, what really limits high precision clock comparison is >> > instrument stability. In this regard, the SDR's digital signal processing >> > steps (frequency translation, sample rate decimation, and low-pass >> > filtering) are at least perfectly stable and can be made sufficiently >> > accurate. >> > >> > We found that in the studied units the limiting non-stationary noise >> > source was likely the aperture jitter of the ADC (the instability of the >> > delay between an idealized sample trigger and actuation of the >> > sample/hold circuitry). However, the ADC's aperture jitter appears highly >> > common-mode in chips with a second "simultaneously-sampled" input >> > channel, allowing for an order-of-magnitue improvement after >> > channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a >> > time deviation floor of ~20 fs after just 10 ms of averaging; the >> > aperture jitter specification was 150 fs. We also describe tests with >> > maser signals lasting several days. >> > >> > Best wishes, >> > Jeff Sherman, Ph.D. >> > >> > National Institute of Standards & Technology >> > Time and Frequency Division (688) >> > 325 Broadway
Re: [time-nuts] Commercial software defined radio for clock metrology
The Red Pitaya FPGA may be a little too small.Its not clear if a single chip ADC is used.If not, the performance will suffer.Dc coupled inputs will degrade the performance somewhat compared to transformer coupled inputs. Input bandwidth would be around 40MHz or so for the Nyquist band of interest.The output bandwidth used was something like 100 kHz. Bruce On Saturday, 28 May 2016 2:01 PM, Hal Murray wrote: bruce.griffi...@xtra.co.nz said: > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. What sort of bandwidth is expected? The usual trick with audio ADCs is to have a low cost analog filter that does't have a sharp corner but lets everything you want through, sample at a high rate - say 16x, run that through a digital filter with a sharp cutoff, then decimate down to the desired sample rate. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
This might be a good job for the Red Pitaya q.v. Don On 2016-05-27 18:17, Bruce Griffiths wrote: On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: Hi Very interesting paper, thanks for sharing !! One question: In many DMTD (and single mixer) systems, a lowpass and high pass filter are applied to the signal coming out of the mixer. This is done to improve the zero crossing detection. It also effectively reduces the “pre detection” bandwidth. My understanding of the setup in your paper does not do this sort of filtering. It simply operated directly on the downconverter signal. Is this correct? I may have missed something really obvious in a quick read of the paper….. Thanks! Bob All the filtering and down mixing is done in the digital domain. Anitialiasing filters in front of the ADCs are also be required. A 2 (or more) receive channel SDR board would be a nice tool to use for this provided the FPGA is large enough. Bruce > On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) > wrote: > > Hello, > > A recently published paper might be of interest to the time-nuts > community. We studied how well an unmodified commercial software defined > radio (SDR) device/firmware could serve in comparing high-performance > oscillators and atomic clocks. Though we chose to study the USRP > platform, the discussion easily generalizes to many other SDRs. > > I understand that for one month, the journal allows for free electronic > downloads of the manuscript at: > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 > (Review of Scientific Instruments 87, 054711 (2016)) > > Afterwards, a preprint will remain available at: > http://arxiv.org/abs/1605.03505 > > There are commercial instruments available with SDR architecture > under-the-hood, but they often cost many thousands of dollars per > measurement channel. In contrast, commercial general-purpose SDRs scale > horizontally and can cost <= $1k per channel. Unlike the classic > dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The > carrier-acceptance range is limited not by the sample clock rate but by > the ADC's input bandwidth (assuming one allows for aliasing), which can > be many times greater. This property is an important feature in > considering the future measurement of optical clocks, often accomplished > through a heterodyne beatnote (often at "practically any" frequency > between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At > typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock > SDR outperforms a purpose-built DMTD instrument. > > Perhaps the biggest worry about the SDR approach is that fast ADCs are in > general much noisier than the analog processing components in DMTD. > However, quantization noise is at least amenable to averaging. As you all > likely appreciate, what really limits high precision clock comparison is > instrument stability. In this regard, the SDR's digital signal processing > steps (frequency translation, sample rate decimation, and low-pass > filtering) are at least perfectly stable and can be made sufficiently > accurate. > > We found that in the studied units the limiting non-stationary noise > source was likely the aperture jitter of the ADC (the instability of the > delay between an idealized sample trigger and actuation of the > sample/hold circuitry). However, the ADC's aperture jitter appears highly > common-mode in chips with a second "simultaneously-sampled" input > channel, allowing for an order-of-magnitue improvement after > channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a > time deviation floor of ~20 fs after just 10 ms of averaging; the > aperture jitter specification was 150 fs. We also describe tests with > maser signals lasting several days. > > Best wishes, > Jeff Sherman, Ph.D. > > National Institute of Standards & Technology > Time and Frequency Division (688) > 325 Broadway / Boulder, CO 80305 / 303-497-3511 > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
bruce.griffi...@xtra.co.nz said: > All the filtering and down mixing is done in the digital domain. > Anitialiasing filters in front of the ADCs are also be required. What sort of bandwidth is expected? The usual trick with audio ADCs is to have a low cost analog filter that does't have a sharp corner but lets everything you want through, sample at a high rate - say 16x, run that through a digital filter with a sharp cutoff, then decimate down to the desired sample rate. -- These are my opinions. I hate spam. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
On Thursday, May 26, 2016 06:40:26 PM Bob Camp wrote: > Hi > > Very interesting paper, thanks for sharing !! > > One question: > > In many DMTD (and single mixer) systems, a lowpass and high pass filter are > applied to the signal coming out of the mixer. This is done to improve the > zero crossing detection. It also effectively reduces the “pre detection” > bandwidth. My understanding of the setup in your paper does not do this > sort of filtering. It simply operated directly on the downconverter signal. > Is this correct? I may have missed something really obvious in a quick > read of the paper….. > > Thanks! > > Bob All the filtering and down mixing is done in the digital domain. Anitialiasing filters in front of the ADCs are also be required. A 2 (or more) receive channel SDR board would be a nice tool to use for this provided the FPGA is large enough. Bruce > > > On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) > > wrote: > > > > Hello, > > > > A recently published paper might be of interest to the time-nuts > > community. We studied how well an unmodified commercial software defined > > radio (SDR) device/firmware could serve in comparing high-performance > > oscillators and atomic clocks. Though we chose to study the USRP > > platform, the discussion easily generalizes to many other SDRs. > > > > I understand that for one month, the journal allows for free electronic > > downloads of the manuscript at: > > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 > > (Review of Scientific Instruments 87, 054711 (2016)) > > > > Afterwards, a preprint will remain available at: > > http://arxiv.org/abs/1605.03505 > > > > There are commercial instruments available with SDR architecture > > under-the-hood, but they often cost many thousands of dollars per > > measurement channel. In contrast, commercial general-purpose SDRs scale > > horizontally and can cost <= $1k per channel. Unlike the classic > > dual-mixer time-difference (DMTD) approach, SDRs are frequency agile. The > > carrier-acceptance range is limited not by the sample clock rate but by > > the ADC's input bandwidth (assuming one allows for aliasing), which can > > be many times greater. This property is an important feature in > > considering the future measurement of optical clocks, often accomplished > > through a heterodyne beatnote (often at "practically any" frequency > > between ~1 MHz to 500 MHz) with a femtosecond laser frequency comb. At > > typical microwave clock frequencies (5 MHz, 10 MHz), we show that a stock > > SDR outperforms a purpose-built DMTD instrument. > > > > Perhaps the biggest worry about the SDR approach is that fast ADCs are in > > general much noisier than the analog processing components in DMTD. > > However, quantization noise is at least amenable to averaging. As you all > > likely appreciate, what really limits high precision clock comparison is > > instrument stability. In this regard, the SDR's digital signal processing > > steps (frequency translation, sample rate decimation, and low-pass > > filtering) are at least perfectly stable and can be made sufficiently > > accurate. > > > > We found that in the studied units the limiting non-stationary noise > > source was likely the aperture jitter of the ADC (the instability of the > > delay between an idealized sample trigger and actuation of the > > sample/hold circuitry). However, the ADC's aperture jitter appears highly > > common-mode in chips with a second "simultaneously-sampled" input > > channel, allowing for an order-of-magnitue improvement after > > channel-to-channel subtraction. For example, at 5 MHz, the SDR showed a > > time deviation floor of ~20 fs after just 10 ms of averaging; the > > aperture jitter specification was 150 fs. We also describe tests with > > maser signals lasting several days. > > > > Best wishes, > > Jeff Sherman, Ph.D. > > > > National Institute of Standards & Technology > > Time and Frequency Division (688) > > 325 Broadway / Boulder, CO 80305 / 303-497-3511 > > ___ > > time-nuts mailing list -- time-nuts@febo.com > > To unsubscribe, go to > > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > > instructions there. > > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the > instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Thx!!! André Esteves 2016-05-25 17:01 GMT+01:00 Sherman, Jeffrey A. (Fed) : > Hello, > > A recently published paper might be of interest to the time-nuts > community. We studied how well an unmodified commercial software defined > radio (SDR) device/firmware could serve in comparing high-performance > oscillators and atomic clocks. Though we chose to study the USRP platform, > the discussion easily generalizes to many other SDRs. > > I understand that for one month, the journal allows for free electronic > downloads of the manuscript at: > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 > (Review of Scientific Instruments 87, 054711 (2016)) > > Afterwards, a preprint will remain available at: > http://arxiv.org/abs/1605.03505 > > There are commercial instruments available with SDR architecture > under-the-hood, but they often cost many thousands of dollars per > measurement channel. In contrast, commercial general-purpose SDRs scale > horizontally and can cost <= $1k per channel. Unlike the classic dual-mixer > time-difference (DMTD) approach, SDRs are frequency agile. The > carrier-acceptance range is limited not by the sample clock rate but by the > ADC's input bandwidth (assuming one allows for aliasing), which can be many > times greater. This property is an important feature in considering the > future measurement of optical clocks, often accomplished through a > heterodyne beatnote (often at "practically any" frequency between ~1 MHz to > 500 MHz) with a femtosecond laser frequency comb. At typical microwave > clock frequencies (5 MHz, 10 MHz), we show that a stock SDR outperforms a > purpose-built DMTD instrument. > > Perhaps the biggest worry about the SDR approach is that fast ADCs are in > general much noisier than the analog processing components in DMTD. > However, quantization noise is at least amenable to averaging. As you all > likely appreciate, what really limits high precision clock comparison is > instrument stability. In this regard, the SDR's digital signal processing > steps (frequency translation, sample rate decimation, and low-pass > filtering) are at least perfectly stable and can be made sufficiently > accurate. > > We found that in the studied units the limiting non-stationary noise > source was likely the aperture jitter of the ADC (the instability of the > delay between an idealized sample trigger and actuation of the sample/hold > circuitry). However, the ADC's aperture jitter appears highly common-mode > in chips with a second "simultaneously-sampled" input channel, allowing for > an order-of-magnitue improvement after channel-to-channel subtraction. For > example, at 5 MHz, the SDR showed a time deviation floor of ~20 fs after > just 10 ms of averaging; the aperture jitter specification was 150 fs. We > also describe tests with maser signals lasting several days. > > Best wishes, > Jeff Sherman, Ph.D. > > National Institute of Standards & Technology > Time and Frequency Division (688) > 325 Broadway / Boulder, CO 80305 / 303-497-3511 > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Hi Very interesting paper, thanks for sharing !! One question: In many DMTD (and single mixer) systems, a lowpass and high pass filter are applied to the signal coming out of the mixer. This is done to improve the zero crossing detection. It also effectively reduces the “pre detection” bandwidth. My understanding of the setup in your paper does not do this sort of filtering. It simply operated directly on the downconverter signal. Is this correct? I may have missed something really obvious in a quick read of the paper….. Thanks! Bob > On May 25, 2016, at 12:01 PM, Sherman, Jeffrey A. (Fed) > wrote: > > Hello, > > A recently published paper might be of interest to the time-nuts community. > We studied how well an unmodified commercial software defined radio (SDR) > device/firmware could serve in comparing high-performance oscillators and > atomic clocks. Though we chose to study the USRP platform, the discussion > easily generalizes to many other SDRs. > > I understand that for one month, the journal allows for free electronic > downloads of the manuscript at: > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 > (Review of Scientific Instruments 87, 054711 (2016)) > > Afterwards, a preprint will remain available at: > http://arxiv.org/abs/1605.03505 > > There are commercial instruments available with SDR architecture > under-the-hood, but they often cost many thousands of dollars per measurement > channel. In contrast, commercial general-purpose SDRs scale horizontally and > can cost <= $1k per channel. Unlike the classic dual-mixer time-difference > (DMTD) approach, SDRs are frequency agile. The carrier-acceptance range is > limited not by the sample clock rate but by the ADC's input bandwidth > (assuming one allows for aliasing), which can be many times greater. This > property is an important feature in considering the future measurement of > optical clocks, often accomplished through a heterodyne beatnote (often at > "practically any" frequency between ~1 MHz to 500 MHz) with a femtosecond > laser frequency comb. At typical microwave clock frequencies (5 MHz, 10 MHz), > we show that a stock SDR outperforms a purpose-built DMTD instrument. > > Perhaps the biggest worry about the SDR approach is that fast ADCs are in > general much noisier than the analog processing components in DMTD. However, > quantization noise is at least amenable to averaging. As you all likely > appreciate, what really limits high precision clock comparison is instrument > stability. In this regard, the SDR's digital signal processing steps > (frequency translation, sample rate decimation, and low-pass filtering) are > at least perfectly stable and can be made sufficiently accurate. > > We found that in the studied units the limiting non-stationary noise source > was likely the aperture jitter of the ADC (the instability of the delay > between an idealized sample trigger and actuation of the sample/hold > circuitry). However, the ADC's aperture jitter appears highly common-mode in > chips with a second "simultaneously-sampled" input channel, allowing for an > order-of-magnitue improvement after channel-to-channel subtraction. For > example, at 5 MHz, the SDR showed a time deviation floor of ~20 fs after just > 10 ms of averaging; the aperture jitter specification was 150 fs. We also > describe tests with maser signals lasting several days. > > Best wishes, > Jeff Sherman, Ph.D. > > National Institute of Standards & Technology > Time and Frequency Division (688) > 325 Broadway / Boulder, CO 80305 / 303-497-3511 > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
Re: [time-nuts] Commercial software defined radio for clock metrology
Jeff thanks for sharing the document with time-nuts. Others with more knowledge will comment I suspect over the next 24 hours. I did read through the document with interest and there are some alternates to a $1K sdr as you suggest. However since I have had an opportunity several times to build a analog DMDT and haven't I suspect this is even further down the road. But on time-nuts there are others that do need a DMDT solution and I look forward to reading their comments and learning. Regards Paul WB8TSL On Wed, May 25, 2016 at 12:01 PM, Sherman, Jeffrey A. (Fed) < jeff.sher...@nist.gov> wrote: > Hello, > > A recently published paper might be of interest to the time-nuts > community. We studied how well an unmodified commercial software defined > radio (SDR) device/firmware could serve in comparing high-performance > oscillators and atomic clocks. Though we chose to study the USRP platform, > the discussion easily generalizes to many other SDRs. > > I understand that for one month, the journal allows for free electronic > downloads of the manuscript at: > http://scitation.aip.org/content/aip/journal/rsi/87/5/10.1063/1.4950898 > (Review of Scientific Instruments 87, 054711 (2016)) > > Afterwards, a preprint will remain available at: > http://arxiv.org/abs/1605.03505 > > There are commercial instruments available with SDR architecture > under-the-hood, but they often cost many thousands of dollars per > measurement channel. In contrast, commercial general-purpose SDRs scale > horizontally and can cost <= $1k per channel. Unlike the classic dual-mixer > time-difference (DMTD) approach, SDRs are frequency agile. The > carrier-acceptance range is limited not by the sample clock rate but by the > ADC's input bandwidth (assuming one allows for aliasing), which can be many > times greater. This property is an important feature in considering the > future measurement of optical clocks, often accomplished through a > heterodyne beatnote (often at "practically any" frequency between ~1 MHz to > 500 MHz) with a femtosecond laser frequency comb. At typical microwave > clock frequencies (5 MHz, 10 MHz), we show that a stock SDR outperforms a > purpose-built DMTD instrument. > > Perhaps the biggest worry about the SDR approach is that fast ADCs are in > general much noisier than the analog processing components in DMTD. > However, quantization noise is at least amenable to averaging. As you all > likely appreciate, what really limits high precision clock comparison is > instrument stability. In this regard, the SDR's digital signal processing > steps (frequency translation, sample rate decimation, and low-pass > filtering) are at least perfectly stable and can be made sufficiently > accurate. > > We found that in the studied units the limiting non-stationary noise > source was likely the aperture jitter of the ADC (the instability of the > delay between an idealized sample trigger and actuation of the sample/hold > circuitry). However, the ADC's aperture jitter appears highly common-mode > in chips with a second "simultaneously-sampled" input channel, allowing for > an order-of-magnitue improvement after channel-to-channel subtraction. For > example, at 5 MHz, the SDR showed a time deviation floor of ~20 fs after > just 10 ms of averaging; the aperture jitter specification was 150 fs. We > also describe tests with maser signals lasting several days. > > Best wishes, > Jeff Sherman, Ph.D. > > National Institute of Standards & Technology > Time and Frequency Division (688) > 325 Broadway / Boulder, CO 80305 / 303-497-3511 > ___ > time-nuts mailing list -- time-nuts@febo.com > To unsubscribe, go to > https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts > and follow the instructions there. > ___ time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts and follow the instructions there.
