date:20090506

The --binary option to envcrc can be used to export the embedded env as a
binary blob so that it can be manipulated/examined/whatever externally.

Signed-off-by: Mike Frysinger vap...@gentoo.org
---
v2
- accept just --binary and have it default to 0xff padding

 tools/envcrc.c |   46 ++
 1 files changed, 42 insertions(+), 4 deletions(-)

diff --git a/tools/envcrc.c b/tools/envcrc.c
index 4334cdf..5b0f7cd 100644
--- a/tools/envcrc.c
+++ b/tools/envcrc.c
@@ -24,6 +24,7 @@
 #include stdio.h
 #include stdint.h
 #include stdlib.h
+#include string.h
 #include unistd.h
 
 #ifndef __ASSEMBLY__
@@ -77,19 +78,56 @@ extern unsigned char environment;
 int main (int argc, char **argv)
 {
 #ifdef ENV_IS_EMBEDDED
+   unsigned char pad = 0x00;
uint32_t crc;
unsigned char *envptr = environment,
*dataptr = envptr + ENV_HEADER_SIZE;
unsigned int datasize = ENV_SIZE;
+   unsigned int eoe;
+
+   if (argv[1]  !strncmp(argv[1], --binary, 8)) {
+   int ipad = 0xff;
+   if (argv[1][8] == '=')
+   sscanf(argv[1] + 9, %i, ipad);
+   pad = ipad;
+   }
+
+   if (pad) {
+   /* find the end of env */
+   for (eoe = 0; eoe  datasize - 1; ++eoe)
+   if (!dataptr[eoe]  !dataptr[eoe+1]) {
+   eoe += 2;
+   break;
+   }
+   if (eoe  datasize - 1)
+   memset(dataptr + eoe, pad, datasize - eoe);
+   }
 
crc = crc32 (0, dataptr, datasize);
 
/* Check if verbose mode is activated passing a parameter to the 
program */
if (argc  1) {
-   printf (CRC32 from offset %08X to %08X of environment = 
%08X\n,
-   (unsigned int) (dataptr - envptr),
-   (unsigned int) (dataptr - envptr) + datasize,
-   crc);
+   if (!strncmp(argv[1], --binary, 8)) {
+   int le = (argc  2 ? !strcmp(argv[2], le) : 1);
+   size_t i, start, end, step;
+   if (le) {
+   start = 0;
+   end = ENV_HEADER_SIZE;
+   step = 1;
+   } else {
+   start = ENV_HEADER_SIZE - 1;
+   end = -1;
+   step = -1;
+   }
+   for (i = start; i != end; i += step)
+   printf(%c, (crc  (0xFF  (i * 8)))  (i * 
8));
+   fwrite(dataptr, 1, datasize, stdout);
+   } else {
+   printf(CRC32 from offset %08X to %08X of environment = 
%08X\n,
+   (unsigned int) (dataptr - envptr),
+   (unsigned int) (dataptr - envptr) + datasize,
+   crc);
+   }
} else {
printf (0x%08X\n, crc);
}
-- 
1.6.2.5

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[U-Boot] [PATCH 4/5] Blackfin: bf527-ezkit: fix SPI flash env params

The BF527-EZKIT settings for storing the environment in SPI flash wasn't
using the correct sector settings for the SPI flash part that is actually
on the board.

Signed-off-by: Mike Frysinger vap...@gentoo.org
---
 include/configs/bf527-ezkit.h |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 42cb0a8..0fe5fa5 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -115,9 +115,9 @@
  */
 #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 #define CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_OFFSET  0x4000
+#define CONFIG_ENV_OFFSET  0x1
 #define CONFIG_ENV_SIZE0x2000
-#define CONFIG_ENV_SECT_SIZE   0x2000
+#define CONFIG_ENV_SECT_SIZE   0x1
 #else
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_OFFSET  0x4000
-- 
1.6.2.5

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[U-Boot] [PATCH 3/5] Blackfin: avoid get_sclk() with early serial debug

When the clock functions were changed to use cached values (and thereby
avoiding expensive math functions), early serial debug broke because the
baud programming is called before external memory is available.

Signed-off-by: Mike Frysinger vap...@gentoo.org
---
 cpu/blackfin/serial.h |   10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/cpu/blackfin/serial.h b/cpu/blackfin/serial.h
index 7b47878..6cbc564 100644
--- a/cpu/blackfin/serial.h
+++ b/cpu/blackfin/serial.h
@@ -81,11 +81,6 @@
 
 #ifndef __ASSEMBLY__
 
-/* We cannot use get_sclk() in initcode as it is defined elsewhere. */
-#ifdef BFIN_IN_INITCODE
-# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
-#endif
-
 #ifdef __ADSPBF54x__
 # define ACCESS_LATCH()
 # define ACCESS_PORT_IER()
@@ -190,6 +185,11 @@ static inline uint16_t serial_early_get_div(void)
return divisor;
 }
 
+/* We cannot use get_sclk() early on as it uses caches in external memory */
+#if defined(BFIN_IN_INITCODE) || defined(CONFIG_DEBUG_EARLY_SERIAL)
+# define get_sclk() (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT / CONFIG_SCLK_DIV)
+#endif
+
 __attribute__((always_inline))
 static inline void serial_early_set_baud(uint32_t baud)
 {
-- 
1.6.2.5

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[U-Boot] [PATCH 0/5] Blackfin fixes for 2009.06

Some random minor bug fixes found during regression testing.

Graf Yang (1):
  Blackfin: bf518f-ezbrd: reset ethernet PHY during init

Mike Frysinger (4):
  Blackfin: recurse with early serial initcode
  Blackfin: fix booting with older bootroms (no EVT1)
  Blackfin: avoid get_sclk() with early serial debug
  Blackfin: bf527-ezkit: fix SPI flash env params

 blackfin_config.mk |6 +++-
 board/bf518f-ezbrd/bf518f-ezbrd.c  |   55 ++--
 board/bf561-ezkit/u-boot.lds.S |9 -
 cpu/blackfin/cpu.c |   10 +-
 cpu/blackfin/initcode.c|4 ++-
 cpu/blackfin/serial.h  |   10 +++---
 include/asm-blackfin/blackfin-config-pre.h |8 
 include/configs/bf527-ezkit.h  |4 +-
 8 files changed, 91 insertions(+), 15 deletions(-)

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[U-Boot] [PATCH 1/5] Blackfin: recurse with early serial initcode

Make sure we recurse through serial_putc() rather than bang on the UART
transmit register directly to avoid hardware overflows when using \n.

Signed-off-by: Mike Frysinger vap...@gentoo.org
---
 cpu/blackfin/initcode.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index aba00e0..c0fe2c6 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -92,7 +92,7 @@ static inline void serial_putc(char c)
return;
 
if (c == '\n')
-   *pUART_THR = '\r';
+   serial_putc('\r');
 
*pUART_THR = c;
 
-- 
1.6.2.5

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[U-Boot] [PATCH 5/5] Blackfin: bf518f-ezbrd: reset ethernet PHY during init

From: Graf Yang graf.y...@analog.com

We don't know what state the ethernet PHY is in when starting up, so make
sure we set it to a sane state.  This fixes troubles seen when Linux boots
up, configures the PHY is a non-default state, and then the system reboots
into U-Boot which previously expected a reset state only.

Signed-off-by: Graf Yang graf.y...@analog.com
Signed-off-by: Mike Frysinger vap...@gentoo.org
---
 board/bf518f-ezbrd/bf518f-ezbrd.c |   55 ++---
 1 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c 
b/board/bf518f-ezbrd/bf518f-ezbrd.c
index 2c7961a..1761b8e 100644
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ b/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -62,18 +62,65 @@ static void board_init_enetaddr(uchar *mac_addr)
eth_setenv_enetaddr(ethaddr, mac_addr);
 }
 
+#define KSZ_MAX_HZ500
+
+#define KSZ_WRITE 0x02
+#define KSZ_READ  0x03
+
+#define KSZ_REG_STPID 0x01 /* Register 1: Chip ID1 / Start Switch */
+#define KSZ_REG_GC9   0x0b /* Register 11: Global Control 9 */
+#define KSZ_REG_P3C0  0x30 /* Register 48: Port 3 Control 0 */
+
+static int ksz8893m_transfer(struct spi_slave *slave, uchar dir, uchar reg,
+ uchar data, uchar result[3])
+{
+   unsigned char dout[3] = { dir, reg, data, };
+   return spi_xfer(slave, sizeof(dout) * 8, dout, result, SPI_XFER_BEGIN | 
SPI_XFER_END);
+}
+
+static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
+{
+   unsigned char din[3];
+   return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
+}
+
+static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+{
+   int ret = 0;
+   unsigned char din[3];
+
+   ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+   ret |= ksz8893m_reg_set(slave, reg, din[2]  mask);
+
+   return ret;
+}
+
+static int ksz8893m_reset(struct spi_slave *slave)
+{
+   int ret = 0;
+
+   /* Disable STPID mode */
+   ret |= ksz8893m_reg_clear(slave, KSZ_REG_GC9, 0x01);
+
+   /* Disable VLAN tag insert on Port3 */
+   ret |= ksz8893m_reg_clear(slave, KSZ_REG_P3C0, 0x04);
+
+   /* Start switch */
+   ret |= ksz8893m_reg_set(slave, KSZ_REG_STPID, 0x01);
+
+   return ret;
+}
+
 int board_eth_init(bd_t *bis)
 {
static bool switch_is_alive = false;
int ret;
 
if (!switch_is_alive) {
-   struct spi_slave *slave = spi_setup_slave(0, 1, 500, 
SPI_MODE_3);
+   struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, 
SPI_MODE_3);
if (slave) {
if (!spi_claim_bus(slave)) {
-   unsigned char dout[3] = { 2, 1, 1, };
-   unsigned char din[3];
-   ret = spi_xfer(slave, sizeof(dout) * 8, dout, 
din, SPI_XFER_BEGIN | SPI_XFER_END);
+   ret = ksz8893m_reset(slave);
if (!ret)
switch_is_alive = true;
spi_release_bus(slave);
-- 
1.6.2.5

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[U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped.  Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.

Signed-off-by: Mike Frysinger vap...@gentoo.org
CC: Scott Wood scottw...@freescale.com
---
v2
- update based on feedback from Scott Wood

 board/bf537-stamp/Makefile|1 -
 board/bf537-stamp/nand.c  |  100 -
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/nand_plat.c  |   53 +++
 include/configs/bf537-stamp.h |   44 +++--
 include/configs/bfin_adi_common.h |3 +
 6 files changed, 75 insertions(+), 127 deletions(-)
 delete mode 100644 board/bf537-stamp/nand.c
 create mode 100644 drivers/mtd/nand/nand_plat.c

diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index 1dbf406..6da04e3 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -32,7 +32,6 @@ LIB   = $(obj)lib$(BOARD).a
 COBJS-y:= $(BOARD).o cmd_bf537led.o
 COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
 COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
-COBJS-$(CONFIG_CMD_NAND)   += nand.o
 COBJS-$(CONFIG_POST)   += post.o post-memory.o
 
 SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
deleted file mode 100644
index 181e83d..000
--- a/board/bf537-stamp/nand.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include common.h
-#include asm/io.h
-
-#include nand.h
-
-#define CONCAT(a,b,c,d) a ## b ## c ## d
-#define PORT(a,b)  CONCAT(pPORT,a,b,)
-
-#ifndef CONFIG_NAND_GPIO_PORT
-#define CONFIG_NAND_GPIO_PORT F
-#endif
-
-/*
- * hardware specific access to control-lines
- */
-static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-   register struct nand_chip *this = mtd-priv;
-   u32 IO_ADDR_W = (u32) this-IO_ADDR_W;
-
-   if (ctrl  NAND_CTRL_CHANGE) {
-   if (ctrl  NAND_CLE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   if (ctrl  NAND_ALE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   this-IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-   }
-   this-IO_ADDR_R = this-IO_ADDR_W;
-
-   /* Drain the writebuffer */
-   SSYNC();
-
-   if (cmd != NAND_CMD_NONE)
-   writeb(cmd, this-IO_ADDR_W);
-}
-
-int bfin_device_ready(struct mtd_info *mtd)
-{
-   int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO)  BFIN_NAND_READY) ? 1 : 0;
-   SSYNC();
-   return ret;
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a ? were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-   *PORT(CONFIG_NAND_GPIO_PORT, _FER) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
-
-   nand-cmd_ctrl = bfin_hwcontrol;
-   nand-ecc.mode = NAND_ECC_SOFT;
-   nand-dev_ready = bfin_device_ready;

[U-Boot] SD Card Support

2009-05-06 Thread Raphael Amorim

Hey guys,

Is anyone working on adding SD card support to U-Boot?

Thanks in advance.

Raphael Amorim
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Re: [U-Boot] SD Card Support

On Wednesday 06 May 2009 10:06:24 Raphael Amorim wrote:
 Is anyone working on adding SD card support to U-Boot?

it already exists, so you'll need to be more specific in what you actually 
want
-mike


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[U-Boot] [PATCH 1/1] at91: Add command to control up to 3 GPIO LEDs from the console

2009-05-06 Thread Daniel Gorsulowski

This patch allows any at91 board, implementing the GPIO LED API,
to control the LEDs from the console.

led [ 1 | 2 | 3 | all ]  [ on | off ]

Adding configuration items CONFIG_AT91_LED and CONFIG_CMD_LED
enables the command.
Moreover the GPIO Pins have to be defined by CONFIG_USER1_LED ...
CONFIG_USER3_LED.
---
 common/Makefile |1 +
 common/cmd_led.c|   86 +++
 cpu/arm926ejs/at91/led.c|   79 +++
 include/asm-arm/arch-at91/led.h |   52 +++
 4 files changed, 218 insertions(+), 0 deletions(-)
 create mode 100644 common/cmd_led.c
 create mode 100644 include/asm-arm/arch-at91/led.h

diff --git a/common/Makefile b/common/Makefile
index b9f4ca7..e0f571c 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -103,6 +103,7 @@ COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
 COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
 COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
 COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
+COBJS-$(CONFIG_CMD_LED) += cmd_led.o
 COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
 COBJS-y += cmd_load.o
 COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
diff --git a/common/cmd_led.c b/common/cmd_led.c
new file mode 100644
index 000..f914d2d
--- /dev/null
+++ b/common/cmd_led.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson ulf.samuelsson at atmel.com
+ *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski daniel.gorsulow...@esd.eu
+ * esd electronic system design gmbh www.esd.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include config.h
+#include command.h
+#include asm/arch/led.h
+
+int do_led(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+   int led;
+
+   /* Validate arguments */
+   if ((argc != 3)) {
+   printf(Usage:\n%s\n, cmdtp-usage);
+   return 1;
+   }
+   if (strcmp(argv[1], 1) == 0) {
+   led = (1  0);
+   } else if (strcmp(argv[1], 2) == 0) {
+   led = (1  1);
+   } else if (strcmp(argv[1], 3) == 0) {
+   led = (1  2);
+   } else if (strcmp(argv[1], all) == 0) {
+   led = 31;
+   } else {
+   printf (Usage:\n%s\n, cmdtp-usage);
+   return 1;
+   }
+
+   if (strcmp(argv[2], off) == 0) {
+#ifdef CONFIG_USER1_LED
+   if(led  1) user1_led_off();
+#endif
+#ifdef CONFIG_USER2_LED
+   if(led  2) user2_led_off();
+#endif
+#ifdef CONFIG_USER3_LED
+   if(led  4) user3_led_off();
+#endif
+   } else if (strcmp(argv[2], on) == 0) {
+#ifdef CONFIG_USER1_LED
+   if(led  1) user1_led_on();
+#endif
+#ifdef CONFIG_USER2_LED
+   if(led  2) user2_led_on();
+#endif
+#ifdef CONFIG_USER3_LED
+   if(led  4) user3_led_on();
+#endif
+   } else {
+   printf (Usage:\n%s\n, cmdtp-usage);
+   return 1;
+   }
+   return 0;
+}
+
+U_BOOT_CMD(
+   led, 3, 1, do_led,
+   [1|2|3|all] [on|off],
+   [1|2|3|all] [on|off] sets/clears led 1,2,3
+);
diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c
index be68f59..46a74fe 100644
--- a/cpu/arm926ejs/at91/led.c
+++ b/cpu/arm926ejs/at91/led.c
@@ -3,6 +3,10 @@
  * Stelian Pop stelian@leadtechdesign.com
  * Lead Tech Design www.leadtechdesign.com
  *
+ * (C) Copyright 2009
+ * Daniel Gorsulowski daniel.gorsulow...@esd.eu
+ * esd electronic system design gmbh www.esd.eu
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -27,6 +31,81 @@
 #include asm/arch/gpio.h
 #include asm/arch/io.h
 
+#ifdef CONFIG_AT91_LED
+
+#if defined(CONFIG_AT91RM9200)
+#include asm/arch/at91rm9200.h
+#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
+#include asm/arch/at91sam9260.h
+#elif defined(CONFIG_AT91SAM9261)
+#include asm/arch/at91sam9261.h
+#elif defined(CONFIG_AT91SAM9263)
+#include asm/arch/at91sam9263.h
+#elif defined(CONFIG_AT91SAM9RL)
+#include asm/arch/at91sam9rl.h
+#elif defined(CONFIG_AT91CAP9)
+#include asm/arch/at91cap9.h
+#endif
+
+#include asm/arch/led.h
+
+void at91_led_init(void)
+{
+   /* Enable clock */
+   at91_sys_write(AT91_PMC_PCER, 1

Re: [U-Boot] Xilinx SPI driver

2009-05-06 Thread Michal Simek

Hi,
 Hi 
 
 After searching internet for a good example of using U-boot PPC405 in xilinx 
 FPGAs with only a SPI Flash, and finding nothing, I began writing my own 
 driver. I used a couple of standalone examples besides the linux driver as 
 the base point, and could finally use it. As much as I have tested the 
 system, it is working fine with a m25p64 spi flash. 
 Now I would be happy to share the driver, but haven't done such a thing 
 previously. I am not even much familiar with patch! Is there any document 
 telling the procedure?
 Besides I have developed board support for suaku V sz410 board, and a 
 simplistic driver for xilinx frame buffer core too (which is not as much 
 tested as the spi driver). Should I submit them too?
 

Adding this driver to mainline depends on style of your driver.
You should look at http://www.denx.de/wiki/U-Boot/CodingStyle and
http://www.denx.de/wiki/U-Boot/Patches

Both drivers will be useful. I can test them on Microblaze cpu.

Please write there any information about configuration - which IP you use and 
how to test it.

If you want you can send your patches directly to me and I take a look before 
you send them to
mailing list.

Regards,
Michal


 Regards
 S. M. Sajjadi
 
 
   
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Re: [U-Boot] [PATCH] OMAP3EVM: net_chip uses CS5 not CS6

2009-05-06 Thread Dirk Behme

Matthias Ludwig wrote:
 Signed-off-by: Matthias Ludwig mlud...@ultratronik.de

Matthias: Thanks for fixing this!

Mani: Can we get your ack as EVM maintainer?

Many thanks and best regards

Dirk

 ---
  board/omap3/evm/evm.c|   16 
  include/asm-arm/arch-omap3/cpu.h |5 +++--
  2 files changed, 11 insertions(+), 10 deletions(-)
 
 diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c
 index c008c2e..5fd5efa 100644
 --- a/board/omap3/evm/evm.c
 +++ b/board/omap3/evm/evm.c
 @@ -92,17 +92,17 @@ void set_muxconf_regs(void)
  static void setup_net_chip(void)
  {
   gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
 - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
 + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
   ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
  
   /* Configure GPMC registers */
 - writel(NET_GPMC_CONFIG1, gpmc_cs6_base-config1);
 - writel(NET_GPMC_CONFIG2, gpmc_cs6_base-config2);
 - writel(NET_GPMC_CONFIG3, gpmc_cs6_base-config3);
 - writel(NET_GPMC_CONFIG4, gpmc_cs6_base-config4);
 - writel(NET_GPMC_CONFIG5, gpmc_cs6_base-config5);
 - writel(NET_GPMC_CONFIG6, gpmc_cs6_base-config6);
 - writel(NET_GPMC_CONFIG7, gpmc_cs6_base-config7);
 + writel(NET_GPMC_CONFIG1, gpmc_cs5_base-config1);
 + writel(NET_GPMC_CONFIG2, gpmc_cs5_base-config2);
 + writel(NET_GPMC_CONFIG3, gpmc_cs5_base-config3);
 + writel(NET_GPMC_CONFIG4, gpmc_cs5_base-config4);
 + writel(NET_GPMC_CONFIG5, gpmc_cs5_base-config5);
 + writel(NET_GPMC_CONFIG6, gpmc_cs5_base-config6);
 + writel(NET_GPMC_CONFIG7, gpmc_cs5_base-config7);
  
   /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
   writew(readw(ctrl_base -gpmc_nwe) | 0x0E00, ctrl_base-gpmc_nwe);
 diff --git a/include/asm-arm/arch-omap3/cpu.h 
 b/include/asm-arm/arch-omap3/cpu.h
 index c544e0c..a4ce45a 100644
 --- a/include/asm-arm/arch-omap3/cpu.h
 +++ b/include/asm-arm/arch-omap3/cpu.h
 @@ -84,9 +84,10 @@ typedef struct ctrl_id {
  /* GPMC CS3/cs4/cs6 not avaliable */
  #define GPMC_BASE(OMAP34XX_GPMC_BASE)
  #define GPMC_CONFIG_CS0  0x60
 -#define GPMC_CONFIG_CS6  0x150
 +#define GPMC_CONFIG_CS5  0x150
 +
  #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
 -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6)
 +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
  #define GPMC_CONFIG_WP   0x10
  
  #define GPMC_CONFIG_WIDTH0x30

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Re: [U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

On Wednesday 06 May 2009 13:35:29 Scott Wood wrote:
 On Wed, May 06, 2009 at 09:05:21AM -0400, Mike Frysinger wrote:
  + *  NAND_PLAT_WRITE_CMD(cmd, chip)
  + *  NAND_PLAT_WRITE_ADR(cmd, chip)

 It seems counterintuitive to have cmd before this -- it's backwards
 from both cmd_ctrl and the blackfin command that you turn it into (yes,
 it's like writeb() -- but I always found that to be weird too).

np

  +/* #define CONFIG_NAND_PLAT */

 Why is this commented out?

because it's a driver for an optional add-on card that people usually dont 
have, let alone plugged in

  +#define NAND_PLAT_DEV_READY(chip)  ((*pPORTFIO  BFIN_NAND_READY) ?
  1 : 0)

 Why not just (*pPORTFIO  BFIN_NAND_READY)?

i thought the nand/mtd layers expect 1/0 only ?  if the higher layers dont 
care, then there's no reason.
-mike


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Re: [U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

2009-05-06 Thread Scott Wood

Mike Frysinger wrote:
 +/* #define CONFIG_NAND_PLAT */
 Why is this commented out?
 
 because it's a driver for an optional add-on card that people usually dont 
 have, let alone plugged in

OK, was hoping there would be at least one config that selects it so it 
gets compilation exposure.

 +#define NAND_PLAT_DEV_READY(chip)  ((*pPORTFIO  BFIN_NAND_READY) ?
 1 : 0)
 Why not just (*pPORTFIO  BFIN_NAND_READY)?
 
 i thought the nand/mtd layers expect 1/0 only ?  if the higher layers dont 
 care, then there's no reason.

A quick grep doesn't show any non-boolean uses.

-Scott
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[U-Boot] MII register display

2009-05-06 Thread Jon Smirl

Why is speed selection = 10 Mbps when both sides support 100Mb?
Is uboot decoding this register correctly?

uboot mii dump 0 0
0. (1000) -- PHY control register --
  (8000:) 0.15= 0reset
  (4000:) 0.14= 0loopback
  (2040:) 0. 6,13 =   b00speed selection = 10 Mbps
  (1000:1000) 0.12= 1A/N enable
  (0800:) 0.11= 0power-down
  (0400:) 0.10= 0isolate
  (0200:) 0. 9= 0restart A/N
  (0100:) 0. 8= 0duplex = half
  (0080:) 0. 7= 0collision test enable
  (003f:) 0. 5- 0 = 0(reserved)

Definition from Linux:

/* Basic mode control register. */
#define BMCR_RESV   0x003f  /* Unused...   */
#define BMCR_SPEED1000  0x0040  /* MSB of Speed (1000) */
#define BMCR_CTST   0x0080  /* Collision test  */
#define BMCR_FULLDPLX   0x0100  /* Full duplex */
#define BMCR_ANRESTART  0x0200  /* Auto negotiation restart*/
#define BMCR_ISOLATE0x0400  /* Disconnect DP83840 from MII */
#define BMCR_PDOWN  0x0800  /* Powerdown the DP83840   */
#define BMCR_ANENABLE   0x1000  /* Enable auto negotiation */
#define BMCR_SPEED100   0x2000  /* Select 100Mbps  */
#define BMCR_LOOPBACK   0x4000  /* TXD loopback bits   */
#define BMCR_RESET  0x8000  /* Reset the DP83840   */




uboot mii dump 0 1
1. (786d) -- PHY status register --
  (8000:) 1.15= 0100BASE-T4 able
  (4000:4000) 1.14= 1100BASE-X  full duplex able
  (2000:2000) 1.13= 1100BASE-X  half duplex able
  (1000:1000) 1.12= 110 Mbpsfull duplex able
  (0800:0800) 1.11= 110 Mbpshalf duplex able
  (0400:) 1.10= 0100BASE-T2 full duplex able
  (0200:) 1. 9= 0100BASE-T2 half duplex able
  (0100:) 1. 8= 0extended status
  (0080:) 1. 7= 0(reserved)
  (0040:0040) 1. 6= 1MF preamble suppression
  (0020:0020) 1. 5= 1A/N complete
  (0010:) 1. 4= 0remote fault
  (0008:0008) 1. 3= 1A/N able
  (0004:0004) 1. 2= 1link status
  (0002:) 1. 1= 0jabber detect
  (0001:0001) 1. 0= 1extended capabilities


uboot mii dump 0 2
2. (0022) -- PHY ID 1 register --
  (:0022) 2.15- 0 =34OUI portion


uboot mii dump 0 3
3. (161a) -- PHY ID 2 register --
  (fc00:1400) 3.15-10 = 5OUI portion
  (03f0:0210) 3. 9- 4 =33manufacturer part number
  (000f:000a) 3. 3- 0 =10manufacturer rev. number


uboot mii dump 0 4
4. (01e1) -- Autonegotiation advertisement register --
  (8000:) 4.15= 0next page able
  (4000:) 4.14= 0reserved
  (2000:) 4.13= 0remote fault
  (1000:) 4.12= 0reserved
  (0800:) 4.11= 0asymmetric pause
  (0400:) 4.10= 0pause enable
  (0200:) 4. 9= 0100BASE-T4 able
  (0100:0100) 4. 8= 1100BASE-TX full duplex able
  (0080:0080) 4. 7= 1100BASE-TX able
  (0040:0040) 4. 6= 110BASE-T   full duplex able
  (0020:0020) 4. 5= 110BASE-T   able
  (001f:0001) 4. 4- 0 = 1selector = IEEE 802.3


uboot mii dump 0 5
5. (c5e1) -- Autonegotiation partner abilities register --
  (8000:8000) 5.15= 1next page able
  (4000:4000) 5.14= 1acknowledge
  (2000:) 5.13= 0remote fault
  (1000:) 5.12= 0(reserved)
  (0800:) 5.11= 0asymmetric pause able
  (0400:0400) 5.10= 1pause able
  (0200:) 5. 9= 0100BASE-T4 able
  (0100:0100) 5. 8= 1100BASE-X full duplex able
  (0080:0080) 5. 7= 1100BASE-TX able
  (0040:0040) 5. 6= 110BASE-T full duplex able
  (0020:0020) 5. 5= 110BASE-T able
  (001f:0001) 5. 4- 0 = 1selector = IEEE 802.3


uboot


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[U-Boot] AMCC 405EX Register Definitions

2009-05-06 Thread Jonathan Haws

It is my understanding that the 405EX CPU is not Book-E, however in 
include/asm-ppc/processor.h line 390, Book-E definitions are used for the 
405EX.  Is this correct?

I am still trying to debug the cause of the AMCC 405EX Trap (see that thread 
for more info) and found this.  I was trying to see if SRR2 is being displayed 
in the register dump when I get the machine check on my board.

From what I can tell, the 405EX does not have a CSRR0/1, but the SRR2/3 
registers have the same functionality.  Elsewhere in the code, that is noted 
and csrr0/1 are defined.  Yet, the exception code that is executed, utilizes 
the Book-E definitions in processor.h.

Again I ask, is this correct?  It would seem like there should be a compiler 
directive that determines which definitions to use and define SPRN_CSRR0 to 
SRR2 and SPRN_CSRR1 to SRR3 and so on for the 34 Book-E definitions defined.

Am I correct in my thinking or am I way off?  Either way, please let me know.  
If this is a bug, it should be easily fixed.

Thanks!

Jonathan



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(435)797-4629


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Re: [U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

On Wednesday 06 May 2009 14:19:07 Scott Wood wrote:
 Mike Frysinger wrote:
  +/* #define CONFIG_NAND_PLAT */
 
  Why is this commented out?
 
  because it's a driver for an optional add-on card that people usually
  dont have, let alone plugged in

 OK, was hoping there would be at least one config that selects it so it
 gets compilation exposure.

i have another board that does rely on it that i'll be merging in the next 
cycle

  +#define NAND_PLAT_DEV_READY(chip)  ((*pPORTFIO  BFIN_NAND_READY)
  ? 1 : 0)
 
  Why not just (*pPORTFIO  BFIN_NAND_READY)?
 
  i thought the nand/mtd layers expect 1/0 only ?  if the higher layers
  dont care, then there's no reason.

 A quick grep doesn't show any non-boolean uses.

sounds good, i'll make the change then
-mike
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[U-Boot] [PATCH 10/10] imx27lite: add support for imx27lite board from LogicPD

This patch adds support for i.MX27-LITEKIT development board from
LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
flash, FEC ethernet controller integrated into i.MX27.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 MAKEALL |1 +
 Makefile|3 +
 board/logicpd/imx27lite/Makefile|   51 +++
 board/logicpd/imx27lite/config.mk   |1 +
 board/logicpd/imx27lite/imx27lite.c |   97 +
 board/logicpd/imx27lite/lowlevel_init.S |  225 +++
 board/logicpd/imx27lite/u-boot.lds  |   56 
 include/configs/imx27lite.h |  188 ++
 8 files changed, 622 insertions(+), 0 deletions(-)
 create mode 100644 board/logicpd/imx27lite/Makefile
 create mode 100644 board/logicpd/imx27lite/config.mk
 create mode 100644 board/logicpd/imx27lite/imx27lite.c
 create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
 create mode 100644 board/logicpd/imx27lite/u-boot.lds
 create mode 100644 include/configs/imx27lite.h

diff --git a/MAKEALL b/MAKEALL
index f13c81a..4806512 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -504,6 +504,7 @@ LIST_ARM9= \
cp946es \
cp966   \
lpd7a400\
+   imx27lite   \
mx1ads  \
mx1fs2  \
netstar \
diff --git a/Makefile b/Makefile
index 137c88f..0c52bfa 100644
--- a/Makefile
+++ b/Makefile
@@ -2790,6 +2790,9 @@ davinci_sffsdr_config :   unconfig
 davinci_sonata_config :unconfig
@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
 
+imx27lite_config:  unconfig
+   @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27
+
 lpd7a400_config \
 lpd7a404_config:   unconfig
@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
diff --git a/board/logicpd/imx27lite/Makefile b/board/logicpd/imx27lite/Makefile
new file mode 100644
index 000..c404cef
--- /dev/null
+++ b/board/logicpd/imx27lite/Makefile
@@ -0,0 +1,51 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).a
+
+COBJS  := imx27lite.o
+SOBJS  := lowlevel_init.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(COBJS))
+SOBJS  := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+   rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+   rm -f $(LIB) core *.bak $(obj).depend
+
+#
+
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
+
diff --git a/board/logicpd/imx27lite/config.mk 
b/board/logicpd/imx27lite/config.mk
new file mode 100644
index 000..a2e7768
--- /dev/null
+++ b/board/logicpd/imx27lite/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xA7F0
diff --git a/board/logicpd/imx27lite/imx27lite.c 
b/board/logicpd/imx27lite/imx27lite.c
new file mode 100644
index 000..7c2658c
--- /dev/null
+++ b/board/logicpd/imx27lite/imx27lite.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige jora...@users.sourceforge.net
+ * Copyright (C) 2009 Ilya Yanok ya...@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330,

[U-Boot] [PATCH 03/10] fec_imx27: driver for FEC ethernet controller on i.MX27

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 drivers/net/Makefile   |1 +
 drivers/net/fec_imx27.c|  795 
 drivers/net/fec_imx27.h|  305 +
 drivers/net/imx27_miiphy.c |  125 +++
 drivers/net/imx27_miiphy.h |  157 +
 5 files changed, 1383 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/fec_imx27.c
 create mode 100644 drivers/net/fec_imx27.h
 create mode 100644 drivers/net/imx27_miiphy.c
 create mode 100644 drivers/net/imx27_miiphy.h

diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index a360a50..819e609 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
 COBJS-$(CONFIG_TULIP) += dc2114x.o
 COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 COBJS-$(CONFIG_DNET) += dnet.o
+COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o imx27_miiphy.o
 COBJS-$(CONFIG_E1000) += e1000.o
 COBJS-$(CONFIG_EEPRO100) += eepro100.o
 COBJS-$(CONFIG_ENC28J60) += enc28j60.o
diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
new file mode 100644
index 000..25299b9
--- /dev/null
+++ b/drivers/net/fec_imx27.c
@@ -0,0 +1,795 @@
+/*
+ * (C) Copyright 2008,2009 Eric Jarrige eric.jarr...@armadeus.org
+ * (C) Copyright 2008 Armadeus Systems nc
+ * (C) Copyright 2007 Pengutronix, Sascha Hauer s.ha...@pengutronix.de
+ * (C) Copyright 2007 Pengutronix, Juergen Beisert j.beis...@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/** TODO eth_register + cleanup gfec !! */
+
+
+#include common.h
+#include malloc.h
+#include net.h
+#include imx27_miiphy.h
+#include fec_imx27.h
+
+#include asm/arch/clock.h
+#include asm/arch/imx-regs.h
+#include asm/io.h
+
+#define CONFIG_PHY_ADDR0
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
+#error CONFIG_MII has to be defined!
+#endif
+
+//#define CONFIG_FEC_IMX27_DEBUG
+#ifdef CONFIG_FEC_IMX27_DEBUG
+#definePRINTF(fmt,args...) printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static int fec_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
+   uint8_t regAddr, uint16_t * retVal);
+static int fec_miiphy_write(struct miiphy_device *mdev, uint8_t phyAddr,
+   uint8_t regAddr, uint16_t data);
+
+typedef struct {
+   uint8_t data[1500]; /** actual data */
+   int length; /** actual length */
+   int used;   /** buffer in use or not */
+   uint8_t head[16];   /** MAC header(6 + 6 + 2) + 2(aligned) */
+} NBUF;
+
+fec_priv gfec=
+{
+   .eth   = (ethernet_regs *)IMX_FEC_BASE,
+   .xcv_type  = MII100,
+   .rbd_base  = NULL,
+   .rbd_index = 0,
+   .tbd_base  = NULL,
+   .tbd_index = 0,
+   .miiphy =
+   {
+   CONFIG_PHY_ADDR,
+   fec_miiphy_read,
+   fec_miiphy_write,
+   0,
+   NULL
+   },
+   .bd= NULL,
+};
+
+/*
+ * MII-interface related functions
+ */
+static int fec_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
+   uint8_t regAddr, uint16_t * retVal)
+{
+   struct eth_device *edev = mdev-edev;
+   fec_priv *fec = (fec_priv *)edev-priv;
+
+   uint32_t reg;   /* convenient holder for the PHY register */
+   uint32_t phy;   /* convenient holder for the PHY */
+   uint32_t start;
+
+   /*
+* reading from any PHY's register is done by properly
+* programming the FEC's MII data register.
+*/
+   writel(FEC_IEVENT_MII, fec-eth-ievent);
+   reg = regAddr  FEC_MII_DATA_RA_SHIFT;
+   phy = phyAddr  FEC_MII_DATA_PA_SHIFT;
+
+   writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | 
reg, fec-eth-mii_data);
+
+   /*
+* wait for the related interrupt
+*/
+   start = get_timer_masked(); /* get_time_ns(); */
+   while (!(readl(fec-eth-ievent)  FEC_IEVENT_MII)) {
+   if (get_timer (start)  (CONFIG_SYS_HZ /1000)  /* 
is_timeout(start, MSECOND)*/) {
+   printf(Read MDIO failed...\n);
+   return -1;
+   }
+   }
+
+   /*
+

[U-Boot] [PATCH 06/10] arm: add support for CONFIG_GENERIC_MMC

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 lib_arm/board.c |7 +++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index 5d05d9b..86635bd 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -48,6 +48,7 @@
 #include serial.h
 #include nand.h
 #include onenand_uboot.h
+#include mmc.h
 
 #ifdef CONFIG_DRIVER_SMC9
 #include ../drivers/net/smc9.h
@@ -439,6 +440,12 @@ extern void davinci_eth_set_mac_addr (const u_int8_t 
*addr);
 #ifdef BOARD_LATE_INIT
board_late_init ();
 #endif
+
+#ifdef CONFIG_GENERIC_MMC
+   puts (MMC:  );
+   mmc_initialize (gd-bd);
+#endif
+
 #if defined(CONFIG_CMD_NET)
 #if defined(CONFIG_NET_MULTI)
puts (Net:   );
-- 
1.6.0.6

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[U-Boot] [PATCH 02/10] serial_mx31: allow it to work with mx27 too

UART hardware on i.MX27 is the same as on the i.MX31 so we just
need to provide the driver with correct address of the registers.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 drivers/serial/serial_mx31.c |   21 +
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/serial_mx31.c b/drivers/serial/serial_mx31.c
index 7c0682a..acc5b7d 100644
--- a/drivers/serial/serial_mx31.c
+++ b/drivers/serial/serial_mx31.c
@@ -18,7 +18,12 @@
  */
 
 #include common.h
+#ifdef CONFIG_MX31
 #include asm/arch/mx31.h
+#else
+#include asm/arch/imx-regs.h
+#include asm/arch/clock.h
+#endif
 
 #define __REG(x) (*((volatile u32 *)(x)))
 
@@ -32,6 +37,18 @@
 #define UART_PHYS 0x43fb
 #elif defined(CONFIG_SYS_MX31_UART5)
 #define UART_PHYS 0x43fb4000
+#elif defined(CONFIG_SYS_MX27_UART1)
+#define UART_PHYS 0x1000a000
+#elif defined(CONFIG_SYS_MX27_UART2)
+#define UART_PHYS 0x1000b000
+#elif defined(CONFIG_SYS_MX27_UART3)
+#define UART_PHYS 0x1000c000
+#elif defined(CONFIG_SYS_MX27_UART4)
+#define UART_PHYS 0x1000d000
+#elif defined(CONFIG_SYS_MX27_UART5)
+#define UART_PHYS 0x1001b000
+#elif defined(CONFIG_SYS_MX27_UART6)
+#define UART_PHYS 0x1001c000
 #else
 #error define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver
 #endif
@@ -149,7 +166,11 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void serial_setbrg (void)
 {
+#ifdef CONFIG_MX31
u32 clk = mx31_get_ipg_clk();
+#else
+   u32 clk = imx_get_perclk1();
+#endif
 
if (!gd-baudrate)
gd-baudrate = CONFIG_BAUDRATE;
-- 
1.6.0.6

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[U-Boot] [PATCH 04/10] mxc_nand: add nand driver for MX2/MX3

Driver for NFC NAND controller found on Freescale's MX2 and MX3
processors. Ported from Linux. Tested only with i.MX27 but should
works with other MX2 and MX3 processors too.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 drivers/mtd/nand/Makefile   |1 +
 drivers/mtd/nand/mxc_nand.c |  891 +++
 2 files changed, 892 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mtd/nand/mxc_nand.c

diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 471cd6b..24de947 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
+COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
 COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
 COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
 COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
new file mode 100644
index 000..48a6b7b
--- /dev/null
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -0,0 +1,891 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, ker...@pengutronix.de
+ * Copyright 2009 Ilya Yanok, ya...@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include common.h
+#include nand.h
+#include linux/err.h
+#include asm/io.h
+#ifdef CONFIG_MX27
+#include asm/arch/imx-regs.h
+#endif
+
+#define DRIVER_NAME mxc_nand
+
+/* Addresses for NFC registers */
+#define NFC_BUF_SIZE   0xE00
+#define NFC_BUF_ADDR   0xE04
+#define NFC_FLASH_ADDR 0xE06
+#define NFC_FLASH_CMD  0xE08
+#define NFC_CONFIG 0xE0A
+#define NFC_ECC_STATUS_RESULT  0xE0C
+#define NFC_RSLTMAIN_AREA  0xE0E
+#define NFC_RSLTSPARE_AREA 0xE10
+#define NFC_WRPROT 0xE12
+#define NFC_UNLOCKSTART_BLKADDR0xE14
+#define NFC_UNLOCKEND_BLKADDR  0xE16
+#define NFC_NF_WRPRST  0xE18
+#define NFC_CONFIG10xE1A
+#define NFC_CONFIG20xE1C
+
+/* Addresses for NFC RAM BUFFER Main area 0 */
+#define MAIN_AREA0 0x000
+#define MAIN_AREA1 0x200
+#define MAIN_AREA2 0x400
+#define MAIN_AREA3 0x600
+
+/* Addresses for NFC SPARE BUFFER Spare area 0 */
+#define SPARE_AREA00x800
+#define SPARE_AREA10x810
+#define SPARE_AREA20x820
+#define SPARE_AREA30x830
+
+/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Command operation */
+#define NFC_CMD0x1
+
+/* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Address operation */
+#define NFC_ADDR   0x2
+
+/* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
+ * for Input operation */
+#define NFC_INPUT  0x4
+
+/* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
+ * for Data Output operation */
+#define NFC_OUTPUT 0x8
+
+/* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
+ * for Read ID operation */
+#define NFC_ID 0x10
+
+/* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
+ * for Read Status operation */
+#define NFC_STATUS 0x20
+
+/* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
+ * Status operation */
+#define NFC_INT0x8000
+
+#define NFC_SP_EN   (1  2)
+#define NFC_ECC_EN  (1  3)
+#define NFC_INT_MSK (1  4)
+#define NFC_BIG (1  5)
+#define NFC_RST (1  6)
+#define NFC_CE  (1  7)
+#define NFC_ONE_CYCLE   (1  8)
+
+typedef enum _bool{false,true} bool;
+
+struct mxc_nand_host {
+   struct mtd_info mtd;
+   struct nand_chip*nand;
+
+   void __iomem*regs;
+   int spare_only;
+   int status_request;
+   int pagesize_2k;
+   int clk_act;
+   uint16_tcol_addr;
+};
+
+static struct mxc_nand_host mxc_host;
+static struct mxc_nand_host *host = mxc_host;
+
+/* Define delays in microsec for NAND device operations */
+#define TROP_US_DELAY   2000
+/* Macros to get byte and

[U-Boot] [PATCH 00/10] Support for LogicPD i.MX27-LITEKIT development board

This patch set adds support for LogicPD i.MX27-LITEKIT development board.
It contains support for i.MX27 CPU, support for serial console, FEC
ethernet controller, NFC NAND controller and SDHC controller. It also
contains some fixes to generic MMC subsystem.

Signed-off-by: Ilya Yanok ya...@emcraft.com

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[U-Boot] [PATCH 01/10] mx27: basic cpu support

This patch adds generic code to support Freescale's i.MX27 SoCs.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 cpu/arm926ejs/mx27/Makefile  |   44 +++
 cpu/arm926ejs/mx27/generic.c |  205 ++
 cpu/arm926ejs/mx27/interrupt.c   |  201 ++
 include/asm-arm/arch-mx27/clock.h|   17 ++
 include/asm-arm/arch-mx27/imx-regs.h |  504 ++
 5 files changed, 971 insertions(+), 0 deletions(-)
 create mode 100644 cpu/arm926ejs/mx27/Makefile
 create mode 100644 cpu/arm926ejs/mx27/generic.c
 create mode 100644 cpu/arm926ejs/mx27/interrupt.c
 create mode 100644 include/asm-arm/arch-mx27/clock.h
 create mode 100644 include/asm-arm/arch-mx27/imx-regs.h

diff --git a/cpu/arm926ejs/mx27/Makefile b/cpu/arm926ejs/mx27/Makefile
new file mode 100644
index 000..c86f3c2
--- /dev/null
+++ b/cpu/arm926ejs/mx27/Makefile
@@ -0,0 +1,44 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).a
+
+COBJS  = interrupt.o generic.o
+
+SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+all:   $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+   $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
new file mode 100644
index 000..fdbc8b7
--- /dev/null
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -0,0 +1,205 @@
+/*
+ *  Copyright (c) 2008 Eric Jarrige eric.jarr...@armadeus.org
+ *  Copyright (c) 2009 Ilya Yanok ya...@emcraft.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include div64.h
+#include asm/arch/imx-regs.h
+/*
+ *  get the system pll clock in Hz
+ *
+ *  mfi + mfn / (mfd +1)
+ *  f = 2 * f_ref * 
+ *pd + 1
+ */
+unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
+{
+   unsigned int mfi = (pll  10)  0xf;
+   unsigned int mfn = pll  0x3ff;
+   unsigned int mfd = (pll  16)  0x3ff;
+   unsigned int pd =  (pll  26)  0xf;
+
+   mfi = mfi = 5 ? 5 : mfi;
+
+   return lldiv((2*(u64)f_ref* (mfi*(mfd+1) + mfn)), ((mfd+1)*(pd+1)));
+}
+
+static ulong clk_in_32k(void)
+{
+   return 1024 * CONFIG_MX31_CLK32;
+}
+
+static ulong clk_in_26m(void)
+{
+   if (CSCR  CSCR_OSC26M_DIV1P5) {
+   /* divide by 1.5 */
+   return 2600 / 1.5;
+   } else {
+   /* divide by 1 */
+   return 2600;
+   }
+}
+
+ulong imx_get_mpllclk(void)
+{
+   ulong cscr = CSCR;
+   ulong fref;
+
+   if (cscr  CSCR_MCU_SEL)
+   fref = clk_in_26m();
+   else
+   fref = clk_in_32k();
+
+   return imx_decode_pll(MPCTL0, fref);
+}
+
+ulong imx_get_armclk(void)
+{
+   ulong cscr = CSCR;
+   ulong fref = imx_get_mpllclk();
+   ulong div;
+
+   if (!(cscr  CSCR_ARM_SRC_MPLL))
+   fref = lldiv((fref * 2), 3);
+
+   div = ((cscr  12)  0x3) + 1;
+
+   return lldiv(fref, div);
+}
+
+ulong imx_get_ahbclk(void)
+{
+   ulong cscr = CSCR;
+   ulong fref = imx_get_mpllclk();
+   ulong div;
+
+   div = ((cscr  8)  0x3) + 1;
+
+   return lldiv(fref * 2, 3

[U-Boot] [PATCH 05/10] mxc-mmc: sdhc host driver for MX2 and MX3 proccessor

This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 cpu/arm926ejs/mx27/generic.c   |   16 ++
 drivers/mmc/Makefile   |1 +
 drivers/mmc/mxcmmc.c   |  520 
 include/asm-arm/arch-mx27/mxcmmc.h |   25 ++
 4 files changed, 562 insertions(+), 0 deletions(-)
 create mode 100644 drivers/mmc/mxcmmc.c
 create mode 100644 include/asm-arm/arch-mx27/mxcmmc.h

diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index fdbc8b7..a0be35b 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -21,6 +21,9 @@
 #include common.h
 #include div64.h
 #include asm/arch/imx-regs.h
+#ifdef CONFIG_MXC_MMC
+#include asm/arch/mxcmmc.h
+#endif
 /*
  *  get the system pll clock in Hz
  *
@@ -143,6 +146,19 @@ int print_cpuinfo (void)
 }
 #endif
 
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+   return mxc_mmc_init(bis);
+#else
+   return 0;
+#endif
+}
+
 void imx_gpio_mode(int gpio_mode)
 {
unsigned int pin = gpio_mode  GPIO_PIN_MASK;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1b0af12..6fa04b8 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
 COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
 COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
 COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
 COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
 
 COBJS  := $(COBJS-y)
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
new file mode 100644
index 000..9635d6e
--- /dev/null
+++ b/drivers/mmc/mxcmmc.c
@@ -0,0 +1,520 @@
+/*
+ *  This is a driver for the SDHC controller found in Freescale MX2/MX3
+ *  SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
+ *  Unlike the hardware found on MX1, this hardware just works and does
+ *  not need all the quirks found in imxmmc.c, hence the seperate driver.
+ *
+ *  Copyright (C) 2009 Ilya Yanok, ya...@emcraft.com
+ *  Copyright (C) 2008 Sascha Hauer, Pengutronix s.ha...@pengutronix.de
+ *  Copyright (C) 2006 Pavel Pisa, PiKRON pp...@pikron.com
+ *
+ *  derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include config.h
+#include common.h
+#include command.h
+#include mmc.h
+#include part.h
+#include malloc.h
+#include mmc.h
+#include asm/errno.h
+#include asm/io.h
+#ifdef CONFIG_MX27
+#include asm/arch/clock.h
+#endif
+
+#define DRIVER_NAME mxc-mmc
+
+#define MMC_REG_STR_STP_CLK0x00
+#define MMC_REG_STATUS 0x04
+#define MMC_REG_CLK_RATE   0x08
+#define MMC_REG_CMD_DAT_CONT   0x0C
+#define MMC_REG_RES_TO 0x10
+#define MMC_REG_READ_TO0x14
+#define MMC_REG_BLK_LEN0x18
+#define MMC_REG_NOB0x1C
+#define MMC_REG_REV_NO 0x20
+#define MMC_REG_INT_CNTR   0x24
+#define MMC_REG_CMD0x28
+#define MMC_REG_ARG0x2C
+#define MMC_REG_RES_FIFO   0x34
+#define MMC_REG_BUFFER_ACCESS  0x38
+
+#define STR_STP_CLK_RESET   (1  3)
+#define STR_STP_CLK_START_CLK   (1  1)
+#define STR_STP_CLK_STOP_CLK(1  0)
+
+#define STATUS_CARD_INSERTION  (1  31)
+#define STATUS_CARD_REMOVAL(1  30)
+#define STATUS_YBUF_EMPTY  (1  29)
+#define STATUS_XBUF_EMPTY  (1  28)
+#define STATUS_YBUF_FULL   (1  27)
+#define STATUS_XBUF_FULL   (1  26)
+#define STATUS_BUF_UND_RUN (1  25)
+#define STATUS_BUF_OVFL(1  24)
+#define STATUS_SDIO_INT_ACTIVE (1  14)
+#define STATUS_END_CMD_RESP(1  13)
+#define STATUS_WRITE_OP_DONE   (1  12)
+#define STATUS_DATA_TRANS_DONE (1  11)
+#define STATUS_READ_OP_DONE(1  11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK  (3  10)
+#define STATUS_CARD_BUS_CLK_RUN(1  8)
+#define STATUS_BUF_READ_RDY(1  7)
+#define STATUS_BUF_WRITE_RDY   (1  6)
+#define STATUS_RESP_CRC_ERR(1  5)
+#define STATUS_CRC_READ_ERR(1  3)
+#define STATUS_CRC_WRITE_ERR   (1  2)
+#define STATUS_TIME_OUT_RESP   (1  1)
+#define STATUS_TIME_OUT_READ   (1  0)
+#define STATUS_ERR_MASK0x2f
+
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1  12)

[U-Boot] [PATCH 07/10] mmc: use lldiv() for 64-bit division

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 drivers/mmc/mmc.c |7 ---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 7791c38..77a9aea 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -31,6 +31,7 @@
 #include malloc.h
 #include linux/list.h
 #include mmc.h
+#include div64.h
 
 static struct list_head mmc_devices;
 static int cur_dev_num = -1;
@@ -155,8 +156,8 @@ int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size)
char *buffer;
int i;
int blklen = mmc-read_bl_len;
-   int startblock = src / blklen;
-   int endblock = (src + size - 1) / blklen;
+   int startblock = lldiv(src, blklen);
+   int endblock = lldiv((src + size - 1), blklen);
int err = 0;
 
/* Make a buffer big enough to hold all the blocks we might read */
@@ -789,7 +790,7 @@ int mmc_startup(struct mmc *mmc)
mmc-block_dev.lun = 0;
mmc-block_dev.type = 0;
mmc-block_dev.blksz = mmc-read_bl_len;
-   mmc-block_dev.lba = mmc-capacity/mmc-read_bl_len;
+   mmc-block_dev.lba = lldiv(mmc-capacity,mmc-read_bl_len);
sprintf(mmc-block_dev.vendor,Man %02x%02x%02x Snr %02x%02x%02x%02x,
mmc-cid[0], mmc-cid[1], mmc-cid[2],
mmc-cid[9], mmc-cid[10], mmc-cid[11], mmc-cid[12]);
-- 
1.6.0.6

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[U-Boot] [PATCH 08/10] mmc: some endianess fixes for generic mmc subsystem

We save response in the cpu order so we need to parse it in the
cpu order too. Things fixed by this patch:
1. OCR_BUSY should be the highest bit in 32-bit response.
2. Proper tran speed calculation on LE systems (tran_exp and
   tran_mant should be in 96..98 and 99..102 bits of 128-bit
   response respectively).
3. Proper MMC version detection.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 drivers/mmc/mmc.c |   10 +-
 include/mmc.h |2 +-
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 77a9aea..f7a989b 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -284,7 +284,7 @@ sd_send_op_cond(struct mmc *mmc)
return err;
 
udelay(1000);
-   } while ((!(cmd.response[0]  OCR_BUSY))  timeout--);
+   } while ((!(((uint *)cmd.response)[0]  OCR_BUSY))  timeout--);
 
if (timeout = 0)
return UNUSABLE_ERR;
@@ -321,7 +321,7 @@ int mmc_send_op_cond(struct mmc *mmc)
return err;
 
udelay(1000);
-   } while (!(cmd.response[0]  OCR_BUSY)  timeout--);
+   } while (!(((uint *)cmd.response)[0]  OCR_BUSY)  timeout--);
 
if (timeout = 0)
return UNUSABLE_ERR;
@@ -651,7 +651,7 @@ int mmc_startup(struct mmc *mmc)
mmc-csd[3] = ((uint *)(cmd.response))[3];
 
if (mmc-version == MMC_VERSION_UNKNOWN) {
-   int version = (cmd.response[0]  2)  0xf;
+   int version = (mmc-csd[0]  26)  0xf;
 
switch (version) {
case 0:
@@ -676,8 +676,8 @@ int mmc_startup(struct mmc *mmc)
}
 
/* divide frequency by 10, since the mults are 10x bigger */
-   freq = fbase[(cmd.response[3]  0x7)];
-   mult = multipliers[((cmd.response[3]  3)  0xf)];
+   freq = fbase[(mmc-csd[0]  0x7)];
+   mult = multipliers[((mmc-csd[0]  3)  0xf)];
 
mmc-tran_speed = freq * mult;
 
diff --git a/include/mmc.h b/include/mmc.h
index b9b27ba..64764cb 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -91,7 +91,7 @@
 #define MMC_HS_TIMING  0x0100
 #define MMC_HS_52MHZ   0x2
 
-#define OCR_BUSY   0x80
+#define OCR_BUSY   0x8000
 #define OCR_HCS0x4000
 
 #define MMC_VDD_165_1950x0080  /* VDD voltage 1.65 - 
1.95 */
-- 
1.6.0.6

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[U-Boot] [PATCH 09/10] mmc: fix mmcinfo command

cid field of stuct mmc stucture is char*, not u32*. so we need to
convert the pointer for mmcinfo code to work correctly.

Signed-off-by: Ilya Yanok ya...@emcraft.com
---
 common/cmd_mmc.c |   11 ++-
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c
index f1fa32f..21b7004 100644
--- a/common/cmd_mmc.c
+++ b/common/cmd_mmc.c
@@ -95,12 +95,13 @@ U_BOOT_CMD(
 
 static void print_mmcinfo(struct mmc *mmc)
 {
+   u32 *cid = mmc-cid;
printf(Device: %s\n, mmc-name);
-   printf(Manufacturer ID: %x\n, mmc-cid[0]  24);
-   printf(OEM: %x\n, (mmc-cid[0]  8)  0x);
-   printf(Name: %c%c%c%c%c \n, mmc-cid[0]  0xff,
-   (mmc-cid[1]  24), (mmc-cid[1]  16)  0xff,
-   (mmc-cid[1]  8)  0xff, mmc-cid[1]  0xff);
+   printf(Manufacturer ID: %x\n, cid[0]  24);
+   printf(OEM: %x\n, (cid[0]  8)  0x);
+   printf(Name: %c%c%c%c%c \n, cid[0]  0xff,
+   (cid[1]  24), (cid[1]  16)  0xff,
+   (cid[1]  8)  0xff, cid[1]  0xff);
 
printf(Tran Speed: %d\n, mmc-tran_speed);
printf(Rd Block Len: %d\n, mmc-read_bl_len);
-- 
1.6.0.6

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Re: [U-Boot] [PATCH V2] arm: timer and interrupt init rework

2009-05-06 Thread Dirk Behme

Wolfgang Denk wrote:
 Dear Jean-Christophe PLAGNIOL-VILLARD,
 
 In message 20090501232305.gi3...@game.jcrosoft.org you wrote:
 +COBJS += board.o
 +COBJS += clock.o
 +COBJS += mem.o
 +COBJS += syslib.o
 +COBJS += sys_info.o
 +COBJS += timer.o
 What do we win with this?
 simple to allow vertical patch to be applied instead of have merge problem

 so yes it's needed
 
 But it must go in a separate patch.
 
 diff --git a/lib_arm/board.c b/lib_arm/board.c
 index 5d05d9b..b678a63 100644
 --- a/lib_arm/board.c
 +++ b/lib_arm/board.c
 @@ -265,8 +265,11 @@ init_fnc_t *init_sequence[] = {
  #if defined(CONFIG_ARCH_CPU_INIT)
arch_cpu_init,  /* basic arch cpu dependent setup */
  #endif
 -  board_init, /* basic board dependent setup */
 +#if defined(CONFIG_USE_IRQ)
interrupt_init, /* set up exceptions */
 +#endif
 +  timer_init, /* initialize timer */
 +  board_init, /* basic board dependent setup */
env_init,   /* initialize environment */
init_baudrate,  /* initialze baudrate settings */
serial_init,/* serial communications setup */
 ... if you tested this on an OMAP3 board: I'm not sure, but it seems to 
 me that the initialization order might change by this?
 maybe read the commit message will answer your question
 
 Argh. Instead of snippy remarks you should read Dirks message yourself
 and answer his (very valid) questions:
 
 | Is this correct? If yes, we have to check that there are no issues 
 | with dependencies?
 | 
 | On which OMAP3 board have you tested this?
 
 Can you please explain on which boards this has actually been tested,
 and especially on which OMAP3 boards?
 
 
 Also, I do not see why we need to implement such a critical change.
 
 If I understand you corrctly, your argument goes that board_init()
 needs delays (like udelay()), delays need timers, and timers need
 interrupts, so we must initialize first interrupts, then timers, and
 only then we can run board_init()?  Is this your argument?
 
 But the I ask why udelay() would need  timers  and  interrupts?  This
 does  not fit into the design philosophy of U-Boot, which attempts to
 bring up a board at least to a state where  we  have  serial  console
 output  with  as  little as possible requirements. Your change breaks
 this, because now we have to initialize timers and interrupts  (which
 are  not  exactly  a  trivial thing to set up or debug if they aren't
 working correctly) BEFORE we have a console  output.  [I  ignore  the
 case  of CONFIG_USE_IRQ here, because only 4 boards actually use this
 feature, and they could probably be changed to do without, too.]
 
 So while I really appreciate your attempts to clean up the timer code
 on ARM, the resulting consequences are expensive, and I  am  not  yet
 convincet  the  advantages  of  the  new  code  are  bigger than this
 disadvantage, and especially I am not convinced  thatthis  is  really
 necessary and unavoidable.
 
 Can we not do delays without interrupts? And do  we  need  full-blown
 timer services for delays? [Keep in mind that a delay is usually used
 to  implement  a timeout in the error branch; that means, it does not
 matter if it has not 10e-6 precision or better.]

Btw, it seems that this patch is already in u-boot-arm next

http://git.denx.de/?p=u-boot/u-boot-arm.git;a=commit;h=482d69eafb6a78c82251f7a346cc67f12a9bd731

Did I miss an ACK somewhere? It's my understanding that this patch is 
still under discussion? Sorry if I missed something ;)

Best regards

Dirk
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Re: [U-Boot] Zoom2 initial support rebased to arm/next

2009-05-06 Thread Dirk Behme

Dear Tom, dear Jean-Christophe,

Dirk Behme wrote:
Dear Tom, dear Jean-Christophe,

Tom wrote:
Dirk Behme wrote:
Hi Tom,

Tom wrote:
Here is the changes to Zoom2 to rebase onto the arm/next branch

I'm not sure and and didn't test it, but it seems to me that we might
get some conflicts with patches in arm/master branch and these
against arm/next.

With Premi's patch that removes unused board-types

http://git.denx.de/?p=u-boot/u-boot-arm.git;a=commit;h=90006e9b33bcdbf241b0295d186e3634137907a9

it might conflict with your patch that still assumes the struct
elements and macros are still there (?).

Best regards

Dirk
Yes, I think so.
My rebase to arm/next was because the arm led patch that was part of
the patch set against master was pushed there.
I think the changes in the above patch are straightforward so should
be easy to fix the conflicts when the merge happens.
Can this wait till after the whole patch set is pushed to arm/next ?

Yes. But somebody should help Jean-Christophe with merge resolve then.

Now that all other OMAP3 patches are in mainline, easiest would be
something like:

1) Update u-boot-arm master and next against mainline

2) Move the three (*) patches from u-boot-arm next to u-boot-arm master
as proposed by Wolfgang [bottom of 1].

3) With (1) and (2) we have all OMAP3 patches and already applied Zoom2
patches in one git. Now we will be able to update the remaining 5 Zoom2
patches against it.

What do you think? Any easier way?

Any news regarding the Zoom2 patches? Seems to me that above (1) is
done. Are you just busy (and I'm too impatient? Sorry!) or are there
other issues delaying Zoom2 patches?

Many thanks and best regards

Dirk

[1] http://lists.denx.de/pipermail/u-boot/2009-May/051863.html

(*) Already applied Zoom2 patches at u-boot-arm next:

- ZOOM1 Remove more legacy NAND defines.
- LED Add documentation describing the status_led and colour led API.
- ARM Add blue colour LED to status_led.

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[U-Boot] [PATCH v3] mtd: nand: new base driver for memory mapped nand devices

The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped.  Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.

Signed-off-by: Mike Frysinger vap...@gentoo.org
CC: Scott Wood scottw...@freescale.com
---
v3
- re-order args to NAND_PLAT_WRITE_*
- dont bother normalizing NAND_PLAT_DEV_READY

 board/bf537-stamp/Makefile|1 -
 board/bf537-stamp/nand.c  |  100 -
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/nand_plat.c  |   53 +++
 include/configs/bf537-stamp.h |   44 +++--
 include/configs/bfin_adi_common.h |3 +
 6 files changed, 75 insertions(+), 127 deletions(-)
 delete mode 100644 board/bf537-stamp/nand.c
 create mode 100644 drivers/mtd/nand/nand_plat.c

diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index 1dbf406..6da04e3 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -32,7 +32,6 @@ LIB   = $(obj)lib$(BOARD).a
 COBJS-y:= $(BOARD).o cmd_bf537led.o
 COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
 COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
-COBJS-$(CONFIG_CMD_NAND)   += nand.o
 COBJS-$(CONFIG_POST)   += post.o post-memory.o
 
 SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
deleted file mode 100644
index 181e83d..000
--- a/board/bf537-stamp/nand.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include common.h
-#include asm/io.h
-
-#include nand.h
-
-#define CONCAT(a,b,c,d) a ## b ## c ## d
-#define PORT(a,b)  CONCAT(pPORT,a,b,)
-
-#ifndef CONFIG_NAND_GPIO_PORT
-#define CONFIG_NAND_GPIO_PORT F
-#endif
-
-/*
- * hardware specific access to control-lines
- */
-static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-   register struct nand_chip *this = mtd-priv;
-   u32 IO_ADDR_W = (u32) this-IO_ADDR_W;
-
-   if (ctrl  NAND_CTRL_CHANGE) {
-   if (ctrl  NAND_CLE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   if (ctrl  NAND_ALE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   this-IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-   }
-   this-IO_ADDR_R = this-IO_ADDR_W;
-
-   /* Drain the writebuffer */
-   SSYNC();
-
-   if (cmd != NAND_CMD_NONE)
-   writeb(cmd, this-IO_ADDR_W);
-}
-
-int bfin_device_ready(struct mtd_info *mtd)
-{
-   int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO)  BFIN_NAND_READY) ? 1 : 0;
-   SSYNC();
-   return ret;
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a ? were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-   *PORT(CONFIG_NAND_GPIO_PORT, _FER) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
-
-   nand-cmd_ctrl = bfin_hwcontrol;
-   nand-ecc.mode =

Re: [U-Boot] [PATCH v3] mtd: nand: new base driver for memory mapped nand devices

2009-05-06 Thread Scott Wood

On Wed, May 06, 2009 at 03:38:36PM -0400, Mike Frysinger wrote:
 The BF537-STAMP Blackfin board had a driver for working with NAND devices
 that are simply memory mapped.  Since there is nothing Blackfin specific
 about this, generalize the driver a bit so that everyone can leverage it.
 
 Signed-off-by: Mike Frysinger vap...@gentoo.org
 CC: Scott Wood scottw...@freescale.com

Applied to u-boot-nand-flash/next.

-Scott
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Re: [U-Boot] [PATCH 03/10] fec_imx27: driver for FEC ethernet controller on i.MX27

2009-05-06 Thread Ben Warren

Hi Ilya,

Ilya Yanok wrote:
 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  drivers/net/Makefile   |1 +
  drivers/net/fec_imx27.c|  795 
 
  drivers/net/fec_imx27.h|  305 +
  drivers/net/imx27_miiphy.c |  125 +++
  drivers/net/imx27_miiphy.h |  157 +
  5 files changed, 1383 insertions(+), 0 deletions(-)
  create mode 100644 drivers/net/fec_imx27.c
  create mode 100644 drivers/net/fec_imx27.h
  create mode 100644 drivers/net/imx27_miiphy.c
  create mode 100644 drivers/net/imx27_miiphy.h

 diff --git a/drivers/net/Makefile b/drivers/net/Makefile
 index a360a50..819e609 100644
 --- a/drivers/net/Makefile
 +++ b/drivers/net/Makefile
 @@ -34,6 +34,7 @@ COBJS-$(CONFIG_DRIVER_CS8900) += cs8900.o
  COBJS-$(CONFIG_TULIP) += dc2114x.o
  COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
  COBJS-$(CONFIG_DNET) += dnet.o
 +COBJS-$(CONFIG_FEC_IMX27) += fec_imx27.o imx27_miiphy.o
  COBJS-$(CONFIG_E1000) += e1000.o
  COBJS-$(CONFIG_EEPRO100) += eepro100.o
  COBJS-$(CONFIG_ENC28J60) += enc28j60.o
 diff --git a/drivers/net/fec_imx27.c b/drivers/net/fec_imx27.c
 new file mode 100644
 index 000..25299b9
 --- /dev/null
 +++ b/drivers/net/fec_imx27.c
 @@ -0,0 +1,795 @@
 +/*
 + * (C) Copyright 2008,2009 Eric Jarrige eric.jarr...@armadeus.org
 + * (C) Copyright 2008 Armadeus Systems nc
 + * (C) Copyright 2007 Pengutronix, Sascha Hauer s.ha...@pengutronix.de
 + * (C) Copyright 2007 Pengutronix, Juergen Beisert j.beis...@pengutronix.de
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +/** TODO eth_register + cleanup gfec !! */
   
Huh?
 +
 +
 +#include common.h
 +#include malloc.h
 +#include net.h
 +#include imx27_miiphy.h
 +#include fec_imx27.h
 +
 +#include asm/arch/clock.h
 +#include asm/arch/imx-regs.h
 +#include asm/io.h
 +
 +#define CONFIG_PHY_ADDR  0
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
 +#if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
 +#error CONFIG_MII has to be defined!
 +#endif
 +
 +//#define CONFIG_FEC_IMX27_DEBUG
   
Please use #undef instead ( no  C++ -style comments).  Can you use 
debug() instead of this?
 +#ifdef CONFIG_FEC_IMX27_DEBUG
 +#define  PRINTF(fmt,args...) printf (fmt ,##args)
 +#else
 +#define PRINTF(fmt,args...)
 +#endif
 +
 +static int fec_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
 + uint8_t regAddr, uint16_t * retVal);
 +static int fec_miiphy_write(struct miiphy_device *mdev, uint8_t phyAddr,
 + uint8_t regAddr, uint16_t data);
 +
 +typedef struct {
 + uint8_t data[1500]; /** actual data */
 + int length; /** actual length */
 + int used;   /** buffer in use or not */
 + uint8_t head[16];   /** MAC header(6 + 6 + 2) + 2(aligned) */
 +} NBUF;
 +
 +fec_priv gfec=
 +{
 + .eth   = (ethernet_regs *)IMX_FEC_BASE,
 + .xcv_type  = MII100,
 + .rbd_base  = NULL,
 + .rbd_index = 0,
 + .tbd_base  = NULL,
 + .tbd_index = 0,
 + .miiphy =
 + {
 + CONFIG_PHY_ADDR,
 + fec_miiphy_read,
 + fec_miiphy_write,
 + 0,
 + NULL
 + },
 + .bd= NULL,
 +};
 +
 +/*
 + * MII-interface related functions
 + */
 +static int fec_miiphy_read(struct miiphy_device *mdev, uint8_t phyAddr,
 + uint8_t regAddr, uint16_t * retVal)
 +{
 + struct eth_device *edev = mdev-edev;
 + fec_priv *fec = (fec_priv *)edev-priv;
 +
 + uint32_t reg;   /* convenient holder for the PHY register */
 + uint32_t phy;   /* convenient holder for the PHY */
 + uint32_t start;
 +
 + /*
 +  * reading from any PHY's register is done by properly
 +  * programming the FEC's MII data register.
 +  */
 + writel(FEC_IEVENT_MII, fec-eth-ievent);
 + reg = regAddr  FEC_MII_DATA_RA_SHIFT;
 + phy = phyAddr  FEC_MII_DATA_PA_SHIFT;
 +
 + writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | 
 reg, fec-eth-mii_data);
   
Line's too long
 +
 + /*
 +  * wait for the related interrupt
 +  */
 + start = get_timer_masked(); /* get_time_ns(); */
 + while (!(readl(fec-eth-ievent)  FEC_IEVENT_MII)) {
 + if

[U-Boot] usbtty Support on AT91SAM9XXX chipsets

2009-05-06 Thread Daniel Sherwood

Hi

 

I am interested in getting usbtty support running on an AT91SAM9G20
board.  I have picked up the latest code on the CDC head on the
u-boot-usb GIT tree and am currently attempting to get the CDC-Ether
support up and running (merging various changes from the 9261 board to
the 9260).  

 

However in order to support our factory processes (which are currently
set up to use serial ports) we need to use the usbtty framework.  I have
had a quick go at replacing CONFIG_USG_ETHER with CONFIG_USB_TTY in the
config file but it doesn't work.  Digging around a bit I think this is
due to the following points:

 

1.  usbtty.c uses a global function call based UDC framework
(udc_init, udc_endpoint_read|write etc)
2.  This framework is implemented on the older UDC devices
(omap1510_udc.c, pxa27x_udh.c  mpc8xx_udc.c) but is not implemented on
at91_udc.c.
3.  drivers/usb/gadget/ether.c uses a new (Linux derived?) USB
gadget framework based on registering function tables and accessing via
helper functions in gadget.h.
4.  at91_udc.c is implemented to this framework.

 

Hence omap1510, pxa27x  mpc8xx support USB TTY operation and at91
supports ethernet operation but other combinations are not currently
possible.

 

Please could someone advise on the best way forward, initially I can
think of a couple of options as follows:

 

1.  create a wrapper that implements the old framework functions
(udc_init, udc_endpoint_read|write etc) and simply maps them on to the
new framework.
2.  import the appropriate TTY gadget implementation from Linux (as
for ether.c) and get it working and registered as a proper device.

 

I suspect 2 is the better option and the way that the project was
moving, but I thought I'd check if this was the way to go and whether
anyone else had made any progress in this area.  Also, if this is the
way to go, could someone confirm which version of the Linux Gadget
framework ether.c and friends are based on.  It appears to be completely
different to the latest version.

 

Cheers

 

Daniel Sherwood
Software Engineer
 
Sepura PLC

Radio House, St Andrew's Road
Cambridge, CB4 1GR, UK
T: +44 (0) 1223 694637
F: +44 (0) 1223 879000
www.sepura.com http://www.sepura.com 

 


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Re: [U-Boot] [PATCH v3] mtd: nand: new base driver for memory mapped nand devices

On Wednesday 06 May 2009 15:49:12 Scott Wood wrote:
 On Wed, May 06, 2009 at 03:38:36PM -0400, Mike Frysinger wrote:
  The BF537-STAMP Blackfin board had a driver for working with NAND devices
  that are simply memory mapped.  Since there is nothing Blackfin specific
  about this, generalize the driver a bit so that everyone can leverage it.
 
  Signed-off-by: Mike Frysinger vap...@gentoo.org
  CC: Scott Wood scottw...@freescale.com

 Applied to u-boot-nand-flash/next.

thanks !
-mike


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Re: [U-Boot] [PATCH 01/10] mx27: basic cpu support

Hi

2009/5/6 Ilya Yanok ya...@emcraft.com:
 This patch adds generic code to support Freescale's i.MX27 SoCs.

 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  cpu/arm926ejs/mx27/Makefile          |   44 +++
  cpu/arm926ejs/mx27/generic.c         |  205 ++
  cpu/arm926ejs/mx27/interrupt.c       |  201 ++
  include/asm-arm/arch-mx27/clock.h    |   17 ++
  include/asm-arm/arch-mx27/imx-regs.h |  504 
 ++
  5 files changed, 971 insertions(+), 0 deletions(-)
  create mode 100644 cpu/arm926ejs/mx27/Makefile
  create mode 100644 cpu/arm926ejs/mx27/generic.c
  create mode 100644 cpu/arm926ejs/mx27/interrupt.c
  create mode 100644 include/asm-arm/arch-mx27/clock.h
  create mode 100644 include/asm-arm/arch-mx27/imx-regs.h

 diff --git a/cpu/arm926ejs/mx27/Makefile b/cpu/arm926ejs/mx27/Makefile
 new file mode 100644
 index 000..c86f3c2
 --- /dev/null
 +++ b/cpu/arm926ejs/mx27/Makefile
 @@ -0,0 +1,44 @@
 +#
 +# (C) Copyright 2000-2006
 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 +#
 +# See file CREDITS for list of people who contributed to this
 +# project.
 +#
 +# This program is free software; you can redistribute it and/or
 +# modify it under the terms of the GNU General Public License as
 +# published by the Free Software Foundation; either version 2 of
 +# the License, or (at your option) any later version.
 +#
 +# This program is distributed in the hope that it will be useful,
 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 +# GNU General Public License for more details.
 +#
 +# You should have received a copy of the GNU General Public License
 +# along with this program; if not, write to the Free Software
 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 +# MA 02111-1307 USA
 +
 +include $(TOPDIR)/config.mk
 +
 +LIB    = $(obj)lib$(SOC).a
 +
 +COBJS  = interrupt.o generic.o
 +
 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
 +OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS))
 +
 +all:   $(obj).depend $(LIB)
 +
 +$(LIB):        $(OBJS)
 +       $(AR) $(ARFLAGS) $@ $(OBJS)
 +
 +#
 +
 +# defines $(obj).depend target
 +include $(SRCTREE)/rules.mk
 +
 +sinclude $(obj).depend
 +
 +#
 diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
 new file mode 100644
 index 000..fdbc8b7
 --- /dev/null
 +++ b/cpu/arm926ejs/mx27/generic.c
 @@ -0,0 +1,205 @@
 +/*
 + *  Copyright (c) 2008 Eric Jarrige eric.jarr...@armadeus.org
 + *  Copyright (c) 2009 Ilya Yanok ya...@emcraft.com
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +#include common.h
 +#include div64.h
 +#include asm/arch/imx-regs.h

An empty line after the last #include statement improves readability, IMO.

 +/*
 + *  get the system pll clock in Hz
 + *
 + *                  mfi + mfn / (mfd +1)
 + *  f = 2 * f_ref * 
 + *                        pd + 1
 + */
 +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 +{
 +       unsigned int mfi = (pll  10)  0xf;
 +       unsigned int mfn = pll  0x3ff;
 +       unsigned int mfd = (pll  16)  0x3ff;
 +       unsigned int pd =  (pll  26)  0xf;
 +
 +       mfi = mfi = 5 ? 5 : mfi;
 +
 +       return lldiv((2*(u64)f_ref* (mfi*(mfd+1) + mfn)), ((mfd+1)*(pd+1)));

Add space before and after * and +

 +}
 +
 +static ulong clk_in_32k(void)
 +{
 +       return 1024 * CONFIG_MX31_CLK32;
 +}
 +
 +static ulong clk_in_26m(void)
 +{
 +       if (CSCR  CSCR_OSC26M_DIV1P5) {
 +               /* divide by 1.5 */
 +               return 2600 / 1.5;
 +       } else {
 +               /* divide by 1 */
 +               return 2600;
 +       }
 +}
 +
 +ulong imx_get_mpllclk(void)
 +{
 +       ulong cscr = CSCR;
 +       ulong fref;
 +
 +       if (cscr  CSCR_MCU_SEL)
 +               fref = clk_in_26m();
 +       else
 +               fref = clk_in_32k();
 +
 +       return imx_decode_pll(MPCTL0, fref);
 +}
 +
 +ulong imx_get_armclk(void)
 +{
 +       ulong cscr = CSCR;
 +       ulong fref = imx_get_mpllclk();
 +       ulong div;
 +
 +       if (!(cscr  CSCR_ARM_SRC_MPLL))
 +

Re: [U-Boot] [PATCH 04/10] mxc_nand: add nand driver for MX2/MX3

Hi

2009/5/6 Ilya Yanok ya...@emcraft.com:
 Driver for NFC NAND controller found on Freescale's MX2 and MX3
 processors. Ported from Linux. Tested only with i.MX27 but should
 works with other MX2 and MX3 processors too.

 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  drivers/mtd/nand/Makefile   |    1 +
  drivers/mtd/nand/mxc_nand.c |  891 
 +++
  2 files changed, 892 insertions(+), 0 deletions(-)
  create mode 100644 drivers/mtd/nand/mxc_nand.c

 diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
 index 471cd6b..24de947 100644
 --- a/drivers/mtd/nand/Makefile
 +++ b/drivers/mtd/nand/Makefile
 @@ -40,6 +40,7 @@ COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
  COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
  COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
  COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 +COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
  COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o
  COBJS-$(CONFIG_NAND_S3C2410) += s3c2410_nand.c
  COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
 diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
 new file mode 100644
 index 000..48a6b7b
 --- /dev/null
 +++ b/drivers/mtd/nand/mxc_nand.c
 @@ -0,0 +1,891 @@
...
 +#define NFC_SP_EN           (1  2)
 +#define NFC_ECC_EN          (1  3)
 +#define NFC_INT_MSK         (1  4)
 +#define NFC_BIG             (1  5)
 +#define NFC_RST             (1  6)
 +#define NFC_CE              (1  7)
 +#define NFC_ONE_CYCLE       (1  8)
 +
 +typedef enum _bool{false,true} bool;

Isn't there some include-file we can use instead of typdefing this locally?

 +

Regards, Magnus
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Re: [U-Boot] [PATCH 07/10] mmc: use lldiv() for 64-bit division

Hi

2009/5/6 Ilya Yanok ya...@emcraft.com:
 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  drivers/mmc/mmc.c |    7 ---
  1 files changed, 4 insertions(+), 3 deletions(-)

 diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
 index 7791c38..77a9aea 100644
 --- a/drivers/mmc/mmc.c
 +++ b/drivers/mmc/mmc.c
 @@ -31,6 +31,7 @@
  #include malloc.h
  #include linux/list.h
  #include mmc.h
 +#include div64.h

  static struct list_head mmc_devices;
  static int cur_dev_num = -1;
 @@ -155,8 +156,8 @@ int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int 
 size)
        char *buffer;
        int i;
        int blklen = mmc-read_bl_len;
 -       int startblock = src / blklen;
 -       int endblock = (src + size - 1) / blklen;
 +       int startblock = lldiv(src, blklen);
 +       int endblock = lldiv((src + size - 1), blklen);
        int err = 0;

        /* Make a buffer big enough to hold all the blocks we might read */
 @@ -789,7 +790,7 @@ int mmc_startup(struct mmc *mmc)
        mmc-block_dev.lun = 0;
        mmc-block_dev.type = 0;
        mmc-block_dev.blksz = mmc-read_bl_len;
 -       mmc-block_dev.lba = mmc-capacity/mmc-read_bl_len;
 +       mmc-block_dev.lba = lldiv(mmc-capacity,mmc-read_bl_len);

Add space after comma.

Regards, Magnus
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Re: [U-Boot] [PATCH 10/10] imx27lite: add support for imx27lite board from LogicPD

Hi

2009/5/6 Ilya Yanok ya...@emcraft.com:
 This patch adds support for i.MX27-LITEKIT development board from
 LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
 flash, FEC ethernet controller integrated into i.MX27.

 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  MAKEALL                                 |    1 +
  Makefile                                |    3 +
  board/logicpd/imx27lite/Makefile        |   51 +++
  board/logicpd/imx27lite/config.mk       |    1 +
  board/logicpd/imx27lite/imx27lite.c     |   97 +
  board/logicpd/imx27lite/lowlevel_init.S |  225 
 +++
  board/logicpd/imx27lite/u-boot.lds      |   56 
  include/configs/imx27lite.h             |  188 ++
  8 files changed, 622 insertions(+), 0 deletions(-)
  create mode 100644 board/logicpd/imx27lite/Makefile
  create mode 100644 board/logicpd/imx27lite/config.mk
  create mode 100644 board/logicpd/imx27lite/imx27lite.c
  create mode 100644 board/logicpd/imx27lite/lowlevel_init.S
  create mode 100644 board/logicpd/imx27lite/u-boot.lds
  create mode 100644 include/configs/imx27lite.h

 diff --git a/MAKEALL b/MAKEALL
 index f13c81a..4806512 100755
 --- a/MAKEALL
 +++ b/MAKEALL
 @@ -504,6 +504,7 @@ LIST_ARM9=                 \
        cp946es                 \
        cp966                   \
        lpd7a400                \
 +       imx27lite               \

I think the list should be sorted alphabetically, so move it up one step.

        mx1ads                  \
        mx1fs2                  \
        netstar                 \
...
 diff --git a/board/logicpd/imx27lite/lowlevel_init.S 
 b/board/logicpd/imx27lite/lowlevel_init.S
 new file mode 100644
 index 000..48c7fe6
 --- /dev/null
 +++ b/board/logicpd/imx27lite/lowlevel_init.S
 @@ -0,0 +1,225 @@
 +/*
 + * For clock initialization, see chapter 3 of the MCIMX27 Multimedia
 + * Applications Processor Reference Manual, Rev. 0.2.
 + *
 + * (C) Copyright 2008 Eric Jarrige eric.jarr...@armadeus.org
 + * (C) Copyright 2009 Ilya Yanok ya...@emcraft.com
 + *
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License as
 + * published by the Free Software Foundation; either version 2 of
 + * the License, or (at your option) any later version.
 + *
 + * This program is distributed in the hope that it will be useful,
 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 + * GNU General Public License for more details.
 + *
 + * You should have received a copy of the GNU General Public License
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
 + */
 +
 +
 +#include config.h
 +#include version.h
 +#include asm/arch/imx-regs.h
 +
 +#define CFG_SDRAM_ESDCFG_REGISTER_VAL(cas)     \
 +               (ESDCFG_TRC(10) |       \
 +               ESDCFG_TRCD(3) |        \
 +               ESDCFG_TCAS(cas) |      \
 +               ESDCFG_TRRD(1) |        \
 +               ESDCFG_TRAS(5) |        \
 +               ESDCFG_TWR |            \
 +               ESDCFG_TMRD(2) |        \
 +               ESDCFG_TRP(2) |         \
 +               ESDCFG_TXP(3))
 +
 +#define CFG_SDRAM_ESDCTL_REGISTER_VAL  \
 +               (ESDCTL_PRCT(0) |       \
 +                ESDCTL_BL |            \
 +                ESDCTL_PWDT(0) |       \
 +                ESDCTL_SREFR(3) |      \
 +                ESDCTL_DSIZ_32 |       \
 +                ESDCTL_COL10 |         \
 +                ESDCTL_ROW13 |         \
 +                ESDCTL_SDE)
 +
 +#define CFG_SDRAM_ALL_VAL              0xf00
 +
 +#define CFG_SDRAM_MODE_REGISTER_VAL    0x33    /* BL: 8, CAS: 3 */
 +#define CFG_SDRAM_EXT_MODE_REGISTER_VAL        0x100
 +
 +#define CFG_MPCTL0_VAL 0x1ef15d5
 +
 +#define CFG_SPCTL0_VAL 0x043a1c09
 +
 +#define CFG_CSCR_VAL   0x33f08107
 +
 +#define CFG_PCDR0_VAL  0x120470c3
 +#define CFG_PCDR1_VAL  0x03030303
 +#define CFG_PCCR0_VAL  0x
 +#define CFG_PCCR1_VAL  0xfffc
 +
 +#define CFG_AIPI1_PSR0_VAL     0x20040304
 +#define CFG_AIPI1_PSR1_VAL     0xdffbfcfb
 +#define CFG_AIPI2_PSR0_VAL     0x07ffc200
 +#define CFG_AIPI2_PSR1_VAL     0x
 +
 +#define writel(reg, val) \
 +       ldr             r0,     =reg;   \
 +       ldr             r1,     =val;   \
 +       str             r1,   [r0];
 +
 +SOC_ESDCTL_BASE_W:     .word   IMX_ESD_BASE
 +SOC_SI_ID_REG_W:       .word   IMX_SYSTEM_CTL_BASE
 +SDRAM_ESDCFG_T1_W:     .word   CFG_SDRAM_ESDCFG_REGISTER_VAL(0)
 +SDRAM_ESDCFG_T2_W:     .word   CFG_SDRAM_ESDCFG_REGISTER_VAL(3)
 +SDRAM_PRECHARGE_CMD_W: .word   (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
 +                                ESDCTL_ROW13 | ESDCTL_COL10)
 +SDRAM_AUTOREF_CMD_W:   .word   (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
 +

Re: [U-Boot] [PATCH 1/1] at91: Add command to control up to 3 GPIO LEDs from the console

Dear Daniel Gorsulowski,

In message 1241619669338-git-send-email-daniel.gorsulow...@esd.eu you wrote:
 This patch allows any at91 board, implementing the GPIO LED API,
 to control the LEDs from the console.
 
 led [ 1 | 2 | 3 | all ]  [ on | off ]
 
 Adding configuration items CONFIG_AT91_LED and CONFIG_CMD_LED
 enables the command.
 Moreover the GPIO Pins have to be defined by CONFIG_USER1_LED ...
 CONFIG_USER3_LED.

Signed-off-by: line missing.

 ---
  common/Makefile |1 +
  common/cmd_led.c|   86 
 +++
  cpu/arm926ejs/at91/led.c|   79 +++
  include/asm-arm/arch-at91/led.h |   52 +++
  4 files changed, 218 insertions(+), 0 deletions(-)
  create mode 100644 common/cmd_led.c
  create mode 100644 include/asm-arm/arch-at91/led.h
 
 diff --git a/common/Makefile b/common/Makefile
 index b9f4ca7..e0f571c 100644
 --- a/common/Makefile
 +++ b/common/Makefile
 @@ -103,6 +103,7 @@ COBJS-$(CONFIG_CMD_IMMAP) += cmd_immap.o
  COBJS-$(CONFIG_CMD_IRQ) += cmd_irq.o
  COBJS-$(CONFIG_CMD_ITEST) += cmd_itest.o
  COBJS-$(CONFIG_CMD_JFFS2) += cmd_jffs2.o
 +COBJS-$(CONFIG_CMD_LED) += cmd_led.o
  COBJS-$(CONFIG_CMD_LICENSE) += cmd_license.o
  COBJS-y += cmd_load.o
  COBJS-$(CONFIG_LOGBUFFER) += cmd_log.o
 diff --git a/common/cmd_led.c b/common/cmd_led.c

Ummm... common is for, well, for common stuff. If this code is
specific to AT91 only, it should not go into common.


...
 +U_BOOT_CMD(
 + led, 3, 1, do_led,
 + [1|2|3|all] [on|off],
 + [1|2|3|all] [on|off] sets/clears led 1,2,3

Do you really say I set a LED? I clear a LED?  I don't think so.

 diff --git a/include/asm-arm/arch-at91/led.h b/include/asm-arm/arch-at91/led.h
 new file mode 100644
 index 000..878b2cf
 --- /dev/null
 +++ b/include/asm-arm/arch-at91/led.h
 @@ -0,0 +1,52 @@
 +/*
 + * (C) Copyright 2000-2004
 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de.

You claim that I have written any of this code?  I decline.


Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 1/1] at91: Add command to control up to 3 GPIO LEDs from the console

On Wednesday 06 May 2009 16:37:28 Wolfgang Denk wrote:
 In message Daniel Gorsulowski wrote:
  --- a/common/Makefile
  +++ b/common/Makefile
  +COBJS-$(CONFIG_CMD_LED) += cmd_led.o

 Ummm... common is for, well, for common stuff. If this code is
 specific to AT91 only, it should not go into common.

well, how common is common ?  ive put commands in there that are common to all 
Blackfin parts, but that's it ... should i be relocating them to lib_blackfin/ 
or something ?
-mike


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Re: [U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

Dear Mike Frysinger,

In message 1241615121-15945-1-git-send-email-vap...@gentoo.org you wrote:
 The BF537-STAMP Blackfin board had a driver for working with NAND devices
 that are simply memory mapped.  Since there is nothing Blackfin specific
 about this, generalize the driver a bit so that everyone can leverage it.
 
 Signed-off-by: Mike Frysinger vap...@gentoo.org
...

 diff --git a/drivers/mtd/nand/nand_plat.c b/drivers/mtd/nand/nand_plat.c
 new file mode 100644
 index 000..9a0e4c0
 --- /dev/null
 +++ b/drivers/mtd/nand/nand_plat.c
 @@ -0,0 +1,53 @@
 +/*
 + * Genericish driver for memory mapped NAND devices

Genericish ?

...
 +#define NAND_PLAT_WRITE_CMD(cmd, chip) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), 
 cmd)
 +#define NAND_PLAT_WRITE_ADR(cmd, chip) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), 
 cmd)
 +#define NAND_PLAT_DEV_READY(chip)  ((*pPORTFIO  BFIN_NAND_READY) ? 1 : 
 0)
 +#define NAND_PLAT_INIT() \
 + do { \
 + *pPORTF_FER = ~BFIN_NAND_READY; \
 + *pPORTFIO_DIR = ~BFIN_NAND_READY; \
 + *pPORTFIO_INEN |= BFIN_NAND_READY; \
 + } while (0)

Please use I/O accessors instead of pointers.


Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH v3] mtd: nand: new base driver for memory mapped nand devices

Dear Mike Frysinger,

In message 1241638716-29824-1-git-send-email-vap...@gentoo.org you wrote:
 The BF537-STAMP Blackfin board had a driver for working with NAND devices
 that are simply memory mapped.  Since there is nothing Blackfin specific
 about this, generalize the driver a bit so that everyone can leverage it.
 
 Signed-off-by: Mike Frysinger vap...@gentoo.org
 CC: Scott Wood scottw...@freescale.com
 ---
 v3
   - re-order args to NAND_PLAT_WRITE_*
   - dont bother normalizing NAND_PLAT_DEV_READY

Please see my comments for v2; they still apply.

Best regards,

Wolfgang Denk

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The philosophy exam was a piece of cake  -  which  was  a  bit  of  a
surprise, actually, because I was expecting some questions on a sheet
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Re: [U-Boot] [PATCH 02/10] serial_mx31: allow it to work with mx27 too

Dear Ilya Yanok,

In message 1241634633-13917-3-git-send-email-ya...@emcraft.com you wrote:
 UART hardware on i.MX27 is the same as on the i.MX31 so we just
 need to provide the driver with correct address of the registers.
 
 Signed-off-by: Ilya Yanok ya...@emcraft.com
 ---
  drivers/serial/serial_mx31.c |   21 +
  1 files changed, 21 insertions(+), 0 deletions(-)
 
 diff --git a/drivers/serial/serial_mx31.c b/drivers/serial/serial_mx31.c
 index 7c0682a..acc5b7d 100644
 --- a/drivers/serial/serial_mx31.c
 +++ b/drivers/serial/serial_mx31.c
 @@ -18,7 +18,12 @@
   */
  
  #include common.h
 +#ifdef CONFIG_MX31
  #include asm/arch/mx31.h
 +#else
 +#include asm/arch/imx-regs.h
 +#include asm/arch/clock.h
 +#endif
  
  #define __REG(x) (*((volatile u32 *)(x)))
  
 @@ -32,6 +37,18 @@
  #define UART_PHYS 0x43fb
  #elif defined(CONFIG_SYS_MX31_UART5)
  #define UART_PHYS 0x43fb4000
 +#elif defined(CONFIG_SYS_MX27_UART1)
 +#define UART_PHYS 0x1000a000
 +#elif defined(CONFIG_SYS_MX27_UART2)
 +#define UART_PHYS 0x1000b000
 +#elif defined(CONFIG_SYS_MX27_UART3)
 +#define UART_PHYS 0x1000c000
 +#elif defined(CONFIG_SYS_MX27_UART4)
 +#define UART_PHYS 0x1000d000
 +#elif defined(CONFIG_SYS_MX27_UART5)
 +#define UART_PHYS 0x1001b000
 +#elif defined(CONFIG_SYS_MX27_UART6)
 +#define UART_PHYS 0x1001c000

Should that file be renamed? serial_mx31.c does not seem correct any
more...

And - what are these constants? I smell addresses? Unse I/O accessors
instead?

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH 01/10] mx27: basic cpu support

Dear Ilya,

in message 1241634633-13917-2-git-send-email-ya...@emcraft.com you wrote:
 This patch adds generic code to support Freescale's i.MX27 SoCs.
...

 +static ulong clk_in_26m(void)
 +{
 + if (CSCR  CSCR_OSC26M_DIV1P5) {
 + /* divide by 1.5 */
 + return 2600 / 1.5;

We definitely do not allow any FP use in U-Boot.

 + } else {
 + /* divide by 1 */
 + return 2600;

divide by 1 ???


 +#if defined(CONFIG_DISPLAY_CPUINFO)
 +int print_cpuinfo (void)
 +{
 +   printf(CPU:   Freescale i.MX27 at %llu MHz\n,
 +   lldiv(imx_get_mpllclk(), 100));

Please use strmhz() to print frequencies.

 +   printf(\n);

No need to waste another function call - just add this to the previous
format element.

 +void imx_gpio_mode(int gpio_mode)
 +{
 + unsigned int pin = gpio_mode  GPIO_PIN_MASK;
 + unsigned int port = (gpio_mode  GPIO_PORT_MASK)  GPIO_PORT_SHIFT;
 + unsigned int ocr = (gpio_mode  GPIO_OCR_MASK)  GPIO_OCR_SHIFT;
 + unsigned int aout = (gpio_mode  GPIO_AOUT_MASK)  GPIO_AOUT_SHIFT;
 + unsigned int bout = (gpio_mode  GPIO_BOUT_MASK)  GPIO_BOUT_SHIFT;
 + unsigned int tmp;
 +
 + /* Pullup enable */
 + if(gpio_mode  GPIO_PUEN)
 + PUEN(port) |= (1  pin);
 + else
 + PUEN(port) = ~(1  pin);

This smells as if these were pointer accesses using register offsets
instead of I/O accessor calls using C structs?

You probably want to use the respective clrbits*() / setbits*() macros
here?

...
 +void reset_cpu (ulong ignored)
 +{
 + /* Disable watchdog and set Time-Out field to 0 */
 + WCR = 0x;
 +
 + /* Write Service Sequence */
 + WSR = 0x;
 + WSR = 0x;

Again: please use I/O accessor calls; also for the rest of the file
and the other patches.

...
 diff --git a/include/asm-arm/arch-mx27/imx-regs.h 
 b/include/asm-arm/arch-mx27/imx-regs.h
 new file mode 100644
 index 000..a856f7e
...
 +# ifndef __ASSEMBLY__
 +# define __REG(x)(*((volatile u32 *)(x)))
 +# define __REG16(x) (*(volatile u16 *)(x))
 +# define __REG2(x,y)(*(volatile u32 *)((u32)__REG(x) + (y)))
 +
 +extern void imx_gpio_mode (int gpio_mode);
 +
 +# else
 +#  define __REG(x) (x)
 +#  define __REG16(x) (x)
 +#  define __REG2(x,y) ((x)+(y))
 +#endif
 +
 +#define IMX_IO_BASE  0x1000
 +
 +#define IMX_AIPI1_BASE (0x0 + IMX_IO_BASE)
 +#define IMX_WDT_BASE   (0x02000 + IMX_IO_BASE)
 +#define IMX_TIM1_BASE  (0x03000 + IMX_IO_BASE)
 +#define IMX_TIM2_BASE  (0x04000 + IMX_IO_BASE)
 +#define IMX_TIM3_BASE  (0x05000 + IMX_IO_BASE)
 +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE)
 +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE)
 +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE)
 +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE)
 +#define IMX_I2C1_BASE  (0x12000 + IMX_IO_BASE)
 +#define IMX_GPIO_BASE  (0x15000 + IMX_IO_BASE)
 +#define IMX_TIM4_BASE  (0x19000 + IMX_IO_BASE)
 +#define IMX_TIM5_BASE  (0x1a000 + IMX_IO_BASE)
 +#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE)
 +#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE)
 +#define IMX_I2C2_BASE  (0x1D000 + IMX_IO_BASE)
 +#define IMX_TIM6_BASE  (0x1f000 + IMX_IO_BASE)
 +#define IMX_AIPI2_BASE (0x2 + IMX_IO_BASE)
 +#define IMX_PLL_BASE   (0x27000 + IMX_IO_BASE)
 +#define IMX_SYSTEM_CTL_BASE(0x27800 + IMX_IO_BASE)
 +#define IMX_IIM_BASE   (0x28000 + IMX_IO_BASE)
 +#define IMX_FEC_BASE   (0x2b000 + IMX_IO_BASE)

NAK. We do not accept device I/O through pointers; please use C
structs to describe the hardware and use I/O accessor calls.

 +/* AIPI */
 +#define AIPI1_PSR0   __REG(IMX_AIPI1_BASE + 0x00)
 +#define AIPI1_PSR1   __REG(IMX_AIPI1_BASE + 0x04)
 +#define AIPI2_PSR0   __REG(IMX_AIPI2_BASE + 0x00)
 +#define AIPI2_PSR1   __REG(IMX_AIPI2_BASE + 0x04)
 +
 +/* System Control */
 +#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14)
 +#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18)
 +#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C)

NAK, for this and all similar code.


Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 03/10] fec_imx27: driver for FEC ethernet controller on i.MX27

Dear Ilya,

In message 1241634633-13917-4-git-send-email-ya...@emcraft.com you wrote:
 
 --- /dev/null
 +++ b/drivers/net/fec_imx27.c
 +#include asm/arch/clock.h
 +#include asm/arch/imx-regs.h
 +#include asm/io.h
 +
 +#define CONFIG_PHY_ADDR  0

Ummm... CONFIG_* variables are by definition user changable, so they
get defined in board config files, but never in common C code.

[Lots of problematic code skipped as others already pointed out the
issues.]

 +int eth_init(bd_t * bd)
 +{
 +
 + if (!once)
 + {
 + PRINTF(eth_init: fec_probe(bd)\n);
 + fec_probe(bd);
 + once = 1;
 + }
 + PRINTF(eth_init: fec_init(gfec.miiphy.edev, bd)\n);
 + return fec_init(gfec.miiphy.edev, bd);
 +};

Incorrect brace style, also elsewhere.


Best regards,

Wolfgang Denk

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 04/10] mxc_nand: add nand driver for MX2/MX3

Dear Ilya,

In message 1241634633-13917-5-git-send-email-ya...@emcraft.com you wrote:
 Driver for NFC NAND controller found on Freescale's MX2 and MX3
 processors. Ported from Linux. Tested only with i.MX27 but should
 works with other MX2 and MX3 processors too.
...
 +/* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
 + * for Command operation */

Incorrect multiline comment style. Here and elsewhere.

...
 +static void send_prog_page(struct mxc_nand_host *host, uint8_t buf_id,
 + int spare_only)
 +{
 + MTDDEBUG(MTD_DEBUG_LEVEL3, send_prog_page (%d)\n, spare_only);
 +
 + /* NANDFC buffer 0 is used for page read/write */
 + writew(buf_id, host-regs + NFC_BUF_ADDR);
 +
 + /* Configure spare or page+spare access */
 + if (!host-pagesize_2k) {
 + uint16_t config1 = readw(host-regs + NFC_CONFIG1);
 + if (spare_only)
 + config1 |= NFC_SP_EN;
 + else
 + config1 = ~(NFC_SP_EN);

Use setbits*() / clrbits*() ? Here and elsewhere.


Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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A:  One per person.
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Re: [U-Boot] [PATCH 00/10] Support for LogicPD i.MX27-LITEKIT development board

Dear Ilya,

In message 1241634633-13917-1-git-send-email-ya...@emcraft.com you wrote:
 This patch set adds support for LogicPD i.MX27-LITEKIT development board.
 It contains support for i.MX27 CPU, support for serial console, FEC
 ethernet controller, NFC NAND controller and SDHC controller. It also
 contains some fixes to generic MMC subsystem.
 
 Signed-off-by: Ilya Yanok ya...@emcraft.com

General comments in addition to what the other posters already
remarked:

The whole patch set needs clean up regarding coding style: line
length, indentation and vertical alignment by TABs, brace style, no
C++ comments, incorrect multiline comment style, etc.

Also, large parts of the code are based on accessing device registers
through pointers, usualy hiddewn in some macros  using  base  address
and  offset. We don't accept such code any more. Please use C structs
and I/O accessor calls.


Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
...and the fully armed nuclear warheads, are, of  course,  merely  a
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Re: [U-Boot] [PATCH 10/10] imx27lite: add support for imx27lite board from LogicPD

Dear Ilya,

In message 1241634633-13917-11-git-send-email-ya...@emcraft.com you wrote:
 This patch adds support for i.MX27-LITEKIT development board from
 LogicPD. This board uses i.MX27 SoC and has 2MB NOR flash, 64MB NAND
 flash, FEC ethernet controller integrated into i.MX27.
...
 +/*=*/
 +/* U-Boot commands */
 +/*=*/
 +#include config_cmd_default.h
 +#define CONFIG_CMD_ASKENV
 +#define CONFIG_CMD_DHCP
 +#define CONFIG_CMD_DIAG
 +#define CONFIG_CMD_NET
 +#undef CONFIG_CMD_NFS

Please enable.

 +#define CONFIG_CMD_MII
 +#define CONFIG_CMD_PING
 +#undef CONFIG_CMD_BDI

Please enable.

 +#undef CONFIG_CMD_FPGA

?

 +#undef CONFIG_CMD_SETGETDCR

?

 +#define CONFIG_CMD_NAND
 +#define CONFIG_CMD_JFFS2
 +#define CONFIG_CMD_MMC
 +#define CONFIG_CMD_FAT

Please keep the list sorted.

 +/*
 + * You can compile in a MAC address and your custom net settings by using
 + * the following syntax.
 + *
 + * #define CONFIG_ETHADDRxx:xx:xx:xx:xx:xx
 + * #define CONFIG_SERVERIP   server ip
 + * #define CONFIG_IPADDR board ip
 + * #define CONFIG_GATEWAYIP  gateway ip
 + * #define CONFIG_NETMASKyour netmask
 + */

Please remove this part.

Best regards,

Wolfgang Denk

-- 
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
panic: kernel trap (ignored)
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[U-Boot] [PATCH] mmc: Fix decoding of SCR function switch data on little-endian machines

2009-05-06 Thread Yauhen Kharuzhy

SCR  switch data are read from card as big-endian words and should be
converted to CPU byte order.

Signed-off-by: Yauhen Kharuzhy jek...@gmail.com
---
 drivers/mmc/mmc.c |   12 +++-
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index b4814d2..596e052 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -487,8 +487,8 @@ retry_scr:
return err;
}
 
-   mmc-scr[0] = scr[0];
-   mmc-scr[1] = scr[1];
+   mmc-scr[0] = __be32_to_cpu(scr[0]);
+   mmc-scr[1] = __be32_to_cpu(scr[1]);
 
switch ((mmc-scr[0]  24)  0xf) {
case 0:
@@ -518,7 +518,7 @@ retry_scr:
return err;
 
/* The high-speed function is busy.  Try again */
-   if (!switch_status[7]  SD_HIGHSPEED_BUSY)
+   if (!(__be32_to_cpu(switch_status[7])  SD_HIGHSPEED_BUSY))
break;
}
 
@@ -526,7 +526,7 @@ retry_scr:
mmc-card_caps |= MMC_MODE_4BIT;
 
/* If high-speed isn't supported, we return */
-   if (!(switch_status[3]  SD_HIGHSPEED_SUPPORTED))
+   if (!(__be32_to_cpu(switch_status[3])  SD_HIGHSPEED_SUPPORTED))
return 0;
 
err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
@@ -534,8 +534,10 @@ retry_scr:
if (err)
return err;
 
-   if ((switch_status[4]  0x0f00) == 0x0100)
+   if ((__be32_to_cpu(switch_status[4])  0x0f00) == 0x0100) {
mmc-card_caps |= MMC_MODE_HS;
+   printf(Switched to HS mode\n);
+   }
 
return 0;
 }
-- 
1.6.2.3

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[U-Boot] QUESTION: How do I generate an assembly listing?

2009-05-06 Thread Jonathan Haws

I need to generate an assembly listing that contains all the assembly code 
generated by the compiler.  I have tried putting the standard GCC options in 
ppc_config.mk, but cannot get the results I am looking for.

What I need is a listing file that contains the address (preferably with _start 
at 0x) and the function name and any assembly code with their 
respective addresses.

Can this easily be done?

--
Jonathan R. Haws
Electrical Engineering
Space Dynamics Laboratory
 
jonathan.h...@sdl.usu.edu
(435)797-4629



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Re: [U-Boot] QUESTION: How do I generate an assembly listing?

Dear Jonathan Haws,

In message bb99a6ba28709744bf22a68e6d7eb51f01cb587...@midas.usurf.usu.edu you 
wrote:
 I need to generate an assembly listing that contains all the assembly code 
 generated by the compiler.  I have tried putting the standard GCC options in 
 ppc_config.mk, but cannot get the results I am looking for.
 
 What I need is a listing file that contains the address (preferably with 
 _start at 0x) and the function name and any assembly code with their 
 respective addresses.
 
 Can this easily be done?

Use objdump -SD u-boot ?  on the other hand - why would anybody need
that? Don't you know how to use gdb?

Best regards,

Wolfgang Denk

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is.   - Terry Pratchett, _Witches Abroad_
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Re: [U-Boot] [PATCH v2] mtd: nand: new base driver for memory mapped nand devices

On Wednesday 06 May 2009 16:51:18 Wolfgang Denk wrote:
 In Mike Frysinger wrote:
  --- /dev/null
  +++ b/drivers/mtd/nand/nand_plat.c
  @@ -0,0 +1,53 @@
  +/*
  + * Genericish driver for memory mapped NAND devices

 Genericish ?

i tried to make it generic.  i dont know if i accomplished that :).

  +#define NAND_PLAT_WRITE_CMD(cmd, chip)
  BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) +#define
  NAND_PLAT_WRITE_ADR(cmd, chip) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
  +#define NAND_PLAT_DEV_READY(chip)  ((*pPORTFIO  BFIN_NAND_READY) ?
  1 : 0) +#define NAND_PLAT_INIT() \
  +   do { \
  +   *pPORTF_FER = ~BFIN_NAND_READY; \
  +   *pPORTFIO_DIR = ~BFIN_NAND_READY; \
  +   *pPORTFIO_INEN |= BFIN_NAND_READY; \
  +   } while (0)

 Please use I/O accessors instead of pointers.

OK
-mike


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[U-Boot] [PATCH v4] mtd: nand: new base driver for memory mapped nand devices

The BF537-STAMP Blackfin board had a driver for working with NAND devices
that are simply memory mapped.  Since there is nothing Blackfin specific
about this, generalize the driver a bit so that everyone can leverage it.

Signed-off-by: Mike Frysinger vap...@gentoo.org
Signed-off-by: Scott Wood scottw...@freescale.com
---
v4
- use I/O accessors

 board/bf537-stamp/Makefile|1 -
 board/bf537-stamp/nand.c  |  100 -
 drivers/mtd/nand/Makefile |1 +
 drivers/mtd/nand/nand_plat.c  |   53 +++
 include/configs/bf537-stamp.h |   44 +++--
 include/configs/bfin_adi_common.h |3 +
 6 files changed, 75 insertions(+), 127 deletions(-)
 delete mode 100644 board/bf537-stamp/nand.c
 create mode 100644 drivers/mtd/nand/nand_plat.c

diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index 1dbf406..6da04e3 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -32,7 +32,6 @@ LIB   = $(obj)lib$(BOARD).a
 COBJS-y:= $(BOARD).o cmd_bf537led.o
 COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
 COBJS-$(CONFIG_CMD_EEPROM) += spi_flash.o
-COBJS-$(CONFIG_CMD_NAND)   += nand.o
 COBJS-$(CONFIG_POST)   += post.o post-memory.o
 
 SRCS   := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
deleted file mode 100644
index 181e83d..000
--- a/board/bf537-stamp/nand.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2006-2007 Analog Devices Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include common.h
-#include asm/io.h
-
-#include nand.h
-
-#define CONCAT(a,b,c,d) a ## b ## c ## d
-#define PORT(a,b)  CONCAT(pPORT,a,b,)
-
-#ifndef CONFIG_NAND_GPIO_PORT
-#define CONFIG_NAND_GPIO_PORT F
-#endif
-
-/*
- * hardware specific access to control-lines
- */
-static void bfin_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
-   register struct nand_chip *this = mtd-priv;
-   u32 IO_ADDR_W = (u32) this-IO_ADDR_W;
-
-   if (ctrl  NAND_CTRL_CHANGE) {
-   if (ctrl  NAND_CLE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   if (ctrl  NAND_ALE)
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
-   else
-   IO_ADDR_W = CONFIG_SYS_NAND_BASE;
-   this-IO_ADDR_W = (void __iomem *) IO_ADDR_W;
-   }
-   this-IO_ADDR_R = this-IO_ADDR_W;
-
-   /* Drain the writebuffer */
-   SSYNC();
-
-   if (cmd != NAND_CMD_NONE)
-   writeb(cmd, this-IO_ADDR_W);
-}
-
-int bfin_device_ready(struct mtd_info *mtd)
-{
-   int ret = (*PORT(CONFIG_NAND_GPIO_PORT, IO)  BFIN_NAND_READY) ? 1 : 0;
-   SSYNC();
-   return ret;
-}
-
-/*
- * Board-specific NAND initialization. The following members of the
- * argument are board-specific (per include/linux/mtd/nand.h):
- * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
- * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
- * - cmd_ctrl: hardwarespecific function for accesing control-lines
- * - dev_ready: hardwarespecific function for  accesing device ready/busy line
- * - enable_hwecc?: function to enable (reset)  hardware ecc generator. Must
- *   only be provided if a hardware ECC is available
- * - ecc.mode: mode of ecc, see defines
- * - chip_delay: chip dependent delay for transfering data from array to
- *   read regs (tR)
- * - options: various chip options. They can partly be set to inform
- *   nand_scan about special functionality. See the defines for further
- *   explanation
- * Members with a ? were not set in the merged testing-NAND branch,
- * so they are not set here either.
- */
-int board_nand_init(struct nand_chip *nand)
-{
-   *PORT(CONFIG_NAND_GPIO_PORT, _FER) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_DIR) = ~BFIN_NAND_READY;
-   *PORT(CONFIG_NAND_GPIO_PORT, IO_INEN) |= BFIN_NAND_READY;
-
-   nand-cmd_ctrl = bfin_hwcontrol;
-   nand-ecc.mode = NAND_ECC_SOFT;
-   nand-dev_ready = bfin_device_ready;
-

Re: [U-Boot] MII register display

2009-05-06 Thread Jon Smirl

On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsm...@gmail.com wrote:
 Why is speed selection = 10 Mbps when both sides support 100Mb?
 Is uboot decoding this register correctly?

 uboot mii dump 0 0
 0.     (1000)                 -- PHY control register --
  (8000:) 0.15    =     0    reset
  (4000:) 0.14    =     0    loopback
  (2040:) 0. 6,13 =   b00    speed selection = 10 Mbps

This b00 here is confusing. b is a valid hex character, I thought this
was reporting the register value as 0xb00.
Instead it appears to be trying to indicate that the two bits are binary?


  (1000:1000) 0.12    =     1    A/N enable
  (0800:) 0.11    =     0    power-down
  (0400:) 0.10    =     0    isolate
  (0200:) 0. 9    =     0    restart A/N
  (0100:) 0. 8    =     0    duplex = half
  (0080:) 0. 7    =     0    collision test enable
  (003f:) 0. 5- 0 =     0    (reserved)

 Definition from Linux:

 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
 #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
 #define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
 #define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
 #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
 #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
 #define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
 #define BMCR_RESET              0x8000  /* Reset the DP83840           */




 uboot mii dump 0 1
 1.     (786d)                 -- PHY status register --
  (8000:) 1.15    =     0    100BASE-T4 able
  (4000:4000) 1.14    =     1    100BASE-X  full duplex able
  (2000:2000) 1.13    =     1    100BASE-X  half duplex able
  (1000:1000) 1.12    =     1    10 Mbps    full duplex able
  (0800:0800) 1.11    =     1    10 Mbps    half duplex able
  (0400:) 1.10    =     0    100BASE-T2 full duplex able
  (0200:) 1. 9    =     0    100BASE-T2 half duplex able
  (0100:) 1. 8    =     0    extended status
  (0080:) 1. 7    =     0    (reserved)
  (0040:0040) 1. 6    =     1    MF preamble suppression
  (0020:0020) 1. 5    =     1    A/N complete
  (0010:) 1. 4    =     0    remote fault
  (0008:0008) 1. 3    =     1    A/N able
  (0004:0004) 1. 2    =     1    link status
  (0002:) 1. 1    =     0    jabber detect
  (0001:0001) 1. 0    =     1    extended capabilities


 uboot mii dump 0 2
 2.     (0022)                 -- PHY ID 1 register --
  (:0022) 2.15- 0 =    34    OUI portion


 uboot mii dump 0 3
 3.     (161a)                 -- PHY ID 2 register --
  (fc00:1400) 3.15-10 =     5    OUI portion
  (03f0:0210) 3. 9- 4 =    33    manufacturer part number
  (000f:000a) 3. 3- 0 =    10    manufacturer rev. number


 uboot mii dump 0 4
 4.     (01e1)                 -- Autonegotiation advertisement register --
  (8000:) 4.15    =     0    next page able
  (4000:) 4.14    =     0    reserved
  (2000:) 4.13    =     0    remote fault
  (1000:) 4.12    =     0    reserved
  (0800:) 4.11    =     0    asymmetric pause
  (0400:) 4.10    =     0    pause enable
  (0200:) 4. 9    =     0    100BASE-T4 able
  (0100:0100) 4. 8    =     1    100BASE-TX full duplex able
  (0080:0080) 4. 7    =     1    100BASE-TX able
  (0040:0040) 4. 6    =     1    10BASE-T   full duplex able
  (0020:0020) 4. 5    =     1    10BASE-T   able
  (001f:0001) 4. 4- 0 =     1    selector = IEEE 802.3


 uboot mii dump 0 5
 5.     (c5e1)                 -- Autonegotiation partner abilities register --
  (8000:8000) 5.15    =     1    next page able
  (4000:4000) 5.14    =     1    acknowledge
  (2000:) 5.13    =     0    remote fault
  (1000:) 5.12    =     0    (reserved)
  (0800:) 5.11    =     0    asymmetric pause able
  (0400:0400) 5.10    =     1    pause able
  (0200:) 5. 9    =     0    100BASE-T4 able
  (0100:0100) 5. 8    =     1    100BASE-X full duplex able
  (0080:0080) 5. 7    =     1    100BASE-TX able
  (0040:0040) 5. 6    =     1    10BASE-T full duplex able
  (0020:0020) 5. 5    =     1    10BASE-T able
  (001f:0001) 5. 4- 0 =     1    selector = IEEE 802.3


 uboot


 --
 Jon Smirl
 jonsm...@gmail.com




-- 
Jon Smirl
jonsm...@gmail.com
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Re: [U-Boot] MII register display

2009-05-06 Thread Jon Smirl

On Wed, May 6, 2009 at 10:03 PM, Mike Frysinger vap...@gentoo.org wrote:
 On Wednesday 06 May 2009 21:53:21 Jon Smirl wrote:
 On Wed, May 6, 2009 at 2:57 PM, Jon Smirl jonsm...@gmail.com wrote:
  Why is speed selection = 10 Mbps when both sides support 100Mb?
  Is uboot decoding this register correctly?
 
  uboot mii dump 0 0
  0.     (1000)                 -- PHY control register --
   (8000:) 0.15    =     0    reset
   (4000:) 0.14    =     0    loopback
   (2040:) 0. 6,13 =   b00    speed selection = 10 Mbps

 This b00 here is confusing. b is a valid hex character, I thought this
 was reporting the register value as 0xb00.
 Instead it appears to be trying to indicate that the two bits are binary?

 looks that way.  it's showing bit6 and bit13.

It's in the source that way. It just confused me when trying to figure
out what is wrong with the new PHY we're having hardware trouble with.

I still haven't figure out why speed selection is 10Mb when the
auto-negotiate came up with 100Mb.

if ((regno == 0)  (pdesc-lo == 6)) {
ushort speed_bits = regval  PHY_BMCR_SPEED_MASK;
printf(%2u,%2u =   b%u%uspeed selection = %s Mbps,
6, 13,
(regval   6)  1,
(regval  13)  1,
speed_bits == PHY_BMCR_1000_MBPS ? 1000 :
speed_bits == PHY_BMCR_100_MBPS  ? 100 :
speed_bits == PHY_BMCR_10_MBPS   ? 10 :
???);
return 1;
}



 -mike




-- 
Jon Smirl
jonsm...@gmail.com
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Re: [U-Boot] MII register display