Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
Dear Wolfgang,
On Tuesday 21 June 2011 11:19 AM, Aneesh V wrote:
Dear Wolfgang,
On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
[snip ..]
+static const u32 clk_modules_hw_auto_essential[] = {
+ CM_WKUP_GPIO1_CLKCTRL,
+ CM_L4PER_GPIO2_CLKCTRL,
+ CM_L4PER_GPIO3_CLKCTRL,
+ CM_L4PER_GPIO4_CLKCTRL,
+ CM_L4PER_GPIO5_CLKCTRL,
+ CM_L4PER_GPIO6_CLKCTRL,
+ CM_MEMIF_EMIF_1_CLKCTRL,
+ CM_MEMIF_EMIF_2_CLKCTRL,
+ CM_L3INIT_HSUSBOTG_CLKCTRL,
+ CM_L3INIT_USBPHY_CLKCTRL,
+ CM_L4CFG_L4_CFG_CLKCTRL,
+ 0
+};
In this series you asked me to convert the base + offset mode of
register address definition to struct based register address
definition. While doing this I am facing a problem. Please note the
above array that contain register addresses. This is a group of
registers that control our clock modules. All these registers have
similar bit fields and they can be programmed in same manner. So, I
keep them in an array and pass the array to a function that iterates
through array and does similar processing on all the registers(see
below).
I am finding it difficult to implement this using the struct based
approach. I tried the sample code below:
struct my_regs_struct {
const unsigned int reg1;
const unsigned int reg2;
const unsigned int reg3;
};
static struct my_regs_struct *const my_regs = (struct my_regs_struct
*)0x1000;
static unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3
};
Apologies for the hasty mail. Looks like I can solve it by doing
something like:
static unsigned int *const reg_arr[] = {
(((struct my_regs_struct *)0x1000)-reg1),
(((struct my_regs_struct *)0x1000)-reg3),
};
Analyzing this further right now. Hopefully, the issue can be solved
cleanly.
best regards,
Aneesh
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Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
Dear Aneesh V,
In message 4e0030f8.6030...@ti.com you wrote:
I am finding it difficult to implement this using the struct based
approach. I tried the sample code below:
struct my_regs_struct {
const unsigned int reg1;
const unsigned int reg2;
const unsigned int reg3;
};
static struct my_regs_struct *const my_regs = (struct my_regs_struct
*)0x1000;
static unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3
};
void main(void)
{
printf(regs %x %x \n, reg_arr[0], reg_arr[1]);
}
Sorry, but I fail to understand the problem. Why is reg_arr[] needed?
Why don't you use
struct my_regs_struct {
const unsigned int reg[3];
};
?
Best regards,
Wolfgang Denk
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
But it's real. And if it's real it can be affected ... we may not be
able to break it, but, I'll bet you credits to Navy Beans we can put
a dent in it.
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Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
On Tuesday 21 June 2011 12:35 PM, Wolfgang Denk wrote:
Dear Aneesh V,
In message4e0030f8.6030...@ti.com you wrote:
I am finding it difficult to implement this using the struct based
approach. I tried the sample code below:
struct my_regs_struct {
const unsigned int reg1;
const unsigned int reg2;
const unsigned int reg3;
};
The const for structure fields above were not intended. I put them
while debugging this issue and forgot to remove later.
static struct my_regs_struct *const my_regs = (struct my_regs_struct
*)0x1000;
static unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3
};
void main(void)
{
printf(regs %x %x \n, reg_arr[0], reg_arr[1]);
}
Sorry, but I fail to understand the problem. Why is reg_arr[] needed?
Why don't you use
struct my_regs_struct {
const unsigned int reg[3];
};
?
I want a number of register addresses in an array - an array of
constant pointers. The array is populated at compile time with the
addresses of all the modules that need to be initialized. At run-time I
do a specific operation on all the registers given in this array.
best regards,
Aneesh
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Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
On Tuesday 21 June 2011 11:55 AM, Aneesh V wrote:
Dear Wolfgang,
On Tuesday 21 June 2011 11:19 AM, Aneesh V wrote:
Dear Wolfgang,
On Sunday 15 May 2011 08:51 PM, Aneesh V wrote:
[snip ..]
+static const u32 clk_modules_hw_auto_essential[] = {
+ CM_WKUP_GPIO1_CLKCTRL,
+ CM_L4PER_GPIO2_CLKCTRL,
+ CM_L4PER_GPIO3_CLKCTRL,
+ CM_L4PER_GPIO4_CLKCTRL,
+ CM_L4PER_GPIO5_CLKCTRL,
+ CM_L4PER_GPIO6_CLKCTRL,
+ CM_MEMIF_EMIF_1_CLKCTRL,
+ CM_MEMIF_EMIF_2_CLKCTRL,
+ CM_L3INIT_HSUSBOTG_CLKCTRL,
+ CM_L3INIT_USBPHY_CLKCTRL,
+ CM_L4CFG_L4_CFG_CLKCTRL,
+ 0
+};
In this series you asked me to convert the base + offset mode of
register address definition to struct based register address
definition. While doing this I am facing a problem. Please note the
above array that contain register addresses. This is a group of
registers that control our clock modules. All these registers have
similar bit fields and they can be programmed in same manner. So, I
keep them in an array and pass the array to a function that iterates
through array and does similar processing on all the registers(see
below).
I am finding it difficult to implement this using the struct based
approach. I tried the sample code below:
struct my_regs_struct {
const unsigned int reg1;
const unsigned int reg2;
const unsigned int reg3;
};
static struct my_regs_struct *const my_regs = (struct my_regs_struct
*)0x1000;
static unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3
};
Apologies for the hasty mail. Looks like I can solve it by doing
something like:
static unsigned int *const reg_arr[] = {
(((struct my_regs_struct *)0x1000)-reg1),
(((struct my_regs_struct *)0x1000)-reg3),
};
Analyzing this further right now. Hopefully, the issue can be solved
cleanly.
Some more interesting information:
I can reproduce the problem with something as simple as this:
main.c:
const int const1 = 10;
const int const2 = 11;
int arr[] = {
const1,
const2
};
$ gcc main.c
main.c:5: error: initializer element is not constant
main.c:5: error: (near initialization for ‘arr[0]’)
main.c:7: error: initializer element is not constant
main.c:7: error: (near initialization for ‘arr[1]’)
The ARM compiler RVCT happily compiles this without an issue. GCC and
Visual C++ compilers fail!
As a result, I will have to do something like this to populate my
array:
static unsigned int *const reg_arr[] = {
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-uart_clkctrl),
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-i2c_clkctrl),
};
Is this acceptable?
best regards,
Aneesh
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Re: [U-Boot] da850evm: u-boot does not start without UBL since commit f1d2b313c9eb6808d30c16a9eb5251240452a56c
Hello Christian, Sorry for the late answer ... Wolfgang Denk wrote: Dear Christian Riesch, In message banlktimhjss_urkzb-q5y7gqzawswe0...@mail.gmail.com you wrote: What is AIS ? I apologize for using that many abbreviations in my mail and not explaining them :-/ AIS is short for Application Image Script [1]. It is a boot script that is processed by the ROM bootloader on Texas Instrument's AM1808/DA850/OMAP-L138 processors. The script allows configuration of boot modes, PLLs, DDR memory, Pinmuxes etc and loading the an application like u-boot from flash to RAM and executing it. Using a suitable AIS one can configure PLL and DDR memory and then directly start u-boot on these processors, without using Texas Instruments's user boot loader (UBL) [2]. In the default configuration of the da850evm the boot sequence is like this: 1) ROM bootloader (RBL): starts reading from flash 2) In the SPI-flash, a very simple AIS is present. This AIS tells the RBL to load the UBL from flash and to start it. 3) The UBL does a lot of hardware initialization and then loads u-boot from flash and starts it. Ok. 4) u-boot does a lot of hardware initialization that has already been done by the UBL and then loads the Linux kernel. Hmm.. why does U-Boot code again such initialization? This is wrong ... this should be cleaned up! Ok, I do actually a similiar job for an TI DM368 based board, booting from NAND flash. I am using instead the UBL, now the nand_spl code from u-boot, bootsequence is: 1) ROM bootloader (RBL) searches for an UBL Header in NAND, which contains the info where to find in the NAND flash the UBL (User Boot Loader). If such an header is found: 2) loading the UBL(now nand_spl code) from NAND to internal RAM and start executing it. 3) The UBL (nand_spl code) inits RAM, clocks... and loads U-Boot from NAND to RAM and jumps to it ... So I actually create with make board_config an u-boot.ubl image, which contains this ubl header(created with mkimage), nand_spl code and u-boot, burn this into nand, and boot it ... For my application I would like to get rid of the UBL since most of the configuration it does is also done by u-boot (although there seems to be a bug in it) or can be done by AIS (like PLL and DDR memory configuration), the resulting boot sequence will be: 1) ROM bootloader (RBL): starts reading from flash How detects the RBL that there is something in the SPI flash, isn;t there such a header like on the DM368? Ah, looked in [1] and there is nothing similiar ... 2) In the SPI-flash, an AIS is present. This AIS tells the RBL to configure PLLs and DDR memory and to load u-boot from flash and to start it. Maybe you can use here the simple AIS header as above in step 2 (maybe create this simple header with the mkimage tool?) and use something like the nand_spl code calling it spi_spl which do all necessary setups (DDR, PLL,...) in C-Code? So we can get rid off this external AIS tool, UBL and do *all* things in/with U-boot? Please look also into the SPL framework re-design thread. 3) u-boot loads the Linux kernel. bye, Heiko [1]: http://focus.ti.com/lit/an/spraba5a/spraba5a.pdf -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
Dear Aneesh,
In message 4e00447b.9070...@ti.com you wrote:
$ gcc main.c
main.c:5: error: initializer element is not constant
main.c:5: error: (near initialization for arr[0])
main.c:7: error: initializer element is not constant
main.c:7: error: (near initialization for arr[1])
I have to admit that I don't understand either why this error is
raised here; after all, from our understanding of the code these _are_
constant addresses.
You may want to ask this in a compiler group...
As a result, I will have to do something like this to populate my
array:
static unsigned int *const reg_arr[] = {
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-uart_clkctrl),
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-i2c_clkctrl),
};
Is this acceptable?
No, please don't.
Note that the following code compiles fine:
- snip -
#include stdio.h
struct my_regs_struct {
unsigned int reg1;
unsigned int reg2;
unsigned int reg3;
};
static struct my_regs_struct *const my_regs = (struct my_regs_struct *) 0x1000;
static void print_regs(void)
{
unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3,
};
printf(regs %p %p \n, (void *)reg_arr[0], (void *)reg_arr[1]);
}
int main(void)
{
print_regs();
return 0;
}
- snip -
With gcc -Wall -pedantic you will get warnings initializer element
is not computable at load time [enabled by default], but this can be
avoided by adding --std=c99 to the compiler options.
Best regards,
Wolfgang Denk
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
Wish not to seem, but to be, the best. - Aeschylus
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Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
On Tuesday 21 June 2011 01:50 PM, Wolfgang Denk wrote:
Dear Aneesh,
In message4e00447b.9070...@ti.com you wrote:
$ gcc main.c
main.c:5: error: initializer element is not constant
main.c:5: error: (near initialization for ‘arr[0]’)
main.c:7: error: initializer element is not constant
main.c:7: error: (near initialization for ‘arr[1]’)
I have to admit that I don't understand either why this error is
raised here; after all, from our understanding of the code these _are_
constant addresses.
You may want to ask this in a compiler group...
Yes. I will.
As a result, I will have to do something like this to populate my
array:
static unsigned int *const reg_arr[] = {
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-uart_clkctrl),
(((struct my_regs_struct *const)OMAP4_PRCM_REG_BASE)-i2c_clkctrl),
};
Is this acceptable?
No, please don't.
Note that the following code compiles fine:
- snip -
#includestdio.h
struct my_regs_struct {
unsigned int reg1;
unsigned int reg2;
unsigned int reg3;
};
static struct my_regs_struct *const my_regs = (struct my_regs_struct *)
0x1000;
static void print_regs(void)
{
unsigned int *const reg_arr[] = {
my_regs-reg1,
my_regs-reg3,
};
printf(regs %p %p \n, (void *)reg_arr[0], (void *)reg_arr[1]);
}
In my function I am using 3 such arrays with quite a few entries in
them. Won't it look ugly besides increasing the stack footprint.
Of course, I can try to break them down to different functions, if need
be.
Or, how about using a utility macro and make it look better like this:
#define OMAP4_PRCM_REG_ADDR(reg)\
struct my_regs_struct *)OMAP4_PRCM_BASE)-reg))
static unsigned int *const reg_arr[] = {
OMAP4_PRCM_REG_ADDR(uart_clkctrl),
OMAP4_PRCM_REG_ADDR(i2c_clkctrl)
};
This one doesn't generate any warning even with 'gcc -Wall -pedantic'.
Are you not comfortable with getting the address in this manner at all?
best regards,
Aneesh
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Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
Dear Aneesh V, In message 4e005f9e.8050...@ti.com you wrote: In my function I am using 3 such arrays with quite a few entries in them. Won't it look ugly besides increasing the stack footprint. I don;t see a significant difference whether you declare these arrays inside a function or with file scope. Regarding the stack footprint: this would actually even be preferrable (assuming this code is run after relocation to RAM), and from what I've seen in the example, the compiler actually optimizes the code and does not really allocate such an array if you don't use it otherwise (like passing it to other functions). Or, how about using a utility macro and make it look better like this: #define OMAP4_PRCM_REG_ADDR(reg)\ struct my_regs_struct *)OMAP4_PRCM_BASE)-reg)) I consider this code too ugly. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Plan to throw one away. You will anyway. - Fred Brooks, The Mythical Man Month ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] SPL framework re-design
Dear Wolfgang,
On Friday 17 June 2011 10:18 PM, Aneesh V wrote:
Dear Wolfgang,
Here is a crude implementation of the top-down approach you had been
suggesting (or my interpretation of it). This is not complete yet and
serves only as a material for further discussions on this topic.
Here is an updated version of my prototype implementation with fixes
for some issues pointed out by Scott. Please let me know your views
about this.
---
Makefile|5 ++
include/configs/omap4_sdp4430.h |1 +
spl/Makefile| 94
+++
spl/mmc/Makefile| 55 +++
4 files changed, 155 insertions(+), 0 deletions(-)
create mode 100644 spl/Makefile
create mode 100644 spl/mmc/Makefile
diff --git a/Makefile b/Makefile
index 8540e39..0321634 100644
--- a/Makefile
+++ b/Makefile
@@ -316,6 +316,7 @@ BOARD_SIZE_CHECK =
endif
# Always append ALL so that arch config.mk's can add custom ones
+ALL += spl
ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
ifeq ($(CONFIG_NAND_U_BOOT),y)
@@ -428,6 +429,9 @@ $(obj)u-boot-onenand.bin: onenand_ipl $(obj)u-boot.bin
mmc_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C mmc_spl/board/$(BOARDDIR) all
+spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
+ $(MAKE) -C spl/ all
+
$(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl
$(VERSION_FILE):
@@ -1142,6 +1146,7 @@ clean:
@rm -f $(obj)spl/{u-boot-spl-generated.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)onenand_ipl/onenand-{ipl,ipl.bin,ipl.map}
@rm -f
$(obj)mmc_spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
+ @rm -f
$(obj)spl/{u-boot.lds,u-boot-spl,u-boot-spl.map,u-boot-spl.bin,u-boot-mmc-spl.bin}
@rm -f $(ONENAND_BIN)
@rm -f $(obj)onenand_ipl/u-boot.lds
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
diff --git a/include/configs/omap4_sdp4430.h
b/include/configs/omap4_sdp4430.h
index c424951..c9adc3c 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -257,4 +257,5 @@
/* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM */
#define CONFIG_SYS_TEXT_BASE 0x8010
+#define CONFIG_SYS_SPL_MMC_SUPPORT
#endif /* __CONFIG_H */
diff --git a/spl/Makefile b/spl/Makefile
new file mode 100644
index 000..9e3a5b1
--- /dev/null
+++ b/spl/Makefile
@@ -0,0 +1,94 @@
+#
+# (C) Copyright 2011 Daniel Schwierzeck, daniel.schwierz...@googlemail.com.
+#
+# This file is released under the terms of GPL v2 and any later version.
+# See the file COPYING in the root directory of the source tree for
details.
+#
+
+include $(TOPDIR)/config.mk
+LIBS-$(CONFIG_SYS_SPL_MMC_SUPPORT) = mmc/libmmc.o
+LIBS-$(CONFIG_SYS_SPL_FAT_SUPPORT) += fat/libfat.o
+LIBS-$(CONFIG_SYS_SPL_NAND_SUPPORT) += nand/libnand.o
+LIBS-$(CONFIG_SYS_SPL_ONENAND_SUPPORT) += onenand/libonenand.o
+
+LIBS-y += $(shell if [ -f $(ARCH)/Makefile ]; then echo \
+ $(ARCH)/lib$(ARCH).o; fi)
+LIBS-y += $(shell if [ -f $(ARCH)/$(CPU)/Makefile ]; then echo \
+ $(ARCH)/$(CPU)/lib$(CPU).o; fi)
+LIBS-y += $(shell if [ -f $(ARCH)/$(CPU)/$(SOC)/Makefile ]; then echo \
+ $(ARCH)/$(CPU)/$(SOC)/lib$(SOC).o; fi)
+LIBS-y += $(shell if [ -f $(ARCH)/$(CPU)/$(SOC)/$(BOARD)/Makefile ];
then echo \
+ $(ARCH)/$(CPU)/$(SOC)/$(BOARD)/lib$(BOARD).o; fi)
+
+LIBS-y := $(addprefix $(obj),$(sort $(LIBS-y)))
+
+__LIBS := $(subst $(obj),,$(LIBS-y))
+
+ifndef SPL_LDSCRIPT
+ ifdef CONFIG_SYS_SPL_LDSCRIPT
+ # need to strip off double quotes
+ SPL_LDSCRIPT := $(subst ,,$(CONFIG_SYS_SPL_LDSCRIPT))
+ endif
+endif
+
+ifndef SPL_LDSCRIPT
+ ifeq ($(wildcard $(SPL_LDSCRIPT)),)
+ SPL_LDSCRIPT :=
$(TOPDIR)/spl/$(ARCH)/$(CPU)/$(SOC)/$(BOARDDIR)/u-boot-spl.lds
+ endif
+ ifeq ($(wildcard $(SPL_LDSCRIPT)),)
+ SPL_LDSCRIPT :=
$(TOPDIR)/spl/$(ARCH)/$(CPU)/$(SOC)/u-boot-spl.lds
+ endif
+ ifeq ($(wildcard $(SPL_LDSCRIPT)),)
+ SPL_LDSCRIPT := $(TOPDIR)/spl/$(ARCH)/$(CPU)/u-boot-spl.lds
+ endif
+ ifeq ($(wildcard $(SPL_LDSCRIPT)),)
+$(error could not find linker script)
+ endif
+endif
+LNDIR := $(OBJTREE)/spl
+
+# Special flags for CPP when processing the linker script.
+# Pass the version down so we can handle backwards compatibility
+# on the fly.
+LDPPFLAGS += \
+ -include $(TOPDIR)/include/u-boot/u-boot.lds.h \
+ $(shell $(LD) --version | \
+ sed -ne 's/GNU ld version
\([0-9][0-9]*\)\.\([0-9][0-9]*\).*/-DLD_MAJOR=\1 -DLD_MINOR=\2/p')
+
+ALL= $(obj)u-boot-spl.bin
+
+all: $(ALL)
+
+$(obj)u-boot-spl.bin: $(obj)u-boot-spl
+ $(OBJCOPY) $(OBJCFLAGS) -O binary $ $@
+
+GEN_UBOOT = \
+ UNDEF_SYM=`$(OBJDUMP) -x $(LIBS-y) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) $(LD) $(LDFLAGS)
Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
On Tuesday 21 June 2011 03:52 PM, Wolfgang Denk wrote: Dear Aneesh V, In message4e005f9e.8050...@ti.com you wrote: In my function I am using 3 such arrays with quite a few entries in them. Won't it look ugly besides increasing the stack footprint. I don;t see a significant difference whether you declare these arrays inside a function or with file scope. Regarding the stack footprint: this would actually even be preferrable (assuming this code is run after relocation to RAM), and from what Indeed this runs before relocation. But I think I can keep the array size to a reasonable level by splitting the function. Also, as you said if the array is optimized out there should not be any problem. best regards, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 13/22] omap4: add clock support
On Tuesday 21 June 2011 02:38 PM, Aneesh V wrote: On Tuesday 21 June 2011 01:50 PM, Wolfgang Denk wrote: Dear Aneesh, In message4e00447b.9070...@ti.com you wrote: $ gcc main.c main.c:5: error: initializer element is not constant main.c:5: error: (near initialization for ‘arr[0]’) main.c:7: error: initializer element is not constant main.c:7: error: (near initialization for ‘arr[1]’) I have to admit that I don't understand either why this error is raised here; after all, from our understanding of the code these _are_ constant addresses. You may want to ask this in a compiler group... Yes. I will. I asked in the GCC mailing list and got this reply. That also seems to explain why the array as a local variable worked. http://gcc.gnu.org/ml/gcc/2011-06/msg00291.html best regards, Aneesh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] omap3: Include array definition only when it is used
The array of strings corresponding to cpu revision is
used only when CONFIG_DISPLAY_CPUINFO is selected - in
the function print_cpuinfo().
Enclose definition of this array in #ifdef...#endif for
the same.
Signed-off-by: Sanjeev Premi pr...@ti.com
---
arch/arm/cpu/armv7/omap3/sys_info.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sys_info.c
b/arch/arm/cpu/armv7/omap3/sys_info.c
index 549ac19..8d0496c 100644
--- a/arch/arm/cpu/armv7/omap3/sys_info.c
+++ b/arch/arm/cpu/armv7/omap3/sys_info.c
@@ -33,6 +33,8 @@
extern omap3_sysinfo sysinfo;
static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+#ifdef CONFIG_DISPLAY_CPUINFO
static char *rev_s[CPU_3XX_MAX_REV] = {
1.0,
2.0,
@@ -42,6 +44,7 @@ static char *rev_s[CPU_3XX_MAX_REV] = {
UNKNOWN,
UNKNOWN,
3.1.2};
+#endif /* CONFIG_DISPLAY_CPUINFO */
/*
* dieid_num_r(void) - read and set die ID
--
1.7.2.2
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Re: [U-Boot] at91rm9200 linking problem (?)
To compile it I also had to add 3 macros to the configuration file: CONFIG_SYS_INIT_RAM_ADDR, Why this? I guess you mean CONFIG_SYS_SDRAM_BASE here. Yes, my mistake. CONFIG_SYS_INIT_RAM_SIZE and CONFIG_SYS_INIT_SP_ADDR. Can this cause this problem? SYS_INIT_SP_ADDR is required, if you see 'DRAM: ...' output it is likely to be a correct value for you. I guess your gd_t parameters for SDRAM size are not correct which leads to a wrong relocation address and therefore relocate_code() fails. Yes, I've fixed gd_t parameter but the result hasn't changed. All behaviour described so far relates to at91rm9200dk board. You mentioned trying at91rm9200ek board, so I switched to it, but I have problems with with compilation when data flash memory is used (I need it to store environment settings). So I tried not to store environment settings by defining CONFIG_ENV_IS_IN_NOWHERE and comment out all data flash configs, but I end up with multiple undefined references (to flash, spi and dataflash). How did you make your board to run only in RAM omitting flash configuration? regards, Marcin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] at91rm9200 linking problem (?)
Dear Marcin Górski, Am 21.06.2011 15:19, schrieb Marcin Górski: CONFIG_SYS_INIT_RAM_SIZE and CONFIG_SYS_INIT_SP_ADDR. Can this cause this problem? SYS_INIT_SP_ADDR is required, if you see 'DRAM: ...' output it is likely to be a correct value for you. I guess your gd_t parameters for SDRAM size are not correct which leads to a wrong relocation address and therefore relocate_code() fails. Yes, I've fixed gd_t parameter but the result hasn't changed. Ok ... can you debug the board_init_f/relocate_code/board_init_r functions? Where is your relocate_code() destination address (it is calculated in board_init_f())? Is relocate_code() reached? Does the fixup loop's run? (don't forget to reload symbol file as described in doc/README.arm-relocation) Is board_init_r() reached? ... All behaviour described so far relates to at91rm9200dk board. at91rm9200dk uses the deprecated arm920t/at91rm9200 stuff and is known to be broken currently! The arm920t/at91rm9200 code will be deleted in near future! (and so at91rm9200dk board, if you have one handy please try to get it working with arm920t/at91 files). If your board uses arm920t/at91rm9200 configuration please convert it to arm920t/at91 ASAP! You mentioned trying at91rm9200ek board, so I switched to it, but I have problems with with compilation when data flash memory is used (I need it to store environment settings). Sorry, I can not help here cause I didn't get dataflash working with at91rm9200ek yet. So I tried not to store environment settings by defining CONFIG_ENV_IS_IN_NOWHERE and comment out all data flash configs, but I end up with multiple undefined references (to flash, spi and dataflash). How did you make your board to run only in RAM omitting flash configuration? Well I own an at91rm9200ek and use the at91rm9200ek_ram_config to build (is mainline). The NOR flash booting is currently broken but getting this working is my next target. Dataflash for at91 targets in principle is currently somewhat broken/unreliable/defective API (there was a discussion these days, search the list). regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] System Administrator
Your Mailbox Has Exceeded It Storage Limit As Set By Your Administrator, To Re-Validate - Click Here:https://spreadsheets.google.com/spreadsheet/viewform?formkey=dGVUdXdjdXRUenJ4cE9PZW5PN01Damc6MQ System Administrator. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Don't do an undefined 32-bit shift on a 32-bit value for a long (4 byte) itest.l command.
On Wed, Jun 15, 2011 at 19:10, Joshua Radel wrote:
Without this fix, the following statement erroneously echoed true (at least
on the microblaze architecture):
if itest.l 0 == 1; then echo true; else echo false; fi
(using itest.w or itest.b worked as expected even without this change)
the subject should read something like:
itest: avoid undefined C semantics with large shift values
Signed-off-by: Josh Radel josh.radel_at_intusurg.com
your s-o-b tag is invalid. you must have a proper e-mail address here.
mode change 100644 = 100755 common/cmd_itest.c
this is wrong. i guess you're editing on a windows machine or
something. no .c file should be executable.
- return (l ((1 (w * 8)) - 1));
+ if (w sizeof(long)) {
+ return (l ((1 (w * 8)) - 1));
+ } else {
+ return (l);
+ }
please add a comment as to why the sizeof(long) test is here. i dont
think most people reading the code at a glance will grok what it's
doing.
-mike
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Re: [U-Boot] [GIT pull] Please pull u-boot-mpc85xx
Dear Kumar Gala, In message alpine.lfd.2.00.1106091556160.27...@right.am.freescale.net you wrote: Merge branch 'master' of git://git.denx.de/u-boot-arm (2011-06-08 23:29:04 +0200) are available in the git repository at: git://git.denx.de/u-boot-mpc85xx master Timur Tabi (1): powerpc/p1022ds: set the clock-frequency prop only if the clock is enabled board/freescale/p1022ds/p1022ds.c | 16 ++-- 1 files changed, 10 insertions(+), 6 deletions(-) Applied, thanks. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Es ist nicht genug zu wissen, man muß auch anwenden; es ist nicht ge- nug zu wollen, man muß auch tun. -- Goethe, Maximen und Reflexionen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-arm/master
Hi Wolfgang, The following changes since commit 29b83d983392fcb5378b915ee2112bb48b8c05be: powerpc/p1022ds: set the clock-frequency prop only if the clock is enabled (2011-06-09 15:53:38 -0500) are available in the git repository at: git://git.denx.de/u-boot-arm.git master Aneesh V (6): omap1610h2: fix build breaks omap5912osk: fix build breaks omap1510inn: fix build breaks omap1610inn: fix build breaks omap2420h4: fix build breaks omap730p2: fix build breaks Eric Benard (4): arm926ejs/at91/lowlevel_init.S: fix defines cpu9260/9G20: fix board support cpuat91: fix board support include/asm/arch-at91: update several .h files to ATMEL_xxx name scheme Fabio Estevam (3): mx1ads: Fix build by using new relocation scheme imx31_phycore: Fix build by using new relocation scheme mx31pdk: Add DHCP command Helmut Raiger (1): mxc_spi.c: typo fixed Jens Scharsig (1): update arm/at91rm9200 work with rework rework110202 Reinhard Meyer (3): AT91 rework: fix at91sam(9260/9g20/9xe)ek board port to build again: AT91 rework: fix TOP9000 files to build again ATMEL spi_dataflash driver - fix to build again Ryan Mallon (1): Add support for Bluewater Systems Snapper 9260/9G20 modules Sergey Lapin (1): Build fix/update of AFEB9260 Stefano Babic (1): MX31: QONG: drop config.mk andreas.de...@googlemail.com (2): at91_emac: fix compile warning macb: fix compile warning MAINTAINERS |5 + MAKEALL |3 - Makefile | 45 - arch/arm/cpu/arm920t/at91/reset.c|2 +- arch/arm/cpu/arm920t/at91/timer.c| 12 +- arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 24 ++-- arch/arm/include/asm/arch-at91/at91_matrix.h | 10 +- arch/arm/include/asm/arch-at91/at91_mc.h | 12 +- arch/arm/include/asm/arch-at91/at91_pio.h| 14 +- arch/arm/include/asm/arch-at91/at91_pmc.h| 10 +- arch/arm/include/asm/arch-at91/at91_rstc.h |2 +- arch/arm/include/asm/arch-at91/at91_wdt.h|2 +- arch/arm/include/asm/arch-at91/at91rm9200.h | 209 -- arch/arm/include/asm/arch-at91/at91sam9260.h |1 + arch/arm/include/asm/arch-at91/at91sam9261.h |1 + arch/arm/include/asm/arch-at91/at91sam9263.h |1 + arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 30 ++-- arch/arm/include/asm/arch-at91/at91sam9_smc.h| 12 +- board/BuS/eb_cpux9k2/cpux9k2.c | 52 +++--- board/afeb9260/afeb9260.c| 101 ++- board/atmel/at91rm9200ek/at91rm9200ek.c |4 +- board/atmel/at91rm9200ek/led.c | 22 ++- board/atmel/at91sam9260ek/at91sam9260ek.c| 127 +++-- board/atmel/at91sam9260ek/config.mk |1 - board/atmel/at91sam9260ek/led.c |8 +- board/bluewater/snapper9260/Makefile | 53 ++ board/bluewater/snapper9260/snapper9260.c| 169 + board/davedenx/qong/config.mk|3 - board/emk/top9000/top9000.c | 64 --- board/eukrea/cpu9260/cpu9260.c | 33 ++-- board/eukrea/cpu9260/led.c |6 +- board/eukrea/cpuat91/cpuat91.c |6 +- board/imx31_phycore/config.mk|1 - board/imx31_phycore/imx31_phycore.c | 20 ++- board/mx1ads/config.mk | 25 --- board/mx1ads/mx1ads.c| 27 ++- boards.cfg |9 + drivers/net/at91_emac.c | 44 +++--- drivers/net/macb.c |5 +- drivers/spi/atmel_dataflash_spi.c|3 +- drivers/spi/mxc_spi.c|2 +- include/configs/afeb9260.h | 78 + include/configs/at91rm9200ek.h |5 +- include/configs/at91sam9260ek.h | 107 +++- include/configs/cpu9260.h| 11 +- include/configs/eb_cpux9k2.h | 23 ++-- include/configs/imx31_phycore.h | 12 ++ include/configs/mx1ads.h | 10 + include/configs/mx31pdk.h|1 + include/configs/omap1510inn.h|5 + include/configs/omap1610h2.h |5 + include/configs/omap1610inn.h|5 + include/configs/omap2420h4.h |4 + include/configs/omap5912osk.h|5 + include/configs/omap730p2.h |5 +
Re: [U-Boot] PCIe Configuration on MPC8544 processor
On Tue, Jun 21, 2011 at 9:27 PM, Swarthout Edward L-SWARTHOU swart...@freescale.com wrote: From: António Silva I am trying to activate a PCIe link between two MPC8544 processor's on a custom board. One processor is configured as Root Complex (cfg_host_agt[0:2] = '111') and the other processor as endpoint (cfg_host_agt[0:2] = '101'). I've done this with many different configurations. Only PCIe1 is active in both processors (cfg_IO_ports[0:2] = '010') In u-boot I set the following flags in both processors: #define CONFIG_PCI/* Enable PCI/PCIE */ #define CONFIG_PCIE1/* PCIE controler 1 (slot 1) */ //MJ #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ In the first processor (configured as RC) I get the following output: * pci_init_board: devdisr= 700 0008, io_sel=2, host_agent=7 Fine. PCIE1 connected to Slot2 as Root Complex (base address e000a000) PCIE link error. Skipping scan.LTSSM=0x00 As you note below, LTSSM zero is the issue. PCIE1 on bus 00 - 00* In the second processor (configured as EP) I get the following output: * pci_init_board: devdisr=708, io_sel=2, host_agent=5 **PCIE1 connected to Slot2 as End Point (base address e000a000) Scanning PCI bus 00 PCI Scan: Found Bus 0, Device 1, Function 0 00 01 1957 0033 0b20 00 The End Point should not scan the bus. Is this old u-boot code? Yes, I am using an old version of u-boot (version 1.15). It seems more straightforward to work. I've considered updating to the latest u-boot but since we had serious problems with DDR configuration and this has changed considerably since the version I am using I am a little reluctant into an update. Do you consider that a change to the latest version of u-boot would solve any problem? ... From the output of the RC processor: PCIE link error. Skipping scan.LTSSM=0x00 from table Table 18-109, the controller doesn't detect any activity on the bus. It is worse than that, a value of zero indicates the interface is either not wired, in reset, or has no clocks. A value of 8 means the end point's receiver's are detected, but has not trained yet. And 16 is good. Out of reset with no software support, it should go to 8 and then 16 when the end point responds. Hi, We've been checking the HW side and the clock of 100MHz is provided for both PCIe blocks. I've to check if the controller is in reset. I proceed trying to check in the HW for any activity in the PCIe bus. I don't see any activity in the bus from any of the processors. Both controller are getting the clock, and apart the PCIe detection both processor are working an proceed the booting stage. Is there any configuration missing in u-boot for the PCIe configuration? There is a controller reset for an errata workaround (see the setbits 0x0800 to pdb_stat). But if that was set, I'd expect different symptoms. I will check this workaround. Does anyone has any clue/hint to aid in the debugging process of the PCIe interface either for the SW and HW side? Thanks in advance, Antonio Thanks for your help. Regards ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] PCIe Configuration on MPC8544 processor
From: António Silva I am trying to activate a PCIe link between two MPC8544 processor's on a custom board. One processor is configured as Root Complex (cfg_host_agt[0:2] = '111') and the other processor as endpoint (cfg_host_agt[0:2] = '101'). I've done this with many different configurations. Only PCIe1 is active in both processors (cfg_IO_ports[0:2] = '010') In u-boot I set the following flags in both processors: #define CONFIG_PCI/* Enable PCI/PCIE */ #define CONFIG_PCIE1/* PCIE controler 1 (slot 1) */ //MJ #define CONFIG_FSL_PCI_INIT/* Use common FSL init code */ In the first processor (configured as RC) I get the following output: * pci_init_board: devdisr= 700 0008, io_sel=2, host_agent=7 Fine. PCIE1 connected to Slot2 as Root Complex (base address e000a000) PCIE link error. Skipping scan.LTSSM=0x00 As you note below, LTSSM zero is the issue. PCIE1 on bus 00 - 00* In the second processor (configured as EP) I get the following output: * pci_init_board: devdisr=708, io_sel=2, host_agent=5 **PCIE1 connected to Slot2 as End Point (base address e000a000) Scanning PCI bus 00 PCI Scan: Found Bus 0, Device 1, Function 0 00 01 1957 0033 0b20 00 The End Point should not scan the bus. Is this old u-boot code? ... From the output of the RC processor: PCIE link error. Skipping scan.LTSSM=0x00 from table Table 18-109, the controller doesn't detect any activity on the bus. It is worse than that, a value of zero indicates the interface is either not wired, in reset, or has no clocks. A value of 8 means the end point's receiver's are detected, but has not trained yet. And 16 is good. Out of reset with no software support, it should go to 8 and then 16 when the end point responds. I proceed trying to check in the HW for any activity in the PCIe bus. I don't see any activity in the bus from any of the processors. Both controller are getting the clock, and apart the PCIe detection both processor are working an proceed the booting stage. Is there any configuration missing in u-boot for the PCIe configuration? There is a controller reset for an errata workaround (see the setbits 0x0800 to pdb_stat). But if that was set, I'd expect different symptoms. Does anyone has any clue/hint to aid in the debugging process of the PCIe interface either for the SW and HW side? Thanks in advance, Antonio ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 0/5] Add Highbank platform
From: Rob Herring rob.herr...@calxeda.com This series enables non-PCI AHCI controllers and adds support for Calxeda Highbank platform which uses the AHCI changes. I've dropped my SDHCI changes as now there are 2 versions of common SDHCI code on the list and that needs sorting out. Wolfgang, Albert, Are there any more comments on these patches? If not, can you apply these to your trees for v2011.09? Rob Rob Herring (5): ARM: Add Calxeda Highbank platform arm: add __ilog2 function scsi/ahci: ata id little endian fix scsi/ahci: add support for non-PCI controllers ARM: highbank: Add AHCI support arch/arm/cpu/armv7/highbank/Makefile | 46 arch/arm/cpu/armv7/highbank/config.mk |4 + arch/arm/cpu/armv7/highbank/timer.c | 124 + arch/arm/include/asm/bitops.h |9 +++ board/highbank/Makefile | 49 + board/highbank/highbank.c | 58 +++ boards.cfg|1 + common/cmd_scsi.c |6 +- drivers/block/ahci.c | 72 --- include/ahci.h|4 + include/configs/highbank.h| 112 + include/scsi.h|1 + 12 files changed, 474 insertions(+), 12 deletions(-) create mode 100644 arch/arm/cpu/armv7/highbank/Makefile create mode 100644 arch/arm/cpu/armv7/highbank/config.mk create mode 100644 arch/arm/cpu/armv7/highbank/timer.c create mode 100644 board/highbank/Makefile create mode 100644 board/highbank/highbank.c create mode 100644 include/configs/highbank.h -- 1.7.4.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/5] arm: add __ilog2 function
From: Rob Herring rob.herr...@calxeda.com
Add __ilog2 function for ARM. Needed for ahci.c
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Albert ARIBAUD albert.arib...@free.fr
---
arch/arm/include/asm/bitops.h |9 +
1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index 270f163..0420182 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -106,6 +106,15 @@ static inline int test_bit(int nr, const void * addr)
return ((unsigned char *) addr)[nr 3] (1U (nr 7));
}
+extern __inline__ int __ilog2(unsigned int x)
+{
+ int ret;
+
+ asm(clz\t%0, %1 : =r (ret) : r (x));
+ ret = 31 - ret;
+ return ret;
+}
+
/*
* ffz = Find First Zero in word. Undefined if no zero exists,
* so code should check against ~0UL first..
--
1.7.4.1
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[U-Boot] [PATCH 1/5] ARM: Add Calxeda Highbank platform
From: Rob Herring rob.herr...@calxeda.com
Add basic support for Calxeda Highbank platform. Only minimal support to boot
is included.
Signed-off-by: Jason Hobbs jason.ho...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Albert ARIBAUD albert.arib...@free.fr
---
arch/arm/cpu/armv7/highbank/Makefile | 46
arch/arm/cpu/armv7/highbank/config.mk |4 +
arch/arm/cpu/armv7/highbank/timer.c | 124 +
board/highbank/Makefile | 49 +
board/highbank/highbank.c | 49 +
boards.cfg|1 +
include/configs/highbank.h| 101 +++
7 files changed, 374 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/highbank/Makefile
create mode 100644 arch/arm/cpu/armv7/highbank/config.mk
create mode 100644 arch/arm/cpu/armv7/highbank/timer.c
create mode 100644 board/highbank/Makefile
create mode 100644 board/highbank/highbank.c
create mode 100644 include/configs/highbank.h
diff --git a/arch/arm/cpu/armv7/highbank/Makefile
b/arch/arm/cpu/armv7/highbank/Makefile
new file mode 100644
index 000..76faeb0
--- /dev/null
+++ b/arch/arm/cpu/armv7/highbank/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS := timer.o
+SOBJS :=
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/arm/cpu/armv7/highbank/config.mk
b/arch/arm/cpu/armv7/highbank/config.mk
new file mode 100644
index 000..5ed5c39
--- /dev/null
+++ b/arch/arm/cpu/armv7/highbank/config.mk
@@ -0,0 +1,4 @@
+STANDALONE_LOAD_ADDR = 0x10
+
+PLATFORM_CPPFLAGS += -march=armv7-a
+
diff --git a/arch/arm/cpu/armv7/highbank/timer.c
b/arch/arm/cpu/armv7/highbank/timer.c
new file mode 100644
index 000..263f11a
--- /dev/null
+++ b/arch/arm/cpu/armv7/highbank/timer.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * Based on arm926ejs/mx27/timer.c
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see http://www.gnu.org/licenses/.
+ */
+
+#include common.h
+#include div64.h
+#include linux/types.h/* for size_t */
+#include linux/stddef.h /* for NULL */
+#include asm/io.h
+#include asm/arch-armv7/systimer.h
+
+#undef SYSTIMER_BASE
+#define SYSTIMER_BASE 0xFFF34000 /* Timer 0 and 1 base */
+#define SYSTIMER_RATE 15000
+
+static ulong timestamp;
+static ulong lastinc;
+static struct systimer *systimer_base = (struct systimer *)SYSTIMER_BASE;
+
+/*
+ * Start the timer
+ */
+int timer_init(void)
+{
+ /*
+* Setup timer0
+*/
+ writel(SYSTIMER_RELOAD, systimer_base-timer0load);
+ writel(SYSTIMER_RELOAD, systimer_base-timer0value);
+ writel(SYSTIMER_EN | SYSTIMER_32BIT, systimer_base-timer0control);
+
+ reset_timer_masked();
+
+ return 0;
+
+}
+
+#define TICK_PER_TIME ((SYSTIMER_RATE + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define NS_PER_TICK(10 / SYSTIMER_RATE)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+ do_div(tick, TICK_PER_TIME);
+ return
[U-Boot] [PATCH 4/5] scsi/ahci: add support for non-PCI controllers
From: Rob Herring rob.herr...@calxeda.com
Add support for AHCI controllers that are not PCI based.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Wolfgang Denk w...@denx.de
---
common/cmd_scsi.c|6 +++-
drivers/block/ahci.c | 70 +++--
include/ahci.h |4 +++
include/scsi.h |1 +
4 files changed, 70 insertions(+), 11 deletions(-)
diff --git a/common/cmd_scsi.c b/common/cmd_scsi.c
index be4fe74..25a8299 100644
--- a/common/cmd_scsi.c
+++ b/common/cmd_scsi.c
@@ -47,7 +47,8 @@
#define SCSI_DEV_ID 0x5288
#else
-#error no scsi device defined
+#define SCSI_VEND_ID 0
+#define SCSI_DEV_ID 0
#endif
@@ -174,7 +175,7 @@ removable:
scsi_curr_dev = -1;
}
-
+#ifdef CONFIG_PCI
void scsi_init(void)
{
int busdevfunc;
@@ -192,6 +193,7 @@ void scsi_init(void)
scsi_low_level_init(busdevfunc);
scsi_scan(1);
}
+#endif
block_dev_desc_t * scsi_get_dev(int dev)
{
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index d431c5a..d12cb71 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -78,13 +78,15 @@ static int waiting_for_cmd_completed(volatile u8 *offset,
static int ahci_host_init(struct ahci_probe_ent *probe_ent)
{
+#ifdef CONFIG_PCI
pci_dev_t pdev = probe_ent-dev;
+ u16 tmp16;
+ unsigned short vendor;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
u32 tmp, cap_save;
- u16 tmp16;
int i, j;
volatile u8 *port_mmio;
- unsigned short vendor;
cap_save = readl(mmio + HOST_CAP);
cap_save = ((1 28) | (1 17));
@@ -110,6 +112,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
writel(cap_save, mmio + HOST_CAP);
writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
+#ifdef CONFIG_PCI
pci_read_config_word(pdev, PCI_VENDOR_ID, vendor);
if (vendor == PCI_VENDOR_ID_INTEL) {
@@ -118,7 +121,7 @@ static int ahci_host_init(struct ahci_probe_ent *probe_ent)
tmp16 |= 0xf;
pci_write_config_word(pdev, 0x92, tmp16);
}
-
+#endif
probe_ent-cap = readl(mmio + HOST_CAP);
probe_ent-port_map = readl(mmio + HOST_PORTS_IMPL);
probe_ent-n_ports = (probe_ent-cap 0x1f) + 1;
@@ -183,22 +186,24 @@ static int ahci_host_init(struct ahci_probe_ent
*probe_ent)
writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
tmp = readl(mmio + HOST_CTL);
debug(HOST_CTL 0x%x\n, tmp);
-
+#ifdef CONFIG_PCI
pci_read_config_word(pdev, PCI_COMMAND, tmp16);
tmp |= PCI_COMMAND_MASTER;
pci_write_config_word(pdev, PCI_COMMAND, tmp16);
-
+#endif
return 0;
}
static void ahci_print_info(struct ahci_probe_ent *probe_ent)
{
+#ifdef CONFIG_PCI
pci_dev_t pdev = probe_ent-dev;
+ u16 cc;
+#endif
volatile u8 *mmio = (volatile u8 *)probe_ent-mmio_base;
u32 vers, cap, impl, speed;
const char *speed_s;
- u16 cc;
const char *scc_s;
vers = readl(mmio + HOST_VERSION);
@@ -212,7 +217,7 @@ static void ahci_print_info(struct ahci_probe_ent
*probe_ent)
speed_s = 3;
else
speed_s = ?;
-
+#ifdef CONFIG_PCI
pci_read_config_word(pdev, 0x0a, cc);
if (cc == 0x0101)
scc_s = IDE;
@@ -222,7 +227,9 @@ static void ahci_print_info(struct ahci_probe_ent
*probe_ent)
scc_s = RAID;
else
scc_s = unknown;
-
+#else
+ scc_s = SATA;
+#endif
printf(AHCI %02x%02x.%02x%02x
%u slots %u ports %s Gbps 0x%x impl %s mode\n,
(vers 24) 0xff,
@@ -249,6 +256,7 @@ static void ahci_print_info(struct ahci_probe_ent
*probe_ent)
cap (1 13) ? part : );
}
+#ifdef CONFIG_PCI
static int ahci_init_one(pci_dev_t pdev)
{
u16 vendor;
@@ -291,7 +299,7 @@ static int ahci_init_one(pci_dev_t pdev)
err_out:
return rc;
}
-
+#endif
#define MAX_DATA_BYTE_COUNT (4*1024*1024)
@@ -667,7 +675,9 @@ void scsi_low_level_init(int busdevfunc)
int i;
u32 linkmap;
+#ifdef CONFIG_PCI
ahci_init_one(busdevfunc);
+#endif
linkmap = probe_ent-link_port_map;
@@ -682,6 +692,48 @@ void scsi_low_level_init(int busdevfunc)
}
}
+int ahci_init(u32 base)
+{
+ int i, rc = 0;
+ u32 linkmap;
+
+ memset(ataid, 0, sizeof(ataid));
+
+ probe_ent = malloc(sizeof(struct ahci_probe_ent));
+ memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
+
+ probe_ent-host_flags = ATA_FLAG_SATA
+ | ATA_FLAG_NO_LEGACY
+ | ATA_FLAG_MMIO
+ | ATA_FLAG_PIO_DMA
+ | ATA_FLAG_NO_ATAPI;
+ probe_ent-pio_mask = 0x1f;
+ probe_ent-udma_mask = 0x7f;/*Fixme,assume to support UDMA6 */
+
+
[U-Boot] [PATCH 3/5] scsi/ahci: ata id little endian fix
From: Rob Herring rob.herr...@calxeda.com
The ata id string always needs swapping, not just on BE machines.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Wolfgang Denk w...@denx.de
---
drivers/block/ahci.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/block/ahci.c b/drivers/block/ahci.c
index a3ca2dc..d431c5a 100644
--- a/drivers/block/ahci.c
+++ b/drivers/block/ahci.c
@@ -468,7 +468,7 @@ static char *ata_id_strcpy(u16 *target, u16 *src, int len)
{
int i;
for (i = 0; i len / 2; i++)
- target[i] = le16_to_cpu(src[i]);
+ target[i] = swab16(src[i]);
return (char *)target;
}
--
1.7.4.1
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[U-Boot] [PATCH 5/5] ARM: highbank: Add AHCI support
From: Rob Herring rob.herr...@calxeda.com
This enables the AHCI driver on highbank platforms.
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Wolfgang Denk w...@denx.de
Cc: Albert ARIBAUD albert.arib...@free.fr
---
board/highbank/highbank.c |9 +
include/configs/highbank.h | 11 +++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c
index 9a0fc19..bec3d2f 100644
--- a/board/highbank/highbank.c
+++ b/board/highbank/highbank.c
@@ -16,6 +16,8 @@
*/
#include common.h
+#include ahci.h
+#include scsi.h
#include asm/sizes.h
@@ -31,6 +33,13 @@ int board_init(void)
return 0;
}
+int misc_init_r(void)
+{
+ ahci_init(0xffe08000);
+ scsi_scan(1);
+ return 0;
+}
+
int dram_init(void)
{
gd-ram_size = SZ_512M;
diff --git a/include/configs/highbank.h b/include/configs/highbank.h
index 6e26848..0ae198d 100644
--- a/include/configs/highbank.h
+++ b/include/configs/highbank.h
@@ -41,6 +41,15 @@
#define CONFIG_BAUDRATE38400
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID5
+#define CONFIG_SYS_SCSI_MAX_LUN1
+#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+ CONFIG_SYS_SCSI_MAX_LUN)
+
+#define CONFIG_DOS_PARTITION
+
/*
* Command line configuration.
*/
@@ -52,6 +61,8 @@
#define CONFIG_CMD_ELF
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_LOADS
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
#define CONFIG_BOOTDELAY 2
/*
--
1.7.4.1
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Re: [U-Boot] [PATCH 1/5] ARM: Add Calxeda Highbank platform
On Tue, Jun 21, 2011 at 6:33 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Add basic support for Calxeda Highbank platform. Only minimal support to boot
is included.
Signed-off-by: Jason Hobbs jason.ho...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Albert ARIBAUD albert.arib...@free.fr
---
arch/arm/cpu/armv7/highbank/Makefile | 46
arch/arm/cpu/armv7/highbank/config.mk | 4 +
arch/arm/cpu/armv7/highbank/timer.c | 124
+
board/highbank/Makefile | 49 +
board/highbank/highbank.c | 49 +
boards.cfg | 1 +
include/configs/highbank.h | 101 +++
You should add an entry to MAINTAINERS file.
...
+int dram_init(void)
+{
+ gd-ram_size = SZ_512M;
You could use
gd-ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
Regards,
Fabio Estevam
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Re: [U-Boot] [PATCH 1/5] ARM: Add Calxeda Highbank platform
On 06/21/2011 05:22 PM, Fabio Estevam wrote:
On Tue, Jun 21, 2011 at 6:33 PM, Rob Herring robherri...@gmail.com wrote:
From: Rob Herring rob.herr...@calxeda.com
Add basic support for Calxeda Highbank platform. Only minimal support to boot
is included.
Signed-off-by: Jason Hobbs jason.ho...@calxeda.com
Signed-off-by: Rob Herring rob.herr...@calxeda.com
Cc: Albert ARIBAUD albert.arib...@free.fr
---
arch/arm/cpu/armv7/highbank/Makefile | 46
arch/arm/cpu/armv7/highbank/config.mk |4 +
arch/arm/cpu/armv7/highbank/timer.c | 124
+
board/highbank/Makefile | 49 +
board/highbank/highbank.c | 49 +
boards.cfg|1 +
include/configs/highbank.h| 101 +++
You should add an entry to MAINTAINERS file.
...
+int dram_init(void)
+{
+ gd-ram_size = SZ_512M;
You could use
gd-ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
Except that does not work on qemu, and qemu can't model all of ram. So I
need to limit the ram size, but have the same image work on h/w and qemu.
Rob
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[U-Boot] how to understand uboot is 32bit program even it is in the 64bit mips
I have a 64bit cnMips borad.In the mail list archives,it says uboot is 32bit,even in the 64bit cpu. but how to understand that? I have a guess,is the 64bit cpu support a 32bit-mode,then when does it switch to 64bit-mode to load 64-bit linux? btw,I have an other question,according to see mips run linux,linux run in the _xkseg_ segment. so the first two bit virtual address in kernel space must be 11, like 11xx (64bit). but when I printf a variable' address in a foo driver,is say 0xa8041c2ea180. not start of _11_. the memory mapping mode has feazed me for _long_ _long_time. Dear Wolfgang(or someone else who can anwser me),thanks -- hacklu 2011-06-22 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] IMX51 EVK Splash Screen
Please constrain your emails to the email list; I do not like direct comment or direct email. Stefano has fixed much of the IPU/Splash Screen stuff. A good deal of that is in current U-Boot tree, last I saw. I am now back on OMAP, so really don't have comment on this. Stefanfo might, but just pull the tree and figure it out on your own; it is not that hard. tom 2011/6/21 童江 tongjiang.clouds...@gmail.com Hi Thomas and all, I have a problem when i deal with the i.MX51 Babbage uboot splash. As I read the the code of uboot , it seems that I only need to add the macro CONFIG_SPLASH_SCREEN defined in the mx51_bbg_android.h to make the splash works, but the fact is not.And i have a doubt of this code ,#define CONFIG_FB_BASE (TEXT_BASE + 0x30), why the base address of the fb is not 0x4000,but instead of a TEXT_BASE baseed. Any problem still going? I get the uboot code as this git clone git://git.denx.de/u-boot.git uboot-imx and i patched freescale R10.2 patch from http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX51ANDROIDfpsp=1tab=Design_Tools_Tab http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX51ANDROIDfpsp=1tab=Design_Tools_Tabsee the ipu files in the attach. Thanks. Vincent ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] sh: Clean up rsk7264 board settings
Applied to next branch.
Thanks.
Nobuhiro
2011/6/9 Phil Edworthy phil.edwor...@renesas.com:
Adjusted default settings so that we can boot zImages and uImages.
Removed unused settings, use default commands and where possible
calculate all other settings.
Signed-off-by: Phil Edworthy phil.edwor...@renesas.com
Cc: Nobuhiro Iwamatsu iwama...@nigauri.org
---
Changes for v2:
- Moved u-boot relocation address to top 256KB of ram
- Removed comments about how memory is used
- Less unnecessary tidying up
include/configs/rsk7264.h | 69 +++-
1 files changed, 24 insertions(+), 45 deletions(-)
diff --git a/include/configs/rsk7264.h b/include/configs/rsk7264.h
index aef37d0..8801993 100644
--- a/include/configs/rsk7264.h
+++ b/include/configs/rsk7264.h
@@ -1,5 +1,5 @@
/*
- * Configuation settings for the Renesas Technology RSK 7264
+ * Configuation settings for the Renesas RSK2+SH7264 board
*
* Copyright (C) 2011 Renesas Electronics Europe Ltd.
* Copyright (C) 2008 Nobuhiro Iwamatsu
@@ -17,83 +17,62 @@
#define CONFIG_SH2 1
#define CONFIG_SH2A 1
#define CONFIG_CPU_SH7264 1
-#define CONFIG_RSK7264 1
+#define CONFIG_RSK7264 1
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_CACHE
+#ifndef _CONFIG_CMD_DEFAULT_H
+# include config_cmd_default.h
+#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTARGS console=ttySC3,115200
#define CONFIG_BOOTDELAY 3
-#define CONFIG_LOADADDR 0x0C10 /* RSK7264_SDRAM_BASE +
1MB */
+#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
-#define CONFIG_VERSION_VARIABLE
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* MEMORY */
-#define RSK7264_SDRAM_BASE 0x0C00
-#define RSK7264_FLASH_BASE_1 0x2000 /* Non cache */
-
-#define CONFIG_SYS_TEXT_BASE 0x0C1C
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
#define CONFIG_SYS_PROMPT = /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the
Console */
#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor
commands */
-/* Buffer size for Boot Arguments passed to kernel */
-#define CONFIG_SYS_BARGSIZE 512
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-/* SCIF */
+/* Serial */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_CONS_SCIF3 1
-#define CONFIG_SYS_MEMTEST_START RSK7264_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (3 * 1024
* 1024))
-
-#define CONFIG_SYS_SDRAM_BASE RSK7264_SDRAM_BASE
+/* Memory */
+/* u-boot relocated to top 256KB of ram */
+#define CONFIG_SYS_TEXT_BASE 0x0CFC
+#define CONFIG_SYS_SDRAM_BASE 0x0C00
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
-#define CONFIG_SYS_MONITOR_BASE RSK7264_FLASH_BASE_1
-#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x10)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
+#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4*1024*1024)
-/* FLASH */
+/* Flash */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on
flinfo */
-#define CONFIG_SYS_FLASH_BASE RSK7264_FLASH_BASE_1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_FLASH_BASE 0x2000 /* Non-cached */
#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
-#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_OFFSET (128 * 1024)
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SECT_SIZE (128 * 1024)
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE +
CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_FLASH_ERASE_TOUT 12
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/* Board Clock */
#define
Re: [U-Boot] u-boot for x86
Hi Raleigh, On Wed, Jun 22, 2011 at 12:44 PM, Raleigh Boulware r_boulw...@hotmail.com wrote: I am looking at the source code for the sc520 and can not figure out which board directory to look in. Which of the board plat form has the sc520? The only board which currently builds for the sc520 is the eNET board Also How do I configure for the sc520 board? How do I do a build for the sc520? 1) Get the latest source using git 2) make eNET_config 3) make all I doubt that will be much help though, as you will need an eNET board to run it on :) If you have another x86 based board you want to get U-Boot running on, I am more than willing to help with advice and the odd bit of code Regards, Graeme ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] how to understand uboot is 32bit program even it is in the 64bit mips
We have dealt with this in our release of U-Boot since we only support 64-bit Linux. We use the n32 ABI with U-Boot and set it up to use a TLB entry to map U-Boot into a 32-bit addressable area. We have some special memcpy type routines that can handle the 64-bit addressing. All of our I/O registers require 64-bit addressing so we use assembly wrappers to do the actual read/writes to those addresses. -Aaron Williams On 06/21/2011 07:07 PM, hacklu wrote: I have a 64bit cnMips borad.In the mail list archives,it says uboot is 32bit,even in the 64bit cpu. but how to understand that? I have a guess,is the 64bit cpu support a 32bit-mode,then when does it switch to 64bit-mode to load 64-bit linux? btw,I have an other question,according to see mips run linux,linux run in the _xkseg_ segment. so the first two bit virtual address in kernel space must be 11, like 11xx (64bit). but when I printf a variable' address in a foo driver,is say 0xa8041c2ea180. not start of _11_. the memory mapping mode has feazed me for _long_ _long_time. Dear Wolfgang(or someone else who can anwser me),thanks -- hacklu 2011-06-22 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
