Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Michael Trimarchi]

On 06/21/2013 06:40 AM, Vipin Kumar wrote:
> On 6/20/2013 7:26 PM, Axel Lin wrote:
>> 2013/6/20 Marek Vasut
>>>
>>> Dear Axel Lin,
>>>
 In current gpio_set_value() implementation, it always sets the gpio control
 bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
 low. This patch fixes this bug.

 Signed-off-by: Axel Lin
 ---
   drivers/gpio/spear_gpio.c | 5 -
   1 file changed, 4 insertions(+), 1 deletion(-)

 diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
 index d3c728e..8878608 100644
 --- a/drivers/gpio/spear_gpio.c
 +++ b/drivers/gpio/spear_gpio.c
 @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
   {
struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;

 - writel(1<<  gpio,®s->gpiodata[DATA_REG_ADDR(gpio)]);
 + if (value)
 + writel(1<<  gpio,®s->gpiodata[DATA_REG_ADDR(gpio)]);
 + else
 + writel(0,®s->gpiodata[DATA_REG_ADDR(gpio)]);
>>>
>>> How can this possibly work? Writing 0 to the whole bank will unset all the
>>> GPIOs, no ?
>>
>>
>> Because each GPIO is controlled by a register.
>> And only one bit will be set when set gpio to high.
>>
>> So it's safe to write 0 for clearing the bit.
>>
>> Note, the gpio_get_value() implementation also assumes there is only one bit
>> will be set. ( If this is not true, both gpio_get_value() and 
>> gpio_set_value()
>> need fix.)
>>
>> Vipin, can you review this patch and confirm this behavior?
>>
> 
> Yes this is right. and the code is fine
> 

The problem is not in set one bit but in reset one bit. Can you check
the else path?


Michael


> Regards
> Vipin
> 
>> Thanks,
>> Axel
>> .
>>
> 
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Re: [U-Boot] Not abled to upload binary using "dfu-util"

[Sumit Gemini]

Hi Tom,

   Thanks for reply and need more help...


on host machine i can easily see the all partition by applying "dfu-util
-l".
and i am able to download images from pc to dfu-devices and it running
fine, but in case of uploading (from dfu-device to PC), my system just
copied only 1 byte data, and said uploading finished.

i stuck here, even i am not getting where is error. and yes when i applied

on host machine : dfu-util -a u-boot -U DFU-UBOOT

Got this output on host machine:-

   bytes_per_hash=4096
   Copying data from DFU device to PC
   Starting upload: [] finished!

  and file DFU-UBOOT created with 4KB size.


on target machine got such output :

  Running: sf read 0x 0x2 0x0
  Failed to map physical memory.


here 0x2 is my u-boot base address.



and sorry for saying i am very new in this DFU, i got complete source code
from client and i already check dfu source code even there is a entry for
dfu usb gadget in board file(am335x.h).



so now what should i verify regarding dfu.
if you want i can send you my board file.

Thanks
~Sumit Gemini


On Thu, Jun 20, 2013 at 8:17 PM, Tom Rini  wrote:

> On Thu, Jun 20, 2013 at 04:14:04PM +0530, Sumit Gemini wrote:
> > HI Heiko,
> >
> >  Thanks for reply and for links, i raised a request for membership.
> >  Here I want to share regarding dfu,
> >
> >
> > when i apply
> >
> > dfu-util -v -a SPL -U dfu-SPL from my host machine,
> >
> >
> > I got such log on Host machine :-
> >
> > Device returned transfer size 4096
> > bytes_per_hash=4096
> > Copying data from DFU device to PC
> > Starting upload: [] finished!
> > Received a total of 1 bytes
> >
> > and finally dfu-SPL file created with 4kb size.
> >
> >
> > but on target machine, i got
> >
> > Running: sf read 0x 0x2 0x0
> > Failed to map physical memory.
> >
> > May i know why i got such error or user have to specify address over
> which
> > we read our binary
>
> There is no DFU-SPI glue in mainline.  Please post the patches you have
> for adding SPI support to DFU, or contact your vendor.
>
> --
> Tom
>
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Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import

[Wolfgang Denk]

Dear ying.zh...@freescale.com,

In message <1371715468-21120-6-git-send-email-ying.zh...@freescale.com> you 
wrote:
> From: Ying Zhang 
> 
> The functionality env_import will be used in the SPL. They
> had been excluded by ifndef CONFIG_SPL_BUILD. Now, put it
> into the SPL.
> 
> Signed-off-by: Ying Zhang 
> ---
> Compared with the original version, Changed as below:
> 1. Split from "boot from SD card/SPI flash with SPL".
> 2. Split from "spl: Make CONFIG_SPL_BUILD contain more functionality"
> 3. No change.
> 4. No change.
> 
>  common/env_common.c |2 --
>  1 files changed, 0 insertions(+), 2 deletions(-)

This affects all boards, all architectures?  How well has this been
tested?

Best regards,

Wolfgang Denk

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Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
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Re: [U-Boot] [PATCH 01/10 v5] powerpc/mpc85xx: support application without resetvec segment in the linker script

[Wolfgang Denk]

Dear ying.zh...@freescale.com,

In message <1371715468-21120-1-git-send-email-ying.zh...@freescale.com> you 
wrote:
>
> --- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> +++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
> @@ -1,8 +1,5 @@
>  /*
> - * (C) Copyright 2006
> - * Wolfgang Denk, DENX Software Engineering, w...@denx.de
> - *
> - * Copyright 2009 Freescale Semiconductor, Inc.
> + * Copyright 2013 Freescale Semiconductor, Inc.

Please never, ever modify existing copyright headers in any such way!!

You MUST keeep existing entries (unless they are clearly wrong).



NAK!

Best regards,

Wolfgang Denk

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Re: [U-Boot] AM335x: enabling datacache in SPL slows down system?

[Wolfgang Denk]

Dear "Bas van den Berg",

In message <20130620080523.aba38...@mail.altenpts.nl> you wrote:
> 
> I'm trying to optimize the boottime for an AM335x based board. Currently
> we're loading the kernel from SPL directly (falcon mode). Loading the kernel
> from flash to ram takes roughly 3 seconds.
> When doing this from U-boot itself with 'nand read .., it only takes 1.8 
> seconds.
> It seems that U-boot has data_cache enabled, while SPL did not.
> 
> When enabling the data cache with dcache_enable(), loading takes 3.5 seconds,
> so even slower! The enabling itself does not take a significant amount of 
> time.

We observed the very same issue with the verry first prototype
implementation of Falcon mode on an AM3517 based board.  At this time
we did not have time nor resources to figure out what exactly was
causing this issue, but it's interesting to see that 1) it
still persists and 2) it also happens on AM335x

> Anyone have any idea why enabling the data cache slows SPL down?
> Or does U-boot do anything else that I'm missing?

@Tom: do you have any additional input what we should check?

Best regards,

Wolfgang Denk

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Re: [U-Boot] [PATCH v2] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Stefan Roese]

On 21.06.2013 05:07, Axel Lin wrote:
> AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
> 
> Signed-off-by: Axel Lin 

Acked-by: Stefan Roese 

Thanks,
Stefan
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Re: [U-Boot] [PATCH] nand: Don't call adjust_size_for_badblocks for erase

[Heiko Schocher]

Hello Scott,

Am 20.06.2013 19:52, schrieb Scott Wood:
> adjust_size_for_badblocks reduces the the operation size to account

nitpicking:
please only one "the".

> for the block skipping done by the read/write functions when an
> interval (partition name or whole chip) is specified rather than a data
> amount.
> 
> Erase does not do block skipping, except for erase.spread which takes
> a data amount rather than an interval (and thus already does not call
> adjust_size_for_badblocks).  Calling adjust_size_for_badblocks when
> block skipping is not done means that if bad blocks are present,
> the "nand erase.part" and "nand erase.chip" commands will fail to erase
> blocks at the end of the interval.
> 
> Signed-off-by: Scott Wood 
> Cc: Harvey Chapman 
> ---
>  common/cmd_nand.c |9 +
>  1 file changed, 1 insertion(+), 8 deletions(-)

Acked-by: Heiko Schocher 

bye,
Heiko
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[U-Boot] [PATCH v3] dfu, nand: before write a buffer to nand, erase the nand sectors

[Heiko Schocher]

before writing the received buffer to nand, erase the nand
sectors. If not doing this, nand write fails. See for
more info here:

http://lists.denx.de/pipermail/u-boot/2013-June/156361.html

Using the nand erase option "spread", maybe overwrite
blocks on, for example another mtd partition, if the
erasing range contains bad blocks.
So a limit option is added to nand_erase_opts()

Signed-off-by: Heiko Schocher 
Cc: Scott Wood 
Cc: Pantelis Antoniou 
Cc: Lukasz Majewski 
Cc: Kyungmin Park 
Cc: Marek Vasut 
Cc: Tom Rini 

---
- changes for v2:
  - use opts.spread as Scott Wood suggested
- changes for v3:
  - add opts.lim as Scott Wood suggested

 drivers/dfu/dfu_nand.c   | 18 --
 drivers/mtd/nand/nand_util.c |  4 
 include/nand.h   |  2 ++
 3 Dateien geändert, 22 Zeilen hinzugefügt(+), 2 Zeilen entfernt(-)

diff --git a/drivers/dfu/dfu_nand.c b/drivers/dfu/dfu_nand.c
index 7dc89b2..07dee89 100644
--- a/drivers/dfu/dfu_nand.c
+++ b/drivers/dfu/dfu_nand.c
@@ -63,12 +63,26 @@ static int nand_block_op(enum dfu_nand_op op, struct 
dfu_entity *dfu,
 
nand = &nand_info[nand_curr_device];
 
-   if (op == DFU_OP_READ)
+   if (op == DFU_OP_READ) {
ret = nand_read_skip_bad(nand, start, &count, &actual,
lim, buf);
-   else
+   } else {
+   nand_erase_options_t opts;
+
+   memset(&opts, 0, sizeof(opts));
+   opts.offset = start;
+   opts.length = count;
+   opts.spread = 1;
+   opts.quiet = 1;
+   opts.lim = lim;
+   /* first erase */
+   ret = nand_erase_opts(nand, &opts);
+   if (ret)
+   return ret;
+   /* then write */
ret = nand_write_skip_bad(nand, start, &count, &actual,
lim, buf, 0);
+   }
 
if (ret != 0) {
printf("%s: nand_%s_skip_bad call failed at %llx!\n",
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index d81972c..2778f7f 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -120,6 +120,10 @@ int nand_erase_opts(nand_info_t *meminfo, const 
nand_erase_options_t *opts)
 
WATCHDOG_RESET();
 
+   if (opts->lim && (erase.addr > (opts->offset + opts->lim))) {
+   puts("Size of erase exceeds limit\n");
+   return -EFBIG;
+   }
if (!opts->scrub && bbtest) {
int ret = mtd_block_isbad(meminfo, erase.addr);
if (ret > 0) {
diff --git a/include/nand.h b/include/nand.h
index 26190e4..228d871 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -125,6 +125,8 @@ struct nand_erase_options {
 
/* Don't include skipped bad blocks in size to be erased */
int spread;
+   /* maximum size that actual may be in order to not exceed the buf */
+   loff_t lim;
 };
 
 typedef struct nand_erase_options nand_erase_options_t;
-- 
1.7.11.7

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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Vipin Kumar]

On 6/20/2013 7:26 PM, Axel Lin wrote:

2013/6/20 Marek Vasut


Dear Axel Lin,


In current gpio_set_value() implementation, it always sets the gpio control
bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
low. This patch fixes this bug.

Signed-off-by: Axel Lin
---
  drivers/gpio/spear_gpio.c | 5 -
  1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
index d3c728e..8878608 100644
--- a/drivers/gpio/spear_gpio.c
+++ b/drivers/gpio/spear_gpio.c
@@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
  {
   struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;

- writel(1<<  gpio,®s->gpiodata[DATA_REG_ADDR(gpio)]);
+ if (value)
+ writel(1<<  gpio,®s->gpiodata[DATA_REG_ADDR(gpio)]);
+ else
+ writel(0,®s->gpiodata[DATA_REG_ADDR(gpio)]);


How can this possibly work? Writing 0 to the whole bank will unset all the
GPIOs, no ?



Because each GPIO is controlled by a register.
And only one bit will be set when set gpio to high.

So it's safe to write 0 for clearing the bit.

Note, the gpio_get_value() implementation also assumes there is only one bit
will be set. ( If this is not true, both gpio_get_value() and gpio_set_value()
need fix.)

Vipin, can you review this patch and confirm this behavior?



Yes this is right. and the code is fine

Regards
Vipin


Thanks,
Axel
.



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[U-Boot] [PATCH v2] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Axel Lin]

AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.

Signed-off-by: Axel Lin 
---
v2: define OMAP_MAX_GPIO and use it.
This change is mainly based on Stefan's comment, however I use
OMAP_MAX_GPIO instead of CONFIG_OMAP_MAX_GPIO because having CONFIG_ prefix
seems meaning it can be configurable in configs.

 drivers/gpio/omap_gpio.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index a30d7f0..6fa57c9 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -40,6 +40,12 @@
 #include 
 #include 
 
+#if defined(CONFIG_AM33XX)
+#define OMAP_MAX_GPIO  128
+#else
+#define OMAP_MAX_GPIO  192
+#endif
+
 #define OMAP_GPIO_DIR_OUT  0
 #define OMAP_GPIO_DIR_IN   1
 
@@ -55,7 +61,7 @@ static inline int get_gpio_index(int gpio)
 
 int gpio_is_valid(int gpio)
 {
-   return (gpio >= 0) && (gpio < 192);
+   return (gpio >= 0) && (gpio < OMAP_MAX_GPIO);
 }
 
 static int check_gpio(int gpio)
-- 
1.8.1.2



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[U-Boot] [PATCH v2 1/3] arm: spl: Fix SPL booting for OMAP3

[Stefan Roese]

Fix a problem with a re-assignment of r8 in the SPL version.

This patch now moves the call to s_init() to a later stage, right before
calling board_init_f(). And makes sure that r8 is correctly initialized
before s_init() is called. r8 now is only written in crt0.S.

This error was detected on the SPL port for the Compulab CM-T35 board
(OMAP3530).

Signed-off-by: Stefan Roese 
Cc: Tom Rini 
Cc: Albert ARIBAUD 
---
v2:
- Change handling/initializing of r8 as suggested by Albert.
  It should only be written in crt0.S.
  
Tom, while working on this version one question came up:
Is lowlevel_init() (file arch/arm/cpu/armv7/omap3/lowlevel_init.S)
needed any more? It calls cpy_clk_code() to copy some clk init
code into SRAM. But I fail to see if and where this code is really
executed from SRAM. Maybe I missed something. Perhaps you could
shed some light into this.

Thanks, Stefan

 arch/arm/cpu/armv7/omap3/board.c | 2 --
 arch/arm/cpu/armv7/omap3/lowlevel_init.S | 3 +--
 arch/arm/lib/crt0.S  | 7 ++-
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index b72fadc..8f41dcd 100644
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -256,8 +256,6 @@ void s_init(void)
 #endif
 
 #ifdef CONFIG_SPL_BUILD
-   gd = &gdata;
-
preloader_console_init();
 
timer_init();
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index eacfef8..8539093 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -226,8 +226,7 @@ ENTRY(lowlevel_init)
 #endif /* NAND Boot */
mov lr, ip  /* restore link reg */
ldr ip, [sp]/* restore save ip */
-   /* tail-call s_init to setup pll, mux, memory */
-   b   s_init
+   mov pc, lr
 
 ENDPROC(lowlevel_init)
 
diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
index a5bffb8..0f8d9f5 100644
--- a/arch/arm/lib/crt0.S
+++ b/arch/arm/lib/crt0.S
@@ -85,8 +85,13 @@ ENTRY(_main)
bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
sub sp, #GD_SIZE/* allocate one GD above SP */
bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
-   mov r8, sp  /* GD is above SP */
mov r0, #0
+#if defined(CONFIG_SPL_BUILD)
+   ldr r8, =gdata  /* SPL assigns r8 directly to &gdata */
+   bl  s_init  /* s_init() needs GD to be setup */
+#else
+   mov r8, sp  /* GD is above SP */
+#endif
bl  board_init_f
 
 #if ! defined(CONFIG_SPL_BUILD)
-- 
1.8.2.3

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Re: [U-Boot] [PATCH 0/2] vf610: Add I2C support for Freescale Vybrid VF610 platform

[Wang Huan-B18965]

Hi, Stefano, Heiko,

What's your suggestions about my two patches?

Thanks!


Best Regards,
Alison Wang

> -Original Message-
> From: u-boot-boun...@lists.denx.de [mailto:u-boot-boun...@lists.denx.de]
> On Behalf Of Alison Wang
> Sent: Monday, June 17, 2013 3:31 PM
> To: sba...@denx.de; Estevam Fabio-R49496; Liu Hui-R64343
> Cc: u-boot@lists.denx.de
> Subject: [U-Boot] [PATCH 0/2] vf610: Add I2C support for Freescale
> Vybrid VF610 platform
> 
> This series contain the I2C support for Freescale Vybrid VF610 platform
> and VF610TWR board.
> 
> Alison Wang (2):
>   vf610: Add I2C support for Vybrid VF610 platform
>   I2C: mxc_i2c: Add support for Vybrid VF610 platform
> 
>  arch/arm/cpu/armv7/vf610/generic.c|  7 +++
>  arch/arm/include/asm/arch-vf610/clock.h   |  1 +
>  arch/arm/include/asm/arch-vf610/crm_regs.h|  1 +
>  arch/arm/include/asm/arch-vf610/imx-regs.h|  1 +
>  arch/arm/include/asm/arch-vf610/iomux-vf610.h |  4 
>  board/freescale/vf610twr/vf610twr.c   | 14 +-
>  drivers/i2c/mxc_i2c.c | 62
> +++---
>  include/configs/vf610twr.h|  7 +++
>  8 files changed, 89 insertions(+), 8 deletions(-)
> 
> 
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Re: [U-Boot] [PATCH] video: exynos_fb: Add the missing #else clause

[Minkyu Kang]

On 22/04/13 10:00, Donghwa Lee wrote:
> It looks good to me.
> 
> Acked-by: Donghwa Lee 
> 
> Thank you,
> Donghwa Lee
> 
> 
> On Mon, Apr 22, 2013 at 02:03, Ajay kumar wrote:
>> ping.
>>
>>
>> On Thu, Apr 4, 2013 at 7:55 PM, Ajay Kumar > > wrote:
>>
>> This patch fixes a bug introduced while adding DT support
>> to Exynos FIMD driver:
>>
>> commit c23f3157d69bbb6c044256870f745f195b12431e
>> Author: Ajay Kumar > >
>> Date:   Thu Feb 21 23:53:01 2013 +
>>
>> video: exynos_fb: add DT support for FIMD driver
>>
>> Even though this part of code was missing, things were working
>> fine on Exynos5250 because, samsung_get_base_fimd() used
>> to give the correct base address for Exynos5250 FIMD.
>>
>> Signed-off-by: Ajay Kumar > >
>> ---
>>  drivers/video/exynos_fimd.c | 3 ++-
>>  1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c
>> index 3359949..7243ea3 100644
>> --- a/drivers/video/exynos_fimd.c
>> +++ b/drivers/video/exynos_fimd.c
>> @@ -280,8 +280,9 @@ void exynos_fimd_lcd_init(vidinfo_t *vid)
>> node, 
>> "reg");
>> if (fimd_ctrl == NULL)
>> debug("Can't get the FIMD base address\n");
>> -#endif
>> +#else
>> fimd_ctrl = (struct exynos_fb *)samsung_get_base_fimd();
>> +#endif
>>
>> offset = exynos_fimd_get_base_offset();
>>
>> --
>> 1.8.0
>>
>> ___
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>> http://lists.denx.de/mailman/listinfo/u-boot
>>
>>
> 

applied to u-boot-samsung.

thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH] exynos: Enable mmc for snow

[Minkyu Kang]

On 11/05/13 12:24, Simon Glass wrote:
> Snow has an internal eMMC and an external SD card. Enable these in the
> device tree.
> 
> Signed-off-by: Simon Glass 
> ---
>  board/samsung/dts/exynos5250-snow.dts | 24 
>  1 file changed, 24 insertions(+)
> 
> diff --git a/board/samsung/dts/exynos5250-snow.dts 
> b/board/samsung/dts/exynos5250-snow.dts
> index 24658c1..d167df9 100644
> --- a/board/samsung/dts/exynos5250-snow.dts
> +++ b/board/samsung/dts/exynos5250-snow.dts
> @@ -30,6 +30,10 @@
>   spi2 = "/spi@12d4";
>   spi3 = "/spi@131a";
>   spi4 = "/spi@131b";
> + mmc0 = "/mmc@1220";
> + mmc1 = "/mmc@1221";
> + mmc2 = "/mmc@1222";
> + mmc3 = "/mmc@1223";
>   };
>  
>   sound@12d6 {
> @@ -56,6 +60,26 @@
>   };
>   };
>  
> + mmc@1220 {
> + samsung,bus-width = <8>;
> + samsung,timing = <1 3 3>;
> + samsung,removable = <0>;
> + };
> +
> + mmc@1221 {
> + status = "disabled";
> + };
> +
> + mmc@1222 {
> + samsung,bus-width = <4>;
> + samsung,timing = <1 2 3>;
> + samsung,removable = <1>;
> + };
> +
> + mmc@1223 {
> + status = "disabled";
> + };
> +
>   tmu@1006 {
>   samsung,min-temp= <25>;
>   samsung,max-temp= <125>;
> 

applied to u-boot-samsung.

Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH v2 5/5] ARM: at91: atmel_nand: add code to check the ONFI parameter ECC requirement

[Scott Wood]

On 06/17/2013 05:51:21 AM, Josh Wu wrote:

+static int pmecc_choose_ecc(struct atmel_nand_host *host,
+   struct nand_chip *chip,
+   int *cap, int *sector_size)
+{
+   /* Get ECC requirement from ONFI parameters */
+   *cap = *sector_size = 0;
+   if (chip->onfi_version) {
+   if (!get_onfi_ecc_param(chip, cap, sector_size))
+			pr_debug("ONFI params, minimum required ECC: %d  
bits in %d bytes\n",

+   *cap, *sector_size);
+   else
+			dev_info(NULL, "NAND chip ECC reqirement is in  
Extended ONFI parameter, we don't support yet.\n");

+   } else {
+		dev_info(NULL, "NAND chip is not ONFI compliant, assume  
ecc_bits is 2 in 512 bytes");

+   }


Don't pass NULL to dev_info().  Either pass host->dev as the Linux code  
does (and use dev_dbg rather than pr_debug), or just use printf() (and  
debug()) if there's no intent to sync this change back to Linux.  It  
doesn't matter if host->dev doesn't exist in U-Boot, as the macro  
doesn't use that parameter, but the only reason to use Linux-style  
prints is to keep the code common with Linux.


-Scott
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Re: [U-Boot] [PATCH v3 12/12] Add verified boot information and test

[Simon Glass]

Hi Tom,

On Thu, Jun 20, 2013 at 9:07 AM, Tom Rini  wrote:

> On Thu, Jun 13, 2013 at 03:33:19PM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, Jun 13, 2013 at 3:10 PM, Simon Glass  wrote:
> >
> > > Add a description of how to implement verified boot using signed FIT
> > > images,
> > > and a simple test which verifies operation on sandbox.
> > >
> > > The test signs a FIT image and verifies it, then signs a FIT
> configuration
> > > and verifies it. Then it corrupts the signature to check that this is
> > > detected.
> > >
> > > Signed-off-by: Simon Glass 
> > >
> >
> > If it helps, here are the results of my build for this series (and the
> > trace one). No new failures but you can see quite a few problems with
> > Xscale.
>
> I _think_ Xscale is toolchain choice related.  My question is, for
> arches which use --gc-sections, what is the size change from before to
> after, when not opting in on this?
>

Including both trace and verified boot series, the size drops a little for
ARM and powerpc:

$ ./tools/buildman/buildman -b us-vboot9d  -sS arm powerpc --step 0
Summary of 2 commits for 955 boards (32 threads, 1 job per thread)
01: Merge branch 'master' of git://www.denx.de/git/u-boot-mmc
   arm: +   palmtc zipitz2 VCMA9 lubbock vpac270_nor_128 colibri_pxa270
kzm9g zynq_dcc zynq xaeniax polaris pxa255_idp vpac270_ond_256
vpac270_nor_256 smdk2410 balloon3 palmld trizepsiv h2200
   powerpc: +   MVBLM7 MVSMR lcd4_lwmon5
36: wip
   arm: (for 290/314 boards)  all -142.6  bss +4.5  data +27.1  rodata
-20.4  spl/u-boot-spl:all +1.9  spl/u-boot-spl:bss +0.0
 spl/u-boot-spl:rodata +1.9  text -153.8
   powerpc: (for 639/641 boards)  all -190.2  bss +0.0  data +25.6  rodata
-12.2  spl/u-boot-spl:all +0.2  spl/u-boot-spl:rodata +0.2  text -203.6

(the wip commit is just a patman change). You can see the text size drops
by 100-200 bytes. This is all due to the bootm refactor which removed
duplicated code.

If you are interested you can see this in the detail view. Commit 16
removes quite a bit of code. Commit 25 adds up to 80 bytes of text.

$ ./tools/buildman/buildman -b us-vboot9d  -sS arm powerpc
Summary of 36 commits for 955 boards (32 threads, 1 job per thread)
01: Merge branch 'master' of git://www.denx.de/git/u-boot-mmc
   arm: +   palmtc zipitz2 VCMA9 lubbock vpac270_nor_128 colibri_pxa270
kzm9g zynq_dcc zynq xaeniax polaris pxa255_idp vpac270_ond_256
vpac270_nor_256 smdk2410 balloon3 palmld trizepsiv h2200
   powerpc: +   MVBLM7 MVSMR lcd4_lwmon5
02: pci: Convert extern inline functions to static inline
03: x86: Correct missing local variable in bootm
04: Fix missing return in do_mem_loop()
05: Show stdout on error in fit-test
06: bootstage: Correct printf types
07: Add function to print a number with grouped digits
   arm: (for 290/314 boards)  all +6.0  bss -1.2  data +0.0  rodata
+7.2  spl/u-boot-spl:all +1.8  spl/u-boot-spl:bss -0.1
 spl/u-boot-spl:rodata +1.9
   powerpc: (for 639/641 boards)  all +7.8  bss -0.0  rodata +4.8
 spl/u-boot-spl:all +0.1  spl/u-boot-spl:rodata +0.1  text +3.0
08: Add trace library
   arm: (for 290/314 boards)  all +0.1  bss -0.0  data +0.1
 spl/u-boot-spl:all +0.1  spl/u-boot-spl:bss +0.1
   powerpc: (for 639/641 boards)  all +0.0  bss +0.0
09: Add a trace command
10: Support tracing in config.mk when enabled
11: Add trace support to generic board
   arm: (for 290/314 boards)  all +2.7  bss -0.4  data +0.6  text +2.5
12: Add proftool to decode profile data
13: sandbox: Support trace feature
14: Add a simple test for sandbox trace
15: Clarify bootm OS arguments
   arm: (for 290/314 boards)  all +13.0  bss +1.1  text +12.0
   powerpc: (for 639/641 boards)  all +15.4  text +15.4
16: Refactor the bootm command to reduce code duplication
   arm: (for 290/314 boards)  all -352.1  bss +2.1  rodata -69.0  text
-285.2
   powerpc: (for 639/641 boards)  all -345.4  rodata -44.2  text -301.2
17: Add a 'fake' go command to the bootm command
   arm: (for 290/314 boards)  all +55.1  bss +0.1  data +26.2  rodata
+5.0  text +23.8
   powerpc: (for 639/641 boards)  all +42.5  data +25.6  rodata +3.2  text
+13.7
18: arm: Implement the 'fake' go command
   arm: (for 290/314 boards)  all +89.4  bss +4.5  rodata +25.0  text
+59.9
19: exynos: Avoid function instrumentation for microsecond timer
20: exynos: config: Add tracing options
   arm: (for 290/314 boards)  all +25.0  bss -0.1  data +0.2  rodata
+6.9  text +18.0
   powerpc: (for 639/641 boards)  all -0.0  text -0.0
21: x86: Support tracing function
   powerpc: (for 639/641 boards)  all +0.0  text +0.0
22: x86: config: Add tracing options
   arm: (for 290/314 boards)  all -0.9  bss -0.7  rodata -0.1
   powerpc: (for 639/641 boards)  all -0.4  rodata -0.4
23: wip
   arm: (for 290/314 boards)  all +0.9  bss +0.7  rodata +0.1
   powerpc: (for 639/641 boards)  all +0.4  rodata +0.4
24: image: Add signing infrastructure
   arm: (for 290/314 boards)  all -0.3  bss -0.4  data +0.1
25: image

Re: [U-Boot] [PATCH v3 17/21] arm: Implement the 'fake' go command

[Simon Glass]

Hi Albert,

On Thu, Jun 20, 2013 at 2:55 AM, Albert ARIBAUD
wrote:

> Hi Simon,
>
> On Wed, 19 Jun 2013 21:15:10 -0700, Simon Glass 
> wrote:
>
> > Implement this feature on ARM for tracing.
> >
> > It would be nice to have generic bootm support so that it is easily
> > implemented on any arch.
> >
> > Signed-off-by: Simon Glass 
> > ---
> > Changes in v3:
> > - Revert to using 'images' instead of 'image' in boot_jump_linux()
> >
> > Changes in v2: None
>
> Small nitpick: I prefer whole series to be reposted even when there is
> only a single patch changed. My rationale for this is: when a series
> has been posted as V2 and a single patch appears as V3, as a reviewer I
> do not know whether that patch was really the only one intended as V3,
> or whether other patches were too but did not make it through for some
> reason.
>
> Also, as this V3 patch did not have any "In-Reply-To" header, it is not
> threaded to the V2 series by my claws-mail. That makes it less easy to
> try and get an overview of the current series.
>
> [insert witty remark about how patman quite adequately addresses the two
> points above :) ]
>

:-) I did use patman but only let it send a single patch. I felt that my
list spam quotient was high enough already, but perhaps not.


>
> Here I will assume 17/21 is the only patch in the series and the rest
> should come from v2 unchanged. As this is the only pure ARM related
> patch in the series (1), I guess my contribution shall be...
>
> Acked-by: Albert ARIBAUD 
>
> (1) patch 18/21 is Samsung and patch 19/21 touches on exynos5250-based
> boards; my ack is less adequate than that of, respectively, Minkyu as
> the Samsung custodian and the exynos5250-based boards' maintainers.
>

Yes


>
> Note: who/what exactly is "u-boot-rev...@google.com"?
>

It is a group of U-Boot people in Google, just so I don't have to copy
heaps of people and break the cc limit of the mailing list.

Regards,
Simon
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Re: [U-Boot] [PATCH] arm: fix memory coherency problem after relocation

[Marek Vasut]

Dear Mike Dunn,

> On 06/20/2013 06:56 AM, Marek Vasut wrote:
> > Dear Mike Dunn,
> > 
> >> On the xscale, the icache must be invalidated and the write buffers
> >> drained after writing code over the data bus, even if the caches are
> >> disabled. After rebasing with the main git repository, u-boot began
> >> crashing in odd places on my pxa270 board (palmtreo680) after the code
> >> relocation routine ran.  This patch fixes it.  Cache coherency problems
> >> are often
> >> hit-and-miss (ha ha), and this latent problem didn't rear its ugly head
> >> until now.  Tested on the pxa270.
> >> 
> >> Signed-off-by: Mike Dunn 
> >> ---
> >> 
> >> I realize that __ARM_ARCH_5TE__ does not necessarily mean xscale.
> > 
> > We should introduce some CONFIG_PXA I guess.
> 
> I think CONFIG_XSCALE is more correct, because if I'm not mistaken more
> recent Marvell processors continue to use the 'pxa' nomenclature in their
> name but do not contain xscale cores.

I suspect we might end up checking all the datasheets (PXA2xx, PXA3xx and 
PXA9xx) to see which CPUs still need this fixup.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Marek Vasut]

Dear Michael Trimarchi,

> Hi
> 
> On 06/20/2013 03:56 PM, Axel Lin wrote:
> > 2013/6/20 Marek Vasut 
> > 
> >> Dear Axel Lin,
> >> 
> >>> In current gpio_set_value() implementation, it always sets the gpio
> >>> control bit no matter the value argument is 0 or 1. Thus the GPIOs
> >>> never set to low. This patch fixes this bug.
> >>> 
> >>> Signed-off-by: Axel Lin 
> >>> ---
> >>> 
> >>>  drivers/gpio/spear_gpio.c | 5 -
> >>>  1 file changed, 4 insertions(+), 1 deletion(-)
> >>> 
> >>> diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> >>> index d3c728e..8878608 100644
> >>> --- a/drivers/gpio/spear_gpio.c
> >>> +++ b/drivers/gpio/spear_gpio.c
> >>> @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
> >>> 
> >>>  {
> >>>  
> >>>   struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
> >>> 
> >>> - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> >>> + if (value)
> >>> + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> >>> + else
> >>> + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> >> 
> >> How can this possibly work? Writing 0 to the whole bank will unset all
> >> the GPIOs, no ?
> > 
> > Because each GPIO is controlled by a register.
> > And only one bit will be set when set gpio to high.
> 
> Yes, but how to reset just one bit if you use the same register offset?
> 
> I don't know this core but I know two possibilities:
> 
> 1) one set register and one clear register
>   if (enable)
>   writel(1 << gpio, REGSET_BANK(gpio));
>   else
>   writel(1 << gpio, REGCLEAR_BANK(gpio));
> 2) or
> set operation
>   reg = readl(REG(gpio);
>   if (enable)
>   reg |= 1 << gpio;
>   else
>   reg &= ~(1 << gpio);
>   writel(reg, REG(GPIO));
> 
> Any other way?

I think it's about time to read the datasheet :b

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v4] usb: omap: ulpi: fix ulpi transceiver access

[Marek Vasut]

Dear Tom Rini,

> On 06/20/2013 03:53 PM, Michael Trimarchi wrote:
> > Hi Tom
> > 
> > Should I need to repost?
> 
> Nope, we're good.  Just had this assigned to Marek in patchwork when I
> did my last pull request, despite telling Marek I'd do it via
> u-boot-ti on IRC before.  I'll pick this up soon.

Urgh, ok. I'll leave that up to you Tom

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Michael Trimarchi]

Hi

On 06/20/2013 03:56 PM, Axel Lin wrote:
> 2013/6/20 Marek Vasut 
>>
>> Dear Axel Lin,
>>
>>> In current gpio_set_value() implementation, it always sets the gpio control
>>> bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
>>> low. This patch fixes this bug.
>>>
>>> Signed-off-by: Axel Lin 
>>> ---
>>>  drivers/gpio/spear_gpio.c | 5 -
>>>  1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
>>> index d3c728e..8878608 100644
>>> --- a/drivers/gpio/spear_gpio.c
>>> +++ b/drivers/gpio/spear_gpio.c
>>> @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
>>>  {
>>>   struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
>>>
>>> - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
>>> + if (value)
>>> + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
>>> + else
>>> + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
>>
>> How can this possibly work? Writing 0 to the whole bank will unset all the
>> GPIOs, no ?
> 
> 
> Because each GPIO is controlled by a register.
> And only one bit will be set when set gpio to high.
> 

Yes, but how to reset just one bit if you use the same register offset?

I don't know this core but I know two possibilities:

1) one set register and one clear register
if (enable)
writel(1 << gpio, REGSET_BANK(gpio));
else
writel(1 << gpio, REGCLEAR_BANK(gpio));
2) or 
set operation
reg = readl(REG(gpio);
if (enable)
reg |= 1 << gpio;
else
reg &= ~(1 << gpio);
writel(reg, REG(GPIO));

Any other way?

Michael 


> So it's safe to write 0 for clearing the bit.
> 
> Note, the gpio_get_value() implementation also assumes there is only one bit
> will be set. ( If this is not true, both gpio_get_value() and gpio_set_value()
> need fix.)
> 
> Vipin, can you review this patch and confirm this behavior?
> 
> Thanks,
> Axel
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-- 
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO  -  Founder  Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |


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Re: [U-Boot] [PATCH v4] usb: omap: ulpi: fix ulpi transceiver access

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 06/20/2013 03:53 PM, Michael Trimarchi wrote:
> Hi Tom
> 
> Should I need to repost?

Nope, we're good.  Just had this assigned to Marek in patchwork when I
did my last pull request, despite telling Marek I'd do it via
u-boot-ti on IRC before.  I'll pick this up soon.

- -- 
Tom
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Re: [U-Boot] [PATCH v4] usb: omap: ulpi: fix ulpi transceiver access

[Michael Trimarchi]

Hi Tom

Should I need to repost?

Michael

On 06/10/2013 06:18 PM, Michael Trimarchi wrote:
> This patch fix the omap access to the transceiver
> configuration registers using the ulpi bus. As reported by
> the documentation the bit31 is used only to check if the
> transaction is done or still running and the reading and
> writing operation have different offset and have different
> values. What we need to do at the end of a transaction is
> leave the bus in done state. Anyway an error using the ulpi
> omap register is not recoverable so any error give out the
> usage of this interface.
> 
> Tested on a custom OMAP5430 board with a TUSB1210 ULPI PHY
> on USBB1.
> 
> Signed-off-by: Michael Trimarchi 
> Acked-by: Igor Grinberg 
> Tested-by: Lubomir Popov 
> Cc: Stefano Babic 
> Cc: Marek Vasut 
> Cc: Tom Rini 
> ---
> - changes for V4
>   * The OMAP INSNREG05_ULPI register expects a value of 1 for Port 1
> and of 2 for Port 2 in the PORTSEL field.
>   * BIT31 OMAP_ULPI_START is used in the read function too
> - changes for V3
>   Fix patch subject
> - changes for V2
>   Fix commit message
> ---
>  drivers/usb/ulpi/omap-ulpi-viewport.c |   42 
> +++--
>  1 file changed, 9 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/usb/ulpi/omap-ulpi-viewport.c 
> b/drivers/usb/ulpi/omap-ulpi-viewport.c
> index 3c1ea1a..4db7fa4 100644
> --- a/drivers/usb/ulpi/omap-ulpi-viewport.c
> +++ b/drivers/usb/ulpi/omap-ulpi-viewport.c
> @@ -22,18 +22,19 @@
>  #include 
>  #include 
>  
> -#define OMAP_ULPI_WR_OPSEL   (3 << 21)
> -#define OMAP_ULPI_ACCESS (1 << 31)
> +#define OMAP_ULPI_WR_OPSEL   (2 << 22)
> +#define OMAP_ULPI_RD_OPSEL   (3 << 22)
> +#define OMAP_ULPI_START  (1 << 31)
>  
>  /*
> - * Wait for the ULPI Access to complete
> + * Wait for having ulpi in done state
>   */
>  static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 mask)
>  {
>   int timeout = CONFIG_USB_ULPI_TIMEOUT;
>  
>   while (--timeout) {
> - if ((readl(ulpi_vp->viewport_addr) & mask))
> + if (!(readl(ulpi_vp->viewport_addr) & mask))
>   return 0;
>  
>   udelay(1);
> @@ -43,40 +44,15 @@ static int ulpi_wait(struct ulpi_viewport *ulpi_vp, u32 
> mask)
>  }
>  
>  /*
> - * Wake the ULPI PHY up for communication
> - *
> - * returns 0 on success.
> - */
> -static int ulpi_wakeup(struct ulpi_viewport *ulpi_vp)
> -{
> - int err;
> -
> - if (readl(ulpi_vp->viewport_addr) & OMAP_ULPI_ACCESS)
> - return 0; /* already awake */
> -
> - writel(OMAP_ULPI_ACCESS, ulpi_vp->viewport_addr);
> -
> - err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
> - if (err)
> - debug("ULPI wakeup timed out\n");
> -
> - return err;
> -}
> -
> -/*
>   * Issue a ULPI read/write request
>   */
>  static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 value)
>  {
>   int err;
>  
> - err = ulpi_wakeup(ulpi_vp);
> - if (err)
> - return err;
> -
>   writel(value, ulpi_vp->viewport_addr);
>  
> - err = ulpi_wait(ulpi_vp, OMAP_ULPI_ACCESS);
> + err = ulpi_wait(ulpi_vp, OMAP_ULPI_START);
>   if (err)
>   debug("ULPI request timed out\n");
>  
> @@ -85,7 +61,7 @@ static int ulpi_request(struct ulpi_viewport *ulpi_vp, u32 
> value)
>  
>  int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 value)
>  {
> - u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
> + u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
>   OMAP_ULPI_WR_OPSEL | ((u32)reg << 16) | (value & 0xff);
>  
>   return ulpi_request(ulpi_vp, val);
> @@ -94,8 +70,8 @@ int ulpi_write(struct ulpi_viewport *ulpi_vp, u8 *reg, u32 
> value)
>  u32 ulpi_read(struct ulpi_viewport *ulpi_vp, u8 *reg)
>  {
>   int err;
> - u32 val = ((ulpi_vp->port_num & 0xf) << 24) |
> -  OMAP_ULPI_WR_OPSEL | ((u32)reg << 16);
> + u32 val = OMAP_ULPI_START | (((ulpi_vp->port_num + 1) & 0xf) << 24) |
> +  OMAP_ULPI_RD_OPSEL | ((u32)reg << 16);
>  
>   err = ulpi_request(ulpi_vp, val);
>   if (err)
> 


-- 
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO  -  Founder  Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |


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Re: [U-Boot] [PATCH] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Marek Vasut]

Dear Stefan Roese,

> On 20.06.2013 17:26, Axel Lin wrote:
> > AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
> > 
> > Signed-off-by: Axel Lin 
> > ---
> > 
> >  drivers/gpio/omap_gpio.c | 4 
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
> > index a30d7f0..9aa6d41 100644
> > --- a/drivers/gpio/omap_gpio.c
> > +++ b/drivers/gpio/omap_gpio.c
> > @@ -55,7 +55,11 @@ static inline int get_gpio_index(int gpio)
> > 
> >  int gpio_is_valid(int gpio)
> >  {
> > 
> > +#if defined(CONFIG_AM33XX)
> > +   return (gpio >= 0) && (gpio < 128);
> > +#else
> > 
> > return (gpio >= 0) && (gpio < 192);
> > 
> > +#endif
> > 
> >  }
> 
> Those ifdef's in the code really ugly and frowned upon. Better would be
> to move this into a define in the top of the C file:
> 
> #if defined(CONFIG_AM33XX)
> #define CONFIG_OMAP_MAX_GPIO  128
> #else
> #define CONFIG_OMAP_MAX_GPIO  192
> #endif
> 
> And then use this define in the code:
> 
>   return (gpio >= 0) && (gpio < CONFIG_OMAP_MAX_GPIO);
> 
> Thanks,
> Stefan

You were faster ;-) and I agree with this method.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3

[Albert ARIBAUD]

Hi Stefan,

On Thu, 20 Jun 2013 20:28:01 +0200, Stefan Roese  wrote:

> Hi Albert,
> 
> On 20.06.2013 19:51, Albert ARIBAUD wrote:
> >>> The correct fix (read: the one I won't NAK) is thus to add a #else
> >>> clause in the code above, in which r8 will be set to =gdata, and to
> >>> remove the corresponding assignments in the various places where they
> >>> reside.
> >>
> >> Here's the problem. Setting r8 in _main is too late. As it has already
> >> been used (in the current implementation) to store some data (e.g.
> >> clocks for baudrate generation etc). Here the code from
> >> arch/arm/cpu/armv7/omap3/board.c:s_init():
> >>
> >> #ifdef CONFIG_SPL_BUILD
> >>gd = &gdata;
> >>
> >>preloader_console_init();
> >>
> >>timer_init();
> >> #endif
> >>
> >> Note that this is done *before* _main() is called (we are talking about
> >> SPL for OMAP here).
> > 
> > Yes, it is done before _main... right before it. Like, really *right*
> > *before* *it*. Like, s_init is called at the very end of lowlevel_init,
> > which was branched straight into from cpu_init_crit which itself is
> > called just before _main.
> > 
> > In other words, after s_init(), _main immediately kicks in, sets up sp
> > and r8 (which was done also in lowlevel_init and will thus be a no-op
> > once gdata is handled in crt0.S too) and calls board_init_f().
> > 
> > So, calling s_init() last in lowlevel_init() would be the same as
> > calling it first in board_init_f().
> >
> > The difference with the current situation is, s_init() is C code, and C
> > runtime is supposed not to be available until just before entering
> > board_init_f(). This is the only reason why sp and r8 are set up in
> > lowlevel_init: because s_init() is called at a time when C runtime is
> > not officially set up yet.
> > 
> > Note that as far as setting the C runtime environment is concerned,
> > crt0.S does *exactly* the same thing as lowlevel_init -- or will, once
> > the gdata stuff is added in crt0.S as I suggest.
> > 
> > --- 8< ---
> > So you just need to add the gdata stuff in crt0.S as I previously
> > suggested, move the s_init() call in crt0.S (conditioned on building
> > SPL) just before the call to board_init_f(), and then make
> > lowlevel_init empty since it would then be useless.
> > --- 8< ---
> 
> Useless? Its still calling cpy_clk_code(). Isn't this needed anymore?

My bad -- I was looking at arch/arm/cpu/armv7/lowlevel_init.S, not
arch/arm/cpu/armv7/omap3/lowlevel_init.S.

> >> And it did cost me quite some time to find this
> >> problem, that r8 was re-configured in _main() and all the already set
> >> values disappeared again (no serial output etc).
> > 
> > Actually your trouble precisely shows why gd/r8 should only be touched
> > in a single file and nowhere else: because it is set in many places,
> > its value was hard to control.
> 
> Full ack on this.
> 
> >> Yes, this needs some cleanup/fixup. Unfortunately I won't find the time
> >> to look into such a cleanup in the next days. Perhaps somebody else
> >> might jump in...
> > 
> > There'll have to be a V2 for this patch anyway.
> > 
> > Here's my offer: you submit V2 of this patch as described above between
> > the '--- 8< ---' markers, and I handle the scrubbing of all spurious
> > assignments to gd myself. Deal?
> 
> Yes, I'll try to squeeze a few cycles from the other projects to get
> this done hopefully tomorrow.

Thank you.

> Thanks,
> Stefan

Amicalement,
-- 
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Re: [U-Boot] AM335x: enabling datacache in SPL slows down system?

[Jeroen Hofstee]

Hallo Bas,

On 06/20/2013 10:05 AM, Bas van den Berg wrote:

I'm trying to optimize the boottime for an AM335x based board. Currently
we're loading the kernel from SPL directly (falcon mode). Loading the kernel
from flash to ram takes roughly 3 seconds.
When doing this from U-boot itself with 'nand read .., it only takes 1.8 
seconds.
It seems that U-boot has data_cache enabled, while SPL did not.

When enabling the data cache with dcache_enable(), loading takes 3.5 seconds,
so even slower! The enabling itself does not take a significant amount of time.

Anyone have any idea why enabling the data cache slows SPL down?
Or does U-boot do anything else that I'm missing?


For an am3517 I added the code below to spl_board_init to
enable caches in SPL. It adds the SRAM region to the mmu,
by an obvious hack, but it works. I don't remember by heart
why I change / update gd->tlb_addr. The used address is
somewhere in the end of DRAM.

No guarantees this is related to your issue (or to work at all).

---
Groet,
Jeroen

if (!spl_start_uboot()) {
dram_init_banksize();

/* reserve TLB table (4k) */
gd->tlb_addr = 0x8fff;
debug("TLB table at: %08lx\n", gd->tlb_addr);

/* add sram (64k actually, but the cp15 counts in MiBs) */
gd->bd->bi_dram[1].start = CONFIG_SPL_TEXT_BASE;
gd->bd->bi_dram[1].size =  (1 << 20);

/* Enable caches */
enable_caches();
}


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Re: [U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3

[Stefan Roese]

Hi Albert,

On 20.06.2013 19:51, Albert ARIBAUD wrote:
>>> The correct fix (read: the one I won't NAK) is thus to add a #else
>>> clause in the code above, in which r8 will be set to =gdata, and to
>>> remove the corresponding assignments in the various places where they
>>> reside.
>>
>> Here's the problem. Setting r8 in _main is too late. As it has already
>> been used (in the current implementation) to store some data (e.g.
>> clocks for baudrate generation etc). Here the code from
>> arch/arm/cpu/armv7/omap3/board.c:s_init():
>>
>> #ifdef CONFIG_SPL_BUILD
>>  gd = &gdata;
>>
>>  preloader_console_init();
>>
>>  timer_init();
>> #endif
>>
>> Note that this is done *before* _main() is called (we are talking about
>> SPL for OMAP here).
> 
> Yes, it is done before _main... right before it. Like, really *right*
> *before* *it*. Like, s_init is called at the very end of lowlevel_init,
> which was branched straight into from cpu_init_crit which itself is
> called just before _main.
> 
> In other words, after s_init(), _main immediately kicks in, sets up sp
> and r8 (which was done also in lowlevel_init and will thus be a no-op
> once gdata is handled in crt0.S too) and calls board_init_f().
> 
> So, calling s_init() last in lowlevel_init() would be the same as
> calling it first in board_init_f().
>
> The difference with the current situation is, s_init() is C code, and C
> runtime is supposed not to be available until just before entering
> board_init_f(). This is the only reason why sp and r8 are set up in
> lowlevel_init: because s_init() is called at a time when C runtime is
> not officially set up yet.
> 
> Note that as far as setting the C runtime environment is concerned,
> crt0.S does *exactly* the same thing as lowlevel_init -- or will, once
> the gdata stuff is added in crt0.S as I suggest.
> 
> --- 8< ---
> So you just need to add the gdata stuff in crt0.S as I previously
> suggested, move the s_init() call in crt0.S (conditioned on building
> SPL) just before the call to board_init_f(), and then make
> lowlevel_init empty since it would then be useless.
> --- 8< ---

Useless? Its still calling cpy_clk_code(). Isn't this needed anymore?

>> And it did cost me quite some time to find this
>> problem, that r8 was re-configured in _main() and all the already set
>> values disappeared again (no serial output etc).
> 
> Actually your trouble precisely shows why gd/r8 should only be touched
> in a single file and nowhere else: because it is set in many places,
> its value was hard to control.

Full ack on this.

>> Yes, this needs some cleanup/fixup. Unfortunately I won't find the time
>> to look into such a cleanup in the next days. Perhaps somebody else
>> might jump in...
> 
> There'll have to be a V2 for this patch anyway.
> 
> Here's my offer: you submit V2 of this patch as described above between
> the '--- 8< ---' markers, and I handle the scrubbing of all spurious
> assignments to gd myself. Deal?

Yes, I'll try to squeeze a few cycles from the other projects to get
this done hopefully tomorrow.

Thanks,
Stefan

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Re: [U-Boot] bootm does not work if netconsole is enabled

[Michael Walle]

Am Mittwoch, 10. April 2013, 18:13:57 schrieb Joe Hershberger:
> > disabling the network console before control is handed over to an
> > operating system sounds reasonable.
> > 
> > If i understand you correctly, the network will only be halted once the
> > bootloader starts an operating system. Then what do you think about
> > making either the nc_send_packet() or nc_putc()/nc_puts() function a
> > noop when the network is halted?
> 
> It's not quite that simple since the state does not really reflect the
> hardware (I know... that's my fault).  I can try to fix this for next
> release, but it is probably too risky to put into the April release.

ping #2 :)

-- 
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[U-Boot] [PATCH] nand: Don't call adjust_size_for_badblocks for erase

[Scott Wood]

adjust_size_for_badblocks reduces the the operation size to account
for the block skipping done by the read/write functions when an
interval (partition name or whole chip) is specified rather than a data
amount.

Erase does not do block skipping, except for erase.spread which takes
a data amount rather than an interval (and thus already does not call
adjust_size_for_badblocks).  Calling adjust_size_for_badblocks when
block skipping is not done means that if bad blocks are present,
the "nand erase.part" and "nand erase.chip" commands will fail to erase
blocks at the end of the interval.

Signed-off-by: Scott Wood 
Cc: Harvey Chapman 
---
 common/cmd_nand.c |9 +
 1 file changed, 1 insertion(+), 8 deletions(-)

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index 8b1e01a..886212a 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -426,7 +426,7 @@ static int raw_access(nand_info_t *nand, ulong addr, loff_t 
off, ulong count,
 }
 
 /* Adjust a chip/partition size down for bad blocks so we don't
- * read/write/erase past the end of a chip/partition by accident.
+ * read/write past the end of a chip/partition by accident.
  */
 static void adjust_size_for_badblocks(loff_t *size, loff_t offset, int dev)
 {
@@ -546,7 +546,6 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
int scrub = !strncmp(cmd, "scrub", 5);
int spread = 0;
int args = 2;
-   int adjust_size = 0;
const char *scrub_warn =
"Warning: "
"scrub option will erase all factory set bad blocks!\n"
@@ -563,10 +562,8 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
spread = 1;
} else if (!strcmp(&cmd[5], ".part")) {
args = 1;
-   adjust_size = 1;
} else if (!strcmp(&cmd[5], ".chip")) {
args = 0;
-   adjust_size = 1;
} else {
goto usage;
}
@@ -586,10 +583,6 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 &maxsize) != 0)
return 1;
 
-   /* size is unspecified */
-   if (adjust_size && !scrub)
-   adjust_size_for_badblocks(&size, off, dev);
-
nand = &nand_info[dev];
 
memset(&opts, 0, sizeof(opts));
-- 
1.7.10.4


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Re: [U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3

[Albert ARIBAUD]

Hi Stefan,

On Thu, 20 Jun 2013 19:01:22 +0200, Stefan Roese  wrote:

> Hi Albert,
> 
> On 20.06.2013 18:42, Albert ARIBAUD wrote:
> >> diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
> >> index a9657d1..b05f66a 100644
> >> --- a/arch/arm/lib/crt0.S
> >> +++ b/arch/arm/lib/crt0.S
> >> @@ -85,7 +85,13 @@ ENTRY(_main)
> >>bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
> >>sub sp, #GD_SIZE/* allocate one GD above SP */
> >>bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
> >> +#if !defined(CONFIG_SPL_BUILD)
> >> +/*
> >> + * SPL already has GD set to the correct location (in s_init), we mustn't
> >> + * move it around now since some data (clocks etc) is already present.
> >> + */
> >>mov r8, sp  /* GD is above SP */
> >> +#endif
> >>mov r0, #0
> >>bl  board_init_f
> >>  
> > 
> > NAK in this form. I don't want gd to be set "somewhere in the code"
> > depending on the actual target; I want it set in crt0.S, period.
> > 
> > I see there are several locations in ARM architecture or board code
> > which set up GD themselves in the same manner as OMAP does. Luckily all
> > these locations set it to the same value, the address of gdata.
> > 
> > The correct fix (read: the one I won't NAK) is thus to add a #else
> > clause in the code above, in which r8 will be set to =gdata, and to
> > remove the corresponding assignments in the various places where they
> > reside.
> 
> Here's the problem. Setting r8 in _main is too late. As it has already
> been used (in the current implementation) to store some data (e.g.
> clocks for baudrate generation etc). Here the code from
> arch/arm/cpu/armv7/omap3/board.c:s_init():
> 
> #ifdef CONFIG_SPL_BUILD
>   gd = &gdata;
> 
>   preloader_console_init();
> 
>   timer_init();
> #endif
> 
> Note that this is done *before* _main() is called (we are talking about
> SPL for OMAP here).

Yes, it is done before _main... right before it. Like, really *right*
*before* *it*. Like, s_init is called at the very end of lowlevel_init,
which was branched straight into from cpu_init_crit which itself is
called just before _main.

In other words, after s_init(), _main immediately kicks in, sets up sp
and r8 (which was done also in lowlevel_init and will thus be a no-op
once gdata is handled in crt0.S too) and calls board_init_f().

So, calling s_init() last in lowlevel_init() would be the same as
calling it first in board_init_f().

The difference with the current situation is, s_init() is C code, and C
runtime is supposed not to be available until just before entering
board_init_f(). This is the only reason why sp and r8 are set up in
lowlevel_init: because s_init() is called at a time when C runtime is
not officially set up yet.

Note that as far as setting the C runtime environment is concerned,
crt0.S does *exactly* the same thing as lowlevel_init -- or will, once
the gdata stuff is added in crt0.S as I suggest.

--- 8< ---
So you just need to add the gdata stuff in crt0.S as I previously
suggested, move the s_init() call in crt0.S (conditioned on building
SPL) just before the call to board_init_f(), and then make
lowlevel_init empty since it would then be useless.
--- 8< ---

> And it did cost me quite some time to find this
> problem, that r8 was re-configured in _main() and all the already set
> values disappeared again (no serial output etc).

Actually your trouble precisely shows why gd/r8 should only be touched
in a single file and nowhere else: because it is set in many places,
its value was hard to control.

> Yes, this needs some cleanup/fixup. Unfortunately I won't find the time
> to look into such a cleanup in the next days. Perhaps somebody else
> might jump in...

There'll have to be a V2 for this patch anyway.

Here's my offer: you submit V2 of this patch as described above between
the '--- 8< ---' markers, and I handle the scrubbing of all spurious
assignments to gd myself. Deal?

> Thanks,
> Stefan

Amicalement,
-- 
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Re: [U-Boot] [PATCH v4 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114

[Stephen Warren]

On 06/20/2013 11:20 AM, Jim Lin wrote:
> 
>> On 06/20/2013 02:13 AM, Jim Lin wrote:
>>> Tegra30 and Tegra114 are compatible except PLL parameters.
>>>
>>> Tested on Tegra30 Cardhu, and Tegra114 Dalmore
>>> platforms. All works well.
>>> Changes in v4:
>>
>>>  - In pinmux-config-cardhu.h, chnage GMI_AD13 pinmux state to be OUTPUT
>>>in order to be driven HIGH for Beaver board.
>>
>> That should be reverted. As I mentioned in my previous response,
>> GMI_AD13 is the wrong pin.
>
> Please help me, test this v4 patch set on Beaver board, and
> tell me result.

It will possibly work since the pin you selected for VBUS does pull up
(weakly) the VBUS line. However, I'm not going to actually bother
testing it, since the code is doing the wrong thing.
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Re: [U-Boot] [PATCH v2] dfu, nand: before write a buffer to nand, erase the nand sectors

[Scott Wood]

On 06/19/2013 11:36:17 PM, Heiko Schocher wrote:

Hello Scott,

Am 18.06.2013 02:51, schrieb Scott Wood:
> Maybe we need an opts.limit?

Yes, I think so ... whats with the following proposal:

diff --git a/drivers/mtd/nand/nand_util.c  
b/drivers/mtd/nand/nand_util.c

index d81972c..b877c7d 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -120,6 +120,10 @@ int nand_erase_opts(nand_info_t *meminfo, const  
nand_erase_options_t *opts)


WATCHDOG_RESET();

+   if ((opts->limit) && (erase.addr > opts->limit)) {
+   puts("Size of write exceeds partition or  
device limit\n");

+   return -EFBIG;
+   }


This is treating limit as an address rather than a size.

Also, unnecessary parens.


diff --git a/include/nand.h b/include/nand.h
index 26190e4..d799df3 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -125,6 +125,8 @@ struct nand_erase_options {

/* Don't include skipped bad blocks in size to be erased */
int spread;
+   /* maximum size that actual may be in order to not exceed the  
buf */

+   loff_t limit;
 };

 typedef struct nand_erase_options nand_erase_options_t;

I checked for all calls from nand_erase_opts, that the  
nand_erase_options_t

parameters are initialized with 0 ... so this patch should not change
current behaviour.

Should I do this in a seperate patch, or add it to the "dfu, nand:
before write a buffer to nand, erase the nand sectors" patch, so it  
adds

no dead code ...


A separate patch within a patchset should be fine, but I'm also OK with  
combining them since the whole thing would still be small and  
straightforward enough to be easily reviewed.


-Scott
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Re: [U-Boot] [PATCH v4 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114

[Jim Lin]

>On 06/20/2013 02:13 AM, Jim Lin wrote:
>> Tegra30 and Tegra114 are compatible except PLL parameters.
>>
>> Tested on Tegra30 Cardhu, and Tegra114 Dalmore
>> platforms. All works well.
>> Changes in v4:
>
>>  - In pinmux-config-cardhu.h, chnage GMI_AD13 pinmux state to be OUTPUT
>>in order to be driven HIGH for Beaver board.
>
>That should be reverted. As I mentioned in my previous response,
>GMI_AD13 is the wrong pin.
Please help me, test this v4 patch set on Beaver board, and
tell me result.
Thanks.

--
nvpublic
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Re: [U-Boot] [PATCH] arm: fix memory coherency problem after relocation

[Mike Dunn]

On 06/20/2013 06:56 AM, Marek Vasut wrote:
> Dear Mike Dunn,
> 
>> On the xscale, the icache must be invalidated and the write buffers drained
>> after writing code over the data bus, even if the caches are disabled. 
>> After rebasing with the main git repository, u-boot began crashing in odd
>> places on my pxa270 board (palmtreo680) after the code relocation routine
>> ran.  This patch fixes it.  Cache coherency problems are often
>> hit-and-miss (ha ha), and this latent problem didn't rear its ugly head
>> until now.  Tested on the pxa270.
>>
>> Signed-off-by: Mike Dunn 
>> ---
>>
>> I realize that __ARM_ARCH_5TE__ does not necessarily mean xscale.
> 
> We should introduce some CONFIG_PXA I guess.


I think CONFIG_XSCALE is more correct, because if I'm not mistaken more recent
Marvell processors continue to use the 'pxa' nomenclature in their name but do
not contain xscale cores.

I'll take a stab at a patch if you like.  Maybe something like this macro in
arch/arm/include/asm/arch-pxa/hardware.h

/*
 * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected.
 * PXA300/310/320 all have distinct register mappings in some cases, that's why
 * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common
 * drivers and compatibility glue with old source then.
 */
#ifndef CONFIG_CPU_MONAHANS
#if defined(CONFIG_CPU_PXA300) || \
defined(CONFIG_CPU_PXA310) || \
defined(CONFIG_CPU_PXA320)
#define CONFIG_CPU_MONAHANS
#endif
#endif

Thanks,
Mike
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Re: [U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3

[Stefan Roese]

Hi Albert,

On 20.06.2013 18:42, Albert ARIBAUD wrote:
>> diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
>> index a9657d1..b05f66a 100644
>> --- a/arch/arm/lib/crt0.S
>> +++ b/arch/arm/lib/crt0.S
>> @@ -85,7 +85,13 @@ ENTRY(_main)
>>  bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
>>  sub sp, #GD_SIZE/* allocate one GD above SP */
>>  bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
>> +#if !defined(CONFIG_SPL_BUILD)
>> +/*
>> + * SPL already has GD set to the correct location (in s_init), we mustn't
>> + * move it around now since some data (clocks etc) is already present.
>> + */
>>  mov r8, sp  /* GD is above SP */
>> +#endif
>>  mov r0, #0
>>  bl  board_init_f
>>  
> 
> NAK in this form. I don't want gd to be set "somewhere in the code"
> depending on the actual target; I want it set in crt0.S, period.
> 
> I see there are several locations in ARM architecture or board code
> which set up GD themselves in the same manner as OMAP does. Luckily all
> these locations set it to the same value, the address of gdata.
> 
> The correct fix (read: the one I won't NAK) is thus to add a #else
> clause in the code above, in which r8 will be set to =gdata, and to
> remove the corresponding assignments in the various places where they
> reside.

Here's the problem. Setting r8 in _main is too late. As it has already
been used (in the current implementation) to store some data (e.g.
clocks for baudrate generation etc). Here the code from
arch/arm/cpu/armv7/omap3/board.c:s_init():

#ifdef CONFIG_SPL_BUILD
gd = &gdata;

preloader_console_init();

timer_init();
#endif

Note that this is done *before* _main() is called (we are talking about
SPL for OMAP here). And it did cost me quite some time to find this
problem, that r8 was re-configured in _main() and all the already set
values disappeared again (no serial output etc).

Yes, this needs some cleanup/fixup. Unfortunately I won't find the time
to look into such a cleanup in the next days. Perhaps somebody else
might jump in...

Thanks,
Stefan

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Re: [U-Boot] [PATCH 1/3] arm: spl: Fix SPL booting for OMAP3

[Albert ARIBAUD]

Hi Stefan,

On Fri, 14 Jun 2013 10:54:59 +0200, Stefan Roese  wrote:

> SPL already has GD set to the correct location (in s_init), we mustn't
> move it around now since some data (clocks etc) is already present.
> 
> This error was detected on the SPL port for the Compulab CM-T35 board
> (OMAP3530).
> 
> Signed-off-by: Stefan Roese 
> Cc: Tom Rini 
> Cc: Albert ARIBAUD 
> ---
>  arch/arm/lib/crt0.S | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S
> index a9657d1..b05f66a 100644
> --- a/arch/arm/lib/crt0.S
> +++ b/arch/arm/lib/crt0.S
> @@ -85,7 +85,13 @@ ENTRY(_main)
>   bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
>   sub sp, #GD_SIZE/* allocate one GD above SP */
>   bic sp, sp, #7  /* 8-byte alignment for ABI compliance */
> +#if !defined(CONFIG_SPL_BUILD)
> +/*
> + * SPL already has GD set to the correct location (in s_init), we mustn't
> + * move it around now since some data (clocks etc) is already present.
> + */
>   mov r8, sp  /* GD is above SP */
> +#endif
>   mov r0, #0
>   bl  board_init_f
>  

NAK in this form. I don't want gd to be set "somewhere in the code"
depending on the actual target; I want it set in crt0.S, period.

I see there are several locations in ARM architecture or board code
which set up GD themselves in the same manner as OMAP does. Luckily all
these locations set it to the same value, the address of gdata.

The correct fix (read: the one I won't NAK) is thus to add a #else
clause in the code above, in which r8 will be set to =gdata, and to
remove the corresponding assignments in the various places where they
reside.

(also, maybe not all SPLs want GD in gdata rather than on the stack;
for instance, those SPLs loaded in DDR by some ROM code. Therefore, the
whole gdata thing could possibly be placed under a specific condition
such as CONFIG_SPL_GD_GLOBAL)

Amicalement,
-- 
Albert.
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Re: [U-Boot] [PATCH v4 2/3] ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114

[Stephen Warren]

On 06/20/2013 02:13 AM, Jim Lin wrote:
> Tegra30 and Tegra114 are compatible except PLL parameters.
> 
> Tested on Tegra30 Cardhu, and Tegra114 Dalmore
> platforms. All works well.

> Changes in v4:

>  - In pinmux-config-cardhu.h, chnage GMI_AD13 pinmux state to be OUTPUT
>in order to be driven HIGH for Beaver board.

That should be reverted. As I mentioned in my previous response,
GMI_AD13 is the wrong pin.

> diff --git a/board/nvidia/cardhu/pinmux-config-cardhu.h 
> b/board/nvidia/cardhu/pinmux-config-cardhu.h

> @@ -332,7 +332,9 @@ static struct pingroup_config unused_pins_lowpower[] = {
>   DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, TRISTATE, OUTPUT),
>   DEFAULT_PINMUX(GMI_AD9, PWM1, NORMAL, NORMAL, OUTPUT),
>   DEFAULT_PINMUX(GMI_AD11, NAND, NORMAL, NORMAL, OUTPUT),
> - DEFAULT_PINMUX(GMI_AD13, NAND, UP, NORMAL, INPUT),
> +
> + /* Beaver, USB13_VBUS_PULLUP GPIO */
> + DEFAULT_PINMUX(GMI_AD13, NAND, NORMAL, NORMAL, OUTPUT),

I assume this table is shared between Cardhu and Beaver. You can't make
Beaver-specific changes to it. If you need to make Beaver-specific
changes, then you need to create a separate pinmux-config-beaver.h, or
use #ifdefs based on the board you're compiling for.

Luckily in this case, GMI_AD13 is not connected on Cardhu, so you
haven't damaged any HW by testing this change on Cardhu.

> diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c

> +struct fdt_usb_controller {
> + int compat;
> + /* flag to determine whether controller supports hostpc register */
> + u8 has_hostpc:1;

I'd suggest "bool" here, or at least "u32 has_hostpc:1"; alignment
concerns will pad the storage out to 32-bit anyway, so you may as well
use a 32-bit variable as is normal for bit-fields.
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Re: [U-Boot] [PATCH v3 12/12] Add verified boot information and test

[Simon Glass]

Hi Tom,

On Thu, Jun 20, 2013 at 9:07 AM, Tom Rini  wrote:

> On Thu, Jun 13, 2013 at 03:33:19PM -0700, Simon Glass wrote:
> > Hi Tom,
> >
> > On Thu, Jun 13, 2013 at 3:10 PM, Simon Glass  wrote:
> >
> > > Add a description of how to implement verified boot using signed FIT
> > > images,
> > > and a simple test which verifies operation on sandbox.
> > >
> > > The test signs a FIT image and verifies it, then signs a FIT
> configuration
> > > and verifies it. Then it corrupts the signature to check that this is
> > > detected.
> > >
> > > Signed-off-by: Simon Glass 
> > >
> >
> > If it helps, here are the results of my build for this series (and the
> > trace one). No new failures but you can see quite a few problems with
> > Xscale.
>
> I _think_ Xscale is toolchain choice related.  My question is, for
> arches which use --gc-sections, what is the size change from before to
> after, when not opting in on this?
>

Yes I think you are right. Unfortunately I don't have that build now, but I
will redo it and check.

Regards,
Simon


>
> --
> Tom
>
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[U-Boot] [PATCH] README: align default commands with code

[Vincent Stehlé]

Align the list of default commands mentioned in the configuration options
paragraph of the README with the actual definitions found in
include/config_cmd_default.h

Signed-off-by: Vincent Stehlé 
---
 README |   14 --
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/README b/README
index cd0336c..787d40f 100644
--- a/README
+++ b/README
@@ -843,7 +843,7 @@ The following options need to be configured:
CONFIG_CMD_FDOS * Dos diskette Support
CONFIG_CMD_FLASH  flinfo, erase, protect
CONFIG_CMD_FPGA   FPGA device initialization support
-   CONFIG_CMD_FUSE   Device fuse support
+   CONFIG_CMD_FUSE * Device fuse support
CONFIG_CMD_GETTIME  * Get time since boot
CONFIG_CMD_GO   * the 'go' command (exec code)
CONFIG_CMD_GREPENV  * search environment
@@ -853,7 +853,7 @@ The following options need to be configured:
CONFIG_CMD_IDE  * IDE harddisk support
CONFIG_CMD_IMIiminfo
CONFIG_CMD_IMLS   List all images found in NOR flash
-   CONFIG_CMD_IMLS_NAND  List all images found in NAND flash
+   CONFIG_CMD_IMLS_NAND* List all images found in NAND flash
CONFIG_CMD_IMMAP* IMMR dump support
CONFIG_CMD_IMPORTENV* import an environment
CONFIG_CMD_INI  * import data from an ini file into the 
env
@@ -861,23 +861,24 @@ The following options need to be configured:
CONFIG_CMD_ITEST  Integer/string test of 2 values
CONFIG_CMD_JFFS2* JFFS2 Support
CONFIG_CMD_KGDB * kgdb
-   CONFIG_CMD_LDRINFOldrinfo (display Blackfin loader)
+   CONFIG_CMD_LDRINFO  * ldrinfo (display Blackfin loader)
CONFIG_CMD_LINK_LOCAL   * link-local IP address 
auto-configuration
  (169.254.*.*)
CONFIG_CMD_LOADB  loadb
CONFIG_CMD_LOADS  loads
-   CONFIG_CMD_MD5SUM print md5 message digest
+   CONFIG_CMD_MD5SUM   * print md5 message digest
  (requires CONFIG_CMD_MEMORY and 
CONFIG_MD5)
CONFIG_CMD_MEMINFO  * Display detailed memory information
CONFIG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base,
  loop, loopw
-   CONFIG_CMD_MEMTESTmtest
+   CONFIG_CMD_MEMTEST  * mtest
CONFIG_CMD_MISC   Misc functions like sleep etc
CONFIG_CMD_MMC  * MMC memory mapped support
CONFIG_CMD_MII  * MII utility commands
CONFIG_CMD_MTDPARTS * MTD partition support
CONFIG_CMD_NAND * NAND support
CONFIG_CMD_NETbootp, tftpboot, rarpboot
+   CONFIG_CMD_NFSNFS support
CONFIG_CMD_PCA953X  * PCA953x I2C gpio commands
CONFIG_CMD_PCA953X_INFO * PCA953x I2C gpio info command
CONFIG_CMD_PCI  * pciinfo
@@ -896,7 +897,7 @@ The following options need to be configured:
CONFIG_CMD_SETGETDCR  Support for DCR Register access
  (4xx only)
CONFIG_CMD_SF   * Read/write/erase SPI NOR flash
-   CONFIG_CMD_SHA1SUMprint sha1 memory digest
+   CONFIG_CMD_SHA1SUM  * print sha1 memory digest
  (requires CONFIG_CMD_MEMORY)
CONFIG_CMD_SOFTSWITCH   * Soft switch setting command for BF60x
CONFIG_CMD_SOURCE "source" command Support
@@ -908,6 +909,7 @@ The following options need to be configured:
CONFIG_CMD_USB  * USB support
CONFIG_CMD_CDP  * Cisco Discover Protocol support
CONFIG_CMD_MFSL * Microblaze FSL support
+   CONFIG_CMD_XIMG   Load part of Multi Image
 
 
EXAMPLE: If you want all functions except of network
-- 
1.7.10.4



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Re: [U-Boot] [PATCH v3 12/12] Add verified boot information and test

[Tom Rini]

On Thu, Jun 13, 2013 at 03:33:19PM -0700, Simon Glass wrote:
> Hi Tom,
> 
> On Thu, Jun 13, 2013 at 3:10 PM, Simon Glass  wrote:
> 
> > Add a description of how to implement verified boot using signed FIT
> > images,
> > and a simple test which verifies operation on sandbox.
> >
> > The test signs a FIT image and verifies it, then signs a FIT configuration
> > and verifies it. Then it corrupts the signature to check that this is
> > detected.
> >
> > Signed-off-by: Simon Glass 
> >
> 
> If it helps, here are the results of my build for this series (and the
> trace one). No new failures but you can see quite a few problems with
> Xscale.

I _think_ Xscale is toolchain choice related.  My question is, for
arches which use --gc-sections, what is the size change from before to
after, when not opting in on this?

-- 
Tom


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Re: [U-Boot] [PATCH v4 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114

[Stephen Warren]

On 06/20/2013 02:13 AM, Jim Lin wrote:
> Add DT node for USB EHCI function.
> Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.

> diff --git a/arch/arm/dts/tegra114.dtsi b/arch/arm/dts/tegra114.dtsi

> + usb@7d004000 {
> + compatible = "nvidia,tegra114-ehci";
> + reg = <0x7d004000 0x4000>;
> + interrupts = <53>;
> + phy_type = "utmi";

If Tegra114 and Tegra30 are anything like Tegra20, then USB2 doesn't
support UTMI mode; it's either ULPI or HSIC. Can you please check this.

The same comment applies in tegra30.dtsi.

> diff --git a/include/fdtdec.h b/include/fdtdec.h

> diff --git a/lib/fdtdec.c b/lib/fdtdec.c

As I said before, driver changes should be in a separate patch to DT
changes. Please move the changes to fdtdec.* into patch 2/3.
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Re: [U-Boot] [PATCH v4 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114

[Stephen Warren]

On 06/20/2013 05:17 AM, Thierry Reding wrote:
> On Thu, Jun 20, 2013 at 04:13:38PM +0800, Jim Lin wrote:
>> Add DT node for USB EHCI function. Add support for T30-Cardhu,
>> T30-Beaver, T114-Dalmore boards.
>> 
>> Signed-off-by: Jim Lin  --- Changes in v2: -
>> Remove PLL parameters from dt file Changes in v3: - Change VBus
>> GPIO from H.05 to DD.04 for Beaver board. Changes in v4: - Change
>> Beaver VBus GPIO to H.05 and value to 0 for polarity to be High. 
>> I don't have Beaver board. So this needs somebody to help test. 
>> Thanks.
> 
> Why did you change it back to H.05 again? I already tested
> successfully that DD.04 is the right one.

Yes, such a change is clearly wrong. Jim, you have access to the
schematics for all these boards. Please use them.

The correct values are:

Beaver:

USB1 VBUS: PEX_L1_CLKREQ / PDD6 / 238
USB3 VBUS: PEX_L1_PRSNT / PDD4 / 236

Incorrect: GMI_AD13 / PH5 / 61
(This is a signal that pulls up all of USB1 VBUS, USB3 VBUS, and
GMI_AD15, which as far as I can tell is entirely unrelated to USB in
any way)

Cardhu A04:

USB1 VBUS: PEX_L1_CLKREQ / PDD6 / 238
USB3 VBUS: PEX_L1_PRSNT / PDD4 / 236

Incorrect: PEX_L0_RST / PDD1 / 233
(This is a signal that pulls up a whole slew of signals, many of which
are entirely unrelated to USB in any way)

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Re: [U-Boot] [PATCH] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Stefan Roese]

On 20.06.2013 17:26, Axel Lin wrote:
> AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
> 
> Signed-off-by: Axel Lin 
> ---
>  drivers/gpio/omap_gpio.c | 4 
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
> index a30d7f0..9aa6d41 100644
> --- a/drivers/gpio/omap_gpio.c
> +++ b/drivers/gpio/omap_gpio.c
> @@ -55,7 +55,11 @@ static inline int get_gpio_index(int gpio)
>  
>  int gpio_is_valid(int gpio)
>  {
> +#if defined(CONFIG_AM33XX)
> + return (gpio >= 0) && (gpio < 128);
> +#else
>   return (gpio >= 0) && (gpio < 192);
> +#endif
>  }

Those ifdef's in the code really ugly and frowned upon. Better would be
to move this into a define in the top of the C file:

#if defined(CONFIG_AM33XX)
#define CONFIG_OMAP_MAX_GPIO128
#else
#define CONFIG_OMAP_MAX_GPIO192
#endif

And then use this define in the code:

return (gpio >= 0) && (gpio < CONFIG_OMAP_MAX_GPIO);

Thanks,
Stefan

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Re: [U-Boot] [PATCH] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Tom Rini]

On Thu, Jun 20, 2013 at 11:26:56PM +0800, Axel Lin wrote:

> AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.
> 
> Signed-off-by: Axel Lin 

Reviewed-by: Tom Rini 

-- 
Tom


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[U-Boot] [PATCH] gpio: omap_gpio: Fix valid gpio range for AM33XX

[Axel Lin]

AM33XX has 4 gpio banks, thus the valid gpio range should be 0 ... 127.

Signed-off-by: Axel Lin 
---
 drivers/gpio/omap_gpio.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpio/omap_gpio.c b/drivers/gpio/omap_gpio.c
index a30d7f0..9aa6d41 100644
--- a/drivers/gpio/omap_gpio.c
+++ b/drivers/gpio/omap_gpio.c
@@ -55,7 +55,11 @@ static inline int get_gpio_index(int gpio)
 
 int gpio_is_valid(int gpio)
 {
+#if defined(CONFIG_AM33XX)
+   return (gpio >= 0) && (gpio < 128);
+#else
return (gpio >= 0) && (gpio < 192);
+#endif
 }
 
 static int check_gpio(int gpio)
-- 
1.8.1.2



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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Marek Vasut]

Dear Michael Trimarchi,

> Hi
> 
> Il giorno 20/giu/2013 15:57, "Marek Vasut"  ha scritto:
> > Dear Michael Trimarchi,
> > 
> > > Hi
> > > 
> > > Il giorno 20/giu/2013 09:14, "Axel Lin"  ha
> 
> scritto:
> > > > In current gpio_set_value() implementation, it always sets the gpio
> > > 
> > > control bit
> > > 
> > > > no matter the value argument is 0 or 1. Thus the GPIOs never set to
> 
> low.
> 
> > > > This patch fixes this bug.
> > > > 
> > > > Signed-off-by: Axel Lin 
> > > > ---
> > > > 
> > > >  drivers/gpio/spear_gpio.c | 5 -
> > > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> > > > index d3c728e..8878608 100644
> > > > --- a/drivers/gpio/spear_gpio.c
> > > > +++ b/drivers/gpio/spear_gpio.c
> > > > @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
> > > > 
> > > >  {
> > > >  
> > > > struct gpio_regs *regs = (struct gpio_regs
> > > > *)CONFIG_GPIO_BASE;
> > > > 
> > > > -   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > > > +   if (value)
> > > > +   writel(1 << gpio,
> 
> ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> 
> > > > +   else
> > > > +   writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > > > 
> > > > return 0;
> > > >  
> > > >  }
> > > 
> > > Does it work the clear? Seems that it sets to 0 all the bank. I'm using
> 
> the
> 
> > > mobile
> > 
> > I don't think I speak language of your tribe (lol) ;-)
> > 
> > What's "the mobile" please ?
> > 
> > Best regards,
> > Marek Vasut
> 
> Android mobile, italian dictinary and same comment of you

Poor you, the android {keyboard,mailer,} is such a crap ;-(

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Michael Trimarchi]

Hi
Il giorno 20/giu/2013 15:57, "Marek Vasut"  ha scritto:
>
> Dear Michael Trimarchi,
>
> > Hi
> >
> > Il giorno 20/giu/2013 09:14, "Axel Lin"  ha
scritto:
> > > In current gpio_set_value() implementation, it always sets the gpio
> >
> > control bit
> >
> > > no matter the value argument is 0 or 1. Thus the GPIOs never set to
low.
> > > This patch fixes this bug.
> > >
> > > Signed-off-by: Axel Lin 
> > > ---
> > >
> > >  drivers/gpio/spear_gpio.c | 5 -
> > >  1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> > > index d3c728e..8878608 100644
> > > --- a/drivers/gpio/spear_gpio.c
> > > +++ b/drivers/gpio/spear_gpio.c
> > > @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
> > >
> > >  {
> > >
> > > struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
> > >
> > > -   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > > +   if (value)
> > > +   writel(1 << gpio,
®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > > +   else
> > > +   writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > >
> > > return 0;
> > >
> > >  }
> >
> > Does it work the clear? Seems that it sets to 0 all the bank. I'm using
the
> > mobile
>
> I don't think I speak language of your tribe (lol) ;-)
>
> What's "the mobile" please ?
>
> Best regards,
> Marek Vasut
Android mobile, italian dictinary and same comment of you

:D

Michael
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Re: [U-Boot] [uBoot] [PATCH v2] musb: Move linux and usb compat files to include/linux/usb

[Marek Vasut]

Dear Dan Murphy,

> Marek
> 
> On 06/20/2013 08:49 AM, Marek Vasut wrote:
> > Dear Dan Murphy,
> > 
> >> + Marek
> >> and a bump
> >> 
> >> On 06/13/2013 02:07 PM, Dan Murphy wrote:
> >>> Move the linux and usb compat files to the
> >>> include/linux/usb directory in order for the files to be
> >>> reused.
> >>> 
> >>> Added GPLv2 license to the linux and usb compat as well.
> >>> 
> >>> Signed-off-by: Dan Murphy 
> >>> ---
> >>> v2 - Fix checkpatch issues only for newly introduced code -
> >>> http://patchwork.ozlabs.org/patch/251127/
> > 
> > Can you please make this into two patches? First adding the license and
> > the other doing the move? This way you would be able to even git
> > format-patch -MC and reduce the patch to a bare minimum , making it
> > nicely reviewable.
> > 
> > btw are you sure about the license?
> > 
> > Best regards,
> > Marek Vasut
> 
> Thanks for the review.
> 
> I am rethinking the move of these files.
> 
> Do you have specific questions on the license?
> Because I will still be sending that patch in.

Tom seem to have cleared it up, no prob.

Best regards,
Marek Vasut
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Re: [U-Boot] Not abled to upload binary using "dfu-util"

[Tom Rini]

On Thu, Jun 20, 2013 at 04:14:04PM +0530, Sumit Gemini wrote:
> HI Heiko,
> 
>  Thanks for reply and for links, i raised a request for membership.
>  Here I want to share regarding dfu,
> 
> 
> when i apply
> 
> dfu-util -v -a SPL -U dfu-SPL from my host machine,
> 
> 
> I got such log on Host machine :-
> 
> Device returned transfer size 4096
> bytes_per_hash=4096
> Copying data from DFU device to PC
> Starting upload: [] finished!
> Received a total of 1 bytes
> 
> and finally dfu-SPL file created with 4kb size.
> 
> 
> but on target machine, i got
> 
> Running: sf read 0x 0x2 0x0
> Failed to map physical memory.
> 
> May i know why i got such error or user have to specify address over which
> we read our binary

There is no DFU-SPI glue in mainline.  Please post the patches you have
for adding SPI support to DFU, or contact your vendor.

-- 
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Re: [U-Boot] Not able to boot using zImage

[Tom Rini]

On Thu, Jun 20, 2013 at 12:27:02PM +0200, Enric Balletbo Serra wrote:

> Hi all,
> 
> I've some problems trying to boot a zImage with following command after
> load the zImage and the fdt file on memory:
> 
> U-Boot > fdt addr ${dtbaddr}; fdt resize; bootz ${loadaddr} - ${dtbaddr}
[snip]
> The same commands using the uImage instead of zImage works without
> problems. Is expected to work ? Any clue before diving into the problem ?

Same kernel tree?  And you're setting bootargs before you do any of the
above?

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Re: [U-Boot] [PATCH 1/2] PHY: micrel: helper function for KSZ9031

[Stefano Babic]

Hi Joe,

On 20/06/2013 13:26, SARTRE Leo wrote:
> micrel.c: Add function ksz9031_phy_extended_write, helper to MDD
> register write
> micrel.h: Prototype and define MDD registers
> 
> Signed-off-by: Leo Sartre 
> ---
>  drivers/net/phy/micrel.c |   29 +++--
>  include/micrel.h |7 +++
>  2 files changed, 34 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index 2a8b6cb..5b5c11b 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -85,7 +85,7 @@ static int ksz90xx_startup(struct phy_device *phydev)
>  }
>  #ifdef CONFIG_PHY_MICREL_KSZ9021
>  
> -/*
> +/**
>   * KSZ9021
>   */
>  
> @@ -148,9 +148,34 @@ static struct phy_driver ksz9021_driver = {
>  };
>  #endif
>  
> -/*
> +/**
>   * KSZ9031
>   */
> +
> +/* PHY Registers */
> +#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
> +#define MII_KSZ9031_MMD_REG_DATA   0x0e
> +
> +/* Accessors to extended registers*/
> +int ksz9031_phy_extended_write(struct phy_device *phydev,
> +int devaddr,
> +int regnum,
> +u16 val)
> +{
> + /*select register addr for mmd*/
> + phy_write(phydev, MDIO_DEVAD_NONE,
> +  MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
> + /*select register for mmd*/
> + phy_write(phydev, MDIO_DEVAD_NONE,
> +  MII_KSZ9031_MMD_REG_DATA, regnum);
> + /*setup mode*/
> + phy_write(phydev, MDIO_DEVAD_NONE,
> +  MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | 0xC000));
> + /*write the value*/
> + return phy_write(phydev, MDIO_DEVAD_NONE,
> +  MII_KSZ9031_MMD_REG_DATA, val);
> +}
> +
>  static struct phy_driver ksz9031_driver = {
>   .name = "Micrel ksz9031",
>   .uid  = 0x221620,
> diff --git a/include/micrel.h b/include/micrel.h
> index 25e8a46..d63ff45 100644
> --- a/include/micrel.h
> +++ b/include/micrel.h
> @@ -9,8 +9,15 @@
>  #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW   0x106
>  #define MII_KSZ9021_EXT_ANALOG_TEST  0x107
>  
> +#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW  0x4
> +#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW   0x5
> +#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW   0x6
> +#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW 0x8
> +
>  struct phy_device;
>  int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 
> val);
>  int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
>  
> +int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
> +int regnum, u16 val);
>  #endif
> 

This patchset belongs to two are, mainly i.MX (for Congatec) and to
Network (this patch). Can you ACK/NACK this ? I will enqueue the other
two patches in the meantime. To proceed, I propose I can merge then
whole patchset into u-boot-imx to avoid to have inconsistent trees.

Thanks,
Stefano

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Re: [U-Boot] [PATCH v2 2/3] ARM: Congatec: Ethernet: Add support for cgtqmx6qeval

[Otavio Salvador]

On Thu, Jun 20, 2013 at 10:46 AM, SARTRE Leo
 wrote:
> cgtqmx6eval.c: add Micrel KSZ9031  Ethernet transceiver
>
> Signed-off-by: Leo Sartre 

Acked-by: Otavio Salvador 

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Re: [U-Boot] [PATCH v2 1/3] PHY: micrel: helper function for KSZ9031

[Otavio Salvador]

On Thu, Jun 20, 2013 at 10:46 AM, SARTRE Leo
 wrote:
> micrel.c: Add function ksz9031_phy_extended_write, helper to MDD
>   register write
> micrel.h: Prototype and define MDD registers
>
> Signed-off-by: Leo Sartre 

Acked-by: Otavio Salvador 

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Re: [U-Boot] [PATCH v2 3/3] ARM: Congatec: README update

[Otavio Salvador]

On Thu, Jun 20, 2013 at 10:46 AM, SARTRE Leo
 wrote:
> README: U-boot works both on SPI-NOR and SDcard
>
> Signed-off-by: Leo Sartre 

Acked-by: Otavio Salvador 

--
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Re: [U-Boot] [uBoot] [PATCH v2] musb: Move linux and usb compat files to include/linux/usb

[Tom Rini]

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 06/20/2013 09:49 AM, Marek Vasut wrote:
> Dear Dan Murphy,
> 
>> + Marek and a bump
>> 
>> On 06/13/2013 02:07 PM, Dan Murphy wrote:
>>> Move the linux and usb compat files to the include/linux/usb
>>> directory in order for the files to be reused.
>>> 
>>> Added GPLv2 license to the linux and usb compat as well.
>>> 
>>> Signed-off-by: Dan Murphy  --- v2 - Fix
>>> checkpatch issues only for newly introduced code - 
>>> http://patchwork.ozlabs.org/patch/251127/
> 
> Can you please make this into two patches? First adding the license
> and the other doing the move? This way you would be able to even
> git format-patch -MC and reduce the patch to a bare minimum ,
> making it nicely reviewable.
> 
> btw are you sure about the license?

Yes, we have talked with Cogent Embedded.  They did the work while
contracting for TI and we're sharing the copyright.

- -- 
Tom
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Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

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Re: [U-Boot] [uBoot] [PATCH v2] musb: Move linux and usb compat files to include/linux/usb

[Dan Murphy]

Marek
On 06/20/2013 08:49 AM, Marek Vasut wrote:
> Dear Dan Murphy,
>
>> + Marek
>> and a bump
>>
>> On 06/13/2013 02:07 PM, Dan Murphy wrote:
>>> Move the linux and usb compat files to the
>>> include/linux/usb directory in order for the files to be
>>> reused.
>>>
>>> Added GPLv2 license to the linux and usb compat as well.
>>>
>>> Signed-off-by: Dan Murphy 
>>> ---
>>> v2 - Fix checkpatch issues only for newly introduced code -
>>> http://patchwork.ozlabs.org/patch/251127/
> Can you please make this into two patches? First adding the license and the 
> other doing the move? This way you would be able to even git format-patch -MC 
> and reduce the patch to a bare minimum , making it nicely reviewable.
>
> btw are you sure about the license?
>
> Best regards,
> Marek Vasut
Thanks for the review.

I am rethinking the move of these files.

Do you have specific questions on the license?
Because I will still be sending that patch in.

-- 
--
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Axel Lin]

2013/6/20 Marek Vasut 
>
> Dear Axel Lin,
>
> > In current gpio_set_value() implementation, it always sets the gpio control
> > bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
> > low. This patch fixes this bug.
> >
> > Signed-off-by: Axel Lin 
> > ---
> >  drivers/gpio/spear_gpio.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> > index d3c728e..8878608 100644
> > --- a/drivers/gpio/spear_gpio.c
> > +++ b/drivers/gpio/spear_gpio.c
> > @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
> >  {
> >   struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
> >
> > - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > + if (value)
> > + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > + else
> > + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
>
> How can this possibly work? Writing 0 to the whole bank will unset all the
> GPIOs, no ?


Because each GPIO is controlled by a register.
And only one bit will be set when set gpio to high.

So it's safe to write 0 for clearing the bit.

Note, the gpio_get_value() implementation also assumes there is only one bit
will be set. ( If this is not true, both gpio_get_value() and gpio_set_value()
need fix.)

Vipin, can you review this patch and confirm this behavior?

Thanks,
Axel
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Marek Vasut]

Dear Michael Trimarchi,

> Hi
> 
> Il giorno 20/giu/2013 09:14, "Axel Lin"  ha scritto:
> > In current gpio_set_value() implementation, it always sets the gpio
> 
> control bit
> 
> > no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
> > This patch fixes this bug.
> > 
> > Signed-off-by: Axel Lin 
> > ---
> > 
> >  drivers/gpio/spear_gpio.c | 5 -
> >  1 file changed, 4 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> > index d3c728e..8878608 100644
> > --- a/drivers/gpio/spear_gpio.c
> > +++ b/drivers/gpio/spear_gpio.c
> > @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
> > 
> >  {
> >  
> > struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
> > 
> > -   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > +   if (value)
> > +   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > +   else
> > +   writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> > 
> > return 0;
> >  
> >  }
> 
> Does it work the clear? Seems that it sets to 0 all the bank. I'm using the
> mobile

I don't think I speak language of your tribe (lol) ;-)

What's "the mobile" please ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] arm: fix memory coherency problem after relocation

[Marek Vasut]

Dear Mike Dunn,

> On the xscale, the icache must be invalidated and the write buffers drained
> after writing code over the data bus, even if the caches are disabled. 
> After rebasing with the main git repository, u-boot began crashing in odd
> places on my pxa270 board (palmtreo680) after the code relocation routine
> ran.  This patch fixes it.  Cache coherency problems are often
> hit-and-miss (ha ha), and this latent problem didn't rear its ugly head
> until now.  Tested on the pxa270.
> 
> Signed-off-by: Mike Dunn 
> ---
> 
> I realize that __ARM_ARCH_5TE__ does not necessarily mean xscale.

We should introduce some CONFIG_PXA I guess.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v6 0/2] pxa: add support for palmtreo680 board

[Marek Vasut]

Dear Mike Dunn,

> These two patches add support for the Palm Treo 680 phone.  The second
> patch provides a userspace utility that is needed to program u-boot to the
> docg4 nand flash in the manner required by the phone's IPL.
> 
> Marek, I thought that these patches were in your tree when you issued the
> PR a few weeks ago, but I must have been mistaken.  Sorry.
> 
> I would have labeled these patches RESEND, but since I submitted v5 I
> learned that README files now go into the board/ directory, so I made that
> change and called it v6.  Each patch contains its full changelog.

Sorry, it must have gone lost. I applied them and will push them shortly.

Best regards,
Marek Vasut
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[U-Boot] [PATCH v2 3/3] ARM: Congatec: README update

[SARTRE Leo]

README: U-boot works both on SPI-NOR and SDcard

Signed-off-by: Leo Sartre 
---
 board/congatec/cgtqmx6eval/README |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/board/congatec/cgtqmx6eval/README 
b/board/congatec/cgtqmx6eval/README
index bbf0f75..5e76d2a 100644
--- a/board/congatec/cgtqmx6eval/README
+++ b/board/congatec/cgtqmx6eval/README
@@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
 1. Boot source, boot from SD card
 -
 
-This version of u-boot works only on the SD card. By default, the
-Congatec board can boot only from the SPI-NOR.
+By default, the Congatec board can boot only from the SPI-NOR.
 But, with the u-boot version provided with the board you can write boot
 registers to force the board to reboot and boot from the SD slot. If
 "bmode" command is not available from your pre-installed u-boot, these
-- 
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[U-Boot] [PATCH v2 1/3] PHY: micrel: helper function for KSZ9031

[SARTRE Leo]

micrel.c: Add function ksz9031_phy_extended_write, helper to MDD
  register write
micrel.h: Prototype and define MDD registers

Signed-off-by: Leo Sartre 
---
 drivers/net/phy/micrel.c |   25 +
 include/micrel.h |7 +++
 2 files changed, 32 insertions(+)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 2a8b6cb..404faac 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -151,6 +151,31 @@ static struct phy_driver ksz9021_driver = {
 /*
  * KSZ9031
  */
+
+/* PHY Registers */
+#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
+#define MII_KSZ9031_MMD_REG_DATA   0x0e
+
+/* Accessors to extended registers*/
+int ksz9031_phy_extended_write(struct phy_device *phydev,
+  int devaddr,
+  int regnum,
+  u16 val)
+{
+   /*select register addr for mmd*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
+   /*select register for mmd*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9031_MMD_REG_DATA, regnum);
+   /*setup mode*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+ MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | 0xC000));
+   /*write the value*/
+   return phy_write(phydev, MDIO_DEVAD_NONE,
+MII_KSZ9031_MMD_REG_DATA, val);
+}
+
 static struct phy_driver ksz9031_driver = {
.name = "Micrel ksz9031",
.uid  = 0x221620,
diff --git a/include/micrel.h b/include/micrel.h
index 25e8a46..d63ff45 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -9,8 +9,15 @@
 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
 #define MII_KSZ9021_EXT_ANALOG_TEST0x107
 
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW0x4
+#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
+#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
+#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW   0x8
+
 struct phy_device;
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
 
+int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
+  int regnum, u16 val);
 #endif
-- 
1.7.10.4
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[U-Boot] [PATCH v2 0/3] Add ethernet support for Congatec qmx6qeval

[SARTRE Leo]

Changes in v2:
-micrel.c : drop two unneeded changes in comments.
-cgtqmx6eval.c: #ifdef CONFIG_FEC_MXC now covers the whole
function board_eth_init.
-README   : placed in a separate patch.

Leo Sartre (3):
  PHY: micrel: helper function for KSZ9031
  ARM: Congatec: Ethernet: Add support for cgtqmx6qeval
  ARM: Congatec: README update

 board/congatec/cgtqmx6eval/README|3 +-
 board/congatec/cgtqmx6eval/cgtqmx6eval.c |  111 ++
 drivers/net/phy/micrel.c |   25 +++
 include/configs/cgtqmx6eval.h|   13 
 include/micrel.h |7 ++
 5 files changed, 157 insertions(+), 2 deletions(-)

-- 
1.7.10.4
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[U-Boot] [PATCH v2 2/3] ARM: Congatec: Ethernet: Add support for cgtqmx6qeval

[SARTRE Leo]

cgtqmx6eval.c: add Micrel KSZ9031  Ethernet transceiver

Signed-off-by: Leo Sartre 
---
 board/congatec/cgtqmx6eval/cgtqmx6eval.c |  111 ++
 include/configs/cgtqmx6eval.h|   13 
 2 files changed, 124 insertions(+)

diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c 
b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index f70f674..c769868 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -76,6 +81,112 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_NANDF_D6__GPIO_2_6| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
+iomux_v3_cfg_t const enet_pads1[] = {
+   MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_ENET_MDC__ENET_MDC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TXC__ENET_RGMII_TXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD0__ENET_RGMII_TD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD1__ENET_RGMII_TD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD2__ENET_RGMII_TD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD3__ENET_RGMII_TD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_GPIO_0__CCM_CLKO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_GPIO_3__CCM_CLKO2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_ENET_REF_CLK__ENET_TX_CLK   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   /* pin 35 - 1 (PHY_AD2) on reset */
+   MX6_PAD_RGMII_RXC__GPIO_6_30| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 32 - 1 - (MODE0) all */
+   MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 31 - 1 - (MODE1) all */
+   MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 28 - 1 - (MODE2) all */
+   MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 27 - 1 - (MODE3) all */
+   MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+   MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 42 PHY nRST */
+   MX6_PAD_EIM_D23__GPIO_3_23  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+   MX6_PAD_RGMII_RXC__ENET_RGMII_RXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD0__ENET_RGMII_RD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD1__ENET_RGMII_RD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD2__ENET_RGMII_RD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD3__ENET_RGMII_RD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+   gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+   imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+   gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+   /* Need delay 10ms according to KSZ9031 spec */
+   udelay(1000 * 10);
+   gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+   imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+   ksz9031_phy_extended_write(phydev, 2,
+   MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
+   0x);
+   ksz9031_phy_extended_write(phydev, 2,
+   MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
+   0x);
+   ksz9031_phy_extended_write(phydev, 2,
+   MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
+   0x);
+   ksz9031_phy_extended_write(phydev, 2,
+   MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
+   0x3FFF);
+
+   phydev->drv->config(phydev);
+
+   return 0;
+}
+
+#ifdef CONFIG_FEC_MXC
+int board_eth_init(bd_t *bis)
+{
+   uint32_t base = IMX_FEC_BASE;
+   struct mii_dev *bus = NULL;
+   struct phy_device *ph

Re: [U-Boot] [uBoot] [PATCH v2] musb: Move linux and usb compat files to include/linux/usb

[Marek Vasut]

Dear Dan Murphy,

> + Marek
> and a bump
> 
> On 06/13/2013 02:07 PM, Dan Murphy wrote:
> > Move the linux and usb compat files to the
> > include/linux/usb directory in order for the files to be
> > reused.
> > 
> > Added GPLv2 license to the linux and usb compat as well.
> > 
> > Signed-off-by: Dan Murphy 
> > ---
> > v2 - Fix checkpatch issues only for newly introduced code -
> > http://patchwork.ozlabs.org/patch/251127/

Can you please make this into two patches? First adding the license and the 
other doing the move? This way you would be able to even git format-patch -MC 
and reduce the patch to a bare minimum , making it nicely reviewable.

btw are you sure about the license?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Marek Vasut]

Dear Axel Lin,

> In current gpio_set_value() implementation, it always sets the gpio control
> bit no matter the value argument is 0 or 1. Thus the GPIOs never set to
> low. This patch fixes this bug.
> 
> Signed-off-by: Axel Lin 
> ---
>  drivers/gpio/spear_gpio.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> index d3c728e..8878608 100644
> --- a/drivers/gpio/spear_gpio.c
> +++ b/drivers/gpio/spear_gpio.c
> @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
>  {
>   struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
> 
> - writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> + if (value)
> + writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> + else
> + writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);

How can this possibly work? Writing 0 to the whole bank will unset all the 
GPIOs, no ?

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH v2] Add support for Wandboard quad.

[Otavio Salvador]

Hello Tapani,

On Tue, May 28, 2013 at 5:04 AM, Tapani Utriainen  wrote:
>
> Add support for Wandboard quad.
>
> Signed-off-by: Tapani Utriainen 

Can you handle the comments done by Wolfgang and Stefano?

It'd be very good to have it merged for 2013.07 but we're getting short on time.

--
Otavio Salvador O.S. Systems
http://www.ossystems.com.brhttp://projetos.ossystems.com.br
Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
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[U-Boot] [PATCH v4 5/6] powerpc/ppc4xx: Consider gdsys FPGA OSD size

[dirk . eibach]

From: Dirk Eibach 

OSD size was constant 32x16 characters.
Now the size is set as announced by the FPGA.

Signed-off-by: Dirk Eibach 
---
Changes in v4: None
Changes in v3: None
Changes in v2: None

 board/gdsys/common/osd.c | 34 ++
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/board/gdsys/common/osd.c b/board/gdsys/common/osd.c
index 5ddd098..ba8c6e1 100644
--- a/board/gdsys/common/osd.c
+++ b/board/gdsys/common/osd.c
@@ -42,10 +42,6 @@
 
 #define PIXCLK_640_480_60 2518
 
-#define BASE_WIDTH 32
-#define BASE_HEIGHT 16
-#define BUFSIZE (BASE_WIDTH * BASE_HEIGHT)
-
 enum {
CH7301_CM = 0x1c,   /* Clock Mode Register */
CH7301_IC = 0x1d,   /* Input Clock Register */
@@ -67,6 +63,11 @@ enum {
CH7301_DSP = 0x56,  /* DVI Sync polarity Register */
 };
 
+unsigned int base_width;
+unsigned int base_height;
+size_t bufsize;
+u16 *buf;
+
 unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
 
 #ifdef CONFIG_SYS_CH7301
@@ -280,7 +281,7 @@ static int osd_write_videomem(unsigned screen, unsigned 
offset,
unsigned int k;
 
for (k = 0; k < charcount; ++k) {
-   if (offset + k >= BUFSIZE)
+   if (offset + k >= bufsize)
return -1;
FPGA_SET_REG(screen, videomem[offset + k], data[k]);
}
@@ -299,7 +300,6 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
unsigned len;
u8 color;
unsigned int k;
-   u16 buf[BUFSIZE];
char *text;
int res;
 
@@ -313,12 +313,12 @@ static int osd_print(cmd_tbl_t *cmdtp, int flag, int 
argc, char * const argv[])
color = simple_strtoul(argv[3], NULL, 16);
text = argv[4];
charcount = strlen(text);
-   len = (charcount > BUFSIZE) ? BUFSIZE : charcount;
+   len = (charcount > bufsize) ? bufsize : charcount;
 
for (k = 0; k < len; ++k)
buf[k] = (text[k] << 8) | color;
 
-   res = osd_write_videomem(screen, y * BASE_WIDTH + x, buf, len);
+   res = osd_write_videomem(screen, y * base_width + x, buf, len);
if (res < 0)
return res;
}
@@ -330,8 +330,6 @@ int osd_probe(unsigned screen)
 {
u16 version;
u16 features;
-   unsigned width;
-   unsigned height;
u8 value;
 #ifdef CONFIG_SYS_CH7301
int old_bus = i2c_get_bus_num();
@@ -340,11 +338,15 @@ int osd_probe(unsigned screen)
FPGA_GET_REG(0, osd.version, &version);
FPGA_GET_REG(0, osd.features, &features);
 
-   width = ((features & 0x3f00) >> 8) + 1;
-   height = (features & 0x001f) + 1;
+   base_width = ((features & 0x3f00) >> 8) + 1;
+   base_height = (features & 0x001f) + 1;
+   bufsize = base_width * base_height;
+   buf = malloc(sizeof(u16) * bufsize);
+   if (!buf)
+   return -1;
 
printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
-   screen, version/100, version%100, width, height);
+   screen, version/100, version%100, base_width, base_height);
 
 #ifdef CONFIG_SYS_CH7301
i2c_set_bus_num(ch7301_i2c[screen]);
@@ -410,7 +412,7 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char * 
const argv[])
unsigned x;
unsigned y;
unsigned k;
-   u16 buffer[BASE_WIDTH];
+   u16 buffer[base_width];
char *rp;
u16 *wp = buffer;
unsigned count = (argc > 4) ?
@@ -435,13 +437,13 @@ int osd_write(cmd_tbl_t *cmdtp, int flag, int argc, char 
* const argv[])
 
rp += 4;
wp++;
-   if (wp - buffer > BASE_WIDTH)
+   if (wp - buffer > base_width)
break;
}
 
for (k = 0; k < count; ++k) {
unsigned offset =
-   y * BASE_WIDTH + x + k * (wp - buffer);
+   y * base_width + x + k * (wp - buffer);
osd_write_videomem(screen, offset, buffer,
wp - buffer);
}
-- 
1.8.3

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[U-Boot] [PATCH v4 1/6] powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA

[dirk . eibach]

From: Dirk Eibach 

A set of accessor functions was added to be able to access not only
memory mapped FPGA in a generic way.

Thanks to Wolfgang Denk for getting this sorted properly.

Signed-off-by: Dirk Eibach 
---
Changes in v4:
- Move unrelated changes ins osd.c to proper commit
- explain why fpga_gpio_ functions are actually useful
- factor out common code for fpga register access
- use macro instead of #ifdef for reflection test

Changes in v3:
- squashed with "Add generic accessor functions for gdsys FPGA"
- strictly replace base address plus offset with  proper C structs

Changes in v2: None

 board/gdsys/405ep/405ep.c| 22 +++---
 board/gdsys/405ep/dlvision-10g.c | 18 +++
 board/gdsys/405ep/io.c   | 16 ++
 board/gdsys/405ep/iocon.c| 24 ++-
 board/gdsys/405ep/neo.c  | 13 +---
 board/gdsys/405ex/405ex.c| 22 +++---
 board/gdsys/405ex/io64.c | 34 +++--
 board/gdsys/common/Makefile  |  2 ++
 board/gdsys/common/osd.c | 66 ++--
 include/configs/dlvision-10g.h   |  6 
 include/configs/io.h |  5 +++
 include/configs/io64.h   |  6 
 include/configs/iocon.h  |  5 +++
 include/configs/neo.h|  5 +++
 include/gdsys_fpga.h | 43 +-
 15 files changed, 188 insertions(+), 99 deletions(-)

diff --git a/board/gdsys/405ep/405ep.c b/board/gdsys/405ep/405ep.c
index 6221171..003911d 100644
--- a/board/gdsys/405ep/405ep.c
+++ b/board/gdsys/405ep/405ep.c
@@ -34,6 +34,12 @@
 #define REFLECTION_TESTPATTERN 0xdede
 #define REFLECTION_TESTPATTERN_INV (~REFLECTION_TESTPATTERN & 0x)
 
+#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
+#define REFLECTION_TESTREG reflection_low
+#else
+#define REFLECTION_TESTREG reflection_high
+#endif
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int get_fpga_state(unsigned dev)
@@ -106,23 +112,17 @@ int board_early_init_r(void)
gd405ep_set_fpga_reset(0);
 
for (k = 0; k < CONFIG_SYS_FPGA_COUNT; ++k) {
-   struct ihs_fpga *fpga =
-   (struct ihs_fpga *)CONFIG_SYS_FPGA_BASE(k);
-#ifdef CONFIG_SYS_FPGA_NO_RFL_HI
-   u16 *reflection_target = &fpga->reflection_low;
-#else
-   u16 *reflection_target = &fpga->reflection_high;
-#endif
/*
 * wait for fpga out of reset
 */
ctr = 0;
while (1) {
-   out_le16(&fpga->reflection_low,
-   REFLECTION_TESTPATTERN);
+   u16 val;
+
+   FPGA_SET_REG(k, reflection_low, REFLECTION_TESTPATTERN);
 
-   if (in_le16(reflection_target) ==
-   REFLECTION_TESTPATTERN_INV)
+   FPGA_GET_REG(k, REFLECTION_TESTREG, &val);
+   if (val == REFLECTION_TESTPATTERN_INV)
break;
 
udelay(10);
diff --git a/board/gdsys/405ep/dlvision-10g.c b/board/gdsys/405ep/dlvision-10g.c
index 644493b..16cd5a9 100644
--- a/board/gdsys/405ep/dlvision-10g.c
+++ b/board/gdsys/405ep/dlvision-10g.c
@@ -71,6 +71,8 @@ enum {
RAM_DDR2_64 = 2,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
/* startup fans */
@@ -95,10 +97,9 @@ static unsigned int get_mc2_present(void)
 
 static void print_fpga_info(unsigned dev)
 {
-   struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(dev);
-   u16 versions = in_le16(&fpga->versions);
-   u16 fpga_version = in_le16(&fpga->fpga_version);
-   u16 fpga_features = in_le16(&fpga->fpga_features);
+   u16 versions;
+   u16 fpga_version;
+   u16 fpga_features;
unsigned unit_type;
unsigned hardware_version;
unsigned feature_rs232;
@@ -112,6 +113,10 @@ static void print_fpga_info(unsigned dev)
 
printf("FPGA%d: ", dev);
 
+   FPGA_GET_REG(dev, versions, &versions);
+   FPGA_GET_REG(dev, fpga_version, &fpga_version);
+   FPGA_GET_REG(dev, fpga_features, &fpga_features);
+
hardware_version = versions & 0x000f;
 
if (fpga_state
@@ -263,8 +268,9 @@ int checkboard(void)
 
 int last_stage_init(void)
 {
-   struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
-   u16 versions = in_le16(&fpga->versions);
+   u16 versions;
+
+   FPGA_GET_REG(0, versions, &versions);
 
print_fpga_info(0);
if (get_mc2_present())
diff --git a/board/gdsys/405ep/io.c b/board/gdsys/405ep/io.c
index 070dcbb..e77ed1e 100644
--- a/board/gdsys/405ep/io.c
+++ b/board/gdsys/405ep/io.c
@@ -53,6 +53,8 @@ enum {
HWVER_122 = 3,
 };
 
+struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
+
 int misc_init_r(void)
 {
/* startup fans */
@@ -117,15 +119,18 @@ int checkboard(void)
 
 static void print_fpga_info(void)
 {
-  

[U-Boot] [PATCH v4 4/6] powerpc/ppc4xx: Support gdsys multichannel iocon hardware

[dirk . eibach]

From: Dirk Eibach 

Signed-off-by: Dirk Eibach 
---
Changes in v4:
- Move changes ins osd.c to proper commit
- do not use common FPGA register accessors here

Changes in v3:
- adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA"
- squashed with powerpc/ppc4xx: Fixup phy erratum on gdsys iocon hardware

Changes in v2:
- fpga_state has been moved to arch_global_data
- include cmd_fpgad in iocon
- use multibus soft-i2c in iocon

 board/gdsys/405ep/iocon.c   | 468 
 board/gdsys/common/Makefile |   2 +-
 board/gdsys/common/osd.c|  20 +-
 include/configs/iocon.h |  58 --
 include/gdsys_fpga.h|  15 +-
 5 files changed, 510 insertions(+), 53 deletions(-)

diff --git a/board/gdsys/405ep/iocon.c b/board/gdsys/405ep/iocon.c
index 249d901..fe14f36 100644
--- a/board/gdsys/405ep/iocon.c
+++ b/board/gdsys/405ep/iocon.c
@@ -23,6 +23,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -31,6 +32,15 @@
 #include 
 
 #include "../common/osd.h"
+#include "../common/mclink.h"
+
+#include 
+#include 
+#include 
+
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
@@ -47,11 +57,20 @@ enum {
HWVER_100 = 0,
HWVER_104 = 1,
HWVER_110 = 2,
+   HWVER_120 = 3,
+   HWVER_200 = 4,
+   HWVER_210 = 5,
+};
+
+enum {
+   FPGA_HWVER_200 = 0,
+   FPGA_HWVER_210 = 1,
 };
 
 enum {
COMPRESSION_NONE = 0,
-   COMPRESSION_TYPE1_DELTA,
+   COMPRESSION_TYPE1_DELTA = 1,
+   COMPRESSION_TYPE1_TYPE2_DELTA = 3,
 };
 
 enum {
@@ -67,10 +86,71 @@ enum {
 
 enum {
RAM_DDR2_32 = 0,
+   RAM_DDR3_32 = 1,
+};
+
+enum {
+   MCFPGA_DONE = 1 << 0,
+   MCFPGA_INIT_N = 1 << 1,
+   MCFPGA_PROGRAM_N = 1 << 2,
+   MCFPGA_UPDATE_ENABLE_N = 1 << 3,
+   MCFPGA_RESET_N = 1 << 4,
+};
+
+enum {
+   GPIO_MDC = 1 << 14,
+   GPIO_MDIO = 1 << 15,
 };
 
+unsigned int mclink_fpgacount;
 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
 
+static int setup_88e1518(const char *bus, unsigned char addr);
+static int verify_88e1518(const char *bus, unsigned char addr);
+
+int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data)
+{
+   int res;
+
+   switch (fpga) {
+   case 0:
+   out_le16(reg, data);
+   break;
+   default:
+   res = mclink_send(fpga - 1, regoff, data);
+   if (res < 0) {
+   printf("mclink_send reg %02lx data %04x returned %d\n",
+  regoff, data, res);
+   return res;
+   }
+   break;
+   }
+
+   return 0;
+}
+
+int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data)
+{
+   int res;
+
+   switch (fpga) {
+   case 0:
+   *data = in_le16(reg);
+   break;
+   default:
+   if (fpga > mclink_fpgacount)
+   return -EINVAL;
+   res = mclink_receive(fpga - 1, regoff, data);
+   if (res < 0) {
+   printf("mclink_receive reg %02lx returned %d\n",
+  regoff, res);
+   return res;
+   }
+   }
+
+   return 0;
+}
+
 /*
  * Check Board Identity:
  */
@@ -92,7 +172,7 @@ int checkboard(void)
return 0;
 }
 
-static void print_fpga_info(void)
+static void print_fpga_info(unsigned int fpga)
 {
u16 versions;
u16 fpga_version;
@@ -106,13 +186,13 @@ static void print_fpga_info(void)
unsigned feature_ramconfig;
unsigned feature_carriers;
unsigned feature_video_channels;
+   int legacy = get_fpga_state(0) & FPGA_STATE_PLATFORM;
 
FPGA_GET_REG(0, versions, &versions);
FPGA_GET_REG(0, fpga_version, &fpga_version);
FPGA_GET_REG(0, fpga_features, &fpga_features);
 
unit_type = (versions & 0xf000) >> 12;
-   hardware_version = versions & 0x000f;
feature_compression = (fpga_features & 0xe000) >> 13;
feature_osd = fpga_features & (1<<11);
feature_audio = (fpga_features & 0x0600) >> 9;
@@ -121,6 +201,9 @@ static void print_fpga_info(void)
feature_carriers = (fpga_features & 0x000c) >> 2;
feature_video_channels = fpga_features & 0x0003;
 
+   if (legacy)
+   printf("legacy ");
+
switch (unit_type) {
case UNITTYPE_MAIN_USER:
printf("Mainchannel");
@@ -135,27 +218,68 @@ static void print_fpga_info(void)
break;
}
 
-   switch (hardware_version) {
-   case HWVER_100:
-   printf(" HW-Ver 1.00\n");
-   break;
-
-   case HWVER_104:
-   printf(" HW-Ver 1.04\n");
-   break;
-
-   case HWVER_110:
-   printf(" HW-Ver 1.10\n");
-   break;
+   if (unit_type == UNITTYPE_MAIN_USER) 

[U-Boot] [PATCH v4 3/6] powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers

[dirk . eibach]

From: Dirk Eibach 

Signed-off-by: Dirk Eibach 
---
Changes in v4: None
Changes in v3:
- adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA"

Changes in v2:
- move cmd_fpgad to common and fix whitespace issues
- update email account

 common/Makefile|   1 +
 common/cmd_fpgad.c | 100 +
 2 files changed, 101 insertions(+)
 create mode 100644 common/cmd_fpgad.c

diff --git a/common/Makefile b/common/Makefile
index 3ba4316..b1a2093 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -110,6 +110,7 @@ COBJS-$(CONFIG_CMD_FLASH) += cmd_flash.o
 ifdef CONFIG_FPGA
 COBJS-$(CONFIG_CMD_FPGA) += cmd_fpga.o
 endif
+COBJS-$(CONFIG_CMD_FPGAD) += cmd_fpgad.o
 COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o
 COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o
 COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
diff --git a/common/cmd_fpgad.c b/common/cmd_fpgad.c
new file mode 100644
index 000..07536ff
--- /dev/null
+++ b/common/cmd_fpgad.c
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2013
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc
+ *
+ * based on cmd_mem.c
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+
+#include 
+
+static uintdp_last_fpga;
+static uintdp_last_addr;
+static uintdp_last_length = 0x40;
+
+/*
+ * FPGA Memory Display
+ *
+ * Syntax:
+ * fpgad {fpga} {addr} {len}
+ */
+#define DISP_LINE_LEN  16
+int do_fpga_md(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+   unsigned int k;
+   unsigned int fpga;
+   ulong   addr, length;
+   int rc = 0;
+   u16 linebuf[DISP_LINE_LEN/sizeof(u16)];
+
+   /*
+* We use the last specified parameters, unless new ones are
+* entered.
+*/
+   fpga = dp_last_fpga;
+   addr = dp_last_addr;
+   length = dp_last_length;
+
+   if (argc < 3)
+   return CMD_RET_USAGE;
+
+   if ((flag & CMD_FLAG_REPEAT) == 0) {
+   /*
+* FPGA is specified since argc > 2
+*/
+   fpga = simple_strtoul(argv[1], NULL, 16);
+
+   /*
+* Address is specified since argc > 2
+*/
+   addr = simple_strtoul(argv[2], NULL, 16);
+
+   /*
+* If another parameter, it is the length to display.
+* Length is the number of objects, not number of bytes.
+*/
+   if (argc > 3)
+   length = simple_strtoul(argv[3], NULL, 16);
+   }
+
+   /* Print the lines. */
+   for (k = 0; k < DISP_LINE_LEN / sizeof(u16); ++k)
+   fpga_get_reg(fpga, (u16 *)fpga_ptr[fpga] + k, k * sizeof(u16),
+&linebuf[k]);
+   print_buffer(addr, (void *)linebuf, sizeof(u16),
+length, DISP_LINE_LEN / sizeof(u16));
+   addr += sizeof(u16)*length;
+
+   dp_last_fpga = fpga;
+   dp_last_addr = addr;
+   dp_last_length = length;
+   return rc;
+}
+
+U_BOOT_CMD(
+   fpgad,  4,  1,  do_fpga_md,
+   "fpga register display",
+   "fpga address [# of objects]"
+);
-- 
1.8.3

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[U-Boot] [PATCH v4 6/6] powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards

[dirk . eibach]

From: Dirk Eibach 

CONFIG_SYS_FLASH_PROTECTION was active on most gdsys boards by default,
while hardware flash protection was not implemented.
Hardware support was added recently and we get into trouble because backward
compatibility is broken (u-boot can't unprotect the protected flash after a
downgrade). So we decided to disable hardware flash protection for all our 
boards.

Signed-off-by: Dirk Eibach 
---
Changes in v4: None
Changes in v3: None
Changes in v2: None

 include/configs/dlvision-10g.h | 3 +--
 include/configs/dlvision.h | 3 +--
 include/configs/io.h   | 3 +--
 include/configs/iocon.h| 3 +--
 include/configs/neo.h  | 3 +--
 5 files changed, 5 insertions(+), 10 deletions(-)

diff --git a/include/configs/dlvision-10g.h b/include/configs/dlvision-10g.h
index 8af7848..a147c00 100644
--- a/include/configs/dlvision-10g.h
+++ b/include/configs/dlvision-10g.h
@@ -34,7 +34,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAMEdlvsion-10g
-#define CONFIG_IDENT_STRING" dlvision-10g 0.03"
+#define CONFIG_IDENT_STRING" dlvision-10g 0.04"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -167,7 +167,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION1   /* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST1   /* no warn upon unknown flash */
diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h
index 24c9fa4..948930e 100644
--- a/include/configs/dlvision.h
+++ b/include/configs/dlvision.h
@@ -34,7 +34,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAMEdlvision
-#define CONFIG_IDENT_STRING" dlvision 0.01"
+#define CONFIG_IDENT_STRING" dlvision 0.02"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F  /* call board_early_init_f */
@@ -125,7 +125,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION1   /* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST1   /* no warn upon unknown flash */
diff --git a/include/configs/io.h b/include/configs/io.h
index f5b4d79..9272ee6 100644
--- a/include/configs/io.h
+++ b/include/configs/io.h
@@ -34,7 +34,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAMEio
-#define CONFIG_IDENT_STRING" io 0.05"
+#define CONFIG_IDENT_STRING" io 0.06"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -139,7 +139,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION1   /* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST1   /* no warn upon unknown flash */
diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 561837c..fd93e9f 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -34,7 +34,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAMEiocon
-#define CONFIG_IDENT_STRING" iocon 0.04"
+#define CONFIG_IDENT_STRING" iocon 0.05"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -188,7 +188,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Timeout for Flash Write/ms */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buff'd writes */
-#define CONFIG_SYS_FLASH_PROTECTION1   /* use hardware flash protect */
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO/* 'E' for empty sector on flinfo */
 #define CONFIG_SYS_FLASH_QUIET_TEST1   /* no warn upon unknown flash */
diff --git a/include/configs/neo.h b/include/configs/neo.h
index d1e07ae..d16db4f 100644
--- a/include/configs/neo.h
+++ b/include/configs/neo.h
@@ -35,7 +35,7 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAMEneo
-#define CONFIG_IDENT_STRING" neo 0.01"
+#define CONFIG_IDENT_STRING" neo 0.02"
 #include "amcc-common.h"
 
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -146,7 +146,6 @@
 #define CONFIG_SYS_FLASH_WRITE_TOUT500 /* Timeout for Flash Write (in 
ms)  */
 
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1/* use buffered writes (20x 
faster) */
-#define CONFIG_SYS_FLASH_PROTECTION1   /* use hardware flash 
protection*/
 
 #defin

[U-Boot] [PATCH v4 2/6] powerpc/ppc4xx: Add gdsys mclink interface

[dirk . eibach]

From: Dirk Eibach 

mclink is a serial interface for communication between gdsys FPGA.

Signed-off-by: Dirk Eibach 
---
Changes in v4: None
Changes in v3:
- adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA"
- squashed with "powerpc/ppc4xx: Increase timeout for gdsys mclink bus startup"

Changes in v2:
- update email account

 board/gdsys/common/mclink.c | 153 
 board/gdsys/common/mclink.h |  31 +
 2 files changed, 184 insertions(+)
 create mode 100644 board/gdsys/common/mclink.c
 create mode 100644 board/gdsys/common/mclink.h

diff --git a/board/gdsys/common/mclink.c b/board/gdsys/common/mclink.c
new file mode 100644
index 000..e0382a3
--- /dev/null
+++ b/board/gdsys/common/mclink.c
@@ -0,0 +1,153 @@
+/*
+ * (C) Copyright 2012
+ * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eib...@gdsys.cc
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+
+enum {
+   MCINT_SLAVE_LINK_CHANGED_EV = 1 << 7,
+   MCINT_TX_ERROR_EV = 1 << 9,
+   MCINT_TX_BUFFER_FREE = 1 << 10,
+   MCINT_TX_PACKET_TRANSMITTED_EV = 1 << 11,
+   MCINT_RX_ERROR_EV = 1 << 13,
+   MCINT_RX_CONTENT_AVAILABLE = 1 << 14,
+   MCINT_RX_PACKET_RECEIVED_EV = 1 << 15,
+};
+
+int mclink_probe(void)
+{
+   unsigned int k;
+   int slaves = 0;
+
+   for (k = 0; k < CONFIG_SYS_MCLINK_MAX; ++k) {
+   int timeout = 0;
+   unsigned int ctr = 0;
+   u16 mc_status;
+
+   FPGA_GET_REG(k, mc_status, &mc_status);
+
+   if (!(mc_status & (1 << 15)))
+   break;
+
+   FPGA_SET_REG(k, mc_control, 0x8000);
+
+   FPGA_GET_REG(k, mc_status, &mc_status);
+   while (!(mc_status & (1 << 14))) {
+   udelay(100);
+   if (ctr++ > 500) {
+   timeout = 1;
+   break;
+   }
+   FPGA_GET_REG(k, mc_status, &mc_status);
+   }
+   if (timeout)
+   break;
+
+   printf("waited %d us for mclink %d to come up\n", ctr * 100, k);
+
+   slaves++;
+   }
+
+   return slaves;
+}
+
+int mclink_send(u8 slave, u16 addr, u16 data)
+{
+   unsigned int ctr = 0;
+   u16 int_status;
+   u16 rx_cmd_status;
+   u16 rx_cmd;
+
+   /* reset interrupt status */
+   FPGA_GET_REG(0, mc_int, &int_status);
+   FPGA_SET_REG(0, mc_int, int_status);
+
+   /* send */
+   FPGA_SET_REG(0, mc_tx_address, addr);
+   FPGA_SET_REG(0, mc_tx_data, data);
+   FPGA_SET_REG(0, mc_tx_cmd, (slave & 0x03) << 14);
+   FPGA_SET_REG(0, mc_control, 0x8001);
+
+   /* wait for reply */
+   FPGA_GET_REG(0, mc_int, &int_status);
+   while (!(int_status & MCINT_RX_PACKET_RECEIVED_EV)) {
+   udelay(100);
+   if (ctr++ > 3)
+   return -ETIMEDOUT;
+   FPGA_GET_REG(0, mc_int, &int_status);
+   }
+
+   FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+   rx_cmd = (rx_cmd_status >> 12) & 0x03;
+   if (rx_cmd != 0)
+   printf("mclink_send: received cmd %d, expected %d\n", rx_cmd,
+  0);
+
+   return 0;
+}
+
+int mclink_receive(u8 slave, u16 addr, u16 *data)
+{
+   u16 rx_cmd_status;
+   u16 rx_cmd;
+   u16 int_status;
+   unsigned int ctr = 0;
+
+   /* send read request */
+   FPGA_SET_REG(0, mc_tx_address, addr);
+   FPGA_SET_REG(0, mc_tx_cmd,
+((slave & 0x03) << 14) | (1 << 12) | (1 << 0));
+   FPGA_SET_REG(0, mc_control, 0x8001);
+
+
+   /* wait for reply */
+   FPGA_GET_REG(0, mc_int, &int_status);
+   while (!(int_status & MCINT_RX_CONTENT_AVAILABLE)) {
+   udelay(100);
+   if (ctr++ > 3)
+   return -ETIMEDOUT;
+   FPGA_GET_REG(0, mc_int, &int_status);
+   }
+
+   /* check reply */
+   FPGA_GET_REG(0, mc_rx_cmd_status, &rx_cmd_status);
+   if ((rx_cmd_status >> 14) != slave) {
+   printf("mclink

[U-Boot] [PATCH v4 0/6] Update gdsys ppc4xx-based boards

[dirk . eibach]

From: Dirk Eibach 


This series depends on the "Bring in new I2C framework" series by Heiko 
Schocher.
Patch "powerpc/ppc4xx: Add bitbang i2c interface for gdsys boards" was dropped 
in
favor of using the new framework.

Changes in v4:
- Move changes ins osd.c to proper commit
- Move unrelated changes ins osd.c to proper commit
- do not use common FPGA register accessors here
- explain why fpga_gpio_ functions are actually useful
- factor out common code for fpga register access
- use macro instead of #ifdef for reflection test

Changes in v3:
- adapt to "powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA"
- squashed with "Add generic accessor functions for gdsys FPGA"
- squashed with "powerpc/ppc4xx: Increase timeout for gdsys mclink bus startup"
- squashed with powerpc/ppc4xx: Fixup phy erratum on gdsys iocon hardware
- strictly replace base address plus offset with  proper C structs

Changes in v2:
- fpga_state has been moved to arch_global_data
- include cmd_fpgad in iocon
- move cmd_fpgad to common and fix whitespace issues
- update email account
- use multibus soft-i2c in iocon

Dirk Eibach (6):
  powerpc/ppc4xx: Use generic accessor functions for gdsys FPGA
  powerpc/ppc4xx: Add gdsys mclink interface
  powerpc/ppc4xx: Add fpgad command for dumping gdsys fpga registers
  powerpc/ppc4xx: Support gdsys multichannel iocon hardware
  powerpc/ppc4xx: Consider gdsys FPGA OSD size
  powerpc/ppc4xx: Remove CONFIG_SYS_FLASH_PROTECTION from gdsys boards

 board/gdsys/405ep/405ep.c|  22 +-
 board/gdsys/405ep/dlvision-10g.c |  18 +-
 board/gdsys/405ep/io.c   |  16 +-
 board/gdsys/405ep/iocon.c| 486 +++
 board/gdsys/405ep/neo.c  |  13 +-
 board/gdsys/405ex/405ex.c|  22 +-
 board/gdsys/405ex/io64.c |  34 +--
 board/gdsys/common/Makefile  |   4 +-
 board/gdsys/common/mclink.c  | 153 
 board/gdsys/common/mclink.h  |  31 +++
 board/gdsys/common/osd.c | 118 ++
 common/Makefile  |   1 +
 common/cmd_fpgad.c   | 100 
 include/configs/dlvision-10g.h   |   9 +-
 include/configs/dlvision.h   |   3 +-
 include/configs/io.h |   8 +-
 include/configs/io64.h   |   6 +
 include/configs/iocon.h  |  60 -
 include/configs/neo.h|   8 +-
 include/gdsys_fpga.h |  58 -
 20 files changed, 999 insertions(+), 171 deletions(-)
 create mode 100644 board/gdsys/common/mclink.c
 create mode 100644 board/gdsys/common/mclink.h
 create mode 100644 common/cmd_fpgad.c

-- 
1.8.3

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Re: [U-Boot] [PATCH] gpio: spear_gpio: Fix gpio_set_value() implementation

[Michael Trimarchi]

Hi
Il giorno 20/giu/2013 09:14, "Axel Lin"  ha scritto:
>
> In current gpio_set_value() implementation, it always sets the gpio
control bit
> no matter the value argument is 0 or 1. Thus the GPIOs never set to low.
> This patch fixes this bug.
>
> Signed-off-by: Axel Lin 
> ---
>  drivers/gpio/spear_gpio.c | 5 -
>  1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpio/spear_gpio.c b/drivers/gpio/spear_gpio.c
> index d3c728e..8878608 100644
> --- a/drivers/gpio/spear_gpio.c
> +++ b/drivers/gpio/spear_gpio.c
> @@ -52,7 +52,10 @@ int gpio_set_value(unsigned gpio, int value)
>  {
> struct gpio_regs *regs = (struct gpio_regs *)CONFIG_GPIO_BASE;
>
> -   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> +   if (value)
> +   writel(1 << gpio, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
> +   else
> +   writel(0, ®s->gpiodata[DATA_REG_ADDR(gpio)]);
>
> return 0;
>  }

Does it work the clear? Seems that it sets to 0 all the bank. I'm using the
mobile

Michael

> --
> 1.8.1.2
>
>
>
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Re: [U-Boot] [PATCH v6 4/5] Build arch/$ARCH/lib/bootm.o depending on CONFIG_CMD_BOOTM

[Dirk Eibach]

2013/6/20 Dirk Eibach :
> Hi Andy,
>
>>> From: Dirk Eibach 
>>>
>>> MAKEALL is fine for ppc4xx and mpc85xx.
>>> Run checks were done on our controlcenterd hardware.
>>>
>>> Signed-off-by: Dirk Eibach 
>>>
>>>
>>> Signed-off-by: Dirk Eibach 
>>
>>
>> You don't need two sign-offs.
>
> patman puts and additional SOB to some of my patches. I'm not sure how
> to fix this.

Never mind. I just discovered that SOB line has to be located after
all the other patman stuff in the commit message, then it works as
expected. Will be fixed in v7.

Cheers
Dirk
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Re: [U-Boot] [PATCH 2/2] ARM: Congatec: Ethernet: Add support for cgtqmx6qeval

[Otavio Salvador]

On Thu, Jun 20, 2013 at 8:26 AM, SARTRE Leo  wrote:
> cgtqmx6eval.c: add Micrel KSZ9031  Ethernet transceiver
> README   : U-boot works both on SPI-NOR and SDcard
>
> Signed-off-by: Leo Sartre 
> ---
>  board/congatec/cgtqmx6eval/README|3 +-
>  board/congatec/cgtqmx6eval/cgtqmx6eval.c |  112 
> ++
>  include/configs/cgtqmx6eval.h|   13 
>  3 files changed, 126 insertions(+), 2 deletions(-)
>
> diff --git a/board/congatec/cgtqmx6eval/README 
> b/board/congatec/cgtqmx6eval/README
> index bbf0f75..5e76d2a 100644
> --- a/board/congatec/cgtqmx6eval/README
> +++ b/board/congatec/cgtqmx6eval/README
> @@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
>  1. Boot source, boot from SD card
>  -
>
> -This version of u-boot works only on the SD card. By default, the
> -Congatec board can boot only from the SPI-NOR.
> +By default, the Congatec board can boot only from the SPI-NOR.
>  But, with the u-boot version provided with the board you can write boot
>  registers to force the board to reboot and boot from the SD slot. If
>  "bmode" command is not available from your pre-installed u-boot, these

Please change this in another patch. This one you can add Stefano in
Cc so he can apply it in his tree.

> diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c 
> b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> index f70f674..00088fb 100644
> --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
> @@ -30,6 +30,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -40,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
> PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
>
> +#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
> +   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
> +
>  int dram_init(void)
>  {
> gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
> @@ -76,6 +81,113 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
> MX6_PAD_NANDF_D6__GPIO_2_6| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
>  };
>
> +iomux_v3_cfg_t const enet_pads1[] = {
> +   MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_ENET_MDC__ENET_MDC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TXC__ENET_RGMII_TXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TD0__ENET_RGMII_TD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TD1__ENET_RGMII_TD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TD2__ENET_RGMII_TD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TD3__ENET_RGMII_TD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_GPIO_0__CCM_CLKO| MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_GPIO_3__CCM_CLKO2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_ENET_REF_CLK__ENET_TX_CLK   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   /* pin 35 - 1 (PHY_AD2) on reset */
> +   MX6_PAD_RGMII_RXC__GPIO_6_30| MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 32 - 1 - (MODE0) all */
> +   MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 31 - 1 - (MODE1) all */
> +   MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 28 - 1 - (MODE2) all */
> +   MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 27 - 1 - (MODE3) all */
> +   MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
> +   MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
> +   /* pin 42 PHY nRST */
> +   MX6_PAD_EIM_D23__GPIO_3_23  | MUX_PAD_CTRL(NO_PAD_CTRL),
> +};
> +
> +iomux_v3_cfg_t const enet_pads2[] = {
> +   MX6_PAD_RGMII_RXC__ENET_RGMII_RXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_RD0__ENET_RGMII_RD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_RD1__ENET_RGMII_RD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_RD2__ENET_RGMII_RD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_RD3__ENET_RGMII_RD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +   MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
> +};
> +
> +static void setup_iomux_enet(void)
> +{
> +   gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
> +   gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
> +   gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
> +   gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
> +   gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
> +   gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
> +   imx_iomux_v3_setup_multipl

Re: [U-Boot] [PATCH 1/2] PHY: micrel: helper function for KSZ9031

[Otavio Salvador]

On Thu, Jun 20, 2013 at 8:26 AM, SARTRE Leo  wrote:
> micrel.c: Add function ksz9031_phy_extended_write, helper to MDD
>   register write
> micrel.h: Prototype and define MDD registers
>
> Signed-off-by: Leo Sartre 
> ---
>  drivers/net/phy/micrel.c |   29 +++--
>  include/micrel.h |7 +++
>  2 files changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
> index 2a8b6cb..5b5c11b 100644
> --- a/drivers/net/phy/micrel.c
> +++ b/drivers/net/phy/micrel.c
> @@ -85,7 +85,7 @@ static int ksz90xx_startup(struct phy_device *phydev)
>  }
>  #ifdef CONFIG_PHY_MICREL_KSZ9021
>
> -/*
> +/**
>   * KSZ9021
>   */

Please drop this change; not need.

> @@ -148,9 +148,34 @@ static struct phy_driver ksz9021_driver = {
>  };
>  #endif
>
> -/*
> +/**
>   * KSZ9031
>   */

Please drop this change; not need.

--
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http://www.ossystems.com.brhttp://projetos.ossystems.com.br
Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750
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[U-Boot] [PATCH 2/2] ARM: Congatec: Ethernet: Add support for cgtqmx6qeval

[SARTRE Leo]

cgtqmx6eval.c: add Micrel KSZ9031  Ethernet transceiver
README   : U-boot works both on SPI-NOR and SDcard

Signed-off-by: Leo Sartre 
---
 board/congatec/cgtqmx6eval/README|3 +-
 board/congatec/cgtqmx6eval/cgtqmx6eval.c |  112 ++
 include/configs/cgtqmx6eval.h|   13 
 3 files changed, 126 insertions(+), 2 deletions(-)

diff --git a/board/congatec/cgtqmx6eval/README 
b/board/congatec/cgtqmx6eval/README
index bbf0f75..5e76d2a 100644
--- a/board/congatec/cgtqmx6eval/README
+++ b/board/congatec/cgtqmx6eval/README
@@ -7,8 +7,7 @@ Conga-QEVAl Evaluation Carrier board with qmx6 quad module.
 1. Boot source, boot from SD card
 -
 
-This version of u-boot works only on the SD card. By default, the
-Congatec board can boot only from the SPI-NOR.
+By default, the Congatec board can boot only from the SPI-NOR.
 But, with the u-boot version provided with the board you can write boot
 registers to force the board to reboot and boot from the SD slot. If
 "bmode" command is not available from your pre-installed u-boot, these
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c 
b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
index f70f674..00088fb 100644
--- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c
+++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c
@@ -30,6 +30,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 #include 
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -40,6 +42,9 @@ DECLARE_GLOBAL_DATA_PTR;
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |\
PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |  \
+   PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
 int dram_init(void)
 {
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -76,6 +81,113 @@ iomux_v3_cfg_t const usdhc4_pads[] = {
MX6_PAD_NANDF_D6__GPIO_2_6| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 };
 
+iomux_v3_cfg_t const enet_pads1[] = {
+   MX6_PAD_ENET_MDIO__ENET_MDIO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_ENET_MDC__ENET_MDC  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TXC__ENET_RGMII_TXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD0__ENET_RGMII_TD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD1__ENET_RGMII_TD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD2__ENET_RGMII_TD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TD3__ENET_RGMII_TD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_GPIO_0__CCM_CLKO| MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_GPIO_3__CCM_CLKO2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_ENET_REF_CLK__ENET_TX_CLK   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   /* pin 35 - 1 (PHY_AD2) on reset */
+   MX6_PAD_RGMII_RXC__GPIO_6_30| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 32 - 1 - (MODE0) all */
+   MX6_PAD_RGMII_RD0__GPIO_6_25| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 31 - 1 - (MODE1) all */
+   MX6_PAD_RGMII_RD1__GPIO_6_27| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 28 - 1 - (MODE2) all */
+   MX6_PAD_RGMII_RD2__GPIO_6_28| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 27 - 1 - (MODE3) all */
+   MX6_PAD_RGMII_RD3__GPIO_6_29| MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+   MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+   /* pin 42 PHY nRST */
+   MX6_PAD_EIM_D23__GPIO_3_23  | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t const enet_pads2[] = {
+   MX6_PAD_RGMII_RXC__ENET_RGMII_RXC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD0__ENET_RGMII_RD0   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD1__ENET_RGMII_RD1   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD2__ENET_RGMII_RD2   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RD3__ENET_RGMII_RD3   | MUX_PAD_CTRL(ENET_PAD_CTRL),
+   MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL  | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+   gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
+   gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
+   gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
+   imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+   gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
+
+   /* Need delay 10ms according to KSZ9031 spec */
+   udelay(1000 * 10);
+   gpio_set_value(IMX_GPIO_NR(3, 23), 1);
+   imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+}
+
+int board_phy_config(struct phy_dev

[U-Boot] [PATCH 0/2] Add ethernet support for Congatec qmx6qeval

[SARTRE Leo]

These patchs add ethernet support for congatec cgtqmx6qeval that uses
Micrel's KSZ9031.
The first patch adds KSZ9031's helper function to access extended
registers, it apply on top of David Andrey's patch
(http://patchwork.ozlabs.org/patch/218793/).

Leo Sartre (2):
  PHY: micrel: helper function for KSZ9031
  ARM: Congatec: Ethernet: Add support for cgtqmx6qeval

 board/congatec/cgtqmx6eval/README|3 +-
 board/congatec/cgtqmx6eval/cgtqmx6eval.c |  112 ++
 drivers/net/phy/micrel.c |   29 +++-
 include/configs/cgtqmx6eval.h|   13 
 include/micrel.h |7 ++
 5 files changed, 160 insertions(+), 4 deletions(-)

-- 
1.7.10.4
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[U-Boot] [PATCH 1/2] PHY: micrel: helper function for KSZ9031

[SARTRE Leo]

micrel.c: Add function ksz9031_phy_extended_write, helper to MDD
  register write
micrel.h: Prototype and define MDD registers

Signed-off-by: Leo Sartre 
---
 drivers/net/phy/micrel.c |   29 +++--
 include/micrel.h |7 +++
 2 files changed, 34 insertions(+), 2 deletions(-)

diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 2a8b6cb..5b5c11b 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -85,7 +85,7 @@ static int ksz90xx_startup(struct phy_device *phydev)
 }
 #ifdef CONFIG_PHY_MICREL_KSZ9021
 
-/*
+/**
  * KSZ9021
  */
 
@@ -148,9 +148,34 @@ static struct phy_driver ksz9021_driver = {
 };
 #endif
 
-/*
+/**
  * KSZ9031
  */
+
+/* PHY Registers */
+#define MII_KSZ9031_MMD_ACCES_CTRL 0x0d
+#define MII_KSZ9031_MMD_REG_DATA   0x0e
+
+/* Accessors to extended registers*/
+int ksz9031_phy_extended_write(struct phy_device *phydev,
+  int devaddr,
+  int regnum,
+  u16 val)
+{
+   /*select register addr for mmd*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+MII_KSZ9031_MMD_ACCES_CTRL, devaddr);
+   /*select register for mmd*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+MII_KSZ9031_MMD_REG_DATA, regnum);
+   /*setup mode*/
+   phy_write(phydev, MDIO_DEVAD_NONE,
+MII_KSZ9031_MMD_ACCES_CTRL, (devaddr | 0xC000));
+   /*write the value*/
+   return phy_write(phydev, MDIO_DEVAD_NONE,
+MII_KSZ9031_MMD_REG_DATA, val);
+}
+
 static struct phy_driver ksz9031_driver = {
.name = "Micrel ksz9031",
.uid  = 0x221620,
diff --git a/include/micrel.h b/include/micrel.h
index 25e8a46..d63ff45 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -9,8 +9,15 @@
 #define MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW 0x106
 #define MII_KSZ9021_EXT_ANALOG_TEST0x107
 
+#define MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW0x4
+#define MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW 0x5
+#define MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW 0x6
+#define MII_KSZ9031_EXT_RGMII_CLOCK_SKEW   0x8
+
 struct phy_device;
 int ksz9021_phy_extended_write(struct phy_device *phydev, int regnum, u16 val);
 int ksz9021_phy_extended_read(struct phy_device *phydev, int regnum);
 
+int ksz9031_phy_extended_write(struct phy_device *phydev, int devaddr,
+  int regnum, u16 val);
 #endif
-- 
1.7.10.4
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Re: [U-Boot] [PATCH v4 1/3] ARM: Tegra: FDT: Add USB EHCI function for T30/T114

[Thierry Reding]

On Thu, Jun 20, 2013 at 04:13:38PM +0800, Jim Lin wrote:
> Add DT node for USB EHCI function.
> Add support for T30-Cardhu, T30-Beaver, T114-Dalmore boards.
> 
> Signed-off-by: Jim Lin 
> ---
> Changes in v2:
>  - Remove PLL parameters from dt file
> Changes in v3:
>  - Change VBus GPIO from H.05 to DD.04 for Beaver board.
> Changes in v4:
>  - Change Beaver VBus GPIO to H.05 and value to 0 for polarity to be High.
>I don't have Beaver board. So this needs somebody to help test.
>Thanks.

Why did you change it back to H.05 again? I already tested successfully
that DD.04 is the right one.

Thierry


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Re: [U-Boot] Not abled to upload binary using "dfu-util"

[Sumit Gemini]

HI Heiko,

 Thanks for reply and for links, i raised a request for membership.
 Here I want to share regarding dfu,


when i apply

dfu-util -v -a SPL -U dfu-SPL from my host machine,


I got such log on Host machine :-

Device returned transfer size 4096
bytes_per_hash=4096
Copying data from DFU device to PC
Starting upload: [] finished!
Received a total of 1 bytes

and finally dfu-SPL file created with 4kb size.


but on target machine, i got

Running: sf read 0x 0x2 0x0
Failed to map physical memory.

May i know why i got such error or user have to specify address over which
we read our binary

Thanks
~Sumit Gemini





On Thu, Jun 20, 2013 at 3:20 PM, Heiko Schocher  wrote:

> Hello Sumit,
>
> Am 20.06.2013 10:44, schrieb Sumit Gemini:
> > Hi All,
> >
> >  I am trying to upload images from dfu devices to PC, but
> >
> > "Copying data from DFU device to PC
> > Starting upload: [] finished!
> > Received a total of 1 bytes"
> >
> > error i got,
> >
> >
> > do not know why i getting this kind of error because downloading of files
> > is made but uploading not.
> >
> > Any help will appreciate.
>
> "man dfu-util" says:
>
>   -U, --upload FILE
>   Read firmware from device into FILE.
>
>   Note: Upload support is currently broken.
>
> Maybe you find more help here:
>
> https://lists.gnumonks.org/mailman/listinfo/dfu-util
>
> bye,
> Heiko
> --
> DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>
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[U-Boot] Not able to boot using zImage

[Enric Balletbo Serra]

Hi all,

I've some problems trying to boot a zImage with following command after
load the zImage and the fdt file on memory:

U-Boot > fdt addr ${dtbaddr}; fdt resize; bootz ${loadaddr} - ${dtbaddr}


But the sistem stops at Starting kernel ...


File transfer via NFS from server 192.168.2.245; our IP address is
192.168.2.242
Filename '/srv/nfs/sandbox/0/am335x/boot/zImage'.
Load address: 0x8000
Loading: #
done
Bytes transferred = 4011728 (3d36d0 hex)
link up on port 0, speed 100, full duplex
Using cpsw device
File transfer via NFS from server 192.168.2.245; our IP address is
192.168.2.242
Filename '/srv/nfs/sandbox/0/am335x/boot/am335x-base0033.dtb'.
Load address: 0x8160
Loading: ###T T
Abort
## Flattened Device Tree blob at 8160
   Booting using the fdt blob at 0x8160
   reserving fdt memory region: addr=8160 size=3000
   Loading Device Tree to 8fe3b000, end 8fe40fff ... OK

Starting kernel ...


The same commands using the uImage instead of zImage works without
problems. Is expected to work ? Any clue before diving into the problem ?

Thanks in advance,
Enric
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Re: [U-Boot] [PATCH v3 17/21] arm: Implement the 'fake' go command

[Albert ARIBAUD]

Hi Simon,

On Wed, 19 Jun 2013 21:15:10 -0700, Simon Glass 
wrote:

> Implement this feature on ARM for tracing.
> 
> It would be nice to have generic bootm support so that it is easily
> implemented on any arch.
> 
> Signed-off-by: Simon Glass 
> ---
> Changes in v3:
> - Revert to using 'images' instead of 'image' in boot_jump_linux()
> 
> Changes in v2: None

Small nitpick: I prefer whole series to be reposted even when there is
only a single patch changed. My rationale for this is: when a series
has been posted as V2 and a single patch appears as V3, as a reviewer I
do not know whether that patch was really the only one intended as V3,
or whether other patches were too but did not make it through for some
reason.

Also, as this V3 patch did not have any "In-Reply-To" header, it is not
threaded to the V2 series by my claws-mail. That makes it less easy to
try and get an overview of the current series.

[insert witty remark about how patman quite adequately addresses the two
points above :) ]

Here I will assume 17/21 is the only patch in the series and the rest
should come from v2 unchanged. As this is the only pure ARM related
patch in the series (1), I guess my contribution shall be...

Acked-by: Albert ARIBAUD 

(1) patch 18/21 is Samsung and patch 19/21 touches on exynos5250-based
boards; my ack is less adequate than that of, respectively, Minkyu as
the Samsung custodian and the exynos5250-based boards' maintainers.

Note: who/what exactly is "u-boot-rev...@google.com"?

Amicalement,
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Re: [U-Boot] Not abled to upload binary using "dfu-util"

[Heiko Schocher]

Hello Sumit,

Am 20.06.2013 10:44, schrieb Sumit Gemini:
> Hi All,
> 
>  I am trying to upload images from dfu devices to PC, but
> 
> "Copying data from DFU device to PC
> Starting upload: [] finished!
> Received a total of 1 bytes"
> 
> error i got,
> 
> 
> do not know why i getting this kind of error because downloading of files
> is made but uploading not.
> 
> Any help will appreciate.

"man dfu-util" says:

  -U, --upload FILE
  Read firmware from device into FILE.

  Note: Upload support is currently broken.

Maybe you find more help here:

https://lists.gnumonks.org/mailman/listinfo/dfu-util

bye,
Heiko
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Re: [U-Boot] [PATCH v3 0/9] Bring in new I2C framework

[Heiko Schocher]

Hello Piotr,

Am 20.06.2013 10:34, schrieb Piotr Wilczek:
> Dear Minkyu and Heiko,
> 
>> -Original Message-
>> From: Heiko Schocher [mailto:h...@denx.de]
>> Sent: Thursday, June 20, 2013 9:14 AM
>> To: Piotr Wilczek
>> Cc: 'Minkyu Kang'; 'Simon Glass'; 'U-Boot Mailing List'; 'Dirk Eibach';
>> 'Stefan Roese'; 'Holger Brunck'; 'Mike Frysinger'; 'Stephen Warren'
>> Subject: Re: [PATCH v3 0/9] Bring in new I2C framework
>>
>> Hello Piotr,
>>
>> Am 20.06.2013 08:41, schrieb Piotr Wilczek:
>>> Dear Heiko,
>>>
 -Original Message-
 From: Minkyu Kang [mailto:mk7.k...@samsung.com]
 Sent: Thursday, June 20, 2013 7:51 AM
 To: Heiko Schocher
 Cc: Simon Glass; Piotr Wilczek; U-Boot Mailing List; Dirk Eibach;
 Stefan Roese; Holger Brunck; Mike Frysinger; Stephen Warren
 Subject: Re: [PATCH v3 0/9] Bring in new I2C framework

 Dear Heiko,

 On 20/06/13 12:38, Heiko Schocher wrote:
> Hello Simon,
>
> Am 20.06.2013 00:07, schrieb Simon Glass:
>> Hi Heiko,
>>
>> On Sun, May 19, 2013 at 11:13 PM, Piotr Wilczek
 mailto:p.wilc...@samsung.com>> wrote:
>>
>> Hi Simon,
>>
>> > -Original Message-
>> > From: s...@google.com 
 [mailto:s...@google.com ] On Behalf Of Simon
 Glass
>> > Sent: Saturday, May 18, 2013 7:41 PM
>> > To: Piotr Wilczek
>> > Cc: Heiko Schocher; U-Boot Mailing List; Dirk Eibach; Stefan
 Roese;
>> > Holger Brunck; Mike Frysinger; Stephen Warren; Minkyu Kang
>> > Subject: Re: [PATCH v3 0/9] Bring in new I2C framework
>> >
>> > Hi Piotr,
>> >
>> > On Fri, May 17, 2013 at 6:17 AM, Piotr Wilczek
 mailto:p.wilc...@samsung.com>>
>> > wrote:
>> > > Dear Heiko,
>> > >
>> > >> -Original Message-
>> > >> From: Heiko Schocher [mailto:h...@denx.de
 ]
>> > >> Sent: Saturday, May 04, 2013 2:02 PM
>> > >> To: u-boot@lists.denx.de 
>> > >> Cc: Heiko Schocher; Dirk Eibach; Stefan Roese; Simon
>> Glass;
 Piotr
>> > >> Wilczek; Holger Brunck; Mike Frysinger; Stephen Warren
>> > >> Subject: [PATCH v3 0/9] Bring in new I2C framework
>> > >>
>> > >> It seems the timing is coming, to bring this finally in
 mainline and
>> > >> move boards over to the new i2c framework.
>> > >>
>> > >> Changes for v3 series:
>> > >>
>> > >> - Compiler collects the used i2c adapters in
 _u_boot_list_i2c,
>> > >>   so no need for defining the used i2c adpaters in the
 board config
>> > >> file.
>> > >>   -> drop CONFIG_SYS_NUM_I2C_ADAPTERS and
 CONFIG_SYS_I2C_ADAPTERS
>> > >> - Some adaptions for the keymile boards, so we can drop
>> > CONFIG_I2C_MUX
>> > >>   completely
>> > >> - add ppc4xx_i2c driver, ported from Dirk Eibach
>> > >>
>> > >> Serie compiles clean on arm and powerpc
>> > >>
>> > >> Ported i2c drivers:
>> > >> soft_i2c  : from me, tested on some arm and powerpc
>> boards
>> > >> fsl_i2c   : from me, only compile tested
>> > >> tegra_i2c : ported from Simon Glass
>> > >> ppc4xx_i2c: adapted from Dirk Eibach
>> 
>> > >> tested on (which board?) with 4 soft_i2c
 drivers
>> > >> and one ppc4x_i2c driver.
>> > >>
>> > >> Cc: Dirk Eibach 
>> > >> Cc: Stefan Roese mailto:s...@denx.de>>
>> > >> Cc: Simon Glass >>> >
>> > >> Cc: Piotr Wilczek >>> >
>> > >> Cc: Holger Brunck >>> >
>> > >> Cc: Mike Frysinger >>> >
>> > >> Cc: Stephen Warren >>> >
>> > >>
>> > >
>> > > I ported s3c24x0_i2c driver and tested this framework on
 Samsung tree
>> > on Trats2 board.
>> >
>> > Please can you send a patch for this port?
>>
>> I posted that patch and some others with series introducing
 Trsts2, where I
>> want to use this framework.
>> I'm sorry I didn't mention it in my first mail.
>> http://patchwork.ozlabs.org/patch/244645/
>> http://patchwork.ozlabs.org/patch/244644/
>> .
>> http://patchwork.ozlabs.org/patch/244638/
>> http://patchwork.ozlabs.org/patch/244637/
>> http://patchwork.ozlabs.org/patch/244640/
>> http://patchwork.ozlabs.org/patch/244636/
>
> Hups, missed this patches ...
>
>> What is the status of this series now please?
>
>>>
>>> If you take this series, please replace the following patch:
>>> http://patchwork.ozlabs.org/patch/244642/
>>>
>>> wit

Re: [U-Boot] [PATCH v3 0/9] Bring in new I2C framework

[Heiko Schocher]

Hello Dirk,

Am 20.06.2013 10:20, schrieb Dirk Eibach:
> Hello Heiko,
> 
> 2013/6/20 Heiko Schocher :
>> Hello Dirk,
>>
>> Am 20.06.2013 08:52, schrieb Dirk Eibach:
>>> Hello Heiko,
>>>
> What is the status of this series now please?

 I heared nothing negatives for the new i2c multibus framework,
 so I plan to merge it into mainline, if the next merge widow is
 open.
>>>
>>> actually I thought it would go into the current release :( What's the
>>> reason for the delay?
>>
>> No real reason (just not found time for it), and we are near to the
>> release date, and this is a big change, which impacts a lot of boards,
>> different architetures...
>>
>> Ok, since my last version from 18.05.2013 I got no more comments,
>> so ... just currently rebased against current head and it compiles
>> clean for arm ... but I have to try it on some plattforms, also
>> look at the powerpc side ... and I am afraid that I have no chance
>> to do this in the next two weeks ... also I am nearly one week
>> on vacation ... so there is not much time till the next release,
>> for reviewing bugfixes ...
>>
>>> I rebased my series on this, so it would not get in either.
>>
>> Sorry for the delay ... I vote for pushing this to mainline when
>> the next merge window opens, so more time for testing/fixing errors
>> remains ...
> 
> OK, so with a strong emphasis on "when the next merge window *opens*"

Yes!

>> You found my current multibus branch here:
>> http://git.denx.de/?p=u-boot/u-boot-i2c.git;a=shortlog;h=refs/heads/20130620_multibus_v2
> 
> As I am just doing a v4 of my series I will rebase it onto this.

Ok, thanks!

bye,
Heiko
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[U-Boot] [PATCH 08/10 v5] powerpc/p1022ds: boot from spi flash with SPL

[ying.zhang]

From: Ying Zhang 

Support to boot from spi flash.

This patch is on top of the patch:
powerpc/p1022ds: boot from SD Card with SPL

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. No change.
3. No change.
4. No change.

 board/freescale/p1022ds/spl.c  |   12 +-
 drivers/mtd/spi/Makefile   |1 +
 drivers/mtd/spi/fsl_espi_spl.c |   78 
 drivers/mtd/spi/spi_flash.c|2 +
 include/configs/P1022DS.h  |   36 +++
 5 files changed, 120 insertions(+), 9 deletions(-)
 create mode 100644 drivers/mtd/spi/fsl_espi_spl.c

diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index 40f000f..1dd9050 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -21,13 +21,12 @@
 
 #include 
 #include 
-#include 
-#include 
 #include 
 #include 
 #include 
 #include "../common/ngpixis.h"
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -54,6 +53,11 @@ void board_init_f(ulong bootflag)
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
 
+#ifdef CONFIG_SPL_SPI_BOOT
+   /* Enable the SPI */
+   clrsetbits_8(&pixis->brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI);
+#endif
+
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
 
@@ -67,6 +71,8 @@ void board_init_f(ulong bootflag)
bus_clk / 16 / CONFIG_BAUDRATE);
 #ifdef CONFIG_SPL_MMC_BOOT
puts("\nSD boot...\n");
+#elif defined(CONFIG_SPL_SPI_BOOT)
+   puts("\nSPI Flash boot...\n");
 #endif
 
/* copy code to RAM and jump to it - this should not return */
@@ -108,5 +114,7 @@ void board_init_r(gd_t *gd, ulong dest_addr)
 
 #ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
+#elif defined(CONFIG_SPL_SPI_BOOT)
+   spi_boot();
 #endif
 }
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 90f8392..5f130d5 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -27,6 +27,7 @@ LIB   := $(obj)libspi_flash.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_SPI_LOAD)   += spi_spl_load.o
+COBJS-$(CONFIG_SPL_SPI_BOOT)   += fsl_espi_spl.o
 endif
 
 COBJS-$(CONFIG_SPI_FLASH)  += spi_flash.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
new file mode 100644
index 000..8375a75
--- /dev/null
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include 
+#include 
+#include 
+
+#define ESPI_BOOT_IMAGE_SIZE   0x48
+#define ESPI_BOOT_IMAGE_ADDR   0x50
+#define CONFIG_CFG_DATA_SECTOR 0
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+   void (*uboot)(void) __noreturn;
+   u32 offset, code_len, i;
+   unsigned char *buf = NULL;
+   struct spi_flash *flash;
+
+   flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+   CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+   if (flash == NULL) {
+   puts("\nspi_flash_probe failed");
+   hang();
+   }
+
+   /*
+   * Load U-Boot image from SPI flash into RAM
+   */
+   buf = malloc(flash->page_size);
+   if (buf == NULL) {
+   puts("\nmalloc failed");
+   hang();
+   }
+   memset(buf, 0, flash->page_size);
+
+   spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, \
+   flash->page_size, (void *)buf);
+   offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
+   /* Skip spl code */
+   offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+   /* Get the code size from offset 0x48 */
+   code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
+   /* Skip spl code */
+   code_len = code_len - CONFIG_SPL_MAX_SIZE;
+   /* copy code to DDR */
+   spi_flash_read(flash, offset, code_len, \
+   (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+   /*
+   * Jump to U-Boot image
+   */
+   flush_cache

[U-Boot] [PATCH 10/10 v5] powerpc: p1022ds: support TPL on the P1022DS

[ying.zhang]

From: Ying Zhang 

Support TPL on the P1022DS.
The TPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are three stage uboot images:
* spl_boot, 4KB size, pad to 128K byte.
* tpl_boot, 88K size, pad to 128K size. The env variables are
copied to L2 SRAM, so that ddr SPD code can get the interleaving
mode setting in env. It loads final uboot image from offset 256KB.
* final uboot image, size is variable depends on the functions
enabled.

This patch is on top of the patch:
nand: tpl : introduce the TPL based on the SPL

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL".
2. No change.
3. No change.
4. No change.

 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |4 +
 board/freescale/p1022ds/Makefile|3 +
 board/freescale/p1022ds/spl_minimal.c   |   57 ++---
 board/freescale/p1022ds/tlb.c   |4 +-
 board/freescale/p1022ds/tpl.c   |  102 +++
 drivers/mtd/nand/fsl_elbc_spl.c |   18 +-
 include/configs/P1022DS.h   |   79 ++--
 7 files changed, 196 insertions(+), 71 deletions(-)
 create mode 100644 board/freescale/p1022ds/tpl.c

diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 4e786a4..1af1da8 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -32,7 +32,11 @@ PHDRS
 #endif
 SECTIONS
 {
+#ifdef CONFIG_SPL_BUILD
. = CONFIG_SPL_TEXT_BASE;
+#else
+   . = CONFIG_TPL_TEXT_BASE;
+#endif
.text : {
*(.text*)
}
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 9746063..58f224e 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -27,6 +27,9 @@ else
 ifdef CONFIG_SPL_BUILD
 COBJS-y += spl.o
 endif
+ifdef CONFIG_TPL_BUILD
+COBJS-y += tpl.o
+endif
 COBJS-y+= $(BOARD).o
 COBJS-y+= ddr.o
 COBJS-y+= law.o
diff --git a/board/freescale/p1022ds/spl_minimal.c 
b/board/freescale/p1022ds/spl_minimal.c
index 8d12fa6..8ab5ec2 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -27,51 +27,6 @@
 #include 
 
 
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
-   volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
-   __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
-   __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
-   __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
-   __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
-#endif
-   __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
-   __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
-   __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
-   __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
-
-   __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
-   __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
-   __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
-
-   __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
-   __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
-   __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
-
-   __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
-   __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
-   __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
-   __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl);
-
-   /* Set, but do not enable the memory */
-   __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN,
-   &ddr->sdram_cfg);
-
-   in_be32(&ddr->sdram_cfg);
-   udelay(500);
-
-   /* Let the controller go */
-   out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-   in_be32(&ddr->sdram_cfg);
-
-   set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
 const static u32 sysclk_tbl[] = {
6000, 7499900, 83332500, 800,
9000, 1000, 12499800, 1200
@@ -83,6 +38,10 @@ void board_init_f(ulong bootflag)
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
+   set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+   set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
/* for FPGA */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -98,19 +57,17 @@ void board_init_f(ulong bootflag)
 

[U-Boot] [PATCH 09/10 v5] nand: tpl : introduce the TPL based on the SPL

[ying.zhang]

From: Ying Zhang 

Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can
not be more than 4K. So, the SPL cannot initialize the DDR with the SPD
code. This patch introduces TPL to enable a loader stub that runs in the
L2 SRAM, after being loaded by the code from the SPL. It initializes the
DDR with the SPD or other operations.

The TPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are three stage uboot images:
* spl_boot, * tpl_boot, * final uboot image,

This patch is on top of the patch:
powerpc/p1022ds: boot from spi flash with SPL

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "powerpc/p1022ds: nand: introduce the TPL based on the SPL".
2. No change.
3. No change.
4. No change.

 Makefile   |   21 +++-
 README |   52 ++-
 arch/powerpc/config.mk |2 +
 .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 +-
 arch/powerpc/lib/Makefile  |2 +
 common/Makefile|9 +
 common/cmd_nvedit.c|8 +-
 config.mk  |   32 
 doc/README.TPL |   69 +
 drivers/mtd/nand/Makefile  |8 +
 drivers/mtd/nand/fsl_elbc_spl.c|4 +
 drivers/serial/serial.c|2 +-
 include/bootstage.h|3 +-
 tpl/Makefile   |  161 
 14 files changed, 366 insertions(+), 11 deletions(-)
 create mode 100644 doc/README.TPL
 create mode 100644 tpl/Makefile

diff --git a/Makefile b/Makefile
index 693b3f2..7954e96 100644
--- a/Makefile
+++ b/Makefile
@@ -118,10 +118,11 @@ endif # ifneq ($(BUILD_DIR),)
 
 OBJTREE:= $(if $(BUILD_DIR),$(BUILD_DIR),$(CURDIR))
 SPLTREE:= $(OBJTREE)/spl
+TPLTREE:= $(OBJTREE)/tpl
 SRCTREE:= $(CURDIR)
 TOPDIR := $(SRCTREE)
 LNDIR  := $(OBJTREE)
-export TOPDIR SRCTREE OBJTREE SPLTREE
+export TOPDIR SRCTREE OBJTREE SPLTREE TPLTREE
 
 MKCONFIG   := $(SRCTREE)/mkconfig
 export MKCONFIG
@@ -412,6 +413,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
 ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
 ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
 ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_TPL) += $(obj)tpl/u-boot-tpl.bin
 ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
 ifneq ($(CONFIG_SPL_TARGET),)
 ALL-$(CONFIG_SPL) += $(obj)$(subst ",,$(CONFIG_SPL_TARGET))
@@ -498,6 +500,18 @@ $(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin 
$(obj)u-boot.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin > $@
rm $(obj)spl/u-boot-spl-pad.bin
 
+$(obj)u-boot-with-tpl.bin: $(obj)spl/u-boot-spl.bin $(obj)tpl/u-boot-tpl.bin \
+   $(obj)u-boot.bin
+   $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+   -I binary -O binary \
+   $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl-pad.bin
+   $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SYS_PAD_TO) \
+   -I binary -O binary \
+   $(obj)tpl/u-boot-tpl.bin $(obj)tpl/u-boot-tpl-pad.bin
+   cat $(obj)spl/u-boot-spl-pad.bin $(obj)tpl/u-boot-tpl-pad.bin \
+   $(obj)u-boot.bin > $@
+   rm $(obj)spl/u-boot-spl-pad.bin $(obj)tpl/u-boot-tpl-pad.bin
+
 $(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
$(OBJTREE)/u-boot-with-spl.imx
@@ -622,6 +636,9 @@ $(obj)u-boot-nand.bin:  nand_spl $(obj)u-boot.bin
 $(obj)spl/u-boot-spl.bin:  $(SUBDIR_TOOLS) depend
$(MAKE) -C spl all
 
+$(obj)tpl/u-boot-tpl.bin:  $(SUBDIR_TOOLS) depend
+   $(MAKE) -C tpl all
+
 updater:
$(MAKE) -C tools/updater all
 
@@ -870,6 +887,8 @@ clobber:tidy
@rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
@rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
@rm -f $(obj)spl/u-boot-spl.lds
+   @rm -f $(obj)tpl/{u-boot-tpl,u-boot-tpl.bin,u-boot-tpl.map}
+   @rm -f $(obj)tpl/u-boot-tpl.lds
@rm -f $(obj)MLO MLO.byteswap
@rm -f $(obj)SPL
@rm -f $(obj)tools/xway-swap-bytes
diff --git a/README b/README
index 5985903..2d47816 100644
--- a/README
+++ b/README
@@ -2983,9 +2983,10 @@ FIT uImage format:
Set for the SPL on PPC mpc8xxx targets, support for
arch/powerpc/cpu/mpc8xxx/ddr/libddr.o 

[U-Boot] [PATCH 07/10 v5] powerpc/p1022ds: boot from SD Card with SPL

[ying.zhang]

From: Ying Zhang 

This patch introduces SPL to enable a loader stub that runs in the L2 SRAM,
after being loaded by the code from the internal on-chip ROM. It loads the
final uboot image into DDR, then jump to it to begin execution.

The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so
that ddr spd code can get the interleaving mode setting in env. It
loads final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions
enabled.

This patch is on top of the following patch:
1. common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment
in SPL.
2. Makefile: move the common makefile line to public area
3. powerpc/mpc85xx: support application without resetvec segment in the
linker script.
4. powerpc/mpc85xx: modify the function clear_bss and the end address of
the BSS
5. powerpc: spl: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and
enabled some functionality for common SPL
6. spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. No change.
3. No change.
4. No change.

 README |7 +
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds|5 +
 .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 +
 board/freescale/common/Makefile|2 -
 board/freescale/p1022ds/Makefile   |3 +
 board/freescale/p1022ds/spl.c  |  112 +
 board/freescale/p1022ds/tlb.c  |9 ++-
 doc/README.mpc85xx-sd-spi-boot |   81 
 drivers/mmc/Makefile   |3 +
 drivers/mmc/fsl_esdhc_spl.c|  131 
 drivers/mmc/mmc.c  |2 +
 include/configs/P1022DS.h  |   55 +++-
 include/fsl_esdhc.h|1 +
 spl/Makefile   |3 +
 14 files changed, 408 insertions(+), 10 deletions(-)
 create mode 100644 board/freescale/p1022ds/spl.c
 create mode 100644 doc/README.mpc85xx-sd-spi-boot
 create mode 100644 drivers/mmc/fsl_esdhc_spl.c

diff --git a/README b/README
index 50ddd1a..5985903 100644
--- a/README
+++ b/README
@@ -2979,6 +2979,13 @@ FIT uImage format:
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
 
+   CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+   Set for the SPL on PPC mpc8xxx targets, support for
+   arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+
+   CONFIG_SPL_COMMON_INIT_DDR
+   Set for common ddr init with serial presence detect in
+   SPL binary.
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 5c7c598..4e786a4 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -57,6 +57,11 @@ SECTIONS
}
_edata  =  .;
 
+   . = .;
+   __start___ex_table = .;
+   __ex_table : { *(__ex_table) }
+   __stop___ex_table = .;
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c 
b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e958e13..56128a7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -218,12 +218,16 @@ compute_lowest_common_dimm_parameters(const dimm_params_t 
*dimm_params,
if (dimm_params[i].n_ranks) {
if (dimm_params[i].registered_dimm) {
temp1 = 1;
+#ifndef CONFIG_SPL_BUILD
printf("Detected RDIMM %s\n",
dimm_params[i].mpart);
+#endif
} else {
temp2 = 1;
+#ifndef CONFIG_SPL_BUILD
printf("Detected UDIMM %s\n",
dimm_params[i].mpart);
+#endif
}
}
}
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 72bb56c..c334797 100644
--- a/board/freescale/common/Makefile
+++ b/board/fr

[U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import

[ying.zhang]

From: Ying Zhang 

The functionality env_import will be used in the SPL. They
had been excluded by ifndef CONFIG_SPL_BUILD. Now, put it
into the SPL.

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. Split from "spl: Make CONFIG_SPL_BUILD contain more functionality"
3. No change.
4. No change.

 common/env_common.c |2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/common/env_common.c b/common/env_common.c
index 906b41f..8cb81e9 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -156,7 +156,6 @@ int set_default_vars(int nvars, char * const vars[])
H_NOCLEAR | H_INTERACTIVE, nvars, vars);
 }
 
-#ifndef CONFIG_SPL_BUILD
 /*
  * Check if CRC is valid and (if yes) import the environment.
  * Note that "buf" may or may not be aligned.
@@ -188,7 +187,6 @@ int env_import(const char *buf, int check)
 
return 0;
 }
-#endif
 
 void env_relocate(void)
 {
-- 
1.7.0.4


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[U-Boot] [PATCH 01/10 v5] powerpc/mpc85xx: support application without resetvec segment in the linker script

[ying.zhang]

From: Ying Zhang 

For SD/SPI 2-stage bootloader, the On-Chip Rom code loads the SPL into L2 SRAM,
then jump to it to begin execution. After that, the SPL loads the final uboot
image into DDR, then jump to it to begin execution. The segment .resetvec in
the SPL and in final U-boot is useless.

So, add new symbols CONFIG_SYS_MPC85XX_NO_RESETVEC for this application.
If CONFIG_SYS_MPC85XX_NO_RESETVEC is set, the segment .resetvec is excluded
and the segment .bootpg is placed in the previous 4K of the segment .text.

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. No change.
3. No change.
4. No change.

 README  |5 +
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |   19 +++
 arch/powerpc/cpu/mpc85xx/u-boot.lds |8 
 3 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/README b/README
index cd0336c..2a7e4c1 100644
--- a/README
+++ b/README
@@ -4074,6 +4074,11 @@ Low Level (hardware related) configuration options:
that is executed before the actual U-Boot. E.g. when
compiling a NAND SPL.
 
+- CONFIG_SYS_MPC85XX_NO_RESETVEC
+   Only for 85xx systems. If this variable is specified, the 
section
+   .resetvec is not kept and the section .bootpg is placed in the
+   previous 4k of the .text section.
+
 - CONFIG_ARCH_MAP_SYSMEM
Generally U-Boot (and in particular the md command) uses
effective address. It is therefore not necessary to regard
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index f2b7bff..c613e58 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -1,8 +1,5 @@
 /*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, w...@denx.de
- *
- * Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -26,6 +23,13 @@
 #include "config.h"/* CONFIG_BOARDDIR */
 
 OUTPUT_ARCH(powerpc)
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+PHDRS
+{
+   text PT_LOAD;
+   bss PT_LOAD;
+}
+#endif
 SECTIONS
 {
. = CONFIG_SPL_TEXT_BASE;
@@ -68,10 +72,17 @@ SECTIONS
 #else
 #error unknown NAND controller
 #endif
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+   .bootpg ADDR(.text) - 0x1000 :
+   {
+   KEEP(*(.bootpg))
+   } :text = 0x
+#else
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0x
 
+#endif
/*
 * Make sure that the bss segment isn't linked at 0x0, otherwise its
 * address won't be updated during relocation fixups.
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 0503dce..2643563 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -95,6 +95,13 @@ SECTIONS
   . = ALIGN(256);
   __init_end = .;
 
+#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
+  .bootpg ADDR(.text) - 0x1000 :
+  {
+KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootpg))
+  } :text = 0x
+  . = ADDR(.text) + 0x8;
+#else
   .bootpg RESET_VECTOR_ADDRESS - 0xffc :
   {
 arch/powerpc/cpu/mpc85xx/start.o   (.bootpg)
@@ -117,6 +124,7 @@ SECTIONS
 #if (RESET_VECTOR_ADDRESS == 0xfffc)
   . |= 0x10;
 #endif
+#endif
 
   __bss_start = .;
   .bss (NOLOAD)   :
-- 
1.7.0.4


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[U-Boot] [PATCH 05/10 v5] powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL

[ying.zhang]

From: Ying Zhang 

1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.

Signed-off-by: Ying Zhang 

---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. Split from "Add the symbol for the minimal SPL used to eliminate
unused code"
3. Give up new symbol and delete the line
ifndef CONFIG_SPL_BUILD in common/env_common.c
4. Use !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)
to replace to new symbols.


 arch/powerpc/cpu/mpc85xx/tlb.c |3 ++-
 arch/powerpc/cpu/mpc8xxx/law.c |6 --
 include/configs/MPC8313ERDB.h  |1 -
 include/configs/P1022DS.h  |1 -
 include/configs/p1_p2_rdb_pc.h |1 -
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 0dff37f..b903d02 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -55,7 +55,8 @@ void init_tlbs(void)
return ;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+   (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
 void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
   phys_addr_t *rpn)
 {
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 6f9d568..6c0a307 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -92,7 +92,8 @@ void disable_law(u8 idx)
return;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+   (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
 static int get_law_entry(u8 i, struct law_entry *e)
 {
u32 lawar;
@@ -122,7 +123,8 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum 
law_trgt_if id)
return idx;
 }
 
-#if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) && \
+   (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 {
u32 idx;
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 1d753e7..0c15195 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -40,7 +40,6 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
 #define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 9c27182..bcbda30 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -41,7 +41,6 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 2fa5372..b35b966 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -159,7 +159,6 @@
 #define CONFIG_SPL_INIT_MINIMAL
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
 #define CONFIG_SPL_FLUSH_IMAGE
 #define CONFIG_SPL_TARGET  "u-boot-with-spl.bin"
 
-- 
1.7.0.4


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[U-Boot] [PATCH 02/10 v5] powerpc/mpc85xx: modify the functionality clear_bss and aligning the end address of the BSS

[ying.zhang]

From: Ying Zhang 

There will clear the BSS in the function clear_bss(), the reset address of
the BSS started from the __bss_start, and increased by four-byte increments,
finally stoped depending on the address is equal to the _bss_end. If the end
address __bss_end is not alignment to 4byte, it will be an infinite loop.

1. The reset action stoped depending on the reset address is greater
than or equal the end address of the BSS.
2. The end address of the BSS should be 4byte aligned. Because the reset unit
is 4 Bytes.

This patch is on top of the patch "powerpc/mpc85xx: support application
without resetvec segment in the linker script".

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. Modified the function clear_bss().
3. Add explicit alignment of the BSS start address.
4. No change.

 arch/powerpc/cpu/mpc85xx/start.S|2 +-
 arch/powerpc/cpu/mpc85xx/u-boot-spl.lds |2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 4f0480b..2657982 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -1795,7 +1795,7 @@ clear_bss:
stw r0,0(r3)
addir3,r3,4
cmplw   0,r3,r4
-   bne 5b
+   blt 5b
 6:
 
mr  r3,r9   /* Init Data pointer*/
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index c613e58..5c7c598 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -89,10 +89,12 @@ SECTIONS
 */
. |= 0x10;
 
+   . = ALIGN(4);
__bss_start = .;
.bss : {
*(.sbss*)
*(.bss*)
}
+   . = ALIGN(4);
__bss_end = .;
 }
-- 
1.7.0.4


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[U-Boot] [PATCH 03/10 v5] common/Makefile: Add new symbol CONFIG_SPL_ENV_SUPPORT for environment in SPL

[ying.zhang]

From: Ying Zhang 

There will need the environment in SPL for reasons other than network
support (in particular, hwconfig contains info for how to set up DDR).

Add a new symbol CONFIG_SPL_ENV_SUPPORT to replace CONFIG_SPL_NET_SUPPORT
for environment in common/Makefile.

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. Added explanation for CONFIG_SPL_ENV_SUPPORT.
3. Add symbol CONFIG_SPL_ENV_SUPPORT in include/configs/a3m071.h.
4. Add symbol CONFIG_SPL_ENV_IS_IN_NOWHERE in include/configs/am335x_evm.h
   and include/configs/am335x_evm.h

 README   |9 +
 common/Makefile  |   27 +--
 include/configs/a3m071.h |1 +
 include/configs/am335x_evm.h |1 +
 include/configs/pcm051.h |1 +
 5 files changed, 29 insertions(+), 10 deletions(-)

diff --git a/README b/README
index 2a7e4c1..50ddd1a 100644
--- a/README
+++ b/README
@@ -3022,6 +3022,15 @@ FIT uImage format:
CONFIG_SPL_LIBGENERIC_SUPPORT
Support for lib/libgeneric.o in SPL binary
 
+   CONFIG_SPL_ENV_SUPPORT
+   Support for the environment operating in SPL binary
+
+   CONFIG_SPL_NET_SUPPORT
+   Support for the net/libnet.o in SPL binary.
+   It only co-exist with CONFIG_ENV_IS_NOWHERE in the SPL. it
+   conflicts with SPL env from storage medium specified by
+   CONFIG_ENV_IS_xxx.
+
CONFIG_SPL_PAD_TO
Image offset to which the SPL should be padded before appending
the SPL payload. By default, this is defined as
diff --git a/common/Makefile b/common/Makefile
index 3ba4316..6c44a23 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -44,13 +44,11 @@ COBJS-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
 COBJS-y += cmd_boot.o
 COBJS-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
 COBJS-y += cmd_help.o
-COBJS-y += cmd_nvedit.o
 COBJS-y += cmd_version.o
 
 # environment
 COBJS-y += env_attr.o
 COBJS-y += env_callback.o
-COBJS-y += env_common.o
 COBJS-y += env_flags.o
 COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o
 COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o
@@ -216,18 +214,27 @@ COBJS-$(CONFIG_CMD_GPT) += cmd_gpt.o
 endif
 
 ifdef CONFIG_SPL_BUILD
-COBJS-y += cmd_nvedit.o
-COBJS-y += env_common.o
 COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += xyzModem.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += cmd_nvedit.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_attr.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_callback.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_common.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_flags.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += env_nowhere.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += miiphyutil.o
+# environment
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_attr.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_flags.o
+COBJS-$(CONFIG_SPL_ENV_SUPPORT) += env_callback.o
+ifneq ($(CONFIG_SPL_NET_SUPPORT),y)
+COBJS-$(CONFIG_ENV_IS_NOWHERE) += env_nowhere.o
+COBJS-$(CONFIG_ENV_IS_IN_MMC) += env_mmc.o
+COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o
+COBJS-$(CONFIG_ENV_IS_IN_SPI_FLASH) += env_sf.o
+COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o
+else
+COBJS-y += env_nowhere.o
+endif
 endif
+# core command
+COBJS-y += cmd_nvedit.o
+#environment
+COBJS-y += env_common.o
 COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 COBJS-y += console.o
 COBJS-y += dlmalloc.o
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
index e9af825..8f29229 100644
--- a/include/configs/a3m071.h
+++ b/include/configs/a3m071.h
@@ -426,6 +426,7 @@
 #define CONFIG_SPL_BSS_MAX_SIZE(64 << 10)
 
 #define CONFIG_SPL_OS_BOOT
+#define CONFIG_SPL_ENV_SUPPORT
 /* Place patched DT blob (fdt) at this address */
 #define CONFIG_SYS_SPL_ARGS_ADDR   0x0180
 
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index 737e19e..d1246f7 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -355,6 +355,7 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 #define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING  "AM335x U-Boot SPL"
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 2ecd105..9b16c47 100644
--- a/include/configs/pcm051.h
+++ b/include/configs/pcm051.h
@@ -231,6 +231,7 @@
 #define CONFIG_SPL_GPIO_SUPPORT
 #define CONFIG_SPL_YMODEM_SUPPORT
 #define CONFIG_SPL_NET_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
 #define CONFIG_SPL_NET_VCI_STRING  "pcm051 U-Boot SPL"
 #define CONFIG_SPL_ETH_SUPPORT
 #define CONFIG_SPL_SPI_SUPPORT
-- 
1.7.0.4


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[U-Boot] [PATCH 04/10 v5] Makefile: move the common makefile line to public area

[ying.zhang]

From: Ying Zhang 

Move the common makefile line shared by the SPL and non-SPL to the public area,
so that we can avoid excessive SPL symbols. Some of them will be used by the
SPL later.

This patch is on top of the patch "common/Makefile: Add new symbol
CONFIG_SPL_ENV_SUPPORT for environment in SPL".

Signed-off-by: Ying Zhang 
---
Compared with the original version, Changed as below:
1. Split from "boot from SD card/SPI flash with SPL".
2. Move more CONFIG_ENV_IS_IN.. section to public area.
3. Resume CONFIG_ENV_IS_IN.. section to private area for non-SPL.
4. No change.

 common/Makefile |   17 +
 lib/Makefile|   14 --
 2 files changed, 13 insertions(+), 18 deletions(-)

diff --git a/common/Makefile b/common/Makefile
index 6c44a23..3581603 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -189,14 +189,6 @@ COBJS-$(CONFIG_CMD_ZIP) += cmd_zip.o
 COBJS-$(CONFIG_CMD_ZFS) += cmd_zfs.o
 
 # others
-ifdef CONFIG_DDR_SPD
-SPD := y
-endif
-ifdef CONFIG_SPD_EEPROM
-SPD := y
-endif
-COBJS-$(SPD) += ddr_spd.o
-COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
 COBJS-$(CONFIG_BOOTSTAGE) += bootstage.o
 COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
 COBJS-y += flash.o
@@ -235,6 +227,15 @@ endif
 COBJS-y += cmd_nvedit.o
 #environment
 COBJS-y += env_common.o
+#others
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+COBJS-$(SPD) += ddr_spd.o
+COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
 COBJS-$(CONFIG_BOUNCE_BUFFER) += bouncebuf.o
 COBJS-y += console.o
 COBJS-y += dlmalloc.o
diff --git a/lib/Makefile b/lib/Makefile
index 5d58609..a94830f 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
 LIB= $(obj)libgeneric.o
 
 ifndef CONFIG_SPL_BUILD
-COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
 COBJS-$(CONFIG_AES) += aes.o
 COBJS-$(CONFIG_BZIP2) += bzlib.o
 COBJS-$(CONFIG_BZIP2) += bzlib_crctable.o
@@ -36,13 +35,10 @@ COBJS-$(CONFIG_BZIP2) += bzlib_huffman.o
 COBJS-$(CONFIG_USB_TTY) += circbuf.o
 COBJS-y += crc7.o
 COBJS-y += crc16.o
-COBJS-y += display_options.o
-COBJS-y += errno.o
 COBJS-$(CONFIG_OF_CONTROL) += fdtdec.o
 COBJS-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
 COBJS-$(CONFIG_GZIP) += gunzip.o
 COBJS-$(CONFIG_GZIP_COMPRESSED) += gzip.o
-COBJS-y += hashtable.o
 COBJS-y += initcall.o
 COBJS-$(CONFIG_LMB) += lmb.o
 COBJS-y += ldiv.o
@@ -60,14 +56,12 @@ endif
 
 ifdef CONFIG_SPL_BUILD
 COBJS-$(CONFIG_SPL_YMODEM_SUPPORT) += crc16.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += crc32.o
-ifneq ($(CONFIG_SPL_SPI_FLASH_SUPPORT)$(CONFIG_SPL_NET_SUPPORT),)
-COBJS-y += display_options.o
-endif
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += errno.o
-COBJS-$(CONFIG_SPL_NET_SUPPORT) += hashtable.o
 COBJS-$(CONFIG_SPL_NET_SUPPORT) += net_utils.o
 endif
+COBJS-$(CONFIG_ADDR_MAP) += addr_map.o
+COBJS-y += hashtable.o
+COBJS-y += errno.o
+COBJS-y += display_options.o
 COBJS-$(CONFIG_BCH) += bch.o
 COBJS-y += crc32.o
 COBJS-y += ctype.o
-- 
1.7.0.4


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[U-Boot] Not abled to upload binary using "dfu-util"

[Sumit Gemini]

Hi All,

 I am trying to upload images from dfu devices to PC, but

"Copying data from DFU device to PC
Starting upload: [] finished!
Received a total of 1 bytes"

error i got,


do not know why i getting this kind of error because downloading of files
is made but uploading not.

Any help will appreciate.

Thanks
~Sumit Gemini
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Re: [U-Boot] Pull request for u-boot-marvell.git

[Albert ARIBAUD]

Hi Prafulla,

On Wed, 19 Jun 2013 22:38:17 -0700, Prafulla Wadaskar
 wrote:

> The following changes since commit c2543a21df335484fa86bd652b5564d0ca90d5f6:
>   Albert ARIBAUD (1):
> Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'
> 
> are available in the git repository at:
> 
>   u-boot-marvell.git master branch.
> 
> Simon Guinot (3):
>   net2big_v2: initialize I2C fan at startup
>   LaCie/common: add support for the CPLD GPIO bus
>   net2big_v2: initialize LEDs at startup
> 
>  board/LaCie/common/cpld-gpio-bus.c  |   50 +++
>  board/LaCie/common/cpld-gpio-bus.h  |   24 ++
>  board/LaCie/net2big_v2/Makefile |3 +
>  board/LaCie/net2big_v2/net2big_v2.c |  154 
> +--
>  board/LaCie/net2big_v2/net2big_v2.h |5 +
>  include/configs/lacie_kw.h  |9 ++-
>  6 files changed, 236 insertions(+), 9 deletions(-)
>  create mode 100644 board/LaCie/common/cpld-gpio-bus.c
>  create mode 100644 board/LaCie/common/cpld-gpio-bus.
> 
> Regards...
> Prafulla . . .

Applied to u-boot-arm/master, thanks!

Amicalement,
-- 
Albert.
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