Re: [U-Boot] [RFC PATCH] arm: arm926ejs: flush cache before disable it
hi Albert, On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote: snip Invalidating the cache in addition to flushing it would not prevent further writes from dirtying the cache lines if they happen before the cache is disabled. I have a doubt on this. The arm926ejs uses a read-allocate policy, wherein a new cache line is allocated only on a read miss -- a write to an address not present in the cache gets written to memory. So if the cache line is invalidated, how will data get written to the cache. The arm926ej-s data cache does not have a single fixed policy, and does not have a bypass-on-write policy, only write-through and copy-back. Other, more complex, policies may be defined, but at the MMU, not cache, level, and those are not constant for all arm926ej-s based SoCs; not even constant for a given SoC as they are configurable at run-time to fit the chosen system addressing map. Can you please elucidate on these policies. Based on my reading of the arm developers manual and the arm926ejs trm, the mmu makes a particular region cacheable and/or write bufferable. I did not find mention of any other policies. Maybe pointers or links to the documents would help. (Besides, bypassing the cache for writes and not reads is of little interest for plain DDR caching.) Again, afaik this is independent of the target interface that is being cached(if i've missed something, can you please point me to the document). Thanks. -sughosh ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Implement AUART for i.MX28
I have tried to implement an AUART driver for i.MX28. However for it to work I must print 1 character to the debug UART via the serial_pl01x driver. If I do this the AUART will start working. If I don't nothing will be printed to the AUART. Anybody can see any obvious errors? Signed-off-by: Andreas Wass andreas.w...@dalelven.com --- drivers/serial/Makefile |1 + drivers/serial/mxs-regs-uartapp.h | 307 + drivers/serial/mxs_auart.c| 161 +++ drivers/serial/serial.c | 11 +- drivers/serial/serial_pl01x.c | 19 ++- 5 files changed, 492 insertions(+), 7 deletions(-) create mode 100644 drivers/serial/mxs-regs-uartapp.h create mode 100644 drivers/serial/mxs_auart.c diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index fbc4e97..f4e0d45 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o +COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o ifndef CONFIG_SPL_BUILD COBJS-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/mxs-regs-uartapp.h b/drivers/serial/mxs-regs-uartapp.h new file mode 100644 index 000..aad9a78 --- /dev/null +++ b/drivers/serial/mxs-regs-uartapp.h @@ -0,0 +1,307 @@ +/* + * Freescale UARTAPP Register Definitions + * + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. + * + * Xml Revision: 1.42 + * Template revision: 26195 + */ + +#ifndef __ARCH_ARM___UARTAPP_H +#define __ARCH_ARM___UARTAPP_H + + +#define HW_UARTAPP_CTRL0 (0x) +#define HW_UARTAPP_CTRL0_SET (0x0004) +#define HW_UARTAPP_CTRL0_CLR (0x0008) +#define HW_UARTAPP_CTRL0_TOG (0x000c) + +#define BM_UARTAPP_CTRL0_SFTRST0x8000 +#define BM_UARTAPP_CTRL0_CLKGATE 0x4000 +#define BM_UARTAPP_CTRL0_RUN 0x2000 +#define BM_UARTAPP_CTRL0_RX_SOURCE 0x1000 +#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x0800 +#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 +#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF +#define BF_UARTAPP_CTRL0_RXTIMEOUT(v) \ + (((v) 16) BM_UARTAPP_CTRL0_RXTIMEOUT) +#define BP_UARTAPP_CTRL0_XFER_COUNT0 +#define BM_UARTAPP_CTRL0_XFER_COUNT0x +#define BF_UARTAPP_CTRL0_XFER_COUNT(v) \ + (((v) 0) BM_UARTAPP_CTRL0_XFER_COUNT) + +#define HW_UARTAPP_CTRL1 (0x0010) +#define HW_UARTAPP_CTRL1_SET (0x0014) +#define HW_UARTAPP_CTRL1_CLR (0x0018) +#define HW_UARTAPP_CTRL1_TOG (0x001c) + +#define BP_UARTAPP_CTRL1_RSVD2 29 +#define BM_UARTAPP_CTRL1_RSVD2 0xE000 +#define BF_UARTAPP_CTRL1_RSVD2(v) \ + (((v) 29) BM_UARTAPP_CTRL1_RSVD2) +#define BM_UARTAPP_CTRL1_RUN 0x1000 +#define BP_UARTAPP_CTRL1_RSVD1 16 +#define BM_UARTAPP_CTRL1_RSVD1 0x0FFF +#define BF_UARTAPP_CTRL1_RSVD1(v) \ + (((v) 16) BM_UARTAPP_CTRL1_RSVD1) +#define BP_UARTAPP_CTRL1_XFER_COUNT0 +#define BM_UARTAPP_CTRL1_XFER_COUNT0x +#define BF_UARTAPP_CTRL1_XFER_COUNT(v) \ + (((v) 0) BM_UARTAPP_CTRL1_XFER_COUNT) + +#define HW_UARTAPP_CTRL2 (0x0020) +#define HW_UARTAPP_CTRL2_SET (0x0024) +#define HW_UARTAPP_CTRL2_CLR (0x0028) +#define HW_UARTAPP_CTRL2_TOG (0x002c) + +#define BM_UARTAPP_CTRL2_INVERT_RTS0x8000 +#define BM_UARTAPP_CTRL2_INVERT_CTS0x4000 +#define BM_UARTAPP_CTRL2_INVERT_TX 0x2000 +#define BM_UARTAPP_CTRL2_INVERT_RX 0x1000 +#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x0800 +#define BM_UARTAPP_CTRL2_DMAONERR 0x0400 +#define BM_UARTAPP_CTRL2_TXDMAE0x0200 +#define BM_UARTAPP_CTRL2_RXDMAE0x0100 +#define BM_UARTAPP_CTRL2_RSVD2 0x0080 +#define BP_UARTAPP_CTRL2_RXIFLSEL 20 +#define BM_UARTAPP_CTRL2_RXIFLSEL 0x0070 +#define BF_UARTAPP_CTRL2_RXIFLSEL(v) \ + (((v) 20) BM_UARTAPP_CTRL2_RXIFLSEL) +#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER0x1 +#define
[U-Boot] [PATCH v2] arm: exynos: fix clock calculation
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes for v2:
- remove hard-coded constants.
arch/arm/cpu/armv7/exynos/clock.c | 43 -
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..9f07181 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,6 +27,10 @@
#include asm/arch/clk.h
#include asm/arch/periph.h
+#define PLL_DIV_1024 1024
+#define PLL_DIV_65535 65535
+#define PLL_DIV_65536 65536
+
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
unsigned long m, p, s = 0, mask, fout;
+ unsigned int div;
unsigned int freq;
/*
* APLL_CON: MIDV [25:16]
@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
if (pllreg == EPLL) {
k = k 0x;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 s)));
+ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 s)));
} else if (pllreg == VPLL) {
k = k 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 s)));
+
+ /*
+* Exynos4210
+* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+*
+* Exynos4412
+* FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+*
+* Exynos5250
+* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+*/
+ if (proid_is_exynos4210())
+ div = PLL_DIV_1024;
+ else if (proid_is_exynos4412())
+ div = PLL_DIV_65535;
+ else if (proid_is_exynos5250())
+ div = PLL_DIV_65536;
+ else
+ return 0;
+
+ fout = (m + k / div) * (freq / (p * (1 s)));
} else {
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 s)));
+ /*
+* Exynos4210
+* FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+*
+* Exynos4412 / Exynos5250
+* FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+*/
+ if (proid_is_exynos4210())
+ fout = m * (freq / (p * (1 s)));
+ else
+ fout = m * (freq / (p * (1 (s - 1;
}
return fout;
--
1.7.9.5
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[U-Boot] [PATCH] ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx according to errata sprz318e.
In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in
Certain Configurations' of the TI Errata it is recommended to use certain
div/mult values for the DPLL5 clock setup.
So far u-boot used the old 34xx values, so I added the errata recommended
values specificly for 36xx init only.
Also, the FSEL registers exist no longer, so removed them from init.
Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt
lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt
usable in U-Boot and kernel. With this patch, kernel panics disappear and USB
working fine in u-boot and kernel.
Signed-off-by: Andreas Naumann anaum...@ultratronik.de
---
arch/arm/cpu/armv7/omap3/clock.c | 20 +++-
arch/arm/cpu/armv7/omap3/lowlevel_init.S | 18 ++
arch/arm/include/asm/arch-omap3/clocks_omap3.h | 22 ++
3 files changed, 59 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/omap3/clock.c b/arch/arm/cpu/armv7/omap3/clock.c
index 81cc859..68833ba 100644
--- a/arch/arm/cpu/armv7/omap3/clock.c
+++ b/arch/arm/cpu/armv7/omap3/clock.c
@@ -491,6 +491,24 @@ static void dpll4_init_36xx(u32 sil_index, u32 clk_index)
wait_on_value(ST_PERIPH_CLK, 2, prcm_base-idlest_ckgen, LDELAY);
}
+static void dpll5_init_36xx(u32 sil_index, u32 clk_index)
+{
+ struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ dpll_param *ptr = (dpll_param *) get_36x_per2_dpll_param();
+
+ /* Moving it to the right sysclk base */
+ ptr = ptr + clk_index;
+
+ /* PER2 DPLL (DPLL5) */
+ sr32(prcm_base-clken2_pll, 0, 3, PLL_STOP);
+ wait_on_value(1, 0, prcm_base-idlest2_ckgen, LDELAY);
+ sr32(prcm_base-clksel5_pll, 0, 5, ptr-m2); /* set M2 (usbtll_fck) */
+ sr32(prcm_base-clksel4_pll, 8, 11, ptr-m); /* set m (11-bit
multiplier) */
+ sr32(prcm_base-clksel4_pll, 0, 7, ptr-n); /* set n (7-bit divider)*/
+ sr32(prcm_base-clken2_pll, 0, 3, PLL_LOCK); /* lock mode */
+ wait_on_value(1, 1, prcm_base-idlest2_ckgen, LDELAY);
+}
+
static void mpu_init_36xx(u32 sil_index, u32 clk_index)
{
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
@@ -595,7 +613,7 @@ void prcm_init(void)
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
- dpll5_init_34xx(0, clk_index);
+ dpll5_init_36xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
diff --git a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
index eacfef8..66a1b48 100644
--- a/arch/arm/cpu/armv7/omap3/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap3/lowlevel_init.S
@@ -480,6 +480,19 @@ per_36x_dpll_param:
.word 26000,432, 12, 9, 16, 9, 4, 3, 1
.word 38400,360, 15, 9, 16, 5, 4, 3, 1
+per2_36x_dpll_param:
+/* 12MHz */
+.word PER2_36XX_M_12, PER2_36XX_N_12, 0, PER2_36XX_M2_12
+/* 13MHz */
+.word PER2_36XX_M_13, PER2_36XX_N_13, 0, PER2_36XX_M2_13
+/* 19.2MHz */
+.word PER2_36XX_M_19P2, PER2_36XX_N_19P2, 0, PER2_36XX_M2_19P2
+/* 26MHz */
+.word PER2_36XX_M_26, PER2_36XX_N_26, 0, PER2_36XX_M2_26
+/* 38.4MHz */
+.word PER2_36XX_M_38P4, PER2_36XX_N_38P4, 0, PER2_36XX_M2_38P4
+
+
ENTRY(get_36x_mpu_dpll_param)
adr r0, mpu_36x_dpll_param
mov pc, lr
@@ -499,3 +512,8 @@ ENTRY(get_36x_per_dpll_param)
adr r0, per_36x_dpll_param
mov pc, lr
ENDPROC(get_36x_per_dpll_param)
+
+ENTRY(get_36x_per2_dpll_param)
+ adr r0, per2_36x_dpll_param
+ mov pc, lr
+ENDPROC(get_36x_per2_dpll_param)
diff --git a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
index 5925ac4..59e61e8 100644
--- a/arch/arm/include/asm/arch-omap3/clocks_omap3.h
+++ b/arch/arm/include/asm/arch-omap3/clocks_omap3.h
@@ -336,4 +336,26 @@
#define PER_36XX_FSEL_38P4 0x07
#define PER_36XX_M2_38P4 0x09
+/* 36XX PER2 DPLL */
+
+#define PER2_36XX_M_12 0x50
+#define PER2_36XX_N_12 0x00
+#define PER2_36XX_M2_120x08
+
+#define PER2_36XX_M_13 0x1BB
+#define PER2_36XX_N_13 0x05
+#define PER2_36XX_M2_130x08
+
+#define PER2_36XX_M_19P2 0x32
+#define PER2_36XX_N_19P2 0x00
+#define PER2_36XX_M2_19P2 0x08
+
+#define PER2_36XX_M_26 0x1BB
+#define PER2_36XX_N_26 0x0B
+#define PER2_36XX_M2_260x08
+
+#define PER2_36XX_M_38P4 0x19
+#define PER2_36XX_N_38P4 0x00
+#define PER2_36XX_M2_38P4 0x08
+
#endif /* endif _CLOCKS_OMAP3_H_ */
--
1.8.3.1
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Re: [U-Boot] Regression due to 020bbcb usb: hub: Power-cycle on root-hub ports
On Tue, Jul 9, 2013 at 1:23 AM, Stephen Warren swar...@wwwdotorg.org wrote: On 07/08/2013 01:50 PM, Marek Vasut wrote: Dear Stephen Warren, [...] I had already tested the commit in your tree right before the reverts (a36466c50b1b3614c3cfdae194227f7dd8e2c592); that's how I noticed that the reverts weren't necessary, since I'd expected that commit to fail but it didn't. Good to hear that things are working now. :-) Sorry, i missed to notice that patch from Simon, i should have caught that earlier on u-boot-usb/master. So we are now all good? Ready for release, no problems anywhere? As far as I know, yes. (Although I haven't tested u-boot/master recently, but anyway) -- Best Regards Vivek ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] arm: exynos: fix clock calculation
Looks fine to me.
Acked-by: Rajeshwari Shinderajeshwar...@samsung.com
On Tue, Jul 9, 2013 at 1:07 PM, Minkyu Kang mk7.k...@samsung.com wrote:
There are differnce with clock calcuation by cpu variations.
This patch will fix it according to user manual.
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
Changes for v2:
- remove hard-coded constants.
arch/arm/cpu/armv7/exynos/clock.c | 43
-
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index e1c4246..9f07181 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -27,6 +27,10 @@
#include asm/arch/clk.h
#include asm/arch/periph.h
+#define PLL_DIV_1024 1024
+#define PLL_DIV_65535 65535
+#define PLL_DIV_65536 65536
+
/* *
* This structure is to store the src bit, div bit and prediv bit
* positions of the peripheral clocks of the src and div registers
@@ -85,6 +89,7 @@ static struct set_epll_con_val exynos5_epll_div[] = {
static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
{
unsigned long m, p, s = 0, mask, fout;
+ unsigned int div;
unsigned int freq;
/*
* APLL_CON: MIDV [25:16]
@@ -110,14 +115,42 @@ static int exynos_get_pll_clk(int pllreg, unsigned int
r, unsigned int k)
if (pllreg == EPLL) {
k = k 0x;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 65536) * (freq / (p * (1 s)));
+ fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 s)));
} else if (pllreg == VPLL) {
k = k 0xfff;
- /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
- fout = (m + k / 1024) * (freq / (p * (1 s)));
+
+ /*
+* Exynos4210
+* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
+*
+* Exynos4412
+* FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
+*
+* Exynos5250
+* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
+*/
+ if (proid_is_exynos4210())
+ div = PLL_DIV_1024;
+ else if (proid_is_exynos4412())
+ div = PLL_DIV_65535;
+ else if (proid_is_exynos5250())
+ div = PLL_DIV_65536;
+ else
+ return 0;
+
+ fout = (m + k / div) * (freq / (p * (1 s)));
} else {
- /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
- fout = m * (freq / (p * (1 s)));
+ /*
+* Exynos4210
+* FOUT = MDIV * FIN / (PDIV * 2^SDIV)
+*
+* Exynos4412 / Exynos5250
+* FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
+*/
+ if (proid_is_exynos4210())
+ fout = m * (freq / (p * (1 s)));
+ else
+ fout = m * (freq / (p * (1 (s - 1;
}
return fout;
--
1.7.9.5
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Regards,
Rajeshwari Shinde
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[U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism? regards, Andreas PS. Does anybody have the ARM Core Cortex-A8 (AT400/AT401) errata document to make sure my assumption above holds true? --- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..84045d8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -236,8 +236,10 @@ void s_init(void) try_unlock_memory(); +#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr(); +#endif #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] please pull u-boot-samsung master
Dear Amar, On 07/07/13 14:43, Minkyu Kang wrote: Dear Amar, On 6 July 2013 04:12, Albert ARIBAUD albert.u.b...@aribaud.net mailto:albert.u.b...@aribaud.net wrote: Hi Minkyu, This breaks build of VCMA9: s3c24x0_i2c.c: In function 'board_i2c_init': s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use in this function) s3c24x0_i2c.c:544:18: note: each undeclared identifier is reported only once for each function it appears in s3c24x0_i2c.c:545:3: warning: implicit declaration of function 'exynos_pinmux_config' [-Wimplicit-function-declaration] s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE' undeclared (first use in this function) make[1]: *** [/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o] Error 1 make: *** [/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2 Culprit is commit 2c07bb9b, authored by Amar amarendra...@samsung.com mailto:amarendra...@samsung.com. (also: Amar seems to be only part of the author's name. Is this intentional?) Amicalement, -- Albert. please check. seems have problem with non-FDT case. Because of we should merge samsung tree to arm tree before release v2013.07. If you don't do anything, I will revert this patch. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] arm: arm926ejs: flush cache before disable it
Hi Sughosh, On Tue, 9 Jul 2013 11:41:34 +0530, Sughosh Ganu urwithsugh...@gmail.com wrote: hi Albert, On Mon Jul 08, 2013 at 09:55:51PM +0200, Albert ARIBAUD wrote: snip Invalidating the cache in addition to flushing it would not prevent further writes from dirtying the cache lines if they happen before the cache is disabled. I have a doubt on this. The arm926ejs uses a read-allocate policy, wherein a new cache line is allocated only on a read miss -- a write to an address not present in the cache gets written to memory. So if the cache line is invalidated, how will data get written to the cache. The arm926ej-s data cache does not have a single fixed policy, and does not have a bypass-on-write policy, only write-through and copy-back. Other, more complex, policies may be defined, but at the MMU, not cache, level, and those are not constant for all arm926ej-s based SoCs; not even constant for a given SoC as they are configurable at run-time to fit the chosen system addressing map. Can you please elucidate on these policies. Based on my reading of the arm developers manual and the arm926ejs trm, the mmu makes a particular region cacheable and/or write bufferable. I did not find mention of any other policies. Maybe pointers or links to the documents would help. You are correct re the other policies of the DDI0198E (ARM926EJ-S TRM) MMU -- page 3-11, bits 3-2 of the section descriptor. Note however that you may have to refer to your specific SoC's TRM or equivalent, as the SoC designer may have defined its own system-level cache and MMU architecture. Note in any case that none of the policies mentioned in DDI0198E is described as read-allocate (let alone read-allocate only where writes would bypass the enabled cache); on the contrary, the only cache policies mentioned are write-through and write-back, both of which contradict cache bypass on write. (Besides, bypassing the cache for writes and not reads is of little interest for plain DDR caching.) Again, afaik this is independent of the target interface that is being cached(if i've missed something, can you please point me to the document). Thanks. Sorry, I don't understand this last comment of yours wrt my point on the (lack of) interest of bypassing cache for DDR caching. -sughosh Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/5] am335x_evm: Add basic README
On Mon, 08 Jul 2013 12:15:18 -0400, Tom Rini wrote:
Add a README for the family of boards the am335x_evm covers, and
include instructions on preparing and using falcon mode, for various
media.
Signed-off-by: Tom Rini tr...@ti.com
---
board/ti/am335x/README | 113
1 file changed, 113
insertions(+) create mode 100644 board/ti/am335x/README
diff --git a/board/ti/am335x/README b/board/ti/am335x/README
new file mode 100644
index 000..ccc5e16
--- /dev/null
+++ b/board/ti/am335x/README
@@ -0,0 +1,113 @@
+Summary
+===
+
+This document covers various features of the 'am335x_evm' build, and
some of +the related build targets (am335x_evm_uartN, etc).
+
+Hardware
+
+
+The binary produced by this board supports, based on parsing of the
EEPROM +documented in TI's reference designs:
+- AM335x GP EVM
+- AM335x EVM SK
+- Beaglebone White
+- Beaglebone Black
+
+Falcon Mode
+===
+
+The default build includes Falcon Mode (see doc/README.falcon) via
NAND, +eMMC (or raw SD cards) and FAT SD cards. Our default behavior
currently is +to read a 'c' on the console while in SPL at any point
prior to loading the +OS payload (so as soon as possible) to opt to
booting full U-Boot. Also +note that while one can program Falcon
Mode in place great care needs to +be taken by the user to not
'brick' their setup. As these are all eval +boards with multiple
boot methods, recovery should not be an issue in this +worst-case
however. +
+Falcon Mode: eMMC
+=
+
+The recommended layout in this case is:
+
+MMC BLOCKS || LOCATION IN BYTES
+0x - 0x007F : MBR or GPT table : 0x00 -
0x02 +0x0080 - 0x00FF : ARGS or FDT file : 0x01
- 0x02 +0x0100 - 0x01FF : SPL.backup1 (first copy used) :
0x02 - 0x04 +0x0200 - 0x02FF : SPL.backup2 (second copy
used) : 0x04 - 0x06 +0x0300 - 0x06FF :
U-Boot : 0x06 - 0x0e +0x0700 -
0x08FF : U-Boot Env + Redundant : 0x0e - 0x12 +0x0900
- 0x28FF : Kernel : 0x12 - 0x52 +
+Note that when we run 'spl export' it will prepare to boot the
kernel. +This includes relocation of the uImage from where we loaded
it to the entry +point defined in the header. As these locations
overlap by default, it +would leave us with an image that if written
to MMC will not boot, so +instead of using the loadaddr variable we
use 0x8100 in the following +example. In this example we are
loading from the network, for simplicity, +and assume a valid
partition table already exists and 'mmc dev' has already +been run to
select the correct device. Also note that if you previously +had a
FAT partition (such as on a Beaglebone Black) it is not enough to
+write garbage into the area, you must delete it from the partition
table +first. +
+# Ensure we are able to talk with this mmc device
+U-Boot # mmc rescan
+U-Boot # tftp 8100 am335x/MLO
+# Write to two of the backup locations ROM uses
+U-Boot # mmc write 8100 100 100
+U-Boot # mmc write 8100 200 100
+# Write U-Boot to the location set in the config
+U-Boot # tftp 8100 am335x/u-boot.img
+U-Boot # mmc write 8100 300 400
+# Load kernel and device tree into memory, perform export
+U-Boot # tftp 8100 am335x/uImage
+U-Boot # run findfdt
+U-Boot # tftp ${fdtaddr} am335x/${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt 8100 - ${fdtaddr}
+# Write the updated device tree to MMC
+U-Boot # mmc write ${fdtaddr} 80 80
+# Write the uImage to MMC
+U-Boot # mmc write 8100 900 2000
+
+Falcon Mode: FAT SD cards
+=
+
+In this case the additional file is written to the filesystem. In
this +example we assume that the uImage and device tree to be used
are already on +the FAT filesystem (only the uImage MUST be for this
to function +afterwards) along with a Falcon Mode aware MLO and the
FAT partition has +already been created and marked bootable:
+
+U-Boot # mmc rescan
+# Load kernel and device tree into memory, perform export
+U-Boot # load mmc 0:1 ${loadaddr} uImage
+U-Boot # run findfdt
+U-Boot # load mmc 0:1 ${fdtaddr} ${fdtfile}
+U-Boot # run mmcargs
+U-Boot # spl export fdt ${loadaddr} - ${fdtaddr}
+
+This will print a number of lines and then end with something like:
+ Using Device Tree in place at 80f8, end 80f85928
+ Using Device Tree in place at 80f8, end 80f88928
+So then you:
+
+U-Boot # fatwrite mmc 0:1 0x80f8 args 8928
+
+Falcon Mode: NAND
+=
+
+In this case the additional data is written to another partition of
the +NAND. In this example we assume that the uImage and device tree
to be are +already located on the NAND somewhere (such as fileystem
or mtd partition) +along with a Falcon Mode aware MLO written to the
correct
Re: [U-Boot] [PATCHv2] socfpga: Move board/socfpga_cyclone5 to board/socfpga
Hi Pavel,
On Tue, 9 Jul 2013 01:22:01 +0200, Pavel Machek pa...@denx.de wrote:
Hi!
From: Dinh Nguyen dingu...@altera.com
Because the SOCFPGA platform will include support for Cyclone V and
Arria V FPGA parts, renaming socfpga_cyclone5 folder to socfpga to
be more generic.
Signed-off-by: Dinh Nguyen dingu...@altera.com
Reviewed-by: Pavel Machek pa...@denx.de
Cc: Chin Liang See cl...@altera.com
Cc: Wolfgang Denk w...@denx.de
CC: Pavel Machek pa...@denx.de
Cc: Tom Rini tr...@ti.com
v2:
- Add Reviewed-by: Pavel Machek
- Cc: Tom Rini
---
Do you really mean that V2 is the exact same code as V1? If it is, then
V2 is unneeded. And if V2 is different from V1, then history should
tells us the difference(s).
V2 is the same as v1 codewise. So should I resend this a V1 to be
applied?
If V1 is the same as V2 as far as the code is concerned, then there is
simply no point in sending V2 or resending V1 again.
The V2 history makes me guess you thought it necessary to officialize
Pavel's Reviewed-By somehow, but that's unneeded; patchworks takes care
of collecting all the {Reviewed,Acked,Tested,...}-by's and providing
them when applying the patch through pwclient.
This got pretty confusing lately. Can we just wait for the patches to
be applied, or do we need to take some action?
No, no need to take action; I was just clarifying why V2 was unneeded
here, so that similar uneeded new versions are avoided in the future.
Since V1 has already been marked as superseded, I'll apply V2 -- after
2013.07 is out.
Thanks,
Pavel
Amicalement,
--
Albert.
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Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi Andreas, On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann d...@andin.de wrote: Hi, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism? regards, Andreas PS. Does anybody have the ARM Core Cortex-A8 (AT400/AT401) errata document to make sure my assumption above holds true? --- arch/arm/cpu/armv7/omap3/board.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c index b72fadc..84045d8 100644 --- a/arch/arm/cpu/armv7/omap3/board.c +++ b/arch/arm/cpu/armv7/omap3/board.c @@ -236,8 +236,10 @@ void s_init(void) try_unlock_memory(); +#ifndef CONFIG_SYS_DISABLE_CORTEXA8_ERRATA_WORKAROUNDS /* Errata workarounds */ omap3_setup_aux_cr(); +#endif #ifndef CONFIG_SYS_L2CACHE_OFF /* Invalidate L2-cache from secure mode */ Two remarks: 1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA 2. (if applicable) I would prefer erratum-specific options, e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, ERRATA will be fine too; what I want is easing the search for errata by number. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import
Excuse me, this patch has not been merged? Thanks. -Original Message- From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini Sent: Friday, June 28, 2013 5:57 AM To: Wood Scott-B07421 Cc: u-boot@lists.denx.de; Wood Scott-B07421; aflem...@gmail.com; Zhang Ying-B40530 Subject: Re: [U-Boot] [PATCH 06/10 v5] spl: env_common.c: make CONFIG_SPL_BUILD contain function env_import On Thu, Jun 27, 2013 at 03:16:34PM -0500, Scott Wood wrote: On 06/27/2013 07:17:48 AM, Tom Rini wrote: On Thu, Jun 27, 2013 at 02:35:34AM +, Zhang Ying-B40530 wrote: -Original Message- From: Tom Rini [mailto:tom.r...@gmail.com] On Behalf Of Tom Rini [snip] Building for am335x_evm and am335x_evm_usbspl should tell you if it is, or is not. Whacking network support into SPL required more than --gc-sections alone could give us and we needed to drop a few couldn't-ever-reach calls and functionality out. [Zhang Ying] Yes, I tried to build for am335x_evm without this ifdef, no problem. Whether it can be removed? Did you also build am335x_evm_usbspl? It builds OK for me with the ifdef removed. It adds 81 bytes to the SPL. I think we can live with that. Acked-by: Tom Rini tr...@ti.com -- Tom ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] usb: omap5-evm: Add ethernet support to the uevm
Hi Dan, On 07/08/2013 11:59 PM, Dan Murphy wrote: Add code to configure the USB EHCI host controller. This enumerates an ethernet controller through USB3 using the HSIC lines. Signed-off-by: Dan Murphy dmur...@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 15 +++ arch/arm/include/asm/arch-omap5/clock.h |6 + arch/arm/include/asm/arch-omap5/ehci.h | 44 +++ arch/arm/include/asm/ehci-omap.h|1 + board/ti/omap5_uevm/evm.c | 35 board/ti/omap5_uevm/mux_data.h |4 ++- drivers/usb/host/ehci-omap.c|2 +- include/configs/omap5_common.h |2 -- include/configs/omap5_uevm.h| 23 9 files changed, 128 insertions(+), 4 deletions(-) create mode 100644 arch/arm/include/asm/arch-omap5/ehci.h diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 56cf1f8..f3973ee 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -412,6 +412,8 @@ void enable_basic_clocks(void) (*prcm)-cm_l4per_gpio4_clkctrl, (*prcm)-cm_l4per_gpio5_clkctrl, (*prcm)-cm_l4per_gpio6_clkctrl, + (*prcm)-cm_clksel_usb_60mhz, + (*prcm)-cm_l3init_hsusbtll_clkctrl, 0 }; @@ -423,6 +425,7 @@ void enable_basic_clocks(void) (*prcm)-cm_wkup_wdtimer2_clkctrl, (*prcm)-cm_l4per_uart3_clkctrl, (*prcm)-cm_l4per_i2c1_clkctrl, + (*prcm)-cm_l3init_hsusbhost_clkctrl, 0 }; @@ -446,6 +449,14 @@ void enable_basic_clocks(void) setbits_le32((*prcm)-cm_wkup_gptimer1_clkctrl, GPTIMER1_CLKCTRL_CLKSEL_MASK); + /* Enbale all 3 usb ports enable uhh, utmi and hsic clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbhost_clkctrl, + USB_HOST_HS_CLKCTRL_MASK); + + /* Enbale all 3 usb host ports tll clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); + Why enable all 3 port clocks here? uEVM uses only 2 ports. Did you verify that if you boot the linux kernel without USB support then the USB_Host and USB_TLL module are back to idle state? Just checking if we need to add something more in the linux kernel to make sure that these modules are not stuck in transition state. If this is taken care of, I really don't mind even if all 3 clocks kept enabled ;). do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, @@ -480,6 +491,10 @@ void enable_basic_uboot_clocks(void) 0 }; + /* Enbale all 3 usb host ports tll clocks*/ + setbits_le32((*prcm)-cm_l3init_hsusbtll_clkctrl, + USB_TLL_HS_CLKCTRL_MASK); + do_enable_clocks(clk_domains_essential, clk_modules_hw_auto_essential, clk_modules_explicit_en_essential, cheers, -roger ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] HACK: ehci-omap: do gpio toggle after port power is set
On 07/08/2013 11:59 PM, Dan Murphy wrote:
Need to check why gpio toggling in ehci-omap is not
working and works only from ehci-hcd.
do you mean HSIC detection is not working?
GPIO toggling has to work from anywhere.
Signed-off-by: Dan Murphy dmur...@ti.com
---
drivers/usb/host/ehci-hcd.c |7 ++-
drivers/usb/host/ehci-omap.c |2 +-
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 706cf0c..17d0c9c 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -29,7 +29,7 @@
#include malloc.h
#include watchdog.h
#include linux/compiler.h
-
+#include asm/ehci-omap.h
#include ehci.h
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
@@ -776,6 +776,11 @@ ehci_submit_root(struct usb_device *dev, unsigned long
pipe, void *buffer,
if (HCS_PPC(ehci_readl(ctrl-hccr-cr_hcsparams))) {
reg |= EHCI_PS_PP;
ehci_writel(status_reg, reg);
+#ifdef CONFIG_USB_EHCI_OMAP
+ omap_ehci_phy_reset(1, 1000);
+ mdelay(10);
+ omap_ehci_phy_reset(0, 1000);
+#endif
Did you try to first keep the PHY in reset, start the EHCI controller
and then release the reset?
At least this is what is done in the Linux kernel to get it to work.
}
break;
case USB_PORT_FEAT_RESET:
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 17f2214..68add44 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -109,7 +109,7 @@ int board_usb_init(void) __attribute__((weak,
alias(__board_usb_init)));
#if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO)
/* controls PHY(s) reset signal(s) */
-static inline void omap_ehci_phy_reset(int on, int delay)
+void omap_ehci_phy_reset(int on, int delay)
{
/*
* Refer ISSUE1:
cheers,
-roger
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Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi Andreas, On 07/09/2013 11:10 AM, Albert ARIBAUD wrote: Hi Andreas, On Tue, 09 Jul 2013 10:08:10 +0200, Andreas Naumann d...@andin.de wrote: Hi, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism? regards, Andreas PS. Does anybody have the ARM Core Cortex-A8 (AT400/AT401) errata document to make sure my assumption above holds true? I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1. snip Two remarks: 1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA 2. (if applicable) I would prefer erratum-specific options, e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, ERRATA will be fine too; what I want is easing the search for errata by number. I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary. Best regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi Andreas, On Tue, 09 Jul 2013 12:42:27 +0200, Andreas Bießmann andreas.de...@googlemail.com wrote: Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary. Seconded. Best regards Andreas Bießmann Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Separately compile Master boot loader
Hi I am working on one board with an arm11 based cpu, NOR flash and DDR2 SDRAM. When I compile u-boot source code, I get u-boot.bin image generated. This image has primary(second stage) and secondary(third stage) bootloader combined. I have following queries: 1) The question that still eats me everyday is, How can I compile primary(Master) boot loader and secondary boot loader separately? 2) I want to Flash only initial 4kb of code (Master boot loader or second stage). The remaining code I want to keep at another partition in the Flash. How can I achieve this? 3) Is there any separate code available for Master boot loader, which copies the third stage bootloader to SDRAM and then transfers control to that third stage boot loader(u-boot)? I am unable to find a way to do this. Can anyone help me please? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/7 v7] powerpc: deleted unused symbol CONFIG_SPL_NAND_MINIMAL and enabled some functionality for common SPL
From: Ying Zhang b40...@freescale.com
1. The symbol CONFIG_SPL_NAND_MINIMAL is unused, so deleted it.
2. Some functions were unused in the minimal SPL, but it is useful
in the common SPL. So, enabled some functionality for common SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- No change.
Change from v5:
- No change.
Change from v4:
- Use !defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL)
- to replace to new symbols.
Change from v3:
- Give up new symbol and delete the line
- ifndef CONFIG_SPL_BUILD in common/env_common.c
Change from v2:
- Split from Add the symbol for the minimal SPL used to eliminate unused
- code
Change from v1:
- Split from boot from SD card/SPI flash with SPL.
arch/powerpc/cpu/mpc85xx/tlb.c |3 ++-
arch/powerpc/cpu/mpc8xxx/law.c |6 --
include/configs/MPC8313ERDB.h |1 -
include/configs/P1022DS.h |1 -
include/configs/p1_p2_rdb_pc.h |1 -
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c
index 0dff37f..b903d02 100644
--- a/arch/powerpc/cpu/mpc85xx/tlb.c
+++ b/arch/powerpc/cpu/mpc85xx/tlb.c
@@ -55,7 +55,8 @@ void init_tlbs(void)
return ;
}
-#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
phys_addr_t *rpn)
{
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 6f9d568..6c0a307 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -92,7 +92,8 @@ void disable_law(u8 idx)
return;
}
-#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
static int get_law_entry(u8 i, struct law_entry *e)
{
u32 lawar;
@@ -122,7 +123,8 @@ int set_next_law(phys_addr_t addr, enum law_size sz, enum
law_trgt_if id)
return idx;
}
-#if !defined(CONFIG_NAND_SPL) !defined(CONFIG_SPL_BUILD)
+#if !defined(CONFIG_NAND_SPL) \
+ (!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
{
u32 idx;
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 1d753e7..0c15195 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -40,7 +40,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND
diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index 9c27182..bcbda30 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -41,7 +41,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 2fa5372..b35b966 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -159,7 +159,6 @@
#define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
-#define CONFIG_SPL_NAND_MINIMAL
#define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET u-boot-with-spl.bin
--
1.7.0.4
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH 4/7 v7] powerpc : spi flash : Support to start from eSPI with SPL
From: Ying Zhang b40...@freescale.com
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so
that ddr spd code can get the interleaving mode setting in env. It
loads final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions
enabled.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- No change.
Change from v5:
- Split from powerpc/p1022ds: boot from spi flash with SPL
- this patch add the capability starting from eSPI with SPL.
Change from v4:
- No change.
Change from v3:
- No change.
Change from v2:
- No change.
Change from v1:
- Split from boot from SD card/SPI flash with SPL.
drivers/mtd/spi/Makefile |1 +
drivers/mtd/spi/fsl_espi_spl.c | 78
drivers/mtd/spi/spi_flash.c|2 +
3 files changed, 81 insertions(+), 0 deletions(-)
create mode 100644 drivers/mtd/spi/fsl_espi_spl.c
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index ecbb210..39e4e1d 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libspi_flash.o
ifdef CONFIG_SPL_BUILD
COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_load.o
+COBJS-$(CONFIG_SPL_SPI_BOOT) += fsl_espi_spl.o
endif
COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o
diff --git a/drivers/mtd/spi/fsl_espi_spl.c b/drivers/mtd/spi/fsl_espi_spl.c
new file mode 100644
index 000..443c2e1
--- /dev/null
+++ b/drivers/mtd/spi/fsl_espi_spl.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include spi_flash.h
+#include malloc.h
+
+#define ESPI_BOOT_IMAGE_SIZE 0x48
+#define ESPI_BOOT_IMAGE_ADDR 0x50
+#define CONFIG_CFG_DATA_SECTOR 0
+
+/*
+ * The main entry for SPI booting. It's necessary that SDRAM is already
+ * configured and available since this code loads the main U-Boot image
+ * from SPI into SDRAM and starts it from there.
+ */
+void spi_boot(void)
+{
+ void (*uboot)(void) __noreturn;
+ u32 offset, code_len;
+ unsigned char *buf = NULL;
+ struct spi_flash *flash;
+
+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
+ if (flash == NULL) {
+ puts(\nspi_flash_probe failed);
+ hang();
+ }
+
+ /*
+ * Load U-Boot image from SPI flash into RAM
+ */
+ buf = malloc(flash-page_size);
+ if (buf == NULL) {
+ puts(\nmalloc failed);
+ hang();
+ }
+ memset(buf, 0, flash-page_size);
+
+ spi_flash_read(flash, CONFIG_CFG_DATA_SECTOR, \
+ flash-page_size, (void *)buf);
+ offset = *(u32 *)(buf + ESPI_BOOT_IMAGE_ADDR);
+ /* Skip spl code */
+ offset += CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS;
+ /* Get the code size from offset 0x48 */
+ code_len = *(u32 *)(buf + ESPI_BOOT_IMAGE_SIZE);
+ /* Skip spl code */
+ code_len = code_len - CONFIG_SPL_MAX_SIZE;
+ /* copy code to DDR */
+ spi_flash_read(flash, offset, code_len, \
+ (void *)CONFIG_SYS_SPI_FLASH_U_BOOT_DST);
+ /*
+ * Jump to U-Boot image
+ */
+ flush_cache(CONFIG_SYS_SPI_FLASH_U_BOOT_DST, \
+ code_len);
+ uboot = (void *) CONFIG_SYS_SPI_FLASH_U_BOOT_START;
+ (*uboot)();
+}
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 6a6fe37..e474f5c 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -554,12 +554,14 @@ struct spi_flash *spi_flash_probe(unsigned int bus,
unsigned int cs,
goto err_manufacturer_probe;
}
#endif
+#ifndef CONFIG_SPL_BUILD
printf(SF: Detected %s with page size , flash-name);
[U-Boot] [PATCH 6/7 v7] NAND: TPL : introduce the TPL based on the SPL
From: Ying Zhang b40...@freescale.com
Due to the nand SPL on some board(e.g. P1022DS)has a size limit, it can
not be more than 4K. So, the SPL cannot initialize the DDR with the SPD
code. This patch introduces TPL to enable a loader stub that is loaded
by the code from the SPL. It initializes the DDR with the SPD or other
operations.
The TPL's size is sizeable, the maximum size is decided by the memory's
size that TPL runs. It initializes the DDR through SPD code, and copys
final uboot image to DDR. So there are three stage uboot images:
* spl_boot, * tpl_boot, * final uboot image
This patch is on top of the patch:
SPL: Makefile: Build a separate autoconf.mk for SPL
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Modify the description of the patch.
- Add the separate the autoconf.mk for TPL.
- Delete the file tpl/Makefile and the directory tpl.
- Reuse the spl/Makefie in TPL.
Change from v5:
- Use ifdef to define nand_load_image to non-static for non-SPL.
Change from v4:
- No change.
Change from v3:
- No change.
Change from v2:
- No change.
Change from v1:
- Split from powerpc/p1022ds: nand: introduce the TPL based on the SPL.
Makefile| 43 ++--
README |9 +
config.mk | 17 +
doc/README.TPL | 69 +++
drivers/mtd/nand/Makefile |8
drivers/mtd/nand/fsl_elbc_spl.c |5 ++-
include/nand.h |3 ++
spl/Makefile| 37 -
8 files changed, 185 insertions(+), 6 deletions(-)
create mode 100644 doc/README.TPL
diff --git a/Makefile b/Makefile
index 7de687c..e3b7a1b 100644
--- a/Makefile
+++ b/Makefile
@@ -413,6 +413,7 @@ ALL-y += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map
ALL-$(CONFIG_NAND_U_BOOT) += $(obj)u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += $(obj)u-boot-onenand.bin
ALL-$(CONFIG_SPL) += $(obj)spl/u-boot-spl.bin
+ALL-$(CONFIG_TPL) += $(obj)spl/u-boot-tpl.bin
ALL-$(CONFIG_OF_SEPARATE) += $(obj)u-boot.dtb $(obj)u-boot-dtb.bin
ifneq ($(CONFIG_SPL_TARGET),)
ALL-$(CONFIG_SPL) += $(obj)$(subst ,,$(CONFIG_SPL_TARGET))
@@ -492,12 +493,25 @@ $(obj)u-boot.dis: $(obj)u-boot
$(OBJDUMP) -d $ $@
-
+ifdef CONFIG_TPL
+$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-tpl.bin \
+ $(obj)u-boot.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary \
+ $(obj)spl/u-boot-spl.bin $(obj)spl/u-boot-spl-pad.bin
+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
+ -I binary -O binary \
+ $(obj)spl/u-boot-tpl.bin $(obj)spl/u-boot-tpl-pad.bin
+ cat $(obj)spl/u-boot-spl-pad.bin $(obj)spl/u-boot-tpl-pad.bin \
+ $(obj)u-boot.bin $@
+# rm $(obj)spl/u-boot-spl-pad.bin $(obj)spl/u-boot-tpl-pad.bin
+else
$(obj)u-boot-with-spl.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(CONFIG_SPL_PAD_TO) \
-I binary -O binary $ $(obj)spl/u-boot-spl-pad.bin
cat $(obj)spl/u-boot-spl-pad.bin $(obj)u-boot.bin $@
rm $(obj)spl/u-boot-spl-pad.bin
+endif
$(obj)u-boot-with-spl.imx: $(obj)spl/u-boot-spl.bin $(obj)u-boot.bin
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common \
@@ -621,7 +635,12 @@ $(obj)u-boot-nand.bin: nand_spl $(obj)u-boot.bin
cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin
$(obj)u-boot-nand.bin
$(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend
- $(MAKE) -C spl all
+ $(MAKE) -C spl clean
+ $(MAKE) -C spl all CONFIG_SPL_BUILD=y
+
+$(obj)spl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
+ $(MAKE) -C spl clean
+ $(MAKE) -C spl all CONFIG_TPL_BUILD=y CONFIG_SPL_BUILD=y
updater:
$(MAKE) -C tools/updater all
@@ -630,6 +649,7 @@ updater:
# parallel sub-makes creating .depend files simultaneously.
depend dep:$(TIMESTAMP_FILE) $(VERSION_FILE) \
$(obj)include/spl-autoconf.mk \
+ $(obj)include/tpl-autoconf.mk \
$(obj)include/autoconf.mk \
$(obj)include/generated/generic-asm-offsets.h \
$(obj)include/generated/asm-offsets.h
@@ -705,6 +725,15 @@ $(obj)include/autoconf.mk: $(obj)include/config.h
sed -n -f tools/scripts/define2mk.sed $@.tmp \
mv $@.tmp $@
# Auto-generate the spl-autoconf.mk file (which is included by all makefiles
for SPL)
+$(obj)include/tpl-autoconf.mk: $(obj)include/config.h
+ @$(XECHO) Generating $@ ; \
+ set -e ; \
+ : Extract the config macros ; \
+ $(CPP) $(CFLAGS) -DCONFIG_TPL_BUILD -DCONFIG_SPL_BUILD\
+
[U-Boot] [PATCH 2/7 v7] powerpc: mpc85xx: Support booting from SD Card with SPL
From: Ying Zhang b40...@freescale.com
This patch introduces SPL to enable a loader stub that being loaded by
the code from the internal on-chip ROM. It loads the final uboot image
into DDR, then jump to it to begin execution.
The SPL's size is sizeable, the maximum size must not exceed the size of L2
SRAM. It initializes the DDR through SPD code, and copys final uboot image
to DDR. So there are two stage uboot images:
* spl_boot, 96KB size. The env variables are copied to L2 SRAM, so
that ddr spd code can get the interleaving mode setting in env. It
loads final uboot image from offset 96KB.
* final uboot image, size is variable depends on the functions
enabled.
This patch is on top of the patch:
SPL: Makefile: Build a separate autoconf.mk for SPL
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Split to the patch Support booting from SD Card with SPL and the patch
- Enable P1022DS to boot from SD Card with SPL. this patch only support
- booting from SD Card with SPL
Change from v5:
- Add new symbol CONFIG_SPL_ENV_IMPORT for contain the functionality
- env_import.
Change from v4:
- No change.
Change from v3:
- No change.
Change from v2:
- No change.
Change from v1:
- Split from boot from SD card/SPI flash with SPL.
README |4 +
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds|5 +
.../cpu/mpc8xxx/ddr/lc_common_dimm_params.c|4 +
doc/README.mpc85xx-sd-spi-boot | 81
drivers/mmc/Makefile |3 +
drivers/mmc/fsl_esdhc_spl.c| 131
drivers/mmc/mmc.c |2 +
include/fsl_esdhc.h|1 +
spl/Makefile |3 +
9 files changed, 234 insertions(+), 0 deletions(-)
create mode 100644 doc/README.mpc85xx-sd-spi-boot
create mode 100644 drivers/mmc/fsl_esdhc_spl.c
diff --git a/README b/README
index 85e5a8d..9543749 100644
--- a/README
+++ b/README
@@ -3023,6 +3023,10 @@ FIT uImage format:
Support for NAND boot using simple NAND drivers that
expose the cmd_ctrl() interface.
+ CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+ Set for the SPL on PPC mpc8xxx targets, support for
+ arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 20284ed..8aeb1a0 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -60,6 +60,11 @@ SECTIONS
}
_edata = .;
+ . = .;
+ __start___ex_table = .;
+ __ex_table : { *(__ex_table) }
+ __stop___ex_table = .;
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
index e958e13..56128a7 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c
@@ -218,12 +218,16 @@ compute_lowest_common_dimm_parameters(const dimm_params_t
*dimm_params,
if (dimm_params[i].n_ranks) {
if (dimm_params[i].registered_dimm) {
temp1 = 1;
+#ifndef CONFIG_SPL_BUILD
printf(Detected RDIMM %s\n,
dimm_params[i].mpart);
+#endif
} else {
temp2 = 1;
+#ifndef CONFIG_SPL_BUILD
printf(Detected UDIMM %s\n,
dimm_params[i].mpart);
+#endif
}
}
}
diff --git a/doc/README.mpc85xx-sd-spi-boot b/doc/README.mpc85xx-sd-spi-boot
new file mode 100644
index 000..d5043cc
--- /dev/null
+++ b/doc/README.mpc85xx-sd-spi-boot
@@ -0,0 +1,81 @@
+
+Booting from On-Chip ROM (eSDHC or eSPI)
+
+
+boot_format is a tool to write SD bootable images to a filesystem and build
+SD/SPI images to a binary file for writing later.
+
+When booting from an SD card/MMC, boot_format puts the configuration file and
+the RAM-based U-Boot image on the card.
+When booting from an EEPROM, boot_format generates a binary image that is used
+to boot from this EEPROM.
+
+Where to get boot_format:
+
+
+you can browse it online at:
+http://git.freescale.com/git/cgit.cgi/ppc/sdk/boot-format.git/
+
+Building
+
+
+Run the following to
[U-Boot] [PATCH 5/7 v7] powerpc : p1022ds : enable p1022ds to start from eSPI with SPL
From: Ying Zhang b40...@freescale.com Enable p1022ds to start from eSPI with SPL. Signed-off-by: Ying Zhang b40...@freescale.com --- Change from v6: - No longer changes the header file included by the file - board/freescale/p1022ds/spl.c Change from v5: - Split from powerpc/p1022ds: boot from spi flash with SPL - this patch enable P1022DS to start from eSPI with SPL. Change from v4: - No change. Change from v3: - No change. Change from v2: - No change. Change from v1: - Split from boot from SD card/SPI flash with SPL. board/freescale/p1022ds/spl.c | 10 ++ include/configs/P1022DS.h | 36 +--- 2 files changed, 39 insertions(+), 7 deletions(-) diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c index 9927671..b6669f3 100644 --- a/board/freescale/p1022ds/spl.c +++ b/board/freescale/p1022ds/spl.c @@ -27,6 +27,7 @@ #include i2c.h #include ../common/ngpixis.h #include fsl_esdhc.h +#include spi_flash.h DECLARE_GLOBAL_DATA_PTR; @@ -53,6 +54,11 @@ void board_init_f(ulong bootflag) setbits_be32(gur-pmuxcr, in_be32(gur-pmuxcr) | MPC85xx_PMUXCR_SD_DATA); +#ifdef CONFIG_SPL_SPI_BOOT + /* Enable the SPI */ + clrsetbits_8(pixis-brdcfg0, PIXIS_ELBC_SPI_MASK, PIXIS_SPI); +#endif + /* Read back the register to synchronize the write. */ in_be32(gur-pmuxcr); @@ -66,6 +72,8 @@ void board_init_f(ulong bootflag) bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts(\nSD boot...\n); +#elif defined(CONFIG_SPL_SPI_BOOT) + puts(\nSPI Flash boot...\n); #endif /* copy code to RAM and jump to it - this should not return */ @@ -107,5 +115,7 @@ void board_init_r(gd_t *gd, ulong dest_addr) #ifdef CONFIG_SPL_MMC_BOOT mmc_boot(); +#elif defined(CONFIG_SPL_SPI_BOOT) + spi_boot(); #endif } diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index 7cb049c..607b754 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -48,11 +48,33 @@ #endif #ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_SYS_TEXT_BASE 0x1100 -#define CONFIG_RESET_VECTOR_ADDRESS0x1107fffc +#define CONFIG_SPL +#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT +#define CONFIG_SPL_ENV_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_FLASH_MINIMAL +#define CONFIG_SPL_FLUSH_IMAGE +#define CONFIG_SPL_TARGET u-boot-with-spl.bin +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_SYS_TEXT_BASE 0x11001000 +#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_SPL_PAD_TO 0x18000 +#define CONFIG_SPL_MAX_SIZE(96 * 1024) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 10) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST(0x1100) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x1100) +#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 10) +#define CONFIG_SYS_MPC85XX_NO_RESETVEC +#define CONFIG_SYS_LDSCRIPTarch/powerpc/cpu/mpc85xx/u-boot.lds +#define CONFIG_SPL_SPI_BOOT +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SPL_COMMON_INIT_DDR +#endif #endif #define CONFIG_NAND_FSL_ELBC @@ -318,7 +340,7 @@ * Config the L2 Cache as L2 SRAM */ #if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR0xf8f8 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #define CONFIG_SYS_L2_SIZE (256 10) @@ -562,7 +584,7 @@ /* * Environment */ -#ifdef CONFIG_RAMBOOT_SPIFLASH +#ifdef CONFIG_SPIFLASH #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/7 v7] powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPL
From: Ying Zhang b40...@freescale.com
Enable p1022ds to start from eSDHC with SPL.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Split from the patch powerpc/p1022ds: boot from SD Card with SPL,
- this patch only enables p1022ds to boot from SD Card with SPL.
Change from v5:
- No change.
Change from v4:
- No change.
Change from v3:
- No change.
Change from v2:
- No change.
Change from v1:
- No change.
README |4 ++
board/freescale/common/Makefile |2 -
board/freescale/p1022ds/Makefile |3 +
board/freescale/p1022ds/spl.c| 111 ++
board/freescale/p1022ds/tlb.c|9 +++-
include/configs/P1022DS.h| 54 ---
6 files changed, 173 insertions(+), 10 deletions(-)
create mode 100644 board/freescale/p1022ds/spl.c
diff --git a/README b/README
index 9543749..5872b5e 100644
--- a/README
+++ b/README
@@ -3027,6 +3027,10 @@ FIT uImage format:
Set for the SPL on PPC mpc8xxx targets, support for
arch/powerpc/cpu/mpc8xxx/ddr/libddr.o in SPL binary.
+ CONFIG_SPL_COMMON_INIT_DDR
+ Set for common ddr init with serial presence detect in
+ SPL binary.
+
CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT,
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE,
CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS,
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 37236d0..e991def 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -61,9 +61,7 @@ COBJS-$(CONFIG_MPC8555CDS)+= cds_pci_ft.o
COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o
COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o
-ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_P1022DS)+= ics307_clk.o
-endif
COBJS-$(CONFIG_P2020DS)+= ics307_clk.o
COBJS-$(CONFIG_P3041DS)+= ics307_clk.o
COBJS-$(CONFIG_P4080DS)+= ics307_clk.o
diff --git a/board/freescale/p1022ds/Makefile b/board/freescale/p1022ds/Makefile
index 0eeef05..9746063 100644
--- a/board/freescale/p1022ds/Makefile
+++ b/board/freescale/p1022ds/Makefile
@@ -24,6 +24,9 @@ ifdef MINIMAL
COBJS-y+= spl_minimal.o tlb.o law.o
else
+ifdef CONFIG_SPL_BUILD
+COBJS-y += spl.o
+endif
COBJS-y+= $(BOARD).o
COBJS-y+= ddr.o
COBJS-y+= law.o
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
new file mode 100644
index 000..9927671
--- /dev/null
+++ b/board/freescale/p1022ds/spl.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ *
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include common.h
+#include ns16550.h
+#include malloc.h
+#include mmc.h
+#include nand.h
+#include i2c.h
+#include ../common/ngpixis.h
+#include fsl_esdhc.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const u32 sysclk_tbl[] = {
+ 6000, 7499900, 83332500, 800,
+ 9000, 1000, 12499800, 1200
+};
+
+ulong get_effective_memsize(void)
+{
+ return CONFIG_SYS_L2_SIZE;
+}
+
+void board_init_f(ulong bootflag)
+{
+ int px_spd;
+ u32 plat_ratio, sys_clk, bus_clk;
+ ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+
+ console_init_f();
+
+ /* Set pmuxcr to allow both i2c1 and i2c2 */
+ setbits_be32(gur-pmuxcr, in_be32(gur-pmuxcr) | 0x1000);
+ setbits_be32(gur-pmuxcr,
+ in_be32(gur-pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
+
+ /* Read back the register to synchronize the write. */
+ in_be32(gur-pmuxcr);
+
+ /* initialize selected port with appropriate baud rate */
+ px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
+ sys_clk = sysclk_tbl[px_spd PIXIS_SPD_SYSCLK_MASK];
+ plat_ratio = in_be32(gur-porpllsr) MPC85xx_PORPLLSR_PLAT_RATIO;
+ bus_clk = sys_clk * plat_ratio / 2;
+
+ NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+ bus_clk / 16 / CONFIG_BAUDRATE);
+#ifdef CONFIG_SPL_MMC_BOOT
+ puts(\nSD boot...\n);
+#endif
+
+ /* copy code to RAM and jump to it - this should not return */
+ /* NOTE - code has to be copied out of NAND buffer
[U-Boot] [PATCH 7/7 v7] powerpc: p1022ds: add TPL for p1022ds nand boot
From: Ying Zhang b40...@freescale.com
TPL is introduced in the patch NAND: TPL : introduce the TPL
based on the SPL, here enable TPL for p1022ds nand boot.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v6:
- Delete the file board/freescale/p1022ds/tpl.c.
- Reuse the file board/freescale/p1022ds/spl.c in the TPL.
Change from v5:
- Change functionality nand_load_image to nand_load, it is called in TPL.
Change from v4:
- No change.
Change from v3:
- No change.
Change from v2:
- No change.
Change from v1:
- Split from powerpc/p1022ds: nand: introduce the TPL based on the SPL.
board/freescale/p1022ds/spl.c | 15 +++
board/freescale/p1022ds/spl_minimal.c | 53 ++---
include/configs/P1022DS.h | 69 ++--
3 files changed, 76 insertions(+), 61 deletions(-)
diff --git a/board/freescale/p1022ds/spl.c b/board/freescale/p1022ds/spl.c
index b6669f3..79e3ac4 100644
--- a/board/freescale/p1022ds/spl.c
+++ b/board/freescale/p1022ds/spl.c
@@ -101,21 +101,36 @@ void board_init_r(gd_t *gd, ulong dest_addr)
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR, \
CONFIG_SPL_RELOC_MALLOC_SIZE);
+#ifndef CONFIG_SPL_NAND_BOOT
env_init();
+#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
#endif
/* relocate environment function pointers etc. */
+#ifdef CONFIG_SPL_NAND_BOOT
+ nand_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+ (uchar *)CONFIG_ENV_ADDR);
+ gd-env_addr = (ulong)(CONFIG_ENV_ADDR);
+ gd-env_valid = 1;
+#else
env_relocate();
+#endif
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
gd-ram_size = initdram(0);
+#ifdef CONFIG_SPL_NAND_BOOT
+ puts(Tertiary program loader running in sram...);
+#else
puts(Second program loader running in sram...\n);
+#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
+#elif defined(CONFIG_SPL_NAND_BOOT)
+ nand_boot();
#endif
}
diff --git a/board/freescale/p1022ds/spl_minimal.c
b/board/freescale/p1022ds/spl_minimal.c
index 8d12fa6..efb2af3 100644
--- a/board/freescale/p1022ds/spl_minimal.c
+++ b/board/freescale/p1022ds/spl_minimal.c
@@ -27,51 +27,6 @@
#include asm/fsl_ddr_sdram.h
-/*
- * Fixed sdram init -- doesn't use serial presence detect.
- */
-void sdram_init(void)
-{
- volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, ddr-cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, ddr-cs0_config);
-#if CONFIG_CHIP_SELECTS_PER_CTRL 1
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, ddr-cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, ddr-cs1_config);
-#endif
- __raw_writel(CONFIG_SYS_DDR_TIMING_3, ddr-timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0, ddr-timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1, ddr-timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2, ddr-timing_cfg_2);
-
- __raw_writel(CONFIG_SYS_DDR_CONTROL_2, ddr-sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1, ddr-sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2, ddr-sdram_mode_2);
-
- __raw_writel(CONFIG_SYS_DDR_INTERVAL, ddr-sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, ddr-sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, ddr-sdram_clk_cntl);
-
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, ddr-timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, ddr-timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, ddr-ddr_zq_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, ddr-ddr_wrlvl_cntl);
-
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL ~SDRAM_CFG_MEM_EN,
- ddr-sdram_cfg);
-
- in_be32(ddr-sdram_cfg);
- udelay(500);
-
- /* Let the controller go */
- out_be32(ddr-sdram_cfg, in_be32(ddr-sdram_cfg) | SDRAM_CFG_MEM_EN);
- in_be32(ddr-sdram_cfg);
-
- set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
-}
-
const static u32 sysclk_tbl[] = {
6000, 7499900, 83332500, 800,
9000, 1000, 12499800, 1200
@@ -83,6 +38,10 @@ void board_init_f(ulong bootflag)
u32 plat_ratio, sys_clk, bus_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+#if defined(CONFIG_SYS_NAND_BR_PRELIM) defined(CONFIG_SYS_NAND_OR_PRELIM)
+ set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
+ set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
+#endif
/* for FPGA */
set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
@@ -98,9 +57,6 @@ void board_init_f(ulong bootflag)
puts(\nNAND boot... );
- /* Initialize the DDR3 */
- sdram_init();
-
/* copy code to RAM and jump to it - this should not return */
Re: [U-Boot] Separately compile Master boot loader
Hi Rajdeep, On Tue, 9 Jul 2013 16:12:14 +0530, Rajdeep Vaghasia rajdeep.vagha...@gmail.com wrote: Hi I am working on one board with an arm11 based cpu, NOR flash and DDR2 SDRAM. When I compile u-boot source code, I get u-boot.bin image generated. This image has primary(second stage) and secondary(third stage) bootloader combined. I have following queries: 1) The question that still eats me everyday is, How can I compile primary(Master) boot loader and secondary boot loader separately? 2) I want to Flash only initial 4kb of code (Master boot loader or second stage). The remaining code I want to keep at another partition in the Flash. How can I achieve this? 3) Is there any separate code available for Master boot loader, which copies the third stage bootloader to SDRAM and then transfers control to that third stage boot loader(u-boot)? I am unable to find a way to do this. Can anyone help me please? Since you do not indicate exactly which target you're building, I'll assume it is one with SPL (what you describe as master or second stage, with third stage being u-boot itself). I don't know of a way to build SPL alone. As for building separate U-Boot and SPL, you'll find them in ELF format in file ./u-boot and ./spl/u-boot-spl. You can then use $(CROSS_COMPILE)objcopy to convert from ELF to .bin. Note that your target may need a specific format different from the pure binary that objcopy can produce. Can you tell us more about your target? Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V0 1/1] Resolve i2c compilation error for non-FDT case
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case.
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function) make[1]: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o]
Error 1 make: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c |9 +
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..262398f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,15 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+PINMUX_FLAG_NONE);
+ }
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
-PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
--
1.7.3.rc2
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Re: [U-Boot] [PATCH 1/2] Revert usb: hub: Parallelize power-cycling of root-hub ports
Hi, This reverts commit 0bf796f7ae22086f0504f3297e9fb4e96aa04161. This commit causes breakage of the EHCI, where on Tegra it is not possible to run usb reset twice as it results in the board hang. Signed-off-by: Marek Vasut ma...@denx.de Cc: Vivek Gautam gautamvivek1...@gmail.com Cc: Stephen Warren swar...@wwwdotorg.org --- common/usb_hub.c | 19 +++ 1 file changed, 7 insertions(+), 12 deletions(-) Please ignore both patches, the problem was resolved by: http://www.mail-archive.com/u-boot@lists.denx.de/msg112944.html Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V0 1/1] Resolve i2c compilation error for non-FDT case
Dear amar_g
On 09/07/13 21:44, amar_g wrote:
Please add prefix at title.
This patch resolves the below mentiond compilation error of i2c driver
typo. - mentiond
for non-FDT case.
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function) make[1]: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o]
Error 1 make: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c |9 +
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..262398f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,15 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
please add blank line here.
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+ PINMUX_FLAG_NONE);
+ }
+}
+
This is for non-fdt case, right?
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
Thanks,
Minkyu Kang.
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Re: [U-Boot] [PATCH V0 1/1] Resolve i2c compilation error for non-FDT case
Dear Minkyu,
Please find my responses below.
Thanks Regards
Amarendra Reddy
On 9 July 2013 18:50, Minkyu Kang mk7.k...@samsung.com wrote:
Dear amar_g
On 09/07/13 21:44, amar_g wrote:
Please add prefix at title.
OK shall add aprefix 'EXYNOS' at title in the next patch.
This patch resolves the below mentiond compilation error of i2c driver
typo. - mentiond
OK shall remove the '.' form for non-FDT case.
for non-FDT case.
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function) make[1]: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o]
Error 1 make: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c |9 +
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..262398f 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,15 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
please add blank line here.
Ok shall add a new line here.
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+ PINMUX_FLAG_NONE);
+ }
+}
+
This is for non-fdt case, right?
Yes, it is for non-fdt case.
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen,
uchar *buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
Thanks,
Minkyu Kang.
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[U-Boot] [PATCH V1 1/1] EXYNOS: Resolve the i2c compilation error for
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function) make[1]: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o]
Error 1 make: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c | 10 ++
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..f1d3d97 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,16 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
+
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+PINMUX_FLAG_NONE);
+ }
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
-PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
--
1.7.3.rc2
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[U-Boot] multi image kernel+ramdisk
Hi, I am trying to boot with a multi image file that was generated with
mkimage. The uboot decompress the file and find the kernel, but is not find
the filesystem. How can I fix the ramdisk address in ram to call bootm in
right way?
- command line used to mkimage: mkimage -A arm -T multi -C gzip -a 0 -e 0
-n 'test multifile' -d vmlinux:ramdisk.gz uMulti
*- Bellow is the log:*
## Booting kernel from Legacy Image at 80007fc0 ...
Image Name: test multifile
Image Type: ARM Linux Multi-File Image (gzip compressed)
Data Size: 14018554 Bytes = 13.4 MiB
Load Address:
Entry Point:
Contents:
Image 0: 3207239 Bytes = 3.1 MiB
Image 1: 10811302 Bytes = 10.3 MiB
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 80007fc0 ...
Image Name: test multifile
Image Type: ARM Linux Multi-File Image (gzip compressed)
Data Size: 14018554 Bytes = 13.4 MiB
Load Address:
Entry Point:
Contents:
Image 0: 3207239 Bytes = 3.1 MiB
Image 1: 10811302 Bytes = 10.3 MiB
Verifying Checksum ... OK
No Linux ARM Ramdisk Image
Ramdisk image is corrupt or invalid
*- Bellow are the environment variables:*
U-Boot# printenv
baudrate=115200
bootargs=console=ttyO0,115200n8
bootargs_defaults=setenv bootargs console=${console} ${optargs}
bootcmd=if mmc rescan ${mmcdev}; then echo SD/MMC found on device
${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};r
un importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run
uenvcmd;fi;if run loaduimagefat; then run mmcboot;elif run loaduima
ge; then run mmcboot;else echo Cound not find ${bootfile} ;fi;else run
nandboot;fi;
bootdelay=3
bootenv=uEnv.txt
bootfile=uImage
bootm=0x 0x80007fc0
console=ttyO0,115200n8
dfu_alt_info=SPL part 0 1;SPL.backup1 part 0 2;SPL.backup2 part 0
3;SPL.backup3 part 0 4;u-boot part 0 5;kernel part 0 7;rootfs part 0 8
ethact=cpsw
ethaddr=00:18:31:e0:9a:d1
fdtaddr=0x80F8
filesize=D5E83A
importbootenv=echo Importing environment from mmc ...; env import -t
$loadaddr $filesize
ip_method=none
kloadaddr=0x80007fc0
loadaddr=0x8020
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}
loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz
loaduimage=ext2load mmc ${mmcdev}:2 ${kloadaddr} /boot/${bootfile}
loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}
mmcargs=run bootargs_defaults;setenv bootargs ${bootargs} root=${mmcroot}
rootfstype=${mmcrootfstype} ip=${ip_method}
mmcboot=echo Booting from mmc ...; run mmcargs; bootm ${kloadaddr}
mmcdev=0
mmcroot=/dev/mmcblk0p2 rw
mmcrootfstype=ext2 rootwait
mtddevname=SPL
mtddevnum=0
mtdids=nand0=omap2-nand.0
mtdparts=mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),128k(u-boot-env),5m(kernel),12441
6k(fs1),124416k(fs2),-(safe_area)
nand_erasesize=2
nand_oobsize=40
nand_writesize=800
nandargs=run bootargs_defaults;setenv bootargs ${bootargs} root=${nandroot}
noinitrd rootfstype=${nandrootfstype} ip=${ip_method}
nandboot=echo Booting from nand ...; run nandargs; nand read.i ${kloadaddr}
${nandsrcaddr} ${nandimgsize}; bootm ${kloadaddr}
nandimgsize=0x100
nandroot=ubi0:rootfs rw ubi.mtd=7,2048 noinitrd
nandrootfstype=ubifs rootwait=1
nandsrcaddr=0x78
netargs=run bootargs_defaults;setenv bootargs ${bootargs} root=/dev/nfs
nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; tftp
${kloadaddr} ${bootfile}; run netargs; bootm ${kloadaddr}
nfsopts=nolock
partition=nand0,0
ramargs=setenv bootargs console=ttyO0,115200n8 root=/dev/ram0 rw
ramdisk_size=65536 initrd=${rdaddr},64M rootfstype=ext2
ramboot=echo Booting from ramdisk ...; run ramargs; bootm 0x8020
ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x8100,64M
ramrootfstype=ramdisk
rdaddr=84207239
rootpath=/export/rootfs
selected_img=1
spiargs=run bootargs_defaults;setenv bootargs ${bootargs}
rootfstype=${spirootfstype} ip=${ip_method}
spiboot=echo Booting from spi ...; run spiargs; sf probe ${spibusno}:0; sf
read ${kloadaddr} ${spisrcaddr} ${spiimgsize}; bootm ${kloadaddr}
spibusno=0
spiimgsize=0x362000
spiroot=/dev/mtdblock4 rw
spirootfstype=jffs2
spisrcaddr=0x8
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial
stdin=serial
stdout=serial
usbnet_devaddr=00:18:31:e0:9a:d1
ver=U-Boot 2012.10 (Dec 16 2012 - 13:54:10)
Environment size: 3358/131068 bytes
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Re: [U-Boot] [PATCH V1 1/1] EXYNOS: Resolve the i2c compilation error for
Hi amar_g,
On Tue, 09 Jul 2013 19:35:40 +0530, amar_g amarendra...@samsung.com
wrote:
This patch resolves the below mentiond compilation error of i2c driver
for non-FDT case
Compilation error:
---8---
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function)
---8---
Please limit info to the error message between 8 above, or better yet,
just mention a summary of the error.
Also: since this is the V1 of a V0, it requires patch history after the
commit message delimiter ('---' line below).
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c | 10 ++
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..f1d3d97 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,16 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
+
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+ PINMUX_FLAG_NONE);
+ }
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
Amicalement,
--
Albert.
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Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that. I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch. So as a simple solution I propose adding a config option to remove these workarounds for boards/silicon that dont need them. Is this sensible or should there be more automatism? regards, Andreas PS. Does anybody have the ARM Core Cortex-A8 (AT400/AT401) errata document to make sure my assumption above holds true? I have rev 20.0 from 13-Apr-10. The three mentioned errata should be fixed in r2p1. snip Two remarks: 1. I would prefer the option to be the other way around, i.e. forcing the inclusion of the workaround when defined rather than when not defined; e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATA If we do that, lots of board configs have to be adapted. People who have custom configs probably wont notice and loose their apropriate errata handling. 2. (if applicable) I would prefer erratum-specific options, e.g. CONFIG_SYS_CORTEXA8_WORK_AROUND_ERRATUM_430973 -- ok, ERRATA will be fine too; what I want is easing the search for errata by number. I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary. So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly? cheers, Andreas ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] multi image kernel+ramdisk
Hi, I am trying to boot with a multi image file that was generated with
mkimage. The uboot decompress the file and find the kernel, but is not find
the filesystem. How can I fix the ramdisk address in ram to call bootm in
right way?
- command line used to mkimage: mkimage -A arm -T multi -C gzip -a 0 -e 0
-n 'test multifile' -d vmlinux:ramdisk.gz uMulti
*- Bellow is the log:*
## Booting kernel from Legacy Image at 80007fc0 ...
Image Name: test multifile
Image Type: ARM Linux Multi-File Image (gzip compressed)
Data Size: 14018554 Bytes = 13.4 MiB
Load Address:
Entry Point:
Contents:
Image 0: 3207239 Bytes = 3.1 MiB
Image 1: 10811302 Bytes = 10.3 MiB
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 80007fc0 ...
Image Name: test multifile
Image Type: ARM Linux Multi-File Image (gzip compressed)
Data Size: 14018554 Bytes = 13.4 MiB
Load Address:
Entry Point:
Contents:
Image 0: 3207239 Bytes = 3.1 MiB
Image 1: 10811302 Bytes = 10.3 MiB
Verifying Checksum ... OK
No Linux ARM Ramdisk Image
Ramdisk image is corrupt or invalid
*- Bellow are the environment variables:*
U-Boot# printenv
baudrate=115200
bootargs=console=ttyO0,115200n8
bootargs_defaults=setenv bootargs console=${console} ${optargs}
bootcmd=if mmc rescan ${mmcdev}; then echo SD/MMC found on device
${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};r
un importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run
uenvcmd;fi;if run loaduimagefat; then run mmcboot;elif run loaduima
ge; then run mmcboot;else echo Cound not find ${bootfile} ;fi;else run
nandboot;fi;
bootdelay=3
bootenv=uEnv.txt
bootfile=uImage
bootm=0x 0x80007fc0
console=ttyO0,115200n8
dfu_alt_info=SPL part 0 1;SPL.backup1 part 0 2;SPL.backup2 part 0
3;SPL.backup3 part 0 4;u-boot part 0 5;kernel part 0 7;rootfs part 0 8
ethact=cpsw
ethaddr=00:18:31:e0:9a:d1
fdtaddr=0x80F8
filesize=D5E83A
importbootenv=echo Importing environment from mmc ...; env import -t
$loadaddr $filesize
ip_method=none
kloadaddr=0x80007fc0
loadaddr=0x8020
loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}
loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz
loaduimage=ext2load mmc ${mmcdev}:2 ${kloadaddr} /boot/${bootfile}
loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}
mmcargs=run bootargs_defaults;setenv bootargs ${bootargs} root=${mmcroot}
rootfstype=${mmcrootfstype} ip=${ip_method}
mmcboot=echo Booting from mmc ...; run mmcargs; bootm ${kloadaddr}
mmcdev=0
mmcroot=/dev/mmcblk0p2 rw
mmcrootfstype=ext2 rootwait
mtddevname=SPL
mtddevnum=0
mtdids=nand0=omap2-nand.0
mtdparts=mtdparts=omap2-nand.0:128k(SPL),128k(SPL.backup1),128k(SPL.backup2),128k(SPL.backup3),1920k(u-boot),128k(u-boot-env),5m(kernel),12441
6k(fs1),124416k(fs2),-(safe_area)
nand_erasesize=2
nand_oobsize=40
nand_writesize=800
nandargs=run bootargs_defaults;setenv bootargs ${bootargs} root=${nandroot}
noinitrd rootfstype=${nandrootfstype} ip=${ip_method}
nandboot=echo Booting from nand ...; run nandargs; nand read.i ${kloadaddr}
${nandsrcaddr} ${nandimgsize}; bootm ${kloadaddr}
nandimgsize=0x100
nandroot=ubi0:rootfs rw ubi.mtd=7,2048 noinitrd
nandrootfstype=ubifs rootwait=1
nandsrcaddr=0x78
netargs=run bootargs_defaults;setenv bootargs ${bootargs} root=/dev/nfs
nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp
netboot=echo Booting from network ...; setenv autoload no; dhcp; tftp
${kloadaddr} ${bootfile}; run netargs; bootm ${kloadaddr}
nfsopts=nolock
partition=nand0,0
ramargs=setenv bootargs console=ttyO0,115200n8 root=/dev/ram0 rw
ramdisk_size=65536 initrd=${rdaddr},64M rootfstype=ext2
ramboot=echo Booting from ramdisk ...; run ramargs; bootm 0x8020
ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=0x8100,64M
ramrootfstype=ramdisk
rdaddr=84207239
rootpath=/export/rootfs
selected_img=1
spiargs=run bootargs_defaults;setenv bootargs ${bootargs}
rootfstype=${spirootfstype} ip=${ip_method}
spiboot=echo Booting from spi ...; run spiargs; sf probe ${spibusno}:0; sf
read ${kloadaddr} ${spisrcaddr} ${spiimgsize}; bootm ${kloadaddr}
spibusno=0
spiimgsize=0x362000
spiroot=/dev/mtdblock4 rw
spirootfstype=jffs2
spisrcaddr=0x8
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off
stderr=serial
stdin=serial
stdout=serial
usbnet_devaddr=00:18:31:e0:9a:d1
ver=U-Boot 2012.10 (Dec 16 2012 - 13:54:10)
Environment size: 3358/131068 bytes
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Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hi Andreas, On 07/09/2013 05:01 PM, Andreas Naumann wrote: It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that. I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch. Ok, understand. snip I join Albert's suggestion. Another solution could be to read the silicon revision and enable erratum workarounds on that information. It would be a step towards single binary. So I'd rather do that, but can we map the ARM revision e.g. r2p1 to the TI die versions ES1.0, 1.1 and so on? Or can the ARM revision be read directly? You should use the ARM revisions. They are available, but dunno how: ---8--- ~ cat /proc/cpuinfo Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS: 512.57 Features: swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part: 0xc08 CPU revision: 2 ---8--- AFAIK is CPU variant 'r3' and CPU revision 'p2' for this cpuinfo. Regards Andreas Bießmann ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] ARM: omap3: Add option to disable errata workarounds.
Hello, It seems that all three ARM errata workarounds done in omap3 board-init (#454179 #430973 #621766) are solved/not longer needed e.g. in the AM/DM37xx chips. Other people have noticed this: http://e2e.ti.com/support/arm/sitara_arm/f/791/t/254742.aspx When still applying them (especcially #430973), lots of segmentations faults and other strange stuff begin to appear. I read your link the other way round. If the #430973 errata fix is _not_ applied to r3p2 it gives a lot of segfaults. Unfortunately the thread has noc more information on that. #430973 is still needed on latest Cortex-A8 silicon of DM3730 according to my testing; this is in contradiction to what TI and ARM claim I dont know what bootloader the guy used, but he states that he needs to enable the errata fix in the kernel for the segfaults to disappear. I the guy used u-boot 2012.10 and linux 3.7 :) found exactly the same: Initially I had no errata fixes configured for the kernel, only when I added them the segfaults disappeared. However they also disappear if I remove the workarounds from kernel as well as u-boot, hence this patch. interesting; I did not consider this dependency between u-boot and kernel here; will try it regards, p. -- Peter Meerwald +43-664-218 (mobile) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] gpio: tca642x: Add the tca642x gpio expander driver
Nishanth
Thanks for the feedback
On 07/08/2013 04:27 PM, Nishanth Menon wrote:
On 07/08/2013 03:53 PM, Dan Murphy wrote:
Add the tca642x gpio expander driver
http://www.ti.com/sitesearch/docs/universalsearch.tsp?searchTerm=tca642linkId=1
I think there are just TCA6424 ?
giving a link to the product helps I suppose.
Done. Next patchset
Signed-off-by: Dan Murphy dmur...@ti.com
---
drivers/gpio/Makefile |1 +
drivers/gpio/tca642x.c | 312
include/tca642x.h | 64 ++
3 files changed, 377 insertions(+)
create mode 100644 drivers/gpio/tca642x.c
create mode 100644 include/tca642x.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f77c1ec..7e74dfe 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_BCM2835_GPIO)+= bcm2835_gpio.o
COBJS-$(CONFIG_S3C2440_GPIO)+= s3c2440_gpio.o
COBJS-$(CONFIG_XILINX_GPIO)+= xilinx_gpio.o
COBJS-$(CONFIG_ADI_GPIO2)+= adi_gpio2.o
+COBJS-$(CONFIG_TCA642X)+= tca642x.o
COBJS:= $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
new file mode 100644
index 000..740714d
--- /dev/null
+++ b/drivers/gpio/tca642x.c
@@ -0,0 +1,312 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * Derived work from the pca953x.c driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include i2c.h
+#include tca642x.h
+
+/* tca642x register address definitions */
+struct tca642x_bank_info tca642x_banks[] = {
+{0x00, 0x04, 0x08, 0x0c},
+{0x01, 0x05, 0x09, 0x0d},
+{0x02, 0x06, 0x0a, 0x0e},
could we use explicit map of the struct params? helps any future
expansion.
Not sure what you are looking for here. These are the register
addresses within the chip.
+};
+
+/*
+ * Modify masked bits in register
+ */
+static int tca642x_reg_write(uint8_t chip, uint addr, uint mask,
uint data)
+{
+uint16_t valw;
why not use u8 instead? same for mask and data?
Doh. That was carried over from the derivation work. Done. Next patchset
+int org_bus_num;
+int ret;
+
+org_bus_num = i2c_get_bus_num();
+i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+
+if (i2c_read(chip, addr, 1, (u8 *)valw, 1)) {
+printf(Could not read before writing\n);
+ret = -1;
+goto error;
+}
+valw = ~mask;
data = mask ?
Well in this case the mask is not being passed in. The bit to flip is
being passed and then the actual mask
is created here.
This code should be fine unless others object as well.
+valw |= data;
+
+ret = i2c_write(chip, addr, 1, (u8 *)valw, 1);
+
+error:
+i2c_set_bus_num(org_bus_num);
+return ret;
+
extra eol?
Done. Next patchset
+}
+
+static int tca642x_reg_read(uint8_t chip, uint addr, uint *data)
same here? addr is u8, data is u8 *?
Done. Next patchset
+{
+uint16_t valw;
val as u8?
Done. Next patchset
+int org_bus_num;
+int ret = 0;
+
+org_bus_num = i2c_get_bus_num();
+i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+if (i2c_read(chip, addr, 1, (u8 *)valw, 1)) {
+ret = -1;
+goto error;
+}
+
+*data = (int)valw;
+
+error:
+i2c_set_bus_num(org_bus_num);
+return ret;
+}
[...]
--
--
Dan Murphy
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Re: [U-Boot] [PATCH 2/2] omap5: Configure the tca6424 gpio expander
On 07/08/2013 04:19 PM, Nishanth Menon wrote:
$subject
Don't know where it went it was in my patch set I submitted.
omap5: uevm
On 07/08/2013 03:54 PM, Dan Murphy wrote:
Configure the tca6424 gpio expander
This allows use of the debug and tri color LEDs.
As well as HDMI PEO signal.
we use HDMI in u-boot?
Removed.
Signed-off-by: Dan Murphy dmur...@ti.com
---
board/ti/omap5_uevm/evm.c | 12
board/ti/omap5_uevm/mux_data.h |2 ++
include/configs/omap5_uevm.h |5 +
3 files changed, 19 insertions(+)
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 90046e8..ee96ae1 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -26,6 +26,7 @@
#include palmas.h
#include asm/arch/sys_proto.h
#include asm/arch/mmc_host_def.h
+#include tca642x.h
#include mux_data.h
@@ -35,6 +36,15 @@ const struct omap_sysinfo sysinfo = {
Board: OMAP5430 EVM\n
};
+/* Initial states for the GPIO expander
Doc comment style.
Will do.
Probably need a patch that fixes all the other interfaces as well.
+ * input reg, output reg, polarity reg, configuration reg
+ */
+struct tca642x_bank_info tca642x_init[] = {
+{0x00, 0x04, 0x00, 0x80},
+{0x00, 0x00, 0x00, 0xff},
+{0x00, 0x00, 0x00, 0x40},
could you be explicit and use .input_reg = etc?
btw, why should board know about input_reg, output_reg polarity_reg?
is'nt that the job of the driver?
These are the default power up values for the uEVM.
I can add .input_reg = blah. Just thought the bank_info structure was
good enough.
+};
+
/**
* @brief board_init
*
@@ -46,6 +56,8 @@ int board_init(void)
gd-bd-bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd-bd-bi_boot_params = (0x8000 + 0x100); /* boot param
addr */
+tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR,
tca642x_init);
+
return 0;
}
diff --git a/board/ti/omap5_uevm/mux_data.h
b/board/ti/omap5_uevm/mux_data.h
index a82795d..7e6415e 100644
--- a/board/ti/omap5_uevm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -56,6 +56,8 @@ const struct pad_conf_entry
core_padconf_array_essential[] = {
{USBD0_HS_DP, (IEN | M0)},/* USBD0_HS_DP */
{USBD0_HS_DM, (IEN | M0)},/* USBD0_HS_DM */
{USBD0_SS_RX, (IEN | M0)},/* USBD0_SS_RX */
+{I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+{I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
};
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 46dacc2..bee1278 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -53,6 +53,11 @@
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+#define CONFIG_TCA642X
+#define CONFIG_CMD_TCA642X
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+
#define CONFIG_SYS_PROMPTOMAP5432 uEVM #
#define CONSOLEDEVttyO2
--
--
Dan Murphy
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Re: [U-Boot] [PATCH 1/2] gpio: tca642x: Add the tca642x gpio expander driver
On 07/09/2013 11:17 AM, Dan Murphy wrote:
On 07/08/2013 04:27 PM, Nishanth Menon wrote:
On 07/08/2013 03:53 PM, Dan Murphy wrote:
[...]
+/* tca642x register address definitions */
+struct tca642x_bank_info tca642x_banks[] = {
+{0x00, 0x04, 0x08, 0x0c},
+{0x01, 0x05, 0x09, 0x0d},
+{0x02, 0x06, 0x0a, 0x0e},
could we use explicit map of the struct params? helps any future
expansion.
Not sure what you are looking for here. These are the register
addresses within the chip.
something like
{.input_reg = 0x00, .polarity_reg = 0x04,
It helps readability and future modification to bank_info structure.
[..]
+int org_bus_num;
+int ret;
+
+org_bus_num = i2c_get_bus_num();
+i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+
+if (i2c_read(chip, addr, 1, (u8 *)valw, 1)) {
+printf(Could not read before writing\n);
+ret = -1;
+goto error;
+}
+valw = ~mask;
data = mask ?
Well in this case the mask is not being passed in. The bit to flip is
being passed and then the actual mask
is created here.
reg_setbits? instead then? following the standard api convention - maybe
make this as a i2c generic api?
--
Regards,
Nishanth Menon
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Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es) (board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet. Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
--
Tom
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[U-Boot] [UBOOT] [PATCH V2 2/2] gpio: omap5-uevm: Configure the tca6424 gpio expander
Configure the tca6424 gpio expander
This allows use of the debug and tri color LEDs.
Signed-off-by: Dan Murphy dmur...@ti.com
---
v2 - Updated per comments- http://patchwork.ozlabs.org/patch/257603
board/ti/omap5_uevm/evm.c | 21 +
board/ti/omap5_uevm/mux_data.h |2 ++
include/configs/omap5_uevm.h |5 +
3 files changed, 28 insertions(+)
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
index 90046e8..0e9a559 100644
--- a/board/ti/omap5_uevm/evm.c
+++ b/board/ti/omap5_uevm/evm.c
@@ -26,6 +26,7 @@
#include palmas.h
#include asm/arch/sys_proto.h
#include asm/arch/mmc_host_def.h
+#include tca642x.h
#include mux_data.h
@@ -35,6 +36,24 @@ const struct omap_sysinfo sysinfo = {
Board: OMAP5430 EVM\n
};
+/* @brief tca642x_init - Initial states for the GPIO expander
+ * input reg, output reg, polarity reg, configuration reg
+ */
+struct tca642x_bank_info tca642x_init[] = {
+ { .input_reg = 0x00,
+ .output_reg = 0x04,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x80 },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0xff },
+ { .input_reg = 0x00,
+ .output_reg = 0x00,
+ .polarity_reg = 0x00,
+ .configuration_reg = 0x40 },
+};
+
/**
* @brief board_init
*
@@ -46,6 +65,8 @@ int board_init(void)
gd-bd-bi_arch_number = MACH_TYPE_OMAP5_SEVM;
gd-bd-bi_boot_params = (0x8000 + 0x100); /* boot param addr */
+ tca642x_set_inital_state(CONFIG_SYS_I2C_TCA642X_ADDR, tca642x_init);
+
return 0;
}
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
index a82795d..7e6415e 100644
--- a/board/ti/omap5_uevm/mux_data.h
+++ b/board/ti/omap5_uevm/mux_data.h
@@ -56,6 +56,8 @@ const struct pad_conf_entry core_padconf_array_essential[] = {
{USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
{USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
{USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
+ {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
+ {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
};
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
index 46dacc2..bee1278 100644
--- a/include/configs/omap5_uevm.h
+++ b/include/configs/omap5_uevm.h
@@ -53,6 +53,11 @@
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART
+#define CONFIG_TCA642X
+#define CONFIG_CMD_TCA642X
+#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4
+#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22
+
#define CONFIG_SYS_PROMPT OMAP5432 uEVM #
#define CONSOLEDEV ttyO2
--
1.7.9.5
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[U-Boot] [UBOOT] [PATCH V2 1/2] gpio: tca642x: Add the tca642x gpio expander driver
Add the tca642x gpio expander driver
Datasheet:
http://www.ti.com/product/tca6424a
Signed-off-by: Dan Murphy dmur...@ti.com
---
v2 - Updated per comments- http://patchwork.ozlabs.org/patch/257602/
drivers/gpio/Makefile |1 +
drivers/gpio/tca642x.c | 321
include/tca642x.h | 65 ++
3 files changed, 387 insertions(+)
create mode 100644 drivers/gpio/tca642x.c
create mode 100644 include/tca642x.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f77c1ec..7e74dfe 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -49,6 +49,7 @@ COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o
COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o
COBJS-$(CONFIG_XILINX_GPIO)+= xilinx_gpio.o
COBJS-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
+COBJS-$(CONFIG_TCA642X)+= tca642x.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
diff --git a/drivers/gpio/tca642x.c b/drivers/gpio/tca642x.c
new file mode 100644
index 000..03bbfb2
--- /dev/null
+++ b/drivers/gpio/tca642x.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright 2013 Texas Instruments, Inc.
+ * Author: Dan Murphy dmur...@ti.com
+ *
+ * Derived work from the pca953x.c driver
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include i2c.h
+#include tca642x.h
+
+/* tca642x register address definitions */
+struct tca642x_bank_info tca642x_regs[] = {
+ { .input_reg = 0x00,
+ .output_reg = 0x04,
+ .polarity_reg = 0x08,
+ .configuration_reg = 0x0c },
+ { .input_reg = 0x01,
+ .output_reg = 0x05,
+ .polarity_reg = 0x09,
+ .configuration_reg = 0x0d },
+ { .input_reg = 0x02,
+ .output_reg = 0x06,
+ .polarity_reg = 0x0a,
+ .configuration_reg = 0x0e },
+};
+
+/*
+ * Modify masked bits in register
+ */
+static int tca642x_reg_write(uchar chip, uint8_t addr,
+ uint8_t reg_bit, uint8_t data)
+{
+ uint8_t valw;
+ int org_bus_num;
+ int ret;
+
+ org_bus_num = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+
+ if (i2c_read(chip, addr, 1, (uint8_t *)valw, 1)) {
+ printf(Could not read before writing\n);
+ ret = -1;
+ goto error;
+ }
+ valw = ~reg_bit;
+ valw |= data;
+
+ ret = i2c_write(chip, addr, 1, (u8 *)valw, 1);
+
+error:
+ i2c_set_bus_num(org_bus_num);
+ return ret;
+}
+
+static int tca642x_reg_read(uchar chip, uint8_t addr, uint8_t *data)
+{
+ uint8_t valw;
+ int org_bus_num;
+ int ret = 0;
+
+ org_bus_num = i2c_get_bus_num();
+ i2c_set_bus_num(CONFIG_SYS_I2C_TCA642X_BUS_NUM);
+ if (i2c_read(chip, addr, 1, (u8 *)valw, 1)) {
+ ret = -1;
+ goto error;
+ }
+
+ *data = valw;
+
+error:
+ i2c_set_bus_num(org_bus_num);
+ return ret;
+}
+
+/*
+ * Set output value of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = low, 1 = high
+ */
+int tca642x_set_val(uchar chip, uint8_t gpio_bank, uint8_t reg_bit, uint8_t
data)
+{
+ uint8_t out_reg = tca642x_regs[gpio_bank].output_reg;
+
+ return tca642x_reg_write(chip, out_reg, reg_bit, data);
+}
+
+/*
+ * Set read polarity of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = read pin value, 1 = read inverted pin value
+ */
+int tca642x_set_pol(uchar chip, uint8_t gpio_bank, uint8_t reg_bit, uint8_t
data)
+{
+ uint8_t pol_reg = tca642x_regs[gpio_bank].polarity_reg;
+
+ return tca642x_reg_write(chip, pol_reg, reg_bit, data);
+}
+
+/*
+ * Set direction of IO pins in 'reg_bit' to corresponding value in 'data'
+ * 0 = output, 1 = input
+ */
+int tca642x_set_dir(uchar chip, uint8_t gpio_bank, uint8_t reg_bit, uint8_t
data)
+{
+ uint8_t config_reg = tca642x_regs[gpio_bank].configuration_reg;
+
+ return tca642x_reg_write(chip, config_reg, reg_bit, data);
+}
+
+/*
+ * Read current logic level of all IO pins
+ */
+int tca642x_get_val(uchar chip, uint8_t gpio_bank)
+{
+ uint8_t val;
+ uint8_t in_reg = tca642x_regs[gpio_bank].input_reg;
+
+ if (tca642x_reg_read(chip, in_reg, val) 0)
+ return -1;
+
+ return (int)val;
+}
+
+/*
+ * Set the inital register states for the tca642x gpio expander
+ */
+int
Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es) (board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet. Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should be able
to try bootz with appeneded dtb on another ARM board.
I've got a fix locally now, and I'm working on cleaning it up further.
The problem is that BOOTM_STATE_FINDOTHER would never work since we
aren't the right image types, so passed ramdisk and/or dtb didn't
work. Another problem was that bootz was never consuming 'bootz', but
this was OK before. I'll post a patch shortly.
My biggest worry right now is, what might show up broken next? Anyone
out there easily able to boot a netbsd kernel or something?
--
Tom
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Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
On Tue, Jul 9, 2013 at 2:00 PM, Simon Glass s...@chromium.org wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es) (board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet. Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we know?
If so then perhaps we are close.
Close.. It's the 'non appended dtb case'...
bootz ${loadaddr} - ${fdt_addr}
It's almost as if bootz doesn't have the location of the dtb binary in memory...
I will see if I can get a Beaglebone today or failing that I should be able
to try bootz with appeneded dtb on another ARM board.
Regards,
--
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Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es) (board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet. Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should be able
to try bootz with appeneded dtb on another ARM board.
Regards,
Simon
--
Tom
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[U-Boot] [PATCH 2/5] am335x_evm: Add am335x_boneblack variant
The BeagleBone Black differs from the other AM335x boards in a few significant ways, so it makes sense to create a custom configuration for it. In particular, it uses eMMC instead of NAND flash. We can use the eMMC boot partition to store the environment, since it isn't used for anything else. Signed-off-by: Justin Waters justin.wat...@timesys.com --- boards.cfg |1 + include/configs/am335x_evm.h |7 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/boards.cfg b/boards.cfg index c0c4282..7dea9e8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -249,6 +249,7 @@ am335x_evm_uart3 arm armv7 am335x ti am335x_evm_uart4 arm armv7 am335x ti am33xx am335x_evm:SERIAL5,CONS_INDEX=5 am335x_evm_uart5 arm armv7 am335x ti am33xx am335x_evm:SERIAL6,CONS_INDEX=6 am335x_evm_usbsplarm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,SPL_USBETH_SUPPORT +am335x_boneblack arm armv7 am335x ti am33xx am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT,NO_NAND ti814x_evm arm armv7 ti814x ti am33xx pcm051 arm armv7 pcm051 phytec am33xx pcm051 sama5d3xek_mmc arm armv7 sama5d3xek atmel at91sama5d3xek:SAMA5D3,SYS_USE_MMC diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 7bcfe2e..5947f5a 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -487,7 +487,12 @@ # define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED # define CONFIG_ENV_OFFSET (892 10) /* 892 KiB in */ # define CONFIG_ENV_SECT_SIZE (4 10) /* 4 KB sectors */ -#endif /* SPI support */ +#elif defined(CONFIG_EMMC_BOOT) +# undef CONFIG_ENV_IS_NOWHERE +# define CONFIG_ENV_IS_IN_MMC +# define CONFIG_SYS_MMC_ENV_DEV1 +# define CONFIG_SYS_MMC_ENV_PART 2 +#endif /* Unsupported features */ #undef CONFIG_USE_IRQ -- 1.7.9.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/5] am335x_evm: Make NAND support modular
Give the user the ability to disable NAND support by defining
CONFIG_NO_NAND. This will allow custom hardware to easily support
this configuration.
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
include/configs/am335x_evm.h | 55 --
1 file changed, 37 insertions(+), 18 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index c5a6d4b..7bcfe2e 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -42,12 +42,39 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
+#ifdef CONFIG_NO_NAND
+#undef CONFIG_NAND
+#else
+#define CONFIG_NAND
+#endif
+
/* commands to include */
#include config_cmd_default.h
#define CONFIG_CMD_ASKENV
#define CONFIG_VERSION_VARIABLE
+#ifdef CONFIG_NAND
+#define NANDARGS \
+ mtdids= MTDIDS_DEFAULT \0 \
+ mtdparts= MTDPARTS_DEFAULT \0 \
+ nandargs=setenv bootargs console=${console} \
+ ${optargs} \
+ root=${nandroot} \
+ rootfstype=${nandrootfstype}\0 \
+ dfu_alt_info_nand= DFU_ALT_INFO_NAND \0 \
+ nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0 \
+ nandrootfstype=ubifs rootwait=1\0 \
+ nandsrcaddr=0x28\0 \
+ nandboot=echo Booting from nand ...; \
+ run nandargs; \
+ nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; \
+ bootm ${loadaddr}\0 \
+ nandimgsize=0x50\0
+#else
+#define NANDARGS
+#endif
+
/* set to negative value for no autoboot */
#define CONFIG_BOOTDELAY 1
#define CONFIG_ENV_VARS_UBOOT_CONFIG
@@ -63,19 +90,12 @@
fdtfile=undefined\0 \
console=ttyO0,115200n8\0 \
optargs=\0 \
- mtdids= MTDIDS_DEFAULT \0 \
- mtdparts= MTDPARTS_DEFAULT \0 \
dfu_alt_info_mmc= DFU_ALT_INFO_MMC \0 \
dfu_alt_info_emmc=rawemmc mmc 0 3751936\0 \
- dfu_alt_info_nand= DFU_ALT_INFO_NAND \0 \
mmcdev=0\0 \
mmcroot=/dev/mmcblk0p2 ro\0 \
mmcrootfstype=ext4 rootwait\0 \
bootpart=0:2\0 \
- nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0 \
- nandrootfstype=ubifs rootwait=1\0 \
- nandsrcaddr=0x28\0 \
- nandimgsize=0x50\0 \
rootpath=/export/rootfs\0 \
nfsopts=nolock\0 \
static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname} \
@@ -86,10 +106,6 @@
${optargs} \
root=${mmcroot} \
rootfstype=${mmcrootfstype}\0 \
- nandargs=setenv bootargs console=${console} \
- ${optargs} \
- root=${nandroot} \
- rootfstype=${nandrootfstype}\0 \
spiroot=/dev/mtdblock4 rw\0 \
spirootfstype=jffs2\0 \
spisrcaddr=0xe\0 \
@@ -118,10 +134,6 @@
mmcboot=echo Booting from mmc ...; \
run mmcargs; \
bootm ${loadaddr} - ${fdtaddr}\0 \
- nandboot=echo Booting from nand ...; \
- run nandargs; \
- nand read ${loadaddr} ${nandsrcaddr} ${nandimgsize}; \
- bootm ${loadaddr}\0 \
spiboot=echo Booting from spi ...; \
run spiargs; \
sf probe ${spibusno}:0; \
@@ -147,7 +159,8 @@
if test $board_name = A335X_SK; then \
setenv fdtfile am335x-evmsk.dtb; fi; \
if test $fdtfile = undefined; then \
- echo WARNING: Could not determine device tree to use;
fi; \0
+ echo WARNING: Could not determine device tree to use;
fi; \0 \
+ NANDARGS
#endif
#define CONFIG_BOOTCOMMAND \
@@ -231,7 +244,6 @@
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_DFU_MMC
-#define CONFIG_DFU_NAND
#define CONFIG_CMD_DFU
#define DFU_ALT_INFO_MMC \
boot part 0 1; \
@@ -241,6 +253,8 @@
u-boot.img.raw mmc 300 3C0; \
u-boot.img fat 0 1; \
uEnv.txt fat 0 1
+#ifdef CONFIG_NAND
+#define CONFIG_DFU_NAND
#define DFU_ALT_INFO_NAND \
SPL part 0 1; \
SPL.backup1 part 0 2; \
@@ -249,6 +263,7 @@
u-boot part 0 5; \
kernel part 0 7; \
rootfs part 0 8
+#endif
/* Physical Memory Map */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
@@ -337,9 +352,11 @@
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */
/* nand */
+#ifdef CONFIG_NAND
#define CONFIG_CMD_SPL_NAND_OFS0x24 /* end of
u-boot */
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS0x28
#define CONFIG_CMD_SPL_WRITE_SIZE 0x1000
+#endif
/* spl export command */
#define CONFIG_CMD_SPL
@@ -369,6 +386,8 @@
#define CONFIG_SPL_LDSCRIPT$(CPUDIR)/am33xx/u-boot-spl.lds
#define CONFIG_SPL_BOARD_INIT
+
+#ifdef CONFIG_NAND
#define CONFIG_SPL_NAND_AM33XX_BCH
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
@@
[U-Boot] [PATCH 4/5] am335x_evm: Rework bootcmd to handle two MMC devs
The BeagleBone Black can boot from either the MMC card
or eMMC chip on board. We should try both interfaces.
This modification also allows a graceful fallback if
a device exists but boot images are not present on it.
Signed-off-by: Justin Waters justin.wat...@timesys.com
---
include/configs/am335x_evm.h | 42 ++
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h
index e33d0ea..0e3db27 100644
--- a/include/configs/am335x_evm.h
+++ b/include/configs/am335x_evm.h
@@ -134,9 +134,22 @@
loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0 \
loaduimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0 \
loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0 \
- mmcboot=echo Booting from mmc ...; \
- run mmcargs; \
- bootm ${loadaddr} - ${fdtaddr}\0 \
+ mmcboot=mmc dev ${mmcdev}; \
+ if mmc rescan; then \
+ echo SD/MMC found on device ${mmcdev}; \
+ if run loadbootenv; then \
+ echo Loaded environment from ${bootenv}; \
+ run importbootenv; \
+ fi; \
+ if test -n $uenvcmd; then \
+ echo Running uenvcmd ...; \
+ run uenvcmd; \
+ fi; \
+ if run loaduimage; then \
+ run mmcargs; \
+ bootm ${loadaddr} - ${fdtaddr}; \
+ fi; \
+ fi;\0 \
spiboot=echo Booting from spi ...; \
run spiargs; \
sf probe ${spibusno}:0; \
@@ -168,23 +181,12 @@
#define CONFIG_BOOTCOMMAND \
run findfdt; \
- mmc dev ${mmcdev}; if mmc rescan; then \
- echo SD/MMC found on device ${mmcdev}; \
- if run loadbootenv; then \
- echo Loaded environment from ${bootenv}; \
- run importbootenv; \
- fi; \
- if test -n $uenvcmd; then \
- echo Running uenvcmd ...; \
- run uenvcmd; \
- fi; \
- if run loaduimage; then \
- run loadfdt; \
- run mmcboot; \
- fi; \
- else \
- run nandboot; \
- fi; \
+ run mmcboot; \
+ setenv mmcdev 1; \
+ setenv bootpart 1:2; \
+ setenv mmcroot /dev/mmcblk1p2 ro; \
+ run mmcboot; \
+ run nandboot;
/* Clock Defines */
#define V_OSCK 2400 /* Clock output from T2 */
--
1.7.9.6
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[U-Boot] [PATCH 0/5] Enhance support for BeagleBone Black
There are a number of differences between the BeagleBone Black and other AM335x boards that require some modification of the default AM335x EVM configuration. In particular, it lacks NAND flash, has multiple MMC interfaces, and can store its environment in an unused eMMC partition. The following patch set improves the out-of-box experience on the BeagleBone Black without impacting the existing AM335x boards. Justin Waters (5): am335x_evm: Make NAND support modular am335x_evm: Add am335x_boneblack variant am335x_evm: Add command line editing am335x_evm: Rework bootcmd to handle two MMC devs Add additional MLO images to .gitignore .gitignore |2 +- boards.cfg |1 + include/configs/am335x_evm.h | 107 +++--- 3 files changed, 70 insertions(+), 40 deletions(-) -- 1.7.9.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/5] am335x_evm: Add command line editing
Many modern U-Boot ports enable command line editing and a history buffer. The am335x_evm configuration is fairly comprehensive as it is, so a few extra kb should not be noticable, and it adds a very convenient feature. Signed-off-by: Justin Waters justin.wat...@timesys.com --- include/configs/am335x_evm.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 5947f5a..e33d0ea 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -37,6 +37,9 @@ #define CONFIG_OF_LIBFDT #define CONFIG_CMD_BOOTZ #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_AUTO_COMPLETE #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG -- 1.7.9.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 5/5] Add additional MLO images to .gitignore
This rule catches images such as MLO.byteswap Signed-off-by: Justin Waters justin.wat...@timesys.com --- .gitignore |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 771b860..d1282e7 100644 --- a/.gitignore +++ b/.gitignore @@ -24,7 +24,7 @@ # Top-level generic files # -/MLO +/MLO* /SPL /System.map /u-boot -- 1.7.9.6 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] cmd_bootm.c: Make bootz consume 'bootz' from argv, decrement argc
Like 'bootm', 'bootz' needs to consume 'bootz' so that the rest of the
state functions will work.
Signed-off-by: Tom Rini tr...@ti.com
---
common/cmd_bootm.c | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index d0ad80f..3a899bc 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -1763,12 +1763,12 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int
argc,
images, 1);
/* Setup Linux kernel zImage entry point */
- if (argc 2) {
+ if (!argc) {
images-ep = load_addr;
debug(* kernel: default image load address = 0x%08lx\n,
load_addr);
} else {
- images-ep = simple_strtoul(argv[1], NULL, 16);
+ images-ep = simple_strtoul(argv[0], NULL, 16);
debug(* kernel: cmdline image address = 0x%08lx\n,
images-ep);
}
@@ -1779,16 +1779,24 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int
argc,
lmb_reserve(images-lmb, images-ep, zi_end - zi_start);
- ret = do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_FINDOTHER,
- images, 1);
+ if (bootm_find_ramdisk(flag, argc, argv))
+ return 1;
- return ret;
+#if defined(CONFIG_OF_LIBFDT)
+ if (bootm_find_fdt(flag, argc, argv))
+ return 1;
+#endif
+
+ return 0;
}
int do_bootz(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret;
+ /* Consume 'bootz' */
+ argc--; argv++;
+
if (bootz_start(cmdtp, flag, argc, argv, images))
return 1;
--
1.7.9.5
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[U-Boot] [PATCH 2/2] cmd_bootm.c: Make bootz handle BOOTM_STATE_FINDOTHER itself
As a zImage does not have a U-Boot header, we cannot really do what
BOOTM_STATE_FINDOTHER does, exactly. Break the ramdisk/fdt portions of
bootm_find_other into bootm_find_ramdisk/fdt which can be called in both
cases.
Signed-off-by: Tom Rini tr...@ti.com
---
common/cmd_bootm.c | 56 +---
1 file changed, 40 insertions(+), 16 deletions(-)
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 3a899bc..1498380 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -309,33 +309,53 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int
argc,
return 0;
}
-static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
+static int bootm_find_ramdisk(int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ /* find ramdisk */
+ ret = boot_get_ramdisk(argc, argv, images, IH_INITRD_ARCH,
+ images.rd_start, images.rd_end);
+ if (ret) {
+ puts(Ramdisk image is corrupt or invalid\n);
+ return 1;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_find_fdt(int flag, int argc, char * const argv[])
{
int ret;
+ /* find flattened device tree */
+ ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, images,
+ images.ft_addr, images.ft_len);
+ if (ret) {
+ puts(Could not find a valid device tree\n);
+ return 1;
+ }
+
+ set_working_fdt_addr(images.ft_addr);
+
+ return 0;
+}
+#endif
+
+static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
if (((images.os.type == IH_TYPE_KERNEL) ||
(images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
(images.os.type == IH_TYPE_MULTI))
(images.os.os == IH_OS_LINUX)) {
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, images, IH_INITRD_ARCH,
- images.rd_start, images.rd_end);
- if (ret) {
- puts(Ramdisk image is corrupt or invalid\n);
+ if (bootm_find_ramdisk(flag, argc, argv))
return 1;
- }
#if defined(CONFIG_OF_LIBFDT)
- /* find flattened device tree */
- ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, images,
- images.ft_addr, images.ft_len);
- if (ret) {
- puts(Could not find a valid device tree\n);
+ if (bootm_find_fdt(flag, argc, argv))
return 1;
- }
-
- set_working_fdt_addr(images.ft_addr);
#endif
}
@@ -1779,6 +1799,10 @@ static int bootz_start(cmd_tbl_t *cmdtp, int flag, int
argc,
lmb_reserve(images-lmb, images-ep, zi_end - zi_start);
+ /*
+* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
+* have a header that provide this informaiton.
+*/
if (bootm_find_ramdisk(flag, argc, argv))
return 1;
--
1.7.9.5
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Re: [U-Boot] [PATCH 1/5] am335x_evm: Make NAND support modular
On Tue, Jul 09, 2013 at 03:00:06PM -0400, Justin Waters wrote: Give the user the ability to disable NAND support by defining CONFIG_NO_NAND. This will allow custom hardware to easily support this configuration. Signed-off-by: Justin Waters justin.wat...@timesys.com Just make boards.cfg set NAND by default, ala the console number. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] twister: usb host support
Hello Stefano,
The twister always had a fragile usb support in u-boot
in the past. Since some floating patches mentioned
alternating success after usb hub resets, I had a look
if these patches fixed the twister as well, they don't.
Some fiddling around [1] makes the usb work however,
by not attempting to reset the USB hub with gpio_25.
I cannot find any document mentioning gpio_25 though.
Any reason for this usage? It seems better to get rid
of it completely.. Anything against that?
---
Regards,
Jeroen
p.s.
I found by sheer accidence that the usb is behaving
completely normal (after the patch) on rev B1. It is
broken on rev B without the patch and working buggy
with it. On rev B1 + patch the USB to SATA converter
is discovered as well, which I have never seen before.
=== [1] patch to disable the usb reset
The change to port_mode[1] is not needed, but since it is unused,
MODE_UNUSED seems appropriate.
diff --git a/board/technexion/twister/twister.c
b/board/technexion/twister/twister.c
index a28c704..31cf6c0 100644
--- a/board/technexion/twister/twister.c
+++ b/board/technexion/twister/twister.c
@@ -63,7 +63,7 @@ static const u32 gpmc_XR16L2751[] = {
#ifdef CONFIG_USB_EHCI
static struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
@@ -92,9 +92,6 @@ int board_init(void)
enable_gpmc_cs_config(gpmc_XR16L2751, gpmc_cfg-cs[3],
XR16L2751_UART2_BASE, GPMC_SIZE_16M);
-gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, USB_PHY1_RESET);
-gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, 1);
-
=== [2] current usb master (rev B1) ===
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
=== [3] after the patch (rev B1) ===
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 4 USB Device(s) found
scanning usb for storage devices... Device NOT ready
Request Sense returned 02 3A 00
1 Storage Device(s) found
twister = usb tree
USB device tree:
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| USB2.0 Hub
|
+-3 Mass Storage (480 Mb/s, 96mA)
| USB Storage 0033
|
+-4 Mass Storage (480 Mb/s, 498mA)
Philips USB Flash Drive 070825AEA237D121
=== [4] after the patch (rev B) ===
Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
bpp3= usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... 3 USB Device(s) found
scanning usb for storage devices... 1 Storage Device(s) found
bpp3= usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
=== [5]
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... port(0) reset error
cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
twister = usb start
(Re)start USB...
USB0: USB EHCI 1.00
scanning bus 0 for devices... cannot reset port 1!?
1 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
return 0;
}
diff --git a/include/configs/tam3517-common.h
b/include/configs/tam3517-common.h
index 2af504b..852bdd7 100644
--- a/include/configs/tam3517-common.h
+++ b/include/configs/tam3517-common.h
@@ -102,7 +102,6 @@
#define CONFIG_USB_EHCI_OMAP
#define CONFIG_USB_ULPI
#define CONFIG_USB_ULPI_VIEWPORT_OMAP
-#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO25
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_USB_STORAGE
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Re: [U-Boot] [PATCH 0/5] Enhance support for BeagleBone Black
On Tue, Jul 09, 2013 at 03:00:05PM -0400, Justin Waters wrote: There are a number of differences between the BeagleBone Black and other AM335x boards that require some modification of the default AM335x EVM configuration. In particular, it lacks NAND flash, has multiple MMC interfaces, and can store its environment in an unused eMMC partition. The following patch set improves the out-of-box experience on the BeagleBone Black without impacting the existing AM335x boards. So, I was wondering how to best handle this last week. The problem is that most of what you've done for BeagleBone Black also fits with BeagleBone White and EVM SK. Or all 3 may be best served (depending on the use case) with env as a file on FAT. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/5] am335x_evm: Make NAND support modular
Tom, On Tue, 2013-07-09 at 15:44 -0400, Tom Rini wrote: On Tue, Jul 09, 2013 at 03:00:06PM -0400, Justin Waters wrote: Give the user the ability to disable NAND support by defining CONFIG_NO_NAND. This will allow custom hardware to easily support this configuration. Signed-off-by: Justin Waters justin.wat...@timesys.com Just make boards.cfg set NAND by default, ala the console number. Sounds good to me. That was my original preference, but I was trying to be as non-invasive as possible. I'll make the change now that I have the blessing. -Justin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB
but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es)
(board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with
separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet.
Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should be
able
to try bootz with appeneded dtb on another ARM board.
I've got a fix locally now, and I'm working on cleaning it up further.
The problem is that BOOTM_STATE_FINDOTHER would never work since we
aren't the right image types, so passed ramdisk and/or dtb didn't
work. Another problem was that bootz was never consuming 'bootz', but
this was OK before. I'll post a patch shortly.
OK great, thanks for looking at this. I wonder if we can collect a set of
different use cases for bootz as a basis for test cases?
My biggest worry right now is, what might show up broken next? Anyone
out there easily able to boot a netbsd kernel or something?
Yes, I am not really comfortable with this. I will see if I can write some
sandbox tests for the other image types today and post my results. I guess
this bootm code has built up over a long time and it is hard to know all
the ways it is used.
Regards,
Simon
--
Tom
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Re: [U-Boot] [PATCH 0/5] Enhance support for BeagleBone Black
Tom, On Tue, 2013-07-09 at 15:47 -0400, Tom Rini wrote: On Tue, Jul 09, 2013 at 03:00:05PM -0400, Justin Waters wrote: There are a number of differences between the BeagleBone Black and other AM335x boards that require some modification of the default AM335x EVM configuration. In particular, it lacks NAND flash, has multiple MMC interfaces, and can store its environment in an unused eMMC partition. The following patch set improves the out-of-box experience on the BeagleBone Black without impacting the existing AM335x boards. So, I was wondering how to best handle this last week. The problem is that most of what you've done for BeagleBone Black also fits with BeagleBone White and EVM SK. Or all 3 may be best served (depending on the use case) with env as a file on FAT. I tried to factor out the work as best I could. For instance, the Black is the only board with eMMC (to my knowledge), so I wanted to treat that similiarly to the SPI flash- if we have the ability to store the environment in a read/write fashion, I'd like to take advantage of it. The multiple SD card boot changes are generic, though- they should work on any of the AM335x boards without any modification. So something like the EVM will function out of the box. I have one on hand- I can give it a try. My personal preference is to provide different targets for each of the flavors (evm, sk, bone, boneblack). The boards.cfg file provides a really nice mechanism for supporting similar platforms, so I tried to separate my changes to allow for that. Then again, I'm not the one maintaining these boards, and there's already an EEPROM on the board for differentiating between the different platforms, so perhaps multiple configurations are overkill. In any event, let me know if you have any preferences. I'm certainly open to suggestions, and I have other AM335x platforms to test on as well. -Justin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB
but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es)
(board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with
separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet.
Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should be
able
to try bootz with appeneded dtb on another ARM board.
I've got a fix locally now, and I'm working on cleaning it up further.
The problem is that BOOTM_STATE_FINDOTHER would never work since we
aren't the right image types, so passed ramdisk and/or dtb didn't
work. Another problem was that bootz was never consuming 'bootz', but
this was OK before. I'll post a patch shortly.
OK great, thanks for looking at this. I wonder if we can collect a set of
different use cases for bootz as a basis for test cases?
Well, what happens on sandbox when you try and boot a kernel? :) bootz
is any of:
kernel, kernel+ramdisk, kernel+ramdisk+fdt, kernel+fdt.
My biggest worry right now is, what might show up broken next? Anyone
out there easily able to boot a netbsd kernel or something?
Yes, I am not really comfortable with this. I will see if I can write some
sandbox tests for the other image types today and post my results. I guess
this bootm code has built up over a long time and it is hard to know all
the ways it is used.
Important, but I really want to see real-world booting in a case or two.
Unfortunately I don't have any ARM boards that work out of the box with
NetBSD.
--
Tom
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Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
On Tue, Jul 9, 2013 at 4:19 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 - 256MiB
but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es)
(board
file) works, but Wand (device tree) is still locking up for me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with
separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we don't
have the rest of the header bits that the code checks for set. I've
taken a few stabs at reworking things, but it's not working yet.
Simon,
do you have any ideas here? I'm starting to wonder if we don't need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should be
able
to try bootz with appeneded dtb on another ARM board.
I've got a fix locally now, and I'm working on cleaning it up further.
The problem is that BOOTM_STATE_FINDOTHER would never work since we
aren't the right image types, so passed ramdisk and/or dtb didn't
work. Another problem was that bootz was never consuming 'bootz', but
this was OK before. I'll post a patch shortly.
OK great, thanks for looking at this. I wonder if we can collect a set of
different use cases for bootz as a basis for test cases?
Well, what happens on sandbox when you try and boot a kernel? :) bootz
is any of:
kernel, kernel+ramdisk, kernel+ramdisk+fdt, kernel+fdt.
My biggest worry right now is, what might show up broken next? Anyone
out there easily able to boot a netbsd kernel or something?
Yes, I am not really comfortable with this. I will see if I can write some
sandbox tests for the other image types today and post my results. I guess
this bootm code has built up over a long time and it is hard to know all
the ways it is used.
Important, but I really want to see real-world booting in a case or two.
Unfortunately I don't have any ARM boards that work out of the box with
NetBSD.
There 'seems' to be a pre-built freebsd arm port...
https://wiki.freebsd.org/FreeBSD/arm/BeagleBone
Regards,
--
Robert Nelson
http://www.rcn-ee.com/
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Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
Important, but I really want to see real-world booting in a case or two. Unfortunately I don't have any ARM boards that work out of the box with NetBSD. There 'seems' to be a pre-built freebsd arm port... https://wiki.freebsd.org/FreeBSD/arm/BeagleBone NM.. they are using the 'bootelf' command.. https://github.com/kientzle/crochet-freebsd/blob/master/board/BeagleBone/files/uboot_patch05.patch#L108 Regards, -- Robert Nelson http://www.rcn-ee.com/ ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 5/5] bootm: Add the missing PREP stage to bootz and correct image handling
Hi Tom,
On Tue, Jul 9, 2013 at 2:19 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 01:04:58PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 12:05 PM, Tom Rini tr...@ti.com wrote:
On Tue, Jul 09, 2013 at 12:00:00PM -0700, Simon Glass wrote:
Hi Tom,
On Tue, Jul 9, 2013 at 10:01 AM, Tom Rini tr...@ti.com wrote:
On Mon, Jul 08, 2013 at 10:22:13AM -0400, Tom Rini wrote:
On Mon, Jul 08, 2013 at 09:17:10AM -0500, Robert Nelson wrote:
On Mon, Jul 8, 2013 at 9:13 AM, Tom Rini tr...@ti.com wrote:
On Thu, Jul 04, 2013 at 01:26:11PM -0700, Simon Glass wrote:
In the recent bootm refactor, the PREP stage was missing in
the
bootz
command. This causes unpredictable behaviour.
The use of a local variable means that the reset of
cmd_bootm.c
does not
in fact use the same image structure, so remove this.
Also manually set the OS type to Linux, since this is the
only
possibility
at present, and we need to select the right boot function.
Signed-off-by: Simon Glass s...@chromium.org
With the whole series applied, I still see a hang at:
Kernel image @ 0x8020 [ 0x00 - 0x3d44a0 ]
Starting kernel ...
Perhaps something to do with how my DDR is not at 0x0 -
256MiB
but
0x8000 - 256MiB ?
Tom, which board is that?
These 5 patches just on top of v2013.07-rc2, the panda (non es)
(board
file) works, but Wand (device tree) is still locking up for
me...
Panda (Board file boot)
load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage
run mmcargs
bootz ${loadaddr}
Ah-ha! It's an appended dtb vs not problem now. I can boot my
beagelbone with with an appended dtb and bootz, but can't with
separate.
OK, the BOOTM_STATE_FINDOTHER state code isn't working since we
don't
have the rest of the header bits that the code checks for set.
I've
taken a few stabs at reworking things, but it's not working yet.
Simon,
do you have any ideas here? I'm starting to wonder if we don't
need to
revert things afterall and sort this out post release.
Yes time is running short. I did post two reverts - I wonder if they
are
effective for this problem?
Is the appended dtb with bootz the only problem remaining as far as
we
know? If so then perhaps we are close.
I will see if I can get a Beaglebone today or failing that I should
be
able
to try bootz with appeneded dtb on another ARM board.
I've got a fix locally now, and I'm working on cleaning it up further.
The problem is that BOOTM_STATE_FINDOTHER would never work since we
aren't the right image types, so passed ramdisk and/or dtb didn't
work. Another problem was that bootz was never consuming 'bootz', but
this was OK before. I'll post a patch shortly.
OK great, thanks for looking at this. I wonder if we can collect a set
of
different use cases for bootz as a basis for test cases?
Well, what happens on sandbox when you try and boot a kernel? :) bootz
is any of:
kernel, kernel+ramdisk, kernel+ramdisk+fdt, kernel+fdt.
Yes certainly there are limitations, but the test I have there so far does
check that all the data appears in the correct place in memory. That seems
to me most of the battle with bootm.
My biggest worry right now is, what might show up broken next? Anyone
out there easily able to boot a netbsd kernel or something?
Yes, I am not really comfortable with this. I will see if I can write
some
sandbox tests for the other image types today and post my results. I
guess
this bootm code has built up over a long time and it is hard to know all
the ways it is used.
Important, but I really want to see real-world booting in a case or two.
Unfortunately I don't have any ARM boards that work out of the box with
NetBSD.
Me neither, unfortunately.
Regards,
Simon
--
Tom
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Re: [U-Boot] Implement AUART for i.MX28
Hi Andreas,
I have tried to implement an AUART driver for i.MX28.
However for it to work I must print 1 character to the
debug UART via the serial_pl01x driver. If I do this
the AUART will start working. If I don't nothing will
be printed to the AUART. Anybody can see any obvious errors?
Signed-off-by: Andreas Wass andreas.w...@dalelven.com
I have to wonder, is the AUART no standard UART IP ? Probably not as Linux also
has a separate driver for this ...
Lots of rambling follows below, but please dont be put off by it.
Make sure to CC me and Fabio on the next submission. I can help you debugging
the driver if you clean it up a bit.
drivers/serial/Makefile |1 +
drivers/serial/mxs-regs-uartapp.h | 307
+ drivers/serial/mxs_auart.c|
161 +++
drivers/serial/serial.c | 11 +-
drivers/serial/serial_pl01x.c | 19 ++-
5 files changed, 492 insertions(+), 7 deletions(-)
create mode 100644 drivers/serial/mxs-regs-uartapp.h
create mode 100644 drivers/serial/mxs_auart.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index fbc4e97..f4e0d45 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -52,6 +52,7 @@ COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o
COBJS-$(CONFIG_SANDBOX_SERIAL) += sandbox.o
COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o
COBJS-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
+COBJS-$(CONFIG_MXS_AUART) += mxs_auart.o
ifndef CONFIG_SPL_BUILD
COBJS-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/mxs-regs-uartapp.h
b/drivers/serial/mxs-regs-uartapp.h new file mode 100644
index 000..aad9a78
--- /dev/null
+++ b/drivers/serial/mxs-regs-uartapp.h
[...]
Please follow the pattern of arch/arm/include/asm/arch-mxs/regs-*.h with
regards
to struct-based access and using (1 n) to declare bits.
diff --git a/drivers/serial/mxs_auart.c b/drivers/serial/mxs_auart.c
new file mode 100644
index 000..b9a4e82
[...]
+#include common.h
+#include serial.h
+#include linux/compiler.h
+#include mxs-regs-uartapp.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define REGS_UARTAPP3_BASE (0x8007)
Use arch/arm/include/asm/arch-mxs/regs-base.h , but since there are multiple,
you can add a config option to select which AUART to use.
+#define REGS_UARTAPP_BASE REGS_UARTAPP3_BASE
+#define REG_RD(base, reg) \
+ (*(volatile unsigned int *)((base) + (reg)))
+#define REG_WR(base, reg, value) \
+ ((*(volatile unsigned int *)((base) + (reg))) = (value))
Use readl() / writel() / clrsetbits_le32() etc.
+/* HACK should be removed when issue is fixed! */
+void dbg_puts(const char *s);
+
+static void mxs_auart_reset(void)
mxs_reset_block();
[...]
+/*
+ * Set baud rate. The settings are always 8n1
+ */
+void mxs_auart_setbrg(void)
+{
+ u32 div;
+ u32 linectrl = 0;
+
+ div = (CONFIG_MXS_AUART_CLK * 32) / CONFIG_BAUDRATE;
Does this not integrate with the MXS clock stuff in
arch/arm/cpu/arm926ejs/mxs/clock.c ? You might want to implement a function
there to govern the clock speed somehow.
+ linectrl |= BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(div 0x3F);
+ linectrl |= BF_UARTAPP_LINECTRL_BAUD_DIVINT(div 6);
+ linectrl |= BF_UARTAPP_LINECTRL_WLEN(3);
+ linectrl |= BM_UARTAPP_LINECTRL_FEN;
+
+ REG_WR(REGS_UARTAPP_BASE, HW_UARTAPP_LINECTRL, linectrl);
+}
+
+void mxs_auart_init(void)
+{
+ mxs_auart_reset();
mxs_reset_block() and drop the above ;-)
+ REG_WR(REGS_UARTAPP_BASE, HW_UARTAPP_INTR, 0);
+ serial_setbrg();
+
+ REG_WR(REGS_UARTAPP_BASE, HW_UARTAPP_CTRL2_CLR,
+ BM_UARTAPP_CTRL2_RTSEN | BM_UARTAPP_CTRL2_CTSEN |
+ BM_UARTAPP_CTRL2_USE_LCR2);
+ REG_WR(REGS_UARTAPP_BASE, HW_UARTAPP_CTRL2_SET,
+ BM_UARTAPP_CTRL2_RXE | BM_UARTAPP_CTRL2_TXE |
+ BM_UARTAPP_CTRL2_UARTEN);
+
+ /* HACK, the driver will not work without this.
+ * Don't know how to fix
+ */
See http://www.denx.de/wiki/U-Boot/CodingStyle about the comments.
+ dbg_puts(\n);
Is your AUART set as default uart ? Or how do you operate it ?
+ return 0;
+}
+
+void mxs_auart_putc(const char c)
+{
+ while (REG_RD(REGS_UARTAPP_BASE, HW_UARTAPP_STAT)
+ BM_UARTAPP_STAT_TXFF)
+ ;
Careful about endless loop here.
+ REG_WR(REGS_UARTAPP_BASE, HW_UARTAPP_DATA, c);
+ if (c == '\n')
+ mxs_auart_putc('\r');
+
+}
+
+void mxs_auart_puts(const char *s)
+{
+ while (*s)
+ mxs_auart_putc(*s++);
Use default_serial_puts()
+}
+
+int mxs_auart_tstc(void)
+{
+ return !(REG_RD(REGS_UARTAPP_BASE, HW_UARTAPP_STAT)
+ BM_UARTAPP_STAT_RXFE);
+}
+
+int mxs_auart_getc(void)
+{
+ while (!mxs_auart_tstc())
+ ;
+
+ return REG_RD(REGS_UARTAPP_BASE,
[U-Boot] [PATCH v3 6/7] ARM: extend non-secure switch to also go into HYP mode
For the KVM and XEN hypervisors to be usable, we need to enter the kernel in HYP mode. Now that we already are in non-secure state, HYP mode switching is within short reach. While doing the non-secure switch, we have to enable the HVC instruction and setup the HYP mode HVBAR (while still secure). The actual switch is done by dropping back from a HYP mode handler without actually leaving HYP mode, so we introduce a new handler routine in our new secure exception vector table. In the assembly switching routine we save and restore the banked LR and SP registers around the hypercall to do the actual HYP mode switch. The C routine first checks whether we are in HYP mode already and also whether the virtualization extensions are available. It also checks whether the HYP mode switch was finally successful. The bootm command part only adds and adjusts some error reporting. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/nonsec_virt.S | 43 +++- arch/arm/cpu/armv7/virt-v7.c | 31 + arch/arm/include/asm/armv7.h | 9 +++-- arch/arm/lib/bootm.c | 19 +++--- 5 files changed, 93 insertions(+), 11 deletions(-) diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index b59f59e..e5eaa56 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,7 +36,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS += lowlevel_init.o endif -ifneq ($(CONFIG_ARMV7_NONSEC),) +ifneq ($(CONFIG_ARMV7_NONSEC)$(CONFIG_ARMV7_VIRT),) SOBJS += nonsec_virt.o COBJS += virt-v7.o endif diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index f9b6b39..895c3b0 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -1,5 +1,5 @@ /* - * code for switching cores into non-secure state + * code for switching cores into non-secure state and into HYP mode * * Copyright (c) 2013 Andre Przywara andre.przyw...@linaro.org * @@ -28,15 +28,16 @@ #include asm/armv7.h .arch_extension sec +.arch_extension virt -/* the vector table for secure state */ +/* the vector table for secure state and HYP mode */ _monitor_vectors: .word 0 /* reset */ .word 0 /* undef */ adr pc, _secure_monitor .word 0 .word 0 - .word 0 + adr pc, _hyp_trap .word 0 .word 0 .word 0 /* pad */ @@ -53,10 +54,27 @@ _secure_monitor: bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits orr r1, r1, #0x31 @ enable NS, AW, FW bits +#ifdef CONFIG_ARMV7_VIRT + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0, #CPUID_ARM_VIRT_MASK@ mask virtualization bits + cmp r0, #(1 CPUID_ARM_VIRT_SHIFT) + orreq r1, r1, #0x100 @ allow HVC instruction +#endif + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) +#ifdef CONFIG_ARMV7_VIRT + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value + mcreq p15, 4, r0, c12, c0, 0 @ write HVBAR +#endif + movspc, lr @ return to non-secure SVC +_hyp_trap: + mrs lr, elr_hyp @ for older asm: .byte 0x00, 0xe3, 0x0e, 0xe1 + mov pc, lr @ do no switch modes, but + @ return to caller + /* * Secondary CPUs start here and call the code for the core specific parts * of the non-secure and HYP mode transition. The GIC distributor specific @@ -71,9 +89,13 @@ ENTRY(_smp_pen) mcr p15, 0, r1, c12, c0, 0 @ set VBAR bl _nonsec_init + mov r12, r0 @ save GICC address +#ifdef CONFIG_ARMV7_VIRT + bl _switch_to_hyp +#endif - ldr r1, [r0, #GICC_IAR] @ acknowledge IPI - str r1, [r0, #GICC_EOIR]@ signal end of interrupt + ldr r1, [r12, #GICC_IAR]@ acknowledge IPI + str r1, [r12, #GICC_EOIR] @ signal end of interrupt adr r1, _smp_pen waitloop: wfi @@ -164,3 +186,14 @@ ENTRY(_nonsec_init) bx lr ENDPROC(_nonsec_init) + +ENTRY(_switch_to_hyp) + mov r0, lr + mov r1, sp @ save SVC copy of LR and SP + isb + hvc #0 @ for older asm: .byte 0x70, 0x00, 0x40, 0xe1 + mov sp, r1 + mov lr, r0 @ restore SVC copy of LR and SP + + bx lr +ENDPROC(_switch_to_hyp) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index a0d0b34..3645572 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -3,6 +3,7 @@ * Andre
[U-Boot] [PATCH v3 2/7] ARM: add secure monitor handler to switch to non-secure state
A prerequisite for using virtualization is to be in HYP mode, which requires the CPU to be in non-secure state first. Add new file in arch/arm/cpu/armv7 to hold a monitor handler routine which switches the CPU to non-secure state by setting the NS and associated bits. According to the ARM architecture reference manual this should not be done in SVC mode, so we have to setup a SMC handler for this. We create a new vector table to avoid interference with other boards. The MVBAR register will be programmed later just before the smc call. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/Makefile | 4 +++ arch/arm/cpu/armv7/nonsec_virt.S | 54 2 files changed, 58 insertions(+) create mode 100644 arch/arm/cpu/armv7/nonsec_virt.S diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 7a8c2d0..5d75077 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -36,6 +36,10 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONF SOBJS += lowlevel_init.o endif +ifneq ($(CONFIG_ARMV7_NONSEC),) +SOBJS += nonsec_virt.o +endif + SRCS := $(START:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) START := $(addprefix $(obj),$(START)) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S new file mode 100644 index 000..68a6b38 --- /dev/null +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -0,0 +1,54 @@ +/* + * code for switching cores into non-secure state + * + * Copyright (c) 2013 Andre Przywara andre.przyw...@linaro.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include config.h + +/* the vector table for secure state */ +_monitor_vectors: + .word 0 /* reset */ + .word 0 /* undef */ + adr pc, _secure_monitor + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 /* pad */ + +/* + * software interrupt aka. secure monitor handler + * This is executed on a smc instruction, we use a smc #0 to switch + * to non-secure state. + * We use only r0 and r1 here, due to constraints in the caller. + */ + .align 5 +_secure_monitor: + mrc p15, 0, r1, c1, c1, 0 @ read SCR + bic r1, r1, #0x4e @ clear IRQ, FIQ, EA, nET bits + orr r1, r1, #0x31 @ enable NS, AW, FW bits + + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) + + movspc, lr @ return to non-secure SVC + -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/7] ARM: add SMP support for non-secure switch
Currently the non-secure switch is only done for the boot processor.
To enable full SMP support, we have to switch all secondary cores
into non-secure state also.
So we add an entry point for secondary CPUs coming out of low-power
state and make sure we put them into WFI again after having switched
to non-secure state.
For this we acknowledge and EOI the wake-up IPI, then go into WFI.
Once being kicked out of it later, we sanity check that the start
address has actually been changed (since another attempt to switch
to non-secure would block the core) and jump to the new address.
The actual CPU kick is done by sending an inter-processor interrupt
via the GIC to all CPU interfaces except the requesting processor.
The secondary cores will then setup their respective GIC CPU
interface.
The address secondary cores jump to is board specific, we provide
the value here for the Versatile Express board.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/nonsec_virt.S| 27 +++
arch/arm/cpu/armv7/virt-v7.c| 19 ++-
arch/arm/include/asm/armv7.h| 1 +
arch/arm/include/asm/gic.h | 2 ++
include/configs/vexpress_ca15_tc2.h | 3 +++
5 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
index e9ee831..f9b6b39 100644
--- a/arch/arm/cpu/armv7/nonsec_virt.S
+++ b/arch/arm/cpu/armv7/nonsec_virt.S
@@ -58,6 +58,33 @@ _secure_monitor:
movspc, lr @ return to non-secure SVC
/*
+ * Secondary CPUs start here and call the code for the core specific parts
+ * of the non-secure and HYP mode transition. The GIC distributor specific
+ * code has already been executed by a C function before.
+ * Then they go back to wfi and wait to be woken up by the kernel again.
+ */
+ENTRY(_smp_pen)
+ mrs r0, cpsr
+ orr r0, r0, #0xc0
+ msr cpsr, r0@ disable interrupts
+ ldr r1, =_start
+ mcr p15, 0, r1, c12, c0, 0 @ set VBAR
+
+ bl _nonsec_init
+
+ ldr r1, [r0, #GICC_IAR] @ acknowledge IPI
+ str r1, [r0, #GICC_EOIR]@ signal end of interrupt
+ adr r1, _smp_pen
+waitloop:
+ wfi
+ ldr r0, =CONFIG_SYSFLAGS_ADDR @ load start address
+ ldr r0, [r0]
+ cmp r0, r1 @ make sure we dont execute this code
+ beq waitloop@ again (due to a spurious wakeup)
+ mov pc, r0
+ENDPROC(_smp_pen)
+
+/*
* Switch a core to non-secure state.
*
* 1. initialize the GIC per-core interface
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
index 54f9746..a0d0b34 100644
--- a/arch/arm/cpu/armv7/virt-v7.c
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -77,6 +77,21 @@ static int get_gicd_base_address(unsigned int *gicdaddr)
#endif
}
+static void kick_secondary_cpus(unsigned int gicdaddr)
+{
+ unsigned int *secondary_boot_addr;
+
+ secondary_boot_addr = (void *)CONFIG_SYSFLAGS_ADDR;
+#ifdef CONFIG_SYSFLAGS_NEED_CLEAR_BITS
+ secondary_boot_addr[1] = (unsigned)-1;
+#endif
+ *secondary_boot_addr = (uintptr_t)_smp_pen;
+ dmb();
+
+ /* now kick all CPUs (except this one) by writing to GICD_SGIR */
+ writel(1U 24, gicdaddr + GICD_SGIR);
+}
+
enum nonsec_virt_errors armv7_switch_nonsec(void)
{
unsigned int reg, ret;
@@ -110,7 +125,9 @@ enum nonsec_virt_errors armv7_switch_nonsec(void)
for (i = 0; i = itlinesnr; i++)
writel((unsigned)-1, gicdaddr + GICD_IGROUPRn + 4 * i);
- /* call the non-sec switching code on this CPU */
+ kick_secondary_cpus(gicdaddr);
+
+ /* call the non-sec switching code on this CPU also */
_nonsec_init();
return NONSEC_VIRT_SUCCESS;
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index e5c0279..f6582a1 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -102,6 +102,7 @@ enum nonsec_virt_errors armv7_switch_nonsec(void);
/* defined in assembly file */
unsigned int _nonsec_init(void);
+void _smp_pen(void);
#endif /* CONFIG_ARMV7_NONSEC */
#endif /* ! __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/gic.h b/arch/arm/include/asm/gic.h
index c2b1e28..a0891cc 100644
--- a/arch/arm/include/asm/gic.h
+++ b/arch/arm/include/asm/gic.h
@@ -13,5 +13,7 @@
#define GIC_CPU_OFFSET_A15 0x2000
#define GICC_CTLR 0x
#define GICC_PMR 0x0004
+#define GICC_IAR 0x000C
+#define GICC_EOIR 0x0010
#endif
diff --git a/include/configs/vexpress_ca15_tc2.h
b/include/configs/vexpress_ca15_tc2.h
index 4f425ac..ade9e5b 100644
--- a/include/configs/vexpress_ca15_tc2.h
+++ b/include/configs/vexpress_ca15_tc2.h
@@ -31,4 +31,7 @@
#include vexpress_common.h
#define CONFIG_BOOTP_VCI_STRING
[U-Boot] [PATCH v3 4/7] ARM: switch to non-secure state during bootm execution
To actually trigger the non-secure switch we just implemented, call
the switching routine from within the bootm command implementation.
This way we automatically enable this feature without further user
intervention.
The core specific part of the work is done in the assembly routine
in nonsec_virt.S, introduced with the previous patch, but for the full
glory we need to setup the GIC distributor interface once for the
whole system, which is done in C here.
The routine is placed in arch/arm/cpu/armv7 to allow easy access from
other ARMv7 boards.
We check the availability of the security extensions first.
Since we need a safe way to access the GIC, we use the PERIPHBASE
registers on Cortex-A15 and A7 CPUs and do some sanity checks.
Board not implementing the CBAR can override this value via a
configuration file variable.
Then we actually do the GIC enablement:
a) enable the GIC distributor, both for non-secure and secure state
(GICD_CTLR[1:0] = 11b)
b) allow all interrupts to be handled from non-secure state
(GICD_IGROUPRn = 0x)
The core specific GIC setup is then done in the assembly routine.
The actual bootm trigger is pretty small: calling the routine and
doing some error reporting.
Signed-off-by: Andre Przywara andre.przyw...@linaro.org
---
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/virt-v7.c | 117 +++
arch/arm/include/asm/armv7.h | 10
arch/arm/lib/bootm.c | 28 +++
4 files changed, 156 insertions(+)
create mode 100644 arch/arm/cpu/armv7/virt-v7.c
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 5d75077..b59f59e 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -38,6 +38,7 @@ endif
ifneq ($(CONFIG_ARMV7_NONSEC),)
SOBJS += nonsec_virt.o
+COBJS += virt-v7.o
endif
SRCS := $(START:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c
new file mode 100644
index 000..54f9746
--- /dev/null
+++ b/arch/arm/cpu/armv7/virt-v7.c
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2013
+ * Andre Przywara, Linaro
+ *
+ * Routines to transition ARMv7 processors from secure into non-secure state
+ * needed to enable ARMv7 virtualization for current hypervisors
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/armv7.h
+#include asm/gic.h
+#include asm/io.h
+
+static unsigned int read_id_pfr1(void)
+{
+ unsigned int reg;
+
+ asm(mrc p15, 0, %0, c0, c1, 1\n : =r(reg));
+ return reg;
+}
+
+static int get_gicd_base_address(unsigned int *gicdaddr)
+{
+#ifdef CONFIG_ARM_GIC_BASE_ADDRESS
+ *gicdaddr = CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET;
+ return 0;
+#else
+ unsigned midr;
+ unsigned periphbase;
+
+ /* check whether we are an Cortex-A15 or A7.
+* The actual HYP switch should work with all CPUs supporting
+* the virtualization extension, but we need the GIC address,
+* which we know only for sure for those two CPUs.
+*/
+ asm(mrc p15, 0, %0, c0, c0, 0\n : =r(midr));
+ switch (midr MIDR_PRIMARY_PART_MASK) {
+ case MIDR_CORTEX_A9_R0P1:
+ case MIDR_CORTEX_A15_R0P0:
+ case MIDR_CORTEX_A7_R0P0:
+ break;
+ default:
+ return NONSEC_ERR_NO_GIC_ADDRESS;
+ }
+
+ /* get the GIC base address from the CBAR register */
+ asm(mrc p15, 4, %0, c15, c0, 0\n : =r (periphbase));
+
+ /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to
+* encode this). Bail out here since we cannot access this without
+* enabling paging.
+*/
+ if ((periphbase 0xff) != 0)
+ return NONSEC_ERR_GIC_ADDRESS_ABOVE_4GB;
+
+ *gicdaddr = periphbase + GIC_DIST_OFFSET;
+
+ return 0;
+#endif
+}
+
+enum nonsec_virt_errors armv7_switch_nonsec(void)
+{
+ unsigned int reg, ret;
+ unsigned int gicdaddr = 0;
+ unsigned itlinesnr, i;
+
+ /* check whether the CPU supports the security extensions */
+ reg = read_id_pfr1();
+ if ((reg 0xF0) == 0)
+ return NONSEC_ERR_NO_SEC_EXT;
+
+ /* the SCR
[U-Boot] [PATCH v3 1/7] ARM: prepare armv7.h to be included from assembly source
armv7.h contains some useful constants, but also C prototypes. To include it also in assembly files, protect the non-assembly part appropriately. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/include/asm/armv7.h | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a73630b..20caa7c 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -23,7 +23,6 @@ */ #ifndef ARMV7_H #define ARMV7_H -#include linux/types.h /* Cortex-A9 revisions */ #define MIDR_CORTEX_A9_R0P10x410FC091 @@ -57,6 +56,9 @@ #define ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA 3 #define ARMV7_CLIDR_CTYPE_UNIFIED 4 +#ifndef __ASSEMBLY__ +#include linux/types.h + /* * CP15 Barrier instructions * Please note that we have separate barrier instructions in ARMv7 @@ -74,4 +76,6 @@ void v7_outer_cache_inval_all(void); void v7_outer_cache_flush_range(u32 start, u32 end); void v7_outer_cache_inval_range(u32 start, u32 end); +#endif /* ! __ASSEMBLY__ */ + #endif -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/7] ARM: add assembly routine to switch to non-secure state
While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0x) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- arch/arm/cpu/armv7/nonsec_virt.S| 85 + arch/arm/include/asm/armv7.h| 18 arch/arm/include/asm/gic.h | 17 include/configs/vexpress_ca15_tc2.h | 2 - 4 files changed, 120 insertions(+), 2 deletions(-) create mode 100644 arch/arm/include/asm/gic.h diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 68a6b38..e9ee831 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -23,6 +23,11 @@ */ #include config.h +#include linux/linkage.h +#include asm/gic.h +#include asm/armv7.h + +.arch_extension sec /* the vector table for secure state */ _monitor_vectors: @@ -52,3 +57,83 @@ _secure_monitor: movspc, lr @ return to non-secure SVC +/* + * Switch a core to non-secure state. + * + * 1. initialize the GIC per-core interface + * 2. allow coprocessor access in non-secure modes + * 3. switch the cpu mode (by calling smc #0) + * + * Called from smp_pen by secondary cores and directly by the BSP. + * Do not assume that the stack is available and only use registers + * r0-r3 and r12. + * + * PERIPHBASE is used to get the GIC address. This could be 40 bits long, + * though, but we check this in C before calling this function. + */ +ENTRY(_nonsec_init) +#ifdef CONFIG_ARM_GIC_BASE_ADDRESS + ldr r2, =CONFIG_ARM_GIC_BASE_ADDRESS +#else + mrc p15, 4, r2, c15, c0, 0 @ read CBAR +#endif + add r3, r2, #GIC_DIST_OFFSET@ GIC dist i/f offset + mvn r1, #0 @ all bits to 1 + str r1, [r3, #GICD_IGROUPRn]@ allow private interrupts + + mrc p15, 0, r0, c0, c0, 0 @ read MIDR + ldr r1, =MIDR_PRIMARY_PART_MASK + and r0, r0, r1 @ mask out variant and revision + + ldr r1, =MIDR_CORTEX_A7_R0P0 MIDR_PRIMARY_PART_MASK + cmp r0, r1 @ check for Cortex-A7 + + ldr r1, =MIDR_CORTEX_A15_R0P0 MIDR_PRIMARY_PART_MASK + cmpne r0, r1 @ check for Cortex-A15 + + movne r1, #GIC_CPU_OFFSET_A9 @ GIC CPU offset for A9 + moveq r1, #GIC_CPU_OFFSET_A15 @ GIC CPU offset for A15/A7 + add r3, r2, r1 @ r3 = GIC CPU i/f addr + + mov r1, #1 @ set GICC_CTLR[enable] + str r1, [r3, #GICC_CTLR]@ and clear all other bits + mov r1, #0xff + str r1, [r3, #GICC_PMR] @ set priority mask register + + movwr1, #0x3fff + movtr1, #0x0006 + mcr p15, 0, r1, c1, c1, 2 @ NSACR = all copros to non-sec + +/* The CNTFRQ register of the generic timer needs to be + * programmed in secure state. Some primary bootloaders / firmware + * omit this, so if the frequency is provided in the configuration, + * we do this here instead. + * But first check if we have the generic timer. + */ +#ifdef CONFIG_SYS_CLK_FREQ + mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1 + and r0, r0,
[U-Boot] [PATCH v3 0/7] ARMv7: Add HYP mode switching support
(for GIT URL and Changelog see below) ARM CPUs with the virtualization extension have a new mode called HYP mode, which allows hypervisors to safely control and monitor guests. The current hypervisor implementations (KVM and Xen) require the kernel to be entered in that HYP mode. This patch series introduces a configuration variable CONFIG_ARMV7_VIRT which enables code to switch all cores into HYP mode. This is done automatically during execution of the bootm command. The process of switching into HYP mode requires the CPU to be in secure state initially when entering u-boot, it will then setup some register and switch to non-secure state. This requires the GIC to be programmed properly first. Explanations about the details are in the commit messages of the respective patches. The patches are structured like this: 1/7: prepare header file 2/7: add monitor handler (assembly) 3/7: add per CPU non-secure switch routine (assembly) 4/7: add system wide non-secure setup and link to bootm command (C) 5/7: add SMP functionality 6/7: add HYP mode switching 7/7: enable code on Versatile Express TC2 Since up to patch 5/7 this code works on non-virtualization capable CPUs also and there has been a request, there is now a second configuration variable CONFIG_ARMV7_NONSEC, which omits the final HYP mode switch and just goes into non-secure SVC state. You can specify either (or none) of them, the code cares about the dependency. The code aims to be as generic as possible, though currently it has only been tested on the Versatile Express TC-2 board. The last patch thus enables the feature for that board. For convenience there is a GIT tree which you can pull these patches from (hypmode_v3 branch): git://git.linaro.org/people/aprzywara/u-boot.git Changes RFC..v1 * not a dedicated command anymore, code run by bootm friends * protecting code with #ifdefs to avoid unnecessary inclusion and accidental crashing (when accessing restricted registers) * moving prototypes to header file to meet checkpatch recommendation * adding comment as proposed by Christoffer Changes v1..v2 mostly style and code layout changes * restructure assembly code to live in a new file and not start.S * split smp, nonsec_init and hyp_init to be separate functions * used named constants from common header files * split C function to be more readable * extend comments to be more precise and elaborate * add provision to override GIC base address (needed for Arndale?) * add configuration variable to enable VExpress specific SMP code * use writel/readl for MMIO GIC accesses * remove superfluous isb instructions * more minor fixes Changes v2..v3 * fix clobbering of GICC address actually spoiling the stack * do CNTFRQ setup in assembly per core (and not only once per SoC) * moving the new code files into arch/arm/cpu/armv7 * add config variable for doing non-secure switch only * use actual HYP and secure instructions mnemonics instead of the encoded byte sequence. This requires more recent compilers. * make the identification of the CPU core more robust and saner * use enum for error codes and rename them * lots of smaller layout and style fixes Please review and comment! I am pretty sure I missed some of the comments from the earlier series, so if you find something that was mentioned before, feel free to repeat it. Contributions and comments to support other boards are welcome. Andre Przywara (7): ARM: prepare armv7.h to be included from assembly source ARM: add secure monitor handler to switch to non-secure state ARM: add assembly routine to switch to non-secure state ARM: switch to non-secure state during bootm execution ARM: add SMP support for non-secure switch ARM: extend non-secure switch to also go into HYP mode ARM: VExpress: enable ARMv7 virt support for VExpress A15 arch/arm/cpu/armv7/Makefile | 5 + arch/arm/cpu/armv7/nonsec_virt.S| 199 arch/arm/cpu/armv7/virt-v7.c| 165 ++ arch/arm/include/asm/armv7.h| 40 +++- arch/arm/include/asm/gic.h | 19 arch/arm/lib/bootm.c| 41 include/configs/vexpress_ca15_tc2.h | 5 +- 7 files changed, 472 insertions(+), 2 deletions(-) -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 7/7] ARM: VExpress: enable ARMv7 virt support for VExpress A15
To enable hypervisors utilizing the ARMv7 virtualization extension on the Versatile Express board with the A15 core tile, we add the respective configuration variable. Signed-off-by: Andre Przywara andre.przyw...@linaro.org --- include/configs/vexpress_ca15_tc2.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h index ade9e5b..5d6928f 100644 --- a/include/configs/vexpress_ca15_tc2.h +++ b/include/configs/vexpress_ca15_tc2.h @@ -34,4 +34,6 @@ #define CONFIG_SYSFLAGS_ADDR 0x1c010030 #define CONFIG_SYSFLAGS_NEED_CLEAR_BITS +#define CONFIG_ARMV7_VIRT + #endif -- 1.7.12.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [RFC][PATCH] arm: Fix flush_dcache_range() on arm926
The flush_dcache_range() on arm926 did not work as expected on i.MX28.
This can be observed during the operation of the FEC ethernet driver
where the driver did occasionally fail with timeout trying to transmit
a frame. The FEC ethernet driver uses DMA for transmitting the frame in
the following fashion:
0) Set bits in DMA descriptor
1) Write DMA descriptor into aligned DRAM address
2) Flush D-Cache over the descriptor
3) Start DMA
4) Invalidate D-Cache over the descriptor
5) Test if certain bits in DMA descriptor are unset
Very not so often it happened that the bits in the DMA descriptor were
still set even after hardware register -- which is not cached -- indicated
otherwise.
Here I will theoreticise, Albert, can you please correct me if I'm wrong?
This leads me to believe the DMA descriptor was still in the cacheline
after being flushed in step 2) and during the DMA gets evicted into DRAM
therefore corrupting the result of readback in 5) . By reading the ARM926
datasheet DDI0198E_arm926ejs_r0p5_trm.pdf page 50 table 2-17, it is not
clear whether cacheline that is Valid+Clean will be invalidated in the
D-Cache using the mcr p15, 0, Rx, c7, c14, 1 instruction or whether
only Valid+Dirty lines are cleaned+invalidated. The other thing that is
unclear to me is whether a cacheline that is Valid+Clear is written back
into DRAM when it is evicted from cache.
Interestingly enough, running invalidate_dcache_range() after doing the
flush_dcache_range() over the descriptor solved the problem and I see no
occasional timeout anymore. This confirms my opinion that the descriptor
might remain in the cache and be written back during the DMA operation.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Albert ARIBAUD albert.u.b...@aribaud.net
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Tom Rini tr...@ti.com
---
arch/arm/cpu/arm926ejs/cache.c | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c
index 2740ad7..2a8da84 100644
--- a/arch/arm/cpu/arm926ejs/cache.c
+++ b/arch/arm/cpu/arm926ejs/cache.c
@@ -72,19 +72,29 @@ void invalidate_dcache_range(unsigned long start, unsigned
long stop)
}
}
-void flush_dcache_range(unsigned long start, unsigned long stop)
+static void clean_dcache_range(unsigned long start, unsigned long stop)
{
if (!check_cache_range(start, stop))
return;
while (start stop) {
- asm volatile(mcr p15, 0, %0, c7, c14, 1\n : : r(start));
+ asm volatile(mcr p15, 0, %0, c7, c10, 1\n : : r(start));
start += CONFIG_SYS_CACHELINE_SIZE;
}
asm volatile(mcr p15, 0, %0, c7, c10, 4\n : : r(0));
}
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ /* See DDI0198E_arm926ejs_r0p5_trm.pdf p.50 Table 2-17 */
+
+ /* Write data to RAM from cachelines that are marked Valid+Dirty. */
+ clean_dcache_range(start, stop);
+ /* Invalidate all cachelines holding this RAM area (Dirty+Clean). */
+ invalidate_dcache_range(start, stop);
+}
+
void flush_cache(unsigned long start, unsigned long size)
{
flush_dcache_range(start, start + size);
--
1.7.10.4
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[U-Boot] [PATCH] video: Allocate the MXSFB framebuffer aligned
Allocate the framebuffer aligned so it can be flushed
and the flush_dcache_range() function won't complain.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Anatolij Gustschin ag...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/video/mxsfb.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c
index a6d8ae9..35836e1 100644
--- a/drivers/video/mxsfb.c
+++ b/drivers/video/mxsfb.c
@@ -202,7 +202,8 @@ void *video_hw_init(void)
panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
/* Allocate framebuffer */
- fb = malloc(panel.memSize);
+ fb = memalign(ARCH_DMA_MINALIGN,
+ roundup(panel.memSize, ARCH_DMA_MINALIGN));
if (!fb) {
printf(MXSFB: Error allocating framebuffer!\n);
return NULL;
--
1.7.10.4
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[U-Boot] [PATCH 06/17] usb: mv_udc: Make use of struct ehci_ctrl
The usb_lowlevel_init() call already fills and passes back struct
ehci_ctrl , which readily contains correctly determined address of
the port register block address computed from values from controller
configuration registers. Leverage this and make use of this value
as this makes the code mode universal, but also gets us rid of the
CONFIG_USB_REG_BASE configuration option.
Moreover, this patch cleans up the usb_gadget_register_driver() call
a little by correcting the error handling. Note the usb_lowlevel_init()
and mvudc_probe() are now called in reversed order, but this has no
impact on the code.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 41 +++--
include/usb/mv_udc.h|6 +++---
2 files changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 1164d74..fd3be77 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -134,7 +134,7 @@ static void mv_ep_free_request(struct usb_ep *ep, struct
usb_request *_req)
static void ep_enable(int num, int in)
{
struct ept_queue_head *head;
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
unsigned n;
head = epts + 2*num + in;
@@ -170,7 +170,7 @@ static int mv_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags)
{
struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
struct ept_queue_item *item;
struct ept_queue_head *head;
unsigned phys;
@@ -236,7 +236,7 @@ static void handle_ep_complete(struct mv_ep *ep)
static void handle_setup(void)
{
struct usb_request *req = controller.ep[0].req;
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
struct ept_queue_head *head;
struct usb_ctrlrequest r;
int status = 0;
@@ -309,7 +309,7 @@ static void stop_activity(void)
{
int i, num, in;
struct ept_queue_head *head;
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
writel(readl(udc-epcomp), udc-epcomp);
writel(readl(udc-epstat), udc-epstat);
writel(0x, udc-epflush);
@@ -331,7 +331,7 @@ static void stop_activity(void)
void udc_irq(void)
{
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
unsigned n = readl(udc-usbsts);
writel(n, udc-usbsts);
int bit, i, num, in;
@@ -389,7 +389,7 @@ void udc_irq(void)
int usb_gadget_handle_interrupts(void)
{
u32 value;
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
value = readl(udc-usbsts);
if (value)
@@ -400,7 +400,7 @@ int usb_gadget_handle_interrupts(void)
static int mv_pullup(struct usb_gadget *gadget, int is_on)
{
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
if (is_on) {
/* RESET */
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, udc-usbcmd);
@@ -428,7 +428,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on)
void udc_disconnect(void)
{
- struct mv_udc *udc = controller.udc;
+ struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
/* disable pullup */
stop_activity();
writel(USBCMD_FS2, udc-usbcmd);
@@ -443,7 +443,6 @@ static int mvudc_probe(void)
int i;
controller.gadget.ops = mv_udc_ops;
- controller.udc = (struct mv_udc *)CONFIG_USB_REG_BASE;
epts = memalign(PAGE_SIZE, QH_MAXNUM * sizeof(struct ept_queue_head));
memset(epts, 0, QH_MAXNUM * sizeof(struct ept_queue_head));
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
@@ -485,9 +484,8 @@ static int mvudc_probe(void)
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
{
- struct mv_udc *udc = controller.udc;
- int retval;
- void *ctrl;
+ struct mv_udc *udc;
+ int ret;
if (!driver
|| driver-speed USB_SPEED_FULL
@@ -497,15 +495,22 @@ int usb_gadget_register_driver(struct usb_gadget_driver
*driver)
return -EINVAL;
}
- if (!mvudc_probe()) {
- usb_lowlevel_init(0, ctrl);
+ ret = usb_lowlevel_init(0, (void **)controller.ctrl);
+ if (ret)
+ return ret;
+
+ ret = mvudc_probe();
+ if (!ret) {
+ udc = (struct mv_udc
[U-Boot] [PATCH 07/17] usb: mv_udc: Clean up the initial variable check
Clean up the code that checks the validity of a USB gadget driver
in usb_gadget_register_driver(). Moreover, limit the speed of the
driver to either FULL or HIGH, this is more precise and once we
have xHCI support, also more correct.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index fd3be77..5b2c16a 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -487,13 +487,12 @@ int usb_gadget_register_driver(struct usb_gadget_driver
*driver)
struct mv_udc *udc;
int ret;
- if (!driver
- || driver-speed USB_SPEED_FULL
- || !driver-bind
- || !driver-setup) {
- DBG(bad parameter.\n);
+ if (!driver)
+ return -EINVAL;
+ if (!driver-bind || !driver-setup || !driver-disconnect)
+ return -EINVAL;
+ if (driver-speed != USB_SPEED_FULL driver-speed != USB_SPEED_HIGH)
return -EINVAL;
- }
ret = usb_lowlevel_init(0, (void **)controller.ctrl);
if (ret)
--
1.7.10.4
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[U-Boot] [PATCH 00/17] usb: mv_udc: Cleanup and cache ops
This series cleans up the mv_udc / chipidea UDC driver and adds support for handling caches. Marek Vasut (17): usb: mv_udc: Unbreak the mv_udc driver usb: mv_udc: Clean up mv_udc.h usb: mv_udc: Move endpoint array into driver data usb: mv_udc: Clean up the EP initialization usb: ehci: Split out struct ehci_ctrl definition usb: mv_udc: Make use of struct ehci_ctrl usb: mv_udc: Clean up the initial variable check usb: mv_udc: Remove QH_MAXNUM macro usb: mv_udc: Init mv_drv.gadget.ops statically usb: mv_udc: Move QH and qTD into mv_drv usb: mv_udc: Properly align the endpoint QH and qTD list usb: mv_udc: Add cacheline length check usb: mv_udc: Implement better QH accessor usb: mv_udc: Improve allocation of qTD items usb: mv_udc: Implement better qTD item accessor usb: mv_udc: Add proper cache management usb: mv_udc: Add bounce buffer drivers/serial/usbtty.h |2 + drivers/usb/gadget/gadget_chips.h |2 +- drivers/usb/gadget/mv_udc.c | 401 + drivers/usb/host/ehci-hcd.c | 11 +- drivers/usb/host/ehci.h | 13 ++ include/usb/mv_udc.h | 88 6 files changed, 375 insertions(+), 142 deletions(-) Cc: Fabio Estevam fabio.este...@freescale.com Cc: Lei Wen lei...@marvell.com Cc: Otavio Salvador ota...@ossystems.com.br Cc: Stefano Babic sba...@denx.de -- 1.7.10.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 01/17] usb: mv_udc: Unbreak the mv_udc driver
The mv_udc driver is broken for a while and doesn't even compile.
This patch fixes the issues and gets the driver into working state
again. This driver was tested on Freescale i.MX233/i.MX28 .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/serial/usbtty.h |2 ++
drivers/usb/gadget/gadget_chips.h |2 +-
drivers/usb/gadget/mv_udc.c |7 ++-
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/usbtty.h b/drivers/serial/usbtty.h
index eb670da..4a0bd45 100644
--- a/drivers/serial/usbtty.h
+++ b/drivers/serial/usbtty.h
@@ -35,6 +35,8 @@
#include usb/pxa27x_udc.h
#elif defined(CONFIG_DW_UDC)
#include usb/designware_udc.h
+#elif defined(CONFIG_MV_UDC)
+#include usb/mv_udc.h
#endif
#include version.h
diff --git a/drivers/usb/gadget/gadget_chips.h
b/drivers/usb/gadget/gadget_chips.h
index e570142..6953174 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -144,7 +144,7 @@
#definegadget_is_m66592(g) 0
#endif
-#ifdef CONFIG_USB_GADGET_MV
+#ifdef CONFIG_MV_UDC
#define gadget_is_mv(g)(!strcmp(mv_udc, (g)-name))
#else
#define gadget_is_mv(g)0
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index cdbdcfa..db30bdd 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -33,6 +33,10 @@
#include linux/types.h
#include usb/mv_udc.h
+#if CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#error This driver only supports one single controller.
+#endif
+
#ifndef DEBUG
#define DBG(x...) do {} while (0)
#else
@@ -469,6 +473,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver
*driver)
{
struct mv_udc *udc = controller.udc;
int retval;
+ void *ctrl;
if (!driver
|| driver-speed USB_SPEED_FULL
@@ -479,7 +484,7 @@ int usb_gadget_register_driver(struct usb_gadget_driver
*driver)
}
if (!mvudc_probe()) {
- usb_lowlevel_init();
+ usb_lowlevel_init(0, ctrl);
/* select ULPI phy */
writel(PTS(PTS_ENABLE) | PFSC, udc-portsc);
}
--
1.7.10.4
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[U-Boot] [PATCH 08/17] usb: mv_udc: Remove QH_MAXNUM macro
The QH_MAXNUM is used in absolutelly incorrect manner and is not
even needed. Remove it and correctly replace it's occurance with
2 * NUM_ENDPOINTS .
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 5b2c16a..04e46e1 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -60,7 +60,7 @@ static const char *reqname(unsigned r)
#endif
#define PAGE_SIZE 4096
-#define QH_MAXNUM 32
+
static struct usb_endpoint_descriptor ep0_out_desc = {
.bLength = sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
@@ -441,10 +441,11 @@ static int mvudc_probe(void)
{
struct ept_queue_head *head;
int i;
+ const int num = 2 * NUM_ENDPOINTS;
controller.gadget.ops = mv_udc_ops;
- epts = memalign(PAGE_SIZE, QH_MAXNUM * sizeof(struct ept_queue_head));
- memset(epts, 0, QH_MAXNUM * sizeof(struct ept_queue_head));
+ epts = memalign(PAGE_SIZE, num * sizeof(struct ept_queue_head));
+ memset(epts, 0, num * sizeof(struct ept_queue_head));
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
/*
* For item0 and item1, they are served as ep0
--
1.7.10.4
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[U-Boot] [PATCH 11/17] usb: mv_udc: Properly align the endpoint QH and qTD list
The endpoint QH list has to be aligned to 10-bit boundary. We also have
to make sure the list is aligned on a cacheline boundary. Make sure it
is. Furthermore, check if the memory allocation for the QH list didn't
fail. Moveover, improve the comment about the QH list structure.
Finally, the qTD item list has to be aligned only to 5-bit boundary, not
10-bit as it is now, fix this as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 422d0a9..394af6b 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -59,8 +59,6 @@ static const char *reqname(unsigned r)
}
#endif
-#define PAGE_SIZE 4096
-
static struct usb_endpoint_descriptor ep0_out_desc = {
.bLength = sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
@@ -440,15 +438,27 @@ static int mvudc_probe(void)
{
struct ept_queue_head *head;
int i;
+
const int num = 2 * NUM_ENDPOINTS;
- controller.epts = memalign(PAGE_SIZE,
- num * sizeof(struct ept_queue_head));
- memset(controller.epts, 0, num * sizeof(struct ept_queue_head));
+ const int eplist_min_align = 4096;
+ const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
+ const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
+ const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
+
+ /* The QH list must be aligned to 4096 bytes. */
+ controller.epts = memalign(eplist_align, eplist_sz);
+ if (!controller.epts)
+ return -ENOMEM;
+ memset(controller.epts, 0, eplist_sz);
+
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
/*
-* For item0 and item1, they are served as ep0
-* outin seperately
+* Configure QH for each endpoint. The structure of the QH list
+* is such that each two subsequent fields, N and N+1 where N is
+* even, in the QH list represent QH for one endpoint. The Nth
+* entry represents OUT configuration and the N+1th entry does
+* represent IN configuration of the endpoint.
*/
head = controller.epts + i;
if (i 2)
@@ -460,7 +470,7 @@ static int mvudc_probe(void)
head-next = TERMINATE;
head-info = 0;
- controller.items[i] = memalign(PAGE_SIZE,
+ controller.items[i] = memalign(roundup(32, ARCH_DMA_MINALIGN),
sizeof(struct ept_queue_item));
}
--
1.7.10.4
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[U-Boot] [PATCH 02/17] usb: mv_udc: Clean up mv_udc.h
Do a coding-style cleanup of this file and throw away useless
defined values. These values were likely a result of a copy-paste
job.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
include/usb/mv_udc.h | 60 +++---
1 file changed, 23 insertions(+), 37 deletions(-)
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index 221e626..42dff29 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -27,28 +27,14 @@
#include linux/usb/ch9.h
#include linux/usb/gadget.h
-/* Endpoint 0 states */
-#define EP0_IDLE 0
-#define EP0_IN_DATA1
-#define EP0_OUT_DATA 2
-#define EP0_XFER_COMPLETE 3
-
+#define NUM_ENDPOINTS 6
/* Endpoint parameters */
#define MAX_ENDPOINTS 4
-#define EP_MAX_PACKET_SIZE 0x200
+#define EP_MAX_PACKET_SIZE 0x200
#define EP0_MAX_PACKET_SIZE64
-#define UDC_OUT_ENDPOINT0x02
-#define UDC_OUT_PACKET_SIZEEP_MAX_PACKET_SIZE
-#define UDC_IN_ENDPOINT 0x01
-#define UDC_IN_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_INT_ENDPOINT0x05
-#define UDC_INT_PACKET_SIZE EP_MAX_PACKET_SIZE
-#define UDC_BULK_PACKET_SIZEEP_MAX_PACKET_SIZE
-
-#defineNUM_ENDPOINTS 6
-#defineREQ_COUNT 12
+
struct mv_ep {
struct usb_ep ep;
struct usb_request req;
@@ -59,7 +45,7 @@ struct mv_ep {
struct mv_udc {
u32 pad0[80];
#define MICRO_8FRAME 0x8
-#define USBCMD_ITC(x) (((x 0xff) ? 0xff : x) 16)
+#define USBCMD_ITC(x) x) 0xff) ? 0xff : x) 16)
#define USBCMD_FS2 (1 15)
#define USBCMD_RST (1 1)
#define USBCMD_RUN (1)
@@ -75,25 +61,25 @@ struct mv_udc {
u32 epinitaddr; /* 0x158 */
u32 pad2[10];
#define PTS_ENABLE 2
-#define PTS(x) ((x 0x3) 30)
+#define PTS(x) (((x) 0x3) 30)
#define PFSC (1 24)
u32 portsc; /* 0x184 */
u32 pad3[8];
#define USBMODE_DEVICE 2
u32 usbmode;/* 0x1a8 */
u32 epstat; /* 0x1ac */
-#define EPT_TX(x) (1 ((x 0x) + 16))
-#define EPT_RX(x) (1 (x 0x))
+#define EPT_TX(x) (1 (((x) 0x) + 16))
+#define EPT_RX(x) (1 ((x) 0x))
u32 epprime;/* 0x1b0 */
u32 epflush;/* 0x1b4 */
u32 pad4;
u32 epcomp; /* 0x1bc */
-#define CTRL_TXE (1 23)
-#define CTRL_TXR (1 22)
-#define CTRL_RXE (1 7)
-#define CTRL_RXR (1 6)
-#define CTRL_TXT_BULK (2 18)
-#define CTRL_RXT_BULK (2 2)
+#define CTRL_TXE (1 23)
+#define CTRL_TXR (1 22)
+#define CTRL_RXE (1 7)
+#define CTRL_RXR (1 6)
+#define CTRL_TXT_BULK (2 18)
+#define CTRL_RXT_BULK (2 2)
u32 epctrl[16]; /* 0x1c0 */
};
@@ -105,7 +91,7 @@ struct mv_drv {
struct ept_queue_head {
unsigned config;
- unsigned current; /* read-only */
+ unsigned current; /* read-only */
unsigned next;
unsigned info;
@@ -124,9 +110,9 @@ struct ept_queue_head {
unsigned reserved_4;
};
-#define CONFIG_MAX_PKT(n) ((n) 16)
-#define CONFIG_ZLT(1 29)/* stop on zero-len xfer */
-#define CONFIG_IOS(1 15)/* IRQ on setup */
+#define CONFIG_MAX_PKT(n) ((n) 16)
+#define CONFIG_ZLT (1 29) /* stop on zero-len xfer */
+#define CONFIG_IOS (1 15) /* IRQ on setup */
struct ept_queue_item {
unsigned next;
@@ -140,12 +126,12 @@ struct ept_queue_item {
};
#define TERMINATE 1
-#define INFO_BYTES(n) ((n) 16)
-#define INFO_IOC (1 15)
-#define INFO_ACTIVE (1 7)
-#define INFO_HALTED (1 6)
-#define INFO_BUFFER_ERROR (1 5)
-#define INFO_TX_ERROR (1 3)
+#define INFO_BYTES(n) ((n) 16)
+#define INFO_IOC (1 15)
+#define INFO_ACTIVE(1 7)
+#define INFO_HALTED(1 6)
+#define INFO_BUFFER_ERROR (1 5)
+#define INFO_TX_ERROR (1 3)
extern int usb_lowlevel_init(int index, void **controller);
#endif /* __MV_UDC_H__ */
--
1.7.10.4
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[U-Boot] [PATCH 04/17] usb: mv_udc: Clean up the EP initialization
Move the constant values that are programmed into mv_ep.ep into
separate static const structure so they can be memcpy()'d when
the initialization happens.
Moveover, we only every init NUM_ENDPOINTS, not 2 * NUM_ENDPOINTS,
so fix this bug as well.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 38 ++
include/usb/mv_udc.h|2 +-
2 files changed, 27 insertions(+), 13 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 4c0755d..1164d74 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -99,6 +99,20 @@ static struct usb_ep_ops mv_ep_ops = {
.free_request = mv_ep_free_request,
};
+/* Init values for USB endpoints. */
+static const struct usb_ep mv_ep_init[2] = {
+ [0] = { /* EP 0 */
+ .maxpacket = 64,
+ .name = ep0,
+ .ops= mv_ep_ops,
+ },
+ [1] = { /* EP 1..n */
+ .maxpacket = 512,
+ .name = ep-,
+ .ops= mv_ep_ops,
+ },
+};
+
static struct mv_drv controller = {
.gadget = {
.name = mv_udc,
@@ -451,21 +465,21 @@ static int mvudc_probe(void)
}
INIT_LIST_HEAD(controller.gadget.ep_list);
- controller.gadget.ep0 = controller.ep[0].ep;
- controller.ep[0].ep.maxpacket = 64;
- controller.ep[0].ep.name = ep0;
+
+ /* Init EP 0 */
+ memcpy(controller.ep[0].ep, mv_ep_init[0], sizeof(*mv_ep_init));
controller.ep[0].desc = ep0_in_desc;
+ controller.gadget.ep0 = controller.ep[0].ep;
INIT_LIST_HEAD(controller.gadget.ep0-ep_list);
- for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
- if (i != 0) {
- controller.ep[i].ep.maxpacket = 512;
- controller.ep[i].ep.name = ep-;
- list_add_tail(controller.ep[i].ep.ep_list,
- controller.gadget.ep_list);
- controller.ep[i].desc = NULL;
- }
- controller.ep[i].ep.ops = mv_ep_ops;
+
+ /* Init EP 1..n */
+ for (i = 1; i NUM_ENDPOINTS; i++) {
+ memcpy(controller.ep[i].ep, mv_ep_init[1],
+ sizeof(*mv_ep_init));
+ list_add_tail(controller.ep[i].ep.ep_list,
+ controller.gadget.ep_list);
}
+
return 0;
}
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index da93ad3..88100ce 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -87,7 +87,7 @@ struct mv_drv {
struct usb_gadget gadget;
struct usb_gadget_driver*driver;
struct mv_udc *udc;
- struct mv_epep[2 * NUM_ENDPOINTS];
+ struct mv_epep[NUM_ENDPOINTS];
};
struct ept_queue_head {
--
1.7.10.4
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[U-Boot] [PATCH 03/17] usb: mv_udc: Move endpoint array into driver data
The endpoints are operated on a per-controller basis, move the
endpoint array into controller's private data. Also shuffle the
struct mv_ep structure definition just above the definition of
the struct mv_drv so they're well grouped together.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 48 +--
include/usb/mv_udc.h| 17 +++
2 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index db30bdd..4c0755d 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -99,10 +99,8 @@ static struct usb_ep_ops mv_ep_ops = {
.free_request = mv_ep_free_request,
};
-static struct mv_ep ep[2 * NUM_ENDPOINTS];
static struct mv_drv controller = {
.gadget = {
- .ep0 = ep[0].ep,
.name = mv_udc,
},
};
@@ -223,7 +221,7 @@ static void handle_ep_complete(struct mv_ep *ep)
static void handle_setup(void)
{
- struct usb_request *req = ep[0].req;
+ struct usb_request *req = controller.ep[0].req;
struct mv_udc *udc = controller.udc;
struct ept_queue_head *head;
struct usb_ctrlrequest r;
@@ -246,11 +244,11 @@ static void handle_setup(void)
if ((r.wValue == 0) (r.wLength == 0)) {
req-length = 0;
for (i = 0; i NUM_ENDPOINTS; i++) {
- if (!ep[i].desc)
+ if (!controller.ep[i].desc)
continue;
- num = ep[i].desc-bEndpointAddress
-USB_ENDPOINT_NUMBER_MASK;
- in = (ep[i].desc-bEndpointAddress
+ num = controller.ep[i].desc-bEndpointAddress
+USB_ENDPOINT_NUMBER_MASK;
+ in = (controller.ep[i].desc-bEndpointAddress
USB_DIR_IN) != 0;
if ((num == _num) (in == _in)) {
ep_enable(num, in);
@@ -306,10 +304,11 @@ static void stop_activity(void)
for (i = 0; i NUM_ENDPOINTS; i++) {
if (i != 0)
writel(0, udc-epctrl[i]);
- if (ep[i].desc) {
- num = ep[i].desc-bEndpointAddress
+ if (controller.ep[i].desc) {
+ num = controller.ep[i].desc-bEndpointAddress
USB_ENDPOINT_NUMBER_MASK;
- in = (ep[i].desc-bEndpointAddress USB_DIR_IN) != 0;
+ in = (controller.ep[i].desc-bEndpointAddress
+USB_DIR_IN) != 0;
head = epts + (num * 2) + (in);
head-info = INFO_ACTIVE;
}
@@ -340,8 +339,8 @@ void udc_irq(void)
if (bit == 2) {
controller.gadget.speed = USB_SPEED_HIGH;
for (i = 1; i NUM_ENDPOINTS n; i++)
- if (ep[i].desc)
- ep[i].ep.maxpacket = 512;
+ if (controller.ep[i].desc)
+ controller.ep[i].ep.maxpacket = 512;
} else {
controller.gadget.speed = USB_SPEED_FULL;
}
@@ -360,14 +359,14 @@ void udc_irq(void)
writel(n, udc-epcomp);
for (i = 0; i NUM_ENDPOINTS n; i++) {
- if (ep[i].desc) {
- num = ep[i].desc-bEndpointAddress
+ if (controller.ep[i].desc) {
+ num = controller.ep[i].desc-bEndpointAddress
USB_ENDPOINT_NUMBER_MASK;
- in = (ep[i].desc-bEndpointAddress
+ in = (controller.ep[i].desc-bEndpointAddress
USB_DIR_IN) != 0;
bit = (in) ? EPT_TX(num) : EPT_RX(num);
if (n bit)
- handle_ep_complete(ep[i]);
+ handle_ep_complete(controller.ep[i]);
}
}
}
@@ -452,19 +451,20 @@ static int mvudc_probe(void)
}
INIT_LIST_HEAD(controller.gadget.ep_list);
- ep[0].ep.maxpacket = 64;
- ep[0].ep.name = ep0;
- ep[0].desc = ep0_in_desc;
+ controller.gadget.ep0 = controller.ep[0].ep;
+ controller.ep[0].ep.maxpacket
[U-Boot] [PATCH 16/17] usb: mv_udc: Add proper cache management
Implement functions to flush/invalidate dcache over QH and qTDs
and make use of them where appropriate. Also use them to replace
the old incorrect cache management attempt. This is the first step
towards making this driver work with data cache enabled.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 82 ---
1 file changed, 77 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 364c8ed..1eda8bc 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -152,6 +152,68 @@ static struct ept_queue_item *mv_get_qtd(int ep_num, int
dir_in)
return controller.items[(ep_num * 2) + dir_in];
}
+/**
+ * mv_flush_qh - flush cache over queue head
+ * @ep_num:Endpoint number
+ *
+ * This function flushes cache over QH for particular endpoint.
+ */
+static void mv_flush_qh(int ep_num)
+{
+ struct ept_queue_head *head = mv_get_qh(ep_num, 0);
+ const uint32_t start = (uint32_t)head;
+ const uint32_t end = start + 2 * sizeof(*head);
+
+ flush_dcache_range(start, end);
+}
+
+/**
+ * mv_invalidate_qh - invalidate cache over queue head
+ * @ep_num:Endpoint number
+ *
+ * This function invalidates cache over QH for particular endpoint.
+ */
+static void mv_invalidate_qh(int ep_num)
+{
+ struct ept_queue_head *head = mv_get_qh(ep_num, 0);
+ uint32_t start = (uint32_t)head;
+ uint32_t end = start + 2 * sizeof(*head);
+
+ invalidate_dcache_range(start, end);
+}
+
+/**
+ * mv_flush_qtd - flush cache over queue item
+ * @ep_num:Endpoint number
+ *
+ * This function flushes cache over qTD pair for particular endpoint.
+ */
+static void mv_flush_qtd(int ep_num)
+{
+ struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
+ const uint32_t start = (uint32_t)item;
+ const uint32_t end_raw = start + 2 * sizeof(*item);
+ const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
+
+ flush_dcache_range(start, end);
+}
+
+/**
+ * mv_invalidate_qtd - invalidate cache over queue item
+ * @ep_num:Endpoint number
+ *
+ * This function invalidates cache over qTD pair for particular endpoint.
+ */
+static void mv_invalidate_qtd(int ep_num)
+{
+ struct ept_queue_item *item = mv_get_qtd(ep_num, 0);
+ const uint32_t start = (uint32_t)item;
+ const uint32_t end_raw = start + 2 * sizeof(*item);
+ const uint32_t end = roundup(end_raw, ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
static struct usb_request *
mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
@@ -177,8 +239,10 @@ static void ep_enable(int num, int in)
else
n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
- if (num != 0)
+ if (num != 0) {
head-config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT;
+ mv_flush_qh(num);
+ }
writel(n, udc-epctrl[num]);
}
@@ -231,8 +295,9 @@ static int mv_ep_queue(struct usb_ep *ep,
else
bit = EPT_RX(num);
- flush_cache(phys, len);
- flush_cache((unsigned long)item, sizeof(struct ept_queue_item));
+ mv_flush_qh(num);
+ mv_flush_qtd(num);
+
writel(bit, udc-epprime);
return 0;
@@ -247,7 +312,8 @@ static void handle_ep_complete(struct mv_ep *ep)
if (num == 0)
ep-desc = ep0_out_desc;
item = mv_get_qtd(num, in);
-
+ mv_invalidate_qtd(num);
+
if (item-info 0xff)
printf(EP%d/%s FAIL nfo=%x pg0=%x\n,
num, in ? in : out, item-info, item-page0);
@@ -277,7 +343,7 @@ static void handle_setup(void)
char *buf;
head = mv_get_qh(0, 0); /* EP0 OUT */
- flush_cache((unsigned long)head, sizeof(struct ept_queue_head));
+ mv_invalidate_qh(0);
memcpy(r, head-setup_data, sizeof(struct usb_ctrlrequest));
writel(EPT_RX(0), udc-epstat);
DBG(handle setup %s, %x, %x index %x value %x\n, reqname(r.bRequest),
@@ -358,6 +424,7 @@ static void stop_activity(void)
USB_DIR_IN) != 0;
head = mv_get_qh(num, in);
head-info = INFO_ACTIVE;
+ mv_flush_qh(num);
}
}
}
@@ -529,6 +596,11 @@ static int mvudc_probe(void)
imem += sizeof(struct ept_queue_item);
controller.items[i] = (struct ept_queue_item *)imem;
+
+ if (i 1) {
+ mv_flush_qh(i - 1);
+ mv_flush_qtd(i - 1);
+ }
}
INIT_LIST_HEAD(controller.gadget.ep_list);
--
1.7.10.4
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[U-Boot] [PATCH 05/17] usb: ehci: Split out struct ehci_ctrl definition
Move the struct ehci_ctrl defition from ehci-hcd.c into ehci.h
so it can be re-used by drivers. In particular, the mv_udc driver
can benefit from this move.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/host/ehci-hcd.c | 11 +--
drivers/usb/host/ehci.h | 13 +
2 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index e0f3e4b..e0ff8cf 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -36,16 +36,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
-static struct ehci_ctrl {
- struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
- struct ehci_hcor *hcor;
- int rootdev;
- uint16_t portreset;
- struct QH qh_list __aligned(USB_DMA_MINALIGN);
- struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
- uint32_t *periodic_list;
- int ntds;
-} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
+static struct ehci_ctrl ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
#define ALIGN_END_ADDR(type, ptr, size)\
((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index d090f0a..bd52afe 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -22,6 +22,8 @@
#ifndef USB_EHCI_H
#define USB_EHCI_H
+#include usb.h
+
#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#endif
@@ -252,6 +254,17 @@ struct QH {
};
};
+struct ehci_ctrl {
+ struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
+ struct ehci_hcor *hcor;
+ int rootdev;
+ uint16_t portreset;
+ struct QH qh_list __aligned(USB_DMA_MINALIGN);
+ struct QH periodic_queue __aligned(USB_DMA_MINALIGN);
+ uint32_t *periodic_list;
+ int ntds;
+};
+
/* Low level init functions */
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int ehci_hcd_stop(int index);
--
1.7.10.4
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[U-Boot] [PATCH 12/17] usb: mv_udc: Add cacheline length check
Check the length of system cacheline at compile-time and fail
if the system uses too long cachelines.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 394af6b..2076717 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -37,6 +37,16 @@
#error This driver only supports one single controller.
#endif
+/*
+ * Check if the system has too long cachelines. If the cachelines are
+ * longer then 128b, the driver will not be able flush/invalidate data
+ * cache over separate QH entries. We use 128b because one QH entry is
+ * 64b long and there are always two QH list entries for each endpoint.
+ */
+#if ARCH_DMA_MINALIGN 128
+#error This driver can not work on systems with caches longer than 128b
+#endif
+
#ifndef DEBUG
#define DBG(x...) do {} while (0)
#else
--
1.7.10.4
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[U-Boot] [PATCH 15/17] usb: mv_udc: Implement better qTD item accessor
The code for retrieving qTD item for particular endpoint is hard
to understand, moreover it's duplicated all over the driver. Move
the code into single nice and documented function.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 55dd5df..364c8ed 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -139,6 +139,19 @@ static struct ept_queue_head *mv_get_qh(int ep_num, int
dir_in)
return controller.epts[(ep_num * 2) + dir_in];
}
+/**
+ * mv_get_qtd() - return queue item for endpoint
+ * @ep_num:Endpoint number
+ * @dir_in:Direction of the endpoint (IN = 1, OUT = 0)
+ *
+ * This function returns the QH associated with particular endpoint
+ * and it's direction.
+ */
+static struct ept_queue_item *mv_get_qtd(int ep_num, int dir_in)
+{
+ return controller.items[(ep_num * 2) + dir_in];
+}
+
static struct usb_request *
mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
@@ -197,7 +210,7 @@ static int mv_ep_queue(struct usb_ep *ep,
int bit, num, len, in;
num = mv_ep-desc-bEndpointAddress USB_ENDPOINT_NUMBER_MASK;
in = (mv_ep-desc-bEndpointAddress USB_DIR_IN) != 0;
- item = controller.items[2 * num + in];
+ item = mv_get_qtd(num, in);
head = mv_get_qh(num, in);
phys = (unsigned)req-buf;
len = req-length;
@@ -233,7 +246,7 @@ static void handle_ep_complete(struct mv_ep *ep)
in = (ep-desc-bEndpointAddress USB_DIR_IN) != 0;
if (num == 0)
ep-desc = ep0_out_desc;
- item = controller.items[2 * num + in];
+ item = mv_get_qtd(num, in);
if (item-info 0xff)
printf(EP%d/%s FAIL nfo=%x pg0=%x\n,
--
1.7.10.4
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[U-Boot] [PATCH 13/17] usb: mv_udc: Implement better QH accessor
The code for retrieving QH for particular endpoint is hard to understand,
moreover it's duplicated all over the driver. Move the code into single
nice and documented function.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 2076717..68ad9f1 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -126,6 +126,19 @@ static struct mv_drv controller = {
},
};
+/**
+ * mv_get_qh() - return queue head for endpoint
+ * @ep_num:Endpoint number
+ * @dir_in:Direction of the endpoint (IN = 1, OUT = 0)
+ *
+ * This function returns the QH associated with particular endpoint
+ * and it's direction.
+ */
+static struct ept_queue_head *mv_get_qh(int ep_num, int dir_in)
+{
+ return controller.epts[(ep_num * 2) + dir_in];
+}
+
static struct usb_request *
mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
@@ -143,7 +156,7 @@ static void ep_enable(int num, int in)
struct ept_queue_head *head;
struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
unsigned n;
- head = controller.epts + 2*num + in;
+ head = mv_get_qh(num, in);
n = readl(udc-epctrl[num]);
if (in)
@@ -185,7 +198,7 @@ static int mv_ep_queue(struct usb_ep *ep,
num = mv_ep-desc-bEndpointAddress USB_ENDPOINT_NUMBER_MASK;
in = (mv_ep-desc-bEndpointAddress USB_DIR_IN) != 0;
item = controller.items[2 * num + in];
- head = controller.epts + 2 * num + in;
+ head = mv_get_qh(num, in);
phys = (unsigned)req-buf;
len = req-length;
@@ -249,7 +262,7 @@ static void handle_setup(void)
int status = 0;
int num, in, _num, _in, i;
char *buf;
- head = controller.epts + 2 * 0 + 0;
+ head = mv_get_qh(0, 0); /* EP0 OUT */
flush_cache((unsigned long)head, sizeof(struct ept_queue_head));
memcpy(r, head-setup_data, sizeof(struct usb_ctrlrequest));
@@ -330,7 +343,7 @@ static void stop_activity(void)
USB_ENDPOINT_NUMBER_MASK;
in = (controller.ep[i].desc-bEndpointAddress
USB_DIR_IN) != 0;
- head = controller.epts + (num * 2) + (in);
+ head = mv_get_qh(num, in);
head-info = INFO_ACTIVE;
}
}
@@ -413,7 +426,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on)
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, udc-usbcmd);
udelay(200);
- writel((unsigned) controller.epts, udc-epinitaddr);
+ writel((unsigned)controller.epts, udc-epinitaddr);
/* select DEVICE mode */
writel(USBMODE_DEVICE, udc-usbmode);
--
1.7.10.4
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[U-Boot] [PATCH 09/17] usb: mv_udc: Init mv_drv.gadget.ops statically
There is no need to init this field at runtime, so init it statically.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 04e46e1..8fa9781 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -114,8 +114,9 @@ static const struct usb_ep mv_ep_init[2] = {
};
static struct mv_drv controller = {
- .gadget = {
- .name = mv_udc,
+ .gadget = {
+ .name = mv_udc,
+ .ops= mv_udc_ops,
},
};
@@ -443,7 +444,6 @@ static int mvudc_probe(void)
int i;
const int num = 2 * NUM_ENDPOINTS;
- controller.gadget.ops = mv_udc_ops;
epts = memalign(PAGE_SIZE, num * sizeof(struct ept_queue_head));
memset(epts, 0, num * sizeof(struct ept_queue_head));
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
--
1.7.10.4
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[U-Boot] [PATCH 10/17] usb: mv_udc: Move QH and qTD into mv_drv
Both the endpoint queue head and the endpoint item list is a controller
specific thing. Move them both into controller private data.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 26 +-
include/usb/mv_udc.h|2 ++
2 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 8fa9781..422d0a9 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -75,8 +75,6 @@ static struct usb_endpoint_descriptor ep0_in_desc = {
.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
};
-struct ept_queue_head *epts;
-struct ept_queue_item *items[2 * NUM_ENDPOINTS];
static int mv_pullup(struct usb_gadget *gadget, int is_on);
static int mv_ep_enable(struct usb_ep *ep,
const struct usb_endpoint_descriptor *desc);
@@ -137,7 +135,7 @@ static void ep_enable(int num, int in)
struct ept_queue_head *head;
struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
unsigned n;
- head = epts + 2*num + in;
+ head = controller.epts + 2*num + in;
n = readl(udc-epctrl[num]);
if (in)
@@ -178,8 +176,8 @@ static int mv_ep_queue(struct usb_ep *ep,
int bit, num, len, in;
num = mv_ep-desc-bEndpointAddress USB_ENDPOINT_NUMBER_MASK;
in = (mv_ep-desc-bEndpointAddress USB_DIR_IN) != 0;
- item = items[2 * num + in];
- head = epts + 2 * num + in;
+ item = controller.items[2 * num + in];
+ head = controller.epts + 2 * num + in;
phys = (unsigned)req-buf;
len = req-length;
@@ -214,7 +212,7 @@ static void handle_ep_complete(struct mv_ep *ep)
in = (ep-desc-bEndpointAddress USB_DIR_IN) != 0;
if (num == 0)
ep-desc = ep0_out_desc;
- item = items[2 * num + in];
+ item = controller.items[2 * num + in];
if (item-info 0xff)
printf(EP%d/%s FAIL nfo=%x pg0=%x\n,
@@ -243,7 +241,7 @@ static void handle_setup(void)
int status = 0;
int num, in, _num, _in, i;
char *buf;
- head = epts;
+ head = controller.epts + 2 * 0 + 0;
flush_cache((unsigned long)head, sizeof(struct ept_queue_head));
memcpy(r, head-setup_data, sizeof(struct usb_ctrlrequest));
@@ -324,7 +322,7 @@ static void stop_activity(void)
USB_ENDPOINT_NUMBER_MASK;
in = (controller.ep[i].desc-bEndpointAddress
USB_DIR_IN) != 0;
- head = epts + (num * 2) + (in);
+ head = controller.epts + (num * 2) + (in);
head-info = INFO_ACTIVE;
}
}
@@ -407,7 +405,7 @@ static int mv_pullup(struct usb_gadget *gadget, int is_on)
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, udc-usbcmd);
udelay(200);
- writel((unsigned) epts, udc-epinitaddr);
+ writel((unsigned) controller.epts, udc-epinitaddr);
/* select DEVICE mode */
writel(USBMODE_DEVICE, udc-usbmode);
@@ -444,14 +442,15 @@ static int mvudc_probe(void)
int i;
const int num = 2 * NUM_ENDPOINTS;
- epts = memalign(PAGE_SIZE, num * sizeof(struct ept_queue_head));
- memset(epts, 0, num * sizeof(struct ept_queue_head));
+ controller.epts = memalign(PAGE_SIZE,
+ num * sizeof(struct ept_queue_head));
+ memset(controller.epts, 0, num * sizeof(struct ept_queue_head));
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
/*
* For item0 and item1, they are served as ep0
* outin seperately
*/
- head = epts + i;
+ head = controller.epts + i;
if (i 2)
head-config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
| CONFIG_ZLT | CONFIG_IOS;
@@ -461,7 +460,8 @@ static int mvudc_probe(void)
head-next = TERMINATE;
head-info = 0;
- items[i] = memalign(PAGE_SIZE, sizeof(struct ept_queue_item));
+ controller.items[i] = memalign(PAGE_SIZE,
+ sizeof(struct ept_queue_item));
}
INIT_LIST_HEAD(controller.gadget.ep_list);
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index 9af9358..78fa81c 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -88,6 +88,8 @@ struct mv_drv {
struct usb_gadget gadget;
struct usb_gadget_driver*driver;
struct ehci_ctrl*ctrl;
+ struct ept_queue_head *epts;
+ struct ept_queue_item
[U-Boot] [PATCH 14/17] usb: mv_udc: Improve allocation of qTD items
Allocate the qTD items all at once instead of allocating them
separately. Moreover, make sure each qTD is properly aligned
to 32-bytes boundary and that cache can be safely flushed over
each qTD touple.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 25 +++--
include/usb/mv_udc.h|1 +
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 68ad9f1..55dd5df 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -460,6 +460,7 @@ void udc_disconnect(void)
static int mvudc_probe(void)
{
struct ept_queue_head *head;
+ uint8_t *imem;
int i;
const int num = 2 * NUM_ENDPOINTS;
@@ -469,12 +470,29 @@ static int mvudc_probe(void)
const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
+ const int ilist_align = roundup(ARCH_DMA_MINALIGN, 32);
+ const int ilist_ent_raw_sz = 2 * sizeof(struct ept_queue_item);
+ const int ilist_ent_sz = roundup(ilist_ent_raw_sz, ARCH_DMA_MINALIGN);
+ const int ilist_sz = NUM_ENDPOINTS * ilist_ent_sz;
+
/* The QH list must be aligned to 4096 bytes. */
controller.epts = memalign(eplist_align, eplist_sz);
if (!controller.epts)
return -ENOMEM;
memset(controller.epts, 0, eplist_sz);
+ /*
+* Each qTD item must be 32-byte aligned, each qTD touple must be
+* cacheline aligned. There are two qTD items for each endpoint and
+* only one of them is used for the endpoint at time, so we can group
+* them together.
+*/
+ controller.items_mem = memalign(ilist_align, ilist_sz);
+ if (!controller.items_mem) {
+ free(controller.epts);
+ return -ENOMEM;
+ }
+
for (i = 0; i 2 * NUM_ENDPOINTS; i++) {
/*
* Configure QH for each endpoint. The structure of the QH list
@@ -493,8 +511,11 @@ static int mvudc_probe(void)
head-next = TERMINATE;
head-info = 0;
- controller.items[i] = memalign(roundup(32, ARCH_DMA_MINALIGN),
- sizeof(struct ept_queue_item));
+ imem = controller.items_mem + ((i 1) * ilist_ent_sz);
+ if (i 1)
+ imem += sizeof(struct ept_queue_item);
+
+ controller.items[i] = (struct ept_queue_item *)imem;
}
INIT_LIST_HEAD(controller.gadget.ep_list);
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index 78fa81c..b58a95f 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -90,6 +90,7 @@ struct mv_drv {
struct ehci_ctrl*ctrl;
struct ept_queue_head *epts;
struct ept_queue_item *items[2 * NUM_ENDPOINTS];
+ uint8_t *items_mem;
struct mv_epep[NUM_ENDPOINTS];
};
--
1.7.10.4
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[U-Boot] [PATCH 17/17] usb: mv_udc: Add bounce buffer
The requests sent to the controller are not properly cache aligned
most of the time, thus implement a simple bounce buffer to avoid
problem with cache.
Signed-off-by: Marek Vasut ma...@denx.de
Cc: Fabio Estevam fabio.este...@freescale.com
Cc: Lei Wen lei...@marvell.com
Cc: Otavio Salvador ota...@ossystems.com.br
Cc: Stefano Babic sba...@denx.de
---
drivers/usb/gadget/mv_udc.c | 84 +++
include/usb/mv_udc.h|6 +++-
2 files changed, 82 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
index 1eda8bc..a87ddc7 100644
--- a/drivers/usb/gadget/mv_udc.c
+++ b/drivers/usb/gadget/mv_udc.c
@@ -263,6 +263,71 @@ static int mv_ep_disable(struct usb_ep *ep)
return 0;
}
+static int mv_bounce(struct mv_ep *ep)
+{
+ uint32_t addr = (uint32_t)ep-req.buf;
+ uint32_t ba;
+
+ /* Input buffer address is not aligned. */
+ if (addr (ARCH_DMA_MINALIGN - 1))
+ goto align;
+
+ /* Input buffer length is not aligned. */
+ if (ep-req.length (ARCH_DMA_MINALIGN - 1))
+ goto align;
+
+ /* The buffer is well aligned, only flush cache. */
+ ep-b_len = ep-req.length;
+ ep-b_buf = ep-req.buf;
+ goto flush;
+
+align:
+ /* Use internal buffer for small payloads. */
+ if (ep-req.length = 64) {
+ ep-b_len = 64;
+ ep-b_buf = ep-b_fast;
+ } else {
+ ep-b_len = roundup(ep-req.length, ARCH_DMA_MINALIGN);
+ ep-b_buf = memalign(ARCH_DMA_MINALIGN, ep-b_len);
+ if (!ep-b_buf)
+ return -ENOMEM;
+ }
+
+ memcpy(ep-b_buf, ep-req.buf, ep-req.length);
+
+flush:
+ ba = (uint32_t)ep-b_buf;
+ flush_dcache_range(ba, ba + ep-b_len);
+
+ return 0;
+}
+
+static void mv_debounce(struct mv_ep *ep)
+{
+ uint32_t addr = (uint32_t)ep-req.buf;
+ uint32_t ba = (uint32_t)ep-b_buf;
+
+ invalidate_dcache_range(ba, ba + ep-b_len);
+
+ /* Input buffer address is not aligned. */
+ if (addr (ARCH_DMA_MINALIGN - 1))
+ goto copy;
+
+ /* Input buffer length is not aligned. */
+ if (ep-req.length (ARCH_DMA_MINALIGN - 1))
+ goto copy;
+
+ /* The buffer is well aligned, only invalidate cache. */
+ return;
+
+copy:
+ memcpy(ep-req.buf, ep-b_buf, ep-req.length);
+
+ /* Large payloads use allocated buffer, free it. */
+ if (ep-req.length 64)
+ free(ep-b_buf);
+}
+
static int mv_ep_queue(struct usb_ep *ep,
struct usb_request *req, gfp_t gfp_flags)
{
@@ -270,25 +335,27 @@ static int mv_ep_queue(struct usb_ep *ep,
struct mv_udc *udc = (struct mv_udc *)controller.ctrl-hcor;
struct ept_queue_item *item;
struct ept_queue_head *head;
- unsigned phys;
- int bit, num, len, in;
+ int bit, num, len, in, ret;
num = mv_ep-desc-bEndpointAddress USB_ENDPOINT_NUMBER_MASK;
in = (mv_ep-desc-bEndpointAddress USB_DIR_IN) != 0;
item = mv_get_qtd(num, in);
head = mv_get_qh(num, in);
- phys = (unsigned)req-buf;
len = req-length;
+ ret = mv_bounce(mv_ep);
+ if (ret)
+ return ret;
+
item-next = TERMINATE;
item-info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
- item-page0 = phys;
- item-page1 = (phys 0xf000) + 0x1000;
+ item-page0 = (uint32_t)mv_ep-b_buf;
+ item-page1 = ((uint32_t)mv_ep-b_buf 0xf000) + 0x1000;
head-next = (unsigned) item;
head-info = 0;
- DBG(ept%d %s queue len %x, buffer %x\n,
- num, in ? in : out, len, phys);
+ DBG(ept%d %s queue len %x, buffer %p\n,
+ num, in ? in : out, len, mv_ep-b_buf);
if (in)
bit = EPT_TX(num);
@@ -319,6 +386,9 @@ static void handle_ep_complete(struct mv_ep *ep)
num, in ? in : out, item-info, item-page0);
len = (item-info 16) 0x7fff;
+
+ mv_debounce(ep);
+
ep-req.length -= len;
DBG(ept%d %s complete %x\n,
num, in ? in : out, len);
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
index b58a95f..b02b439 100644
--- a/include/usb/mv_udc.h
+++ b/include/usb/mv_udc.h
@@ -79,9 +79,13 @@ struct mv_udc {
struct mv_ep {
struct usb_ep ep;
- struct usb_request req;
struct list_head queue;
const struct usb_endpoint_descriptor *desc;
+
+ struct usb_request req;
+ uint8_t *b_buf;
+ uint32_t b_len;
+ uint8_t b_fast[64] __aligned(ARCH_DMA_MINALIGN);
};
struct mv_drv {
--
1.7.10.4
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[U-Boot] [PATCH v2 0/3] net: ftmac110: cosmetics and cleanup
From: Kuo-Jung Su dant...@faraday-tech.com 1. Update license statement 2. struct ftmac110_regs __iomem *regs - struct ftmac110_regs *regs. 3. Reformat hardware tx/rx descriptor as an uniform one, and replace uint32_t[2] with uint64_t for descriptor control. Changes for v2: - Re-send these as separate patches that each have a single, complete purpose. Kuo-Jung Su (3): net: ftmac110: Update license statement net: ftmac110: struct ftmac110_regs __iomem * - struct ftmac110_regs * net: ftmac110: Update tx/rx descriptor format drivers/net/ftmac110.c | 113 drivers/net/ftmac110.h | 87 + 2 files changed, 115 insertions(+), 85 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/3] net: ftmac110: Update license statement
From: Kuo-Jung Su dant...@faraday-tech.com Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com CC: Joe Hershberger joe.hershber...@gmail.com --- drivers/net/ftmac110.c | 17 ++--- drivers/net/ftmac110.h | 17 ++--- 2 files changed, 28 insertions(+), 6 deletions(-) diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c index 35f8633..c7d45e1 100644 --- a/drivers/net/ftmac110.c +++ b/drivers/net/ftmac110.c @@ -1,11 +1,22 @@ /* * Faraday 10/100Mbps Ethernet Controller * - * (C) Copyright 2010 Faraday Technology + * (C) Copyright 2013 Faraday Technology * Dante Su dant...@faraday-tech.com * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include common.h diff --git a/drivers/net/ftmac110.h b/drivers/net/ftmac110.h index 5b2d23b..4bb8b76 100644 --- a/drivers/net/ftmac110.h +++ b/drivers/net/ftmac110.h @@ -1,11 +1,22 @@ /* * Faraday 10/100Mbps Ethernet Controller * - * (C) Copyright 2010 Faraday Technology + * (C) Copyright 2013 Faraday Technology * Dante Su dant...@faraday-tech.com * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef _FTMAC110_H -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/3] net: ftmac110: Update tx/rx descriptor format
From: Kuo-Jung Su dant...@faraday-tech.com
1. Reformat tx/rx descriptor as an uniform struct.
2. Replace uint32_t[2] with uint64_t for descriptor control.
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftmac110.c | 86 ++--
drivers/net/ftmac110.h | 70 +++
2 files changed, 82 insertions(+), 74 deletions(-)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index 1afd95a..d154cb9 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers/net/ftmac110.c
@@ -66,11 +66,11 @@ struct ftmac110_chip {
uint32_t lnkup;
uint32_t phy_addr;
- struct ftmac110_rxd *rxd;
+ struct ftmac110_desc *rxd;
ulongrxd_dma;
uint32_t rxd_idx;
- struct ftmac110_txd *txd;
+ struct ftmac110_desc *txd;
ulongtxd_dma;
uint32_t txd_idx;
};
@@ -224,14 +224,15 @@ static int ftmac110_reset(struct eth_device *dev)
/* 1-1. Init tx ring */
for (i = 0; i CFG_TXDES_NUM; ++i) {
/* owned by SW */
- chip-txd[i].ct[0] = 0;
+ chip-txd[i].ctrl = cpu_to_le64(FTMAC110_TXD_CLRMASK);
}
chip-txd_idx = 0;
/* 1-2. Init rx ring */
for (i = 0; i CFG_RXDES_NUM; ++i) {
/* owned by HW */
- chip-rxd[i].ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
+ chip-rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_CLRMASK);
+ chip-rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
}
chip-rxd_idx = 0;
@@ -292,7 +293,8 @@ static int ftmac110_send(struct eth_device *dev, void *pkt,
int len)
{
struct ftmac110_chip *chip = dev-priv;
struct ftmac110_regs *regs = chip-regs;
- struct ftmac110_txd *des;
+ struct ftmac110_desc *txd;
+ uint64_t ctrl;
if (!chip-lnkup)
return 0;
@@ -304,24 +306,26 @@ static int ftmac110_send(struct eth_device *dev, void
*pkt, int len)
len = max(60, len);
- des = chip-txd[chip-txd_idx];
- if (le32_to_cpu(des-ct[0]) FTMAC110_TXCT0_OWNER) {
+ txd = chip-txd[chip-txd_idx];
+ ctrl = le64_to_cpu(txd-ctrl);
+ if (ctrl FTMAC110_TXD_OWNER) {
/* kick-off Tx DMA */
writel(0x, regs-txpd);
printf(ftmac110: out of txd\n);
return 0;
}
- memcpy(des-vbuf, (void *)pkt, len);
- dma_map_single(des-vbuf, len, DMA_TO_DEVICE);
+ memcpy(txd-vbuf, (void *)pkt, len);
+ dma_map_single(txd-vbuf, len, DMA_TO_DEVICE);
- /* update len, fts and lts */
- des-ct[1] = cpu_to_le32(FTMAC110_TXCT1_END);
- des-ct[1] |= cpu_to_le32(FTMAC110_TXCT1_LEN(len)
- | FTMAC110_TXCT1_FTS | FTMAC110_TXCT1_LTS);
-
- /* set owner bit and clear others */
- des-ct[0] = cpu_to_le32(FTMAC110_TXCT0_OWNER);
+ /* clear control bits */
+ ctrl = FTMAC110_TXD_CLRMASK;
+ /* set len, fts and lts */
+ ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
+ /* set owner bit */
+ ctrl |= FTMAC110_TXD_OWNER;
+ /* write back to descriptor */
+ txd-ctrl = cpu_to_le64(ctrl);
/* kick-off Tx DMA */
writel(0x, regs-txpd);
@@ -334,23 +338,24 @@ static int ftmac110_send(struct eth_device *dev, void
*pkt, int len)
static int ftmac110_recv(struct eth_device *dev)
{
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_rxd *des;
- uint32_t ct0, len, rlen = 0;
+ struct ftmac110_desc *rxd;
+ uint32_t len, rlen = 0;
+ uint64_t ctrl;
uint8_t *buf;
if (!chip-lnkup)
return 0;
do {
- des = chip-rxd[chip-rxd_idx];
- ct0 = le32_to_cpu(des-ct[0]);
- if (ct0 FTMAC110_RXCT0_OWNER)
+ rxd = chip-rxd[chip-rxd_idx];
+ ctrl = le64_to_cpu(rxd-ctrl);
+ if (ctrl FTMAC110_RXD_OWNER)
break;
- len = FTMAC110_RXCT0_LEN(ct0);
- buf = des-vbuf;
+ len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
+ buf = rxd-vbuf;
- if (ct0 FTMAC110_RXCT0_ERRMASK) {
+ if (ctrl FTMAC110_RXD_ERRMASK) {
printf(ftmac110: rx error\n);
} else {
dma_map_single(buf, len, DMA_FROM_DEVICE);
@@ -359,7 +364,9 @@ static int ftmac110_recv(struct eth_device *dev)
}
/* owned by hardware */
- des-ct[0] = cpu_to_le32(FTMAC110_RXCT0_OWNER);
+ ctrl = FTMAC110_RXD_CLRMASK;
+ ctrl |= FTMAC110_RXD_OWNER;
+ rxd-ctrl |= cpu_to_le64(ctrl);
chip-rxd_idx = (chip-rxd_idx + 1) % CFG_RXDES_NUM;
}
[U-Boot] [PATCH v2 2/3] net: ftmac110: struct ftmac110_regs __iomem * - struct ftmac110_regs *
From: Kuo-Jung Su dant...@faraday-tech.com
Signed-off-by: Kuo-Jung Su dant...@faraday-tech.com
CC: Joe Hershberger joe.hershber...@gmail.com
---
drivers/net/ftmac110.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ftmac110.c b/drivers/net/ftmac110.c
index c7d45e1..1afd95a 100644
--- a/drivers/net/ftmac110.c
+++ b/drivers/net/ftmac110.c
@@ -81,7 +81,7 @@ static uint16_t mdio_read(struct eth_device *dev,
uint8_t phyaddr, uint8_t phyreg)
{
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_regs __iomem *regs = chip-regs;
+ struct ftmac110_regs *regs = chip-regs;
uint32_t tmp, ts;
uint16_t ret = 0x;
@@ -110,7 +110,7 @@ static void mdio_write(struct eth_device *dev,
uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
{
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_regs __iomem *regs = chip-regs;
+ struct ftmac110_regs *regs = chip-regs;
uint32_t tmp, ts;
tmp = PHYCR_WRITE
@@ -207,7 +207,7 @@ static int ftmac110_reset(struct eth_device *dev)
uint8_t *a;
uint32_t i, maccr;
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_regs __iomem *regs = chip-regs;
+ struct ftmac110_regs *regs = chip-regs;
/* 1. MAC reset */
writel(MACCR_RESET, regs-maccr);
@@ -280,7 +280,7 @@ static int ftmac110_probe(struct eth_device *dev, bd_t *bis)
static void ftmac110_halt(struct eth_device *dev)
{
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_regs __iomem *regs = chip-regs;
+ struct ftmac110_regs *regs = chip-regs;
writel(0, regs-imr);
writel(0, regs-maccr);
@@ -291,7 +291,7 @@ static void ftmac110_halt(struct eth_device *dev)
static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
{
struct ftmac110_chip *chip = dev-priv;
- struct ftmac110_regs __iomem *regs = chip-regs;
+ struct ftmac110_regs *regs = chip-regs;
struct ftmac110_txd *des;
if (!chip-lnkup)
--
1.7.9.5
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Re: [U-Boot] [PATCH V1 1/1] EXYNOS: Resolve the i2c compilation error for
On 09/07/13 23:05, amar_g wrote:
This patch resolves the below mentiond compilation error of i2c driver
typo.. maybe mentiond will be mentioned?
for non-FDT case
Compilation error:
s3c24x0_i2c.c: In function 'board_i2c_init':
s3c24x0_i2c.c:544:18: error: 'CONFIG_MAX_I2C_NUM' undeclared (first use
in this function) s3c24x0_i2c.c:544:18: note: each undeclared
identifier is reported only once for each function it appears in
s3c24x0_i2c.c:545:3: warning: implicit declaration of function
'exynos_pinmux_config' [-Wimplicit-function-declaration]
s3c24x0_i2c.c:545:25: error: 'PERIPH_ID_I2C0' undeclared (first use in
this function) s3c24x0_i2c.c:546:10: error: 'PINMUX_FLAG_NONE'
undeclared (first use in this function) make[1]: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/s3c24x0_i2c.o]
Error 1 make: ***
[/home/albert/src/u-boot-arm/build/VCMA9/drivers/i2c/libi2c.o] Error 2
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Signed-off-by: Amar amarendra...@samsung.com
---
board/samsung/smdk5250/smdk5250.c | 10 ++
drivers/i2c/s3c24x0_i2c.c |9 +
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c
b/board/samsung/smdk5250/smdk5250.c
index ae1f077..f1d3d97 100644
--- a/board/samsung/smdk5250/smdk5250.c
+++ b/board/samsung/smdk5250/smdk5250.c
@@ -332,6 +332,16 @@ static int board_uart_init(void)
return ret;
}
+void board_i2c_init(const void *blob)
+{
+ int i;
+
+ for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
+ exynos_pinmux_config((PERIPH_ID_I2C0 + i),
+ PINMUX_FLAG_NONE);
+ }
+}
+
#ifdef CONFIG_BOARD_EARLY_INIT_F
int board_early_init_f(void)
{
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index 3fc1c5b..382e4c2 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -515,10 +515,10 @@ int i2c_write(uchar chip, uint addr, int alen, uchar
*buffer, int len)
len) != 0);
}
+#ifdef CONFIG_OF_CONTROL
void board_i2c_init(const void *blob)
{
int i;
-#ifdef CONFIG_OF_CONTROL
int node_list[CONFIG_MAX_I2C_NUM];
int count;
@@ -540,15 +540,8 @@ void board_i2c_init(const void *blob)
bus-bus_num = i2c_busses++;
exynos_pinmux_config(bus-id, 0);
}
-#else
- for (i = 0; i CONFIG_MAX_I2C_NUM; i++) {
- exynos_pinmux_config((PERIPH_ID_I2C0 + i),
- PINMUX_FLAG_NONE);
- }
-#endif
}
-#ifdef CONFIG_OF_CONTROL
static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx)
{
if (bus_idx i2c_busses)
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Re: [U-Boot] [PATCH v5 1/1] NET: Improve TFTP booting performance when CONFIG_USB_KEYBOARD
On Tue, 2013-07-09 at 06:17 +0800, Joe Hershberger wrote:
Hi Jim and Stephen,
On Wed, Jul 3, 2013 at 11:01 PM, Jim Lin ji...@nvidia.com wrote:
TFTP booting is slow when a USB keyboard is installed and
CONFIG_USB_KEYBOARD is defined.
This fix is to change Ctrl-C polling to every second when NET transfer
is running.
Signed-off-by: Jim Lin ji...@nvidia.com
---
Changes in v2:
1. Change configuration name from CONFIG_CTRLC_POLL_MS to
CONFIG_CTRLC_POLL_S.
2. New code will be executed only when CONFIG_CTRLC_POLL_S is defined in
configuration header file.
3. Add description in README.console.
Changes in v3:
1. Move changes to common/usb_kbd.c and doc/README.usb
2. Rename config setting to CONFIG_USBKB_TESTC_PERIOD.
3. Remove slow response on USB-keyboard input when TFTP boot is not
running.
Changes in v4:
1. Remove changes in doc/README.usb, common/usb_kbd.c and
CONFIG_USBKB_TESTC_PERIOD
2. Modify net/net.c
Changes in v5:
1. Change variable name to ctrlc_t_start.
2. Use two calls of get_timer(0) to get time gap.
net/net.c | 22 ++
1 files changed, 22 insertions(+), 0 deletions(-)
diff --git a/net/net.c b/net/net.c
index df94789..ec88b02 100644
--- a/net/net.c
+++ b/net/net.c
@@ -322,6 +322,11 @@ int NetLoop(enum proto_t protocol)
{
bd_t *bd = gd-bd;
int ret = -1;
+#ifdef CONFIG_USB_KEYBOARD
+ unsigned long ctrlc_t_start;
+ unsigned long ctrlc_t;
+ int ctrlc_result;
+#endif
NetRestarted = 0;
NetDevExists = 0;
@@ -472,7 +477,24 @@ restart:
/*
* Abort if ctrl-c was pressed.
*/
+#ifdef CONFIG_USB_KEYBOARD
It seems this is the result of the USB Keyboard behavior. Why is it a
good idea to litter the TFTP code with this unrelated code? It seems
So far this is the best place to resolve this issue.
the very same check could be down inside of ctrlc() somewhere that is
at least console I/O related. Besides, having it in a common place
will allow any operation that accesses the keyboard to benefit from
not hanging up on slow USB stuff.
It also seems that it should depend on what the actual source of the
stdin is, not just if you compiled in CONFIG_USB_KEYBOARD support.
This issue only goes with USB keyboard installed and CONFIG_USB_KEYBOARD
defined. Therefore compiled in CONFIG_USB_KEYBOARD support.
Non-usb-keyboard doesn't have such issue.
Again, something that belongs in the console source.
+ /*
+* Reduce ctrl-c checking to 1 second once
+* to improve TFTP boot performance.
+*/
+ if (ctrlc_t_start get_timer(0))
+ ctrlc_t_start = get_timer(0);
+ ctrlc_t = get_timer(0) - ctrlc_t_start;
Why is it preferable to do the subtraction yourself instead of letting
get_timer() do it? I.e. what compelled did you change this from v4?
As Wolfgang Denk said in another mail,
An exception is arch/arm/cpu/sa1100/timer.c which does not respect
the base argument at all, i. e. which is broken.
.
So this v5 patch uses get_timer(0), like other code did in this file.
+ if (ctrlc_t CONFIG_SYS_HZ) {
Why is hard-coding it to 1 second a good idea?
Is that really how unresponsive it has to be to not
significantly impact TFTP boot time?
Do you want me to add a CONFIG setting to have this time adjustable?
I was thinking 1 second checking on Ctrl-C should be fine while TFT
boot is running.
--
nvpublic
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[U-Boot] [PATCH]mx6qsabresd: Add splash screen support via HDMI
Signed-off-by: Pardeep Kumar Singla b45...@freescale.com
---
board/freescale/mx6qsabresd/mx6qsabresd.c | 92 -
include/configs/mx6qsabre_common.h|3 +-
include/configs/mx6qsabresd.h | 13
3 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6qsabresd/mx6qsabresd.c
b/board/freescale/mx6qsabresd/mx6qsabresd.c
index 2529826..301fd1b 100644
--- a/board/freescale/mx6qsabresd/mx6qsabresd.c
+++ b/board/freescale/mx6qsabresd/mx6qsabresd.c
@@ -31,6 +31,11 @@
#include fsl_esdhc.h
#include miiphy.h
#include netdev.h
+#include asm/arch/crm_regs.h
+#include asm/arch/crm_regs.h
+#include ipu_pixfmt.h
+#include linux/fb.h
+#include asm/arch/mxc_hdmi.h
DECLARE_GLOBAL_DATA_PTR;
@@ -133,6 +138,80 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
+#if defined(CONFIG_VIDEO_IPUV3)
+static void enable_hdmi(void)
+{
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ u8 reg;
+ reg = readb(hdmi-phy_conf0);
+ reg |= HDMI_PHY_CONF0_PDZ_MASK;
+ writeb(reg, hdmi-phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
+ writeb(reg, hdmi-phy_conf0);
+ udelay(3000);
+ reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
+ writeb(reg, hdmi-phy_conf0);
+ writeb(HDMI_MC_PHYRSTZ_ASSERT, hdmi-mc_phyrstz);
+}
+
+static struct fb_videomode const hdmi = {
+ .name = HDMI,
+ .refresh= 60,
+ .xres = 1024,
+ .yres = 768,
+ .pixclock = 15385,
+ .left_margin= 220,
+ .right_margin = 40,
+ .upper_margin = 21,
+ .lower_margin = 7,
+ .hsync_len = 60,
+ .vsync_len = 10,
+ .sync = FB_SYNC_EXT,
+ .vmode = FB_VMODE_NONINTERLACED
+};
+
+int board_video_skip(void)
+{
+ int ret;
+ ret = ipuv3_fb_init(hdmi, 0, IPU_PIX_FMT_RGB24);
+ if (ret)
+ printf(HDMI cannot be configured: %d\n, ret);
+ enable_hdmi();
+ return ret;
+}
+
+static void setup_display(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+ struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
+ int reg;
+
+ /* Turn on IPU clock */
+ reg = readl(mxc_ccm-CCGR3);
+ reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET;
+ writel(reg, mxc_ccm-CCGR3);
+ /* Turn on HDMI PHY clock */
+ reg = readl(mxc_ccm-CCGR2);
+ reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
+MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
+ writel(reg, mxc_ccm-CCGR2);
+ /* clear HDMI PHY reset */
+ writeb(HDMI_MC_PHYRSTZ_DEASSERT, hdmi-mc_phyrstz);
+ reg = readl(mxc_ccm-chsccdr);
+ reg = ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
+MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
+MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
+ reg |= (CHSCCDR_CLK_SEL_LDB_DI0
+ MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)|
+(CHSCCDR_PODF_DIVIDE_BY_3
+ MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
+| (CHSCCDR_IPU_PRE_CLK_540M_PFD
+ MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
+ writel(reg, mxc_ccm-chsccdr);
+}
+#endif /* CONFIG_VIDEO_IPUV3 */
+
#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
{USDHC2_BASE_ADDR},
@@ -257,10 +336,21 @@ int board_eth_init(bd_t *bis)
int board_early_init_f(void)
{
setup_iomux_uart();
-
+#if defined(CONFIG_VIDEO_IPUV3)
+ setup_display();
+#endif
return 0;
}
+/*
+ * Do not overwrite the console
+ * Use always serial for U-Boot console
+ */
+int overwrite_console(void)
+{
+ return 1;
+}
+
int board_init(void)
{
/* address of boot parameters */
diff --git a/include/configs/mx6qsabre_common.h
b/include/configs/mx6qsabre_common.h
index bfaa420..438cb83 100644
--- a/include/configs/mx6qsabre_common.h
+++ b/include/configs/mx6qsabre_common.h
@@ -21,6 +21,7 @@
#define CONFIG_MX6Q
#include mx6_common.h
+#include asm/sizes.h
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
@@ -33,7 +34,7 @@
#define CONFIG_REVISION_TAG
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_LATE_INIT
diff --git a/include/configs/mx6qsabresd.h b/include/configs/mx6qsabresd.h
index 44f07cb..5e561eb 100644
--- a/include/configs/mx6qsabresd.h
+++ b/include/configs/mx6qsabresd.h
@@ -26,6 +26,19 @@
#include mx6qsabre_common.h
+/* Framebuffer */
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_IPUV3
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
