date:20131217

Hi Bo,

On 12/10/2013 09:14 AM, Bo Shen wrote:
 As the cs for spi is worked in gpio mode, so no need to configure
 it as peripheral and then configure to gpio.

That statement may be correct.

 
 Signed-off-by: Bo Shen voice.s...@atmel.com
 ---
 
  arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c |   28 
 +-
  board/atmel/at91sam9x5ek/at91sam9x5ek.c  |1 -
  2 files changed, 6 insertions(+), 23 deletions(-)
 
 diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c 
 b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
 index 6d94572..745dce6 100644
 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
 +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c
 @@ -130,20 +130,12 @@ void at91_spi0_hw_init(unsigned long cs_mask)
   writel(1  ATMEL_ID_SPI0, pmc-pcer);
  
   if (cs_mask  (1  0))
 - at91_set_a_periph(AT91_PIO_PORTA, 14, 0);
 - if (cs_mask  (1  1))
 - at91_set_b_periph(AT91_PIO_PORTA, 7, 0);
 - if (cs_mask  (1  2))
 - at91_set_b_periph(AT91_PIO_PORTA, 1, 0);
 - if (cs_mask  (1  3))
 - at91_set_b_periph(AT91_PIO_PORTB, 3, 0);
 - if (cs_mask  (1  4))
   at91_set_pio_output(AT91_PIO_PORTA, 14, 0);
 - if (cs_mask  (1  5))
 + if (cs_mask  (1  1))
   at91_set_pio_output(AT91_PIO_PORTA, 7, 0);
 - if (cs_mask  (1  6))
 + if (cs_mask  (1  2))
   at91_set_pio_output(AT91_PIO_PORTA, 1, 0);
 - if (cs_mask  (1  7))
 + if (cs_mask  (1  3))
   at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
  }
  
 @@ -159,20 +151,12 @@ void at91_spi1_hw_init(unsigned long cs_mask)
   writel(1  ATMEL_ID_SPI1, pmc-pcer);
  
   if (cs_mask  (1  0))
 - at91_set_b_periph(AT91_PIO_PORTA, 8, 0);
 - if (cs_mask  (1  1))
 - at91_set_b_periph(AT91_PIO_PORTA, 0, 0);
 - if (cs_mask  (1  2))
 - at91_set_b_periph(AT91_PIO_PORTA, 31, 0);
 - if (cs_mask  (1  3))
 - at91_set_b_periph(AT91_PIO_PORTA, 30, 0);
 - if (cs_mask  (1  4))
   at91_set_pio_output(AT91_PIO_PORTA, 8, 0);
 - if (cs_mask  (1  5))
 + if (cs_mask  (1  1))
   at91_set_pio_output(AT91_PIO_PORTA, 0, 0);
 - if (cs_mask  (1  6))
 + if (cs_mask  (1  2))
   at91_set_pio_output(AT91_PIO_PORTA, 31, 0);
 - if (cs_mask  (1  7))
 + if (cs_mask  (1  3))
   at91_set_pio_output(AT91_PIO_PORTA, 30, 0);
  }

But these changes to at91_spiX_hw_init() are wrong!

The point is that we want to set the spi CS line to GPIO or peripheral
mode by the function. Maybe the interface is bad but all of these
functions behave like this. The assumption is that we always have 4 SPI
CS per port, to setup the first one as peripheral we need to give 0x01
as mask, to setup the same CS as GPIO we need to apply offset of 4 bits
- 0x10 mask.

  #endif
 diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c 
 b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
 index 6f67c34..fb74a30 100644
 --- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
 +++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
 @@ -272,7 +272,6 @@ int board_init(void)
  
  #ifdef CONFIG_ATMEL_SPI
   at91_spi0_hw_init(1  0);
 - at91_spi0_hw_init(1  4);

So the correct change would be to remove the first line and leave the
at91_spiX_hw_init() untouched.

  #endif
  
  #ifdef CONFIG_MACB
 

@jagannadh.teki: I grabbed that patch delegated to you @ patchwork.

Best regards

Andreas Bießmann
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Re: [U-Boot] [PATCH 0/3] arm: atmel: clean up for at91sam9x5ek board

Hi Bo,

On 12/10/2013 09:13 AM, Bo Shen wrote:
 This patch series do a clean up for at91sam9x5ek board.

I think this series is to fixup broken things, therefore could be
applied for upcomming release. Can you please provide v1 for 1/3?

 
 Bo Shen (3):
   arm: atmel: at91sam9x5: cleanup cs configure for spi
   arm: atmel: at91sam9x5: cleanup unneeded undef
   arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position
 
  arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c |   28 
 +-
  board/atmel/at91sam9x5ek/at91sam9x5ek.c  |1 -
  include/configs/at91sam9x5ek.h   |   13 +++---
  3 files changed, 9 insertions(+), 33 deletions(-)
 

Best regards

Andreas Bießmann
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[U-Boot] [PATCH][v4] powerpc/mpc85xx: Add support for single source clocking

2013-12-17 Thread Priyanka Jain

Single-source clocking is new feature introduced in T1040.
In this mode, a single differential clock is supplied to the
DIFF_SYSCLK_P/N inputs to the processor, which in turn is
used to supply clocks to the sysclock, ddrclock and usbclock.

So, both ddrclock and syclock are driven by same differential
sysclock in single-source clocking mode whereas in normal clocking
mode, generally separate DDRCLK and SYSCLK pins provides
reference clock for sysclock and ddrclock

DDR_REFCLK_SEL rcw bit is used to determine DDR clock source
-If DDR_REFCLK_SEL rcw bit is 0, then DDR PLLs are driven in
 normal clocking mode by DDR_Reference clock

-If DDR_REFCLK_SEL rcw bit is 1, then DDR PLLs are driven in
 single source clocking mode by DIFF_SYSCLK

Add code to determine ddrclock based on DDR_REFCLK_SEL rcw bit.

Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Priyanka Jain priyanka.j...@freescale.com
---
Changes for v4:
Updated README with CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
description.

Changes for v3:
Incorporated York's comment to move declaration to
beginning of function.

Changes for v2:
Incorporated York's comment to separate out
DDR_CLK_FREQ and SINGLE_SOURCE_CLK code

 README|5 +
 arch/powerpc/cpu/mpc85xx/speed.c  |   25 +++--
 arch/powerpc/include/asm/config_mpc85xx.h |1 +
 arch/powerpc/include/asm/immap_85xx.h |3 +++
 4 files changed, 32 insertions(+), 2 deletions(-)

diff --git a/README b/README
index 8f0b38c..4a3d1c8 100644
--- a/README
+++ b/README
@@ -423,6 +423,11 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space.
 
+   CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+   Single Source Clock is clocking mode present in some of FSL 
SoC's.
+   In this mode, a single differential clock is used to supply
+   clocks to the sysclock, ddrclock and usbclock.
+
 - Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7c7467f..35867df 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -74,12 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+   uint single_src;
+#endif
 
sys_info-freq_systembus = sysclk;
+#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
+   /*
+* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
+* are driven by separate DDR Refclock or single source
+* differential clock.
+*/
+   single_src = (in_be32(gur-rcwsr[5]) 
+ FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) 
+ FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
+   /*
+* For single source clocking, both ddrclock and syclock
+* are driven by differential sysclock.
+*/
+   if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
+   printf(Single Source Clock Configuration\n);
+   sys_info-freq_ddrbus = CONFIG_SYS_CLK_FREQ;
+   } else
+#endif
 #ifdef CONFIG_DDR_CLK_FREQ
-   sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
+   sys_info-freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
-   sys_info-freq_ddrbus = sysclk;
+   sys_info-freq_ddrbus = sysclk;
 #endif
 
sys_info-freq_systembus *= (in_be32(gur-rcwsr[0])  25)  0x1f;
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index 244ccbf..3d8bd9a 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define CONFIG_FM_PLAT_CLK_DIV 1
 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
 #define CONFIG_SYS_FM_MURAM_SIZE   0x3
+#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define CONFIG_SYS_FSL_TBCLK_DIV   16
 #define CONFIG_SYS_FSL_PCIE_COMPAT fsl,qoriq-pcie-v2.4
 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
diff --git a/arch/powerpc/include/asm/immap_85xx.h 
b/arch/powerpc/include/asm/immap_85xx.h
index 672e8c6..68c3c82 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL20x0004
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL10x0002
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL20x0001
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
+#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK0x0011
+#define

[U-Boot] [PATCH v2 1/3] arm: atmel: at91sam9x5: cleanup cs configure for spi

2013-12-17 Thread Bo Shen

As the cs for spi is worked in gpio mode, so no need to configure
it as peripheral and then configure to gpio. Configure it to gpio
directly.

Signed-off-by: Bo Shen voice.s...@atmel.com
---
Change in v2:
  - only move line to configure it to peripheral
---
 board/atmel/at91sam9x5ek/at91sam9x5ek.c |1 -
 1 file changed, 1 deletion(-)

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c 
b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 6f67c34..17a2a40 100644
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -271,7 +271,6 @@ int board_init(void)
 #endif
 
 #ifdef CONFIG_ATMEL_SPI
-   at91_spi0_hw_init(1  0);
at91_spi0_hw_init(1  4);
 #endif
 
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 0/3] arm: atmel: clean up for at91sam9x5ek board

2013-12-17 Thread Bo Shen


Hi Andreas,

On 12/17/2013 05:07 PM, Andreas Bießmann wrote:

Hi Bo,

On 12/10/2013 09:13 AM, Bo Shen wrote:

This patch series do a clean up for at91sam9x5ek board.


I think this series is to fixup broken things, therefore could be
applied for upcomming release. Can you please provide v1 for 1/3?


I have sent v2 for 1/3 of this series.



Bo Shen (3):
   arm: atmel: at91sam9x5: cleanup cs configure for spi
   arm: atmel: at91sam9x5: cleanup unneeded undef
   arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position

  arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c |   28 +-
  board/atmel/at91sam9x5ek/at91sam9x5ek.c  |1 -
  include/configs/at91sam9x5ek.h   |   13 +++---
  3 files changed, 9 insertions(+), 33 deletions(-)



Best regards

Andreas Bießmann



Best Regards,
Bo Shen
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Re: [U-Boot] [PATCH 0/3] arm: atmel: clean up for at91sam9x5ek board

2013-12-17 Thread Bo Shen


Hi Andreas,

On 12/17/2013 05:07 PM, Andreas Bießmann wrote:

Hi Bo,

On 12/10/2013 09:13 AM, Bo Shen wrote:

This patch series do a clean up for at91sam9x5ek board.


I think this series is to fixup broken things, therefore could be
applied for upcomming release. Can you please provide v1 for 1/3?


I have sent v2 for 1/3 of this series.



Bo Shen (3):
   arm: atmel: at91sam9x5: cleanup cs configure for spi
   arm: atmel: at91sam9x5: cleanup unneeded undef
   arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position

  arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c |   28 +-
  board/atmel/at91sam9x5ek/at91sam9x5ek.c  |1 -
  include/configs/at91sam9x5ek.h   |   13 +++---
  3 files changed, 9 insertions(+), 33 deletions(-)



Best regards

Andreas Bießmann



Best Regards,
Bo Shen
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Re: [U-Boot] [PATCH v2] arm: mx5: Add fuse supply enable in fsl_iim

Dear Sergey Alyoshin,

On Tuesday, December 17, 2013 9:17:58 AM, Sergey Alyoshin wrote:
 Enable fuse supply before fuse programming and disable after.
 
 Signed-off-by: Sergey Alyoshin alyoshi...@gmail.com
 Tested-by: Sergey Alyoshin alyoshi...@gmail.com
 
 Tested on i.MX53 custom board by writing MAC addresses in fuse bank 1.

Usually, SoB and other tags are at the end of commit messages, and authors do
not tag their own patches with Tested-by. However, it is possible to add such
information as notes that won't be committed by adding a '---' after the SoB
line above.

 ---
  arch/arm/cpu/armv7/mx5/clock.c   |   12 
  arch/arm/include/asm/arch-mx5/clock.h|1 +
  arch/arm/include/asm/arch-mx5/crm_regs.h |3 +++
  drivers/misc/fsl_iim.c   |   17 -
  4 files changed, 32 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
 index fb3b128..2ca87e4 100644
 --- a/arch/arm/cpu/armv7/mx5/clock.c
 +++ b/arch/arm/cpu/armv7/mx5/clock.c
 @@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
   MXC_CCM_CCGR5_EMI_ENFC(cg));
  }
  
 +#ifdef CONFIG_FSL_IIM
 +void enable_efuse_prog_supply(bool enable)
 +{
 + if (enable)
 + setbits_le32(mxc_ccm-cgpr,
 + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
 + else
 + clrbits_le32(mxc_ccm-cgpr,
 + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
 +}
 +#endif
 +
  /* Config main_bus_clock for periphs */
  static int config_periph_clk(u32 ref, u32 freq)
  {
 diff --git a/arch/arm/include/asm/arch-mx5/clock.h
 b/arch/arm/include/asm/arch-mx5/clock.h
 index 9ee79ae..3db4112 100644
 --- a/arch/arm/include/asm/arch-mx5/clock.h
 +++ b/arch/arm/include/asm/arch-mx5/clock.h
 @@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
  void mxc_set_sata_internal_clock(void);
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  void enable_nfc_clk(unsigned char enable);
 +void enable_efuse_prog_supply(bool enable);
  
  #endif /* __ASM_ARCH_CLOCK_H */
 diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h
 b/arch/arm/include/asm/arch-mx5/crm_regs.h
 index 392881c..efe57e0 100644
 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h
 +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
 @@ -305,6 +305,9 @@ struct mxc_ccm_reg {
  /* Define the bits in register CCDR */
  #define MXC_CCM_CCDR_IPU_HS_MASK (0x1  17)
  
 +/* Define the bits in register CGPR */
 +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE  (1  4)
 +
  /* Define the bits in register CCGRx */
  #define MXC_CCM_CCGR_CG_MASK 0x3
  #define MXC_CCM_CCGR_CG_OFF  0x0
 diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
 index 44ae7b1..8ac4d21 100644
 --- a/drivers/misc/fsl_iim.c
 +++ b/drivers/misc/fsl_iim.c
 @@ -16,6 +16,9 @@
  #ifndef CONFIG_MPC512X
  #include asm/arch/imx-regs.h
  #endif
 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 +#include asm/arch/clock.h
 +#endif
  
  /* FSL IIM-specific constants */
  #define STAT_BUSY0x80
 @@ -93,6 +96,14 @@ struct fsl_iim {
   } bank[8];
  };
  
 +#if !defined(CONFIG_MX51)  !defined(CONFIG_MX53)
 +#define enable_efuse_prog_supply(enable)
 +#endif
 +static void enable_fuse_prog(bool enable)
 +{
 + enable_efuse_prog_supply(enable);
 +}
 +

What I meant in my review is that this enable_fuse_prog() function could just be
removed. I was probably unclear. Here, you just have to keep the #if + #define,
and in the lines below you should just use enable_efuse_prog_supply() instead of
enable_fuse_prog().

  static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int
  assert,
   const char *caller)
  {
 @@ -237,12 +248,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
   if (ret)
   return ret;
  
 + enable_fuse_prog(1);
   for (bit = 0; val; bit++, val = 1)
   if (val  0x01) {
   ret = prog_bit(regs, bank, word, bit);
 - if (ret)
 + if (ret) {
 + enable_fuse_prog(0);
   return ret;
 + }
   }
 + enable_fuse_prog(0);
  
   return 0;
  }
 --
 1.7.10.4

Best regards,
Benoît
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[U-Boot] [PATCH] arm: omap3: Fix beagleboard SPL boot hangup (GPIO clocks not enabled)

2013-12-17 Thread Stefan Roese

Patch f33b9bd3
[arm: omap3: Enable clocks for peripherals only if they are used]
breaks SPL booting on Beagleboard. Since some gpio input's are
read to detect the board revision. But with this patch above, the
clocks to the GPIO subsystems are not enabled per default any more.
The GPIO banks need to be configured specifically now.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
Cc: Michael Trimarchi mich...@amarulasolutions.com
---
 include/configs/omap3_beagle.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 3acb854..1b566c0 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -123,6 +123,9 @@
 #define CONFIG_USB_ETHER_SMSC95XX
 #define CONFIG_USB_ETHER_ASIX
 
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_5/* GPIO128..159 is in GPIO bank 5 */
+#define CONFIG_OMAP3_GPIO_6/* GPIO160..191 is in GPIO bank 6 */
 
 /* commands to include */
 #include config_cmd_default.h
-- 
1.8.4.5

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[U-Boot] [PATCH] arm: omap3: Add cmdline editing feature

2013-12-17 Thread Stefan Roese

This has been missing from beagleboard for quite some time. Add this
now, as its very convenient for the user.

Additionally the 1 is removed after CONFIG_AUTO_COMPLETE. An empty
define is preferred for such compile options.

Signed-off-by: Stefan Roese s...@denx.de
Cc: Tom Rini tr...@ti.com
---
 include/configs/omap3_beagle.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 1b566c0..3dad16a 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -309,7 +309,9 @@
run mmcbootz;  \
fi;  \
 
-#define CONFIG_AUTO_COMPLETE   1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+
 /*
  * Miscellaneous configurable options
  */
-- 
1.8.4.5

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Re: [U-Boot] [PATCH 2/2] mtd: nand: omap: fix ecc ops assignment when changing ecc

2013-12-17 Thread Nikita Kiryanov


On 12/17/2013 01:03 AM, Scott Wood wrote:

On Mon, 2013-12-16 at 19:19 +0200, Nikita Kiryanov wrote:

If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:

If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.

Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().

Cc: Scott Wood scottw...@freescale.com
Cc: Pekon Gupta pe...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
  drivers/mtd/nand/omap_gpmc.c | 13 +
  1 file changed, 13 insertions(+)

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fda1df2..19dcd45 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -765,6 +765,19 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
int eccsteps = pagesize / SECTOR_BYTES;
int i;

+   nand-ecc.calculate = NULL;
+   nand-ecc.correct = NULL;
+   nand-ecc.hwctl = NULL;
+   nand-ecc.read_oob = NULL;
+   nand-ecc.read_oob_raw = NULL;
+   nand-ecc.read_page = NULL;
+   nand-ecc.read_page_raw = NULL;
+   nand-ecc.read_subpage = NULL;
+   nand-ecc.write_oob = NULL;
+   nand-ecc.write_oob_raw = NULL;
+   nand-ecc.write_page = NULL;
+   nand-ecc.write_page_raw = NULL;
+
switch (ecc_scheme) {
case OMAP_ECC_HAM1_CODE_SW:
debug(nand: selected OMAP_ECC_HAM1_CODE_SW\n);


This will leave you with a broken nand-ecc if the function returns an
error.  Instead, each case in the switch should NULL out whichever
members it is not initializing (or perhaps just memset it, once past the
error checks).


Yes you're right. Guess I should've resisted doing a last minue
refactor. V2 coming up.



-Scott





--
Regards,
Nikita.
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[U-Boot] [PATCH V2 2/2] mtd: nand: omap: fix ecc ops assignment when changing ecc

2013-12-17 Thread Nikita Kiryanov

If we change to software ecc and then back to hardware ecc, the nand ecc ops
pointers are populated with incorrect function pointers. This is related to the
way nand_scan_tail() handles assigning functions to ecc ops:

If we are switching to software ecc/no ecc, it assigns default functions to the
ecc ops pointers unconditionally, but if we are switching to hardware ecc,
the default hardware ecc functions are assigned to ops pointers only if these
pointers are NULL (so that drivers could set their own functions). In the case
of omap_gpmc.c driver, when we switch to sw ecc, sw ecc functions are
assigned to ecc ops by nand_scan_tail(), and when we later switch to hw ecc,
the ecc ops pointers are not NULL, so nand_scan_tail() does not overwrite
them with hw ecc functions.
The result: sw ecc functions used to write hw ecc data.

Clear the ecc ops pointers in omap_gpmc.c when switching ecc types, so that
ops which were not assigned by the driver will get the correct default values
from nand_scan_tail().

Cc: Scott Wood scottw...@freescale.com
Cc: Pekon Gupta pe...@ti.com
Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
---
Changes in V2:
- Clear the ops after error checks, not before.
- Use memset on ecc struct to clear the ops.

 drivers/mtd/nand/omap_gpmc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/nand/omap_gpmc.c b/drivers/mtd/nand/omap_gpmc.c
index fda1df2..37822bc 100644
--- a/drivers/mtd/nand/omap_gpmc.c
+++ b/drivers/mtd/nand/omap_gpmc.c
@@ -789,6 +789,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
bch_priv.control= NULL;
bch_priv.type   = 0;
/* populate ecc specific fields */
+   memset(nand-ecc, 0, sizeof(struct nand_ecc_ctrl));
nand-ecc.mode  = NAND_ECC_HW;
nand-ecc.strength  = 1;
nand-ecc.size  = SECTOR_BYTES;
@@ -827,6 +828,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
}
bch_priv.type = ECC_BCH8;
/* populate ecc specific fields */
+   memset(nand-ecc, 0, sizeof(struct nand_ecc_ctrl));
nand-ecc.mode  = NAND_ECC_HW;
nand-ecc.strength  = 8;
nand-ecc.size  = SECTOR_BYTES;
@@ -869,6 +871,7 @@ static int omap_select_ecc_scheme(struct nand_chip *nand,
elm_init();
bch_priv.type   = ECC_BCH8;
/* populate ecc specific fields */
+   memset(nand-ecc, 0, sizeof(struct nand_ecc_ctrl));
nand-ecc.mode  = NAND_ECC_HW;
nand-ecc.strength  = 8;
nand-ecc.size  = SECTOR_BYTES;
-- 
1.8.1.2

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Re: [U-Boot] [PATCH v2] arm: ep9315: Return back Cirrus Logic EDB9315A board support

2013-12-17 Thread sergey kostanbaev

Hi Albert,

I modified the patch, but it didn't worked on the board. Than I
realized the cause of this problem is in interrupt_init() function. It
has IRQ_STACK_START_IN variable touched before relocation, which is in
flash.

Later I found other guys had same problem. So if it's going to be
fixed my patch works ok. I'll send it right away.

Maybe as a hack just to add a special #define for now just not to
break other platform?

Best Regards,
Sergey


On Mon, Dec 2, 2013 at 9:30 PM, Albert ARIBAUD
albert.u.b...@aribaud.net wrote:
 Hi sergey.kostanbaev,

 On Tue, 22 Oct 2013 17:18:45 +0400, sergey.kostanbaev
 sergey.kostanb...@gmail.com wrote:

 From: Sergey Kostanbaev sergey.kostanb...@gmail.com

 This patch returns back support for old ep93xx processors family

 Signed-off-by: Sergey Kostanbaev sergey.kostanb...@fairwaves.ru
 Cc: albert.u.b...@aribaud.net
 ---

 This patch seems not to apply cleanly on current ARM. Can you rebase
 and send V3?

 Amicalement,
 --
 Albert.
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[U-Boot] [PATCH v3] arm: ep9315: Return back Cirrus Logic EDB9315A board support

2013-12-17 Thread sergey.kostanbaev

From: Sergey Kostanbaev sergey.kostanb...@gmail.com

This patch returns back support for old ep93xx processors family

Signed-off-by: Sergey Kostanbaev sergey.kostanb...@fairwaves.ru
Cc: albert.u.b...@aribaud.net
---
Changes for v3:
- Update makefiles to the new style

Changes for v2:
- Replace constants in lowlevel_init.S to defines
- Add more coments in non-trivial places in lowlevel_init.S
- Get rid of ep93xx_sdram_find_bank in lowlevel_init.S and
  move it to dram_fill_bank_addr in edb93xx.c. This procedure
  may be executed later at any time, so no need to be in lowlevel

 arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S | 465 ++--
 arch/arm/include/asm/arch-ep93xx/ep93xx.h   |  86 +
 board/cirrus/edb93xx/Makefile   |  37 +++
 board/cirrus/edb93xx/edb93xx.c  | 382 +++
 board/cirrus/edb93xx/u-boot.lds | 106 +++
 boards.cfg  |   1 +
 drivers/spi/Makefile|   1 +
 drivers/spi/ep93xx_spi.c| 274 
 drivers/usb/host/Makefile   |   1 +
 drivers/usb/host/ohci-ep93xx.c  |  38 +++
 include/configs/edb93xx.h   | 292 +
 11 files changed, 1654 insertions(+), 29 deletions(-)
 create mode 100644 board/cirrus/edb93xx/Makefile
 create mode 100644 board/cirrus/edb93xx/edb93xx.c
 create mode 100644 board/cirrus/edb93xx/u-boot.lds
 create mode 100644 drivers/spi/ep93xx_spi.c
 create mode 100644 drivers/usb/host/ohci-ep93xx.c
 create mode 100644 include/configs/edb93xx.h

diff --git a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S 
b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
index bf2fa2a..3ac0f88 100644
--- a/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ep93xx/lowlevel_init.S
@@ -1,49 +1,456 @@
 /*
  * Low-level initialization for EP93xx
  *
- * Copyright (C) 2009 Matthias Kaehlcke matth...@kaehlcke.net
+ * Copyright (C) 2013
+ * Sergey Kostanabev sergey.kostanbaev at fairwaves.ru
  *
- * Copyright (C) 2006 Dominic Rath dominic.r...@gmx.de
+ * Copyright (C) 2006 Cirrus Logic Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include version.h
-#include asm/arch/ep93xx.h
+#include config.h
+#include asm/arch-ep93xx/ep93xx.h
+
+/*
+/* Configure the SDRAM based on the supplied settings.
+ *
+ * Input:  r0 - SDRAM DEVCFG register
+ * r2 - configuration for SDRAM chips
+ * Output: none
+ * Modifies:   r3, r4
+ */
+ep93xx_sdram_config:
+   /* Program the SDRAM device configuration register. */
+   ldr r3, =SDRAM_BASE
+#ifdef CONFIG_EDB93XX_SDCS0
+   str r0, [r3, #SDRAM_OFF_DEVCFG0]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS1
+   str r0, [r3, #SDRAM_OFF_DEVCFG1]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS2
+   str r0, [r3, #SDRAM_OFF_DEVCFG2]
+#endif
+#ifdef CONFIG_EDB93XX_SDCS3
+   str r0, [r3, #SDRAM_OFF_DEVCFG3]
+#endif
+
+   /* Set the Initialize and MRS bits (issue continuous NOP commands
+* (INIT  MRS set))
+*/
+   ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+   EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
+   EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+   str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+   /* Delay for 200us. */
+   mov r4, #0x3000
+delay1:
+   subsr4, r4, #1
+   bne delay1
+
+   /* Clear the MRS bit to issue a precharge all. */
+   ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
+   EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
+   str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+   /* Temporarily set the refresh timer to 0x10. Make it really low so
+* that refresh cycles are generated.
+*/
+   ldr r4, =0x10
+   str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+   /* Delay for at least 80 SDRAM clock cycles. */
+   mov r4, #80
+delay2:
+   subsr4, r4, #1
+   bne delay2
+
+   /* Set the refresh timer to the fastest required for any device
+* that might be used. Set 9.6 ms refresh time.
+*/
+   ldr r4, =0x01e0
+   str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
+
+   /* Select mode register update mode. */
+   ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
+   EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
+   str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+   /* Program the mode register on the SDRAM by performing fake read */
+   ldr r4, [r2]
+
+   /* Select normal operating mode. */
+   ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
+   str r4, [r3, #SDRAM_OFF_GLCONFIG]
+
+   /* Return to the caller. */
+   mov pc, lr
+
+/*
+ * Test to see if the SDRAM has been configured in a usable mode.
+ *
+ * Input:  r0 - Test address of SDRAM
+ * Output: r0 - 0 -- Test OK, -1 -- Failed

Re: [U-Boot] i.MX6 freeze when running Linux FSL 3.10.9-1.0.0-alpha AND U-Boot 2013.10

Hi Otavio,

On Tue, Nov 26, 2013 at 1:59 PM, Otavio Salvador
ota...@ossystems.com.br wrote:

 isn't the last change (enabling bypass) sufficient to fix the problem
 or do you also need the 2 power_down before ?

 It does indeed. I did a full test cycle from cold boot and also from
 inside system reboot and it works.

What do you get on your board when you do?

= md.l 0x20c8140  1

Regards,

Fabio Estevam
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Re: [U-Boot] i.MX6 freeze when running Linux FSL 3.10.9-1.0.0-alpha AND U-Boot 2013.10

On Tue, Dec 17, 2013 at 12:18 PM, Fabio Estevam feste...@gmail.com wrote:
 Hi Otavio,

 On Tue, Nov 26, 2013 at 1:59 PM, Otavio Salvador
 ota...@ossystems.com.br wrote:

 isn't the last change (enabling bypass) sufficient to fix the problem
 or do you also need the 2 power_down before ?

 It does indeed. I did a full test cycle from cold boot and also from
 inside system reboot and it works.

 What do you get on your board when you do?

 = md.l 0x20c8140  1

Just to clarify, please run the command above with the original
U-boot, ie, without your workaround of setting the ldo bypass mode.

Regards,

Fabio Estevam
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[U-Boot] [PATCH v3] arm: mx5: Add fuse supply enable in fsl_iim

2013-12-17 Thread Sergey Alyoshin

Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin alyoshi...@gmail.com
---
 arch/arm/cpu/armv7/mx5/clock.c   |   12 
 arch/arm/include/asm/arch-mx5/clock.h|1 +
 arch/arm/include/asm/arch-mx5/crm_regs.h |3 +++
 drivers/misc/fsl_iim.c   |   17 -
 4 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index fb3b128..2ca87e4 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
MXC_CCM_CCGR5_EMI_ENFC(cg));
 }
 
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+   if (enable)
+   setbits_le32(mxc_ccm-cgpr,
+   MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+   else
+   clrbits_le32(mxc_ccm-cgpr,
+   MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
diff --git a/arch/arm/include/asm/arch-mx5/clock.h 
b/arch/arm/include/asm/arch-mx5/clock.h
index 9ee79ae..3db4112 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
 void mxc_set_sata_internal_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h 
b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 392881c..efe57e0 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -305,6 +305,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK   (0x1  17)
 
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(1  4)
+
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK   0x3
 #define MXC_CCM_CCGR_CG_OFF0x0
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 44ae7b1..8ac4d21 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -16,6 +16,9 @@
 #ifndef CONFIG_MPC512X
 #include asm/arch/imx-regs.h
 #endif
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include asm/arch/clock.h
+#endif
 
 /* FSL IIM-specific constants */
 #define STAT_BUSY  0x80
@@ -93,6 +96,14 @@ struct fsl_iim {
} bank[8];
 };
 
+#if !defined(CONFIG_MX51)  !defined(CONFIG_MX53)
+#define enable_efuse_prog_supply(enable)
+#endif
+static void enable_fuse_prog(bool enable)
+{
+   enable_efuse_prog_supply(enable);
+}
+
 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int 
assert,
const char *caller)
 {
@@ -237,12 +248,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
if (ret)
return ret;
 
+   enable_fuse_prog(1);
for (bit = 0; val; bit++, val = 1)
if (val  0x01) {
ret = prog_bit(regs, bank, word, bit);
-   if (ret)
+   if (ret) {
+   enable_fuse_prog(0);
return ret;
+   }
}
+   enable_fuse_prog(0);
 
return 0;
 }
-- 
1.7.10.4

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Re: [U-Boot] arm: keep all sections in ELF file breaks Arndale

2013-12-17 Thread Tom Rini

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 12/17/2013 10:24 AM, Andre Przywara wrote:
 Hi,
 
 the Arndale board does not work anymore with current master HEAD.
 If I turn on the board, I see exactly nothing.
 
 I bisected it down to:
 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 is the first bad commit
 commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7
 Author: Albert ARIBAUD albert.u.b...@aribaud.net
 Date:   Thu Nov 7 14:21:46 2013 +0100
 
 arm: keep all sections in ELF file
 
 That patch looks like Chinese to me, does one of you have an idea what's
 wrong here?
 Are we missing a section, maybe for the SPL build?

So on Arndale, what file do you boot exactly?  It sounds like not
u-boot.img but some tool stripping / modifying u-boot (or
spl/u-boot-spl) and having relied on certain sections being stripped out
before being run.

- -- 
Tom
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJSsG4KAAoJENk4IS6UOR1Wd0gP/jve70MGVIbZ7I6ZNVfBMXlC
kUCrbskbSSNhLvp+prf7X4YGAqGkqzHm2kbdPS1BC3nEDbpJxvQodN1DYDat8I9U
7Et3fMLqpWzRSs/8FyN6ISDfo/hn4DSKKLRlHi/sg4RWYhDWIfwNByyVN2Hcpicb
grUqz27GoJbTWld8ojkDCRILYS22RgCXQCdpnDvDv+a1Yvx6pb2/etH2VykOnFdN
FVz0vHr7ecGbDgLuK7elKR0aJhyXkU8z6w2TAW713d+MkXkuHytbO8d4DtIysRrj
L7quOdVH5qWyY8UivMZbSWU/UfExu6lGF8HhzlebWc2x80Ghhyxyc8i0/PpmEL20
n5rrBAAPNBKbbN5YlhZ4XnXIbp8o9FFI6rvXj/Gx6sfbU14BtYkkYnc5IeEz2RcK
dMXYycAdp+7ZzYoMGUYOBR+GCTQ38f0ZFJgkOlmYgShPYEHDMNrW40SKm2zR7xPR
LpQ/YI1XzkuAdoQ6+Plx/Felf5KTS8ul3y55PqWPr8UFcFCggG84WL/aTOsVxCnL
6CM7h4RY0ainSHUw431JoPdILcYQIbJz84vo8hOoIdlXX3+dffSHH0g6Eg4QRHEO
75UK0JMXCHUhg519dy8OEPYwi8jZOlDyx+lEqbhaTYorXxYJzCZmTOpWFVarix7c
fhyXLvN+llrt1v3mjgbb
=siI2
-END PGP SIGNATURE-
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[U-Boot] arm: keep all sections in ELF file breaks Arndale

2013-12-17 Thread Andre Przywara


Hi,

the Arndale board does not work anymore with current master HEAD.
If I turn on the board, I see exactly nothing.

I bisected it down to:
47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 is the first bad commit
commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7
Author: Albert ARIBAUD albert.u.b...@aribaud.net
Date:   Thu Nov 7 14:21:46 2013 +0100

arm: keep all sections in ELF file

That patch looks like Chinese to me, does one of you have an idea what's 
wrong here?

Are we missing a section, maybe for the SPL build?

Regards,
Andre.
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Re: [U-Boot] [PATCH] arm: omap3: Add cmdline editing feature

2013-12-17 Thread Tom Rini

On Tue, Dec 17, 2013 at 02:14:18PM +0100, Stefan Roese wrote:

 This has been missing from beagleboard for quite some time. Add this
 now, as its very convenient for the user.
 
 Additionally the 1 is removed after CONFIG_AUTO_COMPLETE. An empty
 define is preferred for such compile options.
 
 Signed-off-by: Stefan Roese s...@denx.de
 Cc: Tom Rini tr...@ti.com
 ---
  include/configs/omap3_beagle.h | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)
 
 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
 index 1b566c0..3dad16a 100644
 --- a/include/configs/omap3_beagle.h
 +++ b/include/configs/omap3_beagle.h
 @@ -309,7 +309,9 @@
   run mmcbootz;  \
   fi;  \
  
 -#define CONFIG_AUTO_COMPLETE 1
 +#define CONFIG_AUTO_COMPLETE
 +#define CONFIG_CMDLINE_EDITING
 +
  /*
   * Miscellaneous configurable options
   */

I'm fine with this concept, but it shouldn't be needed with Enric's
series to move omap3 to ti_armv7_common.h

-- 
Tom


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Re: [U-Boot] [PATCH v3] arm: mx5: Add fuse supply enable in fsl_iim

Dear Sergey Alyoshin,

On Tuesday, December 17, 2013 3:51:00 PM, Sergey Alyoshin wrote:
[...]
 +#if !defined(CONFIG_MX51)  !defined(CONFIG_MX53)
 +#define enable_efuse_prog_supply(enable)
 +#endif
 +static void enable_fuse_prog(bool enable)
 +{
 + enable_efuse_prog_supply(enable);
 +}
 +

Er, this is like in v2. See my comment here for v2.

Best regards,
Benoît
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Re: [U-Boot] arm: keep all sections in ELF file breaks Arndale

2013-12-17 Thread Tom Rini

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 12/17/2013 10:47 AM, Andre Przywara wrote:
 (CCing Inderpal, Chander and Minkyu)
 
 On 12/17/2013 04:30 PM, Tom Rini wrote:
 On 12/17/2013 10:24 AM, Andre Przywara wrote:
 Hi,

 the Arndale board does not work anymore with current master HEAD.
 If I turn on the board, I see exactly nothing.

 I bisected it down to:
 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 is the first bad commit
 commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7
 Author: Albert ARIBAUD albert.u.b...@aribaud.net
 Date:   Thu Nov 7 14:21:46 2013 +0100

  arm: keep all sections in ELF file

 That patch looks like Chinese to me, does one of you have an idea what's
 wrong here?
 Are we missing a section, maybe for the SPL build?
 
 So on Arndale, what file do you boot exactly?  It sounds like not
 u-boot.img but some tool stripping / modifying u-boot (or
 spl/u-boot-spl) and having relied on certain sections being stripped out
 before being run.
 
 Good point. Indeed I boot u-boot-dtb.bin (the SPL is
 spl/arndale-spl.bin). So the Makefile does:
 cat u-boot.bin u-boot.dtb u-boot-dtb.bin
 
 I guess the address under which U-boot expects to find the attached dtb
 changes due to the non-discarding.
 
 Does any of the Arndale people have an idea how to fix this?

That's a little confusing as we use objcopy -O binary to make
u-boot.bin/u-boot-spl.bin and that would, I would think, drop these
sections anyhow.  But some checking of binary size with the patch in
question locally reverted would help shed some light here.

- -- 
Tom
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJSsHR8AAoJENk4IS6UOR1W+7MQALP3dn79SRWgTTxHQ1SVMUbB
FC0mVsupa296m5WfcDRPkijtZecAeTkFGVmizTSqjLepKhV5Tnqy4uQePhwxwdcg
v9oC5/hq7NXuJIB+bzUyc05kznrBqqJ4nyS7FGJDZNmXYhbtt6BdUDSrPMVX1eLk
TkPPZ1ksD2oyJL8el/f8LlQRrKu68GaJY63qdvgFtRfGaQ+OuRYLJZ6ow3IZDbuu
+Cl9easvbEaq/db/t2U72s5VozGyMgx855w+aU9eZW7OmS2pSpSjETx3VBRW8vDv
HsHKFwykHOtajp644oGEQHvUA7PWZdPsfFOh38POp+7x5YYYNSdNO3D0yZ0PmzrD
E7w6p4bWUlZK/xQ3Bi5BYKI4Ps+0Rf64fGUHc13ML9P0aG4quNHDhHm98UT9EEWD
ZoJLRccoGvZjGNonz/Q8Hx18NWBfcFpwSFHhxMGUGfWiyjSDwaiplpXHujcOXlSC
zZQs7WT4vPfaWsTdpyaREEZ+4W6nJgf2Zyaakdn/ul+6EUjERrHEvVIe9RrsG7Ut
NsOCk0P0txWW+gEHrViorNL6n142Fb/0gwhJnAvUmpvPqOZlQqaDvE998/PzBWmi
E7cY+CEktxaTHGFWsSo/QYS+AUZBx1k7Oq+yKnFXn+pvLnnr4Z9qF2cF/RByJ2v3
1vBudkiMaREUsuKm6H6x
=aMwD
-END PGP SIGNATURE-
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Re: [U-Boot] arm: keep all sections in ELF file breaks Arndale

2013-12-17 Thread Andre Przywara


(CCing Inderpal, Chander and Minkyu)

On 12/17/2013 04:30 PM, Tom Rini wrote:

-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 12/17/2013 10:24 AM, Andre Przywara wrote:

Hi,

the Arndale board does not work anymore with current master HEAD.
If I turn on the board, I see exactly nothing.

I bisected it down to:
47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7 is the first bad commit
commit 47ed5dd031d7d2c587e6afd386e79ccec1a1b7f7
Author: Albert ARIBAUD albert.u.b...@aribaud.net
Date:   Thu Nov 7 14:21:46 2013 +0100

 arm: keep all sections in ELF file

That patch looks like Chinese to me, does one of you have an idea what's
wrong here?
Are we missing a section, maybe for the SPL build?


So on Arndale, what file do you boot exactly?  It sounds like not
u-boot.img but some tool stripping / modifying u-boot (or
spl/u-boot-spl) and having relied on certain sections being stripped out
before being run.


Good point. Indeed I boot u-boot-dtb.bin (the SPL is 
spl/arndale-spl.bin). So the Makefile does:

cat u-boot.bin u-boot.dtb u-boot-dtb.bin

I guess the address under which U-boot expects to find the attached dtb 
changes due to the non-discarding.


Does any of the Arndale people have an idea how to fix this?

Regards,
Andre.



- --
Tom
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.11 (GNU/Linux)
Comment: Using GnuPG with Thunderbird - http://www.enigmail.net/

iQIcBAEBAgAGBQJSsG4KAAoJENk4IS6UOR1Wd0gP/jve70MGVIbZ7I6ZNVfBMXlC
kUCrbskbSSNhLvp+prf7X4YGAqGkqzHm2kbdPS1BC3nEDbpJxvQodN1DYDat8I9U
7Et3fMLqpWzRSs/8FyN6ISDfo/hn4DSKKLRlHi/sg4RWYhDWIfwNByyVN2Hcpicb
grUqz27GoJbTWld8ojkDCRILYS22RgCXQCdpnDvDv+a1Yvx6pb2/etH2VykOnFdN
FVz0vHr7ecGbDgLuK7elKR0aJhyXkU8z6w2TAW713d+MkXkuHytbO8d4DtIysRrj
L7quOdVH5qWyY8UivMZbSWU/UfExu6lGF8HhzlebWc2x80Ghhyxyc8i0/PpmEL20
n5rrBAAPNBKbbN5YlhZ4XnXIbp8o9FFI6rvXj/Gx6sfbU14BtYkkYnc5IeEz2RcK
dMXYycAdp+7ZzYoMGUYOBR+GCTQ38f0ZFJgkOlmYgShPYEHDMNrW40SKm2zR7xPR
LpQ/YI1XzkuAdoQ6+Plx/Felf5KTS8ul3y55PqWPr8UFcFCggG84WL/aTOsVxCnL
6CM7h4RY0ainSHUw431JoPdILcYQIbJz84vo8hOoIdlXX3+dffSHH0g6Eg4QRHEO
75UK0JMXCHUhg519dy8OEPYwi8jZOlDyx+lEqbhaTYorXxYJzCZmTOpWFVarix7c
fhyXLvN+llrt1v3mjgbb
=siI2
-END PGP SIGNATURE-



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Re: [U-Boot] [PATCH 1/2] i.MX6 (DQ/DLS): use macros for mux and pad declarations

On 14/11/2013 00:36, Eric Nelson wrote:
 This allows the use of either or both declarations from
 the files mx6q_pins.h and mx6dl_pins.h.
 
 All board files should include asm/arch/mx6-pins.h
 with one of the following defined in boards.cfg
 MX6Q   - for boards targeting i.MX6Q or i.MX6D
 MX6DL  - for boards targeting i.MX6DL
 MX6S   - for boards targeting i.MX6S
 MX6QDL - for boards that support any of the above with
  run-time detection
 
 Pad declarations will be MX6_PAD_x for single-variant boards
 and MX6Q_PAD_x and MX6DL_PAD_x for boards supporting both
 processor classes.
 
 Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
 ---

Applied to u-boot-imx, sorry for delay.

Best regards,
Stefano Babic


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Re: [U-Boot] [U-Boot,v2,1/3] arm: atmel: at91sam9x5: cleanup cs configure for spi

Dear Bo Shen,

Bo Shen voice.s...@atmel.com writes:
As the cs for spi is worked in gpio mode, so no need to configure
it as peripheral and then configure to gpio. Configure it to gpio
directly.

Signed-off-by: Bo Shen voice.s...@atmel.com

---
Change in v2:
  - only move line to configure it to peripheral
---
 board/atmel/at91sam9x5ek/at91sam9x5ek.c |1 -
 1 file changed, 1 deletion(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot,2/3] arm: atmel: at91sam9x5: cleanup unneeded undef

Dear Bo Shen,

Bo Shen voice.s...@atmel.com writes:
remove unneeded #undef for at91sam9x5ek board.

Signed-off-by: Bo Shen voice.s...@atmel.com

---
include/configs/at91sam9x5ek.h |5 -
 1 file changed, 5 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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Re: [U-Boot] [U-Boot, 3/3] arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position

Dear Bo Shen,

Bo Shen voice.s...@atmel.com writes:
In config_cmd_default.h, it will use CONFIG_SYS_NO_FLASH to decide
whether include CONFIG_CMD_FLASH and CONFIG_CMD_IMLS. So, move the
CONFIG_SYS_NO_FLASH to proper position, then we don't need to undef
these two commands.

Signed-off-by: Bo Shen voice.s...@atmel.com

---
include/configs/at91sam9x5ek.h |8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

applied to u-boot-atmel/master, thanks!

Best regards,
Andreas Bießmann
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[U-Boot] [PULL] u-boot-atmel/master - u-boot-arm/master

Dear Albert Aribaud,

please pull the following fix ups from u-boot-atmel/master into
u-boot-arm/master.

The following changes since commit d2c7074b9593d822e2359a09c21747248fdf5fac:

  ARM: OMAP5: clocks: Update MPU settings for OPP_NOM (2013-12-12 17:43:39 
-0500)

are available in the git repository at:

  git://git.denx.de/u-boot-atmel.git master

for you to fetch changes up to d51a2a2d63d83207b56a7aef7a191d081058d6ae:

  arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position 
(2013-12-17 17:21:18 +0100)


Bo Shen (3):
  arm: atmel: at91sam9x5: cleanup cs configure for spi
  arm: atmel: at91sam9x5: cleanup unneeded undef
  arm: atmel: at91sam9x5: move CONFIG_SYS_NO_FLASH to proper position

 board/atmel/at91sam9x5ek/at91sam9x5ek.c |1 -
 include/configs/at91sam9x5ek.h  |   13 +++--
 2 files changed, 3 insertions(+), 11 deletions(-)
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Re: [U-Boot] [PATCH v4 0/1] nitrogen6x: Move setup_sata to common part

On 28/11/2013 12:32, Giuseppe Pagano wrote:
 Move setup_sata function definition from platform file nitrogen6x.c
 to arch/arm/imx-common/sata.c to avoid code duplication.
 
 Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
 CC: Stefano Babic sba...@denx.de
 CC: Fabio Estevam fabio.este...@freescale.com
 CC: Eric Nelson eric.nel...@boundarydevices.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH v4 1/1] udoo: Add SATA support on uDoo Board.

On 28/11/2013 12:32, Giuseppe Pagano wrote:
 Add SATA support on uDoo Board.
 
 Signed-off-by: Giuseppe Pagano giuseppe.pag...@seco.com
 CC: Stefano Babic sba...@denx.de
 CC: Fabio Estevam fabio.este...@freescale.com
 ---
 


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH] configs: imx: Remove CONFIG_SYS_SPD_BUS_NUM option

On 20/11/2013 23:38, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 According to the README:
 
 - CONFIG_SYS_SPD_BUS_NUM
   If SPD EEPROM is on an I2C bus other than the first
   one, specify here. Note that the value must resolve
   to something your driver can deal with.
 
 There is no SPD EEPROM on the imx boards, so ged rid of this option.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH 1/1] MX6 SabreSD: Use readl() to read the CCM_CCGR3 register

On 29/11/2013 15:38, Liu Ying wrote:
 Align with the context to use readl() to read the CCM_CCGR3
 register with memory barrier instead of __raw_readl().
 
 Signed-off-by: Liu Ying ying@freescale.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH] ARM: mx53: video: Add IPUv3 LCD support for M53EVK

On 02/12/2013 17:01, Marek Vasut wrote:
 This patch adds support for the AMPIRE 800x480 LCD panel that is available
 for M53EVK.
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Stefano Babic sba...@denx.de
 ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH] ARM: mx6: Update non-Freescale boards to include CPU errata.

On 27/11/2013 01:40, Eric Nelson wrote:
 The CPU errata expressed in include/configs/mx6_common.h apply
 to all i.MX6DQ and i.MX6DLS parts.
 
 Signed-off-by: Eric Nelson eric.nel...@boundarydevices.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic


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Re: [U-Boot] [PATCH v2] mx6: clock: Fix the calculation of PLL_ENET frequency

On 03/12/2013 21:26, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 According to the mx6 quad reference manual, the DIV_SELECT field of register
 CCM_ANALOG_PLL_ENETn has the following meaning:
 
 Controls the frequency of the ethernet reference clock.
 - 00 - 25MHz
 - 01 - 50MHz
 - 10 - 100MHz
 - 11 - 125MHz
 
 Current logic does not handle the 25MHz case correctly, so fix it.
 
 Signed-off-by: Rabeeh Khoury rab...@solid-run.com
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH v3 2/2] mx6sabresd: Fix LVDS width and color format

On 04/12/2013 04:08, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 mx6sabresd boards have a 18-bit LVDS data width and the correct color format
 is RGB666.
 
 Suggested-by: Liu Ying ying@freescale.com
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH v3 1/2] mx6sabresd: Allow probing HSYNC, VSYNC and DISP_CLK signals

On 04/12/2013 04:08, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 HSYNC, VSYNC and DISP_CLK are very useful display signals for debugging.
 
 Configure them as active pins.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH] ARM: mxs: tools: Fix errno handling in strtoul() invocation

On 04/12/2013 14:27, Marek Vasut wrote:
 According to NOTE in strtoul(3), the errno must be zeroed before strtoul()
 is called. Zero the errno. The NOTE reads as such:
 
   Since strtoul() can legitimately return 0 or ULONG_MAX (ULLONG_MAX for
   strtoull()) on both success and failure, the calling program should set
   errno  to  0  before the call, and then determine if an error occurred
   by checking whether errno has a nonzero value after the call.
 
 This issue was detected on Fedora 19 with glibc 2.17 .
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Stefano Babic sba...@denx.de
 Cc: Tom Rini tr...@ti.com
 ---


Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH 1/1] imx6: fix random hang when download by usb

On 13/11/2013 17:58, Frank Li wrote:
 ROM did not invalidate L1 cache when download by usb
 Need invalidate L1 cache before enable cache
 
 Signed-off-by: Huang yongcai b20...@freescale.com
 Signed-off-by: Frank Li frank...@freescale.com
 ---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic



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Re: [U-Boot] [PATCH v4] arm: mx5: Add fuse supply enable in fsl_iim

Dear Sergey Alyoshin,

On Tuesday, December 17, 2013 8:24:54 PM, Sergey Alyoshin wrote:
 Enable fuse supply before fuse programming and disable after.
 
 Signed-off-by: Sergey Alyoshin alyoshi...@gmail.com
 ---
  arch/arm/cpu/armv7/mx5/clock.c   |   12 
  arch/arm/include/asm/arch-mx5/clock.h|1 +
  arch/arm/include/asm/arch-mx5/crm_regs.h |3 +++
  drivers/misc/fsl_iim.c   |   13 -
  4 files changed, 28 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
 index fb3b128..2ca87e4 100644
 --- a/arch/arm/cpu/armv7/mx5/clock.c
 +++ b/arch/arm/cpu/armv7/mx5/clock.c
 @@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
   MXC_CCM_CCGR5_EMI_ENFC(cg));
  }
  
 +#ifdef CONFIG_FSL_IIM
 +void enable_efuse_prog_supply(bool enable)
 +{
 + if (enable)
 + setbits_le32(mxc_ccm-cgpr,
 + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
 + else
 + clrbits_le32(mxc_ccm-cgpr,
 + MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
 +}
 +#endif
 +
  /* Config main_bus_clock for periphs */
  static int config_periph_clk(u32 ref, u32 freq)
  {
 diff --git a/arch/arm/include/asm/arch-mx5/clock.h
 b/arch/arm/include/asm/arch-mx5/clock.h
 index 9ee79ae..3db4112 100644
 --- a/arch/arm/include/asm/arch-mx5/clock.h
 +++ b/arch/arm/include/asm/arch-mx5/clock.h
 @@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
  void mxc_set_sata_internal_clock(void);
  int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
  void enable_nfc_clk(unsigned char enable);
 +void enable_efuse_prog_supply(bool enable);
  
  #endif /* __ASM_ARCH_CLOCK_H */
 diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h
 b/arch/arm/include/asm/arch-mx5/crm_regs.h
 index 392881c..efe57e0 100644
 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h
 +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
 @@ -305,6 +305,9 @@ struct mxc_ccm_reg {
  /* Define the bits in register CCDR */
  #define MXC_CCM_CCDR_IPU_HS_MASK (0x1  17)
  
 +/* Define the bits in register CGPR */
 +#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE  (1  4)
 +
  /* Define the bits in register CCGRx */
  #define MXC_CCM_CCGR_CG_MASK 0x3
  #define MXC_CCM_CCGR_CG_OFF  0x0
 diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
 index 44ae7b1..36433a7 100644
 --- a/drivers/misc/fsl_iim.c
 +++ b/drivers/misc/fsl_iim.c
 @@ -16,6 +16,9 @@
  #ifndef CONFIG_MPC512X
  #include asm/arch/imx-regs.h
  #endif
 +#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
 +#include asm/arch/clock.h
 +#endif
  
  /* FSL IIM-specific constants */
  #define STAT_BUSY0x80
 @@ -93,6 +96,10 @@ struct fsl_iim {
   } bank[8];
  };
  
 +#if !defined(CONFIG_MX51)  !defined(CONFIG_MX53)
 +#define enable_efuse_prog_supply(enable)
 +#endif
 +
  static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int
  assert,
   const char *caller)
  {
 @@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
   if (ret)
   return ret;
  
 + enable_efuse_prog_supply(1);
   for (bit = 0; val; bit++, val = 1)
   if (val  0x01) {
   ret = prog_bit(regs, bank, word, bit);
 - if (ret)
 + if (ret) {
 + enable_efuse_prog_supply(0);
   return ret;
 + }
   }
 + enable_efuse_prog_supply(0);
  
   return 0;
  }
 --
 1.7.10.4

Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com

Thanks for this contribution and for your patience.

Best regards,
Benoît
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[U-Boot] [PATCH 2/2] mx6sabre_common.h: Add CONFIG_CMD_FUSE support

From: Fabio Estevam fabio.este...@freescale.com

Add CONFIG_CMD_FUSE option, so that the fuse API can be used.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 include/configs/mx6sabre_common.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/include/configs/mx6sabre_common.h 
b/include/configs/mx6sabre_common.h
index d52c9a8..63405aa 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -34,6 +34,11 @@
 
 #define CONFIG_MXC_UART
 
+#define CONFIG_CMD_FUSE
+#ifdef CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+#endif
+
 /* MMC Configs */
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-- 
1.8.1.2

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[U-Boot] [PATCH 1/2] powerpc/P1022DS: Define new nand_ecclayout structure macros

2013-12-17 Thread York Sun

Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.

Signed-off-by: York Sun york...@freescale.com
CC: Prabhakar Kushwaha prabha...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
 include/configs/P1022DS.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h
index ba43cce..934a6cb 100644
--- a/include/configs/P1022DS.h
+++ b/include/configs/P1022DS.h
@@ -75,6 +75,8 @@
 #endif
 
 #define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 56
+#define CONFIG_SYS_NAND_MAX_OOBFREE5
 
 #ifdef CONFIG_NAND
 #define CONFIG_SPL
-- 
1.7.9.5


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[U-Boot] [PATCH 1/2] doc: README.fuse: Add an example on how to use the fuse API on mx6q

From: Fabio Estevam fabio.este...@freescale.com

When using the fuse API in U-boot user must calculate the 'bank' and 'word' 
values. 

Provide a real example on how to calculate such values for the mx6q.

Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 doc/README.fuse | 57 +
 1 file changed, 57 insertions(+)

diff --git a/doc/README.fuse b/doc/README.fuse
index 1bc91c4..aca1e5e 100644
--- a/doc/README.fuse
+++ b/doc/README.fuse
@@ -65,3 +65,60 @@ Configuration:
 
CONFIG_CMD_FUSE
   Define this to enable the fuse commands.
+
+Example:
+
+For reading the MAC address fuses on a MX6Q:
+
+- The MAC address are stored in two fuse addresses (the fuse addresses are
+described in the Fusemap Descriptions table from the mx6q Reference Manual):
+
+0x620[31:0] - MAC_ADDR[31:0]
+0x630[15:0] - MAC_ADDR[47:32]
+
+In order to use the fuse API, we need to pass the bank and word values, which
+are calculated as below:
+
+Fuse address for the lower MAC address: 0x620
+Base address for the fuses: 0x400
+
+(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+34 / 8 = 4 and the remainder is 2, so in this case:
+
+bank = 4
+word = 2
+
+And the U-boot command would be:
+
+= fuse read 4 2
+Reading bank 4:
+
+Word 0x0002: 9f027772
+
+Doing the same for the upper MAC address:
+
+Fuse address for the upper MAC address: 0x630
+Base address for the fuses: 0x400
+
+(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
+
+As the fuses are arranged in banks of 8 words:
+
+35 / 8 = 4 and the remainder is 3, so in this case:
+
+bank = 4
+word = 3
+
+And the U-boot command would be:
+
+= fuse read 4 3
+Reading bank 4:
+
+Word 0x0003: 0004
+
+,which matches the ethaddr value:
+= echo ${ethaddr}
+00:04:9f:02:77:72
-- 
1.8.1.2

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[U-Boot] [PATCH v4] arm: mx5: Add fuse supply enable in fsl_iim

2013-12-17 Thread Sergey Alyoshin

Enable fuse supply before fuse programming and disable after.

Signed-off-by: Sergey Alyoshin alyoshi...@gmail.com
---
 arch/arm/cpu/armv7/mx5/clock.c   |   12 
 arch/arm/include/asm/arch-mx5/clock.h|1 +
 arch/arm/include/asm/arch-mx5/crm_regs.h |3 +++
 drivers/misc/fsl_iim.c   |   13 -
 4 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index fb3b128..2ca87e4 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -749,6 +749,18 @@ void enable_nfc_clk(unsigned char enable)
MXC_CCM_CCGR5_EMI_ENFC(cg));
 }
 
+#ifdef CONFIG_FSL_IIM
+void enable_efuse_prog_supply(bool enable)
+{
+   if (enable)
+   setbits_le32(mxc_ccm-cgpr,
+   MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+   else
+   clrbits_le32(mxc_ccm-cgpr,
+   MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE);
+}
+#endif
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
diff --git a/arch/arm/include/asm/arch-mx5/clock.h 
b/arch/arm/include/asm/arch-mx5/clock.h
index 9ee79ae..3db4112 100644
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -53,5 +53,6 @@ void enable_usboh3_clk(bool enable);
 void mxc_set_sata_internal_clock(void);
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 void enable_nfc_clk(unsigned char enable);
+void enable_efuse_prog_supply(bool enable);
 
 #endif /* __ASM_ARCH_CLOCK_H */
diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h 
b/arch/arm/include/asm/arch-mx5/crm_regs.h
index 392881c..efe57e0 100644
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -305,6 +305,9 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK   (0x1  17)
 
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(1  4)
+
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK   0x3
 #define MXC_CCM_CCGR_CG_OFF0x0
diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index 44ae7b1..36433a7 100644
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -16,6 +16,9 @@
 #ifndef CONFIG_MPC512X
 #include asm/arch/imx-regs.h
 #endif
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#include asm/arch/clock.h
+#endif
 
 /* FSL IIM-specific constants */
 #define STAT_BUSY  0x80
@@ -93,6 +96,10 @@ struct fsl_iim {
} bank[8];
 };
 
+#if !defined(CONFIG_MX51)  !defined(CONFIG_MX53)
+#define enable_efuse_prog_supply(enable)
+#endif
+
 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int 
assert,
const char *caller)
 {
@@ -237,12 +244,16 @@ int fuse_prog(u32 bank, u32 word, u32 val)
if (ret)
return ret;
 
+   enable_efuse_prog_supply(1);
for (bit = 0; val; bit++, val = 1)
if (val  0x01) {
ret = prog_bit(regs, bank, word, bit);
-   if (ret)
+   if (ret) {
+   enable_efuse_prog_supply(0);
return ret;
+   }
}
+   enable_efuse_prog_supply(0);
 
return 0;
 }
-- 
1.7.10.4

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[U-Boot] [PATCH 2/2] powerpc/B4860QDS: Define new nand_ecclayout structure macros

2013-12-17 Thread York Sun

Define CONFIG_SYS_NAND_MAX_ECCPOS and CONFIG_SYS_NAND_MAX_OOBFREE to
reduce the image size, by taking advantage of the new nand_ecclayout
structure.

Signed-off-by: York Sun york...@freescale.com
CC: Prabhakar Kushwaha prabha...@freescale.com
CC: Scott Wood scottw...@freescale.com
---
 include/configs/B4860QDS.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
index 3c6cd61..c182158 100644
--- a/include/configs/B4860QDS.h
+++ b/include/configs/B4860QDS.h
@@ -289,6 +289,8 @@ unsigned long get_board_ddr_clk(void);
 
 /* NAND Flash on IFC */
 #define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS 256
+#define CONFIG_SYS_NAND_MAX_OOBFREE2
 #define CONFIG_SYS_NAND_BASE   0xff80
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_NAND_BASE_PHYS  (0xfull | CONFIG_SYS_NAND_BASE)
-- 
1.7.9.5


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Re: [U-Boot] [PATCH 1/2] doc: README.fuse: Add an example on how to use the fuse API on mx6q

Hi Fabio,

On Tuesday, December 17, 2013 9:03:40 PM, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 When using the fuse API in U-boot user must calculate the 'bank' and 'word'
 values.
 
 Provide a real example on how to calculate such values for the mx6q.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  doc/README.fuse | 57
  +
  1 file changed, 57 insertions(+)
 
 diff --git a/doc/README.fuse b/doc/README.fuse
 index 1bc91c4..aca1e5e 100644
 --- a/doc/README.fuse
 +++ b/doc/README.fuse
 @@ -65,3 +65,60 @@ Configuration:
  
 CONFIG_CMD_FUSE
Define this to enable the fuse commands.
 +
 +Example:
 +
 +For reading the MAC address fuses on a MX6Q:
 +
 +- The MAC address are stored in two fuse addresses (the fuse addresses are
 +described in the Fusemap Descriptions table from the mx6q Reference Manual):
 +
 +0x620[31:0] - MAC_ADDR[31:0]
 +0x630[15:0] - MAC_ADDR[47:32]
 +
 +In order to use the fuse API, we need to pass the bank and word values,
 which
 +are calculated as below:
 +
 +Fuse address for the lower MAC address: 0x620
 +Base address for the fuses: 0x400
 +
 +(0x620 - 0x400)/0x10 = 0x22 = 34 decimal
 +
 +As the fuses are arranged in banks of 8 words:
 +
 +34 / 8 = 4 and the remainder is 2, so in this case:
 +
 +bank = 4
 +word = 2
 +
 +And the U-boot command would be:
 +
 += fuse read 4 2
 +Reading bank 4:
 +
 +Word 0x0002: 9f027772
 +
 +Doing the same for the upper MAC address:
 +
 +Fuse address for the upper MAC address: 0x630
 +Base address for the fuses: 0x400
 +
 +(0x630 - 0x400)/0x10 = 0x23 = 35 decimal
 +
 +As the fuses are arranged in banks of 8 words:
 +
 +35 / 8 = 4 and the remainder is 3, so in this case:
 +
 +bank = 4
 +word = 3
 +
 +And the U-boot command would be:
 +
 += fuse read 4 3
 +Reading bank 4:
 +
 +Word 0x0003: 0004
 +
 +,which matches the ethaddr value:
 += echo ${ethaddr}
 +00:04:9f:02:77:72
 --
 1.8.1.2

Note that the documentation in this file is also completed for i.MX6 by
doc/README.mxc_ocotp and doc/README.imx6, as explained in each README. The
information that you add here regarding the location of the MAC fuses for i.MX6Q
is already present in doc/README.imx6.

Regarding the 'calculation' part, it is actually not needed since the values
obtained with these calculations are already given by the reference manual in
'46.5 OCOTP Memory Map/Register Definition'.

Examples could still be interesting though. What do you think?
 - Should the calculation part be removed and replaced with a reference to the
   RM §46.5 be added?
 - Should this example be moved to doc/README.imx6, or kept in doc/README.fuse
   as a generic example for the fuse API?
 - Should an example be added to show how to read the whole MAC address with a
   single fuse command (i.e. 'fuse read 4 2 2')?

Best regards,
Benoît
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Re: [U-Boot] [PATCH 2/2] mx6sabre_common.h: Add CONFIG_CMD_FUSE support

Hi Fabio,

On Tuesday, December 17, 2013 9:03:41 PM, Fabio Estevam wrote:
 From: Fabio Estevam fabio.este...@freescale.com
 
 Add CONFIG_CMD_FUSE option, so that the fuse API can be used.
 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  include/configs/mx6sabre_common.h | 5 +
  1 file changed, 5 insertions(+)
 
 diff --git a/include/configs/mx6sabre_common.h
 b/include/configs/mx6sabre_common.h
 index d52c9a8..63405aa 100644
 --- a/include/configs/mx6sabre_common.h
 +++ b/include/configs/mx6sabre_common.h
 @@ -34,6 +34,11 @@
  
  #define CONFIG_MXC_UART
  
 +#define CONFIG_CMD_FUSE
 +#ifdef CONFIG_CMD_FUSE
 +#define CONFIG_MXC_OCOTP
 +#endif
 +
  /* MMC Configs */
  #define CONFIG_FSL_ESDHC
  #define CONFIG_FSL_USDHC
 --
 1.8.1.2

Reviewed-by: Benoît Thébaudeau benoit.thebaud...@advansee.com

Best regards,
Benoît
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Re: [U-Boot] how to limit sandbox to a single thread/core?

2013-12-17 Thread Simon Glass

Hi,

On 16 December 2013 21:59, Abraham V. abraham.varric...@vvdntech.com wrote:
On Tue, Dec 17, 2013 at 2:00 AM, Simon Glass s...@chromium.org wrote:
Hi,

On 13 December 2013 01:47, Abraham V. abraham.varric...@vvdntech.com wrote:
Hello,

I just discovered that uboot has a sandbox build - output binary is
a standard linux application. This prompted me to try stepping through
the code with gdb and I'm running into an annoyance.

The sandbox binary is splitting into 4 threads (I'm guessing one for
each of my cores, am running this on an intel i3). This results in gdb
jumping between the different threads every once in a while.

Is there anyway to setup the sandbox to run as a single thread?

This is news to me - I have not hit this problem yet. Can you see what
the threads are?

Regards,
Simon

I'm ... embarrassed to report that this is a false alarm. Took me a
couple of days and I was about to send a reply today morning when I
saw your response. What happened is that I used the eclipse-cdt
debugger to try tracing the sandbox application. An interesting
'feature' of this debugger is that it shows which core a process is
running on. Here are a few (links) screenshots,

http://imageshack.us/a/img14/2202/ze37.png
http://imageshack.us/a/img855/1153/uwul.png
http://imageshack.us/a/img585/8499/ibz3.png

It wasn't until yesterday when I realized that, while the application
was jumping between cores, the thread number was exactly the same - it
wasn't a multi-threaded application, but a single threaded one just
bouncing around! This puzzled me so much that I even started a SO
question over the matter,

http://stackoverflow.com/questions/20608032/while-debugging-will-a-single-threaded-application-jump-between-cores

Turns out that the scheduler knocked me off-balance. Can't believe I'm
saying this, but I miss the days when everything ran on a single
thread/processor core.

OK that's good, thanks for the detailed explanation, I'm sure others
will hit this.

Regards,
Simon

A little embarrassed,
Abraham V.
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Re: [U-Boot] [PATCH v2 3/4] Add dumpimage, a tool to extract data from U-Boot images

2013-12-17 Thread Simon Glass

Hi Masahiro,

On 16 December 2013 19:25, Masahiro Yamada yamad...@jp.panasonic.com wrote:
 Hello Guilherme, Simon


 diff --git a/Makefile b/Makefile
 index a2fb037..653d3b3 100644
 --- a/Makefile
 +++ b/Makefile
 @@ -796,6 +796,7 @@ clean:
  $(obj)tools/envcrc \
  $(obj)tools/gdb/{astest,gdbcont,gdbsend}   \
  $(obj)tools/gen_eth_addr$(obj)tools/img2srec   \
 +$(obj)tools/dump{env,}image\
  $(obj)tools/mk{env,}image   $(obj)tools/mpc86x_clk \
  $(obj)tools/mk{$(BOARD),}spl   \
  $(obj)tools/mxsboot\

 Where is tools/dumpenvimage created?

I don't see it.

Regards,
Simon



 Best Regards
 Masahiro Yamada

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Re: [U-Boot] mtd: nand: omap: fix ecc-layout for HAM1 ecc-scheme

On Thu, Dec 05, 2013 at 05:54:21PM +0530, pekon gupta wrote:
 As per OMAP3530 TRM referenced below [1]
 
 For large-page NAND, ROM code expects following ecc-layout for HAM1 ecc-scheme
  - OOB[1] (offset of 1 *byte* from start of OOB) for x8 NAND device
  - OOB[2] (offset of 1 *word* from start of OOB) for x16 NAND device
 
 Thus ecc-layout expected by ROM code for HAM1 ecc-scheme is:
  *for x8 NAND Device*
  ++-+-+-+-+-+-+
  |    | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | ECC[B2] | ...
  ++-+-+-+-+-+-+
 
  *for x16 NAND Device*
  
 +++-+-+-+-+-+-+
  | x  | x  | ECC[A0] | ECC[A1] | ECC[A2] | ECC[B0] | ECC[B1] | 
 ECC[B2] |
  
 +++-+-+-+-+-+-+
 
 This patch fixes ecc-layout *only* for HAM1, as required by ROM-code
 For other ecc-schemes like (BCH8) ecc-layout is same for x8 or x16 devices.
 
 [1] OMAP3530: http://www.ti.com/product/omap3530
 TRM: http://www.ti.com/litv/pdf/spruf98x
   Chapter-25: Initialization Sub-topic: Memory Booting
   Section: 25.4.7.4 NAND
   Figure 25-19. ECC Locations in NAND Spare Areas
 
 Reported-by: Stefan Roese s...@denx.de
 Signed-off-by: Pekon Gupta pe...@ti.com
 Tested-by: Stefan Roese s...@denx.de
 
 ---
 drivers/mtd/nand/omap_gpmc.c | 8 ++--
  1 file changed, 6 insertions(+), 2 deletions(-)

Applied to u-boot-nand-flash.git

-Scott
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Re: [U-Boot] mtd: nand: omap_gpmc: cosmetic: Fix indentation

On Thu, Dec 05, 2013 at 07:58:06AM +0100, Stefan Roese wrote:
 Signed-off-by: Stefan Roese s...@denx.de
 Cc: Pekon Gupta pe...@ti.com
 Cc: Scott Wood scottw...@freescale.com

 ---
 drivers/mtd/nand/omap_gpmc.c | 86 ++--
  1 file changed, 43 insertions(+), 43 deletions(-)

Applied to u-boot-nand-flash.git with long lines wrapped.

I'm applying this even though the optimize OMAP NAND driver patchset
addresses the indentation, because it's too late in the release cycle for
that patchset (rc2 is already out, and v9 of the patchset was posted 10
days after the merge window closed) and the misindentation isn't just
ugly, but misleading as to the code flow (when I applied the patch that
introduced this, I thought Pekon had fixed it in the last version
posted).  I didn't want to let this significant readability regression
into the release.

Plus, this keeps the history cleaner than if the indentation fix were
combined with other changes.

-Scott
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Re: [U-Boot] [U-Boot, V2] mtd: nand: omap: fix HAM1_SW ecc using default value for ecc.size

On Thu, Dec 12, 2013 at 03:19:31PM +0200, Nikita Kiryanov wrote:
 Commit mtd: nand: omap: enable BCH ECC scheme using ELM for generic
 platform (d016dc42cedbf6102e100fa9ecb58462edfb14f8) changed the way
 software ECC is configured, both during boot, and during ecc switch, in a way
 that is not backwards compatible with older systems:
 
 Older version of omap_gpmc.c always assigned ecc.size = 0 when configuring
 for software ecc, relying on nand_scan_tail() to select a default for ecc.size
 (256), while the new version of omap_gpmc.c assigns ecc.size = pagesize,
 which is likely to not be 256.
 
 Since 1 bit hamming sw ecc is only meant to be used by legacy devices, revert
 to the original behavior.
 
 Cc: Igor Grinberg grinb...@compulab.co.il
 Cc: Tom Rini tr...@ti.com
 Cc: Scott Wood scottw...@freescale.com
 Cc: Pekon Gupta pe...@ti.com
 Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
 Acked-by: Pekon Gupta pe...@ti.com
 
 ---
 Changes in V2:
   - reworded commit title to better reflect what is being affected (Pekon
   Gupta)
 
  drivers/mtd/nand/omap_gpmc.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-nand-flash.git

-Scott
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Re: [U-Boot] [U-Boot, v2] nand_util.c: Use '%zd' for length in nand_unlock debug print

On Mon, Dec 16, 2013 at 09:59:34AM -0500, Tom Rini wrote:
 length is size_t so needs to be '%zd' not '%d' to avoid warnings.
 
 Cc: Scott Wood scottw...@freescale.com
 Signed-off-by: Tom Rini tr...@ti.com
 Acked-by: Scott Wood scottw...@freescale.com
 
 ---
 Changes in v2:
 - Use %zd, the correct format, rather than %ld, a differntly incorrect
   one.
 ---
  drivers/mtd/nand/nand_util.c |2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

Applied to u-boot-nand-flash.git

-Scott
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Re: [U-Boot] [U-Boot, 1/2] mtd: nand: omap: fix sw-hw-sw ecc switch

On Mon, Dec 16, 2013 at 07:19:01PM +0200, Nikita Kiryanov wrote:
 When switching ecc mode, omap_select_ecc_scheme() assigns the appropriate 
 values
 into the current nand chip's ecc.layout struct. This is done under the
 assumption that the struct exists only to store values, so it is OK to 
 overwrite
 it, but there is at least one situation where this assumption is incorrect:
 
 When switching to 1 bit hamming code sw ecc, the job of assigning layout data
 is outsourced to nand_scan_tail(), which simply assigns into ecc.layout a
 pointer to an existing struct prefilled with the appropriate values. This 
 struct
 doubles as both data and layout definition, and therefore shouldn't be
 overwritten, but on the next switch to hardware ecc, this is exactly what's
 going to happen. The next time the user switches to software ecc, they're
 going to get a messed up ecc layout.
 
 Prevent this and possible similar bugs by explicitly using the
 private-to-omap_gpmc.c omap_ecclayout struct when switching ecc mode.
 
 Cc: Scott Wood scottw...@freescale.com
 Cc: Pekon Gupta pe...@ti.com
 Signed-off-by: Nikita Kiryanov nik...@compulab.co.il
 
 ---
 drivers/mtd/nand/omap_gpmc.c | 7 ++-
  1 file changed, 6 insertions(+), 1 deletion(-)

Applied to u-boot-nand-flash.git

-Scott
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Re: [U-Boot] [U-Boot, V2, 2/2] mtd: nand: omap: fix ecc ops assignment when changing ecc