Re: [U-Boot] [v2 PATCH 10/12] arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
Hello Bo,
Am 31.10.2014 02:50, schrieb Bo Shen:
Hi Heiko,
On 10/30/2014 04:15 PM, Heiko Schocher wrote:
diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c
index 674a470..5c9a3ad 100644
--- a/arch/arm/cpu/at91-common/spl.c
+++ b/arch/arm/cpu/at91-common/spl.c
I am thinking, whether it be better to keep this file as two copy? This will
remove #ifdef, although a little code duplication.
If this solution acceptable, some suggestion as following:
- for armv5 (arm926ejs, now at91 series), named it spl_at91.c,
- for armv7 (cortex-a5, now, sama5d3), named it spl_atmel.c?
(As for arm9 series, we have at91 prefix for SoC name, and for armv7 SoC, we
don't have at91 prefix, and it now changed to Atmel Smart)
Ok, I look into this.
[...]
@@ -57,77 +91,134 @@ static void switch_to_main_crystal_osc(void)
[...]
- /* disable watchdog */
+void spl_board_init(void)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+
+ lowlevel_clock_init();
at91_disable_wdt();
- /* PMC configuration */
- at91_pmc_init();
+ /*
+ * At this stage the main oscillator is supposed to be enabled
+ * PCK = MCK = MOSC
+ */
+ writel(0x00, pmc-pllicpr);
- at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK);
+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+ at91_plla_init(CONFIG_SYS_AT91_PLLA);
- timer_init();
+ /* PCK = PLLA = 2 * MCK */
+ at91_mck_init(CONFIG_SYS_MCKR);
- board_early_init_f();
+ /* Switch MCK on PLLA output */
+ at91_mck_init(CONFIG_SYS_MCKR_CSS);
+
+#if defined(CONFIG_SYS_AT91_PLLB)
+ /* Configure PLLB */
+ at91_pllb_init(CONFIG_SYS_AT91_PLLB);
+#endif
+
+ /* Enable External Reset */
+ enable_ext_reset();
+#if defined(CONFIG_ATMEL_MATRIX_INIT)
+ /* Initialize matrix */
+ matrix_init();
+#endif
Can this also be weak function? And put matrix_init() code to SoC/board related
file.
Changed.
Thanks!
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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Re: [U-Boot] [v2 PATCH 10/12] arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
Dear Bo Shen, In message 5452ead4.7080...@atmel.com you wrote: I am thinking, whether it be better to keep this file as two copy? This will remove #ifdef, although a little code duplication. I agree that we should try and minimize #ifdef's, but code duplication is even worse. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de The explanation requiring the fewest assumptions is the most likely to be correct.-- William of Occam ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: ls102xa: Update PCIe dts node status
The patch changes PCIe dts node status to 'disabled' if the
corresponding controller is disabled according to serdes protocol.
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/config.h | 3 ++
arch/arm/include/asm/pcie_layerscape.h | 13
board/freescale/ls1021aqds/ls1021aqds.c| 5 +++
board/freescale/ls1021atwr/ls1021atwr.c| 5 +++
drivers/pci/Makefile | 1 +
drivers/pci/pcie_layerscape.c | 51 ++
include/configs/ls1021aqds.h | 8 +
include/configs/ls1021atwr.h | 7
8 files changed, 93 insertions(+)
create mode 100644 arch/arm/include/asm/pcie_layerscape.h
create mode 100644 drivers/pci/pcie_layerscape.c
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h
b/arch/arm/include/asm/arch-ls102xa/config.h
index f2c9687..9fd0b2c 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -49,6 +49,9 @@
#define LPUART_BASE(CONFIG_SYS_IMMR + 0x0195)
+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x240)
+#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x250)
+
#ifdef CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR_BE
#define CONFIG_VERY_BIG_RAM
diff --git a/arch/arm/include/asm/pcie_layerscape.h
b/arch/arm/include/asm/pcie_layerscape.h
new file mode 100644
index 000..fb08578
--- /dev/null
+++ b/arch/arm/include/asm/pcie_layerscape.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __PCIE_LAYERSCAPE_H_
+#define __PCIE_LAYERSCAPE_H_
+
+void pci_init_board(void);
+void ft_pcie_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 5fafc85..fccf6b6 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -10,6 +10,7 @@
#include asm/arch/immap_ls102xa.h
#include asm/arch/clock.h
#include asm/arch/fsl_serdes.h
+#include asm/pcie_layerscape.h
#include mmc.h
#include fsl_esdhc.h
#include fsl_ifc.h
@@ -243,6 +244,10 @@ int board_init(void)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
}
u8 flash_read8(void *addr)
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index 50d5640..0b548eb 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -10,6 +10,7 @@
#include asm/arch/immap_ls102xa.h
#include asm/arch/clock.h
#include asm/arch/fsl_serdes.h
+#include asm/pcie_layerscape.h
#include mmc.h
#include fsl_esdhc.h
#include fsl_ifc.h
@@ -293,6 +294,10 @@ int misc_init_r(void)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCIE_LAYERSCAPE
+ ft_pcie_setup(blob, bd);
+#endif
}
u8 flash_read8(void *addr)
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index e73a498..e525ceb 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o
obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o
obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
new file mode 100644
index 000..291c249
--- /dev/null
+++ b/drivers/pci/pcie_layerscape.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ * Layerscape PCIe driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/arch/fsl_serdes.h
+#include pci.h
+#include asm/io.h
+#include asm/pcie_layerscape.h
+
+#ifdef CONFIG_OF_BOARD_SETUP
+#include libfdt.h
+#include fdt_support.h
+
+static void ft_pcie_ls_setup(void *blob, const char *pci_compat,
+unsigned long ctrl_addr, enum srds_prtcl dev)
+{
+ int off;
+
+ off = fdt_node_offset_by_compat_reg(blob, pci_compat,
+ (phys_addr_t)ctrl_addr);
+ if (off 0)
+ return;
+
+ if (!is_serdes_configured(dev))
+ fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
+}
+
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+ #ifdef CONFIG_PCIE1
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1);
+ #endif
+
+ #ifdef CONFIG_PCIE2
+ ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2);
+ #endif
+}
+
+#else
+void ft_pcie_setup(void *blob, bd_t *bd)
+{
+}
+#endif
+
+void pci_init_board(void)
+{
+}
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d1f6ea7..5544b81 100644
--- a/include/configs/ls1021aqds.h
[U-Boot] [PATCH] blackfin: rename blackfin i2c driver to adi
This driver is not only used on blackfin. So it's better to
rename it and access i2c registers by standard io functions.
Fix coding style as well.
Signed-off-by: Scott Jiang scott.jiang.li...@gmail.com
---
drivers/i2c/Makefile |2 +-
drivers/i2c/{bfin-twi_i2c.c = adi_i2c.c} | 154 +++--
include/configs/bct-brettl2.h |2 +-
include/configs/bf518f-ezbrd.h|2 +-
include/configs/bf526-ezbrd.h |2 +-
include/configs/bf527-ad7160-eval.h |2 +-
include/configs/bf527-ezkit.h |2 +-
include/configs/bf527-sdp.h |2 +-
include/configs/bf537-minotaur.h |2 +-
include/configs/bf537-pnav.h |2 +-
include/configs/bf537-srv1.h |2 +-
include/configs/bf537-stamp.h |2 +-
include/configs/bf538f-ezkit.h|2 +-
include/configs/bf548-ezkit.h |2 +-
include/configs/bf609-ezkit.h |2 +-
include/configs/br4.h |2 +-
include/configs/cm-bf527.h|2 +-
include/configs/cm-bf537e.h |2 +-
include/configs/cm-bf537u.h |2 +-
include/configs/cm-bf548.h|2 +-
include/configs/pr1.h |2 +-
include/configs/tcm-bf518.h |2 +-
include/configs/tcm-bf537.h |2 +-
23 files changed, 103 insertions(+), 95 deletions(-)
rename drivers/i2c/{bfin-twi_i2c.c = adi_i2c.c} (72%)
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d067897..b7f0098 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -5,7 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
+obj-$(CONFIG_ADI_I2C) += adi_i2c.o
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/adi_i2c.c
similarity index 72%
rename from drivers/i2c/bfin-twi_i2c.c
rename to drivers/i2c/adi_i2c.c
index cfab064..c971f03 100644
--- a/drivers/i2c/bfin-twi_i2c.c
+++ b/drivers/i2c/adi_i2c.c
@@ -1,7 +1,7 @@
/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
+ * i2c.c - driver for ADI TWI/I2C
*
- * Copyright (c) 2006-2010 Analog Devices Inc.
+ * Copyright (c) 2006-2014 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -9,9 +9,9 @@
#include common.h
#include i2c.h
-#include asm/blackfin.h
#include asm/clock.h
-#include asm/mach-common/bits/twi.h
+#include asm/twi.h
+#include asm/io.h
/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
@@ -40,7 +40,7 @@ struct twi_regs {
#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
#endif
-static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
+static struct twi_regs *twi = (void *)TWI0_CLKDIV;
#ifdef DEBUG
# define dmemset(s, c, n) memset(s, c, n)
@@ -94,53 +94,54 @@ struct i2c_msg {
*/
static int wait_for_completion(struct i2c_msg *msg)
{
- uint16_t int_stat;
+ u16 int_stat, ctl;
ulong timebase = get_timer(0);
do {
- int_stat = twi-int_stat;
+ int_stat = readw(twi-int_stat);
if (int_stat XMTSERV) {
debugi(processing XMTSERV);
- twi-int_stat = XMTSERV;
- SSYNC();
+ writew(XMTSERV, twi-int_stat);
if (msg-alen) {
- twi-xmt_data8 = *(msg-abuf++);
+ writew(*(msg-abuf++), twi-xmt_data8);
--msg-alen;
} else if (!(msg-flags I2C_M_COMBO) msg-len) {
- twi-xmt_data8 = *(msg-buf++);
+ writew(*(msg-buf++), twi-xmt_data8);
--msg-len;
} else {
- twi-master_ctl |= (msg-flags I2C_M_COMBO) ?
RSTART | MDIR : STOP;
- SSYNC();
+ ctl = readw(twi-master_ctl);
+ if (msg-flags I2C_M_COMBO)
+ writew(ctl | RSTART | MDIR,
+ twi-master_ctl);
+ else
+ writew(ctl | STOP, twi-master_ctl);
}
}
if (int_stat RCVSERV) {
debugi(processing RCVSERV);
- twi-int_stat = RCVSERV;
- SSYNC();
+ writew(RCVSERV, twi-int_stat);
if (msg-len) {
- *(msg-buf++) = twi-rcv_data8;
+ *(msg-buf++) =
Re: [U-Boot] [PATCH] blackfin: rename blackfin i2c driver to adi
Hello Scott,
Am 01.11.2014 07:08, schrieb Scott Jiang:
something is wrong with your clock ... patch is not yet
in patchwork ...
This driver is not only used on blackfin. So it's better to
rename it and access i2c registers by standard io functions.
Fix coding style as well.
Signed-off-by: Scott Jiangscott.jiang.li...@gmail.com
---
drivers/i2c/Makefile |2 +-
drivers/i2c/{bfin-twi_i2c.c = adi_i2c.c} | 154
+++--
include/configs/bct-brettl2.h |2 +-
include/configs/bf518f-ezbrd.h|2 +-
include/configs/bf526-ezbrd.h |2 +-
include/configs/bf527-ad7160-eval.h |2 +-
include/configs/bf527-ezkit.h |2 +-
include/configs/bf527-sdp.h |2 +-
include/configs/bf537-minotaur.h |2 +-
include/configs/bf537-pnav.h |2 +-
include/configs/bf537-srv1.h |2 +-
include/configs/bf537-stamp.h |2 +-
include/configs/bf538f-ezkit.h|2 +-
include/configs/bf548-ezkit.h |2 +-
include/configs/bf609-ezkit.h |2 +-
include/configs/br4.h |2 +-
include/configs/cm-bf527.h|2 +-
include/configs/cm-bf537e.h |2 +-
include/configs/cm-bf537u.h |2 +-
include/configs/cm-bf548.h|2 +-
include/configs/pr1.h |2 +-
include/configs/tcm-bf518.h |2 +-
include/configs/tcm-bf537.h |2 +-
23 files changed, 103 insertions(+), 95 deletions(-)
rename drivers/i2c/{bfin-twi_i2c.c = adi_i2c.c} (72%)
Thanks for this work ... some nitpicks ...
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d067897..b7f0098 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -5,7 +5,7 @@
# SPDX-License-Identifier:GPL-2.0+
#
-obj-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o
+obj-$(CONFIG_ADI_I2C) += adi_i2c.o
please use something like CONFIG_SYS_I2C_ADI and please
convert this driver to CONFIG_SYS_I2C framework ...
obj-$(CONFIG_I2C_MV) += mv_i2c.o
obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
diff --git a/drivers/i2c/bfin-twi_i2c.c b/drivers/i2c/adi_i2c.c
similarity index 72%
rename from drivers/i2c/bfin-twi_i2c.c
rename to drivers/i2c/adi_i2c.c
index cfab064..c971f03 100644
--- a/drivers/i2c/bfin-twi_i2c.c
+++ b/drivers/i2c/adi_i2c.c
@@ -1,7 +1,7 @@
/*
- * i2c.c - driver for Blackfin on-chip TWI/I2C
+ * i2c.c - driver for ADI TWI/I2C
*
- * Copyright (c) 2006-2010 Analog Devices Inc.
+ * Copyright (c) 2006-2014 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -9,9 +9,9 @@
#includecommon.h
#includei2c.h
-#includeasm/blackfin.h
#includeasm/clock.h
-#includeasm/mach-common/bits/twi.h
+#includeasm/twi.h
+#includeasm/io.h
/* Every register is 32bit aligned, but only 16bits in size */
#define ureg(name) u16 name; u16 __pad_##name;
@@ -40,7 +40,7 @@ struct twi_regs {
#ifdef TWI_CLKDIV
#define TWI0_CLKDIV TWI_CLKDIV
#endif
-static volatile struct twi_regs *twi = (void *)TWI0_CLKDIV;
+static struct twi_regs *twi = (void *)TWI0_CLKDIV;
#ifdef DEBUG
# define dmemset(s, c, n) memset(s, c, n)
@@ -94,53 +94,54 @@ struct i2c_msg {
*/
static int wait_for_completion(struct i2c_msg *msg)
{
- uint16_t int_stat;
+ u16 int_stat, ctl;
This change is not related to the subject of the patch,
please split this into seperate patches ...
ulong timebase = get_timer(0);
do {
- int_stat = twi-int_stat;
+ int_stat = readw(twi-int_stat);
Here too... please fix globally.
if (int_stat XMTSERV) {
debugi(processing XMTSERV);
- twi-int_stat = XMTSERV;
- SSYNC();
+ writew(XMTSERV,twi-int_stat);
Here too...
if (msg-alen) {
- twi-xmt_data8 = *(msg-abuf++);
+ writew(*(msg-abuf++),twi-xmt_data8);
--msg-alen;
} else if (!(msg-flags I2C_M_COMBO) msg-len) {
- twi-xmt_data8 = *(msg-buf++);
+ writew(*(msg-buf++),twi-xmt_data8);
--msg-len;
} else {
- twi-master_ctl |= (msg-flags I2C_M_COMBO) ?
RSTART | MDIR : STOP;
- SSYNC();
+ ctl = readw(twi-master_ctl);
+ if (msg-flags I2C_M_COMBO)
+ writew(ctl | RSTART | MDIR,
+ twi-master_ctl);
+ else
+
Re: [U-Boot] [PATCH v5] fs: fat/ext4/sandbox - Deal with files greater than 2GB
Hi Suriyan,
On 28 October 2014 17:00, Suriyan Ramasami suriya...@gmail.com wrote:
The commands fatls/ext4ls give negative values when dealing with files
greater than 2GB.
The commands fatsize/ext4size do not update the variable filesize for
these files.
To deal with this, the fs functions have been modified to take an additional
parameter of type * loff_t which is then populated. The return value of the
fs functions are used only for error conditions.
Signed-off-by: Suriyan Ramasami suriya...@gmail.com
---
Changes in v5:
* Simon - update fs.h with comments for fs_read/fs_write/fs_size
* Simon - test/fs/fs-test.sh. Many changes as listed under
* Add README file to document how to run it
* Generate output in a sandbox environment
* Add one line comments on shell variables used
* Avoid camel case through out
* Path to UBOOT is variable at top
* Print PASSED or FAILED at end, and set return code, 0 if OK, 1 otherwise
Changes in v4:
* Support generic fs write commands
* Sync up behavior of fs load vs fatload and ext4load
* Albert - change -ve to negative in commit message
Changes in v3:
* Added testcase to test writes
* Correct function set_contents() in fs/fat/fat_write.c
Changes in v2:
* Added test case for fat/ext4 in test/fs/testfs.sh
* md5sum: call map_sysmem() for buffer that md5_wd will work on
Changes in v1:
* First try.
arch/sandbox/cpu/os.c | 11 +-
arch/sandbox/cpu/state.c | 6 +-
common/board_f.c | 6 +-
common/cmd_ext4.c | 61 +-
common/cmd_fat.c | 9 +-
common/cmd_fs.c | 17 ++
common/cmd_md5sum.c | 12 +-
common/env_fat.c | 4 +-
fs/ext4/ext4_common.c | 24 +--
fs/ext4/ext4_common.h | 4 +-
fs/ext4/ext4_write.c | 32
fs/ext4/ext4fs.c | 37 ++--
fs/fat/fat.c | 124 +++--
fs/fat/fat_write.c| 59 +++---
fs/fat/file.c | 7 +-
fs/fs.c | 77
fs/sandbox/sandboxfs.c| 25 ++-
include/configs/sandbox.h | 2 +
include/ext4fs.h | 13 +-
include/fat.h | 19 +-
include/fs.h | 41 ++--
include/os.h | 2 +-
include/sandboxfs.h | 8 +-
test/fs/README| 4 +
test/fs/fs-test.sh| 462
++
25 files changed, 807 insertions(+), 259 deletions(-)
create mode 100644 test/fs/README
create mode 100755 test/fs/fs-test.sh
I think you close with this patch. So please can you break it up into
several patches? It's too had for people to review as is. My thoughts
are you could have these patches:
- cmd_ms5sum.c is a change to enable md5 for sandbox
- change fs layer to return size in a paramter and fix up return value
- if not too much trouble, put the business of returning the number of
bytes read/written into a separate patch. Otherwise, just leave it in
the one above
- any other changes that remain if any (could be first patch in series)
- patch to add add the test
So that would be 3 to 5 patches depending on how you go.
I've made some comments below anyway. Hopefully this is everything but
it's hard to tell with so much changing!
Thanks again for your efforts.
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 1c4aa3f..43872e8 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -385,7 +385,7 @@ const char *os_dirent_get_typename(enum os_dirent_t type)
return os_dirent_typename[OS_FILET_UNKNOWN];
}
-ssize_t os_get_filesize(const char *fname)
+int os_get_filesize(const char *fname, loff_t *size)
{
struct stat buf;
int ret;
@@ -393,7 +393,8 @@ ssize_t os_get_filesize(const char *fname)
ret = stat(fname, buf);
if (ret)
return ret;
- return buf.st_size;
+ *size = buf.st_size;
+ return 0;
}
void os_putc(int ch)
@@ -427,10 +428,10 @@ int os_read_ram_buf(const char *fname)
{
struct sandbox_state *state = state_get_current();
int fd, ret;
- int size;
+ loff_t size;
- size = os_get_filesize(fname);
- if (size 0)
+ ret = os_get_filesize(fname, size);
+ if (ret 0)
return -ENOENT;
return ret here I think, since you actually have the proper error.
if (size != state-ram_size)
return -ENOSPC;
diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c
index 59adad6..07d2aea 100644
--- a/arch/sandbox/cpu/state.c
+++ b/arch/sandbox/cpu/state.c
@@ -49,12 +49,12 @@ static int state_ensure_space(int extra_size)
static int state_read_file(struct sandbox_state *state, const char *fname)
{
- int size;
+ loff_t size;
int ret;
int fd;
- size = os_get_filesize(fname);
- if (size 0) {
+ ret = os_get_filesize(fname, size);
+ if (ret 0) {
Re: [U-Boot] verified boot of beaglebone black
Thanks a lot for your replies Simon, 1. Could you please confirm whether the beaglebone black support exists in that U-Boot 2014.07 can I use linux-3.12.10-ti2013.12.01 kernel (provided by ti-sdk-am335x-evm-07.00.00.00 )on top of this U-Boot 2014.07 2. Could you please provide me the link for syncing U-Boot 2014.07 for beaglebone black Many Thanks in Advance, Srinivasan S From: s...@google.com s...@google.com on behalf of Simon Glass s...@chromium.org Sent: Thursday, October 30, 2014 8:30 PM To: Srinivasan S Cc: U-Boot Mailing List Subject: Re: verified boot of beaglebone black Hi, On 30 October 2014 01:15, Srinivasan S srinivasa...@tataelxsi.co.in wrote: Hi Simon, Extremely Sorry to push you Hard, Could you please provide any updates w.r.t the below issue I think you missed my reply, am removing context... Please use the latest mainline, or at least U-Boot 2014.07. That board does not exist in older versions. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] verified boot of beaglebone black
Hi Simon Once again thanks a lot for your confirmation As you suggested, I have downloaded u-boot-2014.07.tar.bz2ftp://ftp.denx.de/pub/u-boot/u-boot-2014.07.tar.bz2 when I was trying to build the same , I was facing the below errors srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/u-boot-2014.07$ make O=b/am335x_boneblack_vboot CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm am335x_boneblack_vboot_config all /home/srinivasan/TUNSTALL/board-support/u-boot-2014.07/scripts/dtc-version.sh: line 17: dtc: command not found /home/srinivasan/TUNSTALL/board-support/u-boot-2014.07/scripts/dtc-version.sh: line 18: dtc: command not found *** Your dtc is too old, please upgrade to dtc 1.4 or newer make[2]: *** [checkdtc] Error 1 make[1]: *** [build-one-by-one] Error 2 make: *** [sub-make] Error 2 Please do the needful in resolving this issue Thanks in advance, srinivasan S From: s...@google.com s...@google.com on behalf of Simon Glass s...@chromium.org Sent: Friday, October 31, 2014 9:57 AM To: Srinivasan S Cc: U-Boot Mailing List Subject: Re: verified boot of beaglebone black Hi, On 30 Oct 2014 21:50, Srinivasan S srinivasa...@tataelxsi.co.inmailto:srinivasa...@tataelxsi.co.in wrote: Thanks a lot for your replies Simon, 1. Could you please confirm whether the beaglebone black support exists in that U-Boot 2014.07 can I use linux-3.12.10-ti2013.12.01 kernel (provided by ti-sdk-am335x-evm-07.00.00.00 )on top of this U-Boot 2014.07 That should work ok. 2. Could you please provide me the link for syncing U-Boot 2014.07 for beaglebone black See here: ftp://ftp.denx.de/pub/u-boot/ Regards, Simon Many Thanks in Advance, Srinivasan S From: s...@google.commailto:s...@google.com s...@google.commailto:s...@google.com on behalf of Simon Glass s...@chromium.orgmailto:s...@chromium.org Sent: Thursday, October 30, 2014 8:30 PM To: Srinivasan S Cc: U-Boot Mailing List Subject: Re: verified boot of beaglebone black Hi, On 30 October 2014 01:15, Srinivasan S srinivasa...@tataelxsi.co.inmailto:srinivasa...@tataelxsi.co.in wrote: Hi Simon, Extremely Sorry to push you Hard, Could you please provide any updates w.r.t the below issue I think you missed my reply, am removing context... Please use the latest mainline, or at least U-Boot 2014.07. That board does not exist in older versions. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] DECLARE_GLOBAL_DATA_PTR : move from source to Makefile
Hi, all, I find this macro is found anywhere in the source, nearly one thousand in the source, looks odd sometime. I have a idea about this: 1. remove DECLARE_GLOBAL_DATA_PTR from source about one thousand DECLARE_GLOBAL_DATA_PTR in the source 2. add a file like, same as other archs. arch/arm/include/asm/declare_global_data_ptr.h - - - - #ifndef __DECLARE_GLOBAL_DATA_PTR_H #define __DECLARE_GLOBAL_DATA_PTR_H #ifdef CONFIG_ARM64 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (x18) #else #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (r9) #endif #endif - - - - 3. modify top level Makefile - - - - UBOOTINCLUDE:= \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h \ + -include $(srctree)/arch/$(ARCH)/include/asm/global_data.h - - - - ... Du Huanpeng (+86)13719074147 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [BUG] kwimage v0 broken
Hi Gerald! On 31.10.2014 01:06, drEagle wrote: I have compared the latest kwimage and the oldest one. I have found some minor differences that make my sheevaplugs flashing and u-booting again. Thanks for your effort here. Really appreciated! And sorry for breaking things for you. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] ARM: kwimage: fix v0 format
On 31.10.2014 01:03, Gerald Kerma wrote: This patch fix the kwimage tools for version 0 fileformat used for kirkwood Tested on sheevaplug Signed-off-by: Gerald Kerma drea...@doukki.net I tested this on AXP (version 1 instead of version 0) and found no problems here. So: Tested-by: Stefan Roese s...@denx.de Reviewed-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] verified boot of beaglebone black
On 31 October 2014 10:48, Srinivasan S srinivasa...@tataelxsi.co.in wrote: Hi Simon Once again thanks a lot for your confirmation As you suggested, I have downloaded u-boot-2014.07.tar.bz2ftp://ftp.denx.de/pub/u-boot/u-boot-2014.07.tar.bz2 when I was trying to build the same , I was facing the below errors srinivasan@tata-HP-Elite-7100-Microtower-PC:~/TUNSTALL/board-support/u-boot-2014.07$ make O=b/am335x_boneblack_vboot CROSS_COMPILE=arm-linux-gnueabihf- ARCH=arm am335x_boneblack_vboot_config all /home/srinivasan/TUNSTALL/board-support/u-boot-2014.07/scripts/dtc-version.sh: line 17: dtc: command not found /home/srinivasan/TUNSTALL/board-support/u-boot-2014.07/scripts/dtc-version.sh: line 18: dtc: command not found *** Your dtc is too old, please upgrade to dtc 1.4 or newer make[2]: *** [checkdtc] Error 1 make[1]: *** [build-one-by-one] Error 2 make: *** [sub-make] Error 2 Looks like dtc is not your your bash path, try to build the same and export it. $ git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git $ cd dtc $ make $ sudo make install See doc/README.fdt-control for more info. Please do the needful in resolving this issue Thanks in advance, srinivasan S From: s...@google.com s...@google.com on behalf of Simon Glass s...@chromium.org Sent: Friday, October 31, 2014 9:57 AM To: Srinivasan S Cc: U-Boot Mailing List Subject: Re: verified boot of beaglebone black Hi, On 30 Oct 2014 21:50, Srinivasan S srinivasa...@tataelxsi.co.inmailto:srinivasa...@tataelxsi.co.in wrote: Thanks a lot for your replies Simon, 1. Could you please confirm whether the beaglebone black support exists in that U-Boot 2014.07 can I use linux-3.12.10-ti2013.12.01 kernel (provided by ti-sdk-am335x-evm-07.00.00.00 )on top of this U-Boot 2014.07 That should work ok. 2. Could you please provide me the link for syncing U-Boot 2014.07 for beaglebone black See here: ftp://ftp.denx.de/pub/u-boot/ Regards, Simon Many Thanks in Advance, Srinivasan S From: s...@google.commailto:s...@google.com s...@google.commailto:s...@google.com on behalf of Simon Glass s...@chromium.orgmailto:s...@chromium.org Sent: Thursday, October 30, 2014 8:30 PM To: Srinivasan S Cc: U-Boot Mailing List Subject: Re: verified boot of beaglebone black Hi, On 30 October 2014 01:15, Srinivasan S srinivasa...@tataelxsi.co.inmailto:srinivasa...@tataelxsi.co.in wrote: Hi Simon, Extremely Sorry to push you Hard, Could you please provide any updates w.r.t the below issue I think you missed my reply, am removing context... Please use the latest mainline, or at least U-Boot 2014.07. That board does not exist in older versions. thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] kconfig: arm: select CPU_V7 for some new boards
On 31.10.2014 06:26, Masahiro Yamada wrote: Marvell DB-MV784MP-GP and maxBCM are pretty new boards and were missed by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). This commit adds select CPU_V7 for them and remove redundant config SYS_CPU and string directives. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Savoundararadj savou...@gmail.com Thanks Masahiro-san for taking care of this. As always, you are really amazingly active and attentive! Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: rmobile: r8a7790: Update initialize L2 cache
Initialization of L2CTLR[5] was set only as R8A7790 by commit 237faf095fb43abbed6e40266ef7efccc8b9308b. However, initialization of cash needs to be performed continuously. This changes into the processing which continues initialization of L2CTLR[5] into L2CTLR cash and performs it. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S index 879e0e0..d47546a 100644 --- a/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S +++ b/arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S @@ -60,17 +60,10 @@ do_lowlevel_init: cmp r1, #3 /* has already been set up */ bicne r0, r0, #0xe7 orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ - - ldr r2, =0xFF44 /* PRR */ - ldr r1, [r2] - and r1, r1, #0x7F00 - lsrsr1, r1, #8 - cmp r1, #0x45 /* 0x45 is ID of r8a7790 */ - bne L2CTLR_5_SKIP +#if defined(CONFIG_R8A7790) orrne r0, r0, #0x20 /* L2CTLR[5] */ -L2CTLR_5_SKIP: +#endif mcrne p15, 1, r0, c9, c0, 2 - _exit_init_l2_a15: ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) sub sp, r3, #4 -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] arm: rmobile: lager: Fix change of the CPU frequency
The change of the CPU frequency is waited for until PLL0ST of the PLLECR is
set to 1.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/include/asm/arch-rmobile/rcar-base.h | 2 ++
board/renesas/lager/lager.c | 5 +
2 files changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/arch-rmobile/rcar-base.h
b/arch/arm/include/asm/arch-rmobile/rcar-base.h
index 027e9b1..9c1439b 100644
--- a/arch/arm/include/asm/arch-rmobile/rcar-base.h
+++ b/arch/arm/include/asm/arch-rmobile/rcar-base.h
@@ -385,6 +385,8 @@
#define PLL0CR 0xE61500D8
#define PLL0_STC_MASK 0x7F00
#define PLL0_STC_BIT 24
+#define PLLECR 0xE61500D0
+#define PLL0ST 0x100
#ifndef __ASSEMBLY__
#include asm/types.h
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5302839..1fc5833 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -36,9 +36,14 @@ void s_init(void)
/* CPU frequency setting. Set to 1.4GHz */
if (rmobile_get_cpu_rev_integer() = R8A7790_CUT_ES2X) {
+ u32 stat = 0;
u32 stc = ((1400 / CLK2MHZ(CONFIG_SYS_CLK_FREQ)) - 1)
PLL0_STC_BIT;
clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
+
+ do {
+ stat = readl(PLLECR) PLL0ST;
+ } while (stat == 0x0);
}
/* QoS(Quality-of-Service) Init */
--
2.1.1
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Re: [U-Boot] [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI
On 30 October 2014 22:59, Marek Vasut ma...@denx.de wrote: On Thursday, October 30, 2014 at 03:38:40 PM, Jagan Teki wrote: On 30 October 2014 15:00, Marek Vasut ma...@denx.de wrote: Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Vince Bridgers vbrid...@altera.com Cc: Pavel Machek pa...@denx.de Cc: Stefan Roese s...@denx.de --- include/configs/socfpga_common.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED3000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI Yes, the address is not fixed, since this is FPGA IP. May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config. thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] blackfin: rename blackfin i2c driver to adi
Hi Heiko,
static int wait_for_completion(struct i2c_msg *msg)
{
- uint16_t int_stat;
+ u16 int_stat, ctl;
This change is not related to the subject of the patch,
please split this into seperate patches ...
ulong timebase = get_timer(0);
do {
- int_stat = twi-int_stat;
+ int_stat = readw(twi-int_stat);
Here too... please fix globally.
This patch is to modify blackfin specific string or api to generic.
So I use standard io api readl/writel here. I'm not sure what you
mean.
Scott
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[U-Boot] [PATCH 2/6] arm: rmobile: koelsch: Add external RAM boot
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x7000.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/cpu/armv7/rmobile/Kconfig | 2 +-
board/renesas/koelsch/qos.c| 7 ++-
include/configs/koelsch.h | 14 --
3 files changed, 19 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig
b/arch/arm/cpu/armv7/rmobile/Kconfig
index 0071edf..360141c 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -28,7 +28,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool Enable boot from RAM
- depends on TARGET_LAGER
+ depends on TARGET_LAGER || TARGET_KOELSCH
default n
source board/atmark-techno/armadillo-800eva/Kconfig
diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c
index ecf3eed..d293e3d 100644
--- a/board/renesas/koelsch/qos.c
+++ b/board/renesas/koelsch/qos.c
@@ -14,7 +14,7 @@
#include asm/arch/rmobile.h
/* QoS version 0.240 for ES1 and version 0.334 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -1304,3 +1304,8 @@ void qos_init(void)
writel(0x0001, axi_qos-qosthres2);
writel(0x0001, axi_qos-qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index e015e90..3ccadd0 100644
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -38,7 +38,12 @@
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x7000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
+
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
@@ -69,8 +74,13 @@
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR0xE633fffc
-#define STACK_AREA_SIZE0xC000
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR0x7003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR0xE633fffC
+#endif
+
+#define STACK_AREA_SIZE0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
--
2.1.1
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[U-Boot] [PATCH 4/6] arm: rmobile: lager: Remove RAM address initialization
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/lager/lager.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 1fc5833..2bb8710 100644
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -165,7 +165,6 @@ int board_phy_config(struct phy_device *phydev)
int dram_init(void)
{
- gd-bd-bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
--
2.1.1
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[U-Boot] [PATCH 6/6] arm: rmobile: alt: Remove RAM address initialization
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/alt/alt.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c
index 9d8e8f9..b668bf6 100644
--- a/board/renesas/alt/alt.c
+++ b/board/renesas/alt/alt.c
@@ -140,7 +140,6 @@ int board_eth_init(bd_t *bis)
int dram_init(void)
{
- gd-bd-bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
--
2.1.1
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[U-Boot] [PATCH 5/6] arm: rmobile: koelsch: Remove RAM address initialization
Since board info structure is not still set up, the setting of RAM
address causes illegal access.
Therefore the setting of RAM address is removed.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
board/renesas/koelsch/koelsch.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index bfd0cc6..37202f9 100644
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -150,7 +150,6 @@ int board_eth_init(bd_t *bis)
int dram_init(void)
{
- gd-bd-bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd-ram_size = CONFIG_SYS_SDRAM_SIZE;
return 0;
--
2.1.1
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[U-Boot] [PATCH 1/6] arm: rmobile: lager: Add external RAM boot
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0xB000.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/cpu/armv7/rmobile/Kconfig | 5 +
board/renesas/lager/qos.c | 7 ++-
include/configs/lager.h| 12 ++--
3 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig
b/arch/arm/cpu/armv7/rmobile/Kconfig
index 6c2bb22..0071edf 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -26,6 +26,11 @@ config SYS_CPU
config SYS_SOC
default rmobile
+config RMOBILE_EXTRAM_BOOT
+ bool Enable boot from RAM
+ depends on TARGET_LAGER
+ default n
+
source board/atmark-techno/armadillo-800eva/Kconfig
source board/renesas/koelsch/Kconfig
source board/renesas/lager/Kconfig
diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c
index ce7f8ba..dec37d2 100644
--- a/board/renesas/lager/qos.c
+++ b/board/renesas/lager/qos.c
@@ -13,7 +13,7 @@
#include asm/arch/rmobile.h
/* QoS version 0.955 for ES1 and version 0.963 for ES2 */
-
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
enum {
DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04,
DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09,
@@ -2381,3 +2381,8 @@ void qos_init(void)
else
qos_init_es1();
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/include/configs/lager.h b/include/configs/lager.h
index 699135f..a814b4c 100644
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -39,7 +39,11 @@
#define CONFIG_FAT_WRITE
#define CONFIG_EXT4_WRITE
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0xB000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE808
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
@@ -70,8 +74,12 @@
#define CONFIG_TMU_TIMER
/* STACK */
-#define CONFIG_SYS_INIT_SP_ADDR0xE827fffc
-#define STACK_AREA_SIZE0xC000
+#if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR0xB003FFFC
+#else
+#define CONFIG_SYS_INIT_SP_ADDR0xE827FFFC
+#endif
+#define STACK_AREA_SIZE0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
--
2.1.1
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[U-Boot] [PATCH 3/6] arm: rmobile: alt: Add external RAM boot
If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM.
The default boot address is 0x7000.
Signed-off-by: Hisashi Nakamura hisashi.nakamura...@renesas.com
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com
---
arch/arm/cpu/armv7/rmobile/Kconfig | 2 +-
board/renesas/alt/qos.c| 6 ++
include/configs/alt.h | 8
3 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig
b/arch/arm/cpu/armv7/rmobile/Kconfig
index 360141c..127f254 100644
--- a/arch/arm/cpu/armv7/rmobile/Kconfig
+++ b/arch/arm/cpu/armv7/rmobile/Kconfig
@@ -28,7 +28,7 @@ config SYS_SOC
config RMOBILE_EXTRAM_BOOT
bool Enable boot from RAM
- depends on TARGET_LAGER || TARGET_KOELSCH
+ depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER
default n
source board/atmark-techno/armadillo-800eva/Kconfig
diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c
index d788aa0..f0b349f 100644
--- a/board/renesas/alt/qos.c
+++ b/board/renesas/alt/qos.c
@@ -13,6 +13,7 @@
#include asm/io.h
#include asm/arch/rmobile.h
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
/* QoS version 0.11 */
enum {
@@ -942,3 +943,8 @@ void qos_init(void)
writel(0x0001, axi_qos-qosthres2);
writel(0x0001, axi_qos-qosqon);
}
+#else /* CONFIG_RMOBILE_EXTRAM_BOOT */
+void qos_init(void)
+{
+}
+#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */
diff --git a/include/configs/alt.h b/include/configs/alt.h
index 7238f68..5a19096 100644
--- a/include/configs/alt.h
+++ b/include/configs/alt.h
@@ -34,7 +34,11 @@
#define CONFIG_CMD_SF
#define CONFIG_CMD_SPI
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_TEXT_BASE 0x7000
+#else
#define CONFIG_SYS_TEXT_BASE 0xE6304000
+#endif
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_SYS_GENERIC_BOARD
@@ -59,7 +63,11 @@
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_TMU_TIMER
+#if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
+#define CONFIG_SYS_INIT_SP_ADDR0x7003FFFC
+#else
#define CONFIG_SYS_INIT_SP_ADDR0xE633FFFC
+#endif
#define STACK_AREA_SIZE0xC000
#define LOW_LEVEL_MERAM_STACK \
(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
--
2.1.1
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Re: [U-Boot] DECLARE_GLOBAL_DATA_PTR : move from source to Makefile
Hi Kevin. On Fri, 31 Oct 2014 13:04:38 +0800 Kevin Du Huanpeng u74...@gmail.com wrote: Hi, all, I find this macro is found anywhere in the source, nearly one thousand in the source, looks odd sometime. Only one thousand. We have more than 6000 source files. yamada@beagle:~/workspace/u-boot$ find . -name '*.[ch]' | wc 61586158 198875 yamada@beagle:~/workspace/u-boot$ find . -name '*.[ch]' | xargs grep DECLARE_GLOBAL_DATA_PTR | wc 9441099 54674 I have a idea about this: 1. remove DECLARE_GLOBAL_DATA_PTR from source about one thousand DECLARE_GLOBAL_DATA_PTR in the source 2. add a file like, same as other archs. arch/arm/include/asm/declare_global_data_ptr.h - - - - #ifndef __DECLARE_GLOBAL_DATA_PTR_H #define __DECLARE_GLOBAL_DATA_PTR_H #ifdef CONFIG_ARM64 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (x18) #else #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (r9) #endif #endif - - - - 3. modify top level Makefile - - - - UBOOTINCLUDE:= \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h \ + -include $(srctree)/arch/$(ARCH)/include/asm/global_data.h - - - - I do not like this idea. I think a source file should only include needed headers. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] arm: rmobile: alt: Fix typo of SCIF id
Alt board use SCIF2, not SCIF0. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- board/renesas/alt/alt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index b668bf6..5c5a86f 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -43,7 +43,7 @@ void s_init(void) #define MSTPSR70xE61501C4 #define SMSTPCR7 0xE615014C -#define SCIF0_MSTP719 (1 19) +#define SCIF2_MSTP719 (1 19) #define MSTPSR80xE61509A0 #define SMSTPCR8 0xE6150990 @@ -63,8 +63,8 @@ int board_early_init_f(void) /* TMU */ mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); - /* SCIF0 */ - mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP719); + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); /* ETHER */ mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: rmobile: alt: Add support USB and USB commands
This adds support for USB commands and USB storage device. Signed-off-by: Yoshiyuki Ito yoshiyuki.ito...@renesas.com Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/alt.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/alt.h b/include/configs/alt.h index 5a19096..502b727 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -31,6 +31,7 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_USB #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -170,4 +171,10 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT2 + #endif /* __ALT_H */ -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] arm: rmobile: alt: Add VFAT filesystem support
Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- include/configs/alt.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/include/configs/alt.h b/include/configs/alt.h index 502b727..7bd649f 100644 --- a/include/configs/alt.h +++ b/include/configs/alt.h @@ -32,6 +32,8 @@ #define CONFIG_CMD_NFS #define CONFIG_CMD_BOOTZ #define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE #define CONFIG_CMD_SF #define CONFIG_CMD_SPI @@ -171,6 +173,10 @@ #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ +/* Filesystems */ +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + /* USB */ #define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI -- 2.1.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 PATCH 05/12] arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define
Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Bo Shen voice.s...@atmel.com --- Changes in v3: add Reviewed-by from Bo Shen Changes in v2: add comment from Andreas Biessmann: - rename MPDDRC_CR_EBISHARE to MPDDRC_CR_DQMS_SHARED arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h index 5741f6e..130a85a 100644 --- a/arch/arm/include/asm/arch-at91/atmel_mpddrc.h +++ b/arch/arm/include/asm/arch-at91/atmel_mpddrc.h @@ -57,6 +57,7 @@ int ddr2_init(const unsigned int ram_address, #define ATMEL_MPDDRC_CR_DIC_DS (0x1 8) #define ATMEL_MPDDRC_CR_DIS_DLL(0x1 9) #define ATMEL_MPDDRC_CR_OCD_DEFAULT(0x7 12) +#define ATMEL_MPDDRC_CR_DQMS_SHARED(0x1 16) #define ATMEL_MPDDRC_CR_ENRDM_ON (0x1 17) #define ATMEL_MPDDRC_CR_NB_8BANKS (0x1 20) #define ATMEL_MPDDRC_CR_NDQS_DISABLED (0x1 21) -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 PATCH 06/12] spl, nand: add option to boot raw u-boot.bin image only
enable to boot only a raw u-boot.bin image from nand with the
CONFIG_SPL_NAND_RAW_ONLY define. This option saves space on
boards where spl space is low.
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
Reviewed-by: Bo Shen voice.s...@atmel.com
---
on the siemens taurus board, this option saved 0x14d bytes
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
README| 4
common/spl/spl.c | 15 ++-
common/spl/spl_nand.c | 13 +
include/spl.h | 1 +
4 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/README b/README
index 7b5538e..a34902b 100644
--- a/README
+++ b/README
@@ -3605,6 +3605,10 @@ FIT uImage format:
Support for the MTD subsystem within SPL. Useful for
environment on NAND support within SPL.
+ CONFIG_SPL_NAND_RAW_ONLY
+ Support to boot only raw u-boot.bin images. Use this only
+ if you need to save space.
+
CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
Set for the SPL on PPC mpc8xxx targets, support for
drivers/ddr/fsl/libddr.o in SPL binary.
diff --git a/common/spl/spl.c b/common/spl/spl.c
index d85bab3..f01a21c 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -62,6 +62,15 @@ __weak void spl_board_prepare_for_linux(void)
/* Nothing to do! */
}
+void spl_set_header_raw_uboot(void)
+{
+ spl_image.size = CONFIG_SYS_MONITOR_LEN;
+ spl_image.entry_point = CONFIG_SYS_UBOOT_START;
+ spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
+ spl_image.os = IH_OS_U_BOOT;
+ spl_image.name = U-Boot;
+}
+
void spl_parse_image_header(const struct image_header *header)
{
u32 header_size = sizeof(struct image_header);
@@ -93,11 +102,7 @@ void spl_parse_image_header(const struct image_header
*header)
/* Signature not found - assume u-boot.bin */
debug(mkimage signature not found - ih_magic = %x\n,
header-ih_magic);
- spl_image.size = CONFIG_SYS_MONITOR_LEN;
- spl_image.entry_point = CONFIG_SYS_UBOOT_START;
- spl_image.load_addr = CONFIG_SYS_TEXT_BASE;
- spl_image.os = IH_OS_U_BOOT;
- spl_image.name = U-Boot;
+ spl_set_header_raw_uboot();
}
}
diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c
index 9b200bc..b7801cb 100644
--- a/common/spl/spl_nand.c
+++ b/common/spl/spl_nand.c
@@ -10,6 +10,18 @@
#include asm/io.h
#include nand.h
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
+void spl_nand_load_image(void)
+{
+ nand_init();
+
+ nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
+ CONFIG_SYS_NAND_U_BOOT_SIZE,
+ (void *)CONFIG_SYS_NAND_U_BOOT_DST);
+ spl_set_header_raw_uboot();
+ nand_deselect();
+}
+#else
void spl_nand_load_image(void)
{
struct image_header *header;
@@ -82,3 +94,4 @@ void spl_nand_load_image(void)
spl_image.size, (void *)spl_image.load_addr);
nand_deselect();
}
+#endif
diff --git a/include/spl.h b/include/spl.h
index 16b3566..b2e5bf7 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -35,6 +35,7 @@ extern struct spl_image_info spl_image;
void preloader_console_init(void);
u32 spl_boot_device(void);
u32 spl_boot_mode(void);
+void spl_set_header_raw_uboot(void);
void spl_parse_image_header(const struct image_header *header);
void spl_board_prepare_for_linux(void);
void __noreturn jump_to_image_linux(void *arg);
--
1.8.3.1
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[U-Boot] [v3 PATCH 01/12] spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header
move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher h...@denx.de --- Changes in v3: rebased against 571bdf16a78e9e116a93d46f4809c4f8a3f2adb6 Changes in v2: rebased against d58a9451e7339ed4cf2b2627e534611f427fb791 new in v2 drivers/spi/atmel_spi.h | 4 include/configs/afeb9260.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/ethernut5.h | 1 - include/configs/meesc.h | 1 - include/configs/otc570.h| 1 - include/configs/pm9261.h| 1 - include/configs/pm9263.h| 1 - include/configs/sbc35_a9g20.h | 1 - include/configs/tny_a9260.h | 1 - include/configs/usb_a9263.h | 1 - 14 files changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index d240945..1538a23 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -94,3 +94,7 @@ static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) readl(as-regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as-regs + ATMEL_SPI_##reg) + +#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#endif diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 14bac15..932a309 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -77,7 +77,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS10xD000 /* CS1 */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 73917b0..72247cc 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -135,7 +135,6 @@ #ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS10xD000 /* CS1 */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 226f8c1..cb16bda 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -107,7 +107,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS30xD000 /* CS3 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b666d94..fa19e8b 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -119,7 +119,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define AT91_SPI_CLK 1500 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b8d5dd1..d5f0197 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -100,7 +100,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define AT91_SPI_CLK 1500 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 4c69af6..ce61a16 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -78,7 +78,6 @@ /* SPI */ #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define AT91_SPI_CLK 1500 /* Serial port */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 86ce5f2..955d0e2 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -124,7 +124,6 @@ #ifdef CONFIG_SYS_USE_DATAFLASH # define CONFIG_ATMEL_DATAFLASH_SPI # define CONFIG_HAS_DATAFLASH -# define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) # define
[U-Boot] [v3 PATCH 02/12] arm, at91: add spi dataflash support for the taurus board
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
- add comment from Jagan Teki:
- remove spi_init_f() from board file
- remove CONFIG_SYS_SPI_WRITE_TOUT from board config file
instead define a default in the spi driver - new patch for v2
board/siemens/taurus/taurus.c | 18 ++
include/configs/taurus.h | 10 ++
2 files changed, 28 insertions(+)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 673b302..76609c7 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -22,6 +22,8 @@
#include asm/arch/gpio.h
#include asm/arch/at91sam9_sdramc.h
#include atmel_mci.h
+#include asm/arch/at91_spi.h
+#include spi.h
#include net.h
#include netdev.h
@@ -127,6 +129,21 @@ int board_early_init_f(void)
return 0;
}
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
+}
+
int board_init(void)
{
/* adress of boot parameters */
@@ -139,6 +156,7 @@ int board_init(void)
#ifdef CONFIG_MACB
taurus_macb_hw_init();
#endif
+ at91_spi0_hw_init(TAURUS_SPI_MASK);
return 0;
}
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index aadf4cd..ba9496f 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -127,6 +127,16 @@
#define CONFIG_USB_STORAGE
#endif
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define TAURUS_SPI_MASK (1 4)
+#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
+
/* load address */
#define CONFIG_SYS_LOAD_ADDR 0x2200
--
1.8.3.1
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[U-Boot] [v3 PATCH 03/12] arm, at91, mpddrc: fix typo in ddr2_init()
use the configure value for computing the ba_off value not the value from the cr register. This leaded in a wrong ram configuration on the upcoming corvus spl board support. Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com --- Changes in v3: ignore 80 characters length as Bo Shen and Adreas Biessmann suggested Changes in v2: add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com arch/arm/cpu/at91-common/mpddrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c index 8136396..f78e4be 100644 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ b/arch/arm/cpu/at91-common/mpddrc.c @@ -26,7 +26,7 @@ int ddr2_init(const unsigned int ram_address, /* Compute bank offset according to NC in configuration register */ ba_off = (mpddr_value-cr ATMEL_MPDDRC_CR_NC_MASK) + 9; if (!(mpddr_value-cr ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)) - ba_off += ((mpddr-cr ATMEL_MPDDRC_CR_NR_MASK) 2) + 11; + ba_off += ((mpddr_value-cr ATMEL_MPDDRC_CR_NR_MASK) 2) + 11; ba_off += (mpddr_value-md ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 PATCH 08/12] spl, nand, atmel_nand: add erase one block function
erase one nand block in spl code. keep it simple, as size matters
This is used on the upcoming taurus spl support.
Signed-off-by: Heiko Schocher h...@denx.de
Acked-by: Scott Wood scottw...@freescale.com
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add Acked-by from Scott Wood
add Reviewed-by from Bo Shen
Changes in v2:
add comment from scott wood:
- move nand_erase_one into include/nand.h and rename it
to spl_nand_erase_one
drivers/mtd/nand/atmel_nand.c | 33 +
include/nand.h| 1 +
2 files changed, 34 insertions(+)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index d506e42..d6d6f85 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1274,6 +1274,39 @@ static int nand_read_page(int block, int page, void *dst)
return 0;
}
+
+int spl_nand_erase_one(int block, int page)
+{
+ struct nand_chip *this = mtd.priv;
+ void (*hwctrl)(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl) = this-cmd_ctrl;
+ int page_addr;
+
+ if (nand_chip.select_chip)
+ nand_chip.select_chip(mtd, 0);
+
+ page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
+ hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ /* Row address */
+ hwctrl(mtd, (page_addr 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+ hwctrl(mtd, ((page_addr 8) 0xff),
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
+ /* One more address cycle for devices 128MiB */
+ hwctrl(mtd, (page_addr 16) 0x0f,
+ NAND_CTRL_ALE | NAND_CTRL_CHANGE);
+#endif
+
+ hwctrl(mtd, NAND_CMD_ERASE2, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
+ udelay(2000);
+
+ while (!this-dev_ready(mtd))
+ ;
+
+ nand_deselect();
+
+ return 0;
+}
#else
static int nand_read_page(int block, int page, void *dst)
{
diff --git a/include/nand.h b/include/nand.h
index fc735d1..15e31ab 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -167,3 +167,4 @@ __attribute__((noreturn)) void nand_boot(void);
#define ENV_OFFSET_SIZE 8
int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
#endif
+int spl_nand_erase_one(int block, int page);
--
1.8.3.1
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[U-Boot] [v3 PATCH 04/12] arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45
- compile mpddrc ram init code also for AT91SAM9M10G45
based boards.
- in CONFIG_SAMA5D3 case, look for the ATMEL_MPDDRC_CR_DECOD_INTERLEAVED
in the cr configuration
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
arch/arm/cpu/at91-common/Makefile | 6 +-
arch/arm/cpu/at91-common/mpddrc.c | 11 ++-
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/at91-common/Makefile
b/arch/arm/cpu/at91-common/Makefile
index 5b97838..f62863a 100644
--- a/arch/arm/cpu/at91-common/Makefile
+++ b/arch/arm/cpu/at91-common/Makefile
@@ -9,4 +9,8 @@
#
obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o
-obj-$(CONFIG_SPL_BUILD) += mpddrc.o spl.o
+ifneq ($(CONFIG_SPL_BUILD),)
+obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o
+obj-$(CONFIG_SAMA5D3) += mpddrc.o
+obj-y += spl.o
+endif
diff --git a/arch/arm/cpu/at91-common/mpddrc.c
b/arch/arm/cpu/at91-common/mpddrc.c
index f78e4be..44798e6 100644
--- a/arch/arm/cpu/at91-common/mpddrc.c
+++ b/arch/arm/cpu/at91-common/mpddrc.c
@@ -17,6 +17,15 @@ static inline void atmel_mpddr_op(int mode, u32 ram_address)
writel(0, ram_address);
}
+static int ddr2_decodtype_is_seq(u32 cr)
+{
+#if defined(CONFIG_SAMA5D3)
+ if (cr ATMEL_MPDDRC_CR_DECOD_INTERLEAVED)
+ return 0;
+#endif
+ return 1;
+}
+
int ddr2_init(const unsigned int ram_address,
const struct atmel_mpddr *mpddr_value)
{
@@ -25,7 +34,7 @@ int ddr2_init(const unsigned int ram_address,
/* Compute bank offset according to NC in configuration register */
ba_off = (mpddr_value-cr ATMEL_MPDDRC_CR_NC_MASK) + 9;
- if (!(mpddr_value-cr ATMEL_MPDDRC_CR_DECOD_INTERLEAVED))
+ if (ddr2_decodtype_is_seq(mpddr_value-cr))
ba_off += ((mpddr_value-cr ATMEL_MPDDRC_CR_NR_MASK) 2) +
11;
ba_off += (mpddr_value-md ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2;
--
1.8.3.1
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[U-Boot] [v3 PATCH 09/12] spl, mtd, nand, atmel_nand: invert device ready pin logic
device ready pin is signalling that the device is ready on state 1
not on 0. Simmiliar as it is in drivers/mtd/nand/nand_spl_simple.c
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
Reviewed-by: Bo Shen voice.s...@atmel.com
Acked-by: Scott Wood scottw...@freescale.com
---
Changes in v3:
add Acked-by from Scott Wood
add Reviewed-by from Bo Shen
Changes in v2:
add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com
drivers/mtd/nand/atmel_nand.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c
index d6d6f85..3b6093a 100644
--- a/drivers/mtd/nand/atmel_nand.c
+++ b/drivers/mtd/nand/atmel_nand.c
@@ -1188,7 +1188,7 @@ static int nand_command(int block, int page, uint32_t
offs, u8 cmd)
void (*hwctrl)(struct mtd_info *mtd, int cmd,
unsigned int ctrl) = this-cmd_ctrl;
- while (this-dev_ready(mtd))
+ while (!this-dev_ready(mtd))
;
if (cmd == NAND_CMD_READOOB) {
@@ -1213,7 +1213,7 @@ static int nand_command(int block, int page, uint32_t
offs, u8 cmd)
hwctrl(mtd, NAND_CMD_READSTART, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (this-dev_ready(mtd))
+ while (!this-dev_ready(mtd))
;
return 0;
@@ -1353,7 +1353,7 @@ int at91_nand_wait_ready(struct mtd_info *mtd)
udelay(this-chip_delay);
- return 0;
+ return 1;
}
int board_nand_init(struct nand_chip *nand)
--
1.8.3.1
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[U-Boot] [v3 PATCH 07/12] mtd: atmel_nand: add missign include
using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com Reviewed-by: Bo Shen voice.s...@atmel.com --- Changes in v3: add Reviewed-by from Bo Shen Changes in v2: add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com drivers/mtd/nand/atmel_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 9114a86..d506e42 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -18,6 +18,7 @@ #include malloc.h #include nand.h #include watchdog.h +#include linux/mtd/nand_ecc.h #ifdef CONFIG_ATMEL_NAND_HWECC -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 PATCH 10/12] arm, spl, at91: add at91sam9260 and at91sam9g45 spl support
add support for using spl code on at91sam9260 and at91sam9g45
based boards.
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add comment from Bo shen
- fix AT91_PMC_MCKR_CSS_MASK and AT91_PMC_MCKR_PRES_MASK
- make matrix_init weak, and add it in the taurus board code
- do not introduce ifdef mess for the differences between the SoCs,
instead use a seperate file for each SoC:
- for armv5 (arm926ejs, now at91 series), named it spl_at91.c,
- for armv7 (cortex-a5, now, sama5d3), named it spl_atmel.c
- move common code to arch/arm/cpu/at91-common/spl.c
Changes in v2: None
arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 22
arch/arm/cpu/arm926ejs/at91/clock.c| 60 ++
arch/arm/cpu/armv7/at91/clock.c| 27 +
arch/arm/cpu/at91-common/Makefile | 5 +-
arch/arm/cpu/at91-common/sdram.c | 77 +
arch/arm/cpu/at91-common/spl.c | 89 +--
arch/arm/cpu/at91-common/spl_at91.c| 124 +
arch/arm/cpu/at91-common/spl_atmel.c | 76 +
arch/arm/include/asm/arch-at91/at91_common.h | 6 +
arch/arm/include/asm/arch-at91/at91_pmc.h | 1 +
arch/arm/include/asm/arch-at91/at91sam9260.h | 1 +
.../arm/include/asm/arch-at91/at91sam9260_matrix.h | 5 +
arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 22 +++-
13 files changed, 424 insertions(+), 91 deletions(-)
create mode 100644 arch/arm/cpu/at91-common/sdram.c
create mode 100644 arch/arm/cpu/at91-common/spl_at91.c
create mode 100644 arch/arm/cpu/at91-common/spl_atmel.c
diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
index cae4abc..7a7fd7d 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c
@@ -8,8 +8,10 @@
#include common.h
#include asm/io.h
+#include asm/arch/at91sam9260_matrix.h
#include asm/arch/at91_common.h
#include asm/arch/at91_pmc.h
+#include asm/arch/at91sam9_sdramc.h
#include asm/arch/gpio.h
/*
@@ -207,3 +209,23 @@ void at91_mci_hw_init(void)
#endif
}
#endif
+
+void at91_sdram_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 17, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 20, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 21, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 25, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 28, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 29, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 30, 0);
+ at91_set_a_periph(AT91_PIO_PORTC, 31, 0);
+}
diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c
b/arch/arm/cpu/arm926ejs/at91/clock.c
index 31315b5..f363982 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -187,3 +187,63 @@ int at91_clock_init(unsigned long main_clock)
return 0;
}
+
+#if !defined(AT91_PLL_LOCK_TIMEOUT)
+#define AT91_PLL_LOCK_TIMEOUT 100
+#endif
+
+void at91_plla_init(u32 pllar)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ int timeout = AT91_PLL_LOCK_TIMEOUT;
+
+ writel(pllar, pmc-pllar);
+ while (!(readl(pmc-sr) (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) {
+ timeout--;
+ if (timeout == 0)
+ break;
+ }
+}
+void at91_pllb_init(u32 pllbr)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ int timeout = AT91_PLL_LOCK_TIMEOUT;
+
+ writel(pllbr, pmc-pllbr);
+ while (!(readl(pmc-sr) (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) {
+ timeout--;
+ if (timeout == 0)
+ break;
+ }
+}
+
+void at91_mck_init(u32 mckr)
+{
+ struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+ int timeout = AT91_PLL_LOCK_TIMEOUT;
+ u32 tmp;
+
+ tmp = readl(pmc-mckr);
+ tmp = ~(AT91_PMC_MCKR_PRES_MASK |
+AT91_PMC_MCKR_MDIV_MASK |
+AT91_PMC_MCKR_PLLADIV_MASK |
+AT91_PMC_MCKR_CSS_MASK);
+ tmp |= mckr (AT91_PMC_MCKR_PRES_MASK |
+ AT91_PMC_MCKR_MDIV_MASK |
+ AT91_PMC_MCKR_PLLADIV_MASK |
+ AT91_PMC_MCKR_CSS_MASK);
+ writel(tmp, pmc-mckr);
+
+ while (!(readl(pmc-sr) AT91_PMC_MCKRDY)) {
+ timeout--;
+ if (timeout == 0)
+ break;
+ }
+}
+
+void
[U-Boot] [v3 PATCH 11/12] arm, at91, spl: add spl support for the taurus board
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add comment from Bo Shen:
- make matrix_init weak, and add it in taurs board code
- add Reviewed-by from Bo Shen
Changes in v2:
- rename function nand_erase_one to spl_nand_erase_one as
Scott Wood suggested
arch/arm/Kconfig | 1 +
board/siemens/taurus/taurus.c | 82 +--
configs/taurus_defconfig | 5 +--
include/configs/taurus.h | 52 ++-
4 files changed, 127 insertions(+), 13 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 171ad03..ab45703 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -210,6 +210,7 @@ config TARGET_CORVUS
select CPU_ARM926EJS
config TARGET_TAURUS
+ select SUPPORT_SPL
bool Support taurus
select CPU_ARM926EJS
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 76609c7..b8ff478 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -21,6 +21,8 @@
#include asm/arch/at91_rstc.h
#include asm/arch/gpio.h
#include asm/arch/at91sam9_sdramc.h
+#include asm/arch/clk.h
+#include linux/mtd/nand.h
#include atmel_mci.h
#include asm/arch/at91_spi.h
#include spi.h
@@ -30,7 +32,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_CMD_NAND
static void taurus_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
@@ -63,15 +64,77 @@ static void taurus_nand_hw_init(void)
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include spl.h
+#include nand.h
+
+void matrix_init(void)
+{
+ struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+
+ writel((readl(mat-scfg[3]) (~AT91_MATRIX_SLOT_CYCLE))
+ | AT91_MATRIX_SLOT_CYCLE_(0x40),
+ mat-scfg[3]);
+}
+
+void at91_spl_board_init(void)
+{
+ taurus_nand_hw_init();
+
+ /* Configure recovery button PINs */
+ at91_set_gpio_input(AT91_PIN_PA31, 1);
+
+ /* check if button is pressed */
+ if (at91_get_gpio_value(AT91_PIN_PA31) == 0) {
+ u32 boot_device;
+
+ debug(Recovery button pressed\n);
+ boot_device = spl_boot_device();
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ break;
+#endif
+ }
+ }
+}
+
+void mem_init(void)
+{
+ struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+ struct sdramc_reg setting;
+
+ at91_sdram_hw_init();
+ setting.cr = (AT91_SDRAMC_NC_9 |
+ AT91_SDRAMC_NR_13 |
+ AT91_SDRAMC_CAS_3 |
+ AT91_SDRAMC_NB_4 |
+ AT91_SDRAMC_DBW_32 |
+ AT91_SDRAMC_TWR_VAL(3) |
+ AT91_SDRAMC_TRC_VAL(9) |
+ AT91_SDRAMC_TRP_VAL(3) |
+ AT91_SDRAMC_TRCD_VAL(3) |
+ AT91_SDRAMC_TRAS_VAL(6) |
+ AT91_SDRAMC_TXSR_VAL(10));
+ setting.mdr = AT91_SDRAMC_MD_SDRAM;
+ setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 100;
+
+
+ writel(readl(ma-ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
+ AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
+ ma-ebicsa);
+ sdramc_initialize(ATMEL_BASE_CS1, setting);
+}
#endif
#ifdef CONFIG_MACB
static void taurus_macb_hw_init(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
/* Enable EMAC clock */
- writel(1 ATMEL_ID_EMAC0, pmc-pcer);
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
/*
* Disable pull-up on:
@@ -119,12 +182,12 @@ int board_mmc_init(bd_t *bd)
int board_early_init_f(void)
{
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
-
/* Enable clocks for all PIOs */
- writel((1 ATMEL_ID_PIOA) | (1 ATMEL_ID_PIOB) |
- (1 ATMEL_ID_PIOC),
- pmc-pcer);
+ at91_periph_clk_enable(ATMEL_ID_PIOA);
+ at91_periph_clk_enable(ATMEL_ID_PIOB);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
+
+ at91_seriald_hw_init();
return 0;
}
@@ -149,7 +212,6 @@ int board_init(void)
/* adress of boot parameters */
gd-bd-bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
- at91_seriald_hw_init();
#ifdef CONFIG_CMD_NAND
taurus_nand_hw_init();
#endif
diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig
[U-Boot] [v3 PATCH 12/12] arm, spl, at91: add spl support for the corvus board
replaces the at91bootstrap code with SPL code.
make the spl image with:
./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin
this writes the length of the spl image into the 6th
execption vector. This is needed from the ROM bootloader.
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
- rename function nand_erase_one to spl_nand_erase_one as
Scott Wood suggested
- add comment from Andreas Biessmann:
rename MPDDRC_CR_EBISHARE to MPDDRC_CR_DQMS_SHARED
arch/arm/Kconfig | 1 +
board/siemens/corvus/board.c | 109 ++-
configs/corvus_defconfig | 5 +-
include/configs/corvus.h | 54 +++--
4 files changed, 151 insertions(+), 18 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ab45703..2471c71 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -206,6 +206,7 @@ config TARGET_PM9G45
select CPU_ARM926EJS
config TARGET_CORVUS
+ select SUPPORT_SPL
bool Support corvus
select CPU_ARM926EJS
diff --git a/board/siemens/corvus/board.c b/board/siemens/corvus/board.c
index f1e93ef..0a11540 100644
--- a/board/siemens/corvus/board.c
+++ b/board/siemens/corvus/board.c
@@ -31,12 +31,10 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_CMD_NAND
static void corvus_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
- struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
unsigned long csa;
/* Enable CS3 */
@@ -63,22 +61,111 @@ static void corvus_nand_hw_init(void)
AT91_SMC_MODE_TDF_CYCLE(3),
smc-cs[3].mode);
- writel(1 ATMEL_ID_PIOC, pmc-pcer);
-
- /* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_periph_clk_enable(ATMEL_ID_PIOC);
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
+
+#if defined(CONFIG_SPL_BUILD)
+#include spl.h
+#include nand.h
+
+void at91_spl_board_init(void)
+{
+ /*
+* For on the sam9m10g45ek board, the chip wm9711 stay in the test
+* mode, so it need do some action to exit mode.
+*/
+ at91_set_gpio_output(AT91_PIN_PD7, 0);
+ at91_set_gpio_output(AT91_PIN_PD8, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
+
+ corvus_nand_hw_init();
+
+ /* Configure recovery button PINs */
+ at91_set_gpio_input(AT91_PIN_PB7, 1);
+
+ /* check if button is pressed */
+ if (at91_get_gpio_value(AT91_PIN_PB7) == 0) {
+ u32 boot_device;
+
+ debug(Recovery button pressed\n);
+ boot_device = spl_boot_device();
+ switch (boot_device) {
+#ifdef CONFIG_SPL_NAND_SUPPORT
+ case BOOT_DEVICE_NAND:
+ nand_init();
+ spl_nand_erase_one(0, 0);
+ break;
#endif
+ }
+ }
+}
-#ifdef CONFIG_CMD_USB
-static void taurus_usb_hw_init(void)
+#include asm/arch/atmel_mpddrc.h
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+ ddr2-md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+ ddr2-cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+ ATMEL_MPDDRC_CR_NR_ROW_14 |
+ ATMEL_MPDDRC_CR_DIC_DS |
+ ATMEL_MPDDRC_CR_DQMS_SHARED |
+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+ ddr2-rtr = 0x24b;
+
+ ddr2-tpr0 = (6 ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+ 2 ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+ 2 ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+ 8 ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 75 ns */
+ 2 ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+ 1 ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+ 1 ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+ 2 ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+ ddr2-tpr1 = (2 ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+ 200 ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+ 16 ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+ 14 ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+ ddr2-tpr2 = (1 ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+ 0 ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+ 7 ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+ 2 ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
{
struct at91_pmc
Re: [U-Boot] [v3 PATCH 07/12] mtd: atmel_nand: add missign include
Hi Heiko, Sorry for missing the subject typo error on v2 review. s/missign/missing. I think it can be corrected when apply. On 10/31/2014 03:31 PM, Heiko Schocher wrote: using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com Reviewed-by: Bo Shen voice.s...@atmel.com --- Changes in v3: add Reviewed-by from Bo Shen Changes in v2: add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com drivers/mtd/nand/atmel_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 9114a86..d506e42 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -18,6 +18,7 @@ #include malloc.h #include nand.h #include watchdog.h +#include linux/mtd/nand_ecc.h #ifdef CONFIG_ATMEL_NAND_HWECC Best Regards, Bo Shen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/29] dm: spi: Add a uclass for SPI
Hi Simon, On 31.10.2014 02:30, Simon Glass wrote: But first let's make sure that you really do have the platform that doesn't use device tree... If it is ARM my understanding is that it should. It does. In the kernel. I think I'll dive into adding DT support for SoCFPGA for a few hours. Perhaps thats even easier than adding platform-data support to the SPI DM. Lets see how this goes... Good luck. If you use CONFIG_OF_SEPARATE you will get u-boot-dtb.bin and hopefully it will just work. For CONFIG_OF_EMBED I see a bug was introduced so I need to do a patch for that. I didn't add any of those defines above. Just CONFIG_OF_CONTROL seems to be needed. I already posted a patch for DT support for SoCFPGA yesterday. And with the addition of the aliases for the spi DT nodes I'm now able use and test the driver... Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v3 PATCH 07/12] mtd: atmel_nand: add missign include
Hello Bo, Am 31.10.2014 08:43, schrieb Bo Shen: Hi Heiko, Sorry for missing the subject typo error on v2 review. s/missign/missing. Ups ... corrected ... I think it can be corrected when apply. That would be great, thanks! bye, Heiko On 10/31/2014 03:31 PM, Heiko Schocher wrote: using this driver in SPL code with CONFIG_SPL_NAND_ECC configured leads in an compileerror. Fix this. Signed-off-by: Heiko Schocher h...@denx.de Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com Reviewed-by: Bo Shen voice.s...@atmel.com --- Changes in v3: add Reviewed-by from Bo Shen Changes in v2: add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com drivers/mtd/nand/atmel_nand.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/nand/atmel_nand.c b/drivers/mtd/nand/atmel_nand.c index 9114a86..d506e42 100644 --- a/drivers/mtd/nand/atmel_nand.c +++ b/drivers/mtd/nand/atmel_nand.c @@ -18,6 +18,7 @@ #include malloc.h #include nand.h #include watchdog.h +#include linux/mtd/nand_ecc.h #ifdef CONFIG_ATMEL_NAND_HWECC Best Regards, Bo Shen -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] blackfin: rename blackfin i2c driver to adi
Hello Scott Jiang,
Am 31.10.2014 08:12, schrieb Scott Jiang:
Hi Heiko,
static int wait_for_completion(struct i2c_msg *msg)
{
- uint16_t int_stat;
+ u16 int_stat, ctl;
This change is not related to the subject of the patch,
please split this into seperate patches ...
ulong timebase = get_timer(0);
do {
- int_stat = twi-int_stat;
+ int_stat = readw(twi-int_stat);
Here too... please fix globally.
This patch is to modify blackfin specific string or api to generic.
So I use standard io api readl/writel here. I'm not sure what you
mean.
The use of the generic i/o accessors would be a seperate patch...
subject something like blackfin i2c: use generic io accessors
and put the rename specific changes into
blackfin: rename blackfin i2c driver to adi
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [v3 PATCH 0/12] arm, at91, spl: add spl support for the taurus and corvus boards
This patchset add SPL support for the AT91SAM9G20 based taurus board, and the AT91SAM9M10G45 based corvus board from siemens, and replaces the at91bootstrap code. The boot.bin which replaces the at91bootstrap image can created with mkimage: ./tools/mkimage -T atmelimage -d spl/u-boot-spl.bin spl/boot.bin For other SoC this step is done in one step ... should we add this also for AT91 based boards? For example add a u-boot.at91 target in the Makefile? This patchset is based on the common updates for the taurus and corvus board: Patchwork [U-Boot] arm, at91: add generic board support for the taurus and corvus board http://patchwork.ozlabs.org/patch/395398/ (now in mainline) Patchwork [U-Boot] arm, at91: add spi dataflash support for the taurus board http://patchwork.ozlabs.org/patch/395400/ Changes in v3: rebased against 571bdf16a78e9e116a93d46f4809c4f8a3f2adb6 add Reviewed-by from Bo Shen add Acked-by from Scott Wood add comment from Bo shen - ignore 80 characters length as Bo Shen and Adreas Biessmann suggested - fix AT91_PMC_MCKR_CSS_MASK and AT91_PMC_MCKR_PRES_MASK - make matrix_init weak, and add it in the taurus board code - do not introduce ifdef mess for the differences between the SoCs, instead use a seperate file for each SoC: - for armv5 (arm926ejs, now at91 series), named it spl_at91.c, - for armv7 (cortex-a5, now, sama5d3), named it spl_atmel.c - move common code to arch/arm/cpu/at91-common/spl.c Changes in v2: - rebased against d58a9451e7339ed4cf2b2627e534611f427fb791 - spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header new in v2 - add comment from Jagan Teki: - remove spi_init_f() from board file - remove CONFIG_SYS_SPI_WRITE_TOUT from board config file instead define a default in the spi driver - new patch for v2 - add Reviewed-by: Andreas Bießmann andreas.de...@googlemail.com - add comment from Andreas Biessmann: rename MPDDRC_CR_EBISHARE to MPDDRC_CR_DQMS_SHARED - add comment from scott wood: move nand_erase_one into include/nand.h and rename it to spl_nand_erase_one Heiko Schocher (12): spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header arm, at91: add spi dataflash support for the taurus board arm, at91, mpddrc: fix typo in ddr2_init() arm, at91: compile mpddrc ram init code also for AT91SAM9M10G45 arm, at91: add missing ddr2 cr register MPDDRC_CR_EBISHARE define spl, nand: add option to boot raw u-boot.bin image only mtd: atmel_nand: add missign include spl, nand, atmel_nand: add erase one block function spl, mtd, nand, atmel_nand: invert device ready pin logic arm, spl, at91: add at91sam9260 and at91sam9g45 spl support arm, at91, spl: add spl support for the taurus board arm, spl, at91: add spl support for the corvus board README | 4 + arch/arm/Kconfig | 2 + arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 22 arch/arm/cpu/arm926ejs/at91/clock.c| 60 ++ arch/arm/cpu/armv7/at91/clock.c| 27 + arch/arm/cpu/at91-common/Makefile | 7 +- arch/arm/cpu/at91-common/mpddrc.c | 13 ++- arch/arm/cpu/at91-common/sdram.c | 77 + arch/arm/cpu/at91-common/spl.c | 89 +-- arch/arm/cpu/at91-common/spl_at91.c| 124 + arch/arm/cpu/at91-common/spl_atmel.c | 76 + arch/arm/include/asm/arch-at91/at91_common.h | 6 + arch/arm/include/asm/arch-at91/at91_pmc.h | 1 + arch/arm/include/asm/arch-at91/at91sam9260.h | 1 + .../arm/include/asm/arch-at91/at91sam9260_matrix.h | 5 + arch/arm/include/asm/arch-at91/at91sam9_sdramc.h | 22 +++- arch/arm/include/asm/arch-at91/atmel_mpddrc.h | 1 + board/siemens/corvus/board.c | 109 -- board/siemens/taurus/taurus.c | 100 +++-- common/spl/spl.c | 15 ++- common/spl/spl_nand.c | 13 +++ configs/corvus_defconfig | 5 +- configs/taurus_defconfig | 5 +- drivers/mtd/nand/atmel_nand.c | 40 ++- drivers/spi/atmel_spi.h| 4 + include/configs/afeb9260.h | 1 - include/configs/at91sam9260ek.h| 1 - include/configs/at91sam9261ek.h| 1 - include/configs/at91sam9263ek.h| 1 - include/configs/at91sam9rlek.h | 1 - include/configs/corvus.h | 54 - include/configs/ethernut5.h| 1 - include/configs/meesc.h| 1 - include/configs/otc570.h | 1 - include/configs/pm9261.h
Re: [U-Boot] Flat Image Tree and boot arguments
Hello,
Thanks for your answer.
I recreated the ITB file and it then showed the load address and entry point
given in the IST during boot execution. This however did not change anything.
Strangely enough a newly compiled kernel image did the trick (although the
original image worked in all other boot methods except for use in an image tree
blob) .
Anyways, thanks again.
Cheers, Chris
-Ursprüngliche Nachricht-
Von: Stephen Warren [mailto:swar...@wwwdotorg.org]
Gesendet: Mittwoch, 29. Oktober 2014 17:36
An: Weiß Christoph; u-boot@lists.denx.de
Cc: Tom Warren
Betreff: Re: [U-Boot] Flat Image Tree and boot arguments
On 10/29/2014 08:22 AM, Weiß Christoph wrote:
Dear all,
I am trying to get my own build of U-Boot to boot Linux on a Jetson TK1
board. As we are pushing for verified boot I am using the Flat Image Tree
(unifying kernel image, device tree blob, ...) to describe my system. U-Boot
can load the ITB file and tries to start the kernel but the system hangs
after this message.
...
images {
kernel@1 {
...
load = 0x81008000;
entry = 0x81008000;
That looks plausible, but ...
...
Tegra124 (Jetson TK1) # bootm 0x9000
## Loading kernel from FIT Image at 9000 ...
Using 'conf@1' configuration
Verifying Hash Integrity ... OK
Trying 'kernel@1' kernel subimage
...
Load Address: 0x
Entry Point: 0x
That looks like it's copying the kernel to address 0, which isn't RAM on this
system. You'd need to track down why the wrong address is being used.
BTW, you may want to contact linux-tegra-b...@nvidia.com for support with L4T.
That said, this aspect of L4T U-Boot should be identical to upstream U-Boot,
since the L4T version is so close to upstream now.
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Re: [U-Boot] DECLARE_GLOBAL_DATA_PTR : move from source to Makefile
Hi, Yamada, thanks for your reply, your reasons for keep this are: 1. 973/6535 = 10.60% in your opinion, 10.60 % is good. - - - - du@sailor:~/u-boot$ grep -R DECLARE_GLOBAL_DATA_PTR ./ | wc -l 973 du@sailor:~/openas/u-boot$ find -name *.[chS] | wc -l 6535 - - - - 2. a source file should only include needed headers I agree with this, but as its name it's a GLOBAL DATA, maybe my method is not the best way to fix this, so forget about it. - - - - anyway, we focus on this question shall u-boot keep this macro in 10% source files? ... duhuanpeng (+86)138 232 25852 (+86)137 190 74147 2014-10-31 15:22 GMT+08:00 Masahiro Yamada yamad...@jp.panasonic.com: Hi Kevin. On Fri, 31 Oct 2014 13:04:38 +0800 Kevin Du Huanpeng u74...@gmail.com wrote: Hi, all, I find this macro is found anywhere in the source, nearly one thousand in the source, looks odd sometime. Only one thousand. We have more than 6000 source files. yamada@beagle:~/workspace/u-boot$ find . -name '*.[ch]' | wc 61586158 198875 yamada@beagle:~/workspace/u-boot$ find . -name '*.[ch]' | xargs grep DECLARE_GLOBAL_DATA_PTR | wc 9441099 54674 I have a idea about this: 1. remove DECLARE_GLOBAL_DATA_PTR from source about one thousand DECLARE_GLOBAL_DATA_PTR in the source 2. add a file like, same as other archs. arch/arm/include/asm/declare_global_data_ptr.h - - - - #ifndef __DECLARE_GLOBAL_DATA_PTR_H #define __DECLARE_GLOBAL_DATA_PTR_H #ifdef CONFIG_ARM64 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (x18) #else #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm (r9) #endif #endif - - - - 3. modify top level Makefile - - - - UBOOTINCLUDE:= \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ -I$(srctree)/arch/$(ARCH)/include \ -include $(srctree)/include/linux/kconfig.h \ + -include $(srctree)/arch/$(ARCH)/include/asm/global_data.h - - - - I do not like this idea. I think a source file should only include needed headers. Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] exynos5: fix GPIO information of exynos5420
Hi Hyungwon,
This patch fixes wrong GPIO information such as GPIO bank,
table which is used to convert GPIO name to index, bank base
address, and etc.
Change-Id: Ideb0f1f10257c9c258f8bca68befc47aed3c43c7
Please remove Change-Id from commits.
(you can run your patch through ./scripts/checkpatch.pl)
Also it is a good practice to use buildman script.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232
+++- 2 files changed, 117 insertions(+),
126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h index 7c5c4ff..da4ac6b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -139,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE 0x0381
-#define EXYNOS5420_GPIO_PART6_BASE 0x0386
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
#define EXYNOS5420_PRO_ID0x1000
#define EXYNOS5420_CLOCK_BASE0x1001
#define EXYNOS5420_POWER_BASE0x1004
@@ -161,11 +161,10 @@
#define EXYNOS5420_I2S_BASE 0x12D6
#define EXYNOS5420_PWMTIMER_BASE 0x12DD
#define EXYNOS5420_SPI_ISP_BASE 0x131A
-#define EXYNOS5420_GPIO_PART2_BASE 0x1340
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x1341
-#define EXYNOS5420_GPIO_PART5_BASE 0x1400
-#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_GPIO_PART1_BASE 0x1340
+#define EXYNOS5420_GPIO_PART2_BASE 0x1341
+#define EXYNOS5420_GPIO_PART3_BASE 0x1400
+#define EXYNOS5420_GPIO_PART4_BASE 0x1401
#define EXYNOS5420_MIPI_DSIM_BASE0x1450
#define EXYNOS5420_DP_BASE 0x145B
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h index 32e045a..431ae3a
100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1028,83 +1028,7 @@ enum exynos5_gpio_pin {
};
enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00,/* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10,/* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20,/* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00,/* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10,/* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20,/* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30,/* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40,/* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00,/* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y70,
EXYNOS5420_GPIO_Y71,
EXYNOS5420_GPIO_Y72,
EXYNOS5420_GPIO_Y73,
@@ -1112,10 +1036,7 @@ enum exynos5420_gpio_pin {
EXYNOS5420_GPIO_Y75,
EXYNOS5420_GPIO_Y76,
EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
-
Re: [U-Boot] Need FTP client support in U-Boot
On Thu, 30 Oct 2014 08:08:44 +0100 Gilles Chanteperdrix gilles.chanteperd...@xenomai.org wrote: On Wed, Oct 29, 2014 at 03:49:15PM +0100, Wolfgang Denk wrote: Dear Madhu, In message 23c3598d8b87452eb6a3d1f52afb8...@sg2pr01mb0394.apcprd01.prod.exchangelabs.com you wrote: We are looking for FTP client command in U-boot commands, So that, we can boot the O.S kernel-image through ftp-client(instead of tftpboot over network). It would have been usful if you had told us whyyou thing the existing network protocols (TFTP, NFS) are not sufficient for your use cases? Hi Wolfgang, if you do not mind me interfering, I have started using HTTP with pxelinux recently, and I can answer this question: for large files (such as large initramfs files, which are practical nowadays since even some embedded boards have gigabytes of RAM), TCP based protocols are much, much faster than TFTP. That is because TFTP is a request/response protocol, which takes one round trip time for every packet asked. TCP based protocols, on the other hand benefit from sending several packets before getting an acknowledge, which means there is a pipelining effect. Hmm. low speed of TFTP protocol in U-boot is not a problem of TFTP protocol itself, but problem of TFTP protocol setup. Here is a trivial 16 MiB file transfer benchmark via GbE network. I use tftp client from busybox package on my linux host. $ time busybox tftp -g -r antony/16M -l 16M tftpserver antony/16M 100% |**| 16384k 0:00:00 ETA real0m6.724s user0m0.076s sys 0m0.532s $ time busybox tftp -g -r antony/16M -l 16M berta -b 64000 antony/16M 100% |**| 16384k 0:00:00 ETA real0m0.229s user0m0.000s sys 0m0.040s $ ls -la 16M -rw-r--r-- 1 antony antony 16777216 Oct 31 12:17 16M So default busybox tftp setup give us only 2.3 MiB while huge transfer block setup give us nearly 70 MiB! Why doesn't the U-boot support FTP client ? FTP is based on TCP/IP, but U-Boot implements just a very minimal set of UDP based protocols. Can we implement/add the FTP client protocol code to U-boot sources and customize. if so, how much work activity involved in this ? Is this just need to write a small ftp-client program file by using TCP stream sockets (as like in Linux) ? Or do we need to write up anything more like TCP/IP network stack.. Right, in the first step you would need to implement a full-blown TCP/IP stack, which would most probably require some other deep-goig changes (keep for example in mind that U-Boot is [intentionally] strictly single-threaded; many implementations don't even support interrupts). The big question is: why should we do that? U-Boot is a boot loader. If you need OS functionality like a full-blown network stack, than just boot an OS ... It seems some bootloader or x86 PXE (I do not know where it is implemented) have TCP support. So, that may not be that uncommon after all, and there is maybe even some code to take from these implementations, because they are also most probably single threaded and not using interrupts. Regards. -- Gilles. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot -- --Â Best regards, Â Antony Pavlov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Need FTP client support in U-Boot
On Fri, 31 Oct 2014 12:35:18 +0400 Antony Pavlov antonynpav...@gmail.com wrote: $ time busybox tftp -g -r antony/16M -l 16M tftpserver ^^ antony/16M 100% |**| 16384k 0:00:00 ETA real0m6.724s user0m0.076s sys 0m0.532s $ time busybox tftp -g -r antony/16M -l 16M berta -b 64000 ^ Sorry, I have forgotten to change berta - tftpserver for the second run. The tftp-server for both runs is the same ;) --Â Best regards, Â Antony Pavlov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.
Change-Id: Ia45d119a62b126f2328684485b8c372ba6acbe00
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/cpu/armv7/exynos/Kconfig | 4 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 72 ++
board/samsung/odroid-xu3/Kconfig | 12 ++
board/samsung/odroid-xu3/MAINTAINERS | 6 +
board/samsung/odroid-xu3/Makefile | 7 +
board/samsung/odroid-xu3/odroid-xu3.c | 132 ++
board/samsung/odroid-xu3/setup.h | 123 +
configs/odroid-xu3_defconfig | 4 +
include/configs/odroid_xu3.h | 243 ++
10 files changed, 605 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
create mode 100644 board/samsung/odroid-xu3/Kconfig
create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
create mode 100644 board/samsung/odroid-xu3/Makefile
create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
create mode 100644 board/samsung/odroid-xu3/setup.h
create mode 100644 configs/odroid-xu3_defconfig
create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig
index 3a25fee..a47cb34 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -22,6 +22,9 @@ config TARGET_TRATS2
config TARGET_ODROID
bool Exynos4412 Odroid board
+config TARGET_ODROID_XU3
+ bool Exynos5422 Odroid board
+
config TARGET_ARNDALE
bool Exynos5250 Arndale board
select OF_CONTROL if !SPL_BUILD
@@ -60,6 +63,7 @@ source board/samsung/universal_c210/Kconfig
source board/samsung/origen/Kconfig
source board/samsung/trats2/Kconfig
source board/samsung/odroid/Kconfig
+source board/samsung/odroid-xu3/Kconfig
source board/samsung/arndale/Kconfig
source board/samsung/smdk5250/Kconfig
source board/samsung/smdk5420/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2dcfcc0..66191f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
b/arch/arm/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 000..34f52c6
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,72 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos54xx.dtsi
+
+/ {
+ model = Odroid XU3 based on EXYNOS5422;
+ compatible = samsung,odroidxu3, samsung,exynos5;
+
+ config {
+ hwid = smdk5420 TEST A-A 9382;
+ };
+
+ aliases {
+ serial0 = /serial@12C0;
+ console = /serial@12C2;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x4000 0x1000
+ 0x5000 0x1000
+ 0x6000 0x1000
+ 0x7000 0x1000
+ 0x8000 0x1000
+ 0x9000 0x1000
+ 0xa000 0x1000
+ 0xb000 0xea0;
+ };
+
+ serial@12C2 {
+ status=okay;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca {
+ #address-cells = 1;
+ #size-cells = 0;
+ pmic@66 {
+ reg = 0x66;
+ compatible = samsung,s2mps11-pmic;
+ };
+ };
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ samsung,removable = 0;
+ samsung,pre-init;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ samsung,removable = 1;
+ };
+
+ mmc@1223 {
+ status = disabled;
+ };
+};
diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig
new file mode 100644
index 000..6159692
--- /dev/null
+++ b/board/samsung/odroid-xu3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default odroid-xu3
+
+config SYS_VENDOR
+ default samsung
+
+config SYS_CONFIG_NAME
+ default odroid_xu3
+
+endif
diff --git a/board/samsung/odroid-xu3/MAINTAINERS
b/board/samsung/odroid-xu3/MAINTAINERS
new file mode 100644
[U-Boot] [PATCH 1/3] exynos5: fix GPIO information of exynos5420
This patch fixes wrong GPIO information such as GPIO bank, table which is used
to convert GPIO name to index, bank base address, and etc.
I have done this work on the patchset submitted by Akshay Saraswat.
https://patchwork.ozlabs.org/patch/400043/
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232 +++-
2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 7c5c4ff..da4ac6b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -139,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE0x0381
-#define EXYNOS5420_GPIO_PART6_BASE 0x0386
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
#define EXYNOS5420_PRO_ID 0x1000
#define EXYNOS5420_CLOCK_BASE 0x1001
#define EXYNOS5420_POWER_BASE 0x1004
@@ -161,11 +161,10 @@
#define EXYNOS5420_I2S_BASE0x12D6
#define EXYNOS5420_PWMTIMER_BASE 0x12DD
#define EXYNOS5420_SPI_ISP_BASE0x131A
-#define EXYNOS5420_GPIO_PART2_BASE 0x1340
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x1341
-#define EXYNOS5420_GPIO_PART5_BASE 0x1400
-#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_GPIO_PART1_BASE 0x1340
+#define EXYNOS5420_GPIO_PART2_BASE 0x1341
+#define EXYNOS5420_GPIO_PART3_BASE 0x1400
+#define EXYNOS5420_GPIO_PART4_BASE 0x1401
#define EXYNOS5420_MIPI_DSIM_BASE 0x1450
#define EXYNOS5420_DP_BASE 0x145B
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 32e045a..431ae3a 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1028,83 +1028,7 @@ enum exynos5_gpio_pin {
};
enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00,/* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10,/* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20,/* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00,/* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10,/* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20,/* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30,/* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40,/* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00,/* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y70,
EXYNOS5420_GPIO_Y71,
EXYNOS5420_GPIO_Y72,
EXYNOS5420_GPIO_Y73,
@@ -1112,10 +1036,7 @@ enum exynos5420_gpio_pin {
EXYNOS5420_GPIO_Y75,
EXYNOS5420_GPIO_Y76,
EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
- EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+
[U-Boot] [PATCH 2/3] Exynos5800: Add support for Exynos5800
The gpios of Exynos5800 are different from that of Exynos5420. This patch adds
the gpio information and table of Exynos5800.
Change-Id: Ic609973ab531e2b6ee9a68cfec0b6b9571f203a8
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31 +--
drivers/gpio/s5p_gpio.c | 4 +++-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 431ae3a..8f82ef0 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT },
};
+#define EXYNOS5800_GPIO_NUM_PARTS 4
+static struct gpio_info exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
{ 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[] = {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char *name)
*/
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
--
1.8.3.2
___
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Re: [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
Hi Ian, On 30 October 2014 04:14, Ian Campbell i...@hellion.org.uk wrote: On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote: Hi, On 10/30/2014 10:08 AM, Ian Campbell wrote: On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote: In the meantime could we somehow replace/augment the #ifdef chain in gpio_init with something keyed off the stdout alias perhaps? Tegra has code to convert a device interrupt number (which uniquely identifies a peripheral in that SoC) to an internal peripheral ID, then these is a function which can enable a peripheral given the ID (funcmux). In some cases you could have multiple options for the funcmux, but there is no easy way to support this. I think that although there are multiple options for some functions (UARTs come to mind) we haven't yet found the need to make any dynamic choices, so it's all static right now. But this approach might be good enough for sunxi. We can easily write the function to enable the pins for a particular port, and this could go in arch/arm/...sunxi/ perhaps. I'm ok with it so long as it isn't going to stand in the way of proper dt based pinmux in the future. One way to help with that might be to use the allwinner,function property in DT as the funcmux name. Hans, what do you think? I'm not 100% sure what you're suggesting here, are you suggesting to have a 1:1 mapping between function names as stored in allwinner,function in dts and the value to pass to sunxi_gpio_set_cfgpin ? I was imagining a function which would take the string uart0 and would call sunxi_gpio_set_cfgpin with whatever values that would entail in order to make uart0 work, not one which would try and return something that the caller would then use. I assume that it will take a string, e.g. uart0 and a pin, since uart0 can be routed to either porta or portb, other then that having the function directly call sunxi_gpio_set_cfgpin rather then returning the value to pass to sunxi_gpio_set_cfgpin is a good idea. This is not going to fly very far, e.g. the uart0 function has cfg value of 2 on portb while it has a value of 4 on portf. I believe we currently statically use either portb or portf (I've not looked up which, IIRC it changed recently, but I don't recall which way), so my proposed function would just DTRT. Of course if we ever find we need something more dynamic then we would have to do a proper pinmux implementation (or at least something closer to a proper one) Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming for something which we could eventually use to get the info from devicetree and not have any uart info hardcoded into the binaries at all. Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI
On Friday, October 31, 2014 at 08:09:21 AM, Jagan Teki wrote: On 30 October 2014 22:59, Marek Vasut ma...@denx.de wrote: On Thursday, October 30, 2014 at 03:38:40 PM, Jagan Teki wrote: On 30 October 2014 15:00, Marek Vasut ma...@denx.de wrote: Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Vince Bridgers vbrid...@altera.com Cc: Pavel Machek pa...@denx.de Cc: Stefan Roese s...@denx.de --- include/configs/socfpga_common.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED3000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI Yes, the address is not fixed, since this is FPGA IP. May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config. You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] Exynos5422: Add support for Exynos5422
Hi Hyungwon,
This patch adds support for Exynos5422 including GPIO, clock,
pinmux, and cpu id.
Change-Id: Ic609973ab531e2b6ee9a68cfec0b6b9571f203a8
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31
+--
drivers/gpio/s5p_gpio.c | 4 +++- 2 files changed, 32
insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0
100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] =
{ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, };
+#define EXYNOS5800_GPIO_NUM_PARTS4
+static struct gpio_info
exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info
*get_gpio_data(void) static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = { { 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[] = {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char
*name) */
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
I'm a bit confused here.
We already support exynos5420 in the mainline. It only slightly
differs from Exynos5422. Additionally there is Exynos5800 which is a
different HW revision of Exynos5422.
In the message topic you stated that you add support for Exynos5422.
Maybe we could use Exynos5800 name also for Exynos5422 (with a big,
fat note about those two chips compliance added to ./doc directory)?
@ Akshay, Minkyu:
What do you think about this idea?
--
Best regards,
Lukasz Majewski
Samsung RD Institute Poland (SRPOL) | Linux Platform Group
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Re: [U-Boot] [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI
On 31 October 2014 14:36, Marek Vasut ma...@denx.de wrote: On Friday, October 31, 2014 at 08:09:21 AM, Jagan Teki wrote: On 30 October 2014 22:59, Marek Vasut ma...@denx.de wrote: On Thursday, October 30, 2014 at 03:38:40 PM, Jagan Teki wrote: On 30 October 2014 15:00, Marek Vasut ma...@denx.de wrote: Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Vince Bridgers vbrid...@altera.com Cc: Pavel Machek pa...@denx.de Cc: Stefan Roese s...@denx.de --- include/configs/socfpga_common.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED3000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI Yes, the address is not fixed, since this is FPGA IP. May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config. You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea. In that case - It's true. Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arm: socfpga: Add example config entry for EPCS/EPCQ SPI
On Friday, October 31, 2014 at 10:16:20 AM, Jagan Teki wrote: On 31 October 2014 14:36, Marek Vasut ma...@denx.de wrote: On Friday, October 31, 2014 at 08:09:21 AM, Jagan Teki wrote: On 30 October 2014 22:59, Marek Vasut ma...@denx.de wrote: On Thursday, October 30, 2014 at 03:38:40 PM, Jagan Teki wrote: On 30 October 2014 15:00, Marek Vasut ma...@denx.de wrote: Add example config file entry for the Altera SPI controller. This SPI controller can also, under special conditions, be used to operate the EPCS/EPCQ SPI NOR. Signed-off-by: Marek Vasut ma...@denx.de Cc: Chin Liang See cl...@altera.com Cc: Dinh Nguyen dingu...@opensource.altera.com Cc: Vince Bridgers vbrid...@altera.com Cc: Pavel Machek pa...@denx.de Cc: Stefan Roese s...@denx.de --- include/configs/socfpga_common.h | 19 +++ 1 file changed, 19 insertions(+) diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 83a1bcd..1df886b 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -79,6 +79,25 @@ #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS /* + * EPCS/EPCQx1 Serial Flash Controller + */ +#ifdef CONFIG_ALTERA_SPI +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED3000 +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_BAR +/* + * The base address is configurable in QSys, each board must specify the + * base address based on it's particular FPGA configuration. Please note + * that the address here is incremented by 0x400 from the Base address + * selected in QSys, since the SPI registers are at offset +0x400. + * #define CONFIG_SYS_SPI_BASE 0xff240400 So each board-specific config header will define CONFIG_SYS_SPI_BASE is it? for using ALTERA_SPI Yes, the address is not fixed, since this is FPGA IP. May be use conditional ifdef with CONFIG_SYS_SPI_BASE instead of CONFIG_ALTERA_SPI so who ever use SPI on their board will define CONFIG_SYS_SPI_BASE config. You can have different SPI controllers enabled on the SoCFPGA, so enabling CONFIG_ALTERA_SPI explicitly in case CONFIG_SYS_SPI_BASE is defined is a very bad idea. In that case - It's true. Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.t...@gmail.com Applied to u-boot-socfpga, thanks. Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] Exynos5422: Add support for Exynos5422
Hi,
On Fri, 31 Oct 2014 10:08:34 +0100
Lukasz Majewski l.majew...@samsung.com wrote:
Hi Hyungwon,
This patch adds support for Exynos5422 including GPIO, clock,
pinmux, and cpu id.
Change-Id: Ic609973ab531e2b6ee9a68cfec0b6b9571f203a8
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31
+--
drivers/gpio/s5p_gpio.c | 4 +++- 2 files changed, 32
insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0
100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] =
{ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, };
+#define EXYNOS5800_GPIO_NUM_PARTS 4
+static struct gpio_info
exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info
*get_gpio_data(void) static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = { { 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[] = {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char
*name) */
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
I'm a bit confused here.
We already support exynos5420 in the mainline. It only slightly
differs from Exynos5422. Additionally there is Exynos5800 which is a
different HW revision of Exynos5422.
Yes. You're right. I was not in the subscriber list when I send this mail. So
when I sent this mail, I received an auto-replied mail which I can cancel this
email. I canceled this mail. But the mail sent to your and Minkyu Kang was not.
Sorry for the confusion. Please refer the latest mail.
In the message topic you stated that you add support for Exynos5422.
Maybe we could use Exynos5800 name also for Exynos5422 (with a big,
fat note about those two chips compliance added to ./doc directory)?
@ Akshay, Minkyu:
What do you
Re: [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
On Fri, 2014-10-31 at 10:07 +0100, Hans de Goede wrote: Hi Ian, On 30 October 2014 04:14, Ian Campbell i...@hellion.org.uk wrote: On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote: Hi, On 10/30/2014 10:08 AM, Ian Campbell wrote: On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote: In the meantime could we somehow replace/augment the #ifdef chain in gpio_init with something keyed off the stdout alias perhaps? Tegra has code to convert a device interrupt number (which uniquely identifies a peripheral in that SoC) to an internal peripheral ID, then these is a function which can enable a peripheral given the ID (funcmux). In some cases you could have multiple options for the funcmux, but there is no easy way to support this. I think that although there are multiple options for some functions (UARTs come to mind) we haven't yet found the need to make any dynamic choices, so it's all static right now. But this approach might be good enough for sunxi. We can easily write the function to enable the pins for a particular port, and this could go in arch/arm/...sunxi/ perhaps. I'm ok with it so long as it isn't going to stand in the way of proper dt based pinmux in the future. One way to help with that might be to use the allwinner,function property in DT as the funcmux name. Hans, what do you think? I'm not 100% sure what you're suggesting here, are you suggesting to have a 1:1 mapping between function names as stored in allwinner,function in dts and the value to pass to sunxi_gpio_set_cfgpin ? I was imagining a function which would take the string uart0 and would call sunxi_gpio_set_cfgpin with whatever values that would entail in order to make uart0 work, not one which would try and return something that the caller would then use. I assume that it will take a string, e.g. uart0 and a pin, since uart0 can be routed to either porta or portb, other then that having the function directly call sunxi_gpio_set_cfgpin rather then returning the value to pass to sunxi_gpio_set_cfgpin is a good idea. Actually right now we don't actually dynamically select anything for uarts, so we could just as easily hardcode which pins to use in this new function as we do now, it's still a step in the right direction. This is not going to fly very far, e.g. the uart0 function has cfg value of 2 on portb while it has a value of 4 on portf. I believe we currently statically use either portb or portf (I've not looked up which, IIRC it changed recently, but I don't recall which way), so my proposed function would just DTRT. Of course if we ever find we need something more dynamic then we would have to do a proper pinmux implementation (or at least something closer to a proper one) Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming for something which we could eventually use to get the info from devicetree and not have any uart info hardcoded into the binaries at all. What I'm really hoping for is to enable Simon to get his DM series accepted, but in a way which won't get in the way of future work to use DT fully. Even better if it takes us a little nearer to the full DT path, at least in terms of the interfaces used. This subthreaded initially started with the suggestion from Simon: We can easily write the function to enable the pins for a particular port, and this could go in arch/arm/...sunxi/ perhaps.. Which sounded OK to me so long as it doesn't get in the way of future work to fully use DT. So with that in mind I suggested that using the DT function name as the key passed to that function would help achieve that aim. My thinking was that this function would be a nexus point where we could independently replace the callers (individually on a driver by driver basis) with code parsing the DT to find the function name and the backend with code to lookup the correct pinmux stuff in DT and do the necessary setup. Maybe I've misjudged what the final DT pinmux thing would look like though, in which case maybe this suggestion doesn't actually achieve the aim of not getting in the way. Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
Hi, On 10/31/2014 10:30 AM, Ian Campbell wrote: On Fri, 2014-10-31 at 10:07 +0100, Hans de Goede wrote: Hi Ian, On 30 October 2014 04:14, Ian Campbell i...@hellion.org.uk wrote: On Thu, 2014-10-30 at 10:36 +0100, Hans de Goede wrote: Hi, On 10/30/2014 10:08 AM, Ian Campbell wrote: On Wed, 2014-10-29 at 13:28 -0600, Simon Glass wrote: In the meantime could we somehow replace/augment the #ifdef chain in gpio_init with something keyed off the stdout alias perhaps? Tegra has code to convert a device interrupt number (which uniquely identifies a peripheral in that SoC) to an internal peripheral ID, then these is a function which can enable a peripheral given the ID (funcmux). In some cases you could have multiple options for the funcmux, but there is no easy way to support this. I think that although there are multiple options for some functions (UARTs come to mind) we haven't yet found the need to make any dynamic choices, so it's all static right now. But this approach might be good enough for sunxi. We can easily write the function to enable the pins for a particular port, and this could go in arch/arm/...sunxi/ perhaps. I'm ok with it so long as it isn't going to stand in the way of proper dt based pinmux in the future. One way to help with that might be to use the allwinner,function property in DT as the funcmux name. Hans, what do you think? I'm not 100% sure what you're suggesting here, are you suggesting to have a 1:1 mapping between function names as stored in allwinner,function in dts and the value to pass to sunxi_gpio_set_cfgpin ? I was imagining a function which would take the string uart0 and would call sunxi_gpio_set_cfgpin with whatever values that would entail in order to make uart0 work, not one which would try and return something that the caller would then use. I assume that it will take a string, e.g. uart0 and a pin, since uart0 can be routed to either porta or portb, other then that having the function directly call sunxi_gpio_set_cfgpin rather then returning the value to pass to sunxi_gpio_set_cfgpin is a good idea. Actually right now we don't actually dynamically select anything for uarts, so we could just as easily hardcode which pins to use in this new function as we do now, it's still a step in the right direction. This is not going to fly very far, e.g. the uart0 function has cfg value of 2 on portb while it has a value of 4 on portf. I believe we currently statically use either portb or portf (I've not looked up which, IIRC it changed recently, but I don't recall which way), so my proposed function would just DTRT. Of course if we ever find we need something more dynamic then we would have to do a proper pinmux implementation (or at least something closer to a proper one) Ah, so you mainly just want to clean up the existing #ifdef mess ? I was aiming for something which we could eventually use to get the info from devicetree and not have any uart info hardcoded into the binaries at all. What I'm really hoping for is to enable Simon to get his DM series accepted, but in a way which won't get in the way of future work to use DT fully. Even better if it takes us a little nearer to the full DT path, at least in terms of the interfaces used. Ah, but I plan to merge the v3 Simon has posted to u-boot-sunxi/next and then do a pull-req with that in there this weekend. IOW we don't need to solve the pinmux problem for that series to get merged (from my pov). So maybe we should just delay dealing with the pinmux issue until we really need to ? Regards, Hans ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mtd, cfi, ubi: add missing writebufsize initialization
ff94bc40af3481d47546595ba73c136de6af6929 mtd, ubi, ubifs: resync with Linux-3.14 introduced the writebufsize field in struct mtd_info, which is not initialized in the cfi_flash driver, which leads in not working ubi on cfi flashes. Fix it Signed-off-by: Heiko Schocher h...@denx.de Reported-by: Andrew Ruder andrew.ru...@elecsyscorp.com --- @Andrew: could you test this patch, if it solves your issue? drivers/mtd/cfi_mtd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff..894858e 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd-flags = MTD_CAP_NORFLASH; mtd-size = fi-size; mtd-writesize = 1; + mtd-writebufsize = mtd-writesize; mtd-_erase = cfi_mtd_erase; mtd-_read = cfi_mtd_read; -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd, cfi, ubi: add missing writebufsize initialization
Hi Heiko, On 31.10.2014 10:39, Heiko Schocher wrote: ff94bc40af3481d47546595ba73c136de6af6929 mtd, ubi, ubifs: resync with Linux-3.14 introduced the writebufsize field in struct mtd_info, which is not initialized in the cfi_flash driver, which leads in not working ubi on cfi flashes. Fix it Signed-off-by: Heiko Schocher h...@denx.de Reported-by: Andrew Ruder andrew.ru...@elecsyscorp.com --- @Andrew: could you test this patch, if it solves your issue? drivers/mtd/cfi_mtd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff..894858e 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd-flags = MTD_CAP_NORFLASH; mtd-size= fi-size; mtd-writesize = 1; + mtd-writebufsize = mtd-writesize; Small nitpicking comment: Could you please align the = to those lines above? Thanks! Other than that: Acked-by: Stefan Roese s...@denx.de Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 2/7] Exynos5800: Add DTS for new board Peach-Pi
We have a new board Peach-Pi similar to Peach-Pit. Peach-Pi
differs from Peach-Pit in configuration factors like display
resolution, memory size, SoC version etc.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Rebased this patch
Changes since v1:
- Rebased this patch
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/exynos5800-peach-pi.dts | 157 +++
2 files changed, 159 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c346063..2b9bd93 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -11,7 +11,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-snow.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
- exynos5420-peach-pit.dtb
+ exynos5420-peach-pit.dtb \
+ exynos5800-peach-pi.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5800-peach-pi.dts
b/arch/arm/dts/exynos5800-peach-pi.dts
new file mode 100644
index 000..8aedf8e
--- /dev/null
+++ b/arch/arm/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,157 @@
+/*
+ * SAMSUNG/GOOGLE Peach-Pit board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+#include exynos54xx.dtsi
+
+/ {
+ model = Samsung/Google Peach Pi board based on Exynos5800;
+
+ compatible = google,pit-rev#, google,pit,
+ google,peach, samsung,exynos5800, samsung,exynos5;
+
+ config {
+ google,bad-wake-gpios = gpio 0x56 0; /* gpx0-6 */
+ hwid = PIT TEST A-A 7848;
+ lazy-init = 1;
+ };
+
+ aliases {
+ serial0 = /serial@12C3;
+ console = /serial@12C3;
+ pmic = /i2c@12ca;
+ };
+
+ dmc {
+ mem-manuf = samsung;
+ mem-type = ddr3;
+ clock-frequency = 8;
+ arm-frequency = 17;
+ };
+
+ tmu@1006 {
+ samsung,min-temp= 25;
+ samsung,max-temp= 125;
+ samsung,start-warning = 95;
+ samsung,start-tripping = 105;
+ samsung,hw-tripping = 110;
+ samsung,efuse-min-value = 40;
+ samsung,efuse-value = 55;
+ samsung,efuse-max-value = 100;
+ samsung,slope = 274761730;
+ samsung,dc-value= 25;
+ };
+
+ /* MAX77802 is on i2c bus 4 */
+ i2c@12ca {
+ clock-frequency = 40;
+ power-regulator@9 {
+ compatible = maxim,max77802-pmic;
+ reg = 0x9;
+ };
+ };
+
+ i2c@12cd { /* i2c7 */
+ clock-frequency = 10;
+ soundcodec@20 {
+ reg = 0x20;
+ compatible = maxim,max98090-codec;
+ };
+
+ edp-lvds-bridge@48 {
+ compatible = parade,ps8625;
+ reg = 0x48;
+ };
+ };
+
+sound@383 {
+samsung,codec-type = max98090;
+};
+
+ i2c@12e1 { /* i2c9 */
+ clock-frequency = 40;
+tpm@20 {
+compatible = infineon,slb9645-tpm;
+reg = 0x20;
+ };
+ };
+
+ spi@12d3 { /* spi1 */
+ spi-max-frequency = 5000;
+ firmware_storage_spi: flash@0 {
+ reg = 0;
+
+ /*
+* A region for the kernel to store a panic event
+* which the firmware will add to the log.
+ */
+ elog-panic-event-offset = 0x01e0 0x10;
+
+ elog-shrink-size = 0x400;
+ elog-full-threshold = 0xc00;
+ };
+ };
+
+ spi@12d4 { /* spi2 */
+ spi-max-frequency = 400;
+ spi-deactivate-delay = 200;
+ cros-ec@0 {
+ reg = 0;
+ compatible = google,cros-ec;
+ spi-half-duplex;
+ spi-max-timeout-ms = 1100;
+ spi-frame-header = 0xec;
+ ec-interrupt = gpio 93 1; /* GPX1_5 */
+
+ /*
+* This describes the flash memory within the EC. Note
+* that the STM32L flash erases to 0, not 0xff.
+*/
+
Re: [U-Boot] [PATCH v2 0/6] Addition of new board Peach-Pi
Hi Simon, Hi Simon, Apologies for the delay in reply. I was out of office. Hi Akshay, On 17 October 2014 11:52, Simon Glass wrote: Hi Akshay, On 15 October 2014 18:38, Akshay Saraswat wrote: Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board. Changes since v1: - Rebased all the patches. Sadly this still doesn't work for me. I'll try to debug it. Here's what I found. I am using Pi MP dated in April. 1. It won't boot at all with the patches, but if I change ARM frequency in the device tree from 1700 MHz to 900 MHz then it will boot into SPL OK. This is the same issue as I have on Pit. I'm not sure why this is. See U-Boot mainline commit e4d7610 for what I did. I don't know why this is happening because, as far as I know, right now we are running both 5420 and 5800 at 900 MHz. We are not using dmc node to extract and scale to the max freq value. I will check again and fix any side effects due to this. 2. USB boot hangs in the IROM - it gets as far as calling the IROM to load from USB, but dies in the IROM and does not return. So USB loads BL1, BL2 but will not load U-Boot. I wonder if the IROM USB entry point has changed for this chip? No, as far as I know, IROM USB entry points are same because we are using same entry point in firmware-pit-4482.B branch, which works fine. IROM USB entry point is same but the function prototype for USB download has changed in this SoC. Vadim has already done changes to fix this issue. I am pushing a new patch-set with that patch included. I have tested USB download and SD boot over PV1 and 2 and both works fine for me. Please let me know if it works at your end. 3. SD boot works OK and gets as far as U-Boot, but it dies inside initcall_run_list() called from board_init_f(). It seems to crash on the first function call. I can't really explain that at all. The first call is to setup_mon_len() and if I call that explicitly then it works fine. On my board SD boot works fine and I see U-Boot prompt everytime I boot. So I wonder if the SDRAM init is broken in some way, and there is some other problem with USB. I compared and found SDRAM init same as the one in firmware-pit-4482.B branch. It should not be the cause. In terms of testing with USB download, you should be able to use a simple script that calls smdk_usbdl three times, once each with BL1, BL2 and U-Boot. You might need a short sleep before the first one. I can help you debug cros_bundle_firmware but at present there is not much point since there seems to be some other problem. I changed download_list in ExynosFlashImage of write_firmware.py script to load my bins instead of the ones residing in firmware directory. It works fine for Pit but for Pi, it fails while loading u-boot-dtb.bin and EC log shows XPSHOLD not seen in time which is very strange because if SPL was not executed who was trying to download u-boot binary. I will now try to fix this download failure. Regards, Simon I couldn't find any MP board here. Tested these patches over PV1 and PV2. Steps I followed for testing - $ make peach-pi_config $ make -j32 $ sudo dd if=u-boot.bl1.bin of=/dev/sdc bs=512 seek=1 $ sudo dd if=spl/smdk5420-spl.bin of=/dev/sdc bs=512 seek=17 $ sudo dd if=u-boot-dtb.bin of=/dev/sdc bs=512 seek=49 Console Log - U-Boot 2014.10-rc2-17295-g8ecd390-dirty (Oct 30 2014 - 17:23:07) for Peach-Pi CPU: Exynos5800@900MHz Board: Samsung/Google Peach Pi board based on Exynos5800 I2C: ready DRAM: 3.5 GiB trace: copying 0008bb3c bytes of early data from 5000 to febfb000 trace: enabled MMC: EXYNOS DWMMC: 0, EXYNOS DWMMC: 1 SF: Detected W25Q32DW with page size 256 Bytes, erase size 4 KiB, total 4 MiB TPS65090 PMIC EC init exynos_lcd_power_on: ps8625_init() failed DP Change lane bw to 1.62Gbps DP dp_sw_link_traning() failed DP link training fail In:serial Out: lcd Err: lcd Net: No ethernet found. Hit any key to stop autoboot: 0 Peach-Pi # Peach-Pi # Thanks Regards, Akshay Saraswat Regards, Akshay Saraswat ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 1/7] Exynos5800: Introduce new proid for Exynos5800
This patch intends to add a new proid for Exynos5800 which is a
variant of Exynos5420. Product id for Exynos5800 is 0x5422.
Both Exynos5420 and Exynos5800 are pin to pin compitable. This
gives us an advantage of reusing Exynos5420 clock, pinmux, memory
and other settings.
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Rebased this patch
Changes since v1:
- Rebased this patch
arch/arm/cpu/armv7/exynos/clock.c | 19 ++-
arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +-
arch/arm/cpu/armv7/exynos/pinmux.c | 2 +-
arch/arm/include/asm/arch-exynos/cpu.h | 10 +-
arch/arm/include/asm/arch-exynos/gpio.h| 4 ++--
5 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 7558eff..4ecce44 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -118,7 +118,8 @@ static int exynos_get_pll_clk(int pllreg, unsigned int r,
unsigned int k)
div = PLL_DIV_1024;
else if (proid_is_exynos4412())
div = PLL_DIV_65535;
- else if (proid_is_exynos5250() || proid_is_exynos5420())
+ else if (proid_is_exynos5250() || proid_is_exynos5420()
+|| proid_is_exynos5800())
div = PLL_DIV_65536;
else
return 0;
@@ -1581,7 +1582,7 @@ static unsigned long exynos4_get_i2c_clk(void)
unsigned long get_pll_clk(int pllreg)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pll_clk(pllreg);
return exynos5_get_pll_clk(pllreg);
} else {
@@ -1617,7 +1618,7 @@ unsigned long get_i2c_clk(void)
unsigned long get_pwm_clk(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_pwm_clk();
return clock_get_periph_rate(PERIPH_ID_PWM0);
} else {
@@ -1630,7 +1631,7 @@ unsigned long get_pwm_clk(void)
unsigned long get_uart_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_uart_clk(dev_index);
return exynos5_get_uart_clk(dev_index);
} else {
@@ -1643,7 +1644,7 @@ unsigned long get_uart_clk(int dev_index)
unsigned long get_mmc_clk(int dev_index)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_mmc_clk(dev_index);
return exynos5_get_mmc_clk(dev_index);
} else {
@@ -1654,7 +1655,7 @@ unsigned long get_mmc_clk(int dev_index)
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_mmc_clk(dev_index, div);
else
exynos5_set_mmc_clk(dev_index, div);
@@ -1668,7 +1669,7 @@ unsigned long get_lcd_clk(void)
if (cpu_is_exynos4())
return exynos4_get_lcd_clk();
else {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_get_lcd_clk();
else
return exynos5_get_lcd_clk();
@@ -1682,7 +1683,7 @@ void set_lcd_clk(void)
else {
if (proid_is_exynos5250())
exynos5_set_lcd_clk();
- else if (proid_is_exynos5420())
+ else if (proid_is_exynos5420() || proid_is_exynos5800())
exynos5420_set_lcd_clk();
}
}
@@ -1696,7 +1697,7 @@ void set_mipi_clk(void)
int set_spi_clk(int periph_id, unsigned int rate)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420())
+ if (proid_is_exynos5420() || proid_is_exynos5800())
return exynos5420_set_spi_clk(periph_id, rate);
return exynos5_set_spi_clk(periph_id, rate);
} else {
diff --git a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
index b6a9bc1..0aff3d0 100644
--- a/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
+++ b/arch/arm/cpu/armv7/exynos/clock_init_exynos5.c
@@ -971,7 +971,7 @@ static void exynos5420_system_clock_init(void)
void system_clock_init(void)
{
- if (proid_is_exynos5420())
+
[U-Boot] [PATCH v3 0/7] Addition of new board Peach-Pi
Now we are adding a new Peach-Pi board which is a variant of Peach-Pit and is based on Exynos5800. Exynos5800 itself is a variant of Exynos5420, hence, most of the hardware config and settings are reused for this board. Changes since v1: - Rebased all the patches Changes since v2: - Rebased all the patches - Added new patch Enable update mode for DREX controller Akshay Saraswat (5): Exynos5800: Introduce new proid for Exynos5800 Exynos5800: Add DTS for new board Peach-Pi Config: Exynos5800: Enable build for Peach-Pi Config: Exynos5420: Refactor SDRAM Bank and Size Exynos5: ddr3: Choose between single or double channel config Alim Akhtar (1): DMC: Exynos5: Enable update mode for DREX controller Vadim Bendebury (1): Peach-Pi: Use the enhanced usb_copy() prototype arch/arm/cpu/armv7/exynos/Kconfig | 7 +- arch/arm/cpu/armv7/exynos/clock.c | 19 +-- arch/arm/cpu/armv7/exynos/clock_init_exynos5.c | 2 +- arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 29 + arch/arm/cpu/armv7/exynos/pinmux.c | 2 +- arch/arm/cpu/armv7/exynos/spl_boot.c | 10 +- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5800-peach-pi.dts | 157 + arch/arm/include/asm/arch-exynos/cpu.h | 10 +- arch/arm/include/asm/arch-exynos/dmc.h | 1 + arch/arm/include/asm/arch-exynos/gpio.h| 4 +- board/samsung/smdk5420/Kconfig | 16 +++ board/samsung/smdk5420/MAINTAINERS | 2 + configs/peach-pi_defconfig | 5 + include/configs/exynos5420-common.h| 7 +- include/configs/peach-pi.h | 50 include/configs/peach-pit.h| 8 +- include/configs/smdk5420.h | 4 + 18 files changed, 311 insertions(+), 25 deletions(-) create mode 100644 arch/arm/dts/exynos5800-peach-pi.dts create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/7] Config: Exynos5800: Enable build for Peach-Pi
This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list. Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Changes since v2: - Rebased this patch Changes since v1: - Rebased this patch arch/arm/cpu/armv7/exynos/Kconfig | 7 +- board/samsung/smdk5420/Kconfig | 16 + board/samsung/smdk5420/MAINTAINERS | 2 ++ configs/peach-pi_defconfig | 5 include/configs/exynos5420-common.h | 3 ++- include/configs/peach-pi.h | 46 + include/configs/peach-pit.h | 4 ++-- 7 files changed, 79 insertions(+), 4 deletions(-) create mode 100644 configs/peach-pi_defconfig create mode 100644 include/configs/peach-pi.h diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 090be93..13dbd95 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -44,11 +44,16 @@ config TARGET_SMDK5420 select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD -config TARGET_PEACH_PIT +config TARGET_PEACH_PI bool Peach Pi board select SUPPORT_SPL select OF_CONTROL if !SPL_BUILD +config TARGET_PEACH_PIT + bool Peach Pit board + select SUPPORT_SPL + select OF_CONTROL if !SPL_BUILD + endchoice config SYS_SOC diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index d3a5b7f..e7aafe5 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -1,3 +1,19 @@ +if TARGET_PEACH_PI + +config SYS_BOARD + string + default smdk5420 + +config SYS_VENDOR + string + default samsung + +config SYS_CONFIG_NAME + string + default peach-pi + +endif + if TARGET_PEACH_PIT config SYS_BOARD diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index e0f5c7a..1423f83 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -6,3 +6,5 @@ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig F: include/configs/smdk5420.h F: configs/smdk5420_defconfig +F: include/configs/peach-pi.h +F: configs/peach-pi_defconfig diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig new file mode 100644 index 000..8ada0db --- /dev/null +++ b/configs/peach-pi_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y ++S:CONFIG_ARM=y ++S:CONFIG_ARCH_EXYNOS=y ++S:CONFIG_TARGET_PEACH_PI=y +CONFIG_DEFAULT_DEVICE_TREE=exynos5800-peach-pi diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index b0f940c..b6f2b5a 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -10,6 +10,7 @@ #define __CONFIG_EXYNOS5420_H #define CONFIG_EXYNOS5420 +#define CONFIG_EXYNOS5800 /* A variant of Exynos5420 (Exynos5 Family) */ #define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_SPI_FLASH @@ -38,7 +39,7 @@ #define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) -#define CONFIG_DEVICE_TREE_LIST exynos5420-peach-pit exynos5420-smdk5420 +#define CONFIG_DEVICE_TREE_LIST exynos5800-peach-pi exynos5420-peach-pit exynos5420-smdk5420 #define CONFIG_MAX_I2C_NUM 11 diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h new file mode 100644 index 000..d8da7ef --- /dev/null +++ b/include/configs/peach-pi.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. + * + * SPDX-License-Identifier:GPL-2.0+ + */ + +#ifndef __CONFIG_PEACH_PI_H +#define __CONFIG_PEACH_PI_H + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE0x12D3 +#define FLASH_SIZE (0x4 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) + +#include configs/exynos5420-common.h +#include configs/exynos5-dt-common.h + +#define CONFIG_BOARD_COMMON + +/* select serial console configuration */ +#define CONFIG_SERIAL3 /* use SERIAL 3 */ + +#define CONFIG_SYS_PROMPT Peach-Pi # +#define CONFIG_IDENT_STRING for Peach-Pi + +#define CONFIG_VIDEO_PARADE + +/* Display */ +#define CONFIG_LCD +#ifdef CONFIG_LCD +#define CONFIG_EXYNOS_FB +#define CONFIG_EXYNOS_DP +#define LCD_BPPLCD_COLOR16 +#endif + +#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ +#define CONFIG_DM_CROS_EC + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 91bd37d..29a0996 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -23,8 +23,8 @@ /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */
[U-Boot] [PATCH v3 6/7] Exynos5: ddr3: Choose between single or double channel config
Add a 4G configuration and choose it based on the number of banks
declared in config file. A board with 4 SDRAM banks declared (as
per CONFIG_NR_DRAM_BANKS) will end up with the 2G confiuration.
Signed-off-by: Doug Anderson diand...@chromium.org
Signed-off-by: Akshay Saraswat aksha...@samsung.com
---
Changes since v2:
- Rebased this patch
Changes since v1:
- Rebased this patch
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 4d73b45..7c0b12a 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -464,6 +464,16 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
+ if (CONFIG_NR_DRAM_BANKS 4) {
+ /* Need both controllers. */
+ mem-memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
+ mem-chips_per_channel = 2;
+ mem-chips_to_configure = 2;
+ } else {
+ /* 2GB requires a single controller */
+ mem-memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
+ }
+
/* Enable PAUSE for DREX */
setbits_le32(clk-pause, ENABLE_BIT);
--
1.9.1
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Re: [U-Boot] [PATCH] mtd, cfi, ubi: add missing writebufsize initialization
Hello Stefan, Am 31.10.2014 10:44, schrieb Stefan Roese: Hi Heiko, On 31.10.2014 10:39, Heiko Schocher wrote: ff94bc40af3481d47546595ba73c136de6af6929 mtd, ubi, ubifs: resync with Linux-3.14 introduced the writebufsize field in struct mtd_info, which is not initialized in the cfi_flash driver, which leads in not working ubi on cfi flashes. Fix it Signed-off-by: Heiko Schocher h...@denx.de Reported-by: Andrew Ruder andrew.ru...@elecsyscorp.com --- @Andrew: could you test this patch, if it solves your issue? drivers/mtd/cfi_mtd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff..894858e 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd-flags = MTD_CAP_NORFLASH; mtd-size = fi-size; mtd-writesize = 1; + mtd-writebufsize = mtd-writesize; Small nitpicking comment: Could you please align the = to those lines above? Thanks! Hups ... sorry. Other than that: Acked-by: Stefan Roese s...@denx.de Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 7/7] Peach-Pi: Use the enhanced usb_copy() prototype
From: Vadim Bendebury vben...@chromium.org Exynos5800 IROM has a different, from 5250 and 5420, prototype of the usb_copy() function. Luckily the earlier version did not expect any arguments, which means the same code could be used with old and new SoCs, the old ones just ignoring the arguments. Signed-off-by: Vadim Bendebury vben...@chromium.org Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Changes since v2: - Added in this patch-set. arch/arm/cpu/armv7/exynos/spl_boot.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/spl_boot.c b/arch/arm/cpu/armv7/exynos/spl_boot.c index 658e4cb..dbd312c 100644 --- a/arch/arm/cpu/armv7/exynos/spl_boot.c +++ b/arch/arm/cpu/armv7/exynos/spl_boot.c @@ -195,10 +195,16 @@ void copy_uboot_to_ram(void) void (*end_bootop_from_emmc)(void); #endif #ifdef CONFIG_USB_BOOTING - u32 (*usb_copy)(void); int is_cr_z_set; unsigned int sec_boot_check; + /* +* Note that older hardware (before Exynos5800) does not expect any +* arguments, but it does not hurt to pass them, so a common function +* prototype is used. +*/ + u32 (*usb_copy)(u32 num_of_block, u32 *dst); + /* Read iRAM location to check for secondary USB boot mode */ sec_boot_check = readl(EXYNOS_IRAM_SECONDARY_BASE); if (sec_boot_check == EXYNOS_USB_SECONDARY_BOOT) @@ -240,7 +246,7 @@ void copy_uboot_to_ram(void) */ is_cr_z_set = config_branch_prediction(0); usb_copy = get_irom_func(USB_INDEX); - usb_copy(); + usb_copy(0, (u32 *)CONFIG_SYS_TEXT_BASE); config_branch_prediction(is_cr_z_set); break; #endif -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 5/7] Config: Exynos5420: Refactor SDRAM Bank and Size
Since, not every board may have all memory channels configured and all available banks of DMC used, we wish to refactor configs for Memory Bank size and numbers as per board memory config. For Example, Peach-Pit has 2GB memory and will be using only 4 banks but Peach-Pi has 3.5GB memory and will be using all 7 available SDRAM banks. Signed-off-by: Akshay Saraswat aksha...@samsung.com --- Changes since v2: - Rebased this patch Changes since v1: - Rebased this patch include/configs/exynos5420-common.h | 4 include/configs/peach-pi.h | 4 include/configs/peach-pit.h | 4 include/configs/smdk5420.h | 4 4 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h index b6f2b5a..341d980 100644 --- a/include/configs/exynos5420-common.h +++ b/include/configs/exynos5420-common.h @@ -55,10 +55,6 @@ */ #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_IRAM_TOP - 0x800) -/* DRAM Memory Banks */ -#define CONFIG_NR_DRAM_BANKS 7 -#define SDRAM_BANK_SIZE(512UL 20UL) /* 512 MB */ - /* Miscellaneous configurable options */ #define CONFIG_DEFAULT_CONSOLE console=ttySAC1,115200n8\0 diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index d8da7ef..8a82402 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -43,4 +43,8 @@ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE(512UL 20UL) /* 512 MB */ + #endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 29a0996..ad5db57 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -43,4 +43,8 @@ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 4 +#define SDRAM_BANK_SIZE(512UL 20UL) /* 512 MB */ + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index fd2d482..5c9a3c0 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -23,4 +23,8 @@ #define CONFIG_IDENT_STRING for SMDK5420 #define CONFIG_DEFAULT_CONSOLE console=ttySAC1,115200n8\0 +/* DRAM Memory Banks */ +#define CONFIG_NR_DRAM_BANKS 7 +#define SDRAM_BANK_SIZE(512UL 20UL) /* 512 MB */ + #endif /* __CONFIG_SMDK5420_H */ -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] Odroid-XU3: Add support for Odroid-XU3
Hi Hyungwon,
This patch adds support for Odroid-XU3.
Change-Id: Ia45d119a62b126f2328684485b8c372ba6acbe00
As stated previously - please run checkpatch.pl on a patch before
submitting.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/cpu/armv7/exynos/Kconfig | 4 +
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 72 ++
board/samsung/odroid-xu3/Kconfig | 12 ++
board/samsung/odroid-xu3/MAINTAINERS | 6 +
board/samsung/odroid-xu3/Makefile | 7 +
board/samsung/odroid-xu3/odroid-xu3.c | 132 ++
board/samsung/odroid-xu3/setup.h | 123 +
configs/odroid-xu3_defconfig | 4 +
include/configs/odroid_xu3.h | 243
++ 10 files changed, 605
insertions(+), 1 deletion(-) create mode 100644
arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644
board/samsung/odroid-xu3/Kconfig create mode 100644
board/samsung/odroid-xu3/MAINTAINERS create mode 100644
board/samsung/odroid-xu3/Makefile create mode 100644
board/samsung/odroid-xu3/odroid-xu3.c create mode 100644
board/samsung/odroid-xu3/setup.h create mode 100644
configs/odroid-xu3_defconfig create mode 100644
include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig index 3a25fee..a47cb34 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -22,6 +22,9 @@ config TARGET_TRATS2
config TARGET_ODROID
bool Exynos4412 Odroid board
+config TARGET_ODROID_XU3
+ bool Exynos5422 Odroid board
+
config TARGET_ARNDALE
bool Exynos5250 Arndale board
select OF_CONTROL if !SPL_BUILD
@@ -60,6 +63,7 @@ source board/samsung/universal_c210/Kconfig
source board/samsung/origen/Kconfig
source board/samsung/trats2/Kconfig
source board/samsung/odroid/Kconfig
+source board/samsung/odroid-xu3/Kconfig
source board/samsung/arndale/Kconfig
source board/samsung/smdk5250/Kconfig
source board/samsung/smdk5420/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2dcfcc0..66191f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
b/arch/arm/dts/exynos5422-odroidxu3.dts new file mode 100644
index 000..34f52c6
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,72 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos54xx.dtsi
+
+/ {
+ model = Odroid XU3 based on EXYNOS5422;
+ compatible = samsung,odroidxu3, samsung,exynos5;
+
+ config {
+ hwid = smdk5420 TEST A-A 9382;
+ };
+
+ aliases {
+ serial0 = /serial@12C0;
+ console = /serial@12C2;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x4000 0x1000
+ 0x5000 0x1000
+ 0x6000 0x1000
+ 0x7000 0x1000
+ 0x8000 0x1000
+ 0x9000 0x1000
+ 0xa000 0x1000
+ 0xb000 0xea0;
+ };
+
+ serial@12C2 {
+ status=okay;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca {
+ #address-cells = 1;
+ #size-cells = 0;
+ pmic@66 {
+ reg = 0x66;
+ compatible = samsung,s2mps11-pmic;
+ };
+ };
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ samsung,removable = 0;
+ samsung,pre-init;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ samsung,removable = 1;
+ };
+
+ mmc@1223 {
+ status = disabled;
+ };
+};
diff --git a/board/samsung/odroid-xu3/Kconfig
b/board/samsung/odroid-xu3/Kconfig new file mode 100644
index 000..6159692
--- /dev/null
+++ b/board/samsung/odroid-xu3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default odroid-xu3
+
+config SYS_VENDOR
+ default samsung
+
+config SYS_CONFIG_NAME
+ default odroid_xu3
+
+endif
diff
Re: [U-Boot] [PATCH v2 6/6] dm: sunxi: Add support for serial using driver model
On Fri, 2014-10-31 at 10:33 +0100, Hans de Goede wrote: Ah, but I plan to merge the v3 Simon has posted to u-boot-sunxi/next and then do a pull-req with that in there this weekend. IOW we don't need to solve the pinmux problem for that series to get merged (from my pov). So maybe we should just delay dealing with the pinmux issue until we really need to ? Does it work without having done *something* about this? AFAICT it currently relies on the stdout-path in the DT precisely matching CONFIG_CONS_INDEX (due to its affect on the code in gpio_init()), doesn't it? Ian. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] Exynos5422: Add support for Exynos5422
Hi Hyungwon,
Hi,
On Fri, 31 Oct 2014 10:08:34 +0100
Lukasz Majewski l.majew...@samsung.com wrote:
Hi Hyungwon,
This patch adds support for Exynos5422 including GPIO, clock,
pinmux, and cpu id.
Change-Id: Ic609973ab531e2b6ee9a68cfec0b6b9571f203a8
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31
+--
drivers/gpio/s5p_gpio.c | 4 +++- 2 files
changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h index 431ae3a..8f82ef0
100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] =
{ { EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT }, };
+#define EXYNOS5800_GPIO_NUM_PARTS4
+static struct gpio_info
exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE,
EXYNOS5420_GPIO_MAX_PORT_PART_4 }, +};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() ||
proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info
*get_gpio_data(void) static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() ||
proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = { { 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[]
= {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00,
EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00,
EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10,
EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00,
EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00,
EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00,
EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00,
EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40,
EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00,
EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00,
EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0,
0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char
*name) */
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() ||
proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base =
EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
I'm a bit confused here.
We already support exynos5420 in the mainline. It only slightly
differs from Exynos5422. Additionally there is Exynos5800 which is a
different HW revision of Exynos5422.
Yes. You're right. I was not in the subscriber list when I send this
mail. So when I sent this mail, I received an auto-replied mail which
I can cancel this email. I canceled this mail. But the mail sent to
your and Minkyu Kang was not. Sorry for the confusion. Please refer
the latest mail.
Ok.
Probably by a mistake, I've received this series three times :-).
When you prepare v2, please add change log and cover letter.
In the message
Re: [U-Boot] [PATCH v3 3/7] Config: Exynos5800: Enable build for Peach-Pi
Dear Akshay Saraswat, In message 1414745754-4394-4-git-send-email-aksha...@samsung.com you wrote: This adds following things : - New config and defconfig for Peach-Pi board. - Alterations in Kconfig and MAINTAINERS. - Addition of CONFIG_EXYNOS5800. - ADdition of exynos5800-peach-pi in dts list. WARNING: line over 80 characters #223: FILE: include/configs/exynos5420-common.h:13: +#define CONFIG_EXYNOS5800 /* A variant of Exynos5420 (Exynos5 Family) */ WARNING: line over 80 characters #232: FILE: include/configs/exynos5420-common.h:42: +#define CONFIG_DEVICE_TREE_LIST exynos5800-peach-pi exynos5420-peach-pit exynos5420-smdk5420 Please fix! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de It is your destiny. - Darth Vader ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] mtd, ubi: errormessage handling
Hello all, as I just debugged a problem with ubi on cfi flashes [1], the question raised, if it would be a good idea to enable ubi error messages by default? I think, if we enable them by default, the error Andrew had, would be visible immediately: with ubi errormessages [3]: = ubi part misc UBI error: ubi_attach_mtd_dev: More than 64 PEBs are needed for fastmap, sorry. UBI: default fastmap pool size: 8 UBI: default fastmap WL pool size: 25 UBI: attaching mtd1 to ubi0 UBI error: io_init: bad write buffer size 0 for 1 min. I/O unit UBI error: ubi_init: cannot attach mtd1 = without ubi errormessages: = ubi part misc UBI: default fastmap pool size: 8 UBI: default fastmap WL pool size: 25 UBI: attaching mtd1 to ubi0 = The big con is the space needed for it. I tested on the tqm5200s board (current mainline). without pr_err() enabled in include/linux/mtd/mtd.h $ ls -al u-boot.bin -rwxrwxr-x 1 hs hs 469264 31. Okt 10:21 u-boot.bin with pr_err() enabled: $ ls -al u-boot.bin -rwxrwxr-x 1 hs hs 525584 31. Okt 10:23 u-boot.bin - 55k more space needed!! So there are 2 questions: a) Do we want to make pr_err() configurable seperately? (I vote for yes, proposal CONFIG_UBI_PRINT_ERRORS) b) how would/should be the default setting? (I vote for disabled) bye, Heiko [1] ubi regression http://lists.denx.de/pipermail/u-boot/2014-October/193098.html [2] bugfix Patchwork [U-Boot] mtd, cfi, ubi: add missing writebufsize initialization http://patchwork.ozlabs.org/patch/405245/ [3] enabled ubi error messages patch diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 8666413..156016f 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -458,8 +458,8 @@ static inline void mtd_erase_callback(struct erase_info *instr) #endif /* CONFIG_MTD_DEBUG */ #define pr_info(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) #define pr_warn(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) -#define pr_err(args...)MTDDEBUG(MTD_DEBUG_LEVEL0, args) -#define pr_crit(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) +#define pr_err(args...)printk(KERN_INFO args) +#define pr_crit(args...) printk(KERN_INFO args) #define pr_cont(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) #define pr_notice(args...) MTDDEBUG(MTD_DEBUG_LEVEL0, args) #endif -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] mtd, cfi, ubi: add missing writebufsize initialization
ff94bc40af3481d47546595ba73c136de6af6929 mtd, ubi, ubifs: resync with Linux-3.14 introduced the writebufsize field in struct mtd_info, which is not initialized in the cfi_flash driver, which leads in not working ubi on cfi flashes. Fix it Signed-off-by: Heiko Schocher h...@denx.de Reported-by: Andrew Ruder andrew.ru...@elecsyscorp.com Acked-by: Stefan Roese s...@denx.de --- @Andrew: could you test this patch, if it solves your issue? Changes in v2: add comment from Stefan Roese - align the = with the others lines above add Acked-by from Stefan Roese drivers/mtd/cfi_mtd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index ac805ff..709a486 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -226,6 +226,7 @@ int cfi_mtd_init(void) mtd-flags = MTD_CAP_NORFLASH; mtd-size = fi-size; mtd-writesize = 1; + mtd-writebufsize = mtd-writesize; mtd-_erase = cfi_mtd_erase; mtd-_read = cfi_mtd_read; -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Add MAINTAINERS and doc/git-mailrc entry. Signed-off-by: Heiko Schocher h...@denx.de --- as discussed this step here and there first of all with Scott Wood for example here: http://lists.denx.de/pipermail/u-boot/2014-August/186005.html I am now ready for taking over the ownership for MTD ... @Scott: I would be happy, if you can still have a look in nand patches ;-) please inform me, if you have no longer time for it, so we can set u-boot-nand into not maintained state @all: Please send me a list of pending patches, so I can go through them, thanks! MAINTAINERS| 8 doc/git-mailrc | 1 + 2 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd346c9..e81a08a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,14 @@ S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ +MTD +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* +F: include/linux/mtd* +F: include/mtd* + OPENRISC M: Stefan Kristiansson stefan.kristians...@saunalahti.fi S: Maintained diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..166fe37 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -116,6 +116,7 @@ alias fdtuboot, sjg alias i2cuboot, hs alias kconfiguboot, masahiro alias mmcuboot, panto +alias mtduboot, hs alias nand uboot, scottwood alias netuboot, jhersh alias spi uboot, jagan -- 1.8.3.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v3 PATCH 02/12] arm, at91: add spi dataflash support for the taurus board
On 31 October 2014 13:00, Heiko Schocher h...@denx.de wrote:
Signed-off-by: Heiko Schocher h...@denx.de
Reviewed-by: Bo Shen voice.s...@atmel.com
---
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
- add comment from Jagan Teki:
- remove spi_init_f() from board file
- remove CONFIG_SYS_SPI_WRITE_TOUT from board config file
instead define a default in the spi driver - new patch for v2
board/siemens/taurus/taurus.c | 18 ++
include/configs/taurus.h | 10 ++
2 files changed, 28 insertions(+)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 673b302..76609c7 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -22,6 +22,8 @@
#include asm/arch/gpio.h
#include asm/arch/at91sam9_sdramc.h
#include atmel_mci.h
+#include asm/arch/at91_spi.h
+#include spi.h
#include net.h
#include netdev.h
@@ -127,6 +129,21 @@ int board_early_init_f(void)
return 0;
}
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
+}
+
Please add all these stuff in drivers/spi/atmel_spi.c
Did you see any issues?
int board_init(void)
{
/* adress of boot parameters */
@@ -139,6 +156,7 @@ int board_init(void)
#ifdef CONFIG_MACB
taurus_macb_hw_init();
#endif
+ at91_spi0_hw_init(TAURUS_SPI_MASK);
return 0;
}
diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index aadf4cd..ba9496f 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -127,6 +127,16 @@
#define CONFIG_USB_STORAGE
#endif
+/* SPI EEPROM */
+#define CONFIG_SPI
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ATMEL_SPI
+#define CONFIG_SPI_FLASH_STMICRO
+#define TAURUS_SPI_MASK (1 4)
+#define TAURUS_SPI_CS_PIN AT91_PIN_PA3
+
/* load address */
#define CONFIG_SYS_LOAD_ADDR 0x2200
thanks!
--
Jagan.
___
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[U-Boot] [PATCH v2] powerpc/t208xqds: VID support
From: Ying Zhang b40...@freescale.com
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
Signed-off-by: Ying Zhang b40...@freescale.com
---
Change from v1:
- Set the core voltage according to the VID on startup.
board/freescale/common/Makefile | 1 +
board/freescale/common/vid.c| 491
board/freescale/common/vid.h| 20 ++
board/freescale/t208xqds/t208xqds.c | 13 +
include/configs/T208xQDS.h | 17 ++
5 files changed, 542 insertions(+)
create mode 100644 board/freescale/common/vid.c
create mode 100644 board/freescale/common/vid.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 32b5a3b..1556433 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_FMAN_ENET) += fman.o
obj-$(CONFIG_FSL_PIXIS)+= pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
+obj-$(CONFIG_VID) += vid.o
endif
obj-$(CONFIG_FSL_QIXIS)+= qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
new file mode 100644
index 000..6b8af14
--- /dev/null
+++ b/board/freescale/common/vid.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include i2c.h
+#include asm/immap_85xx.h
+#include vid.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int __weak i2c_multiplexer_select_vid_channel(u8 channel)
+{
+ return 0;
+}
+
+/*
+ * Compensate for a board specific voltage drop between regulator and SoC
+ * return a value in mV
+ */
+int __weak board_vdd_drop_compensation(void)
+{
+ return 0;
+}
+
+/*
+ * Get the i2c address configuration for the IR regulator chip
+ *
+ * There are some variance in the RDB HW regarding the I2C address
configuration
+ * for the IR regulator chip, which is likely a problem of external resistor
+ * accuracy. So we just check each address in a hopefully non-intrusive mode
+ * and use the first one that seems to work
+ *
+ * The IR chip can show up under the following addresses:
+ * 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
+ * 0x09 (Verified on T1040RDB-PA)
+ * 0x38 (Verified on T2080QDS, T2081QDS)
+ */
+static int find_ir_chip_on_i2c(void)
+{
+ int i2caddress;
+ int ret;
+ u8 byte;
+ int i;
+ const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
+
+ /* Check all the address */
+ for (i = 0; i (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
+ i2caddress = ir_i2c_addr[i];
+ ret = i2c_read(i2caddress,
+ IR36021_MFR_ID_OFFSET, 1, (void *)byte,
+ sizeof(byte));
+ if ((ret = 0) (byte == IR36021_MFR_ID))
+ return i2caddress;
+ }
+ return -1;
+}
+
+/* Maximum loop count waiting for new voltage to take effect */
+#define MAX_LOOP_WAIT_NEW_VOL 100
+/* Maximum loop count waiting for the voltage to be stable */
+#define MAX_LOOP_WAIT_VOL_STABLE 100
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for WAIT_FOR_ADC before
+ * another reading
+ */
+#define NUM_READINGS4 /* prefer to be power of 2 for efficiency */
+
+/* If an INA220 chip is available, we can use it to read back the voltage
+ * as it may have a higher accuracy than the IR chip for the same purpose
+ */
+#ifdef CONFIG_VOL_MONITOR_INA220
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#else
+#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
+#define ADC_MIN_ACCURACY 4
+#endif
+
+#ifdef CONFIG_VOL_MONITOR_INA220
+static int read_voltage_from_INA220(int i2caddress)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+ u8 buf[2];
+
+ for (i = 0; i NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
+ (void *)buf, 2);
+ if (ret) {
+ printf(VID: failed to read core voltage\n);
+ return ret;
+ }
+ vol_mon = (buf[0] 8) | buf[1];
+ if (vol_mon I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf(VID: Core voltage sensor error\n);
+ return -1;
+ }
+ debug(VID: bus voltage reads 0x%04x\n, vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon
Re: [U-Boot] [v3 PATCH 01/12] spi, atmel: move CONFIG_SYS_SPI_WRITE_TOUT into common header
On 31 October 2014 13:00, Heiko Schocher h...@denx.de wrote: move CONFIG_SYS_SPI_WRITE_TOUT into drivers/spi/atmel_spi.h and define a default value. Delete this define in the board config files, where it is possible (all boards use currently the same value). Signed-off-by: Heiko Schocher h...@denx.de --- Changes in v3: rebased against 571bdf16a78e9e116a93d46f4809c4f8a3f2adb6 Changes in v2: rebased against d58a9451e7339ed4cf2b2627e534611f427fb791 new in v2 drivers/spi/atmel_spi.h | 4 include/configs/afeb9260.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/ethernut5.h | 1 - include/configs/meesc.h | 1 - include/configs/otc570.h| 1 - include/configs/pm9261.h| 1 - include/configs/pm9263.h| 1 - include/configs/sbc35_a9g20.h | 1 - include/configs/tny_a9260.h | 1 - include/configs/usb_a9263.h | 1 - 14 files changed, 4 insertions(+), 13 deletions(-) diff --git a/drivers/spi/atmel_spi.h b/drivers/spi/atmel_spi.h index d240945..1538a23 100644 --- a/drivers/spi/atmel_spi.h +++ b/drivers/spi/atmel_spi.h @@ -94,3 +94,7 @@ static inline struct atmel_spi_slave *to_atmel_spi(struct spi_slave *slave) readl(as-regs + ATMEL_SPI_##reg) #define spi_writel(as, reg, value) \ writel(value, as-regs + ATMEL_SPI_##reg) + +#if !defined(CONFIG_SYS_SPI_WRITE_TOUT) +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#endif diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 14bac15..932a309 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -77,7 +77,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS10xD000 /* CS1 */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index 73917b0..72247cc 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -135,7 +135,6 @@ #ifndef CONFIG_AT91SAM9G20EK_2MMC #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS10xD000 /* CS1 */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 226f8c1..cb16bda 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -107,7 +107,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS30xD000 /* CS3 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index b666d94..fa19e8b 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -119,7 +119,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define AT91_SPI_CLK 1500 diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index b8d5dd1..d5f0197 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -100,7 +100,6 @@ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI #define CONFIG_HAS_DATAFLASH 1 -#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS00xC000 /* CS0 */ #define AT91_SPI_CLK 1500 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 4c69af6..ce61a16 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -78,7 +78,6 @@ /* SPI */ #define CONFIG_ATMEL_SPI -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) #define AT91_SPI_CLK 1500 /* Serial port */ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 86ce5f2..955d0e2 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -124,7 +124,6 @@ #ifdef
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Hi Heiko, On 31 October 2014 15:56, Heiko Schocher h...@denx.de wrote: Add MAINTAINERS and doc/git-mailrc entry. Signed-off-by: Heiko Schocher h...@denx.de --- as discussed this step here and there first of all with Scott Wood for example here: http://lists.denx.de/pipermail/u-boot/2014-August/186005.html I am now ready for taking over the ownership for MTD ... Is it for entire drivers/mtd ? or any specific parts? @Scott: I would be happy, if you can still have a look in nand patches ;-) please inform me, if you have no longer time for it, so we can set u-boot-nand into not maintained state @all: Please send me a list of pending patches, so I can go through them, thanks! MAINTAINERS| 8 doc/git-mailrc | 1 + 2 files changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fd346c9..e81a08a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -258,6 +258,14 @@ S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ +MTD +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* Don't add entire mtd - drivers/mtd/spi is owned by me. and few spi-flash mtd stuff is being under review. +F: include/linux/mtd* +F: include/mtd* + OPENRISC M: Stefan Kristiansson stefan.kristians...@saunalahti.fi S: Maintained diff --git a/doc/git-mailrc b/doc/git-mailrc index ad22763..166fe37 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -116,6 +116,7 @@ alias fdtuboot, sjg alias i2cuboot, hs alias kconfiguboot, masahiro alias mmcuboot, panto +alias mtduboot, hs alias nand uboot, scottwood alias netuboot, jhersh alias spi uboot, jagan -- 1.8.3.1 thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] imx:mx6sxsabresd fix pfuz probe failed
On Fri, Oct 31, 2014 at 1:08 AM, Peng Fan peng@freescale.com wrote: The PFUZ probe failed with the following msg: wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=0 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=1 wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0x8 retry=2 i2c_init_transfer: give up i2c_regs=021a Can't find PMIC:PFUZE100 board_early_init_f is too early to call i2c related setting, because init_func_i2c is called after board_early_init_f being invoked. Thus move setup_i2c into board_init. Also PFUZ is connected to I2C bus 0, so change 1 - 0. Using this patch PFUZ can be correctly probed: PMIC: PFUZE100 ID=0x11 Signed-off-by: Peng Fan peng@freescale.com Maybe this is a difference between RevA versus RevB board? I have a RevA and PMIC works fine here: U-Boot 2014.10-rc2-17115-g718b923 (Sep 30 2014 - 14:03:24) CPU: Freescale i.MX6SX rev1.0 at 792 MHz Reset cause: WDOG Board: MX6SX SABRE SDB I2C: ready DRAM: 1 GiB MMC: FSL_SDHC: 0 In:serial Out: serial Err: serial PMIC: PFUZE100 ID=0x10 Net: FEC [PRIME] Hit any key to stop autoboot: 0 = = pmic PFUZE100 dump PMIC: PFUZE100 0x00: 0010 0021 0001 003f 0001 0x08: 007f 0081 0x10: 003f 0x18: 0010 0x20: 002b 001b 002b 0008 0044 0x28: 002b 001b 0x30: 002b 0008 0044 0072 0072 0072 0x38: 0008 0054 0026 0026 0026 0008 0x40: 0064 0026 0026 0026 0008 0064 0x48: 0038 0038 0038 0008 0074 0x50: 0x58: 0x60: 0x68: 0010 0006 0018 000e 001a 0010 0x70: 001f 001c 0x78: = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] Adds support for Exynos5422 odroid xu3 board
This patchset adds support for Exynos5422 odroid xu3 board. I have done this work on the patchset submitted by Akshay Saraswat. https://patchwork.ozlabs.org/patch/400043/ Hyungwon Hwang (4): exynos5: fix GPIO information of exynos5420 Exynos5800: Add support for Exynos5800 odroid: make some macros common Odroid-XU3: Add support for Odroid-XU3 arch/arm/cpu/armv7/exynos/Kconfig | 4 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 72 + arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 261 +--- board/samsung/odroid-xu3/Kconfig| 12 ++ board/samsung/odroid-xu3/MAINTAINERS| 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 132 board/samsung/odroid-xu3/setup.h| 115 ++ board/samsung/odroid/odroid.c | 1 + board/samsung/odroid/setup.h| 8 - configs/odroid-xu3_defconfig| 4 + drivers/gpio/s5p_gpio.c | 4 +- include/configs/odroid_xu3.h| 73 + 15 files changed, 576 insertions(+), 137 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] odroid: make some macros common
Some macros are used commonly for odroid series boards. This patch makes a common header file to congregate that kinds of macros. Even though there are more macros which can be common, they are not become common. Because they are a part of a register, the readability is better when they are defined at a place. Signed-off-by: Hyungwon Hwang human.hw...@samsung.com --- board/samsung/odroid/odroid.c | 1 + board/samsung/odroid/setup.h | 8 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -18,6 +18,7 @@ #include usb.h #include usb/s3c_udc.h #include samsung/misc.h +#include ../setup.h #include setup.h DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 --- a/board/samsung/odroid/setup.h +++ b/board/samsung/odroid/setup.h @@ -8,14 +8,6 @@ #ifndef __ODROIDU3_SETUP__ #define __ODROIDU3_SETUP__ -/* A/M PLL_CON0 */ -#define SDIV(x) ((x) 0x7) -#define PDIV(x) (((x) 0x3f) 8) -#define MDIV(x) (((x) 0x3ff) 16) -#define FSEL(x) (((x) 0x1) 27) -#define PLL_LOCKED_BIT (0x1 29) -#define PLL_ENABLE(x) (((x) 0x1) 31) - /* CLK_SRC_CPU */ #define MUX_APLL_SEL(x) ((x) 0x1) #define MUX_CORE_SEL(x) (((x) 0x1) 16) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] exynos5: fix GPIO information of exynos5420
This patch fixes wrong GPIO information such as GPIO bank, table which is used
to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232 +++-
2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 7c5c4ff..da4ac6b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -139,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE0x0381
-#define EXYNOS5420_GPIO_PART6_BASE 0x0386
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
#define EXYNOS5420_PRO_ID 0x1000
#define EXYNOS5420_CLOCK_BASE 0x1001
#define EXYNOS5420_POWER_BASE 0x1004
@@ -161,11 +161,10 @@
#define EXYNOS5420_I2S_BASE0x12D6
#define EXYNOS5420_PWMTIMER_BASE 0x12DD
#define EXYNOS5420_SPI_ISP_BASE0x131A
-#define EXYNOS5420_GPIO_PART2_BASE 0x1340
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x1341
-#define EXYNOS5420_GPIO_PART5_BASE 0x1400
-#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_GPIO_PART1_BASE 0x1340
+#define EXYNOS5420_GPIO_PART2_BASE 0x1341
+#define EXYNOS5420_GPIO_PART3_BASE 0x1400
+#define EXYNOS5420_GPIO_PART4_BASE 0x1401
#define EXYNOS5420_MIPI_DSIM_BASE 0x1450
#define EXYNOS5420_DP_BASE 0x145B
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 32e045a..431ae3a 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1028,83 +1028,7 @@ enum exynos5_gpio_pin {
};
enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00,/* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10,/* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20,/* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00,/* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10,/* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20,/* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30,/* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40,/* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00,/* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y70,
EXYNOS5420_GPIO_Y71,
EXYNOS5420_GPIO_Y72,
EXYNOS5420_GPIO_Y73,
@@ -1112,10 +1036,7 @@ enum exynos5420_gpio_pin {
EXYNOS5420_GPIO_Y75,
EXYNOS5420_GPIO_Y76,
EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
- EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+ EXYNOS5420_GPIO_X00,
EXYNOS5420_GPIO_X01,
EXYNOS5420_GPIO_X02,
EXYNOS5420_GPIO_X03,
[U-Boot] [PATCH 2/4] Exynos5800: Add support for Exynos5800
The gpios of Exynos5800 are different from that of Exynos5420. This patch adds
the gpio information and table of Exynos5800.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31 +--
drivers/gpio/s5p_gpio.c | 4 +++-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 431ae3a..8f82ef0 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT },
};
+#define EXYNOS5800_GPIO_NUM_PARTS 4
+static struct gpio_info exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
{ 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[] = {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char *name)
*/
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
--
1.8.3.2
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[U-Boot] [PATCH 4/4] Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/cpu/armv7/exynos/Kconfig | 4 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++
board/samsung/odroid-xu3/Kconfig | 12
board/samsung/odroid-xu3/MAINTAINERS | 6 ++
board/samsung/odroid-xu3/Makefile | 7 ++
board/samsung/odroid-xu3/odroid-xu3.c | 132 ++
board/samsung/odroid-xu3/setup.h | 115 +
configs/odroid-xu3_defconfig | 4 ++
include/configs/odroid_xu3.h | 73 +++
10 files changed, 427 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
create mode 100644 board/samsung/odroid-xu3/Kconfig
create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
create mode 100644 board/samsung/odroid-xu3/Makefile
create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
create mode 100644 board/samsung/odroid-xu3/setup.h
create mode 100644 configs/odroid-xu3_defconfig
create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig
index 3a25fee..a47cb34 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -22,6 +22,9 @@ config TARGET_TRATS2
config TARGET_ODROID
bool Exynos4412 Odroid board
+config TARGET_ODROID_XU3
+ bool Exynos5422 Odroid board
+
config TARGET_ARNDALE
bool Exynos5250 Arndale board
select OF_CONTROL if !SPL_BUILD
@@ -60,6 +63,7 @@ source board/samsung/universal_c210/Kconfig
source board/samsung/origen/Kconfig
source board/samsung/trats2/Kconfig
source board/samsung/odroid/Kconfig
+source board/samsung/odroid-xu3/Kconfig
source board/samsung/arndale/Kconfig
source board/samsung/smdk5250/Kconfig
source board/samsung/smdk5420/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2dcfcc0..66191f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
b/arch/arm/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 000..34f52c6
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,72 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos54xx.dtsi
+
+/ {
+ model = Odroid XU3 based on EXYNOS5422;
+ compatible = samsung,odroidxu3, samsung,exynos5;
+
+ config {
+ hwid = smdk5420 TEST A-A 9382;
+ };
+
+ aliases {
+ serial0 = /serial@12C0;
+ console = /serial@12C2;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x4000 0x1000
+ 0x5000 0x1000
+ 0x6000 0x1000
+ 0x7000 0x1000
+ 0x8000 0x1000
+ 0x9000 0x1000
+ 0xa000 0x1000
+ 0xb000 0xea0;
+ };
+
+ serial@12C2 {
+ status=okay;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca {
+ #address-cells = 1;
+ #size-cells = 0;
+ pmic@66 {
+ reg = 0x66;
+ compatible = samsung,s2mps11-pmic;
+ };
+ };
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ samsung,removable = 0;
+ samsung,pre-init;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ samsung,removable = 1;
+ };
+
+ mmc@1223 {
+ status = disabled;
+ };
+};
diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig
new file mode 100644
index 000..6159692
--- /dev/null
+++ b/board/samsung/odroid-xu3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default odroid-xu3
+
+config SYS_VENDOR
+ default samsung
+
+config SYS_CONFIG_NAME
+ default odroid_xu3
+
+endif
diff --git a/board/samsung/odroid-xu3/MAINTAINERS
b/board/samsung/odroid-xu3/MAINTAINERS
new file mode 100644
index 000..50cf928
---
[U-Boot] [PATCH v2 0/4] Adds support for Exynos5422 odroid xu3 board
This patchset adds support for Exynos5422 odroid xu3 board. I have done this work on the patchset submitted by Akshay Saraswat. https://patchwork.ozlabs.org/patch/400043/ Hyungwon Hwang (4): exynos5: fix GPIO information of exynos5420 Exynos5800: Add support for Exynos5800 odroid: make some macros common Odroid-XU3: Add support for Odroid-XU3 arch/arm/cpu/armv7/exynos/Kconfig | 4 + arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos5422-odroidxu3.dts | 72 + arch/arm/include/asm/arch-exynos/cpu.h | 11 +- arch/arm/include/asm/arch-exynos/gpio.h | 261 +--- board/samsung/odroid-xu3/Kconfig| 12 ++ board/samsung/odroid-xu3/MAINTAINERS| 6 + board/samsung/odroid-xu3/Makefile | 7 + board/samsung/odroid-xu3/odroid-xu3.c | 132 board/samsung/odroid-xu3/setup.h| 115 ++ board/samsung/odroid/odroid.c | 1 + board/samsung/odroid/setup.h| 8 - configs/odroid-xu3_defconfig| 4 + drivers/gpio/s5p_gpio.c | 4 +- include/configs/odroid_xu3.h| 73 + 15 files changed, 576 insertions(+), 137 deletions(-) create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts create mode 100644 board/samsung/odroid-xu3/Kconfig create mode 100644 board/samsung/odroid-xu3/MAINTAINERS create mode 100644 board/samsung/odroid-xu3/Makefile create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c create mode 100644 board/samsung/odroid-xu3/setup.h create mode 100644 configs/odroid-xu3_defconfig create mode 100644 include/configs/odroid_xu3.h -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] Exynos5800: Add support for Exynos5800
The gpios of Exynos5800 are different from that of Exynos5420. This patch adds
the gpio information and table of Exynos5800.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/gpio.h | 31 +--
drivers/gpio/s5p_gpio.c | 4 +++-
2 files changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 431ae3a..8f82ef0 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1368,11 +1368,21 @@ static struct gpio_info
exynos5420_gpio_data[EXYNOS5420_GPIO_NUM_PARTS] = {
{ EXYNOS5420_GPIO_PART5_BASE, EXYNOS5420_GPIO_MAX_PORT },
};
+#define EXYNOS5800_GPIO_NUM_PARTS 4
+static struct gpio_info exynos5800_gpio_data[EXYNOS5800_GPIO_NUM_PARTS] = {
+ { EXYNOS5420_GPIO_PART1_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS5420_GPIO_PART2_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS5420_GPIO_PART3_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS5420_GPIO_PART4_BASE, EXYNOS5420_GPIO_MAX_PORT_PART_4 },
+};
+
static inline struct gpio_info *get_gpio_data(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return exynos5420_gpio_data;
+ else if (proid_is_exynos5800())
+ return exynos5800_gpio_data;
else
return exynos5_gpio_data;
} else if (cpu_is_exynos4()) {
@@ -1388,8 +1398,10 @@ static inline struct gpio_info *get_gpio_data(void)
static inline unsigned int get_bank_num(void)
{
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800())
+ if (proid_is_exynos5420())
return EXYNOS5420_GPIO_NUM_PARTS;
+ if (proid_is_exynos5800())
+ return EXYNOS5800_GPIO_NUM_PARTS;
else
return EXYNOS5_GPIO_NUM_PARTS;
} else if (cpu_is_exynos4()) {
@@ -1493,6 +1505,21 @@ static const struct gpio_name_num_table
exynos5420_gpio_table[] = {
{ 0 }
};
+static const struct gpio_name_num_table exynos5800_gpio_table[] = {
+ GPIO_ENTRY('x', EXYNOS5420_GPIO_X00, EXYNOS5420_GPIO_C00, 0),
+ GPIO_ENTRY('c', EXYNOS5420_GPIO_C00, EXYNOS5420_GPIO_D10, 0),
+ GPIO_ENTRY('d', EXYNOS5420_GPIO_D10, EXYNOS5420_GPIO_Y00, 0),
+ GPIO_ENTRY('y', EXYNOS5420_GPIO_Y00, EXYNOS5420_GPIO_E00, 0),
+ GPIO_ENTRY('e', EXYNOS5420_GPIO_E00, EXYNOS5420_GPIO_F00, 0),
+ GPIO_ENTRY('f', EXYNOS5420_GPIO_F00, EXYNOS5420_GPIO_G00, 0),
+ GPIO_ENTRY('g', EXYNOS5420_GPIO_G00, EXYNOS5420_GPIO_J40, 0),
+ GPIO_ENTRY('j', EXYNOS5420_GPIO_J40, EXYNOS5420_GPIO_A00, 0),
+ GPIO_ENTRY('a', EXYNOS5420_GPIO_A00, EXYNOS5420_GPIO_B00, 0),
+ GPIO_ENTRY('b', EXYNOS5420_GPIO_B00, EXYNOS5420_GPIO_H00, 0),
+ GPIO_ENTRY('h', EXYNOS5420_GPIO_H00, EXYNOS5420_GPIO_Z0, 0),
+ { 0 }
+};
+
void gpio_cfg_pin(int gpio, int cfg);
void gpio_set_pull(int gpio, int mode);
void gpio_set_drv(int gpio, int mode);
diff --git a/drivers/gpio/s5p_gpio.c b/drivers/gpio/s5p_gpio.c
index bcf44eb..bed7cd7 100644
--- a/drivers/gpio/s5p_gpio.c
+++ b/drivers/gpio/s5p_gpio.c
@@ -57,11 +57,13 @@ static inline int s5p_name_to_gpio(const char *name)
*/
#if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
if (cpu_is_exynos5()) {
- if (proid_is_exynos5420() || proid_is_exynos5800()) {
+ if (proid_is_exynos5420()) {
tabp = exynos5420_gpio_table;
irregular_bank_name = 'y';
irregular_set_number = '7';
irregular_bank_base = EXYNOS5420_GPIO_Y70;
+ } else if (proid_is_exynos5800()) {
+ tabp = exynos5800_gpio_table;
} else {
tabp = exynos5_gpio_table;
irregular_bank_name = 'c';
--
1.8.3.2
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[U-Boot] [PATCH v2 1/4] exynos5: fix GPIO information of exynos5420
This patch fixes wrong GPIO information such as GPIO bank, table which is used
to convert GPIO name to index, bank base address, and etc.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/include/asm/arch-exynos/cpu.h | 11 +-
arch/arm/include/asm/arch-exynos/gpio.h | 232 +++-
2 files changed, 117 insertions(+), 126 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index 7c5c4ff..da4ac6b 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -139,7 +139,7 @@
/* EXYNOS5420 */
#define EXYNOS5420_AUDIOSS_BASE0x0381
-#define EXYNOS5420_GPIO_PART6_BASE 0x0386
+#define EXYNOS5420_GPIO_PART5_BASE 0x0386
#define EXYNOS5420_PRO_ID 0x1000
#define EXYNOS5420_CLOCK_BASE 0x1001
#define EXYNOS5420_POWER_BASE 0x1004
@@ -161,11 +161,10 @@
#define EXYNOS5420_I2S_BASE0x12D6
#define EXYNOS5420_PWMTIMER_BASE 0x12DD
#define EXYNOS5420_SPI_ISP_BASE0x131A
-#define EXYNOS5420_GPIO_PART2_BASE 0x1340
-#define EXYNOS5420_GPIO_PART3_BASE 0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE 0x1341
-#define EXYNOS5420_GPIO_PART5_BASE 0x1400
-#define EXYNOS5420_GPIO_PART1_BASE 0x1401
+#define EXYNOS5420_GPIO_PART1_BASE 0x1340
+#define EXYNOS5420_GPIO_PART2_BASE 0x1341
+#define EXYNOS5420_GPIO_PART3_BASE 0x1400
+#define EXYNOS5420_GPIO_PART4_BASE 0x1401
#define EXYNOS5420_MIPI_DSIM_BASE 0x1450
#define EXYNOS5420_DP_BASE 0x145B
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 32e045a..431ae3a 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -1028,83 +1028,7 @@ enum exynos5_gpio_pin {
};
enum exynos5420_gpio_pin {
- /* GPIO_PART1_STARTS */
- EXYNOS5420_GPIO_A00,/* 0 */
- EXYNOS5420_GPIO_A01,
- EXYNOS5420_GPIO_A02,
- EXYNOS5420_GPIO_A03,
- EXYNOS5420_GPIO_A04,
- EXYNOS5420_GPIO_A05,
- EXYNOS5420_GPIO_A06,
- EXYNOS5420_GPIO_A07,
- EXYNOS5420_GPIO_A10,/* 8 */
- EXYNOS5420_GPIO_A11,
- EXYNOS5420_GPIO_A12,
- EXYNOS5420_GPIO_A13,
- EXYNOS5420_GPIO_A14,
- EXYNOS5420_GPIO_A15,
- EXYNOS5420_GPIO_A16,
- EXYNOS5420_GPIO_A17,
- EXYNOS5420_GPIO_A20,/* 16 0x10 */
- EXYNOS5420_GPIO_A21,
- EXYNOS5420_GPIO_A22,
- EXYNOS5420_GPIO_A23,
- EXYNOS5420_GPIO_A24,
- EXYNOS5420_GPIO_A25,
- EXYNOS5420_GPIO_A26,
- EXYNOS5420_GPIO_A27,
- EXYNOS5420_GPIO_B00,/* 24 0x18 */
- EXYNOS5420_GPIO_B01,
- EXYNOS5420_GPIO_B02,
- EXYNOS5420_GPIO_B03,
- EXYNOS5420_GPIO_B04,
- EXYNOS5420_GPIO_B05,
- EXYNOS5420_GPIO_B06,
- EXYNOS5420_GPIO_B07,
- EXYNOS5420_GPIO_B10,/* 32 0x20 */
- EXYNOS5420_GPIO_B11,
- EXYNOS5420_GPIO_B12,
- EXYNOS5420_GPIO_B13,
- EXYNOS5420_GPIO_B14,
- EXYNOS5420_GPIO_B15,
- EXYNOS5420_GPIO_B16,
- EXYNOS5420_GPIO_B17,
- EXYNOS5420_GPIO_B20,/* 40 0x28 */
- EXYNOS5420_GPIO_B21,
- EXYNOS5420_GPIO_B22,
- EXYNOS5420_GPIO_B23,
- EXYNOS5420_GPIO_B24,
- EXYNOS5420_GPIO_B25,
- EXYNOS5420_GPIO_B26,
- EXYNOS5420_GPIO_B27,
- EXYNOS5420_GPIO_B30,/* 48 0x30 */
- EXYNOS5420_GPIO_B31,
- EXYNOS5420_GPIO_B32,
- EXYNOS5420_GPIO_B33,
- EXYNOS5420_GPIO_B34,
- EXYNOS5420_GPIO_B35,
- EXYNOS5420_GPIO_B36,
- EXYNOS5420_GPIO_B37,
- EXYNOS5420_GPIO_B40,/* 56 0x38 */
- EXYNOS5420_GPIO_B41,
- EXYNOS5420_GPIO_B42,
- EXYNOS5420_GPIO_B43,
- EXYNOS5420_GPIO_B44,
- EXYNOS5420_GPIO_B45,
- EXYNOS5420_GPIO_B46,
- EXYNOS5420_GPIO_B47,
- EXYNOS5420_GPIO_H00,/* 64 0x40 */
- EXYNOS5420_GPIO_H01,
- EXYNOS5420_GPIO_H02,
- EXYNOS5420_GPIO_H03,
- EXYNOS5420_GPIO_H04,
- EXYNOS5420_GPIO_H05,
- EXYNOS5420_GPIO_H06,
- EXYNOS5420_GPIO_H07,
-
- /* GPIO PART 2 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_1,/* 72 0x48 */
- EXYNOS5420_GPIO_Y70 = EXYNOS5420_GPIO_MAX_PORT_PART_1,
+ EXYNOS5420_GPIO_Y70,
EXYNOS5420_GPIO_Y71,
EXYNOS5420_GPIO_Y72,
EXYNOS5420_GPIO_Y73,
@@ -1112,10 +1036,7 @@ enum exynos5420_gpio_pin {
EXYNOS5420_GPIO_Y75,
EXYNOS5420_GPIO_Y76,
EXYNOS5420_GPIO_Y77,
-
- /* GPIO PART 3 STARTS*/
- EXYNOS5420_GPIO_MAX_PORT_PART_2,/* 80 0x50 */
- EXYNOS5420_GPIO_X00 = EXYNOS5420_GPIO_MAX_PORT_PART_2,
+ EXYNOS5420_GPIO_X00,
EXYNOS5420_GPIO_X01,
EXYNOS5420_GPIO_X02,
EXYNOS5420_GPIO_X03,
[U-Boot] [PATCH v2 4/4] Odroid-XU3: Add support for Odroid-XU3
This patch adds support for Odroid-XU3.
Signed-off-by: Hyungwon Hwang human.hw...@samsung.com
---
arch/arm/cpu/armv7/exynos/Kconfig | 4 ++
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/exynos5422-odroidxu3.dts | 72 +++
board/samsung/odroid-xu3/Kconfig | 12
board/samsung/odroid-xu3/MAINTAINERS | 6 ++
board/samsung/odroid-xu3/Makefile | 7 ++
board/samsung/odroid-xu3/odroid-xu3.c | 132 ++
board/samsung/odroid-xu3/setup.h | 115 +
configs/odroid-xu3_defconfig | 4 ++
include/configs/odroid_xu3.h | 73 +++
10 files changed, 427 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/exynos5422-odroidxu3.dts
create mode 100644 board/samsung/odroid-xu3/Kconfig
create mode 100644 board/samsung/odroid-xu3/MAINTAINERS
create mode 100644 board/samsung/odroid-xu3/Makefile
create mode 100644 board/samsung/odroid-xu3/odroid-xu3.c
create mode 100644 board/samsung/odroid-xu3/setup.h
create mode 100644 configs/odroid-xu3_defconfig
create mode 100644 include/configs/odroid_xu3.h
diff --git a/arch/arm/cpu/armv7/exynos/Kconfig
b/arch/arm/cpu/armv7/exynos/Kconfig
index 3a25fee..a47cb34 100644
--- a/arch/arm/cpu/armv7/exynos/Kconfig
+++ b/arch/arm/cpu/armv7/exynos/Kconfig
@@ -22,6 +22,9 @@ config TARGET_TRATS2
config TARGET_ODROID
bool Exynos4412 Odroid board
+config TARGET_ODROID_XU3
+ bool Exynos5422 Odroid board
+
config TARGET_ARNDALE
bool Exynos5250 Arndale board
select OF_CONTROL if !SPL_BUILD
@@ -60,6 +63,7 @@ source board/samsung/universal_c210/Kconfig
source board/samsung/origen/Kconfig
source board/samsung/trats2/Kconfig
source board/samsung/odroid/Kconfig
+source board/samsung/odroid-xu3/Kconfig
source board/samsung/arndale/Kconfig
source board/samsung/smdk5250/Kconfig
source board/samsung/smdk5420/Kconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2dcfcc0..66191f9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -12,7 +12,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5420-smdk5420.dtb \
exynos5420-peach-pit.dtb \
- exynos5800-peach-pi.dtb
+ exynos5800-peach-pi.dtb \
+ exynos5422-odroidxu3.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
b/arch/arm/dts/exynos5422-odroidxu3.dts
new file mode 100644
index 000..34f52c6
--- /dev/null
+++ b/arch/arm/dts/exynos5422-odroidxu3.dts
@@ -0,0 +1,72 @@
+/*
+ * Odroid XU3 device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/dts-v1/;
+/include/ exynos54xx.dtsi
+
+/ {
+ model = Odroid XU3 based on EXYNOS5422;
+ compatible = samsung,odroidxu3, samsung,exynos5;
+
+ config {
+ hwid = smdk5420 TEST A-A 9382;
+ };
+
+ aliases {
+ serial0 = /serial@12C0;
+ console = /serial@12C2;
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x4000 0x1000
+ 0x5000 0x1000
+ 0x6000 0x1000
+ 0x7000 0x1000
+ 0x8000 0x1000
+ 0x9000 0x1000
+ 0xa000 0x1000
+ 0xb000 0xea0;
+ };
+
+ serial@12C2 {
+ status=okay;
+ };
+
+ /* s2mps11 is on i2c bus 4 */
+ i2c@12ca {
+ #address-cells = 1;
+ #size-cells = 0;
+ pmic@66 {
+ reg = 0x66;
+ compatible = samsung,s2mps11-pmic;
+ };
+ };
+
+ mmc@1220 {
+ samsung,bus-width = 8;
+ samsung,timing = 1 3 3;
+ samsung,removable = 0;
+ samsung,pre-init;
+ };
+
+ mmc@1221 {
+ status = disabled;
+ };
+
+ mmc@1222 {
+ samsung,bus-width = 4;
+ samsung,timing = 1 2 3;
+ samsung,removable = 1;
+ };
+
+ mmc@1223 {
+ status = disabled;
+ };
+};
diff --git a/board/samsung/odroid-xu3/Kconfig b/board/samsung/odroid-xu3/Kconfig
new file mode 100644
index 000..6159692
--- /dev/null
+++ b/board/samsung/odroid-xu3/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_ODROID_XU3
+
+config SYS_BOARD
+ default odroid-xu3
+
+config SYS_VENDOR
+ default samsung
+
+config SYS_CONFIG_NAME
+ default odroid_xu3
+
+endif
diff --git a/board/samsung/odroid-xu3/MAINTAINERS
b/board/samsung/odroid-xu3/MAINTAINERS
new file mode 100644
index 000..50cf928
---
[U-Boot] [PATCH v2 3/4] odroid: make some macros common
Some macros are used commonly for odroid series boards. This patch makes a common header file to congregate that kinds of macros. Even though there are more macros which can be common, they are not become common. Because they are a part of a register, the readability is better when they are defined at a place. Signed-off-by: Hyungwon Hwang human.hw...@samsung.com --- board/samsung/odroid/odroid.c | 1 + board/samsung/odroid/setup.h | 8 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..ccbb3a0 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -18,6 +18,7 @@ #include usb.h #include usb/s3c_udc.h #include samsung/misc.h +#include ../setup.h #include setup.h DECLARE_GLOBAL_DATA_PTR; diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h index 3e48dad..35f7af5 100644 --- a/board/samsung/odroid/setup.h +++ b/board/samsung/odroid/setup.h @@ -8,14 +8,6 @@ #ifndef __ODROIDU3_SETUP__ #define __ODROIDU3_SETUP__ -/* A/M PLL_CON0 */ -#define SDIV(x) ((x) 0x7) -#define PDIV(x) (((x) 0x3f) 8) -#define MDIV(x) (((x) 0x3ff) 16) -#define FSEL(x) (((x) 0x1) 27) -#define PLL_LOCKED_BIT (0x1 29) -#define PLL_ENABLE(x) (((x) 0x1) 31) - /* CLK_SRC_CPU */ #define MUX_APLL_SEL(x) ((x) 0x1) #define MUX_CORE_SEL(x) (((x) 0x1) 16) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v3 PATCH 02/12] arm, at91: add spi dataflash support for the taurus board
Hello Jagan,
Am 31.10.2014 11:48, schrieb Jagan Teki:
On 31 October 2014 13:00, Heiko Schocherh...@denx.de wrote:
Signed-off-by: Heiko Schocherh...@denx.de
Reviewed-by: Bo Shenvoice.s...@atmel.com
---
Changes in v3:
add Reviewed-by from Bo Shen
Changes in v2:
- add comment from Jagan Teki:
- remove spi_init_f() from board file
- remove CONFIG_SYS_SPI_WRITE_TOUT from board config file
instead define a default in the spi driver - new patch for v2
board/siemens/taurus/taurus.c | 18 ++
include/configs/taurus.h | 10 ++
2 files changed, 28 insertions(+)
diff --git a/board/siemens/taurus/taurus.c b/board/siemens/taurus/taurus.c
index 673b302..76609c7 100644
--- a/board/siemens/taurus/taurus.c
+++ b/board/siemens/taurus/taurus.c
@@ -22,6 +22,8 @@
#includeasm/arch/gpio.h
#includeasm/arch/at91sam9_sdramc.h
#includeatmel_mci.h
+#includeasm/arch/at91_spi.h
+#includespi.h
#includenet.h
#includenetdev.h
@@ -127,6 +129,21 @@ int board_early_init_f(void)
return 0;
}
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_gpio_value(TAURUS_SPI_CS_PIN, 1);
+}
+
Please add all these stuff in drivers/spi/atmel_spi.c
Did you see any issues?
Hmm.. this is board specific ... or?
bye,
Heiko
--
DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[U-Boot] [PATCH] MAINTAINERS: CFI flash maintainership only includes the CFI related files
All the other files in drivers/mtd/* are not really CFI related. So lets only include the files that are CFI specific. Signed-off-by: Stefan Roese s...@denx.de Cc: Heiko Schocher h...@denx.de Cc: Scott Wood scottw...@freescale.com Cc: Masahiro Yamada yamad...@jp.panasonic.com Cc: Jagan Teki jagannadh.t...@gmail.com --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index fd346c9..15b4e91 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -192,7 +192,8 @@ CFI FLASH M: Stefan Roese s...@denx.de S: Maintained T: git git://git.denx.de/u-boot-cfi-flash.git -F: drivers/mtd/* +F: drivers/mtd/cfi_flash.c +F: drivers/mtd/jedec_flash.c COLDFIRE M: Jason Jin jason@freescale.com -- 2.1.3 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Hello Masahiro Yamada, Am 31.10.2014 13:29, schrieb Masahiro Yamada: Hi Heiko, Wolfgang, On Fri, 31 Oct 2014 12:44:07 +0100 Wolfgang Denkw...@denx.de wrote: Dear Jagan, In messageCAD6G_RRkDhNHC=+OtgtXPd7WdfJzq2bokbMKhKnL=blsx-a...@mail.gmail.com you wrote: I am now ready for taking over the ownership for MTD ... Is it for entire drivers/mtd ? or any specific parts? This is meant for all parts of drivers/mtd that are not already covered by other custodians. +M: Heiko Schocherh...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* I am afraid this does not work at all. Do you mean this? F:drivers/mtd/ Yes, I think this is correct. I will change it to: F: drivers/mtd/ F: include/linux/mtd/ F: include/mtd/ Don't add entire mtd - drivers/mtd/spi is owned by me. I don't know if we have a better notation for all the rest that is not already covered by somebody else? Let's see the last part of the MAINTAINERS: THE REST M: Tom Rinitr...@ti.com L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained T: git git://git.denx.de/u-boot.git F: * F: */ This entry does __not__ mean everything is maintained by Tom, but Tom owns all the rest that is not covered by somebody else. MTD M: Heiko Schocherh...@denx.de S: Maintained T: git git://git.denx.de/u-boot-mtd.git F: drivers/mtd/ I think this makes sense. Yep. Let's study from linux/MAINTAINERS! MEMORY TECHNOLOGY DEVICES (MTD) M: David Woodhousedw...@infradead.org M: Brian Norriscomputersforpe...@gmail.com L: linux-...@lists.infradead.org W: http://www.linux-mtd.infradead.org/ Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ T: git git://git.infradead.org/linux-mtd.git T: git git://git.infradead.org/l2-mtd.git S: Maintained F: drivers/mtd/ F: include/linux/mtd/ F: include/uapi/mtd/ Ok, adapted. [snip] ONENAND FLASH DRIVER M: Kyungmin Parkkyungmin.p...@samsung.com L: linux-...@lists.infradead.org S: Maintained F: drivers/mtd/onenand/ F: include/linux/mtd/onenand*.h BTW, CFI FLASH entry is questionable. CFI FLASH M: Stefan Roeses...@denx.de S: Maintained T: git git://git.denx.de/u-boot-cfi-flash.git F: drivers/mtd/* Do all the files in drivers/mtd belong to CFI FLASH subsystem? I think no ... Stefan, can you send an update for this? Thanks! bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Dear Jagan, In message CAD6G_RRkDhNHC=+OtgtXPd7WdfJzq2bokbMKhKnL=blsx-a...@mail.gmail.com you wrote: I am now ready for taking over the ownership for MTD ... Is it for entire drivers/mtd ? or any specific parts? This is meant for all parts of drivers/mtd that are not already covered by other custodians. +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* Don't add entire mtd - drivers/mtd/spi is owned by me. I don't know if we have a better notation for all the rest that is not already covered by somebody else? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de Humanity has the stars in its future, and that future is too important to be lost under the burden of juvenile folly and ignorant superstition. - Isaac Asimov ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Hi Heiko, Wolfgang, On Fri, 31 Oct 2014 12:44:07 +0100 Wolfgang Denk w...@denx.de wrote: Dear Jagan, In message CAD6G_RRkDhNHC=+OtgtXPd7WdfJzq2bokbMKhKnL=blsx-a...@mail.gmail.com you wrote: I am now ready for taking over the ownership for MTD ... Is it for entire drivers/mtd ? or any specific parts? This is meant for all parts of drivers/mtd that are not already covered by other custodians. +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* I am afraid this does not work at all. Do you mean this? F:drivers/mtd/ Don't add entire mtd - drivers/mtd/spi is owned by me. I don't know if we have a better notation for all the rest that is not already covered by somebody else? Let's see the last part of the MAINTAINERS: THE REST M: Tom Rini tr...@ti.com L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained T: git git://git.denx.de/u-boot.git F: * F: */ This entry does __not__ mean everything is maintained by Tom, but Tom owns all the rest that is not covered by somebody else. MTD M: Heiko Schocher h...@denx.de S: Maintained T: git git://git.denx.de/u-boot-mtd.git F: drivers/mtd/ I think this makes sense. Let's study from linux/MAINTAINERS! MEMORY TECHNOLOGY DEVICES (MTD) M: David Woodhouse dw...@infradead.org M: Brian Norris computersforpe...@gmail.com L: linux-...@lists.infradead.org W: http://www.linux-mtd.infradead.org/ Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ T: git git://git.infradead.org/linux-mtd.git T: git git://git.infradead.org/l2-mtd.git S: Maintained F: drivers/mtd/ F: include/linux/mtd/ F: include/uapi/mtd/ [snip] ONENAND FLASH DRIVER M: Kyungmin Park kyungmin.p...@samsung.com L: linux-...@lists.infradead.org S: Maintained F: drivers/mtd/onenand/ F: include/linux/mtd/onenand*.h BTW, CFI FLASH entry is questionable. CFI FLASH M: Stefan Roese s...@denx.de S: Maintained T: git git://git.denx.de/u-boot-cfi-flash.git F: drivers/mtd/* Do all the files in drivers/mtd belong to CFI FLASH subsystem? Best Regards Masahiro Yamada ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
On 31.10.2014 13:46, Heiko Schocher wrote: BTW, CFI FLASH entry is questionable. CFI FLASH M:Stefan Roeses...@denx.de S:Maintained T:git git://git.denx.de/u-boot-cfi-flash.git F:drivers/mtd/* Do all the files in drivers/mtd belong to CFI FLASH subsystem? I think no ... Stefan, can you send an update for this? Yes, will do. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] MAINTAINERS: add me as a maintainer of MTD
Hi Masahiro Yamada, On 31 October 2014 17:59, Masahiro Yamada yamad...@jp.panasonic.com wrote: Hi Heiko, Wolfgang, On Fri, 31 Oct 2014 12:44:07 +0100 Wolfgang Denk w...@denx.de wrote: Dear Jagan, In message CAD6G_RRkDhNHC=+OtgtXPd7WdfJzq2bokbMKhKnL=blsx-a...@mail.gmail.com you wrote: I am now ready for taking over the ownership for MTD ... Is it for entire drivers/mtd ? or any specific parts? This is meant for all parts of drivers/mtd that are not already covered by other custodians. +M: Heiko Schocher h...@denx.de +S: Maintained +T: git git://git.denx.de/u-boot-mtd.git +F: drivers/mtd* I am afraid this does not work at all. I too feel that this mayn't work - for everything but uncovered part. Do you mean this? F:drivers/mtd/ Don't add entire mtd - drivers/mtd/spi is owned by me. I don't know if we have a better notation for all the rest that is not already covered by somebody else? Let's see the last part of the MAINTAINERS: THE REST M: Tom Rini tr...@ti.com L: u-boot@lists.denx.de Q: http://patchwork.ozlabs.org/project/uboot/list/ S: Maintained T: git git://git.denx.de/u-boot.git F: * F: */ This entry does __not__ mean everything is maintained by Tom, but Tom owns all the rest that is not covered by somebody else. MTD M: Heiko Schocher h...@denx.de S: Maintained T: git git://git.denx.de/u-boot-mtd.git F: drivers/mtd/ I think this makes sense. Let's study from linux/MAINTAINERS! MEMORY TECHNOLOGY DEVICES (MTD) M: David Woodhouse dw...@infradead.org M: Brian Norris computersforpe...@gmail.com L: linux-...@lists.infradead.org W: http://www.linux-mtd.infradead.org/ Q: http://patchwork.ozlabs.org/project/linux-mtd/list/ T: git git://git.infradead.org/linux-mtd.git T: git git://git.infradead.org/l2-mtd.git S: Maintained F: drivers/mtd/ F: include/linux/mtd/ F: include/uapi/mtd/ Linux in MTD is shared by two maintainer where whole drivers/mtd [snip] ONENAND FLASH DRIVER M: Kyungmin Park kyungmin.p...@samsung.com L: linux-...@lists.infradead.org S: Maintained F: drivers/mtd/onenand/ F: include/linux/mtd/onenand*.h BTW, CFI FLASH entry is questionable. CFI FLASH M: Stefan Roese s...@denx.de S: Maintained T: git git://git.denx.de/u-boot-cfi-flash.git F: drivers/mtd/* Do all the files in drivers/mtd belong to CFI FLASH subsystem? No - it has cfi, ubifs, nand, sf thanks! -- Jagan. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
