Re: [U-Boot] moderated list?
On Thu, Feb 12, 2015 at 08:13:40PM +0100, Marco Cavallini wrote: Your mail to 'U-Boot' is being held until the list moderator can review it for approval. Is this list moderated ? For some long time, yes, you must be subscribed and certain emails (large size, large # of recipients) get held too. There's a few people with the password and we try and keep things from being held too long. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] i.MX28 u-boot SPL fail
Hi,
On a custom i.MX28 board I am using u-boot-2015.01.
The debug port DUART is not the same as i.MX28, so I changed these
settings in iomux.c:
const iomux_cfg_t iomux_setup[] = {
/* DUART */
// MX28_PAD_PWM0__DUART_RX,
// MX28_PAD_PWM1__DUART_TX,
/* DUART */
/* Unconfigure BOOT ROM default DUART */
MX28_PAD_PWM0__GPIO_3_16,
MX28_PAD_PWM1__GPIO_3_17,
/* Configure DUART on alternate pins */
MX28_PAD_I2C0_SCL__DUART_RX,
MX28_PAD_I2C0_SDA__DUART_TX,
I enabled #define CONFIG_SPL_SERIAL_SUPPORT and built uboot with :
make u-boot.sb
At last I can program the board only using MfgTools or 'mxsldr', or it
seems working.
The problem is that I get no messages on output debug port or some
random chars every 5, 10 boots
At this point I have some doubts and questions:
- is the u-boot.sb suitable to be run from MfgTools?
- should I expect any char on the serial debug port?
- do I have to use the 'elftosb' tool to convert my binary? (README says not)
TIA
--
Marco
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[U-Boot] [PATCH v2 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move boot image generation to mkimage framework
common/image.c | 1 +
include/image.h | 1 +
scripts/Makefile.spl | 9 +++
tools/Makefile | 1 +
tools/lpc32xximage.c | 178 +++
5 files changed, 190 insertions(+)
create mode 100644 tools/lpc32xximage.c
diff --git a/common/image.c b/common/image.c
index a911aa9..162b682 100644
--- a/common/image.c
+++ b/common/image.c
@@ -149,6 +149,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_MXSIMAGE, mxsimage, Freescale MXS Boot Image,},
{ IH_TYPE_ATMELIMAGE, atmelimage, ATMEL ROM-Boot Image,},
{ IH_TYPE_X86_SETUP, x86_setup, x86 setup.bin,},
+ { IH_TYPE_LPC32XXIMAGE, lpc32xximage, LPC32XX Boot Image, },
{ -1, , , },
};
diff --git a/include/image.h b/include/image.h
index 0e6af00..3844be6 100644
--- a/include/image.h
+++ b/include/image.h
@@ -242,6 +242,7 @@ struct lmb;
#define IH_TYPE_ATMELIMAGE 18 /* ATMEL ROM bootable Image */
#define IH_TYPE_SOCFPGAIMAGE 19 /* Altera SOCFPGA Preloader */
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
+#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
/*
* Compression Types
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index e4b9881..55d8b6f 100644
--- a/scripts/Makefile.spl
+++ b/scripts/Makefile.spl
@@ -147,6 +147,11 @@ endif
boot.bin: $(obj)/u-boot-spl.bin
$(call if_changed,mkimage)
+MKIMAGEFLAGS_lpc32xx-boot.bin = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE)
+
+lpc32xx-boot.bin: $(obj)/u-boot-spl.bin
+ $(call if_changed,mkimage)
+
ALL-y += $(obj)/$(SPL_BIN).bin
ifdef CONFIG_SAMSUNG
@@ -159,6 +164,10 @@ ALL-y += $(obj)/sunxi-spl.bin
endif
endif
+ifdef CONFIG_LPC32XX_SPL
+ALL-y += lpc32xx-boot.bin
+endif
+
ifeq ($(CONFIG_SYS_SOC),at91)
ALL-y += boot.bin
endif
diff --git a/tools/Makefile b/tools/Makefile
index e4b23eb..c34c448 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -83,6 +83,7 @@ dumpimage-mkimage-objs := aisimage.o \
imximage.o \
kwbimage.o \
lib/md5.o \
+ lpc32xximage.o \
mxsimage.o \
omapimage.o \
os_support.o \
diff --git a/tools/lpc32xximage.c b/tools/lpc32xximage.c
new file mode 100644
index 000..6b3865f
--- /dev/null
+++ b/tools/lpc32xximage.c
@@ -0,0 +1,178 @@
+/*
+ * Image manipulator for LPC32XX SoCs
+ *
+ * (C) Copyright 2015 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * Derived from omapimage.c:
+ *
+ * (C) Copyright 2010
+ * Linaro LTD, www.linaro.org
+ * Author: John Rigby john.ri...@linaro.org
+ * Based on TI's signGP.c
+ *
+ * (C) Copyright 2009
+ * Stefano Babic, DENX Software Engineering, sba...@denx.de.
+ *
+ * (C) Copyright 2008
+ * Marvell Semiconductor www.marvell.com
+ * Written-by: Prafulla Wadaskar prafu...@marvell.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include imagetool.h
+#include compiler.h
+#include image.h
+
+/*
+ * NAND page 0 boot header
+ */
+
+struct nand_page_0_boot_header {
+ uint32_t data[129];
+ uint32_t pad[383];
+};
+
+/*
+ * Default ICC (interface configuration data [sic]) if none specified
+ * in board config
+ */
+
+#ifndef LPC32XX_BOOT_ICR
+#define LPC32XX_BOOT_ICR 0x0096
+#endif
+
+/*
+ * Default boot NAND page size if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGESIZE
+#define LPC32XX_BOOT_NAND_PAGESIZE 2048
+#endif
+
+/*
+ * Default boot NAND pages per sector if none specified in board config
+ */
+
+#ifndef LPC32XX_BOOT_NAND_PAGES_PER_SECTOR
+#define LPC32XX_BOOT_NAND_PAGES_PER_SECTOR 64
+#endif
+
+/*
+ * Maximum size for boot code is 56K unless defined in board config
+ */
+
+#ifndef LPC32XX_BOOT_CODESIZE
+#define LPC32XX_BOOT_CODESIZE (56*1024)
+#endif
+
+/* signature byte for a readable block */
+
+#define LPC32XX_BOOT_BLOCK_OK 0xaa
+
+static struct nand_page_0_boot_header lpc32xximage_header;
+
+static int lpc32xximage_check_image_types(uint8_t type)
+{
+ if (type == IH_TYPE_LPC32XXIMAGE)
+ return EXIT_SUCCESS;
+ return EXIT_FAILURE;
+}
+
+static int lpc32xximage_verify_header(unsigned char *ptr, int image_size,
+ struct image_tool_params *params)
+{
+ struct nand_page_0_boot_header *hdr =
+ (struct nand_page_0_boot_header *)ptr;
+
+ /* turn image size from bytes to NAND pages, page 0 included */
+ int image_size_in_pages = ((image_size - 1)
+ / LPC32XX_BOOT_NAND_PAGESIZE);
+
+ if (hdr-data[0] != (0xff LPC32XX_BOOT_ICR))
+ return -1;
+ if
[U-Boot] [PATCH v2 0/8] Extend LPC32xx functionality and add LPC32xx-based work_92015 board
This series extends functionality for the LPC32xx platform and introduces the WORK Microwave work_92105 board which makes use of the extended functionality. NOTES: The series is not entirely checkpatch-clean. The following warnings and checks were not fixed: 1. warning: arch/arm/Kconfig,241: please write a paragraph that describes the config symbol fully Other symbols in the same file have no description either. For consistency, I did not add the requested description. 1. check: include/configs/work_92105.h,177: spaces required around that ':' (ctx:VxV) (5 occurrences on the same line) This is due to the value of CONFIG_ETHADDR not being in quotes. As it never is in any other definition of CONFIG_ETHADDR, I left it unchanged. Changes in v2: - move from legacy to Driver Model support - added MUX setting for SSP0 - cosmetic: added a blank line before copyright - move boot image generation to mkimage framework Albert ARIBAUD (3ADEV) (8): lpc32xx: add Ethernet support lpc32xx: mtd: nand: add MLC NAND controller lpc32xx: i2c: add LPC32xx I2C interface support lpc32xx: add GPIO support lpc32xx: add LPC32xx SSP support (SPI mode) dtt: add ds620 support lpc32xx: add lpc32xx-spl.bin boot image target lpc32xx: add support for board work_92105 arch/arm/Kconfig | 6 + arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 + arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++ arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 13 + arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 43 ++ arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +++ arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 ++ arch/arm/include/asm/arch-lpc32xx/clk.h| 16 + arch/arm/include/asm/arch-lpc32xx/config.h | 3 + arch/arm/include/asm/arch-lpc32xx/cpu.h| 3 + arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++ arch/arm/include/asm/arch-lpc32xx/mux.h| 18 + arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 8 +- board/work-microwave/work_92105/Kconfig| 15 + board/work-microwave/work_92105/MAINTAINERS| 6 + board/work-microwave/work_92105/Makefile | 8 + board/work-microwave/work_92105/README | 23 + board/work-microwave/work_92105/work_92105.c | 86 +++ .../work-microwave/work_92105/work_92105_display.c | 349 +++ .../work-microwave/work_92105/work_92105_display.h | 14 + common/image.c | 1 + configs/work_92105_defconfig | 5 + drivers/gpio/Makefile | 1 + drivers/gpio/lpc32xx_gpio.c| 268 + drivers/hwmon/Makefile | 1 + drivers/hwmon/ds620.c | 65 +++ drivers/i2c/Makefile | 1 + drivers/i2c/lpc32xx_i2c.c | 249 drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/lpc32xx_nand_mlc.c| 589 +++ drivers/net/Makefile | 1 + drivers/net/lpc32xx_eth.c | 636 + drivers/spi/Makefile | 1 + drivers/spi/lpc32xx_ssp.c | 132 + include/configs/work_92105.h | 259 + include/dtt.h | 15 +- include/image.h| 1 + include/netdev.h | 1 + scripts/Makefile.spl | 9 + tools/Makefile | 1 + tools/lpc32xximage.c | 178 ++ 41 files changed, 3222 insertions(+), 8 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h create mode 100644 board/work-microwave/work_92105/Kconfig create mode 100644 board/work-microwave/work_92105/MAINTAINERS create mode 100644 board/work-microwave/work_92105/Makefile create mode 100644 board/work-microwave/work_92105/README create mode 100644 board/work-microwave/work_92105/work_92105.c create mode 100644 board/work-microwave/work_92105/work_92105_display.c create mode 100644 board/work-microwave/work_92105/work_92105_display.h create mode 100644 configs/work_92105_defconfig create mode 100644 drivers/gpio/lpc32xx_gpio.c create mode 100644 drivers/hwmon/ds620.c create mode 100644 drivers/i2c/lpc32xx_i2c.c create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c create mode 100644 drivers/net/lpc32xx_eth.c create mode 100644 drivers/spi/lpc32xx_ssp.c create mode 100644 include/configs/work_92105.h create
[U-Boot] moderated list?
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[U-Boot] [PATCH] m68k: Add generic board support for MCF547X/8X and MCF5445X
This patch adds generic board support for MCF547X/8X and MCF5445X.
It is based on the patch about common generic board support for
M68K architecture sent by Angelo.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
common/board_f.c | 8
common/board_r.c | 2 +-
include/asm-generic/u-boot.h | 7 ++-
include/configs/M54451EVB.h | 2 ++
include/configs/M54455EVB.h | 2 ++
include/configs/M5475EVB.h | 4 +++-
include/configs/M5485EVB.h | 4 +++-
7 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c
index 0de3919..21ea677 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -674,6 +674,14 @@ static int setup_board_part2(void)
bd-bi_ipbfreq = gd-arch.ipb_clk;
bd-bi_pcifreq = gd-pci_clk;
#endif /* CONFIG_MPC5xxx */
+#if defined(CONFIG_M68K) defined(CONFIG_PCI)
+ bd-bi_pcifreq = gd-pci_clk;
+#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ bd-bi_inpfreq = gd-arch.inp_clk; /* input Freq in Hz */
+ bd-bi_vcofreq = gd-arch.vco_clk; /* vco Freq in Hz */
+ bd-bi_flbfreq = gd-arch.flb_clk; /* flexbus Freq in Hz */
+#endif
return 0;
}
diff --git a/common/board_r.c b/common/board_r.c
index b2488c0..05870ef 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -744,7 +744,7 @@ init_fnc_t init_sequence_r[] = {
initr_flash,
#endif
INIT_FUNC_WATCHDOG_RESET
-#if defined(CONFIG_PPC)
+#if defined(CONFIG_PPC) || defined(CONFIG_M68K)
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index e00db7d..5bc13cb 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -62,10 +62,15 @@ typedef struct bd_info {
#if defined(CONFIG_MPC512X)
unsigned long bi_ipsfreq; /* IPS Bus Freq, in MHz */
#endif /* CONFIG_MPC512X */
-#if defined(CONFIG_MPC5xxx)
+#if defined(CONFIG_MPC5xxx) || defined(CONFIG_M68K)
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
+#if defined(CONFIG_EXTRA_CLOCK)
+ unsigned long bi_inpfreq; /* input Freq in MHz */
+ unsigned long bi_vcofreq; /* vco Freq in MHz */
+ unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
+#endif
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405EP) || \
diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h
index 0f4b726..734a77f 100644
--- a/include/configs/M54451EVB.h
+++ b/include/configs/M54451EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54451 /* define processor type */
#define CONFIG_M54451EVB /* M54451EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE115200
diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h
index 7a55d3c..2faf581 100644
--- a/include/configs/M54455EVB.h
+++ b/include/configs/M54455EVB.h
@@ -22,6 +22,8 @@
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE115200
diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h
index e88a6bd..2f4549f 100644
--- a/include/configs/M5475EVB.h
+++ b/include/configs/M5475EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT5000/* timeout in milliseconds, max
timeout is 6.71sec */
/* Command line configuration */
diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h
index e412806..9aa02f7 100644
--- a/include/configs/M5485EVB.h
+++ b/include/configs/M5485EVB.h
@@ -22,11 +22,13 @@
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
+#define CONFIG_DISPLAY_BOARDINFO
+
#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT (0)
#define CONFIG_BAUDRATE115200
-#define CONFIG_HW_WATCHDOG
+#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT5000/* timeout in milliseconds, max
timeout is 6.71sec */
/* Command line configuration */
--
2.1.0.27.g96db324
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[U-Boot] [PATCH v3 0/9] ARM: remove non-generic boards
Based on Tom's announce mail (http://lists.denx.de/pipermail/u-boot/2015-February/203606.html), let's start removing non-generic ARM boards. No conversion patches have been posted for these boards. Changes in v3: - Do not remove devkit3250 because Vladimir has post a patch to convert it into Generic Board. Changes in v2: - Do not remove armada100 boards because Ajay will send a patch to convert them. Masahiro Yamada (9): ARM: remove mx31ads board support ARM: mx31: remove imx31_phycore board ARM: remove jadecpu board support ARM: remove zmx25 board support ARM: remove dkb board support ARM: remove cm4008 and cm41xx board support ARM: remove a320evb board support ARM: remove tnetv107x board support ARM: davinci: remove hawkboard support arch/arm/Kconfig | 45 -- arch/arm/cpu/arm1176/Makefile | 1 - arch/arm/cpu/arm1176/start.S | 22 - arch/arm/cpu/arm1176/tnetv107x/Makefile| 6 - arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 -- arch/arm/cpu/arm1176/tnetv107x/init.c | 22 - arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 - arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 - arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 arch/arm/cpu/arm920t/Makefile | 2 - arch/arm/cpu/arm920t/a320/Makefile | 9 - arch/arm/cpu/arm920t/a320/reset.S | 10 - arch/arm/cpu/arm920t/a320/timer.c | 118 - arch/arm/cpu/arm920t/ks8695/Makefile | 9 - arch/arm/cpu/arm920t/ks8695/lowlevel_init.S| 189 arch/arm/cpu/arm920t/ks8695/timer.c| 77 arch/arm/cpu/arm926ejs/Makefile| 2 - arch/arm/cpu/arm926ejs/davinci/Kconfig | 4 - arch/arm/cpu/arm926ejs/mb86r0x/Makefile| 8 - arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 -- arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 - arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 - arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 - arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 - arch/arm/cpu/arm926ejs/pantheon/timer.c| 201 - arch/arm/include/asm/arch-a320/a320.h | 22 - arch/arm/include/asm/arch-ks8695/platform.h| 294 arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 - arch/arm/include/asm/arch-mb86r0x/mb86r0x.h| 599 - arch/arm/include/asm/arch-pantheon/config.h| 53 --- arch/arm/include/asm/arch-pantheon/cpu.h | 77 arch/arm/include/asm/arch-pantheon/gpio.h | 0 arch/arm/include/asm/arch-pantheon/mfp.h | 39 -- arch/arm/include/asm/arch-pantheon/pantheon.h | 38 -- arch/arm/include/asm/arch-tnetv107x/clock.h| 53 --- arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 --- arch/arm/include/asm/arch-tnetv107x/mux.h | 291 arch/arm/lib/asm-offsets.c | 46 -- board/Marvell/dkb/Kconfig | 15 - board/Marvell/dkb/MAINTAINERS | 6 - board/Marvell/dkb/Makefile | 9 - board/Marvell/dkb/dkb.c| 85 board/cm4008/Kconfig | 12 - board/cm4008/MAINTAINERS | 6 - board/cm4008/Makefile | 8 - board/cm4008/cm4008.c | 88 board/cm4008/config.mk | 1 - board/cm4008/flash.c | 395 board/cm41xx/Kconfig | 12 - board/cm41xx/MAINTAINERS | 6 - board/cm41xx/Makefile | 8 - board/cm41xx/cm41xx.c | 88 board/cm41xx/config.mk | 1 - board/cm41xx/flash.c | 395 board/davinci/da8xxevm/Kconfig | 13 - board/davinci/da8xxevm/MAINTAINERS | 8 - board/davinci/da8xxevm/Makefile| 1 - board/davinci/da8xxevm/README.hawkboard| 92 board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 - board/davinci/da8xxevm/hawkboard.c | 120 - board/davinci/da8xxevm/u-boot-spl-hawk.lds | 69 --- board/faraday/a320evb/Kconfig | 15 - board/faraday/a320evb/MAINTAINERS | 6 - board/faraday/a320evb/Makefile | 9 - board/faraday/a320evb/a320evb.c| 59 --- board/faraday/a320evb/lowlevel_init.S | 106 - board/freescale/mx31ads/Kconfig| 15 - board/freescale/mx31ads/MAINTAINERS| 6 - board/freescale/mx31ads/Makefile | 8 - board/freescale/mx31ads/lowlevel_init.S| 268
[U-Boot] [PATCH v3 8/9] ARM: remove tnetv107x board support
This is still a non-generic board. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Chan-Taek Park c-p...@ti.com --- Changes in v3: None Changes in v2: None arch/arm/Kconfig | 5 - arch/arm/cpu/arm1176/Makefile | 1 - arch/arm/cpu/arm1176/start.S | 22 -- arch/arm/cpu/arm1176/tnetv107x/Makefile| 6 - arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 - arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 - arch/arm/cpu/arm1176/tnetv107x/init.c | 22 -- arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 - arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 -- arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 -- arch/arm/include/asm/arch-tnetv107x/clock.h| 53 --- arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 - arch/arm/include/asm/arch-tnetv107x/mux.h | 291 - board/ti/tnetv107xevm/Kconfig | 15 - board/ti/tnetv107xevm/MAINTAINERS | 6 - board/ti/tnetv107xevm/Makefile | 5 - board/ti/tnetv107xevm/config.mk| 5 - board/ti/tnetv107xevm/sdb_board.c | 134 configs/tnetv107x_evm_defconfig| 2 - doc/README.scrapyard | 1 + drivers/watchdog/Makefile | 1 - drivers/watchdog/tnetv107x_wdt.c | 165 -- include/configs/tnetv107x_evm.h| 139 23 files changed, 1 insertion(+), 1964 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h delete mode 100644 board/ti/tnetv107xevm/Kconfig delete mode 100644 board/ti/tnetv107xevm/MAINTAINERS delete mode 100644 board/ti/tnetv107xevm/Makefile delete mode 100644 board/ti/tnetv107xevm/config.mk delete mode 100644 board/ti/tnetv107xevm/sdb_board.c delete mode 100644 configs/tnetv107x_evm_defconfig delete mode 100644 drivers/watchdog/tnetv107x_wdt.c delete mode 100644 include/configs/tnetv107x_evm.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 350574f..8249567 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -379,10 +379,6 @@ config TARGET_RPI bool Support rpi select CPU_ARM1176 -config TARGET_TNETV107X_EVM - bool Support tnetv107x_evm - select CPU_ARM1176 - config TARGET_INTEGRATORAP_CM946ES bool Support integratorap_cm946es select CPU_ARM946ES @@ -947,7 +943,6 @@ source board/ti/am335x/Kconfig source board/ti/am43xx/Kconfig source board/ti/ti814x/Kconfig source board/ti/ti816x/Kconfig -source board/ti/tnetv107xevm/Kconfig source board/timll/devkit3250/Kconfig source board/toradex/colibri_pxa270/Kconfig source board/tqc/tqma6/Kconfig diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index ead2303..480e130 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -12,4 +12,3 @@ extra-y = start.o obj-y = cpu.o obj-$(CONFIG_BCM2835) += bcm2835/ -obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 0704bdd..ac937bf 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -96,28 +96,6 @@ mmu_disable: mov pc, r2 mmu_disable_phys: -#ifdef CONFIG_DISABLE_TCM - /* -* Disable the TCMs -*/ - mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ - cmp r0, #0 - beq skip_tcmdisable - mov r1, #0 - mov r2, #1 - tst r0, r2 - mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ - tst r0, r2, LSL #16 - mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ -skip_tcmdisable: -#endif -#endif - -#ifdef CONFIG_PERIPORT_REMAP - /* Peri port setup */ - ldr r0, =CONFIG_PERIPORT_BASE - orr r0, r0, #CONFIG_PERIPORT_SIZE - mcr p15,0,r0,c15,c2,4 #endif /* diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile deleted file mode 100644 index a4c1edf..000 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += aemif.o clock.o init.o mux.o timer.o -obj-y += lowlevel_init.o diff --git
[U-Boot] [Q] Why does SPL use uImage load address as entry point?
Hi,
I'm doing some work with U-Boot SPL, and noticed the following code in the
spl_parse_image_header function (common/spl/spl.c):
if (image_get_magic(header) == IH_MAGIC) {
if (spl_image.flags SPL_COPY_PAYLOAD_ONLY) {
...
} else {
spl_image.entry_point = image_get_load(header);
/* Load including the header */
spl_image.load_addr = spl_image.entry_point -
header_size;
...
}
Could anyone tell me why SPL uses the load address from the header as the
entry point address, and then calculates the entry point, rather than just
use the ones in the uImage header?
Thanks
Phil
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[U-Boot] [PATCH v3 6/9] ARM: remove cm4008 and cm41xx board support
These are still non-generic boards. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Greg Ungerer greg.unge...@opengear.com --- Changes in v3: None Changes in v2: None arch/arm/Kconfig| 10 - arch/arm/cpu/arm920t/Makefile | 1 - arch/arm/cpu/arm920t/ks8695/Makefile| 9 - arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 - arch/arm/cpu/arm920t/ks8695/timer.c | 77 -- arch/arm/include/asm/arch-ks8695/platform.h | 294 - board/cm4008/Kconfig| 12 - board/cm4008/MAINTAINERS| 6 - board/cm4008/Makefile | 8 - board/cm4008/cm4008.c | 88 --- board/cm4008/config.mk | 1 - board/cm4008/flash.c| 395 board/cm41xx/Kconfig| 12 - board/cm41xx/MAINTAINERS| 6 - board/cm41xx/Makefile | 8 - board/cm41xx/cm41xx.c | 88 --- board/cm41xx/config.mk | 1 - board/cm41xx/flash.c| 395 configs/cm4008_defconfig| 2 - configs/cm41xx_defconfig| 2 - doc/README.scrapyard| 2 + drivers/net/Makefile| 1 - drivers/net/ks8695eth.c | 229 drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_ks8695.c | 121 - include/configs/cm4008.h| 104 include/configs/cm41xx.h| 104 include/netdev.h| 1 - include/serial.h| 1 - 30 files changed, 2 insertions(+), 2168 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c delete mode 100644 arch/arm/include/asm/arch-ks8695/platform.h delete mode 100644 board/cm4008/Kconfig delete mode 100644 board/cm4008/MAINTAINERS delete mode 100644 board/cm4008/Makefile delete mode 100644 board/cm4008/cm4008.c delete mode 100644 board/cm4008/config.mk delete mode 100644 board/cm4008/flash.c delete mode 100644 board/cm41xx/Kconfig delete mode 100644 board/cm41xx/MAINTAINERS delete mode 100644 board/cm41xx/Makefile delete mode 100644 board/cm41xx/cm41xx.c delete mode 100644 board/cm41xx/config.mk delete mode 100644 board/cm41xx/flash.c delete mode 100644 configs/cm4008_defconfig delete mode 100644 configs/cm41xx_defconfig delete mode 100644 drivers/net/ks8695eth.c delete mode 100644 drivers/serial/serial_ks8695.c delete mode 100644 include/configs/cm4008.h delete mode 100644 include/configs/cm41xx.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6317d9d..9b3a71c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -97,14 +97,6 @@ config TARGET_SCB9328 bool Support scb9328 select CPU_ARM920T -config TARGET_CM4008 - bool Support cm4008 - select CPU_ARM920T - -config TARGET_CM41XX - bool Support cm41xx - select CPU_ARM920T - config TARGET_VCMA9 bool Support VCMA9 select CPU_ARM920T @@ -875,8 +867,6 @@ source board/calao/sbc35_a9g20/Kconfig source board/calao/tny_a9260/Kconfig source board/calao/usb_a9263/Kconfig source board/cirrus/edb93xx/Kconfig -source board/cm4008/Kconfig -source board/cm41xx/Kconfig source board/compulab/cm_t335/Kconfig source board/compulab/cm_fx6/Kconfig source board/congatec/cgtqmx6eval/Kconfig diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a72e5de..a30a572 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -14,5 +14,4 @@ obj-$(if $(filter a320,$(SOC)),y) += a320/ obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_KS8695) += ks8695/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index 400aa89..000 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, w...@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lowlevel_init.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index a2a07f2..000 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer greg.unge...@opengear.com - * - *
Re: [U-Boot] [MinnowBoard] Mainline U-Boot for MinnowBoard MAX
Hi Simon, great to hear! Currently I'm a little bit busy (bringing up of a E3800 board arriving yesterday from production), but as soon as possible I'll give it a try! Thank you very much for your work! Best Regards, Martin -Ursprüngliche Nachricht- Von: elinux-MinnowBoard [mailto:elinux-minnowboard- boun...@lists.elinux.org] Im Auftrag von Simon Glass Gesendet: Mittwoch, 11. Februar 2015 03:41 An: MinnowBoard Development and Community Discussion; U-Boot Mailing List Betreff: [MinnowBoard] Mainline U-Boot for MinnowBoard MAX Hi, Just a note to say that support for the MinnowBoard MAX has now landed in U-Boot mainline (also Intel Quark support as it happens). You can run it both 'bare metal' and as a coreboot payload. The upcoming 2015.04 release will include this support but for now you can get it from the U-Boot git tree. You can find a basic README here [1]. There is still work to do so if anyone is interested, please contribute patches! Thanks to those on the MinnowBoard list who helped with setting up a suitable working environment. Regards, Simon [1] http://git.denx.de/?p=u-boot.git;a=blob;f=doc/README.x86 ___ elinux-MinnowBoard mailing list elinux-minnowbo...@lists.elinux.org http://lists.elinux.org/mailman/listinfo/elinux-minnowboard ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 0/3] imx: mx6slevk add pmic support
Hi Peng, On 12/02/2015 02:36, Peng Fan wrote: This patch set is extracted from the previous imx:mx6 add ldo bypass patch set, with only one return value change. patch 1/3 is add pad settings for I2C1 patch 2/3 is add I2C and PMIC support in board header file patch 3/3 is to add pmic support for mx6slevk. patch 3/3 is from patch 3/12 in previous imx:mx6 add ldo bypass patch, with only one small change is return value. Changes v3: Take Fabio's suggestion, for patch 3/3, remove ret variable, and directly return pfuze_mode_init(xxx) Changes v2: Changing return -EIO to return ret. Peng Fan (3): imx:mx6sl add I2c pad settings imx:mx6slevk add pmic and i2c configuration imx:mx6slevk implement power init board arch/arm/include/asm/arch-mx6/mx6sl_pins.h | 5 board/freescale/mx6slevk/mx6slevk.c| 42 ++ include/configs/mx6slevk.h | 12 + 3 files changed, 59 insertions(+) They look good for me - if no comments will be posted, they will be merge by next iteration. Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de = ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] dm: sh: serial: Add support driver model
On 11 February 2015 at 21:48, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: This adds driver model support with this driver. This was tested by Koelsch board and Gose board. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- V5: Fix build with SH7723 and more. V4: Fix build with SH. V3: Add function of checking -EAGAIN without DM. V2: Fix loop for tx fifo and tx fifo. Fix write return code writing with DM. drivers/serial/serial_sh.c | 321 --- drivers/serial/serial_sh.h | 30 ++-- include/dm/platform_data/serial_sh.h | 37 3 files changed, 275 insertions(+), 113 deletions(-) create mode 100644 include/dm/platform_data/serial_sh.h Acked-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH V2 08/10] arm: socfpga: Add Altera Arria V DK support
On Thursday, February 12, 2015 at 09:29:47 PM, Pavel Machek wrote: Hi! I think we can improve this later. In the end, the structure should be either the way DTs are structured in kernel OR we should have just one single config for all SoCFPGA boards. The later is of course preferred. For now, I'm tempted to apply this as-is so we at least have the groundwork in place and can move on from that. What do you say ? We spent enough time arguing, just go ahead. Roger that ! Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/3] dm:gpio:mxc add a bank_index entry in platdata
On 10 February 2015 at 17:37, Simon Glass s...@chromium.org wrote: On 9 February 2015 at 23:46, Peng Fan peng@freescale.com wrote: Add a new entry in platdata structure and intialize bank_index in mxc_plat array. This new entry can avoid using `plat - mxc_plat` by using `plat-bank_index`. Signed-off-by: Peng Fan peng@freescale.com Acked-by: Igor Grinberg grinb...@compulab.co.il Acked-by: Simon Glass s...@chromium.org Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/3] dm:gpio:mxc add DT support
On 10 February 2015 at 17:37, Simon Glass s...@chromium.org wrote: On 10 February 2015 at 00:46, Igor Grinberg grinb...@compulab.co.il wrote: On 02/10/15 08:46, Peng Fan wrote: This patch add DT support for mxc gpio driver. There are one place using CONFIG_OF_CONTROL macro. 1. The U_BOOT_DEVICES and mxc_plat array are complied out. To DT, platdata is alloced using calloc, so there is no need to use mxc_plat. The following situations are tested, and all work fine: 1. with DM, without DT 2. with DM and DT 3. without DM Since device tree has not been upstreamed, if want to test this patch. The followings need to be done. + pieces of code does not gpio_request when using gpio_direction_xxx and etc, need to request gpio. + move the gpio settings from board_early_init_f to board_init + define CONFIG_DM ,CONFIG_DM_GPIO and CONFIG_OF_CONTROL + Add device tree file and do related configuration in `make ARCH=arm menuconfig` These will be done in future patches by step. Signed-off-by: Peng Fan peng@freescale.com Acked-by: Igor Grinberg grinb...@compulab.co.il Acked-by: Simon Glass s...@chromium.org Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/4] dm: Drop unused driver model config_defaults
On 11 February 2015 at 16:33, Simon Glass s...@chromium.org wrote: These are now in Kconfig so we can drop them from the header file. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v3: None Changes in v2: None include/config_defaults.h | 12 1 file changed, 12 deletions(-) Applied to u-boot-dm. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] dm: Add support for all targets which requires MANUAL_RELOC
On 10 February 2015 at 02:55, Michal Simek michal.si...@xilinx.com wrote: On 02/09/2015 11:14 PM, Simon Glass wrote: Hi MIchal, On 9 February 2015 at 03:27, Michal Simek michal.si...@xilinx.com wrote: Hi Simon, On 02/06/2015 06:45 AM, Simon Glass wrote: With a heavy heart: Acked-by: Simon Glass s...@chromium.org Are you going to take this patch to your DM tree? I'm hoping to bring in the Kconfig patches and send a pull request this week, so could do that if it suits. But it is up to you, so let's do whatever makes your life easier. Let me know. works for me. Taking it via your tree is the right way to reach master branch. Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [sunxi] [RFC/RFH] Adding mainline u-boot support for the Olimex A20-SOM-EVB
Hello, I am working on adding support for the Olimex A20-SOM-EVB development board to mainline u-boot (and to the mainline Linux kernel, but that is a topic for a different thread). The board package actually consists of two parts, the A20-SOM-EVB baseboard providing I/O and power supply, and the A20-SOM CPU/memory board that gets plugged onto the baseboard. The schematics for the boards are available online: - A20-SOM CPU module: https://github.com/OLIMEX/SOM/blob/master/A20/A20-SOM/A20-SOM_board_rev_D.pdf?raw=true - A20-SOM-EVB baseboard: https://www.olimex.com/Products/SOM/A20/A20-SOM-EVB/resources/A20-SOM-EVB_schematic.pdf I use the following defconfig with the master branch of git://git.denx.de/u-boot-sunxi.git, but I currently cannot get it to work fully as intended and would appreciate any advice. configs/Olimex-A20-SOM-EVB_defconfig: = CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS=AXP209_POWER,SUNXI_GMAC,RGMII,AHCI,SATAPWR=SUNXI_GPC(3),USB_EHCI CONFIG_FDTFILE=sun7i-a20-olimex-a20-som-evb.dtb CONFIG_MMC0_CD_PIN=PH1 CONFIG_USB1_VBUS_PIN=PH6 CONFIG_USB2_VBUS_PIN=PH3 +S:CONFIG_ARM=y +S:CONFIG_ARCH_SUNXI=y +S:CONFIG_MACH_SUN7I=y +S:CONFIG_DRAM_CLK=384 +S:CONFIG_DRAM_ZQ=127 +S:CONFIG_DRAM_EMR1=4 I try to start u-boot via FEL, as the Micro-SD slot on the A20-SOM is very difficult to reach (even using pliers) when it is plugged onto the baseboard, and having to change SD cards all the time while testing is really cumbersome. The first problem showing up is that starting u-boot via FEL in the traditional style (using a FEL-specific build) does not work. The SPL gets transferred properly and the fel exe command that starts the SPL returns without error, although I get no output on the serial console. Trying to transfer the main u-boot image afterwards fails: $ make distclean $ make Olimex-A20-SOM-EVB_felconfig [...] $ make -j3 [...] $ fel version AWUSBFEX soc=1651(A20) 0001 ver=0001 44 08 scratchpad=7e00 $ fel write 0x2000 spl/u-boot-spl.bin $ fel exe 0x2000 [wait a few seconds for DRAM init] $ fel write 0x4a00 u-boot.bin [takes some time] libusb usb_bulk_send error -7 I have no idea how to further debug this. My first thought was that my DRAM parameters (based on data from a manufacturer-supplied FEX file for the board) are wrong, so that I run into problems while writing the main u-boot image to DRAM, but this is probably not the reason - see below. Running Siarhei's new fel spl command (using a normal non-FEL u-boot build) succeeds in transferring and starting the SPL, which then - with a build from git://git.denx.de/u-boot-sunxi.git - either complains that it cannot do the SD card voltage select when no card is inserted: U-Boot SPL 2015.01-03533-gdb62a4a (Feb 12 2015 - 20:04:29) DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 Card did not respond to voltage select! spl: mmc init failed: err - -17 ### ERROR ### Please RESET the board ### or boots straight into the old u-boot-sunxi that I have on the card: U-Boot SPL 2015.01-03533-gdb62a4a (Feb 12 2015 - 20:04:29) DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 U-Boot 2014.04-10733-gea1ac32 (Feb 08 2015 - 20:04:39) Allwinner Technology CPU: Allwinner A20 (SUN7I) Board: Olimex_A20-SOM I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In this case the SPL does not know that it is booted via FEL, so it tries to load the main u-boot binary from the SD card. The fact that chainloading the (old) u-boot from the SD card works, shows me that the DRAM is working, so I suppose that my DRAM parameters are probably not the reason why the old-style FEL booting does not work. When using a u-boot build from the 20150208-fel-fixes branch of Siarhei's repository at https://github.com/ssvb/u-boot-sunxi.git (plus Hans' config_distro_bootcmd fix from http://lists.denx.de/pipermail/u-boot/2015-February/204286.html) as follows: $ make distclean [...] $ make Olimex-A20-SOM-EVB_defconfig [...] $ make -j3 [...] $ fel version AWUSBFEX soc=1651(A20) 0001 ver=0001 44 08 scratchpad=7e00 $ fel spl u-boot-sunxi-with-spl.bin $ fel write 0x4a00 u-boot.bin $ fel exe 0x4a00 $ u-boot boots fine until it tries to initialize the EHCI controllers: U-Boot SPL 2015.04-rc1-04039-g6385323 (Feb 12 2015 - 21:08:28) DRAM: 1024 MiB CPU: 96000Hz, AXI/AHB/APB: 3/2/2 U-Boot 2015.04-rc1-04039-g6385323 (Feb 12 2015 - 21:08:28) Allwinner Technology CPU: Allwinner A20 (SUN7I) I2C: ready DRAM: 1 GiB MMC: SUNXI SD/MMC: 0 *** Warning - bad CRC, using default environment In:serial Out: serial Err: serial SCSI: SUNXI SCSI INIT SATA link 0 timeout. AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl SATA mode flags: ncq stag pm led clo only pmp pio slum part ccc apst Net: dwmac.1c5 starting USB... USB0: Then u-boot hangs. The problem appears to be with the GPIO pins that control the USB voltage
Re: [U-Boot] [PATCH V2 08/10] arm: socfpga: Add Altera Arria V DK support
Hi! I think we can improve this later. In the end, the structure should be either the way DTs are structured in kernel OR we should have just one single config for all SoCFPGA boards. The later is of course preferred. For now, I'm tempted to apply this as-is so we at least have the groundwork in place and can move on from that. What do you say ? We spent enough time arguing, just go ahead. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5] dm: sh: serial: Add support driver model
On 12 February 2015 at 15:14, Simon Glass s...@chromium.org wrote: On 11 February 2015 at 21:48, Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com wrote: This adds driver model support with this driver. This was tested by Koelsch board and Gose board. Signed-off-by: Nobuhiro Iwamatsu nobuhiro.iwamatsu...@renesas.com --- V5: Fix build with SH7723 and more. V4: Fix build with SH. V3: Add function of checking -EAGAIN without DM. V2: Fix loop for tx fifo and tx fifo. Fix write return code writing with DM. drivers/serial/serial_sh.c | 321 --- drivers/serial/serial_sh.h | 30 ++-- include/dm/platform_data/serial_sh.h | 37 3 files changed, 275 insertions(+), 113 deletions(-) create mode 100644 include/dm/platform_data/serial_sh.h Acked-by: Simon Glass s...@chromium.org Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] dm: at91: Drop use of ATMEL_PIO_PORTS in the header file
On 12 February 2015 at 02:14, Andreas Bießmann andreas.de...@googlemail.com wrote: On 02/12/2015 12:32 AM, Simon Glass wrote: With driver model the number of PIO ports is defined by platform data, so remove it from the header file. Signed-off-by: Simon Glass s...@chromium.org Acked-by: Andreas Bießmann andreas.de...@googlemail.com Applied to u-boot-dm. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/4] dm: at91: snapper: Move driver model CONFIGs to Kconfig
On 11 February 2015 at 16:32, Simon Glass s...@chromium.org wrote: Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v3: - Split out the ATMEL_PIO_PORTS change into its own patch Changes in v2: None configs/snapper9260_defconfig | 3 +++ configs/snapper9g20_defconfig | 3 +++ include/configs/snapper9260.h | 4 3 files changed, 6 insertions(+), 4 deletions(-) Applied to u-boot-dm. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/3] dm: introduce dev_get_addr interface
On 10 February 2015 at 17:37, Simon Glass s...@chromium.org wrote: On 9 February 2015 at 23:46, Peng Fan peng@freescale.com wrote: Abstracting dev_get_addr can improve drivers that want to get device's address. Signed-off-by: Peng Fan peng@freescale.com Acked-by: Igor Grinberg grinb...@compulab.co.il --- drivers/core/device.c | 12 include/dm/device.h | 10 ++ 2 files changed, 22 insertions(+) Acked-by: Simon Glass s...@chromium.org Applied to u-boot-dm, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/4] dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig
On 11 February 2015 at 16:32, Simon Glass s...@chromium.org wrote: Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass s...@chromium.org --- Changes in v3: None Changes in v2: - Add CONFIG_SYS_MALLOC_F as well as CONFIG_SYS_MALLOC_F_LEN Applied to u-boot-dm. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/12] imx:mx6 Support LDO bypass
On Wed, Feb 11, 2015 at 7:47 AM, Tim Harvey thar...@gateworks.com wrote: On Wed, Feb 11, 2015 at 2:49 AM, Robin Gong b38...@freescale.com wrote: snip This is very board dependent. Here you are referring to a board that has a reset input to the PMIC's from the IMX6's watchdog output. In this case, this reset routing/pinmux would be needed regardless of using ldo-bypass mode or not and that should just be a pinmux of the pin your using for WDOG_B. There are two types of reboot in our chip by watchdog : SRS/warm reset (Software Reset Signal) and WDOG_B(reset signal output to external pmic to trigger next power cycle). In fact, warm reset can work most cases except ldo-bypass mode and this is why we connect WDOG_B reset and ldo-bypass here: kernel may trigger warm reset at the lowest cpu freq setpoint, for example VDDARM 0.975v@396Mhz ldo-bypass mode. i.mx6q will reboot with ldo-enable mode @792Mhz and the VDDARM_IN 0.975v can't support system boot.Thus, we need use WDOG_B pin to reset external pmic if using ldo-byapss mode. Hi Robin, I understand that configuring WDOG_B external reset must be used when LDO bypass is used. This should be done in the kernel but you can also set this pinmux up in uboot in the board-specific init. If your kernel is providing the PMIC driver and cpufreq driver that alter the cpu core frequencies it must also be configuring pinmux so that WDOG_B gets routed to the pin that connects to the PMIC so any reset based on that wdog (SRS or timeout) issues a hard reset to the PMIC. Failure to do so is a kernel bug. I believe this is done properly in the Freescale kernel for the reference boards. If you are trying to take care of an issue caused by a watchdog reset (SRS or timeout) not properly resetting a PMIC (ie perhaps a PCB errata where signal doesn't go to the PMIC) then you should probably simply set the PMIC rails where they need to be for the 800MHz operation in the bootloader and not muck with the CPU frequency. Honestly, if your PMIC rails are too low for 800MHz on powerup your bootloader may not be stable anyway right? Note that the operating setpoints have the same SOC voltage for both 792MHz and 396MHz, its only the ARM voltage that is lower for 396 vs 792 and chances are your not going to have an issue just in the bootloader at that point. Robin, The issue your describing was interesting to me and I ran some tests and found that on a board with no reset to the PMIC, an IMX6Q CPU, ldo-bypass enabled, and the CPU freq set to 400MHz (such that VDD_ARM rail set to 0.960V for 400MHz operation) the chip does not even come out of reset (ie when SRS is set in the watchdog controller). So I don't really see any ability to work around this in bootloader software since you won't get there in this case. Possible solutions I can think of for boards without a PMIC reset is to either blow the eFUSE so the chip comes up in 400MHz or in the kernel never allow the VDD_ARM or VDD_SOC rail to go below where they need to be for CPU startup (the only one that does is VDD_ARM) or before soft-reboot make sure the cpufreq is at 800MHz or above (which must be done at higher levels before single-cpu mode in machine_restart). This also does not deal with the case of a watchdog reset and/or a crash handler. Are you findings different? Tim ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] sandbox: Adjust the order of the NO_SDL check
Hello Simon, On 11-02-15 02:52, Simon Glass wrote: An option is provided to avoid using SDL in U-Boot sandbox (and drop support for the LCD). However the check in the Makefile is too late and warnings are printed even if NO_SDL=y is given. Adjust the order to avoid this warning. Signed-off-by: Simon Glass s...@chromium.org --- arch/sandbox/config.mk | 12 ++-- 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk index e38a44b..7b84f02 100644 --- a/arch/sandbox/config.mk +++ b/arch/sandbox/config.mk @@ -5,10 +5,16 @@ PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE PLATFORM_CPPFLAGS += -DCONFIG_ARCH_MAP_SYSMEM -DCONFIG_SYS_GENERIC_BOARD PLATFORM_LIBS += -lrt +# Define this to avoid linking with SDL, which requires SDL libraries +# This can solve 'sdl-config: Command not found' errors +ifneq ($(NO_SDL),) +PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL +else ifdef CONFIG_SANDBOX_SDL PLATFORM_LIBS += $(shell sdl-config --libs) PLATFORM_CPPFLAGS += $(shell sdl-config --cflags) endif +endif # Support generic board on sandbox __HAVE_ARCH_GENERIC_BOARD := y @@ -18,9 +24,3 @@ cmd_u-boot__ = $(CC) -o $@ -T u-boot.lds \ $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map CONFIG_ARCH_DEVICE_TREE := sandbox - -# Define this to avoid linking with SDL, which requires SDL libraries -# This can solve 'sdl-config: Command not found' errors -ifneq ($(NO_SDL),) -PLATFORM_CPPFLAGS += -DSANDBOX_NO_SDL -endif yup, feel free to commit this (it can't do any harm just prevents some warnings). Which I guess translates to Acked-by: Jeroen Hofstee jer...@myspectrum.nl Regards, Jeroen ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] ARM: HYP/non-sec: relocation before enable secondary cores
Hi, Albert and Tom On 2/4/2015 7:02 PM, Marc Zyngier wrote: On 04/02/15 10:15, Peng Fan wrote: If CONFIG_ARMV7_PSCI is not defined and CONFIG_ARMV7_SECURE_BASE is defined, smp_kicl_all_cpus may enable secondary cores and runs into secure_ram_addr( _smp_pen), before code is relocated to secure ram. So need relocation to secure ram before enable secondary cores. Signed-off-by: Peng Fan peng@freescale.com --- arch/arm/cpu/armv7/virt-v7.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index b69fd37..4cb8806 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -112,13 +112,20 @@ int armv7_init_nonsec(void) for (i = 1; i = itlinesnr; i++) writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); + /* +* Relocate secure section before any cpu runs in secure ram. +* smp_kick_all_cpus may enable other cores and runs into secure +* ram, so need to relocate secure section before enabling other +* cores. +*/ + relocate_secure_section(); + #ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); smp_kick_all_cpus(); #endif /* call the non-sec switching code on this CPU also */ - relocate_secure_section(); secure_ram_addr(_nonsec_init)(); return 0; } Seems like a sensible thing to do. FWIW: Acked-by: Marc Zyngier marc.zyng...@arm.com Just kindly remind. Will this patch be merged into u-boot-arm git repo or directly into u-boot master git repo? M. Thanks, Peng. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/1] usb: gadget: fastboot: Add fastboot erase
Hi Steve,
On 11 February 2015 at 05:25, Steve Rae s...@broadcom.com wrote:
Hi, Dileep
On 15-02-10 12:49 AM, Dileep Katta wrote:
Adds the fastboot erase functionality, to erase a partition
specified by name. The erase is performed based on erase group size,
to avoid erasing other partitions. The start address and the size
is aligned to the erase group size for this.
Currently only supports erasing from eMMC.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
Note: The changes are on top of oem command support added by r...@kernel.org
common/fb_mmc.c | 58
+
drivers/usb/gadget/f_fastboot.c | 23
include/fb_mmc.h| 1 +
3 files changed, 82 insertions(+)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6ea3938..3911989 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -10,6 +10,7 @@
#include part.h
#include aboot.h
#include sparse_format.h
+#include mmc.h
#ifndef CONFIG_FASTBOOT_GPT_NAME
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
@@ -110,3 +111,60 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer,
write_raw_image(dev_desc, info, cmd, download_buffer,
download_bytes);
}
+
+void fb_mmc_erase(const char *cmd, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+ lbaint_t blks, blks_start, blks_size, grp_size;
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ if (mmc == NULL) {
+ error(invalid mmc device\n);
no newline with error()
Will remove
+ fastboot_fail(invalid mmc device);
+ return;
+ }
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev(mmc, CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc-type == DEV_TYPE_UNKNOWN) {
+ error(invalid mmc device\n);
no newline with error()
Will remove
+ fastboot_fail(invalid mmc device);
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, info);
+ if (ret) {
+ error(cannot find partition: '%s'\n, cmd);
no newline with error()
Will remove
+ fastboot_fail(cannot find partition);
+ return;
+ }
+
+ puts(Erasing partition\n);
+
+ /* Align blocks to erase group size to avoid erasing other
partitions */
+ grp_size = mmc-erase_grp_size;
+ blks_start = (info.start + grp_size - 1) ~(grp_size - 1);
+ if (info.size = grp_size)
+ blks_size = (info.size - (blks_start - info.start))
+ (~(grp_size - 1));
+ else
+ blks_size = 0;
Is this logic correct??? Isn't the erase_grp_size in bytes? and the
info.start info.size in LBA's?
Yes, the math will take care of it. Ref: mmc_berase()
+
+ printf(Erasing blocks LBAFU to LBAFU due to alignment\n,
+ blks_start, blks_start + blks_size);
+
+ blks = dev_desc-block_erase(dev_desc-dev, blks_start, blks_size);
+ if (blks != blks_size) {
+ error(failed erasing from device %d\n, dev_desc-dev);
no newline with error()
Will remove
+ fastboot_fail(failed erasing from device);
+ return;
+ }
+
+ printf( erased LBAFU bytes from '%s'\n,
+ blks_size * info.blksz, cmd);
+ fastboot_okay();
+}
diff --git a/drivers/usb/gadget/f_fastboot.c
b/drivers/usb/gadget/f_fastboot.c
index f7d84bf..a8d8205 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -535,6 +535,26 @@ static void cb_oem(struct usb_ep *ep, struct
usb_request *req)
}
}
+static void cb_erase(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req-buf;
+ char response[RESPONSE_LEN];
+
+ strsep(cmd, :);
+ if (!cmd) {
+ error(missing partition name\n);
no newline with error()
Will remove
+ fastboot_tx_write_str(FAILmissing partition name);
+ return;
+ }
+
+ strcpy(response, FAILno flash device defined);
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_erase(cmd, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
@@ -566,6 +586,9 @@ static const struct cmd_dispatch_info
cmd_dispatch_info[] = {
{
.cmd = oem,
.cb = cb_oem,
+ }, {
+ .cmd = erase,
+ .cb = cb_erase,
},
};
diff --git a/include/fb_mmc.h b/include/fb_mmc.h
index 1ad1d13..402ba9b 100644
--- a/include/fb_mmc.h
+++
[U-Boot] [PATCH][v4] crypto/fsl - Add progressive hashing support using hardware acceleration.
Currently only normal hashing is supported using hardware acceleration.
Added support for progressive hashing using hardware.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v4:
Add CONFIG_SHA256, CONFIG_SHA256, CONFIG_SHA_PROG_HW_ACCEL, CONFIG_SHA_HW_ACCEL
to Kconfig.
Modify README for these configs descriptions.
Changes in v3:
Remove duplication of code and create function gen_hash_type.
Modify MAX_SG to MAX_SG_32
Changes in v2:
Merge to common functions for SHA1 and SHA256.
Replace malloc and memset with calloc.
Remove cast conversions for void* pointers.
Replace hardcoded errors with Macros.
Corrected comments.
Kconfig | 4 +-
README| 23 +--
common/hash.c | 10 +++
drivers/crypto/fsl/fsl_hash.c | 138 +-
drivers/crypto/fsl/fsl_hash.h | 34 +++
include/fsl_sec.h | 26
include/hw_sha.h | 41 -
lib/Kconfig | 38
8 files changed, 307 insertions(+), 7 deletions(-)
create mode 100644 drivers/crypto/fsl/fsl_hash.h
diff --git a/Kconfig b/Kconfig
index fed488f..c4afb82 100644
--- a/Kconfig
+++ b/Kconfig
@@ -121,7 +121,9 @@ config FIT_SIGNATURE
select RSA
help
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will be using it.
See doc/uImage.FIT/signature.txt for more details.
config SYS_EXTRA_OPTIONS
diff --git a/README b/README
index cac7978..7a3f1e7 100644
--- a/README
+++ b/README
@@ -3149,8 +3149,21 @@ CBFS (Coreboot Filesystem) support
Enable the hash verify command (hash -v). This adds to code
size a little.
- CONFIG_SHA1 - support SHA1 hashing
- CONFIG_SHA256 - support SHA256 hashing
+ CONFIG_SHA1 - This option enables support of hashing using SHA1
+ algorithm. The hash is calculated in software.
+ CONFIG_SHA256 - This option enables support of hashing using
+ SHA256 algorithm. The hash is calculated in software.
+ CONFIG_SHA_HW_ACCEL - This option enables calculation of hash
+ using SHA1/SHA256 algorithm in hardware. The files using
+ hash_lookup_algo function would get pointer to structure having
+ hardware accelerated SHA support. The hash command would
+ automatically use hardware support if this option is enabled.
+ CONFIG_SHA_PROG_HW_ACCEL - This option enables SHA1 or SHA256
+ progressive hashing using hardware acceleration. The
+ hash_progressive_lookup_algo function would return pointer to
+ structure having support for progressive hashing in hardware.
+ FIT_SIGNATURE which uses this function would automatically
+ use hardware support if this option is enabled.
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
@@ -3444,8 +3457,10 @@ FIT uImage format:
CONFIG_FIT_SIGNATURE
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA. See
- doc/uImage.FIT/signature.txt for more details.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will be using
it.
+ See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with required
signature check the legacy image format is default
diff --git a/common/hash.c b/common/hash.c
index d154d02..9e9f84b 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = {
SHA1_SUM_LEN,
hw_sha1,
CHUNKSZ_SHA1,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
}, {
sha256,
SHA256_SUM_LEN,
hw_sha256,
CHUNKSZ_SHA256,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
},
#endif
#ifdef CONFIG_SHA1
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index d77f257..c298404 100644
--- a/drivers/crypto/fsl/fsl_hash.c
+++
[U-Boot] [PATCH] crypto/fsl: Make function names consistent for blob encapsulation/decapsulation.
This patch does the following:
1. The function names for encapsulation and decapsulation
were inconsistent in freescale's implementation and cmd_blob file.
This patch corrects the issue.
2. The function prototype is also modified to change the length parameter
from u8 to u32 to allow encapsulation and decapsulation of larger images.
3. Modified the description of km parameter in the command usage for better
readability.
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
Reviewed-by: Ruchika Gupta ruchika.gu...@freescale.com
---
common/cmd_blob.c | 18 ++
drivers/crypto/fsl/fsl_blob.c | 4 ++--
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/common/cmd_blob.c b/common/cmd_blob.c
index 82ecaf0..dd6f612 100644
--- a/common/cmd_blob.c
+++ b/common/cmd_blob.c
@@ -90,17 +90,19 @@ static char blob_help_text[] =
enc src dst len km - Encapsulate and create blob of data\n
$len bytes long at address $src and\n
store the result at address $dst.\n
- $km is the 16 byte key modifier\n
- is also required for generation/use as\n
- key for cryptographic operation. Key\n
- modifier should be 16 byte long.\n
+ $km is the address where the key \n
+ modifier is stored.\n
+ The modifier is required for generation\n
+ /use as key for cryptographic operation.\n
+ Key modifier should be 16 byte long.\n
blob dec src dst len km - Decapsulate the blob of data at address\n
$src and store result of $len byte at\n
addr $dst.\n
- $km is the 16 byte key modifier\n
- is also required for generation/use as\n
- key for cryptographic operation. Key\n
- modifier should be 16 byte long.\n;
+ $km is the address where the key \n
+ modifier is stored.\n
+ The modifier is required for generation\n
+ /use as key for cryptographic operation.\n
+ Key modifier should be 16 byte long.\n
U_BOOT_CMD(
blob, 6, 1, do_blob,
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c
index bc01075..9923bcb 100644
--- a/drivers/crypto/fsl/fsl_blob.c
+++ b/drivers/crypto/fsl/fsl_blob.c
@@ -11,7 +11,7 @@
#include desc.h
#include jr.h
-int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
{
int ret, i = 0;
u32 *desc;
@@ -36,7 +36,7 @@ int blob_decrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
return ret;
}
-int blob_encrypt(u8 *key_mod, u8 *src, u8 *dst, u8 len)
+int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len)
{
int ret, i = 0;
u32 *desc;
--
1.8.1.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v5] crypto/fsl - Add progressive hashing support using hardware acceleration.
Currently only normal hashing is supported using hardware acceleration.
Added support for progressive hashing using hardware.
Signed-off-by: Ruchika Gupta ruchika.gu...@freescale.com
Signed-off-by: Gaurav Rana gaurav.r...@freescale.com
CC: Simon Glass s...@chromium.org
---
Changes in v5:
Modify description for CONFIG_SHA256, CONFIG_SHA256.
Changes in v4:
Add CONFIG_SHA256, CONFIG_SHA256, CONFIG_SHA_PROG_HW_ACCEL, CONFIG_SHA_HW_ACCEL
to Kconfig.
Modify README for these configs descriptions.
Changes in v3:
Remove duplication of code and create function gen_hash_type.
Modify MAX_SG to MAX_SG_32
Changes in v2:
Merge to common functions for SHA1 and SHA256.
Replace malloc and memset with calloc.
Remove cast conversions for void* pointers.
Replace hardcoded errors with Macros.
Corrected comments.
Kconfig | 4 +-
README| 23 +--
common/hash.c | 10 +++
drivers/crypto/fsl/fsl_hash.c | 138 +-
drivers/crypto/fsl/fsl_hash.h | 34 +++
include/fsl_sec.h | 26
include/hw_sha.h | 41 -
lib/Kconfig | 38
8 files changed, 307 insertions(+), 7 deletions(-)
create mode 100644 drivers/crypto/fsl/fsl_hash.h
diff --git a/Kconfig b/Kconfig
index fed488f..c4afb82 100644
--- a/Kconfig
+++ b/Kconfig
@@ -121,7 +121,9 @@ config FIT_SIGNATURE
select RSA
help
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will be using it.
See doc/uImage.FIT/signature.txt for more details.
config SYS_EXTRA_OPTIONS
diff --git a/README b/README
index cac7978..7a3f1e7 100644
--- a/README
+++ b/README
@@ -3149,8 +3149,21 @@ CBFS (Coreboot Filesystem) support
Enable the hash verify command (hash -v). This adds to code
size a little.
- CONFIG_SHA1 - support SHA1 hashing
- CONFIG_SHA256 - support SHA256 hashing
+ CONFIG_SHA1 - This option enables support of hashing using SHA1
+ algorithm. The hash is calculated in software.
+ CONFIG_SHA256 - This option enables support of hashing using
+ SHA256 algorithm. The hash is calculated in software.
+ CONFIG_SHA_HW_ACCEL - This option enables calculation of hash
+ using SHA1/SHA256 algorithm in hardware. The files using
+ hash_lookup_algo function would get pointer to structure having
+ hardware accelerated SHA support. The hash command would
+ automatically use hardware support if this option is enabled.
+ CONFIG_SHA_PROG_HW_ACCEL - This option enables SHA1 or SHA256
+ progressive hashing using hardware acceleration. The
+ hash_progressive_lookup_algo function would return pointer to
+ structure having support for progressive hashing in hardware.
+ FIT_SIGNATURE which uses this function would automatically
+ use hardware support if this option is enabled.
Note: There is also a sha1sum command, which should perhaps
be deprecated in favour of 'hash sha1'.
@@ -3444,8 +3457,10 @@ FIT uImage format:
CONFIG_FIT_SIGNATURE
This option enables signature verification of FIT uImages,
- using a hash signed and verified using RSA. See
- doc/uImage.FIT/signature.txt for more details.
+ using a hash signed and verified using RSA. If
+ CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive
+ hashing is available using hardware, RSA library will be using
it.
+ See doc/uImage.FIT/signature.txt for more details.
WARNING: When relying on signed FIT images with required
signature check the legacy image format is default
diff --git a/common/hash.c b/common/hash.c
index d154d02..9e9f84b 100644
--- a/common/hash.c
+++ b/common/hash.c
@@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = {
SHA1_SUM_LEN,
hw_sha1,
CHUNKSZ_SHA1,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
}, {
sha256,
SHA256_SUM_LEN,
hw_sha256,
CHUNKSZ_SHA256,
+#ifdef CONFIG_SHA_PROG_HW_ACCEL
+ hw_sha_init,
+ hw_sha_update,
+ hw_sha_finish,
+#endif
},
#endif
#ifdef CONFIG_SHA1
diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c
index
Re: [U-Boot] [PATCH v1 1/1] usb: gadget: fastboot: Add fastboot erase
Hi Rob,
On 12 February 2015 at 14:35, Rob Herring robherri...@gmail.com wrote:
On Tue, Feb 10, 2015 at 2:49 AM, Dileep Katta dileep.ka...@linaro.org wrote:
Adds the fastboot erase functionality, to erase a partition
specified by name. The erase is performed based on erase group size,
to avoid erasing other partitions. The start address and the size
is aligned to the erase group size for this.
Currently only supports erasing from eMMC.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
Note: The changes are on top of oem command support added by r...@kernel.org
common/fb_mmc.c | 58
+
drivers/usb/gadget/f_fastboot.c | 23
include/fb_mmc.h| 1 +
3 files changed, 82 insertions(+)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6ea3938..3911989 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -10,6 +10,7 @@
#include part.h
#include aboot.h
#include sparse_format.h
+#include mmc.h
#ifndef CONFIG_FASTBOOT_GPT_NAME
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
@@ -110,3 +111,60 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer,
write_raw_image(dev_desc, info, cmd, download_buffer,
download_bytes);
}
+
+void fb_mmc_erase(const char *cmd, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+ lbaint_t blks, blks_start, blks_size, grp_size;
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ if (mmc == NULL) {
+ error(invalid mmc device\n);
+ fastboot_fail(invalid mmc device);
Perhaps fastboot_fail should also call error().
There is error() before every fastboot_fail(). You mean to move
error() inside fastboot_fail()? If yes, I will do it.
+ return;
+ }
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev(mmc, CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc-type == DEV_TYPE_UNKNOWN) {
+ error(invalid mmc device\n);
+ fastboot_fail(invalid mmc device);
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, info);
+ if (ret) {
+ error(cannot find partition: '%s'\n, cmd);
+ fastboot_fail(cannot find partition);
+ return;
+ }
+
+ puts(Erasing partition\n);
This can probably be dropped since you have a print below.
Will remove.
+
+ /* Align blocks to erase group size to avoid erasing other
partitions */
The partitioning could should probably enforce optimal alignment, but
I guess that's a separate patch.
Fine. Will do it as a separate patch.
+ grp_size = mmc-erase_grp_size;
+ blks_start = (info.start + grp_size - 1) ~(grp_size - 1);
+ if (info.size = grp_size)
+ blks_size = (info.size - (blks_start - info.start))
+ (~(grp_size - 1));
+ else
+ blks_size = 0;
+
+ printf(Erasing blocks LBAFU to LBAFU due to alignment\n,
+ blks_start, blks_start + blks_size);
+
+ blks = dev_desc-block_erase(dev_desc-dev, blks_start, blks_size);
+ if (blks != blks_size) {
+ error(failed erasing from device %d\n, dev_desc-dev);
+ fastboot_fail(failed erasing from device);
+ return;
+ }
+
+ printf( erased LBAFU bytes from '%s'\n,
+ blks_size * info.blksz, cmd);
+ fastboot_okay();
+}
diff --git a/drivers/usb/gadget/f_fastboot.c
b/drivers/usb/gadget/f_fastboot.c
index f7d84bf..a8d8205 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -535,6 +535,26 @@ static void cb_oem(struct usb_ep *ep, struct
usb_request *req)
}
}
+static void cb_erase(struct usb_ep *ep, struct usb_request *req)
This should be conditional on CONFIG_FASTBOOT_FLASH
Will make it conditional as in cb_oem().
+{
+ char *cmd = req-buf;
+ char response[RESPONSE_LEN];
+
+ strsep(cmd, :);
+ if (!cmd) {
+ error(missing partition name\n);
+ fastboot_tx_write_str(FAILmissing partition name);
+ return;
+ }
+
+ strcpy(response, FAILno flash device defined);
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_erase(cmd, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
@@ -566,6 +586,9 @@ static const struct cmd_dispatch_info
cmd_dispatch_info[] = {
{
.cmd = oem,
.cb = cb_oem,
+ }, {
+ .cmd = erase,
+ .cb =
[U-Boot] [PATCH] Documentation: gpio: fix bindings document
[ imported from Linux Kernel, commit 74981fb81d83 ] Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Acked-by: Laurent Pinchart laurent.pinch...@ideasonboard.com Signed-off-by: Linus Walleij linus.wall...@linaro.org --- doc/device-tree-bindings/gpio/gpio.txt | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/doc/device-tree-bindings/gpio/gpio.txt b/doc/device-tree-bindings/gpio/gpio.txt index b9bd1d6..f7a158d 100644 --- a/doc/device-tree-bindings/gpio/gpio.txt +++ b/doc/device-tree-bindings/gpio/gpio.txt @@ -69,7 +69,8 @@ GPIO pin number, and GPIO flags as accepted by the qe_pio_e gpio-controller. -- A gpio-specifier should contain a flag indicating the GPIO polarity; active- -high or active-low. If it does, the follow best practices should be followed: +high or active-low. If it does, the following best practices should be +followed: The gpio-specifier's polarity flag should represent the physical level at the GPIO controller that achieves (or represents, for inputs) a logically asserted @@ -147,7 +148,7 @@ contains information structures as follows: numeric-gpio-range ::= pinctrl-phandle gpio-base pinctrl-base count named-gpio-range ::= pinctrl-phandle gpio-base '0 0' - gpio-phandle : phandle to pin controller node. + pinctrl-phandle : phandle to pin controller node gpio-base : Base GPIO ID in the GPIO controller pinctrl-base : Base pinctrl pin ID in the pin controller count : The number of GPIOs/pins in this range -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 7/8] lpc32xx: add lpc32xx-spl.bin boot image target
On 12 February 2015 at 10:37, Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr wrote: Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr --- Changes in v2: - move boot image generation to mkimage framework common/image.c | 1 + include/image.h | 1 + scripts/Makefile.spl | 9 +++ tools/Makefile | 1 + tools/lpc32xximage.c | 178 +++ 5 files changed, 190 insertions(+) create mode 100644 tools/lpc32xximage.c Reviewed-by: Simon Glass s...@chromium.org ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH V2 2/3] bcm2836 SoC support (used in Raspberry Pi 2 model B)
The bcm2835 and bcm2836 are essentially identical, except:
- The CPU is an ARM1176 v.s. a quad-core Cortex-A7.
- The physical address of many IO controllers has moved.
Rather than introducing a whole new bcm2836 value for $(SOC) or $(ARCH),
update the existing bcm2835 code to handle the minor differences, and
plumb it into the ARMv7 CPU architecture.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
V2: No changes.
arch/arm/cpu/armv7/Makefile | 1 +
arch/arm/cpu/armv7/bcm2835/Makefile | 13 +
arch/arm/include/asm/arch-bcm2835/gpio.h | 5 +
arch/arm/include/asm/arch-bcm2835/mbox.h | 6 +-
arch/arm/include/asm/arch-bcm2835/sdhci.h | 6 +-
arch/arm/include/asm/arch-bcm2835/timer.h | 6 +-
arch/arm/include/asm/arch-bcm2835/wdog.h | 6 +-
7 files changed, 39 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/cpu/armv7/bcm2835/Makefile
diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5651b6..7f77c729a191 100644
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -41,6 +41,7 @@ endif
obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/
obj-$(CONFIG_AT91FAMILY) += at91/
+obj-$(CONFIG_BCM2835) += bcm2835/
obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
diff --git a/arch/arm/cpu/armv7/bcm2835/Makefile
b/arch/arm/cpu/armv7/bcm2835/Makefile
new file mode 100644
index ..ed1ee4753d49
--- /dev/null
+++ b/arch/arm/cpu/armv7/bcm2835/Makefile
@@ -0,0 +1,13 @@
+#
+# (C) Copyright 2012 Stephen Warren
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+src_dir := ../../arm1176/bcm2835/
+
+obj-y :=
+obj-y += $(src_dir)/init.o
+obj-y += $(src_dir)/reset.o
+obj-y += $(src_dir)/timer.o
+obj-y += $(src_dir)/mbox.o
diff --git a/arch/arm/include/asm/arch-bcm2835/gpio.h
b/arch/arm/include/asm/arch-bcm2835/gpio.h
index db42896201b3..c8ef8f528a21 100644
--- a/arch/arm/include/asm/arch-bcm2835/gpio.h
+++ b/arch/arm/include/asm/arch-bcm2835/gpio.h
@@ -1,6 +1,7 @@
/*
* Copyright (C) 2012 Vikram Narayananan
* vikram...@gmail.com
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -8,7 +9,11 @@
#ifndef _BCM2835_GPIO_H_
#define _BCM2835_GPIO_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_GPIO_BASE 0x3f20
+#else
#define BCM2835_GPIO_BASE 0x2020
+#endif
#define BCM2835_GPIO_COUNT 54
#define BCM2835_GPIO_FSEL_MASK 0x7
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h
b/arch/arm/include/asm/arch-bcm2835/mbox.h
index 88d2ec11a7c2..c4bbacaf3c3f 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0+
*/
@@ -38,7 +38,11 @@
/* Raw mailbox HW */
+#ifdef CONFIG_BCM2836
+#define BCM2835_MBOX_PHYSADDR 0x3f00b880
+#else
#define BCM2835_MBOX_PHYSADDR 0x2000b880
+#endif
struct bcm2835_mbox_regs {
u32 read;
diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h
b/arch/arm/include/asm/arch-bcm2835/sdhci.h
index da4d5cd5a88f..2a21ccbf66ba 100644
--- a/arch/arm/include/asm/arch-bcm2835/sdhci.h
+++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -7,7 +7,11 @@
#ifndef _BCM2835_SDHCI_H_
#define _BCM2835_SDHCI_H_
+#ifdef CONFIG_BCM2836
+#define BCM2835_SDHCI_BASE 0x3f30
+#else
#define BCM2835_SDHCI_BASE 0x2030
+#endif
int bcm2835_sdhci_init(u32 regbase, u32 emmc_freq);
diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h
b/arch/arm/include/asm/arch-bcm2835/timer.h
index 2d7cfe5c56f8..fc7aec7b7c59 100644
--- a/arch/arm/include/asm/arch-bcm2835/timer.h
+++ b/arch/arm/include/asm/arch-bcm2835/timer.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -7,7 +7,11 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_TIMER_PHYSADDR 0x3f003000
+#else
#define BCM2835_TIMER_PHYSADDR 0x20003000
+#endif
struct bcm2835_timer_regs {
u32 cs;
diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h
b/arch/arm/include/asm/arch-bcm2835/wdog.h
index f369ab589c9a..beb6a0820601 100644
--- a/arch/arm/include/asm/arch-bcm2835/wdog.h
+++ b/arch/arm/include/asm/arch-bcm2835/wdog.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012 Stephen Warren
+ * (C) Copyright 2012,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -7,7 +7,11 @@
#ifndef _BCM2835_TIMER_H
#define _BCM2835_TIMER_H
+#ifdef CONFIG_BCM2836
+#define BCM2835_WDOG_PHYSADDR
Re: [U-Boot] u-boot for Snow problem
Hi Michal, On 11 February 2015 at 10:16, Michal Suchanek hramr...@gmail.com wrote: Hello, I changed the SYS_START to work around the bug in the manufacturer firmware, applied snow_defconfig, built u-boot.bin, packed it into kernel uimage, signed it, copied it to a kernel partition, bumped priority of the partition, and rebooted. Do you mean u-boot-dtb.bin? If not you won't get a device tree and it won't work. I get black screen with backlight on. So 1) is u-boot supposed to have graphics console output? If so where is that output? LCD/HDMI/what HDMI mode? The only display related option in menuconfig seems to be some SPI display bridge. Yes it should be enabled, works for me. 2) is u-boot supposed to have serial console output? If so where is that console? There is supposed to be some 'servo' connector somewhere but I did not find any information on the pinout. Yes but you can only access it on the servo pints. From Pit/Pi this is a little easier, but for snow you will need to do some very fine soldering. 3) how do I tell if u-boot is even running? I think you are doing the right things. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] arm: ls102xa: Fix interleaving issue on CCI400 slave interface S2
On silicon VER1.0, there is an interleaving issue on CCI400
slave interface S2. The workaround is to enable regulation
of outstanding read transactions for slave interface S2.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 2 ++
board/freescale/ls1021aqds/ls1021aqds.c | 7 +++
board/freescale/ls1021atwr/ls1021atwr.c | 7 +++
3 files changed, 16 insertions(+)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 4b1cd3b..1a61d4a 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -463,6 +463,8 @@ struct ccsr_ddr {
#define CCI400_SHAORD_NON_SHAREABLE0x0002
#define CCI400_DVM_MESSAGE_REQ_EN 0x0002
#define CCI400_SNOOP_REQ_EN0x0001
+#define CCI400_REGULATION_READ_EN 0x0008
+#define CCI400_INT_MAX_OUT_TRANS 0x0100
/* CCI-400 registers */
struct ccsr_cci400 {
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index b6bba6c..93df046 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -217,6 +217,13 @@ int board_early_init_f(void)
*/
out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ /*
+* To fix interleaving issue on VER1.0, regulation of
+* outstanding read transactions for slave interface S2
+* is enabled
+*/
+ out_le32(cci-slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+ out_le32(cci-slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
/* Workaround for the issue that DDR could not respond to
* barrier transaction which is generated by executing DSB/ISB
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c
b/board/freescale/ls1021atwr/ls1021atwr.c
index bd6068f..9101bd6 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -301,6 +301,13 @@ int board_early_init_f(void)
*/
out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ /*
+* To fix interleaving issue on VER1.0, regulation of
+* outstanding read transactions for slave interface S2
+* is enabled
+*/
+ out_le32(cci-slave[2].qos_ctrl, CCI400_REGULATION_READ_EN);
+ out_le32(cci-slave[2].max_ot, CCI400_INT_MAX_OUT_TRANS);
}
return 0;
--
2.1.0.27.g96db324
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[U-Boot] [PATCH 1/2] arm: ls102xa: Add silicon version detection for QDS and TWR boards
For LS102xA, some workarounds are only used in VER1.0, so silicon
version detection are added for QDS and TWR boards.
Signed-off-by: Alison Wang alison.w...@freescale.com
---
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 3 +
board/freescale/ls1021aqds/ls1021aqds.c | 69 ---
board/freescale/ls1021atwr/ls1021atwr.c | 19 +--
3 files changed, 64 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index f70d568..4b1cd3b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
#define SOC_VER_LS1021 0x11
#define SOC_VER_LS1022 0x12
+#define SOC_VER_1_00x1
+#define SOC_VER_2_00x2
+
#define CCSR_BRR_OFFSET0xe4
#define CCSR_SCRATCHRW1_OFFSET 0x200
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c
b/board/freescale/ls1021aqds/ls1021aqds.c
index 20eade4..b6bba6c 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -181,6 +181,11 @@ int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(gur-svr);
+ major = SVR_MAJ(svr);
#ifdef CONFIG_TSEC_ENET
out_be32(scfg-etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
@@ -205,19 +210,21 @@ int board_early_init_f(void)
out_le32(cci-slave[4].snoop_ctrl,
CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
- /*
-* Set CCI-400 Slave interface S1, S2 Shareable Override Register
-* All transactions are treated as non-shareable
-*/
- out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
- out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
-
- /* Workaround for the issue that DDR could not respond to
-* barrier transaction which is generated by executing DSB/ISB
-* instruction. Set CCI-400 control override register to
-* terminate the barrier transaction. After DDR is initialized,
-* allow barrier transaction to DDR again */
- out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+ if (major == SOC_VER_1_0) {
+ /*
+* Set CCI-400 Slave interface S1, S2 Shareable Override
+* Register All transactions are treated as non-shareable
+*/
+ out_le32(cci-slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+ out_le32(cci-slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
+ /* Workaround for the issue that DDR could not respond to
+* barrier transaction which is generated by executing DSB/ISB
+* instruction. Set CCI-400 control override register to
+* terminate the barrier transaction. After DDR is initialized,
+* allow barrier transaction to DDR again */
+ out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+ }
#if defined(CONFIG_DEEP_SLEEP)
if (is_warm_boot())
@@ -231,9 +238,10 @@ int board_early_init_f(void)
void board_init_f(ulong dummy)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
#ifdef CONFIG_NAND_BOOT
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
@@ -267,7 +275,12 @@ void board_init_f(ulong dummy)
#ifdef CONFIG_SPL_I2C_SUPPORT
i2c_init_all();
#endif
- out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
+
+ svr = in_be32(gur-svr);
+ major = SVR_MAJ(svr);
+
+ if (major == SOC_VER_1_0)
+ out_le32(cci-ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
dram_init();
@@ -529,10 +542,17 @@ struct smmu_stream_id dev_stream_id[] = {
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ unsigned int svr, major;
+
+ svr = in_be32(gur-svr);
+ major = SVR_MAJ(svr);
- /* Set CCI-400 control override register to
-* enable barrier transaction */
- out_le32(cci-ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ if (major == SOC_VER_1_0) {
+ /* Set CCI-400 control override register to
+* enable barrier transaction */
+ out_le32(cci-ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+ }
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
@@ -559,10 +579,17 @@ int board_init(void)
void board_sleep_prepare(void)
{
Re: [U-Boot] [PATCH v2 4/8] lpc32xx: add GPIO support
Hi Albert,
On 12 February 2015 at 10:37, Albert ARIBAUD (3ADEV)
albert.arib...@3adev.fr wrote:
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 268
+++
4 files changed, 317 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..559894a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..861975e
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,268 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * We only support driver model
+ */
+#ifndef CONFIG_DM_GPIO
+#error Please enable Driver Model GPIO in your target configuration.
+#endif
Minor note - if you base this on dm/master you can use Kconfig
'depends on DM' in this driver's Kconfig bit.
(pull request to mainline coming soon)
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+#include malloc.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ */
+
+#define LPC32XX_GPIOS 128
+
+static struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
Normally this would go in a
struct lpc32xx_priv
in the driver.
+
+/**
+ * We have 4 GPIO ports of 32 bits each
+ */
+
+#define MAX_GPIO 128
+
+#define GPIO_TO_PORT(gpio) ((gpio / 32) 3)
+#define
Re: [U-Boot] [RFC PATCH v3 01/14] dm: core: Allow seq numbers to be resolved before probe
Hi Joe, On 10 February 2015 at 23:08, Joe Hershberger joe.hershber...@gmail.com wrote: Hi Simon, On Tue, Feb 10, 2015 at 10:39 PM, Simon Glass s...@chromium.org wrote: Hi Joe, On 10 February 2015 at 18:30, Joe Hershberger joe.hershber...@ni.com wrote: Before this patch, if the sequence numbers were resolved before probe, this code would insist on defining new non-conflicting-with-itself seq numbers. Now any non -1 seq number is accepted as already resolved. Can you explain what problem this solves? At present, when probing a device, -seq must be -1 (sort-of by definition since it doesn't exist as an active device in the uclass). Please look at eth_post_bind() in patch 07/14. The Ethernet devices need to write their hardware addresses to the registers in bind (since it needs to happen regardless of the device being used so that Linux will see the MAC address). As such, the sequence number is needed to look up the ethaddr. In order to avoid probing all the devices to get the seq number resolved, I resolve it in post_bind to avoid the rest of the overhead (thus no longer probing in post_bind, which was one of the issues previously). Then when probe comes along, the seq is already resolved. That's why this patch is needed. OK I see. This is a bit messy. If the MAC address assignment is part of the bind step then it shouldn't need the seq number. I can think of some poor ways to do this but a nice way is not obvious! One option would be probe all the Ethernet devices on startup. If probe() only set up the hardware (including MAC address) then that might work. It would be fairly fast since it wouldn't involve starting up the link, etc. I suspect you are worried about a lot of Ethernet devices sitting around probed by unused. I'm not sure if that matters though. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-sh/rmolbile
Dear Tom Rini.
Please pull u-boot-sh rmobile branch.
The following changes since commit a4fb5df214c7e8d5bc949c1068d92252f105427a:
Merge branch 'microblaze' of git://git.denx.de/u-boot-microblaze
(2015-02-09 11:44:46 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-sh.git rmobile
for you to fetch changes up to 79bf043e371cfb7bed276e3ce795f066a364f5ff:
ARM: rmobile: silk: Remove initialization of ACTLR.SMP (2015-02-13
13:14:56 +0900)
Nobuhiro Iwamatsu (2):
arm: rmobile: r8a7794: Enable SMP mode of Auxiliary Control Register
ARM: rmobile: silk: Remove initialization of ACTLR.SMP
Vladimir Barinov (2):
arm: rmobile: Add SILK board support
arm: rmobile: Add missed header file for Silk board
arch/arm/cpu/armv7/rmobile/Kconfig | 6 +-
arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | 12 +-
board/renesas/silk/Kconfig | 12 ++
board/renesas/silk/MAINTAINERS | 6 +
board/renesas/silk/Makefile | 10 ++
board/renesas/silk/qos.c| 951
+++
board/renesas/silk/qos.h| 13 +++
board/renesas/silk/silk.c | 163
+++
configs/silk_defconfig | 3 +
include/configs/silk.h | 117 +++
10 files changed, 1291 insertions(+), 2 deletions(-)
create mode 100644 board/renesas/silk/Kconfig
create mode 100644 board/renesas/silk/MAINTAINERS
create mode 100644 board/renesas/silk/Makefile
create mode 100644 board/renesas/silk/qos.c
create mode 100644 board/renesas/silk/qos.h
create mode 100644 board/renesas/silk/silk.c
create mode 100644 configs/silk_defconfig
create mode 100644 include/configs/silk.h
--
Nobuhiro Iwamatsu
iwamatsu at {nigauri.org / debian.org}
GPG ID: 40AD1FA6
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Re: [U-Boot] [RFC PATCH v2 5/8] net: Add basic driver model support to Ethernet stack
Hi Joe,
On 10 February 2015 at 23:25, Joe Hershberger joe.hershber...@gmail.com wrote:
On Fri, Feb 6, 2015 at 7:25 PM, Simon Glass s...@chromium.org wrote:
Hi Joe,
On 2 February 2015 at 17:38, Joe Hershberger joe.hershber...@ni.com
wrote:
First just add support for MAC drivers.
Signed-off-by: Joe Hershberger joe.hershber...@ni.com
---
Changes in v2:
-Updated comments
-Removed extra parentheses
-Changed eth_uclass_priv local var names to be uc_priv
-Update error codes
-Cause an invalid name to fail binding
-Rebase on top of dm/master
-Stop maintaining our own index and use DM seq now that it works for our
needs
-Move the hwaddr to platdata so that its memory is allocated at bind
when we need it
-Prevent device from being probed before used by a command (i.e. before
eth_init()).
common/board_r.c | 4 +-
common/cmd_bdinfo.c| 2 +
include/dm/uclass-id.h | 1 +
include/net.h | 24
net/eth.c | 319
-
5 files changed, 346 insertions(+), 4 deletions(-)
[snip]
diff --git a/net/eth.c b/net/eth.c
index c02548c..1b5a169 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -72,6 +72,320 @@ static int eth_mac_skip(int index)
return ((skip_state = getenv(enetvar)) != NULL);
}
+static void eth_current_changed(void);
+
+#ifdef CONFIG_DM_ETH
+#include dm.h
+#include dm/device-internal.h
These should go at the top of the file - should be OK to always
include them (i.e. no #ifdef)
OK... Moved them.
+
+struct eth_device_priv {
+ int state;
+ void *priv;
+};
+
+struct eth_uclass_priv {
+ struct udevice *current;
+};
+
+static void eth_set_current_to_next(void)
+{
+ struct uclass *uc;
+ struct eth_uclass_priv *uc_priv;
+
+ uclass_get(UCLASS_ETH, uc);
This can actually return an error, although I agree there is little
point in handling it. So I suppose this is OK.
I think this should be a given.
+ uc_priv = uc-priv;
+ uclass_next_device(uc_priv-current);
+ if (!uc_priv-current)
+ uclass_first_device(UCLASS_ETH, uc_priv-current);
+}
+
+struct udevice *eth_get_dev(void)
+{
+ struct uclass *uc;
blank line here
OK on all of these.
+ uclass_get(UCLASS_ETH, uc);
+
+ struct eth_uclass_priv *uc_priv = uc-priv;
+ return uc_priv-current;
+}
+
+static void eth_set_dev(struct udevice *dev)
+{
+ struct uclass *uc;
blank line here
+ uclass_get(UCLASS_ETH, uc);
+
+ struct eth_uclass_priv *uc_priv = uc-priv;
+ uc_priv-current = dev;
+}
+
+unsigned char *eth_get_ethaddr(void)
+{
+ struct eth_pdata *pdata;
blank line here
+ if (eth_get_dev()) {
+ pdata = eth_get_dev()-platdata;
+ if (pdata)
+ return pdata-enetaddr;
+ }
+ return NULL;
+}
+
+/* Set active state */
+int eth_init_state_only(bd_t *bis)
+{
+ struct eth_device_priv *priv;
blank line here
+ if (eth_get_dev()) {
+ priv = eth_get_dev()-uclass_priv;
+ if (priv)
+ priv-state = ETH_STATE_ACTIVE;
+ }
+
+ return 0;
+}
+/* Set passive state */
+void eth_halt_state_only(void)
+{
+ struct eth_device_priv *priv;
blank line here
+ if (eth_get_dev()) {
+ priv = eth_get_dev()-uclass_priv;
+ if (priv)
+ priv-state = ETH_STATE_PASSIVE;
+ }
+}
+
+int eth_get_dev_index(void)
+{
+ if (eth_get_dev())
+ return eth_get_dev()-seq;
+ return -1;
+}
+
+int eth_init(bd_t *bis)
+{
+ struct udevice *current, *old_current, *dev;
+ struct uclass *uc;
+
+ current = eth_get_dev();
+ if (!current) {
+ puts(No ethernet found.\n);
+ return -1;
+ }
+ device_probe(current);
Check error
OK.
+
+ /* Sync environment with network devices */
+ uclass_get(UCLASS_ETH, uc);
+ uclass_foreach_dev(dev, uc) {
+ uchar env_enetaddr[6];
+
+ if (eth_getenv_enetaddr_by_index(eth, dev-seq,
+env_enetaddr)) {
+ struct eth_pdata *pdata = dev-platdata;
blank line
Do all devices have the same platdata by design? What if a particular
device wants its own?
That's a good question. I imagine some devices may have something unique,
but I would expect they would read that data into the priv data that they
define. How do other subsystems handle platform data for unique devices?
There isn't great support for it. Typically the device has its own
platform data. For buses there is per-child platform data,
[U-Boot] [PATCH V2 3/3] rpi: add support for Raspberry Pi 2 model B
USB doesn't seem to work yet; the controller detects the on-board Hub/
Ethernet device but can't read the descriptors from it. I haven't
investigated yet.
Signed-off-by: Stephen Warren swar...@wwwdotorg.org
---
V2: Implement new board_rev decoding scheme, to avoid hard-coding the
board revision onthe RPi 2.
arch/arm/Kconfig | 5 +
arch/arm/include/asm/arch-bcm2835/mbox.h | 4 +
board/raspberrypi/rpi/rpi.c | 28 -
board/raspberrypi/rpi_2/Kconfig | 15 +++
board/raspberrypi/rpi_2/MAINTAINERS | 6 +
board/raspberrypi/rpi_2/Makefile | 7 ++
configs/rpi_2_defconfig | 2 +
include/configs/rpi-common.h | 193 +++
include/configs/rpi.h| 175 +---
include/configs/rpi_2.h | 15 +++
10 files changed, 275 insertions(+), 175 deletions(-)
create mode 100644 board/raspberrypi/rpi_2/Kconfig
create mode 100644 board/raspberrypi/rpi_2/MAINTAINERS
create mode 100644 board/raspberrypi/rpi_2/Makefile
create mode 100644 configs/rpi_2_defconfig
create mode 100644 include/configs/rpi-common.h
create mode 100644 include/configs/rpi_2.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 47806f85dafa..b916eb0dd44c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -413,6 +413,10 @@ config TARGET_RPI
bool Support rpi
select CPU_ARM1176
+config TARGET_RPI_2
+ bool Support rpi_2
+ select CPU_V7
+
config TARGET_TNETV107X_EVM
bool Support tnetv107x_evm
select CPU_ARM1176
@@ -958,6 +962,7 @@ source board/phytec/pcm051/Kconfig
source board/ppcag/bg0900/Kconfig
source board/pxa255_idp/Kconfig
source board/raspberrypi/rpi/Kconfig
+source board/raspberrypi/rpi_2/Kconfig
source board/ronetix/pm9261/Kconfig
source board/ronetix/pm9263/Kconfig
source board/ronetix/pm9g45/Kconfig
diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h
b/arch/arm/include/asm/arch-bcm2835/mbox.h
index c4bbacaf3c3f..04bf480a5493 100644
--- a/arch/arm/include/asm/arch-bcm2835/mbox.h
+++ b/arch/arm/include/asm/arch-bcm2835/mbox.h
@@ -125,6 +125,9 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002
+#ifdef CONFIG_BCM2836
+#define BCM2836_BOARD_REV_2_B 0x4
+#else
/*
* 0x2..0xf from:
*
http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/
@@ -145,6 +148,7 @@ struct bcm2835_mbox_tag_hdr {
#define BCM2835_BOARD_REV_B_PLUS 0x10
#define BCM2835_BOARD_REV_CM 0x11
#define BCM2835_BOARD_REV_A_PLUS 0x12
+#endif
struct bcm2835_mbox_tag_get_board_rev {
struct bcm2835_mbox_tag_hdr tag_hdr;
diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
index 2185b1bd029a..5ea96935fbde 100644
--- a/board/raspberrypi/rpi/rpi.c
+++ b/board/raspberrypi/rpi/rpi.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2012-2013 Stephen Warren
+ * (C) Copyright 2012-2013,2015 Stephen Warren
*
* SPDX-License-Identifier:GPL-2.0
*/
@@ -28,7 +28,11 @@ U_BOOT_DEVICE(bcm2835_gpios) = {
};
static const struct pl01x_serial_platdata serial_platdata = {
+#ifdef CONFIG_BCM2836
+ .base = 0x3f201000,
+#else
.base = 0x20201000,
+#endif
.type = TYPE_PL011,
.clock = 300,
};
@@ -76,9 +80,20 @@ static const struct {
} models[] = {
[0] = {
Unknown model,
+#ifdef CONFIG_BCM2836
+ bcm2836-rpi-other.dtb,
+#else
bcm2835-rpi-other.dtb,
+#endif
false,
},
+#ifdef CONFIG_BCM2836
+ [BCM2836_BOARD_REV_2_B] = {
+ 2 Model B,
+ bcm2836-rpi-2-b.dtb,
+ true,
+ },
+#else
[BCM2835_BOARD_REV_B_I2C0_2] = {
Model B (no P5),
bcm2835-rpi-b-i2c0.dtb,
@@ -149,6 +164,7 @@ static const struct {
bcm2835-rpi-a-plus.dtb,
false,
},
+#endif
};
u32 rpi_board_rev = 0;
@@ -256,7 +272,15 @@ static void get_board_rev(void)
return;
}
+ /*
+* For details of old-vs-new scheme, see:
+* https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py
+* http://www.raspberrypi.org/forums/viewtopic.php?f=63t=99293p=690282
+* (a few posts down)
+*/
rpi_board_rev = msg-get_board_rev.body.resp.rev;
+ if (rpi_board_rev 0x80)
+ rpi_board_rev = (rpi_board_rev 4) 0xff;
if (rpi_board_rev = ARRAY_SIZE(models)) {
printf(RPI: Board rev %u outside known range\n,
rpi_board_rev);
@@ -268,7 +292,7 @@ static void get_board_rev(void)
}
name = models[rpi_board_rev].name;
- printf(RPI model: %s\n, name);
+ printf(RPI %s\n, name);
}
int board_init(void)
diff --git a/board/raspberrypi/rpi_2/Kconfig
[U-Boot] [PATCH V2 1/3] bcm2835/rpi: add SPDX license tags for some files
Signed-off-by: Stephen Warren swar...@wwwdotorg.org --- V2: No changes. arch/arm/cpu/arm1176/bcm2835/Makefile | 12 ++-- arch/arm/include/asm/arch-bcm2835/sdhci.h | 12 +--- arch/arm/include/asm/arch-bcm2835/timer.h | 12 +--- arch/arm/include/asm/arch-bcm2835/wdog.h | 12 +--- board/raspberrypi/rpi/Makefile| 12 ++-- board/raspberrypi/rpi/rpi.c | 12 +--- include/configs/rpi.h | 12 +--- 7 files changed, 9 insertions(+), 75 deletions(-) diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 0ad36906dfc5..7e5dbe1fdeaf 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := lowlevel_init.o diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h index a4f867b2e9a4..da4d5cd5a88f 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _BCM2835_SDHCI_H_ diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h index c2001b6f932a..2d7cfe5c56f8 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/include/asm/arch-bcm2835/timer.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _BCM2835_TIMER_H diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h index 303a65f32e08..f369ab589c9a 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/include/asm/arch-bcm2835/wdog.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier:GPL-2.0 */ #ifndef _BCM2835_TIMER_H diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile index c53c92b1ddb7..4ce2c983b382 100644 --- a/board/raspberrypi/rpi/Makefile +++ b/board/raspberrypi/rpi/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := rpi.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
[U-Boot] MPC8541 / MPC8555E: DDR_SDRAM_CLK_CNLT[SS_EN] handling
Hello, I am curious about the setting of the SS_EN bit in the DDR_SDRAM_CLK_CNLT register: Source synchronous enable. This bit field must be set during initialization. See Section 9.6.1, “DDR SDRAM Initialization Sequence,” for details. 0 - Reserved 1 - The address and command are sent to the DDR SDRAMs source synchronously. The MPC8555E reference manual and this app note are pretty clear that this bit should be set: http://cache.freescale.com/files/32bit/doc/app_note/AN2805.pdf (page 17) set_ddr_sdram_clk_cntl() in u-boot/drivers/ddr/fsl/ctrl_regs.c has this: clk_adjust = popts-clk_adjust; ddr-ddr_sdram_clk_cntl = (clk_adjust 0xF) 23; There is no accounting for the SS_EN bit on 8541/8555E. I would have expected to see an #ifdef for the MPC8555 that sets the SS_EN bit. I know 8541 has been around forever and is working fine. I am just trying to find some back ground information on this setting. Searching the old mailing lists did not turn up anything useful. Any insight is appreciated. Cheers, Curt ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] arc: introduce U-Boot port for ARCv2 ISA
On Tue, 2015-02-10 at 13:38 +0300, Alexey Brodkin wrote: ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary incompatible with ISAv1 (AKA ARCompact). Significant difference between ISAv2 and v1 is implementation of interrupt vector table. In v1 it is implemented in the same way as on many other architectures - as a special location where user may put whether code executed in place (if machine word of space is enough) or jump to a full-scale interrupt handler. In v2 interrupt table is just an array of adresses of real interrupt handlers. That requires a separate section for IVT that is not encoded as code by assembler. This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU) As a part of ARC HS38 new version of MMU (v4) was introduced. Also this change adds AXS131 board which is the same DW ARC SDP base board but with ARC HS38 CPU tile. Signed-off-by: Alexey Brodkin abrod...@synopsys.com --- arch/arc/Kconfig | 59 ﯯ뻻 arch/arc/config.mk | 12 寧���珷⦻狽뼱ꤞ縩廯귈罪뜿犛뽪뜯 Applied -Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v1 1/3] fastboot: OUT transaction length must be aligned to wMaxPacketSize
OUT transactions must be aligned to wMaxPacketSize for each transfer,
or else transfer will not complete successfully. This patch modifies
rx_bytes_expected to return a transfer length that is aligned to
wMaxPacketSize.
Note that the value of ep-desc-wMaxPacketSize and ep-maxpacket
may not be the same value, and it is the value of ep-desc-wMaxPacketSize
that should be used for alignment.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
drivers/usb/gadget/f_fastboot.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index a8d8205..0d53a61 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -370,13 +370,20 @@ static void cb_getvar(struct usb_ep *ep, struct
usb_request *req)
fastboot_tx_write_str(response);
}
-static unsigned int rx_bytes_expected(void)
+static unsigned int rx_bytes_expected(unsigned maxpacket)
{
int rx_remain = download_size - download_bytes;
+ int rem = 0;
if (rx_remain 0)
return 0;
if (rx_remain EP_BUFFER_SIZE)
return EP_BUFFER_SIZE;
+ if (rx_remain maxpacket) {
+ rx_remain = maxpacket;
+ } else if (rx_remain % maxpacket != 0) {
+ rem = rx_remain % maxpacket;
+ rx_remain = rx_remain + (maxpacket - rem);
+ }
return rx_remain;
}
@@ -425,7 +432,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct
usb_request *req)
printf(\ndownloading of %d bytes finished\n, download_bytes);
} else {
- req-length = rx_bytes_expected();
+ req-length = rx_bytes_expected(ep-desc-wMaxPacketSize);
if (req-length ep-maxpacket)
req-length = ep-maxpacket;
}
@@ -453,7 +460,7 @@ static void cb_download(struct usb_ep *ep, struct
usb_request *req)
} else {
sprintf(response, DATA%08x, download_size);
req-complete = rx_handler_dl_image;
- req-length = rx_bytes_expected();
+ req-length = rx_bytes_expected(ep-desc-wMaxPacketSize);
if (req-length ep-maxpacket)
req-length = ep-maxpacket;
}
--
1.8.3.2
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[U-Boot] [PATCH v1 2/3] fastboot: Correct fastboot_fail and fastboot_okay strings
If the string is copied without NULL termination using strncpy(),
then strncat() on the next line, may concatenate the string after
some stale (or random) data, if the response string was not
zero-initialized.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
common/fb_mmc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 3911989..73055cc 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -23,13 +23,13 @@ static char *response_str;
void fastboot_fail(const char *s)
{
- strncpy(response_str, FAIL, 4);
+ strncpy(response_str, FAIL\0, 5);
strncat(response_str, s, RESPONSE_LEN - 4 - 1);
}
void fastboot_okay(const char *s)
{
- strncpy(response_str, OKAY, 4);
+ strncpy(response_str, OKAY\0, 5);
strncat(response_str, s, RESPONSE_LEN - 4 - 1);
}
--
1.8.3.2
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[U-Boot] [PATCH v1 3/3] usb: gadget: fastboot: Set the Serial Number for Fastboot Gadget
Configure the serial number using the serial# environment variable during the fastboot bind. This enables fastboot devices to return the serial number for the attached devices. Signed-off-by: Dileep Katta dileep.ka...@linaro.org --- drivers/usb/gadget/f_fastboot.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c index 0d53a61..d114c07 100644 --- a/drivers/usb/gadget/f_fastboot.c +++ b/drivers/usb/gadget/f_fastboot.c @@ -136,6 +136,7 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) int id; struct usb_gadget *gadget = c-cdev-gadget; struct f_fastboot *f_fb = func_to_fastboot(f); + const char *s; /* DYNAMIC interface numbers assignments */ id = usb_interface_id(c, f); @@ -161,6 +162,10 @@ static int fastboot_bind(struct usb_configuration *c, struct usb_function *f) hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress; + s = getenv(serial#); + if (s) + g_dnl_set_serialnumber((char *)s); + return 0; } -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM: atmel: sama5d4 xplained: enable mmc power
Enable the power for MMC/SD port.
Signed-off-by: Bo Shen voice.s...@atmel.com
---
board/atmel/sama5d4_xplained/sama5d4_xplained.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
index bc2aa38..e7f225a 100644
--- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c
+++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c
@@ -228,6 +228,9 @@ void sama5d4_xplained_mci1_hw_init(void)
int board_mmc_init(bd_t *bis)
{
+ /* Enable the power supply */
+ at91_set_pio_output(AT91_PIO_PORTE, 4, 0);
+
return atmel_mci_init((void *)ATMEL_BASE_MCI1);
}
#endif /* CONFIG_GENERIC_ATMEL_MCI */
--
2.3.0
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[U-Boot] please pull u-boot-arc master
Dear Tom, The following changes since commit bd2a4888b123713adec271d6c8040ca9f609aa2f: sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART (2015-02-11 19:43:45 -0500) are available in the git repository at: git://git.denx.de/u-boot-arc.git for you to fetch changes up to f13606b77d32344d35f6430eb45cffd47302e244: arc: introduce U-Boot port for ARCv2 ISA (2015-02-13 09:17:51 +0300) Alexey Brodkin (1): arc: introduce U-Boot port for ARCv2 ISA arch/arc/Kconfig | 59 ++- arch/arc/config.mk | 12 arch/arc/cpu/arcv2/Makefile | 7 +++ arch/arc/cpu/arcv2/start.S | 254 + arch/arc/include/asm/cache.h | 6 +- configs/axs103_defconfig | 5 ++ 6 files changed, 340 insertions(+), 3 deletions(-) create mode 100644 arch/arc/cpu/arcv2/Makefile create mode 100644 arch/arc/cpu/arcv2/start.S create mode 100644 configs/axs103_defconfig Best regards, Alexey ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/8] lpc32xx: add GPIO support
Hi Simon,
Le Thu, 12 Feb 2015 22:06:51 -0700, Simon Glass s...@chromium.org a
écrit :
Hi Albert,
On 12 February 2015 at 10:37, Albert ARIBAUD (3ADEV)
albert.arib...@3adev.fr wrote:
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 268
+++
4 files changed, 317 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs
*)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..559894a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..861975e
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,268 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * We only support driver model
+ */
+#ifndef CONFIG_DM_GPIO
+#error Please enable Driver Model GPIO in your target configuration.
+#endif
Minor note - if you base this on dm/master you can use Kconfig
'depends on DM' in this driver's Kconfig bit.
(pull request to mainline coming soon)
I will rebase then for v3.
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+#include malloc.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ */
+
+#define LPC32XX_GPIOS 128
+
+static
Re: [U-Boot] [PATCH v2 07/10] ARM: remove cm4008 and cm41xx board support
Hi Masahiro, On 12/02/15 11:17, Masahiro Yamada wrote: Hi Greg, On Tue, 10 Feb 2015 18:12:25 +1000 Greg Ungerer greg.unge...@opengear.com wrote: Hi Masahiro, On 10/02/15 17:00, Masahiro Yamada wrote: These are still non-generic boards. Signed-off-by: Masahiro Yamada yamad...@jp.panasonic.com Cc: Greg Ungerer greg.unge...@opengear.com I have only seen this one patch, and the message above doesn't really give me much of a clue what the intention is here. Quite a few of the files you are removing below are not board specific. Many relate to the KS8695 SoC and its peripherals. Are you removing all KS8695 support as well? You still have a chance to keep these boards. If you want to keep them, please support Generic Board for these boards (+ a little test). (Ajay Bhargav and Vladimir Zapolskiy chose to do so to keep their boards.) doc/README.generic-board will help you know the background. If you give up maintaining them, you need not do anything. It is up to you, of course. I don't intend doing any work on them, so I don't have an objection. My only suggestion would be to include the details from your last response in the commit log message. Regards Greg ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] add example for file on VFAT filesystem usage
For example on a raspberry pi the u-boot environment can be saved in a file on the first VFAT partition. This example illustrates how to use it with fw_printenv/fw_setenv. Signed-off-by: Waldemar Brodkorb w...@openadk.org --- tools/env/fw_env.config | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config index c9b9f6a..6f216f9 100644 --- a/tools/env/fw_env.config +++ b/tools/env/fw_env.config @@ -20,3 +20,6 @@ # Block device example #/dev/mmcblk0 0xc 0x2 + +# VFAT example +#/boot/uboot.env 0x 0x4000 -- 1.9.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] bootvx command: flush cache not working properly
Hello all, I have a board with CPU powerpc-p1015 and DDR RAM. I am using VxWorks application executed in the following way: 1. The application load is saved on NOR flash. 2. The application is copied to RAM with: cp.l $source_address $dest_address $size 3. Then the application is executed with bootvx I experience a problem that sometimes a section of the load (8 longs ) is not copied to RAM. It seems that this section remain in the data cache. When I add flush_dcache after the copy, the problem is resolved . The bootvx command already calls the flush_dcache but for some reason it is not enough. Any insight about this problem? Thanks, Rami Meiran ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] arm: relocation: clear .bss section with arch memset if defined
On Sun, Feb 01, 2015 at 03:38:42AM +0100, Albert ARIBAUD wrote: Hello Przemyslaw, On Wed, 28 Jan 2015 13:55:42 +0100, Przemyslaw Marczak p.marc...@samsung.com wrote: For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY, will highly increase the memset/memcpy performance. This is able thanks to the ARM multiple register instructions. Unfortunatelly the relocation is done without the cache enabled, so it takes some time, but zeroing the BSS memory takes much more longer, especially for the configs with big static buffers. A quick test confirms, that the boot time improvement after using the arch memcpy for relocation has no significant meaning. The same test confirms that enable the memset for zeroing BSS, reduces the boot time. So this patch enables the arch memset for zeroing the BSS after the relocation process. For ARM boards, this can be enabled in board configs by defining: 'CONFIG_USE_ARCH_MEMSET'. Since the issue is that zeroing is done one word at a time, could we not simply clear r3 as well as r2 (possibly even r4 and r5 too) and do a double (possibly quadruple) write loop? That would avoid calling a libc routine from the almost sole file in U-Boot where a C environment is not necessarily granted. I want to jump up here again. Note that the arch memset/memcpy routines are in asm and I don't belive require a C environment. Why don't we simply use the asm versions for everyone and backport whatever we need from the kernel to re-sync there as it's not a choice there and it's a performance win too? -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC PATCH] ARM: Merge v7 and v8 outer cache operations
On Sat, Jan 31, 2015 at 11:08:54AM +0800, feng...@phytium.com.cn wrote: From: David Feng feng...@phytium.com.cn Armv7 and Armv8 allow outer cache exist, it is outside of the architecture defined cache hierarchy and can not be manipulated by architecture defined instructions. It's processor specific. This patch merge v7_outer_cache_* and v8 l3_cache_*. Signed-off-by: David Feng feng...@phytium.com.cn I think this makes some sense. Albert? Reviewed-by: Tom Rini tr...@ti.com -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v1 1/1] usb: gadget: fastboot: Add fastboot erase
On 15-02-12 01:21 AM, Dileep Katta wrote:
Hi Rob,
On 12 February 2015 at 14:35, Rob Herring robherri...@gmail.com wrote:
On Tue, Feb 10, 2015 at 2:49 AM, Dileep Katta dileep.ka...@linaro.org wrote:
Adds the fastboot erase functionality, to erase a partition
specified by name. The erase is performed based on erase group size,
to avoid erasing other partitions. The start address and the size
is aligned to the erase group size for this.
Currently only supports erasing from eMMC.
Signed-off-by: Dileep Katta dileep.ka...@linaro.org
---
Note: The changes are on top of oem command support added by r...@kernel.org
common/fb_mmc.c | 58 +
drivers/usb/gadget/f_fastboot.c | 23
include/fb_mmc.h| 1 +
3 files changed, 82 insertions(+)
diff --git a/common/fb_mmc.c b/common/fb_mmc.c
index 6ea3938..3911989 100644
--- a/common/fb_mmc.c
+++ b/common/fb_mmc.c
@@ -10,6 +10,7 @@
#include part.h
#include aboot.h
#include sparse_format.h
+#include mmc.h
#ifndef CONFIG_FASTBOOT_GPT_NAME
#define CONFIG_FASTBOOT_GPT_NAME GPT_ENTRY_NAME
@@ -110,3 +111,60 @@ void fb_mmc_flash_write(const char *cmd, void
*download_buffer,
write_raw_image(dev_desc, info, cmd, download_buffer,
download_bytes);
}
+
+void fb_mmc_erase(const char *cmd, char *response)
+{
+ int ret;
+ block_dev_desc_t *dev_desc;
+ disk_partition_t info;
+ lbaint_t blks, blks_start, blks_size, grp_size;
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ if (mmc == NULL) {
+ error(invalid mmc device\n);
+ fastboot_fail(invalid mmc device);
Perhaps fastboot_fail should also call error().
There is error() before every fastboot_fail(). You mean to move
error() inside fastboot_fail()? If yes, I will do it.
I disagree - most of the error() report more information about the
issue; and the fastboot_fail() just informs the host that it was
unsuccessful -- I don't think that we should force these to be the same
Thanks, Steve
+ return;
+ }
+
+ /* initialize the response buffer */
+ response_str = response;
+
+ dev_desc = get_dev(mmc, CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc-type == DEV_TYPE_UNKNOWN) {
+ error(invalid mmc device\n);
+ fastboot_fail(invalid mmc device);
+ return;
+ }
+
+ ret = get_partition_info_efi_by_name(dev_desc, cmd, info);
+ if (ret) {
+ error(cannot find partition: '%s'\n, cmd);
+ fastboot_fail(cannot find partition);
+ return;
+ }
+
+ puts(Erasing partition\n);
This can probably be dropped since you have a print below.
Will remove.
+
+ /* Align blocks to erase group size to avoid erasing other partitions */
The partitioning could should probably enforce optimal alignment, but
I guess that's a separate patch.
Fine. Will do it as a separate patch.
+ grp_size = mmc-erase_grp_size;
+ blks_start = (info.start + grp_size - 1) ~(grp_size - 1);
+ if (info.size = grp_size)
+ blks_size = (info.size - (blks_start - info.start))
+ (~(grp_size - 1));
+ else
+ blks_size = 0;
+
+ printf(Erasing blocks LBAFU to LBAFU due to alignment\n,
+ blks_start, blks_start + blks_size);
+
+ blks = dev_desc-block_erase(dev_desc-dev, blks_start, blks_size);
+ if (blks != blks_size) {
+ error(failed erasing from device %d\n, dev_desc-dev);
+ fastboot_fail(failed erasing from device);
+ return;
+ }
+
+ printf( erased LBAFU bytes from '%s'\n,
+ blks_size * info.blksz, cmd);
+ fastboot_okay();
+}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index f7d84bf..a8d8205 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -535,6 +535,26 @@ static void cb_oem(struct usb_ep *ep, struct usb_request
*req)
}
}
+static void cb_erase(struct usb_ep *ep, struct usb_request *req)
This should be conditional on CONFIG_FASTBOOT_FLASH
Will make it conditional as in cb_oem().
+{
+ char *cmd = req-buf;
+ char response[RESPONSE_LEN];
+
+ strsep(cmd, :);
+ if (!cmd) {
+ error(missing partition name\n);
+ fastboot_tx_write_str(FAILmissing partition name);
+ return;
+ }
+
+ strcpy(response, FAILno flash device defined);
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+ fb_mmc_erase(cmd, response);
+#endif
+ fastboot_tx_write_str(response);
+}
+
struct cmd_dispatch_info {
char *cmd;
void (*cb)(struct usb_ep *ep, struct usb_request *req);
@@ -566,6 +586,9 @@ static const struct
Re: [U-Boot] [RFC PATCH] ARM: Merge v7 and v8 outer cache operations
On Sat, Jan 31, 2015 at 03:08:54AM +, feng...@phytium.com.cn wrote:
From: David Feng feng...@phytium.com.cn
Armv7 and Armv8 allow outer cache exist, it is outside of the architecture
defined cache hierarchy and can not be manipulated by architecture defined
instructions. It's processor specific.
This patch merge v7_outer_cache_* and v8 l3_cache_*.
This commit message is a little misleading, though it probably makes
sense to have something of this sort ARMv8. Info dump below.
Recently the ARMv8 architecture reference manual was clarified to
mention that any such system caches _must_ respect maintenance by VA,
and are affected by the architected instructions for this. The arm64
Linux port relies on this property.
Set/Way maintenance will not affect system caches. So if you want to
flush/empty the entire cache hierarchy, you will need to rely on a
mechanism specific to the outer cache implementation (rather than one
specific to the processor).
Additionally, the interconnect and cache hierarchies in ARMv8
implementations are becoming more complex, and it is more likely that
dirty lines may migrate arbitrarily between CPUs and the system caches.
Due to this you will need to ensure that CPU caches are disabled and
empty before system cache maintenance is performed (I don't know whether
your current sequences for ARMv7 ensure that).
Thanks,
Mark.
Signed-off-by: David Feng feng...@phytium.com.cn
---
arch/arm/cpu/armv7/cache_v7.c| 22 +++---
arch/arm/cpu/armv7/cpu.c |2 +-
arch/arm/cpu/armv7/exynos/soc.c |2 +-
arch/arm/cpu/armv7/mx6/soc.c |4 ++--
arch/arm/cpu/armv7/omap3/board.c |2 +-
arch/arm/cpu/armv7/omap4/hwinit.c|4 ++--
arch/arm/cpu/armv7/s5pc1xx/cache.c |4 ++--
arch/arm/cpu/armv7/uniphier/cache_uniphier.c | 14 +++---
arch/arm/cpu/armv8/cache_v8.c| 21 -
arch/arm/cpu/armv8/fsl-lsch3/cpu.c |2 +-
arch/arm/include/asm/armv7.h |7 ---
arch/arm/include/asm/cache.h |7 +++
arch/arm/include/asm/system.h|2 --
arch/arm/lib/cache-pl310.c | 12 ++--
14 files changed, 57 insertions(+), 48 deletions(-)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 0f9d837..7d4d5d3 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -237,7 +237,7 @@ void invalidate_dcache_all(void)
{
v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
- v7_outer_cache_inval_all();
+ outer_cache_inval_all();
}
/*
@@ -248,7 +248,7 @@ void flush_dcache_all(void)
{
v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
- v7_outer_cache_flush_all();
+ outer_cache_flush_all();
}
/*
@@ -259,7 +259,7 @@ void invalidate_dcache_range(unsigned long start,
unsigned long stop)
{
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
- v7_outer_cache_inval_range(start, stop);
+ outer_cache_inval_range(start, stop);
}
/*
@@ -271,12 +271,12 @@ void flush_dcache_range(unsigned long start, unsigned
long stop)
{
v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
- v7_outer_cache_flush_range(start, stop);
+ outer_cache_flush_range(start, stop);
}
void arm_init_before_mmu(void)
{
- v7_outer_cache_enable();
+ outer_cache_enable();
invalidate_dcache_all();
v7_inval_tlb();
}
@@ -355,9 +355,9 @@ void invalidate_icache_all(void)
#endif
/* Stub implementations for outer cache operations */
-__weak void v7_outer_cache_enable(void) {}
-__weak void v7_outer_cache_disable(void) {}
-__weak void v7_outer_cache_flush_all(void) {}
-__weak void v7_outer_cache_inval_all(void) {}
-__weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
-__weak void v7_outer_cache_inval_range(u32 start, u32 end) {}
+__weak void outer_cache_enable(void) {}
+__weak void outer_cache_disable(void) {}
+__weak void outer_cache_flush_all(void) {}
+__weak void outer_cache_inval_all(void) {}
+__weak void outer_cache_flush_range(unsigned long start, unsigned long end)
{}
+__weak void outer_cache_inval_range(unsigned long start, unsigned long end)
{}
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 01cdb7e..07ad549 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -47,7 +47,7 @@ int cleanup_before_linux(void)
* dcache_disable() in turn flushes the d-cache and disables MMU
*/
dcache_disable();
- v7_outer_cache_disable();
+ outer_cache_disable();
/*
* After D-cache is flushed and before it is disabled there may
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
Re: [U-Boot] [PATCH 0/3] arm: reduce .bss section clear time
On Thu, Feb 05, 2015 at 10:51:00AM +0100, Lukasz Majewski wrote: Hi Simon, Hi Lukasz, On 2 February 2015 at 01:46, Lukasz Majewski l.majew...@samsung.com wrote: Dear All, And the next is interesting. odroid_defconfig has more than 80MB for malloc (we need about 64mb for the DFU now, to be able write 32MB file). This is the CONFIG_SYS_MALLOC_LEN. And the memory area for malloc is set to 0 in function mem_malloc_init(). So for this config that function sets more than 80MB to zero. This is not good, because we shouldn't expect zeroed memory returned by malloc pointer. This is a job for calloc. Especially if some command expects zeroed memory after malloc, probably after few next calls - it can crash... I think that the above excerpt is _really_ important and should be discussed. I've cut it from the original post, so it won't get lost between the lines. It seems really strange, that malloc() area is cleared after relocation. Which means that all first malloc'ed buffers get implicitly zeroed. Przemek is right here that this zeroing shouldn't be performed. I'm also concerned about potential bugs, which show up (or even worse - won't show up soon) after this change. Hence, I would like to ask directly the community about the possible solutions. Please look at: ./common/dlmalloc.c mem_alloc_init() function [1]. On the one hand removing memset() at [1] speeds up booting time and makes malloc() doing what is is supposed to do. On the other hand there might be in space some boards, which rely on this memset and without it some wired things may start to happening. I think removing it is a good idea. It was one optimisation that I did for boot time in the Chromium tree. If you do it now (and Tom agrees) then there is plenty of time to test for this release cycle. You could go further and add a test CONFIG which fills it with some other non-zero value. Tom, is such approach acceptable for you? I was thinking at first we should default to a poisoned value. But given what we're seeing with generic board updates (lots of boards aren't even build-tested at every release which isn't really a surprise), I think the funky boards which may exist are probably not going to be seen for a while anyhow so we'd have to default to a poison for a long while. So yes, lets just add a CONFIG option (and Kconfig line) to optionally do it and default to no memset. ... but I just audited everyone doing malloc ( and found a few things to fixup so we really do want to take a poke around. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] imx6: Added DEK blob generator command
From: Raul Cardenas ulises.carde...@freescale.com
Freescale's SEC block has built-in Data Encryption
Key(DEK) Blob Protocol which provides a method for
protecting a DEK for non-secure memory storage.
SEC block protects data in a data structure called
a Secret Key Blob, which provides both confidentiality
and integrity protection.
Every time the blob encapsulation is executed,
a SHA-256 key is randomly generated to encrypt the DEK.
This key is itself encrypted with the OTP Secret key
from SoC. The ending blob consists of the encrypted
SHA-256 key, the encrypted DEK, and a 16-bit MAC.
During decapsulation, the reverse process is performed
to get back the original DEK. A caveat to the blob
decapsulation process, is that the DEK is decrypted
in secure-memory and can only be read by FSL SEC HW.
The DEK is used to decrypt data during encrypted boot.
Commands added
--
dek_blob - encapsulating DEK as a cryptgraphic blob
Commands Syntax
---
dek_blob src dst len
Encapsulate and create blob of a len-bits DEK at
address src and store the result at address dst.
Signed-off-by: Raul Cardenas ulises.carde...@freescale.com
Signed-off-by: Nitin Garg nitin.g...@freescale.com
---
Changes in v3:
-Improve cache management for relevant descriptors
-Add cache management to RNG instantiate
Changes in v2:
-Remove weak symbol as recommended by Ruchika
arch/arm/imx-common/Makefile |1 +
arch/arm/imx-common/cmd_dek.c| 89 +++
arch/arm/imx-common/timer.c | 17
arch/arm/include/asm/arch-mx6/imx-regs.h |4 +
doc/README.mxc_hab | 48 ++
drivers/crypto/fsl/Makefile |2 +-
drivers/crypto/fsl/desc.h| 15
drivers/crypto/fsl/fsl_blob.c| 50 +++
drivers/crypto/fsl/jobdesc.c | 142 +-
drivers/crypto/fsl/jobdesc.h |5 ++
drivers/crypto/fsl/jr.c | 31 ++-
include/fsl_sec.h| 60 +
12 files changed, 457 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/imx-common/cmd_dek.c
diff --git a/arch/arm/imx-common/Makefile b/arch/arm/imx-common/Makefile
index 25a9d4c..606482f 100644
--- a/arch/arm/imx-common/Makefile
+++ b/arch/arm/imx-common/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_IMX_VIDEO_SKIP) += video.o
endif
obj-$(CONFIG_CMD_BMODE) += cmd_bmode.o
obj-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
+obj-$(CONFIG_CMD_DEKBLOB) += cmd_dek.o
quiet_cmd_cpp_cfg = CFGS$@
cmd_cpp_cfg = $(CPP) $(cpp_flags) -x c -o $@ $
diff --git a/arch/arm/imx-common/cmd_dek.c b/arch/arm/imx-common/cmd_dek.c
new file mode 100644
index 000..1a3a996a
--- /dev/null
+++ b/arch/arm/imx-common/cmd_dek.c
@@ -0,0 +1,89 @@
+/*
+ * Command for encapsulating DEK blob
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include command.h
+#include environment.h
+#include malloc.h
+#include asm/byteorder.h
+#include linux/compiler.h
+#include fsl_sec.h
+#include asm/arch/clock.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/**
+* blob_dek() - Encapsulate the DEK as a blob using CAM's Key
+* @src: - Address of data to be encapsulated
+* @dst: - Address of data to be encapsulated
+* @len: - Size of data to be encapsulated
+*
+* Returns zero on success,and negative on error.
+*/
+static int blob_encap_dek(u8 *src, u8 *dst, u32 len)
+{
+ int ret = 0;
+ u32 jr_size = 4;
+
+ u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + 0x102c);
+ if (out_jr_size != jr_size) {
+ hab_caam_clock_enable(1);
+ sec_init();
+ }
+
+ if (!((len == 128)|(len == 192)|(len == 256))) {
+ debug(Invalid DEK size. Valid sizes are 128, 192 and 256b\n);
+ return -1;
+ }
+
+ len /= 8;
+ ret = blob_dek(src, dst, len);
+
+ return ret;
+}
+
+/**
+ * do_dek_blob() - Handle the dek_blob command-line command
+ * @cmdtp: Command data struct pointer
+ * @flag: Command flag
+ * @argc: Command-line argument count
+ * @argv: Array of command-line arguments
+ *
+ * Returns zero on success, CMD_RET_USAGE in case of misuse and negative
+ * on error.
+ */
+static int do_dek_blob(cmd_tbl_t *cmdtp, int flag, int argc, char *const
argv[])
+{
+ uint32_t src_addr, dst_addr, len;
+ uint8_t *src_ptr, *dst_ptr;
+ int ret = 0;
+
+ if (argc != 4)
+ return CMD_RET_USAGE;
+
+ src_addr = simple_strtoul(argv[1], NULL, 16);
+ dst_addr = simple_strtoul(argv[2], NULL, 16);
+ len = simple_strtoul(argv[3], NULL, 10);
+
+ src_ptr = (uint8_t *)src_addr;
+ dst_ptr = (uint8_t *)dst_addr;
+
+ ret = blob_encap_dek(src_ptr, dst_ptr, len);
+
+ return ret;
+}
+
+/***/
+static char dek_blob_help_text[] =
+ src dst len- Encapsulate and create blob of
[U-Boot] [PATCH] misc: Call calloc() not malloc() to ensure buffer is zeroed
- mpc512x_fec.c: 'fec' was not being memset while dev was, just call
calloc() instead for both. 'bd' was being memset afterwards but given
that it's an awkward looking call, just calloc() it directly.
- bzlib.c: Some fields to 'bzf' are being set to NULL later but for
clarity calloc() the structure.
- string.c: We rely on malloc() having zeroed the buffer here so use
calloc() instead.
Signed-off-by: Tom Rini tr...@ti.com
---
drivers/net/mpc512x_fec.c |8 +++-
lib/bzip2/bzlib.c |4 ++--
lib/string.c |2 +-
3 files changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 427e0b8..bee67d33 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -616,9 +616,8 @@ int mpc512x_fec_initialize (bd_t * bis)
struct eth_device *dev;
void * bd;
- fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
- dev = (struct eth_device *) malloc (sizeof(*dev));
- memset (dev, 0, sizeof *dev);
+ fec = (mpc512x_fec_priv *) cmalloc (sizeof(*fec));
+ dev = (struct eth_device *) cmalloc (sizeof(*dev));
fec-eth = im-fec;
@@ -650,9 +649,8 @@ int mpc512x_fec_initialize (bd_t * bis)
* Malloc space for BDs (must be quad word-aligned)
* this pointer is lost, so cannot be freed
*/
- bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
+ bd = cmalloc (sizeof(mpc512x_buff_descs) + 0x1f);
fec-bdBase = (mpc512x_buff_descs*)((u32)bd 0xfff0);
- memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
/*
* Set interrupt mask register
diff --git a/lib/bzip2/bzlib.c b/lib/bzip2/bzlib.c
index 9262e40..1305808 100644
--- a/lib/bzip2/bzlib.c
+++ b/lib/bzip2/bzlib.c
@@ -963,7 +963,7 @@ BZFILE* BZ_API(BZ2_bzWriteOpen)
if (ferror(f))
{ BZ_SETERR(BZ_IO_ERROR); return NULL; };
- bzf = malloc ( sizeof(bzFile) );
+ bzf = cmalloc ( sizeof(bzFile) );
if (bzf == NULL)
{ BZ_SETERR(BZ_MEM_ERROR); return NULL; };
@@ -1135,7 +1135,7 @@ BZFILE* BZ_API(BZ2_bzReadOpen)
if (ferror(f))
{ BZ_SETERR(BZ_IO_ERROR); return NULL; };
- bzf = malloc ( sizeof(bzFile) );
+ bzf = cmalloc ( sizeof(bzFile) );
if (bzf == NULL)
{ BZ_SETERR(BZ_MEM_ERROR); return NULL; };
diff --git a/lib/string.c b/lib/string.c
index 87c9a40..f496dbe 100644
--- a/lib/string.c
+++ b/lib/string.c
@@ -284,7 +284,7 @@ char * strdup(const char *s)
char *new;
if ((s == NULL) ||
- ((new = malloc (strlen(s) + 1)) == NULL) ) {
+ ((new = cmalloc (strlen(s) + 1)) == NULL) ) {
return NULL;
}
--
1.7.9.5
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Re: [U-Boot] [PATCH 07/12] imx:mx6 Support LDO bypass
On Tue, Feb 10, 2015 at 06:33:38AM -0800, Tim Harvey wrote:
On Fri, Jan 9, 2015 at 12:59 AM, Peng Fan peng@freescale.com wrote:
The basic graph for voltage input is:
VDDARM_IN --- LDO_DIG(ARM) --- VDD_ARM_CAP
VDDSOC_IN --- LDO_DIG(SOC) --- VDD_SOC_CAP
Hi Peng,
Glad to see someone else interested in IMX6 LDO bypass mode. I've made
a couple of stabs at getting it supported in mainline but I haven't
had the time to follow-through yet there.
We can bypass the LDO to save power, if the board already has pmic.
set_anatop_bypass is the function to do the bypass VDDARM and VDDSOC
work.
Current only set VDDARM_IN@1.175V/VDDSOC_IN@1.175V before ldo
bypass switch. So until ldo bypass switch happened, these voltage
setting is set in ldo-enable mode. But in datasheet, we need
1.15V + 125mV = 1.275V for VDDARM_IN. We need to downgrade cpufreq
to 400Mhz and restore after ldo bypass mode switch. So add
prep_anatop_bypass/finish_anatop_bypass/set_arm_freq_400M to do
this work.
LDO bypass is dependent on the flatten device tree file. If speed
grading fuse is for 1.2GHz, enable LDO bypass and setup PMIC voltages.
So add check for 1.2GHz core speed. So add check_1_2G function.
This isn't quite how it works. If you are 'operating at 1.2GHz'
(supposing you had a processor cabable of it) you must use the LDO (to
avoid ripple sensitivity issues).
Hi Peng, the limitation is must use ldo-enable mode in 1.2Ghz, NOT ldo-bypass
In ldo-bypass mode, we need trigger WDOG_B pin to reset pmic in
ldo-bypass mode. So add set_wdog_reset to do this work.
This is very board dependent. Here you are referring to a board that
has a reset input to the PMIC's from the IMX6's watchdog output. In
this case, this reset routing/pinmux would be needed regardless of
using ldo-bypass mode or not and that should just be a pinmux of the
pin your using for WDOG_B.
There are two types of reboot in our chip by watchdog : SRS/warm reset
(Software Reset Signal) and WDOG_B(reset signal output to external pmic
to trigger next power cycle). In fact, warm reset can work most cases except
ldo-bypass mode and this is why we connect WDOG_B reset and ldo-bypass here:
kernel may trigger warm reset at the lowest cpu freq setpoint, for example
VDDARM 0.975v@396Mhz ldo-bypass mode. i.mx6q will reboot with ldo-enable mode
@792Mhz and the VDDARM_IN 0.975v can't support system boot.Thus, we need use
WDOG_B pin to reset external pmic if using ldo-byapss mode.
snip
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5f5f497..5d02755 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -18,6 +18,7 @@
#include asm/arch/sys_proto.h
#include asm/imx-common/boot_mode.h
#include asm/imx-common/dma.h
+#include libfdt.h
#include stdbool.h
#include asm/arch/mxc_hdmi.h
#include asm/arch/crm_regs.h
@@ -429,6 +430,146 @@ void s_init(void)
writel(mask528, anatop-pfd_528_clr);
}
+#ifdef CONFIG_LDO_BYPASS_CHECK
+DECLARE_GLOBAL_DATA_PTR;
+static int ldo_bypass;
+
+int check_ldo_bypass(void)
+{
+ const int *ldo_mode;
+ int node;
+
+ /* get the right fdt_blob from the global working_fdt */
+ gd-fdt_blob = working_fdt;
+ /* Get the node from FDT for anatop ldo-bypass */
+ node = fdt_node_offset_by_compatible(gd-fdt_blob, -1,
+ fsl,imx6q-gpc);
+ if (node 0) {
+ printf(No gpc device node %d, force to ldo-enable.\n,
node);
+ return 0;
+ }
+ ldo_mode = fdt_getprop(gd-fdt_blob, node, fsl,ldo-bypass, NULL);
+ /*
+* return 1 if fsl,ldo-bypass = 1, else return 0 if
+* fsl,ldo-bypass = 0 or no fsl,ldo-bypass property
+*/
+ ldo_bypass = fdt32_to_cpu(*ldo_mode) == 1 ? 1 : 0;
+
+ return ldo_bypass;
+}
What you are doing here is relying on a device-tree binding from the
Freescale 'vendor' kernel, which will NEVER make it upstream and this
is one of the issues I was running into getting ldo-bypass capability
upstream in the kernel.
The issue here is that LDO bypass is dependent on the following things:
1. your voltage rail requirements - which are dependent on the CPU
frequency (there is a nice table in the IMX6 datasheets of voltage on
each rail at each frequency operating point validated by Freescale).
The exception of always using the LDO for 1.2GHz is specified here as
well.
2. you have a PMIC in your design on VDD_ARM_IN and VDD_SOC_IN rails
- this should be specified in the device-tree as well
3. you have valid PMIC drivers configured
In the kernel, its not desired to have a single device-tree node
called 'fsl,ldo-bypass' for an enable. Instead you need to make sure
that you PMIC regulators that are 'not' the internal IMX6 anatop
regulators. This property is not a mainline linux device-tree binding.
Re: [U-Boot] Can I load uEnv.txt conditionally, based on the boot source?
Hello, That would be the most obvious thing, wouldn't it. I thought of that, but am not sure of the answer in u-boot. Thanks, Brian On 2/11/2015 12:09 AM, Joe Hershberger wrote: On Tue, Feb 10, 2015 at 7:18 PM, Brian Smucker b...@bsmucker.eu.org mailto:b...@bsmucker.eu.org wrote: Hello, I was wondering if there is a way to tell what the boot source is? My am335x SOC can boot to the mmc or the flash, based on the status of a digital line. I would like to load the uEnv.txt, only if booting from SD card (mmc). I notice at least in some codebases that the automatic loading of uEnv.txt is based on whether the SD card is available, not whether we are currently booting from the SD card. Is there a way to sense which we are booting from? Are you able to read the same digital line that the SoC is using to decide? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] dm: at91: Drop use of ATMEL_PIO_PORTS in the header file
On 02/12/2015 12:32 AM, Simon Glass wrote:
With driver model the number of PIO ports is defined by platform data, so
remove it from the header file.
Signed-off-by: Simon Glass s...@chromium.org
Acked-by: Andreas Bießmann andreas.de...@googlemail.com
---
Changes in v3:
- Split out the ATMEL_PIO_PORTS change into its own patch
Changes in v2: None
arch/arm/include/asm/arch-at91/at91_pio.h | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h
b/arch/arm/include/asm/arch-at91/at91_pio.h
index 50464ff..3012278 100644
--- a/arch/arm/include/asm/arch-at91/at91_pio.h
+++ b/arch/arm/include/asm/arch-at91/at91_pio.h
@@ -114,14 +114,10 @@ typedef union at91_pio {
at91_port_t pioa;
at91_port_t piob;
at91_port_t pioc;
- #if (ATMEL_PIO_PORTS 3)
- at91_port_t piod;
- #endif
- #if (ATMEL_PIO_PORTS 4)
- at91_port_t pioe;
- #endif
- } ;
- at91_port_t port[ATMEL_PIO_PORTS];
+ at91_port_t piod; /* not present in all hardware */
+ at91_port_t pioe;/* not present in all hardware */
+ };
+ at91_port_t port[5];
} at91_pio_t;
#ifdef CONFIG_AT91_GPIO
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[U-Boot] [PATCH v2 3/8] lpc32xx: i2c: add LPC32xx I2C interface support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile | 1 +
drivers/i2c/lpc32xx_i2c.c | 249 ++
6 files changed, 268 insertions(+)
create mode 100644 drivers/i2c/lpc32xx_i2c.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index be4c93d..81b53ea 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -50,3 +50,14 @@ void lpc32xx_mlc_nand_init(void)
/* Enable NAND interface */
writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
}
+
+void lpc32xx_i2c_init(unsigned int devnum)
+{
+ /* Enable I2C interface */
+ uint32_t ctrl = readl(clk-i2cclk_ctrl);
+ if (devnum == 1)
+ ctrl |= CLK_I2C1_ENABLE;
+ if (devnum == 2)
+ ctrl |= CLK_I2C2_ENABLE;
+ writel(ctrl, clk-i2cclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index bc7d33d..781ac07 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -123,6 +123,10 @@ struct clk_pm_regs {
#define CLK_MAC_SLAVE (1 1)
#define CLK_MAC_REG(1 0)
+/* I2C Clock Control Register bits */
+#define CLK_I2C2_ENABLE(1 1)
+#define CLK_I2C1_ENABLE(1 0)
+
/* Timer Clock Control1 Register bits */
#define CLK_TIMCLK_MOTOR (1 6)
#define CLK_TIMCLK_TIMER3 (1 5)
diff --git a/arch/arm/include/asm/arch-lpc32xx/cpu.h
b/arch/arm/include/asm/arch-lpc32xx/cpu.h
index 199b4a0..1067107 100644
--- a/arch/arm/include/asm/arch-lpc32xx/cpu.h
+++ b/arch/arm/include/asm/arch-lpc32xx/cpu.h
@@ -37,6 +37,8 @@
#define UART4_BASE 0x40088000 /* UART 4 registers base*/
#define UART5_BASE 0x4009 /* UART 5 registers base*/
#define UART6_BASE 0x40098000 /* UART 6 registers base*/
+#define I2C1_BASE 0x400A /* I2C 1 registers base*/
+#define I2C2_BASE 0x400A8000 /* I2C 2 registers base*/
/* External SDRAM Memory Bank base addresses */
#define EMC_DYCS0_BASE 0x8000 /* SDRAM DYCS0 base address */
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 0c4e712..a4a05d1 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -10,5 +10,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
+void lpc32xx_i2c_init(unsigned int devnum);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 774bc94..26ea854 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_SYS_I2C_FSL) += fsl_i2c.o
obj-$(CONFIG_SYS_I2C_FTI2C010) += fti2c010.o
obj-$(CONFIG_SYS_I2C_IHS) += ihs_i2c.o
obj-$(CONFIG_SYS_I2C_KONA) += kona_i2c.o
+obj-$(CONFIG_SYS_I2C_LPC32XX) += lpc32xx_i2c.o
obj-$(CONFIG_SYS_I2C_MVTWSI) += mvtwsi.o
obj-$(CONFIG_SYS_I2C_MXC) += mxc_i2c.o
obj-$(CONFIG_SYS_I2C_MXS) += mxs_i2c.o
diff --git a/drivers/i2c/lpc32xx_i2c.c b/drivers/i2c/lpc32xx_i2c.c
new file mode 100644
index 000..78d26e4
--- /dev/null
+++ b/drivers/i2c/lpc32xx_i2c.c
@@ -0,0 +1,249 @@
+/*
+ * LPC32xx I2C interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+#include i2c.h
+#include asm/errno.h
+#include asm/arch/clk.h
+
+/*
+ * Provide default speed and slave if target did not
+ */
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SPEED)
+#define CONFIG_SYS_I2C_LPC32XX_SPEED 35
+#endif
+
+#if !defined(CONFIG_SYS_I2C_LPC32XX_SLAVE)
+#define CONFIG_SYS_I2C_LPC32XX_SLAVE 0
+#endif
+
+/* i2c register set */
+struct lpc32xx_i2c_registers {
+ union {
+ u32 rx;
+ u32 tx;
+ };
+ u32 stat;
+ u32 ctrl;
+ u32 clk_hi;
+ u32 clk_lo;
+ u32 adr;
+ u32 rxfl;
+ u32 txfl;
+ u32 rxb;
+ u32 txb;
+ u32 stx;
+ u32 stxfl;
+};
+
+/* TX register fields */
+#define LPC32XX_I2C_TX_START 0x0100
+#define LPC32XX_I2C_TX_STOP0x0200
+
+/* Control register values */
+#define LPC32XX_I2C_SOFT_RESET 0x0100
+
+/* Status register values */
+#define LPC32XX_I2C_STAT_TFF 0x0400
+#define LPC32XX_I2C_STAT_RFE
[U-Boot] [PATCH v2 4/8] lpc32xx: add GPIO support
This driver only supports Driver Model, not legacy model.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- move from legacy to Driver Model support
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 5 +
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 +
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 268 +++
4 files changed, 317 insertions(+)
create mode 100644 arch/arm/include/asm/arch-lpc32xx/gpio.h
create mode 100644 drivers/gpio/lpc32xx_gpio.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 81b53ea..a407098 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -9,6 +9,7 @@
#include asm/arch/clk.h
#include asm/arch/uart.h
#include asm/io.h
+#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
@@ -61,3 +62,7 @@ void lpc32xx_i2c_init(unsigned int devnum)
ctrl |= CLK_I2C2_ENABLE;
writel(ctrl, clk-i2cclk_ctrl);
}
+
+U_BOOT_DEVICE(lpc32xx_gpios) = {
+ .name = gpio_lpc32xx
+};
diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio.h
b/arch/arm/include/asm/arch-lpc32xx/gpio.h
new file mode 100644
index 000..3bd94e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-lpc32xx/gpio.h
@@ -0,0 +1,43 @@
+/*
+ * LPC32xx GPIO interface
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * GPIO Register map for LPC32xx
+ */
+
+struct gpio_regs {
+ u32 p3_inp_state;
+ u32 p3_outp_set;
+ u32 p3_outp_clr;
+ u32 p3_outp_state;
+ /* Watch out! the following are shared between p2 and p3 */
+ u32 p2_p3_dir_set;
+ u32 p2_p3_dir_clr;
+ u32 p2_p3_dir_state;
+ /* Now back to 'one register for one port' */
+ u32 p2_inp_state;
+ u32 p2_outp_set;
+ u32 p2_outp_clr;
+ u32 reserved1[6];
+ u32 p0_inp_state;
+ u32 p0_outp_set;
+ u32 p0_outp_clr;
+ u32 p0_outp_state;
+ u32 p0_dir_set;
+ u32 p0_dir_clr;
+ u32 p0_dir_state;
+ u32 reserved2;
+ u32 p1_inp_state;
+ u32 p1_outp_set;
+ u32 p1_outp_clr;
+ u32 p1_outp_state;
+ u32 p1_dir_set;
+ u32 p1_dir_clr;
+ u32 p1_dir_state;
+};
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index aa11f15..559894a 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ADI_GPIO2) += adi_gpio2.o
obj-$(CONFIG_TCA642X) += tca642x.o
oby-$(CONFIG_SX151X) += sx151x.o
obj-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o
+obj-$(CONFIG_LPC32XX_GPIO) += lpc32xx_gpio.o
diff --git a/drivers/gpio/lpc32xx_gpio.c b/drivers/gpio/lpc32xx_gpio.c
new file mode 100644
index 000..861975e
--- /dev/null
+++ b/drivers/gpio/lpc32xx_gpio.c
@@ -0,0 +1,268 @@
+/*
+ * LPC32xxGPIO driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/**
+ * We only support driver model
+ */
+#ifndef CONFIG_DM_GPIO
+#error Please enable Driver Model GPIO in your target configuration.
+#endif
+
+#include asm/io.h
+#include asm/arch-lpc32xx/cpu.h
+#include asm/arch-lpc32xx/gpio.h
+#include asm-generic/gpio.h
+#include dm.h
+#include malloc.h
+
+/**
+ * LPC32xx GPIOs work in banks but are non-homogeneous:
+ * - each bank holds a different number of GPIOs
+ * - some GPIOs are input/ouput, some input only, some output only;
+ * - some GPIOs have different meanings as an input and as an output;
+ * - some GPIOs are controlled on a given port and bit index, but
+ * read on another one.
+*
+ * In order to keep this code simple, GPIOS are considered here as
+ * homogeneous and linear, from 0 to 127.
+ *
+ * ** WARNING **
+ *
+ * Client code is responsible for properly using valid GPIO numbers,
+ * including cases where a single physical GPIO has differing numbers
+ * for setting its direction, reading it and/or writing to it.
+ */
+
+#define LPC32XX_GPIOS 128
+
+static struct gpio_regs *regs = (struct gpio_regs *)GPIO_BASE;
+
+/**
+ * We have 4 GPIO ports of 32 bits each
+ */
+
+#define MAX_GPIO 128
+
+#define GPIO_TO_PORT(gpio) ((gpio / 32) 3)
+#define GPIO_TO_RANK(gpio) (gpio % 32)
+#define GPIO_TO_MASK(gpio) (1 (gpio % 32))
+
+/**
+ * Array of current GPIO functions. Allocated as unsigned chars to
+ * limit memory consumption.
+ */
+
+static signed char lpc32xx_function[LPC32XX_GPIOS];
+
+/**
+ * Configure a GPIO number 'offset' as input
+ */
+
+static int lpc32xx_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ int port, mask;
+
+ port = GPIO_TO_PORT(offset);
+ mask =
[U-Boot] [PATCH v2 1/8] lpc32xx: add Ethernet support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile | 1 +
drivers/net/lpc32xx_eth.c | 636 ++
include/netdev.h | 1 +
7 files changed, 658 insertions(+)
create mode 100644 drivers/net/lpc32xx_eth.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index 35095a9..eec4d9e 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -5,6 +5,7 @@
*/
#include common.h
+#include netdev.h
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/wdt.h
@@ -55,3 +56,11 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+ lpc32xx_eth_initialize(bis);
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index b567657..062db8d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -37,3 +37,10 @@ void lpc32xx_uart_init(unsigned int uart_id)
writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
clk-u3clk + (uart_id - 3));
}
+
+void lpc32xx_mac_init(void)
+{
+ /* Enable MAC interface */
+ writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
+ | CLK_MAC_MII, clk-macclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/config.h
b/arch/arm/include/asm/arch-lpc32xx/config.h
index 8f6426b..6c9526d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/config.h
+++ b/arch/arm/include/asm/arch-lpc32xx/config.h
@@ -50,6 +50,9 @@
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
+/* Ethernet */
+#define LPC32XX_ETH_BASE ETHERNET_BASE
+
/* NOR Flash */
#if defined(CONFIG_SYS_FLASH_CFI)
#define CONFIG_FLASH_CFI_DRIVER
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index 28812be..a6b8826 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -8,5 +8,6 @@
#define _LPC32XX_SYS_PROTO_H
void lpc32xx_uart_init(unsigned int uart_id);
+void lpc32xx_mac_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 46c4ac6..35fdb51 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o
obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o
obj-$(CONFIG_LAN91C96) += lan91c96.o
+obj-$(CONFIG_LPC32XX_ETH) += lpc32xx_eth.o
obj-$(CONFIG_MACB) += macb.o
obj-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
obj-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
new file mode 100644
index 000..16c8ef0
--- /dev/null
+++ b/drivers/net/lpc32xx_eth.c
@@ -0,0 +1,636 @@
+/*
+ * LPC32xx Ethernet MAC interface driver
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD - 3ADEV albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include net.h
+#include malloc.h
+#include miiphy.h
+#include asm/io.h
+#include asm/errno.h
+#include asm/types.h
+#include asm/system.h
+#include asm/byteorder.h
+#include asm/arch/cpu.h
+#include asm/arch/config.h
+
+/*
+ * Notes:
+ *
+ * 1. Unless specified otherwise, all references to tables or paragraphs
+ *are to UM10326, LPC32x0 and LPC32x0/01 User manual.
+ *
+ * 2. Only bitfield masks/values which are actually used by the driver
+ *are defined.
+ */
+
+/* a single RX descriptor. The controller has an array of these */
+struct lpc32xx_eth_rxdesc {
+ u32 packet; /* Receive packet pointer */
+ u32 control;/* Descriptor command status */
+};
+
+#define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
+
+/* RX control bitfields/masks (see Table 330) */
+#define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x07FF
+#define LPC32XX_ETH_RX_CTRL_UNUSED0x7800
+#define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x8000
+
+/* a single RX status. The controller has an array of these */
+struct lpc32xx_eth_rxstat {
+ u32 statusinfo; /* Transmit Descriptor status */
+ u32 statushashcrc; /* Transmit Descriptor CRCs */
+};
+
+#define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
+
+/* RX statusinfo bitfields/masks (see Table 333) */
+#define RX_STAT_RXSIZE 0x07FF
+/* Helper: OR of all errors except RANGE */
+#define RX_STAT_ERRORS 0x1B80
+
+/* a single TX descriptor. The
[U-Boot] [PATCH v2 2/8] lpc32xx: mtd: nand: add MLC NAND controller
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/mtd/nand/Makefile | 1 +
drivers/mtd/nand/lpc32xx_nand_mlc.c | 589 ++
5 files changed, 601 insertions(+)
create mode 100644 drivers/mtd/nand/lpc32xx_nand_mlc.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index 062db8d..be4c93d 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -44,3 +44,9 @@ void lpc32xx_mac_init(void)
writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
| CLK_MAC_MII, clk-macclk_ctrl);
}
+
+void lpc32xx_mlc_nand_init(void)
+{
+ /* Enable NAND interface */
+ writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, clk-flashclk_ctrl);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 92f6c15..bc7d33d 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -147,6 +147,10 @@ struct clk_pm_regs {
/* DMA Clock Control Register bits */
#define CLK_DMA_ENABLE (1 0)
+/* NAND Clock Control Register bits */
+#define CLK_NAND_MLC (1 1)
+#define CLK_NAND_MLC_INT (1 5)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a6b8826..0c4e712 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -9,5 +9,6 @@
void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
+void lpc32xx_mlc_nand_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 1f02bfc..347ea62 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_NAND_JZ4740) += jz4740_nand.o
obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
+obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
obj-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
obj-$(CONFIG_NAND_MXC) += mxc_nand.o
diff --git a/drivers/mtd/nand/lpc32xx_nand_mlc.c
b/drivers/mtd/nand/lpc32xx_nand_mlc.c
new file mode 100644
index 000..cb23972
--- /dev/null
+++ b/drivers/mtd/nand/lpc32xx_nand_mlc.c
@@ -0,0 +1,589 @@
+/*
+ * LPC32xx MLC NAND flash controller driver
+ *
+ * (C) Copyright 2014 3ADEV http://3adev.com
+ * Written by Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * NOTE:
+ *
+ * The MLC NAND flash controller provides hardware Reed-Solomon ECC
+ * covering in- and out-of-band data together. Therefore, in- and out-
+ * of-band data must be written together in order to have a valid ECC.
+ *
+ * Consequently, pages with meaningful in-band data are written with
+ * blank (all-ones) out-of-band data and a valid ECC, and any later
+ * out-of-band data write will void the ECC.
+ *
+ * Therefore, code which reads such late-written out-of-band data
+ * should not rely on the ECC validity.
+ */
+
+#include common.h
+#include nand.h
+#include asm/errno.h
+#include asm/io.h
+#include nand.h
+#include asm/arch/clk.h
+#include asm/arch/sys_proto.h
+
+/*
+ * MLC NAND controller registers.
+ */
+struct lpc32xx_nand_mlc_registers {
+ u8 buff[32768]; /* controller's serial data buffer */
+ u8 data[32768]; /* NAND's raw data buffer */
+ u32 cmd;
+ u32 addr;
+ u32 ecc_enc_reg;
+ u32 ecc_dec_reg;
+ u32 ecc_auto_enc_reg;
+ u32 ecc_auto_dec_reg;
+ u32 rpr;
+ u32 wpr;
+ u32 rubp;
+ u32 robp;
+ u32 sw_wp_add_low;
+ u32 sw_wp_add_hig;
+ u32 icr;
+ u32 time_reg;
+ u32 irq_mr;
+ u32 irq_sr;
+ u32 lock_pr;
+ u32 isr;
+ u32 ceh;
+};
+
+/* LOCK_PR register defines */
+#define LOCK_PR_UNLOCK_KEY 0xA25E /* Magic unlock value */
+
+/* ICR defines */
+#define ICR_LARGE_BLOCKS 0x0004/* configure for 2KB blocks */
+#define ICR_ADDR40x0002/* configure for 4-word addrs */
+
+/* CEH defines */
+#define CEH_NORMAL_CE 0x0001 /* do not force CE ON */
+
+/* ISR register defines */
+#define ISR_NAND_READY0x0001
+#define ISR_CONTROLLER_READY 0x0002
+#define ISR_ECC_READY 0x0004
+#define ISR_DECODER_ERRORS(s) s) 4) 3)+1)
+#define
[U-Boot] [PATCH v2 5/8] lpc32xx: add LPC32xx SSP support (SPI mode)
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- added MUX setting for SSP0
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 14 +++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c | 132 ++
5 files changed, 151 insertions(+)
create mode 100644 drivers/spi/lpc32xx_ssp.c
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
index a407098..5a453e3 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/devices.c
@@ -8,11 +8,13 @@
#include asm/arch/cpu.h
#include asm/arch/clk.h
#include asm/arch/uart.h
+#include asm/arch/mux.h
#include asm/io.h
#include dm.h
static struct clk_pm_regs*clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
+static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
void lpc32xx_uart_init(unsigned int uart_id)
{
@@ -66,3 +68,15 @@ void lpc32xx_i2c_init(unsigned int devnum)
U_BOOT_DEVICE(lpc32xx_gpios) = {
.name = gpio_lpc32xx
};
+
+/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
+
+#define P_MUX_SET_SSP0 0x1600
+
+void lpc32xx_ssp_init(void)
+{
+ /* Enable SSP0 interface */
+ writel(CLK_SSP0_ENABLE_CLOCK, clk-ssp_ctrl);
+ /* Mux SSP0 pins */
+ writel(P_MUX_SET_SSP0, mux-p_mux_set);
+}
diff --git a/arch/arm/include/asm/arch-lpc32xx/clk.h
b/arch/arm/include/asm/arch-lpc32xx/clk.h
index 781ac07..2cb5703 100644
--- a/arch/arm/include/asm/arch-lpc32xx/clk.h
+++ b/arch/arm/include/asm/arch-lpc32xx/clk.h
@@ -155,6 +155,9 @@ struct clk_pm_regs {
#define CLK_NAND_MLC (1 1)
#define CLK_NAND_MLC_INT (1 5)
+/* SSP Clock Control Register bits */
+#define CLK_SSP0_ENABLE_CLOCK (1 0)
+
unsigned int get_sys_clk_rate(void);
unsigned int get_hclk_pll_rate(void);
unsigned int get_hclk_clk_div(void);
diff --git a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
index a4a05d1..86d5ee9 100644
--- a/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
+++ b/arch/arm/include/asm/arch-lpc32xx/sys_proto.h
@@ -11,5 +11,6 @@ void lpc32xx_uart_init(unsigned int uart_id);
void lpc32xx_mac_init(void);
void lpc32xx_mlc_nand_init(void);
void lpc32xx_i2c_init(unsigned int devnum);
+void lpc32xx_ssp_init(void);
#endif /* _LPC32XX_SYS_PROTO_H */
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index edbd520..ce6f1cc 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
obj-$(CONFIG_FTSSP010_SPI) += ftssp010_spi.o
obj-$(CONFIG_ICH_SPI) += ich.o
obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
+obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o
obj-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
obj-$(CONFIG_MXC_SPI) += mxc_spi.o
diff --git a/drivers/spi/lpc32xx_ssp.c b/drivers/spi/lpc32xx_ssp.c
new file mode 100644
index 000..40270df
--- /dev/null
+++ b/drivers/spi/lpc32xx_ssp.c
@@ -0,0 +1,132 @@
+/*
+ * LPC32xx SSP interface (SPI mode)
+ *
+ * (C) Copyright 2014 DENX Software Engineering GmbH
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include common.h
+#include linux/compat.h
+#include asm/io.h
+#include malloc.h
+#include spi.h
+#include asm/arch/clk.h
+
+/* SSP chip registers */
+struct ssp_regs {
+ u32 cr0;
+ u32 cr1;
+ u32 data;
+ u32 sr;
+ u32 cpsr;
+ u32 imsc;
+ u32 ris;
+ u32 mis;
+ u32 icr;
+ u32 dmacr;
+};
+
+/* CR1 register defines */
+#define SSP_CR1_SSP_ENABLE 0x0002
+
+/* SR register defines */
+#define SSP_SR_TNF 0x0002
+/* SSP status RX FIFO not empty bit */
+#define SSP_SR_RNE 0x0004
+
+static struct ssp_regs *ssp0_regs = (struct ssp_regs *)SSP0_BASE;
+
+static struct spi_slave ssp0_slave = {
+ .bus = 0,
+ .cs = 0,
+ .op_mode_rx = 0,
+ .op_mode_tx = 0,
+ .wordlen = 8,
+ .max_write_size = 1, /* this is for SPI FLASHes -- don't care */
+ .memory_map = NULL, /* for SPI FLASHes too */
+ .option = 0,
+ .flags = 0
+};
+
+/* spi_init is called during boot when CONFIG_CMD_SPI is defined */
+void spi_init(void)
+{
+ /*
+* nothing to do: clocking was enabled in lpc32xx_ssp_enable()
+* and configuration will be done in spi_setup_slave()
+ */
+}
+
+/* the following is called in sequence by do_spi_xfer() */
+
+struct spi_slave *spi_setup_slave(uint bus, uint cs, uint max_hz, uint mode)
+{
+ /* we only set up SSP0 for now, so ignore bus */
+
+ if (mode SPI_3WIRE) {
+ error(3-wire mode not supported);
+ return NULL;
+ }
+
+ if
[U-Boot] [PATCH v2 6/8] dtt: add ds620 support
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2:
- cosmetic: added a blank line before copyright
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 65 ++
include/dtt.h | 15 ++--
3 files changed, 74 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 25b8e8a..b4fb057 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_DTT_ADT7460) += adt7460.o
obj-$(CONFIG_DTT_DS1621) += ds1621.o
obj-$(CONFIG_DTT_DS1722) += ds1722.o
obj-$(CONFIG_DTT_DS1775) += ds1775.o
+obj-$(CONFIG_DTT_DS620) += ds620.o
obj-$(CONFIG_DTT_LM63) += lm63.o
obj-$(CONFIG_DTT_LM73) += lm73.o
obj-$(CONFIG_DTT_LM75) += lm75.o
diff --git a/drivers/hwmon/ds620.c b/drivers/hwmon/ds620.c
new file mode 100644
index 000..1ecc3da
--- /dev/null
+++ b/drivers/hwmon/ds620.c
@@ -0,0 +1,65 @@
+/*
+ * DS620 DTT support
+ *
+ * (C) Copyright 2014 3ADEV http://www.3adev.com
+ * Written-by: Albert ARIBAUD albert.arib...@3adev.fr
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * Dallas Semiconductor's DS1621/1631 Digital Thermometer and Thermostat.
+ */
+
+#include common.h
+#include i2c.h
+#include dtt.h
+
+/*
+ * Device code
+ */
+#define DTT_I2C_DEV_CODE 0x48
+#define DTT_START_CONVERT 0x51
+#define DTT_TEMP 0xAA
+#define DTT_CONFIG 0xAC
+
+/*
+ * Config register MSB bits
+ */
+#define DTT_CONFIG_1SHOT 0x01
+#define DTT_CONFIG_AUTOC 0x02
+#define DTT_CONFIG_R0 0x04 /* always 1 */
+#define DTT_CONFIG_R1 0x08 /* always 1 */
+#define DTT_CONFIG_TLF 0x10
+#define DTT_CONFIG_THF 0x20
+#define DTT_CONFIG_NVB 0x40
+#define DTT_CONFIG_DONE0x80
+
+#define CHIP(sensor) (DTT_I2C_DEV_CODE + (sensor 0x07))
+
+int dtt_init_one(int sensor)
+{
+ uint8_t config = DTT_CONFIG_1SHOT
+ | DTT_CONFIG_R0
+ | DTT_CONFIG_R1;
+ return i2c_write(CHIP(sensor), DTT_CONFIG, 1, config, 1);
+}
+
+int dtt_get_temp(int sensor)
+{
+ uint8_t status;
+ uint8_t temp[2];
+
+ /* Start a conversion, may take up to 1 second. */
+ i2c_write(CHIP(sensor), DTT_START_CONVERT, 1, NULL, 0);
+ do {
+ if (i2c_read(CHIP(sensor), DTT_CONFIG, 1, status, 1))
+ /* bail out if I2C error */
+ status |= DTT_CONFIG_DONE;
+ } while (!(status DTT_CONFIG_DONE));
+ if (i2c_read(CHIP(sensor), DTT_TEMP, 1, temp, 2))
+ /* bail out if I2C error */
+ return -274; /* below absolute zero == error */
+
+ return ((int16_t)(temp[1] | (temp[0] 8))) 7;
+}
diff --git a/include/dtt.h b/include/dtt.h
index 058bca4..173159d 100644
--- a/include/dtt.h
+++ b/include/dtt.h
@@ -12,13 +12,14 @@
#define _DTT_H_
#if defined(CONFIG_DTT_ADM1021)|| \
-defined(CONFIG_DTT_ADT7460)|| \
-defined(CONFIG_DTT_DS1621) || \
-defined(CONFIG_DTT_DS1775) || \
-defined(CONFIG_DTT_LM63) || \
-defined(CONFIG_DTT_LM73) || \
-defined(CONFIG_DTT_LM75) || \
-defined(CONFIG_DTT_LM81)
+ defined(CONFIG_DTT_ADT7460) || \
+ defined(CONFIG_DTT_DS1621) || \
+ defined(CONFIG_DTT_DS1775) || \
+ defined(CONFIG_DTT_DS620) || \
+ defined(CONFIG_DTT_LM63)|| \
+ defined(CONFIG_DTT_LM73)|| \
+ defined(CONFIG_DTT_LM75)|| \
+ defined(CONFIG_DTT_LM81)
#define CONFIG_DTT /* We have a DTT */
--
2.1.0
___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v2 8/8] lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x MAX518)
- SPI (through SSP interface)
- Port expander MAX6957
- LCD display (HD44780-compatible), controlled
through the port expander and DACs
This board has SPL support, and uses the LPC32XX boot
image format.
Signed-off-by: Albert ARIBAUD (3ADEV) albert.arib...@3adev.fr
---
Changes in v2: None
arch/arm/Kconfig | 6 +
arch/arm/cpu/arm926ejs/lpc32xx/Makefile| 2 +
arch/arm/cpu/arm926ejs/lpc32xx/clk.c | 34 ++
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 4 +
arch/arm/cpu/arm926ejs/lpc32xx/dram.c | 80 +
arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S | 45 +++
arch/arm/include/asm/arch-lpc32xx/clk.h| 5 +
arch/arm/include/asm/arch-lpc32xx/cpu.h| 1 +
arch/arm/include/asm/arch-lpc32xx/mux.h| 18 ++
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 4 +-
board/work-microwave/work_92105/Kconfig| 15 +
board/work-microwave/work_92105/MAINTAINERS| 6 +
board/work-microwave/work_92105/Makefile | 8 +
board/work-microwave/work_92105/README | 23 ++
board/work-microwave/work_92105/work_92105.c | 86 +
.../work-microwave/work_92105/work_92105_display.c | 349 +
.../work-microwave/work_92105/work_92105_display.h | 14 +
configs/work_92105_defconfig | 5 +
include/configs/work_92105.h | 259 +++
19 files changed, 963 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/dram.c
create mode 100644 arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
create mode 100644 arch/arm/include/asm/arch-lpc32xx/mux.h
create mode 100644 board/work-microwave/work_92105/Kconfig
create mode 100644 board/work-microwave/work_92105/MAINTAINERS
create mode 100644 board/work-microwave/work_92105/Makefile
create mode 100644 board/work-microwave/work_92105/README
create mode 100644 board/work-microwave/work_92105/work_92105.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.c
create mode 100644 board/work-microwave/work_92105/work_92105_display.h
create mode 100644 configs/work_92105_defconfig
create mode 100644 include/configs/work_92105.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 47806f8..42983a3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -247,6 +247,11 @@ config TARGET_DEVKIT3250
bool Support devkit3250
select CPU_ARM926EJS
+config TARGET_WORK_92105
+ bool Support work_92105
+ select CPU_ARM926EJS
+ select SUPPORT_SPL
+
config TARGET_JADECPU
bool Support jadecpu
select CPU_ARM926EJS
@@ -999,6 +1004,7 @@ source board/udoo/Kconfig
source board/vpac270/Kconfig
source board/wandboard/Kconfig
source board/woodburn/Kconfig
+source board/work-microwave/work_92105/Kconfig
source board/xaeniax/Kconfig
source board/zipitz2/Kconfig
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
index 314f004..4837377 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Makefile
@@ -6,3 +6,5 @@
#
obj-y = cpu.o clk.o devices.o timer.o
+
+obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
index b7a44d5..1ef8a36 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/clk.c
@@ -98,6 +98,40 @@ unsigned int get_periph_clk_rate(void)
return get_hclk_pll_rate() / get_periph_clk_div();
}
+unsigned int get_sdram_clk_rate(void)
+{
+ unsigned int src_clk;
+
+ if (!(readl(clk-pwr_ctrl) CLK_PWR_NORMAL_RUN))
+ return get_sys_clk_rate();
+
+ src_clk = get_hclk_pll_rate();
+
+ if (readl(clk-sdramclk_ctrl) CLK_SDRAM_DDR_SEL) {
+ /* using DDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_DDRAM_MASK) {
+ case CLK_HCLK_DDRAM_HALF:
+ return src_clk/2;
+ case CLK_HCLK_DDRAM_NOMINAL:
+ return src_clk;
+ default:
+ return 0;
+ }
+ } else {
+ /* using SDR */
+ switch (readl(clk-hclkdiv_ctrl) CLK_HCLK_ARM_PLL_DIV_MASK) {
+ case CLK_HCLK_ARM_PLL_DIV_4:
+ return src_clk/4;
+ case CLK_HCLK_ARM_PLL_DIV_2:
+ return src_clk/2;
+ case CLK_HCLK_ARM_PLL_DIV_1:
+ return src_clk;
+ default:
+ return 0;
+
