Re: [U-Boot] [PATCH 4/7] arm: Make new baltos board not break on savedefconfig
Hi Joe, On Wed, Jun 24, 2015 at 5:26 AM, Joe Hershberger wrote: > Hi Tom, > > On Tue, Jun 23, 2015 at 9:23 AM, Tom Rini wrote: >> On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote: >> >>> This config defined a CONS_INDEX as a config but did not define it in >>> any Kconfig, so savedefconfig will delete that entry. Use >>> CONFIG_SYS_EXTRA_OPTIONS for now until that is added to Kconfig. >>> >>> Signed-off-by: Joe Hershberger >>> --- >>> >>> configs/am335x_baltos_defconfig | 3 +-- >>> 1 file changed, 1 insertion(+), 2 deletions(-) >>> >>> diff --git a/configs/am335x_baltos_defconfig >>> b/configs/am335x_baltos_defconfig >>> index 679b04f..030cb51 100644 >>> --- a/configs/am335x_baltos_defconfig >>> +++ b/configs/am335x_baltos_defconfig >>> @@ -1,7 +1,6 @@ >>> CONFIG_SPL=y >>> CONFIG_SPL_STACK_R=y >>> CONFIG_SPL_STACK_R_ADDR=0x8200 >>> -CONFIG_SYS_EXTRA_OPTIONS="NAND" >>> -CONFIG_CONS_INDEX=1 >>> +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND" >>> CONFIG_ARM=y >>> CONFIG_TARGET_AM335X_BALTOS=y >> >> No, something else is wrong. board/vscom/baltos/Kconfig has CONS_INDEX >> (like the other am335x boards and yes this needs moving to a better >> place). > > Any thoughts on what's wrong, then? I'm at FTF this week and won't be > debugging it until next week. There was an issue with this board, > caused by savedefconfig, which is why I even noticed this board exists > now. Maybe whoever added it (Yegor Yefremov) didn't try safedefconfig > against the board? > > If nothing else, at least this makes it consistent with all other > boards that specify CONS_INDEX. At least they don't break. I'll take a look at this. Yegor ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 22/25] rockchip: Add SPI driver
On 24 June 2015 at 04:59, Simon Glass wrote:
> Add a SPI driver for the Rockchip RK3288, using driver model. It should work
> for other Rockchip SoCs also.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/spi/Kconfig | 10 ++
> drivers/spi/Makefile | 1 +
> drivers/spi/rk_spi.c | 375
> +++
> drivers/spi/rk_spi.h | 121 +
> 4 files changed, 507 insertions(+)
> create mode 100644 drivers/spi/rk_spi.c
> create mode 100644 drivers/spi/rk_spi.h
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 357a335..52e1a56 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -51,3 +51,13 @@ config CADENCE_QSPI
> Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
> used to access the SPI NOR flash on platforms embedding this
> Cadence IP core.
> +
> +config ROCKCHIP_SPI
> + bool "Rockchip SPI driver"
> + depends on DM_SPI
> + help
> + Enable the Rockchip SPI driver, used to access SPI NOR flash and
> + other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
> + This uses driver model and requires a device tree binding to
> + operate.
> +
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index e288692..2d74ca4 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
> obj-$(CONFIG_SH_SPI) += sh_spi.o
> obj-$(CONFIG_SH_QSPI) += sh_qspi.o
> obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
> +obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
> obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
> obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
> obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
> diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
> new file mode 100644
> index 000..7ef0d63
> --- /dev/null
> +++ b/drivers/spi/rk_spi.c
> @@ -0,0 +1,375 @@
> +/*
> + * spi driver for rockchip
> + *
> + * (C) Copyright 2015 Google, Inc
> + *
> + * (C) Copyright 2008-2013 Rockchip Electronics
> + * Peter, Software Engineering, .
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "rk_spi.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
Just move the code from .h to here, I'm always considered the driver
code be part of single file ie good for reading and maintenance of-course
not for too much big code like cadence_spi
> +
> +struct rockchip_spi_platdata {
> + enum periph_id periph_id;
> + struct udevice *pinctrl;
> + s32 frequency; /* Default clock frequency, -1 for none */
> + fdt_addr_t base;
> + uint deactivate_delay_us; /* Delay to wait after deactivate */
> +};
> +
> +struct rockchip_spi_priv {
> + struct rockchip_spi *regs;
> + struct udevice *clk_gpll;
> + unsigned int max_freq;
> + unsigned int mode;
> + enum periph_id periph_id; /* Peripheral ID for this device */
> + ulong last_transaction_us; /* Time of last transaction end */
> + u8 bits_per_word; /* max 16 bits per word */
> + u8 n_bytes;
> + unsigned int speed_hz;
> + unsigned int tmode;
> + uint input_rate;
> +};
> +
> +#define SPI_FIFO_DEPTH 32
> +
> +static void rkspi_dump_regs(struct rockchip_spi *regs)
> +{
> + debug("RK SPI registers:\n");
> + debug("=\n");
Unnecessary debugs's since we know this is reg dump why we specify.
> + debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
> + debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
> + debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
> + debug("ser: \t\t0x%08x\n", readl(®s->ser));
> + debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
> + debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
> + debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
> + debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
> + debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
> + debug("sr: \t\t0x%08x\n", readl(®s->sr));
> + debug("imr: \t\t0x%08x\n", readl(®s->imr));
> + debug("isr: \t\t0x%08x\n", readl(®s->isr));
> + debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
> + debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
> + debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
> + debug("=\n");
-- ditto
> +}
> +
> +static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
> +{
> + writel(enable ? 1 : 0, ®s->enr);
> +}
> +
> +static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
> +{
> + uint clk_div;
> +
> + clk_div = priv->input_rate / speed;
> + clk_div = (clk_div + 1) & 0xfffe;
> + debug("spi speed %u, div %u\n", speed, clk_div);
> +
> +
[U-Boot] [PATCH] drivers: usb: fsl: Remove LS102XA immap inclusion
Remove LS102XA immap header inclusion from xhci fsl driver. It removes redefinition warnings when built for platforms other than LS102XA Signed-off-by: Nikhil Badola --- drivers/usb/host/xhci-fsl.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/xhci-fsl.c index 6781b94..6481e07 100644 --- a/drivers/usb/host/xhci-fsl.c +++ b/drivers/usb/host/xhci-fsl.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include -- 2.1.0 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 11/11] dm: x86: baytrail: Correct PCI region 3 when driver model is used
Hi Simon, On Wed, Jun 24, 2015 at 11:23 AM, Simon Glass wrote: > Hi, > > On 8 June 2015 at 06:32, Andrew Bradford wrote: >> Hi Bin / Simon, >> >> On 06/08 10:57, Bin Meng wrote: >>> Hi Simon, >>> >>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote: >>> > Commit afbbd413a fixed this for non-driver-model. Make sure that the >>> > driver >>> > model code handles this also. >>> > >>> > Signed-off-by: Simon Glass >>> > --- >>> > >>> > drivers/pci/pci-uclass.c | 3 ++- >>> > 1 file changed, 2 insertions(+), 1 deletion(-) >>> > >>> > diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c >>> > index edec93f..4255c02 100644 >>> > --- a/drivers/pci/pci-uclass.c >>> > +++ b/drivers/pci/pci-uclass.c >>> > @@ -495,7 +495,8 @@ static int decode_regions(struct pci_controller >>> > *hose, const void *blob, >>> > >>> > /* Add a region for our local memory */ >>> > pci_set_region(hose->regions + hose->region_count++, 0, 0, >>> > - gd->ram_size, PCI_REGION_MEM | >>> > PCI_REGION_SYS_MEMORY); >>> > + gd->ram_size < 0x8000U ? gd->ram_size : >>> > 0x8000U, >>> > + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); >>> > >>> > return 0; >>> > } >>> > -- >>> >>> I think this is specific to baytrail fsp configuration. It should not >>> be put into a common driver. >> >> Yes, I agree with Bin, this is likely only a Bay Trail (or maybe a very >> small number of other processors) configuration. I believe your change >> here will impact all PCI hosts which have > 2 GiB of RAM. >> >> It might be a bit ugly to have an #ifdef in this file, it all seems like >> nice clean generic code. But maybe it's not a big deal to limit all >> u-boot to 2 GiB of RAM for this region? > Yep, maybe not a big deal, but it may also break some boards if the allocated buffer for PCI device happens to be above 2 GiB, but that case might be rare (ie: like 3 GiB memory is installed where on most cases we only see boards with 1 GiB, 2 GiB, 4 GiB memory) > Yes, this will bite us when something else moves PCI to driver model > and we may as well fix it now. > > What is the best option? We could add a pci_max_addr to global_data > perhaps? This could be set to ram_size for most machines, and adjusted > for x86. I'd prefer to avoid #ifdef CONFIG_X86. Adding pci_max_addr to global_data sounds good if we want to avoid #ifdefs. It would be good to hear more comments from other domains? Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 25/25] rockchip: Add a simple README
Hi, On Wed, Jun 24, 2015 at 8:29 AM, Simon Glass wrote: > Add a few notes on how to try out the Rockchip support so far. > > Signed-off-by: Simon Glass > --- > > Changes in v3: > - Update README to mention available drivers > - Add various new patches to get RK3288 booting to a prompt > > Changes in v2: None > > doc/README.rockchip | 246 > > 1 file changed, 246 insertions(+) > create mode 100644 doc/README.rockchip > > diff --git a/doc/README.rockchip b/doc/README.rockchip > new file mode 100644 > index 000..a34e198 > --- /dev/null > +++ b/doc/README.rockchip > @@ -0,0 +1,246 @@ > +# > +# Copyright (C) 2015 Google. Inc > +# Written by Simon Glass > +# > +# SPDX-License-Identifier: GPL-2.0+ > +# > + > +U-Boot on Rockchip > +== > + > +There are several repositories available with versions of U-Boot that support > +many Rockchip devices [1] [2]. > + > +The current mainline support is experimental only and is not useful for > +anything. It should provide a base on which to build. > + > +So far only support for the RK3288 is provided. > + > + > +Prerequisites > += > + > +You will need: > + > + - Firefly RK3288 baord > + - Power connection to 5V using the supplied micro-USB power cable > + - Separate USB serial cable attached to your computer and the Firefly > +(connect to the micro-USB connector below the logo) > + - rkflashtool [3] > + - openssl (sudo apt-get install openssl) > + - Serial UART connection [4] > + - Suitable ARM cross compiler, e.g.: > +sudo apt-get install gcc-4.7-arm-linux-gnueabi > + > + > +Building > + > + > +At present three RK3288 boards are supported: > + > + - Firefly RK3288 - use firefly-rk3288 configuration > + - Radxa Rock Pro - also uses firefly-rk3288 configuration > + - Haier Chromebook - use chromebook_jerry configuration > + > +For example: > + > + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig > all > + > +(or you can use another cross compiler if you prefer) > + > +Note that the Radxa Rock Pro uses the Firefly configuration for now as > +device tree files are not yet available for the Rock Pro. Clearly the two > +have hardware differences, so this approach will break down as more drivers > +are added. > + > + > +Writing to the board with USB > += > + > +For USB to work you must get your board into ROM boot mode, either by erasing > +your MMC or (perhaps) holding the recovery button when you boot the board. "holding the recovery" method will load & run loader from flash storage (if available). if my memory is correct, SPL cannot be loaded in this case. (rkflashtool l doesn't work) if working (Rockchip's) loader is already loaded, "rkflashtool b 3" might work to enter mask rom mode. https://github.com/linux-rockchip/rkflashtool/commit/f6159af25af766374e1d8a2cb2901d522102b8b8 I'll check it later. > +To erase your MMC, you can boot into Linux and type (as root) > + > + dd if=/dev/zero of=/dev/mmcblk0 bs=1M > + > +Connect your board's OTG port to your computer. > + > +To create a suitable image and write it to the board: > + > + ./firefly-rk3288/tools/mkimage -T rkimage -d > ./firefly-rk3288/spl/u-boot-spl-dtb.bin out > + cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l > + > +If all goes well you should something like: > + > + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 10:06:49) > + Card did not respond to voltage select! > + spl: mmc init failed with error: -17 > + ### ERROR ### Please RESET the board ### > + > +You will need to reset the board before each time you try. Yes, that's all > +it does so far. If support for the Rockchip USB protocol or DFU were added > +in SPL then we could in principle load U-Boot and boot to a prompt from USB > +as several other platforms do. However it does not seem to be possible to > +use the existing boot ROM code from SPL. > + > + > +Booting from an SD card > +=== > + > +To write an image that boots from an SD card (assumed to be /dev/sdc): > + > + ./firefly-rk3288/tools/mkimage -T rksd -d > firefly-rk3288/spl/u-boot-spl-dtb.bin out > + sudo dd if=out of=/dev/sdc > + sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 > + > +This puts the Rockchip header and SPL image first and then places the U-Boot > +image at block 256 (i.e. 128KB from the start of the SD card). This > +corresponds with this setting in U-Boot: > + > + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 > + > +Put this SD (or micro-SD) card into your board and reset it. You should see > +something like: > + > + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) > + > + > + U-Boot 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) > + > + DRAM: 2 GiB > + MMC: > + Using default environment > + > + In:serial@ff69 > + Out: serial@ff6900
Re: [U-Boot] [PATCH v3 06/25] rockchip: Add the rkimage format to mkimage
Hi,
On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote:
> Rockchip SoCs require certain formats for code that they execute, The
> simplest format is a 4-byte header at the start of a binary file. Add
> support for this so that we can create images that the boot ROM understands.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> common/image.c | 1 +
> include/image.h | 3 ++-
> tools/Makefile | 3 +++
> tools/rkcommon.c | 72
>
> tools/rkcommon.h | 28 ++
> tools/rkimage.c | 65 ++
> 6 files changed, 171 insertions(+), 1 deletion(-)
> create mode 100644 tools/rkcommon.c
> create mode 100644 tools/rkcommon.h
> create mode 100644 tools/rkimage.c
>
> diff --git a/common/image.c b/common/image.c
> index 9efacf8..1114206 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -151,6 +151,7 @@ static const table_entry_t uimage_type[] = {
> { IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",},
> { IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin",},
> { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image",
> },
> + { IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
> { -1, "", "", },
> };
>
> diff --git a/include/image.h b/include/image.h
> index 63c3d37..2daa74a 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -245,8 +245,9 @@ struct lmb;
> #define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
> #define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
> #define IH_TYPE_LOADABLE 22 /* A list of typeless images*/
> +#define IH_TYPE_RKIMAGE23 /* Rockchip Boot Image
> */
>
> -#define IH_TYPE_COUNT 23 /* Number of image types */
> +#define IH_TYPE_COUNT 24 /* Number of image types */
>
> /*
> * Compression Types
> diff --git a/tools/Makefile b/tools/Makefile
> index 98414f7..55c8ae1 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -64,6 +64,8 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
> rsa-sign.o rsa-verify.o
> rsa-checksum.o \
> rsa-mod-exp.o)
>
> +ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o
> +
> # common objs for dumpimage and mkimage
> dumpimage-mkimage-objs := aisimage.o \
> atmelimage.o \
> @@ -90,6 +92,7 @@ dumpimage-mkimage-objs := aisimage.o \
> os_support.o \
> pblimage.o \
> pbl_crc32.o \
> + $(ROCKCHIP_OBS) \
> socfpgaimage.o \
> lib/sha1.o \
> lib/sha256.o \
> diff --git a/tools/rkcommon.c b/tools/rkcommon.c
> new file mode 100644
> index 000..4389622
> --- /dev/null
> +++ b/tools/rkcommon.c
> @@ -0,0 +1,72 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Written by Simon Glass
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + * Helper functions for Rockchip images
> + */
> +
> +#include "imagetool.h"
> +#include
> +#include
> +#include "mkimage.h"
> +#include "rkcommon.h"
> +
> +enum {
> + RK_SIGNATURE= 0x0ff0aa55,
> +};
> +
> +/**
> + * struct header0_info - header block for boot ROM
this block should be called as ID Block sector 0.
(if you just followed name of my old SD boot image file, sorry)
> + *
> + * This is stored at SD card block 64 (where each block is 512 bytes, or at
> + * the start of SPI flash. It is encoded with RC4.
> + *
> + * @signature: Signature (must be RKSD_SIGNATURE)
> + * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
> + * @code1_offset: Offset in blocks of the SPL code from this header
> + * block. E.g. 4 means 2KB after the start of this
> header.
> + * Other fields are not used by U-Boot
(this is just a question)
2nd code block is not loaded to DRAM by mask rom?
as like as "rkflashtool L" thing, I thought(just imagined) this block
is loaded by mask rom, not by 1st code block (on SRAM).
> + */
> +struct header0_info {
> + uint32_t signature;
> + uint8_t reserved[4];
> + uint32_t disable_rc4;
> + uint16_t code1_offset;
> + uint16_t code2_offset;
> + uint8_t reserved1[490];
> + uint16_t usflashdatasize;
> + uint16_t ucflashbootsize;
> + uint8_t reserved2[2];
> +};
> +
> +static unsigned char rc4_key[16] = {
> + 124, 78, 3, 4, 85, 5, 9, 7,
> + 45, 44, 123, 56, 23, 13, 23, 17
> +};
> +
> +int rkcommon_set_header(void *buf, uint file_size)
> +{
> + struct header0_info *hdr;
> +
> + if (file_size > RK_MAX_CODE1_SIZE)
> + return -ENOSPC;
> +
> +
Re: [U-Boot] [PATCH v3 08/25] rockchip: Add support for the SPI image
Hi,
On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote:
> The Rockchip boot ROM requires a particular file format for booting from SPI.
> It consists of a 512-byte header encoded with RC4, some padding and then up
> to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
>
> Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
> converted to this format. This allows booting from SPI flash on supported
> machines.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> common/image.c | 1 +
> include/image.h | 3 +-
> tools/rkspi.c | 119
>
> 3 files changed, 122 insertions(+), 1 deletion(-)
> create mode 100644 tools/rkspi.c
>
> diff --git a/common/image.c b/common/image.c
> index 85b88b2..bcb1a12 100644
> --- a/common/image.c
> +++ b/common/image.c
> @@ -153,6 +153,7 @@ static const table_entry_t uimage_type[] = {
> { IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image",
> },
> { IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
> { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
> + { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
> { -1, "", "", },
> };
>
> diff --git a/include/image.h b/include/image.h
> index ea16205..b4c4fd7 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -247,8 +247,9 @@ struct lmb;
> #define IH_TYPE_LOADABLE 22 /* A list of typeless images*/
> #define IH_TYPE_RKIMAGE23 /* Rockchip Boot Image
> */
> #define IH_TYPE_RKSD 24 /* Rockchip SD card */
> +#define IH_TYPE_RKSPI 25 /* Rockchip SD card */
sorry for nitpicking,
"Rockchip SPI image" ?
>
> -#define IH_TYPE_COUNT 25 /* Number of image types */
> +#define IH_TYPE_COUNT 26 /* Number of image types */
>
> /*
> * Compression Types
> diff --git a/tools/rkspi.c b/tools/rkspi.c
> new file mode 100644
> index 000..a3c4c73
> --- /dev/null
> +++ b/tools/rkspi.c
> @@ -0,0 +1,119 @@
> +/*
> + * (C) Copyright 2015 Google, Inc
> + * Written by Simon Glass
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + *
> + * See README.rockchip for details of the rkspi format
> + */
> +
> +#include "imagetool.h"
> +#include
> +#include
> +#include "mkimage.h"
> +#include "rkcommon.h"
> +
> +enum {
> + RKSPI_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE,
> + RKSPI_SPL_START = RKSPI_SPL_HDR_START + 4,
> + RKSPI_HEADER_LEN= RKSPI_SPL_START,
> + RKSPI_SECT_LEN = RK_BLK_SIZE * 4,
> +};
> +
> +static char dummy_hdr[RKSPI_HEADER_LEN];
> +
> +static int rkspi_check_params(struct image_tool_params *params)
> +{
> + return 0;
> +}
> +
> +static int rkspi_verify_header(unsigned char *buf, int size,
> + struct image_tool_params *params)
> +{
> + return 0;
> +}
> +
> +static void rkspi_print_header(const void *buf)
> +{
> +}
> +
> +static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd,
> +struct image_tool_params *params)
> +{
> + int sector;
> + unsigned int size;
> + int ret;
> +
> + size = params->orig_file_size;
> + ret = rkcommon_set_header(buf, size);
> + debug("size %x\n", size);
> + if (ret) {
> + /* TODO(s...@chromium.org): This method should return an
> error */
> + printf("Warning: SPL image is too large (size %#x) and will
> not boot\n",
> + size);
> + }
> +
> + memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4);
> +
> + /*
> +* Spread the image out so we only use the first 2KB of each 4KB
> +* region. This is a feature of the SPI format required by the
> Rockchip
> +* boot ROM. Its rationale is unknown.
> +*/
> + for (sector = size / RKSPI_SECT_LEN - 1; sector >= 0; sector--) {
> + printf("sector %u\n", sector);
> + memmove(buf + sector * RKSPI_SECT_LEN * 2,
> + buf + sector * RKSPI_SECT_LEN,
> + RKSPI_SECT_LEN);
> + memset(buf + sector * RKSPI_SECT_LEN * 2 + RKSPI_SECT_LEN,
> + '\0', RKSPI_SECT_LEN);
> + }
> +}
> +
> +static int rkspi_extract_subimage(void *buf, struct image_tool_params
> *params)
> +{
> + return 0;
> +}
> +
> +static int rkspi_check_image_type(uint8_t type)
> +{
> + if (type == IH_TYPE_RKSPI)
> + return EXIT_SUCCESS;
> + else
> + return EXIT_FAILURE;
> +}
> +
> +/* We pad the file out to a fixed size - this method returns that size */
> +static int rkspi_vrec_header(struct image_tool_params *params,
> +struct image_type_params *tpar
Re: [U-Boot] [PATCH v3 00/25] dm: Introduce Rockchip RK3288 support
Hi, On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote: > Since much of the code is generic, this also supports the Radxa Rock Pro. > Since there is no device tree available for that yet, it uses the same > config and device tree as the Firefly. This works because not all > peripherals are supported, so the differences don't matter. https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/rk3188-radxarock.dts this should be ok for all Radxa Rock(1) boards. > Support for booting from USB OTG is also provided, using the on-chip boot > ROM and the rkflashtool utility. This can boot as far as SPL, but there is > no support for reading U-Boot proper from USB as yet. This requires > implementing a suitable protocol (perhaps DFU or Rockchip's proprietary > one) in SPL. https://github.com/linux-rockchip/rkflashtool/commit/6da95a860e856e559310a6d96830eb687c23a132 "rkflashtool L" doesn't work after running your SPL code? I thought(just imagined, no confirmation) mask rom does the work after DRAM is initialized. > There is a large amount of additional work to bring other Rockchip drivers > and features into mainline U-Boot, so this is only a start. this is great start! :) Best Regards, ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/11] x86: pci: Tidy up the generic x86 PCI driver
Hi Simon,
On Wed, Jun 24, 2015 at 11:54 AM, Simon Glass wrote:
> Hi Bin,
>
> On 23 June 2015 at 21:46, Bin Meng wrote:
>> Hi Simon,
>>
>> On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>> On 7 June 2015 at 20:15, Bin Meng wrote:
Hi Simon,
On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
> This driver should use the x86 PCI configuration functions. Also adjust
> its
> compatible string to something generic (i.e. without a vendor name).
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci_x86.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
> index 901bdca..9f842c3 100644
> --- a/drivers/pci/pci_x86.c
> +++ b/drivers/pci/pci_x86.c
> @@ -7,12 +7,15 @@
> #include
> #include
> #include
> +#include
>
> static const struct dm_pci_ops x86_pci_ops = {
To keep the consistent naming to match the driver name, can we rename
this to pci_x86_ops?
>>>
>>> OK
>>>
> + .read_config= pci_x86_read_config,
> + .write_config = pci_x86_write_config,
Can we move pci_x86_read_config() and pci_x86_write_config() from
arch/x86/cpu/pci.c to this file to make it a complete driver file?
Also create a new header file pci_x86.h to declare these two so that
it can be used by ivybridge.
>>>
>>> I can certainly drop the ivybridge duplication. But I don't think it
>>> is right to call directly into a driver in drivers/...
>>>
>>> We should use driver model for this if we want to do it properly. I
>>> would like to continue the work to move x86 fully to driver model.
>>>
>>> In the meantime I think that directly called functions should be in
>>> arch/x86.
>>>
>>
>> Sorry I don't get it. I mean moving the implementation of
>> pci_x86_read_config() and pci_x86_write_config() to
>> drivers/pci/pci_x86.c. Do you have some concern about this?
>>
>> [snip]
>
> Yes it is still used by arch/x86/cpu/coreboot/pci.c - and as I say I
> don't like the 'call directly into driver' idea. If we could remove
> the coreboot case then it would be fine.
Why not we drop this coreboot pci driver (arch/x86/cpu/coreboot/pci.c)
and use the new one (drivers/pci/pci_x86.c) directly?
Regards,
Bin
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Re: [U-Boot] [PATCH 07/11] x86: pci: Tidy up the generic x86 PCI driver
Hi Bin,
On 23 June 2015 at 21:46, Bin Meng wrote:
> Hi Simon,
>
> On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 7 June 2015 at 20:15, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass
---
drivers/pci/pci_x86.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
index 901bdca..9f842c3 100644
--- a/drivers/pci/pci_x86.c
+++ b/drivers/pci/pci_x86.c
@@ -7,12 +7,15 @@
#include
#include
#include
+#include
static const struct dm_pci_ops x86_pci_ops = {
>>>
>>> To keep the consistent naming to match the driver name, can we rename
>>> this to pci_x86_ops?
>>
>> OK
>>
>>>
+ .read_config= pci_x86_read_config,
+ .write_config = pci_x86_write_config,
>>>
>>> Can we move pci_x86_read_config() and pci_x86_write_config() from
>>> arch/x86/cpu/pci.c to this file to make it a complete driver file?
>>> Also create a new header file pci_x86.h to declare these two so that
>>> it can be used by ivybridge.
>>
>> I can certainly drop the ivybridge duplication. But I don't think it
>> is right to call directly into a driver in drivers/...
>>
>> We should use driver model for this if we want to do it properly. I
>> would like to continue the work to move x86 fully to driver model.
>>
>> In the meantime I think that directly called functions should be in arch/x86.
>>
>
> Sorry I don't get it. I mean moving the implementation of
> pci_x86_read_config() and pci_x86_write_config() to
> drivers/pci/pci_x86.c. Do you have some concern about this?
>
> [snip]
Yes it is still used by arch/x86/cpu/coreboot/pci.c - and as I say I
don't like the 'call directly into driver' idea. If we could remove
the coreboot case then it would be fine.
Regards,
Simon
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Re: [U-Boot] [PATCH 07/11] x86: pci: Tidy up the generic x86 PCI driver
Hi Simon,
On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
> Hi Bin,
>
> On 7 June 2015 at 20:15, Bin Meng wrote:
>> Hi Simon,
>>
>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>>> This driver should use the x86 PCI configuration functions. Also adjust its
>>> compatible string to something generic (i.e. without a vendor name).
>>>
>>> Signed-off-by: Simon Glass
>>> ---
>>>
>>> drivers/pci/pci_x86.c | 5 -
>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
>>> index 901bdca..9f842c3 100644
>>> --- a/drivers/pci/pci_x86.c
>>> +++ b/drivers/pci/pci_x86.c
>>> @@ -7,12 +7,15 @@
>>> #include
>>> #include
>>> #include
>>> +#include
>>>
>>> static const struct dm_pci_ops x86_pci_ops = {
>>
>> To keep the consistent naming to match the driver name, can we rename
>> this to pci_x86_ops?
>
> OK
>
>>
>>> + .read_config= pci_x86_read_config,
>>> + .write_config = pci_x86_write_config,
>>
>> Can we move pci_x86_read_config() and pci_x86_write_config() from
>> arch/x86/cpu/pci.c to this file to make it a complete driver file?
>> Also create a new header file pci_x86.h to declare these two so that
>> it can be used by ivybridge.
>
> I can certainly drop the ivybridge duplication. But I don't think it
> is right to call directly into a driver in drivers/...
>
> We should use driver model for this if we want to do it properly. I
> would like to continue the work to move x86 fully to driver model.
>
> In the meantime I think that directly called functions should be in arch/x86.
>
Sorry I don't get it. I mean moving the implementation of
pci_x86_read_config() and pci_x86_write_config() to
drivers/pci/pci_x86.c. Do you have some concern about this?
[snip]
Regards,
Bin
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Re: [U-Boot] [PATCH 7/7] Move defaults from config_cmd_default.h to Kconfig
Hi Tom, On Tue, Jun 23, 2015 at 9:33 AM, Tom Rini wrote: > On Mon, Jun 22, 2015 at 04:15:30PM -0500, Joe Hershberger wrote: > >> This sets the default commands Kconfig to match >> include/config_cmd_default.h commands in the common/Kconfig and removes >> them from include/configs. > [snip] >> diff --git a/common/Kconfig b/common/Kconfig >> index cb14592..2976cd7 100644 >> --- a/common/Kconfig >> +++ b/common/Kconfig > [snip] >> config CMD_IMLS >> bool "imls" >> + default y >> help >> List all images found in flash > [snip] >> >> config CMD_FLASH >> bool "flinfo, erase, protect" >> + default y >> help >> NOR flash support. >> flinfo - print FLASH memory information > > Today we only set these when !SYS_NO_FLASH so we need to Kconfig that > first. While that's true, the moveconfig tool will de-select that option based on SYS_NO_FLASH having been set for that board. While that may not be ideal as far as reacting to an end-user changing that default setting for a given board, the defconfig itself should be consistent with the former default behavior. Also, once SYS_NO_FLASH is moved, such defconfig entries will be removed automatically by savedefconfig. I was trying to limit the number of changes included in this already sizable undertaking. If you feel it's important to include moving this change at the same time, then I can add a patch at the end of the series to include this move. >> @@ -352,6 +371,7 @@ menu "Network commands" >> config CMD_NET >> bool "bootp, tftpboot" >> select NET >> + default y >> help >> Network commands. >> bootp - boot image via network using BOOTP/TFTP protocol >> @@ -379,6 +399,7 @@ config CMD_DHCP >> >> config CMD_NFS >> bool "nfs" >> + default y >> help >> Boot image via network using NFS protocol. > > I think we now have the smarts available to us to do this only if we > have NET set, so "depends NET", yes? Sure. It could also be a follow-on, though, right? I'm just a bit hesitant to redo all of this, since it really takes a long time to validate (and still may not be perfect). I need a new build machine. :/ -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 10/11] dm: pci: Correct bus number when scanning sub-buses
On 7 June 2015 at 08:50, Simon Glass wrote: > The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it > so that sub-buses are numbered correctly. > > Signed-off-by: Simon Glass > --- > > drivers/pci/pci-uclass.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to u-boot-86. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/7] arm: Make new baltos board not break on savedefconfig
Hi Tom, On Tue, Jun 23, 2015 at 9:23 AM, Tom Rini wrote: > On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote: > >> This config defined a CONS_INDEX as a config but did not define it in >> any Kconfig, so savedefconfig will delete that entry. Use >> CONFIG_SYS_EXTRA_OPTIONS for now until that is added to Kconfig. >> >> Signed-off-by: Joe Hershberger >> --- >> >> configs/am335x_baltos_defconfig | 3 +-- >> 1 file changed, 1 insertion(+), 2 deletions(-) >> >> diff --git a/configs/am335x_baltos_defconfig >> b/configs/am335x_baltos_defconfig >> index 679b04f..030cb51 100644 >> --- a/configs/am335x_baltos_defconfig >> +++ b/configs/am335x_baltos_defconfig >> @@ -1,7 +1,6 @@ >> CONFIG_SPL=y >> CONFIG_SPL_STACK_R=y >> CONFIG_SPL_STACK_R_ADDR=0x8200 >> -CONFIG_SYS_EXTRA_OPTIONS="NAND" >> -CONFIG_CONS_INDEX=1 >> +CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1,NAND" >> CONFIG_ARM=y >> CONFIG_TARGET_AM335X_BALTOS=y > > No, something else is wrong. board/vscom/baltos/Kconfig has CONS_INDEX > (like the other am335x boards and yes this needs moving to a better > place). Any thoughts on what's wrong, then? I'm at FTF this week and won't be debugging it until next week. There was an issue with this board, caused by savedefconfig, which is why I even noticed this board exists now. Maybe whoever added it (Yegor Yefremov) didn't try safedefconfig against the board? If nothing else, at least this makes it consistent with all other boards that specify CONS_INDEX. At least they don't break. -Joe ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 09/11] dm: pci: Use the correct hose when configuring devices
On 7 June 2015 at 08:50, Simon Glass wrote: > Only the PCI controller has access to the PCI region information. Make sure > to use the controller (rather than any attached bridges) when configuring > devices. > > This corrects a failure to scan and configure devices when driver model is > enabled for PCI. > > Also add a comment to explain the problem. > > Signed-off-by: Simon Glass > --- > > drivers/pci/pci-uclass.c | 6 +- > drivers/pci/pci_common.c | 6 ++ > include/pci.h| 10 ++ > 3 files changed, 21 insertions(+), 1 deletion(-) Applied to u-boot-86. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 11/11] dm: x86: baytrail: Correct PCI region 3 when driver model is used
Hi, On 8 June 2015 at 06:32, Andrew Bradford wrote: > Hi Bin / Simon, > > On 06/08 10:57, Bin Meng wrote: >> Hi Simon, >> >> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote: >> > Commit afbbd413a fixed this for non-driver-model. Make sure that the driver >> > model code handles this also. >> > >> > Signed-off-by: Simon Glass >> > --- >> > >> > drivers/pci/pci-uclass.c | 3 ++- >> > 1 file changed, 2 insertions(+), 1 deletion(-) >> > >> > diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c >> > index edec93f..4255c02 100644 >> > --- a/drivers/pci/pci-uclass.c >> > +++ b/drivers/pci/pci-uclass.c >> > @@ -495,7 +495,8 @@ static int decode_regions(struct pci_controller *hose, >> > const void *blob, >> > >> > /* Add a region for our local memory */ >> > pci_set_region(hose->regions + hose->region_count++, 0, 0, >> > - gd->ram_size, PCI_REGION_MEM | >> > PCI_REGION_SYS_MEMORY); >> > + gd->ram_size < 0x8000U ? gd->ram_size : >> > 0x8000U, >> > + PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); >> > >> > return 0; >> > } >> > -- >> >> I think this is specific to baytrail fsp configuration. It should not >> be put into a common driver. > > Yes, I agree with Bin, this is likely only a Bay Trail (or maybe a very > small number of other processors) configuration. I believe your change > here will impact all PCI hosts which have > 2 GiB of RAM. > > It might be a bit ugly to have an #ifdef in this file, it all seems like > nice clean generic code. But maybe it's not a big deal to limit all > u-boot to 2 GiB of RAM for this region? Yes, this will bite us when something else moves PCI to driver model and we may as well fix it now. What is the best option? We could add a pci_max_addr to global_data perhaps? This could be set to ram_size for most machines, and adjusted for x86. I'd prefer to avoid #ifdef CONFIG_X86. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 07/11] x86: pci: Tidy up the generic x86 PCI driver
Hi Bin,
On 7 June 2015 at 20:15, Bin Meng wrote:
> Hi Simon,
>
> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>> This driver should use the x86 PCI configuration functions. Also adjust its
>> compatible string to something generic (i.e. without a vendor name).
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> drivers/pci/pci_x86.c | 5 -
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/pci/pci_x86.c b/drivers/pci/pci_x86.c
>> index 901bdca..9f842c3 100644
>> --- a/drivers/pci/pci_x86.c
>> +++ b/drivers/pci/pci_x86.c
>> @@ -7,12 +7,15 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> static const struct dm_pci_ops x86_pci_ops = {
>
> To keep the consistent naming to match the driver name, can we rename
> this to pci_x86_ops?
OK
>
>> + .read_config= pci_x86_read_config,
>> + .write_config = pci_x86_write_config,
>
> Can we move pci_x86_read_config() and pci_x86_write_config() from
> arch/x86/cpu/pci.c to this file to make it a complete driver file?
> Also create a new header file pci_x86.h to declare these two so that
> it can be used by ivybridge.
I can certainly drop the ivybridge duplication. But I don't think it
is right to call directly into a driver in drivers/...
We should use driver model for this if we want to do it properly. I
would like to continue the work to move x86 fully to driver model.
In the meantime I think that directly called functions should be in arch/x86.
>
>> };
>>
>> static const struct udevice_id x86_pci_ids[] = {
>
> Can we rename this to pci_x86_ids?
OK
>
>> - { .compatible = "x86,pci" },
>> + { .compatible = "pci-x86" },
>> { }
>> };
>>
>> --
>
Regards,
Simon
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Re: [U-Boot] BTRFS support in u-boot?
Hi, On 4 June 2015 at 10:32, Joakim Tjernlund wrote: > I have seen btrfs patches for u-boot flying around a year ago or so then > it went silent. Is there any efforts ongoing to add btrfs support to u-boot? > > Jocke I'm not sure. It would be good to get that in - if someone reposts I am willing to review it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ls2085a: esdhc: flush D-cache before 'mmc read'
It needs to flush D-cache before 'mmc read' so that
we can see the right data in DDR. And fix parameter
for invalidate_dcache_range() after 'mmc read'.
Signed-off-by: Yangbo Lu
Cc: York Sun
---
drivers/mmc/fsl_esdhc.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c4719e6..3ca25bd 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -192,6 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
wml_value = data->blocksize/4;
if (data->flags & MMC_DATA_READ) {
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+ /*
+* It's temporary for ls2085a so that
+* we can see right data in DDR
+*/
+ flush_dcache_range((ulong)data->dest,
+ (ulong)data->dest+data->blocks
+*data->blocksize);
+#endif
+#endif
if (wml_value > WML_RD_WML_MAX)
wml_value = WML_RD_WML_MAX_VAL;
@@ -278,14 +289,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct
mmc_data *data)
static void check_and_invalidate_dcache_range
(struct mmc_cmd *cmd,
struct mmc_data *data) {
-#ifdef CONFIG_LS2085A
- unsigned start = 0;
-#else
- unsigned start = (unsigned)data->dest ;
-#endif
+ unsigned start, end;
unsigned size = roundup(ARCH_DMA_MINALIGN,
data->blocks*data->blocksize);
- unsigned end = start+size ;
#ifdef CONFIG_LS2085A
dma_addr_t addr;
@@ -294,7 +300,10 @@ static void check_and_invalidate_dcache_range
printf("Error found for upper 32 bits\n");
else
start = lower_32_bits(addr);
+#else
+ start = (unsigned)data->dest;
#endif
+ end = start + size;
invalidate_dcache_range(start, end);
}
#endif
--
2.1.0.27.g96db324
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Re: [U-Boot] [RESPIN PATCH v2 14/15] x86: crownbay: Enable writing MP table
On 22 June 2015 at 22:18, Bin Meng wrote: > Enable writing MP table for Intel Crown Bay board. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > > --- > > Changes in v2: None > > configs/crownbay_defconfig | 1 + > 1 file changed, 1 insertion(+) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 15/15] x86: queensbay: Change PCIe root ports' interrupt routing
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> So far interrupt routing works pretty well for any on-chip devices >> on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, >> Linux kernel is smart enough to do interrupt swizzling and figure >> out device's irq using its parent bridge's interrupt routing info >> all the way up to its root port. In U-Boot all PCIe root ports' >> interrupts were routed to PIRQ E/F/G/H before, while actually all >> PCIe downstream ports received INTx are routed to PIRQ A/B/C/D >> directly and not configurable. Now we change this mapping so that >> any external PCIe device can work correctly. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to change PCIe root ports' interrupt routing for queensbay >> >> arch/x86/cpu/queensbay/tnc.c | 13 +++-- >> arch/x86/dts/crownbay.dts| 20 >> 2 files changed, 23 insertions(+), 10 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 10/15] x86: Remove inline for lapic access routines
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Remove inline for lapic access routines and expose lapic_read() >> & lapic_write() as APIs to read/write lapic registers. Also move >> stop_this_cpu() to mp_init.c as it has nothing to do with lapic. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to remove inline for lapic access routines >> >> arch/x86/cpu/lapic.c | 143 >> +-- >> arch/x86/cpu/mp_init.c | 27 +--- >> arch/x86/include/asm/lapic.h | 134 +++- >> 3 files changed, 153 insertions(+), 151 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 13/15] x86: Update README.x86 for SMP support
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Document U-Boot multi-processor support as well as configuration >> tables like SFI and MP tables for SMP OS kernel. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to update README.x86 for SMP support >> >> doc/README.x86 | 13 + >> 1 file changed, 13 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 11/15] x86: Add MultiProcessor (MP) table APIs
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> The MP table provides a way for the operating system to support >> for symmetric multiprocessing as well as symmetric I/O interrupt >> handling with the local APIC and I/O APIC. We provide a bunch of >> APIs for U-Boot to write the floating table, configuration table >> header as well as base and extended table entries. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Avoid using u16 and u8 in parameters >> - Create a helper routine of strncpy that pads with spaces >> >> arch/x86/include/asm/mpspec.h | 434 >> ++ >> arch/x86/include/asm/tables.h | 14 ++ >> arch/x86/lib/Makefile | 1 + >> arch/x86/lib/mpspec.c | 225 ++ >> arch/x86/lib/tables.c | 14 ++ >> 5 files changed, 688 insertions(+) >> create mode 100644 arch/x86/include/asm/mpspec.h >> create mode 100644 arch/x86/lib/mpspec.c > > Nice! > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 09/15] x86: Add I/O APIC register access routines
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> I/O APIC registers are addressed indirectly. Add io_apic_read() and >> io_apic_write() routines to help register access. Two macros for I/O >> APIC ID and version register offset are also added. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Do not use inline for register access >> >> arch/x86/cpu/Makefile | 2 +- >> arch/x86/cpu/ioapic.c | 21 + >> arch/x86/include/asm/ioapic.h | 24 >> 3 files changed, 46 insertions(+), 1 deletion(-) >> create mode 100644 arch/x86/cpu/ioapic.c > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 12/15] x86: Generate a valid MultiProcessor (MP) table
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Implement write_mp_table() to create a minimal working MP table. >> This includes an MP floating table, a configuration table header >> and all of the 5 base configuration table entries. The I/O interrupt >> assignment table entry is created based on the same information used >> in the creation of PIRQ routing table from device tree. A check >> duplicated entry logic is applied to prevent writing multiple I/O >> interrupt entries with the same information. >> >> Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we >> need actually write the MP table at the F seg, just like we did for >> PIRQ routing and SFI tables. With MP table existence, linux kernel >> will switch to I/O APIC and local APIC to process all the peripheral >> interrupts instead of 8259 PICs. This takes full advantage of the >> multicore hardware and the SMP kernel. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - Avoid using u16 and u8 in parameters >> - Add a comment block for check_dup_entry() >> - Return and check error codes of mptable_add_intsrc() >> - Remove __weak for write_mp_table() >> >> arch/x86/Kconfig | 9 +++ >> arch/x86/include/asm/mpspec.h | 10 +++ >> arch/x86/lib/mpspec.c | 157 >> ++ >> arch/x86/lib/tables.c | 5 ++ >> 4 files changed, 181 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 04/15] x86: queensbay: Correct Topcliff device irqs
On 22 June 2015 at 22:18, Bin Meng wrote: > There are 4 usb ports on the Intel Crown Bay board, 2 of which are > connected to Topcliff usb host 0 and the other 2 connected to usb > host 1. USB devices inserted in the ports connected to usb host 1 > cannot get detected due to wrong IRQ assigned to the controller. > Actually we need apply the PCI interrupt pin swizzling logic to all > devices on the Topcliff chipset when configuring the PIRQ routing. > > This was observed on usb ports, but device 6 and 10 irqs are also > wrong. Correct them all together. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/dts/crownbay.dts | 24 > 1 file changed, 12 insertions(+), 12 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 08/15] x86: Clean up ioapic header file
On 22 June 2015 at 22:18, Bin Meng wrote: > Remove all the dead/unused macros from asm/ioapic.h. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/include/asm/ioapic.h | 26 +++--- > 1 file changed, 3 insertions(+), 23 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 06/15] x86: Ignore function number when writing PIRQ routing table
On 22 June 2015 at 22:18, Bin Meng wrote: > In fill_irq_info() pci device's function number is written into > the table, however this is not really necessary. The function > number can be anything as OS doesn't care about this field, > neither does the PIRQ routing specification. Change to always > writing 0 as the function number. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/cpu/irq.c | 7 +++ > 1 file changed, 3 insertions(+), 4 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 03/15] x86: crownbay: Enable DM RTC support
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Add a RTC node in the device tree to enable DM RTC support. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to enable DM RTC support for Crown Bay >> >> arch/x86/dts/crownbay.dts | 1 + >> arch/x86/dts/rtc.dtsi | 6 ++ >> configs/crownbay_defconfig | 1 + >> 3 files changed, 8 insertions(+) >> create mode 100644 arch/x86/dts/rtc.dtsi > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 07/15] x86: Reduce PIRQ routing table size
On 22 June 2015 at 22:18, Bin Meng wrote: > There is no need to populate multiple irq info entries with the same > bus number and device number, but with different interrupt pin. We > can use the same entry to store all the 4 interrupt pin (INT A/B/C/D) > routing information to reduce the whole PIRQ routing table size. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > > --- > > Changes in v2: > - Avoid using u16 and u8 in parameters > > arch/x86/cpu/irq.c | 65 > ++ > 1 file changed, 56 insertions(+), 9 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 05/15] x86: Write correct bus number for the irq router
On 22 June 2015 at 22:18, Bin Meng wrote: > We should write correct bus number to the PIRQ routing table for the > irq router from device tree, instead of hard-coded zero. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v2: None > > arch/x86/cpu/irq.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 6/6] x86: crownbay: Add MP initialization
On 16 June 2015 at 21:15, Bin Meng wrote: > Intel Crown Bay board has a TunnelCreek processor which supports > hyper-threading. Add /cpus node in the crownbay.dts and enable > the MP initialization. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: > - Move CONFIG_MAX_CPUS after CONFIG_SMP in crownbay_defconfig to > match the order in Kconfig > > arch/x86/dts/crownbay.dts | 20 > configs/crownbay_defconfig | 4 > 2 files changed, 24 insertions(+) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 02/15] cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Currently CONFIG_DM_I2C is used in cmd_date.c for driver model, >> but it should be actually CONFIG_DM_RTC. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C >> >> common/cmd_date.c | 12 ++-- >> 1 file changed, 6 insertions(+), 6 deletions(-) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 5/6] x86: Clean up lapic codes
On 16 June 2015 at 21:15, Bin Meng wrote: > This commit cleans up the lapic codes: > - Delete arch/x86/include/asm/lapic_def.h, and move register and bit > defines into arch/x86/include/asm/lapic.h > - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic() > - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and > CONFIG_AP_IN_SIPI_WAIT > - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as > it is not apic related and only used by ivybridge > - Fix coding convention issues > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/ivybridge/model_206ax.c | 2 +- > arch/x86/cpu/lapic.c | 38 > arch/x86/include/asm/arch-ivybridge/bd82x6x.h | 14 ++- > arch/x86/include/asm/lapic.h | 131 > ++ > arch/x86/include/asm/lapic_def.h | 101 > 5 files changed, 103 insertions(+), 183 deletions(-) > delete mode 100644 arch/x86/include/asm/lapic_def.h Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 01/15] dm: rtc: Support mc146818 driver in driver model
On 23 June 2015 at 19:45, Simon Glass wrote: > On 22 June 2015 at 22:18, Bin Meng wrote: >> Add driver model support to the mc146818 rtc driver. Also clean up >> the driver a little bit for coding convention issues. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v2: >> - New patch to support mc146818 driver in driver model >> >> drivers/rtc/mc146818.c | 312 >> - >> 1 file changed, 204 insertions(+), 108 deletions(-) > > Acked-by: Simon Glass Again I am going to apply this series now, as I think lack of MP table support causes problems at present. Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 2/6] x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONS
Hi Bin, On 16 June 2015 at 21:15, Bin Meng wrote: > > Ivybridge is not ready for U-Boot MP initialization yet. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > > --- > > Changes in v4: None > Changes in v3: > - New patch to remove SMP from CPU_SPECIFIC_OPTIONS for ivybridge > > Changes in v2: None > > arch/x86/cpu/ivybridge/Kconfig | 1 - > 1 file changed, 1 deletion(-) I'm going to apply this series now since it seems that the SFI-only mutiprocessor support is not good enough. Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 4/6] x86: Move lapic_setup() call into init_bsp()
On 16 June 2015 at 21:15, Bin Meng wrote: > Currently lapic_setup() is called before calling mp_init(), which > then calls init_bsp() where it calls enable_lapic(), which was > already enabled in lapic_setup(). Hence move lapic_setup() call > into init_bsp() to avoid the duplication. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > arch/x86/cpu/cpu.c | 2 -- > arch/x86/cpu/mp_init.c | 2 +- > 2 files changed, 1 insertion(+), 3 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 3/6] x86: Move MP initialization codes into a common place
On 16 June 2015 at 21:15, Bin Meng wrote: > Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is > common to all x86 processors, except detect_num_cpus() which varies > from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the > new 'get_count' method for baytrail and cpu_x86 drivers. Now we call > cpu_get_count() in mp_init() to get the number of CPUs. > > Signed-off-by: Bin Meng > Acked-by: Simon Glass > > --- > > Changes in v4: > - Update to match cpu_get_count() > > Changes in v3: > - Remove num_cpus from struct mp_params > - Call cpu_get_count() in mp_init() to get the number of CPUs > - Add missing DECLARE_GLOBAL_DATA_PTR in cpu-uclass.c and cpu_x86.c > > Changes in v2: None > > arch/x86/cpu/baytrail/cpu.c | 98 > ++--- > arch/x86/cpu/cpu.c | 40 ++ > arch/x86/cpu/cpu_x86.c | 28 + > arch/x86/cpu/mp_init.c | 18 +++-- > arch/x86/include/asm/mp.h | 1 - > drivers/cpu/cpu-uclass.c| 2 + > 6 files changed, 114 insertions(+), 73 deletions(-) Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 1/6] dm: cpu: Add a new get_count method to cpu uclass
On 17 June 2015 at 09:11, Simon Glass wrote: > On 16 June 2015 at 21:15, Bin Meng wrote: >> Introduce a new method 'get_count' in the UCLASS_CPU ops to get >> the number of CPUs in the system. >> >> Signed-off-by: Bin Meng >> >> --- >> >> Changes in v4: >> - Remove parameter 'count' from cpu_get_count() >> >> Changes in v3: >> - Drop patches already applied and rebase on u-boot-x86/master >> - New patch to add a new get_count method to cpu uclass >> >> Changes in v2: None >> >> drivers/cpu/cpu-uclass.c | 10 ++ >> include/cpu.h| 16 >> 2 files changed, 26 insertions(+) > > Acked-by: Simon Glass Applied to u-boot-x86, thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 27/54] mmc: Avoid using printf() for errors
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass wrote:
> These bloat the code and cause problems for SPL. Use debug() where possible
> and try to return a useful error code instead.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/mmc/dw_mmc.c | 21 +++--
Subject line and description should show this is dwmmc specific.
ChenYu
> 1 file changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 53a8aca..8f28d7e 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -8,6 +8,7 @@
>
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -119,7 +120,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
> *cmd,
>
> while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
> if (get_timer(start) > timeout) {
> - printf("%s: Timeout on data busy\n", __func__);
> + debug("%s: Timeout on data busy\n", __func__);
> return TIMEOUT;
> }
> }
> @@ -178,7 +179,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
> *cmd,
> }
>
> if (i == retry) {
> - printf("%s: Timeout.\n", __func__);
> + debug("%s: Timeout.\n", __func__);
> return TIMEOUT;
> }
>
> @@ -194,8 +195,8 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
> *cmd,
> debug("%s: Response Timeout.\n", __func__);
> return TIMEOUT;
> } else if (mask & DWMCI_INTMSK_RE) {
> - printf("%s: Response Error.\n", __func__);
> - return -1;
> + debug("%s: Response Error.\n", __func__);
> + return -EIO;
> }
>
>
> @@ -214,7 +215,7 @@ static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd
> *cmd,
> do {
> mask = dwmci_readl(host, DWMCI_RINTSTS);
> if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
> - printf("%s: DATA ERROR!\n", __func__);
> + debug("%s: DATA ERROR!\n", __func__);
> return -1;
> }
> } while (!(mask & DWMCI_INTMSK_DTO));
> @@ -251,7 +252,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
> freq)
> else if (host->bus_hz)
> sclk = host->bus_hz;
> else {
> - printf("%s: Didn't get source clock value.\n", __func__);
> + debug("%s: Didn't get source clock value.\n", __func__);
> return -EINVAL;
> }
>
> @@ -270,7 +271,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
> freq)
> do {
> status = dwmci_readl(host, DWMCI_CMD);
> if (timeout-- < 0) {
> - printf("%s: Timeout!\n", __func__);
> + debug("%s: Timeout!\n", __func__);
> return -ETIMEDOUT;
> }
> } while (status & DWMCI_CMD_START);
> @@ -285,7 +286,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
> freq)
> do {
> status = dwmci_readl(host, DWMCI_CMD);
> if (timeout-- < 0) {
> - printf("%s: Timeout!\n", __func__);
> + debug("%s: Timeout!\n", __func__);
> return -ETIMEDOUT;
> }
> } while (status & DWMCI_CMD_START);
> @@ -339,8 +340,8 @@ static int dwmci_init(struct mmc *mmc)
> dwmci_writel(host, DWMCI_PWREN, 1);
>
> if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
> - printf("%s[%d] Fail-reset!!\n", __func__, __LINE__);
> - return -1;
> + debug("%s[%d] Fail-reset!!\n", __func__, __LINE__);
> + return -EIO;
> }
>
> /* Enumerate at 400KHz */
> --
> 2.4.3.573.g4eafbef
>
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Re: [U-Boot] [PATCH v3 31/54] mmc: Support bypass mode with the get_mmc_clk() method
Hi,
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass wrote:
> Some SoCs want to adjust the input clock to the DWMMC block as a way of
> controlling the MMC bus clock. Update the get_mmc_clk() method to support
> this.
The subject line should probably reflect this is a DWMMC only patch?
There are systems that have MMC and don't use the DWMMC controller.
ChenYu
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/mmc/dw_mmc.c| 2 +-
> drivers/mmc/exynos_dw_mmc.c | 2 +-
> include/dwmmc.h | 16 +++-
> 3 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
> index 8f28d7e..a034c3f 100644
> --- a/drivers/mmc/dw_mmc.c
> +++ b/drivers/mmc/dw_mmc.c
> @@ -248,7 +248,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
> freq)
> * host->bus_hz should be set by user.
> */
> if (host->get_mmc_clk)
> - sclk = host->get_mmc_clk(host);
> + sclk = host->get_mmc_clk(host, freq);
> else if (host->bus_hz)
> sclk = host->bus_hz;
> else {
> diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
> index e083745..3f702ba 100644
> --- a/drivers/mmc/exynos_dw_mmc.c
> +++ b/drivers/mmc/exynos_dw_mmc.c
> @@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
> dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
> }
>
> -unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
> +unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
> {
> unsigned long sclk;
> int8_t clk_div;
> diff --git a/include/dwmmc.h b/include/dwmmc.h
> index 7a7555a..25cf42c 100644
> --- a/include/dwmmc.h
> +++ b/include/dwmmc.h
> @@ -163,7 +163,21 @@ struct dwmci_host {
>
> void (*clksel)(struct dwmci_host *host);
> void (*board_init)(struct dwmci_host *host);
> - unsigned int (*get_mmc_clk)(struct dwmci_host *host);
> +
> + /**
> +* Get / set a particular MMC clock frequency
> +*
> +* This is used to request the current clock frequency of the clock
> +* that drives the DWMMC peripheral. The caller will then use this
> +* information to work out the divider it needs to achieve the
> +* required MMC bus clock frequency. If you want to handle the
> +* clock external to DWMMC, use @freq to select the frequency and
> +* return that value too. Then DWMMC will put itself in bypass mode.
> +*
> +* @host: DWMMC host
> +* @freq: Frequency the host is trying to achieve
> +*/
> + unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
>
> struct mmc_config cfg;
> };
> --
> 2.4.3.573.g4eafbef
>
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Re: [U-Boot] [RESPIN PATCH v2 12/15] x86: Generate a valid MultiProcessor (MP) table
On 22 June 2015 at 22:18, Bin Meng wrote: > Implement write_mp_table() to create a minimal working MP table. > This includes an MP floating table, a configuration table header > and all of the 5 base configuration table entries. The I/O interrupt > assignment table entry is created based on the same information used > in the creation of PIRQ routing table from device tree. A check > duplicated entry logic is applied to prevent writing multiple I/O > interrupt entries with the same information. > > Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we > need actually write the MP table at the F seg, just like we did for > PIRQ routing and SFI tables. With MP table existence, linux kernel > will switch to I/O APIC and local APIC to process all the peripheral > interrupts instead of 8259 PICs. This takes full advantage of the > multicore hardware and the SMP kernel. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Avoid using u16 and u8 in parameters > - Add a comment block for check_dup_entry() > - Return and check error codes of mptable_add_intsrc() > - Remove __weak for write_mp_table() > > arch/x86/Kconfig | 9 +++ > arch/x86/include/asm/mpspec.h | 10 +++ > arch/x86/lib/mpspec.c | 157 > ++ > arch/x86/lib/tables.c | 5 ++ > 4 files changed, 181 insertions(+) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 13/15] x86: Update README.x86 for SMP support
On 22 June 2015 at 22:18, Bin Meng wrote: > Document U-Boot multi-processor support as well as configuration > tables like SFI and MP tables for SMP OS kernel. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to update README.x86 for SMP support > > doc/README.x86 | 13 + > 1 file changed, 13 insertions(+) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 10/15] x86: Remove inline for lapic access routines
On 22 June 2015 at 22:18, Bin Meng wrote: > Remove inline for lapic access routines and expose lapic_read() > & lapic_write() as APIs to read/write lapic registers. Also move > stop_this_cpu() to mp_init.c as it has nothing to do with lapic. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to remove inline for lapic access routines > > arch/x86/cpu/lapic.c | 143 > +-- > arch/x86/cpu/mp_init.c | 27 +--- > arch/x86/include/asm/lapic.h | 134 +++- > 3 files changed, 153 insertions(+), 151 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 09/15] x86: Add I/O APIC register access routines
On 22 June 2015 at 22:18, Bin Meng wrote: > I/O APIC registers are addressed indirectly. Add io_apic_read() and > io_apic_write() routines to help register access. Two macros for I/O > APIC ID and version register offset are also added. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Do not use inline for register access > > arch/x86/cpu/Makefile | 2 +- > arch/x86/cpu/ioapic.c | 21 + > arch/x86/include/asm/ioapic.h | 24 > 3 files changed, 46 insertions(+), 1 deletion(-) > create mode 100644 arch/x86/cpu/ioapic.c Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 15/15] x86: queensbay: Change PCIe root ports' interrupt routing
On 22 June 2015 at 22:18, Bin Meng wrote: > So far interrupt routing works pretty well for any on-chip devices > on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, > Linux kernel is smart enough to do interrupt swizzling and figure > out device's irq using its parent bridge's interrupt routing info > all the way up to its root port. In U-Boot all PCIe root ports' > interrupts were routed to PIRQ E/F/G/H before, while actually all > PCIe downstream ports received INTx are routed to PIRQ A/B/C/D > directly and not configurable. Now we change this mapping so that > any external PCIe device can work correctly. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to change PCIe root ports' interrupt routing for queensbay > > arch/x86/cpu/queensbay/tnc.c | 13 +++-- > arch/x86/dts/crownbay.dts| 20 > 2 files changed, 23 insertions(+), 10 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 11/15] x86: Add MultiProcessor (MP) table APIs
On 22 June 2015 at 22:18, Bin Meng wrote: > The MP table provides a way for the operating system to support > for symmetric multiprocessing as well as symmetric I/O interrupt > handling with the local APIC and I/O APIC. We provide a bunch of > APIs for U-Boot to write the floating table, configuration table > header as well as base and extended table entries. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - Avoid using u16 and u8 in parameters > - Create a helper routine of strncpy that pads with spaces > > arch/x86/include/asm/mpspec.h | 434 > ++ > arch/x86/include/asm/tables.h | 14 ++ > arch/x86/lib/Makefile | 1 + > arch/x86/lib/mpspec.c | 225 ++ > arch/x86/lib/tables.c | 14 ++ > 5 files changed, 688 insertions(+) > create mode 100644 arch/x86/include/asm/mpspec.h > create mode 100644 arch/x86/lib/mpspec.c Nice! Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 03/15] x86: crownbay: Enable DM RTC support
On 22 June 2015 at 22:18, Bin Meng wrote: > Add a RTC node in the device tree to enable DM RTC support. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to enable DM RTC support for Crown Bay > > arch/x86/dts/crownbay.dts | 1 + > arch/x86/dts/rtc.dtsi | 6 ++ > configs/crownbay_defconfig | 1 + > 3 files changed, 8 insertions(+) > create mode 100644 arch/x86/dts/rtc.dtsi Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 02/15] cmd: date: Change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
On 22 June 2015 at 22:18, Bin Meng wrote: > Currently CONFIG_DM_I2C is used in cmd_date.c for driver model, > but it should be actually CONFIG_DM_RTC. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C > > common/cmd_date.c | 12 ++-- > 1 file changed, 6 insertions(+), 6 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESPIN PATCH v2 01/15] dm: rtc: Support mc146818 driver in driver model
On 22 June 2015 at 22:18, Bin Meng wrote: > Add driver model support to the mc146818 rtc driver. Also clean up > the driver a little bit for coding convention issues. > > Signed-off-by: Bin Meng > > --- > > Changes in v2: > - New patch to support mc146818 driver in driver model > > drivers/rtc/mc146818.c | 312 > - > 1 file changed, 204 insertions(+), 108 deletions(-) Acked-by: Simon Glass ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 23/25] rockchip: Add basic support for firefly-rk3288
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.
This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.
Signed-off-by: Simon Glass
---
Changes in v3:
- Make use of additional features since version 2
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
- Drop use of CONFIG_USE_PRIVATE_LIBGCC=y
arch/arm/dts/Makefile | 2 +
arch/arm/dts/rk3288-firefly.dts | 75 +
arch/arm/dts/rk3288-firefly.dtsi | 457 ++
arch/arm/mach-rockchip/rk3288/Kconfig | 10 +
board/firefly/firefly-rk3288/Kconfig | 15 +
board/firefly/firefly-rk3288/MAINTAINERS | 6 +
board/firefly/firefly-rk3288/Makefile | 7 +
board/firefly/firefly-rk3288/firefly-rk3288.c | 7 +
configs/firefly-rk3288_defconfig | 36 ++
include/configs/firefly-rk3288.h | 15 +
include/configs/rk3288_common.h | 101 ++
11 files changed, 731 insertions(+)
create mode 100644 arch/arm/dts/rk3288-firefly.dts
create mode 100644 arch/arm/dts/rk3288-firefly.dtsi
create mode 100644 board/firefly/firefly-rk3288/Kconfig
create mode 100644 board/firefly/firefly-rk3288/MAINTAINERS
create mode 100644 board/firefly/firefly-rk3288/Makefile
create mode 100644 board/firefly/firefly-rk3288/firefly-rk3288.c
create mode 100644 configs/firefly-rk3288_defconfig
create mode 100644 include/configs/firefly-rk3288.h
create mode 100644 include/configs/rk3288_common.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9c735c6..598fa04 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -14,6 +14,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5420-peach-pit.dtb \
exynos5800-peach-pi.dtb \
exynos5422-odroidxu3.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk3288-firefly.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/rk3288-firefly.dts b/arch/arm/dts/rk3288-firefly.dts
new file mode 100644
index 000..aed8d3a
--- /dev/null
+++ b/arch/arm/dts/rk3288-firefly.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3288-firefly.dtsi"
+
+/ {
+ model = "Firefly-RK3288";
+ compatible = "firefly,firefly-rk3288", "rockchip,rk3288";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ config {
+ u-boot,dm-pre-reloc;
+ u-boot,boot-led = "firefly:green:power";
+ };
+};
+
+&dmc {
+ rockchip,num-channels = <2>;
+ rockchip,pctl-timing = <0x29a 0xc8 0x1f8 0x42 0x4e 0x4 0xea 0xa
+ 0x5 0x0 0xa 0x7 0x19 0x24 0xa 0x7
+ 0x5 0xa 0x5 0x200 0x5 0x10 0x40 0x0
+ 0x1 0x7 0x7 0x4 0xc 0x43 0x100 0x0
+ 0x5 0x0>;
+ rockchip,phy-timing = <0x48f9aab4 0xea0910 0x1002c200
+ 0xa60 0x40 0x10 0x0>;
+ rockchip,sdram-channel = /bits/ 8 <0x1 0xa 0x3 0x2 0x1 0x0 0xf 0xf>;
+ rockchip,sdram-params = <0x30B25564 0x627 3 66600 3 9 1>;
+};
+
+&ir {
+ gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+ act8846 {
+ pmic_vsel: pmic-vsel {
+ rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_output_low>;
+ };
+ };
+
+ ir {
+ ir_int: ir-int {
+ rockchip,pins = <7 0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+ reg-shift = <2>;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio8 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-firefly.dtsi b/arch/arm/dts/rk3288-firefly.dtsi
new file mode 100644
index 000..8a083f0
--- /dev/null
+++ b/arch/arm/dts/rk3288-firefly.dtsi
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2014, 2015 FUKAUMI Naoki
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+ memory {
+ reg = <0 0x8000>;
+ };
+
+ ext_gmac: external-gmac-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12500>;
+ clock-output-names = "ext_gmac";
+ };
+
+ ir: ir-receiver {
+ compatible = "gpio-ir-receiver";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_int>;
+ };
+
+ keys: gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ button@0 {
+ gp
[U-Boot] [PATCH v3 24/25] rockchip: Add basic support for jerry
This builds and displays an SPL message, but does not function beyond that.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/cros-ec-sbs.dtsi | 16 +
arch/arm/dts/rk3288-jerry.dts | 203 +++
arch/arm/dts/rk3288-veyron-chromebook.dtsi | 200 +++
arch/arm/dts/rk3288-veyron.dtsi| 844 +
arch/arm/mach-rockchip/rk3288/Kconfig | 10 +
board/google/chromebook_jerry/Kconfig | 15 +
board/google/chromebook_jerry/MAINTAINERS | 6 +
board/google/chromebook_jerry/Makefile | 7 +
board/google/chromebook_jerry/jerry.c | 7 +
board/google/common/Makefile | 2 +-
configs/chromebook_jerry_defconfig | 37 ++
include/configs/chromebook_jerry.h | 16 +
13 files changed, 1364 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/cros-ec-sbs.dtsi
create mode 100644 arch/arm/dts/rk3288-jerry.dts
create mode 100644 arch/arm/dts/rk3288-veyron-chromebook.dtsi
create mode 100644 arch/arm/dts/rk3288-veyron.dtsi
create mode 100644 board/google/chromebook_jerry/Kconfig
create mode 100644 board/google/chromebook_jerry/MAINTAINERS
create mode 100644 board/google/chromebook_jerry/Makefile
create mode 100644 board/google/chromebook_jerry/jerry.c
create mode 100644 configs/chromebook_jerry_defconfig
create mode 100644 include/configs/chromebook_jerry.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 598fa04..cc13866 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -15,7 +15,8 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \
exynos5800-peach-pi.dtb \
exynos5422-odroidxu3.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
- rk3288-firefly.dtb
+ rk3288-firefly.dtb \
+ rk3288-jerry.dtb
dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
tegra20-medcom-wide.dtb \
tegra20-paz00.dtb \
diff --git a/arch/arm/dts/cros-ec-sbs.dtsi b/arch/arm/dts/cros-ec-sbs.dtsi
new file mode 100644
index 000..3f35d20
--- /dev/null
+++ b/arch/arm/dts/cros-ec-sbs.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Smart battery dts fragment for devices that use cros-ec-sbs
+ *
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+*/
+
+&i2c_tunnel {
+ battery: sbs-battery@b {
+ compatible = "sbs,sbs-battery";
+ reg = <0xb>;
+ sbs,i2c-retry-count = <2>;
+ sbs,poll-retry-count = <1>;
+ };
+};
diff --git a/arch/arm/dts/rk3288-jerry.dts b/arch/arm/dts/rk3288-jerry.dts
new file mode 100644
index 000..da37ea8
--- /dev/null
+++ b/arch/arm/dts/rk3288-jerry.dts
@@ -0,0 +1,203 @@
+/*
+ * Google Veyron Jerry Rev 3+ board device tree source
+ *
+ * Copyright 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+/dts-v1/;
+#include "rk3288-veyron-chromebook.dtsi"
+#include "cros-ec-sbs.dtsi"
+
+/ {
+ model = "Google Jerry";
+ compatible = "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
+"google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
+"google,veyron-jerry-rev3", "google,veyron-jerry",
+"google,veyron", "rockchip,rk3288";
+
+chosen {
+stdout-path = &uart2;
+};
+
+ panel_regulator: panel-regualtor {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_enable_h>;
+ regulator-name = "panel_regulator";
+ vin-supply = <&vcc33_sys>;
+ };
+
+ vcc18_lcd: vcc18-lcd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&avdd_1v8_disp_en>;
+ regulator-name = "vcc18_lcd";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc18_wl>;
+ };
+
+ backlight_regulator: backlight-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bl_pwr_en>;
+ regulator-name = "backlight_regulator";
+ vin-supply = <&vcc33_sys>;
+ startup-delay-us = <15000>;
+ };
+};
+
+&gpio_keys {
+ power {
+ gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&backlight {
+ power-supply = <&backlight_regulator>;
+};
+
+&panel {
+ power-supply= <&panel_regulator>;
+};
+
+&rk808 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
+ dvs-gpios = <&gpi
[U-Boot] [PATCH v3 20/25] rockchip: Add core SoC start-up code
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 10 ++
arch/arm/Makefile | 1 +
arch/arm/mach-rockchip/Kconfig| 41 +
arch/arm/mach-rockchip/Makefile | 13 ++
arch/arm/mach-rockchip/board-spl.c| 290 ++
arch/arm/mach-rockchip/board.c| 46 ++
arch/arm/mach-rockchip/common.c | 28
arch/arm/mach-rockchip/rk3288/Kconfig | 6 +
8 files changed, 435 insertions(+)
create mode 100644 arch/arm/mach-rockchip/Kconfig
create mode 100644 arch/arm/mach-rockchip/Makefile
create mode 100644 arch/arm/mach-rockchip/board-spl.c
create mode 100644 arch/arm/mach-rockchip/board.c
create mode 100644 arch/arm/mach-rockchip/common.c
create mode 100644 arch/arm/mach-rockchip/rk3288/Kconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0829235..6124498 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -817,6 +817,14 @@ config TARGET_STM32F429_DISCOVERY
bool "Support STM32F429 Discovery"
select CPU_V7M
+config ARCH_ROCKCHIP
+ bool "Support Rockchip SoCs"
+ select SUPPORT_SPL
+ select SPL
+ select OF_CONTROL
+ select CPU_V7
+ select DM
+
endchoice
source "arch/arm/mach-at91/Kconfig"
@@ -851,6 +859,8 @@ source "arch/arm/mach-orion5x/Kconfig"
source "arch/arm/cpu/armv7/rmobile/Kconfig"
+source "arch/arm/mach-rockchip/Kconfig"
+
source "arch/arm/cpu/armv7/s5pc1xx/Kconfig"
source "arch/arm/mach-socfpga/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f30098..2a91c04 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -54,6 +54,7 @@ machine-$(CONFIG_ARCH_NOMADIK)+= nomadik
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
+machine-$(CONFIG_ARCH_ROCKCHIP)+= rockchip
machine-$(CONFIG_TEGRA)+= tegra
machine-$(CONFIG_ARCH_UNIPHIER)+= uniphier
machine-$(CONFIG_ARCH_VERSATILE) += versatile
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 000..ab50f4e
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,41 @@
+if ARCH_ROCKCHIP
+
+config ROCKCHIP_RK3288
+ bool "Support Rockchip RK3288"
+ help
+ The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
+ including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
+ video interfaces supporting HDMI and eDP, several DDR3 options
+ and video codec support. Peripherals include Gigabit Ethernet,
+ USB2 host and OTG, SDIO, I2S, UART,s, SPI, I2C and PWMs.
+
+config SYS_MALLOC_F
+ default y
+
+config SYS_MALLOC_F_LEN
+ default 0x800
+
+config SPL_DM
+ default y
+
+config DM_SERIAL
+ default y
+
+config DM_SPI
+ default y
+
+config DM_SPI_FLASH
+ default y
+
+config DM_I2C
+ default y
+
+config DM_GPIO
+ default y
+
+config ROCKCHIP_SERIAL
+ default y
+
+source "arch/arm/mach-rockchip/rk3288/Kconfig"
+
+endif
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 000..5a4e383
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2014 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifdef CONFIG_SPL_BUILD
+obj-y += board-spl.o
+else
+obj-y += board.o
+endif
+obj-y += common.o
+obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/
diff --git a/arch/arm/mach-rockchip/board-spl.c
b/arch/arm/mach-rockchip/board-spl.c
new file mode 100644
index 000..2df255f
--- /dev/null
+++ b/arch/arm/mach-rockchip/board-spl.c
@@ -0,0 +1,290 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 spl_boot_device(void)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ const char *bootdev;
+ int node;
+ int ret;
+
+ bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
+ debug("Boot device %s\n", bootdev);
+ if (!bootdev)
+ goto fallback;
+
+ node = fdt_path_offset(blob, bootdev);
+ if (node < 0) {
+ debug("node=%d\n", node);
+ goto fallback;
+ }
+ ret = device_get_global_by_of_offset(node, &dev);
+ if (ret) {
+ debug("device at node %s/%d not found: %d\n", bootdev, node,
+ ret);
+ goto fallback;
[U-Boot] [PATCH v3 21/25] rockchip: Add I2C driver
Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/i2c.h | 70 ++
drivers/i2c/Kconfig | 9 +
drivers/i2c/Makefile | 1 +
drivers/i2c/rk_i2c.c | 391 +++
4 files changed, 471 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/i2c.h
create mode 100644 drivers/i2c/rk_i2c.c
diff --git a/arch/arm/include/asm/arch-rockchip/i2c.h
b/arch/arm/include/asm/arch-rockchip/i2c.h
new file mode 100644
index 000..d81f8ff
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/i2c.h
@@ -0,0 +1,70 @@
+/*
+ * (C) Copyright 2012 SAMSUNG Electronics
+ * Jaehoon Chung
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __ASM_ARCH_I2C_H
+#define __ASM_ARCH_I2C_H
+
+struct i2c_regs {
+ u32 con;
+ u32 clkdiv;
+ u32 mrxaddr;
+ u32 mrxraddr;
+ u32 mtxcnt;
+ u32 mrxcnt;
+ u32 ien;
+ u32 ipd;
+ u32 fcnt;
+ u32 reserved0[0x37];
+ u32 txdata[8];
+ u32 reserved1[0x38];
+ u32 rxdata[8];
+};
+
+/* Control register */
+#define I2C_CON_EN (1 << 0)
+#define I2C_CON_MOD(mod) ((mod) << 1)
+#define I2C_MODE_TX0x00
+#define I2C_MODE_TRX 0x01
+#define I2C_MODE_RX0x02
+#define I2C_MODE_RRX 0x03
+#define I2C_CON_MASK (3 << 1)
+
+#define I2C_CON_START (1 << 3)
+#define I2C_CON_STOP (1 << 4)
+#define I2C_CON_LASTACK(1 << 5)
+#define I2C_CON_ACTACK (1 << 6)
+
+/* Clock dividor register */
+#define I2C_CLKDIV_VAL(divl, divh) \
+ (((divl) & 0x) | (((divh) << 16) & 0x))
+
+/* the slave address accessed for master rx mode */
+#define I2C_MRXADDR_SET(vld, addr) (((vld) << 24) | (addr))
+
+/* the slave register address accessed for master rx mode */
+#define I2C_MRXRADDR_SET(vld, raddr) (((vld) << 24) | (raddr))
+
+/* interrupt enable register */
+#define I2C_BTFIEN (1 << 0)
+#define I2C_BRFIEN (1 << 1)
+#define I2C_MBTFIEN(1 << 2)
+#define I2C_MBRFIEN(1 << 3)
+#define I2C_STARTIEN (1 << 4)
+#define I2C_STOPIEN(1 << 5)
+#define I2C_NAKRCVIEN (1 << 6)
+
+/* interrupt pending register */
+#define I2C_BTFIPD (1 << 0)
+#define I2C_BRFIPD (1 << 1)
+#define I2C_MBTFIPD (1 << 2)
+#define I2C_MBRFIPD (1 << 3)
+#define I2C_STARTIPD(1 << 4)
+#define I2C_STOPIPD (1 << 5)
+#define I2C_NAKRCVIPD (1 << 6)
+#define I2C_IPD_ALL_CLEAN 0x7f
+
+#endif
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 86fb36b..066bca4 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -28,6 +28,15 @@ config DM_I2C_GPIO
bindings are supported.
Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
+config SYS_I2C_ROCKCHIP
+ bool "Rockchip I2C driver"
+ depends on DM_I2C
+ help
+ Add support for the Rockchip I2C driver. This is used with various
+ Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
+ have several I2C ports and all are provided, controled by the
+ device tree.
+
config SYS_I2C_SANDBOX
bool "Sandbox I2C driver"
depends on SANDBOX && DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index d9e912f..f12c3ad 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_SYS_I2C_OMAP24XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_OMAP34XX) += omap24xx_i2c.o
obj-$(CONFIG_SYS_I2C_PPC4XX) += ppc4xx_i2c.o
obj-$(CONFIG_SYS_I2C_RCAR) += rcar_i2c.o
+obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o
obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
diff --git a/drivers/i2c/rk_i2c.c b/drivers/i2c/rk_i2c.c
new file mode 100644
index 000..4466e68
--- /dev/null
+++ b/drivers/i2c/rk_i2c.c
@@ -0,0 +1,391 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, .
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* i2c timerout */
+#define I2C_TIMEOUT_MS 100
+#define I2C_RETRY_COUNT3
+
+/* rk i2c fifo max transfer bytes */
+#define RK_I2C_FIFO_SIZE 32
+
+struct rk_i2c {
+ struct udevice *clk;
+ struct udevice *pinctrl;
+ struct i2c_regs *regs;
+ unsigned int speed;
+ enum periph_id id;
+};
+
+static inline void rk_i2c_get_div(int div, int *divh, int *divl)
+{
+ *divl = div / 2
[U-Boot] [PATCH v3 16/25] rockchip: rk3288: Add a simple syscon driver
Add a driver that provides access to system controllers.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile| 1 +
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 +
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
diff --git a/arch/arm/mach-rockchip/rk3288/Makefile
b/arch/arm/mach-rockchip/rk3288/Makefile
index c6663f0..3f9900d 100644
--- a/arch/arm/mach-rockchip/rk3288/Makefile
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -5,3 +5,4 @@
#
obj-y += reset_rk3288.o
+obj-y += syscon_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
new file mode 100644
index 000..c9f7c4e
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+static const struct udevice_id rk3288_syscon_ids[] = {
+ { .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
+ { .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3288-sgrf", .data = ROCKCHIP_SYSCON_SGRF },
+ { .compatible = "rockchip,rk3288-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3288) = {
+ .name = "rk3288_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3288_syscon_ids,
+};
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 17/25] rockchip: rk3288: Add pinctrl driver
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/rockchip/Makefile | 8 +
drivers/pinctrl/rockchip/pinctrl_rk3288.c | 429 ++
4 files changed, 447 insertions(+)
create mode 100644 drivers/pinctrl/rockchip/Makefile
create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3288.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index e667361..9e45acd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -17,3 +17,12 @@ config SPL_PINCTRL_SUPPORT
to adjust pin multiplexing in SPL in order to boot into U-Boot,
enable this option. You will need to enable device tree in SPL
for this to work.
+
+config ROCKCHIP_PINCTRL
+ bool "Rockchip pin control driver"
+ depends on DM
+ help
+ Support pin multiplexing control on Rockchip SoCs. The driver is
+ controlled by a device tree node which contains both the GPIO
+ definitions and pin control functions for each available multiplex
+ function.
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 6e63ee7..764b1bf 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -6,3 +6,4 @@
#
obj-$(CONFIG_PINCTRL) += pinctrl-uclass.o
+obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/pinctrl/rockchip/Makefile
b/drivers/pinctrl/rockchip/Makefile
new file mode 100644
index 000..251bace
--- /dev/null
+++ b/drivers/pinctrl/rockchip/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2015 Google, Inc
+# Written by Simon Glass
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_ROCKCHIP_PINCTRL) += pinctrl_rk3288.o
diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3288.c
b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
new file mode 100644
index 000..9a01929
--- /dev/null
+++ b/drivers/pinctrl/rockchip/pinctrl_rk3288.c
@@ -0,0 +1,429 @@
+/*
+ * Pinctrl driver for Rockchip SoCs
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rk3288_pinctrl_priv {
+ struct rk3288_grf *grf;
+ struct rk3288_pmu *pmu;
+};
+
+static void pinctrl_rk3288_pwm_config(struct rk3288_grf *grf, int pwm_id)
+{
+ switch (pwm_id) {
+ case PERIPH_ID_PWM0:
+ rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A0_MASK << GPIO7A0_SHIFT,
+GPIO7A0_PWM_0 << GPIO7A0_SHIFT);
+ break;
+ case PERIPH_ID_PWM1:
+ rk_clrsetreg(&grf->gpio7a_iomux, GPIO7A1_MASK << GPIO7A1_SHIFT,
+GPIO7A1_PWM_1 << GPIO7A1_SHIFT);
+ break;
+ case PERIPH_ID_PWM2:
+ rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C6_MASK << GPIO7C6_SHIFT,
+GPIO7C6_PWM_2 << GPIO7C6_SHIFT);
+ break;
+ case PERIPH_ID_PWM3:
+ rk_clrsetreg(&grf->gpio7a_iomux, GPIO7C7_MASK << GPIO7C6_SHIFT,
+GPIO7C7_PWM_3 << GPIO7C7_SHIFT);
+ break;
+ default:
+ debug("pwm id = %d iomux error!\n", pwm_id);
+ break;
+ }
+}
+
+static void pinctrl_rk3288_i2c_config(struct rk3288_grf *grf,
+ struct rk3288_pmu *pmu, int i2c_id)
+{
+ switch (i2c_id) {
+ case PERIPH_ID_I2C0:
+ clrsetbits_le32(&pmu->gpio0b_iomux,
+ GPIO0_B7_MASK << GPIO0_B7_SHIFT,
+ GPIO0_B7_I2C0PMU_SDA << GPIO0_B7_SHIFT);
+ clrsetbits_le32(&pmu->gpio0b_iomux,
+ GPIO0_C0_MASK << GPIO0_C0_SHIFT,
+ GPIO0_C0_I2C0PMU_SCL << GPIO0_C0_SHIFT);
+ break;
+ case PERIPH_ID_I2C1:
+ rk_clrsetreg(&grf->gpio8a_iomux,
+GPIO8A4_MASK << GPIO8A4_SHIFT |
+GPIO8A5_MASK << GPIO8A5_SHIFT,
+GPIO8A4_I2C2SENSOR_SDA << GPIO8A4_SHIFT |
+GPIO8A5_I2C2SENSOR_SCL << GPIO8A5_SHIFT);
+ break;
+ case PERIPH_ID_I2C2:
+ rk_clrsetreg(&grf->gpio6b_iomux,
+GPIO6B1_MASK << GPIO6B1_SHIFT |
+GPIO6B2_MASK << GPIO6B2_SHIFT,
+GPIO6B1_I2C1AUDIO_SDA << GPIO6B1_SHIFT |
+GPIO6B2_I2C1AUDIO_SCL << GPIO6B2_SHIFT);
+ break;
+ case PERIPH_ID_I2C3:
+ rk_clrsetreg(&grf->gpio2c_iomux,
+GPIO2C1_MASK << GPIO2C1_SHIFT |
+
[U-Boot] [PATCH v3 25/25] rockchip: Add a simple README
Add a few notes on how to try out the Rockchip support so far. Signed-off-by: Simon Glass --- Changes in v3: - Update README to mention available drivers - Add various new patches to get RK3288 booting to a prompt Changes in v2: None doc/README.rockchip | 246 1 file changed, 246 insertions(+) create mode 100644 doc/README.rockchip diff --git a/doc/README.rockchip b/doc/README.rockchip new file mode 100644 index 000..a34e198 --- /dev/null +++ b/doc/README.rockchip @@ -0,0 +1,246 @@ +# +# Copyright (C) 2015 Google. Inc +# Written by Simon Glass +# +# SPDX-License-Identifier: GPL-2.0+ +# + +U-Boot on Rockchip +== + +There are several repositories available with versions of U-Boot that support +many Rockchip devices [1] [2]. + +The current mainline support is experimental only and is not useful for +anything. It should provide a base on which to build. + +So far only support for the RK3288 is provided. + + +Prerequisites += + +You will need: + + - Firefly RK3288 baord + - Power connection to 5V using the supplied micro-USB power cable + - Separate USB serial cable attached to your computer and the Firefly +(connect to the micro-USB connector below the logo) + - rkflashtool [3] + - openssl (sudo apt-get install openssl) + - Serial UART connection [4] + - Suitable ARM cross compiler, e.g.: +sudo apt-get install gcc-4.7-arm-linux-gnueabi + + +Building + + +At present three RK3288 boards are supported: + + - Firefly RK3288 - use firefly-rk3288 configuration + - Radxa Rock Pro - also uses firefly-rk3288 configuration + - Haier Chromebook - use chromebook_jerry configuration + +For example: + + CROSS_COMPILE=arm-linux-gnueabi- make O=firefly firefly-rk3288_defconfig all + +(or you can use another cross compiler if you prefer) + +Note that the Radxa Rock Pro uses the Firefly configuration for now as +device tree files are not yet available for the Rock Pro. Clearly the two +have hardware differences, so this approach will break down as more drivers +are added. + + +Writing to the board with USB += + +For USB to work you must get your board into ROM boot mode, either by erasing +your MMC or (perhaps) holding the recovery button when you boot the board. +To erase your MMC, you can boot into Linux and type (as root) + + dd if=/dev/zero of=/dev/mmcblk0 bs=1M + +Connect your board's OTG port to your computer. + +To create a suitable image and write it to the board: + + ./firefly-rk3288/tools/mkimage -T rkimage -d ./firefly-rk3288/spl/u-boot-spl-dtb.bin out + cat out | openssl rc4 -K 7c4e0304550509072d2c7b38170d1711 | rkflashtool l + +If all goes well you should something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 10:06:49) + Card did not respond to voltage select! + spl: mmc init failed with error: -17 + ### ERROR ### Please RESET the board ### + +You will need to reset the board before each time you try. Yes, that's all +it does so far. If support for the Rockchip USB protocol or DFU were added +in SPL then we could in principle load U-Boot and boot to a prompt from USB +as several other platforms do. However it does not seem to be possible to +use the existing boot ROM code from SPL. + + +Booting from an SD card +=== + +To write an image that boots from an SD card (assumed to be /dev/sdc): + + ./firefly-rk3288/tools/mkimage -T rksd -d firefly-rk3288/spl/u-boot-spl-dtb.bin out + sudo dd if=out of=/dev/sdc + sudo dd if=firefly-rk3288/u-boot-dtb.img of=/dev/sdc seek=256 + +This puts the Rockchip header and SPL image first and then places the U-Boot +image at block 256 (i.e. 128KB from the start of the SD card). This +corresponds with this setting in U-Boot: + + #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 256 + +Put this SD (or micro-SD) card into your board and reset it. You should see +something like: + + U-Boot SPL 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + + U-Boot 2015.07-rc1-00383-ge345740-dirty (Jun 03 2015 - 11:04:40) + + DRAM: 2 GiB + MMC: + Using default environment + + In:serial@ff69 + Out: serial@ff69 + Err: serial@ff69 + => + + +Booting from SPI + + +To write an image that boots from SPI flash (e.g. for the Haier Chromebook): + + ./chromebook_jerry/tools/mkimage -T rkspi -d chromebook_jerry/spl/u-boot-spl-dtb.bin out + dd if=spl.bin of=out.bin bs=128K conv=sync + cat chromebook_jerry/u-boot-dtb.img out.bin + dd if=out.bin of=out.bin.pad bs=4M conv=sync + +This converts the SPL image to the required SPI format by adding the Rockchip +header and skipping every 2KB block. Then the U-Boot image is written at +offset 128KB and the whole image is padded to 4MB which is the SPI flash size. +The position of U-Boot is controlled with this setting in U-Boot: + + #define CONFIG_SYS_SPI_U_BOOT
[U-Boot] [PATCH v3 18/25] rockchip: rk3288: Add SDRAM init
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/ddr_rk3288.h | 484 +
arch/arm/include/asm/arch-rockchip/sdram.h | 92 +++
arch/arm/mach-rockchip/rk3288/Makefile | 1 +
arch/arm/mach-rockchip/rk3288/sdram_rk3288.c| 878
4 files changed, 1455 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
create mode 100644 arch/arm/include/asm/arch-rockchip/sdram.h
create mode 100644 arch/arm/mach-rockchip/rk3288/sdram_rk3288.c
diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
new file mode 100644
index 000..fccabcd
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3288.h
@@ -0,0 +1,484 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_DDR_RK3288_H
+#define _ASM_ARCH_DDR_RK3288_H
+
+struct rk3288_ddr_pctl {
+ u32 scfg;
+ u32 sctl;
+ u32 stat;
+ u32 intrstat;
+ u32 reserved0[12];
+ u32 mcmd;
+ u32 powctl;
+ u32 powstat;
+ u32 cmdtstat;
+ u32 tstaten;
+ u32 reserved1[3];
+ u32 mrrcfg0;
+ u32 mrrstat0;
+ u32 mrrstat1;
+ u32 reserved2[4];
+ u32 mcfg1;
+ u32 mcfg;
+ u32 ppcfg;
+ u32 mstat;
+ u32 lpddr2zqcfg;
+ u32 reserved3;
+ u32 dtupdes;
+ u32 dtuna;
+ u32 dtune;
+ u32 dtuprd0;
+ u32 dtuprd1;
+ u32 dtuprd2;
+ u32 dtuprd3;
+ u32 dtuawdt;
+ u32 reserved4[3];
+ u32 togcnt1u;
+ u32 tinit;
+ u32 trsth;
+ u32 togcnt100n;
+ u32 trefi;
+ u32 tmrd;
+ u32 trfc;
+ u32 trp;
+ u32 trtw;
+ u32 tal;
+ u32 tcl;
+ u32 tcwl;
+ u32 tras;
+ u32 trc;
+ u32 trcd;
+ u32 trrd;
+ u32 trtp;
+ u32 twr;
+ u32 twtr;
+ u32 texsr;
+ u32 txp;
+ u32 txpdll;
+ u32 tzqcs;
+ u32 tzqcsi;
+ u32 tdqs;
+ u32 tcksre;
+ u32 tcksrx;
+ u32 tcke;
+ u32 tmod;
+ u32 trstl;
+ u32 tzqcl;
+ u32 tmrr;
+ u32 tckesr;
+ u32 tdpd;
+ u32 reserved5[14];
+ u32 ecccfg;
+ u32 ecctst;
+ u32 eccclr;
+ u32 ecclog;
+ u32 reserved6[28];
+ u32 dtuwactl;
+ u32 dturactl;
+ u32 dtucfg;
+ u32 dtuectl;
+ u32 dtuwd0;
+ u32 dtuwd1;
+ u32 dtuwd2;
+ u32 dtuwd3;
+ u32 dtuwdm;
+ u32 dturd0;
+ u32 dturd1;
+ u32 dturd2;
+ u32 dturd3;
+ u32 dtulfsrwd;
+ u32 dtulfsrrd;
+ u32 dtueaf;
+ u32 dfitctrldelay;
+ u32 dfiodtcfg;
+ u32 dfiodtcfg1;
+ u32 dfiodtrankmap;
+ u32 dfitphywrdata;
+ u32 dfitphywrlat;
+ u32 reserved7[2];
+ u32 dfitrddataen;
+ u32 dfitphyrdlat;
+ u32 reserved8[2];
+ u32 dfitphyupdtype0;
+ u32 dfitphyupdtype1;
+ u32 dfitphyupdtype2;
+ u32 dfitphyupdtype3;
+ u32 dfitctrlupdmin;
+ u32 dfitctrlupdmax;
+ u32 dfitctrlupddly;
+ u32 reserved9;
+ u32 dfiupdcfg;
+ u32 dfitrefmski;
+ u32 dfitctrlupdi;
+ u32 reserved10[4];
+ u32 dfitrcfg0;
+ u32 dfitrstat0;
+ u32 dfitrwrlvlen;
+ u32 dfitrrdlvlen;
+ u32 dfitrrdlvlgateen;
+ u32 dfiststat0;
+ u32 dfistcfg0;
+ u32 dfistcfg1;
+ u32 reserved11;
+ u32 dfitdramclken;
+ u32 dfitdramclkdis;
+ u32 dfistcfg2;
+ u32 dfistparclr;
+ u32 dfistparlog;
+ u32 reserved12[3];
+ u32 dfilpcfg0;
+ u32 reserved13[3];
+ u32 dfitrwrlvlresp0;
+ u32 dfitrwrlvlresp1;
+ u32 dfitrwrlvlresp2;
+ u32 dfitrrdlvlresp0;
+ u32 dfitrrdlvlresp1;
+ u32 dfitrrdlvlresp2;
+ u32 dfitrwrlvldelay0;
+ u32 dfitrwrlvldelay1;
+ u32 dfitrwrlvldelay2;
+ u32 dfitrrdlvldelay0;
+ u32 dfitrrdlvldelay1;
+ u32 dfitrrdlvldelay2;
+ u32 dfitrrdlvlgatedelay0;
+ u32 dfitrrdlvlgatedelay1;
+ u32 dfitrrdlvlgatedelay2;
+ u32 dfitrcmd;
+ u32 reserved14[46];
+ u32 ipvr;
+ u32 iptr;
+};
+check_member(rk3288_ddr_pctl, iptr, 0x03fc);
+
+struct rk3288_ddr_publ_datx {
+ u32 dxgcr;
+ u32 dxgsr[2];
+ u32 dxdllcr;
+ u32 dxdqtr;
+ u32 dxdqstr;
+ u32 reserved[10];
+};
+
+struct rk3288_ddr_publ {
+ u32 ridr;
+ u32 pir;
+ u32 pgcr;
+ u32 pgsr;
+ u32 dllgcr;
+ u32 acdllcr;
+ u32 ptr[3];
+ u32 aciocr;
+ u32 dxccr;
+ u32 dsgcr;
+ u32 dcr;
+ u32 dtpr[3];
+
[U-Boot] [PATCH v3 22/25] rockchip: Add SPI driver
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/Kconfig | 10 ++
drivers/spi/Makefile | 1 +
drivers/spi/rk_spi.c | 375 +++
drivers/spi/rk_spi.h | 121 +
4 files changed, 507 insertions(+)
create mode 100644 drivers/spi/rk_spi.c
create mode 100644 drivers/spi/rk_spi.h
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 357a335..52e1a56 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -51,3 +51,13 @@ config CADENCE_QSPI
Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
used to access the SPI NOR flash on platforms embedding this
Cadence IP core.
+
+config ROCKCHIP_SPI
+ bool "Rockchip SPI driver"
+ depends on DM_SPI
+ help
+ Enable the Rockchip SPI driver, used to access SPI NOR flash and
+ other SPI peripherals (such as the Chrome OS EC) on Rockchip SoCs.
+ This uses driver model and requires a device tree binding to
+ operate.
+
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index e288692..2d74ca4 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_SANDBOX_SPI) += sandbox_spi.o
obj-$(CONFIG_SH_SPI) += sh_spi.o
obj-$(CONFIG_SH_QSPI) += sh_qspi.o
obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
+obj-$(CONFIG_ROCKCHIP_SPI) += rk_spi.o
obj-$(CONFIG_TEGRA20_SFLASH) += tegra20_sflash.o
obj-$(CONFIG_TEGRA20_SLINK) += tegra20_slink.o
obj-$(CONFIG_TEGRA114_SPI) += tegra114_spi.o
diff --git a/drivers/spi/rk_spi.c b/drivers/spi/rk_spi.c
new file mode 100644
index 000..7ef0d63
--- /dev/null
+++ b/drivers/spi/rk_spi.c
@@ -0,0 +1,375 @@
+/*
+ * spi driver for rockchip
+ *
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2013 Rockchip Electronics
+ * Peter, Software Engineering, .
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "rk_spi.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rockchip_spi_platdata {
+ enum periph_id periph_id;
+ struct udevice *pinctrl;
+ s32 frequency; /* Default clock frequency, -1 for none */
+ fdt_addr_t base;
+ uint deactivate_delay_us; /* Delay to wait after deactivate */
+};
+
+struct rockchip_spi_priv {
+ struct rockchip_spi *regs;
+ struct udevice *clk_gpll;
+ unsigned int max_freq;
+ unsigned int mode;
+ enum periph_id periph_id; /* Peripheral ID for this device */
+ ulong last_transaction_us; /* Time of last transaction end */
+ u8 bits_per_word; /* max 16 bits per word */
+ u8 n_bytes;
+ unsigned int speed_hz;
+ unsigned int tmode;
+ uint input_rate;
+};
+
+#define SPI_FIFO_DEPTH 32
+
+static void rkspi_dump_regs(struct rockchip_spi *regs)
+{
+ debug("RK SPI registers:\n");
+ debug("=\n");
+ debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
+ debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
+ debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
+ debug("ser: \t\t0x%08x\n", readl(®s->ser));
+ debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
+ debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
+ debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
+ debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
+ debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
+ debug("sr: \t\t0x%08x\n", readl(®s->sr));
+ debug("imr: \t\t0x%08x\n", readl(®s->imr));
+ debug("isr: \t\t0x%08x\n", readl(®s->isr));
+ debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
+ debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
+ debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
+ debug("=\n");
+}
+
+static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
+{
+ writel(enable ? 1 : 0, ®s->enr);
+}
+
+static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
+{
+ uint clk_div;
+
+ clk_div = priv->input_rate / speed;
+ clk_div = (clk_div + 1) & 0xfffe;
+ debug("spi speed %u, div %u\n", speed, clk_div);
+
+ writel(clk_div, &priv->regs->baudr);
+}
+
+static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
+{
+ unsigned int delay = 1000;
+
+ while (delay--) {
+ if (!(readl(®s->sr) & SR_BUSY))
+ return 0;
+
+ udelay(1);
+ }
+ debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
+
+ return -ETIMEDOUT;
+}
+
+static void spi_cs_activate(struct rockchip_spi *regs, uint cs)
+{
+ debug("activate cs%u\n", cs);
+ writel(1 << cs, ®s->ser);
+}
+
+static void spi_cs_deactivate(str
[U-Boot] [PATCH v3 10/25] rockchip: Add basic peripheral and clock definitions
Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/clock.h| 45 ++
arch/arm/include/asm/arch-rockchip/hardware.h | 20 ++
arch/arm/include/asm/arch-rockchip/periph.h | 54 +++
3 files changed, 119 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/clock.h
create mode 100644 arch/arm/include/asm/arch-rockchip/hardware.h
create mode 100644 arch/arm/include/asm/arch-rockchip/periph.h
diff --git a/arch/arm/include/asm/arch-rockchip/clock.h
b/arch/arm/include/asm/arch-rockchip/clock.h
new file mode 100644
index 000..2e5ba86
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/clock.h
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_CLOCK_H
+#define _ASM_ARCH_CLOCK_H
+
+/* define pll mode */
+#define RKCLK_PLL_MODE_SLOW0
+#define RKCLK_PLL_MODE_NORMAL 1
+
+enum {
+ ROCKCHIP_SYSCON_NOC,
+ ROCKCHIP_SYSCON_GRF,
+ ROCKCHIP_SYSCON_SGRF,
+ ROCKCHIP_SYSCON_PMU,
+};
+
+/* Standard Rockchip clock numbers */
+enum rk_clk_id {
+ CLK_OSC,
+ CLK_ARM,
+ CLK_DDR,
+ CLK_CODEC,
+ CLK_GENERAL,
+ CLK_NEW,
+
+ CLK_COUNT,
+};
+
+static inline int rk_pll_id(enum rk_clk_id clk_id)
+{
+ return clk_id - 1;
+}
+
+/**
+ * rockchip_get_cru() - get a pointer to the clock/reset unit registers
+ *
+ * @return pointer to registers, or -ve error on error
+ */
+void *rockchip_get_cru(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/hardware.h
b/arch/arm/include/asm/arch-rockchip/hardware.h
new file mode 100644
index 000..d5af5b8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/hardware.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_HARDWARE_H
+#define _ASM_ARCH_HARDWARE_H
+
+#define RK_CLRSETBITS(clr, set)clr) | (set)) << 16) | set)
+#define RK_SETBITS(set)RK_CLRSETBITS(0, set)
+#define RK_CLRBITS(clr)RK_CLRSETBITS(clr, 0)
+
+#define TIMER7_BASE0xff810020
+
+#define rk_clrsetreg(addr, clr, set) writel((clr) << 16 | (set), addr)
+#define rk_clrreg(addr, clr) writel((clr) << 16, addr)
+#define rk_setreg(addr, set) writel(set, addr)
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/periph.h
b/arch/arm/include/asm/arch-rockchip/periph.h
new file mode 100644
index 000..fa6069b
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/periph.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * The peripherals supported by the hardware. This is used to specify clocks
+ * and pinctrl settings. Some SoCs will not support all of these, but it
+ * provides a common reference for common drivers to use.
+ */
+enum periph_id {
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_I2C0,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_SPI0,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_UART0,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LCDC0,
+ PERIPH_ID_LCDC1,
+ PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_HDMI,
+
+ PERIPH_ID_COUNT,
+
+ /* Some aliases */
+ PERIPH_ID_EMMC = PERIPH_ID_SDMMC0,
+ PERIPH_ID_SDCARD = PERIPH_ID_SDMMC1,
+ PERIPH_ID_UART_BT = PERIPH_ID_UART0,
+ PERIPH_ID_UART_BB = PERIPH_ID_UART1,
+ PERIPH_ID_UART_DBG = PERIPH_ID_UART2,
+ PERIPH_ID_UART_GPS = PERIPH_ID_UART3,
+ PERIPH_ID_UART_EXP = PERIPH_ID_UART4,
+};
+
+#endif
--
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[U-Boot] [PATCH v3 19/25] rockchip: Add an MMC driver
Add an MMC driver which supports RK3288, but may also support other SoCs.
It uses the Designware MMC device.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig| 9 +
drivers/mmc/Makefile | 1 +
drivers/mmc/rockchip_mmc.c | 98 ++
3 files changed, 108 insertions(+)
create mode 100644 drivers/mmc/rockchip_mmc.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 3e835f7..cd5f53c 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -10,6 +10,15 @@ config DM_MMC
appear as block devices in U-Boot and can support filesystems such
as EXT4 and FAT.
+config ROCKCHIP_MMC
+ bool "Rockchip SD/MMC controller support"
+ depends on DM && OF_CONTROL
+ help
+ This enables support for the Rockchip SD/MMM controller, which is
+ based on Designware IP. The device is compatible with SD 3.0,
+ SDIO 3.0 and MMC 4.5 and supports common eMMC chips as well as
+ removeable SD and micro-SD cards.
+
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on RMOBILE
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 2680c63..83e1ff3 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MXS_MMC) += mxsmmc.o
obj-$(CONFIG_OMAP_HSMMC) += omap_hsmmc.o
obj-$(CONFIG_X86) += pci_mmc.o
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
+obj-$(CONFIG_ROCKCHIP_MMC) += rockchip_mmc.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += rpmb.o
obj-$(CONFIG_S3C_SDI) += s3c_sdi.o
obj-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o
diff --git a/drivers/mmc/rockchip_mmc.c b/drivers/mmc/rockchip_mmc.c
new file mode 100644
index 000..430e7e5
--- /dev/null
+++ b/drivers/mmc/rockchip_mmc.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct rockchip_mmc_priv {
+ struct udevice *clk;
+ struct rk3288_grf *grf;
+ struct dwmci_host host;
+};
+
+static uint rockchip_mmc_get_mmc_clk(struct dwmci_host *host, uint freq)
+{
+ struct udevice *dev = host->priv;
+ struct rockchip_mmc_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = clk_set_periph_rate(priv->clk, PERIPH_ID_SDMMC0 + host->dev_index,
+ freq);
+ if (ret < 0) {
+ debug("%s: err=%d\n", __func__, ret);
+ return ret;
+ }
+
+ return freq;
+}
+
+static int rockchip_mmc_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rockchip_mmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+
+ host->name = dev->name;
+ host->ioaddr = (void *)dev_get_addr(dev);
+ host->buswidth = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
+ "bus-width", 4);
+ host->get_mmc_clk = rockchip_mmc_get_mmc_clk;
+ host->priv = dev;
+
+ /* TODO(s...@chromium.org): Remove the need for this hack */
+ host->dev_index = (ulong)host->ioaddr == 0xff0f ? 0 : 1;
+
+ return 0;
+}
+
+int rockchip_mmc_probe(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+ struct rockchip_mmc_priv *priv = dev_get_priv(dev);
+ struct dwmci_host *host = &priv->host;
+ u32 minmax[2];
+ int ret;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+ ret = uclass_get_device(UCLASS_CLK, CLK_GENERAL, &priv->clk);
+ if (ret)
+ return ret;
+
+ ret = fdtdec_get_int_array(gd->fdt_blob, dev->of_offset,
+ "clock-freq-min-max", minmax, 2);
+ if (!ret)
+ ret = add_dwmci(host, minmax[1], minmax[0]);
+ if (ret)
+ return ret;
+
+ upriv->mmc = host->mmc;
+
+ return 0;
+}
+
+static const struct udevice_id rockchip_mmc_ids[] = {
+ { .compatible = "rockchip,rk3288-dw-mshc" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_mmc_drv) = {
+ .name = "rockchip_mmc",
+ .id = UCLASS_MMC,
+ .of_match = rockchip_mmc_ids,
+ .ofdata_to_platdata = rockchip_mmc_ofdata_to_platdata,
+ .probe = rockchip_mmc_probe,
+ .priv_auto_alloc_size = sizeof(struct dwmci_host),
+};
--
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[U-Boot] [PATCH v3 11/25] power: Add support for ACT8846 PMIC
Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and
is connected to the I2C bus. This driver supports using a regulator driver
to access the regulators.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/Kconfig | 9 +
drivers/power/pmic/Makefile | 1 +
drivers/power/pmic/act8846.c | 90
include/power/act8846_pmic.h | 37 ++
4 files changed, 137 insertions(+)
create mode 100644 drivers/power/pmic/act8846.c
create mode 100644 include/power/act8846_pmic.h
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 164f421..0047a4c 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -10,6 +10,15 @@ config DM_PMIC
- 'drivers/power/pmic/pmic-uclass.c'
- 'include/power/pmic.h'
+config PMIC_ACT8846
+ bool "Enable support for the active-semi 8846 PMIC"
+ depends on DM_PMIC && DM_I2C
+ ---help---
+ This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout
+ regulators (LDOs). It also provides some GPIO, reset and battery
+ functions. It uses an I2C interface and is designed for use with
+ tablets and smartphones.
+
config DM_PMIC_MAX77686
bool "Enable Driver Model for PMIC MAX77686"
depends on DM_PMIC
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index ae86f04..4d62288 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_DM_PMIC) += pmic-uclass.o
obj-$(CONFIG_DM_PMIC_MAX77686) += max77686.o
obj-$(CONFIG_DM_PMIC_SANDBOX) += sandbox.o i2c_pmic_emul.o
+obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_POWER_LTC3676) += pmic_ltc3676.o
obj-$(CONFIG_POWER_MAX8998) += pmic_max8998.o
obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
diff --git a/drivers/power/pmic/act8846.c b/drivers/power/pmic/act8846.c
new file mode 100644
index 000..ff096b3
--- /dev/null
+++ b/drivers/power/pmic/act8846.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct pmic_child_info pmic_children_info[] = {
+ { .prefix = "REG", .driver = "act8846_reg"},
+ { },
+};
+
+static int act8846_reg_count(struct udevice *dev)
+{
+ return ACT8846_NUM_OF_REGS;
+}
+
+static int act8846_write(struct udevice *dev, uint reg, const uint8_t *buff,
+ int len)
+{
+ if (dm_i2c_write(dev, reg, buff, len)) {
+ debug("write error to device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int act8846_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
+{
+ if (dm_i2c_read(dev, reg, buff, len)) {
+ debug("read error from device: %p register: %#x!", dev, reg);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int act8846_bind(struct udevice *dev)
+{
+ const void *blob = gd->fdt_blob;
+ int regulators_node;
+ int children;
+
+ regulators_node = fdt_subnode_offset(blob, dev->of_offset,
+"regulators");
+ if (regulators_node <= 0) {
+ debug("%s: %s regulators subnode not found!", __func__,
+ dev->name);
+ return -ENXIO;
+ }
+
+ debug("%s: '%s' - found regulators subnode\n", __func__, dev->name);
+
+ children = pmic_bind_children(dev, regulators_node, pmic_children_info);
+ if (!children)
+ debug("%s: %s - no child found\n", __func__, dev->name);
+
+ /* Always return success for this device */
+ return 0;
+}
+
+static struct dm_pmic_ops act8846_ops = {
+ .reg_count = act8846_reg_count,
+ .read = act8846_read,
+ .write = act8846_write,
+};
+
+static const struct udevice_id act8846_ids[] = {
+ { .compatible = "active-semi,act8846" },
+ { }
+};
+
+U_BOOT_DRIVER(pmic_act8846) = {
+ .name = "act8846 pmic",
+ .id = UCLASS_PMIC,
+ .of_match = act8846_ids,
+ .bind = act8846_bind,
+ .ops = &act8846_ops,
+};
diff --git a/include/power/act8846_pmic.h b/include/power/act8846_pmic.h
new file mode 100644
index 000..a811f28
--- /dev/null
+++ b/include/power/act8846_pmic.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _PMIC_ACT8846_H_
+#define _PMIC_ACT8846_H_
+
+#include
+
+#define ACT8846_NUM_OF_REGS12
+
+#define BUCK_VOL_MASK 0x3f
+#define LDO_VOL_MASK 0x3f
+
+#define BUCK_EN_MASK 0x80
+#define LDO_EN_MASK 0x80
+
+#define VOL_MIN_IDX 0x00
+#define VOL_MAX_IDX 0x3f
+
+struct act8846_reg_table {
+ char*name;
+ charreg_c
[U-Boot] [PATCH v3 15/25] rockchip: rk3288: Add SoC reset driver
We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile | 7 +
arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47
2 files changed, 54 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3288/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3288/reset_rk3288.c
diff --git a/arch/arm/mach-rockchip/rk3288/Makefile
b/arch/arm/mach-rockchip/rk3288/Makefile
new file mode 100644
index 000..c6663f0
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2015 Google, Inc
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += reset_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
new file mode 100644
index 000..7affd11
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/reset_rk3288.c
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int rk3288_reset_request(struct udevice *dev, enum reset_t type)
+{
+ struct rk3288_cru *cru = rockchip_get_cru();
+
+ if (IS_ERR(cru))
+ return PTR_ERR(cru);
+ switch (type) {
+ case RESET_WARM:
+ writel(RK_CLRBITS(0x), &cru->cru_mode_con);
+ writel(0xeca8, &cru->cru_glb_srst_snd_value);
+ break;
+ case RESET_COLD:
+ writel(RK_CLRBITS(0x), &cru->cru_mode_con);
+ writel(0xfdb9, &cru->cru_glb_srst_fst_value);
+ break;
+ default:
+ return -EPROTONOSUPPORT;
+ }
+
+ return -EINPROGRESS;
+}
+
+static struct reset_ops rk3288_reset = {
+ .request= rk3288_reset_request,
+};
+
+U_BOOT_DRIVER(reset_rk3288) = {
+ .name = "rk3288_reset",
+ .id = UCLASS_RESET,
+ .ops= &rk3288_reset,
+};
--
2.4.3.573.g4eafbef
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 06/25] rockchip: Add the rkimage format to mkimage
Rockchip SoCs require certain formats for code that they execute, The
simplest format is a 4-byte header at the start of a binary file. Add
support for this so that we can create images that the boot ROM understands.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/image.c | 1 +
include/image.h | 3 ++-
tools/Makefile | 3 +++
tools/rkcommon.c | 72
tools/rkcommon.h | 28 ++
tools/rkimage.c | 65 ++
6 files changed, 171 insertions(+), 1 deletion(-)
create mode 100644 tools/rkcommon.c
create mode 100644 tools/rkcommon.h
create mode 100644 tools/rkimage.c
diff --git a/common/image.c b/common/image.c
index 9efacf8..1114206 100644
--- a/common/image.c
+++ b/common/image.c
@@ -151,6 +151,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_ATMELIMAGE, "atmelimage", "ATMEL ROM-Boot Image",},
{ IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin",},
{ IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", },
+ { IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 63c3d37..2daa74a 100644
--- a/include/image.h
+++ b/include/image.h
@@ -245,8 +245,9 @@ struct lmb;
#define IH_TYPE_X86_SETUP 20 /* x86 setup.bin Image */
#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
#define IH_TYPE_LOADABLE 22 /* A list of typeless images*/
+#define IH_TYPE_RKIMAGE23 /* Rockchip Boot Image
*/
-#define IH_TYPE_COUNT 23 /* Number of image types */
+#define IH_TYPE_COUNT 24 /* Number of image types */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 98414f7..55c8ae1 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -64,6 +64,8 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o
+
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
atmelimage.o \
@@ -90,6 +92,7 @@ dumpimage-mkimage-objs := aisimage.o \
os_support.o \
pblimage.o \
pbl_crc32.o \
+ $(ROCKCHIP_OBS) \
socfpgaimage.o \
lib/sha1.o \
lib/sha256.o \
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
new file mode 100644
index 000..4389622
--- /dev/null
+++ b/tools/rkcommon.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * Helper functions for Rockchip images
+ */
+
+#include "imagetool.h"
+#include
+#include
+#include "mkimage.h"
+#include "rkcommon.h"
+
+enum {
+ RK_SIGNATURE= 0x0ff0aa55,
+};
+
+/**
+ * struct header0_info - header block for boot ROM
+ *
+ * This is stored at SD card block 64 (where each block is 512 bytes, or at
+ * the start of SPI flash. It is encoded with RC4.
+ *
+ * @signature: Signature (must be RKSD_SIGNATURE)
+ * @disable_rc4: 0 to use rc4 for boot image, 1 to use plain binary
+ * @code1_offset: Offset in blocks of the SPL code from this header
+ * block. E.g. 4 means 2KB after the start of this header.
+ * Other fields are not used by U-Boot
+ */
+struct header0_info {
+ uint32_t signature;
+ uint8_t reserved[4];
+ uint32_t disable_rc4;
+ uint16_t code1_offset;
+ uint16_t code2_offset;
+ uint8_t reserved1[490];
+ uint16_t usflashdatasize;
+ uint16_t ucflashbootsize;
+ uint8_t reserved2[2];
+};
+
+static unsigned char rc4_key[16] = {
+ 124, 78, 3, 4, 85, 5, 9, 7,
+ 45, 44, 123, 56, 23, 13, 23, 17
+};
+
+int rkcommon_set_header(void *buf, uint file_size)
+{
+ struct header0_info *hdr;
+
+ if (file_size > RK_MAX_CODE1_SIZE)
+ return -ENOSPC;
+
+ memset(buf, '\0', RK_CODE1_OFFSET * RK_BLK_SIZE);
+ hdr = (struct header0_info *)buf;
+ hdr->signature = RK_SIGNATURE;
+ hdr->disable_rc4 = 1;
+ hdr->code1_offset = RK_CODE1_OFFSET;
+ hdr->code2_offset = 8;
+
+ hdr->usflashdatasize = (file_size + RK_BLK_SIZE - 1) / RK_BLK_SIZE;
+ hdr->usflashdatasize = (hdr->usflashdatasize + 3) & ~3;
+ hdr->ucflashbootsize = hdr->usflashdatasize;
+
+ debug("size=%x, %x\n", params->file_size, hdr->usflashdatasize);
+
+ rc4_encode(buf, RK_BLK_SIZE, rc4_key);
+
+ return 0;
+}
diff --git a/tools/rkcommon.h b/tools/rkcommon.h
new file mode
[U-Boot] [PATCH v3 14/25] rockchip: rk3288: Add header files for PMU and GRF
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768
arch/arm/include/asm/arch-rockchip/pmu_rk3288.h | 89 +++
2 files changed, 857 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3288.h
create mode 100644 arch/arm/include/asm/arch-rockchip/pmu_rk3288.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
new file mode 100644
index 000..0117a17
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3288.h
@@ -0,0 +1,768 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Copyright 2014 Rockchip Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#ifndef _ASM_ARCH_GRF_RK3288_H
+#define _ASM_ARCH_GRF_RK3288_H
+
+struct rk3288_grf_gpio_lh {
+ u32 l;
+ u32 h;
+};
+
+struct rk3288_grf {
+ u32 reserved[3];
+ u32 gpio1d_iomux;
+ u32 gpio2a_iomux;
+ u32 gpio2b_iomux;
+
+ u32 gpio2c_iomux;
+ u32 reserved2;
+ u32 gpio3a_iomux;
+ u32 gpio3b_iomux;
+
+ u32 gpio3c_iomux;
+ u32 gpio3dl_iomux;
+ u32 gpio3dh_iomux;
+ u32 gpio4al_iomux;
+
+ u32 gpio4ah_iomux;
+ u32 gpio4bl_iomux;
+ u32 reserved3;
+ u32 gpio4c_iomux;
+
+ u32 gpio4d_iomux;
+ u32 reserved4;
+ u32 gpio5b_iomux;
+ u32 gpio5c_iomux;
+
+ u32 reserved5;
+ u32 gpio6a_iomux;
+ u32 gpio6b_iomux;
+ u32 gpio6c_iomux;
+ u32 reserved6;
+ u32 gpio7a_iomux;
+ u32 gpio7b_iomux;
+ u32 gpio7cl_iomux;
+ u32 gpio7ch_iomux;
+ u32 reserved7;
+ u32 gpio8a_iomux;
+ u32 gpio8b_iomux;
+ u32 reserved8[30];
+ struct rk3288_grf_gpio_lh gpio_sr[8];
+ u32 gpio1_p[8][4];
+ u32 gpio1_e[8][4];
+ u32 gpio_smt;
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_status[22];
+ u32 reserved9[2];
+ u32 peridmac_con[4];
+ u32 ddrc0_con0;
+ u32 ddrc1_con0;
+ u32 cpu_con[5];
+ u32 reserved10[3];
+ u32 cpu_status0;
+ u32 reserved11;
+ u32 uoc0_con[5];
+ u32 uoc1_con[5];
+ u32 uoc2_con[4];
+ u32 uoc3_con[2];
+ u32 uoc4_con[2];
+ u32 pvtm_con[3];
+ u32 pvtm_status[3];
+ u32 io_vsel;
+ u32 saradc_testbit;
+ u32 tsadc_testbit_l;
+ u32 tsadc_testbit_h;
+ u32 os_reg[4];
+ u32 reserved12;
+ u32 soc_con15;
+ u32 soc_con16;
+};
+
+struct rk3288_sgrf {
+ u32 soc_con0;
+ u32 soc_con1;
+ u32 soc_con2;
+ u32 soc_con3;
+ u32 soc_con4;
+ u32 soc_con5;
+ u32 reserved1[(0x20-0x18)/4];
+ u32 busdmac_con[2];
+ u32 reserved2[(0x40-0x28)/4];
+ u32 cpu_con[3];
+ u32 reserved3[(0x50-0x4c)/4];
+ u32 soc_con6;
+ u32 soc_con7;
+ u32 soc_con8;
+ u32 soc_con9;
+ u32 soc_con10;
+ u32 soc_con11;
+ u32 soc_con12;
+ u32 soc_con13;
+ u32 soc_con14;
+ u32 soc_con15;
+ u32 soc_con16;
+ u32 soc_con17;
+ u32 soc_con18;
+ u32 soc_con19;
+ u32 soc_con20;
+ u32 soc_con21;
+ u32 reserved4[(0x100-0x90)/4];
+ u32 soc_status[2];
+ u32 reserved5[(0x120-0x108)/4];
+ u32 fast_boot_addr;
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+ GPIO1D3_SHIFT = 6,
+ GPIO1D3_MASK= 1,
+ GPIO1D3_GPIO= 0,
+ GPIO1D3_LCDC0_DCLK,
+
+ GPIO1D2_SHIFT = 4,
+ GPIO1D2_MASK= 1,
+ GPIO1D2_GPIO= 0,
+ GPIO1D2_LCDC0_DEN,
+
+ GPIO1D1_SHIFT = 2,
+ GPIO1D1_MASK= 1,
+ GPIO1D1_GPIO= 0,
+ GPIO1D1_LCDC0_VSYNC,
+
+ GPIO1D0_SHIFT = 0,
+ GPIO1D0_MASK= 1,
+ GPIO1D0_GPIO= 0,
+ GPIO1D0_LCDC0_HSYNC,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+ GPIO2C1_SHIFT = 2,
+ GPIO2C1_MASK= 1,
+ GPIO2C1_GPIO= 0,
+ GPIO2C1_I2C3CAM_SDA,
+
+ GPIO2C0_SHIFT = 0,
+ GPIO2C0_MASK= 1,
+ GPIO2C0_GPIO= 0,
+ GPIO2C0_I2C3CAM_SCL,
+};
+
+/* GRF_GPIO3A_IOMUX */
+enum {
+ GPIO3A7_SHIFT = 14,
+ GPIO3A7_MASK= 3,
+ GPIO3A7_GPIO= 0,
+ GPIO3A7_FLASH0_DATA7,
+ GPIO3A7_EMMC_DATA7,
+
+ GPIO3A6_SHIFT = 12,
+ GPIO3A6_MASK
[U-Boot] [PATCH v3 07/25] rockchip: Add support for the SD image
The Rockchip boot ROM requires a particular file format. It consists of
64KB of zeroes, a 512-byte header encoded with RC4, and then some executable
code.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/image.c | 1 +
include/image.h | 3 +-
tools/Makefile | 2 +-
tools/rksd.c| 102
4 files changed, 106 insertions(+), 2 deletions(-)
create mode 100644 tools/rksd.c
diff --git a/common/image.c b/common/image.c
index 1114206..85b88b2 100644
--- a/common/image.c
+++ b/common/image.c
@@ -152,6 +152,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_X86_SETUP, "x86_setup", "x86 setup.bin",},
{ IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", },
{ IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
+ { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 2daa74a..ea16205 100644
--- a/include/image.h
+++ b/include/image.h
@@ -246,8 +246,9 @@ struct lmb;
#define IH_TYPE_LPC32XXIMAGE 21 /* x86 setup.bin Image */
#define IH_TYPE_LOADABLE 22 /* A list of typeless images*/
#define IH_TYPE_RKIMAGE23 /* Rockchip Boot Image
*/
+#define IH_TYPE_RKSD 24 /* Rockchip SD card */
-#define IH_TYPE_COUNT 24 /* Number of image types */
+#define IH_TYPE_COUNT 25 /* Number of image types */
/*
* Compression Types
diff --git a/tools/Makefile b/tools/Makefile
index 55c8ae1..333dec6 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -64,7 +64,7 @@ RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
rsa-sign.o rsa-verify.o rsa-checksum.o \
rsa-mod-exp.o)
-ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o
+ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
diff --git a/tools/rksd.c b/tools/rksd.c
new file mode 100644
index 000..2efcd68
--- /dev/null
+++ b/tools/rksd.c
@@ -0,0 +1,102 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * See README.rockchip for details of the rksd format
+ */
+
+#include "imagetool.h"
+#include
+#include
+#include "mkimage.h"
+#include "rkcommon.h"
+
+enum {
+ RKSD_HEADER0_START = 64 * RK_BLK_SIZE,
+ RKSD_SPL_HDR_START = RKSD_HEADER0_START +
+ RK_CODE1_OFFSET * RK_BLK_SIZE,
+ RKSD_SPL_START = RKSD_SPL_HDR_START + 4,
+ RKSD_HEADER_LEN = RKSD_SPL_START,
+};
+
+static char dummy_hdr[RKSD_HEADER_LEN];
+
+static int rksd_check_params(struct image_tool_params *params)
+{
+ return 0;
+}
+
+static int rksd_verify_header(unsigned char *buf, int size,
+struct image_tool_params *params)
+{
+ return 0;
+}
+
+static void rksd_print_header(const void *buf)
+{
+}
+
+static void rksd_set_header(void *buf, struct stat *sbuf, int ifd,
+ struct image_tool_params *params)
+{
+ unsigned int size;
+ int ret;
+
+ /* Zero the whole header. The first 32KB is empty */
+ memset(buf, '\0', RKSD_HEADER0_START);
+
+ size = params->file_size - RKSD_SPL_HDR_START;
+ ret = rkcommon_set_header(buf + RKSD_HEADER0_START, size);
+ if (ret) {
+ /* TODO(s...@chromium.org): This method should return an error
*/
+ printf("Warning: SPL image is too large (size %#x) and will not
boot\n",
+ size);
+ }
+
+ memcpy(buf + RKSD_SPL_HDR_START, "RK32", 4);
+}
+
+static int rksd_extract_subimage(void *buf, struct image_tool_params *params)
+{
+ return 0;
+}
+
+static int rksd_check_image_type(uint8_t type)
+{
+ if (type == IH_TYPE_RKSD)
+ return EXIT_SUCCESS;
+ else
+ return EXIT_FAILURE;
+}
+
+/* We pad the file out to a fixed size - this method returns that size */
+static int rksd_vrec_header(struct image_tool_params *params,
+ struct image_type_params *tparams)
+{
+ int pad_size;
+
+ pad_size = RKSD_SPL_HDR_START + RK_MAX_CODE1_SIZE;
+ debug("pad_size %x\n", pad_size);
+
+ return pad_size - params->file_size;
+}
+
+/*
+ * rk_sd parameters
+ */
+U_BOOT_IMAGE_TYPE(
+ rksd,
+ "Rockchip SD Boot Image support",
+ RKSD_HEADER_LEN,
+ dummy_hdr,
+ rksd_check_params,
+ rksd_verify_header,
+ rksd_print_header,
+ rksd_set_header,
+ rksd_extract_subimage,
[U-Boot] [PATCH v3 09/25] rockchip: gpio: Add rockchip GPIO driver
This supports RK3288 at present. It does not implement functions or support
for pull up/down.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/gpio.h | 28 +++
drivers/gpio/Kconfig | 9 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/rk_gpio.c| 123 ++
4 files changed, 161 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/gpio.h
create mode 100644 drivers/gpio/rk_gpio.c
diff --git a/arch/arm/include/asm/arch-rockchip/gpio.h
b/arch/arm/include/asm/arch-rockchip/gpio.h
new file mode 100644
index 000..e39218d
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+struct rockchip_gpio_regs {
+ u32 swport_dr;
+ u32 swport_ddr;
+ u32 reserved0[(0x30 - 0x08) / 4];
+ u32 inten;
+ u32 intmask;
+ u32 inttype_level;
+ u32 int_polarity;
+ u32 int_status;
+ u32 int_rawstatus;
+ u32 debounce;
+ u32 porta_eoi;
+ u32 ext_port;
+ u32 reserved1[(0x60 - 0x54) / 4];
+ u32 ls_sync;
+};
+check_member(rockchip_gpio_regs, ls_sync, 0x60);
+
+#endif
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 0c43777..8f5d3e7 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -15,6 +15,15 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config ROCKCHIP_GPIO
+ bool "Rockchip GPIO driver"
+ depends on DM_GPIO
+ help
+ Support GPIO access on Rockchip SoCs. The GPIOs are arranged into
+ a number of banks (different for each SoC type) each with 32 GPIOs.
+ The GPIOs for a device are defined in the device tree with one node
+ for each bank.
+
config SANDBOX_GPIO
bool "Enable sandbox GPIO driver"
depends on SANDBOX && DM && DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 67c6374..bdd2d7e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_MXC_GPIO)+= mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o
obj-$(CONFIG_PCA953X) += pca953x.o
obj-$(CONFIG_PCA9698) += pca9698.o
+obj-$(CONFIG_ROCKCHIP_GPIO)+= rk_gpio.o
obj-$(CONFIG_S5P) += s5p_gpio.o
obj-$(CONFIG_SANDBOX_GPIO) += sandbox.o
obj-$(CONFIG_SPEAR_GPIO) += spear_gpio.o
diff --git a/drivers/gpio/rk_gpio.c b/drivers/gpio/rk_gpio.c
new file mode 100644
index 000..fbdf9f3
--- /dev/null
+++ b/drivers/gpio/rk_gpio.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, .
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ ROCKCHIP_GPIOS_PER_BANK = 32,
+};
+
+#define OFFSET_TO_BIT(bit) (1UL << (bit))
+
+struct rockchip_gpio_priv {
+ struct rockchip_gpio_regs *regs;
+ char name[2];
+};
+
+static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
+{
+ struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ struct rockchip_gpio_regs *regs = priv->regs;
+
+ clrbits_le32(®s->swport_ddr, OFFSET_TO_BIT(offset));
+
+ return 0;
+}
+
+static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ struct rockchip_gpio_regs *regs = priv->regs;
+ int mask = OFFSET_TO_BIT(offset);
+
+ clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
+ setbits_le32(®s->swport_ddr, mask);
+
+ return 0;
+}
+
+static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
+{
+ struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ struct rockchip_gpio_regs *regs = priv->regs;
+
+ return readl(®s->ext_port) & OFFSET_TO_BIT(offset);
+}
+
+static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
+ int value)
+{
+ struct rockchip_gpio_priv *priv = dev_get_priv(dev);
+ struct rockchip_gpio_regs *regs = priv->regs;
+ int mask = OFFSET_TO_BIT(offset);
+
+ clrsetbits_le32(®s->swport_dr, mask, value ? mask : 0);
+
+ return 0;
+}
+
+static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
+{
+ return -ENOSYS;
+}
+
+static int rockchip_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
+ struct fdtdec_phandle_args *args)
+{
+ desc->offset = args->args[0];
+ desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
+
+ return 0;
+}
+
+static int rockchip_gpio_probe(struct
[U-Boot] [PATCH v3 13/25] rockchip: rk3288: Add clock driver
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3288.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++
drivers/clk/Makefile| 1 +
drivers/clk/clk_rk3288.c| 618
3 files changed, 804 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3288.h
create mode 100644 drivers/clk/clk_rk3288.c
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
new file mode 100644
index 000..7ebcc40
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ * Peter, Software Engineering, .
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_CRU_RK3288_H
+#define _ASM_ARCH_CRU_RK3288_H
+
+#define OSC_HZ (24 * 1000 * 1000)
+
+#define APLL_HZ(1800 * 100)
+#define GPLL_HZ(594 * 100)
+#define CPLL_HZ(384 * 100)
+#define NPLL_HZ(384 * 100)
+
+/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
+#define PD_BUS_ACLK_HZ 29700
+#define PD_BUS_HCLK_HZ 14850
+#define PD_BUS_PCLK_HZ 7425
+
+#define PERI_ACLK_HZ 14850
+#define PERI_HCLK_HZ 14850
+#define PERI_PCLK_HZ 7425
+
+struct rk3288_cru {
+ struct rk3288_pll {
+ u32 con0;
+ u32 con1;
+ u32 con2;
+ u32 con3;
+ } pll[5];
+ u32 cru_mode_con;
+ u32 reserved0[3];
+ u32 cru_clksel_con[43];
+ u32 reserved1[21];
+ u32 cru_clkgate_con[19];
+ u32 reserved2;
+ u32 cru_glb_srst_fst_value;
+ u32 cru_glb_srst_snd_value;
+ u32 cru_softrst_con[12];
+ u32 cru_misc_con;
+ u32 cru_glb_cnt_th;
+ u32 cru_glb_rst_con;
+ u32 reserved3;
+ u32 cru_glb_rst_st;
+ u32 reserved4;
+ u32 cru_sdmmc_con[2];
+ u32 cru_sdio0_con[2];
+ u32 cru_sdio1_con[2];
+ u32 cru_emmc_con[2];
+};
+check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
+
+/* CRU_CLKSEL11_CON */
+enum {
+ HSICPHY_DIV_SHIFT = 8,
+ HSICPHY_DIV_MASK= 0x3f,
+
+ MMC0_PLL_SHIFT = 6,
+ MMC0_PLL_MASK = 3,
+ MMC0_PLL_SELECT_CODEC = 0,
+ MMC0_PLL_SELECT_GENERAL,
+ MMC0_PLL_SELECT_24MHZ,
+
+ MMC0_DIV_SHIFT = 0,
+ MMC0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL12_CON */
+enum {
+ EMMC_PLL_SHIFT = 0xe,
+ EMMC_PLL_MASK = 3,
+ EMMC_PLL_SELECT_CODEC = 0,
+ EMMC_PLL_SELECT_GENERAL,
+ EMMC_PLL_SELECT_24MHZ,
+
+ EMMC_DIV_SHIFT = 8,
+ EMMC_DIV_MASK = 0x3f,
+
+ SDIO0_PLL_SHIFT = 6,
+ SDIO0_PLL_MASK = 3,
+ SDIO0_PLL_SELECT_CODEC = 0,
+ SDIO0_PLL_SELECT_GENERAL,
+ SDIO0_PLL_SELECT_24MHZ,
+
+ SDIO0_DIV_SHIFT = 0,
+ SDIO0_DIV_MASK = 0x3f,
+};
+
+/* CRU_CLKSEL25_CON */
+enum {
+ SPI1_PLL_SHIFT = 0xf,
+ SPI1_PLL_MASK = 1,
+ SPI1_PLL_SELECT_CODEC = 0,
+ SPI1_PLL_SELECT_GENERAL,
+
+ SPI1_DIV_SHIFT = 8,
+ SPI1_DIV_MASK = 0x7f,
+
+ SPI0_PLL_SHIFT = 7,
+ SPI0_PLL_MASK = 1,
+ SPI0_PLL_SELECT_CODEC = 0,
+ SPI0_PLL_SELECT_GENERAL,
+
+ SPI0_DIV_SHIFT = 0,
+ SPI0_DIV_MASK = 0x7f,
+};
+
+/* CRU_CLKSEL39_CON */
+enum {
+ ACLK_HEVC_PLL_SHIFT = 0xe,
+ ACLK_HEVC_PLL_MASK = 3,
+ ACLK_HEVC_PLL_SELECT_CODEC = 0,
+ ACLK_HEVC_PLL_SELECT_GENERAL,
+ ACLK_HEVC_PLL_SELECT_NEW,
+
+ ACLK_HEVC_DIV_SHIFT = 8,
+ ACLK_HEVC_DIV_MASK = 0x1f,
+
+ SPI2_PLL_SHIFT = 7,
+ SPI2_PLL_MASK = 1,
+ SPI2_PLL_SELECT_CODEC = 0,
+ SPI2_PLL_SELECT_GENERAL,
+
+ SPI2_DIV_SHIFT = 0,
+ SPI2_DIV_MASK = 0x7f,
+};
+
+/* CRU_MODE_CON */
+enum {
+ NPLL_WORK_SHIFT = 0xe,
+ NPLL_WORK_MASK = 3,
+ NPLL_WORK_SLOW = 0,
+ NPLL_WORK_NORMAL,
+ NPLL_WORK_DEEP,
+
+ GPLL_WORK_SHIFT = 0xc,
+ GPLL_WORK_MASK = 3,
+ GPLL_WORK_SLOW = 0,
+ GPLL_WORK_NORMAL,
+ GPLL_WORK_DEEP,
+
+ CPLL_WORK_SHIFT = 8,
+ CPLL_WORK_MASK = 3,
+ CPLL_WORK_SLOW = 0,
+ CPLL_WORK_NORMAL,
+ CPLL_WORK_DEEP,
+
+ DPLL_WORK_SHIFT = 4,
+ DPLL_WORK_MASK = 3,
+ DPLL_WORK_SLOW = 0,
+ DPLL_WORK_NORMAL,
+ DPLL_WORK_DEEP,
+
+ APLL_WORK_SHIFT = 0,
+ APLL_WORK_MASK
[U-Boot] [PATCH v3 12/25] power: regulator: Add a driver for ACT8846 regulators
Add a full regulator driver for the ACT8846. This provides easy access to
voltage and current settings for each regulator.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/Kconfig | 9 +++
drivers/power/regulator/Makefile | 1 +
drivers/power/regulator/act8846.c | 155 ++
3 files changed, 165 insertions(+)
create mode 100644 drivers/power/regulator/act8846.c
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index 6289b83..618019a 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -16,6 +16,15 @@ config DM_REGULATOR
for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_node()
otherwise. Detailed information can be found in the header file.
+config REGULATOR_ACT8846
+ bool "Enable driver for ACT8846 regulator"
+ depends on DM_REGULATOR && PMIC_ACT8846
+ ---help---
+ Enable support for the regulator functions of the ACT8846 PMIC. The
+ driver implements get/set api for the various BUCKS and LDOS supported
+ by the PMIC device. This driver is controlled by a device tree node
+ which includes voltage limits.
+
config DM_REGULATOR_MAX77686
bool "Enable Driver Model for REGULATOR MAX77686"
depends on DM_REGULATOR && DM_PMIC_MAX77686
diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile
index 96aa624..f2b1f82 100644
--- a/drivers/power/regulator/Makefile
+++ b/drivers/power/regulator/Makefile
@@ -6,6 +6,7 @@
#
obj-$(CONFIG_DM_REGULATOR) += regulator-uclass.o
+obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
obj-$(CONFIG_DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
diff --git a/drivers/power/regulator/act8846.c
b/drivers/power/regulator/act8846.c
new file mode 100644
index 000..255f8b0
--- /dev/null
+++ b/drivers/power/regulator/act8846.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * Based on Rockchip's drivers/power/pmic/pmic_act8846.c:
+ * Copyright (C) 2012 rockchips
+ * zyw
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static const u16 voltage_map[] = {
+ 600, 625, 650, 675, 700, 725, 750, 775,
+ 800, 825, 850, 875, 900, 925, 950, 975,
+ 1000, 1025, 1050, 1075, 1100, 1125, 1150, 1175,
+ 1200, 1250, 1300, 1350, 1400, 1450, 1500, 1550,
+ 1600, 1650, 1700, 1750, 1800, 1850, 1900, 1950,
+ 2000, 2050, 2100, 2150, 2200, 2250, 2300, 2350,
+ 2400, 2500, 2600, 2700, 2800, 2900, 3000, 3100,
+ 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900,
+};
+
+enum {
+ REG_SYS0,
+ REG_SYS1,
+ REG1_VOL= 0x10,
+ REG1_CTL= 0X11,
+ REG2_VOL0 = 0x20,
+ REG2_VOL1,
+ REG2_CTL,
+ REG3_VOL0 = 0x30,
+ REG3_VOL1,
+ REG3_CTL,
+ REG4_VOL0 = 0x40,
+ REG4_VOL1,
+ REG4_CTL,
+ REG5_VOL= 0x50,
+ REG5_CTL,
+ REG6_VOL= 0X58,
+ REG6_CTL,
+ REG7_VOL= 0x60,
+ REG7_CTL,
+ REG8_VOL= 0x68,
+ REG8_CTL,
+ REG9_VOL= 0x70,
+ REG9_CTL,
+ REG10_VOL = 0x80,
+ REG10_CTL,
+ REG11_VOL = 0x90,
+ REG11_CTL,
+ REG12_VOL = 0xa0,
+ REG12_CTL,
+ REG13 = 0xb1,
+};
+
+static const u8 addr_vol[] = {
+ 0, REG1_VOL, REG2_VOL0, REG3_VOL0, REG4_VOL0,
+ REG5_VOL, REG6_VOL, REG7_VOL, REG8_VOL, REG9_VOL,
+ REG10_VOL, REG11_VOL, REG12_VOL,
+};
+
+static const u8 addr_ctl[] = {
+ 0, REG1_CTL, REG2_CTL, REG3_CTL, REG4_CTL,
+ REG5_CTL, REG6_CTL, REG7_CTL, REG8_CTL, REG9_CTL,
+ REG10_CTL, REG11_CTL, REG12_CTL,
+};
+
+static int check_volt_table(const u16 *volt_table, int uvolt)
+{
+ int i;
+
+ for (i = VOL_MIN_IDX; i < VOL_MAX_IDX; i++) {
+ if (uvolt <= (volt_table[i] * 1000))
+ return i;
+ }
+ return -EINVAL;
+}
+
+static int reg_get_value(struct udevice *dev)
+{
+ int reg = dev->driver_data;
+ int ret;
+
+ ret = pmic_reg_read(dev->parent, reg);
+ if (ret < 0)
+ return ret;
+
+ return voltage_map[ret & LDO_VOL_MASK] * 1000;
+}
+
+static int reg_set_value(struct udevice *dev, int uvolt)
+{
+ int reg = dev->driver_data;
+ int val;
+
+ val = check_volt_table(voltage_map, uvolt);
+ if (val < 0)
+ return val;
+
+ return pmic_clrsetbits(dev->parent, addr_vol[reg], LDO_VOL_MASK, val);
+}
+
+static int reg_set_enable(struct udevice *dev, bool enable)
+{
+ int reg = dev->driver_data;
+
+ return pmic_clrsetbits(dev->parent, addr_ctl[reg], LDO_EN_MASK,
+ enable ? LDO_EN_MASK
[U-Boot] [PATCH v3 02/25] rockchip: Bring in RK3288 device tree file includes and bindings
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add device tree bindings for CRU and DMC
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/rk3288-thermal.dtsi | 88 ++
arch/arm/dts/rk3288.dtsi | 1458
.../clock/rockchip,rk3188-cru.txt | 61 +
.../clock/rockchip,rk3288-cru.txt | 61 +
.../clock/rockchip,rk3288-dmc.txt | 155 +++
doc/device-tree-bindings/clock/rockchip.txt| 77 ++
.../pinctrl/rockchip,pinctrl.txt | 157 +++
.../thermal/rockchip-thermal.txt | 68 +
include/dt-bindings/clock/rk3288-cru.h | 370 +
include/dt-bindings/clock/rockchip,rk808.h | 11 +
include/dt-bindings/pinctrl/rockchip.h | 26 +
include/dt-bindings/power-domain/rk3288.h | 11 +
12 files changed, 2543 insertions(+)
create mode 100644 arch/arm/dts/rk3288-thermal.dtsi
create mode 100644 arch/arm/dts/rk3288.dtsi
create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3188-cru.txt
create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-cru.txt
create mode 100644 doc/device-tree-bindings/clock/rockchip,rk3288-dmc.txt
create mode 100644 doc/device-tree-bindings/clock/rockchip.txt
create mode 100644 doc/device-tree-bindings/pinctrl/rockchip,pinctrl.txt
create mode 100644 doc/device-tree-bindings/thermal/rockchip-thermal.txt
create mode 100644 include/dt-bindings/clock/rk3288-cru.h
create mode 100644 include/dt-bindings/clock/rockchip,rk808.h
create mode 100644 include/dt-bindings/pinctrl/rockchip.h
create mode 100644 include/dt-bindings/power-domain/rk3288.h
diff --git a/arch/arm/dts/rk3288-thermal.dtsi b/arch/arm/dts/rk3288-thermal.dtsi
new file mode 100644
index 000..59482c1
--- /dev/null
+++ b/arch/arm/dts/rk3288-thermal.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Device Tree Source for RK3288 SoC thermal
+ *
+ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:GPL-2.0
+ */
+
+#include
+
+reserve_thermal: reserve_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&tsadc 0>;
+
+};
+
+cpu_thermal: cpu_thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&tsadc 1>;
+ linux,hwmon;
+
+ trips {
+ cpu_alert0: cpu_alert0 {
+ temperature = <7>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_alert1: cpu_alert1 {
+ temperature = <75000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ cpu_crit: cpu_crit {
+ temperature = <10>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT 6>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+gpu_thermal: gpu_thermal {
+ polling-delay-passive = <100>; /* milliseconds */
+ polling-delay = <5000>; /* milliseconds */
+
+ /* sensor ID */
+ thermal-sensors = <&tsadc 2>;
+ linux,hwmon;
+
+ trips {
+ gpu_alert0: gpu_alert0 {
+ temperature = <8>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ gpu_crit: gpu_crit {
+ temperature = <10>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&gpu_alert0>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+};
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
ne
[U-Boot] [PATCH v3 01/25] rockchip: Add serial support
Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v3:
- Update clock rate to always be 24MHz
Changes in v2: None
drivers/serial/Kconfig | 9 +
drivers/serial/Makefile | 1 +
drivers/serial/serial_rockchip.c | 43
3 files changed, 53 insertions(+)
create mode 100644 drivers/serial/serial_rockchip.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 4829284..3544d66 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -76,6 +76,15 @@ config DEBUG_UART_SHIFT
value. Use this value to specify the shift to use, where 0=byte
registers, 2=32-bit word registers, etc.
+config ROCKCHIP_SERIAL
+ bool "Rockchip on-chip UART support"
+ depends on ARCH_UNIPHIER && DM_SERIAL
+ help
+ Select this to enable a debug UART for Rockchip devices. This uses
+ the ns16550 driver. You will need to #define CONFIG_SYS_NS16550 in
+ your board config header. The clock input is automatically set to
+ use the oscillator (24MHz).
+
config SANDBOX_SERIAL
bool "Sandbox UART support"
depends on SANDBOX && DM
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index d183eed..b926b49 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ZYNQ_SERIAL) += serial_zynq.o
obj-$(CONFIG_BFIN_SERIAL) += serial_bfin.o
obj-$(CONFIG_FSL_LPUART) += serial_lpuart.o
obj-$(CONFIG_MXS_AUART) += mxs_auart.o
+obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
obj-$(CONFIG_ARC_SERIAL) += serial_arc.o
obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
diff --git a/drivers/serial/serial_rockchip.c b/drivers/serial/serial_rockchip.c
new file mode 100644
index 000..0e7bbfc
--- /dev/null
+++ b/drivers/serial/serial_rockchip.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+static const struct udevice_id rockchip_serial_ids[] = {
+ { .compatible = "rockchip,rk3288-uart" },
+ { }
+};
+
+static int rockchip_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ns16550_platdata *plat = dev_get_platdata(dev);
+ int ret;
+
+ ret = ns16550_serial_ofdata_to_platdata(dev);
+ if (ret)
+ return ret;
+
+ /* Do all Rockchip parts use 24MHz? */
+ plat->clock = 24 * 100;
+
+ return 0;
+}
+
+U_BOOT_DRIVER(serial_ns16550) = {
+ .name = "serial_rockchip",
+ .id = UCLASS_SERIAL,
+ .of_match = rockchip_serial_ids,
+ .ofdata_to_platdata = rockchip_serial_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+ .priv_auto_alloc_size = sizeof(struct NS16550),
+ .probe = ns16550_serial_probe,
+ .ops= &ns16550_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 08/25] rockchip: Add support for the SPI image
The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format. This allows booting from SPI flash on supported
machines.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/image.c | 1 +
include/image.h | 3 +-
tools/rkspi.c | 119
3 files changed, 122 insertions(+), 1 deletion(-)
create mode 100644 tools/rkspi.c
diff --git a/common/image.c b/common/image.c
index 85b88b2..bcb1a12 100644
--- a/common/image.c
+++ b/common/image.c
@@ -153,6 +153,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_LPC32XXIMAGE, "lpc32xximage", "LPC32XX Boot Image", },
{ IH_TYPE_RKIMAGE,"rkimage","Rockchip Boot Image" },
{ IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" },
+ { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index ea16205..b4c4fd7 100644
--- a/include/image.h
+++ b/include/image.h
@@ -247,8 +247,9 @@ struct lmb;
#define IH_TYPE_LOADABLE 22 /* A list of typeless images*/
#define IH_TYPE_RKIMAGE23 /* Rockchip Boot Image
*/
#define IH_TYPE_RKSD 24 /* Rockchip SD card */
+#define IH_TYPE_RKSPI 25 /* Rockchip SD card */
-#define IH_TYPE_COUNT 25 /* Number of image types */
+#define IH_TYPE_COUNT 26 /* Number of image types */
/*
* Compression Types
diff --git a/tools/rkspi.c b/tools/rkspi.c
new file mode 100644
index 000..a3c4c73
--- /dev/null
+++ b/tools/rkspi.c
@@ -0,0 +1,119 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ *
+ * See README.rockchip for details of the rkspi format
+ */
+
+#include "imagetool.h"
+#include
+#include
+#include "mkimage.h"
+#include "rkcommon.h"
+
+enum {
+ RKSPI_SPL_HDR_START = RK_CODE1_OFFSET * RK_BLK_SIZE,
+ RKSPI_SPL_START = RKSPI_SPL_HDR_START + 4,
+ RKSPI_HEADER_LEN= RKSPI_SPL_START,
+ RKSPI_SECT_LEN = RK_BLK_SIZE * 4,
+};
+
+static char dummy_hdr[RKSPI_HEADER_LEN];
+
+static int rkspi_check_params(struct image_tool_params *params)
+{
+ return 0;
+}
+
+static int rkspi_verify_header(unsigned char *buf, int size,
+ struct image_tool_params *params)
+{
+ return 0;
+}
+
+static void rkspi_print_header(const void *buf)
+{
+}
+
+static void rkspi_set_header(void *buf, struct stat *sbuf, int ifd,
+struct image_tool_params *params)
+{
+ int sector;
+ unsigned int size;
+ int ret;
+
+ size = params->orig_file_size;
+ ret = rkcommon_set_header(buf, size);
+ debug("size %x\n", size);
+ if (ret) {
+ /* TODO(s...@chromium.org): This method should return an error
*/
+ printf("Warning: SPL image is too large (size %#x) and will not
boot\n",
+ size);
+ }
+
+ memcpy(buf + RKSPI_SPL_HDR_START, "RK32", 4);
+
+ /*
+* Spread the image out so we only use the first 2KB of each 4KB
+* region. This is a feature of the SPI format required by the Rockchip
+* boot ROM. Its rationale is unknown.
+*/
+ for (sector = size / RKSPI_SECT_LEN - 1; sector >= 0; sector--) {
+ printf("sector %u\n", sector);
+ memmove(buf + sector * RKSPI_SECT_LEN * 2,
+ buf + sector * RKSPI_SECT_LEN,
+ RKSPI_SECT_LEN);
+ memset(buf + sector * RKSPI_SECT_LEN * 2 + RKSPI_SECT_LEN,
+ '\0', RKSPI_SECT_LEN);
+ }
+}
+
+static int rkspi_extract_subimage(void *buf, struct image_tool_params *params)
+{
+ return 0;
+}
+
+static int rkspi_check_image_type(uint8_t type)
+{
+ if (type == IH_TYPE_RKSPI)
+ return EXIT_SUCCESS;
+ else
+ return EXIT_FAILURE;
+}
+
+/* We pad the file out to a fixed size - this method returns that size */
+static int rkspi_vrec_header(struct image_tool_params *params,
+struct image_type_params *tparams)
+{
+ int pad_size;
+
+ pad_size = (RK_MAX_CODE1_SIZE + 0x7ff) / 0x800 * 0x800;
+ params->orig_file_size = pad_size;
+
+ /* We will double the image size due to the SPI format */
+ pad_size *= 2;
+ pad_size += RKSPI_SPL_HDR_START;
+ debug("pad_size %x\n", pad_size);
+
+ return pad_size - params->file_size;
+}
+
+/*
+ * rk_spi parameters
+ */
[U-Boot] [PATCH v3 03/25] rockchip: rk3288: dts: Make core devices available early
In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/rk3288.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 6b5145c..0f49709 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -16,6 +16,15 @@
interrupt-parent = <&gic>;
aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ gpio5 = &gpio5;
+ gpio6 = &gpio6;
+ gpio7 = &gpio7;
+ gpio8 = &gpio8;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -454,6 +463,7 @@
};
dmc: dmc@ff61 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
@@ -569,11 +579,13 @@
};
pmu: power-management@ff73 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff73 0x100>;
};
sgrf: syscon@ff74 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-sgrf", "syscon";
reg = <0xff74 0x1000>;
};
@@ -582,6 +594,7 @@
compatible = "rockchip,rk3288-cru";
reg = <0xff76 0x1000>;
rockchip,grf = <&grf>;
+ u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
@@ -600,6 +613,7 @@
};
grf: syscon@ff77 {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-grf", "syscon";
reg = <0xff77 0x1000>;
};
@@ -804,6 +818,7 @@
};
noc: syscon@ffac {
+ u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac 0x2000>;
};
--
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[U-Boot] [PATCH v3 04/25] mkimage: Allow padding to any length
At present there is an arbitrary limit of 4KB for padding. Rockchip needs
more than that, so remove this restriction.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/mkimage.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/tools/mkimage.c b/tools/mkimage.c
index e81d455..c50af05 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -488,12 +488,6 @@ copy_file (int ifd, const char *datafile, int pad)
int size;
struct image_type_params *tparams = imagetool_get_type(params.type);
- if (pad >= sizeof(zeros)) {
- fprintf(stderr, "%s: Can't pad to %d\n",
- params.cmdname, pad);
- exit(EXIT_FAILURE);
- }
-
memset(zeros, 0, sizeof(zeros));
if (params.vflag) {
@@ -563,11 +557,18 @@ copy_file (int ifd, const char *datafile, int pad)
exit (EXIT_FAILURE);
}
} else if (pad > 1) {
- if (write(ifd, (char *)&zeros, pad) != pad) {
- fprintf(stderr, "%s: Write error on %s: %s\n",
- params.cmdname, params.imagefile,
- strerror(errno));
- exit(EXIT_FAILURE);
+ while (pad > 0) {
+ int todo = sizeof(zeros);
+
+ if (todo > pad)
+ todo = pad;
+ if (write(ifd, (char *)&zeros, todo) != todo) {
+ fprintf(stderr, "%s: Write error on %s: %s\n",
+ params.cmdname, params.imagefile,
+ strerror(errno));
+ exit(EXIT_FAILURE);
+ }
+ pad -= todo;
}
}
--
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[U-Boot] [PATCH v3 05/25] mkimage: Allow the original file size to be recorded
Allow the image handler to store the original input file size so that it
can reference it later.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/imagetool.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 99bbf2f..23c7d30 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -60,6 +60,7 @@ struct image_tool_params {
const char *comment;/* Comment to add to signature node */
int require_keys; /* 1 to mark signing keys as 'required' */
int file_size; /* Total size of output file */
+ int orig_file_size; /* Pad size for file */
};
/*
--
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[U-Boot] [PATCH v3 00/25] dm: Introduce Rockchip RK3288 support
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good set of peripherals. Various full-featured U-Boot ports are available and this is an attempt to bring those features into mainline. With this series the Firefly RK3288 can boot to a prompt from an SD card. Since much of the code is generic, this also supports the Radxa Rock Pro. Since there is no device tree available for that yet, it uses the same config and device tree as the Firefly. This works because not all peripherals are supported, so the differences don't matter. Support for booting from USB OTG is also provided, using the on-chip boot ROM and the rkflashtool utility. This can boot as far as SPL, but there is no support for reading U-Boot proper from USB as yet. This requires implementing a suitable protocol (perhaps DFU or Rockchip's proprietary one) in SPL. Support is also provided for the Haier Chromebook, which is based on the same SoC. In this case it boots from SPI rather than an SD card. The basic approach here is to use driver model for everything, so this series adds several new uclasses. Some of these have been discussed for a while. The list is: - Clocks - setting and getting PLL and peripheral clocks - Pinctrl - adjusting pin multiplexing settings - Reset - reseting the board or SoC - RAM - setting up RAM controllers and detecting the available RAM - MMC - MMC controllers (using the existing block device framework) - LEDs - turning LEDs on and off, with only a GPIO driver so far Trivial support is also added for regmap and syscon controllers, modelled on how the kernel does this. This series avoids hard-coding RK3288-specific code into the build. There is a CONFIG_ROCKCHIP_RK3288 but it only *adds* support for RK3288. In principle another CONFIG could add support for a different Rockchip SoC with only the device tree selecting which one U-Boot works on. Support is provided in mkimage to build these image types: - rkimage - suitable for packaging up SPL to be sent to the boot ROM over USB OTG - rksd- suitable for writing to an SD card Much of the source and ideas for this series came from downstream Rockchip U-Boot trees. SDRAM init came from Coreboot. In most cases it has been pretty heavily cleaned up / rewritten to meet U-Boot style and remove hard-coding of things. Drivers are provided for: - Clocks - Pinctrl - SoC reset - DDR3 SDRAM - I2C - SPI - GPIOs - LEDs using GPIOS - MMC - Firefly main PMIC (ACT8846) and included regulators These are lightly tested and doubtless some problems exist with some, particularly I2C. One problem with device tree is that U-Boot has no way of dropping features it does not need or use. For SPL this problem needs to be solved and this series uses a new 'fdtgrep' tool for this. The 45KB Firefly device tree reduces to a 6KB bytes when unused material is removed. SDRAM timings are also in the device tree. This series includes some changes aimed at reduce code size in SPL, including: - dropping alias sequence support (the aliases node) since many boards just use a single UART in SPL - adding a smaller panic() function that does not support printf()-format strings - removing device unbind code which will never be used in SPL There is a large amount of additional work to bring other Rockchip drivers and features into mainline U-Boot, so this is only a start. Changes in v3: - Update clock rate to always be 24MHz - Add device tree bindings for CRU and DMC - Make use of additional features since version 2 - Update README to mention available drivers - Add various new patches to get RK3288 booting to a prompt Changes in v2: - Tidy up license headers and remove SPL #ifdefs - Tidy up license headers and remove SPL #ifdefs - Drop use of CONFIG_USE_PRIVATE_LIBGCC=y - Tidy up license headers and remove SPL #ifdefs Simon Glass (25): rockchip: Add serial support rockchip: Bring in RK3288 device tree file includes and bindings rockchip: rk3288: dts: Make core devices available early mkimage: Allow padding to any length mkimage: Allow the original file size to be recorded rockchip: Add the rkimage format to mkimage rockchip: Add support for the SD image rockchip: Add support for the SPI image rockchip: gpio: Add rockchip GPIO driver rockchip: Add basic peripheral and clock definitions power: Add support for ACT8846 PMIC power: regulator: Add a driver for ACT8846 regulators rockchip: rk3288: Add clock driver rockchip: rk3288: Add header files for PMU and GRF rockchip: rk3288: Add SoC reset driver rockchip: rk3288: Add a simple syscon driver rockchip: rk3288: Add pinctrl driver rockchip: rk3288: Add SDRAM init rockchip: Add an MMC driver rockchip: Add core SoC start-up code rockchip: Add I2C driver rockchip: Add SPI driver rockchip: Add basic support for firefly-rk3288 rockchip: Add basic support for jerry rockchip: Add a simple README arch/arm/Kconfig | 10 + arch/arm/Mak
[U-Boot] [PATCH v3 26/54] dm: mmc: Add an MMC uclass
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile | 2 ++
drivers/mmc/mmc-uclass.c | 34 ++
drivers/mmc/mmc.c| 2 ++
include/dm/uclass-id.h | 1 +
include/mmc.h| 22 ++
6 files changed, 71 insertions(+)
create mode 100644 drivers/mmc/mmc-uclass.c
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 7ba85a2..3e835f7 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -1,5 +1,15 @@
menu "MMC Host controller Support"
+config DM_MMC
+ bool "Enable MMC controllers using Driver Model"
+ depends on DM
+ help
+ This enables the MultiMediaCard (MMC) uclass which suports MMC and
+ Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
+ and non-removable (e.g. eMMC chip) devices are supported. These
+ appear as block devices in U-Boot and can support filesystems such
+ as EXT4 and FAT.
+
config SH_SDHI
bool "SuperH/Renesas ARM SoCs on-chip SDHI host controller support"
depends on RMOBILE
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index ed73687..2680c63 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -5,6 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
+obj-$(CONFIG_DM_MMC) += mmc-uclass.o
+
obj-$(CONFIG_ARM_PL180_MMCI) += arm_pl180_mmci.o
obj-$(CONFIG_BCM2835_SDHCI) += bcm2835_sdhci.o
obj-$(CONFIG_BFIN_SDH) += bfin_sdh.o
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
new file mode 100644
index 000..777489f
--- /dev/null
+++ b/drivers/mmc/mmc-uclass.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+struct mmc *mmc_get_mmc_dev(struct udevice *dev)
+{
+ struct mmc_uclass_priv *upriv;
+
+ if (!device_active(dev))
+ return NULL;
+ upriv = dev_get_uclass_priv(dev);
+ return upriv->mmc;
+}
+
+U_BOOT_DRIVER(mmc) = {
+ .name = "mmc",
+ .id = UCLASS_MMC,
+};
+
+UCLASS_DRIVER(mmc) = {
+ .id = UCLASS_MMC,
+ .name = "mmc",
+ .flags = DM_UC_FLAG_SEQ_ALIAS,
+ .per_device_auto_alloc_size = sizeof(struct mmc_uclass_priv),
+};
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 79e6fee..4eab274 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -1761,8 +1761,10 @@ int mmc_initialize(bd_t *bis)
INIT_LIST_HEAD (&mmc_devices);
cur_dev_num = 0;
+#ifndef CONFIG_DM_MMC
if (board_mmc_init(bis) < 0)
cpu_mmc_init(bis);
+#endif
#ifndef CONFIG_SPL_BUILD
print_mmc_devices(',');
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index a961648..cba7c0a 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -36,6 +36,7 @@ enum uclass_id {
UCLASS_LED, /* Light-emitting diode (LED) */
UCLASS_LPC, /* x86 'low pin count' interface */
UCLASS_MASS_STORAGE,/* Mass storage device */
+ UCLASS_MMC, /* SD / MMC card or chip */
UCLASS_MOD_EXP, /* RSA Mod Exp device */
UCLASS_PCH, /* x86 platform controller hub */
UCLASS_PCI, /* PCI bus */
diff --git a/include/mmc.h b/include/mmc.h
index dd98b3b..cda9a19 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -266,6 +266,28 @@
#define MMC_NUM_BOOT_PARTITION 2
#define MMC_PART_RPMB 3 /* RPMB partition number */
+/* Driver model support */
+
+/**
+ * struct mmc_uclass_priv - Holds information about a device used by the uclass
+ */
+struct mmc_uclass_priv {
+ struct mmc *mmc;
+};
+
+/**
+ * mmc_get_mmc_dev() - get the MMC struct pointer for a device
+ *
+ * Provided that the device is already probed and ready for use, this value
+ * will be available.
+ *
+ * @dev: Device
+ * @return associated mmc struct pointer if available, else NULL
+ */
+struct mmc *mmc_get_mmc_dev(struct udevice *dev);
+
+/* End of driver model support */
+
struct mmc_cid {
unsigned long psn;
unsigned short oid;
--
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[U-Boot] [PATCH v3 43/54] dm: spi: Make local functions static
Several functions in this file should be marked as static. Update them.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/spi-uclass.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index 737ae64..d666272 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -95,13 +95,13 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return spi_get_ops(bus)->xfer(dev, bitlen, dout, din, flags);
}
-int spi_post_bind(struct udevice *dev)
+static int spi_post_bind(struct udevice *dev)
{
/* Scan the bus for devices */
return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
}
-int spi_child_post_bind(struct udevice *dev)
+static int spi_child_post_bind(struct udevice *dev)
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
@@ -111,7 +111,7 @@ int spi_child_post_bind(struct udevice *dev)
return spi_slave_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
}
-int spi_post_probe(struct udevice *bus)
+static int spi_post_probe(struct udevice *bus)
{
struct dm_spi_bus *spi = dev_get_uclass_priv(bus);
@@ -121,7 +121,7 @@ int spi_post_probe(struct udevice *bus)
return 0;
}
-int spi_child_pre_probe(struct udevice *dev)
+static int spi_child_pre_probe(struct udevice *dev)
{
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
struct spi_slave *slave = dev_get_parentdata(dev);
--
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[U-Boot] [PATCH v3 45/54] Add rivest cipher 4 (rc4) implementation
Add an implementation of RC4. This will be used by Rockchip booting but may
be useful in other situations.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/rc4.h | 21 +
lib/Makefile | 1 +
lib/rc4.c | 49 +
3 files changed, 71 insertions(+)
create mode 100644 include/rc4.h
create mode 100644 lib/rc4.c
diff --git a/include/rc4.h b/include/rc4.h
new file mode 100644
index 000..ea409c2
--- /dev/null
+++ b/include/rc4.h
@@ -0,0 +1,21 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __RC4_H
+#define __RC4_H
+
+/**
+ * rc4_encode() - encode a buf with the RC4 cipher
+ *
+ * @buf: Buffer to encode (it is overwrite in the process
+ * @len: Length of buffer in bytes
+ * @key: 16-byte key to use
+ */
+void rc4_encode(unsigned char *buf, unsigned int len, unsigned char key[16]);
+
+#endif
diff --git a/lib/Makefile b/lib/Makefile
index 1139f9b..fd106b9 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_MD5) += md5.o
obj-y += net_utils.o
obj-$(CONFIG_PHYSMEM) += physmem.o
obj-y += qsort.o
+obj-y += rc4.o
obj-$(CONFIG_SHA1) += sha1.o
obj-$(CONFIG_SUPPORT_EMMC_RPMB) += sha256.o
obj-$(CONFIG_SHA256) += sha256.o
diff --git a/lib/rc4.c b/lib/rc4.c
new file mode 100644
index 000..89d15f3
--- /dev/null
+++ b/lib/rc4.c
@@ -0,0 +1,49 @@
+/*
+ * (C) Copyright 2015 Google, Inc
+ *
+ * (C) Copyright 2008-2014 Rockchip Electronics
+ *
+ * Rivest Cipher 4 (RC4) implementation
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef USE_HOSTCC
+#include
+#endif
+#include
+
+void rc4_encode(unsigned char *buf, unsigned int len, unsigned char key[16])
+{
+ unsigned char s[256], k[256], temp;
+ unsigned short i, j, t;
+ int ptr;
+
+ j = 0;
+ for (i = 0; i < 256; i++) {
+ s[i] = (unsigned char)i;
+ j &= 0x0f;
+ k[i] = key[j];
+ j++;
+ }
+
+ j = 0;
+ for (i = 0; i < 256; i++) {
+ j = (j + s[i] + k[i]) % 256;
+ temp = s[i];
+ s[i] = s[j];
+ s[j] = temp;
+ }
+
+ i = 0;
+ j = 0;
+ for (ptr = 0; ptr < len; ptr++) {
+ i = (i + 1) % 256;
+ j = (j + s[i]) % 256;
+ temp = s[i];
+ s[i] = s[j];
+ s[j] = temp;
+ t = (s[i] + (s[j] % 256)) % 256;
+ buf[ptr] = buf[ptr] ^ s[t];
+ }
+}
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 23/54] dm: Add support for LEDs
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
doc/device-tree-bindings/leds/common.txt | 23 ++
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/led/Kconfig | 17 +++
drivers/led/Makefile | 8 +
drivers/led/led-uclass.c | 48 ++
include/dm/uclass-id.h | 1 +
include/led.h| 51
scripts/Makefile.spl | 1 +
9 files changed, 152 insertions(+)
create mode 100644 doc/device-tree-bindings/leds/common.txt
create mode 100644 drivers/led/Kconfig
create mode 100644 drivers/led/Makefile
create mode 100644 drivers/led/led-uclass.c
create mode 100644 include/led.h
diff --git a/doc/device-tree-bindings/leds/common.txt
b/doc/device-tree-bindings/leds/common.txt
new file mode 100644
index 000..2d88816
--- /dev/null
+++ b/doc/device-tree-bindings/leds/common.txt
@@ -0,0 +1,23 @@
+Common leds properties.
+
+Optional properties for child nodes:
+- label : The label for this LED. If omitted, the label is
+ taken from the node name (excluding the unit address).
+
+- linux,default-trigger : This parameter, if present, is a
+string defining the trigger assigned to the LED. Current triggers are:
+ "backlight" - LED will act as a back-light, controlled by the framebuffer
+ system
+ "default-on" - LED will turn on (but for leds-gpio see "default-state"
+ property in Documentation/devicetree/bindings/gpio/led.txt)
+ "heartbeat" - LED "double" flashes at a load average based rate
+ "ide-disk" - LED indicates disk activity
+ "timer" - LED flashes at a fixed, configurable rate
+
+Examples:
+
+system-status {
+ label = "Status";
+ linux,default-trigger = "heartbeat";
+ ...
+};
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 1f40887..ee942e2 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -20,6 +20,8 @@ source "drivers/net/Kconfig"
source "drivers/input/Kconfig"
+source "drivers/led/Kconfig"
+
source "drivers/serial/Kconfig"
source "drivers/tpm/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 405b64b..c090aba 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_CPU) += cpu/
obj-y += crypto/
obj-$(CONFIG_FPGA) += fpga/
obj-y += hwmon/
+obj-$(CONFIG_LED) += led/
obj-y += misc/
obj-y += pcmcia/
obj-y += dfu/
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
new file mode 100644
index 000..e4d9a84
--- /dev/null
+++ b/drivers/led/Kconfig
@@ -0,0 +1,17 @@
+config LED
+ bool "Enable LED support"
+ depends on DM
+ help
+ Many boards have LEDs which can be used to signal status or alerts.
+ U-Boot provides a uclass API to implement this feature. LED drivers
+ can provide access to board-specific LEDs. Use of the device tree
+ for configuration is encouraged.
+
+config SPL_LED_SUPPORT
+ bool "Enable LED support in SPL"
+ depends on LED
+ help
+ The LED subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use LEDs in SPL,
+ enable this option. You will need to enable device tree in SPL
+ for this to work.
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
new file mode 100644
index 000..b39b205
--- /dev/null
+++ b/drivers/led/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2015 Google, Inc
+# Written by Simon Glass
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_LED) += led-uclass.o
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
new file mode 100644
index 000..a80ae93
--- /dev/null
+++ b/drivers/led/led-uclass.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+int led_get_by_label(const char *label, struct udevice **devp)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ ret = uclass_get(UCLASS_LED, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(dev, uc) {
+ struct led_uclass_plat *uc_plat = dev_get_uclass_platdata(dev);
+
+ if (!strcmp(label, uc_plat->label))
+ return uclass_get_device_tail(dev, 0, devp);
+ }
+
+ return -ENOENT;
+}
+
+int led_set_on(struct udevice *dev, int on)
+{
+ struct led_ops *ops = led_get_ops(dev);
+
+ if (!ops->set_on)
+ return -ENOSYS;
+
+ re
[U-Boot] [PATCH v3 24/54] dm: led: Add a driver for GPIO-controlled LEDs
Add a simple driver which allows use of LEDs attached to GPIOs. The linux
device tree binding is used.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
doc/device-tree-bindings/leds/leds-gpio.txt | 52 ++
drivers/led/Kconfig | 9 +++
drivers/led/Makefile| 1 +
drivers/led/led_gpio.c | 101
4 files changed, 163 insertions(+)
create mode 100644 doc/device-tree-bindings/leds/leds-gpio.txt
create mode 100644 drivers/led/led_gpio.c
diff --git a/doc/device-tree-bindings/leds/leds-gpio.txt
b/doc/device-tree-bindings/leds/leds-gpio.txt
new file mode 100644
index 000..df1b308
--- /dev/null
+++ b/doc/device-tree-bindings/leds/leds-gpio.txt
@@ -0,0 +1,52 @@
+LEDs connected to GPIO lines
+
+Required properties:
+- compatible : should be "gpio-leds".
+
+Each LED is represented as a sub-node of the gpio-leds device. Each
+node's name represents the name of the corresponding LED.
+
+LED sub-node properties:
+- gpios : Should specify the LED's GPIO, see "gpios property" in
+ Documentation/devicetree/bindings/gpio/gpio.txt. Active low LEDs should be
+ indicated using flags in the GPIO specifier.
+- label : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- linux,default-trigger : (optional)
+ see Documentation/devicetree/bindings/leds/common.txt
+- default-state: (optional) The initial state of the LED. Valid
+ values are "on", "off", and "keep". If the LED is already on or off
+ and the default-state property is set the to same value, then no
+ glitch should be produced where the LED momentarily turns off (or
+ on). The "keep" setting will keep the LED at whatever its current
+ state is, without producing a glitch. The default is off if this
+ property is not present.
+
+Examples:
+
+leds {
+ compatible = "gpio-leds";
+ hdd {
+ label = "IDE Activity";
+ gpios = <&mcu_pio 0 1>; /* Active low */
+ linux,default-trigger = "ide-disk";
+ };
+
+ fault {
+ gpios = <&mcu_pio 1 0>;
+ /* Keep LED on if BIOS detected hardware fault */
+ default-state = "keep";
+ };
+};
+
+run-control {
+ compatible = "gpio-leds";
+ red {
+ gpios = <&mpc8572 6 0>;
+ default-state = "off";
+ };
+ green {
+ gpios = <&mpc8572 7 0>;
+ default-state = "on";
+ };
+};
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index e4d9a84..de5feea 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -15,3 +15,12 @@ config SPL_LED_SUPPORT
If this is acceptable and you have a need to use LEDs in SPL,
enable this option. You will need to enable device tree in SPL
for this to work.
+
+config LED_GPIO
+ bool "LED support for GPIO-connected LEDs"
+ depends on LED && DM_GPIO
+ help
+ Enable support for LEDs which are connected to GPIO lines. These
+ GPIOs may be on the SoC or some other device which provides GPIOs.
+ The GPIO driver must used driver model. LEDs are configured using
+ the device tree.
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index b39b205..990129e 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -6,3 +6,4 @@
#
obj-$(CONFIG_LED) += led-uclass.o
+obj-$(CONFIG_LED_GPIO) += led_gpio.o
diff --git a/drivers/led/led_gpio.c b/drivers/led/led_gpio.c
new file mode 100644
index 000..a4cd618
--- /dev/null
+++ b/drivers/led/led_gpio.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct led_gpio_priv {
+ struct gpio_desc gpio;
+};
+
+static int gpio_led_set_on(struct udevice *dev, int on)
+{
+ struct led_gpio_priv *priv = dev_get_priv(dev);
+
+ if (!dm_gpio_is_valid(&priv->gpio))
+ return -EREMOTEIO;
+
+ return dm_gpio_set_value(&priv->gpio, on);
+}
+
+static int led_gpio_probe(struct udevice *dev)
+{
+ struct led_uclass_plat *uc_plat = dev_get_uclass_platdata(dev);
+ struct led_gpio_priv *priv = dev_get_priv(dev);
+
+ /* Ignore the top-level LED node */
+ if (!uc_plat->label)
+ return 0;
+ return gpio_request_by_name(dev, "gpios", 0, &priv->gpio, GPIOD_IS_OUT);
+}
+
+static int led_gpio_remove(struct udevice *dev)
+{
+ struct led_gpio_priv *priv = dev_get_priv(dev);
+
+ if (dm_gpio_is_valid(&priv->gpio))
+ dm_gpio_free(dev, &priv->gpio);
+
+ return 0;
+}
+
+static int led_gpio_bind(struct udevice *parent)
+{
+ const void *blob = gd->fdt_blob;
+ struct udevice *dev;
+ int node;
+ int ret;
+
+ for (node = fdt_first_subnode(blob, par
[U-Boot] [PATCH v3 17/54] dm: gpio: Allow GPIO uclass to be used in SPL
Now that we support driver model in SPL, allow GPIO drivers to be used there also. Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: None drivers/gpio/Makefile | 4 1 file changed, 4 deletions(-) diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 5864850..67c6374 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -6,13 +6,9 @@ # ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_DM_GPIO) += gpio-uclass.o obj-$(CONFIG_AXP_GPIO) += axp_gpio.o endif -/* TODO(s...@chromium.org): Only tegra supports driver model in SPL */ -ifdef CONFIG_TEGRA_GPIO obj-$(CONFIG_DM_GPIO) += gpio-uclass.o -endif obj-$(CONFIG_AT91_GPIO)+= at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o -- 2.4.3.573.g4eafbef ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 35/54] dm: power: Add regulator flags to centralise auto-set logic
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 12
include/power/regulator.h | 8
2 files changed, 20 insertions(+)
diff --git a/drivers/power/regulator/regulator-uclass.c
b/drivers/power/regulator/regulator-uclass.c
index 31ffd44..0f1ca77 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -319,6 +319,18 @@ static int regulator_pre_probe(struct udevice *dev)
uc_pdata->boot_on = fdtdec_get_bool(gd->fdt_blob, offset,
"regulator-boot-on");
+ /* Those values are optional (-ENODATA if unset) */
+ if ((uc_pdata->min_uV != -ENODATA) &&
+ (uc_pdata->max_uV != -ENODATA) &&
+ (uc_pdata->min_uV == uc_pdata->max_uV))
+ uc_pdata->flags |= REGULATOR_FLAG_AUTOSET_UV;
+
+ /* Those values are optional (-ENODATA if unset) */
+ if ((uc_pdata->min_uA != -ENODATA) &&
+ (uc_pdata->max_uA != -ENODATA) &&
+ (uc_pdata->min_uA == uc_pdata->max_uA))
+ uc_pdata->flags |= REGULATOR_FLAG_AUTOSET_UA;
+
return 0;
}
diff --git a/include/power/regulator.h b/include/power/regulator.h
index 03a2cef..79ce0a4 100644
--- a/include/power/regulator.h
+++ b/include/power/regulator.h
@@ -128,6 +128,11 @@ struct dm_regulator_mode {
const char *name;
};
+enum regulator_flag {
+ REGULATOR_FLAG_AUTOSET_UV = 1 << 0,
+ REGULATOR_FLAG_AUTOSET_UA = 1 << 1,
+};
+
/**
* struct dm_regulator_uclass_platdata - pointed by dev->uclass_platdata, and
* allocated on each regulator bind. This structure holds an information
@@ -143,6 +148,8 @@ struct dm_regulator_mode {
* @max_uA*- maximum amperage (micro Amps)
* @always_on* - bool type, true or false
* @boot_on* - bool type, true or false
+ * TODO(s...@chromium.org): Consider putting the above two into @flags
+ * @flags: - flags value (see REGULATOR_FLAG_...)
* @name** - fdt regulator name - should be taken from the device tree
*
* Note:
@@ -162,6 +169,7 @@ struct dm_regulator_uclass_platdata {
bool always_on;
bool boot_on;
const char *name;
+ int flags;
};
/* Regulator device operations */
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 32/54] mmc: Calculate dwmmc FIFO threshold size if not provided
We can calculate this. Add code to do this if it is not provided.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index a034c3f..cce2a5d 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -355,9 +355,15 @@ static int dwmci_init(struct mmc *mmc)
dwmci_writel(host, DWMCI_IDINTEN, 0);
dwmci_writel(host, DWMCI_BMOD, 1);
- if (host->fifoth_val) {
- dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
+ if (!host->fifoth_val) {
+ uint32_t fifo_size;
+
+ fifo_size = dwmci_readl(host, DWMCI_FIFOTH);
+ fifo_size = ((fifo_size & RX_WMARK_MASK) >> RX_WMARK_SHIFT) + 1;
+ host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_size / 2 - 1) |
+ TX_WMARK(fifo_size / 2);
}
+ dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
dwmci_writel(host, DWMCI_CLKENA, 0);
dwmci_writel(host, DWMCI_CLKSRC, 0);
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 53/54] dm: Add a clock uclass
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and Exynos. This is useful but it would be better to have a
common API that can be understood and used throughout U-Boot.
Add a simple clock API as a starting point. It supports querying and setting
the rate of a clock. Each clock is a device. To reduce memory and processing
overhead the concept of peripheral clocks is provided. These do not need to
be explicit devices - it is possible to write a driver that can adjust the
I2C clock (for example) without an explicit I2C clock device. This can
dramatically reduce the number of devices (and associated overhead) in a
complex SoC.
Clocks are referenced by a number, and it is expected that SoCs will define
that numbering themselves via an enum.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/Kconfig | 2 ++
drivers/Makefile | 1 +
drivers/clk/Kconfig | 19
drivers/clk/Makefile | 8 +
drivers/clk/clk-uclass.c | 58 +++
include/clk.h| 80
include/dm/uclass-id.h | 1 +
scripts/Makefile.spl | 1 +
8 files changed, 170 insertions(+)
create mode 100644 drivers/clk/Kconfig
create mode 100644 drivers/clk/Makefile
create mode 100644 drivers/clk/clk-uclass.c
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 7c9eefc..619d93a 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -1,5 +1,7 @@
menu "Device Drivers"
+source "drivers/clk/Kconfig"
+
source "drivers/core/Kconfig"
source "drivers/cpu/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 39b7919..9f5cec7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -1,3 +1,4 @@
+obj-$(CONFIG_CLK) += clk/
obj-$(CONFIG_DM) += core/
obj-$(CONFIG_DM_DEMO) += demo/
obj-$(CONFIG_BIOSEMU) += bios_emulator/
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
new file mode 100644
index 000..07eb54c
--- /dev/null
+++ b/drivers/clk/Kconfig
@@ -0,0 +1,19 @@
+config CLK
+ bool "Enable clock driver support"
+ depends on DM
+ help
+ This allows drivers to be provided for clock generators, including
+ oscillators and PLLs. Devices can use a common clock API to request
+ a particular clock rate and check on available clocks. Clocks can
+ feed into other clocks in a tree structure, with multiplexers to
+ choose the source for each clock.
+
+config SPL_CLK_SUPPORT
+ bool "Enable clock support in SPL"
+ depends on CLK
+ help
+ The clock subsystem adds a small amount of overhead to the image.
+ If this is acceptable and you have a need to use clock drivers in
+ SPL, enable this option. It might provide a cleaner interface to
+ setting up clocks within SPL, and allows the same drivers to be
+ used as U-Boot proper.
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
new file mode 100644
index 000..b51cf23
--- /dev/null
+++ b/drivers/clk/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2015 Google, Inc
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CLK) += clk-uclass.o
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
new file mode 100644
index 000..73dfd7d
--- /dev/null
+++ b/drivers/clk/clk-uclass.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+ulong clk_get_rate(struct udevice *dev)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->get_rate)
+ return -ENOSYS;
+
+ return ops->get_rate(dev);
+}
+
+ulong clk_set_rate(struct udevice *dev, ulong rate)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->set_rate)
+ return -ENOSYS;
+
+ return ops->set_rate(dev, rate);
+}
+
+ulong clk_get_periph_rate(struct udevice *dev, int periph)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->get_periph_rate)
+ return -ENOSYS;
+
+ return ops->get_periph_rate(dev, periph);
+}
+
+ulong clk_set_periph_rate(struct udevice *dev, int periph, ulong rate)
+{
+ struct clk_ops *ops = clk_get_ops(dev);
+
+ if (!ops->set_periph_rate)
+ return -ENOSYS;
+
+ return ops->set_periph_rate(dev, periph, rate);
+}
+
+UCLASS_DRIVER(clk) = {
+ .id = UCLASS_CLK,
+ .name = "clk",
+};
diff --git a/include/clk.h b/include/clk.h
index df4570c..254ad2b 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -1,6 +1,86 @@
+/*
+ * Copyrigh
[U-Boot] [PATCH v3 31/54] mmc: Support bypass mode with the get_mmc_clk() method
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c| 2 +-
drivers/mmc/exynos_dw_mmc.c | 2 +-
include/dwmmc.h | 16 +++-
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index 8f28d7e..a034c3f 100644
--- a/drivers/mmc/dw_mmc.c
+++ b/drivers/mmc/dw_mmc.c
@@ -248,7 +248,7 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32
freq)
* host->bus_hz should be set by user.
*/
if (host->get_mmc_clk)
- sclk = host->get_mmc_clk(host);
+ sclk = host->get_mmc_clk(host, freq);
else if (host->bus_hz)
sclk = host->bus_hz;
else {
diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c
index e083745..3f702ba 100644
--- a/drivers/mmc/exynos_dw_mmc.c
+++ b/drivers/mmc/exynos_dw_mmc.c
@@ -39,7 +39,7 @@ static void exynos_dwmci_clksel(struct dwmci_host *host)
dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
}
-unsigned int exynos_dwmci_get_clk(struct dwmci_host *host)
+unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
{
unsigned long sclk;
int8_t clk_div;
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 7a7555a..25cf42c 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -163,7 +163,21 @@ struct dwmci_host {
void (*clksel)(struct dwmci_host *host);
void (*board_init)(struct dwmci_host *host);
- unsigned int (*get_mmc_clk)(struct dwmci_host *host);
+
+ /**
+* Get / set a particular MMC clock frequency
+*
+* This is used to request the current clock frequency of the clock
+* that drives the DWMMC peripheral. The caller will then use this
+* information to work out the divider it needs to achieve the
+* required MMC bus clock frequency. If you want to handle the
+* clock external to DWMMC, use @freq to select the frequency and
+* return that value too. Then DWMMC will put itself in bypass mode.
+*
+* @host: DWMMC host
+* @freq: Frequency the host is trying to achieve
+*/
+ unsigned int (*get_mmc_clk)(struct dwmci_host *host, uint freq);
struct mmc_config cfg;
};
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 51/54] dm: Add a system reset uclass
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
SoC or board. Also there is a distinction sometimes between resetting just
the CPU (leaving GPIO state alone) and resetting all the PMICs, just cutting
power.
To achieve this, add a simple system reset uclass. It allows multiple devices
to provide reset functionality and provides a way to walk through them,
requesting a particular reset type until is it provided.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/misc/Kconfig| 9 +++
drivers/misc/Makefile | 1 +
drivers/misc/reset-uclass.c | 62 +
include/dm/uclass-id.h | 1 +
include/reset.h | 62 +
5 files changed, 135 insertions(+)
create mode 100644 drivers/misc/reset-uclass.c
create mode 100644 include/reset.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 64b07a3..3b7f76a 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -73,3 +73,12 @@ config PCA9551_I2C_ADDR
default 0x60
help
The I2C address of the PCA9551 LED controller.
+
+config RESET
+ bool "Enable support for reset drivers"
+ depends on DM
+ help
+ Enable reset drivers which can be used to reset the CPU or board.
+ Each driver can provide a reset method which will be called to
+ effect a reset. The uclass will try all available drivers when
+ reset_walk() is called.
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 120babc..5da5178 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -32,3 +32,4 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
+obj-$(CONFIG_RESET) += reset-uclass.o
diff --git a/drivers/misc/reset-uclass.c b/drivers/misc/reset-uclass.c
new file mode 100644
index 000..ba27757
--- /dev/null
+++ b/drivers/misc/reset-uclass.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+int reset_request(struct udevice *dev, enum reset_t type)
+{
+ struct reset_ops *ops = reset_get_ops(dev);
+
+ if (!ops->request)
+ return -ENOSYS;
+
+ return ops->request(dev, type);
+}
+
+void reset_walk(enum reset_t type)
+{
+ struct udevice *dev;
+ int ret = 0;
+
+ while (ret != -EINPROGRESS && type < RESET_COUNT) {
+ for (uclass_first_device(UCLASS_RESET, &dev);
+ dev;
+ uclass_next_device(&dev)) {
+ ret = reset_request(dev, type);
+ if (ret == -EINPROGRESS)
+ break;
+ }
+ }
+
+ /* Wait for the reset to take effect */
+ mdelay(100);
+
+ /* Still no reset? Give up */
+ printf("Reset not supported on this platform\n");
+ hang();
+}
+
+/**
+ * reset_cpu() - calls reset_walk(RESET_WARM)
+ */
+void reset_cpu(ulong addr)
+{
+ reset_walk(RESET_WARM);
+}
+
+UCLASS_DRIVER(reset) = {
+ .id = UCLASS_RESET,
+ .name = "reset",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 5bb602f..fc486f2 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -45,6 +45,7 @@ enum uclass_id {
UCLASS_PINCTRL, /* Pin multiplexing control */
UCLASS_PMIC,/* PMIC I/O device */
UCLASS_REGULATOR, /* Regulator device */
+ UCLASS_RESET, /* Reset device */
UCLASS_RTC, /* Real time clock device */
UCLASS_SERIAL, /* Serial UART */
UCLASS_SPI, /* SPI bus */
diff --git a/include/reset.h b/include/reset.h
new file mode 100644
index 000..d29e108
--- /dev/null
+++ b/include/reset.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __RESET_H
+#define __RESET_H
+
+enum reset_t {
+ RESET_WARM, /* Reset CPU, keep GPIOs active */
+ RESET_COLD, /* Reset CPU and GPIOs */
+ RESET_POWER,/* Reset PMIC (remove and restore power) */
+
+ RESET_COUNT,
+};
+
+struct reset_ops {
+ /**
+* request() - request a reset of the given type
+*
+* Note that this function may return before the reset takes effect.
+*
+* @type: Reset type to request
+* @return -EINPROGRESS if the reset has
[U-Boot] [PATCH v3 48/54] dm: spl: Allow device tree/driver model in board_init_f()
Add an spl_init() function that does basic init such that board_init_f() can
use simple malloc(), device tree and driver model. Each one is set up only
if enabled for SPL.
Note: We really should refactor SPL such that there is a single
board_init_f() and rename the existing weak board_init_f() functions
provided by boards, calling them from the single board_init_f().
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 35 ---
include/asm-generic/global_data.h | 1 +
include/spl.h | 12
3 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index aeb0645..074c41d 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -148,18 +148,12 @@ static void spl_ram_load_image(void)
}
#endif
-void board_init_r(gd_t *dummy1, ulong dummy2)
+int spl_init(void)
{
- u32 boot_device;
int ret;
- debug(">>spl:board_init_r()\n");
-
-#if defined(CONFIG_SYS_SPL_MALLOC_START)
- mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
- CONFIG_SYS_SPL_MALLOC_SIZE);
- gd->flags |= GD_FLG_FULL_MALLOC_INIT;
-#elif defined(CONFIG_SYS_MALLOC_F_LEN)
+ debug("spl_init()\n");
+#if defined(CONFIG_SYS_MALLOC_F_LEN)
gd->malloc_limit = CONFIG_SYS_MALLOC_F_LEN;
gd->malloc_ptr = 0;
#endif
@@ -168,17 +162,36 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
ret = fdtdec_setup();
if (ret) {
debug("fdtdec_setup() returned error %d\n", ret);
- hang();
+ return ret;
}
}
if (IS_ENABLED(CONFIG_SPL_DM)) {
ret = dm_init_and_scan(true);
if (ret) {
debug("dm_init_and_scan() returned error %d\n", ret);
- hang();
+ return ret;
}
}
+ gd->flags |= GD_FLG_SPL_INIT;
+
+ return 0;
+}
+void board_init_r(gd_t *dummy1, ulong dummy2)
+{
+ u32 boot_device;
+
+ debug(">>spl:board_init_r()\n");
+
+#if defined(CONFIG_SYS_SPL_MALLOC_START)
+ mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
+ CONFIG_SYS_SPL_MALLOC_SIZE);
+ gd->flags |= GD_FLG_FULL_MALLOC_INIT;
+#endif
+ if (!(gd->flags & GD_FLG_SPL_INIT)) {
+ if (spl_init())
+ hang();
+ }
#ifndef CONFIG_PPC
/*
* timer_init() does not exist on PPC systems. The timer is initialized
diff --git a/include/asm-generic/global_data.h
b/include/asm-generic/global_data.h
index 6747619..73c61e6 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -115,5 +115,6 @@ typedef struct global_data {
#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */
#define GD_FLG_SERIAL_READY0x00100 /* Pre-reloc serial console ready */
#define GD_FLG_FULL_MALLOC_INIT0x00200 /* Full malloc() is ready
*/
+#define GD_FLG_SPL_INIT0x00400 /* spl_init() has been called
*/
#endif /* __ASM_GENERIC_GBL_DATA_H */
diff --git a/include/spl.h b/include/spl.h
index d19940f..8e53426 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -81,6 +81,18 @@ void __noreturn jump_to_image_no_args(struct spl_image_info
*spl_image);
int spl_load_image_ext(block_dev_desc_t *block_dev, int partition, const char
*filename);
int spl_load_image_ext_os(block_dev_desc_t *block_dev, int partition);
+/**
+ * spl_init() - Set up device tree and driver model in SPL if enabled
+ *
+ * Call this function in board_init_f() if you want to use device tree and
+ * driver model early, before board_init_r() is called. This function will
+ * be called from board_init_r() if not called earlier.
+ *
+ * If this is not called, then driver model will be inactive in SPL's
+ * board_init_f(), and no device tree will be available.
+ */
+int spl_init(void);
+
#ifdef CONFIG_SPL_BOARD_INIT
void spl_board_init(void);
#endif
--
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[U-Boot] [PATCH v3 38/54] dm: power: Use debug() for errors in regulator uclass
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/regulator/regulator-uclass.c
b/drivers/power/regulator/regulator-uclass.c
index a2d0b9f..12e141b 100644
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -262,7 +262,7 @@ static int regulator_post_bind(struct udevice *dev)
if (regulator_name_is_unique(dev, uc_pdata->name))
return 0;
- error("\"%s\" of dev: \"%s\", has nonunique value: \"%s\"",
+ debug("\"%s\" of dev: \"%s\", has nonunique value: \"%s\"",
property, dev->name, uc_pdata->name);
return -EINVAL;
--
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[U-Boot] [PATCH v3 28/54] mmc: Add debug() output on read errors
Allow read errors to be diagnosed more easily.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/mmc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4eab274..da47037 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -250,14 +250,18 @@ static ulong mmc_bread(int dev_num, lbaint_t start,
lbaint_t blkcnt, void *dst)
return 0;
}
- if (mmc_set_blocklen(mmc, mmc->read_bl_len))
+ if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
+ debug("%s: Failed to set blocklen\n", __func__);
return 0;
+ }
do {
cur = (blocks_todo > mmc->cfg->b_max) ?
mmc->cfg->b_max : blocks_todo;
- if(mmc_read_blocks(mmc, dst, start, cur) != cur)
+ if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
+ debug("%s: Failed to read blocks\n", __func__);
return 0;
+ }
blocks_todo -= cur;
start += cur;
dst += cur * mmc->read_bl_len;
--
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[U-Boot] [PATCH v3 39/54] dm: pmic: Add functions to adjust PMIC registers
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/pmic-uclass.c | 32
include/power/pmic.h | 34 ++
2 files changed, 66 insertions(+)
diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
index 40b5135..dbab3e3 100644
--- a/drivers/power/pmic/pmic-uclass.c
+++ b/drivers/power/pmic/pmic-uclass.c
@@ -139,6 +139,38 @@ int pmic_write(struct udevice *dev, uint reg, const
uint8_t *buffer, int len)
return ops->write(dev, reg, buffer, len);
}
+int pmic_reg_read(struct udevice *dev, uint reg)
+{
+ u8 byte;
+ int ret;
+
+ ret = pmic_read(dev, reg, &byte, 1);
+ debug("%s: reg=%x, value=%x\n", __func__, reg, byte);
+
+ return ret ? ret : byte;
+}
+
+int pmic_reg_write(struct udevice *dev, uint reg, uint value)
+{
+ u8 byte = value;
+
+ debug("%s: reg=%x, value=%x\n", __func__, reg, value);
+ return pmic_read(dev, reg, &byte, 1);
+}
+
+int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set)
+{
+ u8 byte;
+ int ret;
+
+ ret = pmic_reg_read(dev, reg);
+ if (ret < 0)
+ return ret;
+ byte = (ret & ~clr) | set;
+
+ return pmic_reg_write(dev, reg, byte);
+}
+
UCLASS_DRIVER(pmic) = {
.id = UCLASS_PMIC,
.name = "pmic",
diff --git a/include/power/pmic.h b/include/power/pmic.h
index eb152ef..6ba4b6e 100644
--- a/include/power/pmic.h
+++ b/include/power/pmic.h
@@ -264,6 +264,40 @@ int pmic_reg_count(struct udevice *dev);
*/
int pmic_read(struct udevice *dev, uint reg, uint8_t *buffer, int len);
int pmic_write(struct udevice *dev, uint reg, const uint8_t *buffer, int len);
+
+/**
+ * pmic_reg_read() - read a PMIC register value
+ *
+ * @dev: PMIC device to read
+ * @reg: Register to read
+ * @return value read on success or negative value of errno.
+ */
+int pmic_reg_read(struct udevice *dev, uint reg);
+
+/**
+ * pmic_reg_write() - write a PMIC register value
+ *
+ * @dev: PMIC device to write
+ * @reg: Register to write
+ * @value: Value to write
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_reg_write(struct udevice *dev, uint reg, uint value);
+
+/**
+ * pmic_clrsetbits() - clear and set bits in a PMIC register
+ *
+ * This reads a register, optionally clears some bits, optionally sets some
+ * bits, then writes the register.
+ *
+ * @dev: PMIC device to update
+ * @reg: Register to update
+ * @clr: Bit mask to clear (set those bits that you want cleared)
+ * @set: Bit mask to set (set those bits that you want set)
+ * @return 0 on success or negative value of errno.
+ */
+int pmic_clrsetbits(struct udevice *dev, uint reg, uint clr, uint set);
+
#endif /* CONFIG_DM_PMIC */
#ifdef CONFIG_POWER
--
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[U-Boot] [PATCH v3 20/54] dm: Add support for register maps (regmap)
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that bus.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/core/Makefile | 1 +
drivers/core/regmap.c | 86 +++
include/regmap.h | 72 ++
3 files changed, 159 insertions(+)
create mode 100644 drivers/core/regmap.c
create mode 100644 include/regmap.h
diff --git a/drivers/core/Makefile b/drivers/core/Makefile
index ed21fed..7851824 100644
--- a/drivers/core/Makefile
+++ b/drivers/core/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_OF_CONTROL) += simple-bus.o
endif
obj-$(CONFIG_DM_DEVICE_REMOVE) += device-remove.o
obj-$(CONFIG_DM) += dump.o
+obj-$(CONFIG_OF_CONTROL) += regmap.o
diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c
new file mode 100644
index 000..519832f
--- /dev/null
+++ b/drivers/core/regmap.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int regmap_init_mem(struct udevice *dev, struct regmap **mapp)
+{
+ const void *blob = gd->fdt_blob;
+ struct regmap_range *range;
+ const fdt32_t *cell;
+ struct regmap *map;
+ int count;
+ int addr_len, size_len, both_len;
+ int parent;
+ int len;
+
+ parent = dev->parent->of_offset;
+ addr_len = fdt_address_cells(blob, parent);
+ size_len = fdt_size_cells(blob, parent);
+ both_len = addr_len + size_len;
+
+ cell = fdt_getprop(blob, dev->of_offset, "reg", &len);
+ len /= sizeof(*cell);
+ count = len / both_len;
+ if (!cell || !count)
+ return -EINVAL;
+
+ map = malloc(sizeof(struct regmap));
+ if (!map)
+ return -ENOMEM;
+
+ if (count <= 1) {
+ map->range = &map->base_range;
+ } else {
+ map->range = malloc(count * sizeof(struct regmap_range));
+ if (!map->range) {
+ free(map);
+ return -ENOMEM;
+ }
+ }
+
+ map->base = fdtdec_get_number(cell, addr_len);
+ map->range_count = count;
+
+ for (range = map->range; count > 0;
+count--, cell += both_len, range++) {
+ range->start = fdtdec_get_number(cell, addr_len);
+ range->size = fdtdec_get_number(cell + addr_len, size_len);
+ }
+
+ *mapp = map;
+
+ return 0;
+}
+
+void *regmap_get_range(struct regmap *map, unsigned int range_num)
+{
+ struct regmap_range *range;
+
+ if (range_num >= map->range_count)
+ return NULL;
+ range = &map->range[range_num];
+
+ return map_sysmem(range->start, range->size);
+}
+
+int regmap_uninit(struct regmap *map)
+{
+ if (map->range_count > 1)
+ free(map->range);
+ free(map);
+
+ return 0;
+}
diff --git a/include/regmap.h b/include/regmap.h
new file mode 100644
index 000..eccf770
--- /dev/null
+++ b/include/regmap.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2015 Google, Inc
+ * Written by Simon Glass
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __REGMAP_H
+#define __REGMAP_H
+
+/**
+ * struct regmap_range - a register map range
+ *
+ * @start: Start address
+ * @size: Size in bytes
+ */
+struct regmap_range {
+ ulong start;
+ ulong size;
+};
+
+/**
+ * struct regmap - a way of accessing hardware/bus registers
+ *
+ * @base: Base address of register map
+ * @range_count: Number of ranges available within the map
+ * @range: Pointer to the list of ranges, allocated if @range_count > 1
+ * @base_range:If @range_count is <= 1, @range points here
+ */
+struct regmap {
+ phys_addr_t base;
+ int range_count;
+ struct regmap_range *range, base_range;
+};
+
+/*
+ * Interface to provide access to registers either through a direct memory
+ * bus or through a peripheral bus like I2C, SPI.
+ */
+int regmap_write(struct regmap *map, uint offset, uint val);
+int regmap_read(struct regmap *map, uint offset, uint *valp);
+
+#define regmap_write32(map, ptr, member, val) \
+ regmap_write(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), val)
+
+#define regmap_read32(map, ptr, member, valp) \
+ regmap_read(map, (uint32_t *)(ptr)->member - (uint32_t *)(ptr), valp)
+
+/**
+ * regmap_init_mem() - Set up a new register map that uses memory access
+ *
+ * Use regmap_uninit() to free it.
+ *
+ * @dev: Device that uses this map
+ * @mapp: Returns allocated map
+ */
+int regmap_init_mem(struct u
[U-Boot] [PATCH v3 30/54] mmc: Add structure comments for dwmmc
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/dwmmc.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dwmmc.h b/include/dwmmc.h
index 86a5491..7a7555a 100644
--- a/include/dwmmc.h
+++ b/include/dwmmc.h
@@ -129,8 +129,24 @@
/* quirks */
#define DWMCI_QUIRK_DISABLE_SMU(1 << 0)
+/**
+ * struct dwmci_host - Information about a designware MMC host
+ *
+ * @name: Device name
+ * @ioaddr:Base I/O address of controller
+ * @quirks:Quick flags - see DWMCI_QUIRK_...
+ * @caps: Capabilities - see MMC_MODE_...
+ * @bus_hz:Bus speed in Hz, if @get_mmc_clk() is NULL
+ * @div: Arbitrary clock divider value for use by controller
+ * @dev_index: Arbitrary device index for use by controller
+ * @dev_id:Arbitrary device ID for use by controller
+ * @buswidth: Bus width in bits (8 or 4)
+ * @fifoth_val:Value for FIFOTH register (or 0 to leave unset)
+ * @mmc: Pointer to generic MMC structure for this device
+ * @priv: Private pointer for use by controller
+ */
struct dwmci_host {
- char *name;
+ const char *name;
void *ioaddr;
unsigned int quirks;
unsigned int caps;
--
2.4.3.573.g4eafbef
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[U-Boot] [PATCH v3 40/54] dm: power: Allow use of regulators in SPL
This functionality may be useful for setting up regulators early during boot. Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: None scripts/Makefile.spl | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 24ca58b..1e58be9 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -67,6 +67,7 @@ libs-y += fs/ libs-$(CONFIG_SPL_LED_SUPPORT) += drivers/led/ libs-$(CONFIG_SPL_LIBGENERIC_SUPPORT) += lib/ libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/ drivers/power/pmic/ +libs-$(CONFIG_SPL_POWER_SUPPORT) += drivers/power/regulator/ libs-$(CONFIG_SPL_MTD_SUPPORT) += drivers/mtd/ libs-$(CONFIG_SPL_NAND_SUPPORT) += drivers/mtd/nand/ libs-$(CONFIG_SPL_DRIVERS_MISC_SUPPORT) += drivers/misc/ -- 2.4.3.573.g4eafbef ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 49/54] spl: Add a debug string before the jump to U-Boot
As a debug option, add positive confirmation that SPL has completed
execution. This can help with diagnosing the location of unexpected hangs.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/spl/spl.c b/common/spl/spl.c
index 074c41d..94b01da 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -298,6 +298,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
gd->malloc_ptr / 1024);
#endif
+ debug("loaded - jumping to U-Boot...");
jump_to_image_no_args(&spl_image);
}
--
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[U-Boot] [PATCH v3 47/54] fdt: Provide debug info when a device tree cannot be found
It can be quite confusing with a new platform to figure out why the device
tree cannot be located. Add some debug information for this case.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
lib/fdtdec.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index add9adc..a78d577 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -568,6 +568,13 @@ int fdtdec_prepare_fdt(void)
puts("Missing DTB\n");
#else
puts("No valid device tree binary found - please append one to
U-Boot binary, use u-boot-dtb.bin or define CONFIG_OF_EMBED. For sandbox, use
-d \n");
+# ifdef DEBUG
+ if (gd->fdt_blob) {
+ printf("fdt_blob=%p\n", gd->fdt_blob);
+ print_buffer((ulong)gd->fdt_blob, gd->fdt_blob, 4,
+32, 0);
+ }
+# endif
#endif
return -1;
}
--
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[U-Boot] [PATCH v3 34/54] dm: power: Avoid case-insensitve match for child names
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/pmic-uclass.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/power/pmic/pmic-uclass.c b/drivers/power/pmic/pmic-uclass.c
index 812ac13..40b5135 100644
--- a/drivers/power/pmic/pmic-uclass.c
+++ b/drivers/power/pmic/pmic-uclass.c
@@ -55,7 +55,7 @@ int pmic_bind_children(struct udevice *pmic, int offset,
child = NULL;
for (info = child_info; info->prefix && info->driver; info++) {
prefix_len = strlen(info->prefix);
- if (strncasecmp(info->prefix, node_name, prefix_len))
+ if (strncmp(info->prefix, node_name, prefix_len))
continue;
debug(" - compatible prefix: '%s'\n", info->prefix);
--
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[U-Boot] [PATCH v3 52/54] zynq: Rename struct clk_ops to zynq_clk_ops
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq
version until it can be converted to driver model.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-zynq/clk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-zynq/clk.c b/arch/arm/mach-zynq/clk.c
index d2885dc..6444be8 100644
--- a/arch/arm/mach-zynq/clk.c
+++ b/arch/arm/mach-zynq/clk.c
@@ -48,11 +48,11 @@ DECLARE_GLOBAL_DATA_PTR;
struct clk;
/**
- * struct clk_ops:
+ * struct zynq_clk_ops:
* @set_rate: Function pointer to set_rate() implementation
* @get_rate: Function pointer to get_rate() implementation
*/
-struct clk_ops {
+struct zynq_clk_ops {
int (*set_rate)(struct clk *clk, unsigned long rate);
unsigned long (*get_rate)(struct clk *clk);
};
@@ -72,7 +72,7 @@ struct clk {
enum zynq_clk parent;
unsigned intflags;
u32 *reg;
- struct clk_ops ops;
+ struct zynq_clk_ops ops;
};
#define ZYNQ_CLK_FLAGS_HAS_2_DIVS 1
--
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[U-Boot] [PATCH v3 44/54] ns16550: Improve debug UART so it can work with 32-bit access
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/serial/ns16550.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 9b044a3..c8a77e2 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -246,6 +246,17 @@ int NS16550_tstc(NS16550_t com_port)
#include
+#define serial_dout(reg, value)\
+ serial_out_shift((char *)com_port + \
+ ((char *)reg - (char *)com_port) * \
+ (1 << CONFIG_DEBUG_UART_SHIFT), \
+ CONFIG_DEBUG_UART_SHIFT, value)
+#define serial_din(reg) \
+ serial_in_shift((char *)com_port + \
+ ((char *)reg - (char *)com_port) * \
+ (1 << CONFIG_DEBUG_UART_SHIFT), \
+ CONFIG_DEBUG_UART_SHIFT)
+
void debug_uart_init(void)
{
struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
@@ -259,28 +270,23 @@ void debug_uart_init(void)
*/
baud_divisor = calc_divisor(com_port, CONFIG_DEBUG_UART_CLOCK,
CONFIG_BAUDRATE);
- serial_out_shift(&com_port->ier, CONFIG_DEBUG_UART_SHIFT,
-CONFIG_SYS_NS16550_IER);
- serial_out_shift(&com_port->mcr, CONFIG_DEBUG_UART_SHIFT, UART_MCRVAL);
- serial_out_shift(&com_port->fcr, CONFIG_DEBUG_UART_SHIFT, UART_FCRVAL);
-
- serial_out_shift(&com_port->lcr, CONFIG_DEBUG_UART_SHIFT,
-UART_LCR_BKSE | UART_LCRVAL);
- serial_out_shift(&com_port->dll, CONFIG_DEBUG_UART_SHIFT,
-baud_divisor & 0xff);
- serial_out_shift(&com_port->dlm, CONFIG_DEBUG_UART_SHIFT,
-(baud_divisor >> 8) & 0xff);
- serial_out_shift(&com_port->lcr, CONFIG_DEBUG_UART_SHIFT,
-UART_LCRVAL);
+ serial_dout(&com_port->ier, CONFIG_SYS_NS16550_IER);
+ serial_dout(&com_port->mcr, UART_MCRVAL);
+ serial_dout(&com_port->fcr, UART_FCRVAL);
+
+ serial_dout(&com_port->lcr, UART_LCR_BKSE | UART_LCRVAL);
+ serial_dout(&com_port->dll, baud_divisor & 0xff);
+ serial_dout(&com_port->dlm, (baud_divisor >> 8) & 0xff);
+ serial_dout(&com_port->lcr, UART_LCRVAL);
}
static inline void _debug_uart_putc(int ch)
{
struct NS16550 *com_port = (struct NS16550 *)CONFIG_DEBUG_UART_BASE;
- while (!(serial_in_shift(&com_port->lsr, 0) & UART_LSR_THRE))
+ while (!(serial_din(&com_port->lsr) & UART_LSR_THRE))
;
- serial_out_shift(&com_port->thr, CONFIG_DEBUG_UART_SHIFT, ch);
+ serial_dout(&com_port->thr, ch);
}
DEBUG_UART_FUNCS
--
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