Re: [U-Boot] [PATCH 2/3] arm: at91/spl: matrix: improve implementation of matrix

[Yang, Wenyou]

Hi Josh,

Thank you for your review.

> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:54
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 2/3] arm: at91/spl: matrix: improve 
> implementation
> of matrix
> 
> Hi, Wenyou
> 
> On 11/4/2015 2:28 PM, Wenyou Yang wrote:
> > To make matrix initialization code sharing with others, use the matrix
> > slave id macros, instead of hard-coding.
> it is better if you split the following 'removing code' as another patch.
Thank you for your advice, next version I will handle it.

> 
> Best Regards,
> Josh Wu
> > Remove the write protection mode code, it is unneeded for writing
> > registers.
> >
> > Remove the security peripheral selecting code, it is unneeded for SPL
> > use-case.
> >
> > Signed-off-by: Wenyou Yang 
> > ---
> >
> >   arch/arm/mach-at91/include/mach/sama5d4.h |   25
> +
> >   arch/arm/mach-at91/matrix.c   |   35 
> > -
> >   2 files changed, 34 insertions(+), 26 deletions(-)
> >
> > diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h
> > b/arch/arm/mach-at91/include/mach/sama5d4.h
> > index 3da8aff..449cf0e 100644
> > --- a/arch/arm/mach-at91/include/mach/sama5d4.h
> > +++ b/arch/arm/mach-at91/include/mach/sama5d4.h
> > @@ -179,6 +179,31 @@
> >   #define CPU_HAS_PCR
> >   #define CPU_HAS_H32MXDIV
> >
> > +/* MATRIX0(H64MX) slave id definitions */
> > +#define H64MX_SLAVE_AXIMX_BRIDGE   0   /* Bridge from H64MX to
> AXIMX */
> > +#define H64MX_SLAVE_PERIPH_BRIDGE  1   /* H64MX Peripheral
> Bridge */
> > +#define H64MX_SLAVE_VDEC   2   /* Video Decoder */
> > +#define H64MX_SLAVE_DDRC_PORT0 3   /* DDR2 Port0-
> AESOTF */
> > +#define H64MX_SLAVE_DDRC_PORT1 4   /* DDR2 Port1 */
> > +#define H64MX_SLAVE_DDRC_PORT2 5   /* DDR2 Port2 */
> > +#define H64MX_SLAVE_DDRC_PORT3 6   /* DDR2 Port3 */
> > +#define H64MX_SLAVE_DDRC_PORT4 7   /* DDR2 Port4 */
> > +#define H64MX_SLAVE_DDRC_PORT5 8   /* DDR2 Port5 */
> > +#define H64MX_SLAVE_DDRC_PORT6 9   /* DDR2 Port6 */
> > +#define H64MX_SLAVE_DDRC_PORT7 10  /* DDR2 Port7 */
> > +#define H64MX_SLAVE_SRAM   11  /* Internal SRAM 128K */
> > +#define H64MX_SLAVE_H32MX_BRIDGE   12  /* Bridge from H64MX to
> H32MX */
> > +
> > +/* MATRIX1(H32MX) slave id definitions */
> > +#define H32MX_SLAVE_H64MX_BRIDGE   0   /* Bridge from H32MX to
> H64MX */
> > +#define H32MX_SLAVE_PERIPH_BRIDGE0 1   /* H32MX Peripheral
> Bridge 0 */
> > +#define H32MX_SLAVE_PERIPH_BRIDGE1 2   /* H32MX Peripheral
> Bridge 1 */
> > +#define H32MX_SLAVE_EBI3   /* External Bus 
> > Interface
> */
> > +#define H32MX_SLAVE_NFC_CMD3   /* NFC command
> Register */
> > +#define H32MX_SLAVE_NFC_SRAM   4   /* NFC SRAM */
> > +#define H32MX_SLAVE_USB5   /* USB Device &
> Host */
> > +#define H32MX_SLAVE_SMD6   /* Soft Modem
> (SMD) */
> > +
> >   /* sama5d4 series chip id definitions */
> >   #define ARCH_ID_SAMA5D4   0x8a5c07c0
> >   #define ARCH_EXID_SAMA5D410x0001
> > diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
> > index cf36386..57d7270 100644
> > --- a/arch/arm/mach-at91/matrix.c
> > +++ b/arch/arm/mach-at91/matrix.c
> > @@ -15,37 +15,20 @@ void matrix_init(void)
> > struct atmel_matrix *h32mx = (struct atmel_matrix
> *)ATMEL_BASE_MATRIX1;
> > int i;
> >
> > -   /* Disable the write protect */
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
> > -
> > -   /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
> > -   for (i = 4; i <= 10; i++) {
> > +   /* DDR port 1 ~ port 7 */
> > +   for (i = H64MX_SLAVE_DDRC_PORT1; i <=
> H64MX_SLAVE_DDRC_PORT7; i++) {
> > writel(0x000f0f0f, &h64mx->ssr[i]);
> > writel(0x, &h64mx->sassr[i]);
> > writel(0x000f, &h64mx->srtsr[i]);
> > }
> >
> > -   /* CS3 */
> > -   writel(0x00c0c0c0, &h32mx->ssr[3]);
> > -   writel(0xff00, &h32mx->sassr[3]);
> > -   writel(0xff00, &h32mx->srtsr[3]);
> > +   /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
> > +   writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
> > +   writel(0xff00, &h32mx->sassr[H32MX_SLAVE_EBI]);
> > +   writel(0xff00, &h32mx->srtsr[H32MX_SLAVE_EBI]);
> >
> > /* NFC SRAM */
> > -   writel(0x00010101, &h32mx->ssr[4]);
> > -   writel(0x0001, &h32mx->sassr[4]);
> > -   writel(0x0001, &h32mx->srtsr[4]);
> > -
> > -   /* Configure Programmable Security peripherals on matrix 64 */
> > -   writel(readl(&h64mx->spselr[0]) | 0x0008, &h64mx->spselr[0]);
> > -   writel(readl(&h64mx->spselr[1]) | 0x0018, &h64mx->spselr[1]);
> > -   

Re: [U-Boot] [PATCH v4 01/16] spi: Add zynq qspi controller driver

[Jagan Teki]

On 5 November 2015 at 13:03, Hannes Schmelzer  wrote:
> Hi Jagan,
>
> did you take notice about that?
> Maybe i've not seen your answer.

I will get my hardware next week, sure we can discuss this.

>
>
> On 15.10.2015 10:39, Hannes Schmelzer wrote:
>>
>>
>> Hi Jagan,
>>
>> during bringing up QSPI within SPL on my ZYNQ ZC702 board i made some
>> review of your code.
>> Have a look.
>>
>> On 01.09.2015 08:11, Jagan Teki wrote:
>>>
>>> Added zynq qspi controller driver for Xilinx Zynq APSOC,
>>> this driver is driver-model driven with devicetree support.
>>
>> (...)
>>>
>>> +
>>> +/* zynq qspi priv */
>>> +struct zynq_qspi_priv {
>>> +struct zynq_qspi_regs *regs;
>>> +u8 cs;
>>> +u8 mode;
>>> +u8 fifo_depth;
>>> +u32 freq;/* required frequency */
>>> +const void *tx_buf;
>>> +void *rx_buf;
>>> +unsigned len;
>>> +int bytes_to_transfer;
>>> +int bytes_to_receive;
>>> +unsigned int is_inst;
>>> +unsigned cs_change:1;
>>> +};
>>
>> why not use "u32" for len ?
>>>
>>> +static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
>>> +{
>>> +struct zynq_qspi_regs *regs = priv->regs;
>>> +u32 confr;
>>
>> During bring up this driver within SPL i've figured out, that it is very
>> important to do a clear reset to the QSPI unit.
>> Initially the ROM codes fetches our SPL-binary from the flash into the OCM
>> and executes.
>> We don't know at this point how ROM-code has left the QSPI unit, and have
>> to reset the Unit using responsible Bits in sclr area.
>> Otherwise we can see strange behaviours like hang on reading RxFIFO
>> sometimes and sometimes not.
>>>
>>> +
>>> +/* Disable QSPI */
>>> +writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
>>> +
>>> +/* Disable Interrupts */
>>> +writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
>>> +
>>> +/* Clear the TX and RX threshold reg */
>>> +writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
>>> +writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
>>> +
>>> +/* Clear the RX FIFO */
>>> +while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
>>> +readl(®s->drxr);
>>> +
>>> +/* Clear Interrupts */
>>> +writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
>>> +
>>> +/* Manual slave select and Auto start */
>>> +confr = readl(®s->cr);
>>> +confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
>>> +confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
>>> +ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
>>> +ZYNQ_QSPI_CR_MSTREN_MASK;
>>> +writel(confr, ®s->cr);
>>> +
>>> +/* Enable SPI */
>>> +writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
>>> +}
>>
>> (...)
>>>
>>> +
>>> +/*
>>> + * zynq_qspi_read_data - Copy data to RX buffer
>>> + * @zqspi:Pointer to the zynq_qspi structure
>>> + * @data:The 32 bit variable where data is stored
>>> + * @size:Number of bytes to be copied from data to RX buffer
>>> + */
>>> +static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data,
>>> u8 size)
>>> +{
>>> +u8 byte3;
>>> +
>>> +debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
>>> +  data, (unsigned)(priv->rx_buf), size);
>>
>> use 0x%p instead 0x%08x to display pointer addresses, with the advantage
>> that no cast is necessary.
>>>
>>> +
>>> +if (priv->rx_buf) {
>>> +switch (size) {
>>> +case 1:
>>> +*((u8 *)priv->rx_buf) = data;
>>> +priv->rx_buf += 1;
>>> +break;
>>> +case 2:
>>> +*((u16 *)priv->rx_buf) = data;
>>> +priv->rx_buf += 2;
>>> +break;
>>> +case 3:
>>> +*((u16 *)priv->rx_buf) = data;
>>> +priv->rx_buf += 2;
>>> +byte3 = (u8)(data >> 16);
>>> +*((u8 *)priv->rx_buf) = byte3;
>>> +priv->rx_buf += 1;
>>> +break;
>>> +case 4:
>>> +/* Can not assume word aligned buffer */
>>> +memcpy(priv->rx_buf, &data, size);
>>> +priv->rx_buf += 4;
>>> +break;
>>> +default:
>>> +/* This will never execute */
>>> +break;
>>> +}
>>> +}
>>> +priv->bytes_to_receive -= size;
>>> +if (priv->bytes_to_receive < 0)
>>> +priv->bytes_to_receive = 0;
>>> +}
>>
>> wouldn't it be good enough using always "memcpy" ?
>> maybe we can drop this function completely ?
>>>
>>> +
>>> +/*
>>> + * zynq_qspi_write_data - Copy data from TX buffer
>>> + * @zqspi:Pointer to the zynq_qspi structure
>>> + * @data:Pointer to the 32 bit variable where data is to be copied
>>> + * @size:Number of bytes to be copied from TX buffer to data
>>> + */
>>> +static void zynq_qspi_write_data(struct  zynq_qspi_priv *priv,
>>> +u32 *data, u8 size)
>>> +{
>>> +if (priv->tx_buf) {
>>> +switch (size) {
>>> +case 1:
>>> +*data = *((u8 *)priv->tx_buf);
>>> +priv->tx_buf += 1;
>>> +*data |= 0xFF00;
>>> +break;

Re: [U-Boot] [PATCH 3/3] arm: at91: spl/atmel_sfr: move saic redirect to separate file

[Yang, Wenyou]

Hi Josh,

Thank you for your review.

> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:59
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 3/3] arm: at91: spl/atmel_sfr: move saic 
> redirect to
> separate file
> 
> Hi, Wenyou
> 
> On 11/4/2015 2:28 PM, Wenyou Yang wrote:
> > To make saic redirect code sharing with other SoCs, move the saic
> > redirect code from SAMA5D4 particular file,
> > mach-at91/armv7/sama5d4_devices.c to a separate file,
> > mach-at91/atmel_sfr.c
> 
> maybe move it as mach-at91/armv7/atmel_sfr.c?
The explanation is given at the previous mail.

> 
> Best Regards,
> Josh Wu
> >
> > Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
> SoC
> > has its own value.
> >
> > Signed-off-by: Wenyou Yang 
> > ---
> >
> >   arch/arm/mach-at91/Makefile |2 +-
> >   arch/arm/mach-at91/armv7/sama5d4_devices.c  |   13 -
> >   arch/arm/mach-at91/atmel_sfr.c  |   21 +
> >   arch/arm/mach-at91/include/mach/sama5_sfr.h |1 -
> >   arch/arm/mach-at91/include/mach/sama5d4.h   |3 +++
> >   5 files changed, 25 insertions(+), 15 deletions(-)
> >   create mode 100644 arch/arm/mach-at91/atmel_sfr.c
> >
> > diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> > index 649aff2..ca60397 100644
> > --- a/arch/arm/mach-at91/Makefile
> > +++ b/arch/arm/mach-at91/Makefile
> > @@ -6,7 +6,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o
> spl_at91.o
> >   obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
> >   obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
> >   obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
> > -obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o
> > +obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
> >   obj-y += spl.o
> >   endif
> >
> > diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > b/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > index 52f4862..ce33cd4 100644
> > --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > @@ -45,16 +45,3 @@ void at91_udp_hw_init(void)
> > at91_periph_clk_enable(ATMEL_ID_UDPHS);
> >   }
> >   #endif
> > -
> > -#ifdef CONFIG_SPL_BUILD
> > -void redirect_int_from_saic_to_aic(void)
> > -{
> > -   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
> > -   u32 key32;
> > -
> > -   if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
> > -   key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
> > -   writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
> > -   }
> > -}
> > -#endif
> > diff --git a/arch/arm/mach-at91/atmel_sfr.c
> > b/arch/arm/mach-at91/atmel_sfr.c new file mode 100644 index
> > 000..2bccb84
> > --- /dev/null
> > +++ b/arch/arm/mach-at91/atmel_sfr.c
> > @@ -0,0 +1,21 @@
> > +/*
> > + * Copyright (C) 2015 Atmel Corporation
> > + *   Wenyou Yang 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +void redirect_int_from_saic_to_aic(void)
> > +{
> > +   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
> > +   u32 key32;
> > +
> > +   if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
> > +   key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
> > +   writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
> > +   }
> > +}
> > diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h
> > b/arch/arm/mach-at91/include/mach/sama5_sfr.h
> > index 3081d37..7b19a20 100644
> > --- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
> > +++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
> > @@ -32,7 +32,6 @@ struct atmel_sfr {
> >   #define ATMEL_SFR_DDRCFG_FDQSIEN  0x0002
> >
> >   /* Bit field in AICREDIR */
> > -#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
> >   #define ATMEL_SFR_AICREDIR_NSAIC  0x0001
> >
> >   #endif
> > diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h
> > b/arch/arm/mach-at91/include/mach/sama5d4.h
> > index 449cf0e..90085da 100644
> > --- a/arch/arm/mach-at91/include/mach/sama5d4.h
> > +++ b/arch/arm/mach-at91/include/mach/sama5d4.h
> > @@ -204,6 +204,9 @@
> >   #define H32MX_SLAVE_USB   5   /* USB Device &
> Host */
> >   #define H32MX_SLAVE_SMD   6   /* Soft Modem
> (SMD) */
> >
> > +/* AICREDIR Unlock Key */
> > +#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
> > +
> >   /* sama5d4 series chip id definitions */
> >   #define ARCH_ID_SAMA5D4   0x8a5c07c0
> >   #define ARCH_EXID_SAMA5D410x0001

Best Regards,
Wenyou Yang

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Re: [U-Boot] [PATCH 1/3] arm: at91/spl: matrix: move matrix init to separate file

[Yang, Wenyou]

Hi Josh,

Thank you for your review.

> -Original Message-
> From: Wu, Josh
> Sent: 2015年11月5日 10:53
> To: Yang, Wenyou; U-Boot Mailing List
> Subject: Re: [U-Boot] [PATCH 1/3] arm: at91/spl: matrix: move matrix init to
> separate file
> 
> Hi, Wenyou
> 
> On 11/4/2015 2:28 PM, Wenyou Yang wrote:
> > To make the matrix initialization code sharing with other SoCs, move
> > it from SAMA5D4 particular file, mach-at91/armv7/sama5d4_devices.c to
> > a separate file, mach-at91/matrix.c
> is it possible just move it to mach-at91/armv7/matrix.c, as it is only used by
> armv7 core?
As you know, the at91 spl code is placed at the directory, mach-at91/, so place 
matrix.c here is acceptable.
Yes,  we should consider a separate directory to accommodate the at91 spl code 
in the future.

> 
> Best Regards,
> Josh Wu
> >
> > Signed-off-by: Wenyou Yang 
> > ---
> >
> >   arch/arm/mach-at91/Makefile|2 +-
> >   arch/arm/mach-at91/armv7/sama5d4_devices.c |   42 ---
> >   arch/arm/mach-at91/matrix.c|   51
> 
> >   3 files changed, 52 insertions(+), 43 deletions(-)
> >   create mode 100644 arch/arm/mach-at91/matrix.c
> >
> > diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> > index 313eb47..649aff2 100644
> > --- a/arch/arm/mach-at91/Makefile
> > +++ b/arch/arm/mach-at91/Makefile
> > @@ -6,7 +6,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o
> spl_at91.o
> >   obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
> >   obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
> >   obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
> > -obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
> > +obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o
> >   obj-y += spl.o
> >   endif
> >
> > diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > b/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > index 76301d6..52f4862 100644
> > --- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
> > @@ -10,7 +10,6 @@
> >   #include 
> >   #include 
> >   #include 
> > -#include 
> >   #include 
> >   #include 
> >
> > @@ -48,47 +47,6 @@ void at91_udp_hw_init(void)
> >   #endif
> >
> >   #ifdef CONFIG_SPL_BUILD
> > -void matrix_init(void)
> > -{
> > -   struct atmel_matrix *h64mx = (struct atmel_matrix
> *)ATMEL_BASE_MATRIX0;
> > -   struct atmel_matrix *h32mx = (struct atmel_matrix
> *)ATMEL_BASE_MATRIX1;
> > -   int i;
> > -
> > -   /* Disable the write protect */
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
> > -
> > -   /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
> > -   for (i = 4; i <= 10; i++) {
> > -   writel(0x000f0f0f, &h64mx->ssr[i]);
> > -   writel(0x, &h64mx->sassr[i]);
> > -   writel(0x000f, &h64mx->srtsr[i]);
> > -   }
> > -
> > -   /* CS3 */
> > -   writel(0x00c0c0c0, &h32mx->ssr[3]);
> > -   writel(0xff00, &h32mx->sassr[3]);
> > -   writel(0xff00, &h32mx->srtsr[3]);
> > -
> > -   /* NFC SRAM */
> > -   writel(0x00010101, &h32mx->ssr[4]);
> > -   writel(0x0001, &h32mx->sassr[4]);
> > -   writel(0x0001, &h32mx->srtsr[4]);
> > -
> > -   /* Configure Programmable Security peripherals on matrix 64 */
> > -   writel(readl(&h64mx->spselr[0]) | 0x0008, &h64mx->spselr[0]);
> > -   writel(readl(&h64mx->spselr[1]) | 0x0018, &h64mx->spselr[1]);
> > -   writel(readl(&h64mx->spselr[2]) | 0x0008, &h64mx->spselr[2]);
> > -
> > -   /* Configure Programmable Security peripherals on matrix 32 */
> > -   writel(readl(&h32mx->spselr[0]) | 0xFFC0, &h32mx->spselr[0]);
> > -   writel(readl(&h32mx->spselr[1]) | 0x60E3, &h32mx->spselr[1]);
> > -
> > -   /* Enable the write protect */
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY |
> ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
> > -   writel(ATMEL_MATRIX_WPMR_WPKEY |
> ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
> > -}
> > -
> >   void redirect_int_from_saic_to_aic(void)
> >   {
> > struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; diff
> > --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c new
> > file mode 100644 index 000..cf36386
> > --- /dev/null
> > +++ b/arch/arm/mach-at91/matrix.c
> > @@ -0,0 +1,51 @@
> > +/*
> > + * Copyright (C) 2015 Atmel Corporation
> > + *   Wenyou Yang 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +
> > +void matrix_init(void)
> > +{
> > +   struct atmel_matrix *h64mx = (struct atmel_matrix
> *)ATMEL_BASE_MATRIX0;
> > +   struct atmel_matrix *h32mx = (struct atmel_matrix
> *)ATMEL_BASE_MATRIX1;
> > +   int i;
> > +
> > +   /* Disable the write protect */
> > +   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
> > +   writel(ATMEL_MATRIX_WPMR_WPKEY &
> ~ATMEL_MATRIX_WPMR_WPEN,
> > +&h32mx->wpmr);
> > +
> > +   /* D

Re: [U-Boot] [PATCH 2/2] video: Drop DEV_EXT_VIDEO flag

[Anatolij Gustschin]

On Tue,  3 Nov 2015 23:23:38 -0800
Bin Meng  wrote:

> DEV_EXT_VIDEO does not have any actual meaning, hence drop it.
> 
> Signed-off-by: Bin Meng 
> 
> ---
> 
>  arch/powerpc/cpu/mpc8xx/video.c | 1 -
>  board/bf527-ezkit/video.c   | 1 -
>  board/bf533-stamp/video.c   | 1 -
>  board/bf548-ezkit/video.c   | 1 -
>  board/cm-bf548/video.c  | 1 -
>  drivers/video/cfb_console.c | 1 -
>  include/stdio_dev.h | 1 -
>  7 files changed, 7 deletions(-)

applied to u-boot-video/master, thanks!

Anatolij
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Re: [U-Boot] [PATCH 1/2] video: Drop DEV_FLAGS_SYSTEM flag

[Anatolij Gustschin]

On Tue,  3 Nov 2015 23:23:37 -0800
Bin Meng  wrote:

> DEV_FLAGS_SYSTEM does not have any actual meaning, hence drop it.
> 
> Signed-off-by: Bin Meng 
> ---
> 
>  arch/blackfin/cpu/jtag-console.c | 2 +-
>  board/bf527-ezkit/video.c| 1 -
>  board/bf533-stamp/video.c| 1 -
>  board/bf548-ezkit/video.c| 1 -
>  board/cm-bf548/video.c   | 1 -
>  board/kosagi/novena/novena.c | 2 +-
>  board/mpl/common/kbd.c   | 2 +-
>  board/mpl/pati/pati.c| 2 +-
>  common/cmd_console.c | 3 +--
>  common/stdio.c   | 4 ++--
>  common/usb_kbd.c | 2 +-
>  drivers/input/cros_ec_keyb.c | 2 +-
>  drivers/input/keyboard.c | 2 +-
>  drivers/input/tegra-kbc.c| 2 +-
>  drivers/net/netconsole.c | 2 +-
>  drivers/video/cfb_console.c  | 2 +-
>  include/stdio_dev.h  | 1 -
>  17 files changed, 13 insertions(+), 19 deletions(-)

applied to u-boot-video/master, thanks!

Anatolij
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Re: [U-Boot] [PATCH V3 01/16] mxs: add parameter base_addr for mxs_set_lcdclk

[Anatolij Gustschin]

On Thu, 29 Oct 2015 15:54:39 +0800
Peng Fan  wrote:

> Change mxs_set_lcdclk prototype to add a new parameter
> base_addr. There are two LCD interfaces for i.MX6SX,
> we may support LCDIF1 or LCDIF2.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Anatolij Gustschin 
> ---
> 
> V3:
>  Add __maybe_unused attribute
> 
> V2:
>  none
> 
>  arch/arm/cpu/arm926ejs/mxs/clock.c| 2 +-
>  arch/arm/include/asm/arch-mxs/clock.h | 2 +-
>  drivers/video/mxsfb.c | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)

Acked-by: Anatolij Gustschin 
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Re: [U-Boot] [PATCH v4 01/16] spi: Add zynq qspi controller driver

[Hannes Schmelzer]

Hi Jagan,

did you take notice about that?
Maybe i've not seen your answer.

regards,
Hannes


On 15.10.2015 10:39, Hannes Schmelzer wrote:


Hi Jagan,

during bringing up QSPI within SPL on my ZYNQ ZC702 board i made some 
review of your code.

Have a look.

On 01.09.2015 08:11, Jagan Teki wrote:

Added zynq qspi controller driver for Xilinx Zynq APSOC,
this driver is driver-model driven with devicetree support.

(...)

+
+/* zynq qspi priv */
+struct zynq_qspi_priv {
+struct zynq_qspi_regs *regs;
+u8 cs;
+u8 mode;
+u8 fifo_depth;
+u32 freq;/* required frequency */
+const void *tx_buf;
+void *rx_buf;
+unsigned len;
+int bytes_to_transfer;
+int bytes_to_receive;
+unsigned int is_inst;
+unsigned cs_change:1;
+};

why not use "u32" for len ?

+static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
+{
+struct zynq_qspi_regs *regs = priv->regs;
+u32 confr;
During bring up this driver within SPL i've figured out, that it is 
very important to do a clear reset to the QSPI unit.
Initially the ROM codes fetches our SPL-binary from the flash into the 
OCM and executes.
We don't know at this point how ROM-code has left the QSPI unit, and 
have to reset the Unit using responsible Bits in sclr area.
Otherwise we can see strange behaviours like hang on reading RxFIFO 
sometimes and sometimes not.

+
+/* Disable QSPI */
+writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
+
+/* Disable Interrupts */
+writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->idr);
+
+/* Clear the TX and RX threshold reg */
+writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, ®s->txftr);
+writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, ®s->rxftr);
+
+/* Clear the RX FIFO */
+while (readl(®s->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
+readl(®s->drxr);
+
+/* Clear Interrupts */
+writel(ZYNQ_QSPI_IXR_ALL_MASK, ®s->isr);
+
+/* Manual slave select and Auto start */
+confr = readl(®s->cr);
+confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
+confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
+ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
+ZYNQ_QSPI_CR_MSTREN_MASK;
+writel(confr, ®s->cr);
+
+/* Enable SPI */
+writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, ®s->enr);
+}

(...)

+
+/*
+ * zynq_qspi_read_data - Copy data to RX buffer
+ * @zqspi:Pointer to the zynq_qspi structure
+ * @data:The 32 bit variable where data is stored
+ * @size:Number of bytes to be copied from data to RX buffer
+ */
+static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 
data, u8 size)

+{
+u8 byte3;
+
+debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
+  data, (unsigned)(priv->rx_buf), size);
use 0x%p instead 0x%08x to display pointer addresses, with the 
advantage that no cast is necessary.

+
+if (priv->rx_buf) {
+switch (size) {
+case 1:
+*((u8 *)priv->rx_buf) = data;
+priv->rx_buf += 1;
+break;
+case 2:
+*((u16 *)priv->rx_buf) = data;
+priv->rx_buf += 2;
+break;
+case 3:
+*((u16 *)priv->rx_buf) = data;
+priv->rx_buf += 2;
+byte3 = (u8)(data >> 16);
+*((u8 *)priv->rx_buf) = byte3;
+priv->rx_buf += 1;
+break;
+case 4:
+/* Can not assume word aligned buffer */
+memcpy(priv->rx_buf, &data, size);
+priv->rx_buf += 4;
+break;
+default:
+/* This will never execute */
+break;
+}
+}
+priv->bytes_to_receive -= size;
+if (priv->bytes_to_receive < 0)
+priv->bytes_to_receive = 0;
+}

wouldn't it be good enough using always "memcpy" ?
maybe we can drop this function completely ?

+
+/*
+ * zynq_qspi_write_data - Copy data from TX buffer
+ * @zqspi:Pointer to the zynq_qspi structure
+ * @data:Pointer to the 32 bit variable where data is to be copied
+ * @size:Number of bytes to be copied from TX buffer to data
+ */
+static void zynq_qspi_write_data(struct  zynq_qspi_priv *priv,
+u32 *data, u8 size)
+{
+if (priv->tx_buf) {
+switch (size) {
+case 1:
+*data = *((u8 *)priv->tx_buf);
+priv->tx_buf += 1;
+*data |= 0xFF00;
+break;
+case 2:
+*data = *((u16 *)priv->tx_buf);
+priv->tx_buf += 2;
+*data |= 0x;
+break;
+case 3:
+*data = *((u16 *)priv->tx_buf);
+priv->tx_buf += 2;
+*data |= (*((u8 *)priv->tx_buf) << 16);
+priv->tx_buf += 1;
+*data |= 0xFF00;
+break;
+case 4:
+/* Can not assume word aligned buffer */
+memcpy(data, priv->tx_buf, size);
+priv->tx_buf += 4;
+break;
+default:
+/* This will never execute */
+break;
+}
+} else {
+

Re: [U-Boot] [PATCH V3 12/16] video: mxsfb: introduce lcdif_power_down

[Anatolij Gustschin]

On Thu, 29 Oct 2015 15:54:49 +0800
Peng Fan  wrote:

> Introudce a new function lcdif_power_down.
> 
> 1. Waits for a VSYNC interrupt to guarantee the reset is done at the
>VSYNC edge, which somehow makes the LCDIF consume the display FIFO(?)
>and helps the LCDIF work normally at the kernel stage.
> 2. Add power down function to stop lcdif.
> 
> The reason to introduce lcdif_power_down is that we want lcdif to be in
> initial state when doing uboot reset or before kernel boot to make
> system stable, otherwise system may hang.
> 
> Signed-off-by: Peng Fan 
> Cc: Stefano Babic 
> Cc: Anatolij Gustschin 
> ---
> 
> V3:
>  none
> V2:
>  none
> 
>  arch/arm/include/asm/imx-common/sys_proto.h |  2 ++
>  drivers/video/mxsfb.c   | 17 +
>  2 files changed, 19 insertions(+)

Acked-by: Anatolij Gustschin 
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Re: [U-Boot] [PATCH] Makefile: Include vendor common library in include search path

[Nishanth Menon]

On 11/05/2015 01:28 AM, Nishanth Menon wrote:
> When the vendor common libraries exists, then board should be able to
> reference headers located there, rather than having to do weird logic
> such as '#include "../common/xyz.h"'.
> 
> Signed-off-by: Nishanth Menon 
> ---
> 
>  Makefile| 1 +
>  board/ti/am57xx/board.c | 2 +-
>  2 files changed, 2 insertions(+), 1 deletion(-)

Arrgh.. Apologies on the diffstat messup, but anyways, the patch does
apply, and will wait to repost in case of further comments.

> 
> diff --git a/Makefile b/Makefile
> index 3c21f8ddf9e9..75d5ea802dfd 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -620,6 +620,7 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
>  # U-Boot objectsorder is important (i.e. start must be first)
>  
>  HAVE_VENDOR_COMMON_LIB = $(if $(wildcard 
> $(srctree)/board/$(VENDOR)/common/Makefile),y,n)
> +UBOOTINCLUDE += $(if $(HAVE_VENDOR_COMMON_LIB:y=1), 
> -I$(srctree)/board/$(VENDOR)/common)
>  
>  libs-y += lib/
>  libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
> 


-- 
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Nishanth Menon
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[U-Boot] [PATCH] Makefile: Include vendor common library in include search path

[Nishanth Menon]

When the vendor common libraries exists, then board should be able to
reference headers located there, rather than having to do weird logic
such as '#include "../common/xyz.h"'.

Signed-off-by: Nishanth Menon 
---

 Makefile| 1 +
 board/ti/am57xx/board.c | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 3c21f8ddf9e9..75d5ea802dfd 100644
--- a/Makefile
+++ b/Makefile
@@ -620,6 +620,7 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
 # U-Boot objectsorder is important (i.e. start must be first)
 
 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard 
$(srctree)/board/$(VENDOR)/common/Makefile),y,n)
+UBOOTINCLUDE += $(if $(HAVE_VENDOR_COMMON_LIB:y=1), 
-I$(srctree)/board/$(VENDOR)/common)
 
 libs-y += lib/
 libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/
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Re: [U-Boot] [PATCH 5/5] LS102XA:workaround:disable priorities within DDR

[Yao Yuan]

Yes, it's an erratum. But I don't have the erratum  number from the document. I 
will connect the hardware team to check whether there is an erratum number.

Thanks.

Best Regards,
Yuan Yao

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05, 2015 2:49 AM
> To: Yuan Yao-B46683 ; Wang Huan-B18965
> 
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH 5/5] LS102XA:workaround:disable priorities within DDR
> 
> 
> 
> On 10/21/2015 03:14 AM, Yuan Yao wrote:
> > EDDRTQCFG Registers are Integration Strap values which controls
> > performance parameters for DDR Controller.
> >
> > The bit 25 is used to disable priorities within DDR since DDR are
> > connected backwards on Rev2.0.
> >
> > Signed-off-by: Yuan Yao 
> > ---
> >  arch/arm/cpu/armv7/ls102xa/soc.c | 13 -
> >  1 file changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c
> > b/arch/arm/cpu/armv7/ls102xa/soc.c
> > index b15cd60..98d4acd 100644
> > --- a/arch/arm/cpu/armv7/ls102xa/soc.c
> > +++ b/arch/arm/cpu/armv7/ls102xa/soc.c
> > @@ -25,7 +25,7 @@ int arch_soc_init(void)  {
> > struct ccsr_scfg *scfg = (struct ccsr_scfg
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> > struct ccsr_cci400 *cci = (struct ccsr_cci400
> *)CONFIG_SYS_CCI400_ADDR;
> > -   unsigned int major;
> > +   unsigned int major, reg;
> >
> >  #ifdef CONFIG_FSL_QSPI
> > out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); @@ -86,5 +86,16 @@
> int
> > arch_soc_init(void)
> >  */
> > out_be32(&scfg->eddrtqcfg, 0x63b20002);
> >
> > +   /*
> > +* EDDRTQCFG Registers are Integration Strap values which controls
> > +* performance parameters for DDR Controller.
> > +* The bit 25 is used for disable priorities within DDR.
> > +* This is a workaround because of the DDR are connected backwards
> > +* on Rev2.0.
> > +*/
> 
> Is there an erratum number for this? If not, please be specific about rev 2.0.
> Is it SoC version, or something else?
> 
> York
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Re: [U-Boot] [PATCH v3 3/5] ARM: omap-common: Add standard access for board description EEPROM

[Nishanth Menon]

On 11/05/2015 12:00 AM, Lokesh Vutla wrote:
[...]

>> diff --git a/board/ti/common/board.h b/board/ti/common/board.h
>> new file mode 100644
>> index ..19d63cad82f9
>> --- /dev/null
>> +++ b/board/ti/common/board.h
> 
> May be keep this header file under arch/arm/include/asm/ so that it can
> be included properly.
> 
if we do something like this: then we'd not have to add cruft to the
generic location..

diff --git a/Makefile b/Makefile
index 3c21f8ddf9e9..75d5ea802dfd 100644
--- a/Makefile
+++ b/Makefile
@@ -620,6 +620,7 @@ c_flags := $(KBUILD_CFLAGS) $(cpp_flags)
 # U-Boot objectsorder is important (i.e. start must be first)

 HAVE_VENDOR_COMMON_LIB = $(if $(wildcard
$(srctree)/board/$(VENDOR)/common/Makefile),y,n)
+UBOOTINCLUDE += $(if $(HAVE_VENDOR_COMMON_LIB:y=1),
-I$(srctree)/board/$(VENDOR)/common)

 libs-y += lib/
 libs-$(HAVE_VENDOR_COMMON_LIB) += board/$(VENDOR)/common/



-- 
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Nishanth Menon
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[U-Boot] [v2] please pull u-boot-samsung master

[Minkyu Kang]

Dear Tom,

The following changes since commit 0e067a65f57189703668826d9841fea477026bf6:

  x86: Select the ns16550 debug UART for minnowmax, chromebook_link (2015-10-30 
18:04:14 -0400)

are available in the git repository at:

  http://git.denx.de/u-boot-samsung 

for you to fetch changes up to 58cb44cf6623faeebd9b04ac44cf11d2eb39ea36:

  sandbox: adc: Add missing header file (2015-11-05 12:58:04 +0900)


Minkyu Kang (5):
  arm: exynos: clean up checkpatch issues
  smdkv310: clean up checkpatch issues
  smdk2410: clean up checkpatch issues
  odroid: clean up checkpatch issues
  samsung: clean up checkpatch issues

Przemyslaw Marczak (17):
  samsung: board/misc: check returned pointer for get_board_type() calls
  s5p: cpu_info: print "cpu-model" if exists in dts
  Peach-Pi: dts: add cpu-model string
  Exynos5422/5800: set cpu id to 0x5422
  dm: pmic: add s2mps11 PMIC I/O driver
  dm: regulator: add function device_get_supply_regulator()
  dm: adc: add simple ADC uclass implementation
  dm: adc: add Exynos54xx compatible ADC driver
  Odroid-XU3: enable s2mps11 PMIC support
  Exynos54xx: dts: add ADC node
  Odroid-XU3: dts: enable ADC, with request for pre-reloc bind
  exynos5-dt-types: add board detection for Odroid XU3/XU3L/XU4.
  sandbox: add ADC driver
  sandbox: add ADC unit tests
  Exynos4412: pinmux: disable pull for MMC pins
  s5p sdhci: call pinmux for card's gpio pins before use them
  sandbox: adc: Add missing header file

 arch/arm/cpu/armv7/s5p-common/cpu_info.c   |  14 +-
 arch/arm/dts/exynos5422-odroidxu3.dts  |  12 +
 arch/arm/dts/exynos54xx.dtsi   |   7 +
 arch/arm/dts/exynos5800-peach-pi.dts   |   1 +
 arch/arm/mach-exynos/clock.c   |  16 +-
 arch/arm/mach-exynos/clock_init_exynos5.c  |   2 +-
 arch/arm/mach-exynos/common_setup.h|   4 +-
 arch/arm/mach-exynos/dmc_init_ddr3.c   |   8 +-
 arch/arm/mach-exynos/include/mach/adc.h|  44 
 arch/arm/mach-exynos/include/mach/cpu.h|   6 +-
 arch/arm/mach-exynos/include/mach/gpio.h   |   4 +-
 arch/arm/mach-exynos/pinmux.c  |   4 +-
 arch/arm/mach-exynos/power.c   |   2 +-
 arch/sandbox/dts/sandbox_pmic.dtsi |   2 +-
 arch/sandbox/dts/test.dts  |   6 +
 board/samsung/common/Makefile  |   5 +-
 board/samsung/common/board.c   |   4 +-
 board/samsung/common/exynos5-dt-types.c| 196 ++
 board/samsung/common/exynos5-dt.c  |  12 +
 board/samsung/common/misc.c|  10 +-
 board/samsung/odroid/odroid.c  |  15 +-
 board/samsung/smdk2410/smdk2410.c  |  10 +-
 board/samsung/smdkv310/smdkv310.c  |   8 +-
 configs/odroid-xu3_defconfig   |   5 +
 configs/sandbox_defconfig  |   2 +
 doc/device-tree-bindings/adc/adc.txt   |  62 +
 doc/device-tree-bindings/exynos/soc.txt|  21 ++
 doc/device-tree-bindings/pmic/s2mps11.txt  |  17 ++
 drivers/Kconfig|   2 +
 drivers/Makefile   |   1 +
 drivers/adc/Kconfig|  30 +++
 drivers/adc/Makefile   |  10 +
 drivers/adc/adc-uclass.c   | 409 +
 drivers/adc/exynos-adc.c   | 145 ++
 drivers/adc/sandbox.c  | 174 
 drivers/mmc/s5p_sdhci.c|  14 +-
 drivers/power/pmic/Kconfig |  14 +
 drivers/power/pmic/Makefile|   1 +
 drivers/power/pmic/s2mps11.c   |  62 +
 drivers/power/regulator/regulator-uclass.c |   7 +
 include/adc.h  | 288 
 include/configs/odroid_xu3.h   |  12 +
 include/dm/uclass-id.h |   1 +
 include/power/regulator.h  |  16 ++
 include/power/s2mps11.h| 109 
 include/power/sandbox_pmic.h   |   4 +
 include/samsung/exynos5-dt-types.h |  27 ++
 include/sandbox-adc.h  |  31 +++
 test/dm/Makefile   |   1 +
 test/dm/adc.c  | 165 
 50 files changed, 1966 insertions(+), 56 deletions(-)
 create mode 100644 board/samsung/common/exynos5-dt-types.c
 create mode 100644 doc/device-tree-bindings/adc/adc.txt
 create mode 100644 doc/device-tree-bindings/exynos/soc.txt
 create mode 100644 doc/device-tree-bindings/pmic/s2mps11.txt
 create mode 100644 drivers/adc/Kconfig
 create mode 100644 drivers/adc/Makefile
 create mode 100644 drivers/adc/adc-uclass.c
 create mode 100644 drivers/adc/exynos-adc.c
 create mode 100644 drivers/adc/sandbox.c
 create mode 100644 drivers/power/pmic/s2mps11.c
 create mode 100644 include/adc.h
 create mode 100644 include/power/s2mps11.h
 create mode 100644 inc

Re: [U-Boot] [PATCH] sandbox: adc: Add missing header file

[Minkyu Kang]

2015년 11월 5일 목요일, Przemyslaw Marczak님이 작성한 메시지:

> Commit: sandbox: add ADC driver
>
> adds the driver without its main header file.
> It causes build brake for sandbox_defonfig.
>
> This commit adds a missing header:
> - include/sandbox-adc.h
>
> Signed-off-by: Przemyslaw Marczak >
> Cc: Minkyu Kang >
> Cc: Simon Glass >
> ---
>  include/sandbox-adc.h | 31 +++
>  1 file changed, 31 insertions(+)
>  create mode 100644 include/sandbox-adc.h
>
> diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h
> new file mode 100644
> index 000..79ff01c
> --- /dev/null
> +++ b/include/sandbox-adc.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright (C) 2015 Samsung Electronics
> + * Przemyslaw Marczak >
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#ifndef _SANDBOX_ADC_H_
> +#define _SANDBOX_ADC_H_
> +
> +#define SANDBOX_ADC_DEVNAME"adc@0"
> +#define SANDBOX_ADC_DATA_MASK  0x /* 16-bits resolution */
> +#define SANDBOX_ADC_CHANNELS   4
> +#define SANDBOX_ADC_CHANNEL0_DATA  0x0
> +#define SANDBOX_ADC_CHANNEL1_DATA  0x1000
> +#define SANDBOX_ADC_CHANNEL2_DATA  0x2000
> +#define SANDBOX_ADC_CHANNEL3_DATA  0x3000
> +
> +enum sandbox_adc_mode {
> +   SANDBOX_ADC_MODE_SINGLE_CHANNEL = 0,
> +   SANDBOX_ADC_MODE_MULTI_CHANNEL,
> +};
> +
> +enum sandbox_adc_status {
> +   SANDBOX_ADC_INACTIVE = 0,
> +   SANDBOX_ADC_ACTIVE,
> +};
> +
> +#define SANDBOX_ADC_VSS_VALUE  0
> +
> +#endif
> --
> 1.9.1
>
> ___
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> U-Boot@lists.denx.de 
> http://lists.denx.de/mailman/listinfo/u-boot
>

applied to u-boot-samsung.

Thanks,
Minkyu Kang.


-- 
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Minkyu Kang.
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[U-Boot] [PATCH][v3] armv8: ls2085a: Add workaround of errata A009635

[Prabhakar Kushwaha]

If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.

Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.

Signed-off-by: Prabhakar Kushwaha 
---
Changes for v2: Updated description
Changes for v3: Added README and comments

 arch/arm/cpu/armv8/fsl-layerscape/README.lsch3| 21 +++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  6 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 43 +++
 arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 +
 arch/arm/include/asm/arch-fsl-layerscape/soc.h|  3 ++
 5 files changed, 82 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3 
b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
index d1f92c4..baa80b7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
+++ b/arch/arm/cpu/armv8/fsl-layerscape/README.lsch3
@@ -272,3 +272,24 @@ b) fsl_mc start aiop [FW_addr] - Start AIOP
 c) fsl_mc apply DPL [DPL_addr] - Apply DPL file
 d) No DPMACs availabe for use in u-boot
 Please note actual AIOP start will happen during DPL parsing of Management 
complex
+
+
+Errata A009635
+---
+If the core runs at higher than x3 speed of the platform, there is
+possiblity about sev instruction to getting missed by other cores.
+This is because of SoC Run Control block may not able to sample
+the EVENTI(Sev) signals.
+
+Workaround: Configure Run Control and EPU to periodically send out EVENTI 
signals to
+wake up A57 cores
+
+Errata workaround uses Env variable "a009635_interval_val". It uses decimal
+value.
+- Default value of env variable is platform clock (MHz)
+
+- User can modify default value by updating the env variable
+  setenv a009635_interval_val 600; saveenv;
+  It configure platform clock as 600 MHz
+
+- Env variable as 0 signifies no workaround
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 0cb0afa..dbb12c2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -484,7 +484,13 @@ int arch_early_init_r(void)
 {
 #ifdef CONFIG_MP
int rv = 1;
+#endif
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+   erratum_a009635();
+#endif
 
+#ifdef CONFIG_MP
rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 637853d..34f9a94 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -9,10 +9,53 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_LS2085A
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
+#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
+
+static unsigned long get_internval_val_mhz(void)
+{
+   char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
+   /*
+*  interval is the number of platform cycles(MHz) between
+*  wake up events generated by EPU.
+*/
+   ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
+
+   if (interval)
+   interval_mhz = simple_strtoul(interval, NULL, 10);
+
+   return interval_mhz;
+}
+
+void erratum_a009635(void)
+{
+   u32 val;
+   unsigned long interval_mhz = get_internval_val_mhz();
+
+   if (!interval_mhz)
+   return;
+
+   val = in_le32(DCSR_CGACRE5);
+   writel(val | 0x0200, DCSR_CGACRE5);
+
+   val = in_le32(EPU_EPCMPR5);
+   writel(interval_mhz, EPU_EPCMPR5);
+   val = in_le32(EPU_EPCCR5);
+   writel(val | 0x8282, EPU_EPCCR5);
+   val = in_le32(EPU_EPSMCR5);
+   writel(val | 0x002f, EPU_EPSMCR5);
+   val = in_le32(EPU_EPECR5);
+   writel(val | 0x2000, EPU_EPECR5);
+   val = in_le32(EPU_EPGCR);
+   writel(val | 0x8000, EPU_EPGCR);
+}
+#endif
+
 static void erratum_a008751(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008751
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..c7169ab 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -84,11 +84,20 @@
 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
 
+#define DCSR_CGACRE5   0x700070914ULL
+#define EPU_EPCMPR50x700060914ULL
+#define EPU_EPCCR5 0x700060814ULL
+#define EPU_EPSMCR50x700060228ULL
+#define EPU_EPECR5 0x700060314ULL
+#define EPU_EPCTR5 0x700060a14ULL
+#define EPU_EPGCR  0x70006ULL
+
 #define CONFIG_SYS_FSL_ERRATUM_A008336
 #define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ER

Re: [U-Boot] [PATCH v3 3/5] ARM: omap-common: Add standard access for board description EEPROM

[Lokesh Vutla]

On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> From: Lokesh Vutla 
> 
> Several TI EVMs have EEPROM that can contain board description information
> such as revision, DDR definition, serial number, etc. In just about all
> cases, these EEPROM are on the I2C bus and provides us the opportunity
> to centralize the generic operations involved.
> 
> The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
> AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
> However, DRA-7* EVMs, OMAP4SDP use a modified format.
> 
> We hence introduce logic which is generic between these platforms
> without enforcing any specific format. This allows the boards to use the
> relevant format for operations that they might choose.
> 
> This module will compile for all TI SoC based boards when I2C is enabled,
> even non-TI boards that do not have the EEPROM. If the functions are not
> used, they will not be linked in.
> 
> It is important to note that this logic is fundamental to the board
> configuration process such as DDR configuration which is needed in
> SPL, hence cannot be part of the standard u-boot driver model (which
> is available later in the process). Hence, to aid efficiency, the
> eeprom contents are copied over to SRAM scratchpad memory area at the
> first invocation to retrieve data.
> 
> The follow on patches introduce the use of this library for AM57x
> platform support. AM335x/AM43xx cleanups need to first ensure usage of
> omap_common prior to switch over to this generic solution.
> 
> Signed-off-by: Lokesh Vutla 
> Signed-off-by: Steve Kipisz 
> ---
> v3 Based on:
>  master  83bf0057 arm: at91: reworked meesc board support
> 
> Changes in v3 (since v2):
>  - Create a new directory board/ti/common for code common to TI board
>  - Move the EEPROM code to the new directory
>  - Move the inline code that access the EEPROM data from omap_common.h
>to new files in the common directory
> 
> v2:  http://marc.info/?t=14465534481&r=1&w=2
>(mailing list squashed original submission)
> 
> Changes in v2:
>  - New Patch
> 
>  arch/arm/include/asm/omap_common.h |   5 +-
>  board/ti/am57xx/Makefile   |   2 +
>  board/ti/common/board.c|  54 ++
>  board/ti/common/board.h| 117 +
>  board/ti/common/ti-i2c-eeprom.c| 148 
> +
>  5 files changed, 325 insertions(+), 1 deletion(-)
>  create mode 100644 board/ti/common/board.c
>  create mode 100644 board/ti/common/board.h
>  create mode 100644 board/ti/common/ti-i2c-eeprom.c
> 
> diff --git a/arch/arm/include/asm/omap_common.h 
> b/arch/arm/include/asm/omap_common.h
> index d773b0430ad4..f6d929b15e82 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -713,7 +713,9 @@ static inline u8 is_dra72x(void)
>  #define OMAP_SRAM_SCRATCH_VCORES_PTR(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
>  #define OMAP_SRAM_SCRATCH_SYS_CTRL   (SRAM_SCRATCH_SPACE_ADDR + 0x20)
>  #define OMAP_SRAM_SCRATCH_BOOT_PARAMS(SRAM_SCRATCH_SPACE_ADDR + 0x24)
> -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
> +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
> +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
> +#define OMAP_SRAM_SCRATCH_SPACE_END  (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
>  
>  /* Boot parameters */
>  #define DEVICE_DATA_OFFSET   0x18
> @@ -728,4 +730,5 @@ static inline u8 is_dra72x(void)
>  u32 omap_sys_boot_device(void);
>  #endif
>  
> +
>  #endif /* _OMAP_COMMON_H_ */
> diff --git a/board/ti/am57xx/Makefile b/board/ti/am57xx/Makefile
> index 5cd6873f5e97..9d85d31b2cf1 100644
> --- a/board/ti/am57xx/Makefile
> +++ b/board/ti/am57xx/Makefile
> @@ -6,3 +6,5 @@
>  #
>  
>  obj-y:= board.o
> +obj-y+= ../common/board.o
> +obj-${CONFIG_I2C} += ../common/ti-i2c-eeprom.o
> diff --git a/board/ti/common/board.c b/board/ti/common/board.c
> new file mode 100644
> index ..1c02e44916f0
> --- /dev/null
> +++ b/board/ti/common/board.c
> @@ -0,0 +1,54 @@
> +/*
> + * board.c
> + *
> + * Common board functions for TI AM based boards.
> + *
> + * Copyright (C) 2015, Texas Instruments Incorporated - http://www.ti.com
> + *
> + * Author: Steven Kipisz 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +
> +#include "board.h"
> +
> +/**
> + * board_am_is() - Generic Board detection logic
> + * @name_tag:Tag used in eeprom for the board
> + *
> + * Return: false if board information does not match OR eeprom was'nt read.
> + *  true otherwise
> + */
> +bool board_am_is(char *name_tag)
> +{
> + struct ti_am_eeprom *ep = TI_AM_EEPROM_DATA;
> +
> + if (ep->header != TI_EEPROM_HEADER_MAGIC)
> + return false;
> + return !strncmp(ep->name, name_tag, TI_EEPROM_HDR_NAME_LEN);
> +}
> +
> +/**
> + * board_am_rev_is() - Compare board revi

Re: [U-Boot] [PATCH v3 4/5] ARM: OMAP4/5: Add generic board detection hook

[Lokesh Vutla]

On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Many TI EVMs have capability to store relevant board information
> such as DDR description in EEPROM. Further many pad configuration
> variations can occur as part of revision changes in the platform.
> In-order to support these at runtime, we for a board detection hook
> which is available for override from board files that may desire to do
> so.
> 
> NOTE: All TI EVMs are capable of detecting board information based on
> early clocks that are configured. However, in case of additional needs
> this can be achieved within the override logic from within the board
> file.

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> 
> Signed-off-by: Steve Kipisz 
> Reviewed-by: Tom Rini 
> ---
> v3 Based on:
>  master 83bf0057 arm: at91: reworked meesc board support
> 
> Changes in v3 (since v2):
>  - No changes
> 
> v2:  http://marc.info/?t=14465534466&r=1&w=2
>   (mailing list squashed original submission)
> 
> Changes in v2:
>  - New patch
> 
>  arch/arm/cpu/armv7/omap-common/hwinit-common.c | 11 +++
>  arch/arm/include/asm/arch-omap4/sys_proto.h|  1 +
>  arch/arm/include/asm/arch-omap5/sys_proto.h|  1 +
>  3 files changed, 13 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c 
> b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> index 91f2dead364b..9e9376d0e6e6 100644
> --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> @@ -97,6 +97,16 @@ int arch_cpu_init(void)
>  }
>  #endif /* CONFIG_ARCH_CPU_INIT */
>  
> +/**
> + * do_board_detect() - Detect board description
> + *
> + * Function to detect board description. This is expected to be
> + * overridden in the SoC family board file where desired.
> + */
> +void __weak do_board_detect(void)
> +{
> +}
> +
>  /*
>   * Routine: s_init
>   * Description: Does early system init of watchdog, muxing,  andclocks
> @@ -128,6 +138,7 @@ void s_init(void)
>   do_io_settings();
>  #endif
>   setup_early_clocks();
> + do_board_detect();
>   prcm_init();
>  }
>  
> diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
> b/arch/arm/include/asm/arch-omap4/sys_proto.h
> index 26e9a194f036..fbb52093c65a 100644
> --- a/arch/arm/include/asm/arch-omap4/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
> @@ -39,6 +39,7 @@ u32 wait_on_value(u32, u32, void *, u32);
>  void sdelay(unsigned long);
>  void setup_early_clocks(void);
>  void prcm_init(void);
> +void do_board_detect(void);
>  void bypass_dpll(u32 const base);
>  void freq_update_core(void);
>  u32 get_sys_clk_freq(void);
> diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
> b/arch/arm/include/asm/arch-omap5/sys_proto.h
> index 18902628739b..23a33cb233bb 100644
> --- a/arch/arm/include/asm/arch-omap5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
> @@ -50,6 +50,7 @@ u32 wait_on_value(u32, u32, void *, u32);
>  void sdelay(unsigned long);
>  void setup_early_clocks(void);
>  void prcm_init(void);
> +void do_board_detect(void);
>  void bypass_dpll(u32 const base);
>  void freq_update_core(void);
>  u32 get_sys_clk_freq(void);
> 
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Re: [U-Boot] [PATCH v3 2/5] ARM: OMAP4/5: Centralize gpi2c_init

[Lokesh Vutla]

On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Centralize gpi2c_init into omap_common from the sys_proto header so
> that the information can be reused across SoCs.

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh
> 
> Signed-off-by: Steve Kipisz 
> Reviewed-by: Tom Rini 
> ---
> v3 Based on:
>  master 83bf0057 arm: at91: reworked meesc board support
> 
> Changes in v3 (since v2):
>  - No changes
> 
> v2:  http://marc.info/?t=14465534467&r=1&w=2
>(mailing list squashed original submission)
> 
> Changes in v2:
>  - New Patch
> 
>  arch/arm/include/asm/arch-omap4/sys_proto.h | 1 -
>  arch/arm/include/asm/arch-omap5/sys_proto.h | 1 -
>  arch/arm/include/asm/omap_common.h  | 3 +++
>  3 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
> b/arch/arm/include/asm/arch-omap4/sys_proto.h
> index 71e3d776aa0d..26e9a194f036 100644
> --- a/arch/arm/include/asm/arch-omap4/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
> @@ -51,7 +51,6 @@ void save_omap_boot_params(void);
>  void init_omap_revision(void);
>  void do_io_settings(void);
>  void sri2c_init(void);
> -void gpi2c_init(void);
>  int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
>  u32 warm_reset(void);
>  void force_emif_self_refresh(void);
> diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
> b/arch/arm/include/asm/arch-omap5/sys_proto.h
> index b9e09e7c52a8..18902628739b 100644
> --- a/arch/arm/include/asm/arch-omap5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
> @@ -62,7 +62,6 @@ void save_omap_boot_params(void);
>  void init_omap_revision(void);
>  void do_io_settings(void);
>  void sri2c_init(void);
> -void gpi2c_init(void);
>  int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
>  u32 warm_reset(void);
>  void force_emif_self_refresh(void);
> diff --git a/arch/arm/include/asm/omap_common.h 
> b/arch/arm/include/asm/omap_common.h
> index d7b81c101b79..d773b0430ad4 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -617,6 +617,9 @@ void disable_edma3_clocks(void);
>  
>  void omap_die_id(unsigned int *die_id);
>  
> +/* Initialize general purpose I2C(0) on the SoC */
> +void gpi2c_init(void);
> +
>  /* ABB */
>  #define OMAP_ABB_NOMINAL_OPP 0
>  #define OMAP_ABB_FAST_OPP1
> 
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Re: [U-Boot] [PATCH v3 1/5] ARM: OMAP4/5: Centralize early clock initialization

[Lokesh Vutla]

On Thursday 05 November 2015 03:30 AM, Steve Kipisz wrote:
> Early clock initialization is currently done in two stages for OMAP4/5
> SoCs. The first stage is the initialization of console clocks and
> then we initialize basic clocks for functionality necessary for SoC
> initialization and basic board functionality.
> 
> By splitting up prcm_init and centralizing this clock initialization,
> we setup the code for follow on patches that can do board specific
> initialization such as board detection which will depend on these
> basic clocks.
> 
> As part of this change, since the early clock initialization
> is centralized, we no longer need to expose the console clock
> initialization.
> 
> NOTE: we change the sequence slightly by initializing console clocks
> timer after the io settings are complete, but this is not expected
> to have any functioanlity impact since we setup the basic IO drive
> strength initialization as part of do_io_settings

Reviewed-by: Lokesh Vutla 

Thanks and regards,
Lokesh

> 
> Signed-off-by: Steve Kipisz 
> Reviewed-by: Tom Rini  ---
> v3 Based on:
>  master  83bf0057 arm: at91: reworked meesc board support
> 
> Changes in v3 (since v2):
>  - Remove SPL-only build of setup_clocks_for_console since it needs
>to be built in u-boot for NOR boot
>  - Move setup_clocks_for_console from top of setup_early_clocks to inside
>the switch statement.
> 
> v2:  http://marc.info/?t=14465536301&r=1&w=2
>   (mailing list squashed original submission)
> 
> Changes in v2:
>  - New patch
> 
>  arch/arm/cpu/armv7/omap-common/clocks-common.c | 21 +++--
>  arch/arm/cpu/armv7/omap-common/hwinit-common.c |  3 +--
>  arch/arm/include/asm/arch-omap4/sys_proto.h|  2 +-
>  arch/arm/include/asm/arch-omap5/sys_proto.h|  2 +-
>  4 files changed, 22 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
> b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> index e28b79568d1d..367d224361be 100644
> --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
> @@ -769,7 +769,7 @@ void lock_dpll(u32 const base)
>   wait_for_lock(base);
>  }
>  
> -void setup_clocks_for_console(void)
> +static void setup_clocks_for_console(void)
>  {
>   /* Do not add any spl_debug prints in this function */
>   clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
> @@ -853,14 +853,31 @@ void do_disable_clocks(u32 const *clk_domains,
>   disable_clock_domain(clk_domains[i]);
>  }
>  
> -void prcm_init(void)
> +/**
> + * setup_early_clocks() - Setup early clocks needed for SoC
> + *
> + * Setup clocks for console, SPL basic initialization clocks and initialize
> + * the timer. This is invoked prior prcm_init.
> + */
> +void setup_early_clocks(void)
>  {
>   switch (omap_hw_init_context()) {
>   case OMAP_INIT_CONTEXT_SPL:
>   case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
>   case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
> + setup_clocks_for_console();
>   enable_basic_clocks();
>   timer_init();
> + /* Fall through */
> + }
> +}
> +
> +void prcm_init(void)
> +{
> + switch (omap_hw_init_context()) {
> + case OMAP_INIT_CONTEXT_SPL:
> + case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
> + case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
>   scale_vcores(*omap_vcores);
>   setup_dplls();
>   setup_warmreset_time();
> diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c 
> b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> index 80794f9c611a..91f2dead364b 100644
> --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
> @@ -125,10 +125,9 @@ void s_init(void)
>   set_mux_conf_regs();
>  #ifdef CONFIG_SPL_BUILD
>   srcomp_enable();
> - setup_clocks_for_console();
> -
>   do_io_settings();
>  #endif
> + setup_early_clocks();
>   prcm_init();
>  }
>  
> diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
> b/arch/arm/include/asm/arch-omap4/sys_proto.h
> index f30f86539130..71e3d776aa0d 100644
> --- a/arch/arm/include/asm/arch-omap4/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
> @@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const 
> *array, int size);
>  void set_muxconf_regs_essential(void);
>  u32 wait_on_value(u32, u32, void *, u32);
>  void sdelay(unsigned long);
> -void setup_clocks_for_console(void);
> +void setup_early_clocks(void);
>  void prcm_init(void);
>  void bypass_dpll(u32 const base);
>  void freq_update_core(void);
> diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
> b/arch/arm/include/asm/arch-omap5/sys_proto.h
> index 7fcb78389403..b9e09e7c52a8 100644
> --- a/arch/arm/include/asm/arch-omap5/sys_proto.h
> +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
> @@ -48,7 +48,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const 

Re: [U-Boot] [PATCH 2/2] nios2: trim CONFIG_SYS_MEMTEST_END

[Thomas Chou]

Hi Chin Liang,

On 2015年11月04日 22:27, Chin Liang See wrote:

+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \
+CONFIG_ENV_SIZE - \
+CONFIG_SYS_MALLOC_LEN -\


Since CONFIG_ENV_IS_IN_FLASH, I believe we can take out the
CONFIG_ENV_SIZE here.



This comes from a very old macro in common.h,

#if defined(CONFIG_ENV_IS_EMBEDDED)
#define TOTAL_MALLOC_LENCONFIG_SYS_MALLOC_LEN
#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
	(CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) 
) || \

  defined(CONFIG_ENV_IS_IN_NVRAM)
#define TOTAL_MALLOC_LEN(CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE)
#else
#define TOTAL_MALLOC_LENCONFIG_SYS_MALLOC_LEN
#endif

The TOTAL_MALLOC_LEN is (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) for 
nios2. I think the macro might need fix though.


Best regards,
Thomas
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Re: [U-Boot] [PATCH] usb:ci_udc: Remove ULPI setting for i.MX OTG controller

[Marek Vasut]

On Thursday, November 05, 2015 at 04:17:38 AM, Ye.Li wrote:
> All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI
> interface. Set to ULPI is not correct, even the controller will reject
> this
> setting in PORTSC register.
> 
> Signed-off-by: Ye.Li 
> ---
>  drivers/usb/gadget/ci_udc.c |   12 
>  1 files changed, 0 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
> index 1ba5054..cb35982 100644
> --- a/drivers/usb/gadget/ci_udc.c
> +++ b/drivers/usb/gadget/ci_udc.c
> @@ -1018,18 +1018,6 @@ int usb_gadget_register_driver(struct
> usb_gadget_driver *driver) return ret;
> 
>   ret = ci_udc_probe();

You're now dropping the error handling for this function, that's really not
good, so I cannot accept the patch. But the current error handling looks
totally broken. So the solution I would propose here is to fix the error
handling for ci_udc_probe() here instead of outright removing the code. What
do you think ?

> -#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
> - /*
> -  * FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
> -  * HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
> -  */
> - if (!ret) {
> - struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
> -
> - /* select ULPI phy */
> - writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
> - }
> -#endif
> 
>   ret = driver->bind(&controller.gadget);
>   if (ret) {

Best regards,
Marek Vasut
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Re: [U-Boot] [Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT register access

[Bin Meng]

+Simon,

Hi,

On Thu, Nov 5, 2015 at 7:45 AM, Scott Wood  wrote:
> On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
>> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
>> index 4cee038..8471678 100644
>> --- a/drivers/pci/pcie_layerscape.c
>> +++ b/drivers/pci/pcie_layerscape.c
>> @@ -13,6 +13,7 @@
>>  #include 
>>  #ifdef CONFIG_FSL_LAYERSCAPE
>>  #include 
>> +#include 
>>  #endif
>>
>>  #ifndef CONFIG_SYS_PCI_MEMORY_BUS
>> @@ -57,11 +58,6 @@
>>  #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
>>  #define PCIE_ATU_UPPER_TARGET0x91C
>>
>> -/* LUT registers */
>> -#define PCIE_LUT_BASE0x8
>> -#define PCIE_LUT_LCTRL0  0x7F8
>> -#define PCIE_LUT_DBG 0x7FC
>> -
>>  #define PCIE_DBI_RO_WR_EN0x8bc
>>
>>  #define PCIE_LINK_CAP0x7c
>> @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
>>
>>   return 1;
>>  }
>> -#else
>> +#elif defined(CONFIG_FSL_LAYERSCAPE)
>>  static int ls_pcie_link_state(struct ls_pcie *pcie)
>>  {
>>   u32 state;
>>
>> - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
>> + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
>>   LTSSM_STATE_MASK;
>>   if (state < LTSSM_PCIE_L0) {
>>   debug("PCIe link error. LTSSM=0x%02x.\n", state);
>> @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie,
>> struct ls_pcie_info *info)
>>
>>   for (pf = 0; pf < PCIE_PF_NUM; pf++) {
>>   for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
>> +#ifdef CONFIG_FSL_LAYERSCAPE
>>   writel(PCIE_LCTRL0_VAL(pf, vf),
>>  pcie->dbi + PCIE_LUT_BASE +
>>  PCIE_LUT_LCTRL0);
>> +#endif
>
> It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file
> whose name suggests is layerscape-specific.  What chips use this file that
> are not CONFIG_FSL_LAYERSCAPE?
>
> -Scott

Can we start converting the driver to use DM PCI? We should not
continue using legacy PCI codes since right now DM PCI is in a good
shape. These #ifdef in the driver should really go into device tree as
needed.

Regards,
Bin
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Re: [U-Boot] [PATCH v3 3/5] ARM: omap-common: Add standard access for board description EEPROM

[Nishanth Menon]

On 11/04/2015 05:43 PM, Nishanth Menon wrote:
[...]
>> index 5cd6873f5e97..9d85d31b2cf1 100644
>> --- a/board/ti/am57xx/Makefile
>> +++ b/board/ti/am57xx/Makefile
>> @@ -6,3 +6,5 @@
>>  #
>>  
>>  obj-y   := board.o
>> +obj-y   += ../common/board.o
> 

One final comment on the ../common/board.o:

all we need is:
board/ti/common/Makefile

which contains:
obj-${CONFIG_I2C} += board-detect.o

That should build it for all TI platforms and then optimize link time
using __maybe_unused.

This also removes the cruft of including specific headers since root
Makefile already will enable flag HAVE_VENDOR_COMMON_LIB if a Makefile
exists in board/{vendor}/common/ directory, and will build accordingly.

This makes sense now since the entire series claims commonality and
should allow us to remove stuff from am335x/437x following this series
by just using the APIs.


-- 
Regards,
Nishanth Menon
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Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Marek Vasut]

On Thursday, November 05, 2015 at 05:26:25 AM, Thomas Chou wrote:
> HI Chin Liang,
> 
> On 2015年11月05日 11:05, Chin Liang See wrote:
> > I notice you are writing in word style which might have concern in
> > performance. As the burst count can go up to 64, we can write larger
> > data through memcpy. This will avoid redundancy of data header
> > (opcode + address + dummy).
>  
>  You cannot do that, memcpy works on memory while write*() operators
>  work on I/O. You should use readsl() and friends then.
> >>> 
> >>> Actually I am thinking to take advantage the cache fill and dump. But
> >>> after rethinking, this might limit some of the use case as we want the
> >>> driver to support NIOS II without cache. With that, just ignore this
> >>> comment for now.
> >> 
> >> I'm not sure I want to ask for details here. I think we're reading data
> >> from some sort of IO device, so we should just use readl() or readsl()
> >> to read them out (and write*() for the other direction). I don't think
> >> cache operations can be involved in any way. Correct me if I'm wrong
> >> please.
> > 
> > Sure, I can share more. Since the read can support up to burst of 64
> > byte, we can use the a cache fill method which eventually trigger a read
> > of 32 byte (which is size of a cache line) to the Quad SPI controller.
> > To ensure we don't read from old data, we need to invalidate that cache
> > line (through address). By doing this, we can gain better performance as
> > we are reading 32 bytes of data instead 4 per transaction.
> > 
> >>> But your comment lead to the fact that the read part is now using
> >>> memcpy. Thomas needs to fix that to use the readl :)
> >> 
> >> Uhm, I don't think I understand this remark, sorry. I never suggested to
> >> use memcpy() in this entire thread, did I ?
> > 
> > Nope, but this trigger me that we need to do the same for read. The
> > memcpy might lead to the driver reading old data that stay on cache
> > instead from controller. Another way to get rid of this is invalidate
> > the cache.
> 
> Thank for the reminding about the read part. I should not use memcpy()
> indeed.
> 
> Maybe we could pull the memcpy_fromio() and memcpy_toio() or the
> asm-generic/io.h from Linux kernel?
> 
> For i/o access, we bypass the cache for u-boot nios2 with ioremap() or
> map_physaddr(uncached). So no worries or advantage about cache.

Oh, you need those memcpy_{from,to}io() for this hardware? In that case,
go ahead and either implement them or use them :) Now I understand why
you cannot use the reads*() function.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Thomas Chou]

HI Chin Liang,

On 2015年11月05日 11:05, Chin Liang See wrote:

I notice you are writing in word style which might have concern in
performance. As the burst count can go up to 64, we can write larger
data through memcpy. This will avoid redundancy of data header (opcode
+ address + dummy).


You cannot do that, memcpy works on memory while write*() operators work
on I/O. You should use readsl() and friends then.


Actually I am thinking to take advantage the cache fill and dump. But
after rethinking, this might limit some of the use case as we want the
driver to support NIOS II without cache. With that, just ignore this
comment for now.


I'm not sure I want to ask for details here. I think we're reading data from
some sort of IO device, so we should just use readl() or readsl() to read
them out (and write*() for the other direction). I don't think cache operations
can be involved in any way. Correct me if I'm wrong please.



Sure, I can share more. Since the read can support up to burst of 64
byte, we can use the a cache fill method which eventually trigger a read
of 32 byte (which is size of a cache line) to the Quad SPI controller.
To ensure we don't read from old data, we need to invalidate that cache
line (through address). By doing this, we can gain better performance as
we are reading 32 bytes of data instead 4 per transaction.


But your comment lead to the fact that the read part is now using
memcpy. Thomas needs to fix that to use the readl :)


Uhm, I don't think I understand this remark, sorry. I never suggested to use
memcpy() in this entire thread, did I ?



Nope, but this trigger me that we need to do the same for read. The
memcpy might lead to the driver reading old data that stay on cache
instead from controller. Another way to get rid of this is invalidate
the cache.


Thank for the reminding about the read part. I should not use memcpy() 
indeed.


Maybe we could pull the memcpy_fromio() and memcpy_toio() or the 
asm-generic/io.h from Linux kernel?


For i/o access, we bypass the cache for u-boot nios2 with ioremap() or 
map_physaddr(uncached). So no worries or advantage about cache.


Best regards,
Thomas
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Re: [U-Boot] [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635

[Kushwaha Prabhakar]

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05, 2015 9:38 AM
> To: Kushwaha Prabhakar-B32579 ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
> 
> 
> 
> On 11/04/2015 07:58 PM, Kushwaha Prabhakar-B32579 wrote:
> >
> >> -Original Message-
> >> From: York Sun [mailto:york...@freescale.com]
> >> Sent: Thursday, November 05, 2015 12:27 AM
> >> To: Kushwaha Prabhakar-B32579 ; u-
> >> b...@lists.denx.de
> >> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata
> >> A009635
> >>
> >>
> >>
> >> On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
> >>> If the core runs at higher than x3 speed of the platform, there is
> >>> possiblity about sev instruction to getting missed by other cores.
> >>> This is because of SoC Run Control block may not able to sample the
> >>> EVENTI(Sev) signals.
> >>>
> >>> Configure Run Control and EPU to periodically send out EVENTI
> >>> signals to wake up A57 cores.
> >>>
> >>> Signed-off-by: Prabhakar Kushwaha 
> >>> ---
> >>> Chages for v2: Updated description
> >>>
> >>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  6 
> >>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 39
> >> +++
> >>>  arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 ++
> >>>  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  3 ++
> >>>  4 files changed, 57 insertions(+)
> >>>
> >>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >>> index 0cb0afa..dbb12c2 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> >>> @@ -484,7 +484,13 @@ int arch_early_init_r(void)  {  #ifdef CONFIG_MP
> >>>   int rv = 1;
> >>> +#endif
> >>> +
> >>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> >>> + erratum_a009635();
> >>> +#endif
> >>>
> >>> +#ifdef CONFIG_MP
> >>>   rv = fsl_layerscape_wake_seconday_cores();
> >>>   if (rv)
> >>>   printf("Did not wake secondary cores\n"); diff --git
> >>> a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> index 637853d..e8cdb10 100644
> >>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >>> @@ -9,10 +9,49 @@
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>> +#include 
> >>>
> >>>  DECLARE_GLOBAL_DATA_PTR;
> >>>
> >>>  #ifdef CONFIG_LS2085A
> >>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> >>> +#define PLATFORM_CYCLE_ENV_VAR   "a009635_interval_val"
> >>> +
> >>> +static unsigned long get_internval_val_mhz(void) {
> >>> + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
> >>
> >> Why do you need a variable to override the calculation?
> >>
> >
> > Following needs to be supported as part of errata workaround 1.
> > Ability to modify platform clock value to increase time interval 2.
> > Disable workaround in platform clock 0
> >
> > As per Errata workaround,
> >  "For  value above,  it is the number of platform cycles between
> wake up events generated by EPU.  For example:
> > A typical value is 1 microsecond.  If the platform frequency is 500MHz, each
> cycle is 2ns. interval = 1us/2ns=500=0x1F4."
> 
> This is taken care of by the formula. Is there any need to adjust the time
> interval? If you do, you are risking of running too fast or too slow. 

Yes, customer may like to increase or decrease the time interval to fine tune 
the system behavior. 

> If setting
> the variable as 0, does it have the same effect as not running this
> workaround?

Yes, setting 0 == Not running WA. I verified it. 

> If this is a debug technique, please remove if not required by the
> workaround.

This problem occur when core clock is > 2.5.x of platform clock.
If anyone using core clock < 2.5x of platform clock, this workaround is not 
required. 

> If you really want to support override, please add a comment inline and in
> commit message.

OK


> 
> >
> >>
> >>> + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
> >>
> >> Please add a comment here to explain what the interval does and why
> >> it is calculated this way.
> >>
> >
> > Sure,
> 
> York

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[U-Boot] [PATCH] board/ls2085qds: Fix typo in README for QSGMII riser card

[Prabhakar Kushwaha]

DPMACx to PHY mapping for SGMII is mentioned as QSGMII.

So fix typo in README for QSGMII rise card.

Signed-off-by: Prabhakar Kushwaha 
---
 board/freescale/ls2085aqds/README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/freescale/ls2085aqds/README 
b/board/freescale/ls2085aqds/README
index e4a6f69..b3ed854 100644
--- a/board/freescale/ls2085aqds/README
+++ b/board/freescale/ls2085aqds/README
@@ -172,7 +172,7 @@ Supported PHY addresses during SGMII:
 #define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
 #define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
 
-Mapping DPMACx to PHY during QSGMII
+Mapping DPMACx to PHY during SGMII
 DPMAC1 -> PHY1-P0
 DPMAC2 -> PHY2-P0
 DPMAC3 -> PHY3-P0
-- 
1.9.1


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Re: [U-Boot] [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635

[York Sun]

On 11/04/2015 07:58 PM, Kushwaha Prabhakar-B32579 wrote:
> 
>> -Original Message-
>> From: York Sun [mailto:york...@freescale.com]
>> Sent: Thursday, November 05, 2015 12:27 AM
>> To: Kushwaha Prabhakar-B32579 ; u-
>> b...@lists.denx.de
>> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
>>
>>
>>
>> On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
>>> If the core runs at higher than x3 speed of the platform, there is
>>> possiblity about sev instruction to getting missed by other cores.
>>> This is because of SoC Run Control block may not able to sample the
>>> EVENTI(Sev) signals.
>>>
>>> Configure Run Control and EPU to periodically send out EVENTI signals
>>> to wake up A57 cores.
>>>
>>> Signed-off-by: Prabhakar Kushwaha 
>>> ---
>>> Chages for v2: Updated description
>>>
>>>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  6 
>>>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 39
>> +++
>>>  arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 ++
>>>  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  3 ++
>>>  4 files changed, 57 insertions(+)
>>>
>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>>> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>>> index 0cb0afa..dbb12c2 100644
>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
>>> @@ -484,7 +484,13 @@ int arch_early_init_r(void)  {  #ifdef CONFIG_MP
>>> int rv = 1;
>>> +#endif
>>> +
>>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
>>> +   erratum_a009635();
>>> +#endif
>>>
>>> +#ifdef CONFIG_MP
>>> rv = fsl_layerscape_wake_seconday_cores();
>>> if (rv)
>>> printf("Did not wake secondary cores\n");
>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> index 637853d..e8cdb10 100644
>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>>> @@ -9,10 +9,49 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>>
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>
>>>  #ifdef CONFIG_LS2085A
>>> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
>>> +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
>>> +
>>> +static unsigned long get_internval_val_mhz(void)
>>> +{
>>> +   char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
>>
>> Why do you need a variable to override the calculation?
>>
> 
> Following needs to be supported as part of errata workaround
> 1. Ability to modify platform clock value to increase time interval
> 2. Disable workaround in platform clock 0
> 
> As per Errata workaround, 
>  "For  value above,  it is the number of platform cycles between 
> wake up events generated by EPU.  For example: 
> A typical value is 1 microsecond.  If the platform frequency is 500MHz, each 
> cycle is 2ns. interval = 1us/2ns=500=0x1F4."

This is taken care of by the formula. Is there any need to adjust the time
interval? If you do, you are risking of running too fast or too slow. If setting
the variable as 0, does it have the same effect as not running this workaround?
If this is a debug technique, please remove if not required by the workaround.
If you really want to support override, please add a comment inline and in
commit message.

> 
>>
>>> +   ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
>>
>> Please add a comment here to explain what the interval does and why it is
>> calculated this way.
>>
> 
> Sure, 

York

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Re: [U-Boot] [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635

[Kushwaha Prabhakar]

> -Original Message-
> From: York Sun [mailto:york...@freescale.com]
> Sent: Thursday, November 05, 2015 12:27 AM
> To: Kushwaha Prabhakar-B32579 ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635
> 
> 
> 
> On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
> > If the core runs at higher than x3 speed of the platform, there is
> > possiblity about sev instruction to getting missed by other cores.
> > This is because of SoC Run Control block may not able to sample the
> > EVENTI(Sev) signals.
> >
> > Configure Run Control and EPU to periodically send out EVENTI signals
> > to wake up A57 cores.
> >
> > Signed-off-by: Prabhakar Kushwaha 
> > ---
> > Chages for v2: Updated description
> >
> >  arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  6 
> >  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 39
> +++
> >  arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 ++
> >  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  3 ++
> >  4 files changed, 57 insertions(+)
> >
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > index 0cb0afa..dbb12c2 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> > @@ -484,7 +484,13 @@ int arch_early_init_r(void)  {  #ifdef CONFIG_MP
> > int rv = 1;
> > +#endif
> > +
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> > +   erratum_a009635();
> > +#endif
> >
> > +#ifdef CONFIG_MP
> > rv = fsl_layerscape_wake_seconday_cores();
> > if (rv)
> > printf("Did not wake secondary cores\n");
> > diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > index 637853d..e8cdb10 100644
> > --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> > @@ -9,10 +9,49 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> >
> >  #ifdef CONFIG_LS2085A
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> > +#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
> > +
> > +static unsigned long get_internval_val_mhz(void)
> > +{
> > +   char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
> 
> Why do you need a variable to override the calculation?
> 

Following needs to be supported as part of errata workaround
1. Ability to modify platform clock value to increase time interval
2. Disable workaround in platform clock 0

As per Errata workaround, 
 "For  value above,  it is the number of platform cycles between wake 
up events generated by EPU.  For example: 
A typical value is 1 microsecond.  If the platform frequency is 500MHz, each 
cycle is 2ns. interval = 1us/2ns=500=0x1F4."

> 
> > +   ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
> 
> Please add a comment here to explain what the interval does and why it is
> calculated this way.
> 

Sure, 

--PK

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[U-Boot] [PATCH] usb:ci_udc: Remove ULPI setting for i.MX OTG controller

[Ye . Li]

All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface.
Set to ULPI is not correct, even the controller will reject this
setting in PORTSC register.

Signed-off-by: Ye.Li 
---
 drivers/usb/gadget/ci_udc.c |   12 
 1 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c
index 1ba5054..cb35982 100644
--- a/drivers/usb/gadget/ci_udc.c
+++ b/drivers/usb/gadget/ci_udc.c
@@ -1018,18 +1018,6 @@ int usb_gadget_register_driver(struct usb_gadget_driver 
*driver)
return ret;
 
ret = ci_udc_probe();
-#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
-   /*
-* FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
-* HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
-*/
-   if (!ret) {
-   struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
-
-   /* select ULPI phy */
-   writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
-   }
-#endif
 
ret = driver->bind(&controller.gadget);
if (ret) {
-- 
1.7.4.1

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Re: [U-Boot] Ethernet i210 (e1000 driver) on tegra K1

[Bin Meng]

On Thu, Nov 5, 2015 at 2:54 AM, Stephen Warren  wrote:
> On 10/30/2015 05:07 AM, Ivan Mercier wrote:
>>
>> Hi,
>>
>> I'm using a ethernet controller intel i210
>> (http://www.commell.com.tw/product/Surveillance/MPX-210.htm) on my
>> nvidia tegra k1 jetson.
>
>
> (You didn't actually CC anyone involved with Tegra, so I only accidentally
> noticed this while I was looking at my mailing list folder)
>
>> I not an expert with pci, but the only way to make it working in u-boot
>> (upstream) is with the workaround below.
>>
>> E1000 is very common, so finding a critical bug in this driver seems
>> weird...
>> Do you think there is a bug in e1000.c or in tegra pci layer?
>
>
>> diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
>
>
>> @@ -5186,7 +5186,7 @@ static int _e1000_transmit(struct e1000_hw *hw,
>> void *txpacket, int length)
>>   txp = tx_base + tx_tail;
>>   tx_tail = (tx_tail + 1) % 8;
>>
>> -txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
>> +txp->buffer_addr = cpu_to_le64((unsigned long) nv_packet);
>>   txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
>>   txp->upper.data = 0;
>
>
> In order to work out what's going on, perhaps you could print out the values
> of nv_packet and virt_to_bus(hw->pdev, nv_packet).
>
> It's not terribly surprising that removing the call to virt_to_bus works,
> since IIRC U-Boot on Tegra uses the same address setup for the PCIe bus as
> for CPU physical addresses as for CPU virtual addresses.
>
> So, the question is: what is virt_to_bus() doing, and is it the right API to
> call?

virt_to_bus() is to translate cpu virtual address to pci bus physical
address. Basically two levels of translation.

>
> I see that virt_to_bus() is defined as:
>
> e1000.c:
>
> #define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))
>
> pci.h:
>
> #define pci_virt_to_mem(dev, addr) \
> pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
>
> #define pci_virt_to_bus(dev, addr, flags) \
> pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
>  (virt_to_phys(addr)), (flags))
>
> I know that the RTL8169 driver works on the same board (it's soldered down
> and attached to the other PCIe root port on the SoC). For what looks like
> the same "use case", it seems to call pci_mem_to_phys() which is:
>
> pci.h:
>
> #define pci_mem_to_phys(dev, addr) \
> pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
>
> #define pci_bus_to_phys(dev, addr, flags) \
> pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), \
> (flags))
>
> That's odd, since one of those does a phys -> bus translation and the other
> does a bus -> phys translation. That's the opposite direction, so both can't
> possibly be right. I wonder if those mapping functions are no-ops on

Indeed these address translation macros in pci.h are confusing. But
most SoC defines 1:1:1 mapping so these are not needed. The reason why
it fails on Tegra is probably due to the addresses are not 1:1:1
mapped?

> whatever architectures the e1000 driver has been used on (and hence have
> caused no issues), but fail for some reason on ARM?
>
> (The other difference is the call to virt_to_phys(), but that's a no-op on
> ARM as far as I can tell).

Regards,
Bin
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[U-Boot] [PATCH] arm: ls102xa: Update fdt_high and initrd_high for LS1021AQDS board

[Alison Wang]

As 3G/1G user/kernel memory split is used on LS1021A, the Linux kernel
fails to access the device tree blob on boot. The reason is that u-boot
relocates the device tree blob into high memory when booting the kernel
and the kernel is unable to access the blob.

To avoid this issue, fdt_high is set to the value of 0x. The
device tree blob will not get relocated and is still in low memory to
make it accessible to the kernel.

For the same reason, initrd_high is set to the value of 0x too.

This patch is to update fdt_high and initrd_high for LS1021AQDS board.

Signed-off-by: Alison Wang 
---
 include/configs/ls1021aqds.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 562e78f..489db9c 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -579,14 +579,14 @@ unsigned long get_board_ddr_clk(void);
 #ifdef CONFIG_LPUART
 #define CONFIG_EXTRA_ENV_SETTINGS   \
"bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
-   "fdt_high=0xcfff\0" \
-   "initrd_high=0xcfff\0"  \
+   "fdt_high=0x\0" \
+   "initrd_high=0x\0"  \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS  \
"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
-   "fdt_high=0xcfff\0" \
-   "initrd_high=0xcfff\0"  \
+   "fdt_high=0x\0" \
+   "initrd_high=0x\0"  \
"hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 #endif
 
-- 
2.1.0.27.g96db324

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[U-Boot] [PATCH] armv8/layerscape: Update MMU table with execute-never bits

[Alison Wang]

For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.

Signed-off-by: York Sun 
Signed-off-by: Alison Wang 
Reported-by: Zhichun Hua 
---
 arch/arm/cpu/armv8/cache_v8.c  |  4 +-
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c|  2 +-
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 79 +-
 arch/arm/include/asm/armv8/mmu.h   |  2 +-
 4 files changed, 56 insertions(+), 31 deletions(-)

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index b1ea822..8f3ca40 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-u64 memory_type, u64 share)
+u64 memory_type, u64 attribute)
 {
u64 value;
 
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
-   value |= share;
+   value |= attribute;
page_table[index] = value;
 }
 
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 0cb0afa..9d1c70f 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list,
index,
block_addr,
list->memory_type,
-   list->share);
+   list->attribute);
block_addr += block_size;
index++;
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 2903996..b4b85a8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -103,7 +103,7 @@ struct sys_mmu_table {
u64 phys_addr;
u64 size;
u64 memory_type;
-   u64 share;
+   u64 attribute;
 };
 
 struct table_info {
@@ -115,7 +115,8 @@ struct table_info {
 static const struct sys_mmu_table early_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
/* For IFC Region #1, only the first 4MB is cache-enabled */
@@ -130,16 +131,19 @@ static const struct sys_mmu_table early_mmu_table[] = {
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
  CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
 #elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
- CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
  CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@@ -152,72 +156,93 @@ static const struct sys_mmu_table early_mmu_table[] = {
 static const struct sys_mmu_table final_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
- CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+ CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+ PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
  CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
  CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_

Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Chin Liang See]

On Thu, 2015-11-05 at 03:53 +0100, ma...@denx.de wrote:
> On Thursday, November 05, 2015 at 03:49:18 AM, Chin Liang See wrote:
> > Hi Marek,
> > 
> > On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> > > On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > > > On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > > > > Add Altera Generic Quad SPI Controller support. The controller
> > > > > converts SPI NOR flash to parallel flash interface. So it is
> > > > > not like other SPI flash, but rather like CFI flash.
> > > > > 
> > > > > Signed-off-by: Thomas Chou 
> > > > > ---
> > > > > 
> > > > >  doc/device-tree-bindings/mtd/altera_qspi.txt |  35 +++
> > > > >  drivers/mtd/Kconfig  |   9 +
> > > > >  drivers/mtd/Makefile |   1 +
> > > > >  drivers/mtd/altera_qspi.c| 312
> > > > >  +++ 4 files changed, 357 insertions(+)
> > > > >  create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt
> > > > >  create mode 100644 drivers/mtd/altera_qspi.c
> > > > >  ...
> > > > > 
> > > > > diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
> > > > > new file mode 100644
> > > > > index 000..06bc53e
> > > > > --- /dev/null
> > > > > +++ b/drivers/mtd/altera_qspi.c
> > > > > @@ -0,0 +1,312 @@
> > > > > +/*
> > > > > + * Copyright (C) 2015 Thomas Chou 
> > > > > + *
> > > > > + * SPDX-License-Identifier:  GPL-2.0+
> > > > > + */
> > > > > +
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +#include 
> > > > > +
> > > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > > +
> > > > > +/*
> > > > > + * The QUADSPI_MEM_OP register is used to do memory protect and
> > > > > erase operations + */
> > > > > +#define QUADSPI_MEM_OP_BULK_ERASE0x0001
> > > > > +#define QUADSPI_MEM_OP_SECTOR_ERASE  0x0002
> > > > > +#define QUADSPI_MEM_OP_SECTOR_PROTECT0x0003
> > > > > +
> > > > > +/*
> > > > > + * The QUADSPI_ISR register is used to determine whether an invalid
> > > > > write or + * erase operation trigerred an interrupt
> > > > > + */
> > > > > +#define QUADSPI_ISR_ILLEGAL_ERASEBIT(0)
> > > > > +#define QUADSPI_ISR_ILLEGAL_WRITEBIT(1)
> > > > > +
> > > > > +struct altera_qspi_regs {
> > > > > + u32 rd_status;
> > > > > + u32 rd_sid;
> > > > > + u32 rd_rdid;
> > > > > + u32 mem_op;
> > > > > + u32 isr;
> > > > > + u32 imr;
> > > > > + u32 chip_select;
> > > > > +};
> > > > > +
> > > > > +struct altera_qspi_platdata {
> > > > > + struct altera_qspi_regs *regs;
> > > > > + void *base;
> > > > > + unsigned long size;
> > > > > +};
> > > > > +
> > > > > +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips
> > > 
> > > info
> > > 
> > > > > */ +
> > > > > +void flash_print_info(flash_info_t *info)
> > > > > +{
> > > > > + printf("Altera QSPI flash  Size: %ld MB in %d Sectors\n",
> > > > > +info->size >> 20, info->sector_count);
> > > > > +}
> > > > > +
> > > > > +int flash_erase(flash_info_t *info, int s_first, int s_last)
> > > > > +{
> > > > > + struct mtd_info *mtd = info->mtd;
> > > > > + struct erase_info instr;
> > > > > + int ret;
> > > > > +
> > > > > + memset(&instr, 0, sizeof(instr));
> > > > > + instr.addr = mtd->erasesize * s_first;
> > > > > + instr.len = mtd->erasesize * (s_last + 1 - s_first);
> > > > > + ret = mtd_erase(mtd, &instr);
> > > > > + if (ret)
> > > > > + return ERR_NOT_ERASED;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong
> > > > > cnt) +{
> > > > > + struct mtd_info *mtd = info->mtd;
> > > > > + struct udevice *dev = mtd->dev;
> > > > > + struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > > > + ulong base = (ulong)pdata->base;
> > > > > + loff_t to = addr - base;
> > > > > + size_t retlen;
> > > > > + int ret;
> > > > > +
> > > > > + ret = mtd_write(mtd, to, cnt, &retlen, src);
> > > > > + if (ret)
> > > > > + return ERR_NOT_ERASED;
> > > > > +
> > > > > + return 0;
> > > > > +}
> > > > > +
> > > > > +unsigned long flash_init(void)
> > > > > +{
> > > > > + struct udevice *dev;
> > > > > +
> > > > > + /* probe every MTD device */
> > > > > + for (uclass_first_device(UCLASS_MTD, &dev);
> > > > > +  dev;
> > > > > +  uclass_next_device(&dev)) {
> > > > > + }
> > > > > +
> > > > > + return flash_info[0].size;
> > > > > +}
> > > > > +
> > > > > +static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info
> > > > > *instr) +{
> > > > > + struct udevice *dev = mtd->dev;
> > > > > + struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > > > + struct al

Re: [U-Boot] [PATCH 3/3] arm: at91: spl/atmel_sfr: move saic redirect to separate file

[Josh Wu]

Hi, Wenyou

On 11/4/2015 2:28 PM, Wenyou Yang wrote:

To make saic redirect code sharing with other SoCs, move the
saic redirect code from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/atmel_sfr.c


maybe move it as mach-at91/armv7/atmel_sfr.c?

Best Regards,
Josh Wu


Move ATMEL_SFR_AICREDIR_KEY definition to sama5d4.h, because each
SoC has its own value.

Signed-off-by: Wenyou Yang 
---

  arch/arm/mach-at91/Makefile |2 +-
  arch/arm/mach-at91/armv7/sama5d4_devices.c  |   13 -
  arch/arm/mach-at91/atmel_sfr.c  |   21 +
  arch/arm/mach-at91/include/mach/sama5_sfr.h |1 -
  arch/arm/mach-at91/include/mach/sama5d4.h   |3 +++
  5 files changed, 25 insertions(+), 15 deletions(-)
  create mode 100644 arch/arm/mach-at91/atmel_sfr.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 649aff2..ca60397 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
  obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
  obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
  obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
  obj-y += spl.o
  endif
  
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c

index 52f4862..ce33cd4 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -45,16 +45,3 @@ void at91_udp_hw_init(void)
at91_periph_clk_enable(ATMEL_ID_UDPHS);
  }
  #endif
-
-#ifdef CONFIG_SPL_BUILD
-void redirect_int_from_saic_to_aic(void)
-{
-   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-   u32 key32;
-
-   if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
-   key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
-   writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
-   }
-}
-#endif
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
new file mode 100644
index 000..2bccb84
--- /dev/null
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *   Wenyou Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+void redirect_int_from_saic_to_aic(void)
+{
+   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+   u32 key32;
+
+   if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
+   key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
+   writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
+   }
+}
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h 
b/arch/arm/mach-at91/include/mach/sama5_sfr.h
index 3081d37..7b19a20 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/sama5_sfr.h
@@ -32,7 +32,6 @@ struct atmel_sfr {
  #define ATMEL_SFR_DDRCFG_FDQSIEN  0x0002
  
  /* Bit field in AICREDIR */

-#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
  #define ATMEL_SFR_AICREDIR_NSAIC  0x0001
  
  #endif

diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h 
b/arch/arm/mach-at91/include/mach/sama5d4.h
index 449cf0e..90085da 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -204,6 +204,9 @@
  #define H32MX_SLAVE_USB   5   /* USB Device & Host */
  #define H32MX_SLAVE_SMD   6   /* Soft Modem (SMD) */
  
+/* AICREDIR Unlock Key */

+#define ATMEL_SFR_AICREDIR_KEY 0x5F67B102
+
  /* sama5d4 series chip id definitions */
  #define ARCH_ID_SAMA5D4   0x8a5c07c0
  #define ARCH_EXID_SAMA5D410x0001


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Re: [U-Boot] [PATCH 2/3] arm: at91/spl: matrix: improve implementation of matrix

[Josh Wu]

Hi, Wenyou

On 11/4/2015 2:28 PM, Wenyou Yang wrote:

To make matrix initialization code sharing with others,
use the matrix slave id macros, instead of hard-coding.

it is better if you split the following 'removing code' as another patch.

Best Regards,
Josh Wu

Remove the write protection mode code, it is unneeded for
writing registers.

Remove the security peripheral selecting code, it is
unneeded for SPL use-case.

Signed-off-by: Wenyou Yang 
---

  arch/arm/mach-at91/include/mach/sama5d4.h |   25 +
  arch/arm/mach-at91/matrix.c   |   35 -
  2 files changed, 34 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h 
b/arch/arm/mach-at91/include/mach/sama5d4.h
index 3da8aff..449cf0e 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -179,6 +179,31 @@
  #define CPU_HAS_PCR
  #define CPU_HAS_H32MXDIV
  
+/* MATRIX0(H64MX) slave id definitions */

+#define H64MX_SLAVE_AXIMX_BRIDGE   0   /* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE  1   /* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC   2   /* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0 3   /* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1 4   /* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2 5   /* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3 6   /* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4 7   /* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5 8   /* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6 9   /* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7 10  /* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM   11  /* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE   12  /* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE   0   /* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0 1   /* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1 2   /* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI3   /* External Bus 
Interface */
+#define H32MX_SLAVE_NFC_CMD3   /* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM   4   /* NFC SRAM */
+#define H32MX_SLAVE_USB5   /* USB Device & Host */
+#define H32MX_SLAVE_SMD6   /* Soft Modem (SMD) */
+
  /* sama5d4 series chip id definitions */
  #define ARCH_ID_SAMA5D4   0x8a5c07c0
  #define ARCH_EXID_SAMA5D410x0001
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
index cf36386..57d7270 100644
--- a/arch/arm/mach-at91/matrix.c
+++ b/arch/arm/mach-at91/matrix.c
@@ -15,37 +15,20 @@ void matrix_init(void)
struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
int i;
  
-	/* Disable the write protect */

-   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
-   /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
-   for (i = 4; i <= 10; i++) {
+   /* DDR port 1 ~ port 7 */
+   for (i = H64MX_SLAVE_DDRC_PORT1; i <= H64MX_SLAVE_DDRC_PORT7; i++) {
writel(0x000f0f0f, &h64mx->ssr[i]);
writel(0x, &h64mx->sassr[i]);
writel(0x000f, &h64mx->srtsr[i]);
}
  
-	/* CS3 */

-   writel(0x00c0c0c0, &h32mx->ssr[3]);
-   writel(0xff00, &h32mx->sassr[3]);
-   writel(0xff00, &h32mx->srtsr[3]);
+   /* EBI CS3 (NANDFlash 128M) and NFC Command Registers(128M) */
+   writel(0x00c0c0c0, &h32mx->ssr[H32MX_SLAVE_EBI]);
+   writel(0xff00, &h32mx->sassr[H32MX_SLAVE_EBI]);
+   writel(0xff00, &h32mx->srtsr[H32MX_SLAVE_EBI]);
  
  	/* NFC SRAM */

-   writel(0x00010101, &h32mx->ssr[4]);
-   writel(0x0001, &h32mx->sassr[4]);
-   writel(0x0001, &h32mx->srtsr[4]);
-
-   /* Configure Programmable Security peripherals on matrix 64 */
-   writel(readl(&h64mx->spselr[0]) | 0x0008, &h64mx->spselr[0]);
-   writel(readl(&h64mx->spselr[1]) | 0x0018, &h64mx->spselr[1]);
-   writel(readl(&h64mx->spselr[2]) | 0x0008, &h64mx->spselr[2]);
-
-   /* Configure Programmable Security peripherals on matrix 32 */
-   writel(readl(&h32mx->spselr[0]) | 0xFFC0, &h32mx->spselr[0]);
-   writel(readl(&h32mx->spselr[1]) | 0x60E3, &h32mx->spselr[1]);
-
-   /* Enable the write protect */
-   writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-   writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
+   writel(0x00010101, &h32mx->ssr[H32MX_SLAVE_NFC_SRAM]);
+   writel(0x0001, &h32mx->sassr[H32MX_SL

Re: [U-Boot] [PATCH 1/3] arm: at91/spl: matrix: move matrix init to separate file

[Josh Wu]

Hi, Wenyou

On 11/4/2015 2:28 PM, Wenyou Yang wrote:

To make the matrix initialization code sharing with other SoCs,
move it from SAMA5D4 particular file,
mach-at91/armv7/sama5d4_devices.c to a separate file,
mach-at91/matrix.c
is it possible just move it to mach-at91/armv7/matrix.c, as it is only 
used by armv7 core?


Best Regards,
Josh Wu


Signed-off-by: Wenyou Yang 
---

  arch/arm/mach-at91/Makefile|2 +-
  arch/arm/mach-at91/armv7/sama5d4_devices.c |   42 ---
  arch/arm/mach-at91/matrix.c|   51 
  3 files changed, 52 insertions(+), 43 deletions(-)
  create mode 100644 arch/arm/mach-at91/matrix.c

diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 313eb47..649aff2 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -6,7 +6,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o
  obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o
  obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o
  obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o
-obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o
+obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o
  obj-y += spl.o
  endif
  
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c

index 76301d6..52f4862 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -10,7 +10,6 @@
  #include 
  #include 
  #include 
-#include 
  #include 
  #include 
  
@@ -48,47 +47,6 @@ void at91_udp_hw_init(void)

  #endif
  
  #ifdef CONFIG_SPL_BUILD

-void matrix_init(void)
-{
-   struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
-   struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
-   int i;
-
-   /* Disable the write protect */
-   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-
-   /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
-   for (i = 4; i <= 10; i++) {
-   writel(0x000f0f0f, &h64mx->ssr[i]);
-   writel(0x, &h64mx->sassr[i]);
-   writel(0x000f, &h64mx->srtsr[i]);
-   }
-
-   /* CS3 */
-   writel(0x00c0c0c0, &h32mx->ssr[3]);
-   writel(0xff00, &h32mx->sassr[3]);
-   writel(0xff00, &h32mx->srtsr[3]);
-
-   /* NFC SRAM */
-   writel(0x00010101, &h32mx->ssr[4]);
-   writel(0x0001, &h32mx->sassr[4]);
-   writel(0x0001, &h32mx->srtsr[4]);
-
-   /* Configure Programmable Security peripherals on matrix 64 */
-   writel(readl(&h64mx->spselr[0]) | 0x0008, &h64mx->spselr[0]);
-   writel(readl(&h64mx->spselr[1]) | 0x0018, &h64mx->spselr[1]);
-   writel(readl(&h64mx->spselr[2]) | 0x0008, &h64mx->spselr[2]);
-
-   /* Configure Programmable Security peripherals on matrix 32 */
-   writel(readl(&h32mx->spselr[0]) | 0xFFC0, &h32mx->spselr[0]);
-   writel(readl(&h32mx->spselr[1]) | 0x60E3, &h32mx->spselr[1]);
-
-   /* Enable the write protect */
-   writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
-   writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
-}
-
  void redirect_int_from_saic_to_aic(void)
  {
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
diff --git a/arch/arm/mach-at91/matrix.c b/arch/arm/mach-at91/matrix.c
new file mode 100644
index 000..cf36386
--- /dev/null
+++ b/arch/arm/mach-at91/matrix.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *   Wenyou Yang 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+void matrix_init(void)
+{
+   struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0;
+   struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1;
+   int i;
+
+   /* Disable the write protect */
+   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr);
+   writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr);
+
+   /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */
+   for (i = 4; i <= 10; i++) {
+   writel(0x000f0f0f, &h64mx->ssr[i]);
+   writel(0x, &h64mx->sassr[i]);
+   writel(0x000f, &h64mx->srtsr[i]);
+   }
+
+   /* CS3 */
+   writel(0x00c0c0c0, &h32mx->ssr[3]);
+   writel(0xff00, &h32mx->sassr[3]);
+   writel(0xff00, &h32mx->srtsr[3]);
+
+   /* NFC SRAM */
+   writel(0x00010101, &h32mx->ssr[4]);
+   writel(0x0001, &h32mx->sassr[4]);
+   writel(0x0001, &h32mx->srtsr[4]);
+
+   /* Configure Programmable Security peripherals on matrix 64 */
+   writel(readl(&h64mx->spselr[0]) | 0x0008, &h64mx->spselr[0]);
+   writel(readl(&h64mx->spselr[1]) | 0x0018, &h64mx->sp

Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Marek Vasut]

On Thursday, November 05, 2015 at 03:49:18 AM, Chin Liang See wrote:
> Hi Marek,
> 
> On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> > On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > > On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > > > Add Altera Generic Quad SPI Controller support. The controller
> > > > converts SPI NOR flash to parallel flash interface. So it is
> > > > not like other SPI flash, but rather like CFI flash.
> > > > 
> > > > Signed-off-by: Thomas Chou 
> > > > ---
> > > > 
> > > >  doc/device-tree-bindings/mtd/altera_qspi.txt |  35 +++
> > > >  drivers/mtd/Kconfig  |   9 +
> > > >  drivers/mtd/Makefile |   1 +
> > > >  drivers/mtd/altera_qspi.c| 312
> > > >  +++ 4 files changed, 357 insertions(+)
> > > >  create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt
> > > >  create mode 100644 drivers/mtd/altera_qspi.c
> > > >  ...
> > > > 
> > > > diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
> > > > new file mode 100644
> > > > index 000..06bc53e
> > > > --- /dev/null
> > > > +++ b/drivers/mtd/altera_qspi.c
> > > > @@ -0,0 +1,312 @@
> > > > +/*
> > > > + * Copyright (C) 2015 Thomas Chou 
> > > > + *
> > > > + * SPDX-License-Identifier:GPL-2.0+
> > > > + */
> > > > +
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +
> > > > +DECLARE_GLOBAL_DATA_PTR;
> > > > +
> > > > +/*
> > > > + * The QUADSPI_MEM_OP register is used to do memory protect and
> > > > erase operations + */
> > > > +#define QUADSPI_MEM_OP_BULK_ERASE  0x0001
> > > > +#define QUADSPI_MEM_OP_SECTOR_ERASE0x0002
> > > > +#define QUADSPI_MEM_OP_SECTOR_PROTECT  0x0003
> > > > +
> > > > +/*
> > > > + * The QUADSPI_ISR register is used to determine whether an invalid
> > > > write or + * erase operation trigerred an interrupt
> > > > + */
> > > > +#define QUADSPI_ISR_ILLEGAL_ERASE  BIT(0)
> > > > +#define QUADSPI_ISR_ILLEGAL_WRITE  BIT(1)
> > > > +
> > > > +struct altera_qspi_regs {
> > > > +   u32 rd_status;
> > > > +   u32 rd_sid;
> > > > +   u32 rd_rdid;
> > > > +   u32 mem_op;
> > > > +   u32 isr;
> > > > +   u32 imr;
> > > > +   u32 chip_select;
> > > > +};
> > > > +
> > > > +struct altera_qspi_platdata {
> > > > +   struct altera_qspi_regs *regs;
> > > > +   void *base;
> > > > +   unsigned long size;
> > > > +};
> > > > +
> > > > +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* FLASH chips
> > 
> > info
> > 
> > > > */ +
> > > > +void flash_print_info(flash_info_t *info)
> > > > +{
> > > > +   printf("Altera QSPI flash  Size: %ld MB in %d Sectors\n",
> > > > +  info->size >> 20, info->sector_count);
> > > > +}
> > > > +
> > > > +int flash_erase(flash_info_t *info, int s_first, int s_last)
> > > > +{
> > > > +   struct mtd_info *mtd = info->mtd;
> > > > +   struct erase_info instr;
> > > > +   int ret;
> > > > +
> > > > +   memset(&instr, 0, sizeof(instr));
> > > > +   instr.addr = mtd->erasesize * s_first;
> > > > +   instr.len = mtd->erasesize * (s_last + 1 - s_first);
> > > > +   ret = mtd_erase(mtd, &instr);
> > > > +   if (ret)
> > > > +   return ERR_NOT_ERASED;
> > > > +
> > > > +   return 0;
> > > > +}
> > > > +
> > > > +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong
> > > > cnt) +{
> > > > +   struct mtd_info *mtd = info->mtd;
> > > > +   struct udevice *dev = mtd->dev;
> > > > +   struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > > +   ulong base = (ulong)pdata->base;
> > > > +   loff_t to = addr - base;
> > > > +   size_t retlen;
> > > > +   int ret;
> > > > +
> > > > +   ret = mtd_write(mtd, to, cnt, &retlen, src);
> > > > +   if (ret)
> > > > +   return ERR_NOT_ERASED;
> > > > +
> > > > +   return 0;
> > > > +}
> > > > +
> > > > +unsigned long flash_init(void)
> > > > +{
> > > > +   struct udevice *dev;
> > > > +
> > > > +   /* probe every MTD device */
> > > > +   for (uclass_first_device(UCLASS_MTD, &dev);
> > > > +dev;
> > > > +uclass_next_device(&dev)) {
> > > > +   }
> > > > +
> > > > +   return flash_info[0].size;
> > > > +}
> > > > +
> > > > +static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info
> > > > *instr) +{
> > > > +   struct udevice *dev = mtd->dev;
> > > > +   struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > > +   struct altera_qspi_regs *regs = pdata->regs;
> > > > +   size_t addr = instr->addr;
> > > > +   size_t len = instr->len;
> > > > +   size_t end = addr + len;
> > > > +   u32 sect;
> > > > +   u32 stat;
> > > > +
> > > > +

[U-Boot] [PULL] u-boot-usb/master

[Marek Vasut]

The following changes since commit 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4:

  mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 (2015-11-02 08:51:50 
-0800)

are available in the git repository at:

  git://git.denx.de/u-boot-usb.git 

for you to fetch changes up to f6fcebf5c181365a3c9ebc672d88121d54359eed:

  usb: udc: Fix warnings on 64-bit builds (2015-11-03 17:29:54 +0100)


Hans de Goede (1):
  ohci: Add missing cache-flush for hcca area

Michal Simek (3):
  usb: dwc3: Fix warnings on 64-bit builds
  usb: lthor: Specify correct parameter for sizeof type
  usb: udc: Fix warnings on 64-bit builds

Tom Rini (1):
  common/usb_storage.c: Clean up usb_storage_probe()

Vignesh R (2):
  dfu: dfu_sf: Pass duplicate devstr to parse_dev
  ARM: dra7xx_evm: Add DFU support for qspi flash

 common/usb_storage.c  | 29 ++---
 drivers/dfu/dfu_sf.c  |  4 +++-
 drivers/usb/dwc3/core.c   |  7 ---
 drivers/usb/dwc3/ep0.c| 10 +-
 drivers/usb/dwc3/gadget.c | 10 +-
 drivers/usb/dwc3/io.h |  4 ++--
 drivers/usb/gadget/f_thor.c   |  2 +-
 drivers/usb/gadget/udc/udc-core.c |  2 +-
 drivers/usb/host/ohci-hcd.c   |  1 +
 include/configs/dra7xx_evm.h  | 16 +++-
 10 files changed, 39 insertions(+), 46 deletions(-)
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[U-Boot] [PULL] u-boot-socfpga/master

[Marek Vasut]

The following changes since commit 96d59e9d6aa74e35c63dc74da10e41f8ba0f6de4:

  mpc85xx/t2081: enable parsing DDR ratio for T2081 rev1.1 (2015-11-02 08:51:50 
-0800)

are available in the git repository at:

  git://git.denx.de/u-boot-socfpga.git 

for you to fetch changes up to a55f28624e97e1e43ac333c39713b8b9435fcbd3:

  arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash (2015-11-05 
02:34:15 +0100)


Chin Liang See (5):
  lib, fdt: Adding fdtdec_get_uint function
  spi: cadence_qspi: Ensure spi_calibration is run when sclk change
  spi: cadence_qspi: Fix fdt read of spi-max-frequency
  spi: cadence_qspi: Ensure check for max frequency in place
  arm: dts: socfpga: Increase the spi-max-frequency for QSPI flash

Dinh Nguyen (1):
  arm: socfpga: reset: correct dma, qspi, and sdmmc reset bit defines

 arch/arm/dts/socfpga_cyclone5_socdk.dts|  2 +-
 arch/arm/mach-socfpga/include/mach/reset_manager.h |  6 +++---
 drivers/spi/cadence_qspi.c | 33 
-
 drivers/spi/cadence_qspi.h |  1 +
 include/fdtdec.h   | 13 +
 lib/fdtdec_common.c| 18 ++
 6 files changed, 56 insertions(+), 17 deletions(-)
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Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Chin Liang See]

Hi Marek,

On Wed, 2015-11-04 at 10:18 +, ma...@denx.de wrote:
> On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> > On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > > Add Altera Generic Quad SPI Controller support. The controller
> > > converts SPI NOR flash to parallel flash interface. So it is
> > > not like other SPI flash, but rather like CFI flash.
> > > 
> > > Signed-off-by: Thomas Chou 
> > > ---
> > > 
> > >  doc/device-tree-bindings/mtd/altera_qspi.txt |  35 +++
> > >  drivers/mtd/Kconfig  |   9 +
> > >  drivers/mtd/Makefile |   1 +
> > >  drivers/mtd/altera_qspi.c| 312
> > >  +++ 4 files changed, 357 insertions(+)
> > >  create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt
> > >  create mode 100644 drivers/mtd/altera_qspi.c
> > >  ...
> > > 
> > > diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
> > > new file mode 100644
> > > index 000..06bc53e
> > > --- /dev/null
> > > +++ b/drivers/mtd/altera_qspi.c
> > > @@ -0,0 +1,312 @@
> > > +/*
> > > + * Copyright (C) 2015 Thomas Chou 
> > > + *
> > > + * SPDX-License-Identifier:  GPL-2.0+
> > > + */
> > > +
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +#include 
> > > +
> > > +DECLARE_GLOBAL_DATA_PTR;
> > > +
> > > +/*
> > > + * The QUADSPI_MEM_OP register is used to do memory protect and erase
> > > operations + */
> > > +#define QUADSPI_MEM_OP_BULK_ERASE0x0001
> > > +#define QUADSPI_MEM_OP_SECTOR_ERASE  0x0002
> > > +#define QUADSPI_MEM_OP_SECTOR_PROTECT0x0003
> > > +
> > > +/*
> > > + * The QUADSPI_ISR register is used to determine whether an invalid
> > > write or + * erase operation trigerred an interrupt
> > > + */
> > > +#define QUADSPI_ISR_ILLEGAL_ERASEBIT(0)
> > > +#define QUADSPI_ISR_ILLEGAL_WRITEBIT(1)
> > > +
> > > +struct altera_qspi_regs {
> > > + u32 rd_status;
> > > + u32 rd_sid;
> > > + u32 rd_rdid;
> > > + u32 mem_op;
> > > + u32 isr;
> > > + u32 imr;
> > > + u32 chip_select;
> > > +};
> > > +
> > > +struct altera_qspi_platdata {
> > > + struct altera_qspi_regs *regs;
> > > + void *base;
> > > + unsigned long size;
> > > +};
> > > +
> > > +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* FLASH chips 
> info
> > > */ +
> > > +void flash_print_info(flash_info_t *info)
> > > +{
> > > + printf("Altera QSPI flash  Size: %ld MB in %d Sectors\n",
> > > +info->size >> 20, info->sector_count);
> > > +}
> > > +
> > > +int flash_erase(flash_info_t *info, int s_first, int s_last)
> > > +{
> > > + struct mtd_info *mtd = info->mtd;
> > > + struct erase_info instr;
> > > + int ret;
> > > +
> > > + memset(&instr, 0, sizeof(instr));
> > > + instr.addr = mtd->erasesize * s_first;
> > > + instr.len = mtd->erasesize * (s_last + 1 - s_first);
> > > + ret = mtd_erase(mtd, &instr);
> > > + if (ret)
> > > + return ERR_NOT_ERASED;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> > > +{
> > > + struct mtd_info *mtd = info->mtd;
> > > + struct udevice *dev = mtd->dev;
> > > + struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > + ulong base = (ulong)pdata->base;
> > > + loff_t to = addr - base;
> > > + size_t retlen;
> > > + int ret;
> > > +
> > > + ret = mtd_write(mtd, to, cnt, &retlen, src);
> > > + if (ret)
> > > + return ERR_NOT_ERASED;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +unsigned long flash_init(void)
> > > +{
> > > + struct udevice *dev;
> > > +
> > > + /* probe every MTD device */
> > > + for (uclass_first_device(UCLASS_MTD, &dev);
> > > +  dev;
> > > +  uclass_next_device(&dev)) {
> > > + }
> > > +
> > > + return flash_info[0].size;
> > > +}
> > > +
> > > +static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info
> > > *instr) +{
> > > + struct udevice *dev = mtd->dev;
> > > + struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > > + struct altera_qspi_regs *regs = pdata->regs;
> > > + size_t addr = instr->addr;
> > > + size_t len = instr->len;
> > > + size_t end = addr + len;
> > > + u32 sect;
> > > + u32 stat;
> > > +
> > > + instr->state = MTD_ERASING;
> > > + addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
> > > + while (addr < end) {
> > > + sect = addr / mtd->erasesize;
> > > + sect <<= 8;
> > > + sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
> > > + debug("erase %08x\n", sect);
> > > + writel(sect, ®s->mem_op);
> > > + stat = readl(®s->isr);
> > > + if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
> > > + /* erase failed, sector might be protected */
> > > + debug("erase %08x fail %x\n", sect, stat);
> > > + writel(stat, ®s->isr); /* clear isr *

Re: [U-Boot] [PATCH v5 4/5] spi: cadence_qspi: Ensure check for max frequency in place

[Chin Liang See]

On Thu, 2015-11-05 at 02:34 +0100, ma...@denx.de wrote:
> On Wednesday, November 04, 2015 at 03:51:56 PM, Chin Liang See wrote:
> > On Sat, 2015-10-17 at 16:14 +0200, ma...@denx.de wrote:
> > > On Saturday, October 17, 2015 at 03:32:38 PM, Chin Liang See wrote:
> > > > Ensure the intended SCLK frequency not exceeding the maximum
> > > > frequency. If that happen, SCLK will set to maximum frequency.
> > > > 
> > > > Signed-off-by: Chin Liang See 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Dinh Nguyen 
> > > > Cc: Marek Vasut 
> > > > Cc: Stefan Roese 
> > > > Cc: Vikas Manocha 
> > > > Cc: Jagannadh Teki 
> > > > Cc: Pavel Machek 
> > > > Acked-by: Pavel Machek 
> > > 
> > > Acked-by: Marek Vasut 
> > 
> > Thanks Marek for the review.
> > 
> > I noticed these patches yet to be applied.
> > Wonder you able to apply these?
> 
> Sorry about that, applied all five, thanks!

No worries, thanks Marek!

Thanks
Chin Liang

> 
> Best regards,
> Marek Vasut

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Re: [U-Boot] Fastboot behaviour with sparse images

[Maxime Ripard]

Hi Colin,

On Tue, Oct 27, 2015 at 02:00:24PM -0700, Colin Cross wrote:
> On Monday, October 12, 2015 at 6:43:37 AM UTC-7, Maxime Ripard wrote:
> >
> > Hi, 
> >
> > I'm currently writing the support in U-Boot for NAND-backed devices 
> > using fastboot [1], and that work derived a bit to supporting the 
> > sparse images. 
> >
> > For "regular" images that are being stored, we expect a pair of 
> > download and flash commands. Simple. 
> >
> > Things start to get a bit more complex with sparse images that have 
> > been split because of a max-download-size lower than the actual image 
> > size. 
> >
> > Here, from what I could gather from various random blog posts, the 
> > fastboot client implementation and dumping a few USB sessions, the 
> > client simply creates several download / flash pairs, always on the 
> > same partition, without any way to distinct that from several 
> > subsequent writes issued by the user. 
> >
> > So, I'm guessing that the expectation is that the bootloader 
> > implementation should store the last offset it wrote to, and simple 
> > resume from there if the partition names in the flash commands are the 
> > same, which would prevent two subsequent write on the same partition 
> > by any client. Am I right? 
> >
> 
> No, each blob passed to the bootloader will begin with a sparse "skip" 
> chunk that will seek to the correct place to resume writing.  The 
> bootloader shouldn't need to store any metadata across commands.  Just read 
> in the blob from the data command, then write it out using a port of the 
> Apache-licensed libsparse during the flash command.

Oh, so that's how it works. Great. I guess however that you still need
to scan out the area you skip for bad blocks to account them in the
offset calculation as well then (when you're using NAND).

> > A related question is when should we erase the NAND partition? Only 
> > when doing fastboot erase, or also when doing fastboot write (which, 
> > combined with the issue raised above, would also mean that we don't 
> > want to do an erase on the whole partition everytime there's a flash 
> > command on it).
> 
> Fastboot should send an erase command before every sequence of writes. 
>  Erase the whole partition on the erase command, and don't erase anything 
> on the flash command.

Ack.

Thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com


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Re: [U-Boot] [PATCH v5 4/5] spi: cadence_qspi: Ensure check for max frequency in place

[Marek Vasut]

On Wednesday, November 04, 2015 at 03:51:56 PM, Chin Liang See wrote:
> On Sat, 2015-10-17 at 16:14 +0200, ma...@denx.de wrote:
> > On Saturday, October 17, 2015 at 03:32:38 PM, Chin Liang See wrote:
> > > Ensure the intended SCLK frequency not exceeding the maximum
> > > frequency. If that happen, SCLK will set to maximum frequency.
> > > 
> > > Signed-off-by: Chin Liang See 
> > > Cc: Dinh Nguyen 
> > > Cc: Dinh Nguyen 
> > > Cc: Marek Vasut 
> > > Cc: Stefan Roese 
> > > Cc: Vikas Manocha 
> > > Cc: Jagannadh Teki 
> > > Cc: Pavel Machek 
> > > Acked-by: Pavel Machek 
> > 
> > Acked-by: Marek Vasut 
> 
> Thanks Marek for the review.
> 
> I noticed these patches yet to be applied.
> Wonder you able to apply these?

Sorry about that, applied all five, thanks!

Best regards,
Marek Vasut
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[U-Boot] [PATCH] omap3_logic: Cleanup and remove redundant defines make bootz easier

[Adam Ford]

>From 3af52a1a6d71ac3d78e0dec56da2fd8eb07a91d1 Mon Sep 17 00:00:00 2001
From: Adam Ford 
Date: Wed, 4 Nov 2015 17:13:15 -0600
Subject: [PATCH] omap3_logic:  Cleanup and remove redundant defines make bootz
 easier

Some unnecesary includes still exist from the initial conversion
to ti_omap3_common.h

Add some boot scripts to allow for other boot options and unify some
environmental variable names with other omap3 devices.

Signed-off-by: Adam Ford 
---
 include/configs/omap3_logic.h | 125 +++---
 1 file changed, 57 insertions(+), 68 deletions(-)

diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h
index ecd5615..ce06dd3 100644
--- a/include/configs/omap3_logic.h
+++ b/include/configs/omap3_logic.h
@@ -19,7 +19,8 @@
 #define CONFIG_SYS_TEXT_BASE 0x8040

 #include 
-#define CONFIG_OMAP3_LOGIC /* working with Logic OMAP boards */
+
+
 /*
  * Display CPU and Board information
  */
@@ -27,29 +28,23 @@
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

-/* Clock Defines */
-#define V_OSCK 2600 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
 #define CONFIG_MISC_INIT_R /* misc_init_r dumps the die id */
-
 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
-
 #define CONFIG_CMDLINE_EDITING /* cmd line edit/history */
 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check keypress w/no delay */

-/*
- * Size of malloc() pool
- */
+
 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  /* Sector */
 /*
  * Hardware drivers
  */

+#define CONFIG_USB_OMAP3
+
 /*
  * select serial console configuration
  */
@@ -58,58 +53,46 @@
 #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
 #define CONFIG_SERIAL1 1 /* UART1 on OMAP Logic boards */

-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-#define CONFIG_GENERIC_MMC
-#define CONFIG_MMC
-#define CONFIG_OMAP_HSMMC
-#define CONFIG_DOS_PARTITION

 /* commands to include */
 #define CONFIG_CMD_CACHE
-#define CONFIG_CMD_EXT2 /* EXT2 Support */
-#define CONFIG_CMD_FAT /* FAT support */
-#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT  /* FAT support  */
+#define CONFIG_CMD_MTDPARTS
 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
-#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
- "1920k(u-boot),128k(u-boot-env),"\
- "4m(kernel),-(fs)"
-
-#define CONFIG_CMD_I2C /* I2C serial bus support */
-#define CONFIG_CMD_MMC /* MMC support */
-#define CONFIG_CMD_NAND /* NAND support */
+#define MTDIDS_DEFAULT "nand0=omap2-nand.0"
+#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(x-loader),"\
+ "1920k(u-boot),128k(u-boot-env),"\
+ "4m(kernel),-(fs)"
+
 #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP

-#define CONFIG_SYS_NO_FLASH
+#define CONFIG_YAFFS2

 /*
  * I2C
  */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_OMAP24_I2C_SPEED 10
-#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
 #define CONFIG_SYS_I2C_OMAP34XX
+#define CONFIG_SYS_I2C_EEPROM_ADDR  0x50/* EEPROM
AT24C64   */
+#define EXPANSION_EEPROM_I2C_BUS2   /* I2C Bus
for AT24C64  */
+#define CONFIG_OMAP3_LOGIC_USE_NEW_PRODUCT_ID

 /*
  * TWL4030
  */
-
+#define CONFIG_TWL4030_PWM

 /*
  * Board NAND Info.
  */
+#define CONFIG_CMD_NAND
 #define CONFIG_SYS_NAND_BASENAND_BASE
 #define CONFIG_NAND_OMAP_GPMC
 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  /* to access nand */

-
 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  /* NAND devices */
 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
@@ -144,10 +127,13 @@

 #define CONFIG_EXTRA_ENV_SETTINGS \
  "loadaddr=0x8100\0" \
- "bootfile=uImage\0" \
+ "uimage=uImage\0" \
+ "zimage=zImage\0" \
  "mtdids=" MTDIDS_DEFAULT "\0" \
  "mtdparts=" MTDPARTS_DEFAULT "\0" \
  "mmcdev=0\0" \
+ "mmcroot=/dev/mmcblk0p2 rw\0" \
+ "mmcrootfstype=ext3 rootwait\0" \
  "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
  "if run loadbootscript; then " \
  "run bootscript; " \
@@ -165,34 +151,60 @@
  "setenv bootargs ${bootargs} omapfb.vrfb=y " \
  "omapfb.rotate=${rotation}; " \
  "fi\0" \
- "otherbootargs=ignore_loglevel early_printk no_console_suspend\0" \
+ "optargs=ignore_loglevel early_printk no_console_suspend\0" \
  "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
  "common_bootargs=setenv bootargs ${bootargs} display=${display} " \
- "${otherbootargs};" \
+ "${optargss};" \
  "run addmtdparts; " \
  "run vrfb_arg\0" \
  "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  "bootscript=echo 'Running bootscript from mmc ...'; " \
  "source ${loadaddr}\0" \
- "loaduimage=mmc rescan

Re: [U-Boot] [Patch V2 3/4] armv8/ls1043aqds: add LS1043AQDS board support

[Scott Wood]

On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:

> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h 
> b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> index 4da73ab..e3989a8 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fdt.h
> @@ -11,4 +11,7 @@ void alloc_stream_ids(int start_id, int count, u32 
> *stream_ids, int max_cnt);
>  void append_mmu_masters(void *blob, const char *smmu_path,
>   const char *master_name, u32 *stream_ids, int count);
>  void fdt_fixup_smmu_pcie(void *blob);
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +void fdt_fixup_board_enet(void *fdt);
> +#endif
>  #endif   /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */

Why are you ifdeffing a prototype?

-Scott

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Re: [U-Boot] [PATCH v3 0/5] ARM: omap-common: Add board detection support for TI EVMs

[Nishanth Menon]

On 11/04/2015 04:00 PM, Steve Kipisz wrote:
> Several TI EVMs have onboard EEPROM that contain board description
> information. The onboard EEPROM on Beaglebone, Beaglebone Black, AM335x
> EVM, AM43x EVM, AM57xx EVM, Beagleboard-x15 all share the same format.
> 
> This series of patches introduces code which is generic among these
> platforms. The boards can use the data for any operations they might
> choose.
> 
> Lokesh Vutla (1):
>   ARM: omap-common: Add standard access for board description EEPROM
> 
> Steve Kipisz (4):
>   ARM: OMAP4/5: Centralize early clock initialization
>   ARM: OMAP4/5: Centralize gpi2c_init
>   ARM: OMAP4/5: Add generic board detection hook
>   board: ti: AM57xx: Add detection logic for AM57xx-evm
> 
>  arch/arm/cpu/armv7/omap-common/clocks-common.c |  21 +++-
>  arch/arm/cpu/armv7/omap-common/hwinit-common.c |  14 ++-
>  arch/arm/include/asm/arch-omap4/sys_proto.h|   4 +-
>  arch/arm/include/asm/arch-omap5/sys_proto.h|   4 +-
>  arch/arm/include/asm/omap_common.h |   8 +-
>  board/ti/am57xx/Makefile   |   2 +
>  board/ti/am57xx/board.c|  52 +
>  board/ti/common/board.c|  54 +
>  board/ti/common/board.h| 117 +++
>  board/ti/common/ti-i2c-eeprom.c| 148 
> +
>  include/configs/am57xx_evm.h   |   4 +
>  11 files changed, 419 insertions(+), 9 deletions(-)
>  create mode 100644 board/ti/common/board.c
>  create mode 100644 board/ti/common/board.h
>  create mode 100644 board/ti/common/ti-i2c-eeprom.c
> 

In the future, please:
a) CC beagleboard-x15 mailing list (beagleboard-x15
)
b) CC previous reviewers: I think I dont see Igor
(grinb...@compulab.co.il) in CC list. it is a good practice to cc
previous reviewers because, we dont always watch all emails coming to
the list and you'd like to respect the time and effort reviewers put
in when sending newer revisions.
c) even though I see that you have provided in-context of each patch
what the changes are (that is good), it is usually better to add to
the covering letter what the v1,v2 links were, and also what the
baseline for this series is - in this case, you do depend on
https://patchwork.ozlabs.org/patch/538046/ - and should be highlighted
in cover-letter and reiterated in the corresponding patch.
d) provide links to test logs in cover-letter. most of folks do not
possess x15 and evms - While I do realize that you have covered that
data in the patch #5, personally, I dont usually review patches that
are'nt even tested - and I personally respect the patches that tell me
upfront in cover letter than the patches have been tested and links to
the same.
e) provide the baseline for the patches in cover letter, instead of
repeating them over and over in each of the patches. it is a series,
and patches following will depend on previous patches. For example,
your patch #5 claims:
"v3 Based on:
 master 83bf0057 arm: at91: reworked meesc board support"

That is not really true - because you do depend on x15 rename patch.
If I attempt to apply this series on current u-boot master, I will
fail and that does not give me a good impression of the series overall.


Apologies on ranting about this, but I'd thought it might help you
give a better perspective of what, at least I, as a reviewer would
like to see in a series.


-- 
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Nishanth Menon
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Re: [U-Boot] [Patch V2 2/4] armv8/ls1043ardb: dts: add dtb support

[Scott Wood]

On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> Reuse dts files from ls1043a linux kernel. Some parts in dts files
> may not be needed by U-Boot.
> 
> Signed-off-by: Gong Qianyu 
> ---
> V2:
>  - New Patch.
> 
>  arch/arm/dts/Makefile|   1 +
>  arch/arm/dts/fsl-ls1043a-rdb.dts | 169 +++
>  arch/arm/dts/fsl-ls1043a.dtsi| 346 
> +++
>  configs/ls1043ardb_defconfig |   2 +
>  4 files changed, 518 insertions(+)
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index ddc6a05..3f3a739 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -83,6 +83,7 @@ dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
>   ls1021a-twr.dtb
>  dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
>   fsl-ls2085a-rdb.dtb
> +dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-rdb.dtb
>  
>  dtb-$(CONFIG_MACH_SUN4I) += \
>   sun4i-a10-a1000.dtb \
> diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-
> rdb.dts
> new file mode 100644
> index 000..51b5e9f
> --- /dev/null
> +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
> @@ -0,0 +1,169 @@
> +/*
> + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
> + *
> + * Copyright (C) 2015, Freescale Semiconductor
> + *
> + * Mingkai Hu 
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2.  This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +/dts-v1/;
> +/include/ "fsl-ls1043a.dtsi"
> +
> +/ {
> + model = "LS1043A RDB Board";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +  ina220@40{
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +  adt7461a@4c{
> + compatible = "adt7461a";
> + reg = <0x4c>;
> + };
> +  eeprom@56{
> + compatible = "at24,24c512";
> + reg = <0x52>;
> + };
> +
> +  eeprom@57{
> + compatible = "at24,24c512";
> + reg = <0x53>;
> + };
> +
> +  rtc@68{
> + compatible = "pericom,pt7c4338";
> + reg = <0x68>;
> + };
> +};
> +
> +&ifc {
> + status = "okay";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + /* NOR, NAND Flashes and FPGA on board */
> + ranges = <0x0 0x0 0x0 0x6000 0x0800
> +   0x2 0x0 0x0 0x7e80 0x0001
> +   0x3 0x0 0x0 0x7fb0 0x0100>;
> +
> + nor@0,0 {
> + compatible = "cfi-flash";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0 0x0 0x800>;
> + bank-width = <2>;
> + device-width = <1>;
> +
> +  partition@0{
> + /* 1MB for RCW and PBI Image */
> + reg = <0x 0x0010>;
> + label = "NOR bank0 RCW Image";
> + };
> +
> +  partition@10{
> + /* 1MB for bank0 u-boot Image */
> + reg = <0x0010 0x0010>;
> + label = "NOR bank0 U-Boot Image";
> + };
> +
> +  partition@20{
> + /* 1 MB for bank0 u-boot Env */
> + reg = <0x0020 0x0010>;
> + label = "NOR bank0 U-Boot Env";
> + };
> +
> +  partition@30{
> + /* 1MB for FMan ucode */
> + reg = <0x0030 0x0010>;
> + label = "NOR bank0 FMan ucode";
> + };
> +
> +  partition@110{
> + /* 40MB for bank0 FIT Image */
> + reg = <0x0110 0x280>;
> + label = "NOR bank0 FIT Image";
> + };
> +
> +  partition@400{
> + /* 1MB for bank4 RCW and PBI Image */
> + reg = <0x0400 0x10>;
> + label = "NOR bank4 RCW Image";
> + };
> +
> +  partition@410{
> + /* 1MB for bank4 u-boot Image */
> + reg = <0x0410 0x10>;
> + label = "NOR bank4 U-Boot Image";
> + };
> +
> +  partition@420{
> + /* 1 MB for bank4 u-boot Env */
> + reg = <0x0420 0x10>;
> + label = "NOR bank4 U-Boot Env";
> + };
> +
> +  partition@430

Re: [U-Boot] [Patch V2 1/4] pci/layerscape: add support for LS1043A PCIe LUT register access

[Scott Wood]

On Mon, 2015-11-02 at 19:15 +0800, Gong Qianyu wrote:
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 4cee038..8471678 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -13,6 +13,7 @@
>  #include 
>  #ifdef CONFIG_FSL_LAYERSCAPE
>  #include 
> +#include 
>  #endif
>  
>  #ifndef CONFIG_SYS_PCI_MEMORY_BUS
> @@ -57,11 +58,6 @@
>  #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
>  #define PCIE_ATU_UPPER_TARGET0x91C
>  
> -/* LUT registers */
> -#define PCIE_LUT_BASE0x8
> -#define PCIE_LUT_LCTRL0  0x7F8
> -#define PCIE_LUT_DBG 0x7FC
> -
>  #define PCIE_DBI_RO_WR_EN0x8bc
>  
>  #define PCIE_LINK_CAP0x7c
> @@ -157,12 +153,12 @@ static int ls_pcie_link_state(struct ls_pcie *pcie)
>  
>   return 1;
>  }
> -#else
> +#elif defined(CONFIG_FSL_LAYERSCAPE)
>  static int ls_pcie_link_state(struct ls_pcie *pcie)
>  {
>   u32 state;
>  
> - state = readl(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
> + state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
>   LTSSM_STATE_MASK;
>   if (state < LTSSM_PCIE_L0) {
>   debug("PCIe link error. LTSSM=0x%02x.\n", state);
> @@ -466,16 +462,20 @@ static void ls_pcie_setup_ep(struct ls_pcie *pcie, 
> struct ls_pcie_info *info)
>  
>   for (pf = 0; pf < PCIE_PF_NUM; pf++) {
>   for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
> +#ifdef CONFIG_FSL_LAYERSCAPE
>   writel(PCIE_LCTRL0_VAL(pf, vf),
>  pcie->dbi + PCIE_LUT_BASE +
>  PCIE_LUT_LCTRL0);
> +#endif

It looks really weird to have "#ifdef CONFIG_FSL_LAYERSCAPE" inside a file 
whose name suggests is layerscape-specific.  What chips use this file that 
are not CONFIG_FSL_LAYERSCAPE?

-Scott

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Re: [U-Boot] Please pull u-boot-mpc85xx master

[Tom Rini]

On Wed, Nov 04, 2015 at 03:24:09PM -0800, York Sun wrote:

> Tom,
> 
> The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313:
> 
>   arm: at91: reworked meesc board support (2015-11-03 14:21:32 +0100)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-mpc85xx.git master
> 
> for you to fetch changes up to 87e29878caba758ed3e09e9912ac8eb6dfc55f39:
> 
>   mpc85xx: Add support for the Varisys Cyrus board (2015-11-04 15:19:34 -0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [U-Boot] [PATCH v3 3/5] ARM: omap-common: Add standard access for board description EEPROM

[Nishanth Menon]

On 11/04/2015 04:00 PM, Steve Kipisz wrote:
> From: Lokesh Vutla 
> 
> Several TI EVMs have EEPROM that can contain board description information
> such as revision, DDR definition, serial number, etc. In just about all
> cases, these EEPROM are on the I2C bus and provides us the opportunity
> to centralize the generic operations involved.
> 
> The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
> AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
> However, DRA-7* EVMs, OMAP4SDP use a modified format.
> 
> We hence introduce logic which is generic between these platforms
> without enforcing any specific format. This allows the boards to use the
> relevant format for operations that they might choose.
> 
> This module will compile for all TI SoC based boards when I2C is enabled,
> even non-TI boards that do not have the EEPROM. If the functions are not
> used, they will not be linked in.
> 
> It is important to note that this logic is fundamental to the board
> configuration process such as DDR configuration which is needed in
> SPL, hence cannot be part of the standard u-boot driver model (which
> is available later in the process). Hence, to aid efficiency, the
> eeprom contents are copied over to SRAM scratchpad memory area at the
> first invocation to retrieve data.
> 
> The follow on patches introduce the use of this library for AM57x
> platform support. AM335x/AM43xx cleanups need to first ensure usage of
> omap_common prior to switch over to this generic solution.
> 
> Signed-off-by: Lokesh Vutla 
> Signed-off-by: Steve Kipisz 
> ---
> v3 Based on:
>  master  83bf0057 arm: at91: reworked meesc board support
> 
> Changes in v3 (since v2):
>  - Create a new directory board/ti/common for code common to TI board
>  - Move the EEPROM code to the new directory
>  - Move the inline code that access the EEPROM data from omap_common.h
>to new files in the common directory
> 
> v2:  http://marc.info/?t=14465534481&r=1&w=2
>(mailing list squashed original submission)
> 
> Changes in v2:
>  - New Patch
> 
>  arch/arm/include/asm/omap_common.h |   5 +-
>  board/ti/am57xx/Makefile   |   2 +
>  board/ti/common/board.c|  54 ++
>  board/ti/common/board.h| 117 +
>  board/ti/common/ti-i2c-eeprom.c| 148 
> +
>  5 files changed, 325 insertions(+), 1 deletion(-)
>  create mode 100644 board/ti/common/board.c
>  create mode 100644 board/ti/common/board.h
>  create mode 100644 board/ti/common/ti-i2c-eeprom.c
> 
> diff --git a/arch/arm/include/asm/omap_common.h 
> b/arch/arm/include/asm/omap_common.h
> index d773b0430ad4..f6d929b15e82 100644
> --- a/arch/arm/include/asm/omap_common.h
> +++ b/arch/arm/include/asm/omap_common.h
> @@ -713,7 +713,9 @@ static inline u8 is_dra72x(void)
>  #define OMAP_SRAM_SCRATCH_VCORES_PTR(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
>  #define OMAP_SRAM_SCRATCH_SYS_CTRL   (SRAM_SCRATCH_SPACE_ADDR + 0x20)
>  #define OMAP_SRAM_SCRATCH_BOOT_PARAMS(SRAM_SCRATCH_SPACE_ADDR + 0x24)
> -#define OMAP5_SRAM_SCRATCH_SPACE_END (SRAM_SCRATCH_SPACE_ADDR + 0x28)
> +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
> +#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
> +#define OMAP_SRAM_SCRATCH_SPACE_END  (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
>  
>  /* Boot parameters */
>  #define DEVICE_DATA_OFFSET   0x18
> @@ -728,4 +730,5 @@ static inline u8 is_dra72x(void)
>  u32 omap_sys_boot_device(void);
>  #endif
>  
> +

Umm.. I think you should not have this.


>  #endif /* _OMAP_COMMON_H_ */
> diff --git a/board/ti/am57xx/Makefile b/board/ti/am57xx/Makefile
> index 5cd6873f5e97..9d85d31b2cf1 100644
> --- a/board/ti/am57xx/Makefile
> +++ b/board/ti/am57xx/Makefile
> @@ -6,3 +6,5 @@
>  #
>  
>  obj-y:= board.o
> +obj-y+= ../common/board.o

> +obj-${CONFIG_I2C} += ../common/ti-i2c-eeprom.o
> diff --git a/board/ti/common/board.c b/board/ti/common/board.c
> new file mode 100644
> index ..1c02e44916f0
> --- /dev/null
> +++ b/board/ti/common/board.c
> @@ -0,0 +1,54 @@
> +/*
> + * board.c

please drop this.
> + *
> + * Common board functions for TI AM based boards.
why just AM? it is called board.c and can extend to dra7 platforms
as well. why not call merge this with the eeprom code and call it
board-detect.c ?

> + *
> + * Copyright (C) 2015, Texas Instruments Incorporated - http://www.ti.com
> + *
> + * Author: Steven Kipisz 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +
> +#include "board.h"
> +
> +/**
> + * board_am_is() - Generic Board detection logic
> + * @name_tag:Tag used in eeprom for the board
> + *

Document that this is for AM* TI EVM platforms

> + * Return: false if board information does not match OR eeprom was'nt read.
> + *  true otherwise
> + */
> +bool board_am_is(char *name_tag)

I dont see a usage o

[U-Boot] Fwd: Please pull u-boot-mpc85xx master

[York Sun]

Oops. Clicked send button too fast. Adding mailing list.


 Forwarded Message 
Subject: Please pull u-boot-mpc85xx master
Date: Wed, 4 Nov 2015 15:24:09 -0800
From: York Sun 
To: Tom Rini 

Tom,

The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313:

  arm: at91: reworked meesc board support (2015-11-03 14:21:32 +0100)

are available in the git repository at:

  git://git.denx.de/u-boot-mpc85xx.git master

for you to fetch changes up to 87e29878caba758ed3e09e9912ac8eb6dfc55f39:

  mpc85xx: Add support for the Varisys Cyrus board (2015-11-04 15:19:34 -0800)


Andy Fleming (2):
  rtc: Add MCP79411 support to DS1307 rtc driver
  mpc85xx: Add support for the Varisys Cyrus board

 arch/powerpc/cpu/mpc85xx/Kconfig |4 +
 board/varisys/common/Makefile|   23 ++
 board/varisys/common/eeprom.h|6 +
 board/varisys/common/sys_eeprom.c|  498 
 board/varisys/cyrus/Kconfig  |   12 +
 board/varisys/cyrus/MAINTAINERS  |7 +
 board/varisys/cyrus/Makefile |8 +
 board/varisys/cyrus/README   |   19 ++
 board/varisys/cyrus/cyrus.c  |  116 +++
 board/varisys/cyrus/cyrus.h  |   11 +
 board/varisys/cyrus/ddr.c|  188 +++
 board/varisys/cyrus/eth.c|  100 ++
 board/varisys/cyrus/law.c|   27 ++
 board/varisys/cyrus/pbi.cfg  |   35 ++
 board/varisys/cyrus/pci.c|   23 ++
 board/varisys/cyrus/rcw_p5020_v2.cfg |   11 +
 board/varisys/cyrus/rcw_p5040.cfg|   11 +
 board/varisys/cyrus/tlb.c|  106 ++
 configs/Cyrus_P5020_defconfig|9 +
 configs/Cyrus_P5040_defconfig|9 +
 drivers/rtc/Makefile |2 +-
 drivers/rtc/ds1307.c |   34 ++
 include/configs/cyrus.h  |  587 ++
 23 files changed, 1845 insertions(+), 1 deletion(-)
 create mode 100644 board/varisys/common/Makefile
 create mode 100644 board/varisys/common/eeprom.h
 create mode 100644 board/varisys/common/sys_eeprom.c
 create mode 100644 board/varisys/cyrus/Kconfig
 create mode 100644 board/varisys/cyrus/MAINTAINERS
 create mode 100644 board/varisys/cyrus/Makefile
 create mode 100644 board/varisys/cyrus/README
 create mode 100644 board/varisys/cyrus/cyrus.c
 create mode 100644 board/varisys/cyrus/cyrus.h
 create mode 100644 board/varisys/cyrus/ddr.c
 create mode 100644 board/varisys/cyrus/eth.c
 create mode 100644 board/varisys/cyrus/law.c
 create mode 100644 board/varisys/cyrus/pbi.cfg
 create mode 100644 board/varisys/cyrus/pci.c
 create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
 create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
 create mode 100644 board/varisys/cyrus/tlb.c
 create mode 100644 configs/Cyrus_P5020_defconfig
 create mode 100644 configs/Cyrus_P5040_defconfig
 create mode 100644 include/configs/cyrus.h

Thanks.

York


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Re: [U-Boot] [PATCH v3] mpc85xx: Add support for the Varisys Cyrus board

[York Sun]

On 11/04/2015 01:48 PM, Andy Fleming wrote:
> This board runs a P5020 or P5040 chip, and utilizes
> an EEPROM with similar formatting to the Freescale P5020DS.
> 
> Large amounts of this code were developed by
> Adrian Cox 
> 
> Signed-off-by: Andy Fleming 
> ---
> v3:
>   * Clarified sys_eeprom.c comments
>   * Removed errant whitespace
>   * Added MAINTAINERS file
> v2:
>   * Cleaned up sys_eeprom.c
>   * Removed redundant CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD

Applied to u-boot-mpc85xx, awaiting upstream.

York
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Re: [U-Boot] [PATCH 1/2] rtc: Add MCP79411 support to DS1307 rtc driver

[York Sun]

On 10/21/2015 04:59 PM, Andy Fleming wrote:
> The code is from Adrian Cox, and is patterned after similar
> support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> chip is used on the Cyrus board from Varisys.
> 
> Signed-off-by: Andy Fleming 
> ---
>  drivers/rtc/Makefile |  2 +-
>  drivers/rtc/ds1307.c | 34 ++
>  2 files changed, 35 insertions(+), 1 deletion(-)

Applied to u-boot-mpc85xx, awaiting upstream.

York

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Re: [U-Boot] [PATCH 1/2] rtc: Add MCP79411 support to DS1307 rtc driver

[Tom Rini]

On Wed, Nov 04, 2015 at 02:34:42PM -0800, York Sun wrote:
> 
> 
> On 10/21/2015 04:59 PM, Andy Fleming wrote:
> > The code is from Adrian Cox, and is patterned after similar
> > support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> > chip is used on the Cyrus board from Varisys.
> > 
> > Signed-off-by: Andy Fleming 
> > ---
> >  drivers/rtc/Makefile |  2 +-
> >  drivers/rtc/ds1307.c | 34 ++
> >  2 files changed, 35 insertions(+), 1 deletion(-)
> 
> Tom,
> 
> We don't have a custodian for RTC, do we? Shall I take this in with Andy's 
> other
> patch?

Works for me, thanks!

-- 
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Re: [U-Boot] [PATCH 1/2] rtc: Add MCP79411 support to DS1307 rtc driver

[York Sun]

On 10/21/2015 04:59 PM, Andy Fleming wrote:
> The code is from Adrian Cox, and is patterned after similar
> support in Linux (drivers/rtc/rtc-ds1307.c:1121-1135). This
> chip is used on the Cyrus board from Varisys.
> 
> Signed-off-by: Andy Fleming 
> ---
>  drivers/rtc/Makefile |  2 +-
>  drivers/rtc/ds1307.c | 34 ++
>  2 files changed, 35 insertions(+), 1 deletion(-)

Tom,

We don't have a custodian for RTC, do we? Shall I take this in with Andy's other
patch?

York

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Re: [U-Boot] [GIT PULL] Zynq changes

[Tom Rini]

On Wed, Nov 04, 2015 at 03:48:33PM +0100, Michal Simek wrote:

> Hi Tom,
> 
> please pull these patches to your tree. They are enabling DM for Zynq
> and ZynqMP targets and also they are fixing compilation error which is
> currently in the tree.
> Also as I have promised I am removing zc70x target from u-boot and only
> zc702 and zc706 will be used.
> 
> There will be some others pull request for fixing stuff when they are
> properly reviewed.
> 
> Thanks,
> Michal
> 
> 
> The following changes since commit 83bf005710a1e01341de5e2f44a3ce082717e313:
> 
>   arm: at91: reworked meesc board support (2015-11-03 14:21:32 +0100)
> 
> are available in the git repository at:
> 
>   git://www.denx.de/git/u-boot-microblaze.git zynq
> 
> for you to fetch changes up to 1e370ef7e7a4fb0b801a848e190c01e06a2fbfce:
> 
>   ARM: zynq: Remove zc70x target (2015-11-04 14:49:53 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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[U-Boot] [PATCH v3 3/5] ARM: omap-common: Add standard access for board description EEPROM

[Steve Kipisz]

From: Lokesh Vutla 

Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.

The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
However, DRA-7* EVMs, OMAP4SDP use a modified format.

We hence introduce logic which is generic between these platforms
without enforcing any specific format. This allows the boards to use the
relevant format for operations that they might choose.

This module will compile for all TI SoC based boards when I2C is enabled,
even non-TI boards that do not have the EEPROM. If the functions are not
used, they will not be linked in.

It is important to note that this logic is fundamental to the board
configuration process such as DDR configuration which is needed in
SPL, hence cannot be part of the standard u-boot driver model (which
is available later in the process). Hence, to aid efficiency, the
eeprom contents are copied over to SRAM scratchpad memory area at the
first invocation to retrieve data.

The follow on patches introduce the use of this library for AM57x
platform support. AM335x/AM43xx cleanups need to first ensure usage of
omap_common prior to switch over to this generic solution.

Signed-off-by: Lokesh Vutla 
Signed-off-by: Steve Kipisz 
---
v3 Based on:
 master  83bf0057 arm: at91: reworked meesc board support

Changes in v3 (since v2):
 - Create a new directory board/ti/common for code common to TI board
 - Move the EEPROM code to the new directory
 - Move the inline code that access the EEPROM data from omap_common.h
   to new files in the common directory

v2:  http://marc.info/?t=14465534481&r=1&w=2
   (mailing list squashed original submission)

Changes in v2:
 - New Patch

 arch/arm/include/asm/omap_common.h |   5 +-
 board/ti/am57xx/Makefile   |   2 +
 board/ti/common/board.c|  54 ++
 board/ti/common/board.h| 117 +
 board/ti/common/ti-i2c-eeprom.c| 148 +
 5 files changed, 325 insertions(+), 1 deletion(-)
 create mode 100644 board/ti/common/board.c
 create mode 100644 board/ti/common/board.h
 create mode 100644 board/ti/common/ti-i2c-eeprom.c

diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index d773b0430ad4..f6d929b15e82 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -713,7 +713,9 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL (SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS  (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP5_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#define OMAP_SRAM_SCRATCH_SPACE_END(OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET 0x18
@@ -728,4 +730,5 @@ static inline u8 is_dra72x(void)
 u32 omap_sys_boot_device(void);
 #endif
 
+
 #endif /* _OMAP_COMMON_H_ */
diff --git a/board/ti/am57xx/Makefile b/board/ti/am57xx/Makefile
index 5cd6873f5e97..9d85d31b2cf1 100644
--- a/board/ti/am57xx/Makefile
+++ b/board/ti/am57xx/Makefile
@@ -6,3 +6,5 @@
 #
 
 obj-y  := board.o
+obj-y  += ../common/board.o
+obj-${CONFIG_I2C} += ../common/ti-i2c-eeprom.o
diff --git a/board/ti/common/board.c b/board/ti/common/board.c
new file mode 100644
index ..1c02e44916f0
--- /dev/null
+++ b/board/ti/common/board.c
@@ -0,0 +1,54 @@
+/*
+ * board.c
+ *
+ * Common board functions for TI AM based boards.
+ *
+ * Copyright (C) 2015, Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Author: Steven Kipisz 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+
+#include "board.h"
+
+/**
+ * board_am_is() - Generic Board detection logic
+ * @name_tag:  Tag used in eeprom for the board
+ *
+ * Return: false if board information does not match OR eeprom was'nt read.
+ *true otherwise
+ */
+bool board_am_is(char *name_tag)
+{
+   struct ti_am_eeprom *ep = TI_AM_EEPROM_DATA;
+
+   if (ep->header != TI_EEPROM_HEADER_MAGIC)
+   return false;
+   return !strncmp(ep->name, name_tag, TI_EEPROM_HDR_NAME_LEN);
+}
+
+/**
+ * board_am_rev_is() - Compare board revision
+ * @rev_tag:   Revision tag to check in eeprom
+ * @cmp_len:   How many chars to compare?
+ *
+ * NOTE: revision information is often messed up (hence the str len match) :(
+ *
+ * Return: false if board information does not match OR eeprom was'nt read.
+ *true otherwise
+ */
+bool board_am_rev_is(char *rev_tag, in

[U-Boot] [PATCH v3 5/5] board: ti: AM57xx: Add detection logic for AM57xx-evm

[Steve Kipisz]

Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).

The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.

Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.

NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.

This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.

Signed-off-by: Steve Kipisz 
---
v3 Based on:
 master 83bf0057 arm: at91: reworked meesc board support

Build testing: MAKEALL -s omap4 -s omap5 (no warning/build errors)
Boot Testing:
am57xx_evm_nodt_config: http://pastebin.ubuntu.com/13105264/

Changes in v3 (since v2):
 - Rename is_xxx to board_is_xxx
 - Remove usage of default_name and default to beagle_x15 if there
   are errors reading the EEPROM

v2:  http://marc.info/?t=14465534463&r=1&w=2
  (mailing list squashed original submission)

Build testing: MAKEALL -s omap4 -s omap5 (no warnings/build errors)
Boot Testing:
am57xx_evm_nodt_config: http://pastebin.ubuntu.com/13039296/
beagle_x15_config: http://pastebin.ubuntu.com/13039331/

Changes in v2 (since v1):
- move the board detection code into the new routine
  do_board_detect
- eliminate board.h and move the ix_xxx into board.c
- redo commit message to be more clear

v1:  http://marc.info/?t=14460800792&r=1&w=2
 http://marc.info/?t=14460800794&r=1&w=2
(mailing list squashed original submission)


 board/ti/am57xx/board.c  | 52 
 include/configs/am57xx_evm.h |  4 
 2 files changed, 56 insertions(+)

diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
index 042f9ab1965a..4aa8424e975e 100644
--- a/board/ti/am57xx/board.c
+++ b/board/ti/am57xx/board.c
@@ -31,6 +31,10 @@
 #include 
 
 #include "mux_data.h"
+#include "../common/board.h"
+
+#define board_is_x15() board_am_is("BBRDX15_")
+#define board_is_am572x_evm()  board_am_is("AM572PM_")
 
 #ifdef CONFIG_DRIVER_TI_CPSW
 #include 
@@ -246,6 +250,52 @@ struct vcores_data beagle_x15_volts = {
.iva.pmic   = &tps659038,
 };
 
+#ifdef CONFIG_SPL_BUILD
+/* No env to setup for SPL */
+static inline void setup_board_eeprom_env(void) { }
+
+/* Override function to read eeprom information */
+void do_board_detect(void)
+{
+   struct ti_am_eeprom *ep;
+   int rc;
+
+   rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
+ CONFIG_EEPROM_CHIP_ADDRESS, &ep);
+   if (rc)
+   printf("ti_i2c_eeprom_init failed %d\n", rc);
+}
+
+#else  /* CONFIG_SPL_BUILD */
+
+static void setup_board_eeprom_env(void)
+{
+   char *name = "beagle_x15";
+   int rc;
+   struct ti_am_eeprom_printable p;
+
+   rc = ti_i2c_eeprom_am_get_print(CONFIG_EEPROM_BUS_ADDRESS,
+   CONFIG_EEPROM_CHIP_ADDRESS, &p);
+   if (rc) {
+   printf("Invalid EEPROM data(@0x%p). Default to X15\n",
+  TI_AM_EEPROM_DATA);
+   goto invalid_eeprom;
+   }
+
+   if (board_is_am572x_evm())
+   name = "am57xx_evm";
+   else
+   printf("Unidentified board claims %s in eeprom header\n",
+  p.name);
+
+invalid_eeprom:
+   set_board_info_env(name, p.version, p.serial);
+}
+
+/* Eeprom is alread read by SPL.. nothing more to do here.. */
+
+#endif /* CONFIG_SPL_BUILD */
+
 void hw_data_init(void)
 {
*prcm = &dra7xx_prcm;
@@ -265,6 +315,8 @@ int board_init(void)
 int board_late_init(void)
 {
init_sata(0);
+   setup_board_eeprom_env();
+
/*
 * DEV_CTRL.DEV_ON = 1 please - else palmas switches off in 8 seconds
 * This is the POWERHOLD-in-Low behavior.
diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h
index 6308cab8e680..1fffdb18fbcd 100644
--- a/include/configs/am57xx_evm.h
+++ b/include/configs/am57xx_evm.h
@@ -88,4 +88,8 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
 
+/* EEPROM */
+#define CONFIG_EEPROM_CHIP_ADDRESS 0x50
+#define CONFIG_EEPROM_BUS_ADDRESS 0
+
 #endif /* __CONFIG_AM57XX_EVM_H */
-- 
1.9.1

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[U-Boot] [PATCH v3 2/5] ARM: OMAP4/5: Centralize gpi2c_init

[Steve Kipisz]

Centralize gpi2c_init into omap_common from the sys_proto header so
that the information can be reused across SoCs.

Signed-off-by: Steve Kipisz 
Reviewed-by: Tom Rini 
---
v3 Based on:
 master 83bf0057 arm: at91: reworked meesc board support

Changes in v3 (since v2):
 - No changes

v2:  http://marc.info/?t=14465534467&r=1&w=2
   (mailing list squashed original submission)

Changes in v2:
 - New Patch

 arch/arm/include/asm/arch-omap4/sys_proto.h | 1 -
 arch/arm/include/asm/arch-omap5/sys_proto.h | 1 -
 arch/arm/include/asm/omap_common.h  | 3 +++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 71e3d776aa0d..26e9a194f036 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -51,7 +51,6 @@ void save_omap_boot_params(void);
 void init_omap_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
-void gpi2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index b9e09e7c52a8..18902628739b 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -62,7 +62,6 @@ void save_omap_boot_params(void);
 void init_omap_revision(void);
 void do_io_settings(void);
 void sri2c_init(void);
-void gpi2c_init(void);
 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
 u32 warm_reset(void);
 void force_emif_self_refresh(void);
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index d7b81c101b79..d773b0430ad4 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -617,6 +617,9 @@ void disable_edma3_clocks(void);
 
 void omap_die_id(unsigned int *die_id);
 
+/* Initialize general purpose I2C(0) on the SoC */
+void gpi2c_init(void);
+
 /* ABB */
 #define OMAP_ABB_NOMINAL_OPP   0
 #define OMAP_ABB_FAST_OPP  1
-- 
1.9.1

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[U-Boot] [PATCH v3 4/5] ARM: OMAP4/5: Add generic board detection hook

[Steve Kipisz]

Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.

NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.

Signed-off-by: Steve Kipisz 
Reviewed-by: Tom Rini 
---
v3 Based on:
 master 83bf0057 arm: at91: reworked meesc board support

Changes in v3 (since v2):
 - No changes

v2:  http://marc.info/?t=14465534466&r=1&w=2
  (mailing list squashed original submission)

Changes in v2:
 - New patch

 arch/arm/cpu/armv7/omap-common/hwinit-common.c | 11 +++
 arch/arm/include/asm/arch-omap4/sys_proto.h|  1 +
 arch/arm/include/asm/arch-omap5/sys_proto.h|  1 +
 3 files changed, 13 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c 
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 91f2dead364b..9e9376d0e6e6 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -97,6 +97,16 @@ int arch_cpu_init(void)
 }
 #endif /* CONFIG_ARCH_CPU_INIT */
 
+/**
+ * do_board_detect() - Detect board description
+ *
+ * Function to detect board description. This is expected to be
+ * overridden in the SoC family board file where desired.
+ */
+void __weak do_board_detect(void)
+{
+}
+
 /*
  * Routine: s_init
  * Description: Does early system init of watchdog, muxing,  andclocks
@@ -128,6 +138,7 @@ void s_init(void)
do_io_settings();
 #endif
setup_early_clocks();
+   do_board_detect();
prcm_init();
 }
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index 26e9a194f036..fbb52093c65a 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -39,6 +39,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void setup_early_clocks(void);
 void prcm_init(void);
+void do_board_detect(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 18902628739b..23a33cb233bb 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -50,6 +50,7 @@ u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 void setup_early_clocks(void);
 void prcm_init(void);
+void do_board_detect(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
 u32 get_sys_clk_freq(void);
-- 
1.9.1

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[U-Boot] [PATCH v3 0/5] ARM: omap-common: Add board detection support for TI EVMs

[Steve Kipisz]

Several TI EVMs have onboard EEPROM that contain board description
information. The onboard EEPROM on Beaglebone, Beaglebone Black, AM335x
EVM, AM43x EVM, AM57xx EVM, Beagleboard-x15 all share the same format.

This series of patches introduces code which is generic among these
platforms. The boards can use the data for any operations they might
choose.

Lokesh Vutla (1):
  ARM: omap-common: Add standard access for board description EEPROM

Steve Kipisz (4):
  ARM: OMAP4/5: Centralize early clock initialization
  ARM: OMAP4/5: Centralize gpi2c_init
  ARM: OMAP4/5: Add generic board detection hook
  board: ti: AM57xx: Add detection logic for AM57xx-evm

 arch/arm/cpu/armv7/omap-common/clocks-common.c |  21 +++-
 arch/arm/cpu/armv7/omap-common/hwinit-common.c |  14 ++-
 arch/arm/include/asm/arch-omap4/sys_proto.h|   4 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h|   4 +-
 arch/arm/include/asm/omap_common.h |   8 +-
 board/ti/am57xx/Makefile   |   2 +
 board/ti/am57xx/board.c|  52 +
 board/ti/common/board.c|  54 +
 board/ti/common/board.h| 117 +++
 board/ti/common/ti-i2c-eeprom.c| 148 +
 include/configs/am57xx_evm.h   |   4 +
 11 files changed, 419 insertions(+), 9 deletions(-)
 create mode 100644 board/ti/common/board.c
 create mode 100644 board/ti/common/board.h
 create mode 100644 board/ti/common/ti-i2c-eeprom.c

-- 
1.9.1

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[U-Boot] [PATCH v3 1/5] ARM: OMAP4/5: Centralize early clock initialization

[Steve Kipisz]

Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.

By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.

As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.

NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings

Signed-off-by: Steve Kipisz 
Reviewed-by: Tom Rini http://marc.info/?t=14465536301&r=1&w=2
  (mailing list squashed original submission)

Changes in v2:
 - New patch

 arch/arm/cpu/armv7/omap-common/clocks-common.c | 21 +++--
 arch/arm/cpu/armv7/omap-common/hwinit-common.c |  3 +--
 arch/arm/include/asm/arch-omap4/sys_proto.h|  2 +-
 arch/arm/include/asm/arch-omap5/sys_proto.h|  2 +-
 4 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c 
b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index e28b79568d1d..367d224361be 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -769,7 +769,7 @@ void lock_dpll(u32 const base)
wait_for_lock(base);
 }
 
-void setup_clocks_for_console(void)
+static void setup_clocks_for_console(void)
 {
/* Do not add any spl_debug prints in this function */
clrsetbits_le32((*prcm)->cm_l4per_clkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
@@ -853,14 +853,31 @@ void do_disable_clocks(u32 const *clk_domains,
disable_clock_domain(clk_domains[i]);
 }
 
-void prcm_init(void)
+/**
+ * setup_early_clocks() - Setup early clocks needed for SoC
+ *
+ * Setup clocks for console, SPL basic initialization clocks and initialize
+ * the timer. This is invoked prior prcm_init.
+ */
+void setup_early_clocks(void)
 {
switch (omap_hw_init_context()) {
case OMAP_INIT_CONTEXT_SPL:
case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+   setup_clocks_for_console();
enable_basic_clocks();
timer_init();
+   /* Fall through */
+   }
+}
+
+void prcm_init(void)
+{
+   switch (omap_hw_init_context()) {
+   case OMAP_INIT_CONTEXT_SPL:
+   case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
+   case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
scale_vcores(*omap_vcores);
setup_dplls();
setup_warmreset_time();
diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c 
b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
index 80794f9c611a..91f2dead364b 100644
--- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c
+++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c
@@ -125,10 +125,9 @@ void s_init(void)
set_mux_conf_regs();
 #ifdef CONFIG_SPL_BUILD
srcomp_enable();
-   setup_clocks_for_console();
-
do_io_settings();
 #endif
+   setup_early_clocks();
prcm_init();
 }
 
diff --git a/arch/arm/include/asm/arch-omap4/sys_proto.h 
b/arch/arm/include/asm/arch-omap4/sys_proto.h
index f30f86539130..71e3d776aa0d 100644
--- a/arch/arm/include/asm/arch-omap4/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap4/sys_proto.h
@@ -37,7 +37,7 @@ void do_set_mux(u32 base, struct pad_conf_entry const *array, 
int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h 
b/arch/arm/include/asm/arch-omap5/sys_proto.h
index 7fcb78389403..b9e09e7c52a8 100644
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ b/arch/arm/include/asm/arch-omap5/sys_proto.h
@@ -48,7 +48,7 @@ void do_set_mux32(u32 base, struct pad_conf_entry const 
*array, int size);
 void set_muxconf_regs_essential(void);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
-void setup_clocks_for_console(void);
+void setup_early_clocks(void);
 void prcm_init(void);
 void bypass_dpll(u32 const base);
 void freq_update_core(void);
-- 
1.9.1

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[U-Boot] [PATCH] Fix trini email in the get_maintainer.pl script

[Andy Fleming]

Looks like one spot got missed. Probably due to the backslash.

Signed-off-by: Andy Fleming 
---
Noticed this while reading up on the MAINTAINERS files

 scripts/get_maintainer.pl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index 368a20e..4707dfd 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -62,7 +62,7 @@ my %commit_author_hash;
 my %commit_signer_hash;
 
 my @penguin_chief = ();
-push(@penguin_chief, "Tom Rini:trini\@ti.com");
+push(@penguin_chief, "Tom Rini:trini\@konsulko.com");
 
 my @penguin_chief_names = ();
 foreach my $chief (@penguin_chief) {
-- 
1.9.1

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[U-Boot] [PATCH v3] mpc85xx: Add support for the Varisys Cyrus board

[Andy Fleming]

This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.

Large amounts of this code were developed by
Adrian Cox 

Signed-off-by: Andy Fleming 
---
v3:
* Clarified sys_eeprom.c comments
* Removed errant whitespace
* Added MAINTAINERS file
v2:
* Cleaned up sys_eeprom.c
* Removed redundant CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD

 arch/powerpc/cpu/mpc85xx/Kconfig |   4 +
 board/varisys/common/Makefile|  23 ++
 board/varisys/common/eeprom.h|   6 +
 board/varisys/common/sys_eeprom.c| 498 +
 board/varisys/cyrus/Kconfig  |  12 +
 board/varisys/cyrus/MAINTAINERS  |   7 +
 board/varisys/cyrus/Makefile |   8 +
 board/varisys/cyrus/README   |  19 ++
 board/varisys/cyrus/cyrus.c  | 116 +++
 board/varisys/cyrus/cyrus.h  |  11 +
 board/varisys/cyrus/ddr.c| 188 +++
 board/varisys/cyrus/eth.c| 100 ++
 board/varisys/cyrus/law.c|  27 ++
 board/varisys/cyrus/pbi.cfg  |  35 +++
 board/varisys/cyrus/pci.c|  23 ++
 board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
 board/varisys/cyrus/rcw_p5040.cfg|  11 +
 board/varisys/cyrus/tlb.c| 106 +++
 configs/Cyrus_P5020_defconfig|   9 +
 configs/Cyrus_P5040_defconfig|   9 +
 include/configs/cyrus.h  | 587 +++
 21 files changed, 1810 insertions(+)
 create mode 100644 board/varisys/common/Makefile
 create mode 100644 board/varisys/common/eeprom.h
 create mode 100644 board/varisys/common/sys_eeprom.c
 create mode 100644 board/varisys/cyrus/Kconfig
 create mode 100644 board/varisys/cyrus/MAINTAINERS
 create mode 100644 board/varisys/cyrus/Makefile
 create mode 100644 board/varisys/cyrus/README
 create mode 100644 board/varisys/cyrus/cyrus.c
 create mode 100644 board/varisys/cyrus/cyrus.h
 create mode 100644 board/varisys/cyrus/ddr.c
 create mode 100644 board/varisys/cyrus/eth.c
 create mode 100644 board/varisys/cyrus/law.c
 create mode 100644 board/varisys/cyrus/pbi.cfg
 create mode 100644 board/varisys/cyrus/pci.c
 create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
 create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
 create mode 100644 board/varisys/cyrus/tlb.c
 create mode 100644 configs/Cyrus_P5020_defconfig
 create mode 100644 configs/Cyrus_P5040_defconfig
 create mode 100644 include/configs/cyrus.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index ae0823a..0b89157 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -149,6 +149,9 @@ config TARGET_XPEDITE550X
 config TARGET_UCP1020
bool "Support uCP1020"
 
+config TARGET_CYRUS
+   bool "Support Varisys Cyrus"
+
 endchoice
 
 source "board/freescale/b4860qds/Kconfig"
@@ -185,6 +188,7 @@ source "board/gdsys/p1022/Kconfig"
 source "board/keymile/kmp204x/Kconfig"
 source "board/sbc8548/Kconfig"
 source "board/socrates/Kconfig"
+source "board/varisys/cyrus/Kconfig"
 source "board/xes/xpedite520x/Kconfig"
 source "board/xes/xpedite537x/Kconfig"
 source "board/xes/xpedite550x/Kconfig"
diff --git a/board/varisys/common/Makefile b/board/varisys/common/Makefile
new file mode 100644
index 000..1e6dcbb
--- /dev/null
+++ b/board/varisys/common/Makefile
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+MINIMAL=
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_SPL_INIT_MINIMAL
+MINIMAL=y
+endif
+endif
+
+ifdef MINIMAL
+# necessary to create built-in.o
+obj- := __dummy__.o
+else
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ID_EEPROM)+= sys_eeprom.o
+endif
+endif
diff --git a/board/varisys/common/eeprom.h b/board/varisys/common/eeprom.h
new file mode 100644
index 000..004816a
--- /dev/null
+++ b/board/varisys/common/eeprom.h
@@ -0,0 +1,6 @@
+/* EEPROM init functions for Cyrus */
+
+
+void init_eeprom(int bus_num, int addr, int addr_len);
+void mac_read_from_fixed_id(void);
+int mac_read_from_eeprom_common(void);
diff --git a/board/varisys/common/sys_eeprom.c 
b/board/varisys/common/sys_eeprom.c
new file mode 100644
index 000..b55ab81
--- /dev/null
+++ b/board/varisys/common/sys_eeprom.c
@@ -0,0 +1,498 @@
+/*
+ * Based on board/freescale/common/sys_eeprom.c
+ * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
+ *
+ * This defines the API for storing board information in the
+ * eeprom. It has been adapted from an earlier version of the
+ * Freescale API, but has a number of key differences. Because
+ * the two APIs are independent and may diverge further, the
+ * Varisys version of the API is implemented separately here.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include "eeprom.h"
+
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
+#define MAX_NUM_PORTS  CONFIG_SYS_I2C_EE

Re: [U-Boot] [PATCH v2] mpc85xx: Add support for the Varisys Cyrus board

[Andy Fleming]

On Wed, Nov 4, 2015 at 12:39 PM, York Sun  wrote:
>
>
> On 11/03/2015 03:30 PM, Andy Fleming wrote:
>> This board runs a P5020 or P5040 chip, and utilizes
>> an EEPROM with similar formatting to the Freescale P5020DS.
>>
>> Large amounts of this code were developed by
>> Adrian Cox 
>>
>> Signed-off-by: Andy Fleming 
>> ---
>> v2:
>>   * Cleaned up sys_eeprom.c
>>   * Removed CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD
>
> Why do you want to remove CONFIG_SYS_GENERIC_BOARD? We are dropping 
> non-generic
> board.

Sorry, my comment was misleading. I didn't disable
CONFIG_SYS_GENERIC_BOARD. I removed it from the config file because
this patch made it the default:

commit 09f3ca3dd53b671b009ddc4e1dad669c280094f0
Author: Masahiro Yamada 
Date:   Tue Oct 20 21:09:06 2015 +0900

arm, powerpc: select SYS_GENERIC_BOARD

Otherwise, u-boot doesn't build. Same thing is true for
CONFIG_CMD_ELF. Didn't disable it, just deleted the redundant config.

>
>>
>>  arch/powerpc/cpu/mpc85xx/Kconfig |   4 +
>>  board/varisys/common/Makefile|  23 ++
>>  board/varisys/common/eeprom.h|   6 +
>>  board/varisys/common/sys_eeprom.c| 500 +
>>  board/varisys/cyrus/Kconfig  |  13 +
>>  board/varisys/cyrus/Makefile |   8 +
>>  board/varisys/cyrus/README   |  21 ++
>>  board/varisys/cyrus/cyrus.c  | 116 +++
>>  board/varisys/cyrus/cyrus.h  |  11 +
>>  board/varisys/cyrus/ddr.c| 188 +++
>>  board/varisys/cyrus/eth.c| 100 ++
>>  board/varisys/cyrus/law.c|  27 ++
>>  board/varisys/cyrus/pbi.cfg  |  35 +++
>>  board/varisys/cyrus/pci.c|  23 ++
>>  board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
>>  board/varisys/cyrus/rcw_p5040.cfg|  11 +
>>  board/varisys/cyrus/tlb.c| 106 +++
>>  configs/Cyrus_P5020_defconfig|   9 +
>>  configs/Cyrus_P5040_defconfig|   9 +
>>  include/configs/cyrus.h  | 588 
>> +++
>>  20 files changed, 1809 insertions(+)
>>  create mode 100644 board/varisys/common/Makefile
>>  create mode 100644 board/varisys/common/eeprom.h
>>  create mode 100644 board/varisys/common/sys_eeprom.c
>>  create mode 100644 board/varisys/cyrus/Kconfig
>>  create mode 100644 board/varisys/cyrus/Makefile
>>  create mode 100644 board/varisys/cyrus/README
>>  create mode 100644 board/varisys/cyrus/cyrus.c
>>  create mode 100644 board/varisys/cyrus/cyrus.h
>>  create mode 100644 board/varisys/cyrus/ddr.c
>>  create mode 100644 board/varisys/cyrus/eth.c
>>  create mode 100644 board/varisys/cyrus/law.c
>>  create mode 100644 board/varisys/cyrus/pbi.cfg
>>  create mode 100644 board/varisys/cyrus/pci.c
>>  create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
>>  create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
>>  create mode 100644 board/varisys/cyrus/tlb.c
>>  create mode 100644 configs/Cyrus_P5020_defconfig
>>  create mode 100644 configs/Cyrus_P5040_defconfig
>>  create mode 100644 include/configs/cyrus.h
>
> Please add MAINTAINERS file.


Will do.


>
> 
>
>> diff --git a/board/varisys/common/sys_eeprom.c 
>> b/board/varisys/common/sys_eeprom.c
>> new file mode 100644
>> index 000..086fad2
>> --- /dev/null
>> +++ b/board/varisys/common/sys_eeprom.c
>> @@ -0,0 +1,500 @@
>> +/*
>> + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
>> + * York Sun (york...@freescale.com)
>> + * Haiying Wang (haiying.w...@freescale.com)
>> + * Timur Tabi (ti...@freescale.com)
>> + *
>> + * This defines the API for storing board information in the
>> + * eeprom. It has been adapted from an earlier version of the
>> + * Freescale code for doing the same thing. Therefore it is
>> + * nearly identical to the Freescale code, but is intended for
>> + * use with Varisys-produced boards.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +#include "eeprom.h"
>> +
>> +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
>> +#define MAX_NUM_PORTSCONFIG_SYS_I2C_EEPROM_NXID_MAC
>> +#else
>> +#define MAX_NUM_PORTS8
>> +#endif
>> +#define NXID_VERSION 0
>> +
>> +/**
>> + * static eeprom: EEPROM layout for NXID formats
>> + *
>> + * See Freescale application note AN3638 for details.
>> + */
>
> This comment and file header still implies this file follows Freescale EEPROM
> spec. I think additional comment is needed to state the difference.
>
> There are several blank lines added to the end of files.

I'll fix these and send a new version today.

Andy
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Re: [U-Boot] [PATCH][v2] armv8: ls2085a: Add workaround of errata A009635

[York Sun]

On 11/03/2015 11:24 PM, Prabhakar Kushwaha wrote:
> If the core runs at higher than x3 speed of the platform, there is
> possiblity about sev instruction to getting missed by other cores. 
> This is because of SoC Run Control block may not able to sample
> the EVENTI(Sev) signals.
> 
> Configure Run Control and EPU to periodically send out EVENTI signals to
> wake up A57 cores.
> 
> Signed-off-by: Prabhakar Kushwaha 
> ---
> Chages for v2: Updated description
> 
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c   |  6 
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c   | 39 
> +++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h |  9 ++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h|  3 ++
>  4 files changed, 57 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> index 0cb0afa..dbb12c2 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
> @@ -484,7 +484,13 @@ int arch_early_init_r(void)
>  {
>  #ifdef CONFIG_MP
>   int rv = 1;
> +#endif
> +
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> + erratum_a009635();
> +#endif
>  
> +#ifdef CONFIG_MP
>   rv = fsl_layerscape_wake_seconday_cores();
>   if (rv)
>   printf("Did not wake secondary cores\n");
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index 637853d..e8cdb10 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -9,10 +9,49 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
>  #ifdef CONFIG_LS2085A
> +#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
> +#define PLATFORM_CYCLE_ENV_VAR   "a009635_interval_val"
> +
> +static unsigned long get_internval_val_mhz(void)
> +{
> + char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);

Why do you need a variable to override the calculation?


> + ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);

Please add a comment here to explain what the interval does and why it is
calculated this way.

York
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Re: [U-Boot] Ethernet i210 (e1000 driver) on tegra K1

[Stephen Warren]

On 10/30/2015 05:07 AM, Ivan Mercier wrote:

Hi,

I'm using a ethernet controller intel i210
(http://www.commell.com.tw/product/Surveillance/MPX-210.htm) on my
nvidia tegra k1 jetson.


(You didn't actually CC anyone involved with Tegra, so I only 
accidentally noticed this while I was looking at my mailing list folder)



I not an expert with pci, but the only way to make it working in u-boot
(upstream) is with the workaround below.

E1000 is very common, so finding a critical bug in this driver seems
weird...
Do you think there is a bug in e1000.c or in tegra pci layer?



diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c



@@ -5186,7 +5186,7 @@ static int _e1000_transmit(struct e1000_hw *hw,
void *txpacket, int length)
  txp = tx_base + tx_tail;
  tx_tail = (tx_tail + 1) % 8;

-txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet));
+txp->buffer_addr = cpu_to_le64((unsigned long) nv_packet);
  txp->lower.data = cpu_to_le32(hw->txd_cmd | length);
  txp->upper.data = 0;


In order to work out what's going on, perhaps you could print out the 
values of nv_packet and virt_to_bus(hw->pdev, nv_packet).


It's not terribly surprising that removing the call to virt_to_bus 
works, since IIRC U-Boot on Tegra uses the same address setup for the 
PCIe bus as for CPU physical addresses as for CPU virtual addresses.


So, the question is: what is virt_to_bus() doing, and is it the right 
API to call?


I see that virt_to_bus() is defined as:

e1000.c:

#define virt_to_bus(devno, v)   pci_virt_to_mem(devno, (void *) (v))

pci.h:

#define pci_virt_to_mem(dev, addr) \
pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)

#define pci_virt_to_bus(dev, addr, flags) \
pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
 (virt_to_phys(addr)), (flags))

I know that the RTL8169 driver works on the same board (it's soldered 
down and attached to the other PCIe root port on the SoC). For what 
looks like the same "use case", it seems to call pci_mem_to_phys() which is:


pci.h:

#define pci_mem_to_phys(dev, addr) \
pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)

#define pci_bus_to_phys(dev, addr, flags) \
pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), \
(flags))

That's odd, since one of those does a phys -> bus translation and the 
other does a bus -> phys translation. That's the opposite direction, so 
both can't possibly be right. I wonder if those mapping functions are 
no-ops on whatever architectures the e1000 driver has been used on (and 
hence have caused no issues), but fail for some reason on ARM?


(The other difference is the call to virt_to_phys(), but that's a no-op 
on ARM as far as I can tell).

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Re: [U-Boot] [PATCH 5/5] LS102XA:workaround:disable priorities within DDR

[York Sun]

On 10/21/2015 03:14 AM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
> 
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on Rev2.0.
> 
> Signed-off-by: Yuan Yao 
> ---
>  arch/arm/cpu/armv7/ls102xa/soc.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c 
> b/arch/arm/cpu/armv7/ls102xa/soc.c
> index b15cd60..98d4acd 100644
> --- a/arch/arm/cpu/armv7/ls102xa/soc.c
> +++ b/arch/arm/cpu/armv7/ls102xa/soc.c
> @@ -25,7 +25,7 @@ int arch_soc_init(void)
>  {
>   struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
>   struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
> - unsigned int major;
> + unsigned int major, reg;
>  
>  #ifdef CONFIG_FSL_QSPI
>   out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
> @@ -86,5 +86,16 @@ int arch_soc_init(void)
>*/
>   out_be32(&scfg->eddrtqcfg, 0x63b20002);
>  
> + /*
> +  * EDDRTQCFG Registers are Integration Strap values which controls
> +  * performance parameters for DDR Controller.
> +  * The bit 25 is used for disable priorities within DDR.
> +  * This is a workaround because of the DDR are connected backwards
> +  * on Rev2.0.
> +  */

Is there an erratum number for this? If not, please be specific about rev 2.0.
Is it SoC version, or something else?

York
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Re: [U-Boot] [PATCH 4/5] armv7/fsl-ls102xa: Workaround for DDR erratum A008514

[York Sun]

On 10/21/2015 03:14 AM, Yuan Yao wrote:
> Affects: DDR
> Description: Memory controller performance is not optimal with default
> internal target queue register values.
> Impact: Memory controller performance is not optimal.
> Workaround: Write a value of 63b2_0002h to address: 157_020Ch.
> 
>
Please rewrite the commit message to explain why and what this patch does, not
copy-n-paste from erratum document.

York

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Re: [U-Boot] [PATCH v2] mpc85xx: Add support for the Varisys Cyrus board

[York Sun]

On 11/03/2015 03:30 PM, Andy Fleming wrote:
> This board runs a P5020 or P5040 chip, and utilizes
> an EEPROM with similar formatting to the Freescale P5020DS.
> 
> Large amounts of this code were developed by
> Adrian Cox 
> 
> Signed-off-by: Andy Fleming 
> ---
> v2:
>   * Cleaned up sys_eeprom.c
>   * Removed CONFIG_CMD_ELF, CONFIG_SYS_GENERIC_BOARD

Why do you want to remove CONFIG_SYS_GENERIC_BOARD? We are dropping non-generic
board.

> 
>  arch/powerpc/cpu/mpc85xx/Kconfig |   4 +
>  board/varisys/common/Makefile|  23 ++
>  board/varisys/common/eeprom.h|   6 +
>  board/varisys/common/sys_eeprom.c| 500 +
>  board/varisys/cyrus/Kconfig  |  13 +
>  board/varisys/cyrus/Makefile |   8 +
>  board/varisys/cyrus/README   |  21 ++
>  board/varisys/cyrus/cyrus.c  | 116 +++
>  board/varisys/cyrus/cyrus.h  |  11 +
>  board/varisys/cyrus/ddr.c| 188 +++
>  board/varisys/cyrus/eth.c| 100 ++
>  board/varisys/cyrus/law.c|  27 ++
>  board/varisys/cyrus/pbi.cfg  |  35 +++
>  board/varisys/cyrus/pci.c|  23 ++
>  board/varisys/cyrus/rcw_p5020_v2.cfg |  11 +
>  board/varisys/cyrus/rcw_p5040.cfg|  11 +
>  board/varisys/cyrus/tlb.c| 106 +++
>  configs/Cyrus_P5020_defconfig|   9 +
>  configs/Cyrus_P5040_defconfig|   9 +
>  include/configs/cyrus.h  | 588 
> +++
>  20 files changed, 1809 insertions(+)
>  create mode 100644 board/varisys/common/Makefile
>  create mode 100644 board/varisys/common/eeprom.h
>  create mode 100644 board/varisys/common/sys_eeprom.c
>  create mode 100644 board/varisys/cyrus/Kconfig
>  create mode 100644 board/varisys/cyrus/Makefile
>  create mode 100644 board/varisys/cyrus/README
>  create mode 100644 board/varisys/cyrus/cyrus.c
>  create mode 100644 board/varisys/cyrus/cyrus.h
>  create mode 100644 board/varisys/cyrus/ddr.c
>  create mode 100644 board/varisys/cyrus/eth.c
>  create mode 100644 board/varisys/cyrus/law.c
>  create mode 100644 board/varisys/cyrus/pbi.cfg
>  create mode 100644 board/varisys/cyrus/pci.c
>  create mode 100644 board/varisys/cyrus/rcw_p5020_v2.cfg
>  create mode 100644 board/varisys/cyrus/rcw_p5040.cfg
>  create mode 100644 board/varisys/cyrus/tlb.c
>  create mode 100644 configs/Cyrus_P5020_defconfig
>  create mode 100644 configs/Cyrus_P5040_defconfig
>  create mode 100644 include/configs/cyrus.h

Please add MAINTAINERS file.



> diff --git a/board/varisys/common/sys_eeprom.c 
> b/board/varisys/common/sys_eeprom.c
> new file mode 100644
> index 000..086fad2
> --- /dev/null
> +++ b/board/varisys/common/sys_eeprom.c
> @@ -0,0 +1,500 @@
> +/*
> + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
> + * York Sun (york...@freescale.com)
> + * Haiying Wang (haiying.w...@freescale.com)
> + * Timur Tabi (ti...@freescale.com)
> + *
> + * This defines the API for storing board information in the
> + * eeprom. It has been adapted from an earlier version of the
> + * Freescale code for doing the same thing. Therefore it is
> + * nearly identical to the Freescale code, but is intended for
> + * use with Varisys-produced boards.
> + *
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include "eeprom.h"
> +
> +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
> +#define MAX_NUM_PORTSCONFIG_SYS_I2C_EEPROM_NXID_MAC
> +#else
> +#define MAX_NUM_PORTS8
> +#endif
> +#define NXID_VERSION 0
> +
> +/**
> + * static eeprom: EEPROM layout for NXID formats
> + *
> + * See Freescale application note AN3638 for details.
> + */

This comment and file header still implies this file follows Freescale EEPROM
spec. I think additional comment is needed to state the difference.

There are several blank lines added to the end of files.

York
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Re: [U-Boot] [PATCH] net: altera_tse: get numbers of fdt address and size cells

[Joe Hershberger]

Hi Thomas,

On Wed, Nov 4, 2015 at 6:28 AM, Thomas Chou  wrote:
> Get numbers of fdt address and size cells in altera_tse_probe(),
> thereby remove the assumption of one address cell and one size
> cell.
>
> Signed-off-by: Thomas Chou 
> ---

Acked-by: Joe Hershberger 
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Re: [U-Boot] [PATCH 8/8] net: zynq: Fix MDC setting for zynq

[Joe Hershberger]

On Wed, Nov 4, 2015 at 7:40 AM, Michal Simek  wrote:
> On 11/02/2015 10:39 PM, Joe Hershberger wrote:
>> On Tue, Oct 27, 2015 at 10:17 AM, Michal Simek  
>> wrote:
>>> Based on spec:
>>> "MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
>>> write operations)"
>>> Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
>>
>> Isn't it dependent on which board and what the clock setup is? Should
>> this be specified by the board?
>
> I am not aware about it. It is related to internal chip clock. I expect
> that 111MHz is software default value is is used by most of the chip.
> The clock range based on mainline Linux driver is 80MHz - 120MHz that's
> why I expect all non standard configuration will fit to it.
> For lower values as we used till now none reported any functional issue
> too.

OK, sounds good.

>>
>>> which is above of 2.5MHz.
>>> Using 48 divider will give us correct setting according spec
>>> (111/48=2.31).
>>>
>>> Signed-off-by: Michal Simek 
>>
>> Acked-by: Joe Hershberger 
>>
>
> Thanks,
> Michal
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[U-Boot] [PATCH v1 7/7] armv8/ls2085ardb: Update DDR settings for four chip-select case

[York Sun]

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun 

---

 board/freescale/ls2085ardb/ddr.c |   16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/board/freescale/ls2085ardb/ddr.c b/board/freescale/ls2085ardb/ddr.c
index 8d71ae1..e1d6aa1 100644
--- a/board/freescale/ls2085ardb/ddr.c
+++ b/board/freescale/ls2085ardb/ddr.c
@@ -131,10 +131,18 @@ found:
popts->zq_en = 1;
 
if (ddr_freq < 2350) {
-   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
-   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
+   if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+   /* four chip-selects */
+   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+   popts->twot_en = 1; /* enable 2T timing */
+   } else {
+   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+   }
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
-- 
1.7.9.5

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[U-Boot] [PATCH v1 3/7] driver/ddr/fsl: Update MR5 RTT park

[York Sun]

For four chip-selects enabled case, RTT is parked on all of them.

Signed-off-by: York Sun 
---

 drivers/ddr/fsl/ctrl_regs.c |   19 +++
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 36bf647..99714bf 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1117,10 +1117,18 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t 
*ddr,
unsigned short esdmode4 = 0;/* Extended SDRAM mode 4 */
unsigned short esdmode5;/* Extended SDRAM mode 5 */
int rtt_park = 0;
-
+   bool four_cs = false;
+
+#if CONFIG_CHIP_SELECTS_PER_CTRL == 4
+   if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
+   (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
+   (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
+   (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
+   four_cs = true;
+#endif
if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
esdmode5 = 0x0500;  /* Data mask enable, RTT_PARK CS0 */
-   rtt_park = 1;
+   rtt_park = four_cs ? 0 : 1;
} else {
esdmode5 = 0x0400;  /* Data mask enabled */
}
@@ -1130,7 +1138,10 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
 | ((esdmode5 & 0x) << 0)
);
 
-   /* only mode_9 use 0x500, others use 0x400 */
+   /* Normally only the first enabled CS use 0x500, others use 0x400
+* But when four chip-selects are all enabled, all mode registers
+* need 0x500 to park.
+*/
 
debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
if (unq_mrs_en) {   /* unique mode registers are supported */
@@ -1138,7 +1149,7 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
if (!rtt_park &&
(ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
esdmode5 |= 0x0500; /* RTT_PARK */
-   rtt_park = 1;
+   rtt_park = four_cs ? 0 : 1;
} else {
esdmode5 = 0x0400;
}
-- 
1.7.9.5

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[U-Boot] [PATCH v1 5/7] driver/ddr/fsl: Update timing config for heavy load

[York Sun]

In case four chip-selects are all active, the turnaround times need to
increase to avoid overlapping under heavy load.

Signed-off-by: York Sun 
---

 drivers/ddr/fsl/ctrl_regs.c |   26 --
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 99714bf..0bfcd34 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -317,7 +317,24 @@ static void set_timing_cfg_0(const unsigned int ctrl_num,
 
/* for faster clock, need more time for data setup */
trwt_mclk = (data_rate/100 > 1900) ? 3 : 2;
-   twrt_mclk = 1;
+
+   /*
+* for single quad-rank DIMM and two-slot DIMMs
+* to avoid ODT overlap
+*/
+   switch (avoid_odt_overlap(dimm_params)) {
+   case 2:
+   twrt_mclk = 2;
+   twwt_mclk = 2;
+   trrt_mclk = 2;
+   break;
+   default:
+   twrt_mclk = 1;
+   twwt_mclk = 1;
+   trrt_mclk = 0;
+   break;
+   }
+
act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
pre_pd_exit_mclk = act_pd_exit_mclk;
/*
@@ -1822,6 +1839,7 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
+   unsigned int trwt_mclk = 0; /* ext_rwt */
unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
 
 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
@@ -1835,17 +1853,21 @@ static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
wwt = 2;/* BL/2 + 2 clocks */
}
 #endif
-
 #ifdef CONFIG_SYS_FSL_DDR4
dll_lock = 2;   /* tDLLK = 1024 clocks */
 #elif defined(CONFIG_SYS_FSL_DDR3)
dll_lock = 1;   /* tDLLK = 512 clocks from spec */
 #endif
+
+   if (popts->trwt_override)
+   trwt_mclk = popts->trwt;
+
ddr->timing_cfg_4 = (0
 | ((rwt & 0xf) << 28)
 | ((wrt & 0xf) << 24)
 | ((rrt & 0xf) << 20)
 | ((wwt & 0xf) << 16)
+| ((trwt_mclk & 0xc) << 12)
 | (dll_lock & 0x3)
 );
debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
-- 
1.7.9.5

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[U-Boot] [PATCH v1 2/7] driver/ddr/fsl: Update DDR4 MR6 for Vref range

[York Sun]

MR6 bit 6 is set accrodingly for range 1 or 2, per JEDEC spec.

Signed-off-by: York Sun 
---

 drivers/ddr/fsl/ctrl_regs.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c
index 8543679..36bf647 100644
--- a/drivers/ddr/fsl/ctrl_regs.c
+++ b/drivers/ddr/fsl/ctrl_regs.c
@@ -1186,6 +1186,9 @@ static void set_ddr_sdram_mode_10(const unsigned int 
ctrl_num,
 
esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
 
+   if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
+   esdmode6 |= 1 << 6; /* Range 2 */
+
ddr->ddr_sdram_mode_10 = (0
 | ((esdmode6 & 0x) << 16)
 | ((esdmode7 & 0x) << 0)
-- 
1.7.9.5

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[U-Boot] [PATCH v1 6/7] armv8/ls2085aqds: Update DDR settings for four chip-select case

[York Sun]

When 4 chip-selects are used, vref should use range 1 and CDT uses 80 ohm,
and 2T timing is enabled.

Signed-off-by: York Sun 
---

 board/freescale/ls2085aqds/ddr.c |   16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c
index 8d71ae1..d8562b1 100644
--- a/board/freescale/ls2085aqds/ddr.c
+++ b/board/freescale/ls2085aqds/ddr.c
@@ -131,10 +131,18 @@ found:
popts->zq_en = 1;
 
if (ddr_freq < 2350) {
-   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
- DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
-   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
- DDR_CDR2_VREF_RANGE_2;
+   if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
+   /* four chip-selects */
+   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
+   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
+   popts->twot_en = 1; /* enable 2T timing */
+   } else {
+   popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+ DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+   popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+ DDR_CDR2_VREF_RANGE_2;
+   }
} else {
popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
  DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
-- 
1.7.9.5

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[U-Boot] [PATCH v1 4/7] driver/ddr/fsl: Update workaround for A008511 for vref range

[York Sun]

The workaround requires different setting for range 1 vs 2.
Also adjust timeout value for waiting for controller to be idle.

Signed-off-by: York Sun 
---

 drivers/ddr/fsl/fsl_ddr_gen4.c |   22 +++---
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 49e4688..70ce1b8 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -54,6 +54,9 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008511
u32 temp32, mr6;
+   u32 vref_seq1[3] = {0x80, 0x96, 0x16};  /* for range 1 */
+   u32 vref_seq2[3] = {0xc0, 0xf0, 0x70};  /* for range 2 */
+   u32 *vref_seq = vref_seq1;
 #endif
 #ifdef CONFIG_FSL_DDR_BIST
u32 mtcr, err_detect, err_sbe;
@@ -307,16 +310,21 @@ step2:
/* This erraum only applies to verion 5.2.0 */
if (fsl_ddr_get_version(ctrl_num) == 0x50200) {
/* Wait for idle */
-   timeout = 200;
+   timeout = 40;
while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
   (timeout > 0)) {
-   udelay(100);
+   udelay(1000);
timeout--;
}
if (timeout <= 0) {
printf("Controler %d timeout, debug_2 = %x\n",
   ctrl_num, ddr_in32(&ddr->debug[1]));
}
+
+   /* The vref setting sequence is different for range 2 */
+   if (regs->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
+   vref_seq = vref_seq2;
+
/* Set VREF */
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
@@ -327,17 +335,17 @@ step2:
 MD_CNTL_CS_SEL(i)  |
 MD_CNTL_MD_SEL(6)  |
 0x0020;
-   temp32 = mr6 | 0xc0;
+   temp32 = mr6 | vref_seq[0];
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
temp32, MD_CNTL_MD_EN);
udelay(1);
debug("MR6 = 0x%08x\n", temp32);
-   temp32 = mr6 | 0xf0;
+   temp32 = mr6 | vref_seq[1];
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
temp32, MD_CNTL_MD_EN);
udelay(1);
debug("MR6 = 0x%08x\n", temp32);
-   temp32 = mr6 | 0x70;
+   temp32 = mr6 | vref_seq[2];
set_wait_for_bits_clear(&ddr->sdram_md_cntl,
temp32, MD_CNTL_MD_EN);
udelay(1);
@@ -347,10 +355,10 @@ step2:
ddr_out32(&ddr->debug[28], 0);  /* Enable deskew */
ddr_out32(&ddr->debug[1], 0x400);   /* restart deskew */
/* wait for idle */
-   timeout = 200;
+   timeout = 40;
while (!(ddr_in32(&ddr->debug[1]) & 0x2) &&
   (timeout > 0)) {
-   udelay(100);
+   udelay(1000);
timeout--;
}
if (timeout <= 0) {
-- 
1.7.9.5

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[U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

[York Sun]

This patch set revises the DDR driver to support higher speed for DDR4
under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
Single quad-rank DIMM is not supported yet.


York Sun (7):
  driver/ddr/fsl: Update DDR4 RTT values
  driver/ddr/fsl: Update DDR4 MR6 for Vref range
  driver/ddr/fsl: Update MR5 RTT park
  driver/ddr/fsl: Update workaround for A008511 for vref range
  driver/ddr/fsl: Update timing config for heavy load
  armv8/ls2085aqds: Update DDR settings for four chip-select case
  armv8/ls2085ardb: Update DDR settings for four chip-select case

 board/freescale/ls2085aqds/ddr.c |   16 ++-
 board/freescale/ls2085ardb/ddr.c |   16 ++-
 drivers/ddr/fsl/ctrl_regs.c  |   48 +++-
 drivers/ddr/fsl/fsl_ddr_gen4.c   |   22 ++--
 drivers/ddr/fsl/options.c|  237 +-
 include/fsl_ddr_sdram.h  |9 ++
 6 files changed, 325 insertions(+), 23 deletions(-)

-- 
1.7.9.5

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[U-Boot] [PATCH v1 1/7] driver/ddr/fsl: Update DDR4 RTT values

[York Sun]

DDR4 has different RTT value and code according to JEDEC spec. Update
the macros and options .

Signed-off-by: York Sun 
---

 drivers/ddr/fsl/options.c |  237 -
 include/fsl_ddr_sdram.h   |9 ++
 2 files changed, 244 insertions(+), 2 deletions(-)

diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c
index 3c09c64..791d644 100644
--- a/drivers/ddr/fsl/options.c
+++ b/drivers/ddr/fsl/options.c
@@ -29,7 +29,240 @@ struct dynamic_odt {
unsigned int odt_rtt_wr;
 };
 
-#if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
+#ifdef CONFIG_SYS_FSL_DDR4
+/* Quad rank is not verified yet due availability.
+ * Replacing 20 OHM with 34 OHM since DDR4 doesn't have 20 OHM option
+ */
+static const struct dynamic_odt single_Q[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+   DDR4_RTT_34_OHM,/* unverified */
+   DDR4_RTT_120_OHM
+   },
+   {   /* cs1 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_NEVER,
+   DDR4_RTT_OFF,
+   DDR4_RTT_120_OHM
+   },
+   {   /* cs2 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_CS_AND_OTHER_DIMM,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_120_OHM
+   },
+   {   /* cs3 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_NEVER,  /* tied high */
+   DDR4_RTT_OFF,
+   DDR4_RTT_120_OHM
+   }
+};
+
+static const struct dynamic_odt single_D[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_40_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs1 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_NEVER,
+   DDR4_RTT_OFF,
+   DDR4_RTT_OFF
+   },
+   {0, 0, 0, 0},
+   {0, 0, 0, 0}
+};
+
+static const struct dynamic_odt single_S[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_40_OHM,
+   DDR4_RTT_OFF
+   },
+   {0, 0, 0, 0},
+   {0, 0, 0, 0},
+   {0, 0, 0, 0},
+};
+
+static const struct dynamic_odt dual_DD[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_SAME_DIMM,
+   DDR4_RTT_120_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs1 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_OTHER_DIMM,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs2 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_SAME_DIMM,
+   DDR4_RTT_120_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs3 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_OTHER_DIMM,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_OFF
+   }
+};
+
+static const struct dynamic_odt dual_DS[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_SAME_DIMM,
+   DDR4_RTT_120_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs1 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_OTHER_DIMM,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs2 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_120_OHM
+   },
+   {0, 0, 0, 0}
+};
+static const struct dynamic_odt dual_SD[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_120_OHM
+   },
+   {0, 0, 0, 0},
+   {   /* cs2 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_SAME_DIMM,
+   DDR4_RTT_120_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs3 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_OTHER_DIMM,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_OFF
+   }
+};
+
+static const struct dynamic_odt dual_SS[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_120_OHM
+   },
+   {0, 0, 0, 0},
+   {   /* cs2 */
+   FSL_DDR_ODT_OTHER_DIMM,
+   FSL_DDR_ODT_ALL,
+   DDR4_RTT_34_OHM,
+   DDR4_RTT_120_OHM
+   },
+   {0, 0, 0, 0}
+};
+
+static const struct dynamic_odt dual_D0[4] = {
+   {   /* cs0 */
+   FSL_DDR_ODT_NEVER,
+   FSL_DDR_ODT_SAME_DIMM,
+   DDR4_RTT_40_OHM,
+   DDR4_RTT_OFF
+   },
+   {   /* cs1 */
+   FSL_DDR_ODT_NEVER,
+   

Re: [U-Boot] [PATCH 1/4] mips: Use the generic bitops headers

[Daniel Schwierzeck]

Am 04.11.2015 um 18:13 schrieb Fabio Estevam:
> From: Fabio Estevam 
> 
> The generic bitops headers are required when calling logarithimic
> functions, such as ilog2().
> 
> Signed-off-by: Fabio Estevam 
> ---
> Applies against u-boot-spi next
> 
>  arch/mips/include/asm/bitops.h | 5 +
>  1 file changed, 5 insertions(+)
> 

Reviewed-by: Daniel Schwierzeck 

--
After applying your patches

include: Add log2 header from the kernel
include: Add generic bitops headers

I've got warnings on almost all MIPS boards. Maybe you should move your
modification on "include/linux/bitops.h" in the second patch to a
separate patch to be applied after all arch-specific patches to avoid
this. I guess the other archs have the same problem.

-- 
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[U-Boot] [PATCH v1] drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3

[York Sun]

Freescale LSCH3 platforms use two DDR controlers interleaving mode out of
reset. It can be configured to disable one controller. To support this
operation, the driver needs to detect and skip the disabled controller.

Signed-off-by: York Sun 

---
Change log
  v1: Initial patch. Tested on LS2085AQDS and LS2085ARDB.

 arch/arm/include/asm/arch-fsl-layerscape/config.h |7 
 drivers/ddr/fsl/main.c|1 +
 drivers/ddr/fsl/util.c|   40 +
 include/fsl_ddr.h |1 +
 4 files changed, 49 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h 
b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 87bb937..b0f0957 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -60,6 +60,13 @@
 #define CCI_MN_DVM_DOMAIN_CTL  0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET  0x210
 
+#define CCI_HN_F_0_BASE(CCI_MN_BASE + 0x20)
+#define CCI_HN_F_1_BASE(CCI_MN_BASE + 0x21)
+#define CCN_HN_F_SAM_CTL   0x8 /* offset on base HN_F base */
+#define CCN_HN_F_SAM_NODEID_MASK   0x7f
+#define CCN_HN_F_SAM_NODEID_DDR0   0x4
+#define CCN_HN_F_SAM_NODEID_DDR1   0xe
+
 #define CCI_RN_I_0_BASE(CCI_MN_BASE + 0x80)
 #define CCI_RN_I_2_BASE(CCI_MN_BASE + 0x82)
 #define CCI_RN_I_6_BASE(CCI_MN_BASE + 0x86)
diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c
index 72ec1be..c686632 100644
--- a/drivers/ddr/fsl/main.c
+++ b/drivers/ddr/fsl/main.c
@@ -813,6 +813,7 @@ phys_size_t fsl_ddr_sdram(void)
info.board_need_mem_reset = board_need_mem_reset;
info.board_mem_reset = board_assert_mem_reset;
info.board_mem_de_reset = board_deassert_mem_reset;
+   remove_unused_controllers(&info);
 
return __fsl_ddr_sdram(&info);
 }
diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c
index ce55aea..1a49b28 100644
--- a/drivers/ddr/fsl/util.c
+++ b/drivers/ddr/fsl/util.c
@@ -385,3 +385,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
 }
 #endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
+
+void remove_unused_controllers(fsl_ddr_info_t *info)
+{
+#ifdef CONFIG_FSL_LSCH3
+   int i;
+   u64 nodeid;
+   void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
+   bool ddr0_used = false;
+   bool ddr1_used = false;
+
+   for (i = 0; i < 8; i++) {
+   nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
+   if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
+   ddr0_used = true;
+   } else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
+   ddr1_used = true;
+   } else {
+   printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
+  nodeid);
+   }
+   hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
+   }
+   if (!ddr0_used && !ddr1_used) {
+   printf("Invalid configuration in HN-F SAM control\n");
+   return;
+   }
+
+   if (!ddr0_used && info->first_ctrl == 0) {
+   info->first_ctrl = 1;
+   info->num_ctrls = 1;
+   debug("First DDR controller disabled\n");
+   return;
+   }
+
+   if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
+   info->num_ctrls = 1;
+   debug("Second DDR controller disabled\n");
+   }
+#endif
+}
diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h
index 1ac092b..9aaf6b3 100644
--- a/include/fsl_ddr.h
+++ b/include/fsl_ddr.h
@@ -131,6 +131,7 @@ void board_add_ram_info(int use_default);
 /* processor specific function */
 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
   unsigned int ctrl_num, int step);
+void remove_unused_controllers(fsl_ddr_info_t *info);
 
 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
-- 
1.7.9.5

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Re: [U-Boot] [PATCH 1/4] mips: Use the generic bitops headers

[Dinh Nguyen]

On 11/04/2015 11:13 AM, Fabio Estevam wrote:
> From: Fabio Estevam 
> 
> The generic bitops headers are required when calling logarithimic
> functions, such as ilog2().
> 

s/logarithimic/logarithmic

Same comment for 2/4 and 3/4

Dinh

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Re: [U-Boot] [ANN] U-Boot v2015.10-rc5 released

[Dennis Gilmore]

On Thursday, October 15, 2015 04:55:55 PM Tom Rini wrote:
> On Thu, Oct 15, 2015 at 03:52:08AM +0200, Andreas Färber wrote:
> > Am 15.10.2015 um 02:40 schrieb Tom Rini:
> > > On Thu, Oct 15, 2015 at 02:28:34AM +0200, Andreas Färber wrote:
> > >> Am 12.10.2015 um 17:18 schrieb Tom Rini:
> > >>> If you have a regression, speak up.
> > >> 
> > >> For -rc4 I had reported that CONFIG_API is broken for sunxi among
> > >> others. I was told this was fallout of the new Driver Model. Has anyone
> > >> thought about how to fix this? Is that already a lost cause for
> > >> 2015.10?
> > >> 
> > >> Improving test coverage for such off-by-default features will also be
> > >> helpful going forward. For instance, Simon's brand-new rk3288 code was
> > >> lacking some MMC define for CONFIG_API to build iirc - that part is
> > >> trivial to fix when actually build-testing. I'll see if I can polish
> > >> some of my fixes in time.
> > > 
> > > I'm just not sure what to do about CONFIG_API some days.  I know one use
> > > case is for GRUB but I'd like to move away from that if possible
> > > (distros should be doing the generic distro bits and extlinux.conf).
> > > After that, I'm only hazily aware of the real use-cases.
> > 
> > The problem is that no other platform uses those. On x86_64, ppc64le,
> > s390x, aarch64, etc. we always use GRUB2. Whether it's boot.scr,
> > extlinux.conf or anything else, it'll require changes to distro tools
> > that end up being special-cased to 32-bit arm. With more and more server
> > vendors adopting UEFI and aarch64, that seems a waste of effort.
> 
> That's a thing to ponder, yes.  There's nothing ARM32 centric about the
> generic distro framework and it's on my TODO list now to poke Fedora
> about enabling the extlinux.conf knob on x86 because there's a growing
> number of platforms using U-Boot there.  And hikey does (and Juno
> should/will) be doing it as well.

it is already there 
https://rhinstaller.github.io/anaconda/boot-options.html#boot-loader-options  
add extlinux to the boot arguments on a x86 
install and it will use extlinux.


> > A boot.scr is easy to generate once for an installation image, and I see
> > Guillaume has been helping to make it usable where necessary, but as
> > long as that points to a single zImage / initrd / dtb (ext4 symlinks
> > pointing to the latest), after the user installs a new kernel package,
> > things might simply become unbootable for the average user. That's where
> > GRUB is handy in offering a selection of multiple kernels to go back to
> > a previously working state. I'm not particularly attached to CONFIG_API
> > myself - if the same can be achieved either in GRUB without CONFIG_API
> > or inside U-Boot with scripts and without GRUB, I'd be happy to hear
> > about it. :)
> 
> Well, that roughly is the point of the whole config_distro_defaults /
> config_distro_bootcmd stuff is that the distro doesn't have to care what
> board it's on, it can just boot.

yep :)

> > Regarding GRUB, I've mainly tested it on jetson-tk1 (adjusting grub's
> > hardcoded RAM offsets), and I've found it to load unreliably, as if
> > there's garbage in memory. Might be our 2.02~beta2 is missing some
> > backports. bootz works fine, so I guess bootm is not to blame there.
> > 
> > Anyway, I think it's valid to say that we should either fix CONFIG_API
> > to build okay, or drop it completely, but not carry it around in
> > decaying state. ;)
> 
> So as Wolfgang brought up, FreeBSD uses CONFIG_API so some care must be
> taken here, but we need to cover things a lot better than we do today.

the reason we did not look at grub was that it needed hard coded values, so 
you would need different grub builds for different boards. and a whole world 
of extra pain, and no one was actively working on the arm port of grub. u-boot 
had the extlinux support built in. though I need to find time to extend it a 
bit.

Dennis
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[U-Boot] [PATCH] sandbox: adc: Add missing header file

[Przemyslaw Marczak]

Commit: sandbox: add ADC driver

adds the driver without its main header file.
It causes build brake for sandbox_defonfig.

This commit adds a missing header:
- include/sandbox-adc.h

Signed-off-by: Przemyslaw Marczak 
Cc: Minkyu Kang 
Cc: Simon Glass 
---
 include/sandbox-adc.h | 31 +++
 1 file changed, 31 insertions(+)
 create mode 100644 include/sandbox-adc.h

diff --git a/include/sandbox-adc.h b/include/sandbox-adc.h
new file mode 100644
index 000..79ff01c
--- /dev/null
+++ b/include/sandbox-adc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2015 Samsung Electronics
+ * Przemyslaw Marczak 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SANDBOX_ADC_H_
+#define _SANDBOX_ADC_H_
+
+#define SANDBOX_ADC_DEVNAME"adc@0"
+#define SANDBOX_ADC_DATA_MASK  0x /* 16-bits resolution */
+#define SANDBOX_ADC_CHANNELS   4
+#define SANDBOX_ADC_CHANNEL0_DATA  0x0
+#define SANDBOX_ADC_CHANNEL1_DATA  0x1000
+#define SANDBOX_ADC_CHANNEL2_DATA  0x2000
+#define SANDBOX_ADC_CHANNEL3_DATA  0x3000
+
+enum sandbox_adc_mode {
+   SANDBOX_ADC_MODE_SINGLE_CHANNEL = 0,
+   SANDBOX_ADC_MODE_MULTI_CHANNEL,
+};
+
+enum sandbox_adc_status {
+   SANDBOX_ADC_INACTIVE = 0,
+   SANDBOX_ADC_ACTIVE,
+};
+
+#define SANDBOX_ADC_VSS_VALUE  0
+
+#endif
-- 
1.9.1

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Re: [U-Boot] please pull u-boot-samsung master

[Przemyslaw Marczak]

Hello Minkyu,

On 11/04/2015 04:43 PM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,

On 4 November 2015 at 18:37, Przemyslaw Marczak mailto:p.marc...@samsung.com>> wrote:

Hello Minkyu,

On 11/04/2015 03:05 AM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,

2015년 11월 4일 수요일, Tom Rinimailto:tr...@konsulko.com>

 On Tue, Nov 03, 2015 at 02:02:57PM +0900, Minkyu Kang wrote:

  > Dear Tom,
  >
  > The following changes since commit
 0e067a65f57189703668826d9841fea477026bf6:
  >
  >   x86: Select the ns16550 debug UART for minnowmax,
 chromebook_link (2015-10-30 18:04:14 -0400)
  >
  > are available in the git repository at:
  >
  > http://git.denx.de/u-boot-samsung
  >
  > for you to fetch changes up to
 de5f9733f653091d4b227914d04432099a6448dc:
  >
  >   samsung: clean up checkpatch issues (2015-11-02
10:38:22 +0900)
  >

 NAK:

 +(sandbox) ../drivers/adc/sandbox.c:11:25: fatal error:
 sandbox-adc.h: No such file or directory
 +(sandbox)  #include 
 +(sandbox)  ^
 +(sandbox) compilation terminated.
 +(sandbox) make[3]: *** [drivers/adc/sandbox.o] Error 1
 +(sandbox) make[2]: *** [drivers/adc] Error 2
 +(sandbox) make[1]: *** [drivers] Error 2

 "sandbox: add ADC unit tests" is missing adding sandbox-adc.h


Could you please check it?

 --
 Tom


Thanks,
Minkyu Kang.


--
Thanks.
Minkyu Kang.


Sorry for this mistake. I have this file locally, so it build
properly for me.

Is that good to you if I send you a patch with this missing file, to
squash with one commit? Or do you prefer V3 of the whole patch-set?


If squash your patch  then I should do push forced.
I think it's not a good way.
I will merge your patch separately.

Thanks,
Minkyu Kang.
--
from. prom.
www.promsoft.net 


Squashing would be better if we want prevent build break. This single 
file (include/sandbox-adc.h) will not conflict with any other, so it's 
easy to rebase it.
This is not a master tree, so I think that push with force will not 
cause any problems.


But if you really prefer to take it as a separate patch, then I will 
send one, with a proper commit message in a moment.


Best regards,
--
Przemyslaw Marczak
Samsung R&D Institute Poland
Samsung Electronics
p.marc...@samsung.com
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[U-Boot] [PATCH 4/4] spi: sf_ops: Use size_t for len

[Fabio Estevam]

From: Fabio Estevam 

Let the function and its prototype use the same variable type for 'len'.

Signed-off-by: Fabio Estevam 
---
Applies against u-boot-spi next

 drivers/mtd/spi/sf_ops.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c
index 31c79c6..d832464 100644
--- a/drivers/mtd/spi/sf_ops.c
+++ b/drivers/mtd/spi/sf_ops.c
@@ -652,7 +652,7 @@ int stm_is_locked(struct spi_flash *flash, u32 ofs, size_t 
len)
  *
  * Returns negative on errors, 0 on success.
  */
-int stm_lock(struct spi_flash *flash, u32 ofs, u32 len)
+int stm_lock(struct spi_flash *flash, u32 ofs, size_t len)
 {
u8 status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
@@ -703,7 +703,7 @@ int stm_lock(struct spi_flash *flash, u32 ofs, u32 len)
  *
  * Returns negative on errors, 0 on success.
  */
-int stm_unlock(struct spi_flash *flash, u32 ofs, u32 len)
+int stm_unlock(struct spi_flash *flash, u32 ofs, size_t len)
 {
uint8_t status_old, status_new;
u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
-- 
1.9.1

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[U-Boot] [PATCH 3/4] avr32: Use the generic bitops headers

[Fabio Estevam]

From: Fabio Estevam 

The generic bitops headers are required when calling logarithimic
functions, such as ilog2().

Signed-off-by: Fabio Estevam 
---
Applies against u-boot-spi next

 arch/avr32/include/asm/bitops.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/avr32/include/asm/bitops.h b/arch/avr32/include/asm/bitops.h
index 0ec6784..0d425c2 100644
--- a/arch/avr32/include/asm/bitops.h
+++ b/arch/avr32/include/asm/bitops.h
@@ -6,4 +6,9 @@
 #ifndef __ASM_AVR32_BITOPS_H
 #define __ASM_AVR32_BITOPS_H
 
+#include 
+#include 
+#include 
+#include 
+
 #endif /* __ASM_AVR32_BITOPS_H */
-- 
1.9.1

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[U-Boot] [PATCH 1/4] mips: Use the generic bitops headers

[Fabio Estevam]

From: Fabio Estevam 

The generic bitops headers are required when calling logarithimic
functions, such as ilog2().

Signed-off-by: Fabio Estevam 
---
Applies against u-boot-spi next

 arch/mips/include/asm/bitops.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index b5c2a63..c31ff6e 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -17,6 +17,11 @@
 #include 
 #include 
 
+#include 
+#include 
+#include 
+#include 
+
 /*
  * clear_bit() doesn't provide any barrier for the compiler.
  */
-- 
1.9.1

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[U-Boot] [PATCH 2/4] arc: Use the generic bitops headers

[Fabio Estevam]

From: Fabio Estevam 

The generic bitops headers are required when calling logarithimic
functions, such as ilog2().

Signed-off-by: Fabio Estevam 
---
Applies against u-boot-spi next

 arch/arc/include/asm/bitops.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arc/include/asm/bitops.h b/arch/arc/include/asm/bitops.h
index 85721aa..370cb46 100644
--- a/arch/arc/include/asm/bitops.h
+++ b/arch/arc/include/asm/bitops.h
@@ -16,4 +16,9 @@
 #define hweight16(x) generic_hweight16(x)
 #define hweight8(x) generic_hweight8(x)
 
+#include 
+#include 
+#include 
+#include 
+
 #endif /* __ASM_ARC_BITOPS_H */
-- 
1.9.1

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Re: [U-Boot] [PATCH 6/6] net: altera_tse: use BIT macro

[Jagan Teki]

On 4 November 2015 at 21:52, Chin Liang See  wrote:
> On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
>> Replace numerical bit shift with BIT macro
>> in altera_tse
>>
>> :%s/(1 << nr)/BIT(nr)/g
>> where nr = 0, 1, 2  31
>>
>> Signed-off-by: Thomas Chou 
>> ---
>
>
> Reviewed-by: Chin Liang See 

 Reviewed-by: Jagan Teki 

-- 
Jagan | openedev.
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Re: [U-Boot] [PATCH 6/6] net: altera_tse: use BIT macro

[Chin Liang See]

On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Replace numerical bit shift with BIT macro
> in altera_tse
> 
> :%s/(1 << nr)/BIT(nr)/g
> where nr = 0, 1, 2  31
> 
> Signed-off-by: Thomas Chou 
> ---


Reviewed-by: Chin Liang See 

Thanks
Chin Liang

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Re: [U-Boot] [PATCH 5/6] net: altera_tse: remove unused macro

[Chin Liang See]

On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Remove unused macro.
> 
> Signed-off-by: Thomas Chou 
> ---

Reviewed-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH 4/6] net: altera_tse: remove the useless parenthesis

[Chin Liang See]

On Wed, 2015-11-04 at 03:29 +, tho...@wytron.com.tw wrote:
> Remove the useless parenthesis.
> 
> Signed-off-by: Thomas Chou 
> ---

Reviewed-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH] mtd: add altera quadspi driver

[Marek Vasut]

On Wednesday, November 04, 2015 at 04:56:10 PM, Chin Liang See wrote:
> On Tue, 2015-11-03 at 21:22 +0800, tho...@wytron.com.tw wrote:
> > Add Altera Generic Quad SPI Controller support. The controller
> > converts SPI NOR flash to parallel flash interface. So it is
> > not like other SPI flash, but rather like CFI flash.
> > 
> > Signed-off-by: Thomas Chou 
> > ---
> > 
> >  doc/device-tree-bindings/mtd/altera_qspi.txt |  35 +++
> >  drivers/mtd/Kconfig  |   9 +
> >  drivers/mtd/Makefile |   1 +
> >  drivers/mtd/altera_qspi.c| 312
> >  +++ 4 files changed, 357 insertions(+)
> >  create mode 100644 doc/device-tree-bindings/mtd/altera_qspi.txt
> >  create mode 100644 drivers/mtd/altera_qspi.c
> >  ...
> > 
> > diff --git a/drivers/mtd/altera_qspi.c b/drivers/mtd/altera_qspi.c
> > new file mode 100644
> > index 000..06bc53e
> > --- /dev/null
> > +++ b/drivers/mtd/altera_qspi.c
> > @@ -0,0 +1,312 @@
> > +/*
> > + * Copyright (C) 2015 Thomas Chou 
> > + *
> > + * SPDX-License-Identifier:GPL-2.0+
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +DECLARE_GLOBAL_DATA_PTR;
> > +
> > +/*
> > + * The QUADSPI_MEM_OP register is used to do memory protect and erase
> > operations + */
> > +#define QUADSPI_MEM_OP_BULK_ERASE  0x0001
> > +#define QUADSPI_MEM_OP_SECTOR_ERASE0x0002
> > +#define QUADSPI_MEM_OP_SECTOR_PROTECT  0x0003
> > +
> > +/*
> > + * The QUADSPI_ISR register is used to determine whether an invalid
> > write or + * erase operation trigerred an interrupt
> > + */
> > +#define QUADSPI_ISR_ILLEGAL_ERASE  BIT(0)
> > +#define QUADSPI_ISR_ILLEGAL_WRITE  BIT(1)
> > +
> > +struct altera_qspi_regs {
> > +   u32 rd_status;
> > +   u32 rd_sid;
> > +   u32 rd_rdid;
> > +   u32 mem_op;
> > +   u32 isr;
> > +   u32 imr;
> > +   u32 chip_select;
> > +};
> > +
> > +struct altera_qspi_platdata {
> > +   struct altera_qspi_regs *regs;
> > +   void *base;
> > +   unsigned long size;
> > +};
> > +
> > +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];   /* FLASH chips 
info
> > */ +
> > +void flash_print_info(flash_info_t *info)
> > +{
> > +   printf("Altera QSPI flash  Size: %ld MB in %d Sectors\n",
> > +  info->size >> 20, info->sector_count);
> > +}
> > +
> > +int flash_erase(flash_info_t *info, int s_first, int s_last)
> > +{
> > +   struct mtd_info *mtd = info->mtd;
> > +   struct erase_info instr;
> > +   int ret;
> > +
> > +   memset(&instr, 0, sizeof(instr));
> > +   instr.addr = mtd->erasesize * s_first;
> > +   instr.len = mtd->erasesize * (s_last + 1 - s_first);
> > +   ret = mtd_erase(mtd, &instr);
> > +   if (ret)
> > +   return ERR_NOT_ERASED;
> > +
> > +   return 0;
> > +}
> > +
> > +int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
> > +{
> > +   struct mtd_info *mtd = info->mtd;
> > +   struct udevice *dev = mtd->dev;
> > +   struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > +   ulong base = (ulong)pdata->base;
> > +   loff_t to = addr - base;
> > +   size_t retlen;
> > +   int ret;
> > +
> > +   ret = mtd_write(mtd, to, cnt, &retlen, src);
> > +   if (ret)
> > +   return ERR_NOT_ERASED;
> > +
> > +   return 0;
> > +}
> > +
> > +unsigned long flash_init(void)
> > +{
> > +   struct udevice *dev;
> > +
> > +   /* probe every MTD device */
> > +   for (uclass_first_device(UCLASS_MTD, &dev);
> > +dev;
> > +uclass_next_device(&dev)) {
> > +   }
> > +
> > +   return flash_info[0].size;
> > +}
> > +
> > +static int altera_qspi_erase(struct mtd_info *mtd, struct erase_info
> > *instr) +{
> > +   struct udevice *dev = mtd->dev;
> > +   struct altera_qspi_platdata *pdata = dev_get_platdata(dev);
> > +   struct altera_qspi_regs *regs = pdata->regs;
> > +   size_t addr = instr->addr;
> > +   size_t len = instr->len;
> > +   size_t end = addr + len;
> > +   u32 sect;
> > +   u32 stat;
> > +
> > +   instr->state = MTD_ERASING;
> > +   addr &= ~(mtd->erasesize - 1); /* get lower aligned address */
> > +   while (addr < end) {
> > +   sect = addr / mtd->erasesize;
> > +   sect <<= 8;
> > +   sect |= QUADSPI_MEM_OP_SECTOR_ERASE;
> > +   debug("erase %08x\n", sect);
> > +   writel(sect, ®s->mem_op);
> > +   stat = readl(®s->isr);
> > +   if (stat & QUADSPI_ISR_ILLEGAL_ERASE) {
> > +   /* erase failed, sector might be protected */
> > +   debug("erase %08x fail %x\n", sect, stat);
> > +   writel(stat, ®s->isr); /* clear isr */
> > +   instr->state = MTD_ERASE_FAILED;
> > +   return -EIO;
> > +   }
> > +   addr += mtd->erasesize;
> > +   }
> > +   instr->state = MTD_ERASE_DONE;
> > +   mtd_erase_callback(instr);
> > +
> > +   r

Re: [U-Boot] [PATCH 3/6] net: altera_tse: fix CamelCase

[Chin Liang See]

Hi Thomas,


On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> fix CamelCase.
> 
> CHECK: Avoid CamelCase: 
> #170: FILE: drivers/net/altera_tse.h:170:
> + u32 aMACID_1;   /*The MAC addresses */
> 
> Signed-off-by: Thomas Chou 
> ---
>  drivers/net/altera_tse.h | 81 
> 
>  1 file changed, 41 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/net/altera_tse.h b/drivers/net/altera_tse.h
> index 7b92b12..1652e40 100644
> --- a/drivers/net/altera_tse.h
> +++ b/drivers/net/altera_tse.h
> @@ -167,57 +167,58 @@ struct alt_tse_mac {
>   u32 min_tx_ipg_length;
>  
>   /* IEEE 802.3 oEntity Managed Object Support */
> - u32 aMACID_1;   /*The MAC addresses */
> - u32 aMACID_2;
> - u32 aFramesTransmittedOK;
> - u32 aFramesReceivedOK;
> - u32 aFramesCheckSequenceErrors;
> - u32 aAlignmentErrors;
> - u32 aOctetsTransmittedOK;
> - u32 aOctetsReceivedOK;
> + u32 mac_id_1;
> + u32 mac_id_2;
> + u32 frames_transmitted_ok;
> + u32 frames_received_ok;
> + u32 frames_check_sequence_errors;
> + u32 alignment_errors;
> + u32 octets_transmitted_ok;
> + u32 octets_received_ok;
>  
>   /* IEEE 802.3 oPausedEntity Managed Object Support */
> - u32 aTxPAUSEMACCtrlFrames;
> - u32 aRxPAUSEMACCtrlFrames;
> + u32 tx_pause_mac_ctrl_frames;
> + u32 rx_pause_mac_ctrl_frames;
>  
>   /* IETF MIB (MIB-II) Object Support */
> - u32 ifInErrors;
> - u32 ifOutErrors;
> - u32 ifInUcastPkts;
> - u32 ifInMulticastPkts;
> - u32 ifInBroadcastPkts;
> - u32 ifOutDiscards;
> - u32 ifOutUcastPkts;
> - u32 ifOutMulticastPkts;
> - u32 ifOutBroadcastPkts;
> + u32 if_in_errors;
> + u32 if_out_errors;
> + u32 if_in_ucast_pkts;
> + u32 if_in_multicast_pkts;
> + u32 if_in_broadcast_pkts;
> + u32 if_out_discards;
> + u32 if_out_ucast_pkts;
> + u32 if_out_multicast_pkts;
> + u32 if_out_broadcast_pkts;
>  
>   /* IETF RMON MIB Object Support */
> - u32 etherStatsDropEvent;
> - u32 etherStatsOctets;
> - u32 etherStatsPkts;
> - u32 etherStatsUndersizePkts;
> - u32 etherStatsOversizePkts;
> - u32 etherStatsPkts64Octets;
> - u32 etherStatsPkts65to127Octets;
> - u32 etherStatsPkts128to255Octets;
> - u32 etherStatsPkts256to511Octets;
> - u32 etherStatsPkts512to1023Octets;
> - u32 etherStatsPkts1024to1518Octets;
> -
> - u32 etherStatsPkts1519toXOctets;
> - u32 etherStatsJabbers;
> - u32 etherStatsFragments;
> -
> - u32 reservedxE4;
> + u32 ether_stats_drop_events;
> + u32 ether_stats_octets;
> + u32 ether_stats_pkts;
> + u32 ether_stats_undersize_pkts;
> + u32 ether_stats_oversize_pkts;
> + u32 ether_stats_pkts_64_octets;
> + u32 ether_stats_pkts_65to127_octets;
> + u32 ether_stats_pkts_128to255_octets;
> + u32 ether_stats_pkts_256to511_octets;
> + u32 ether_stats_pkts_512to1023_octets;
> + u32 ether_stats_pkts_1024to1518_octets;
> + u32 ether_stats_pkts_1519tox_octets;
> + u32 ether_stats_jabbers;
> + u32 ether_stats_fragments;
> +
> + u32 reserved2;
>  
>   /*FIFO control register. */
>   u32 tx_cmd_stat;
>   u32 rx_cmd_stat;
>  
> - u32 ipaccTxConf;
> - u32 ipaccRxConf;
> - u32 ipaccRxStat;
> - u32 ipaccRxStatSum;
> + /* Extended Statistics Counters */
> + u32 msb_octets_transmitted_ok;
> + u32 msb_octets_received_ok;
> + u32 msb_ether_stats_octets;
> +
> + u32 reserved3;
>  
>   /*Multicast address resolution table */
>   u32 hash_table[64];

It seems these declaration are not used in the altera_tse.c.

Thanks
Chin Liang
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Re: [U-Boot] [PATCH 2/6] net: altera_tse: fix packed and aligned attribute

[Chin Liang See]

On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Fix packed and aligned attribute warnings.
> 
> WARNING: __packed is preferred over __attribute__((packed))
> #14: FILE: drivers/net/altera_tse.h:14:
> +#define __packed_1___attribute__ ((packed, aligned(1)))
> 
> WARNING: __aligned(size) is preferred over
> __attribute__((aligned(size)))
> #14: FILE: drivers/net/altera_tse.h:14:
> +#define __packed_1___attribute__ ((packed, aligned(1)))
> 
> Signed-off-by: Thomas Chou 

Reviewed-by: Chin Liang See 

Thanks
Chin Liang
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Re: [U-Boot] [PATCH 1/6] net: altera_tse: use data type u32 for regs and desc

[Chin Liang See]

On Wed, 2015-11-04 at 17:12 +0800, tho...@wytron.com.tw wrote:
> Use data type u32/u16/u8 for regs and desc, as it is more
> portable.
> 
> Signed-off-by: Thomas Chou 


Reviewed-by: Chin Liang See 

Thanks
Chin Liang
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