[U-Boot] [PATCH v3 2/2] ARM: dts: at91: add dts file for sama5d4ek

[Wenyou Yang]

Add the dts file for sama5d4ek board.

The dts file is copied from the kernel, do the changes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Remove unneeded the pinctrl node for cs pin of spi0.

 arch/arm/dts/Makefile   |   3 +
 arch/arm/dts/at91-sama5d4ek.dts | 334 
 2 files changed, 337 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d4ek.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 47af809..2929b7a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,9 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D4EK) += \
+   at91-sama5d4ek.dtb
+
 dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
at91-sama5d4_xplained.dtb
 
diff --git a/arch/arm/dts/at91-sama5d4ek.dts b/arch/arm/dts/at91-sama5d4ek.dts
new file mode 100644
index 000..ea141da
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4ek.dts
@@ -0,0 +1,334 @@
+/*
+ * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
+ *
+ *  Copyright (C) 2014 Atmel,
+ *2014 Nicolas Ferre 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+   model = "Atmel SAMA5D4-EK";
+   compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
+
+   aliases {
+   spi0 = 
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+
+   memory {
+   reg = <0x2000 0x2000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   adc0: adc@fc034000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <
+   /* external trigger conflicts with 
USBA_VBUS */
+   _adc0_ad0
+   _adc0_ad1
+   _adc0_ad2
+   _adc0_ad3
+   _adc0_ad4
+   >;
+   /* The vref depends on JP22 of EK. If connect 
1-2 then use 3.3V. connect 2-3 use 3.0V */
+   atmel,adc-vref = <3300>;
+   /*atmel,adc-ts-wires = <4>;*/   /* Set up ADC 
touch screen */
+   status = "okay";/* Enable ADC 
IIO support */
+   };
+
+   mmc0: mmc@f800 {
+   pinctrl-names = "default";
+   pinctrl-0 = 

[U-Boot] [PATCH v3 1/2] ARM: dts: at91: add dts files for sama5d4 Xplained

[Wenyou Yang]

Add the dts files for sama5d4 Xplained board.

The dts file is copied from the kernel, do the following changes.
 - add reg property for pinctrl node.
 - move the gpio (pioA, pioB, pioC ...) nodes from the pinctrl
   child's nodes to its slibling nodes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Remove unneeded the pinctrl node for cs pin of spi0.

 arch/arm/dts/Makefile  |3 +
 arch/arm/dts/at91-sama5d4_xplained.dts |  279 +
 arch/arm/dts/sama5d4.dtsi  | 1910 
 3 files changed, 2192 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts
 create mode 100644 arch/arm/dts/sama5d4.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8dbaea0..47af809 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,9 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \
+   at91-sama5d4_xplained.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/at91-sama5d4_xplained.dts 
b/arch/arm/dts/at91-sama5d4_xplained.dts
new file mode 100644
index 000..5a3c203
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d4_xplained.dts
@@ -0,0 +1,279 @@
+/*
+ * at91-sama5d4_xplained.dts - Device Tree file for SAMA5D4 Xplained board
+ *
+ *  Copyright (C) 2015 Atmel,
+ *2015 Josh Wu 
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "sama5d4.dtsi"
+
+/ {
+   model = "Atmel SAMA5D4 Xplained";
+   compatible = "atmel,sama5d4-xplained", "atmel,sama5d4", "atmel,sama5";
+
+   aliases {
+   spi0 = 
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   memory {
+   reg = <0x2000 0x2000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   spi0: spi@f801 {
+   cs-gpios = < 3 0>, <0>, <0>, <0>;
+   status = "okay";
+   spi_flash@0 {
+   compatible = "spi-flash";
+   spi-max-frequency = <5000>;
+   reg = <0>;
+   };
+   };
+
+   i2c0: i2c@f8014000 {
+   status = "okay";
+   };
+
+   macb0: ethernet@f802 {
+   phy-mode = "rmii";
+   status = "okay";
+   

[U-Boot] [PATCH v3 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D4

[Wenyou Yang]

The purpose of the patchset is add the dts files for boards,
sama5d4 Xplained board and sama5d4ek board.

Changes in v3:
 - Fix the compatible of spi flash, use "spi-flash".
 - Fix the compatible of spi flash, use "spi-flash".

Changes in v2:
 - Remove unneeded the pinctrl node for cs pin of spi0.
 - Remove unneeded the pinctrl node for cs pin of spi0.

Wenyou Yang (2):
  ARM: dts: at91: add dts files for sama5d4 Xplained
  ARM: dts: at91: add dts file for sama5d4ek

 arch/arm/dts/Makefile  |6 +
 arch/arm/dts/at91-sama5d4_xplained.dts |  279 +
 arch/arm/dts/at91-sama5d4ek.dts|  334 ++
 arch/arm/dts/sama5d4.dtsi  | 1910 
 4 files changed, 2529 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d4_xplained.dts
 create mode 100644 arch/arm/dts/at91-sama5d4ek.dts
 create mode 100644 arch/arm/dts/sama5d4.dtsi

-- 
2.7.4

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[U-Boot] [PATCH RESEND v2 2/2] spi: ti_qspi: Fix baudrate divider calculation

[Vignesh R]

Fix the divider calculation logic to choose a value so that the
resulting baudrate is either equal to or closest possible baudrate less
than the requested value. While at that, cleanup ti_spi_set_speed().

Signed-off-by: Vignesh R 
---

v2: cleanup ti_spi_set_speed() a bit.

 drivers/spi/ti_qspi.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c
index 52520dff6325..b5de70bf40e3 100644
--- a/drivers/spi/ti_qspi.c
+++ b/drivers/spi/ti_qspi.c
@@ -16,6 +16,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,21 +119,19 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, 
uint hz)
if (!hz)
clk_div = 0;
else
-   clk_div = (priv->fclk / hz) - 1;
-
-   debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+   clk_div = DIV_ROUND_UP(priv->fclk, hz) - 1;
 
/* disable SCLK */
writel(readl(>base->clk_ctrl) & ~QSPI_CLK_EN,
   >base->clk_ctrl);
 
-   /* assign clk_div values */
-   if (clk_div < 0)
-   clk_div = 0;
-   else if (clk_div > QSPI_CLK_DIV_MAX)
+   /* truncate clk_div value to QSPI_CLK_DIV_MAX */
+   if (clk_div > QSPI_CLK_DIV_MAX)
clk_div = QSPI_CLK_DIV_MAX;
 
-   /* enable SCLK */
+   debug("ti_spi_set_speed: hz: %d, clock divider %d\n", hz, clk_div);
+
+   /* enable SCLK and program the clk divider */
writel(QSPI_CLK_EN | clk_div, >base->clk_ctrl);
 }
 
-- 
2.10.2

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[U-Boot] [PATCH RESEND v2 1/2] ARM: dts: dra7xx: Update spi-max-frequency for qspi slave node

[Vignesh R]

Update the spi-max-frequency property of m25p80 flash slave to match
that of TI QSPI controller node, so that QSPI operations happen at
maximum supported frequency of 76.8MHz.

Signed-off-by: Vignesh R 
Reviewed-by: Jagan Teki 
---

v2: No changes

 arch/arm/dts/dra7-evm.dts  | 2 +-
 arch/arm/dts/dra72-evm-common.dtsi | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts
index fe755c05841d..be36d456206d 100644
--- a/arch/arm/dts/dra7-evm.dts
+++ b/arch/arm/dts/dra7-evm.dts
@@ -505,7 +505,7 @@
spi-max-frequency = <7680>;
m25p80@0 {
compatible = "s25fl256s1","spi-flash";
-   spi-max-frequency = <6400>;
+   spi-max-frequency = <7680>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
diff --git a/arch/arm/dts/dra72-evm-common.dtsi 
b/arch/arm/dts/dra72-evm-common.dtsi
index b0993e5bf7e0..1e1ca725577f 100644
--- a/arch/arm/dts/dra72-evm-common.dtsi
+++ b/arch/arm/dts/dra72-evm-common.dtsi
@@ -441,7 +441,7 @@
spi-max-frequency = <7680>;
m25p80@0 {
compatible = "s25fl256s1", "spi-flash";
-   spi-max-frequency = <6400>;
+   spi-max-frequency = <7680>;
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
-- 
2.10.2

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[U-Boot] [RESEND PATCH v2 2/2] ARM: at91: dt: add dts file for sama5d3 Xplained

[Wenyou Yang]

Add the dts file for sama5d3 Xplained board.

The dts files is copied from the kernel, do changes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/at91-sama5d3_xplained.dts | 341 +
 2 files changed, 344 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5bc4f06..a65a983 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -298,6 +298,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d36ek.dtb \
sama5d36ek_cmp.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
+   at91-sama5d3_xplained.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts 
b/arch/arm/dts/at91-sama5d3_xplained.dts
new file mode 100644
index 000..2ee2e3b
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d3_xplained.dts
@@ -0,0 +1,341 @@
+/*
+ * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
+ *
+ *  Copyright (C) 2014 Atmel,
+ *   2014 Nicolas Ferre 
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+
+/ {
+   model = "SAMA5D3 Xplained";
+   compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   spi0 = 
+   };
+
+   memory {
+   reg = <0x2000 0x1000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   mmc0: mmc@f000 {
+   pinctrl-0 = <_mmc0_clk_cmd_dat0 
_mmc0_dat1_3 _mmc0_dat4_7 _mmc0_cd>;
+   vmmc-supply = <_mmc0_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "okay";
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   cd-gpios = < 0 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   mmc1: mmc@f800 {
+   vmmc-supply = <_3v3_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "disabled";
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   cd-gpios = < 1 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   spi0: spi@f0004000 {
+   cs-gpios = < 13 0>, <0>, <0>, < 16 0>;
+   status = "okay";
+   };
+
+   can0: can@f000c000 {
+   status = "okay";
+   };
+
+   i2c0: i2c@f0014000 {
+   pinctrl-0 = <_i2c0_pu>;
+   status = "okay";
+   };
+
+   i2c1: i2c@f0018000 {
+   status = "okay";
+
+   pmic: act8865@5b {
+   compatible = "active-semi,act8865";
+   reg = <0x5b>;
+   status = "disabled";
+
+   regulators {
+   vcc_1v8_reg: DCDC_REG1 {
+   regulator-name = 
"VCC_1V8";
+   regulator-min-microvolt 
= <180>;
+   regulator-max-microvolt 
= <180>;
+   regulator-always-on;
+   };
+
+   vcc_1v2_reg: DCDC_REG2 {
+   regulator-name = 
"VCC_1V2";
+   regulator-min-microvolt 
= <120>;
+   regulator-max-microvolt 
= <120>;
+   regulator-always-on;
+   };
+
+   vcc_3v3_reg: DCDC_REG3 {
+   

[U-Boot] [RESEND PATCH v2 1/2] ARM: at91: dt: add dts files for sama5d3ek board

[Wenyou Yang]

Add the dts files for sama5d3ek board.

The dts files is copied from the kernel, do changes as below.
 - add reg property for the pinctrl node.
 - move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v2:
 - Fix spi flash compatible using "spi-flash".

 arch/arm/dts/Makefile|4 +
 arch/arm/dts/sama5d3.dtsi| 1505 ++
 arch/arm/dts/sama5d31.dtsi   |   16 +
 arch/arm/dts/sama5d31ek.dts  |   52 ++
 arch/arm/dts/sama5d33.dtsi   |   14 +
 arch/arm/dts/sama5d33ek.dts  |   45 ++
 arch/arm/dts/sama5d34.dtsi   |   16 +
 arch/arm/dts/sama5d34ek.dts  |   62 ++
 arch/arm/dts/sama5d35.dtsi   |   18 +
 arch/arm/dts/sama5d35ek.dts  |   55 ++
 arch/arm/dts/sama5d36.dtsi   |   20 +
 arch/arm/dts/sama5d36ek.dts  |   57 ++
 arch/arm/dts/sama5d36ek_cmp.dts  |   55 ++
 arch/arm/dts/sama5d3_can.dtsi|   74 ++
 arch/arm/dts/sama5d3_emac.dtsi   |   55 ++
 arch/arm/dts/sama5d3_gmac.dtsi   |   88 +++
 arch/arm/dts/sama5d3_lcd.dtsi|  215 ++
 arch/arm/dts/sama5d3_mci2.dtsi   |   59 ++
 arch/arm/dts/sama5d3_tcb1.dtsi   |   39 +
 arch/arm/dts/sama5d3_uart.dtsi   |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi |  123 
 arch/arm/dts/sama5d3xcm_cmp.dtsi |  166 +
 arch/arm/dts/sama5d3xdm.dtsi |   41 ++
 arch/arm/dts/sama5d3xmb.dtsi |  221 ++
 arch/arm/dts/sama5d3xmb_cmp.dtsi |  230 ++
 25 files changed, 3309 insertions(+)
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8dbaea0..5bc4f06 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,10 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
+   sama5d36ek.dtb \
+   sama5d36ek_cmp.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
new file mode 100644
index 000..bb4ff30
--- /dev/null
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -0,0 +1,1505 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 
SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *2013 Ludovic Desroches 
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Atmel SAMA5D3 family SoC";
+   compatible = "atmel,sama5d3", "atmel,sama5";
+   interrupt-parent = <>;
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   tcb0 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   ssc0 = 
+   ssc1 = 
+   pwm0 = 
+   };
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a5";
+   reg = <0x0>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,cortex-a5-pmu";
+   interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
+   };
+
+   memory {
+   reg = <0x2000 0x800>;
+   };
+
+   clocks {
+   slow_xtal: slow_xtal {
+   compatible = "fixed-clock";
+   

[U-Boot] [RESEND PATCH v2 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3

[Wenyou Yang]

The purpose of the patchset is add the dts files for boards,
sama5d3 Xplained board and sama5d3xek board.

Changes in v2:
 - Fix spi flash compatible using "spi-flash".

Wenyou Yang (2):
  ARM: at91: dt: add dts files for sama5d3ek board
  ARM: at91: dt: add dts file for sama5d3 Xplained

 arch/arm/dts/Makefile  |7 +
 arch/arm/dts/at91-sama5d3_xplained.dts |  341 
 arch/arm/dts/sama5d3.dtsi  | 1505 
 arch/arm/dts/sama5d31.dtsi |   16 +
 arch/arm/dts/sama5d31ek.dts|   52 ++
 arch/arm/dts/sama5d33.dtsi |   14 +
 arch/arm/dts/sama5d33ek.dts|   45 +
 arch/arm/dts/sama5d34.dtsi |   16 +
 arch/arm/dts/sama5d34ek.dts|   62 ++
 arch/arm/dts/sama5d35.dtsi |   18 +
 arch/arm/dts/sama5d35ek.dts|   55 ++
 arch/arm/dts/sama5d36.dtsi |   20 +
 arch/arm/dts/sama5d36ek.dts|   57 ++
 arch/arm/dts/sama5d36ek_cmp.dts|   55 ++
 arch/arm/dts/sama5d3_can.dtsi  |   74 ++
 arch/arm/dts/sama5d3_emac.dtsi |   55 ++
 arch/arm/dts/sama5d3_gmac.dtsi |   88 ++
 arch/arm/dts/sama5d3_lcd.dtsi  |  215 +
 arch/arm/dts/sama5d3_mci2.dtsi |   59 ++
 arch/arm/dts/sama5d3_tcb1.dtsi |   39 +
 arch/arm/dts/sama5d3_uart.dtsi |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi   |  123 +++
 arch/arm/dts/sama5d3xcm_cmp.dtsi   |  166 
 arch/arm/dts/sama5d3xdm.dtsi   |   41 +
 arch/arm/dts/sama5d3xmb.dtsi   |  221 +
 arch/arm/dts/sama5d3xmb_cmp.dtsi   |  230 +
 26 files changed, 3653 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi

-- 
2.7.4

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[U-Boot] [PATCH v2 1/2] ARM: at91: dt: add dts files for sama5d3ek board

[Wenyou Yang]

Add the dts files for sama5d3ek board.

The dts files is copied from the kernel, do changes as below.
 - add reg property for the pinctrl node.
 - move the gpio (pioA, pioB, pioC ...) nodes as the pinctrl's
   slibling nodes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
ARM: at91: sama5d3: fix spi

---

Changes in v2:
 - Fix spi flash compatible using "spi-flash".

 arch/arm/dts/Makefile|4 +
 arch/arm/dts/sama5d3.dtsi| 1505 ++
 arch/arm/dts/sama5d31.dtsi   |   16 +
 arch/arm/dts/sama5d31ek.dts  |   52 ++
 arch/arm/dts/sama5d33.dtsi   |   14 +
 arch/arm/dts/sama5d33ek.dts  |   45 ++
 arch/arm/dts/sama5d34.dtsi   |   16 +
 arch/arm/dts/sama5d34ek.dts  |   62 ++
 arch/arm/dts/sama5d35.dtsi   |   18 +
 arch/arm/dts/sama5d35ek.dts  |   55 ++
 arch/arm/dts/sama5d36.dtsi   |   20 +
 arch/arm/dts/sama5d36ek.dts  |   57 ++
 arch/arm/dts/sama5d36ek_cmp.dts  |   55 ++
 arch/arm/dts/sama5d3_can.dtsi|   74 ++
 arch/arm/dts/sama5d3_emac.dtsi   |   55 ++
 arch/arm/dts/sama5d3_gmac.dtsi   |   88 +++
 arch/arm/dts/sama5d3_lcd.dtsi|  215 ++
 arch/arm/dts/sama5d3_mci2.dtsi   |   59 ++
 arch/arm/dts/sama5d3_tcb1.dtsi   |   39 +
 arch/arm/dts/sama5d3_uart.dtsi   |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi |  123 
 arch/arm/dts/sama5d3xcm_cmp.dtsi |  166 +
 arch/arm/dts/sama5d3xdm.dtsi |   41 ++
 arch/arm/dts/sama5d3xmb.dtsi |  221 ++
 arch/arm/dts/sama5d3xmb_cmp.dtsi |  230 ++
 25 files changed, 3309 insertions(+)
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8dbaea0..5bc4f06 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -294,6 +294,10 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
 dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
+   sama5d36ek.dtb \
+   sama5d36ek_cmp.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/sama5d3.dtsi b/arch/arm/dts/sama5d3.dtsi
new file mode 100644
index 000..bb4ff30
--- /dev/null
+++ b/arch/arm/dts/sama5d3.dtsi
@@ -0,0 +1,1505 @@
+/*
+ * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
+ *applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 
SoC
+ *
+ *  Copyright (C) 2013 Atmel,
+ *2013 Ludovic Desroches 
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include "skeleton.dtsi"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/ {
+   model = "Atmel SAMA5D3 family SoC";
+   compatible = "atmel,sama5d3", "atmel,sama5";
+   interrupt-parent = <>;
+
+   aliases {
+   serial0 = 
+   serial1 = 
+   serial2 = 
+   serial3 = 
+   serial4 = 
+   serial5 = 
+   gpio0 = 
+   gpio1 = 
+   gpio2 = 
+   gpio3 = 
+   gpio4 = 
+   tcb0 = 
+   i2c0 = 
+   i2c1 = 
+   i2c2 = 
+   ssc0 = 
+   ssc1 = 
+   pwm0 = 
+   };
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   cpu@0 {
+   device_type = "cpu";
+   compatible = "arm,cortex-a5";
+   reg = <0x0>;
+   };
+   };
+
+   pmu {
+   compatible = "arm,cortex-a5-pmu";
+   interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
+   };
+
+   memory {
+   reg = <0x2000 0x800>;
+   };
+
+   clocks {
+   slow_xtal: slow_xtal {
+   compatible = 

[U-Boot] [PATCH v2 2/2] ARM: at91: dt: add dts file for sama5d3 Xplained

[Wenyou Yang]

Add the dts file for sama5d3 Xplained board.

The dts files is copied from the kernel, do changes.
 - fix the compile warning.

Signed-off-by: Wenyou Yang 
---

Changes in v2: None

 arch/arm/dts/Makefile  |   3 +
 arch/arm/dts/at91-sama5d3_xplained.dts | 341 +
 2 files changed, 344 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 5bc4f06..a65a983 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -298,6 +298,9 @@ dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \
sama5d36ek.dtb \
sama5d36ek_cmp.dtb
 
+dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \
+   at91-sama5d3_xplained.dtb
+
 targets += $(dtb-y)
 
 # Add any required device tree compiler flags here
diff --git a/arch/arm/dts/at91-sama5d3_xplained.dts 
b/arch/arm/dts/at91-sama5d3_xplained.dts
new file mode 100644
index 000..2ee2e3b
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d3_xplained.dts
@@ -0,0 +1,341 @@
+/*
+ * at91-sama5d3_xplained.dts - Device Tree file for the SAMA5D3 Xplained board
+ *
+ *  Copyright (C) 2014 Atmel,
+ *   2014 Nicolas Ferre 
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "sama5d36.dtsi"
+
+/ {
+   model = "SAMA5D3 Xplained";
+   compatible = "atmel,sama5d3-xplained", "atmel,sama5d3", "atmel,sama5";
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   };
+
+   aliases {
+   spi0 = 
+   };
+
+   memory {
+   reg = <0x2000 0x1000>;
+   };
+
+   clocks {
+   slow_xtal {
+   clock-frequency = <32768>;
+   };
+
+   main_xtal {
+   clock-frequency = <1200>;
+   };
+   };
+
+   ahb {
+   apb {
+   mmc0: mmc@f000 {
+   pinctrl-0 = <_mmc0_clk_cmd_dat0 
_mmc0_dat1_3 _mmc0_dat4_7 _mmc0_cd>;
+   vmmc-supply = <_mmc0_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "okay";
+   slot@0 {
+   reg = <0>;
+   bus-width = <8>;
+   cd-gpios = < 0 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   mmc1: mmc@f800 {
+   vmmc-supply = <_3v3_reg>;
+   vqmmc-supply = <_3v3_reg>;
+   status = "disabled";
+   slot@0 {
+   reg = <0>;
+   bus-width = <4>;
+   cd-gpios = < 1 GPIO_ACTIVE_LOW>;
+   };
+   };
+
+   spi0: spi@f0004000 {
+   cs-gpios = < 13 0>, <0>, <0>, < 16 0>;
+   status = "okay";
+   };
+
+   can0: can@f000c000 {
+   status = "okay";
+   };
+
+   i2c0: i2c@f0014000 {
+   pinctrl-0 = <_i2c0_pu>;
+   status = "okay";
+   };
+
+   i2c1: i2c@f0018000 {
+   status = "okay";
+
+   pmic: act8865@5b {
+   compatible = "active-semi,act8865";
+   reg = <0x5b>;
+   status = "disabled";
+
+   regulators {
+   vcc_1v8_reg: DCDC_REG1 {
+   regulator-name = 
"VCC_1V8";
+   regulator-min-microvolt 
= <180>;
+   regulator-max-microvolt 
= <180>;
+   regulator-always-on;
+   };
+
+   vcc_1v2_reg: DCDC_REG2 {
+   regulator-name = 
"VCC_1V2";
+   regulator-min-microvolt 
= <120>;
+   regulator-max-microvolt 
= <120>;
+   regulator-always-on;
+   };
+
+   vcc_3v3_reg: DCDC_REG3 {
+   

[U-Boot] [PATCH v2 0/2] ARM: dts: at91: add dts files for the boards of SAMA5D3

[Wenyou Yang]

The purpose of the patchset is add the dts files for boards,
sama5d3 Xplained board and sama5d3xek board.

Changes in v2:
 - Fix spi flash compatible using "spi-flash".

Wenyou Yang (2):
  ARM: at91: dt: add dts files for sama5d3ek board
  ARM: at91: dt: add dts file for sama5d3 Xplained

 arch/arm/dts/Makefile  |7 +
 arch/arm/dts/at91-sama5d3_xplained.dts |  341 
 arch/arm/dts/sama5d3.dtsi  | 1505 
 arch/arm/dts/sama5d31.dtsi |   16 +
 arch/arm/dts/sama5d31ek.dts|   52 ++
 arch/arm/dts/sama5d33.dtsi |   14 +
 arch/arm/dts/sama5d33ek.dts|   45 +
 arch/arm/dts/sama5d34.dtsi |   16 +
 arch/arm/dts/sama5d34ek.dts|   62 ++
 arch/arm/dts/sama5d35.dtsi |   18 +
 arch/arm/dts/sama5d35ek.dts|   55 ++
 arch/arm/dts/sama5d36.dtsi |   20 +
 arch/arm/dts/sama5d36ek.dts|   57 ++
 arch/arm/dts/sama5d36ek_cmp.dts|   55 ++
 arch/arm/dts/sama5d3_can.dtsi  |   74 ++
 arch/arm/dts/sama5d3_emac.dtsi |   55 ++
 arch/arm/dts/sama5d3_gmac.dtsi |   88 ++
 arch/arm/dts/sama5d3_lcd.dtsi  |  215 +
 arch/arm/dts/sama5d3_mci2.dtsi |   59 ++
 arch/arm/dts/sama5d3_tcb1.dtsi |   39 +
 arch/arm/dts/sama5d3_uart.dtsi |   79 ++
 arch/arm/dts/sama5d3xcm.dtsi   |  123 +++
 arch/arm/dts/sama5d3xcm_cmp.dtsi   |  166 
 arch/arm/dts/sama5d3xdm.dtsi   |   41 +
 arch/arm/dts/sama5d3xmb.dtsi   |  221 +
 arch/arm/dts/sama5d3xmb_cmp.dtsi   |  230 +
 26 files changed, 3653 insertions(+)
 create mode 100644 arch/arm/dts/at91-sama5d3_xplained.dts
 create mode 100644 arch/arm/dts/sama5d3.dtsi
 create mode 100644 arch/arm/dts/sama5d31.dtsi
 create mode 100644 arch/arm/dts/sama5d31ek.dts
 create mode 100644 arch/arm/dts/sama5d33.dtsi
 create mode 100644 arch/arm/dts/sama5d33ek.dts
 create mode 100644 arch/arm/dts/sama5d34.dtsi
 create mode 100644 arch/arm/dts/sama5d34ek.dts
 create mode 100644 arch/arm/dts/sama5d35.dtsi
 create mode 100644 arch/arm/dts/sama5d35ek.dts
 create mode 100644 arch/arm/dts/sama5d36.dtsi
 create mode 100644 arch/arm/dts/sama5d36ek.dts
 create mode 100644 arch/arm/dts/sama5d36ek_cmp.dts
 create mode 100644 arch/arm/dts/sama5d3_can.dtsi
 create mode 100644 arch/arm/dts/sama5d3_emac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_gmac.dtsi
 create mode 100644 arch/arm/dts/sama5d3_lcd.dtsi
 create mode 100644 arch/arm/dts/sama5d3_mci2.dtsi
 create mode 100644 arch/arm/dts/sama5d3_tcb1.dtsi
 create mode 100644 arch/arm/dts/sama5d3_uart.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xcm_cmp.dtsi
 create mode 100644 arch/arm/dts/sama5d3xdm.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb.dtsi
 create mode 100644 arch/arm/dts/sama5d3xmb_cmp.dtsi

-- 
2.7.4

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[U-Boot] [PATCH] fsl: serdes: fix a deadloop issue for P4080

[Zhiqiang Hou]

From: Hou Zhiqiang 

This deadloop is introduced by commit:
71fe222 fsl: serdes: ensure accessing the initialized maps of serdes protocol

deadloop detail:
cpu_init_r => fsl_serdes_init => p4080_erratum_serdes_a005 =>
is_serdes_configured => fsl_serdes_init

Signed-off-by: Hou Zhiqiang 
---
 arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c 
b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 72d5e30..b6c4341 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -607,6 +607,9 @@ void fsl_serdes_init(void)
 
soc_serdes_init();
 
+   /* Set the first bit to indicate serdes has been initialized */
+   serdes_prtcl_map |= (1 << NONE);
+
 #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES8
/*
 * Bank two uses the clock from bank three, so if bank two is enabled,
@@ -862,9 +865,6 @@ void fsl_serdes_init(void)
 SRDS_RSTCTL_SDPD);
}
 #endif
-
-   /* Set the first bit to indicate serdes has been initialized */
-   serdes_prtcl_map |= (1 << NONE);
 }
 
 const char *serdes_clock_to_string(u32 clock)
-- 
2.1.0.27.g96db324

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Re: [U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Vignesh R]

On Sunday 30 October 2016 11:16 PM, Jagan Teki wrote:
[...]
> + {"S25FL128P_64K",  INFO(0x012018, 0x0301,  64 * 1024,   256, RD_FULL | 
> WR_QPP) },
> + {"S25FL032P",  INFO(0x010215, 0x4d00,  64 * 1024,64, RD_FULL | 
> WR_QPP) },
> + {"S25FL064P",  INFO(0x010216, 0x4d00,  64 * 1024,   128, RD_FULL | 
> WR_QPP) },
> + {"S25FL128S_256K", INFO(0x012018, 0x4d00, 256 * 1024,64, RD_FULL | 
> WR_QPP) },
> + {"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | 
> WR_QPP) },
> + {"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
> WR_QPP) },
> + {"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
> WR_QPP) },
> + {"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
> WR_QPP) },
> + {"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
> WR_QPP) },

Could you change above S25FS512S and S25FL512S_256K to use INFO6 macro?
Right now, S25FL512S_256K gets detected as S25FS512S and sf update fails
due as erasesizes are different.

-- 
Regards
Vignesh
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Re: [U-Boot] [PATCH 0/6] Add ARMv8 PSCI framework

[Hongbo Zhang]

Thanks Tom.
I am sending out an updated v2 soon, with the related configs updated.

On Fri, Oct 28, 2016 at 9:30 PM, Tom Rini  wrote:
> On Wed, Sep 28, 2016 at 03:16:38PM +0800, Hongbo Zhang wrote:
>> On Wed, Sep 28, 2016 at 1:23 AM, Tom Rini  wrote:
>> > On Tue, Sep 27, 2016 at 05:29:00PM +0800, macro.wav...@gmail.com wrote:
>> >> From: Hongbo Zhang 
>> >>
>> >> This patch set introduces ARMv8 PSCI framework, all the PSCI functions are
>> >> implemented a default dummy one, it is up to each platform to implement 
>> >> their
>> >> own specific ones.
>> >>
>> >> The first 1/6 patch is a prepare clean up for adding ARMv8 PSCI.
>> >> Patches 2/6 to 5/6 introduce new ARMv8 framework and set it up.
>> >> The last 6/6 adds a most simple implementation on NXP LS1043 platform, to
>> >> verify this framework.
>> >>
>> >> This patch set mainly introduces ARMv8 PSCI framework, for easier review 
>> >> and
>> >> merge, further PSCI implementation on LS1043 is coming later.
>> >>
>> >> Hongbo Zhang (6):
>> >>   ARMv8: LS1043A: change macro CONFIG_ARMV8_PSCI definition
>> >>   ARMv8: Add secure sections for PSCI text and data
>> >>   ARMv8: Add basic PSCI framework
>> >>   ARMv8: Setup PSCI memory and dt
>> >>   ARMv8: Enable SMC instruction
>> >>   ARMv8: LS1043A: Enable LS1043A default PSCI support
>> >
>> > Conceptually this is good.  I have some issues around order of the
>> > patches, and where the Kconfig entries end up.  Looking over the series
>> > we introduce usage of some CONFIG symbols prior to declaring them in
>> > Kconfig.  This is more of a hard no now as it will break bisecting when
>> > the test for no new CONFIG symbols is tripped.  The other problem is
>> > that I think the symbols you're adding in
>> > board/freescale/ls1043ardb/Kconfig need to be in
>> > arch/arm/cpu/armv8/Kconfig and then use default ... if ... to give the
>> > right address for the layerscape boards.
>>
>> Thanks Tom for quick response.
>>
>> For config options introduced:
>> CONFIG_ARMV8_PSCI
>> CONFIG_ARMV8_PSCI_NR_CPUS
>> CONFIG_CPU_PER_CLUSTER
>> CONFIG_ARMV8_SECURE_BASE
>>
>> I've tested adding patch one by one, there is no problem with the
>> check-config script.
>
> OK.
>
>> And my idea was like this: let the CONFIG_ARMV8_PSCI to be an overall
>> switch, and if it is enabled even without the other three ones, the
>> default PSCI still works, as I've tested, this really works because
>> any of the other three macros, when used, there is a #ifdef to check
>> if it exists, if no, a default value is used or it isn't used at all.
>> The later three macros, because they are platform specific so I
>> intended to let every platform to define them.
>>
>> This is slightly different from ARMv7, plan was if this get accepted,
>> I would like to send patch to update ARMv7's.
>
> I think that at the end of the day we need to have less options be
> defined and asked under board/ and make more and in some cases better
> use of the common Kconfig files.  Looking at how things are done in the
> Linux Kernel, in general, can be instructive here.  Maybe the right
> answer here is to have CONFIG_ARCH_WANT_GENERIC_PSCI_... with default y
> (if most cases would be the generic one) and in the negative use the
> other option which is board specific values.
>
> But re-reading patch 6/6, I'm still not convinced that we shouldn't
> start out with these being all in arch/arm/cpu/armv8/Kconfig, under the
> PSCI option, for everyone, and default ... if layerscape.  And that
> reminds that I wonder if we shouldn't have some higher level option to
> say "I am ARMv8 Layerscape" to cover the cases where today we test vs a
> number of TARGET_LS choices.  Thanks!
>
> --
> Tom
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Re: [U-Boot] [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC node

[Wenbin Song]

Hi york:


Best Regards
Wenbin Song

> -Original Message-
> From: york sun
> Sent: Friday, October 28, 2016 11:40 PM
> To: Wenbin Song ; albert.u.b...@aribaud.net;
> Mingkai Hu ; u-boot@lists.denx.de
> Subject: Re: [PATCH v5 1/2] armv8/fsl-layerscape: fdt: fixup LS1043A rev1 GIC
> node
> 
> On 10/27/2016 02:06 AM, Wenbin song wrote:
> > The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
> > alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
> > is used to choose which offset will be used. If GIC_ADDR_BIT bit is
> > set, 4K alignment is used, or else 64K alignment is used. The rev1.0
> > silicon only supports the CIG offset with 4K alignment.
> >
> > GIC offset is decided by SVR and GIC_ADDR_BIT bit.
> >
> > Overriding the weak smp_kick_all_cpus, the new impletment is able to
> > detect GIC offset.
> >
> > Signed-off-by: Wenbin Song 
> > Signed-off-by: Mingkai Hu 
> > ---
> > Changes in v5:
> > Replace fix_gic_off with get_gic_off.
> > Add #if condition to check CONFIG_GICV2 and CONFIG_GICV3 on
> smp_kick_all_cpus.
> > Fixup gic node with 64K alignment when running on rev1.1 with
> GIC_ADDR_BIT cleared.
> > ---
> 
> 
> 
> >
> > +#ifdef CONFIG_HAS_FEATURE_GIC4K_ALIGN static void fdt_fixup_gic(void
> > +*blob) {
> > +   int offset, err;
> > +   u64 reg[8];
> > +   struct ccsr_gur __iomem *gur = (void
> *)(CONFIG_SYS_FSL_GUTS_ADDR);
> > +   unsigned int rev;
> > +   struct ccsr_scfg __iomem *scfg = (void
> *)CONFIG_SYS_FSL_SCFG_ADDR;
> > +   int align_4k = 1;
> > +
> > +   rev = gur_in32(>svr) & 0xff;
> > +
> > +   if (rev > REV1_0) {
> > +   rev = scfg_in32(>gic_align) & (0x01 << GIC_ADDR_BIT);
> > +   if (!rev)
> > +   align_4k = 0;
> > +   }
> > +
> 
> Does this register scfg->gic_align exist for other SoCs? Can you get a 
> consistent
> reading from this register if not set by PBI? If yes, can you revert the 
> logic in PBI
> command to set this bit in backward compatible way?


[]  scfg->gic_align  is a new added  register on ls1043a rev1.1 or more higher  
to select the GIC offset by PBI.
If it is set by PBI,  GIC offset is 4K alignment.
If it is cleared by PBI, GIC offset is 64K alignment.
The reset value is cleared.

So for ls1043a rev1.1 or more higher , we are be able to select the GIC offset  
by using different rcw. 
If  not set by PBI, reading from it always gets  0. 

 And the scfg->gic_align is reserved for other SoCs. 
> 
> York

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[U-Boot] [PATCH V2 2/4] mx6: ddr: pass mx6_ddr_sysinfo to calibration routines

[Eric Nelson]

The DDR calibration routines have scattered support for bus
widths other than 64-bits:

-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.

Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.

This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.

Signed-off-by: Eric Nelson 
Reviewed-by: Marek Vasut 
---
No change in V2
 arch/arm/cpu/armv7/mx6/ddr.c| 98 +++--
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  4 +-
 board/kosagi/novena/novena_spl.c|  4 +-
 3 files changed, 60 insertions(+), 46 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index b15f376..274a0ba 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -86,14 +86,15 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, 
u32 *reg_ctrl)
writel(val_ctrl, reg_ctrl);
 }
 
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 {
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
u32 esdmisc_val, zq_val;
u32 errors = 0;
-   u32 ldectrl[4];
+   u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
+   u32 rwalat_max;
 
/*
 * Stash old values in case calibration fails,
@@ -101,8 +102,10 @@ int mmdc_do_write_level_calibration(void)
 */
ldectrl[0] = readl(>mpwldectrl0);
ldectrl[1] = readl(>mpwldectrl1);
-   ldectrl[2] = readl(>mpwldectrl0);
-   ldectrl[3] = readl(>mpwldectrl1);
+   if (sysinfo->dsize == 2) {
+   ldectrl[2] = readl(>mpwldectrl0);
+   ldectrl[3] = readl(>mpwldectrl1);
+   }
 
/* disable DDR logic power down timer */
clrbits_le32(>mdpdc, 0xff00);
@@ -122,10 +125,10 @@ int mmdc_do_write_level_calibration(void)
writel(zq_val & ~0x3, >mpzqhwctrl);
 
/* 3. increase walat and ralat to maximum */
-   setbits_le32(>mdmisc,
-(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
-   setbits_le32(>mdmisc,
-(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+   rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+   setbits_le32(>mdmisc, rwalat_max);
+   if (sysinfo->dsize == 2)
+   setbits_le32(>mdmisc, rwalat_max);
/*
 * 4 & 5. Configure the external DDR device to enter write-leveling
 * mode through Load Mode Register command.
@@ -152,21 +155,25 @@ int mmdc_do_write_level_calibration(void)
 */
if (readl(>mpwlgcr) & 0x0F00)
errors |= 1;
-   if (readl(>mpwlgcr) & 0x0F00)
-   errors |= 2;
+   if (sysinfo->dsize == 2)
+   if (readl(>mpwlgcr) & 0x0F00)
+   errors |= 2;
 
debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
 
/* check to see if cal failed */
if ((readl(>mpwldectrl0) == 0x001F001F) &&
(readl(>mpwldectrl1) == 0x001F001F) &&
-   (readl(>mpwldectrl0) == 0x001F001F) &&
-   (readl(>mpwldectrl1) == 0x001F001F)) {
+   ((sysinfo->dsize < 2) ||
+((readl(>mpwldectrl0) == 0x001F001F) &&
+ (readl(>mpwldectrl1) == 0x001F001F {
debug("Cal seems to have soft-failed due to memory not 
supporting write leveling on all channels. Restoring original write leveling 
values.\n");
writel(ldectrl[0], >mpwldectrl0);
writel(ldectrl[1], >mpwldectrl1);
-   writel(ldectrl[2], >mpwldectrl0);
-   writel(ldectrl[3], >mpwldectrl1);
+   if (sysinfo->dsize == 2) {
+   writel(ldectrl[2], >mpwldectrl0);
+   writel(ldectrl[3], >mpwldectrl1);
+   }
errors |= 4;
}
 
@@ -189,16 +196,20 @@ int mmdc_do_write_level_calibration(void)
  readl(>mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
  readl(>mpwldectrl1));
-   debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(>mpwldectrl0));
-   debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(>mpwldectrl1));
+   if (sysinfo->dsize == 2) {
+   debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(>mpwldectrl0));
+   debug("\tMMDC_MPWLDECTRL1 

[U-Boot] [PATCH V2 3/4] mx6: ddr: add routine to return DDR calibration data

[Eric Nelson]

Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.

This routine will be used in a subsequent patch set adding a virtual
"mx6memcal" board, but could also be useful when gathering statistics
during an initial production run.

Signed-off-by: Eric Nelson 
---
Commit message expanded in V2

 arch/arm/cpu/armv7/mx6/ddr.c| 23 +++
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 274a0ba..b12fb64 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1501,6 +1501,29 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mdelay(1);
 }
 
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+   struct mx6_mmdc_calibration *calib)
+{
+   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+   struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+   calib->p0_mpwldectrl0 = readl(>mpwldectrl0);
+   calib->p0_mpwldectrl1 = readl(>mpwldectrl1);
+   calib->p0_mpdgctrl0 = readl(>mpdgctrl0);
+   calib->p0_mpdgctrl1 = readl(>mpdgctrl1);
+   calib->p0_mprddlctl = readl(>mprddlctl);
+   calib->p0_mpwrdlctl = readl(>mpwrdlctl);
+
+   if (sysinfo->dsize == 2) {
+   calib->p1_mpwldectrl0 = readl(>mpwldectrl0);
+   calib->p1_mpwldectrl1 = readl(>mpwldectrl1);
+   calib->p1_mpdgctrl0 = readl(>mpdgctrl0);
+   calib->p1_mpdgctrl1 = readl(>mpdgctrl1);
+   calib->p1_mprddlctl = readl(>mprddlctl);
+   calib->p1_mpwrdlctl = readl(>mpwrdlctl);
+   }
+}
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  const struct mx6_mmdc_calibration *calib,
  const void *ddr_cfg)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index cd5bc97..12454fa 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -461,6 +461,8 @@ void mx6sl_dram_iocfg(unsigned width,
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+   struct mx6_mmdc_calibration *calib);
 #endif
 
 /* configure mx6 mmdc registers */
-- 
2.7.4

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[U-Boot] [PATCH V2 4/4] ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

[Eric Nelson]

The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.

Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.

Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/Kconfig  | 8 
 arch/arm/cpu/armv7/mx6/ddr.c| 3 +--
 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +-
 configs/novena_defconfig| 1 +
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..8b2217e 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,6 +35,14 @@ config MX6ULL
bool
select MX6UL
 
+config MX6_DDRCAL
+   bool "Include dynamic DDR calibration routines"
+   depends on SPL
+   default n
+   help
+ Say "Y" if your board uses dynamic (per-boot) DDR calibration.
+ If unsure, say N.
+
 choice
prompt "MX6 board select"
optional
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index b12fb64..0cf391e 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -14,8 +14,7 @@
 #include 
 #include 
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-
+#if defined(CONFIG_MX6_DDRCAL)
 static void reset_read_data_fifos(void)
 {
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 12454fa..2a8d443 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -458,7 +458,7 @@ void mx6sl_dram_iocfg(unsigned width,
  const struct mx6sl_iomux_ddr_regs *,
  const struct mx6sl_iomux_grp_regs *);
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_MX6_DDRCAL)
 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 1ffdddc..9d47d5b 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
-- 
2.7.4

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[U-Boot] [PATCH V2 0/4] mx6: ddr: updates for dynamic DDR calibration

[Eric Nelson]

This set of patches updates the interface to the DDR calibration in 
preparation for the addition of a pseudo-board for calibration on
i.MX6.

The first patch fixes an ommission in the use of the DG_CMP_CYC flag
in register MPDGCTRL0.

The second patch cleans up the handling of bus widths by passing
the system configuration information to the calibration routines.

The third patch adds support for returning the calibration data
written to the MMDC registers.

The fourth patch adds a Kconfig selection to inclut the DDR calibration
routines.

Eric Nelson (4):
  mx6: ddr: allow 32 cycles for DQS gating calibration
  mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
  mx6: ddr: add routine to return DDR calibration data
  ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

 arch/arm/cpu/armv7/mx6/Kconfig  |   5 ++
 arch/arm/cpu/armv7/mx6/ddr.c| 131 +---
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |   8 +-
 board/kosagi/novena/novena_spl.c|   4 +-
 configs/novena_defconfig|   1 +
 5 files changed, 100 insertions(+), 49 deletions(-)

-- 
V2 adds patch 4
2.7.4

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[U-Boot] [PATCH V2 1/4] mx6: ddr: allow 32 cycles for DQS gating calibration

[Eric Nelson]

The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.

Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.

Signed-off-by: Eric Nelson 
Reviewed-by: Marek Vasut 
---
No change in V2.
 arch/arm/cpu/armv7/mx6/ddr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7beb7ea..b15f376 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -347,6 +347,8 @@ int mmdc_do_dqs_calibration(void)
 * 16 before comparing read data.
 */
setbits_le32(>mpdgctrl0, 1 << 30);
+   if (sysinfo->dsize == 2)
+   setbits_le32(>mpdgctrl0, 1 << 30);
 
/* Set bit 28 to start automatic read DQS gating calibration */
setbits_le32(>mpdgctrl0, 5 << 28);
@@ -365,6 +367,11 @@ int mmdc_do_dqs_calibration(void)
if ((bus_size == 0x2) && (readl(>mpdgctrl0) & 0x1000))
errors |= 2;
 
+   /* now disable mpdgctrl0[DG_CMP_CYC] */
+   clrbits_le32(>mpdgctrl0, 1 << 30);
+   if (sysinfo->dsize == 2)
+   clrbits_le32(>mpdgctrl0, 1 << 30);
+
/*
 * DQS gating absolute offset should be modified from
 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
-- 
2.7.4

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Re: [U-Boot] [PATCH] ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

[Eric Nelson]

Thanks Marek,

On 10/30/2016 01:03 PM, Marek Vasut wrote:
> On 10/30/2016 08:20 PM, Eric Nelson wrote:
>> The DDR calibration routines are gated by conditionals for the
>> i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
>> are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
>>
>> Also, since only the Novena board currently uses the dynamic
>> DDR calibration routines, these routines waste space on other
>> boards using SPL.
>>
>> Add a KConfig entry to allow boards to selectively include the
>> DDR calibration routines.
>>
>> Signed-off-by: Eric Nelson 
>> ---
>>  arch/arm/cpu/armv7/mx6/Kconfig  | 5 +
>>  arch/arm/cpu/armv7/mx6/ddr.c| 3 +--
>>  arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +-
>>  configs/novena_defconfig| 1 +
>>  4 files changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
>> index 762a581..32536c0 100644
>> --- a/arch/arm/cpu/armv7/mx6/Kconfig
>> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
>> @@ -35,6 +35,11 @@ config MX6ULL
>>  bool
>>  select MX6UL
>>  
>> +config MX6_DDRCAL
>> +bool "Include dynamic DDR calibration routines"
>> +depends on SPL
>> +default n
> 
> Help text would really be helpful ;)
> 

Cool.

I'll fix this and re-send the series as V2 (with the fourth patch).
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Re: [U-Boot] S5PV210 boot problem

[smart]

Any suggestions? Should I provide more information?


On ۱۶/۱۰/۰۱ 02:55, nader last wrote:

Good day,

I have a custom HW around an s5pv210 soc. It's based on mini210 board 
and uses u-boot v1.3.4 as its bootloader. I want to use a newer 
version of u-boot to boot my HW.
AFAIK in recent version of u-boot (e.g. v2016.09) GONI board is the 
only supported HW which is based on s5pv210 too. I can successfully 
compile the source with this configuration and burn it on an SD card. 
But when I try to boot the HW, it complains about the checksum with 
"SD checksum error" message. The script used to burn u-boot on the SD 
card, calculates the checksum for the first 8192 bytes of u-boot.bin 
and adds it somewhere which used to be working when the u-boot version 
was v1.3.4.

Any help would greatly be appreciated.

Thank you for your time.

Nasser


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Re: [U-Boot] [PATCH] ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

[Marek Vasut]

On 10/30/2016 08:20 PM, Eric Nelson wrote:
> The DDR calibration routines are gated by conditionals for the
> i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
> are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.
> 
> Also, since only the Novena board currently uses the dynamic
> DDR calibration routines, these routines waste space on other
> boards using SPL.
> 
> Add a KConfig entry to allow boards to selectively include the
> DDR calibration routines.
> 
> Signed-off-by: Eric Nelson 
> ---
>  arch/arm/cpu/armv7/mx6/Kconfig  | 5 +
>  arch/arm/cpu/armv7/mx6/ddr.c| 3 +--
>  arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +-
>  configs/novena_defconfig| 1 +
>  4 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
> index 762a581..32536c0 100644
> --- a/arch/arm/cpu/armv7/mx6/Kconfig
> +++ b/arch/arm/cpu/armv7/mx6/Kconfig
> @@ -35,6 +35,11 @@ config MX6ULL
>   bool
>   select MX6UL
>  
> +config MX6_DDRCAL
> + bool "Include dynamic DDR calibration routines"
> + depends on SPL
> + default n

Help text would really be helpful ;)

>  choice
>   prompt "MX6 board select"
>   optional
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index b12fb64..0cf391e 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -14,8 +14,7 @@
>  #include 
>  #include 
>  
> -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
> -
> +#if defined(CONFIG_MX6_DDRCAL)
>  static void reset_read_data_fifos(void)
>  {
>   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
> b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> index 12454fa..2a8d443 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -458,7 +458,7 @@ void mx6sl_dram_iocfg(unsigned width,
> const struct mx6sl_iomux_ddr_regs *,
> const struct mx6sl_iomux_grp_regs *);
>  
> -#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
> +#if defined(CONFIG_MX6_DDRCAL)
>  int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
>  int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
>  void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
> diff --git a/configs/novena_defconfig b/configs/novena_defconfig
> index 1ffdddc..9d47d5b 100644
> --- a/configs/novena_defconfig
> +++ b/configs/novena_defconfig
> @@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
>  CONFIG_SPL_GPIO_SUPPORT=y
>  CONFIG_SPL_LIBCOMMON_SUPPORT=y
>  CONFIG_SPL_LIBGENERIC_SUPPORT=y
> +CONFIG_MX6_DDRCAL=y
>  CONFIG_TARGET_KOSAGI_NOVENA=y
>  CONFIG_SPL_EXT_SUPPORT=y
>  CONFIG_SPL_FAT_SUPPORT=y
> 


-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 3/3] mx6: ddr: add routine to return DDR calibration data

[Marek Vasut]

On 10/30/2016 08:14 PM, Eric Nelson wrote:
> Hi Marek,

Hi!

> On 10/30/2016 10:30 AM, Marek Vasut wrote:
>> On 10/30/2016 06:19 PM, Eric Nelson wrote:
>>> Add routine mmdc_read_calibration() to return the output of DDR
>>> calibration. This can be used for debugging or to aid in construction
>>> of static memory configuration.
>>>
>>> Signed-off-by: Eric Nelson 
>>
>> Do you plan to use it or will this be mostly dead code ?
>>
> 
> I plan to use it.
> 
> I'm cleaning things up before (re)sending a patch adding the
> virtual "mx6memcal" board and wanted to push the supporting
> changes in a separate set.

Oh cool, all right.

> I have one more independent patch (4/3?) to send before
> the new board.
> 


-- 
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Re: [U-Boot] [Resend PATCH] tools: imximage: use 'new style' header length for imximage v1

[Martin Kaiser]

Thus wrote Martin Kaiser (li...@kaiser.cx):

> Resending this patch after one month of silence. Is there anything I can do to
> get this reviewed? My tests haven't shown any problems so far.

I just saw that the patch doesn't apply to master any more. I'll check
this and send an updated version.

Sorry for the noise,

   Martin
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[U-Boot] [Resend PATCH] tools: imximage: use 'new style' header length for imximage v1

[Martin Kaiser]

From: Martin Kaiser 

We can use the same mechanism for the imximage v1 header length
calculations that we're using for v2. Doing so, we can share more code
between v1 and v2.

Additionally, *header_size_ptr in imximage_set_header() will then have
the correct value for both v1 and v2.

Signed-off-by: Martin Kaiser 
---

I discovered the problem when I tried to use csf_ptr with imximage v1
(as part of a private modification).

*csf_ptr = params->ep + *header_size_ptr - imximage_init_loadsize;
 = params->ep + sbuf->st_size +
 imximage_ivt_offset - imximage_init_loadsize;
 = params->ep + padded data file size + alloc_len -
 (imximage_init_loadsize - imximage_ivt_offset);

This works only if
alloc_len == imximage_init_loadsize - imximage_ivt_offset,
not if alloc_len is always 4096.

 tools/imximage.c |   43 ---
 1 file changed, 20 insertions(+), 23 deletions(-)




Resending this patch after one month of silence. Is there anything I can do to
get this reviewed? My tests haven't shown any problems so far.



diff --git a/tools/imximage.c b/tools/imximage.c
index 092d550..e280da6 100644
--- a/tools/imximage.c
+++ b/tools/imximage.c
@@ -291,8 +291,7 @@ static void set_imx_hdr_v1(struct imx_header *imxhdr, 
uint32_t dcd_len,
/* Set magic number */
fhdr_v1->app_code_barker = APP_CODE_BARKER;
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   hdr_base = entry_point - 4096;
+   hdr_base = entry_point - imximage_init_loadsize + flash_offset;
fhdr_v1->app_dest_ptr = hdr_base - flash_offset;
fhdr_v1->app_code_jump_vector = entry_point;
 
@@ -649,6 +648,7 @@ static void imximage_set_header(void *ptr, struct stat 
*sbuf, int ifd,
 {
struct imx_header *imxhdr = (struct imx_header *)ptr;
uint32_t dcd_len;
+   uint32_t imx_hdr_size;
 
/*
 * In order to not change the old imx cfg file
@@ -664,12 +664,13 @@ static void imximage_set_header(void *ptr, struct stat 
*sbuf, int ifd,
/* Parse dcd configuration file */
dcd_len = parse_cfg_file(imxhdr, params->imagename);
 
-   if (imximage_version == IMXIMAGE_V2) {
-   if (imximage_init_loadsize < imximage_ivt_offset +
-   sizeof(imx_header_v2_t))
-   imximage_init_loadsize = imximage_ivt_offset +
-   sizeof(imx_header_v2_t);
-   }
+   if (imximage_version == IMXIMAGE_V1)
+   imx_hdr_size = sizeof(imx_header_v1_t);
+   else
+   imx_hdr_size = sizeof(imx_header_v2_t);
+
+   if (imximage_init_loadsize < imximage_ivt_offset + imx_hdr_size)
+   imximage_init_loadsize = imximage_ivt_offset + imx_hdr_size;
 
/* Set the imx header */
(*set_imx_hdr)(imxhdr, dcd_len, params->ep, imximage_ivt_offset);
@@ -722,6 +723,7 @@ static int imximage_generate(struct image_tool_params 
*params,
struct stat sbuf;
char *datafile = params->datafile;
uint32_t pad_len;
+   uint32_t imx_hdr_size;
 
memset(_header, 0, sizeof(imximage_header));
 
@@ -739,16 +741,15 @@ static int imximage_generate(struct image_tool_params 
*params,
/* Parse dcd configuration file */
parse_cfg_file(_header, params->imagename);
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   if (imximage_version == IMXIMAGE_V1) {
-   alloc_len = 4096;
-   } else {
-   if (imximage_init_loadsize < imximage_ivt_offset +
-   sizeof(imx_header_v2_t))
-   imximage_init_loadsize = imximage_ivt_offset +
-   sizeof(imx_header_v2_t);
-   alloc_len = imximage_init_loadsize - imximage_ivt_offset;
-   }
+   if (imximage_version == IMXIMAGE_V1)
+   imx_hdr_size = sizeof(imx_header_v1_t);
+   else
+   imx_hdr_size = sizeof(imx_header_v2_t);
+
+   if (imximage_init_loadsize < imximage_ivt_offset + imx_hdr_size)
+   imximage_init_loadsize = imximage_ivt_offset + imx_hdr_size;
+
+   alloc_len = imximage_init_loadsize - imximage_ivt_offset;
 
if (alloc_len < sizeof(struct imx_header)) {
fprintf(stderr, "%s: header error\n",
@@ -779,11 +780,7 @@ static int imximage_generate(struct image_tool_params 
*params,
 
pad_len = ROUND(sbuf.st_size, 4096) - sbuf.st_size;
 
-   /* TODO: check i.MX image V1 handling, for now use 'old' style */
-   if (imximage_version == IMXIMAGE_V1)
-   return 0;
-   else
-   return pad_len;
+   return pad_len;
 }
 
 
-- 
1.7.10.4

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[U-Boot] [PATCH] ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

[Eric Nelson]

The DDR calibration routines are gated by conditionals for the
i.MX6DQ SOCs, but with the use of the sysinfo parameter, these
are usable on at least i.MX6SDL and i.MX6SL variants with DDR3.

Also, since only the Novena board currently uses the dynamic
DDR calibration routines, these routines waste space on other
boards using SPL.

Add a KConfig entry to allow boards to selectively include the
DDR calibration routines.

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/Kconfig  | 5 +
 arch/arm/cpu/armv7/mx6/ddr.c| 3 +--
 arch/arm/include/asm/arch-mx6/mx6-ddr.h | 2 +-
 configs/novena_defconfig| 1 +
 4 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/Kconfig b/arch/arm/cpu/armv7/mx6/Kconfig
index 762a581..32536c0 100644
--- a/arch/arm/cpu/armv7/mx6/Kconfig
+++ b/arch/arm/cpu/armv7/mx6/Kconfig
@@ -35,6 +35,11 @@ config MX6ULL
bool
select MX6UL
 
+config MX6_DDRCAL
+   bool "Include dynamic DDR calibration routines"
+   depends on SPL
+   default n
+
 choice
prompt "MX6 board select"
optional
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index b12fb64..0cf391e 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -14,8 +14,7 @@
 #include 
 #include 
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
-
+#if defined(CONFIG_MX6_DDRCAL)
 static void reset_read_data_fifos(void)
 {
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 12454fa..2a8d443 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -458,7 +458,7 @@ void mx6sl_dram_iocfg(unsigned width,
  const struct mx6sl_iomux_ddr_regs *,
  const struct mx6sl_iomux_grp_regs *);
 
-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_MX6_DDRCAL)
 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
diff --git a/configs/novena_defconfig b/configs/novena_defconfig
index 1ffdddc..9d47d5b 100644
--- a/configs/novena_defconfig
+++ b/configs/novena_defconfig
@@ -3,6 +3,7 @@ CONFIG_ARCH_MX6=y
 CONFIG_SPL_GPIO_SUPPORT=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_MX6_DDRCAL=y
 CONFIG_TARGET_KOSAGI_NOVENA=y
 CONFIG_SPL_EXT_SUPPORT=y
 CONFIG_SPL_FAT_SUPPORT=y
-- 
2.7.4

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Re: [U-Boot] [PATCH 3/3] mx6: ddr: add routine to return DDR calibration data

[Eric Nelson]

Hi Marek,

On 10/30/2016 10:30 AM, Marek Vasut wrote:
> On 10/30/2016 06:19 PM, Eric Nelson wrote:
>> Add routine mmdc_read_calibration() to return the output of DDR
>> calibration. This can be used for debugging or to aid in construction
>> of static memory configuration.
>>
>> Signed-off-by: Eric Nelson 
> 
> Do you plan to use it or will this be mostly dead code ?
> 

I plan to use it.

I'm cleaning things up before (re)sending a patch adding the
virtual "mx6memcal" board and wanted to push the supporting
changes in a separate set.

I have one more independent patch (4/3?) to send before
the new board.
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[U-Boot] [PATCH v9 02/21] mtd: Add SPI-NOR core support

[Jagan Teki]

Some of the SPI device drivers at drivers/spi not a real
spi controllers, Unlike normal/generic SPI controllers they
operates only with SPI-NOR flash devices. these were technically
termed as SPI-NOR controllers, Ex: drivers/spi/fsl_qspi.c

The problem with these were resides at drivers/spi is entire
SPI layer becomes SPI-NOR flash oriented which is absolutely
a wrong indication where SPI layer getting effected more with
flash operations - So this SPI-NOR core will resolve this issue
by separating all SPI-NOR flash operations from spi layer and
creats a generic layer called SPI-NOR core which can be used to
interact SPI-NOR to SPI driver interface layer and the SPI-NOR
controller driver. The idea is taken from Linux spi-nor framework.

--
mtd.c
--
mtd-uclass
---
SPI-NOR Core
---
m25p80.czynq_qspi
---
spi-uclass  SPI NOR chip
---
spi drivers
---
SPI NOR chip
---

Signed-off-by: Jagan Teki 
---
 Makefile  |   1 +
 drivers/mtd/spi-nor/Makefile  |   9 +
 drivers/mtd/spi-nor/spi-nor-ids.c | 176 +++
 drivers/mtd/spi-nor/spi-nor.c | 648 ++
 include/linux/err.h   |   5 +
 include/linux/mtd/spi-nor.h   | 207 
 6 files changed, 1046 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/Makefile
 create mode 100644 drivers/mtd/spi-nor/spi-nor-ids.c
 create mode 100644 drivers/mtd/spi-nor/spi-nor.c
 create mode 100644 include/linux/mtd/spi-nor.h

diff --git a/Makefile b/Makefile
index c67cc99..6404b12 100644
--- a/Makefile
+++ b/Makefile
@@ -642,6 +642,7 @@ libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
 libs-y += drivers/mtd/onenand/
 libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
 libs-y += drivers/mtd/spi/
+libs-y += drivers/mtd/spi-nor/
 libs-y += drivers/net/
 libs-y += drivers/net/phy/
 libs-y += drivers/pci/
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
new file mode 100644
index 000..15e43ea
--- /dev/null
+++ b/drivers/mtd/spi-nor/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Jagan Teki 
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+## spi-nor core
+ifdef CONFIG_MTD_SPI_NOR
+obj-y  += spi-nor.o spi-nor-ids.o
+endif
diff --git a/drivers/mtd/spi-nor/spi-nor-ids.c 
b/drivers/mtd/spi-nor/spi-nor-ids.c
new file mode 100644
index 000..bde8513
--- /dev/null
+++ b/drivers/mtd/spi-nor/spi-nor-ids.c
@@ -0,0 +1,176 @@
+/*
+ * SPI NOR IDs.
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+const struct spi_nor_info spi_nor_ids[] = {
+#ifdef CONFIG_SPI_NOR_MACRONIX /* MACRONIX */
+   {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
+   {"mx25l4005",

[U-Boot] [PATCH v9 21/21] dm: zynq: microzed: Enable MTD/SPI-NOR

[Jagan Teki]

- Enable MTD driver model
- Enable cmd/mtd.c
- Enable SPI-NOR
- Enable MTD_ZYNQ_QSPI
- Add mtd1 alias for qspinor node
- Disable SPI_FLASH

Log:

Zynq> mtd
mtd - MTD Sub-system

Usage:
mtd list- show list of MTD devices
mtd info- show current MTD device info
mtd probe devnum- probe the 'devnum' MTD device
mtd erase offset len- erase 'len' bytes from 'offset'
mtd write addr to len   - write 'len' bytes to 'to' from 'addr'
mtd read addr from len  - read 'len' bytes from 'from' to 'addr'
Zynq> mtd list
MTD 1:  spi-nor@e000d000
Zynq>
MTD 1:  spi-nor@e000d000
Zynq> mtd list
MTD 1:  spi-nor@e000d000
Zynq> mtd probe 0
failing to set MTD device 0
Zynq> mtd probe 1
SPI-NOR: detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, 
total 16 MiB
Zynq> mtd info
MTD Device 1: s25fl128s_64k
 Page size: 256 B
 Erase size:64 KiB
 Size:  16 MiB
Zynq> mtd list
MTD 1:  spi-nor@e000d000  (active 1)
Zynq> mtd erase 0xE0 0x10
MTD: 1048576 bytes @ 0xe0 Erased: OK
Zynq> mw.b 0x100 0xaa 0x10
Zynq> mtd write 0x100 0xE0 0x10
device 0 offset 0xe0, size 0x10
MTD: 1048576 bytes @ 0xe0 Written: OK
Zynq> mtd read 0x300 0xE0 0x10
device 0 offset 0xe0, size 0x10
MTD: 1048576 bytes @ 0xe0 Read: OK
Zynq> cmp.b 0x300 0x100 0x10
Total of 1048576 byte(s) were the same

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/zynq-microzed.dts  |  6 ++
 configs/zynq_microzed_defconfig | 14 +-
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts
index cb238cd..8f56f44 100644
--- a/arch/arm/dts/zynq-microzed.dts
+++ b/arch/arm/dts/zynq-microzed.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = 
spi0 = 
+   mtd1 = 
mmc0 = 
};
 
@@ -43,6 +44,11 @@
status = "okay";
 };
 
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
  {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig
index ad0da0b..87bcbbb 100644
--- a/configs/zynq_microzed_defconfig
+++ b/configs/zynq_microzed_defconfig
@@ -11,6 +11,7 @@ CONFIG_SYS_PROMPT="Zynq> "
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_DFU=y
@@ -31,13 +32,16 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_ZYNQ_SDHCI=y
-CONFIG_SPI_FLASH=y
-CONFIG_SPI_FLASH_BAR=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_ZYNQ_GEM=y
 CONFIG_ZYNQ_QSPI=y
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_ZYNQ_QSPI=y
+CONFIG_SPI_NOR_STMICRO=y
+CONFIG_SPI_NOR_SPANSION=y
+CONFIG_SPI_NOR_SST=y
+CONFIG_SPI_NOR_WINBOND=y
+CONFIG_SPI_NOR_MACRONIX=y
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_ULPI_VIEWPORT=y
-- 
2.7.4

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[U-Boot] [PATCH v9 17/21] dm: mtd: Add uclass_driver.flags

[Jagan Teki]

Add flags for mtd-uclass driver.

Signed-off-by: Jagan Teki 
---
 drivers/mtd/mtd-uclass.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index acbd713..5922b70 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -89,5 +89,6 @@ int dm_add_mtd_device(struct udevice *dev)
 UCLASS_DRIVER(mtd) = {
.id = UCLASS_MTD,
.name   = "mtd",
+   .flags  = DM_UC_FLAG_SEQ_ALIAS,
.per_device_auto_alloc_size = sizeof(struct mtd_info),
 };
-- 
2.7.4

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[U-Boot] [PATCH v9 18/21] dm: mtd: Add post_bind

[Jagan Teki]

Add .post_bind on mtd-uclass driver

Signed-off-by: Jagan Teki 
---
 drivers/mtd/mtd-uclass.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index 5922b70..8eb6e8f 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -11,6 +11,8 @@
 #include 
 #include 
 
+#include 
+
 int dm_mtd_read(struct udevice *dev, loff_t from, size_t len, size_t *retlen,
u_char *buf)
 {
@@ -90,5 +92,6 @@ UCLASS_DRIVER(mtd) = {
.id = UCLASS_MTD,
.name   = "mtd",
.flags  = DM_UC_FLAG_SEQ_ALIAS,
+   .post_bind  = dm_scan_fdt_dev,
.per_device_auto_alloc_size = sizeof(struct mtd_info),
 };
-- 
2.7.4

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[U-Boot] [PATCH v9 20/21] arm: dts: zynq: Add zynq-qspinor node

[Jagan Teki]

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/zynq-7000.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index b618a3f..b1aa480 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -206,6 +206,18 @@
#size-cells = <0>;
};
 
+   qspinor: spi-nor@e000d000 {
+   clock-names = "ref_clk", "pclk";
+   clocks = < 10>, < 43>;
+   compatible = "xlnx,zynq-qspinor-1.0";
+   status = "disabled";
+   interrupt-parent = <>;
+   interrupts = <0 19 4>;
+   reg = <0xe000d000 0x1000>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+
gem0: ethernet@e000b000 {
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
-- 
2.7.4

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[U-Boot] [PATCH v9 19/21] cmd: Add mtd command support

[Jagan Teki]

cmd/mtd.c is a generic command to access all low level
MTD devices, like SPI-NOR, Parallel NOR and NAND.

This is implemented based on u-boot driver model, so any
new driver added for using this command must follow dm principles.

Signed-off-by: Jagan Teki 
---
 cmd/Kconfig  |   6 +
 cmd/Makefile |   1 +
 cmd/mtd.c| 285 +++
 drivers/mtd/Makefile |   2 +-
 drivers/mtd/mtd-uclass.c |  17 +++
 include/mtd.h|   9 ++
 6 files changed, 319 insertions(+), 1 deletion(-)
 create mode 100644 cmd/mtd.c

diff --git a/cmd/Kconfig b/cmd/Kconfig
index 86554ea..9386692 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -706,6 +706,12 @@ config CMD_FS_GENERIC
  fs types.
 endmenu
 
+config CMD_MTD
+   bool "Generic command for accessing MTD devices"
+   help
+ Command to support MTD devices accessing.
+ MTD devices like SPI-NOR, Parallel NOR and NAND.
+
 config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
select CRC32
diff --git a/cmd/Makefile b/cmd/Makefile
index 81b98ee..d50a405 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_CMD_MISC) += misc.o
 obj-$(CONFIG_CMD_MMC) += mmc.o
 obj-$(CONFIG_CMD_MMC_SPI) += mmc_spi.o
 obj-$(CONFIG_MP) += mp.o
+obj-$(CONFIG_CMD_MTD) += mtd.o
 obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
 obj-$(CONFIG_CMD_NAND) += nand.o
 obj-$(CONFIG_CMD_NET) += net.o
diff --git a/cmd/mtd.c b/cmd/mtd.c
new file mode 100644
index 000..0dc529d
--- /dev/null
+++ b/cmd/mtd.c
@@ -0,0 +1,285 @@
+/*
+ * Command for accessing MTD device.
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct udevice *mtd_cur_dev;
+
+static int cmd_mtd_set_devnum(unsigned int devnum)
+{
+   struct udevice *dev;
+   int ret;
+
+   ret = uclass_get_device_by_seq(UCLASS_MTD, devnum, );
+   if (ret) {
+   debug("%s: No MTD device %d\n", __func__, devnum);
+   return ret;
+   }
+   mtd_cur_dev = dev;
+
+   return 0;
+}
+
+static int mtd_get_cur_dev(struct udevice **devp)
+{
+   if (!mtd_cur_dev) {
+   puts("No MTD device selected\n");
+   return -ENODEV;
+   }
+   *devp = mtd_cur_dev;
+
+   return 0;
+}
+
+static int do_mtd_write_read(int argc, char * const argv[])
+{
+   struct udevice *dev;
+   struct mtd_info *mtd;
+   loff_t offset, addr, len, maxsize;
+   u_char *buf;
+   char *endp;
+   int idx = 0;
+   int ret;
+
+   if (argc < 3)
+   return -1;
+
+   ret = mtd_get_cur_dev();
+   if (ret)
+   return CMD_RET_FAILURE;
+
+   addr = simple_strtoul(argv[1], , 16);
+   if (*argv[1] == 0 || *endp != 0)
+   return -1;
+
+   mtd = mtd_get_info(dev);
+   if (mtd_arg_off_size(argc - 2, [2], , , ,
+, MTD_DEV_TYPE_NOR, mtd->size))
+   return -1;
+
+   buf = map_physmem(addr, len, MAP_WRBACK);
+   if (!buf) {
+   puts("failed to map physical memory\n");
+   return 1;
+   }
+
+   if (strcmp(argv[0], "write") == 0)
+   ret = dm_mtd_write(dev, offset, len, (size_t *), buf);
+   else if (strcmp(argv[0], "read") == 0)
+   ret = dm_mtd_read(dev, offset, len, (size_t *), buf);
+
+   printf("MTD: %zu bytes @ %#llx %s: ", (size_t)len, offset,
+  (strcmp(argv[0], "read") == 0) ? "Read" : "Written");
+   if (ret)
+   printf("ERROR %d\n", ret);
+   else
+   printf("OK\n");
+
+   unmap_physmem(buf, len);
+
+   return ret == 0 ? 0 : 1;
+}
+
+static int mtd_parse_len_arg(struct mtd_info *mtd, char *arg, loff_t *len)
+{
+   char *ep;
+   char round_up_len; /* indicates if the "+length" form used */
+   ulong len_arg;
+
+   round_up_len = 0;
+   if (*arg == '+') {
+   round_up_len = 1;
+   ++arg;
+   }
+
+   len_arg = simple_strtoul(arg, , 16);
+   if (ep == arg || *ep != '\0')
+   return -1;
+
+   if (round_up_len && mtd->erasesize > 0)
+   *len = ROUND(len_arg, mtd->erasesize);
+   else
+   *len = len_arg;
+
+   return 1;
+}
+
+static int do_mtd_erase(int argc, char * const argv[])
+{
+   struct udevice *dev;
+   struct mtd_info *mtd;
+   struct erase_info instr;
+   loff_t addr, len, maxsize;
+   int idx = 0;
+   int ret;
+
+   if (argc < 3)
+   return -1;
+
+   ret = mtd_get_cur_dev();
+   if (ret)
+   return CMD_RET_FAILURE;
+
+   mtd = mtd_get_info(dev);
+   if (mtd_arg_off(argv[1], , , , ,
+   MTD_DEV_TYPE_NOR, mtd->size))
+   return -1;
+
+   ret = mtd_parse_len_arg(mtd, 

[U-Boot] [PATCH v9 16/21] mtd: spi-nor: Add 4-byte addresswidth support

[Jagan Teki]

Add 4-byte address supports, so-that SPI-NOR chips
has > 16MiB should accessible.

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/m25p80.c  |  1 +
 drivers/mtd/spi-nor/spi-nor.c | 36 
 include/linux/mtd/spi-nor.h   |  6 +-
 3 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c
index 740d3f6..285fae5 100644
--- a/drivers/mtd/spi-nor/m25p80.c
+++ b/drivers/mtd/spi-nor/m25p80.c
@@ -31,6 +31,7 @@ static void m25p_addr2cmd(struct spi_nor *nor, unsigned int 
addr, u8 *cmd)
cmd[1] = addr >> (nor->addr_width * 8 -  8);
cmd[2] = addr >> (nor->addr_width * 8 - 16);
cmd[3] = addr >> (nor->addr_width * 8 - 24);
+   cmd[4] = addr >> (nor->addr_width * 8 - 32);
 }
 
 static int m25p_cmdsz(struct spi_nor *nor)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 12e7cfe..103b68b 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -378,6 +378,36 @@ static int sst_write_bp(struct udevice *dev, loff_t to, 
size_t len,
 }
 #endif
 
+/* Enable/disable 4-byte addressing mode. */
+static int set_4byte(struct spi_nor *nor, const struct spi_nor_info *info,
+int enable)
+{
+   int status;
+   bool need_wren = false;
+   u8 cmd;
+
+   switch (JEDEC_MFR(info)) {
+   case SNOR_MFR_MICRON:
+   /* Some Micron need WREN command; all will accept it */
+   need_wren = true;
+   case SNOR_MFR_MACRONIX:
+   case SNOR_MFR_WINBOND:
+   if (need_wren)
+   write_enable(nor);
+
+   cmd = enable ? SNOR_OP_EN4B : SNOR_OP_EX4B;
+   status = nor->write_reg(nor, cmd, NULL, 0);
+   if (need_wren)
+   write_disable(nor);
+
+   return status;
+   default:
+   /* Spansion style */
+   nor->cmd_buf[0] = enable << 7;
+   return nor->write_reg(nor, SNOR_OP_BRWR, nor->cmd_buf, 1);
+   }
+}
+
 #ifdef CONFIG_SPI_NOR_MACRONIX
 static int macronix_quad_enable(struct spi_nor *nor)
 {
@@ -613,6 +643,12 @@ int spi_nor_scan(struct udevice *dev)
}
 
nor->addr_width = 3;
+   if (mtd->size > SNOR_16MB_BOUN) {
+   nor->addr_width = 4;
+   ret = set_4byte(nor, info, true);
+   if (ret)
+   return ret;
+   }
 
/* Dummy cycles for read */
switch (nor->read_opcode) {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 4e5b3ba..ad573db 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -62,6 +62,10 @@
 #define SNOR_OP_BP 0x02/* Byte program */
 #define SNOR_OP_AAI_WP 0xad/* Auto addr increment word program */
 
+/* Used for Macronix and Winbond flashes. */
+#define SNOR_OP_EN4B   0xb7/* Enter 4-byte mode */
+#define SNOR_OP_EX4B   0xe9/* Exit 4-byte mode */
+
 /* Status Register bits. */
 #define SR_WIP BIT(0)  /* Write in progress */
 #define SR_WEL BIT(1)  /* Write enable latch */
@@ -83,7 +87,7 @@
 /* Flash timeout values */
 #define SNOR_READY_WAIT_PROG   (2 * CONFIG_SYS_HZ)
 #define SNOR_READY_WAIT_ERASE  (5 * CONFIG_SYS_HZ)
-#define SNOR_MAX_CMD_SIZE  4
+#define SNOR_MAX_CMD_SIZE  6
 #define SNOR_16MB_BOUN 0x100
 
 enum snor_option_flags {
-- 
2.7.4

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[U-Boot] [PATCH v9 15/21] mtd: spi-nor: zynq_qspi: Kconfig: Add MTD_ZYNQ

[Jagan Teki]

Add CONFIG_MTD_ZYNQ_QSPI kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 64d5553..4b2a5e8 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -46,6 +46,15 @@ config MTD_SPI_NOR_USE_4K_SECTORS
  Please note that some tools/drivers/filesystems may not work with
  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
 
+config MTD_ZYNQ_QSPI
+   bool "Zynq QSPI NOR controller driver"
+   depends on ARCH_ZYNQ
+   help
+ Enable the Zynq Quad-SPI (QSPI) driver. This driver can be
+ used to access the SPI NOR flash on platforms embedding this
+ Zynq QSPI IP core. This IP is used to connect the flash in
+ 4-bit qspi, 8-bit dual stacked and shared 4-bit dual parallel.
+
 config SPI_NOR_MISC
bool "Miscellaneous SPI NOR flash's support"
help
-- 
2.7.4

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[U-Boot] [PATCH v9 10/21] mtd: spi-nor: Kconfig: Add SPI_NOR_WINBOND entry

[Jagan Teki]

Added CONFIG_SPI_NOR_WINBOND kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index edcc47e..3ad2b16 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -55,4 +55,9 @@ config SPI_NOR_SST
help
  Add support for various SST SPI flash chips (SST25xxx)
 
+config SPI_NOR_WINBOND
+   bool "Winbond SPI NOR flash support"
+   help
+ Add support for various Winbond SPI flash chips (W25xxx)
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 14/21] mtd: spi-nor: Add zynq qspinor driver

[Jagan Teki]

Zynq qspinor controller is works similar way as generic
spi controller with additional features that make this
controller work more specific to flash chips as salve
devices.

Why, zynq qspi written as spi-nor controller driver.

(1) dual flash:
This describes two/dual memories are connected with
a single chip select line from a controller like dual stack
and dual parallel connections see doc/SPI/README.dual-flash
for more details.

Adding this support to spi-nor core looks quite managable and
other generic code might effect and more over this is controller
specific.

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Makefile   |   3 +
 drivers/mtd/spi-nor/zynq_qspinor.c | 641 +
 2 files changed, 644 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/zynq_qspinor.c

diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index d11ccf4..bbaeee0 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -10,3 +10,6 @@ endif
 
 ## spi-nor to spi interface driver
 obj-$(CONFIG_MTD_M25P80)   += m25p80.o
+
+## spi-nor drivers
+obj-$(CONFIG_MTD_ZYNQ_QSPI)+= zynq_qspinor.o
diff --git a/drivers/mtd/spi-nor/zynq_qspinor.c 
b/drivers/mtd/spi-nor/zynq_qspinor.c
new file mode 100644
index 000..c04e87a
--- /dev/null
+++ b/drivers/mtd/spi-nor/zynq_qspinor.c
@@ -0,0 +1,641 @@
+/*
+ * (C) Copyright 2016 Jagan Teki 
+ *
+ * Xilinx Zynq Quad-SPI(QSPI) NOR controller driver
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* zynq qspi register bit masks ZYNQ_QSPI___MASK */
+#define ZYNQ_QSPI_CR_IFMODE_MASK   BIT(31) /* Flash intrface mode*/
+#define ZYNQ_QSPI_CR_MSA_MASK  BIT(15) /* Manual start enb */
+#define ZYNQ_QSPI_CR_MCS_MASK  BIT(14) /* Manual chip select */
+#define ZYNQ_QSPI_CR_PCS_MASK  BIT(10) /* Peri chip select */
+#define ZYNQ_QSPI_CR_FW_MASK   GENMASK(7, 6)   /* FIFO width */
+#define ZYNQ_QSPI_CR_SS_MASK   GENMASK(13, 10) /* Slave Select */
+#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3)   /* Baud rate div */
+#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2)  /* Clock phase */
+#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1)  /* Clock polarity */
+#define ZYNQ_QSPI_CR_MSTREN_MASK   BIT(0)  /* Mode select */
+#define ZYNQ_QSPI_IXR_RXNEMPTY_MASKBIT(4)  /* RX_FIFO_not_empty */
+#define ZYNQ_QSPI_IXR_TXOW_MASKBIT(2)  /* TX_FIFO_not_full */
+#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0)   /* All IXR bits */
+#define ZYNQ_QSPI_ENR_SPI_EN_MASK  BIT(0)  /* SPI Enable */
+#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
+
+/* zynq qspi Transmit Data Register */
+#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C/* Transmit 4-byte inst */
+#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80/* Transmit 1-byte inst */
+#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84/* Transmit 2-byte inst */
+#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88/* Transmit 3-byte inst */
+
+#define ZYNQ_QSPI_XFER_BEGIN   BIT(0)
+#define ZYNQ_QSPI_XFER_END BIT(1)
+#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1   /* Tx FIFO threshold level*/
+#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32  /* Rx FIFO threshold level */
+
+#define ZYNQ_QSPI_CR_BAUD_MAX  8   /* Baud rate divisor max val */
+#define ZYNQ_QSPI_CR_BAUD_SHIFT3   /* Baud rate divisor 
shift */
+#define ZYNQ_QSPI_CR_SS_SHIFT  10  /* Slave select shift */
+#define ZYNQ_QSPI_MAX_CMDSZ4   /* 1 byte opcode,3 byte addr */
+
+#define ZYNQ_QSPI_FIFO_DEPTH   63
+#ifndef CONFIG_SYS_ZYNQ_QSPI_WAIT
+#define CONFIG_SYS_ZYNQ_QSPI_WAIT  CONFIG_SYS_HZ/100   /* 10 ms */
+#endif
+
+/* zynq qspi register set */
+struct zynq_qspinor_regs {
+   u32 cr; /* 0x00 */
+   u32 isr;/* 0x04 */
+   u32 ier;/* 0x08 */
+   u32 idr;/* 0x0C */
+   u32 imr;/* 0x10 */
+   u32 enr;/* 0x14 */
+   u32 dr; /* 0x18 */
+   u32 txd0r;  /* 0x1C */
+   u32 drxr;   /* 0x20 */
+   u32 sicr;   /* 0x24 */
+   u32 txftr;  /* 0x28 */
+   u32 rxftr;  /* 0x2C */
+   u32 gpior;  /* 0x30 */
+   u32 reserved0[19];
+   u32 txd1r;  /* 0x80 */
+   u32 txd2r;  /* 0x84 */
+   u32 txd3r;  /* 0x88 */
+   u32 reserved1[5];
+   u32 lqspicfg;   /* 0xA0 */
+   u32 lqspists;   /* 0xA4 */
+};
+
+/* zynq qspi platform data */
+struct zynq_qspinor_platdata {
+   struct zynq_qspinor_regs *regs;
+   u32 frequency;  /* input frequency */
+   u32 speed_hz;
+};
+
+/* zynq qspi priv */
+struct zynq_qspinor_priv {
+   struct zynq_qspinor_regs *regs;
+   struct spi_nor spi_nor;
+   u8 cs;
+   u8 mode;
+   

[U-Boot] [PATCH v9 13/21] mtd: spi-nor: Kconfig: Add MTD_M25P80 entry

[Jagan Teki]

Add CONFIG_MTD_M25P80 kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 17 +
 1 file changed, 17 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 3ad2b16..64d5553 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -15,6 +15,23 @@ menuconfig MTD_SPI_NOR
 
 if MTD_SPI_NOR
 
+config MTD_M25P80
+   tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
+   depends on DM_SPI
+   help
+ This enables access to most modern SPI flash chips, used for
+ program and data storage.   Series supported include Atmel AT26DF,
+ Spansion S25SL, SST 25VF, ST M25P, and Winbond W25X.  Other chips
+ are supported as well.  See the driver source for the current list,
+ or to add other chips.
+
+ Note that the original DataFlash chips (AT45 series, not AT26DF),
+ need an entirely different driver.
+
+ Set up your spi devices with the right board-specific platform data,
+ if you want to specify device partitioning or to use a device which
+ doesn't support the JEDEC ID instruction.
+
 config MTD_SPI_NOR_USE_4K_SECTORS
bool "Use small 4096 B erase sectors"
default y
-- 
2.7.4

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[U-Boot] [PATCH v9 12/21] mtd: spi-nor: Add m25p80 driver

[Jagan Teki]

This is MTD SPI-NOR driver for ST M25Pxx (and similar)
serial flash chips which is written as MTD_UCLASS.

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Makefile |   3 +
 drivers/mtd/spi-nor/m25p80.c | 217 +++
 2 files changed, 220 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/m25p80.c

diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
index 15e43ea..d11ccf4 100644
--- a/drivers/mtd/spi-nor/Makefile
+++ b/drivers/mtd/spi-nor/Makefile
@@ -7,3 +7,6 @@
 ifdef CONFIG_MTD_SPI_NOR
 obj-y  += spi-nor.o spi-nor-ids.o
 endif
+
+## spi-nor to spi interface driver
+obj-$(CONFIG_MTD_M25P80)   += m25p80.o
diff --git a/drivers/mtd/spi-nor/m25p80.c b/drivers/mtd/spi-nor/m25p80.c
new file mode 100644
index 000..740d3f6
--- /dev/null
+++ b/drivers/mtd/spi-nor/m25p80.c
@@ -0,0 +1,217 @@
+/*
+ * MTD SPI-NOR driver for ST M25Pxx (and similar) serial flash chips
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+
+#define MAX_CMD_SIZE   6
+struct m25p {
+   struct spi_slave*spi;
+   struct spi_nor  spi_nor;
+   u8  command[MAX_CMD_SIZE];
+};
+
+static void m25p_addr2cmd(struct spi_nor *nor, unsigned int addr, u8 *cmd)
+{
+   /* opcode is in cmd[0] */
+   cmd[1] = addr >> (nor->addr_width * 8 -  8);
+   cmd[2] = addr >> (nor->addr_width * 8 - 16);
+   cmd[3] = addr >> (nor->addr_width * 8 - 24);
+}
+
+static int m25p_cmdsz(struct spi_nor *nor)
+{
+   return 1 + nor->addr_width;
+}
+
+static int m25p80_read_reg(struct spi_nor *nor, u8 opcode, u8 *val, int len)
+{
+   struct m25p *flash = nor->priv;
+   struct spi_slave *spi = flash->spi;
+   int ret;
+
+   ret = spi_write_then_read(spi, , 1, NULL, val, len);
+   if (ret < 0) {
+   debug("m25p80: error %d reading register %x\n", ret, opcode);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int m25p80_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
+{
+   struct m25p *flash = nor->priv;
+   struct spi_slave *spi = flash->spi;
+   int ret;
+
+   ret = spi_write_then_read(spi, , 1, buf, NULL, len);
+   if (ret < 0) {
+   debug("m25p80: error %d writing register %x\n", ret, opcode);
+   return ret;
+   }
+
+   return ret;
+}
+
+/*
+ * TODO: remove the weak after all the other spi_flash_copy_mmap
+ * implementations removed from drivers
+ */
+void __weak flash_copy_mmap(void *data, void *offset, size_t len)
+{
+#ifdef CONFIG_DMA
+   if (!dma_memcpy(data, offset, len))
+   return;
+#endif
+   memcpy(data, offset, len);
+}
+
+static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len,
+  u_char *buf)
+{
+   struct m25p *flash = nor->priv;
+   struct spi_slave *spi = flash->spi;
+   unsigned int dummy = nor->read_dummy;
+   int ret;
+
+   if (nor->memory_map) {
+   spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP);
+   flash_copy_mmap(buf, nor->memory_map + from, len);
+   spi_xfer(spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
+   spi_release_bus(spi);
+   return 0;
+   }
+
+   /* convert the dummy cycles to the number of bytes */
+   dummy /= 8;
+
+   flash->command[0] = nor->read_opcode;
+   m25p_addr2cmd(nor, from, flash->command);
+
+   ret = spi_write_then_read(spi, flash->command, m25p_cmdsz(nor) + dummy,
+ NULL, buf, len);
+   if (ret < 0) {
+   debug("m25p80: error %d reading %x\n", ret, flash->command[0]);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int m25p80_write(struct spi_nor *nor, loff_t to, size_t len,
+   const u_char *buf)
+{
+   struct m25p *flash = nor->priv;
+   struct spi_slave *spi = flash->spi;
+   int cmd_sz = m25p_cmdsz(nor);
+   int ret;
+
+   if ((nor->program_opcode == SNOR_OP_AAI_WP) && (buf != NULL))
+   cmd_sz = 1;
+
+   flash->command[0] = nor->program_opcode;
+   if (buf == NULL)
+   flash->command[0] = nor->erase_opcode;
+   m25p_addr2cmd(nor, to, flash->command);
+
+   ret = spi_write_then_read(spi, flash->command, cmd_sz, buf, NULL, len);
+   if (ret < 0) {
+   debug("m25p80: error %d writing %x\n", ret, flash->command[0]);
+   return ret;
+   }
+
+   return ret;
+}
+
+static int m25p_probe(struct udevice *dev)
+{
+   struct mtd_info *mtd = mtd_get_info(dev);
+   struct spi_slave *spi = dev_get_parent_priv(dev);
+   struct m25p *flash = dev_get_priv(dev);
+   struct spi_nor *nor;
+   int ret;
+
+   nor = >spi_nor;
+
+   flash->spi = spi;

[U-Boot] [PATCH v9 11/21] spi: Add spi_write_then_read

[Jagan Teki]

Add support for SPI synchronous write followed by read,
this is common interface call from spi-nor to spi drivers.

Signed-off-by: Jagan Teki 
---
 drivers/spi/spi-uclass.c | 24 
 include/spi.h| 20 
 2 files changed, 44 insertions(+)

diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index d9c49e4..bb33fd8 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -108,6 +108,30 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
return dm_spi_xfer(slave->dev, bitlen, dout, din, flags);
 }
 
+int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
+   size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+   size_t n_buf)
+{
+   unsigned long flags = SPI_XFER_BEGIN;
+   int ret;
+
+   if (n_buf == 0)
+   flags |= SPI_XFER_END;
+
+   ret = spi_xfer(slave, n_opcode * 8, opcode, NULL, flags);
+   if (ret) {
+   debug("spi: failed to send command (%zu bytes): %d\n",
+ n_opcode, ret);
+   } else if (n_buf != 0) {
+   ret = spi_xfer(slave, n_buf * 8, txbuf, rxbuf, SPI_XFER_END);
+   if (ret)
+   debug("spi: failed to transfer %zu bytes of data: %d\n",
+ n_buf, ret);
+   }
+
+   return ret;
+}
+
 static int spi_child_post_bind(struct udevice *dev)
 {
struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
diff --git a/include/spi.h b/include/spi.h
index 4c17983..336ac99 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -258,6 +258,26 @@ int spi_set_wordlen(struct spi_slave *slave, unsigned int 
wordlen);
 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags);
 
+/**
+ * spi_write_then_read - SPI synchronous write followed by read
+ *
+ * This performs a half duplex transaction in which the first transaction
+ * is to send the opcode and if the length of buf is non-zero then it start
+ * the second transaction as tx or rx based on the need from respective slave.
+ *
+ * @slave: slave device with which opcode/data will be exchanged
+ * @opcode:opcode used for specific transfer
+ * @n_opcode:  size of opcode, in bytes
+ * @txbuf: buffer into which data to be written
+ * @rxbuf: buffer into which data will be read
+ * @n_buf: size of buf (whether it's [tx|rx]buf), in bytes
+ *
+ * Returns: 0 on success, not 0 on failure
+ */
+int spi_write_then_read(struct spi_slave *slave, const u8 *opcode,
+   size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+   size_t n_buf);
+
 /* Copy memory mapped data */
 void spi_flash_copy_mmap(void *data, void *offset, size_t len);
 
-- 
2.7.4

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[U-Boot] [PATCH v9 09/21] mtd: spi-nor: Kconfig: Add SPI_NOR_SST entry

[Jagan Teki]

Added CONFIG_SPI_NOR_SST kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 8ed4891..edcc47e 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -50,4 +50,9 @@ config SPI_NOR_STMICRO
help
  Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx)
 
+config SPI_NOR_SST
+   bool "SST SPI NOR flash support"
+   help
+ Add support for various SST SPI flash chips (SST25xxx)
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 08/21] mtd: spi-nor: Kconfig: Add SPI_NOR_STMICRO entry

[Jagan Teki]

Added CONFIG_SPI_NOR_STMICRO kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index d4303db..8ed4891 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -45,4 +45,9 @@ config SPI_NOR_SPANSION
help
  Add support for various Spansion SPI flash chips (S25FLxxx)
 
+config SPI_NOR_STMICRO
+   bool "STMicro SPI NOR flash support"
+   help
+ Add support for various STMicro SPI flash chips (M25Pxxx and N25Qxxx)
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 07/21] mtd: spi-nor: Kconfig: Add SPI_NOR_SPANSION entry

[Jagan Teki]

Added CONFIG_SPI_NOR_SPANSION kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index c0ca14b..d4303db 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -40,4 +40,9 @@ config SPI_NOR_MACRONIX
help
  Add support for various Macronix SPI flash chips (MX25Lxxx)
 
+config SPI_NOR_SPANSION
+   bool "Spansion SPI NOR flash support"
+   help
+ Add support for various Spansion SPI flash chips (S25FLxxx)
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 06/21] mtd: spi-nor: Kconfig: Add SPI_NOR_MACRONIX entry

[Jagan Teki]

Added CONFIG_SPI_NOR_MACRONIX kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 348709b..c0ca14b 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -35,4 +35,9 @@ config SPI_NOR_MISC
  Add SPI-NOR support for various flash chips like Atmel, EON,
  GigaDevice, and ISSI.
 
+config SPI_NOR_MACRONIX
+   bool "Macronix SPI NOR flash support"
+   help
+ Add support for various Macronix SPI flash chips (MX25Lxxx)
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 01/21] dm: mtd: Add dm mtd core ops

[Jagan Teki]

- Add generic dm_mtd operations
- Add mtd_read|erase|write_dm
- Add add_mtd_device_dm

The respetive MTD_UCLASS drivers must install the hooks to these
dm_mtd_ops and other core ops are act as a interface b/w drivers
vs command code.

Signed-off-by: Jagan Teki 
---
 drivers/mtd/mtd-uclass.c | 72 
 include/mtd.h| 54 
 2 files changed, 126 insertions(+)

diff --git a/drivers/mtd/mtd-uclass.c b/drivers/mtd/mtd-uclass.c
index 7b7c48e..acbd713 100644
--- a/drivers/mtd/mtd-uclass.c
+++ b/drivers/mtd/mtd-uclass.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (C) 2016 Jagan Teki 
  * Copyright (C) 2015 Thomas Chou 
  *
  * SPDX-License-Identifier:GPL-2.0+
@@ -8,6 +9,77 @@
 #include 
 #include 
 #include 
+#include 
+
+int dm_mtd_read(struct udevice *dev, loff_t from, size_t len, size_t *retlen,
+   u_char *buf)
+{
+   struct mtd_info *mtd = mtd_get_info(dev);
+
+   *retlen = 0;
+   if (from < 0 || from > mtd->size || len > mtd->size - from)
+   return -EINVAL;
+   if (!len)
+   return 0;
+
+   return mtd_get_ops(dev)->_read(dev, from, len, retlen, buf);
+}
+
+int dm_mtd_erase(struct udevice *dev, struct erase_info *instr)
+{
+   struct mtd_info *mtd = mtd_get_info(dev);
+
+   if (instr->addr > mtd->size || instr->len > mtd->size - instr->addr)
+   return -EINVAL;
+   if (!(mtd->flags & MTD_WRITEABLE))
+   return -EROFS;
+   instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+   if (!instr->len) {
+   instr->state = MTD_ERASE_DONE;
+   return 0;
+   }
+
+   return mtd_get_ops(dev)->_erase(dev, instr);
+}
+
+int dm_mtd_write(struct udevice *dev, loff_t to, size_t len, size_t *retlen,
+const u_char *buf)
+{
+   struct mtd_info *mtd = mtd_get_info(dev);
+
+   *retlen = 0;
+   if (to < 0 || to > mtd->size || len > mtd->size - to)
+   return -EINVAL;
+   if (!mtd_get_ops(dev)->_write || !(mtd->flags & MTD_WRITEABLE))
+   return -EROFS;
+   if (!len)
+   return 0;
+
+   return mtd_get_ops(dev)->_write(dev, to, len, retlen, buf);
+}
+
+int dm_add_mtd_device(struct udevice *dev)
+{
+   struct mtd_info *mtd = mtd_get_info(dev);
+
+   BUG_ON(mtd->writesize == 0);
+   mtd->usecount = 0;
+
+   if (is_power_of_2(mtd->erasesize))
+   mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+   else
+   mtd->erasesize_shift = 0;
+
+   if (is_power_of_2(mtd->writesize))
+   mtd->writesize_shift = ffs(mtd->writesize) - 1;
+   else
+   mtd->writesize_shift = 0;
+
+   mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+   mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+
+   return 0;
+}
 
 /*
  * Implement a MTD uclass which should include most flash drivers.
diff --git a/include/mtd.h b/include/mtd.h
index 3f8c293..93b5eaf 100644
--- a/include/mtd.h
+++ b/include/mtd.h
@@ -20,4 +20,58 @@ static inline struct mtd_info *mtd_get_info(struct udevice 
*dev)
return dev_get_uclass_priv(dev);
 }
 
+struct dm_mtd_ops {
+   int (*_erase)(struct udevice *dev, struct erase_info *instr);
+   int (*_read)(struct udevice *dev, loff_t from, size_t len,
+size_t *retlen, u_char *buf);
+   int (*_write)(struct udevice *dev, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf);
+};
+
+/* Access the serial operations for a device */
+#define mtd_get_ops(dev) ((struct dm_mtd_ops *)(dev)->driver->ops)
+
+/**
+ * dm_mtd_read() - Read data from MTD device
+ *
+ * @dev:   MTD device
+ * @from:  Offset into device in bytes to read from
+ * @len:   Length of bytes to read
+ * @retlen:Length of return bytes read to
+ * @buf:   Buffer to put the data that is read
+ * @return 0 if OK, -ve on error
+ */
+int dm_mtd_read(struct udevice *dev, loff_t from, size_t len, size_t *retlen,
+   u_char *buf);
+
+/**
+ * dm_mtd_write() - Write data to MTD device
+ *
+ * @dev:   MTD device
+ * @to:Offset into device in bytes to write to
+ * @len:   Length of bytes to write
+ * @retlen:Length of return bytes to write to
+ * @buf:   Buffer containing bytes to write
+ * @return 0 if OK, -ve on error
+ */
+int dm_mtd_write(struct udevice *dev, loff_t to, size_t len, size_t *retlen,
+const u_char *buf);
+
+/**
+ * dm_mtd_erase() - Erase blocks of the MTD device
+ *
+ * @dev:   MTD device
+ * @instr: Erase info details of MTD device
+ * @return 0 if OK, -ve on error
+ */
+int dm_mtd_erase(struct udevice *dev, struct erase_info *instr);
+
+/**
+ * dm_add_mtd_device() - Add MTD device
+ *
+ * @dev:   MTD device
+ * @return 0 if OK, -ve on error
+ */
+int dm_add_mtd_device(struct udevice *dev);
+
 

[U-Boot] [PATCH v9 02/21] mtd: Add SPI-NOR core support

[Jagan Teki]

Some of the SPI device drivers at drivers/spi not a real
spi controllers, Unlike normal/generic SPI controllers they
operates only with SPI-NOR flash devices. these were technically
termed as SPI-NOR controllers, Ex: drivers/spi/fsl_qspi.c

The problem with these were resides at drivers/spi is entire
SPI layer becomes SPI-NOR flash oriented which is absolutely
a wrong indication where SPI layer getting effected more with
flash operations - So this SPI-NOR core will resolve this issue
by separating all SPI-NOR flash operations from spi layer and
creats a generic layer called SPI-NOR core which can be used to
interact SPI-NOR to SPI driver interface layer and the SPI-NOR
controller driver. The idea is taken from Linux spi-nor framework.

--
cmd_sf.c
--
mtd-uclass
---
SPI-NOR Core
---
m25p80.czynq_qspi
---
spi-uclass  SPI NOR chip
---
spi drivers
---
SPI NOR chip
---

Signed-off-by: Jagan Teki 
---
 Makefile  |   1 +
 drivers/mtd/spi-nor/Makefile  |   9 +
 drivers/mtd/spi-nor/spi-nor-ids.c | 176 +++
 drivers/mtd/spi-nor/spi-nor.c | 648 ++
 include/linux/err.h   |   5 +
 include/linux/mtd/spi-nor.h   | 207 
 6 files changed, 1046 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/Makefile
 create mode 100644 drivers/mtd/spi-nor/spi-nor-ids.c
 create mode 100644 drivers/mtd/spi-nor/spi-nor.c
 create mode 100644 include/linux/mtd/spi-nor.h

diff --git a/Makefile b/Makefile
index c67cc99..6404b12 100644
--- a/Makefile
+++ b/Makefile
@@ -642,6 +642,7 @@ libs-$(CONFIG_CMD_NAND) += drivers/mtd/nand/
 libs-y += drivers/mtd/onenand/
 libs-$(CONFIG_CMD_UBI) += drivers/mtd/ubi/
 libs-y += drivers/mtd/spi/
+libs-y += drivers/mtd/spi-nor/
 libs-y += drivers/net/
 libs-y += drivers/net/phy/
 libs-y += drivers/pci/
diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
new file mode 100644
index 000..15e43ea
--- /dev/null
+++ b/drivers/mtd/spi-nor/Makefile
@@ -0,0 +1,9 @@
+#
+# Copyright (C) 2016 Jagan Teki 
+#
+# SPDX-License-Identifier: GPL-2.0+
+
+## spi-nor core
+ifdef CONFIG_MTD_SPI_NOR
+obj-y  += spi-nor.o spi-nor-ids.o
+endif
diff --git a/drivers/mtd/spi-nor/spi-nor-ids.c 
b/drivers/mtd/spi-nor/spi-nor-ids.c
new file mode 100644
index 000..bde8513
--- /dev/null
+++ b/drivers/mtd/spi-nor/spi-nor-ids.c
@@ -0,0 +1,176 @@
+/*
+ * SPI NOR IDs.
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+const struct spi_nor_info spi_nor_ids[] = {
+#ifdef CONFIG_SPI_NOR_MACRONIX /* MACRONIX */
+   {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
+   {"mx25l4005", 

[U-Boot] [PATCH v9 05/21] mtd: spi-nor: Kconfig: Add SPI_NOR_MISC entry

[Jagan Teki]

Added CONFIG_SPI_NOR_MISC kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 40cd5ba..348709b 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -29,4 +29,10 @@ config MTD_SPI_NOR_USE_4K_SECTORS
  Please note that some tools/drivers/filesystems may not work with
  4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
 
+config SPI_NOR_MISC
+   bool "Miscellaneous SPI NOR flash's support"
+   help
+ Add SPI-NOR support for various flash chips like Atmel, EON,
+ GigaDevice, and ISSI.
+
 endif # MTD_SPI_NOR
-- 
2.7.4

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[U-Boot] [PATCH v9 00/21] dm: Generic MTD Subsystem/SPI-NOR

[Jagan Teki]

The previous series [1] [2] are added SPI-NOR on top of
mtd/spi where it bypassing DM_SPI_FLASH and use the existing
mtd core (which is non-dm), I feel this is moving in a reverse
direction where adding new feature with the help of non-dm mtd
core support and also few of the spi drivers are not fully dm-driven.

Previous design series[3]: keep the mtd/spi as it is and start adding
spi-nor features separately. The idea here is to add the dm features
to MTD first and then add UCLASS_MTD spi-nor drivers so-that the commands
are interfacing to spi-nor through dm-driven MTD core to spi-nor.

This series adding a new command 'mtd.c' which is common for all MTD devices
SPI-NOR, SPI-NOR(master) and Parallel NOR with dm-driven. 

SPI-NOR and Parallel NOR:



  mtd.c

mtd-uclass

   SPI-NOR CoreCFI FLASH

m25p80.czynq_qspi
---
spi-uclass  SPI NOR chip
---
spi drivers
---
SPI NOR chip
---

drivers/mtd/spi-nor/

- Add dm mtd operations
- spi-nor.c:   Add basic SPI-NOR core like erase/read/write ops and lock's will 
add later
- m25p80.c:spi-nor to spi divers interface layer drivers/spi-nor
- zynq_qspi.c: zynq qspi spi-nor controller driver.

Current Status:
--
- SPI-NOR Controller design flow working, see Log

TODO:

- SPI-NOR with SPI bus
- Parallel NOR.

Log:

Zynq> mtd
mtd - MTD Sub-system

Usage:
mtd list- show list of MTD devices
mtd info- show current MTD device info
mtd probe devnum- probe the 'devnum' MTD device
mtd erase offset len- erase 'len' bytes from 'offset'
mtd write addr to len   - write 'len' bytes to 'to' from 'addr'
mtd read addr from len  - read 'len' bytes from 'from' to 'addr'
Zynq> mtd list
MTD 1:  spi-nor@e000d000
Zynq>
MTD 1:  spi-nor@e000d000
Zynq> mtd list
MTD 1:  spi-nor@e000d000
Zynq> mtd probe 0
failing to set MTD device 0
Zynq> mtd probe 1
SPI-NOR: detected s25fl128s_64k with page size 256 Bytes, erase size 64 KiB, 
total 16 MiB
Zynq> mtd info  
MTD Device 1: s25fl128s_64k
 Page size: 256 B
 Erase size:64 KiB
 Size:  16 MiB
Zynq> mtd list
MTD 1:  spi-nor@e000d000  (active 1)
Zynq> mtd erase 0xE0 0x10
MTD: 1048576 bytes @ 0xe0 Erased: OK
Zynq> mw.b 0x100 0xaa 0x10
Zynq> mtd write 0x100 0xE0 0x10
device 0 offset 0xe0, size 0x10
MTD: 1048576 bytes @ 0xe0 Written: OK
Zynq> mtd read 0x300 0xE0 0x10
device 0 offset 0xe0, size 0x10
MTD: 1048576 bytes @ 0xe0 Read: OK
Zynq> cmp.b 0x300 0x100 0x10
Total of 1048576 byte(s) were the same

Testing:
---
$ git clone git://git.denx.de/u-boot-spi.git
$ cd u-boot-spi
$ git checkout -b mtd origin/mtd-working

[1] http://lists.denx.de/pipermail/u-boot/2016-March/249286.html
[2] http://lists.denx.de/pipermail/u-boot/2016-February/245418.html
[3] [PATCH RFC v8 00/16]  SPI-NOR/MTD addition

Jagan Teki (21):
  dm: mtd: Add dm mtd core ops
  mtd: Add SPI-NOR core support
  mtd: spi-nor: Kconfig: Add MTD_SPI_NOR entry
  mtd: spi-nor: Kconfig: Add MTD_SPI_NOR_USE_4K_SECTORS
  mtd: spi-nor: Kconfig: Add SPI_NOR_MISC entry
  mtd: spi-nor: Kconfig: Add SPI_NOR_MACRONIX entry
  mtd: spi-nor: Kconfig: Add SPI_NOR_SPANSION entry
  mtd: spi-nor: Kconfig: Add SPI_NOR_STMICRO entry
  mtd: spi-nor: Kconfig: Add SPI_NOR_SST entry
  mtd: spi-nor: Kconfig: Add SPI_NOR_WINBOND entry
  spi: Add spi_write_then_read
  mtd: spi-nor: Add m25p80 driver
  mtd: spi-nor: Kconfig: Add MTD_M25P80 entry
  mtd: spi-nor: Add zynq qspinor driver
  mtd: spi-nor: zynq_qspi: Kconfig: Add MTD_ZYNQ
  mtd: spi-nor: Add 4-byte addresswidth support
  dm: mtd: Add uclass_driver.flags
  dm: mtd: Add post_bind
  cmd: Add mtd command support
  arm: dts: zynq: Add zynq-qspinor node
  dm: zynq: microzed: Enable MTD/SPI-NOR

 Makefile   |   1 +
 arch/arm/dts/zynq-7000.dtsi|  12 +
 arch/arm/dts/zynq-microzed.dts |   6 +
 cmd/Kconfig|   6 +
 cmd/Makefile   |   1 +
 cmd/mtd.c  | 285 
 configs/zynq_microzed_defconfig|  14 +-
 drivers/mtd/Kconfig|   2 +
 drivers/mtd/Makefile   |   2 +-
 drivers/mtd/mtd-uclass.c   |  93 +
 drivers/mtd/spi-nor/Kconfig|  89 +
 drivers/mtd/spi-nor/Makefile   |  15 +
 drivers/mtd/spi-nor/m25p80.c   | 218 
 drivers/mtd/spi-nor/spi-nor-ids.c  | 176 ++
 drivers/mtd/spi-nor/spi-nor.c  | 684 +
 drivers/mtd/spi-nor/zynq_qspinor.c | 641 ++
 drivers/spi/spi-uclass.c   |  24 

[U-Boot] [PATCH v9 03/21] mtd: spi-nor: Kconfig: Add MTD_SPI_NOR entry

[Jagan Teki]

Added CONFIG_MTD_SPI_NOR kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/Kconfig |  2 ++
 drivers/mtd/spi-nor/Kconfig | 14 ++
 2 files changed, 16 insertions(+)
 create mode 100644 drivers/mtd/spi-nor/Kconfig

diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 3a9705c..3dc4221 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -41,4 +41,6 @@ source "drivers/mtd/nand/Kconfig"
 
 source "drivers/mtd/spi/Kconfig"
 
+source "drivers/mtd/spi-nor/Kconfig"
+
 source "drivers/mtd/ubi/Kconfig"
diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
new file mode 100644
index 000..130b0a4
--- /dev/null
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -0,0 +1,14 @@
+menuconfig MTD_SPI_NOR
+   tristate "SPI-NOR device support"
+   depends on MTD
+   help
+ This is the core SPI NOR framework which can be used to interact 
SPI-NOR
+ to SPI driver interface layer and the SPI-NOR controller driver.
+
+ Unlike normal/generic spi controllers, they are few controllers which 
are
+ exclusively used to connect SPI-NOR devices, called SPI-NOR 
controllers.
+ So technically these controllers shouldn't reside at drivers/spi as 
these
+ may effect the generic SPI bus functionalities, so this SPI-NOR core 
acts
+ as a common core framework between the generic SPI controller drivers 
vs
+ SPI-NOR controller drivers for SPI-NOR device access. Note that from 
SPI-NOR
+ core to SPI drivers there should be an interface layer.
-- 
2.7.4

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[U-Boot] [PATCH v9 04/21] mtd: spi-nor: Kconfig: Add MTD_SPI_NOR_USE_4K_SECTORS

[Jagan Teki]

Added CONFIG_MTD_SPI_NOR_USE_4K_SECTORS kconfig entry

Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi-nor/Kconfig | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/drivers/mtd/spi-nor/Kconfig b/drivers/mtd/spi-nor/Kconfig
index 130b0a4..40cd5ba 100644
--- a/drivers/mtd/spi-nor/Kconfig
+++ b/drivers/mtd/spi-nor/Kconfig
@@ -12,3 +12,21 @@ menuconfig MTD_SPI_NOR
  as a common core framework between the generic SPI controller drivers 
vs
  SPI-NOR controller drivers for SPI-NOR device access. Note that from 
SPI-NOR
  core to SPI drivers there should be an interface layer.
+
+if MTD_SPI_NOR
+
+config MTD_SPI_NOR_USE_4K_SECTORS
+   bool "Use small 4096 B erase sectors"
+   default y
+   help
+ Many flash memories support erasing small (4096 B) sectors. Depending
+ on the usage this feature may provide performance gain in comparison
+ to erasing whole blocks (32/64 KiB).
+ Changing a small part of the flash's contents is usually faster with
+ small sectors. On the other hand erasing should be faster when using
+ 64 KiB block instead of 16 × 4 KiB sectors.
+
+ Please note that some tools/drivers/filesystems may not work with
+ 4096 B erase size (e.g. UBIFS requires 15 KiB as a minimum).
+
+endif # MTD_SPI_NOR
-- 
2.7.4

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Re: [U-Boot] Please pull u-boot-sunxi sun9i-a80-spl

[Tom Rini]

On Sun, Oct 30, 2016 at 12:53:25PM +0100, Hans de Goede wrote:

> Hi Tom,
> 
> Here is another sunxi pull-req, this one is to be applied on top of the
> bug-fix one I send out a few seconds ago. I'm sending this one as
> a separate pull-req since it contains non-bugfix changes which were
> first submitted outside the merge window.
> 
> The entire set of patches in this pull-req enables DRAM controller init
> and SPL for the Allwinner A80 SoC. These changes are isolated to the A80
> SoC and should not impact other (sunxi) SoCs. Without SPL u-boot was never
> really usable on the A80 SoC, so in a sense this is a bug-fix pull-req,
> as it makes u-boot fully functional on the A80 for the first time.
> 
> Anyways I've deliberately put this in a separate pull-req to make it
> easy for you to nack this one as being too late in the cycle, and I'm
> fine with keeping these in my tree until the next merge-window opens.
> 
> I assume it is clear that my preference (and judgement call on this
> being safe) is to get these into v2016.11, otherwise I would not have
> send the pull-req.
> 
> The following changes since commit fed329aebe3aaac0928c73547ac6316af2adf0cd:
> 
>   tools: add mksunxiboot to tools-all target (2016-10-30 11:38:04 +0100)
> 
> are available in the git repository at:
> 
>   http://git.denx.de/u-boot-sunxi.git sun9i-a80-spl
> 
> for you to fetch changes up to fda9d5d327302e2e5a45ade25e88edc0002336ec:
> 
>   sunxi: Add support for Cubieboard4 (2016-10-30 11:38:05 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] Please pull u-boot-sunxi master

[Tom Rini]

On Sun, Oct 30, 2016 at 12:52:06PM +0100, Hans de Goede wrote:

> Hi Tom,
> 
> Here is a pull request with some small sunxi cleanups / fixes
> for v2016.11.
> 
> Note I expect you to merge this after Marek's usb pull-req. If you don't
> nothing will break, but you will get a whole bunch of new compiler warnings
> when building the pine64_plus defconfig.
> 
> The following changes since commit 4d6afd69babafbf6580cb04dacd9479df03a5de0:
> 
>   configs/chromebox_panther_defconfig: Re-enable CONFIG_DM_PCI (2016-10-29 
> 09:00:01 -0400)
> 
> are available in the git repository at:
> 
>   http://git.denx.de/u-boot-sunxi.git master
> 
> for you to fetch changes up to fed329aebe3aaac0928c73547ac6316af2adf0cd:
> 
>   tools: add mksunxiboot to tools-all target (2016-10-30 11:38:04 +0100)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH 1/3] mx6: ddr: allow 32 cycles for DQS gating calibration

[Marek Vasut]

On 10/30/2016 06:19 PM, Eric Nelson wrote:
> The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
> cycle) for the first PHY.
> 
> Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
> output value isn't polluted with calibration artifacts.
> 
> Signed-off-by: Eric Nelson 

Reviewed-by: Marek Vasut 

> ---
>  arch/arm/cpu/armv7/mx6/ddr.c | 7 +++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index 7beb7ea..b15f376 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -347,6 +347,8 @@ int mmdc_do_dqs_calibration(void)
>* 16 before comparing read data.
>*/
>   setbits_le32(>mpdgctrl0, 1 << 30);
> + if (sysinfo->dsize == 2)
> + setbits_le32(>mpdgctrl0, 1 << 30);
>  
>   /* Set bit 28 to start automatic read DQS gating calibration */
>   setbits_le32(>mpdgctrl0, 5 << 28);
> @@ -365,6 +367,11 @@ int mmdc_do_dqs_calibration(void)
>   if ((bus_size == 0x2) && (readl(>mpdgctrl0) & 0x1000))
>   errors |= 2;
>  
> + /* now disable mpdgctrl0[DG_CMP_CYC] */
> + clrbits_le32(>mpdgctrl0, 1 << 30);
> + if (sysinfo->dsize == 2)
> + clrbits_le32(>mpdgctrl0, 1 << 30);
> +
>   /*
>* DQS gating absolute offset should be modified from
>* reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
> 


-- 
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Re: [U-Boot] [PATCH 2/3] mx6: ddr: pass mx6_ddr_sysinfo to calibration routines

[Marek Vasut]

On 10/30/2016 06:19 PM, Eric Nelson wrote:
> The DDR calibration routines have scattered support for bus
> widths other than 64-bits:
> 
> -- The mmdc_do_write_level_calibration() routine assumes the
> presence of PHY1, and
> -- The mmdc_do_dqs_calibration() routine tries to determine
> whether one or two DDR PHYs are active by reading MDCTL.
> 
> Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
> for use in calling mx6_dram_cfg(), and the bus width is available in the
> "dsize" field, use this structure to inform the calibration routines which
> PHYs are active.
> 
> This allows the use of the DDR calibration routines on CPU variants
> like i.MX6SL that only have a single MMDC port.
> 
> Signed-off-by: Eric Nelson 

Reviewed-by: Marek Vasut 

-- 
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Re: [U-Boot] [PATCH 3/3] mx6: ddr: add routine to return DDR calibration data

[Marek Vasut]

On 10/30/2016 06:19 PM, Eric Nelson wrote:
> Add routine mmdc_read_calibration() to return the output of DDR
> calibration. This can be used for debugging or to aid in construction
> of static memory configuration.
> 
> Signed-off-by: Eric Nelson 

Do you plan to use it or will this be mostly dead code ?

> ---
>  arch/arm/cpu/armv7/mx6/ddr.c| 23 +++
>  arch/arm/include/asm/arch-mx6/mx6-ddr.h |  2 ++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
> index 274a0ba..b12fb64 100644
> --- a/arch/arm/cpu/armv7/mx6/ddr.c
> +++ b/arch/arm/cpu/armv7/mx6/ddr.c
> @@ -1501,6 +1501,29 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo 
> *sysinfo,
>   mdelay(1);
>  }
>  
> +void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
> +   struct mx6_mmdc_calibration *calib)
> +{
> + struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
> + struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
> +
> + calib->p0_mpwldectrl0 = readl(>mpwldectrl0);
> + calib->p0_mpwldectrl1 = readl(>mpwldectrl1);
> + calib->p0_mpdgctrl0 = readl(>mpdgctrl0);
> + calib->p0_mpdgctrl1 = readl(>mpdgctrl1);
> + calib->p0_mprddlctl = readl(>mprddlctl);
> + calib->p0_mpwrdlctl = readl(>mpwrdlctl);
> +
> + if (sysinfo->dsize == 2) {
> + calib->p1_mpwldectrl0 = readl(>mpwldectrl0);
> + calib->p1_mpwldectrl1 = readl(>mpwldectrl1);
> + calib->p1_mpdgctrl0 = readl(>mpdgctrl0);
> + calib->p1_mpdgctrl1 = readl(>mpdgctrl1);
> + calib->p1_mprddlctl = readl(>mprddlctl);
> + calib->p1_mpwrdlctl = readl(>mpwrdlctl);
> + }
> +}
> +
>  void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
> const struct mx6_mmdc_calibration *calib,
> const void *ddr_cfg)
> diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
> b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> index cd5bc97..12454fa 100644
> --- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> +++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
> @@ -461,6 +461,8 @@ void mx6sl_dram_iocfg(unsigned width,
>  #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
>  int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
>  int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
> +void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
> +   struct mx6_mmdc_calibration *calib);
>  #endif
>  
>  /* configure mx6 mmdc registers */
> 


-- 
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[U-Boot] [PATCH v5 20/21] sf: dataflash: Fix add_dataflash return logic

[Jagan Teki]

This patch fixed the add_dataflash return logic,
so-that it can handle both jedec and older chips
same as Linux.

Cc: Bin Meng 
Cc: Simon Glass 
Cc: York Sun 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_dataflash.c | 127 -
 1 file changed, 61 insertions(+), 66 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 7c6c8d2..212aa69 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -586,15 +586,15 @@ static int spi_dataflash_probe(struct udevice *dev)
struct spi_slave *spi = dev_get_parent_priv(dev);
struct spi_flash *spi_flash;
struct flash_info *info;
-   int ret, status = 0;
+   int status;
 
spi_flash = dev_get_uclass_priv(dev);
spi_flash->spi = spi;
spi_flash->dev = dev;
 
-   ret = spi_claim_bus(spi);
-   if (ret)
-   return ret;
+   status = spi_claim_bus(spi);
+   if (status)
+   return status;
 
/*
 * Try to detect dataflash by JEDEC ID.
@@ -605,74 +605,69 @@ static int spi_dataflash_probe(struct udevice *dev)
 */
info = jedec_probe(spi);
if (IS_ERR(info))
-   return PTR_ERR(info);
-   if (info != NULL)
-   add_dataflash(dev, info->name, info->nr_pages,
- info->pagesize, info->pageoffset,
- (info->flags & SUP_POW2PS) ? 'd' : 'c');
-   else {
-   /*
-   * Older chips support only legacy commands, identifing
-   * capacity using bits in the status byte.
-   */
-   status = dataflash_status(spi);
-   if (status <= 0 || status == 0xff) {
-   printf("SPI DataFlash: read status error %d\n", status);
-   if (status == 0 || status == 0xff)
-   status = -ENODEV;
-   goto err_read_cmd;
-   }
-   /*
-   * if there's a device there, assume it's dataflash.
-   * board setup should have set spi->max_speed_max to
-   * match f(car) for continuous reads, mode 0 or 3.
-   */
-   switch (status & 0x3c) {
-   case 0x0c:  /* 0 0 1 1 x x */
-   status = add_dataflash(dev, "AT45DB011B",
-  512, 264, 9, 0);
-   break;
-   case 0x14:  /* 0 1 0 1 x x */
-   status = add_dataflash(dev, "AT45DB021B",
-  1024, 264, 9, 0);
-   break;
-   case 0x1c:  /* 0 1 1 1 x x */
-   status = add_dataflash(dev, "AT45DB041x",
-  2048, 264, 9, 0);
-   break;
-   case 0x24:  /* 1 0 0 1 x x */
-   status = add_dataflash(dev, "AT45DB081B",
-  4096, 264, 9, 0);
-   break;
-   case 0x2c:  /* 1 0 1 1 x x */
-   status = add_dataflash(dev, "AT45DB161x",
-  4096, 528, 10, 0);
-   break;
-   case 0x34:  /* 1 1 0 1 x x */
-   status = add_dataflash(dev, "AT45DB321x",
-  8192, 528, 10, 0);
-   break;
-   case 0x38:  /* 1 1 1 x x x */
-   case 0x3c:
-   status = add_dataflash(dev, "AT45DB642x",
-  8192, 1056, 11, 0);
-   break;
-   /* obsolete AT45DB1282 not (yet?) supported */
-   default:
-   dev_info(>dev, "unsupported device (%x)\n",
-status & 0x3c);
+   goto err_jedec_probe;
+   if (info != NULL) {
+   status = add_dataflash(dev, info->name, info->nr_pages,
+   info->pagesize, info->pageoffset,
+   (info->flags & SUP_POW2PS) ? 'd' : 'c');
+   if (status < 0)
+   goto err_status;
+   }
+
+   /*
+   * Older chips support only legacy commands, identifing
+   * capacity using bits in the status byte.
+   */
+   status = dataflash_status(spi);
+   if (status <= 0 || status == 0xff) {
+   printf("SPI DataFlash: read status error %d\n", status);
+   if (status == 0 || status == 0xff)
status = -ENODEV;
-   goto err_read_cmd;
-   }
+   goto err_jedec_probe;
}
 
-   spi_release_bus(spi);

[U-Boot] [PATCH v5 21/21] sf: dataflash: Minor cleanups

[Jagan Teki]

- fix single line comments
- remove unneeded spaces
- ascending order of include files
- rename SPI DATAFLASH to dataflash
- rename SPI DataFlash to dataflash
- return NULL replaced with error code

Cc: Bin Meng 
Cc: Simon Glass 
Cc: York Sun 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_dataflash.c | 38 +++---
 1 file changed, 15 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 212aa69..bcddfa0 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -1,12 +1,12 @@
 /*
- *
  * Atmel DataFlash probing
  *
  * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
  * Haikun Wang (haikun.w...@freescale.com)
  *
  * SPDX-License-Identifier:GPL-2.0+
-*/
+ */
+
 #include 
 #include 
 #include 
@@ -67,15 +67,12 @@
 #define OP_WRITE_SECURITY_REVC 0x9A
 #define OP_WRITE_SECURITY  0x9B/* revision D */
 
-
 struct dataflash {
uint8_t command[16];
unsigned short  page_offset;/* offset in flash address */
 };
 
-/*
- * Return the status of the DataFlash device.
- */
+/* Return the status of the DataFlash device */
 static inline int dataflash_status(struct spi_slave *spi)
 {
int ret;
@@ -114,9 +111,7 @@ static int dataflash_waitready(struct spi_slave *spi)
return -ETIME;
 }
 
-/*
- * Erase pages of flash.
- */
+/* Erase pages of flash */
 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
 {
struct dataflash*dataflash;
@@ -147,7 +142,7 @@ static int spi_dataflash_erase(struct udevice *dev, u32 
offset, size_t len)
 
status = spi_claim_bus(spi);
if (status) {
-   debug("SPI DATAFLASH: unable to claim SPI bus\n");
+   debug("dataflash: unable to claim SPI bus\n");
return status;
}
 
@@ -232,7 +227,7 @@ static int spi_dataflash_read(struct udevice *dev, u32 
offset, size_t len,
 
status = spi_claim_bus(spi);
if (status) {
-   debug("SPI DATAFLASH: unable to claim SPI bus\n");
+   debug("dataflash: unable to claim SPI bus\n");
return status;
}
 
@@ -290,7 +285,7 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
 
status = spi_claim_bus(spi);
if (status) {
-   debug("SPI DATAFLASH: unable to claim SPI bus\n");
+   debug("dataflash: unable to claim SPI bus\n");
return status;
}
 
@@ -387,7 +382,7 @@ int spi_dataflash_write(struct udevice *dev, u32 offset, 
size_t len,
 
/* Check result of the compare operation */
if (status & (1 << 6)) {
-   printf("SPI DataFlash: write compare page %u, err %d\n",
+   printf("dataflash: write compare page %u, err %d\n",
   pageaddr, status);
remaining = 0;
status = -EIO;
@@ -539,7 +534,7 @@ static struct flash_info *jedec_probe(struct spi_slave *spi)
if (info->flags & SUP_POW2PS) {
status = dataflash_status(spi);
if (status < 0) {
-   debug("SPI DataFlash: status error 
%d\n",
+   debug("dataflash: status error %d\n",
  status);
return NULL;
}
@@ -561,10 +556,8 @@ static struct flash_info *jedec_probe(struct spi_slave 
*spi)
 * size (it might be binary) even when we can tell which density
 * class is involved (legacy chip id scheme).
 */
-   printf("SPI DataFlash: Unsupported flash IDs: ");
-   printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
-  id[0], jedec, id[3] << 8 | id[4]);
-   return NULL;
+   printf("dataflash: JEDEC id %06x not handled\n", jedec);
+   return ERR_PTR(-ENODEV);
 }
 
 /*
@@ -614,19 +607,19 @@ static int spi_dataflash_probe(struct udevice *dev)
goto err_status;
}
 
-   /*
+   /*
* Older chips support only legacy commands, identifing
* capacity using bits in the status byte.
*/
status = dataflash_status(spi);
if (status <= 0 || status == 0xff) {
-   printf("SPI DataFlash: read status error %d\n", status);
+   printf("dataflash: read status error %d\n", status);
if (status == 0 || status == 0xff)
status = -ENODEV;
goto err_jedec_probe;
}
 
-   /*
+   /*
* if there's a device there, assume it's dataflash.
* board setup should have set spi->max_speed_max to
* match f(car) 

[U-Boot] [PATCH v5 19/21] sf: dataflash: Move flash id detection into jedec_probe

[Jagan Teki]

Flash id detection should be the first step to enumerate
the connected flash on the board, once ie done checking
with respective id codes locally in the driver all this
should be part of jedec_probe instead of id detection and
validated through flash_info{} table separatly.

Cc: Bin Meng 
Cc: Simon Glass 
Cc: York Sun 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_dataflash.c | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index 6a9dfef..7c6c8d2 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -501,9 +501,10 @@ static struct flash_info dataflash_data[] = {
{ "at45db642d",  0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
 };
 
-static struct flash_info *jedec_probe(struct spi_slave *spi, u8 *id)
+static struct flash_info *jedec_probe(struct spi_slave *spi)
 {
int tmp;
+   uint8_t id[5];
uint32_tjedec;
struct flash_info   *info;
int status;
@@ -517,6 +518,11 @@ static struct flash_info *jedec_probe(struct spi_slave 
*spi, u8 *id)
 * That's not an error; only rev C and newer chips handle it, and
 * only Atmel sells these chips.
 */
+   tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
+   if (tmp < 0) {
+   printf("dataflash: error %d reading JEDEC ID\n", tmp);
+   return ERR_PTR(tmp);
+   }
if (id[0] != 0x1f)
return NULL;
 
@@ -580,7 +586,6 @@ static int spi_dataflash_probe(struct udevice *dev)
struct spi_slave *spi = dev_get_parent_priv(dev);
struct spi_flash *spi_flash;
struct flash_info *info;
-   u8 idcode[5];
int ret, status = 0;
 
spi_flash = dev_get_uclass_priv(dev);
@@ -591,12 +596,6 @@ static int spi_dataflash_probe(struct udevice *dev)
if (ret)
return ret;
 
-   ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
-   if (ret) {
-   printf("SPI DataFlash: Failed to get idcodes\n");
-   goto err_read_cmd;
-   }
-
/*
 * Try to detect dataflash by JEDEC ID.
 * If it succeeds we know we have either a C or D part.
@@ -604,7 +603,9 @@ static int spi_dataflash_probe(struct udevice *dev)
 * Both support the security register, though with different
 * write procedures.
 */
-   info = jedec_probe(spi, idcode);
+   info = jedec_probe(spi);
+   if (IS_ERR(info))
+   return PTR_ERR(info);
if (info != NULL)
add_dataflash(dev, info->name, info->nr_pages,
  info->pagesize, info->pageoffset,
-- 
2.7.4

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[U-Boot] [PATCH v5 18/21] sf: dataflash: Remove unneeded spi data

[Jagan Teki]

dataflash doesn't require options, memory_map from spi.

Cc: Bin Meng 
Cc: Simon Glass 
Cc: York Sun 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_dataflash.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/mtd/spi/sf_dataflash.c b/drivers/mtd/spi/sf_dataflash.c
index b2a56da..6a9dfef 100644
--- a/drivers/mtd/spi/sf_dataflash.c
+++ b/drivers/mtd/spi/sf_dataflash.c
@@ -584,6 +584,7 @@ static int spi_dataflash_probe(struct udevice *dev)
int ret, status = 0;
 
spi_flash = dev_get_uclass_priv(dev);
+   spi_flash->spi = spi;
spi_flash->dev = dev;
 
ret = spi_claim_bus(spi);
@@ -664,11 +665,6 @@ static int spi_dataflash_probe(struct udevice *dev)
}
}
 
-   /* Assign spi data */
-   spi_flash->spi = spi;
-   spi_flash->memory_map = spi->memory_map;
-   spi_flash->dual_flash = spi->option;
-
spi_release_bus(spi);
 
return 0;
-- 
2.7.4

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[U-Boot] [PATCH v5 17/21] spi: Remove dual flash code

[Jagan Teki]

Dual flash code in spi are usually take the spi controller
to work with dual connected flash devices. Usually these
dual connection operation's are referred to flash controller
protocol rather with spi controller protocol, these are still
present in flash side for the usage of spi-nor controllers.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf.c| 4 
 drivers/mtd/spi/spi_flash.c | 1 -
 include/spi.h   | 6 --
 3 files changed, 11 deletions(-)

diff --git a/drivers/mtd/spi/sf.c b/drivers/mtd/spi/sf.c
index 664e860..d5e175c 100644
--- a/drivers/mtd/spi/sf.c
+++ b/drivers/mtd/spi/sf.c
@@ -18,10 +18,6 @@ static int spi_flash_read_write(struct spi_slave *spi,
unsigned long flags = SPI_XFER_BEGIN;
int ret;
 
-#ifdef CONFIG_SF_DUAL_FLASH
-   if (spi->flags & SPI_XFER_U_PAGE)
-   flags |= SPI_XFER_U_PAGE;
-#endif
if (data_len == 0)
flags |= SPI_XFER_END;
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b4001a5..708991c 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1016,7 +1016,6 @@ int spi_flash_scan(struct spi_flash *flash)
 
flash->name = info->name;
flash->memory_map = spi->memory_map;
-   flash->dual_flash = spi->option;
 
if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
diff --git a/include/spi.h b/include/spi.h
index 4c17983..deb65ef 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -30,10 +30,6 @@
 #define SPI_RX_DUALBIT(12) /* receive with 2 wires */
 #define SPI_RX_QUADBIT(13) /* receive with 4 wires */
 
-/* SPI bus connection options - see enum spi_dual_flash */
-#define SPI_CONN_DUAL_SHARED   (1 << 0)
-#define SPI_CONN_DUAL_SEPARATED(1 << 1)
-
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE  0xec
 
@@ -93,7 +89,6 @@ struct dm_spi_slave_platdata {
  * @max_write_size:If non-zero, the maximum number of bytes which can
  * be written at once, excluding command bytes.
  * @memory_map:Address of read-only SPI flash access.
- * @option:Varies SPI bus options - separate, shared bus.
  * @flags: Indication of SPI flags.
  */
 struct spi_slave {
@@ -117,7 +112,6 @@ struct spi_slave {
 #define SPI_XFER_ONCE  (SPI_XFER_BEGIN | SPI_XFER_END)
 #define SPI_XFER_MMAP  BIT(2)  /* Memory Mapped start */
 #define SPI_XFER_MMAP_END  BIT(3)  /* Memory Mapped End */
-#define SPI_XFER_U_PAGEBIT(4)
 };
 
 /**
-- 
2.7.4

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[U-Boot] [PATCH v5 16/21] sf: Rename few local functions

[Jagan Teki]

spi_flash_write_bar-> write_bar
spi_flash_write_bar -> read_bar
spi_flash_cmd_wait_ready -> spi_flash_wait_till_ready

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  2 +-
 drivers/mtd/spi/spi_flash.c   | 23 +++
 2 files changed, 12 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index d50fb9a..2feb3b8 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -184,7 +184,7 @@ static inline int spi_flash_cmd_write_disable(struct 
spi_flash *flash)
  * - SPI claim
  * - spi_flash_cmd_write_enable
  * - spi_flash_cmd_write
- * - spi_flash_cmd_wait_ready
+ * - spi_flash_wait_till_ready
  * - SPI release
  */
 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index c1025c9..b4001a5 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -144,7 +144,7 @@ static int write_evcr(struct spi_flash *flash, u8 evcr)
 #endif
 
 #ifdef CONFIG_SPI_FLASH_BAR
-static int spi_flash_write_bar(struct spi_flash *flash, u32 offset)
+static int write_bar(struct spi_flash *flash, u32 offset)
 {
u8 cmd, bank_sel;
int ret;
@@ -165,8 +165,7 @@ bar_end:
return flash->bank_curr;
 }
 
-static int spi_flash_read_bar(struct spi_flash *flash,
- const struct spi_flash_info *info)
+static int read_bar(struct spi_flash *flash, const struct spi_flash_info *info)
 {
u8 curr_bank = 0;
int ret;
@@ -263,8 +262,8 @@ static int spi_flash_ready(struct spi_flash *flash)
return sr && fsr;
 }
 
-static int spi_flash_cmd_wait_ready(struct spi_flash *flash,
-   unsigned long timeout)
+static int spi_flash_wait_till_ready(struct spi_flash *flash,
+unsigned long timeout)
 {
unsigned long timebase;
int ret;
@@ -312,7 +311,7 @@ int spi_flash_write_common(struct spi_flash *flash, const 
u8 *cmd,
return ret;
}
 
-   ret = spi_flash_cmd_wait_ready(flash, timeout);
+   ret = spi_flash_wait_till_ready(flash, timeout);
if (ret < 0) {
debug("SF: write %s timed out\n",
  timeout == SPI_FLASH_PROG_TIMEOUT ?
@@ -354,7 +353,7 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 
offset, size_t len)
spi_flash_dual(flash, _addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, erase_addr);
+   ret = write_bar(flash, erase_addr);
if (ret < 0)
return ret;
 #endif
@@ -405,7 +404,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 
offset,
spi_flash_dual(flash, _addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, write_addr);
+   ret = write_bar(flash, write_addr);
if (ret < 0)
return ret;
 #endif
@@ -509,7 +508,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 
offset,
spi_flash_dual(flash, _addr);
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_write_bar(flash, read_addr);
+   ret = write_bar(flash, read_addr);
if (ret < 0)
return ret;
bank_sel = flash->bank_curr;
@@ -561,7 +560,7 @@ static int sst_byte_write(struct spi_flash *flash, u32 
offset, const void *buf)
if (ret)
return ret;
 
-   return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+   return spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 }
 
 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
@@ -609,7 +608,7 @@ int sst_write_wp(struct spi_flash *flash, u32 offset, 
size_t len,
break;
}
 
-   ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+   ret = spi_flash_wait_till_ready(flash, SPI_FLASH_PROG_TIMEOUT);
if (ret)
break;
 
@@ -1137,7 +1136,7 @@ int spi_flash_scan(struct spi_flash *flash)
 
/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
-   ret = spi_flash_read_bar(flash, info);
+   ret = read_bar(flash, info);
if (ret < 0)
return ret;
 #endif
-- 
2.7.4

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[U-Boot] [PATCH v5 15/21] sf: ids: Use small letter in ext_jedec

[Jagan Teki]

Use small 'd' in s25s512s ext_jedec

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash_ids.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index bdc6244..77fe3dd 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -95,7 +95,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25s256s_64k",   INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
-   {"s25s512s",   INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
+   {"s25s512s",   INFO(0x010220, 0x4d00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"s25fl512s_64k",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
-- 
2.7.4

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[U-Boot] [PATCH v5 14/21] sf: ids: Use small letter's with flash name

[Jagan Teki]

For readability use small letter's with flash name.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash_ids.c | 220 
 1 file changed, 110 insertions(+), 110 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index 3648608..bdc6244 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -41,136 +41,136 @@
 
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
-   {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-   {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
-   {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
-   {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
-   {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
-   {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT25DF321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
-   {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
+   {"at45db011d", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+   {"at45db021d", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"at45db041d", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"at45db081d", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
+   {"at45db161d", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
+   {"at45db321d", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at45db641d", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"at25df321a", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at25df321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"at26df081a", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_EON/* EON */
-   {"EN25Q32B",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
-   {"EN25Q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"EN25Q128B",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
-   {"EN25S64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
+   {"en25q32b",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
+   {"en25q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"en25q128b",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
+   {"en25s64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
 #endif
 #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
-   {"GD25Q64B",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
-   {"GD25LQ32",   INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
+   {"gd25q64b",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"gd25lq32",   INFO(0xc86016, 0x0, 64 * 1024,64, SECT_4K) },
 #endif
 #ifdef CONFIG_SPI_FLASH_ISSI   /* ISSI */
-   {"IS25LP032",  INFO(0x9d6016, 0x0, 64 * 1024,64, 0) },
-   {"IS25LP064",  INFO(0x9d6017, 0x0, 64 * 1024,   128, 0) },
-   {"IS25LP128",  INFO(0x9d6018, 0x0, 64 * 1024,   256, 0) },
+   {"is25lp032",  INFO(0x9d6016, 0x0, 64 * 1024,64, 0) },
+   {"is25lp064",  INFO(0x9d6017, 0x0, 64 * 1024,   128, 0) },
+   {"is25lp128",  INFO(0x9d6018, 0x0, 64 * 1024,   256, 0) },
 #endif
 #ifdef CONFIG_SPI_FLASH_MACRONIX   /* MACRONIX */
-   {"MX25L2006E", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
-   {"MX25L4005",  INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
-   {"MX25L8005",  INFO(0xc22014, 0x0, 64 * 1024,16, 0) },
-   {"MX25L1605D", INFO(0xc22015, 0x0, 64 * 1024,32, 0) },
-   {"MX25L3205D", INFO(0xc22016, 0x0, 64 * 1024,64, 0) },
-   {"MX25L6405D", INFO(0xc22017, 0x0, 64 * 1024,   128, 0) },
-   {"MX25L12805", INFO(0xc22018, 0x0, 64 * 1024,   256, RD_FULL | 
WR_QPP) },
-   {"MX25L25635F",INFO(0xc22019, 0x0, 64 * 1024,   512, RD_FULL | 
WR_QPP) },
-   {"MX25L51235F",INFO(0xc2201a, 0x0, 64 * 1024,  1024, RD_FULL | 
WR_QPP) },
-   {"MX25L12855E",INFO(0xc22618, 0x0, 64 * 1024,   256, RD_FULL | 
WR_QPP) },
+   {"mx25l2006e", INFO(0xc22012, 0x0, 64 * 1024, 4, 0) },
+   {"mx25l4005",  INFO(0xc22013, 0x0, 64 * 1024, 8, 0) },
+   {"mx25l8005",  INFO(0xc22014, 0x0, 64 * 1024,16, 0) },
+   {"mx25l1605d", INFO(0xc22015, 0x0, 64 * 1024,32, 0) },
+   {"mx25l3205d",   

[U-Boot] [PATCH v5 12/21] sf: Remove non-meaningful comments

[Jagan Teki]

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 27b85ba..c1025c9 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1015,16 +1015,13 @@ int spi_flash_scan(struct spi_flash *flash)
JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST)
write_sr(flash, 0);
 
-   /* Assign spi data */
flash->name = info->name;
flash->memory_map = spi->memory_map;
flash->dual_flash = spi->option;
 
-   /* Assign spi flash flags */
if (info->flags & SST_WR)
flash->flags |= SNOR_F_SST_WR;
 
-   /* Assign spi_flash ops */
 #ifndef CONFIG_DM_SPI_FLASH
flash->write = spi_flash_cmd_write_ops;
 #if defined(CONFIG_SPI_FLASH_SST)
-- 
2.7.4

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[U-Boot] [PATCH v5 13/21] sf: Rename sf_params.c to spi_flash_ids

[Jagan Teki]

spi_flash_ids.c is more meaningful name as the flash_info
table structure spi_flash_info has spi_flash_ids instance.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/Makefile|   2 +-
 drivers/mtd/spi/spi_flash_ids.c | 176 
 2 files changed, 177 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/spi/spi_flash_ids.c

diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index f3dc409..fcda023 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SPL_SPI_BOOT)+= fsl_espi_spl.o
 obj-$(CONFIG_SPL_SPI_SUNXI)+= sunxi_spi_spl.o
 endif
 
-obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o sf_params.o sf.o
+obj-$(CONFIG_SPI_FLASH) += sf_probe.o spi_flash.o spi_flash_ids.o sf.o
 obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
 obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
 obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
new file mode 100644
index 000..3648608
--- /dev/null
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -0,0 +1,176 @@
+/*
+ * SPI Flash ID's.
+ *
+ * Copyright (C) 2016 Jagan Teki 
+ * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include "sf_internal.h"
+
+/* Used when the "_ext_id" is two bytes at most */
+#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
+const struct spi_flash_info spi_flash_ids[] = {
+#ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
+   {"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
+   {"AT45DB021D", INFO(0x1f2300, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB041D", INFO(0x1f2400, 0x0, 64 * 1024, 8, SECT_4K) },
+   {"AT45DB081D", INFO(0x1f2500, 0x0, 64 * 1024,16, SECT_4K) },
+   {"AT45DB161D", INFO(0x1f2600, 0x0, 64 * 1024,32, SECT_4K) },
+   {"AT45DB321D", INFO(0x1f2700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT45DB641D", INFO(0x1f2800, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"AT25DF321A", INFO(0x1f4701, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT25DF321",  INFO(0x1f4700, 0x0, 64 * 1024,64, SECT_4K) },
+   {"AT26DF081A", INFO(0x1f4501, 0x0, 64 * 1024,16, SECT_4K) },
+#endif
+#ifdef CONFIG_SPI_FLASH_EON/* EON */
+   {"EN25Q32B",   INFO(0x1c3016, 0x0, 64 * 1024,64, 0) },
+   {"EN25Q64",INFO(0x1c3017, 0x0, 64 * 1024,   128, SECT_4K) },
+   {"EN25Q128B",  INFO(0x1c3018, 0x0, 64 * 1024,   256, 0) },
+   {"EN25S64",INFO(0x1c3817, 0x0, 64 * 1024,   128, 0) },
+#endif
+#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
+   {"GD25Q64B",   INFO(0xc84017, 0x0, 64 * 1024,   128, SECT_4K) },
+

[U-Boot] [PATCH v5 11/21] sf: Remove legacy idcode detection code

[Jagan Teki]

Since flash detection code is more mature to
detect even with 6 bytes id length devices
removed old code and related references.

Cc: Yunhui Cui 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Michael Trimarchi 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h |  6 
 drivers/mtd/spi/spi_flash.c   | 78 ---
 2 files changed, 84 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index f2ea368..d50fb9a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -99,12 +99,6 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, size_t 
len,
const void *buf);
 #endif
 
-#ifdef CONFIG_SPI_FLASH_SPANSION
-/* Used for Spansion S25FS-S family flash only. */
-#define CMD_SPANSION_RDAR  0x65 /* Read any device register */
-#define CMD_SPANSION_WRAR  0x71 /* Write any device register */
-#endif
-
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index ba884d7..27b85ba 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -999,94 +999,16 @@ int spi_flash_decode_fdt(const void *blob, struct 
spi_flash *flash)
 }
 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
 
-#ifdef CONFIG_SPI_FLASH_SPANSION
-static int spansion_s25fss_disable_4KB_erase(struct spi_slave *spi)
-{
-   u8 cmd[4];
-   u32 offset = 0x84; /* CR3V register offset */
-   u8 cr3v;
-   int ret;
-
-   cmd[0] = CMD_SPANSION_RDAR;
-   cmd[1] = offset >> 16;
-   cmd[2] = offset >> 8;
-   cmd[3] = offset >> 0;
-
-   ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
-   if (ret)
-   return -EIO;
-   /* CR3V bit3: 4-KB Erase */
-   if (cr3v & 0x8)
-   return 0;
-
-   cmd[0] = CMD_SPANSION_WRAR;
-   cr3v |= 0x8;
-   ret = spi_flash_cmd_write(spi, cmd, 4, , 1);
-   if (ret)
-   return -EIO;
-
-   cmd[0] = CMD_SPANSION_RDAR;
-   ret = spi_flash_cmd_read(spi, cmd, 4, , 1);
-   if (ret)
-   return -EIO;
-   if (!(cr3v & 0x8))
-   return -EFAULT;
-
-   return 0;
-}
-#endif
-
 int spi_flash_scan(struct spi_flash *flash)
 {
struct spi_slave *spi = flash->spi;
const struct spi_flash_info *info = NULL;
-   u16 jedec, ext_jedec;
-   u8 idcode[5];
int ret;
 
info = spi_flash_read_id(flash);
if (IS_ERR_OR_NULL(info))
return -ENOENT;
 
-   jedec = idcode[1] << 8 | idcode[2];
-   ext_jedec = idcode[3] << 8 | idcode[4];
-
-#ifdef CONFIG_SPI_FLASH_SPANSION
-   /*
-* The S25FS-S family physical sectors may be configured as a
-* hybrid combination of eight 4-kB parameter sectors
-* at the top or bottom of the address space with all
-* but one of the remaining sectors being uniform size.
-* The Parameter Sector Erase commands (20h or 21h) must
-* be used to erase the 4-kB parameter sectors individually.
-* The Sector (uniform sector) Erase commands (D8h or DCh)
-* must be used to erase any of the remaining
-* sectors, including the portion of highest or lowest address
-* sector that is not overlaid by the parameter sectors.
-* The uniform sector erase command has no effect on parameter sectors.
-*/
-   if ((jedec == 0x0219 || (jedec == 0x0220)) &&
-   (ext_jedec & 0xff00) == 0x4d00) {
-   int ret;
-   u8 id[6];
-
-   /* Read the ID codes again, 6 bytes */
-   ret = spi_flash_cmd(flash->spi, CMD_READ_ID, id, sizeof(id));
-   if (ret)
-   return -EIO;
-
-   ret = memcmp(id, idcode, 5);
-   if (ret)
-   return -EIO;
-
-   /* 0x81: S25FS-S family 0x80: S25FL-S family */
-   if (id[5] == 0x81) {
-   ret = spansion_s25fss_disable_4KB_erase(spi);
-   if (ret)
-   return ret;
-   }
-   }
-#endif
/* Flash powers up read-only, so clear BP# bits */
if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_ATMEL ||
JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_MACRONIX ||
-- 
2.7.4

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[U-Boot] [PATCH v5 10/21] sf: params: Add S25FS256S_64K spi flash support

[Jagan Teki]

Add Spansion S25FS256S_64K spi flash to the list of spi_flash_ids.

In spansion S25FS-S family the physical sectors are grouped as
normal and parameter sectors. Parameter sectors are 4kB in size
with 8 set located at the bottom or top address of a device.
Normal sectors are similar to other flash family with sizes of
64kB or 32 kB.

To erase whole flash using sector erase(D8h or DCh) won't effect
the parameter sectors, so in order to erase these we must use 4K
sector erase commands (20h or 21h) separately.

So better to erase the whole flash using 4K sector erase instead
of detecting these family parts again and do two different erase
operations.

Cc: Yunhui Cui 
Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Michael Trimarchi 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_params.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 344d9c9..b029c76 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -93,6 +93,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"S25FL128S_64K",  INFO(0x012018, 0x4d01,  64 * 1024,   256, RD_FULL | 
WR_QPP) },
{"S25FL256S_256K", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"S25FL256S_64K",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
+   {"S25FS256S_64K",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
{"S25FS512S",  INFO(0x010220, 0x4D00, 128 * 1024,   512, RD_FULL | 
WR_QPP) },
{"S25FL512S_256K", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"S25FL512S_64K",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
-- 
2.7.4

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[U-Boot] [PATCH v5 07/21] sf: Add SPI_FLASH_MAX_ID_LEN

[Jagan Teki]

Add id length of 5 bytes numerical value to macro.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 3 ++-
 drivers/mtd/spi/spi_flash.c   | 4 ++--
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 527c252..437ac8a 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,6 +108,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
+#define SPI_FLASH_MAX_ID_LEN   5
 
 struct spi_flash_info {
const char  *name;
@@ -117,7 +118,7 @@ struct spi_flash_info {
 * The first three bytes are the JEDIC ID.
 * JEDEC ID zero means "no ID" (mostly older chips).
 */
-   u8  id[5];
+   u8  id[SPI_FLASH_MAX_ID_LEN];
u8  id_len;
 
/* The size listed here is what works with SPINOR_OP_SE, which isn't
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0777bb5..ba884d7 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -928,10 +928,10 @@ static int micron_quad_enable(struct spi_flash *flash)
 static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
 {
int tmp;
-   u8  id[5];
+   u8  id[SPI_FLASH_MAX_ID_LEN];
const struct spi_flash_info *info;
 
-   tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, 5);
+   tmp = spi_flash_cmd(flash->spi, CMD_READ_ID, id, SPI_FLASH_MAX_ID_LEN);
if (tmp < 0) {
printf("SF: error %d reading JEDEC ID\n", tmp);
return ERR_PTR(tmp);
-- 
2.7.4

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[U-Boot] [PATCH v5 08/21] sf: Increase max id length by 1 byte

[Jagan Teki]

So, now SPI_FLASH_ID_MAX_LEN is 6 bytes useful for
few spansion flash families S25FS-S

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 437ac8a..f2ea368 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,7 +108,7 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_MFR(info)((info)->id[0])
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
-#define SPI_FLASH_MAX_ID_LEN   5
+#define SPI_FLASH_MAX_ID_LEN   6
 
 struct spi_flash_info {
const char  *name;
-- 
2.7.4

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[U-Boot] [PATCH v5 09/21] sf: Add INFO6 flash_info macro

[Jagan Teki]

INFO6 is for tabulating 6 byte flash parts, Ex: S25FS256S_64K

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_params.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 8a2a6b2..344d9c9 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -23,6 +23,21 @@
.page_size = 256,   \
.flags = (_flags),
 
+#define INFO6(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags)\
+   .id = { \
+   ((_jedec_id) >> 16) & 0xff, \
+   ((_jedec_id) >> 8) & 0xff,  \
+   (_jedec_id) & 0xff, \
+   ((_ext_id) >> 16) & 0xff,   \
+   ((_ext_id) >> 8) & 0xff,\
+   (_ext_id) & 0xff,   \
+   },  \
+   .id_len = 6,\
+   .sector_size = (_sector_size),  \
+   .n_sectors = (_n_sectors),  \
+   .page_size = 256,   \
+   .flags = (_flags),
+
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-- 
2.7.4

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[U-Boot] [PATCH v5 06/21] sf: nr_sectors -> n_sectors

[Jagan Teki]

Rename nr_sectors as n_sectors to sync with Linux.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c | 2 +-
 drivers/mtd/spi/sf_internal.h | 2 +-
 drivers/mtd/spi/sf_params.c   | 2 +-
 drivers/mtd/spi/spi_flash.c   | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index 09ce783..4944059 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -289,7 +289,7 @@ static int sandbox_sf_process_cmd(struct sandbox_spi_flash 
*sbsf, const u8 *rx,
/* we only support erase here */
if (sbsf->cmd == CMD_ERASE_CHIP) {
sbsf->erase_size = sbsf->data->sector_size *
-   sbsf->data->nr_sectors;
+   sbsf->data->n_sectors;
} else if (sbsf->cmd == CMD_ERASE_4K && (flags & SECT_4K)) {
sbsf->erase_size = 4 << 10;
} else if (sbsf->cmd == CMD_ERASE_64K && !(flags & SECT_4K)) {
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 4a88cf7..527c252 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -124,7 +124,7 @@ struct spi_flash_info {
 * necessarily called a "sector" by the vendor.
 */
u32 sector_size;
-   u32 nr_sectors;
+   u32 n_sectors;
 
u16 page_size;
 
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 7314455..8a2a6b2 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -19,7 +19,7 @@
},  \
.id_len = (!(_jedec_id) ? 0 : (3 + ((_ext_id) ? 2 : 0))),   
\
.sector_size = (_sector_size),  \
-   .nr_sectors = (_n_sectors), \
+   .n_sectors = (_n_sectors),  \
.page_size = 256,   \
.flags = (_flags),
 
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index b92b0bf..0777bb5 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1143,7 +1143,7 @@ int spi_flash_scan(struct spi_flash *flash)
}
flash->page_size <<= flash->shift;
flash->sector_size = info->sector_size << flash->shift;
-   flash->size = flash->sector_size * info->nr_sectors << flash->shift;
+   flash->size = flash->sector_size * info->n_sectors << flash->shift;
 #ifdef CONFIG_SF_DUAL_FLASH
if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
flash->size <<= 1;
-- 
2.7.4

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[U-Boot] [PATCH v5 05/21] sf: Cleanup sf_params

[Jagan Teki]

- Move headers froms sf_params to common header file
- Removed unnecessary comment

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 5 +++--
 drivers/mtd/spi/sf_params.c   | 5 -
 2 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 71feba9..4a88cf7 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -10,8 +10,9 @@
 #ifndef _SF_INTERNAL_H_
 #define _SF_INTERNAL_H_
 
-#include 
-#include 
+#include 
+#include 
+#include 
 
 /* Dual SPI flash memories - see SPI_COMM_DUAL_... */
 enum spi_dual_flash {
diff --git a/drivers/mtd/spi/sf_params.c b/drivers/mtd/spi/sf_params.c
index 7fcc3bc..7314455 100644
--- a/drivers/mtd/spi/sf_params.c
+++ b/drivers/mtd/spi/sf_params.c
@@ -6,10 +6,6 @@
  * SPDX-License-Identifier:GPL-2.0+
  */
 
-#include 
-#include 
-#include 
-
 #include "sf_internal.h"
 
 /* Used when the "_ext_id" is two bytes at most */
@@ -27,7 +23,6 @@
.page_size = 256,   \
.flags = (_flags),
 
-/* SPI/QSPI flash device params structure */
 const struct spi_flash_info spi_flash_ids[] = {
 #ifdef CONFIG_SPI_FLASH_ATMEL  /* ATMEL */
{"AT45DB011D", INFO(0x1f2200, 0x0, 64 * 1024, 4, SECT_4K) },
-- 
2.7.4

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[U-Boot] [PATCH v5 04/21] sf: Cleanup spi_flash_info{}

[Jagan Teki]

- Proper tabs spaces
- Removed unnecessary
- Added meaningful comments 

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sf_internal.h | 22 --
 1 file changed, 8 insertions(+), 14 deletions(-)

diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index a9455ac..71feba9 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -108,17 +108,8 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
 #define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
 
-/**
- * struct spi_flash_info - SPI/QSPI flash device params structure
- *
- * @name:  Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @sector_size:   Isn't necessarily a sector size from vendor,
- * the size listed here is what works with CMD_ERASE_64K
- * @nr_sectors:No.of sectors on this device
- * @flags: Important param, for flash specific behaviour
- */
 struct spi_flash_info {
-   const char *name;
+   const char  *name;
 
/*
 * This array stores the ID bytes.
@@ -128,12 +119,15 @@ struct spi_flash_info {
u8  id[5];
u8  id_len;
 
-   u32 sector_size;
-   u32 nr_sectors;
+   /* The size listed here is what works with SPINOR_OP_SE, which isn't
+* necessarily called a "sector" by the vendor.
+*/
+   u32 sector_size;
+   u32 nr_sectors;
 
-   u16 page_size;
+   u16 page_size;
 
-   u16 flags;
+   u16 flags;
 #define SECT_4KBIT(0)
 #define E_FSR  BIT(1)
 #define SST_WR BIT(2)
-- 
2.7.4

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[U-Boot] [PATCH v5 02/21] sf: Simplify lock ops detection code

[Jagan Teki]

Simplify the flash_lock ops detection code and added
meaningful comment.

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/spi_flash.c | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index daa9014..b92b0bf 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -1117,19 +1117,15 @@ int spi_flash_scan(struct spi_flash *flash)
flash->read = spi_flash_cmd_read_ops;
 #endif
 
-   /* lock hooks are flash specific - assign them based on idcode0 */
-   switch (JEDEC_MFR(info)) {
 #if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
-   case SPI_FLASH_CFI_MFR_STMICRO:
-   case SPI_FLASH_CFI_MFR_SST:
+   /* NOR protection support for STmicro/Micron chips and similar */
+   if (JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_STMICRO ||
+   JEDEC_MFR(info) == SPI_FLASH_CFI_MFR_SST) {
flash->flash_lock = stm_lock;
flash->flash_unlock = stm_unlock;
flash->flash_is_locked = stm_is_locked;
-#endif
-   break;
-   default:
-   debug("SF: Lock ops not supported for %02x flash\n", 
JEDEC_MFR(info));
}
+#endif
 
/* Compute the flash size */
flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
-- 
2.7.4

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[U-Boot] [PATCH v5 03/21] sf: sandbox: Use JEDEC_MFR|ID in id exctract

[Jagan Teki]

Instead of extracting id's separately better
to use JEDEC_MFR|ID for code simplicity.

Cc: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index d68ee4a..09ce783 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -359,9 +359,8 @@ static int sandbox_sf_xfer(struct udevice *dev, unsigned 
int bitlen,
debug(" id: off:%u tx:", sbsf->off);
if (sbsf->off < IDCODE_LEN) {
/* Extract correct byte from ID 0x00aabbcc */
-   id = sbsf->data)->id[0]) << 16) |
-   (((sbsf->data)->id[1]) << 8 |
-   ((sbsf->data)->id[2]))) >>
+   id = ((JEDEC_MFR(sbsf->data) << 16) |
+   JEDEC_ID(sbsf->data)) >>
(8 * (IDCODE_LEN - 1 - sbsf->off));
} else {
id = 0;
-- 
2.7.4

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[U-Boot] [PATCH v5 01/21] sf: Adopt flash table INFO macro from Linux

[Jagan Teki]

INFO macro make flash table entries more adjustable like
adding new flash_info attributes, update ID length bytes
and so on and more over it will sync to Linux way of defining
flash_info attributes.

- Add JEDEC_ID
- Add JEDEC_EXT macro
- Add JEDEC_MFR
- spi_flash_params => spi_flash_info
- params => info

Cc: Simon Glass 
Cc: Bin Meng 
Cc: York Sun 
Cc: Vignesh R 
Cc: Mugunthan V N 
Cc: Michal Simek 
Cc: Siva Durga Prasad Paladugu 
Signed-off-by: Jagan Teki 
---
 drivers/mtd/spi/sandbox.c |  10 +-
 drivers/mtd/spi/sf_internal.h |  26 +++--
 drivers/mtd/spi/sf_params.c   | 217 ++
 drivers/mtd/spi/spi_flash.c   | 119 ---
 include/linux/err.h   |   5 +
 5 files changed, 205 insertions(+), 172 deletions(-)

diff --git a/drivers/mtd/spi/sandbox.c b/drivers/mtd/spi/sandbox.c
index f59134f..d68ee4a 100644
--- a/drivers/mtd/spi/sandbox.c
+++ b/drivers/mtd/spi/sandbox.c
@@ -88,7 +88,7 @@ struct sandbox_spi_flash {
/* The current flash status (see STAT_XXX defines above) */
u16 status;
/* Data describing the flash we're emulating */
-   const struct spi_flash_params *data;
+   const struct spi_flash_info *data;
/* The file on disk to serv up data from */
int fd;
 };
@@ -112,7 +112,7 @@ static int sandbox_sf_probe(struct udevice *dev)
struct sandbox_spi_flash *sbsf = dev_get_priv(dev);
const char *file;
size_t len, idname_len;
-   const struct spi_flash_params *data;
+   const struct spi_flash_info *data;
struct sandbox_spi_flash_plat_data *pdata = dev_get_platdata(dev);
struct sandbox_state *state = state_get_current();
struct udevice *bus = dev->parent;
@@ -168,7 +168,7 @@ static int sandbox_sf_probe(struct udevice *dev)
}
debug("%s: device='%s'\n", __func__, spec);
 
-   for (data = spi_flash_params_table; data->name; data++) {
+   for (data = spi_flash_ids; data->name; data++) {
len = strlen(data->name);
if (idname_len != len)
continue;
@@ -359,7 +359,9 @@ static int sandbox_sf_xfer(struct udevice *dev, unsigned 
int bitlen,
debug(" id: off:%u tx:", sbsf->off);
if (sbsf->off < IDCODE_LEN) {
/* Extract correct byte from ID 0x00aabbcc */
-   id = sbsf->data->jedec >>
+   id = sbsf->data)->id[0]) << 16) |
+   (((sbsf->data)->id[1]) << 8 |
+   ((sbsf->data)->id[2]))) >>
(8 * (IDCODE_LEN - 1 - sbsf->off));
} else {
id = 0;
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index cde4cfb..a9455ac 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -103,24 +103,36 @@ int sst_write_bp(struct spi_flash *flash, u32 offset, 
size_t len,
 #define CMD_SPANSION_RDAR  0x65 /* Read any device register */
 #define CMD_SPANSION_WRAR  0x71 /* Write any device register */
 #endif
+
+#define JEDEC_MFR(info)((info)->id[0])
+#define JEDEC_ID(info) (((info)->id[1]) << 8 | ((info)->id[2]))
+#define JEDEC_EXT(info)(((info)->id[3]) << 8 | ((info)->id[4]))
+
 /**
- * struct spi_flash_params - SPI/QSPI flash device params structure
+ * struct spi_flash_info - SPI/QSPI flash device params structure
  *
  * @name:  Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
- * @jedec: Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
- * @ext_jedec: Device ext_jedec ID
  * @sector_size:   Isn't necessarily a sector size from vendor,
  * the size listed here is what works with CMD_ERASE_64K
  * @nr_sectors:No.of sectors on this device
  * @flags: Important param, for flash specific behaviour
  */
-struct spi_flash_params {
+struct spi_flash_info {
const char *name;
-   u32 jedec;
-   u16 ext_jedec;
+
+   /*
+* This array stores the ID bytes.
+* The first three bytes are the JEDIC ID.
+* JEDEC ID zero means "no ID" (mostly older chips).
+*/
+   u8  id[5];
+   u8  id_len;
+
u32 sector_size;
u32 nr_sectors;
 
+   u16 page_size;
+
u16 flags;
 #define SECT_4KBIT(0)
 #define E_FSR  BIT(1)
@@ -133,7 +145,7 @@ struct spi_flash_params {
 #define RD_FULL(RD_QUAD | RD_DUAL | RD_QUADIO | 
RD_DUALIO)
 };
 
-extern const struct spi_flash_params spi_flash_params_table[];
+extern const struct 

[U-Boot] [PATCH v5 00/21] sf: Updates on flash detection

[Jagan Teki]

Updated spi_flash_info table in sync with Linux, and removed
legacy and unsupported code.

Changes for v5:
- Add dataflash fixes in this series
- Rebase to master

Changes for v4:
- Rebase to master

Changes for v3:
- New patches
- Fix checkpatch.pl
- Fix BIT positions in spi.h
- Fix ti_qspi.c mode
- Fix commit Nit: s/becuase/because

Changes for v2:
- New patches.

Testing:
$ git clone git://git.denx.de/u-boot-spi.git
$ cd u-boot-spi
$ git checkout -b next origin/next

Jagan Teki (21):
  sf: Adopt flash table INFO macro from Linux
  sf: Simplify lock ops detection code
  sf: sandbox: Use JEDEC_MFR|ID in id exctract
  sf: Cleanup spi_flash_info{}
  sf: Cleanup sf_params
  sf: nr_sectors -> n_sectors
  sf: Add SPI_FLASH_MAX_ID_LEN
  sf: Increase max id length by 1 byte
  sf: Add INFO6 flash_info macro
  sf: params: Add S25FS256S_64K spi flash support
  sf: Remove legacy idcode detection code
  sf: Remove non-meaningful comments
  sf: Rename sf_params.c to spi_flash_ids
  sf: ids: Use small letter's with flash name
  sf: ids: Use small letter in ext_jedec
  sf: Rename few local functions
  spi: Remove dual flash code
  sf: dataflash: Remove unneeded spi data
  sf: dataflash: Move flash id detection into jedec_probe
  sf: dataflash: Fix add_dataflash return logic
  sf: dataflash: Minor cleanups

 drivers/mtd/spi/Makefile|   2 +-
 drivers/mtd/spi/sandbox.c   |  11 +-
 drivers/mtd/spi/sf.c|   4 -
 drivers/mtd/spi/sf_dataflash.c  | 178 ++
 drivers/mtd/spi/sf_internal.h   |  58 +-
 drivers/mtd/spi/sf_params.c | 238 ++--
 drivers/mtd/spi/spi_flash.c | 226 --
 drivers/mtd/spi/spi_flash_ids.c | 176 +
 include/linux/err.h |   5 +
 include/spi.h   |   6 -
 10 files changed, 500 insertions(+), 404 deletions(-)
 create mode 100644 drivers/mtd/spi/spi_flash_ids.c

-- 
2.7.4

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[U-Boot] [PATCH 3/3] mx6: ddr: add routine to return DDR calibration data

[Eric Nelson]

Add routine mmdc_read_calibration() to return the output of DDR
calibration. This can be used for debugging or to aid in construction
of static memory configuration.

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/ddr.c| 23 +++
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  2 ++
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 274a0ba..b12fb64 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1501,6 +1501,29 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
mdelay(1);
 }
 
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+   struct mx6_mmdc_calibration *calib)
+{
+   struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+   struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+   calib->p0_mpwldectrl0 = readl(>mpwldectrl0);
+   calib->p0_mpwldectrl1 = readl(>mpwldectrl1);
+   calib->p0_mpdgctrl0 = readl(>mpdgctrl0);
+   calib->p0_mpdgctrl1 = readl(>mpdgctrl1);
+   calib->p0_mprddlctl = readl(>mprddlctl);
+   calib->p0_mpwrdlctl = readl(>mpwrdlctl);
+
+   if (sysinfo->dsize == 2) {
+   calib->p1_mpwldectrl0 = readl(>mpwldectrl0);
+   calib->p1_mpwldectrl1 = readl(>mpwldectrl1);
+   calib->p1_mpdgctrl0 = readl(>mpdgctrl0);
+   calib->p1_mpdgctrl1 = readl(>mpdgctrl1);
+   calib->p1_mprddlctl = readl(>mprddlctl);
+   calib->p1_mpwrdlctl = readl(>mpwrdlctl);
+   }
+}
+
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
  const struct mx6_mmdc_calibration *calib,
  const void *ddr_cfg)
diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h 
b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index cd5bc97..12454fa 100644
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -461,6 +461,8 @@ void mx6sl_dram_iocfg(unsigned width,
 #if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
 int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
 int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+   struct mx6_mmdc_calibration *calib);
 #endif
 
 /* configure mx6 mmdc registers */
-- 
2.7.4

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[U-Boot] [PATCH 0/3] mx6: ddr: updates for dynamic DDR calibration

[Eric Nelson]

This set of patches updates the interface to the DDR calibration in 
preparation for the addition of a pseudo-board for calibration on
i.MX6.

The first patch fixes an ommission in the use of the DG_CMP_CYC flag
in register MPDGCTRL0.

The second patch cleans up the handling of bus widths by passing
the system configuration information to the calibration routines.

The third routine adds support for returning the calibration data
written to the MMDC registers.

Eric Nelson (3):
  mx6: ddr: allow 32 cycles for DQS gating calibration
  mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
  mx6: ddr: add mmdc_read_calibration routine to return dynamic data

 arch/arm/cpu/armv7/mx6/ddr.c| 128 +---
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |   6 +-
 board/kosagi/novena/novena_spl.c|   4 +-
 3 files changed, 92 insertions(+), 46 deletions(-)

-- 
2.7.4

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[U-Boot] [PATCH 1/3] mx6: ddr: allow 32 cycles for DQS gating calibration

[Eric Nelson]

The DDR calibration code is only setting flag DG_CMP_CYC (DQS gating sample
cycle) for the first PHY.

Set the 32-cycle flag for both PHYs and clear when done so the MPDGCTRL0
output value isn't polluted with calibration artifacts.

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/ddr.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7beb7ea..b15f376 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -347,6 +347,8 @@ int mmdc_do_dqs_calibration(void)
 * 16 before comparing read data.
 */
setbits_le32(>mpdgctrl0, 1 << 30);
+   if (sysinfo->dsize == 2)
+   setbits_le32(>mpdgctrl0, 1 << 30);
 
/* Set bit 28 to start automatic read DQS gating calibration */
setbits_le32(>mpdgctrl0, 5 << 28);
@@ -365,6 +367,11 @@ int mmdc_do_dqs_calibration(void)
if ((bus_size == 0x2) && (readl(>mpdgctrl0) & 0x1000))
errors |= 2;
 
+   /* now disable mpdgctrl0[DG_CMP_CYC] */
+   clrbits_le32(>mpdgctrl0, 1 << 30);
+   if (sysinfo->dsize == 2)
+   clrbits_le32(>mpdgctrl0, 1 << 30);
+
/*
 * DQS gating absolute offset should be modified from
 * reflecting (HW_DG_LOWx + HW_DG_UPx)/2 to
-- 
2.7.4

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[U-Boot] [PATCH 2/3] mx6: ddr: pass mx6_ddr_sysinfo to calibration routines

[Eric Nelson]

The DDR calibration routines have scattered support for bus
widths other than 64-bits:

-- The mmdc_do_write_level_calibration() routine assumes the
presence of PHY1, and
-- The mmdc_do_dqs_calibration() routine tries to determine
whether one or two DDR PHYs are active by reading MDCTL.

Since a caller of these routines must have a valid struct mx6_ddr_sysinfo
for use in calling mx6_dram_cfg(), and the bus width is available in the
"dsize" field, use this structure to inform the calibration routines which
PHYs are active.

This allows the use of the DDR calibration routines on CPU variants
like i.MX6SL that only have a single MMDC port.

Signed-off-by: Eric Nelson 
---
 arch/arm/cpu/armv7/mx6/ddr.c| 98 +++--
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |  4 +-
 board/kosagi/novena/novena_spl.c|  4 +-
 3 files changed, 60 insertions(+), 46 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index b15f376..274a0ba 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -86,14 +86,15 @@ static void modify_dg_result(u32 *reg_st0, u32 *reg_st1, 
u32 *reg_ctrl)
writel(val_ctrl, reg_ctrl);
 }
 
-int mmdc_do_write_level_calibration(void)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
 {
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
u32 esdmisc_val, zq_val;
u32 errors = 0;
-   u32 ldectrl[4];
+   u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
+   u32 rwalat_max;
 
/*
 * Stash old values in case calibration fails,
@@ -101,8 +102,10 @@ int mmdc_do_write_level_calibration(void)
 */
ldectrl[0] = readl(>mpwldectrl0);
ldectrl[1] = readl(>mpwldectrl1);
-   ldectrl[2] = readl(>mpwldectrl0);
-   ldectrl[3] = readl(>mpwldectrl1);
+   if (sysinfo->dsize == 2) {
+   ldectrl[2] = readl(>mpwldectrl0);
+   ldectrl[3] = readl(>mpwldectrl1);
+   }
 
/* disable DDR logic power down timer */
clrbits_le32(>mdpdc, 0xff00);
@@ -122,10 +125,10 @@ int mmdc_do_write_level_calibration(void)
writel(zq_val & ~0x3, >mpzqhwctrl);
 
/* 3. increase walat and ralat to maximum */
-   setbits_le32(>mdmisc,
-(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
-   setbits_le32(>mdmisc,
-(1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17));
+   rwalat_max = (1 << 6) | (1 << 7) | (1 << 8) | (1 << 16) | (1 << 17);
+   setbits_le32(>mdmisc, rwalat_max);
+   if (sysinfo->dsize == 2)
+   setbits_le32(>mdmisc, rwalat_max);
/*
 * 4 & 5. Configure the external DDR device to enter write-leveling
 * mode through Load Mode Register command.
@@ -152,21 +155,25 @@ int mmdc_do_write_level_calibration(void)
 */
if (readl(>mpwlgcr) & 0x0F00)
errors |= 1;
-   if (readl(>mpwlgcr) & 0x0F00)
-   errors |= 2;
+   if (sysinfo->dsize == 2)
+   if (readl(>mpwlgcr) & 0x0F00)
+   errors |= 2;
 
debug("Ending write leveling calibration. Error mask: 0x%x\n", errors);
 
/* check to see if cal failed */
if ((readl(>mpwldectrl0) == 0x001F001F) &&
(readl(>mpwldectrl1) == 0x001F001F) &&
-   (readl(>mpwldectrl0) == 0x001F001F) &&
-   (readl(>mpwldectrl1) == 0x001F001F)) {
+   ((sysinfo->dsize < 2) ||
+((readl(>mpwldectrl0) == 0x001F001F) &&
+ (readl(>mpwldectrl1) == 0x001F001F {
debug("Cal seems to have soft-failed due to memory not 
supporting write leveling on all channels. Restoring original write leveling 
values.\n");
writel(ldectrl[0], >mpwldectrl0);
writel(ldectrl[1], >mpwldectrl1);
-   writel(ldectrl[2], >mpwldectrl0);
-   writel(ldectrl[3], >mpwldectrl1);
+   if (sysinfo->dsize == 2) {
+   writel(ldectrl[2], >mpwldectrl0);
+   writel(ldectrl[3], >mpwldectrl1);
+   }
errors |= 4;
}
 
@@ -189,16 +196,20 @@ int mmdc_do_write_level_calibration(void)
  readl(>mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
  readl(>mpwldectrl1));
-   debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
- readl(>mpwldectrl0));
-   debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
- readl(>mpwldectrl1));
+   if (sysinfo->dsize == 2) {
+   debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08X\n",
+ readl(>mpwldectrl0));
+   debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08X\n",
+ 

[U-Boot] [PATCH] README: fix typo candiate -> candidate

[Jelle van der Waa]

Signed-off-by: Jelle van der Waa 
---
 README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README b/README
index 39a3042..7d6d4a5 100644
--- a/README
+++ b/README
@@ -127,7 +127,7 @@ releases in "stable" maintenance trees.
 Examples:
U-Boot v2009.11 - Release November 2009
U-Boot v2009.11.1   - Release 1 in version November 2009 stable tree
-   U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release
+   U-Boot v2010.09-rc1 - Release candidate 1 for September 2010 release
 
 
 Directory Hierarchy:
-- 
2.10.1

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Re: [U-Boot] [PATCH v2 0/9] MIPS: improve start.S and add exception support

[Daniel Schwierzeck]

Am 03.10.2016 um 19:51 schrieb Daniel Schwierzeck:
> Fix and optinmize initialization of cp0 registers. Also add
> the possibilty to setup the initial stack and global data in
> SRAM to provide a C environment for lowlevel_init(). This
> could be used on the QCA ath79 platform to rewrite and
> optimize the low-level init code.
> 
> Add support for a dynamic exception vectors in RAM and add
> initial exception handlers. The general exception handler
> prints an oops message similar to Linux kernel and then hangs.
> The EJTAG exception handler checks for SDBBP and delegates to
> the SDBBP handler if necessary. Otherwise the debug mode
> will be simply exited. The SDBBP handler currently only
> prints the content of registers c0_depc and c0_debug. This
> could be extended in the future to handle semi-hosting
> according to the MIPS UHI specification.
> 
> This patch series is also available at:
> git://git.denx.de/u-boot-mips.git mips_rework_start_v2
> 
> Changes in v2:
> - invoke UHI exception operation for all exception vectors but
>   the EJTAG debug exception
> - use EHB after setting cp0 status
> - reordered macros in genex.S to allow side-by-side diff with Linux's
>   arch/mips/include/asm/stackframe.h
> - sync'ed genex.S with Linux v4.8-rc8 to incorporate changes for
>   MIPS r6
> - add execution_hazard_barrier() after clearing c0 status.BEV
> 
> Daniel Schwierzeck (9):
>   MIPS: make inclusion of ROM exception vectors configurable
>   MIPS: fix ROM exception vectors
>   MIPS: fix iand optimize setup of CP0 registers
>   MIPS: factor out code for initial stack and global data
>   MIPS: add possibility to setup initial stack and global data in SRAM
>   MIPS: add asm-offsets for struct pt_regs
>   MIPS: reserve space for exception vectors
>   MIPS: add handling for generic and EJTAG exceptions
>   common/board_f: enable initr_trap for MIPS
> 
>  arch/mips/Kconfig   |  32 ++
>  arch/mips/cpu/start.S   | 174 ++--
>  arch/mips/include/asm/asm-offsets.h |   5 +
>  arch/mips/include/asm/mipsregs.h|   1 +
>  arch/mips/include/asm/system.h  |   8 ++
>  arch/mips/include/asm/u-boot-mips.h |   4 +
>  arch/mips/lib/Makefile  |   3 +
>  arch/mips/lib/asm-offsets.c |  61 ++
>  arch/mips/lib/genex.S   | 224 
> 
>  arch/mips/lib/stack.c   |  19 +++
>  arch/mips/lib/traps.c   | 106 +
>  arch/mips/mach-ath79/Kconfig|   2 +
>  arch/mips/mach-pic32/Kconfig|   1 +
>  common/board_r.c|   4 +-
>  14 files changed, 581 insertions(+), 63 deletions(-)
>  create mode 100644 arch/mips/include/asm/asm-offsets.h
>  create mode 100644 arch/mips/lib/asm-offsets.c
>  create mode 100644 arch/mips/lib/genex.S
>  create mode 100644 arch/mips/lib/stack.c
>  create mode 100644 arch/mips/lib/traps.c
> 

applied to u-boot-mips/next

-- 
- Daniel



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Re: [U-Boot] [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

[Marek Vasut]

On 10/30/2016 10:51 AM, André Przywara wrote:
> On 29/10/16 18:42, Marek Vasut wrote:
>> On 10/29/2016 02:50 PM, Hans de Goede wrote:
>>> Hi,
>>>
>>> On 21-10-16 03:24, Andre Przywara wrote:
 OHCI has a known limitation of allowing only 32-bit DMA buffer
 addresses, so we have a lot of u32 variables around, which are assigned
 to pointers and vice versa. This obviously creates issues with 64-bit
 systems, so the compiler complains here and there.
 To allow compilation for 64-bit boards which use only memory below 4GB
 anyway (and to avoid more invasive fixes), adjust some casts and types
 and assume that the EDs and TDs are all located in the lower 4GB.
 This fixes compilation of the OHCI driver for the Pine64.

 Signed-off-by: Andre Przywara 
>>>
>>> Patch looks good to me:
>>>
>>> Reviewed-by: Hans de Goede 
>>
>> Applied, thanks.
>>
>> Andre, it would be nice if you CC'd me on the original submission.
> 
> Yeah, sorry about that. I think I had you in To: on my --dry-run test,
> but somehow managed to drop you after fixing "just one more thing".
> 
> Thanks for applying this!

np, PR is out too.

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Re: [U-Boot] [PATCH] arm: dts: Pine64: add Ethernet alias

[Jagan Teki]

On Sun, Oct 30, 2016 at 3:16 PM, André Przywara  wrote:
> On 30/10/16 08:48, Jagan Teki wrote:
>> On Fri, Oct 28, 2016 at 11:21 PM, Jagan Teki  wrote:
>>> On Thu, Oct 27, 2016 at 2:20 AM, André Przywara  
>>> wrote:
 On 26/10/16 19:51, Jagan Teki wrote:
 Hi,

> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara  
> wrote:
>> The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
>> missing an alias entry to trigger the driver instantiation by U-Boot.
>> Add the line to point U-Boot to the Ethernet DT node.
>> This enables TFTP boot on the Pine64.
>>
>> Signed-off-by: Andre Przywara 
>> ---
>>  arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
>> b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>> index d5a7249..c0fde44 100644
>> --- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>> +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
>> @@ -46,6 +46,7 @@
>>
>> aliases {
>> serial0 = 
>> +   ethernet0 = 
>
> Better to have this alias on sun50i-a64.dtsi since the node is defined 
> there?

 Mmh, I find examples for both ways (.dtsi vs. .dts) in the kernel. I
 need to learn what's the best practice here.

 But the U-Boot DTs need to get replaced anyway soon-ish, since the Linux
 DTs (which are WIP) have already diverged.
 So what about we keep this alias here next to the existing one for the
 2016.11 release and possibly fix this later once we replace the DTs
 anyway with what gets merged into the kernel eventually?
>>>
>>> OK, but please stick with the current discussion and still I see a
>>> good point to see alias on dtsi because the dts files which are using
>>> this dtsi shouldn't separately define the alias.
>>>
>>> And also status on dtsi is showing "disabled" are you enabled it some
>>> other patches? or missed?
>
> We have the status = "okay" in sun50i-a64-pine64-plus.dts, which is the
> only dts that is used these days.
> The non-plus board version has a different PHY (100 MBit only) and a
> quick test a while ago showed that this didn't work out of the box, so
> we just don't enable it there. It seems like that not many people have
> this version of the board and they would need to hack U-Boot to use it
> anyway (because defconfig select -plus.dts).
> This will be revisited when the SPL FIT support introduces board
> detection and we actually choose the proper DT for each board.

OK.

Reviewed-by: Jagan Teki 

thanks!
-- 
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Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] pull request: u-boot-uniphier/master

[Tom Rini]

On Sat, Oct 29, 2016 at 05:29:12PM +0900, Masahiro Yamada wrote:

> Hi Tom,
> 
> Please pull some more UniPhier SoC updates:
>   - DRAM init code updates
>   - Misc SoC-related fixes
> 
> 
> The following changes since commit 1df182ddf700de49fb4400ba67c3029278ea88e7:
> 
>   Merge branch 'master' of git://git.denx.de/u-boot-atmel (2016-10-28
> 14:14:18 -0400)
> 
> are available in the git repository at:
> 
> 
>   git://git.denx.de/u-boot-uniphier.git master
> 
> for you to fetch changes up to 6eeb624148c1aaedd1cf4f89286c7719bb140fd0:
> 
>   ARM: uniphier: update DRAM init code for LD11 SoC (2016-10-29 17:24:30 
> +0900)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PULL] u-boot-socfpga/master

[Tom Rini]

On Sat, Oct 29, 2016 at 08:01:50PM +0200, Marek Vasut wrote:

> The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d:
> 
>   travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29
> -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-socfpga.git master
> 
> for you to fetch changes up to 4f9378cf67c657c8de20284ed1be8be38a6e47bc:
> 
> 
>   dm: mmc: socfpga: fix MMC_OPS support (2016-10-28 04:21:21 +0200)
> 
> 
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PULL] u-boot-usb/master

[Tom Rini]

On Sat, Oct 29, 2016 at 08:00:57PM +0200, Marek Vasut wrote:

> The following changes since commit 5ac5861c4ba851b473e6a24940b412b397627d8d:
> 
>   travis-ci: Add test.py for various qemu platforms (2016-10-24 08:06:29
> -0400)
> 
> are available in the git repository at:
> 
>   git://git.denx.de/u-boot-usb.git master
> 
> for you to fetch changes up to 57faca19a82fc9b43a227824c30aeb76a43d1957:
> 
>   drivers: USB: OHCI: allow compilation for 64-bit targets (2016-10-29
> 19:45:40 +0200)
> 

Applied to u-boot/master, thanks!

-- 
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Re: [U-Boot] [PATCH v2 2/2] arm: Set TTB XN bit in case DCACHE_OFF for LPAE mode

[Marek Vasut]

On 10/30/2016 02:59 AM, Keerthy wrote:
> 
> 
> On Saturday 29 October 2016 11:19 PM, Marek Vasut wrote:
>> On 10/29/2016 07:47 PM, Tom Rini wrote:
>>> On Sat, Oct 29, 2016 at 07:44:34PM +0200, Marek Vasut wrote:
 On 10/29/2016 07:41 PM, Tom Rini wrote:
> On Sat, Oct 29, 2016 at 03:19:10PM +0530, Keerthy wrote:
>
>> While we setup the mmu initially we mark set_section_dcache with
>> DCACHE_OFF flag. In case of non-LPAE mode the DCACHE_OFF macro
>> is rightly defined with TTB_SECT_XN_MASK set so as to mark all the
>> 4GB XN. In case of LPAE mode  XN(Execute-never) bit is not set with
>> DCACHE_OFF. Hence XN bit is not set by default for DCACHE_OFF which
>> keeps all the regions execute okay and this leads to random
>> speculative
>> fetches in random memory regions which was eventually caught by
>> kernel
>> omap-l3-noc driver.
>>
>> Fix this to mark the regions as XN by default.
>>
>> Signed-off-by: Keerthy 
>> Reviewed-by: Alexander Graf 
>
> Reviewed-by: Tom Rini 
>
 Isn't this patch exactly undoing the following one ?

 commit 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
 Author: Marek Vasut <>
 Date:   Tue Dec 29 19:44:02 2015 +0100

 arm: Remove S bit from MMU section entry

 Restore the old behavior of the MMU section entries configuration,
 which is without the S-bit.
>>>
>>> Is it?  I guess perhaps you and Keerthy need to chat then as there's
>>> some other problem they're addressing.
>>
>> U, wait a second, I think this one adds XN bit and the previous one
>> removed S bit. I think I was wrong, but please double-check this. I
>> recall we had some odd cache issues on V7 back then.
> 
> Marek,
> 
> First and foremost if we git blame on the file:
> arch/arm/include/asm/system.h
> 
> your commit:
> 8890c2fbe6ed4c5ca9a61f21e846a55f8f2c38fc
> 
> arm: Remove S bit from MMU section entry
> 
> It is removing S bit under
> #elif defined(CONFIG_CPU_V7)
> 
> I am adding the missing XN bit under:
> #ifdef CONFIG_ARMV7_LPAE
> 
> So we are dealing with different modes.
> 
> In a nutshell your patch removes S bit from MMU section entry for
> non-LPAE cases for ARMV7 and mine adds XN bit for LPAE cases.
> 
> Hope this clears out the confusion.

Yeah, it does, thanks.

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[U-Boot] Please pull u-boot-sunxi sun9i-a80-spl

[Hans de Goede]

Hi Tom,

Here is another sunxi pull-req, this one is to be applied on top of the
bug-fix one I send out a few seconds ago. I'm sending this one as
a separate pull-req since it contains non-bugfix changes which were
first submitted outside the merge window.

The entire set of patches in this pull-req enables DRAM controller init
and SPL for the Allwinner A80 SoC. These changes are isolated to the A80
SoC and should not impact other (sunxi) SoCs. Without SPL u-boot was never
really usable on the A80 SoC, so in a sense this is a bug-fix pull-req,
as it makes u-boot fully functional on the A80 for the first time.

Anyways I've deliberately put this in a separate pull-req to make it
easy for you to nack this one as being too late in the cycle, and I'm
fine with keeping these in my tree until the next merge-window opens.

I assume it is clear that my preference (and judgement call on this
being safe) is to get these into v2016.11, otherwise I would not have
send the pull-req.

The following changes since commit fed329aebe3aaac0928c73547ac6316af2adf0cd:

  tools: add mksunxiboot to tools-all target (2016-10-30 11:38:04 +0100)

are available in the git repository at:

  http://git.denx.de/u-boot-sunxi.git sun9i-a80-spl

for you to fetch changes up to fda9d5d327302e2e5a45ade25e88edc0002336ec:

  sunxi: Add support for Cubieboard4 (2016-10-30 11:38:05 +0100)


Chen-Yu Tsai (5):
  sunxi: Set default CPU clock rate to 1008 MHz for sun9i (A80)
  sunxi: Add support for SID e-fuses on sun9i
  sunxi: Add default zq value for sun9i (A80)
  sunxi: Enable SPL support for A80 Optimus board
  sunxi: Add support for Cubieboard4

Philipp Tomsich (6):
  sunxi: DRAM initialisation for sun9i
  sunxi: add gtbus-initialisation for sun9i
  sunxi: Enable SMP mode for the boot CPU on sun9i (A80)
  sunxi: add initial clock setup for sun9i for SPL
  sunxi: enable SPL for sun9i
  sunxi: add MMC pinmux setup for SDC2 on sun9i

 arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 116 +++-
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h   |  10 +
 arch/arm/include/asm/arch-sunxi/dram.h|   2 +
 arch/arm/include/asm/arch-sunxi/dram_sun9i.h  | 278 
 arch/arm/include/asm/arch-sunxi/gtbus.h   |  21 +
 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h |  92 +++
 arch/arm/mach-sunxi/Makefile  |   3 +-
 arch/arm/mach-sunxi/board.c   |   3 +-
 arch/arm/mach-sunxi/clock.c   |   6 +
 arch/arm/mach-sunxi/clock_sun9i.c | 146 +++-
 arch/arm/mach-sunxi/dram_sun9i.c  | 961 ++
 arch/arm/mach-sunxi/gtbus_sun9i.c |  48 ++
 board/sunxi/Kconfig   |  10 +-
 board/sunxi/MAINTAINERS   |  10 +
 board/sunxi/board.c   |   7 +
 configs/Cubieboard4_defconfig |  18 +
 configs/Merrii_A80_Optimus_defconfig  |  15 +-
 17 files changed, 1718 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun9i.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus.h
 create mode 100644 arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h
 create mode 100644 arch/arm/mach-sunxi/dram_sun9i.c
 create mode 100644 arch/arm/mach-sunxi/gtbus_sun9i.c
 create mode 100644 configs/Cubieboard4_defconfig

Regards,

Hans

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[U-Boot] Please pull u-boot-sunxi master

[Hans de Goede]

Hi Tom,

Here is a pull request with some small sunxi cleanups / fixes
for v2016.11.

Note I expect you to merge this after Marek's usb pull-req. If you don't
nothing will break, but you will get a whole bunch of new compiler warnings
when building the pine64_plus defconfig.

The following changes since commit 4d6afd69babafbf6580cb04dacd9479df03a5de0:

  configs/chromebox_panther_defconfig: Re-enable CONFIG_DM_PCI (2016-10-29 
09:00:01 -0400)

are available in the git repository at:

  http://git.denx.de/u-boot-sunxi.git master

for you to fetch changes up to fed329aebe3aaac0928c73547ac6316af2adf0cd:

  tools: add mksunxiboot to tools-all target (2016-10-30 11:38:04 +0100)


Amit Singh Tomar (1):
  sunxi: A64: enable USB support

Andre Przywara (1):
  sunxi: dts: Pine64: add Ethernet alias

Jagan Teki (1):
  sunxi: Rename CONFIG_SUNXI to CONFIG_ARCH_SUNXI

Masahiro Yamada (1):
  sunxi: remove unneeded CONFIG_USB_MAX_CONTROLLER_COUNT defines

Stefan Brüns (1):
  tools: add mksunxiboot to tools-all target

Stefan Mavrodiev (1):
  sunxi: Update DRAM clock for Olimex A20 boards

 Makefile|  2 +-
 arch/arm/cpu/armv7/Makefile |  2 +-
 arch/arm/dts/sun50i-a64-pine64-common.dtsi  | 13 +
 arch/arm/dts/sun50i-a64.dtsi| 29 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
 arch/arm/mach-sunxi/usb_phy.c   |  5 +++--
 configs/A20-Olimex-SOM-EVB_defconfig|  2 +-
 configs/pine64_plus_defconfig   |  1 +
 drivers/i2c/mvtwsi.c|  6 +++---
 drivers/usb/host/ehci-sunxi.c   |  7 ---
 drivers/usb/host/ohci-sunxi.c   |  1 +
 include/configs/sun4i.h |  1 -
 include/configs/sun50i.h|  5 +
 include/configs/sun5i.h |  1 -
 include/configs/sun6i.h |  1 -
 include/configs/sun7i.h |  1 -
 include/configs/sun8i.h |  1 -
 include/configs/sunxi-common.h  |  1 -
 scripts/Makefile.spl|  2 +-
 scripts/config_whitelist.txt|  1 -
 tools/Makefile  |  3 ++-
 tools/mksunxiboot.c |  2 +-
 22 files changed, 67 insertions(+), 22 deletions(-)

Regards,

Hans

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Re: [U-Boot] [linux-sunxi] Re: [U-Boot, 2/2] sunxi: A64: enable USB support

[Hans de Goede]

Hi,

On 29-10-16 14:52, Hans de Goede wrote:

Hi,

On 21-10-16 03:24, Andre Przywara wrote:

From: Amit Singh Tomar 

Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on the Pine64.
This is limited to the first USB controller at the moment, which is
connected to the lower USB socket on the Pine64 board.
[Andre: remove unneeded defines, enable OHCI, add commit message]

Signed-off-by: Amit Singh Tomar 
Signed-off-by: Andre Przywara 


Other then CONFIG_USB_MAX_CONTROLLER_COUNT no longer being necessary
(it should be dropped from include/configs/sun50i.h) this patch looks
good to me and is:

Reviewed-by: Hans de Goede 

Note I cannot merged it till Marek merges the first patch in
the series, which really needs to go through the u-boot-usb tree.


Marek just send out a pull-req with this patch in there so I've
added this patch to my tree and will include it in the pull-req I
will send out later today.

Regards,

Hans


---
 arch/arm/dts/sun50i-a64-pine64-common.dtsi  | 12 
 arch/arm/dts/sun50i-a64.dtsi| 29 +
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  2 +-
 arch/arm/mach-sunxi/usb_phy.c   |  5 +++--
 configs/pine64_plus_defconfig   |  1 +
 drivers/usb/host/ehci-sunxi.c   |  7 ---
 drivers/usb/host/ohci-sunxi.c   |  1 +
 include/configs/sun50i.h|  5 +
 8 files changed, 56 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
index c0fde44..9ec81c6 100644
--- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
+++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
@@ -79,3 +79,15 @@
 pinctrl-0 = <_pins>;
 status = "okay";
 };
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64.dtsi b/arch/arm/dts/sun50i-a64.dtsi
index 7d0dc76..bef0d00 100644
--- a/arch/arm/dts/sun50i-a64.dtsi
+++ b/arch/arm/dts/sun50i-a64.dtsi
@@ -653,5 +653,34 @@
 #address-cells = <1>;
 #size-cells = <0>;
 };
+
+usbphy: phy@1c1b810 {
+compatible = "allwinner,sun50i-a64-usb-phy",
+ "allwinner,sun8i-a33-usb-phy";
+reg = <0x01c1b810 0x14>, <0x01c1b800 0x4>;
+reg-names = "phy_ctrl", "pmu1";
+status = "disabled";
+#phy-cells = <1>;
+};
+
+ehci1: usb@01c1b000 {
+compatible = "allwinner,sun50i-a64-ehci",
+ "generic-ehci";
+reg = <0x01c1b000 0x100>;
+interrupts = ;
+phys = < 1>;
+phy-names = "usb";
+status = "disabled";
+};
+
+ohci1: usb@01c1b400 {
+compatible = "allwinner,sun50i-a64-ohci",
+ "generic-ohci";
+reg = <0x01c1b400 0x100>;
+interrupts = ;
+phys = < 1>;
+phy-names = "usb";
+status = "enabled";
+};
 };
 };
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h 
b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index 5f93830..7232f6d 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -56,7 +56,7 @@
 #define SUNXI_USB2_BASE0x01c1c000
 #endif
 #ifdef CONFIG_SUNXI_GEN_SUN6I
-#ifdef CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 #define SUNXI_USBPHY_BASE0x01c19000
 #define SUNXI_USB0_BASE0x01c1a000
 #define SUNXI_USB1_BASE0x01c1b000
diff --git a/arch/arm/mach-sunxi/usb_phy.c b/arch/arm/mach-sunxi/usb_phy.c
index bd1bbee..278587b 100644
--- a/arch/arm/mach-sunxi/usb_phy.c
+++ b/arch/arm/mach-sunxi/usb_phy.c
@@ -146,12 +146,13 @@ __maybe_unused static void usb_phy_write(struct 
sunxi_usb_phy *phy, int addr,
 }
 }

-#if defined CONFIG_MACH_SUN8I_H3
+#if defined(CONFIG_MACH_SUN8I_H3) || defined(CONFIG_MACH_SUN50I)
 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
 {
+#if defined CONFIG_MACH_SUN8I_H3
 if (phy->id == 0)
 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
-
+#endif
 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
 }
 #elif defined CONFIG_MACH_SUN8I_A83T
diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig
index 6f82190..bd3e2e6 100644
--- a/configs/pine64_plus_defconfig
+++ b/configs/pine64_plus_defconfig
@@ -10,3 +10,4 @@ CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pine64-plus"
 # CONFIG_CMD_FLASH is not set
 # CONFIG_CMD_FPGA is not set
 CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
diff --git a/drivers/usb/host/ehci-sunxi.c 

Re: [U-Boot] [U-Boot, 1/2] drivers: USB: OHCI: allow compilation for 64-bit targets

[André Przywara]

On 29/10/16 18:42, Marek Vasut wrote:
> On 10/29/2016 02:50 PM, Hans de Goede wrote:
>> Hi,
>>
>> On 21-10-16 03:24, Andre Przywara wrote:
>>> OHCI has a known limitation of allowing only 32-bit DMA buffer
>>> addresses, so we have a lot of u32 variables around, which are assigned
>>> to pointers and vice versa. This obviously creates issues with 64-bit
>>> systems, so the compiler complains here and there.
>>> To allow compilation for 64-bit boards which use only memory below 4GB
>>> anyway (and to avoid more invasive fixes), adjust some casts and types
>>> and assume that the EDs and TDs are all located in the lower 4GB.
>>> This fixes compilation of the OHCI driver for the Pine64.
>>>
>>> Signed-off-by: Andre Przywara 
>>
>> Patch looks good to me:
>>
>> Reviewed-by: Hans de Goede 
> 
> Applied, thanks.
> 
> Andre, it would be nice if you CC'd me on the original submission.

Yeah, sorry about that. I think I had you in To: on my --dry-run test,
but somehow managed to drop you after fixing "just one more thing".

Thanks for applying this!

Cheers,
Andre.

> 
>> Regards,
>>
>> Hans
>>
>> p.s.
>>
>> About the ohci_writel macro changes also giving the macro parameters
>> more sensible names, I believe it is fine to do this while at it and
>> that this does not need to be split out.
> 
> Indeed, I am fine with it as well.
> 

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Re: [U-Boot] [PATCH] arm: dts: Pine64: add Ethernet alias

[André Przywara]

On 30/10/16 08:48, Jagan Teki wrote:
> On Fri, Oct 28, 2016 at 11:21 PM, Jagan Teki  wrote:
>> On Thu, Oct 27, 2016 at 2:20 AM, André Przywara  
>> wrote:
>>> On 26/10/16 19:51, Jagan Teki wrote:
>>> Hi,
>>>
 On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara  
 wrote:
> The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
> missing an alias entry to trigger the driver instantiation by U-Boot.
> Add the line to point U-Boot to the Ethernet DT node.
> This enables TFTP boot on the Pine64.
>
> Signed-off-by: Andre Przywara 
> ---
>  arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
> b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
> index d5a7249..c0fde44 100644
> --- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
> +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
> @@ -46,6 +46,7 @@
>
> aliases {
> serial0 = 
> +   ethernet0 = 

 Better to have this alias on sun50i-a64.dtsi since the node is defined 
 there?
>>>
>>> Mmh, I find examples for both ways (.dtsi vs. .dts) in the kernel. I
>>> need to learn what's the best practice here.
>>>
>>> But the U-Boot DTs need to get replaced anyway soon-ish, since the Linux
>>> DTs (which are WIP) have already diverged.
>>> So what about we keep this alias here next to the existing one for the
>>> 2016.11 release and possibly fix this later once we replace the DTs
>>> anyway with what gets merged into the kernel eventually?
>>
>> OK, but please stick with the current discussion and still I see a
>> good point to see alias on dtsi because the dts files which are using
>> this dtsi shouldn't separately define the alias.
>>
>> And also status on dtsi is showing "disabled" are you enabled it some
>> other patches? or missed?

We have the status = "okay" in sun50i-a64-pine64-plus.dts, which is the
only dts that is used these days.
The non-plus board version has a different PHY (100 MBit only) and a
quick test a while ago showed that this didn't work out of the box, so
we just don't enable it there. It seems like that not many people have
this version of the board and they would need to hack U-Boot to use it
anyway (because defconfig select -plus.dts).
This will be revisited when the SPL FIT support introduces board
detection and we actually choose the proper DT for each board.

Cheers,
Andre.

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Re: [U-Boot] [PATCH] arm: dts: Pine64: add Ethernet alias

[Jagan Teki]

On Fri, Oct 28, 2016 at 11:21 PM, Jagan Teki  wrote:
> On Thu, Oct 27, 2016 at 2:20 AM, André Przywara  
> wrote:
>> On 26/10/16 19:51, Jagan Teki wrote:
>> Hi,
>>
>>> On Fri, Oct 21, 2016 at 5:41 AM, Andre Przywara  
>>> wrote:
 The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
 missing an alias entry to trigger the driver instantiation by U-Boot.
 Add the line to point U-Boot to the Ethernet DT node.
 This enables TFTP boot on the Pine64.

 Signed-off-by: Andre Przywara 
 ---
  arch/arm/dts/sun50i-a64-pine64-common.dtsi | 1 +
  1 file changed, 1 insertion(+)

 diff --git a/arch/arm/dts/sun50i-a64-pine64-common.dtsi 
 b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 index d5a7249..c0fde44 100644
 --- a/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 +++ b/arch/arm/dts/sun50i-a64-pine64-common.dtsi
 @@ -46,6 +46,7 @@

 aliases {
 serial0 = 
 +   ethernet0 = 
>>>
>>> Better to have this alias on sun50i-a64.dtsi since the node is defined 
>>> there?
>>
>> Mmh, I find examples for both ways (.dtsi vs. .dts) in the kernel. I
>> need to learn what's the best practice here.
>>
>> But the U-Boot DTs need to get replaced anyway soon-ish, since the Linux
>> DTs (which are WIP) have already diverged.
>> So what about we keep this alias here next to the existing one for the
>> 2016.11 release and possibly fix this later once we replace the DTs
>> anyway with what gets merged into the kernel eventually?
>
> OK, but please stick with the current discussion and still I see a
> good point to see alias on dtsi because the dts files which are using
> this dtsi shouldn't separately define the alias.
>
> And also status on dtsi is showing "disabled" are you enabled it some
> other patches? or missed?

Any response for this?

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] MAINTAINERS: SUNXI: Add Jagan as Co-Maintainer

[Jagan Teki]

Hi Hans,

On Sun, Oct 30, 2016 at 1:49 PM, Hans de Goede  wrote:
> Hi Jagan,
>
> On 29-10-16 21:26, Jagan Teki wrote:
>>
>> Due to the discussion from thread[1] about the Hans
>> stepping down as sunix custodian, I would like to
>> volunteer as a co-maintainer for sunxi and discussed
>> the same with Hans as well.
>>
>> [1] http://lists.denx.de/pipermail/u-boot/2016-July/259688.html
>>
>> Cc: Maxime Ripard 
>> Cc: Ian Campbell 
>> Cc: Hans De Goede 
>> Signed-off-by: Jagan Teki 
>
>
> I appreciate all the reviews you've done of sunxi patches,
> thank you for that. But I've yet to see any significant
> contributions to u-boot sunxi support from you, as such
> I do not feel that you are ready to co-maintain the
> sunxi code, sorry.

I sent this volunteer mail, based of our offline communication as well
as discussion on the thread.
Unfortunately we never discussed the point you "noted here" - anyway I
am fine, no issue.

thanks!
-- 
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
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Re: [U-Boot] [PATCH] MAINTAINERS: SUNXI: Add Jagan as Co-Maintainer

[Hans de Goede]

Hi Jagan,

On 29-10-16 21:26, Jagan Teki wrote:

Due to the discussion from thread[1] about the Hans
stepping down as sunix custodian, I would like to
volunteer as a co-maintainer for sunxi and discussed
the same with Hans as well.

[1] http://lists.denx.de/pipermail/u-boot/2016-July/259688.html

Cc: Maxime Ripard 
Cc: Ian Campbell 
Cc: Hans De Goede 
Signed-off-by: Jagan Teki 


I appreciate all the reviews you've done of sunxi patches,
thank you for that. But I've yet to see any significant
contributions to u-boot sunxi support from you, as such
I do not feel that you are ready to co-maintain the
sunxi code, sorry.

Regards,

Hans




---
 MAINTAINERS| 1 +
 doc/git-mailrc | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 0bd8995..c96625a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -169,6 +169,7 @@ F:  arch/arm/include/asm/arch-stv0991/
 ARM SUNXI
 M: Ian Campbell 
 M: Hans De Goede 
+M: Jagan Teki 
 S: Maintained
 T: git git://git.denx.de/u-boot-sunxi.git
 F: arch/arm/cpu/armv7/sunxi/
diff --git a/doc/git-mailrc b/doc/git-mailrc
index d01a8c7..9e26c4d 100644
--- a/doc/git-mailrc
+++ b/doc/git-mailrc
@@ -70,7 +70,7 @@ alias s5pc   samsung
 alias samsunguboot, prom
 alias snapdragon uboot, mateusz
 alias socfpgauboot, marex, Dinh Nguyen 
-alias sunxi  uboot, ijc, jwrdegoede
+alias sunxi  uboot, ijc, jwrdegoede, jagan
 alias tegra  uboot, sjg, Tom Warren , Stephen Warren 

 alias tegra2 tegra
 alias ti uboot, trini


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Re: [U-Boot] [linux-sunxi] Re: [PATCH 00/11] sunxi: Add full SPL support for sun9i (A80)

[Hans de Goede]

Hi,

On 30-10-16 06:30, Chen-Yu Tsai wrote:

On Sat, Oct 29, 2016 at 8:06 PM, Hans de Goede  wrote:

Hi,


On 28-10-16 19:30, Hans de Goede wrote:


Hi Chen-Yu,

On 28-10-16 12:21, Chen-Yu Tsai wrote:


Hi everyone,

This series adds full SPL with DRAM initialization for sun9i (A80).
The bulk of the work was done by the people at Theobroma Systems.
Their work can be found here:

https://git.theobroma-systems.com/armadillo-u-boot.git/

I picked the essential patches and cleaned them up a bit more,
and added commit messages if they were missing.

As the DRAM bits are essentially a code dump with some cleanups and
some bits disabled, expect many warnings. Checkpatch is still not
happy with it.

I've tested the series on both my A80 boards, which I've added
defconfigs for in the last 2 patches. My A80 Optimus does not
boot from micro SD, so I'm still FEL booting that one. But my
Cubieboard 4 is now standalone.

As usual, please have a look, test if possible.



Awesome, thanks for doing this and it was good to have
some face2face time at ELCE.

I've merged this into my personal sunxi-wip u-boot branch,
I've made 2 changes:

1) in : ¨sunxi: DRAM initialisation for sun9i" there are a
lot of #if 0 #endif blocks, most of these document some features
which we may want to enable in the future, but a few were just
dead weight IMHO, so I've pruned a few

2) in : "sunxi: Add support for A80 Optimus board", we already
have a configs/Merrii_A80_Optimus_defconfig, so I've made the patch
update that instead of adding a new defconfig

I have not tested this yet, I will do tomorrow, assuming it
works for me too I will include it in my next pull-req (*)



Ok, just finished testing, u-boot seems to work well. I do
seem to have one kernel issue (with the last 4.8 based
sunxi-next kernel, I still need to upgrade that) :

[1.137105] Division by zero in kernel.
[1.140988] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0+ #475
[1.147089] Hardware name: Allwinner sun9i Family
[1.151830] [] (unwind_backtrace) from []
(show_stack+0x18/0x1c)
[1.159596] [] (show_stack) from []
(dump_stack+0x80/0x9c)
[1.166839] [] (dump_stack) from [] (Ldiv0+0x8/0x10)
[1.173558] [] (Ldiv0) from []
(sun4i_a10_get_mod0_factors+0x2c/0x8c)
[1.181758] [] (sun4i_a10_get_mod0_factors) from []
(clk_factors_determine_rate+0xb8/0xf8)
[1.191781] [] (clk_factors_determine_rate) from []
(clk_composite_determine_rate+0x58/0x1cc)
[1.202062] [] (clk_composite_determine_rate) from []
(clk_calc_new_rates+0xa0/0x240)
[1.211647] [] (clk_calc_new_rates) from []
(clk_core_set_rate_nolock+0x4c/0xbc)
[1.220798] [] (clk_core_set_rate_nolock) from []
(clk_set_rate+0x28/0x38)
[1.229432] [] (clk_set_rate) from []
(sunxi_ir_probe+0xfc/0x480)
[1.420454] [] (sunxi_ir_probe) from []
(platform_drv_pro
be+0x58/0xa4)

...

And it fails to find any mmc controllers, but that might be related to
the above oops (maybe it stops probing after that due to a stuck lock).


This is related to the regulators, specifically cold boot default
values for ldo_ios causing the regulators to fail to register. You
actually fixed this for the axp22x's before.

There's also the addressing issue for the axp806.

See the top of https://github.com/wens/linux/commits/sun9i-gmac-wifi
for the bunch of fixes I need to send.


Anyways the u-boot side looks good. One issue I see is that your
optimus has an emmc, where as mine has a nand. We may want to
gave 2 optimus defconfigs for this once we've nand support.


Hmm... This implies the need for 2 versions of dts files as well.
Any ideas on probing for nand/emmc during boot?


If we want to use a single devicetree and use something like quirks
or some such, I'm sure we can up with some way to find out whether
there is an emmc or nand connected during boot (in u-boot), but
this requires a mechanism like dt-quirks to first get merged
upstream. Anyways NAND support is still not here, lets just go
with eMMC support in u-boot + the dts and we can worry about NAND
support later (this will likely cause some kernel errors on optimus
boards with NAND, but I live with that).

Regards,

Hans
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