date:20190117

From: Anup Patel 

This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.

The patches are based upon latest RISC-V U-Boot tree
(git://git.denx.de/u-boot-riscv.git) at commit id
91882c472d8c0aef4db699d3f2de55bf43d4ae4b

All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work fine on actual SiFive Unleashed board and
QEMU sifive_u machine.

Anup Patel (7):
  riscv: Rename cpu/qemu to cpu/generic
  riscv: Add asm/dma-mapping.h for DMA mappings
  riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
  net: macb: Fix clk API usage for RISC-V systems
  clk: Add SiFive FU540 PRCI clock driver
  clk: Add fixed-factor clock driver
  riscv: Add SiFive FU540 board support

Atish Patra (4):
  net: macb: Fix GEM hardware detection
  drivers: serial_sifive: Fix baud rate calculation
  drivers: serial: serial_sifive: Skip baudrate config if no input clock
  cpu: Bind timer driver for boot hart

 arch/riscv/Kconfig|   6 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  |   2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile |   0
 arch/riscv/cpu/{qemu => generic}/cpu.c|   0
 arch/riscv/cpu/generic/dram.c |  39 ++
 arch/riscv/cpu/qemu/dram.c|  17 -
 arch/riscv/include/asm/dma-mapping.h  |  38 ++
 board/emulation/qemu-riscv/Kconfig|   4 +-
 .../qemu-riscv => sifive/fu540}/Kconfig   |  36 +-
 board/sifive/fu540/MAINTAINERS|   9 +
 board/sifive/fu540/Makefile   |   5 +
 board/sifive/fu540/fu540.c|  17 +
 configs/sifive_fu540_defconfig|  11 +
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   5 +-
 drivers/clk/clk_fixed_factor.c|  74 +++
 drivers/clk/sifive/Kconfig|  19 +
 drivers/clk/sifive/Makefile   |   5 +
 .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
 drivers/clk/sifive/fu540-prci.c   | 604 ++
 drivers/clk/sifive/wrpll-cln28hpc.c   | 390 +++
 drivers/cpu/riscv_cpu.c   |   7 +-
 drivers/net/macb.c|   6 +-
 drivers/serial/serial_sifive.c|  60 +-
 include/configs/sifive-fu540.h|  43 ++
 include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
 26 files changed, 1467 insertions(+), 61 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 create mode 100644 arch/riscv/cpu/generic/dram.c
 delete mode 100644 arch/riscv/cpu/qemu/dram.c
 create mode 100644 arch/riscv/include/asm/dma-mapping.h
 copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%)
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 drivers/clk/clk_fixed_factor.c
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/configs/sifive-fu540.h
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

-- 
2.17.1

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[U-Boot] [PATCH 04/11] net: macb: Fix clk API usage for RISC-V systems

From: Anup Patel 

This patch does following fixes in MACB ethernet driver
for using it on RISC-V systems (particularly QEMU sifive_u
machine):
1. asm/arch/clk.h is not available on RISC-V port so include
   it only for non-RISC-V systems.
2. Don't fail in macb_enable_clk() if clk_enable() returns
   -ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 drivers/net/macb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 94c89c762b..9a06b523cc 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -38,7 +38,9 @@
 #include 
 #include 
 #include 
+#ifndef CONFIG_RISCV
 #include 
+#endif
 #include 
 
 #include "macb.h"
@@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev)
 */
 #ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
-   if (ret)
+   if (ret && ret != -ENOSYS)
return ret;
 #endif
 
-- 
2.17.1

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[U-Boot] [PATCH 01/11] riscv: Rename cpu/qemu to cpu/generic

From: Anup Patel 

The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel 
---
 arch/riscv/Kconfig| 2 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  | 2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile | 0
 arch/riscv/cpu/{qemu => generic}/cpu.c| 0
 arch/riscv/cpu/{qemu => generic}/dram.c   | 0
 board/emulation/qemu-riscv/Kconfig| 4 ++--
 6 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 rename arch/riscv/cpu/{qemu => generic}/dram.c (100%)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c45e4d73a8..6879047ff7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below
 
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig
similarity index 91%
rename from arch/riscv/cpu/qemu/Kconfig
rename to arch/riscv/cpu/generic/Kconfig
index f48751e6de..1d6ab5032d 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -2,7 +2,7 @@
 #
 # Copyright (C) 2018, Bin Meng 
 
-config QEMU_RISCV
+config GENERIC_RISCV
bool
select ARCH_EARLY_INIT_R
imply CPU
diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile
similarity index 100%
rename from arch/riscv/cpu/qemu/Makefile
rename to arch/riscv/cpu/generic/Makefile
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c
similarity index 100%
rename from arch/riscv/cpu/qemu/cpu.c
rename to arch/riscv/cpu/generic/cpu.c
diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c
similarity index 100%
rename from arch/riscv/cpu/qemu/dram.c
rename to arch/riscv/cpu/generic/dram.c
diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 0d865acf10..88d07d568e 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "emulation"
 
 config SYS_CPU
-   default "qemu"
+   default "generic"
 
 config SYS_CONFIG_NAME
default "qemu-riscv"
@@ -18,7 +18,7 @@ config SYS_TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
-   select QEMU_RISCV
+   select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
-- 
2.17.1

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[U-Boot] [PATCH 02/11] riscv: Add asm/dma-mapping.h for DMA mappings

From: Anup Patel 

This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 arch/riscv/include/asm/dma-mapping.h | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 arch/riscv/include/asm/dma-mapping.h

diff --git a/arch/riscv/include/asm/dma-mapping.h 
b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 00..3d930c90ec
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include 
+
+#define dma_mapping_error(x, y)0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+   *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+   return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+   free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+  enum dma_data_direction dir)
+{
+   return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+   unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
-- 
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[U-Boot] [PATCH 03/11] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems

From: Anup Patel 

On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 arch/riscv/cpu/generic/dram.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 84d87d2a7f..dea2d3701d 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -6,6 +6,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int dram_init(void)
 {
return fdtdec_setup_mem_size_base();
@@ -15,3 +17,23 @@ int dram_init_banksize(void)
 {
return fdtdec_setup_memory_banksize();
 }
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+   /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capabale
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+   if (gd->ram_top > 0x1UL)
+   return 0x1UL;
+   else
+   return gd->ram_top;
+#else
+   return gd->ram_top;
+#endif
+}
-- 
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[U-Boot] [PATCH 07/11] clk: Add fixed-factor clock driver

From: Anup Patel 

This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 drivers/clk/Makefile   |  4 +-
 drivers/clk/clk_fixed_factor.c | 74 ++
 2 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk_fixed_factor.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2f4446568c..fa59259ea3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,7 +4,9 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
 
-obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 
 obj-y += imx/
 obj-y += tegra/
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
new file mode 100644
index 00..eab1724c26
--- /dev/null
+++ b/drivers/clk/clk_fixed_factor.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Author: Anup Patel 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct clk_fixed_factor {
+   struct clk parent;
+   unsigned int div;
+   unsigned int mult;
+};
+
+#define to_clk_fixed_factor(dev)   \
+   ((struct clk_fixed_factor *)dev_get_platdata(dev))
+
+static ulong clk_fixed_factor_get_rate(struct clk *clk)
+{
+   int ret;
+   struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
+
+   if (clk->id != 0)
+   return -EINVAL;
+
+   ret = clk_get_rate(&ff->parent);
+   if (IS_ERR_VALUE(ret))
+   return ret;
+
+   do_div(ret, ff->div);
+
+   return ret * ff->mult;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+   .get_rate = clk_fixed_factor_get_rate,
+};
+
+static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   int err;
+   struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+
+   err = clk_get_by_index(dev, 0, &ff->parent);
+   if (err)
+   return err;
+
+   ff->div = dev_read_u32_default(dev, "clock-div", 1);
+   ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+#endif
+
+   return 0;
+}
+
+static const struct udevice_id clk_fixed_factor_match[] = {
+   {
+   .compatible = "fixed-factor-clock",
+   },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+   .name = "fixed_factor_clock",
+   .id = UCLASS_CLK,
+   .of_match = clk_fixed_factor_match,
+   .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+   .ops = &clk_fixed_factor_ops,
+};
-- 
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[U-Boot] [PATCH 05/11] net: macb: Fix GEM hardware detection

From: Atish Patra 

Fix MID bit field check to correctly identify all GEM hardwares.

The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259

Signed-off-by: Atish Patra 
---
 drivers/net/macb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 9a06b523cc..e04ec9a0a3 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -145,7 +145,7 @@ struct macb_device {
 
 static int macb_is_gem(struct macb_device *macb)
 {
-   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
+   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
 }
 
 #ifndef cpu_is_sama5d2
-- 
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[U-Boot] [PATCH 08/11] drivers: serial_sifive: Fix baud rate calculation

From: Atish Patra 

Compute the baud rate multipler with more precision.

Signed-off-by: Atish Patra 
---
 drivers/serial/serial_sifive.c | 28 ++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index 341728a690..ea4d35d48c 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -33,16 +33,40 @@ struct uart_sifive {
 };
 
 struct sifive_uart_platdata {
-   unsigned int clock;
+   unsigned long clock;
int saved_input_char;
struct uart_sifive *regs;
 };
 
+/**
+ * Find minimum divisor divides in_freq to max_target_hz;
+ * Based on uart driver n SiFive FSBL.
+ *
+ * f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
+ * The nearest integer solution requires rounding up as to not exceed
+ * max_target_hz.
+ * div  = ceil(f_in / f_baud) - 1
+ * = floor((f_in - 1 + f_baud) / f_baud) - 1
+ * This should not overflow as long as (f_in - 1 + f_baud) does not exceed
+ * 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ */
+static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
+   unsigned long max_target_hz)
+{
+   unsigned long quotient =
+   (in_freq + max_target_hz - 1) / (max_target_hz);
+   /* Avoid underflow */
+   if (quotient == 0)
+   return 0;
+   else
+   return quotient - 1;
+}
+
 /* Set up the baud rate in gd struct */
 static void _sifive_serial_setbrg(struct uart_sifive *regs,
  unsigned long clock, unsigned long baud)
 {
-   writel((u32)((clock / baud) - 1), ®s->div);
+   writel((uart_min_clk_divisor(clock, baud)), ®s->div);
 }
 
 static void _sifive_serial_init(struct uart_sifive *regs)
-- 
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[U-Boot] [PATCH 09/11] drivers: serial: serial_sifive: Skip baudrate config if no input clock

From: Atish Patra 

It is possible that input clock is not available because clk
device was not available and 'clock-frequency' DT property is
also not available.

In this case, instead of failing we should just skip baudrate
config by returning zero.

Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
---
 drivers/serial/serial_sifive.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index ea4d35d48c..537bc7a975 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -99,27 +99,27 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
 
 static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
 {
-   int err;
+   int ret;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+   u32 clock = 0;
 
-   err = clk_get_by_index(dev, 0, &clk);
-   if (!err) {
-   err = clk_get_rate(&clk);
-   if (!IS_ERR_VALUE(err))
-   platdata->clock = err;
-   } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (IS_ERR_VALUE(ret)) {
debug("SiFive UART failed to get clock\n");
-   return err;
-   }
-
-   if (!platdata->clock)
-   platdata->clock = dev_read_u32_default(dev, "clock-frequency", 
0);
-   if (!platdata->clock) {
-   debug("SiFive UART clock not defined\n");
-   return -EINVAL;
+   ret = dev_read_u32(dev, "clock-frequency", &clock);
+   if (IS_ERR_VALUE(ret)) {
+   debug("SiFive UART clock not defined\n");
+   return 0;
+   }
+   } else {
+   clock = clk_get_rate(&clk);
+   if (IS_ERR_VALUE(clock)) {
+   debug("SiFive UART clock get rate failed\n");
+   return 0;
+   }
}
-
+   platdata->clock = clock;
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
 
return 0;
-- 
2.17.1

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[U-Boot] [PATCH 06/11] clk: Add SiFive FU540 PRCI clock driver

From: Anup Patel 

Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra 
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley 
Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/sifive/Kconfig|  19 +
 drivers/clk/sifive/Makefile   |   5 +
 .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
 drivers/clk/sifive/fu540-prci.c   | 604 ++
 drivers/clk/sifive/wrpll-cln28hpc.c   | 390 +++
 include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
 8 files changed, 1150 insertions(+)
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eadf7f8250..ce462f5717 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -104,6 +104,7 @@ source "drivers/clk/imx/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 9acbb1a650..2f4446568c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
+obj-$(CONFIG_CLK_SIFIVE) += sifive/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
new file mode 100644
index 00..81fc9f8fda
--- /dev/null
+++ b/drivers/clk/sifive/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+   bool
+
+config CLK_SIFIVE
+   bool "SiFive SoC driver support"
+   depends on CLK
+   help
+ SoC drivers for SiFive Linux-capable SoCs.
+
+config CLK_SIFIVE_FU540_PRCI
+   bool "PRCI driver for SiFive FU540 SoCs"
+   depends on CLK_SIFIVE
+   select CLK_ANALOGBITS_WRPLL_CLN28HPC
+   help
+ Supports the Power Reset Clock interface (PRCI) IP block found in
+ FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
+ enable this driver.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
new file mode 100644
index 00..1155e07e37
--- /dev/null
+++ b/drivers/clk/sifive/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)+= wrpll-cln28hpc.o
+
+obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o
diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h 
b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
new file mode 100644
index 00..4432e24749
--- /dev/null
+++ b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+
+#include 
+
+/* DIVQ_VALUES: number of valid DIVQ values */
+#define DIVQ_VALUES6
+
+/*
+ * Bit definitions for struct analogbits_wrpll_cfg.flags
+ *
+ * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
+ * programmed to enter bypass
+ * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
+ * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
+ * feedback mode
+ * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
+ * feedback mode (not yet supported by this driver)
+ *
+ * The flags WRPLL_FLAGS_INT_F

[U-Boot] [PATCH 10/11] cpu: Bind timer driver for boot hart

From: Atish Patra 

Currently, timer driver is bound only for hart0.

There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.

The timer driver should be bound for boot hart.

Signed-off-by: Atish Patra 
---
 drivers/cpu/riscv_cpu.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5e15df590e..f77c126499 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -10,6 +10,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
 {
const char *isa;
@@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev)
 
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
-
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
/* if not found, then look at the parent /cpus node */
@@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev)
 &plat->timebase_freq);
 
/*
-* Bind riscv-timer driver on hart 0
+* Bind riscv-timer driver on boot hart.
 *
 * We only instantiate one timer device which is enough for U-Boot.
 * Pass the "timebase-frequency" value as the driver data for the
@@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev)
 * Return value is not checked since it's possible that the timer
 * driver is not included.
 */
-   if (!plat->cpu_id && plat->timebase_freq) {
+   if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
drv = lists_driver_lookup_name("riscv_timer");
if (!drv) {
debug("Cannot find the timer driver, not included?\n");
-- 
2.17.1

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[U-Boot] [PATCH 11/11] riscv: Add SiFive FU540 board support

From: Anup Patel 

This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 arch/riscv/Kconfig |  4 
 board/sifive/fu540/Kconfig | 42 +
 board/sifive/fu540/MAINTAINERS |  9 +++
 board/sifive/fu540/Makefile|  5 
 board/sifive/fu540/fu540.c | 17 ++
 configs/sifive_fu540_defconfig | 11 +
 include/configs/sifive-fu540.h | 43 ++
 7 files changed, 131 insertions(+)
 create mode 100644 board/sifive/fu540/Kconfig
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 include/configs/sifive-fu540.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6879047ff7..36512a8995 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,11 +14,15 @@ config TARGET_AX25_AE350
 config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
 
+config TARGET_SIFIVE_FU540
+   bool "Support SiFive FU540 Board"
+
 endchoice
 
 # board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
+source "board/sifive/fu540/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
new file mode 100644
index 00..6be3d88144
--- /dev/null
+++ b/board/sifive/fu540/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_SIFIVE_FU540
+
+config SYS_BOARD
+   default "fu540"
+
+config SYS_VENDOR
+   default "sifive"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "sifive-fu540"
+
+config SYS_TEXT_BASE
+   default 0x8000 if !RISCV_SMODE
+   default 0x8020 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select GENERIC_RISCV
+   imply CMD_DHCP
+   imply CMD_EXT2
+   imply CMD_EXT4
+   imply CMD_FAT
+   imply CMD_FS_GENERIC
+   imply CMD_NET
+   imply CMD_PING
+   imply CLK_SIFIVE
+   imply CLK_SIFIVE_FU540_PRCI
+   imply DOS_PARTITION
+   imply EFI_PARTITION
+   imply IP_DYN
+   imply ISO_PARTITION
+   imply MACB
+   imply MII
+   imply NET_RANDOM_ETHADDR
+   imply PHY_LIB
+   imply PHY_MSCC
+   imply SIFIVE_SERIAL
+
+endif
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
new file mode 100644
index 00..702d803ad8
--- /dev/null
+++ b/board/sifive/fu540/MAINTAINERS
@@ -0,0 +1,9 @@
+SiFive FU540 BOARD
+M: Paul Walmsley 
+M: Palmer Dabbelt 
+M: Anup Patel 
+M: Atish Patra 
+S: Maintained
+F: board/sifive/fu540/
+F: include/configs/sifive-fu540.h
+F: configs/sifive_fu540_defconfig
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
new file mode 100644
index 00..6e1862c475
--- /dev/null
+++ b/board/sifive/fu540/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y  += fu540.o
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
new file mode 100644
index 00..5adc4a3d4a
--- /dev/null
+++ b/board/sifive/fu540/fu540.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#include 
+#include 
+
+int board_init(void)
+{
+   /* For now nothing to do here. */
+
+   return 0;
+}
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
new file mode 100644
index 00..2f8cca9de0
--- /dev/null
+++ b/configs/sifive_fu540_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_RISCV_SMODE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_MII=y
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
new file mode 100644
index 00..7007b5f6af
--- /dev/null
+++ b/include/configs/sifive-fu540.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include 
+
+#define CONFIG_SYS_SDRAM_BASE  0x8000
+#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN  SZ_8M

Re: [U-Boot] [PATCH 00/11] SiFive FU540 Support

Hi All,

My apologies for spaming some of you.

First time I send patches using anup.pa...@wdc.com which got block
U-Boot mailing list server (Don't know why).

Regards,
Anup
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Re: [U-Boot] [PATCH] dts: am335x-pdu001: Fix polarity of card detection input

2019-01-17 Thread Felix Brack

Hi Tom,

On 29.11.2018 21:27, Tom Rini wrote:
> On Thu, Nov 29, 2018 at 05:07:47PM +0100, Felix Brack wrote:
>> On 29.11.2018 16:52, Tom Rini wrote:
>>> On Thu, Nov 29, 2018 at 04:33:36PM +0100, Felix Brack wrote:
 On 29.11.2018 16:25, Tom Rini wrote:
> On Thu, Nov 29, 2018 at 01:45:06PM +0100, Felix Brack wrote:
>
>> When a micro SD card is inserted in the PDU001 card cage, the card
>> detection switch is opened and the corresponding GPIO input is driven
>> by a pull-up. Hence change the active level of the card detection
>> input from low to high.
>>
>> Signed-off-by: Felix Brack 
>> ---
>>
>>  arch/arm/dts/am335x-pdu001.dts | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/am335x-pdu001.dts 
>> b/arch/arm/dts/am335x-pdu001.dts
>> index 121e2c6207..3a5e952663 100644
>> --- a/arch/arm/dts/am335x-pdu001.dts
>> +++ b/arch/arm/dts/am335x-pdu001.dts
>> @@ -576,7 +576,7 @@
>>  bus-width = <4>;
>>  pinctrl-names = "default";
>>  pinctrl-0 = <&mmc2_pins>;
>> -cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
>> +cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
>>  };
>>  
>>  &sham {
>
> Is this in upstream Linux as well?  If so what tag/hash?  Thanks!
>
 Not yet. I will send the Linux patch within a few days.
 The fix appears for U-Boot first as it is required for the upcoming
 patch that enables CONFIG_BLK and CONFIG_DM_MMC for this board.
>>>
>>> Please reply to the thread with a ML link there so we can track and make
>>> sure it doesn't get out of sync, thanks!
>>> I'm not sure if I got that correctly. What is an 'ML link'?
>> Was there something wrong with my last post or would you like me to post
>> a message in this thread once the patch is in upstream Linux?
> 
> The general preference is that when we touch the dts files that aren't
> U-Boot centric the commit message references the Linux githash/tag it's
> taken from, for easier future re-syncs.  Since you're in progress on
> fixing this in Linux too, you can just reply here so it's at least
> tracked on the ML and archives that the change _is_ going upstream so we
> aren't likely to overwrite it by accident later (and since you'd be the
> one pushing a future re-sync, you'd also notice, so it's really not
> likely to happen).  Thanks!
> 

FYI: with patch https://patchwork.ozlabs.org/patch/1026522/ DTS for this
board is now in identical in U-Boot and Linux.

regards Felix
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Re: [U-Boot] Problems to boot i.MX8QXP EVK board

2019-01-17 Thread Fabio Estevam

Hi Peng,

On Thu, Jan 17, 2019 at 8:27 AM Breno Matheus Lima
 wrote:

> Hi Peng,
>
> I'm using the following versions:
>
> - U-Boot upstream v2019.01
> - ATF from NXP codeaurora (rel_imx_4.14.78_1.0.0_ga)
> - SCFW binary from imx-sc-firmware-1.1 package
> - SECO FW from firmware-imx-8.0 package
>
> The same issue still happening, I can only boot my board after
> reverting commit f7e475db4011("tools: imx8image: set dcd_skip to
> true").
>
> As you can see in log below, SCFW top is 65afe5f6:
>
> U-Boot 2019.01-1-g2df3ad4767 (Jan 17 2019 - 08:15:39 -0200)
>
> CPU:   NXP i.MX8QXP RevB A35 at 147228 MHz

The reported frequency is 147.2 GHz. Do you have a fix for this?

> Model: Freescale i.MX8QXP MEK
> Board: iMX8QXP MEK
> Build: SCFW 65afe5f6
> Boot:  SD1
> DRAM:  3 GiB
> MMC:   FSL_SDHC: 0, FSL_SDHC: 1
> Loading Environment from MMC... *** Warning - bad CRC, using default 
> environment

Should we revert f7e475db4011 ("tools: imx8image: set dcd_skip to true")?
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[U-Boot] [PATCH v3 1/1] avb: add support for named persistent values

2019-01-17 Thread Igor Opaniuk

AVB version 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].

Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent values.

Correspondent pull request in the OP-TEE OS project repo [2].

[1]: https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22
[2]: https://github.com/OP-TEE/optee_os/pull/2699

Signed-off-by: Igor Opaniuk 
---

Changes in v3:
- fix possible mem lick in avb_read_persistent/avb_write_persistent
- add additional sanity checks
- cover avb read_pvalue/write_pvalue commands with python tests

Changes in v2:
- fix output format for avb read_pvalue/write_pvalue commands
- fix issue with named value buffer size

 cmd/avb.c  |  78 
 common/avb_verify.c| 125 +
 include/tee.h  |   2 +
 include/tee/optee_ta_avb.h |  16 ++
 test/py/tests/test_avb.py  |  16 ++
 5 files changed, 237 insertions(+)

diff --git a/cmd/avb.c b/cmd/avb.c
index ff00be4..c5af4a2 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -340,6 +340,76 @@ int do_avb_is_unlocked(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
 }
 
+int do_avb_read_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
+  char * const argv[])
+{
+   const char *name;
+   size_t bytes;
+   size_t bytes_read;
+   void *buffer;
+   char *endp;
+
+   if (!avb_ops) {
+   printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (argc != 3)
+   return CMD_RET_USAGE;
+
+   name = argv[1];
+   bytes = simple_strtoul(argv[2], &endp, 10);
+   if (*endp && *endp != '\n')
+   return CMD_RET_USAGE;
+
+   buffer = malloc(bytes);
+   if (!buffer)
+   return CMD_RET_FAILURE;
+
+   if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
+  &bytes_read) == AVB_IO_RESULT_OK) {
+   printf("Read %ld bytes, value = %s\n", bytes_read,
+  (char *)buffer);
+   free(buffer);
+   return CMD_RET_SUCCESS;
+   }
+
+   printf("Failed to read persistent value\n");
+
+   free(buffer);
+
+   return CMD_RET_FAILURE;
+}
+
+int do_avb_write_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
+   char * const argv[])
+{
+   const char *name;
+   const char *value;
+
+   if (!avb_ops) {
+   printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (argc != 3)
+   return CMD_RET_USAGE;
+
+   name = argv[1];
+   value = argv[2];
+
+   if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
+   (const uint8_t *)value) ==
+   AVB_IO_RESULT_OK) {
+   printf("Wrote %ld bytes\n", strlen(value) + 1);
+   return CMD_RET_SUCCESS;
+   }
+
+   printf("Failed to write persistent value\n");
+
+   return CMD_RET_FAILURE;
+}
+
 static cmd_tbl_t cmd_avb[] = {
U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""),
U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""),
@@ -350,6 +420,10 @@ static cmd_tbl_t cmd_avb[] = {
U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
+#ifdef CONFIG_OPTEE_TA_AVB
+   U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
+   U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
+#endif
 };
 
 static int do_avb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -384,6 +458,10 @@ U_BOOT_CMD(
"partition  and print to stdout\n"
"avb write_part - write  bytes 
to\n"
" by  using data from \n"
+#ifdef CONFIG_OPTEE_TA_AVB
+   "avb read_pvalue   - read a persistent value \n"
+   "avb write_pvalue   - write a persistent value \n"
+#endif
"avb verify - run verification process using hash data\n"
"from vbmeta structure\n"
);
diff --git a/common/avb_verify.c b/common/avb_verify.c
index a8c5a3e..584e235 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -647,6 +647,10 @@ static AvbIOResult invoke_func(struct AvbOpsData 
*ops_data, u32 func,
return AVB_IO_RESULT_OK;
case TEE_ERROR_OUT_OF_MEMORY:
return AVB_IO_RESULT_ERROR_OOM;
+   case TEE_ERROR_STORAGE_NO_SPACE:
+   return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
+   case TEE_ERROR_ITEM_NOT_FOUND:
+   return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
c

Re: [U-Boot] [PATCH 1/3] mtd: spi: export functions to sf_internal.h

Hi Daniel,

The 01/16/2019 15:07, Daniel Schwierzeck wrote:
> 
> 
> Am 16.01.19 um 13:07 schrieb Horatiu Vultur:
> > Expose the following functions: clean_bar, write_bar, spi_flash_std_write,
> > spi_flash_std_erase and spi_flash_std_probe to sf_internal.h to be able to
> > reuse them.
> > 
> > Cc: Jagan Teki 
> > Signed-off-by: Horatiu Vultur 
> > ---
> >  drivers/mtd/spi/sf_internal.h | 8 
> >  drivers/mtd/spi/sf_probe.c| 8 
> >  drivers/mtd/spi/spi_flash.c   | 4 ++--
> >  3 files changed, 14 insertions(+), 6 deletions(-)
> > 
> 
> maybe you should wait with this series as there is on-going work to
> import spi-nor from Linux [1]
> 
> [1] https://lists.denx.de/pipermail/u-boot/2018-December/350565.html
> 

That is perfectly fine for me, I will submit another patch after the
spi-nor series is accepted. Thank you.

> -- 
> - Daniel

-- 
/Horatiu
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[U-Boot] [RESEND v3 1/1] avb: add support for named persistent values

2019-01-17 Thread Igor Opaniuk

AVB version 1.1 introduces support for named persistent values
that must be tamper evident and allows AVB to store arbitrary key-value
pairs [1].

Introduce implementation of two additional AVB operations
read_persistent_value()/write_persistent_value() for retrieving/storing
named persistent values.

Correspondent pull request in the OP-TEE OS project repo [2].

[1]: https://android.googlesource.com/platform/external/avb/+/android-9.0.0_r22
[2]: https://github.com/OP-TEE/optee_os/pull/2699

Signed-off-by: Igor Opaniuk 
---

Changes in v3:
- fix possible mem lick in avb_read_persistent/avb_write_persistent
- added additional sanity checks
- covered avb read_pvalue/write_pvalue commands with python tests

Changes in v2:
- fix output format for avb read_pvalue/write_pvalue commands
- fix issue with named value buffer size

 cmd/avb.c  |  78 
 common/avb_verify.c| 125 +
 include/tee.h  |   2 +
 include/tee/optee_ta_avb.h |  16 ++
 test/py/tests/test_avb.py  |  16 ++
 5 files changed, 237 insertions(+)

diff --git a/cmd/avb.c b/cmd/avb.c
index ff00be4..c5af4a2 100644
--- a/cmd/avb.c
+++ b/cmd/avb.c
@@ -340,6 +340,76 @@ int do_avb_is_unlocked(cmd_tbl_t *cmdtp, int flag,
return CMD_RET_FAILURE;
 }
 
+int do_avb_read_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
+  char * const argv[])
+{
+   const char *name;
+   size_t bytes;
+   size_t bytes_read;
+   void *buffer;
+   char *endp;
+
+   if (!avb_ops) {
+   printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (argc != 3)
+   return CMD_RET_USAGE;
+
+   name = argv[1];
+   bytes = simple_strtoul(argv[2], &endp, 10);
+   if (*endp && *endp != '\n')
+   return CMD_RET_USAGE;
+
+   buffer = malloc(bytes);
+   if (!buffer)
+   return CMD_RET_FAILURE;
+
+   if (avb_ops->read_persistent_value(avb_ops, name, bytes, buffer,
+  &bytes_read) == AVB_IO_RESULT_OK) {
+   printf("Read %ld bytes, value = %s\n", bytes_read,
+  (char *)buffer);
+   free(buffer);
+   return CMD_RET_SUCCESS;
+   }
+
+   printf("Failed to read persistent value\n");
+
+   free(buffer);
+
+   return CMD_RET_FAILURE;
+}
+
+int do_avb_write_pvalue(cmd_tbl_t *cmdtp, int flag, int argc,
+   char * const argv[])
+{
+   const char *name;
+   const char *value;
+
+   if (!avb_ops) {
+   printf("AVB 2.0 is not initialized, run 'avb init' first\n");
+   return CMD_RET_FAILURE;
+   }
+
+   if (argc != 3)
+   return CMD_RET_USAGE;
+
+   name = argv[1];
+   value = argv[2];
+
+   if (avb_ops->write_persistent_value(avb_ops, name, strlen(value) + 1,
+   (const uint8_t *)value) ==
+   AVB_IO_RESULT_OK) {
+   printf("Wrote %ld bytes\n", strlen(value) + 1);
+   return CMD_RET_SUCCESS;
+   }
+
+   printf("Failed to write persistent value\n");
+
+   return CMD_RET_FAILURE;
+}
+
 static cmd_tbl_t cmd_avb[] = {
U_BOOT_CMD_MKENT(init, 2, 0, do_avb_init, "", ""),
U_BOOT_CMD_MKENT(read_rb, 2, 0, do_avb_read_rb, "", ""),
@@ -350,6 +420,10 @@ static cmd_tbl_t cmd_avb[] = {
U_BOOT_CMD_MKENT(read_part_hex, 4, 0, do_avb_read_part_hex, "", ""),
U_BOOT_CMD_MKENT(write_part, 5, 0, do_avb_write_part, "", ""),
U_BOOT_CMD_MKENT(verify, 1, 0, do_avb_verify_part, "", ""),
+#ifdef CONFIG_OPTEE_TA_AVB
+   U_BOOT_CMD_MKENT(read_pvalue, 3, 0, do_avb_read_pvalue, "", ""),
+   U_BOOT_CMD_MKENT(write_pvalue, 3, 0, do_avb_write_pvalue, "", ""),
+#endif
 };
 
 static int do_avb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -384,6 +458,10 @@ U_BOOT_CMD(
"partition  and print to stdout\n"
"avb write_part - write  bytes 
to\n"
" by  using data from \n"
+#ifdef CONFIG_OPTEE_TA_AVB
+   "avb read_pvalue   - read a persistent value \n"
+   "avb write_pvalue   - write a persistent value \n"
+#endif
"avb verify - run verification process using hash data\n"
"from vbmeta structure\n"
);
diff --git a/common/avb_verify.c b/common/avb_verify.c
index a8c5a3e..584e235 100644
--- a/common/avb_verify.c
+++ b/common/avb_verify.c
@@ -647,6 +647,10 @@ static AvbIOResult invoke_func(struct AvbOpsData 
*ops_data, u32 func,
return AVB_IO_RESULT_OK;
case TEE_ERROR_OUT_OF_MEMORY:
return AVB_IO_RESULT_ERROR_OOM;
+   case TEE_ERROR_STORAGE_NO_SPACE:
+   return AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE;
+   case TEE_ERROR_ITEM_NOT_FOUND:
+   return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;

Re: [U-Boot] [PATCH] configs: Remove am335x_boneblack_defconfig

On Thu, Jan 17, 2019 at 03:44:06PM +0530, Faiz Abbas wrote:

> The am335x_evm_defconfig supports all am335x_boneblack variants. Remove
> the redundant am335x_boneblack_defconfig.
> 
> Signed-off-by: Faiz Abbas 

Since the thinking at the time was to have env somewhere usable on these
platforms (it was not on the _evm variant at the time), yes:

Reviewed-by: Tom Rini 

But the _vboot one needs to be updated as that's one of the canonical
examples of using FIT images and verified boot in U-Boot.  Thanks!

-- 
Tom

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[U-Boot] [PATCH 01/11] riscv: Rename cpu/qemu to cpu/generic

The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel 
---
 arch/riscv/Kconfig| 2 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  | 2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile | 0
 arch/riscv/cpu/{qemu => generic}/cpu.c| 0
 arch/riscv/cpu/{qemu => generic}/dram.c   | 0
 board/emulation/qemu-riscv/Kconfig| 4 ++--
 6 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 rename arch/riscv/cpu/{qemu => generic}/dram.c (100%)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c45e4d73a8..6879047ff7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below
 
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig
similarity index 91%
rename from arch/riscv/cpu/qemu/Kconfig
rename to arch/riscv/cpu/generic/Kconfig
index f48751e6de..1d6ab5032d 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -2,7 +2,7 @@
 #
 # Copyright (C) 2018, Bin Meng 
 
-config QEMU_RISCV
+config GENERIC_RISCV
bool
select ARCH_EARLY_INIT_R
imply CPU
diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile
similarity index 100%
rename from arch/riscv/cpu/qemu/Makefile
rename to arch/riscv/cpu/generic/Makefile
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c
similarity index 100%
rename from arch/riscv/cpu/qemu/cpu.c
rename to arch/riscv/cpu/generic/cpu.c
diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c
similarity index 100%
rename from arch/riscv/cpu/qemu/dram.c
rename to arch/riscv/cpu/generic/dram.c
diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 0d865acf10..88d07d568e 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "emulation"
 
 config SYS_CPU
-   default "qemu"
+   default "generic"
 
 config SYS_CONFIG_NAME
default "qemu-riscv"
@@ -18,7 +18,7 @@ config SYS_TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
-   select QEMU_RISCV
+   select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
-- 
2.17.1

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[U-Boot] [PATCH 00/11] SiFive FU540 Support

This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.

The patches are based upon latest RISC-V U-Boot tree
(git://git.denx.de/u-boot-riscv.git) at commit id
91882c472d8c0aef4db699d3f2de55bf43d4ae4b

All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work fine on actual SiFive Unleashed board and
QEMU sifive_u machine.

Anup Patel (7):
  riscv: Rename cpu/qemu to cpu/generic
  riscv: Add asm/dma-mapping.h for DMA mappings
  riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
  net: macb: Fix clk API usage for RISC-V systems
  clk: Add SiFive FU540 PRCI clock driver
  clk: Add fixed-factor clock driver
  riscv: Add SiFive FU540 board support

Atish Patra (4):
  net: macb: Fix GEM hardware detection
  drivers: serial_sifive: Fix baud rate calculation
  drivers: serial: serial_sifive: Skip baudrate config if no input clock
  cpu: Bind timer driver for boot hart

 arch/riscv/Kconfig|   6 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  |   2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile |   0
 arch/riscv/cpu/{qemu => generic}/cpu.c|   0
 arch/riscv/cpu/generic/dram.c |  39 ++
 arch/riscv/cpu/qemu/dram.c|  17 -
 arch/riscv/include/asm/dma-mapping.h  |  38 ++
 board/emulation/qemu-riscv/Kconfig|   4 +-
 .../qemu-riscv => sifive/fu540}/Kconfig   |  36 +-
 board/sifive/fu540/MAINTAINERS|   9 +
 board/sifive/fu540/Makefile   |   5 +
 board/sifive/fu540/fu540.c|  17 +
 configs/sifive_fu540_defconfig|  11 +
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   5 +-
 drivers/clk/clk_fixed_factor.c|  74 +++
 drivers/clk/sifive/Kconfig|  19 +
 drivers/clk/sifive/Makefile   |   5 +
 .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
 drivers/clk/sifive/fu540-prci.c   | 604 ++
 drivers/clk/sifive/wrpll-cln28hpc.c   | 390 +++
 drivers/cpu/riscv_cpu.c   |   7 +-
 drivers/net/macb.c|   6 +-
 drivers/serial/serial_sifive.c|  60 +-
 include/configs/sifive-fu540.h|  43 ++
 include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
 26 files changed, 1467 insertions(+), 61 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 create mode 100644 arch/riscv/cpu/generic/dram.c
 delete mode 100644 arch/riscv/cpu/qemu/dram.c
 create mode 100644 arch/riscv/include/asm/dma-mapping.h
 copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%)
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 drivers/clk/clk_fixed_factor.c
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/configs/sifive-fu540.h
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

-- 
2.17.1

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[U-Boot] [PATCH 03/11] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems

On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 arch/riscv/cpu/generic/dram.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 84d87d2a7f..dea2d3701d 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -6,6 +6,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int dram_init(void)
 {
return fdtdec_setup_mem_size_base();
@@ -15,3 +17,23 @@ int dram_init_banksize(void)
 {
return fdtdec_setup_memory_banksize();
 }
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+   /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capabale
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+   if (gd->ram_top > 0x1UL)
+   return 0x1UL;
+   else
+   return gd->ram_top;
+#else
+   return gd->ram_top;
+#endif
+}
-- 
2.17.1

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[U-Boot] [PATCH 05/11] net: macb: Fix GEM hardware detection

From: Atish Patra 

Fix MID bit field check to correctly identify all GEM hardwares.

The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259

Signed-off-by: Atish Patra 
---
 drivers/net/macb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 9a06b523cc..e04ec9a0a3 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -145,7 +145,7 @@ struct macb_device {
 
 static int macb_is_gem(struct macb_device *macb)
 {
-   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
+   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
 }
 
 #ifndef cpu_is_sama5d2
-- 
2.17.1

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[U-Boot] [PATCH 04/11] net: macb: Fix clk API usage for RISC-V systems

This patch does following fixes in MACB ethernet driver
for using it on RISC-V systems (particularly QEMU sifive_u
machine):
1. asm/arch/clk.h is not available on RISC-V port so include
   it only for non-RISC-V systems.
2. Don't fail in macb_enable_clk() if clk_enable() returns
   -ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 drivers/net/macb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 94c89c762b..9a06b523cc 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -38,7 +38,9 @@
 #include 
 #include 
 #include 
+#ifndef CONFIG_RISCV
 #include 
+#endif
 #include 
 
 #include "macb.h"
@@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev)
 */
 #ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
-   if (ret)
+   if (ret && ret != -ENOSYS)
return ret;
 #endif
 
-- 
2.17.1

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[U-Boot] [PATCH 02/11] riscv: Add asm/dma-mapping.h for DMA mappings

This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 arch/riscv/include/asm/dma-mapping.h | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 arch/riscv/include/asm/dma-mapping.h

diff --git a/arch/riscv/include/asm/dma-mapping.h 
b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 00..3d930c90ec
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include 
+
+#define dma_mapping_error(x, y)0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+   *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+   return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+   free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+  enum dma_data_direction dir)
+{
+   return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+   unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
-- 
2.17.1

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[U-Boot] [PATCH 06/11] clk: Add SiFive FU540 PRCI clock driver

Add driver code for the SiFive FU540 PRCI IP block.  This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.

Based on code written by Wesley Terpstra 
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux

Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.

Signed-off-by: Paul Walmsley 
Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
---
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   1 +
 drivers/clk/sifive/Kconfig|  19 +
 drivers/clk/sifive/Makefile   |   5 +
 .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
 drivers/clk/sifive/fu540-prci.c   | 604 ++
 drivers/clk/sifive/wrpll-cln28hpc.c   | 390 +++
 include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
 8 files changed, 1150 insertions(+)
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index eadf7f8250..ce462f5717 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -104,6 +104,7 @@ source "drivers/clk/imx/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
 source "drivers/clk/owl/Kconfig"
 source "drivers/clk/renesas/Kconfig"
+source "drivers/clk/sifive/Kconfig"
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 9acbb1a650..2f4446568c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
 obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
 obj-$(CONFIG_CLK_OWL) += owl/
 obj-$(CONFIG_CLK_RENESAS) += renesas/
+obj-$(CONFIG_CLK_SIFIVE) += sifive/
 obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
 obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
 obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig
new file mode 100644
index 00..81fc9f8fda
--- /dev/null
+++ b/drivers/clk/sifive/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config CLK_ANALOGBITS_WRPLL_CLN28HPC
+   bool
+
+config CLK_SIFIVE
+   bool "SiFive SoC driver support"
+   depends on CLK
+   help
+ SoC drivers for SiFive Linux-capable SoCs.
+
+config CLK_SIFIVE_FU540_PRCI
+   bool "PRCI driver for SiFive FU540 SoCs"
+   depends on CLK_SIFIVE
+   select CLK_ANALOGBITS_WRPLL_CLN28HPC
+   help
+ Supports the Power Reset Clock interface (PRCI) IP block found in
+ FU540 SoCs.  If this kernel is meant to run on a SiFive FU540 SoC,
+ enable this driver.
diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile
new file mode 100644
index 00..1155e07e37
--- /dev/null
+++ b/drivers/clk/sifive/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)+= wrpll-cln28hpc.o
+
+obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o
diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h 
b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
new file mode 100644
index 00..4432e24749
--- /dev/null
+++ b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
@@ -0,0 +1,101 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Copyright (C) 2018 SiFive, Inc.
+ * Wesley Terpstra
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H
+
+#include 
+
+/* DIVQ_VALUES: number of valid DIVQ values */
+#define DIVQ_VALUES6
+
+/*
+ * Bit definitions for struct analogbits_wrpll_cfg.flags
+ *
+ * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be
+ * programmed to enter bypass
+ * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset
+ * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal
+ * feedback mode
+ * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external
+ * feedback mode (not yet supported by this driver)
+ *
+ * The flags WRPLL_FLAGS_INT_FEEDBACK_FLAG and WR

[U-Boot] [PATCH 00/11] SiFive FU540 Support

This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.

The patches are based upon latest RISC-V U-Boot tree
(git://git.denx.de/u-boot-riscv.git) at commit id
91882c472d8c0aef4db699d3f2de55bf43d4ae4b

All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work fine on actual SiFive Unleashed board and
QEMU sifive_u machine.

Anup Patel (7):
  riscv: Rename cpu/qemu to cpu/generic
  riscv: Add asm/dma-mapping.h for DMA mappings
  riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
  net: macb: Fix clk API usage for RISC-V systems
  clk: Add SiFive FU540 PRCI clock driver
  clk: Add fixed-factor clock driver
  riscv: Add SiFive FU540 board support

Atish Patra (4):
  net: macb: Fix GEM hardware detection
  drivers: serial_sifive: Fix baud rate calculation
  drivers: serial: serial_sifive: Skip baudrate config if no input clock
  cpu: Bind timer driver for boot hart

 arch/riscv/Kconfig|   6 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  |   2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile |   0
 arch/riscv/cpu/{qemu => generic}/cpu.c|   0
 arch/riscv/cpu/generic/dram.c |  39 ++
 arch/riscv/cpu/qemu/dram.c|  17 -
 arch/riscv/include/asm/dma-mapping.h  |  38 ++
 board/emulation/qemu-riscv/Kconfig|   4 +-
 .../qemu-riscv => sifive/fu540}/Kconfig   |  36 +-
 board/sifive/fu540/MAINTAINERS|   9 +
 board/sifive/fu540/Makefile   |   5 +
 board/sifive/fu540/fu540.c|  17 +
 configs/sifive_fu540_defconfig|  11 +
 drivers/clk/Kconfig   |   1 +
 drivers/clk/Makefile  |   5 +-
 drivers/clk/clk_fixed_factor.c|  74 +++
 drivers/clk/sifive/Kconfig|  19 +
 drivers/clk/sifive/Makefile   |   5 +
 .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
 drivers/clk/sifive/fu540-prci.c   | 604 ++
 drivers/clk/sifive/wrpll-cln28hpc.c   | 390 +++
 drivers/cpu/riscv_cpu.c   |   7 +-
 drivers/net/macb.c|   6 +-
 drivers/serial/serial_sifive.c|  60 +-
 include/configs/sifive-fu540.h|  43 ++
 include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
 26 files changed, 1467 insertions(+), 61 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 create mode 100644 arch/riscv/cpu/generic/dram.c
 delete mode 100644 arch/riscv/cpu/qemu/dram.c
 create mode 100644 arch/riscv/include/asm/dma-mapping.h
 copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%)
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 drivers/clk/clk_fixed_factor.c
 create mode 100644 drivers/clk/sifive/Kconfig
 create mode 100644 drivers/clk/sifive/Makefile
 create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
 create mode 100644 drivers/clk/sifive/fu540-prci.c
 create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c
 create mode 100644 include/configs/sifive-fu540.h
 create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h

-- 
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[U-Boot] [PATCH 07/11] clk: Add fixed-factor clock driver

This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 drivers/clk/Makefile   |  4 +-
 drivers/clk/clk_fixed_factor.c | 74 ++
 2 files changed, 77 insertions(+), 1 deletion(-)
 create mode 100644 drivers/clk/clk_fixed_factor.c

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 2f4446568c..fa59259ea3 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,7 +4,9 @@
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
 #
 
-obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
 
 obj-y += imx/
 obj-y += tegra/
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
new file mode 100644
index 00..eab1724c26
--- /dev/null
+++ b/drivers/clk/clk_fixed_factor.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Author: Anup Patel 
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+struct clk_fixed_factor {
+   struct clk parent;
+   unsigned int div;
+   unsigned int mult;
+};
+
+#define to_clk_fixed_factor(dev)   \
+   ((struct clk_fixed_factor *)dev_get_platdata(dev))
+
+static ulong clk_fixed_factor_get_rate(struct clk *clk)
+{
+   int ret;
+   struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
+
+   if (clk->id != 0)
+   return -EINVAL;
+
+   ret = clk_get_rate(&ff->parent);
+   if (IS_ERR_VALUE(ret))
+   return ret;
+
+   do_div(ret, ff->div);
+
+   return ret * ff->mult;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+   .get_rate = clk_fixed_factor_get_rate,
+};
+
+static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+{
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+   int err;
+   struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+
+   err = clk_get_by_index(dev, 0, &ff->parent);
+   if (err)
+   return err;
+
+   ff->div = dev_read_u32_default(dev, "clock-div", 1);
+   ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+#endif
+
+   return 0;
+}
+
+static const struct udevice_id clk_fixed_factor_match[] = {
+   {
+   .compatible = "fixed-factor-clock",
+   },
+   { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+   .name = "fixed_factor_clock",
+   .id = UCLASS_CLK,
+   .of_match = clk_fixed_factor_match,
+   .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
+   .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+   .ops = &clk_fixed_factor_ops,
+};
-- 
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[U-Boot] [PATCH 02/11] riscv: Add asm/dma-mapping.h for DMA mappings

This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 arch/riscv/include/asm/dma-mapping.h | 38 
 1 file changed, 38 insertions(+)
 create mode 100644 arch/riscv/include/asm/dma-mapping.h

diff --git a/arch/riscv/include/asm/dma-mapping.h 
b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 00..3d930c90ec
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include 
+
+#define dma_mapping_error(x, y)0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+   *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+   return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+   free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+  enum dma_data_direction dir)
+{
+   return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+   unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
-- 
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[U-Boot] [PATCH 04/11] net: macb: Fix clk API usage for RISC-V systems

This patch does following fixes in MACB ethernet driver
for using it on RISC-V systems (particularly QEMU sifive_u
machine):
1. asm/arch/clk.h is not available on RISC-V port so include
   it only for non-RISC-V systems.
2. Don't fail in macb_enable_clk() if clk_enable() returns
   -ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
 drivers/net/macb.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 94c89c762b..9a06b523cc 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -38,7 +38,9 @@
 #include 
 #include 
 #include 
+#ifndef CONFIG_RISCV
 #include 
+#endif
 #include 
 
 #include "macb.h"
@@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev)
 */
 #ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);
-   if (ret)
+   if (ret && ret != -ENOSYS)
return ret;
 #endif
 
-- 
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[U-Boot] [PATCH 01/11] riscv: Rename cpu/qemu to cpu/generic

The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel 
---
 arch/riscv/Kconfig| 2 +-
 arch/riscv/cpu/{qemu => generic}/Kconfig  | 2 +-
 arch/riscv/cpu/{qemu => generic}/Makefile | 0
 arch/riscv/cpu/{qemu => generic}/cpu.c| 0
 arch/riscv/cpu/{qemu => generic}/dram.c   | 0
 board/emulation/qemu-riscv/Kconfig| 4 ++--
 6 files changed, 4 insertions(+), 4 deletions(-)
 rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
 rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
 rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
 rename arch/riscv/cpu/{qemu => generic}/dram.c (100%)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c45e4d73a8..6879047ff7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
 
 # architecture-specific options below
 
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig
similarity index 91%
rename from arch/riscv/cpu/qemu/Kconfig
rename to arch/riscv/cpu/generic/Kconfig
index f48751e6de..1d6ab5032d 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -2,7 +2,7 @@
 #
 # Copyright (C) 2018, Bin Meng 
 
-config QEMU_RISCV
+config GENERIC_RISCV
bool
select ARCH_EARLY_INIT_R
imply CPU
diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile
similarity index 100%
rename from arch/riscv/cpu/qemu/Makefile
rename to arch/riscv/cpu/generic/Makefile
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c
similarity index 100%
rename from arch/riscv/cpu/qemu/cpu.c
rename to arch/riscv/cpu/generic/cpu.c
diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c
similarity index 100%
rename from arch/riscv/cpu/qemu/dram.c
rename to arch/riscv/cpu/generic/dram.c
diff --git a/board/emulation/qemu-riscv/Kconfig 
b/board/emulation/qemu-riscv/Kconfig
index 0d865acf10..88d07d568e 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "emulation"
 
 config SYS_CPU
-   default "qemu"
+   default "generic"
 
 config SYS_CONFIG_NAME
default "qemu-riscv"
@@ -18,7 +18,7 @@ config SYS_TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
-   select QEMU_RISCV
+   select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
-- 
2.17.1

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[U-Boot] [PATCH 05/11] net: macb: Fix GEM hardware detection

From: Atish Patra 

Fix MID bit field check to correctly identify all GEM hardwares.

The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259

Signed-off-by: Atish Patra 
---
 drivers/net/macb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 9a06b523cc..e04ec9a0a3 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -145,7 +145,7 @@ struct macb_device {
 
 static int macb_is_gem(struct macb_device *macb)
 {
-   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
+   return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
 }
 
 #ifndef cpu_is_sama5d2
-- 
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[U-Boot] [PATCH 03/11] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems

On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 arch/riscv/cpu/generic/dram.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 84d87d2a7f..dea2d3701d 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -6,6 +6,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 int dram_init(void)
 {
return fdtdec_setup_mem_size_base();
@@ -15,3 +17,23 @@ int dram_init_banksize(void)
 {
return fdtdec_setup_memory_banksize();
 }
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+   /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capabale
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+   if (gd->ram_top > 0x1UL)
+   return 0x1UL;
+   else
+   return gd->ram_top;
+#else
+   return gd->ram_top;
+#endif
+}
-- 
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[U-Boot] [PATCH 11/11] riscv: Add SiFive FU540 board support

This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 
---
 arch/riscv/Kconfig |  4 
 board/sifive/fu540/Kconfig | 42 +
 board/sifive/fu540/MAINTAINERS |  9 +++
 board/sifive/fu540/Makefile|  5 
 board/sifive/fu540/fu540.c | 17 ++
 configs/sifive_fu540_defconfig | 11 +
 include/configs/sifive-fu540.h | 43 ++
 7 files changed, 131 insertions(+)
 create mode 100644 board/sifive/fu540/Kconfig
 create mode 100644 board/sifive/fu540/MAINTAINERS
 create mode 100644 board/sifive/fu540/Makefile
 create mode 100644 board/sifive/fu540/fu540.c
 create mode 100644 configs/sifive_fu540_defconfig
 create mode 100644 include/configs/sifive-fu540.h

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6879047ff7..36512a8995 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,11 +14,15 @@ config TARGET_AX25_AE350
 config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
 
+config TARGET_SIFIVE_FU540
+   bool "Support SiFive FU540 Board"
+
 endchoice
 
 # board-specific options below
 source "board/AndesTech/ax25-ae350/Kconfig"
 source "board/emulation/qemu-riscv/Kconfig"
+source "board/sifive/fu540/Kconfig"
 
 # platform-specific options below
 source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
new file mode 100644
index 00..6be3d88144
--- /dev/null
+++ b/board/sifive/fu540/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_SIFIVE_FU540
+
+config SYS_BOARD
+   default "fu540"
+
+config SYS_VENDOR
+   default "sifive"
+
+config SYS_CPU
+   default "generic"
+
+config SYS_CONFIG_NAME
+   default "sifive-fu540"
+
+config SYS_TEXT_BASE
+   default 0x8000 if !RISCV_SMODE
+   default 0x8020 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+   def_bool y
+   select GENERIC_RISCV
+   imply CMD_DHCP
+   imply CMD_EXT2
+   imply CMD_EXT4
+   imply CMD_FAT
+   imply CMD_FS_GENERIC
+   imply CMD_NET
+   imply CMD_PING
+   imply CLK_SIFIVE
+   imply CLK_SIFIVE_FU540_PRCI
+   imply DOS_PARTITION
+   imply EFI_PARTITION
+   imply IP_DYN
+   imply ISO_PARTITION
+   imply MACB
+   imply MII
+   imply NET_RANDOM_ETHADDR
+   imply PHY_LIB
+   imply PHY_MSCC
+   imply SIFIVE_SERIAL
+
+endif
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
new file mode 100644
index 00..702d803ad8
--- /dev/null
+++ b/board/sifive/fu540/MAINTAINERS
@@ -0,0 +1,9 @@
+SiFive FU540 BOARD
+M: Paul Walmsley 
+M: Palmer Dabbelt 
+M: Anup Patel 
+M: Atish Patra 
+S: Maintained
+F: board/sifive/fu540/
+F: include/configs/sifive-fu540.h
+F: configs/sifive_fu540_defconfig
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
new file mode 100644
index 00..6e1862c475
--- /dev/null
+++ b/board/sifive/fu540/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y  += fu540.o
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
new file mode 100644
index 00..5adc4a3d4a
--- /dev/null
+++ b/board/sifive/fu540/fu540.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#include 
+#include 
+
+int board_init(void)
+{
+   /* For now nothing to do here. */
+
+   return 0;
+}
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
new file mode 100644
index 00..2f8cca9de0
--- /dev/null
+++ b/configs/sifive_fu540_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_RISCV_SMODE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_MII=y
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
new file mode 100644
index 00..7007b5f6af
--- /dev/null
+++ b/include/configs/sifive-fu540.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include 
+
+#define CONFIG_SYS_SDRAM_BASE  0x8000
+#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN  SZ_8M
+
+#define CONFIG_

Re: [U-Boot] [PATCH] spl: fat/fs: Add control to build FS EXT4 in SPL

On Thu, Jan 17, 2019 at 03:01:49PM +0800, tien.fong.c...@intel.com wrote:

> From: Tien Fong Chee 
> 
> CONFIG_SPL_EXT_SUPPORT can be used to include/exclude the FS EXT4 from
> SPL build. Excluding the FS EXT4 from SPL build can help to save 20KiB
> memory.
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  fs/fs.c |4 +++-
>  1 files changed, 3 insertions(+), 1 deletions(-)
> 
> diff --git a/fs/fs.c b/fs/fs.c
> index 0b8088b..252e2f5 100644
> --- a/fs/fs.c
> +++ b/fs/fs.c
> @@ -184,7 +184,9 @@ static struct fstype_info fstypes[] = {
>   .closedir = fat_closedir,
>   },
>  #endif
> -#ifdef CONFIG_FS_EXT4
> +/* #ifdef CONFIG_FS_EXT4 */
> +#if (!defined(CONFIG_SPL_BUILD) && defined(CONFIG_FS_EXT4)) || \
> + (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_EXT_SUPPORT))
>   {
>   .fstype = FS_TYPE_EXT,
>   .name = "ext4",

This should be CONFIG_IS_ENABLED(FS_EXT4) in a 2/2 patch with a 1/2
patch renaming SPL_EXT_SUPPORT TO SPL_FS_EXT4, thanks!

-- 
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[U-Boot] [PATCH 09/11] drivers: serial: serial_sifive: Skip baudrate config if no input clock

From: Atish Patra 

It is possible that input clock is not available because clk
device was not available and 'clock-frequency' DT property is
also not available.

In this case, instead of failing we should just skip baudrate
config by returning zero.

Signed-off-by: Atish Patra 
Signed-off-by: Anup Patel 
---
 drivers/serial/serial_sifive.c | 32 
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index ea4d35d48c..537bc7a975 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -99,27 +99,27 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
 
 static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
 {
-   int err;
+   int ret;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+   u32 clock = 0;
 
-   err = clk_get_by_index(dev, 0, &clk);
-   if (!err) {
-   err = clk_get_rate(&clk);
-   if (!IS_ERR_VALUE(err))
-   platdata->clock = err;
-   } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+   ret = clk_get_by_index(dev, 0, &clk);
+   if (IS_ERR_VALUE(ret)) {
debug("SiFive UART failed to get clock\n");
-   return err;
-   }
-
-   if (!platdata->clock)
-   platdata->clock = dev_read_u32_default(dev, "clock-frequency", 
0);
-   if (!platdata->clock) {
-   debug("SiFive UART clock not defined\n");
-   return -EINVAL;
+   ret = dev_read_u32(dev, "clock-frequency", &clock);
+   if (IS_ERR_VALUE(ret)) {
+   debug("SiFive UART clock not defined\n");
+   return 0;
+   }
+   } else {
+   clock = clk_get_rate(&clk);
+   if (IS_ERR_VALUE(clock)) {
+   debug("SiFive UART clock get rate failed\n");
+   return 0;
+   }
}
-
+   platdata->clock = clock;
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
 
return 0;
-- 
2.17.1

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[U-Boot] board/amlogic/odroid-c2/README - how to make the instructions more portable?

2019-01-17 Thread Martin Husemann

Hi folks,

I am trying to get a new u-boot on my Odroid C2 following the instructions
in board/amlogic/odroid-c2/README.

Unfortunately these tell me to use not only the vendor provided blobs, but
also their tools. This is painfull: 

file $DIR/fip/fip_create
odroid-c2/fip/fip_create: ELF 64-bit LSB executable, x86-64, version 1 (SYSV), 
dynamically linked, interpreter /lib64/ld-linux-x86-64.so.2, for GNU/Linux 
2.6.32, BuildID[sha1]=0dc4b0e1bd118ffc3c0f77e815b6d86acc1f25c2, not stripped

so I need to set up an environment where I can run that.

There are alternatives, so the instructions should probably be updated to
use them. I have "fiptool" from ARM trusted firmware v2.0, and
"fiptool create" should be able to do what fip_create did. Also I have
meson-tools installed, providing amlbootsig which could replace 
aml_encrypt_gxb.

Has someone used these alternate tools instead of the vendor binaries?
How do the fip_create options from the README translate to fiptool?

Martin
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[U-Boot] [PATCH 08/11] drivers: serial_sifive: Fix baud rate calculation

From: Atish Patra 

Compute the baud rate multipler with more precision.

Signed-off-by: Atish Patra 
---
 drivers/serial/serial_sifive.c | 28 ++--
 1 file changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index 341728a690..ea4d35d48c 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -33,16 +33,40 @@ struct uart_sifive {
 };
 
 struct sifive_uart_platdata {
-   unsigned int clock;
+   unsigned long clock;
int saved_input_char;
struct uart_sifive *regs;
 };
 
+/**
+ * Find minimum divisor divides in_freq to max_target_hz;
+ * Based on uart driver n SiFive FSBL.
+ *
+ * f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
+ * The nearest integer solution requires rounding up as to not exceed
+ * max_target_hz.
+ * div  = ceil(f_in / f_baud) - 1
+ * = floor((f_in - 1 + f_baud) / f_baud) - 1
+ * This should not overflow as long as (f_in - 1 + f_baud) does not exceed
+ * 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ */
+static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
+   unsigned long max_target_hz)
+{
+   unsigned long quotient =
+   (in_freq + max_target_hz - 1) / (max_target_hz);
+   /* Avoid underflow */
+   if (quotient == 0)
+   return 0;
+   else
+   return quotient - 1;
+}
+
 /* Set up the baud rate in gd struct */
 static void _sifive_serial_setbrg(struct uart_sifive *regs,
  unsigned long clock, unsigned long baud)
 {
-   writel((u32)((clock / baud) - 1), ®s->div);
+   writel((uart_min_clk_divisor(clock, baud)), ®s->div);
 }
 
 static void _sifive_serial_init(struct uart_sifive *regs)
-- 
2.17.1

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[U-Boot] [PATCH 10/11] cpu: Bind timer driver for boot hart

From: Atish Patra 

Currently, timer driver is bound only for hart0.

There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.

The timer driver should be bound for boot hart.

Signed-off-by: Atish Patra 
---
 drivers/cpu/riscv_cpu.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5e15df590e..f77c126499 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -10,6 +10,8 @@
 #include 
 #include 
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
 {
const char *isa;
@@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev)
 
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
-
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
/* if not found, then look at the parent /cpus node */
@@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev)
 &plat->timebase_freq);
 
/*
-* Bind riscv-timer driver on hart 0
+* Bind riscv-timer driver on boot hart.
 *
 * We only instantiate one timer device which is enough for U-Boot.
 * Pass the "timebase-frequency" value as the driver data for the
@@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev)
 * Return value is not checked since it's possible that the timer
 * driver is not included.
 */
-   if (!plat->cpu_id && plat->timebase_freq) {
+   if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
drv = lists_driver_lookup_name("riscv_timer");
if (!drv) {
debug("Cannot find the timer driver, not included?\n");
-- 
2.17.1

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Re: [U-Boot] [PATCH] spl: fat/fs: Add option to include/exclude FAT write build in SPL

On Thu, Jan 17, 2019 at 08:54:48AM +0100, Simon Goldschmidt wrote:
> On Thu, Jan 17, 2019 at 8:10 AM  wrote:
> >
> > From: Tien Fong Chee 
> >
> > Most of the time SPL only needs very simple FAT reading, so having
> > CONFIG_SPL_FAT_WRITE to exclude or undefined would help to save 64KiB
> > default max clustersize from memory.
> >
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  common/spl/Kconfig |7 +++
> >  fs/fat/Makefile|7 ++-
> >  fs/fat/fat.c   |4 +++-
> >  fs/fs.c|3 ++-
> >  4 files changed, 18 insertions(+), 3 deletions(-)
> >
> > diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> > index 0ddbffc..dad4c11 100644
> > --- a/common/spl/Kconfig
> > +++ b/common/spl/Kconfig
> > @@ -403,6 +403,13 @@ config SPL_FAT_SUPPORT
> >   filesystem from within SPL. Support for the underlying block
> >   device (e.g. MMC or USB) must be enabled separately.
> >
> > +config SPL_FAT_WRITE
> > +   bool "Support write for FAT filesystems"
> > +   help
> > + Enable write support for FAT and VFAT filesystems with SPL.
> > + Support for the underlying block device (e.g. MMC or USB) must be
> > + enabled separately.
> > +
> >  config SPL_FPGA_SUPPORT
> > bool "Support FPGAs"
> > help
> > diff --git a/fs/fat/Makefile b/fs/fat/Makefile
> > index e64b61a..654b8c3 100644
> > --- a/fs/fat/Makefile
> > +++ b/fs/fat/Makefile
> > @@ -1,5 +1,10 @@
> >  # SPDX-License-Identifier: GPL-2.0+
> >  #
> >
> > +ifdef CONFIG_SPL_BUILD
> >  obj-$(CONFIG_FS_FAT)   := fat.o
> > -obj-$(CONFIG_FAT_WRITE):= fat_write.o
> > +obj-$(CONFIG_SPL_FAT_WRITE) = fat_write.o
> > +else
> > +obj-$(CONFIG_FS_FAT)   := fat.o
> > +obj-$(CONFIG_FAT_WRITE) = fat_write.o

Like the ext4 one, we need a patch to rename SPL_FAT_SUPPORT to
SPL_FS_FAT and then:

obj-$(CONFIG_$(SPL_)FS_FAT) += fat.o
obj-$(CONFIG_$(SPL_)FAT_WRITE) += fat_write.o

> > +endif
> > diff --git a/fs/fat/fat.c b/fs/fat/fat.c
> > index ac8913e..8803fb4 100644
> > --- a/fs/fat/fat.c
> > +++ b/fs/fat/fat.c
> > @@ -145,7 +145,9 @@ static void get_name(dir_entry *dirent, char *s_name)
> >  }
> >
> >  static int flush_dirty_fat_buffer(fsdata *mydata);
> > -#if !defined(CONFIG_FAT_WRITE)
> > +
> > +#if (!defined(CONFIG_SPL_BUILD) && !defined(CONFIG_FAT_WRITE)) || \
> > +   (defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_FAT_WRITE))
> 
> What about 'CONFIG_IS_ENABLED(FAT_WRITE)' ?

Yes, CONFIG_IS_ENABLED(FAT_WRITE) please.

-- 
Tom


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[U-Boot] [PATCH] MTD: nand: mxs_nand: Allow driver to auto setup ECC in SPL

2019-01-17 Thread Adam Ford

The initialization of the NAND in SPL hard-coded ecc.bytes,
ecc.size, and ecc.strength which may work for some NAND parts,
but it not appropriate for others.  With the pending patch
"mxs_nand: Fix BCH read timeout error on boards requiring ECC"
the driver can auto configure the ECC when these entries are
blank.  This patch has been tested in NAND flash with oob 64
and oob 128.

Signed-off-by: Adam Ford 

diff --git a/drivers/mtd/nand/raw/mxs_nand.c b/drivers/mtd/nand/raw/mxs_nand.c
index 2d84bfffe2..95fa452cef 100644
--- a/drivers/mtd/nand/raw/mxs_nand.c
+++ b/drivers/mtd/nand/raw/mxs_nand.c
@@ -1191,9 +1191,6 @@ int mxs_nand_init_spl(struct nand_chip *nand)
nand->ecc.read_page = mxs_nand_ecc_read_page;
 
nand->ecc.mode  = NAND_ECC_HW;
-   nand->ecc.bytes = 9;
-   nand->ecc.size  = 512;
-   nand->ecc.strength  = 8;
 
return 0;
 }
-- 
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Re: [U-Boot] board/amlogic/odroid-c2/README - how to make the instructions more portable?

2019-01-17 Thread Neil Armstrong

Hi Martin,

On 17/01/2019 13:22, Martin Husemann wrote:
> Hi folks,
> 
> I am trying to get a new u-boot on my Odroid C2 following the instructions
> in board/amlogic/odroid-c2/README.
> 
> Unfortunately these tell me to use not only the vendor provided blobs, but
> also their tools. This is painfull: 
> 
> file $DIR/fip/fip_create
> odroid-c2/fip/fip_create: ELF 64-bit LSB executable, x86-64, version 1 
> (SYSV), dynamically linked, interpreter /lib64/ld-linux-x86-64.so.2, for 
> GNU/Linux 2.6.32, BuildID[sha1]=0dc4b0e1bd118ffc3c0f77e815b6d86acc1f25c2, not 
> stripped
> 
> so I need to set up an environment where I can run that.
> 
> There are alternatives, so the instructions should probably be updated to
> use them. I have "fiptool" from ARM trusted firmware v2.0, and
> "fiptool create" should be able to do what fip_create did. Also I have
> meson-tools installed, providing amlbootsig which could replace 
> aml_encrypt_gxb.
> 
> Has someone used these alternate tools instead of the vendor binaries?
> How do the fip_create options from the README translate to fiptool?

Yes, Andreas Faerber has developed some tools for that : 
https://github.com/afaerber/meson-tools

You are free to join #linux-amlogic on Freenode and open source the missing 
bits,
but for now we haven't got issues with the ATF binary blobs provided by Amlogic 
and
we focused to have a clean and stable implementation of U-Boot & Linux.

The BL31 has already landed on ARM ATF repo : 
https://github.com/ARM-software/arm-trusted-firmware/tree/master/plat/meson/gxbb

Seems a couple of hackers are trying to reverse-engineer the BL2 and SCPI blobs,
but it's a complex job...

But note the GXBB SoC on he Odroid-C2 is deprecated and not supported anymore 
by Amlogic,
we focus mainly on the new platforms while trying to maintain the GXBB SoCs 
working
with the new features introduced.

Neil

> 
> Martin
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Re: [U-Boot] u-boot-fw-utils issue

2019-01-17 Thread Heiko Schocher

Hello Hardik Padhariya,

Am 09.01.2019 um 09:14 schrieb Hardik Padhariya:

Hello,

We are trying to access uboot variables from our application running over
Linux.

We are using Yocto krogoth 2.1.1 for imx6ul evaluation kit
"mx6ul_14x14_evk".

We have built u-boot-fw-utils by adding "CORE_IMAGE_EXTRA_INSTALL +=
"u-boot-fw-utils" in the local.conf file.

Issues:

1. We are unable to update the existing uboot delay from the user space. We
have tried updating it but it is not reflected once we reboot the device.

2. We are unable to add the new variables in uboot. When we execute
"fw_setenv board_name evalkit" then we can see it using fw_printenv but
after rebooting the device when we check the boot variables using the
command "printenv" (uboot command interface) then the variable is not shown.

3. We also tried adding the variable through CONFIG_EXTRA_ENV_SETTINGS in
mx6ul_14x14_evk.h at ./tmp/work/../../include/configs/ but it is also not
shown when we use fw_printenv command.

We get warning " Bad CRC, using default environment" if we try to set any
variable using fw_setenv.

This means, that your fw_printenv util does not find the U-Boot
environment on your env storage device.

Yoiu have to add a "/etc/fw_env.config" file, which fit with your
device. See for some examples:

http://git.denx.de/?p=u-boot.git;a=blob;f=tools/env/fw_env.config;h=053895a2c07b23891e098c2370066204f04b8ea1;hb=aac0c29d4b8418c5c78b552070ffeda022b16949

I do not know the exact values for "mx6ul_14x14_evk" ...

bye,
Heiko
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[U-Boot] [PATCH 2/2] arm: mvebu: armada-xp/37x/38x: Enable PCIe DT node

2019-01-17 Thread Stefan Roese

This patch enables the DT PCIe nodes for the Armada XP/37x/38x boards.
This is needed for the new DM_PCI support in the MVEBU PCIe driver.

Signed-off-by: Stefan Roese 
Cc: Dirk Eibach 
Cc: Mario Six 
Cc: Chris Packham 
Cc: Phil Sutter 
Cc: Marek Behún 
Cc: VlaoMao 
---
 arch/arm/dts/armada-375.dtsi| 2 +-
 arch/arm/dts/armada-380.dtsi| 2 +-
 arch/arm/dts/armada-385.dtsi| 2 +-
 arch/arm/dts/armada-xp-mv78230.dtsi | 2 +-
 arch/arm/dts/armada-xp-mv78260.dtsi | 2 +-
 arch/arm/dts/armada-xp-mv78460.dtsi | 2 +-
 6 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/dts/armada-375.dtsi b/arch/arm/dts/armada-375.dtsi
index 249c41c757..7b2723cdf2 100644
--- a/arch/arm/dts/armada-375.dtsi
+++ b/arch/arm/dts/armada-375.dtsi
@@ -584,7 +584,7 @@
 
pcie-controller {
compatible = "marvell,armada-370-pcie";
-   status = "disabled";
+   status = "okay";
device_type = "pci";
 
#address-cells = <3>;
diff --git a/arch/arm/dts/armada-380.dtsi b/arch/arm/dts/armada-380.dtsi
index 5102d19cc8..95c8a1bae0 100644
--- a/arch/arm/dts/armada-380.dtsi
+++ b/arch/arm/dts/armada-380.dtsi
@@ -73,7 +73,7 @@
 
pcie-controller {
compatible = "marvell,armada-370-pcie";
-   status = "disabled";
+   status = "okay";
device_type = "pci";
 
#address-cells = <3>;
diff --git a/arch/arm/dts/armada-385.dtsi b/arch/arm/dts/armada-385.dtsi
index 8e67d2c083..d1d277e165 100644
--- a/arch/arm/dts/armada-385.dtsi
+++ b/arch/arm/dts/armada-385.dtsi
@@ -78,7 +78,7 @@
 
pcie-controller {
compatible = "marvell,armada-370-pcie";
-   status = "disabled";
+   status = "enabled";
device_type = "pci";
 
#address-cells = <3>;
diff --git a/arch/arm/dts/armada-xp-mv78230.dtsi 
b/arch/arm/dts/armada-xp-mv78230.dtsi
index 6e6d0f04bf..d750ac1f6f 100644
--- a/arch/arm/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/dts/armada-xp-mv78230.dtsi
@@ -88,7 +88,7 @@
 */
pcie-controller {
compatible = "marvell,armada-xp-pcie";
-   status = "disabled";
+   status = "okay";
device_type = "pci";
 
#address-cells = <3>;
diff --git a/arch/arm/dts/armada-xp-mv78260.dtsi 
b/arch/arm/dts/armada-xp-mv78260.dtsi
index c5fdc99f0d..50d3716b96 100644
--- a/arch/arm/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/dts/armada-xp-mv78260.dtsi
@@ -89,7 +89,7 @@
 */
pcie-controller {
compatible = "marvell,armada-xp-pcie";
-   status = "disabled";
+   status = "okay";
device_type = "pci";
 
#address-cells = <3>;
diff --git a/arch/arm/dts/armada-xp-mv78460.dtsi 
b/arch/arm/dts/armada-xp-mv78460.dtsi
index 0e24f1a385..5921f41264 100644
--- a/arch/arm/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/dts/armada-xp-mv78460.dtsi
@@ -106,7 +106,7 @@
 */
pcie-controller {
compatible = "marvell,armada-xp-pcie";
-   status = "disabled";
+   status = "okay";
device_type = "pci";
 
#address-cells = <3>;
-- 
2.20.1

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[U-Boot] [PATCH 1/2] pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig

2019-01-17 Thread Stefan Roese

This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.

To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.

Signed-off-by: Stefan Roese 
Cc: Dirk Eibach 
Cc: Mario Six 
Cc: Chris Packham 
Cc: Phil Sutter 
Cc: Marek Behún 
Cc: VlaoMao 
---
 configs/clearfog_defconfig  |   1 +
 configs/controlcenterdc_defconfig   |   3 +
 configs/db-88f6820-amc_defconfig|   1 +
 configs/db-88f6820-gp_defconfig |   1 +
 configs/db-mv784mp-gp_defconfig |   1 +
 configs/ds414_defconfig |   1 +
 configs/theadorable_debug_defconfig |   2 +
 configs/turris_omnia_defconfig  |   3 +-
 drivers/pci/Kconfig |   9 +
 drivers/pci/pci_mvebu.c | 329 ++--
 include/configs/clearfog.h  |   1 -
 include/configs/controlcenterdc.h   |   3 -
 include/configs/db-88f6820-amc.h|   1 -
 include/configs/db-88f6820-gp.h |   1 -
 include/configs/db-mv784mp-gp.h |   1 -
 include/configs/ds414.h |   1 -
 include/configs/theadorable.h   |   7 -
 include/configs/turris_omnia.h  |   1 -
 scripts/config_whitelist.txt|   1 -
 19 files changed, 236 insertions(+), 132 deletions(-)

diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig
index e1c5a1fa13..0f69ff606d 100644
--- a/configs/clearfog_defconfig
+++ b/configs/clearfog_defconfig
@@ -56,6 +56,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/configs/controlcenterdc_defconfig 
b/configs/controlcenterdc_defconfig
index 0c762ad77c..f22a3ab819 100644
--- a/configs/controlcenterdc_defconfig
+++ b/configs/controlcenterdc_defconfig
@@ -58,6 +58,9 @@ CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/configs/db-88f6820-amc_defconfig b/configs/db-88f6820-amc_defconfig
index 9068a58406..03bf2bcafc 100644
--- a/configs/db-88f6820-amc_defconfig
+++ b/configs/db-88f6820-amc_defconfig
@@ -60,6 +60,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig
index 413010c4ef..b36b7c3b2c 100644
--- a/configs/db-88f6820-gp_defconfig
+++ b/configs/db-88f6820-gp_defconfig
@@ -56,6 +56,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_SCSI=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
diff --git a/configs/db-mv784mp-gp_defconfig b/configs/db-mv784mp-gp_defconfig
index 3f140986b6..b6c61c3a48 100644
--- a/configs/db-mv784mp-gp_defconfig
+++ b/configs/db-mv784mp-gp_defconfig
@@ -55,6 +55,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/ds414_defconfig b/configs/ds414_defconfig
index 5325bd9968..32f37440c3 100644
--- a/configs/ds414_defconfig
+++ b/configs/ds414_defconfig
@@ -52,6 +52,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/theadorable_debug_defconfig 
b/configs/theadorable_debug_defconfig
index 9e99618998..ac6dfd6844 100644
--- a/configs/theadorable_debug_defconfig
+++ b/configs/theadorable_debug_defconfig
@@ -62,6 +62,8 @@ CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
 CONFIG_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCI_MVEBU=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 4a1e23c86c..5cafe2ee34 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -37,7 +37,6 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-turris-omnia"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_SCSI_AHCI=y
-CONFIG_MISC=y
 CONFIG_ATSHA204A=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_MV=y
@@ -45,6 +44,8 @@ CONFIG_PHY_MARVELL=y
 CONFIG_PHY_GIGE=y
 CONFIG_MVNETA=y
 CONFIG_MII=y
+CONFIG_PCI=y
+CONFIG_PCI_MVEBU=y
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYS_NS16550=y
 CONFIG_KIRKWOOD_SPI=y
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index f59803dbd6..1521885bde 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -112,4 +112,13 @@ config PCIE_INTEL_FPGA
  Say Y here if you want to enable PCIe controller support on Intel
  FPGA, example Stratix 10.
 
+config PCI_MVEBU
+   bool "Enable Armada XP/38x PCIe driver"
+   depends on ARCH_MVEBU
+   select DM_PCI
+   select MISC
+   help
+ Say

Re: [U-Boot] [U-Boot, v2, 4/7] ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point

2019-01-17 Thread Andrew F. Davis

On 1/16/19 3:14 PM, Tom Rini wrote:
> On Wed, Dec 05, 2018 at 11:51:33AM -0600, Andrew F. Davis wrote:
> 
>> Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to
>> have an non-standard boot address in memory. This may be due
>> to the device being a high security variant, which place the
>> Initial SoftWare (ISW) after certificates and secure software.
>>
>> Allow these devices to set this from Kconfig.
>>
>> Signed-off-by: Andrew F. Davis 
>> Reviewed-by: Tom Rini 
>> ---
>>  arch/arm/mach-omap2/Kconfig| 13 +
>>  arch/arm/mach-omap2/am33xx/Kconfig | 15 ---
>>  include/configs/ti_omap5_common.h  |  2 +-
>>  3 files changed, 14 insertions(+), 16 deletions(-)
> 
> Turns out this breaks OMAP3 among others as the question is asked there
> now and we have no default value (nor I suspect a reasonable one).

The only thing changed is ti_omap5_common.h, the default provided in
that file is 0x40301350, would it be okay to just make that the default
for ISW_ENTRY_ADDR for all platforms that included that file?

Andrew

> Thanks!
> 
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Re: [U-Boot] [U-Boot, v2, 4/7] ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point

On Thu, Jan 17, 2019 at 08:13:21AM -0600, Andrew F. Davis wrote:
> On 1/16/19 3:14 PM, Tom Rini wrote:
> > On Wed, Dec 05, 2018 at 11:51:33AM -0600, Andrew F. Davis wrote:
> > 
> >> Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to
> >> have an non-standard boot address in memory. This may be due
> >> to the device being a high security variant, which place the
> >> Initial SoftWare (ISW) after certificates and secure software.
> >>
> >> Allow these devices to set this from Kconfig.
> >>
> >> Signed-off-by: Andrew F. Davis 
> >> Reviewed-by: Tom Rini 
> >> ---
> >>  arch/arm/mach-omap2/Kconfig| 13 +
> >>  arch/arm/mach-omap2/am33xx/Kconfig | 15 ---
> >>  include/configs/ti_omap5_common.h  |  2 +-
> >>  3 files changed, 14 insertions(+), 16 deletions(-)
> > 
> > Turns out this breaks OMAP3 among others as the question is asked there
> > now and we have no default value (nor I suspect a reasonable one).
> 
> The only thing changed is ti_omap5_common.h, the default provided in
> that file is 0x40301350, would it be okay to just make that the default
> for ISW_ENTRY_ADDR for all platforms that included that file?

Well, ISW_ENTRY_ADDR doesn't make sense for OMAP3, right?  I suspect the
problem is that in moving it from mach-omap2/am33xx/Kconfig to
mach-omap2/Kconfig you need to update the depends on guards so that it
doesn't show up where it's not used.

-- 
Tom


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Re: [U-Boot] [PATCH 2/3] mmc: hi6220_dw_mmc: add compatible for Poplar support

On Thu, Jan 17, 2019 at 12:09:51PM +0800, Shawn Guo wrote:
> It adds compatible "hisilicon,hi3798cv200-dw-mshc" for Poplar SoC
> Hi3798CV200 to probe this mmc driver.
> 
> Signed-off-by: Shawn Guo 

Acked-by: Manivannan Sadhasivam 

Thanks,
Mani

> ---
>  drivers/mmc/hi6220_dw_mmc.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
> index cc58aff38cc4..effd1e4c7c84 100644
> --- a/drivers/mmc/hi6220_dw_mmc.c
> +++ b/drivers/mmc/hi6220_dw_mmc.c
> @@ -77,6 +77,7 @@ static int hi6220_dwmmc_bind(struct udevice *dev)
>  
>  static const struct udevice_id hi6220_dwmmc_ids[] = {
>   { .compatible = "hisilicon,hi6220-dw-mshc" },
> + { .compatible = "hisilicon,hi3798cv200-dw-mshc" },
>   { }
>  };
>  
> -- 
> 2.18.0
> 
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[U-Boot] [PATCH v1 1/1] arm64: dt: poplar: add optee node

2019-01-17 Thread Igor Opaniuk

As Poplar supports running TF-A with OP-TEE as BL32
payload, add op-tee node in DT, which enables usage of
OP-TEE driver (which provides an interface for requesting services
from OP-TEE).

Signed-off-by: Igor Opaniuk 
---
 arch/arm/dts/hi3798cv200-poplar.dts | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/hi3798cv200-poplar.dts 
b/arch/arm/dts/hi3798cv200-poplar.dts
index 964326e..6bc2a23 100644
--- a/arch/arm/dts/hi3798cv200-poplar.dts
+++ b/arch/arm/dts/hi3798cv200-poplar.dts
@@ -28,6 +28,13 @@
reg = <0x0 0x0 0x0 0x8000>;
};
 
+   firmware {
+   optee {
+   compatible = "linaro,optee-tz";
+   method = "smc";
+   };
+   };
+
leds {
compatible = "gpio-leds";
 
-- 
2.7.4

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Re: [U-Boot] [PATCH 3/3] poplar: clean up board level mmc initialization code

On Thu, Jan 17, 2019 at 12:09:52PM +0800, Shawn Guo wrote:
> We have converted mmc to driver model on Poplar.  So let's clean up
> board level mmc initialization code.
> 
> Signed-off-by: Shawn Guo 

Acked-by: Manivannan Sadhasivam 

Thanks,
Mani

> ---
>  arch/arm/include/asm/arch-hi3798cv200/dwmmc.h   | 12 
>  arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h |  1 -
>  board/hisilicon/poplar/poplar.c | 12 
>  3 files changed, 25 deletions(-)
>  delete mode 100644 arch/arm/include/asm/arch-hi3798cv200/dwmmc.h
> 
> diff --git a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h 
> b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h
> deleted file mode 100644
> index d08c20b36d31..
> --- a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h
> +++ /dev/null
> @@ -1,12 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0+ */
> -/*
> - * (C) Copyright 2017 Linaro
> - * Jorge Ramirez-Ortiz 
> - */
> -
> -#ifndef _HI3798cv200_DWMMC_H_
> -#define _HI3798cv200_DWMMC_H_
> -
> -int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width);
> -
> -#endif /* _HI3798cv200_DWMMC_H_ */
> diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h 
> b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
> index bb221e17e0ed..b98b45cc817b 100644
> --- a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
> +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h
> @@ -11,7 +11,6 @@
>  #define REG_BASE_CRG 0xF8A22000
>  
>  /* DEVICES */
> -#define REG_BASE_MCI 0xF983
>  #define REG_BASE_UART0   0xF8B0
>  #define HIOTG_BASE_ADDR  0xF98C
>  
> diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c
> index 155dfbb401f1..77948445e261 100644
> --- a/board/hisilicon/poplar/poplar.c
> +++ b/board/hisilicon/poplar/poplar.c
> @@ -9,7 +9,6 @@
>  #include 
>  #include 
>  #include 
> -#include 
>  #include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
> @@ -155,17 +154,6 @@ static void usb2_phy_init(void)
>   udelay(200);
>  }
>  
> -int board_mmc_init(bd_t *bis)
> -{
> - int ret;
> -
> - ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8);
> - if (ret)
> - printf("mmc init error (%d)\n", ret);
> -
> - return ret;
> -}
> -
>  #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
>  #include 
>  #include 
> -- 
> 2.18.0
> 
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Re: [U-Boot] [PATCH 1/3] poplar: sync up device tree with kernel 4.20

Hi Shawn,

On Thu, Jan 17, 2019 at 12:09:50PM +0800, Shawn Guo wrote:
> It adds missing pinctrl headers, updates clock header and sync up Poplar
> device tree with kernel 4.20 release.
> 
> Signed-off-by: Shawn Guo 
> ---
>  arch/arm/dts/hi3798cv200-poplar.dts |  68 ++--
>  arch/arm/dts/hi3798cv200.dtsi   | 221 +++-
>  arch/arm/dts/poplar-pinctrl.dtsi|  98 +++
>  include/dt-bindings/clock/histb-clock.h |  56 +++---
>  include/dt-bindings/pinctrl/hisi.h  |  74 
>  5 files changed, 482 insertions(+), 35 deletions(-)
>  create mode 100644 arch/arm/dts/poplar-pinctrl.dtsi
>  create mode 100644 include/dt-bindings/pinctrl/hisi.h
> 
> diff --git a/arch/arm/dts/hi3798cv200-poplar.dts 
> b/arch/arm/dts/hi3798cv200-poplar.dts
> index 964326eae89b..d30f6eb8a5ee 100644
> --- a/arch/arm/dts/hi3798cv200-poplar.dts
> +++ b/arch/arm/dts/hi3798cv200-poplar.dts
> @@ -1,14 +1,17 @@
> -// SPDX-License-Identifier: GPL-2.0
>  /*
>   * DTS File for HiSilicon Poplar Development Board
>   *
>   * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * Released under the GPLv2 only.
> + * SPDX-License-Identifier: GPL-2.0

This is a malformed license identifier. Eventhough it is being imported
from Linux kernel, we need to fix this (on both).

>   */
>  
>  /dts-v1/;
>  
>  #include 
>  #include "hi3798cv200.dtsi"
> +#include "poplar-pinctrl.dtsi"
>  
>  / {
>   model = "HiSilicon Poplar Development Board";
> @@ -59,6 +62,33 @@
>   default-state = "off";
>   };
>   };
> +
> + reg_pcie: regulator-pcie {
> + compatible = "regulator-fixed";
> + regulator-name = "3V3_PCIE0";
> + regulator-min-microvolt = <330>;
> + regulator-max-microvolt = <330>;
> + gpio = <&gpio6 7 0>;
> + enable-active-high;
> + };
> +};
> +
> +&ehci {
> + status = "okay";
> +};
> +
> +&emmc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
> +  &emmc_pins_3 &emmc_pins_4>;
> + fifo-depth = <256>;
> + clock-frequency = <2>;
> + cap-mmc-highspeed;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + non-removable;
> + bus-width = <8>;
> + status = "okay";
>  };
>  
>  &gmac1 {
> @@ -76,17 +106,17 @@
>  
>  &gpio1 {
>   status = "okay";
> - gpio-line-names = "LS-GPIO-E",  "",
> + gpio-line-names = "GPIO-E", "",
> "",   "",
> -   "",   "LS-GPIO-F",
> -   "",   "LS-GPIO-J";
> +   "",   "GPIO-F",
> +   "",   "GPIO-J";
>  };
>  
>  &gpio2 {
>   status = "okay";
> - gpio-line-names = "LS-GPIO-H",  "LS-GPIO-I",
> -   "LS-GPIO-L",  "LS-GPIO-G",
> -   "LS-GPIO-K",  "",
> + gpio-line-names = "GPIO-H", "GPIO-I",
> +   "GPIO-L", "GPIO-G",
> +   "GPIO-K", "",
> "",   "";
>  };
>  
> @@ -94,15 +124,15 @@
>   status = "okay";
>   gpio-line-names = "",   "",
> "",   "",
> -   "LS-GPIO-C",  "",
> -   "",   "LS-GPIO-B";
> +   "GPIO-C", "",
> +   "",   "GPIO-B";
>  };
>  
>  &gpio4 {
>   status = "okay";
>   gpio-line-names = "",   "",
> "",   "",
> -   "",   "LS-GPIO-D",
> +   "",   "GPIO-D",
> "",   "";
>  };
>  
> @@ -110,7 +140,7 @@
>   status = "okay";
>   gpio-line-names = "",   "USER-LED-1",
> "USER-LED-2", "",
> -   "",   "LS-GPIO-A",
> +   "",   "GPIO-A",
> "",   "";
>  };
>  
> @@ -144,6 +174,22 @@
>   status = "okay";
>  };
>  
> +&ohci {
> + status = "okay";
> +};
> +
> +&pcie {
> + reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
> + vpcie-supply = <®_pcie>;
> + status = "okay";
> +};
> +
> +&sd0 {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + status = "okay";
> +};
> +
>  &spi0 {
>   status = "okay";
>   label = "LS-SPI0";
> diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi
> index 8b9c5ad05a19..7c0fddd7c8cf 100644
> --- a/arch/arm/dts/hi3798cv200.dtsi
> +++ b/arch/arm/dts/hi3798cv200.dtsi
> @@ -1,12 +1,16 @@
> -// SPDX-License-Identifier: GPL-2.0
>  /*
>   * DTS File for HiSilicon Hi3798cv200 SoC.
>   *
>   * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
> + *
> + * Released under the GPLv2 only.
> + * SPDX-License-Identifier: GPL-2.0

Same as above.

>   */
>  
>  #include 
> +#include 
>  #include 
> +#include 
>  #include

[U-Boot] [PATCH v2 0/3] MSCC: Add Servalt SoC family

This patch series adds support for MSCC Servalt SoC family. In this
family there is only one board: Servalt(pcb116).

This is based off the u-boot-mips/next repository

v2-changes:
  - rename label for gpio in dts.

Horatiu Vultur (3):
  pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.
  MSCC: Add support for Servalt SoC family.
  MSCC: Add board support for Servalt SoC family

 arch/mips/dts/Makefile |   1 +
 arch/mips/dts/mscc,servalt.dtsi| 149 ++
 arch/mips/dts/servalt_pcb116.dts   |  56 
 arch/mips/mach-mscc/Kconfig|   8 +
 arch/mips/mach-mscc/cpu.c  |   2 +-
 arch/mips/mach-mscc/dram.c |   3 +-
 arch/mips/mach-mscc/include/mach/common.h  |   5 +
 arch/mips/mach-mscc/include/mach/ddr.h |  22 +-
 arch/mips/mach-mscc/include/mach/servalt/servalt.h |  24 ++
 .../include/mach/servalt/servalt_devcpu_gcb.h  |  20 ++
 .../mach/servalt/servalt_devcpu_gcb_miim_regs.h|  25 ++
 .../include/mach/servalt/servalt_icpu_cfg.h| 319 +
 arch/mips/mach-mscc/reset.c|   2 +-
 board/mscc/servalt/Kconfig |  14 +
 board/mscc/servalt/Makefile|   3 +
 board/mscc/servalt/servalt.c   |  52 
 configs/mscc_servalt_defconfig |  60 
 drivers/pinctrl/mscc/Kconfig   |   9 +
 drivers/pinctrl/mscc/Makefile  |   1 +
 drivers/pinctrl/mscc/pinctrl-servalt.c | 269 +
 20 files changed, 1033 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/dts/mscc,servalt.dtsi
 create mode 100644 arch/mips/dts/servalt_pcb116.dts
 create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt.h
 create mode 100644 
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h
 create mode 100644 
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h
 create mode 100644 board/mscc/servalt/Kconfig
 create mode 100644 board/mscc/servalt/Makefile
 create mode 100644 board/mscc/servalt/servalt.c
 create mode 100644 configs/mscc_servalt_defconfig
 create mode 100644 drivers/pinctrl/mscc/pinctrl-servalt.c

-- 
2.7.4

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[U-Boot] [PATCH v2 1/3] pinctrl: mscc: Add gpio and pinctrl for Servalt SoC family.

The Servalt SoC family has 36 pins. Currently there is not support
for Servalt pinctrl in Linux kernel.

Reviewed-by: Daniel Schwierzeck 
Signed-off-by: Horatiu Vultur 
---
 drivers/pinctrl/mscc/Kconfig   |   9 ++
 drivers/pinctrl/mscc/Makefile  |   1 +
 drivers/pinctrl/mscc/pinctrl-servalt.c | 269 +
 3 files changed, 279 insertions(+)
 create mode 100644 drivers/pinctrl/mscc/pinctrl-servalt.c

diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
index d07ea1b..0269565 100644
--- a/drivers/pinctrl/mscc/Kconfig
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -29,3 +29,12 @@ config PINCTRL_MSCC_JR2
help
Support pin multiplexing and pin configuration control on
Microsemi jr2 SoCs.
+
+config PINCTRL_MSCC_SERVALT
+   depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL
+   select PINCTRL_MSCC
+   default y
+   bool "Microsemi servalt family pin control driver"
+   help
+   Support pin multiplexing and pin configuration control on
+   Microsemi servalt SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
index 8038d54..c6b0373 100644
--- a/drivers/pinctrl/mscc/Makefile
+++ b/drivers/pinctrl/mscc/Makefile
@@ -4,3 +4,4 @@ obj-y += mscc-common.o
 obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
 obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
 obj-$(CONFIG_PINCTRL_MSCC_JR2) += pinctrl-jr2.o
+obj-$(CONFIG_PINCTRL_MSCC_SERVALT) += pinctrl-servalt.o
diff --git a/drivers/pinctrl/mscc/pinctrl-servalt.c 
b/drivers/pinctrl/mscc/pinctrl-servalt.c
new file mode 100644
index 000..592b7c5
--- /dev/null
+++ b/drivers/pinctrl/mscc/pinctrl-servalt.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author: 
+ * Copyright (c) 2019 Microsemi Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "mscc-common.h"
+
+enum {
+   FUNC_NONE,
+   FUNC_GPIO,
+   FUNC_IRQ0_IN,
+   FUNC_IRQ0_OUT,
+   FUNC_IRQ1_IN,
+   FUNC_IRQ1_OUT,
+   FUNC_MIIM1,
+   FUNC_MIIM2,
+   FUNC_PCI_WAKE,
+   FUNC_PTP0,
+   FUNC_PTP1,
+   FUNC_PTP2,
+   FUNC_PTP3,
+   FUNC_PWM,
+   FUNC_RCVRD_CLK0,
+   FUNC_RCVRD_CLK1,
+   FUNC_RCVRD_CLK2,
+   FUNC_RCVRD_CLK3,
+   FUNC_REF_CLK0,
+   FUNC_REF_CLK1,
+   FUNC_REF_CLK2,
+   FUNC_REF_CLK3,
+   FUNC_SFP0,
+   FUNC_SFP1,
+   FUNC_SFP2,
+   FUNC_SFP3,
+   FUNC_SFP4,
+   FUNC_SFP5,
+   FUNC_SFP6,
+   FUNC_SFP7,
+   FUNC_SFP8,
+   FUNC_SFP9,
+   FUNC_SFP10,
+   FUNC_SFP11,
+   FUNC_SFP12,
+   FUNC_SFP13,
+   FUNC_SFP14,
+   FUNC_SFP15,
+   FUNC_SIO,
+   FUNC_SPI,
+   FUNC_TACHO,
+   FUNC_TWI,
+   FUNC_TWI2,
+   FUNC_TWI_SCL_M,
+   FUNC_UART,
+   FUNC_UART2,
+   FUNC_MAX
+};
+
+static char * const servalt_function_names[] = {
+   [FUNC_NONE] = "none",
+   [FUNC_GPIO] = "gpio",
+   [FUNC_IRQ0_IN]  = "irq0_in",
+   [FUNC_IRQ0_OUT] = "irq0_out",
+   [FUNC_IRQ1_IN]  = "irq1_in",
+   [FUNC_IRQ1_OUT] = "irq1_out",
+   [FUNC_MIIM1]= "miim1",
+   [FUNC_MIIM2]= "miim2",
+   [FUNC_PCI_WAKE] = "pci_wake",
+   [FUNC_PTP0] = "ptp0",
+   [FUNC_PTP1] = "ptp1",
+   [FUNC_PTP2] = "ptp2",
+   [FUNC_PTP3] = "ptp3",
+   [FUNC_PWM]  = "pwm",
+   [FUNC_RCVRD_CLK0]   = "rcvrd_clk0",
+   [FUNC_RCVRD_CLK1]   = "rcvrd_clk1",
+   [FUNC_RCVRD_CLK2]   = "rcvrd_clk2",
+   [FUNC_RCVRD_CLK3]   = "rcvrd_clk3",
+   [FUNC_REF_CLK0] = "ref_clk0",
+   [FUNC_REF_CLK1] = "ref_clk1",
+   [FUNC_REF_CLK2] = "ref_clk2",
+   [FUNC_REF_CLK3] = "ref_clk3",
+   [FUNC_SFP0] = "sfp0",
+   [FUNC_SFP1] = "sfp1",
+   [FUNC_SFP2] = "sfp2",
+   [FUNC_SFP3] = "sfp3",
+   [FUNC_SFP4] = "sfp4",
+   [FUNC_SFP5] = "sfp5",
+   [FUNC_SFP6] = "sfp6",
+   [FUNC_SFP7] = "sfp7",
+   [FUNC_SFP8] = "sfp8",
+   [FUNC_SFP9] = "sfp9",
+   [FUNC_SFP10]= "sfp10",
+   [FUNC_SFP11]= "sfp11",
+   [FUNC_SFP12]= "sfp12",
+   [FUNC_SFP13]= "sfp13",
+   [FUNC_SFP14]= "sfp14",
+   [FUNC_SFP15]= "sfp15",
+   [FUNC_SIO]  = "sio",
+   [FUNC_SPI]  = "spi",
+   [FUNC_TACHO]= "tacho",
+   [FUNC_TWI]  = "twi",
+   [FUNC_TWI2] = "twi2",
+   [FUNC_TWI_SCL_M]= "twi_scl_m",
+

[U-Boot] [PATCH v2 2/3] MSCC: Add support for Servalt SoC family.

As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.

Reviewed-by: Daniel Schwierzeck 
Signed-off-by: Horatiu Vultur 
---
 arch/mips/mach-mscc/Kconfig|   8 +
 arch/mips/mach-mscc/cpu.c  |   2 +-
 arch/mips/mach-mscc/dram.c |   3 +-
 arch/mips/mach-mscc/include/mach/common.h  |   5 +
 arch/mips/mach-mscc/include/mach/ddr.h |  22 +-
 arch/mips/mach-mscc/include/mach/servalt/servalt.h |  24 ++
 .../include/mach/servalt/servalt_devcpu_gcb.h  |  20 ++
 .../mach/servalt/servalt_devcpu_gcb_miim_regs.h|  25 ++
 .../include/mach/servalt/servalt_icpu_cfg.h| 319 +
 arch/mips/mach-mscc/reset.c|   2 +-
 10 files changed, 419 insertions(+), 11 deletions(-)
 create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt.h
 create mode 100644 
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb.h
 create mode 100644 
arch/mips/mach-mscc/include/mach/servalt/servalt_devcpu_gcb_miim_regs.h
 create mode 100644 arch/mips/mach-mscc/include/mach/servalt/servalt_icpu_cfg.h

diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index fc6aa03..80e4b44 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -40,6 +40,13 @@ config SOC_JR2
help
  This supports MSCC Jaguar2 family of SOCs.
 
+config SOC_SERVALT
+   bool "Servalt SOC Family"
+   select SOC_VCOREIII
+   select MSCC_BB_SPI
+   help
+ This supports MSCC Servalt family of SOCs.
+
 endchoice
 
 config SYS_CONFIG_NAME
@@ -74,4 +81,5 @@ source "board/mscc/luton/Kconfig"
 
 source "board/mscc/jr2/Kconfig"
 
+source "board/mscc/servalt/Kconfig"
 endmenu
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 4729b7a..1bfd636 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -91,7 +91,7 @@ int mach_cpu_init(void)
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
   ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
 #endif
-#ifdef CONFIG_SOC_JR2
+#if defined(CONFIG_SOC_JR2) || defined(CONFIG_SOC_SERVALT)
writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
   ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
   ICPU_SPI_MST_CFG_CLK_DIV(14), BASE_CFG + ICPU_SPI_MST_CFG);
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 8002e07..2073821 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -19,7 +19,8 @@ static inline int vcoreiii_train_bytelane(void)
 
ret = hal_vcoreiii_train_bytelane(0);
 
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+   defined(CONFIG_SOC_SERVALT)
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
diff --git a/arch/mips/mach-mscc/include/mach/common.h 
b/arch/mips/mach-mscc/include/mach/common.h
index b9e0939..97b3f82 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -21,6 +21,11 @@
 #include 
 #include 
 #include 
+#elif defined(CONFIG_SOC_SERVALT)
+#include 
+#include 
+#include 
+#include 
 #else
 #error Unsupported platform
 #endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h 
b/arch/mips/mach-mscc/include/mach/ddr.h
index 7552acb..ff32f22 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -161,7 +161,8 @@
 
 #endif
 
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+   defined(CONFIG_SOC_SERVALT)
 #define MIPS_VCOREIII_MEMORY_16BIT 1
 #endif
 
@@ -239,7 +240,8 @@
ICPU_MEMCTRL_CFG_MSB_ROW_ADDR(VC3_MPAR_row_addr_cnt - 1) |  \
ICPU_MEMCTRL_CFG_MSB_COL_ADDR(VC3_MPAR_col_addr_cnt - 1)
 
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+   defined(CONFIG_SOC_SERVALT)
 #define MSCC_MEMPARM_PERIOD\
ICPU_MEMCTRL_REF_PERIOD_MAX_PEND_REF(8) |   \
ICPU_MEMCTRL_REF_PERIOD_REF_PERIOD(VC3_MPAR_tREFI)
@@ -378,7 +380,8 @@ static inline void memphy_soft_reset(void)
PAUSE();
 }
 
-#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2)
+#if defined(CONFIG_SOC_OCELOT) || defined(CONFIG_SOC_JR2) || \
+   defined(CONFIG_SOC_SERVALT)
 static u8 training_data[] = { 0xfe, 0x11, 0x33, 0x55, 0x77, 0x99, 0xbb, 0xdd };
 
 static inline void sleep_100ns(u32 val)
@@ -449,7 +452,7 @@ static inline void hal_vcoreiii_ddr_failed(void)
 
panic("DDR init failed\n");
 }
-#else  /* JR2 */
+#else  /* JR2 || ServalT */
 static inline void hal_vcoreiii_ddr_reset_assert(void)
 {
/* Ensure the memory controller physical iface is forced reset */
@@

[U-Boot] [PATCH v2 3/3] MSCC: Add board support for Servalt SoC family

Add board support, configuration and DTS for Servalt SoC
family. Currently there is one board in this family.

Reviewed-by: Daniel Schwierzeck 
Signed-off-by: Horatiu Vultur 
---
 arch/mips/dts/Makefile   |   1 +
 arch/mips/dts/mscc,servalt.dtsi  | 149 +++
 arch/mips/dts/servalt_pcb116.dts |  56 +++
 board/mscc/servalt/Kconfig   |  14 
 board/mscc/servalt/Makefile  |   3 +
 board/mscc/servalt/servalt.c |  52 ++
 configs/mscc_servalt_defconfig   |  60 
 7 files changed, 335 insertions(+)
 create mode 100644 arch/mips/dts/mscc,servalt.dtsi
 create mode 100644 arch/mips/dts/servalt_pcb116.dts
 create mode 100644 board/mscc/servalt/Kconfig
 create mode 100644 board/mscc/servalt/Makefile
 create mode 100644 board/mscc/servalt/servalt.c
 create mode 100644 configs/mscc_servalt_defconfig

diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile
index 1484db9..af264ff 100644
--- a/arch/mips/dts/Makefile
+++ b/arch/mips/dts/Makefile
@@ -20,6 +20,7 @@ dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
 dtb-$(CONFIG_SOC_LUTON) += luton_pcb090.dtb luton_pcb091.dtb
 dtb-$(CONFIG_SOC_OCELOT) += ocelot_pcb120.dtb ocelot_pcb123.dtb
 dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb
+dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/mips/dts/mscc,servalt.dtsi b/arch/mips/dts/mscc,servalt.dtsi
new file mode 100644
index 000..4beb7a3
--- /dev/null
+++ b/arch/mips/dts/mscc,servalt.dtsi
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "mscc,servalt";
+
+   cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   cpu@0 {
+   compatible = "mips,mips24KEc";
+   device_type = "cpu";
+   clocks = <&cpu_clk>;
+   reg = <0>;
+   };
+   };
+
+   aliases {
+   serial0 = &uart0;
+   };
+
+   cpuintc: interrupt-controller@0 {
+   #address-cells = <0>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   compatible = "mti,cpu-interrupt-controller";
+   };
+
+   cpu_clk: cpu-clock {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <5>;
+   };
+
+   sys_clk: sys-clk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <25000>;
+   };
+
+   ahb_clk: ahb-clk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   clock-frequency = <25000>;
+   };
+
+   ahb {
+   compatible = "simple-bus";
+   #address-cells = <1>;
+   #size-cells = <1>;
+   ranges = <0 0x7000 0x200>;
+
+   interrupt-parent = <&intc>;
+
+   cpu_ctrl: syscon@0 {
+   compatible = "mscc,servalt-cpu-syscon", "syscon";
+   reg = <0x0 0x2c>;
+   };
+
+   intc: interrupt-controller@70 {
+   compatible = "mscc,servalt-icpu-intr";
+   reg = <0x70 0x74>;
+   #interrupt-cells = <1>;
+   interrupt-controller;
+   interrupt-parent = <&cpuintc>;
+   interrupts = <2>;
+   };
+
+   uart0: serial@10 {
+   pinctrl-0 = <&uart_pins>;
+   pinctrl-names = "default";
+   compatible = "ns16550a";
+   reg = <0x10 0x20>;
+   interrupts = <6>;
+   clocks = <&ahb_clk>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+
+   status = "disabled";
+   };
+
+   uart2: serial@100800 {
+   pinctrl-0 = <&uart2_pins>;
+   pinctrl-names = "default";
+   compatible = "ns16550a";
+   reg = <0x100800 0x20>;
+   interrupts = <7>;
+   clocks = <&ahb_clk>;
+   reg-io-width = <4>;
+   reg-shift = <2>;
+
+   status = "disabled";
+   };
+
+   reset@1010008 {
+   compatible = "mscc,servalt-chip-reset";
+   reg = <0x1010008 0x4>;
+   };
+
+   gpio: pinctrl@1010034 {
+   compatible = "mscc,servalt-pinctrl";
+   reg = <0x1010034 0x90>;
+   gpio-controller;
+

Re: [U-Boot] [U-Boot, v2, 4/7] ARM: mach-omap2: Kconfig: Allow OMAP5 devices to set entry point

2019-01-17 Thread Andrew F. Davis

On 1/17/19 8:15 AM, Tom Rini wrote:
> On Thu, Jan 17, 2019 at 08:13:21AM -0600, Andrew F. Davis wrote:
>> On 1/16/19 3:14 PM, Tom Rini wrote:
>>> On Wed, Dec 05, 2018 at 11:51:33AM -0600, Andrew F. Davis wrote:
>>>
 Like AM33xx and AM43xx, DRA7xx and AM57xx devices may need to
 have an non-standard boot address in memory. This may be due
 to the device being a high security variant, which place the
 Initial SoftWare (ISW) after certificates and secure software.

 Allow these devices to set this from Kconfig.

 Signed-off-by: Andrew F. Davis 
 Reviewed-by: Tom Rini 
 ---
  arch/arm/mach-omap2/Kconfig| 13 +
  arch/arm/mach-omap2/am33xx/Kconfig | 15 ---
  include/configs/ti_omap5_common.h  |  2 +-
  3 files changed, 14 insertions(+), 16 deletions(-)
>>>
>>> Turns out this breaks OMAP3 among others as the question is asked there
>>> now and we have no default value (nor I suspect a reasonable one).
>>
>> The only thing changed is ti_omap5_common.h, the default provided in
>> that file is 0x40301350, would it be okay to just make that the default
>> for ISW_ENTRY_ADDR for all platforms that included that file?
> 
> Well, ISW_ENTRY_ADDR doesn't make sense for OMAP3, right?  I suspect the
> problem is that in moving it from mach-omap2/am33xx/Kconfig to
> mach-omap2/Kconfig you need to update the depends on guards so that it
> doesn't show up where it's not used.
> 

CONFIG_SPL_TEXT_BASE should be converted to Kconfig, but cannot be right
now due to some other platforms using strange methods for setting it in
header files. So we have ISW_ENTRY_ADDR in Kconfig that is used to set
CONFIG_SPL_TEXT_BASE. ISW_ENTRY_ADDR can be defined for any platform, I
just may not be used depending on what headers it includes and whether
they use it to set CONFIG_SPL_TEXT_BASE.

The change here is using it in ti_omap5_common.h, which a lot more
platforms use is seems than I noticed. So all these platforms now need
ISW_ENTRY_ADDR set to what the header to set them as (0x40301350).

Again, all this goes away when CONFIG_SPL_TEXT_BASE gets converted to
Kconfig.

Andrew
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Re: [U-Boot] [PATCH v3 3/9] clk: actions: Add common clock driver

Hi,

On Tue, Jan 15, 2019 at 12:43:36AM +, André Przywara wrote:
> On 14/01/2019 12:41, Amit Singh Tomar wrote:
> 
> Hi,
> 
> > CMU block on most of the actions SoC seems to be identical(at-least, S900 
> > and S700).
> 
> Actually they are not. Not even for the small subset that we implement
> here. Try "diff -wu arch/arm/include/asm/arch-owl/regs_s*.h" for a
> start, plus the differences in the #ifdefs below.
> 
> > This patch converts S900 clock driver to something common that can
> > be used for other SoCs, for instance S700(most of clk registres are same).
> 
> I am not sure this is a viable approach, really.
> The driver claims to support both SoC's via their compatible strings,
> but in fact is just implementing the one configured via Kconfig.
> While we should be able to easily replace the #ifdefs with something
> checking the .data member associated with the respective .compatible
> string, it gets hairy with the #defines in regs_s[79]00.h.
> So either it's two different .c files, with the register definitions in
> there, or we change the CMU_* defines to CMU_S[79]00_* and include both.
> 
> Maybe you could try this and report how it looks like?
> If half of the file is within if-else statements, separating is problem
> more worthwhile.
> Mani, you mentioned the S500, I guess this is even more different,
> right? Which would point into the "separate files" direction.
> 

S500 is different in terms of the clock initializations. Ideally we should
have a minimal set of common clk driver like in Linux which I authored.
Otherwise, we should move forward with individual clk files for each
SoC. Having #ifdef's will definitely make the code look messy.

Thanks,
Mani

> > 
> > Signed-off-by: Amit Singh Tomar 
> > ---
> > Changes since v1:
> > * Moved CLK and CLK_OWL symbols from defconfig to arch/arm/Kconfig.
> > ---
> >  arch/arm/Kconfig  |   2 +
> >  arch/arm/include/asm/arch-owl/clk_owl.h   |  61 +
> >  arch/arm/include/asm/arch-owl/clk_s900.h  |  57 -
> >  arch/arm/include/asm/arch-owl/regs_s700.h |  56 
> 
> This file doesn't define an interface, so should live in the
> drivers/clk/owl directory. Same with the regs_s900.h.
> 
> >  configs/bubblegum_96_defconfig|   3 -
> >  drivers/clk/owl/Kconfig   |  10 +--
> >  drivers/clk/owl/Makefile  |   2 +-
> >  drivers/clk/owl/clk_owl.c | 132 
> > 
> >  drivers/clk/owl/clk_s900.c| 137 
> > --
> >  9 files changed, 255 insertions(+), 205 deletions(-)
> >  create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h
> >  delete mode 100644 arch/arm/include/asm/arch-owl/clk_s900.h
> >  create mode 100644 arch/arm/include/asm/arch-owl/regs_s700.h
> >  create mode 100644 drivers/clk/owl/clk_owl.c
> >  delete mode 100644 drivers/clk/owl/clk_s900.c
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 1a2e561..1daf3bf 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -764,6 +764,8 @@ config ARCH_OWL
> > select DM
> > select DM_SERIAL
> > select OWL_SERIAL
> > +   select CLK
> > +   select CLK_OWL
> > select OF_CONTROL
> > imply CMD_DM
> >  
> > diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h 
> > b/arch/arm/include/asm/arch-owl/clk_owl.h
> > new file mode 100644
> > index 000..962badd
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-owl/clk_owl.h
> > @@ -0,0 +1,61 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Actions Semi SoCs Clock Definitions
> > + *
> > + * Copyright (C) 2015 Actions Semi Co., Ltd.
> > + * Copyright (C) 2018 Manivannan Sadhasivam 
> > 
> > + *
> > + */
> > +
> > +#ifndef _OWL_CLK_H_
> > +#define _OWL_CLK_H_
> > +
> > +#include 
> > +
> > +struct owl_clk_priv {
> > +   phys_addr_t base;
> > +};
> > +
> > +/* BUSCLK register definitions */
> > +#define CMU_PDBGDIV_8  7
> > +#define CMU_PDBGDIV_SHIFT  26
> > +#define CMU_PDBGDIV_DIV(CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
> > +#define CMU_PERDIV_8   7
> > +#define CMU_PERDIV_SHIFT   20
> > +#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
> > +#define CMU_NOCDIV_2   1
> > +#define CMU_NOCDIV_SHIFT   19
> > +#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
> > +#define CMU_DMMCLK_SRC_APLL2
> > +#define CMU_DMMCLK_SRC_SHIFT   10
> > +#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << 
> > CMU_DMMCLK_SRC_SHIFT)
> > +#define CMU_APBCLK_DIV BIT(8)
> > +#define CMU_NOCCLK_SRC BIT(7)
> > +#define CMU_AHBCLK_DIV BIT(4)
> > +#define CMU_CORECLK_MASK   3
> > +#define CMU_CORECLK_CPLL   BIT(1)
> > +#define CMU_CORECLK_HOSC   BIT(0)
> > +
> > +/* COREPLL register definitions */
> > +#define CMU_COREPLL_EN BIT(9)
> > +#define CMU_COREPLL_HOSC_ENBIT(8)
> > +#define CMU_COREPLL_O

Re: [U-Boot] [PATCH v2 1/9] arm: actions: Add common framework for Actions Semi SoCs

Hi,

[On top of Andre's review]

On Mon, Jan 14, 2019 at 06:11:03PM +0530, Amit Singh Tomar wrote:
> This adds common arch owl support that can drive, 64-bits SoCs
> from Actions Semi.
> 

Could be, "This commit adds common arch support for Actions Semi Owl
series SoCs and removes the Bubblegum96 board files."

> It also removes the Bubblegum specific board files.
> 
> Signed-off-by: Amit Singh Tomar 
> ---
> Changes since v1:
>   * Moved S700 specific changes to patch 4 of 9.
>   * Moved couple of symbols from defconfig to arch/arm/Kconfig
>   and platform owl Kconfig.
> ---
>  arch/arm/Kconfig |  3 +-
>  arch/arm/mach-owl/Kconfig| 29 ++
>  arch/arm/mach-owl/Makefile   |  1 +
>  arch/arm/mach-owl/soc.c  | 56 
> 
>  board/ucRobotics/bubblegum_96/Kconfig| 15 
>  board/ucRobotics/bubblegum_96/MAINTAINERS|  6 ---
>  board/ucRobotics/bubblegum_96/Makefile   |  3 --
>  board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 
> 
>  configs/bubblegum_96_defconfig   |  4 +-
>  include/configs/bubblegum_96.h   | 42 -
>  include/configs/owl-common.h | 42 +
>  include/configs/s900.h   | 18 +
>  12 files changed, 131 insertions(+), 144 deletions(-)
>  create mode 100644 arch/arm/mach-owl/soc.c
>  delete mode 100644 board/ucRobotics/bubblegum_96/Kconfig
>  delete mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS
>  delete mode 100644 board/ucRobotics/bubblegum_96/Makefile
>  delete mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c
>  delete mode 100644 include/configs/bubblegum_96.h
>  create mode 100644 include/configs/owl-common.h
>  create mode 100644 include/configs/s900.h
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index d6b1629..1a2e561 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -761,9 +761,9 @@ config ARCH_MX5
>  
>  config ARCH_OWL
>   bool "Actions Semi OWL SoCs"
> - select ARM64
>   select DM
>   select DM_SERIAL
> + select OWL_SERIAL
>   select OF_CONTROL
>   imply CMD_DM
>  
> @@ -1555,7 +1555,6 @@ source "board/spear/spear600/Kconfig"
>  source "board/spear/x600/Kconfig"
>  source "board/st/stv0991/Kconfig"
>  source "board/tcl/sl50/Kconfig"
> -source "board/ucRobotics/bubblegum_96/Kconfig"
>  source "board/birdland/bav335x/Kconfig"
>  source "board/toradex/colibri_pxa270/Kconfig"
>  source "board/vscom/baltos/Kconfig"
> diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
> index 199e772..5eb93c9 100644
> --- a/arch/arm/mach-owl/Kconfig
> +++ b/arch/arm/mach-owl/Kconfig
> @@ -1,27 +1,22 @@
>  if ARCH_OWL
>  
> -config SYS_SOC
> - default "owl"
> -
>  choice
> -prompt "Actions Semi OWL SoCs board select"
> +prompt "Actions Semi SoC Variant"

We should explicitly say "Owl" series SoCs here.

>  optional
>  
> -config TARGET_BUBBLEGUM_96
> - bool "96Boards Bubblegum-96"
> - help
> -   Support for 96Boards Bubblegum-96. This board complies with
> -   96Board Consumer Edition Specification. Features:
> -   - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
> -   - 2GiB RAM
> -   - 8GiB eMMC, uSD slot
> -   - WiFi, Bluetooth and GPS module
> -   - 2x Host, 1x Device USB port
> -   - HDMI
> -   - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
> +config MACH_S900
> +bool "Actionss Semi S900"
> +select ARM64
>  
>  endchoice
>  
> -source "board/ucRobotics/bubblegum_96/Kconfig"
> +config SYS_CONFIG_NAME
> +default "s900" if MACH_S900
> +
> +config SYS_SOC
> +default "s900" if MACH_S900
> +
> +config SYS_TEXT_BASE
> +default 0x1100
>  

Move the above config symbols before MACH_S900.

>  endif
> diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile
> index 1b43dc2..0b181c6 100644
> --- a/arch/arm/mach-owl/Makefile
> +++ b/arch/arm/mach-owl/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier:   GPL-2.0+
>  
> +obj-y += soc.o
>  obj-y += sysmap-s900.o
> diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c
> new file mode 100644
> index 000..d0630d2
> --- /dev/null
> +++ b/arch/arm/mach-owl/soc.c
> @@ -0,0 +1,56 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Actions Semi SoCs Boards Support.

Owl SoCs...

> + *
> + * Copyright (C) 2018 Manivannan Sadhasivam 
> 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * dram_init - sets uboots idea of sdram size
> + */
> +int dram_init(void)
> +{
> + gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
> + return 0;
> +}
> +
> +/* This is called after dram_init() so use get_ram_size result */
> +int dram_init_banksize(void)
> +{
> + gd->bd->bi

[U-Boot] [PATCH v3 0/4] Add network support for Ocelots SoCs

Hello,

this the third version of a series allowing to use the switch
component of the Ocelots SoC as a network interface.

The binding used is exactly the same of the one already used by Linux.

There is also a patch adding a workaround needed on the Ocelot based
boards: indeed the pin connected to the DDR reset is part of the
switch subsystem. So we need ensure that the DDR is not reset during
the switch reset.

Gregory

Changelog:
v2 -> v3:

 - Use wait_for_bit_le32() whenever it is possible instead of
   timer_get_us() (Suggested by Daniel Schwierzeck)
 - Remove ocelot_ofdata_to_platdata() and get the resources directly
   from the probe function (Suggested by Daniel Schwierzeck)
 - Use dev_remap_addr_name() to simplify the address mapping
   (Suggested by Daniel Schwierzeck)
 - Simplify the mdio initialization by only manage the internal PHY
   for now

v1 -> v2:
 - Use wait_for_bit_le32() (suggested by Stefan Roese)
 - Use debug() instead of printf() for the debug messages in
   mscc_switch_reset.

Gregory CLEMENT (4):
  MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
  net: add MSCC Ocelot switch support
  MIPS: mscc: ocelot: add switch reset support
  configs: mscc_ocelot: add network support

 MAINTAINERS |   1 +
 arch/mips/dts/mscc,ocelot.dtsi  |  97 
 arch/mips/dts/ocelot_pcb123.dts |  20 +
 board/mscc/ocelot/ocelot.c  |  24 +
 configs/mscc_ocelot_defconfig   |   1 +
 drivers/net/Kconfig |   7 +
 drivers/net/Makefile|   1 +
 drivers/net/ocelot_switch.c | 765 
 8 files changed, 916 insertions(+)
 create mode 100644 drivers/net/ocelot_switch.c

-- 
2.20.1

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[U-Boot] [PATCH v3 1/4] MIPS: mscc: ocelot: Add ethernet nodes for Ocelot

Import Ethernet related nodes from Linux

Signed-off-by: Gregory CLEMENT 
---
 arch/mips/dts/mscc,ocelot.dtsi  | 97 +
 arch/mips/dts/ocelot_pcb123.dts | 20 +++
 2 files changed, 117 insertions(+)

diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 2592003103..4f3fe356c4 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,6 +112,98 @@
status = "disabled";
};
 
+   switch@101 {
+   pinctrl-0 = <&miim1_pins>;
+   pinctrl-names = "default";
+
+   compatible = "mscc,vsc7514-switch";
+   reg = <0x101 0x1>, /* VTSS_TO_SYS */
+ <0x103 0x1>, /* VTSS_TO_REW */
+ <0x108 0x100>, /* VTSS_TO_DEVCPU_QS */
+ <0x10d 0x1>, /* VTSS_TO_HSIO */
+ <0x11e 0x100>, /* VTSS_TO_DEV_0 */
+ <0x11f 0x100>, /* VTSS_TO_DEV_1 */
+ <0x120 0x100>, /* VTSS_TO_DEV_2 */
+ <0x121 0x100>, /* VTSS_TO_DEV_3 */
+ <0x122 0x100>, /* VTSS_TO_DEV_4 */
+ <0x123 0x100>, /* VTSS_TO_DEV_5 */
+ <0x124 0x100>, /* VTSS_TO_DEV_6 */
+ <0x125 0x100>, /* VTSS_TO_DEV_7 */
+ <0x126 0x100>, /* VTSS_TO_DEV_8 */
+ <0x127 0x100>, /* NA */
+ <0x128 0x100>, /* NA */
+ <0x180 0x8>, /* VTSS_TO_QSYS */
+ <0x188 0x1>; /* VTSS_TO_ANA */
+   reg-names = "sys", "rew", "qs", "hsio", "port0",
+   "port1", "port2", "port3", "port4", "port5",
+   "port6", "port7", "port8", "port9",
+   "port10", "qsys", "ana";
+   interrupts = <21 22>;
+   interrupt-names = "xtr", "inj";
+   status = "okay";
+
+   ethernet-ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port0: port@0 {
+   reg = <0>;
+   };
+   port1: port@1 {
+   reg = <1>;
+   };
+   port2: port@2 {
+   reg = <2>;
+   };
+   port3: port@3 {
+   reg = <3>;
+   };
+   port4: port@4 {
+   reg = <4>;
+   };
+   port5: port@5 {
+   reg = <5>;
+   };
+   port6: port@6 {
+   reg = <6>;
+   };
+   port7: port@7 {
+   reg = <7>;
+   };
+   port8: port@8 {
+   reg = <8>;
+   };
+   port9: port@9 {
+   reg = <9>;
+   };
+   port10: port@10 {
+   reg = <10>;
+   };
+   };
+   };
+
+   mdio0: mdio@107009c {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "mscc,ocelot-miim";
+   reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+   interrupts = <14>;
+   status = "disabled";
+
+   phy0: ethernet-phy@0 {
+   reg = <0>;
+   };
+   phy1: ethernet-phy@1 {
+   reg = <1>;
+   };
+   phy2: ethernet-phy@2 {
+   reg = <2>;
+   };
+   phy3: ethernet-phy@3 {
+   reg = <3>;
+   };
+   };
+
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
@@ -144,6 +236,11 @@
function =

[U-Boot] [PATCH v3 4/4] configs: mscc_ocelot: add network support

Now that network support is added for the ocelot platform, let's add it
in the default configuration.

Signed-off-by: Gregory CLEMENT 
---
 configs/mscc_ocelot_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
index fb6a5bdc31..792d00e646 100644
--- a/configs/mscc_ocelot_defconfig
+++ b/configs/mscc_ocelot_defconfig
@@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_SPI_FLASH_MTD=y
 CONFIG_DM_ETH=y
+CONFIG_MSCC_OCELOT_SWITCH=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_DM_SERIAL=y
-- 
2.20.1

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[U-Boot] [PATCH v3 3/4] MIPS: mscc: ocelot: add switch reset support

On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.

Signed-off-by: Gregory CLEMENT 
---
 board/mscc/ocelot/ocelot.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..532d06f000 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -18,6 +19,29 @@ enum {
BOARD_TYPE_PCB123,
 };
 
+void mscc_switch_reset(bool enter)
+{
+   /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+   mscc_gpio_set_alternate(19, 2);
+
+   debug("applying SwC reset\n");
+
+   writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+   writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+   if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+ PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+   pr_err("Tiemout while waiting for switch reset\n");
+
+   /*
+* Reset GPIO19 mode back as regular GPIO, output, high (DDR
+* not reset) (Order is important)
+*/
+   setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+   writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+   mscc_gpio_set_alternate(19, 0);
+}
+
 void board_debug_uart_init(void)
 {
/* too early for the pinctrl driver, so configure the UART pins here */
-- 
2.20.1

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[U-Boot] [PATCH v3 2/4] net: add MSCC Ocelot switch support

This patch adds support for the Microsemi Ethernet switch present on
Ocelot SoCs.

Signed-off-by: Gregory CLEMENT 
---
 MAINTAINERS |   1 +
 drivers/net/Kconfig |   7 +
 drivers/net/Makefile|   1 +
 drivers/net/ocelot_switch.c | 765 
 4 files changed, 774 insertions(+)
 create mode 100644 drivers/net/ocelot_switch.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 3fa5d3e96f..af44e19eae 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -529,6 +529,7 @@ F:  drivers/gpio/mscc_sgpio.c
 F: drivers/spi/mscc_bb_spi.c
 F: include/configs/vcoreiii.h
 F: drivers/pinctrl/mscc/
+F: drivers/net/ocelot_switch.c
 
 MIPS JZ4780
 M: Ezequiel Garcia 
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7044c6adf3..10ac15cc6c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -432,6 +432,13 @@ config SNI_AVE
  This driver implements support for the Socionext AVE Ethernet
  controller, as found on the Socionext UniPhier family.
 
+config MSCC_OCELOT_SWITCH
+   bool "Ocelot switch driver"
+   depends on DM_ETH && ARCH_MSCC
+   select PHYLIB
+   help
+ This driver supports the Ocelot network switch device.
+
 config ETHER_ON_FEC1
bool "FEC1"
depends on MPC8XX_FEC
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0dbfa03306..bd108c21d1 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -74,3 +74,4 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
 obj-$(CONFIG_FSL_PFE) += pfe_eth/
 obj-$(CONFIG_SNI_AVE) += sni_ave.o
 obj-y += ti/
+obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o
diff --git a/drivers/net/ocelot_switch.c b/drivers/net/ocelot_switch.c
new file mode 100644
index 00..9fed26cd94
--- /dev/null
+++ b/drivers/net/ocelot_switch.c
@@ -0,0 +1,765 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MIIM_STATUS0x0
+#defineMIIM_STAT_BUSY  BIT(3)
+#define MIIM_CMD   0x8
+#defineMIIM_CMD_SCAN   BIT(0)
+#defineMIIM_CMD_OPR_WRITE  BIT(1)
+#defineMIIM_CMD_OPR_READ   BIT(2)
+#defineMIIM_CMD_SINGLE_SCANBIT(3)
+#defineMIIM_CMD_WRDATA(x)  ((x) << 4)
+#defineMIIM_CMD_REGAD(x)   ((x) << 20)
+#defineMIIM_CMD_PHYAD(x)   ((x) << 25)
+#defineMIIM_CMD_VLDBIT(31)
+#define MIIM_DATA  0xC
+#defineMIIM_DATA_ERROR (0x2 << 16)
+
+#define PHY_CFG0x0
+#define PHY_CFG_ENA0xF
+#define PHY_CFG_COMMON_RST BIT(4)
+#define PHY_CFG_RST(0xF << 5)
+#define PHY_STAT   0x4
+#define PHY_STAT_SUPERVISOR_COMPLETE   BIT(0)
+
+#define ANA_PORT_VLAN_CFG(x)   (0x7000 + 0x100 * (x))
+#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20)
+#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18)
+#define ANA_PORT_PORT_CFG(x)   (0x7070 + 0x100 * (x))
+#defineANA_PORT_PORT_CFG_RECV_ENA  BIT(6)
+#defineANA_TABLES_MACHDATA 0x8b34
+#defineANA_TABLES_MACLDATA 0x8b38
+#define ANA_TABLES_MACACCESS   0x8b3c
+#defineANA_TABLES_MACACCESS_VALID  BIT(11)
+#defineANA_TABLES_MACACCESS_ENTRYTYPE(x)   ((x) << 9)
+#defineANA_TABLES_MACACCESS_DEST_IDX(x)((x) << 3)
+#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD(x)   (x)
+#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD_MGENMASK(2, 0)
+#defineMACACCESS_CMD_IDLE 0
+#defineMACACCESS_CMD_LEARN1
+#defineMACACCESS_CMD_GET_NEXT 4
+#define ANA_PGID(x)(0x8c00 + 4 * (x))
+
+#define SYS_FRM_AGING  0x574
+#defineSYS_FRM_AGING_ENA   BIT(20)
+
+#define SYS_SYSTEM_RST_CFG 0x508
+#defineSYS_SYSTEM_RST_MEM_INIT BIT(0)
+#defineSYS_SYSTEM_RST_MEM_ENA  BIT(1)
+#defineSYS_SYSTEM_RST_CORE_ENA BIT(2)
+#define SYS_PORT_MODE(x)   (0x514 + 0x4 * (x))
+#defineSYS_PORT_MODE_INCL_INJ_HDR(x)   ((x) << 3)
+#defineSYS_PORT_MODE_INCL_INJ_HDR_MGENMASK(4, 3)
+#defineSYS_PORT_MODE_INCL_XTR_HDR(x)   ((x) << 1)
+#defineSYS_PORT_MODE_INCL_XTR_HDR_MGENMASK(2, 1)
+#defineSYS_PAUSE_CFG(x)(0x608 + 0x4 * (x))
+#defineSYS_PAUSE_CFG_PAUSE_ENA B

Re: [U-Boot] [PATCH v2 2/9] arm: actions: Add owl memory map regions

On Mon, Jan 14, 2019 at 06:11:04PM +0530, Amit Singh Tomar wrote:
> This adds memory regions needed to setup MMU for actions
> S900 and S700 SoCs.
> 
> Signed-off-by: Amit Singh Tomar 
> ---
> Changes since v1:
>   * compile sysmap-owl.c against CONFIG_ARM64 now.
> ---
>  arch/arm/mach-owl/Makefile  |  3 ++-
>  arch/arm/mach-owl/sysmap-owl.c  | 32 
>  arch/arm/mach-owl/sysmap-s900.c | 32 
>  3 files changed, 34 insertions(+), 33 deletions(-)
>  create mode 100644 arch/arm/mach-owl/sysmap-owl.c
>  delete mode 100644 arch/arm/mach-owl/sysmap-s900.c
> 
> diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile
> index 0b181c6..b17fc14 100644
> --- a/arch/arm/mach-owl/Makefile
> +++ b/arch/arm/mach-owl/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier:   GPL-2.0+
>  
>  obj-y += soc.o
> -obj-y += sysmap-s900.o
> +obj-$(CONFIG_ARM64) += sysmap-owl.o
> +
> diff --git a/arch/arm/mach-owl/sysmap-owl.c b/arch/arm/mach-owl/sysmap-owl.c
> new file mode 100644
> index 000..9d30759
> --- /dev/null
> +++ b/arch/arm/mach-owl/sysmap-owl.c
> @@ -0,0 +1,32 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Memory map for Actions Semi S900/S700 based SoCs.

Actions Semi Owl series SoCs?

With this,

Reviewed-by: Manivannan Sadhasivam 

Thanks,
Mani

> + *
> + * Copyright (C) 2015 Actions Semi Co., Ltd.
> + * Copyright (C) 2018 Manivannan Sadhasivam 
> 
> + */
> +
> +#include 
> +#include 
> +
> +static struct mm_region owl_mem_map[] = {
> + {
> + .virt = 0x0UL, /* DDR */
> + .phys = 0x0UL, /* DDR */
> + .size = 0x8000UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> +  PTE_BLOCK_INNER_SHARE
> + }, {
> + .virt = 0xE000UL, /* Peripheral block */
> + .phys = 0xE000UL, /* Peripheral block */
> + .size = 0x0800UL,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> +  PTE_BLOCK_NON_SHARE |
> +  PTE_BLOCK_PXN | PTE_BLOCK_UXN
> + }, {
> + /* List terminator */
> + 0,
> + }
> +};
> +
> +struct mm_region *mem_map = owl_mem_map;
> diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c
> deleted file mode 100644
> index f78b639..000
> --- a/arch/arm/mach-owl/sysmap-s900.c
> +++ /dev/null
> @@ -1,32 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Actions Semi S900 Memory map
> - *
> - * Copyright (C) 2015 Actions Semi Co., Ltd.
> - * Copyright (C) 2018 Manivannan Sadhasivam 
> 
> - */
> -
> -#include 
> -#include 
> -
> -static struct mm_region s900_mem_map[] = {
> - {
> - .virt = 0x0UL, /* DDR */
> - .phys = 0x0UL, /* DDR */
> - .size = 0x8000UL,
> - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
> -  PTE_BLOCK_INNER_SHARE
> - }, {
> - .virt = 0xE000UL, /* Peripheral block */
> - .phys = 0xE000UL, /* Peripheral block */
> - .size = 0x0800UL,
> - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> -  PTE_BLOCK_NON_SHARE |
> -  PTE_BLOCK_PXN | PTE_BLOCK_UXN
> - }, {
> - /* List terminator */
> - 0,
> - }
> -};
> -
> -struct mm_region *mem_map = s900_mem_map;
> -- 
> 2.7.4
> 
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Re: [U-Boot] [PATCH v2 6/9] arm: add Cubieboard7 board support

On Mon, Jan 14, 2019 at 10:57:47PM +, André Przywara wrote:
> On 14/01/2019 12:41, Amit Singh Tomar wrote:
> > The Cubieboard is a single board computer containing a
> > Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).
> > 
> > This patch adds respective defconfig alongwith device tree(sync with
> > Linux 4.20).
> 
> This should come later in the series, as patch 8/9, just _after_
> everything works. It compiles at this point, but you still need the next
> two patches for it to work.
>

Usually, DTS patches comes before driver bits.

Regards,
Mani

> The _defconfig is still a bit too crowded, but so is the S900 version, so:
> 
> > Signed-off-by: Amit Singh Tomar 
> 
> Reviewed-by: Andre Przywara 
> 
> Cheers,
> Andre.
> 
> > ---
> > Changes since v1:
> > * No changes.
> > ---
> >  arch/arm/dts/s700-cubieboard7.dts | 39 
> > +++
> >  configs/cubieboard7_defconfig | 16 
> >  2 files changed, 55 insertions(+)
> >  create mode 100644 arch/arm/dts/s700-cubieboard7.dts
> >  create mode 100644 configs/cubieboard7_defconfig
> > 
> > diff --git a/arch/arm/dts/s700-cubieboard7.dts 
> > b/arch/arm/dts/s700-cubieboard7.dts
> > new file mode 100644
> > index 000..28f3f4a
> > --- /dev/null
> > +++ b/arch/arm/dts/s700-cubieboard7.dts
> > @@ -0,0 +1,39 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2017 Andreas Färber
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "s700.dtsi"
> > +
> > +/ {
> > +   compatible = "cubietech,cubieboard7", "actions,s700";
> > +   model = "CubieBoard7";
> > +
> > +   aliases {
> > +   serial3 = &uart3;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial3:115200n8";
> > +   };
> > +
> > +   memory@0 {
> > +   device_type = "memory";
> > +   reg = <0x0 0x0 0x0 0x8000>;
> > +   };
> > +
> > +   memory@1,e000 {
> > +   device_type = "memory";
> > +   reg = <0x1 0xe000 0x0 0x0>;
> > +   };
> > +};
> > +
> > +&timer {
> > +   clocks = <&hosc>;
> > +};
> > +
> > +&uart3 {
> > +   status = "okay";
> > +};
> > diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig
> > new file mode 100644
> > index 000..0459997
> > --- /dev/null
> > +++ b/configs/cubieboard7_defconfig
> > @@ -0,0 +1,16 @@
> > +CONFIG_ARM=y
> > +CONFIG_ARCH_OWL=y
> > +CONFIG_MACH_S700=y
> > +CONFIG_IDENT_STRING="\ncubieboard7"
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_BOOTDELAY=5
> > +CONFIG_USE_BOOTARGS=y
> > +CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
> > +# CONFIG_DISPLAY_CPUINFO is not set
> > +# CONFIG_DISPLAY_BOARDINFO is not set
> > +CONFIG_SYS_PROMPT="U-Boot => "
> > +CONFIG_CMD_MD5SUM=y
> > +CONFIG_CMD_MEMINFO=y
> > +CONFIG_CMD_TIMER=y
> > +CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
> > 
> 
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Re: [U-Boot] [PATCH v2 6/9] arm: add Cubieboard7 board support

On Mon, Jan 14, 2019 at 06:11:08PM +0530, Amit Singh Tomar wrote:
> The Cubieboard is a single board computer containing a
> Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).
> 
> This patch adds respective defconfig alongwith device tree(sync with
> Linux 4.20).
> 
> Signed-off-by: Amit Singh Tomar 

Reviewed-by: Manivannan Sadhasivam 

Thanks,
Mani

> ---
> Changes since v1:
>   * No changes.
> ---
>  arch/arm/dts/s700-cubieboard7.dts | 39 
> +++
>  configs/cubieboard7_defconfig | 16 
>  2 files changed, 55 insertions(+)
>  create mode 100644 arch/arm/dts/s700-cubieboard7.dts
>  create mode 100644 configs/cubieboard7_defconfig
> 
> diff --git a/arch/arm/dts/s700-cubieboard7.dts 
> b/arch/arm/dts/s700-cubieboard7.dts
> new file mode 100644
> index 000..28f3f4a
> --- /dev/null
> +++ b/arch/arm/dts/s700-cubieboard7.dts
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2017 Andreas Färber
> + */
> +
> +/dts-v1/;
> +
> +#include "s700.dtsi"
> +
> +/ {
> + compatible = "cubietech,cubieboard7", "actions,s700";
> + model = "CubieBoard7";
> +
> + aliases {
> + serial3 = &uart3;
> + };
> +
> + chosen {
> + stdout-path = "serial3:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x8000>;
> + };
> +
> + memory@1,e000 {
> + device_type = "memory";
> + reg = <0x1 0xe000 0x0 0x0>;
> + };
> +};
> +
> +&timer {
> + clocks = <&hosc>;
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> diff --git a/configs/cubieboard7_defconfig b/configs/cubieboard7_defconfig
> new file mode 100644
> index 000..0459997
> --- /dev/null
> +++ b/configs/cubieboard7_defconfig
> @@ -0,0 +1,16 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_OWL=y
> +CONFIG_MACH_S700=y
> +CONFIG_IDENT_STRING="\ncubieboard7"
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_BOOTDELAY=5
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="console=ttyOWL3,115200n8"
> +# CONFIG_DISPLAY_CPUINFO is not set
> +# CONFIG_DISPLAY_BOARDINFO is not set
> +CONFIG_SYS_PROMPT="U-Boot => "
> +CONFIG_CMD_MD5SUM=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_TIMER=y
> +CONFIG_DEFAULT_DEVICE_TREE="s700-cubieboard7"
> -- 
> 2.7.4
> 
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Re: [U-Boot] [PATCH v2 4/9] arm: add support Actions Semi S700

On Mon, Jan 14, 2019 at 06:11:06PM +0530, Amit Singh Tomar wrote:
> This patch adds basic support for Actions Semi based S700
> SoC, which is driven by common owl framework.
> 
> Signed-off-by: Amit Singh Tomar 
> ---
> Changes since v1:
>   * S700 specific changes are factored out here 
> from patch 1 of 9.
> ---
>  arch/arm/mach-owl/Kconfig |  6 ++
>  include/configs/s700.h| 15 +++
>  2 files changed, 21 insertions(+)
>  create mode 100644 include/configs/s700.h
> 
> diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
> index 5eb93c9..d05cc68 100644
> --- a/arch/arm/mach-owl/Kconfig
> +++ b/arch/arm/mach-owl/Kconfig
> @@ -8,13 +8,19 @@ config MACH_S900
>  bool "Actionss Semi S900"
>  select ARM64
>  
> +config MACH_S700
> +bool "Actions Semi S700"
> +select ARM64
> +
>  endchoice
>  
>  config SYS_CONFIG_NAME
>  default "s900" if MACH_S900
> +default "s700" if MACH_S700
>  
>  config SYS_SOC
>  default "s900" if MACH_S900
> +default "s700" if MACH_S700
>  
>  config SYS_TEXT_BASE
>  default 0x1100
> diff --git a/include/configs/s700.h b/include/configs/s700.h
> new file mode 100644
> index 000..84f9174
> --- /dev/null
> +++ b/include/configs/s700.h
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Board configuration file for Action semi s700

Please be consistent with naming conventions... Actions Semi S700 SoC.

Thanks,
Mani

> + *
> + */
> +
> +#ifndef _CONFIG_S700_H_
> +#define _CONFIG_S700_H_
> +
> +/*
> + * Include common owl configuration where most the settings are
> + */
> +#include 
> +
> +#endif
> -- 
> 2.7.4
> 
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Re: [U-Boot] [PATCH v2 7/9] actions:s700: add u-boot specific dts file

On Mon, Jan 14, 2019 at 06:11:09PM +0530, Amit Singh Tomar wrote:
> Devices like uart and clk are needed to be enabled before relocation.
> this patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.
> 
> Signed-off-by: Amit Singh Tomar 
> ---
> Changes since v1:
>   * This is newly added file that was *not* present in v1 and
>   contains u-boot specific changes.   
> ---
>  arch/arm/dts/s700-u-boot.dtsi | 14 ++
>  1 file changed, 14 insertions(+)
>  create mode 100644 arch/arm/dts/s700-u-boot.dtsi
> 
> diff --git a/arch/arm/dts/s700-u-boot.dtsi b/arch/arm/dts/s700-u-boot.dtsi
> new file mode 100644
> index 000..46e98de
> --- /dev/null
> +++ b/arch/arm/dts/s700-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +/{

Missing License and description.

Regards,
Mani

> + soc {
> + u-boot,dm-pre-reloc;
> + };
> +};
> +
> +&uart3 {
> + u-boot,dm-pre-reloc;
> +};
> +
> +&cmu {
> + u-boot,dm-pre-reloc;
> +};
> +
> -- 
> 2.7.4
> 
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Re: [U-Boot] [PATCH 11/11] riscv: Add SiFive FU540 board support

2019-01-17 Thread Troy Benjegerdes

So I take it I could use my version of U-boot to load BBL,
then your S-mode U-boot?

I've been holding off on refactoring or submitting anything
from the MicroSemi U-boot that runs in M-mode and inits the
DRAM until I have some decent method to regression test the
whole system (bootloader, kernel, userspace). I also want
to make sure we don't break any other RiscV platforms when
we add new code.

It looks HiFive unleashed boards are available for purchase
again, is there any place to get an AndesTech board?

(fyi, the *proof of concept* hacks for regression testing
that work for me based on MicroSemi patches are at
https://github.com/tmagik/freedom-u-sdk/tree/regression/kernel4.15 )

On Thu, Jan 17, 2019 at 10:39:27AM +, Anup Patel wrote:
> This patch adds SiFive FU540 board support. For now, only
> SiFive serial, SiFive PRCI, and Cadance MACB drivers are
> only enabled. The SiFive FU540 defconfig by default builds
> U-Boot for S-Mode because U-Boot on SiFive FU540 will run
> in S-Mode as payload of BBL or OpenSBI.
> 
> Signed-off-by: Anup Patel 
> Signed-off-by: Atish Patra 
> ---
>  arch/riscv/Kconfig |  4 
>  board/sifive/fu540/Kconfig | 42 +
>  board/sifive/fu540/MAINTAINERS |  9 +++
>  board/sifive/fu540/Makefile|  5 
>  board/sifive/fu540/fu540.c | 17 ++
>  configs/sifive_fu540_defconfig | 11 +
>  include/configs/sifive-fu540.h | 43 ++
>  7 files changed, 131 insertions(+)
>  create mode 100644 board/sifive/fu540/Kconfig
>  create mode 100644 board/sifive/fu540/MAINTAINERS
>  create mode 100644 board/sifive/fu540/Makefile
>  create mode 100644 board/sifive/fu540/fu540.c
>  create mode 100644 configs/sifive_fu540_defconfig
>  create mode 100644 include/configs/sifive-fu540.h
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 6879047ff7..36512a8995 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -14,11 +14,15 @@ config TARGET_AX25_AE350
>  config TARGET_QEMU_VIRT
>   bool "Support QEMU Virt Board"
>  
> +config TARGET_SIFIVE_FU540
> + bool "Support SiFive FU540 Board"
> +
>  endchoice
>  
>  # board-specific options below
>  source "board/AndesTech/ax25-ae350/Kconfig"
>  source "board/emulation/qemu-riscv/Kconfig"
> +source "board/sifive/fu540/Kconfig"
>  
>  # platform-specific options below
>  source "arch/riscv/cpu/ax25/Kconfig"
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> new file mode 100644
> index 00..6be3d88144
> --- /dev/null
> +++ b/board/sifive/fu540/Kconfig
> @@ -0,0 +1,42 @@
> +if TARGET_SIFIVE_FU540
> +
> +config SYS_BOARD
> + default "fu540"
> +
> +config SYS_VENDOR
> + default "sifive"
> +
> +config SYS_CPU
> + default "generic"
> +
> +config SYS_CONFIG_NAME
> + default "sifive-fu540"
> +
> +config SYS_TEXT_BASE
> + default 0x8000 if !RISCV_SMODE
> + default 0x8020 if RISCV_SMODE
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> + def_bool y
> + select GENERIC_RISCV
> + imply CMD_DHCP
> + imply CMD_EXT2
> + imply CMD_EXT4
> + imply CMD_FAT
> + imply CMD_FS_GENERIC
> + imply CMD_NET
> + imply CMD_PING
> + imply CLK_SIFIVE
> + imply CLK_SIFIVE_FU540_PRCI
> + imply DOS_PARTITION
> + imply EFI_PARTITION
> + imply IP_DYN
> + imply ISO_PARTITION
> + imply MACB
> + imply MII
> + imply NET_RANDOM_ETHADDR
> + imply PHY_LIB
> + imply PHY_MSCC
> + imply SIFIVE_SERIAL
> +
> +endif
> diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
> new file mode 100644
> index 00..702d803ad8
> --- /dev/null
> +++ b/board/sifive/fu540/MAINTAINERS
> @@ -0,0 +1,9 @@
> +SiFive FU540 BOARD
> +M:   Paul Walmsley 
> +M:   Palmer Dabbelt 
> +M:   Anup Patel 
> +M:   Atish Patra 
> +S:   Maintained
> +F:   board/sifive/fu540/
> +F:   include/configs/sifive-fu540.h
> +F:   configs/sifive_fu540_defconfig
> diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
> new file mode 100644
> index 00..6e1862c475
> --- /dev/null
> +++ b/board/sifive/fu540/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2019 Western Digital Corporation or its affiliates.
> +
> +obj-y+= fu540.o
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> new file mode 100644
> index 00..5adc4a3d4a
> --- /dev/null
> +++ b/board/sifive/fu540/fu540.c
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2019 Western Digital Corporation or its affiliates.
> + *
> + * Authors:
> + *   Anup Patel 
> + */
> +
> +#include 
> +#include 
> +
> +int board_init(void)
> +{
> + /* For now nothing to do here. */
> +
> + return 0;
> +}
> diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
> new file mode 100644
> index 00..2f8cca9de0
> --- /dev/null
> +++ b/con

[U-Boot] [PATCH 1/2] mmc: mtk-sd: fix possible incomplete read ops

2019-01-17 Thread Fabien Parent

The code is checking for incomplete read when it see the INT_XFER_COMPL
flag, but it forget to first check whether there is anything left in the
FIFO to copy to the RX buffer. This means that sometimes we will get
errors because of erroneous incomplete read operation.

This commit fixes the driver re-ordering the code so that we first
check for data inside the RX fifo and only after check the status
of the INT_XFER_COMPL flag.

Signed-off-by: Fabien Parent 
---
 drivers/mmc/mtk-sd.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 0741a525c0..e668df7017 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -554,6 +554,14 @@ static int msdc_pio_read(struct msdc_host *host, u8 *ptr, 
u32 size)
break;
}
 
+   chksz = min(size, (u32)MSDC_FIFO_SIZE);
+
+   if (msdc_fifo_rx_bytes(host) >= chksz) {
+   msdc_fifo_read(host, ptr, chksz);
+   ptr += chksz;
+   size -= chksz;
+   }
+
if (status & MSDC_INT_XFER_COMPL) {
if (size) {
pr_err("data not fully read\n");
@@ -562,15 +570,7 @@ static int msdc_pio_read(struct msdc_host *host, u8 *ptr, 
u32 size)
 
break;
}
-
-   chksz = min(size, (u32)MSDC_FIFO_SIZE);
-
-   if (msdc_fifo_rx_bytes(host) >= chksz) {
-   msdc_fifo_read(host, ptr, chksz);
-   ptr += chksz;
-   size -= chksz;
-   }
-   }
+}
 
return ret;
 }
-- 
2.20.1

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[U-Boot] [PATCH 2/2] mmc: mtk-sd: fix SPL compilation when GPIO=y and SPL_GPIO=n

2019-01-17 Thread Fabien Parent

It is not possible to link the SPL image when CONFIG_GPIO is enabled
but CONFIG_SPL_GPIO is not.  Use the IS_ENABLED macro instead to
correctly check whether CONFIG_{SPL_}GPIO is enabled.

This commit fixes the following errors:
* undefined reference to `dm_gpio_get_value
* undefined reference to `gpio_request_by_name'

Signed-off-by: Fabien Parent 
---
 drivers/mmc/mtk-sd.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index e668df7017..4c997977d7 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -269,7 +269,7 @@ struct msdc_host {
bool builtin_cd;
 
/* card detection / write protection GPIOs */
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
struct gpio_desc gpio_wp;
struct gpio_desc gpio_cd;
 #endif
@@ -849,7 +849,7 @@ static int msdc_ops_get_cd(struct udevice *dev)
return !(val & MSDC_PS_CDSTS);
}
 
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
if (!host->gpio_cd.dev)
return 1;
 
@@ -863,7 +863,7 @@ static int msdc_ops_get_wp(struct udevice *dev)
 {
struct msdc_host *host = dev_get_priv(dev);
 
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
if (!host->gpio_wp.dev)
return 0;
 
@@ -1332,7 +1332,7 @@ static int msdc_ofdata_to_platdata(struct udevice *dev)
if (ret < 0)
return ret;
 
-#ifdef CONFIG_DM_GPIO
+#if IS_ENABLED(DM_GPIO)
gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN);
gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
 #endif
-- 
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[U-Boot] [PATCH v2 0/7] mmc: sunxi: Enable DM_MMC

V2 for previous version[1] changes, for enabling DM_MMC
on Allwinner platform.

Changes for v2:
- update the 'reset enablement' logic to do
  required SoC's

Note: All changes available at u-boot-sunxi/next

[1] https://patchwork.ozlabs.org/cover/1023710/

Any comments?
Jagan.

Jagan Teki (7):
  mmc: sunxi: Configure reset support for DM_MMC
  mmc: sunxi: Add A83T emmc compatible
  mmc: sunxi: Add mmc, emmc H5/A64 compatible
  mmc: sunxi: Add DM_MMC support for H6
  mmc: sunxi: Add DM_MMC support for A80
  arm: sunxi: Enable DM_MMC
  arm: dts: sunxi: Enumerate MMC2 as MMC1

 arch/arm/Kconfig  |  1 +
 arch/arm/dts/sunxi-u-boot.dtsi|  4 +
 .../include/asm/arch-sunxi/clock_sun50i_h6.h  |  3 +
 arch/arm/mach-sunxi/Kconfig   |  1 -
 configs/Linksprite_pcDuino3_defconfig |  1 -
 drivers/mmc/sunxi_mmc.c   | 73 ++-
 6 files changed, 79 insertions(+), 4 deletions(-)

-- 
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[U-Boot] [PATCH v2 2/7] mmc: sunxi: Add A83T emmc compatible

Add emmc compatible for A83T SoC.

Signed-off-by: Jagan Teki 
---
 drivers/mmc/sunxi_mmc.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 0e53701c5b..c25967afd1 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -710,6 +710,10 @@ static const struct udevice_id sunxi_mmc_ids[] = {
  .compatible = "allwinner,sun7i-a20-mmc",
  .data = (ulong)&sun7i_a20_variant,
},
+   {
+ .compatible = "allwinner,sun8i-a83t-emmc",
+ .data = (ulong)&sun7i_a20_variant,
+   },
{ /* sentinel */ }
 };
 
-- 
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[U-Boot] [PATCH v2 1/7] mmc: sunxi: Configure reset support for DM_MMC

Start with Allwinner A31, mmc controllers do support reset
control bit. This code add support to enable the reset control
start from SUN6I even though it share same compatible between
SUN4I and SUN6I.

Signed-off-by: Jagan Teki 
---
 drivers/mmc/sunxi_mmc.c | 21 +++--
 1 file changed, 19 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 302332bf97..0e53701c5b 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -21,8 +21,11 @@
 
 #ifdef CONFIG_DM_MMC
 struct sunxi_mmc_variant {
+   bool has_reset;
u16 gate_offset;
u16 mclk_offset;
+   u16 reset_offset;
+   u8 reset_start_bit;
 };
 #endif
 
@@ -609,7 +612,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
struct sunxi_mmc_priv *priv = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
struct ofnode_phandle_args args;
-   u32 *gate_reg, *ccu_reg;
+   u32 *gate_reg, *reset_reg, *ccu_reg;
int bus_width, ret;
 
cfg->name = dev->name;
@@ -644,6 +647,12 @@ static int sunxi_mmc_probe(struct udevice *dev)
gate_reg = (void *)ccu_reg + priv->variant->gate_offset;
setbits_le32(gate_reg, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
 
+   if ((!IS_ENABLED(CONFIG_MACH_SUN7I)) && priv->variant->has_reset) {
+   reset_reg = (void *)ccu_reg + priv->variant->reset_offset;
+   setbits_le32(reset_reg, BIT(priv->mmc_no +
+priv->variant->reset_start_bit));
+   }
+
ret = mmc_set_mod_clk(priv, 2400);
if (ret)
return ret;
@@ -680,6 +689,14 @@ static const struct sunxi_mmc_variant sun4i_a10_variant = {
.mclk_offset = 0x88,
 };
 
+static const struct sunxi_mmc_variant sun7i_a20_variant = {
+   .has_reset = true,
+   .gate_offset = 0x60,
+   .mclk_offset = 0x88,
+   .reset_offset = 0x2c0,
+   .reset_start_bit = 8,
+};
+
 static const struct udevice_id sunxi_mmc_ids[] = {
{
  .compatible = "allwinner,sun4i-a10-mmc",
@@ -691,7 +708,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
},
{
  .compatible = "allwinner,sun7i-a20-mmc",
- .data = (ulong)&sun4i_a10_variant,
+ .data = (ulong)&sun7i_a20_variant,
},
{ /* sentinel */ }
 };
-- 
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[U-Boot] [PATCH v2 6/7] arm: sunxi: Enable DM_MMC

Enable DM_MMC for all Allwinner SoCs, this will eventually
enable BLK.

Also removed DM_MMC enablement in few parts of sunxi
configurations.

Signed-off-by: Jagan Teki 
---
 arch/arm/Kconfig  | 1 +
 arch/arm/mach-sunxi/Kconfig   | 1 -
 configs/Linksprite_pcDuino3_defconfig | 1 -
 3 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a23cbd5719..075c3dfe81 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -851,6 +851,7 @@ config ARCH_SUNXI
select DM_ETH
select DM_GPIO
select DM_KEYBOARD
+   select DM_MMC if MMC
select DM_SERIAL
select DM_USB if DISTRO_DEFAULTS
select OF_BOARD_SETUP
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 3c54f5106d..74e234cded 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -154,7 +154,6 @@ config MACH_SUN4I
bool "sun4i (Allwinner A10)"
select CPU_V7A
select ARM_CORTEX_CPU_IS_UP
-   select DM_MMC if MMC
select DM_SCSI if SCSI
select PHY_SUN4I_USB
select DRAM_SUN4I
diff --git a/configs/Linksprite_pcDuino3_defconfig 
b/configs/Linksprite_pcDuino3_defconfig
index 9156f132d1..18f658e96b 100644
--- a/configs/Linksprite_pcDuino3_defconfig
+++ b/configs/Linksprite_pcDuino3_defconfig
@@ -14,7 +14,6 @@ CONFIG_SPL_I2C_SUPPORT=y
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3"
 CONFIG_SCSI_AHCI=y
-CONFIG_DM_MMC=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_MII=y
 CONFIG_SUN7I_GMAC=y
-- 
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[U-Boot] [PATCH v2 5/7] mmc: sunxi: Add DM_MMC support for A80

Unlike other Allwinner SoC's, A80 comes with different ahb
gate clock offset values and also has mmc common controller.
So support them via driver data.

Cc: Rask Ingemann Lambertsen 
Signed-off-by: Jagan Teki 
---
 drivers/mmc/sunxi_mmc.c | 24 
 1 file changed, 24 insertions(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 5b9ac5f82c..7fab88c47f 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -22,6 +22,7 @@
 #ifdef CONFIG_DM_MMC
 struct sunxi_mmc_variant {
bool has_reset;
+   bool has_mmc_common;
u16 gate_offset;
u16 mclk_offset;
u16 reset_offset;
@@ -653,6 +654,19 @@ static int sunxi_mmc_probe(struct udevice *dev)
 priv->variant->reset_start_bit));
}
 
+   if (priv->variant->has_mmc_common) {
+   u32 *mmc_config_clk, *mmc_common_base;
+
+   ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 
0,
+ 0, &args);
+   if (ret)
+   return ret;
+   mmc_config_clk = (u32 *)ofnode_get_addr(args.node);
+
+   mmc_common_base = (void *)mmc_config_clk + (priv->mmc_no * 4);
+   setbits_le32(mmc_common_base, BIT(18) | BIT(16));
+   }
+
ret = mmc_set_mod_clk(priv, 2400);
if (ret)
return ret;
@@ -697,6 +711,12 @@ static const struct sunxi_mmc_variant sun7i_a20_variant = {
.reset_start_bit = 8,
 };
 
+static const struct sunxi_mmc_variant sun9i_a80_variant = {
+   .has_mmc_common = true,
+   .gate_offset = 0x580,
+   .mclk_offset = 0x410,
+};
+
 static const struct sunxi_mmc_variant sun50i_h6_variant = {
.has_reset = true,
.gate_offset = 0x84c,
@@ -722,6 +742,10 @@ static const struct udevice_id sunxi_mmc_ids[] = {
  .compatible = "allwinner,sun8i-a83t-emmc",
  .data = (ulong)&sun7i_a20_variant,
},
+   {
+ .compatible = "allwinner,sun9i-a80-mmc",
+ .data = (ulong)&sun9i_a80_variant,
+   },
{
  .compatible = "allwinner,sun50i-a64-mmc",
  .data = (ulong)&sun7i_a20_variant,
-- 
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[U-Boot] [PATCH v2 3/7] mmc: sunxi: Add mmc, emmc H5/A64 compatible

Added H5, A64 compatible for mmc and emmc.

Signed-off-by: Jagan Teki 
---
 drivers/mmc/sunxi_mmc.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index c25967afd1..b1c177bba3 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -714,6 +714,14 @@ static const struct udevice_id sunxi_mmc_ids[] = {
  .compatible = "allwinner,sun8i-a83t-emmc",
  .data = (ulong)&sun7i_a20_variant,
},
+   {
+ .compatible = "allwinner,sun50i-a64-mmc",
+ .data = (ulong)&sun7i_a20_variant,
+   },
+   {
+ .compatible = "allwinner,sun50i-a64-emmc",
+ .data = (ulong)&sun7i_a20_variant,
+   },
{ /* sentinel */ }
 };
 
-- 
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[U-Boot] [PATCH v2 4/7] mmc: sunxi: Add DM_MMC support for H6

Unlike other Allwinner SoC's, H6 comes with different
clock and reset control offset values. So support them
via driver data.

Signed-off-by: Jagan Teki 
---
 .../arm/include/asm/arch-sunxi/clock_sun50i_h6.h |  3 +++
 drivers/mmc/sunxi_mmc.c  | 16 
 2 files changed, 19 insertions(+)

diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h 
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index e36937059b..baf9b2e6e2 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -301,6 +301,9 @@ struct sunxi_ccm_reg {
 #define DRAM_CLK_SRC_PLL5  (0 << 24)
 #define DRAM_CLK_M(m)  (((m)-1) << 0)
 
+/* MMC ahb clock bit field */
+#define AHB_GATE_OFFSET_MMC(n) ((n))
+
 /* MMC clock bit field */
 #define CCM_MMC_CTRL_M(x)  ((x) - 1)
 #define CCM_MMC_CTRL_N(x)  ((x) << 8)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index b1c177bba3..5b9ac5f82c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -697,6 +697,14 @@ static const struct sunxi_mmc_variant sun7i_a20_variant = {
.reset_start_bit = 8,
 };
 
+static const struct sunxi_mmc_variant sun50i_h6_variant = {
+   .has_reset = true,
+   .gate_offset = 0x84c,
+   .mclk_offset = 0x830,
+   .reset_offset = 0x84c,
+   .reset_start_bit = 16,
+};
+
 static const struct udevice_id sunxi_mmc_ids[] = {
{
  .compatible = "allwinner,sun4i-a10-mmc",
@@ -722,6 +730,14 @@ static const struct udevice_id sunxi_mmc_ids[] = {
  .compatible = "allwinner,sun50i-a64-emmc",
  .data = (ulong)&sun7i_a20_variant,
},
+   {
+ .compatible = "allwinner,sun50i-h6-mmc",
+ .data = (ulong)&sun50i_h6_variant,
+   },
+   {
+ .compatible = "allwinner,sun50i-h6-emmc",
+ .data = (ulong)&sun50i_h6_variant,
+   },
{ /* sentinel */ }
 };
 
-- 
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[U-Boot] [PATCH v2 7/7] arm: dts: sunxi: Enumerate MMC2 as MMC1

Environment and fastboot MMC devices are configured based number
of mmc slots defined on particular board in sunxi platform.

If number of slots are not more than 1, it assigns 0 which usually mmc
device on SD slot. With DM_MMC it is detected as 0 since mmc0 node always
be an mmc device.

If number of slots are more than 1, it assigns 1 which assumes 0 is mmc
device and 1 is emmc device. But with DM_MMC there is chance of detecting
emmc as device 2 since mmc1 is SDIO as per devicetree definition.

So override mmc2 to mmc1 in sunxi dtsi, this will eventually detect mmc2
as mmc 1 device even if the board dts has mmc0, mmc1, mmc2.

Some platforms like A20 has mmc0...mmc3, but there is no usecases now for
enabling all mmc controllers in any of A20 board dts files.

Signed-off-by: Jagan Teki 
---
 arch/arm/dts/sunxi-u-boot.dtsi | 4 
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 8a9f2a6417..fdd4c80aa4 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -1,6 +1,10 @@
 #include 
 
 / {
+   aliases {
+   mmc1 = &mmc2;
+   };
+
binman {
filename = "u-boot-sunxi-with-spl.bin";
pad-byte = <0xff>;
-- 
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[U-Boot] [PATCH 1/2] Kconfig: Migrate CONFIG_BUILD_TARGET

Migrate CONFIG_BUILD_TARGET into Kconfig.

Signed-off-by: Jagan Teki 
---
 Kconfig   | 13 +
 README|  7 ---
 arch/arm/mach-mvebu/include/mach/config.h |  5 -
 configs/SBx81LIFKW_defconfig  |  1 +
 configs/SBx81LIFXCAT_defconfig|  1 +
 configs/dreamplug_defconfig   |  1 +
 configs/ds109_defconfig   |  1 +
 configs/guruplug_defconfig|  1 +
 configs/ib62x0_defconfig  |  1 +
 configs/nsa310s_defconfig |  1 +
 configs/sheevaplug_defconfig  |  1 +
 include/configs/SBx81LIFKW.h  |  1 -
 include/configs/SBx81LIFXCAT.h|  1 -
 include/configs/ib62x0.h  |  3 ---
 include/configs/mv-plug-common.h  |  3 ---
 include/configs/nsa310s.h |  3 ---
 include/configs/rcar-gen3-common.h|  1 -
 include/configs/socfpga_common.h  |  3 ---
 include/configs/sunxi-common.h|  1 -
 scripts/config_whitelist.txt  |  1 -
 20 files changed, 21 insertions(+), 29 deletions(-)

diff --git a/Kconfig b/Kconfig
index aff7b2e00a..3a3a8d4d5b 100644
--- a/Kconfig
+++ b/Kconfig
@@ -224,6 +224,19 @@ config BUILD_ROM
  which are not shipped in the U-Boot source tree.
  Please, see doc/README.x86 for details.
 
+config BUILD_TARGET
+   string "Build target special images"
+   default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
+   default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
+   default "u-boot-elf.srec" if RCAR_GEN3
+   default "u-boot.itb" if ARCH_SUNXI && ARM64
+   help
+ Some SoCs need special image types (e.g. U-Boot binary
+ with a special header) as build targets. By defining
+ CONFIG_BUILD_TARGET in the SoC / board header, this
+ special image will be automatically built upon calling
+ make / buildman.
+
 endmenu# General setup
 
 menu "Boot images"
diff --git a/README b/README
index 17d56b8034..01ad69e926 100644
--- a/README
+++ b/README
@@ -1998,13 +1998,6 @@ The following options need to be configured:
200 ms.
 
 - Configuration Management:
-   CONFIG_BUILD_TARGET
-
-   Some SoCs need special image types (e.g. U-Boot binary
-   with a special header) as build targets. By defining
-   CONFIG_BUILD_TARGET in the SoC / board header, this
-   special image will be automatically built upon calling
-   make / buildman.
 
CONFIG_IDENT_STRING
 
diff --git a/arch/arm/mach-mvebu/include/mach/config.h 
b/arch/arm/mach-mvebu/include/mach/config.h
index f165d10018..e3235fc67e 100644
--- a/arch/arm/mach-mvebu/include/mach/config.h
+++ b/arch/arm/mach-mvebu/include/mach/config.h
@@ -40,11 +40,6 @@
 #defineCONFIG_SYS_KWD_CONFIG   arch/arm/mach-mvebu/kwbimage.cfg
 #endif /* CONFIG_SYS_KWD_CONFIG */
 
-/* Add target to build it automatically upon "make" */
-#ifdef CONFIG_SPL
-#define CONFIG_BUILD_TARGET"u-boot-spl.kwb"
-#endif
-
 /* end of 16M scrubbed by training in bootrom */
 #define CONFIG_SYS_INIT_SP_ADDR0x00FF
 
diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig
index e0ce1595c5..52bb70ae8c 100644
--- a/configs/SBx81LIFKW_defconfig
+++ b/configs/SBx81LIFKW_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_SBx81LIFKW=y
 CONFIG_IDENT_STRING="\nSBx81LIFKW"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_BOOTDELAY=3
+CONFIG_BUILD_TARGET="u-boot.kwb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SILENT_U_BOOT_ONLY=y
 CONFIG_MISC_INIT_R=y
diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig
index 4a6e05844f..b322ab0959 100644
--- a/configs/SBx81LIFXCAT_defconfig
+++ b/configs/SBx81LIFXCAT_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_SBx81LIFXCAT=y
 CONFIG_IDENT_STRING="\nSBx81LIFXCAT"
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_BOOTDELAY=3
+CONFIG_BUILD_TARGET="u-boot.kwb"
 CONFIG_SILENT_CONSOLE=y
 CONFIG_SILENT_U_BOOT_ONLY=y
 CONFIG_MISC_INIT_R=y
diff --git a/configs/dreamplug_defconfig b/configs/dreamplug_defconfig
index d3263cf9cd..762521f97d 100644
--- a/configs/dreamplug_defconfig
+++ b/configs/dreamplug_defconfig
@@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="\nMarvell-DreamPlug"
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_BOOTDELAY=3
+CONFIG_BUILD_TARGET="u-boot.kwb"
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_HUSH_PARSER=y
 # CONFIG_CMD_FLASH is not set
diff --git a/configs/ds109_defconfig b/configs/ds109_defconfig
index 352403e573..b72174eada 100644
--- a/configs/ds109_defconfig
+++ b/configs/ds109_defconfig
@@ -5,6 +5,7 @@ CONFIG_TARGET_DS109=y
 CONFIG_NR_DRAM_BANKS=2
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_HUSH_PARSER=y
+CONFIG_BUILD_TARGET="u-boot.kwb"
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_IDE=y
 CONFIG_CMD_I2C=y
diff --git a/configs/guruplug_defconfig b/configs/guruplug_defconfig
index 99

[U-Boot] [PATCH 2/2] Kconfig: Add u-boot.itb BUILD_TARGET for RK3368/3399

Add u-boot.itb BUILD_TARGET for Rockchip RK3368 and RK3399
SoC, this can get rid of building itb explicitly with
'make u-boot.itb' all required images will now build just
by make.

Signed-off-by: Jagan Teki 
---
 Kconfig| 1 +
 board/rockchip/evb_rk3399/README   | 1 -
 board/theobroma-systems/lion_rk3368/README | 9 ++---
 board/theobroma-systems/puma_rk3399/README | 1 -
 board/vamrs/rock960_rk3399/README  | 1 -
 5 files changed, 3 insertions(+), 10 deletions(-)

diff --git a/Kconfig b/Kconfig
index 3a3a8d4d5b..247ace3ce0 100644
--- a/Kconfig
+++ b/Kconfig
@@ -230,6 +230,7 @@ config BUILD_TARGET
default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
default "u-boot-elf.srec" if RCAR_GEN3
default "u-boot.itb" if ARCH_SUNXI && ARM64
+   default "u-boot.itb" if ROCKCHIP_RK3368 || ROCKCHIP_RK3399
help
  Some SoCs need special image types (e.g. U-Boot binary
  with a special header) as build targets. By defining
diff --git a/board/rockchip/evb_rk3399/README b/board/rockchip/evb_rk3399/README
index 8321467046..c388f269c1 100644
--- a/board/rockchip/evb_rk3399/README
+++ b/board/rockchip/evb_rk3399/README
@@ -58,7 +58,6 @@ Compile the U-Boot
   for firefly-rk3399, use below instead:
   > make firefly-rk3399_defconfig
   > make
-  > make u-boot.itb
 
   Get spl/u-boot-spl.bin and u-boot.itb in this step.
 
diff --git a/board/theobroma-systems/lion_rk3368/README 
b/board/theobroma-systems/lion_rk3368/README
index 83e4332984..241d4d9ec8 100644
--- a/board/theobroma-systems/lion_rk3368/README
+++ b/board/theobroma-systems/lion_rk3368/README
@@ -14,18 +14,13 @@ Configure U-Boot
   > cd ../u-boot
   > make lion-rk3368_defconfig
 
-Build the TPL/SPL stage
-===
+Build the TPL/SPL, U-Boot proper and a FIT image including the ATF
+==
 
   > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm
   > tools/mkimage -n rk3368 -T rksd -d tpl/u-boot-tpl.bin spl-3368.img
   > cat spl/u-boot-spl-dtb.bin >> spl-3368.img
 
-Build the full U-Boot and a FIT image including the ATF
-===
-
-  > make CROSS_COMPILE=aarch64-unknown-elf- ARCH=arm u-boot.itb
-
 Flash the image
 ===
 
diff --git a/board/theobroma-systems/puma_rk3399/README 
b/board/theobroma-systems/puma_rk3399/README
index f67dfb451f..c06c9650b8 100644
--- a/board/theobroma-systems/puma_rk3399/README
+++ b/board/theobroma-systems/puma_rk3399/README
@@ -60,7 +60,6 @@ Creating a SPL image for SD-Card/eMMC
 Creating a SPL image for SPI-NOR
   > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img
 Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree
-  > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb
 
 Flash the image
 ===
diff --git a/board/vamrs/rock960_rk3399/README 
b/board/vamrs/rock960_rk3399/README
index d14399090e..c5c675c4ea 100644
--- a/board/vamrs/rock960_rk3399/README
+++ b/board/vamrs/rock960_rk3399/README
@@ -61,7 +61,6 @@ Compile the U-Boot
   > export CROSS_COMPILE=aarch64-linux-gnu-
   > make rock960-rk3399_defconfig
   > make
-  > make u-boot.itb
 
 Compile the rkdeveloptool
 =
-- 
2.18.0.321.gffc6fa0e3

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Re: [U-Boot] [PATCH 01/11] riscv: Rename cpu/qemu to cpu/generic


On 01/17/2019 11:38 AM, Anup Patel wrote:

The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel 


Reviewed-by: Alexander Graf 


Alex

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Re: [U-Boot] [PATCH 02/11] riscv: Add asm/dma-mapping.h for DMA mappings


On 01/17/2019 11:38 AM, Anup Patel wrote:

This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 



Reviewed-by: Alexander Graf 

Alex
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Re: [U-Boot] [PATCH 03/11] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems


On 01/17/2019 11:38 AM, Anup Patel wrote:

On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.

To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.

Signed-off-by: Anup Patel 
Signed-off-by: Atish Patra 


You could probably write that with MIN() more easily, but this way works 
fine too.


Reviewed-by: Alexander Graf 

Alex

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Re: [U-Boot] [PATCH 04/11] net: macb: Fix clk API usage for RISC-V systems


On 01/17/2019 11:38 AM, Anup Patel wrote:

This patch does following fixes in MACB ethernet driver
for using it on RISC-V systems (particularly QEMU sifive_u
machine):
1. asm/arch/clk.h is not available on RISC-V port so include
it only for non-RISC-V systems.
2. Don't fail in macb_enable_clk() if clk_enable() returns
-ENOSYS because we get -ENOSYS for fixed-rate clocks.

Signed-off-by: Anup Patel 
Reviewed-by: Bin Meng 
---
  drivers/net/macb.c | 4 +++-
  1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 94c89c762b..9a06b523cc 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -38,7 +38,9 @@
  #include 
  #include 
  #include 
+#ifndef CONFIG_RISCV
  #include 
+#endif
  #include 
  
  #include "macb.h"

@@ -1066,7 +1068,7 @@ static int macb_enable_clk(struct udevice *dev)
 */
  #ifndef CONFIG_MACB_ZYNQ
ret = clk_enable(&clk);


If clk.h is not available, who exports clk_enable() then; and why is the 
included needed in the first place?



Alex


-   if (ret)
+   if (ret && ret != -ENOSYS)
return ret;
  #endif
  



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Re: [U-Boot] [uboot-snps-arc] [PATCH v3 2/5] dts: switch spi-flash to jedec, spi-nor compatible

2019-01-17 Thread Eugeniy Paltsev

Hi Neil,

On Tue, 2019-01-15 at 13:59 +0100, Neil Armstrong wrote:
> There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot
> dts files. This compatible has been added in sf_probe, let use it.
> 
> This patch switches to jedec,spi-nor when spi-flash is used in the DTS
> and DTSI files, and removed spi-flash when jedec,spi-nor is already
> present.
> 
> The x86 dts are switched in a separate commit since it depends on a change
> in fdtdec.
> 
> Signed-off-by: Neil Armstrong 
> Acked-by: Stefan Roese 
> Reviewed-by: Simon Goldschmidt 
> ---

For the ARC part:
>  arch/arc/dts/axs10x_mb.dtsi   |  2 +-
>  arch/arc/dts/hsdk.dts |  2 +-

Reviewed-by: Evgeniy Paltsev 

> diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
> index dfc03810ca..b5aacd5170 100644
> --- a/arch/arc/dts/axs10x_mb.dtsi
> +++ b/arch/arc/dts/axs10x_mb.dtsi
> @@ -71,7 +71,7 @@
>   clock-names = "spi_clk";
>   cs-gpio = <&cs_gpio 0>;
>   spi_flash@0 {
> - compatible = "spi-flash";
> + compatible = "jedec,spi-nor";
>   reg = <0>;
>   spi-max-frequency = <400>;
>   };
> diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts
> index f024b96925..5e9ba054a4 100644
> --- a/arch/arc/dts/hsdk.dts
> +++ b/arch/arc/dts/hsdk.dts
> @@ -96,7 +96,7 @@
>   clock-names = "spi_clk";
>   cs-gpio = <&cs_gpio 0>;
>   spi_flash@0 {
> - compatible = "spi-flash";
> + compatible = "jedec,spi-nor";
>   reg = <0>;
>   spi-max-frequency = <400>;
>   };
> 
-- 
 Eugeniy Paltsev
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Re: [U-Boot] [PATCH 05/11] net: macb: Fix GEM hardware detection