Re: [U-Boot] [PATCH] mtd: qspi: support read the flag status in fspi driver
Hi, On 09/02/19 10:59 PM, Jagan Teki wrote: > On Mon, Jan 7, 2019 at 2:24 PM Ye Li wrote: >> >> From: Han Xu >> >> Support to read the flag status in driver to avoid the spi-nor framework >> wait_for_ready hang issue. >> >> Signed-off-by: Han Xu >> --- >> drivers/spi/fsl_qspi.c | 47 +++ >> 1 file changed, 47 insertions(+) >> >> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c >> index 1987a72..ed0e649 100644 >> --- a/drivers/spi/fsl_qspi.c >> +++ b/drivers/spi/fsl_qspi.c >> @@ -47,6 +47,7 @@ DECLARE_GLOBAL_DATA_PTR; >> #endif >> #define SEQID_WRAR 13 >> #define SEQID_RDAR 14 >> +#define SEQID_RDFSR15 >> >> /* QSPI CMD */ >> #define QSPI_CMD_PP0x02/* Page program (up to 256 bytes) */ >> @@ -57,6 +58,7 @@ DECLARE_GLOBAL_DATA_PTR; >> #define QSPI_CMD_CHIP_ERASE0xc7/* Erase whole flash chip */ >> #define QSPI_CMD_SE0xd8/* Sector erase (usually 64KiB) */ >> #define QSPI_CMD_RDID 0x9f/* Read JEDEC ID */ >> +#define QSPI_CMD_FLAG_SR 0x70/* Read FLAG STATUS*/ > > NAK, need to handle this from flash side. better keep working on that front. > U-Boot now supports spi-mem abstraction just like kernel. Could you move fsl_qspi to use spi-mem APIs to get rid of using opcodes directly within the driver? -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] mtd: add spi flash id s25fl064l
On 08/02/19 3:33 PM, Heiko Schocher wrote:
> Add support for SPANSION s25fl064l
>
> Signed-off-by: Heiko Schocher
> ---
>
> Changes in v2:
> - s/s25f064l/s25fl064l
> as Vignesh R suggested
>
> drivers/mtd/spi/spi-nor-ids.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 3215e2431d..ef18a0568e 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -187,6 +187,7 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) },
> { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K |
> SPI_NOR_DUAL_READ) },
> + { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> #endif
> #ifdef CONFIG_SPI_FLASH_SST /* SST */
>
Acked-by: Vignesh R
--
Regards
Vignesh
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Re: [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
On Tue, 2019-02-05 at 09:46 +0100, Marek Vasut wrote:
> On 2/1/19 5:02 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:25 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:48 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee
> > > > > >
> > > > > > This patch adds description on properties about file name
> > > > > > used
> > > > > > for
> > > > > > both
> > > > > > peripheral bitstream and core bitstream.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee
> > > > > >
> > > > > > ---
> > > > > >
> > > > > > changes for v7
> > > > > > - Provided example of setting FPGA FIT image for both early
> > > > > > IO
> > > > > > release
> > > > > > and full release FPGA configuration.
> > > > > > ---
> > > > > > .../fpga/altera-socfpga-a10-fpga-mgr.txt | 34
> > > > > > +-
> > > > > > 1 file changed, 33 insertions(+), 1 deletion(-)
> > > > > >
> > > > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-
> > > > > > a10-
> > > > > > fpga-
> > > > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > index 2fd8e7a..5f81a32 100644
> > > > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > fpga-
> > > > > > mgr.txt
> > > > > > @@ -7,8 +7,39 @@ Required properties:
> > > > > > - The second index is for writing FPGA
> > > > > > configuration data.
> > > > > > - resets : Phandle and reset specifier for the
> > > > > > device's
> > > > > > reset.
> > > > > > - clocks : Clocks used by the device.
> > > > > > +- altr,bitstream : File name for FPGA peripheral bitstream
> > > > > > which
> > > > > > is used
> > > > > > + to initialize FPGA IOs, PLL, IO48 and
> > > > > > DDR.
> > > > > > This
> > > > > > bitstream is
> > > > > > + required to get DDR up running.
> > > > > > + or
> > > > > > + File name for full bitstream, consist
> > > > > > of
> > > > > > peripheral bitstream
> > > > > > + and core bitstream.
> > > > > > +- altr,bitstream-core(optional) : File name for core
> > > > > > bitstream
> > > > > > which contains
> > > > > Is the name of the property 'altr,bitstream-core(optional)' ?
> > > > > I
> > > > > think
> > > > > the "optional" part should be in the description.
> > > > Yes, you are right.
> > > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > >
> > > > > > + FPGA design which is
> > > > > > used to
> > > > > > program FPGA CRAM
> > > > > > + and ERAM.
> > > > > >
> > > > > > -Example:
> > > > > > +Example: Bundles both peripheral bitstream and core
> > > > > > bitstream
> > > > > > into
> > > > > > FIT image
> > > > > > + called fit_spl_fpga.itb. This FIT image can be
> > > > > > created
> > > > > > through running
> > > > > > + this command: tools/mkimage
> > > > > > + -E -p 400
> > > > > > + -f board/altera/arria10-
> > > > > > socdk/fit_spl_fpga.its
> > > > > > + fit_spl_fpga.itb
> > > > > > +
> > > > > > + For details of describing structure and contents
> > > > > > of
> > > > > > the
> > > > > > FIT image,
> > > > > > + please refer board/altera/arria10-
> > > > > > socdk/fit_spl_fpga.its
> > > > > > +
> > > > > > +- Examples for booting with early IO release, and enter
> > > > > > early
> > > > > > user
> > > > > > mode:
> > > > > > +
> > > > > > + fpga_mgr: fpga-mgr@ffd03000 {
> > > > > > + compatible = "altr,socfpga-a10-fpga-mgr";
> > > > > > + reg = <0xffd03000 0x100
> > > > > > + 0xffcfe400 0x20>;
> > > > > > + clocks = <&l4_mp_clk>;
> > > > > > + resets = <&rst FPGAMGR_RESET>;
> > > > > > + altr,bitstream = "fit_spl_fpga.itb";
> > > > > > + altr,bitstream-core = "fit_spl_fpga.itb";
> > > > > It's the same file, why does it use two properties ?
> > > > 1. Allows user to run optional for program core. When "" is set
> > > > to
> > > > altr,bitstream-core, then SPL would skip programming FPGA with
> > > > core, so
> > > > user can program it later on U-Boot or Linux.
> > > You can just pass in a fitImage with only the periph image in it
> > > in
> > > such
> > > a case.
> > What if user want to program the core on U-Boot? User need to
> > create
> > two FIT images, one FIT with periph image, and another FIT with
> > core
> > image only.
> >
> > Current implementation supports one FIT image for above
> > configuration.
> What if user want to program the core on U-Boot in this
> implementation?
> It is not possible either, is it ?
There are fe
[U-Boot] [PATCH v7 00/15] SiFive FU540 Support
This patchset adds SiFive Freedom Unleashed (FU540) support
to RISC-V U-Boot.
The patches are based upon latest U-Boot source tree
(git://git.denx.de/u-boot.git) at commit id
dbe70c7d4e3d5c705a98d82952e05a591efd0683
All drivers namely: SiFive PRCI, SiFive Serial, and Cadance
MACB Ethernet work fine on actual SiFive Unleashed board and
QEMU sifive_u machine.
Changes since v6:
- Rebased patches to latest U-Boot source tree
- Droped PATCH1 and PATCH2. Instead added a PATCH to
select CREATE_ARCH_SYMLINK for RISC-V
- Few typo fixes in SiFive FU540 readme
Changes since v5:
- Added PATCH16 to fix INITRD passing to Linux using bootm
for U-Boot RISC-V
Changes since v4:
- Removed #ifndef from macb_enable_clk() in PATCH7
- Updated test/dm/clk.c in PATCH10 to test fixed factor clock
using sandbox
Changes since v3:
- Added patch to un-ignore arch/riscv/include/asm/arch
- Added patch to fix mrproper make target to only remove
arch/*/include/asm/arch paths which are symlinks
- Added patch to have place-holder asm/arch/clk.h for RISC-V
- Removed "#ifndef CONFIG_RISCV" from macb clk API patch
Changes since v2:
- Fixed typo in PATCH3 comments
- Removed "#if" from clk_fixed_factor_ofdata_to_platdata() in PATCH7
- Added PATCH12 for SiFive FU540 README guide
Changes since v1:
- Re-ordered SoB in patches with multiple SoB
- Simplified board_get_usable_ram_top() added by PATCH3
Anup Patel (10):
riscv: Enable create symlink using kconfig
riscv: Rename cpu/qemu to cpu/generic
riscv: Add asm/dma-mapping.h for DMA mappings
riscv: Add place-holder asm/arch/clk.h for driver compilation
riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
net: macb: Fix clk API usage for RISC-V systems
clk: Add SiFive FU540 PRCI clock driver
clk: Add fixed-factor clock driver
riscv: Add SiFive FU540 board support
riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
Atish Patra (5):
net: macb: Fix GEM hardware detection
drivers: serial_sifive: Fix baud rate calculation
drivers: serial_sifive: Skip baudrate config if no input clock
cpu: Bind timer driver for boot hart
doc: Add a readme guide for SiFive FU540
arch/Kconfig | 1 +
arch/riscv/Kconfig| 6 +-
arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +-
arch/riscv/cpu/{qemu => generic}/Makefile | 0
arch/riscv/cpu/{qemu => generic}/cpu.c| 0
arch/riscv/cpu/generic/dram.c | 37 ++
arch/riscv/cpu/qemu/dram.c| 17 -
arch/riscv/include/asm/arch-generic/clk.h | 14 +
arch/riscv/include/asm/config.h | 1 +
arch/riscv/include/asm/dma-mapping.h | 38 ++
arch/sandbox/dts/test.dts | 8 +
board/emulation/qemu-riscv/Kconfig| 4 +-
.../qemu-riscv => sifive/fu540}/Kconfig | 36 +-
board/sifive/fu540/MAINTAINERS| 9 +
board/sifive/fu540/Makefile | 5 +
board/sifive/fu540/fu540.c| 17 +
configs/sifive_fu540_defconfig| 11 +
doc/README.sifive-fu540 | 303 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 5 +-
drivers/clk/clk_fixed_factor.c| 72 +++
drivers/clk/sifive/Kconfig| 19 +
drivers/clk/sifive/Makefile | 5 +
.../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++
drivers/clk/sifive/fu540-prci.c | 604 ++
drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++
drivers/cpu/riscv_cpu.c | 7 +-
drivers/net/macb.c| 11 +-
drivers/serial/serial_sifive.c| 60 +-
include/configs/sifive-fu540.h| 43 ++
include/dt-bindings/clk/sifive-fu540-prci.h | 29 +
test/dm/clk.c | 5 +-
32 files changed, 1795 insertions(+), 66 deletions(-)
rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
create mode 100644 arch/riscv/cpu/generic/dram.c
delete mode 100644 arch/riscv/cpu/qemu/dram.c
create mode 100644 arch/riscv/include/asm/arch-generic/clk.h
create mode 100644 arch/riscv/include/asm/dma-mapping.h
copy board/{emulation/qemu-riscv => sifive/fu540}/Kconfig (57%)
create mode 100644 board/sifive/fu540/MAINTAINERS
create mode 100644 board/sifive/fu540/Makefile
create mode 100644 board/sifive/fu540/fu540.c
create mode 100644 configs/sifive_fu540_defconfig
create mode 100644 doc/README.sifive-fu540
create mode 100644 drivers/clk/clk_fixed_factor.c
create mode 100644 drivers/clk/sifive/Kconfig
create mode 100644 drivers/clk/sifive/Makefile
create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
create mode 100644 drivers/clk/sifive/fu540-prc
[U-Boot] [PATCH v7 01/15] riscv: Enable create symlink using kconfig
We select CREATE_ARCH_SYMLINK for RISC-V so that we can have include/asm/arch linked to include/asm/arch-xyz. Signed-off-by: Anup Patel --- arch/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/Kconfig b/arch/Kconfig index 35e2712fce..4ebc66227e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -61,6 +61,7 @@ config PPC config RISCV bool "RISC-V architecture" + select CREATE_ARCH_SYMLINK select SUPPORT_OF_CONTROL select OF_CONTROL select DM -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 04/15] riscv: Add place-holder asm/arch/clk.h for driver compilation
Some of the drivers (such as Cadence MACB ethernet driver) expect asm/arch/clk.h to be provided by arch support so we add place-holder asm/arch-generic/clk.h for RISC-V generic CPU. Signed-off-by: Anup Patel Reviewed-by: Lukas Auer --- arch/riscv/include/asm/arch-generic/clk.h | 14 ++ 1 file changed, 14 insertions(+) create mode 100644 arch/riscv/include/asm/arch-generic/clk.h diff --git a/arch/riscv/include/asm/arch-generic/clk.h b/arch/riscv/include/asm/arch-generic/clk.h new file mode 100644 index 00..1631f5f0bd --- /dev/null +++ b/arch/riscv/include/asm/arch-generic/clk.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + */ + +#ifndef __ASM_RISCV_ARCH_CLK_H +#define __ASM_RISCV_ARCH_CLK_H + +/* Note: This is a placeholder header for driver compilation. */ + +#endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 02/15] riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.
This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Reviewed-by: Bin Meng
---
arch/riscv/Kconfig| 2 +-
arch/riscv/cpu/{qemu => generic}/Kconfig | 2 +-
arch/riscv/cpu/{qemu => generic}/Makefile | 0
arch/riscv/cpu/{qemu => generic}/cpu.c| 0
arch/riscv/cpu/{qemu => generic}/dram.c | 0
board/emulation/qemu-riscv/Kconfig| 4 ++--
6 files changed, 4 insertions(+), 4 deletions(-)
rename arch/riscv/cpu/{qemu => generic}/Kconfig (91%)
rename arch/riscv/cpu/{qemu => generic}/Makefile (100%)
rename arch/riscv/cpu/{qemu => generic}/cpu.c (100%)
rename arch/riscv/cpu/{qemu => generic}/dram.c (100%)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index c45e4d73a8..6879047ff7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -22,7 +22,7 @@ source "board/emulation/qemu-riscv/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
-source "arch/riscv/cpu/qemu/Kconfig"
+source "arch/riscv/cpu/generic/Kconfig"
# architecture-specific options below
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/generic/Kconfig
similarity index 91%
rename from arch/riscv/cpu/qemu/Kconfig
rename to arch/riscv/cpu/generic/Kconfig
index f48751e6de..1d6ab5032d 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/generic/Kconfig
@@ -2,7 +2,7 @@
#
# Copyright (C) 2018, Bin Meng
-config QEMU_RISCV
+config GENERIC_RISCV
bool
select ARCH_EARLY_INIT_R
imply CPU
diff --git a/arch/riscv/cpu/qemu/Makefile b/arch/riscv/cpu/generic/Makefile
similarity index 100%
rename from arch/riscv/cpu/qemu/Makefile
rename to arch/riscv/cpu/generic/Makefile
diff --git a/arch/riscv/cpu/qemu/cpu.c b/arch/riscv/cpu/generic/cpu.c
similarity index 100%
rename from arch/riscv/cpu/qemu/cpu.c
rename to arch/riscv/cpu/generic/cpu.c
diff --git a/arch/riscv/cpu/qemu/dram.c b/arch/riscv/cpu/generic/dram.c
similarity index 100%
rename from arch/riscv/cpu/qemu/dram.c
rename to arch/riscv/cpu/generic/dram.c
diff --git a/board/emulation/qemu-riscv/Kconfig
b/board/emulation/qemu-riscv/Kconfig
index 0d865acf10..88d07d568e 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
default "emulation"
config SYS_CPU
- default "qemu"
+ default "generic"
config SYS_CONFIG_NAME
default "qemu-riscv"
@@ -18,7 +18,7 @@ config SYS_TEXT_BASE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
- select QEMU_RISCV
+ select GENERIC_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
--
2.17.1
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[U-Boot] [PATCH v7 06/15] net: macb: Fix clk API usage for RISC-V systems
Don't fail in macb_enable_clk() if clk_enable() returns -ENOSYS because we get -ENOSYS for fixed-rate clocks. Signed-off-by: Anup Patel Reviewed-by: Bin Meng --- drivers/net/macb.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c9ee22279a..0254e211e6 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -1061,14 +1061,13 @@ static int macb_enable_clk(struct udevice *dev) return -EINVAL; /* -* Zynq clock driver didn't support for enable or disable -* clock. Hence, clk_enable() didn't apply for Zynq +* If clock driver didn't support enable or disable then +* we get -ENOSYS from clk_enable(). To handle this, we +* don't fail for ret == -ENOSYS. */ -#ifndef CONFIG_MACB_ZYNQ ret = clk_enable(&clk); - if (ret) + if (ret && ret != -ENOSYS) return ret; -#endif clk_rate = clk_get_rate(&clk); if (!clk_rate) -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v7 10/15] drivers: serial_sifive: Fix baud rate calculation
From: Atish Patra
Compute the baud rate multipler with more precision.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
---
drivers/serial/serial_sifive.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index 341728a690..ea4d35d48c 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -33,16 +33,40 @@ struct uart_sifive {
};
struct sifive_uart_platdata {
- unsigned int clock;
+ unsigned long clock;
int saved_input_char;
struct uart_sifive *regs;
};
+/**
+ * Find minimum divisor divides in_freq to max_target_hz;
+ * Based on uart driver n SiFive FSBL.
+ *
+ * f_baud = f_in / (div + 1) => div = (f_in / f_baud) - 1
+ * The nearest integer solution requires rounding up as to not exceed
+ * max_target_hz.
+ * div = ceil(f_in / f_baud) - 1
+ * = floor((f_in - 1 + f_baud) / f_baud) - 1
+ * This should not overflow as long as (f_in - 1 + f_baud) does not exceed
+ * 2^32 - 1, which is unlikely since we represent frequencies in kHz.
+ */
+static inline unsigned int uart_min_clk_divisor(unsigned long in_freq,
+ unsigned long max_target_hz)
+{
+ unsigned long quotient =
+ (in_freq + max_target_hz - 1) / (max_target_hz);
+ /* Avoid underflow */
+ if (quotient == 0)
+ return 0;
+ else
+ return quotient - 1;
+}
+
/* Set up the baud rate in gd struct */
static void _sifive_serial_setbrg(struct uart_sifive *regs,
unsigned long clock, unsigned long baud)
{
- writel((u32)((clock / baud) - 1), ®s->div);
+ writel((uart_min_clk_divisor(clock, baud)), ®s->div);
}
static void _sifive_serial_init(struct uart_sifive *regs)
--
2.17.1
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[U-Boot] [PATCH v7 03/15] riscv: Add asm/dma-mapping.h for DMA mappings
This patch adds asm/dma-mapping.h for Linux-like DMA mappings
APIs required by some of the drivers (such as, Cadance MACB
Ethernet driver).
Signed-off-by: Anup Patel
Reviewed-by: Bin Meng
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
---
arch/riscv/include/asm/dma-mapping.h | 38
1 file changed, 38 insertions(+)
create mode 100644 arch/riscv/include/asm/dma-mapping.h
diff --git a/arch/riscv/include/asm/dma-mapping.h
b/arch/riscv/include/asm/dma-mapping.h
new file mode 100644
index 00..3d930c90ec
--- /dev/null
+++ b/arch/riscv/include/asm/dma-mapping.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2018 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel
+ */
+
+#ifndef __ASM_RISCV_DMA_MAPPING_H
+#define __ASM_RISCV_DMA_MAPPING_H
+
+#include
+
+#define dma_mapping_error(x, y)0
+
+static inline void *dma_alloc_coherent(size_t len, unsigned long *handle)
+{
+ *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len);
+ return (void *)*handle;
+}
+
+static inline void dma_free_coherent(void *addr)
+{
+ free(addr);
+}
+
+static inline unsigned long dma_map_single(volatile void *vaddr, size_t len,
+ enum dma_data_direction dir)
+{
+ return (unsigned long)vaddr;
+}
+
+static inline void dma_unmap_single(volatile void *vaddr, size_t len,
+ unsigned long paddr)
+{
+}
+
+#endif /* __ASM_RISCV_DMA_MAPPING_H */
--
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[U-Boot] [PATCH v7 07/15] net: macb: Fix GEM hardware detection
From: Atish Patra
Fix MID bit field check to correctly identify all GEM hardwares.
The check is updated as per macb driver in Linux location:
/drivers/net/ethernet/cadence/macb_main.c:259
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Acked-by: Joe Hershberger
---
drivers/net/macb.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 0254e211e6..182331f61d 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -143,7 +143,7 @@ struct macb_device {
static int macb_is_gem(struct macb_device *macb)
{
- return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
+ return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
}
#ifndef cpu_is_sama5d2
--
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[U-Boot] [PATCH v7 05/15] riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems
On 64bit systems, the DRAM top can be easily beyond 4GB and U-Boot
DMA mapping APIs will generate DMA addresses beyond 4GB. This
breaks DMA programming in 32bit DMA capable devices (such as
Cadence MACB ethernet). For example, If DRAM is more then 2GB
on QEMU sifive_u machine then Cadence MACB ethernet stops working
for U-Boot because it is a 32bit DMA capable device.
To handle 32bit DMA capable devices on 64bit systems, we provide
custom implementation of board_get_usable_ram_top() which ensures
that usable ram top is not more then 4GB. This in-turn ensures
that U-Boot always runs within 4GB hence DMA addresses generated
by DMA mapping APIs will be within 4GB too.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Reviewed-by: Bin Meng
---
arch/riscv/cpu/generic/dram.c | 20
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 84d87d2a7f..b7b1207235 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -5,6 +5,9 @@
#include
#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
@@ -15,3 +18,20 @@ int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+#ifdef CONFIG_64BIT
+ /*
+* Ensure that we run from first 4GB so that all
+* addresses used by U-Boot are 32bit addresses.
+*
+* This in-turn ensures that 32bit DMA capable
+* devices work fine because DMA mapping APIs will
+* provide 32bit DMA addresses only.
+*/
+ if (gd->ram_top > SZ_4G)
+ return SZ_4G;
+#endif
+ return gd->ram_top;
+}
--
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[U-Boot] [PATCH v7 13/15] riscv: Add SiFive FU540 board support
This patch adds SiFive FU540 board support. For now, only
SiFive serial, SiFive PRCI, and Cadance MACB drivers are
only enabled. The SiFive FU540 defconfig by default builds
U-Boot for S-Mode because U-Boot on SiFive FU540 will run
in S-Mode as payload of BBL or OpenSBI.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Reviewed-by: Bin Meng
---
arch/riscv/Kconfig | 4
board/sifive/fu540/Kconfig | 42 +
board/sifive/fu540/MAINTAINERS | 9 +++
board/sifive/fu540/Makefile| 5
board/sifive/fu540/fu540.c | 17 ++
configs/sifive_fu540_defconfig | 11 +
include/configs/sifive-fu540.h | 43 ++
7 files changed, 131 insertions(+)
create mode 100644 board/sifive/fu540/Kconfig
create mode 100644 board/sifive/fu540/MAINTAINERS
create mode 100644 board/sifive/fu540/Makefile
create mode 100644 board/sifive/fu540/fu540.c
create mode 100644 configs/sifive_fu540_defconfig
create mode 100644 include/configs/sifive-fu540.h
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6879047ff7..36512a8995 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -14,11 +14,15 @@ config TARGET_AX25_AE350
config TARGET_QEMU_VIRT
bool "Support QEMU Virt Board"
+config TARGET_SIFIVE_FU540
+ bool "Support SiFive FU540 Board"
+
endchoice
# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+source "board/sifive/fu540/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
new file mode 100644
index 00..6be3d88144
--- /dev/null
+++ b/board/sifive/fu540/Kconfig
@@ -0,0 +1,42 @@
+if TARGET_SIFIVE_FU540
+
+config SYS_BOARD
+ default "fu540"
+
+config SYS_VENDOR
+ default "sifive"
+
+config SYS_CPU
+ default "generic"
+
+config SYS_CONFIG_NAME
+ default "sifive-fu540"
+
+config SYS_TEXT_BASE
+ default 0x8000 if !RISCV_SMODE
+ default 0x8020 if RISCV_SMODE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select GENERIC_RISCV
+ imply CMD_DHCP
+ imply CMD_EXT2
+ imply CMD_EXT4
+ imply CMD_FAT
+ imply CMD_FS_GENERIC
+ imply CMD_NET
+ imply CMD_PING
+ imply CLK_SIFIVE
+ imply CLK_SIFIVE_FU540_PRCI
+ imply DOS_PARTITION
+ imply EFI_PARTITION
+ imply IP_DYN
+ imply ISO_PARTITION
+ imply MACB
+ imply MII
+ imply NET_RANDOM_ETHADDR
+ imply PHY_LIB
+ imply PHY_MSCC
+ imply SIFIVE_SERIAL
+
+endif
diff --git a/board/sifive/fu540/MAINTAINERS b/board/sifive/fu540/MAINTAINERS
new file mode 100644
index 00..702d803ad8
--- /dev/null
+++ b/board/sifive/fu540/MAINTAINERS
@@ -0,0 +1,9 @@
+SiFive FU540 BOARD
+M: Paul Walmsley
+M: Palmer Dabbelt
+M: Anup Patel
+M: Atish Patra
+S: Maintained
+F: board/sifive/fu540/
+F: include/configs/sifive-fu540.h
+F: configs/sifive_fu540_defconfig
diff --git a/board/sifive/fu540/Makefile b/board/sifive/fu540/Makefile
new file mode 100644
index 00..6e1862c475
--- /dev/null
+++ b/board/sifive/fu540/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2019 Western Digital Corporation or its affiliates.
+
+obj-y += fu540.o
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
new file mode 100644
index 00..5adc4a3d4a
--- /dev/null
+++ b/board/sifive/fu540/fu540.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel
+ */
+
+#include
+#include
+
+int board_init(void)
+{
+ /* For now nothing to do here. */
+
+ return 0;
+}
diff --git a/configs/sifive_fu540_defconfig b/configs/sifive_fu540_defconfig
new file mode 100644
index 00..2f8cca9de0
--- /dev/null
+++ b/configs/sifive_fu540_defconfig
@@ -0,0 +1,11 @@
+CONFIG_RISCV=y
+CONFIG_TARGET_SIFIVE_FU540=y
+CONFIG_RISCV_SMODE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_CMD_MII=y
+CONFIG_OF_PRIOR_STAGE=y
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
new file mode 100644
index 00..7007b5f6af
--- /dev/null
+++ b/include/configs/sifive-fu540.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ * Anup Patel
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include
+
+#define CONFIG_SYS_SDRAM_BASE 0x8000
+#define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BAS
[U-Boot] [PATCH v7 11/15] drivers: serial_sifive: Skip baudrate config if no input clock
From: Atish Patra
It is possible that input clock is not available because clk
device was not available and 'clock-frequency' DT property is
also not available.
In this case, instead of failing we should just skip baudrate
config by returning zero.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
---
drivers/serial/serial_sifive.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index ea4d35d48c..537bc7a975 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -99,27 +99,27 @@ static int _sifive_serial_getc(struct uart_sifive *regs)
static int sifive_serial_setbrg(struct udevice *dev, int baudrate)
{
- int err;
+ int ret;
struct clk clk;
struct sifive_uart_platdata *platdata = dev_get_platdata(dev);
+ u32 clock = 0;
- err = clk_get_by_index(dev, 0, &clk);
- if (!err) {
- err = clk_get_rate(&clk);
- if (!IS_ERR_VALUE(err))
- platdata->clock = err;
- } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) {
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (IS_ERR_VALUE(ret)) {
debug("SiFive UART failed to get clock\n");
- return err;
- }
-
- if (!platdata->clock)
- platdata->clock = dev_read_u32_default(dev, "clock-frequency",
0);
- if (!platdata->clock) {
- debug("SiFive UART clock not defined\n");
- return -EINVAL;
+ ret = dev_read_u32(dev, "clock-frequency", &clock);
+ if (IS_ERR_VALUE(ret)) {
+ debug("SiFive UART clock not defined\n");
+ return 0;
+ }
+ } else {
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ debug("SiFive UART clock get rate failed\n");
+ return 0;
+ }
}
-
+ platdata->clock = clock;
_sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate);
return 0;
--
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[U-Boot] [PATCH v7 09/15] clk: Add fixed-factor clock driver
This patch adds fixed-factor clock driver which derives clock
rate by dividing (div) and multiplying (mult) fixed factors
to a parent clock.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
---
arch/sandbox/dts/test.dts | 8
drivers/clk/Makefile | 4 +-
drivers/clk/clk_fixed_factor.c | 72 ++
test/dm/clk.c | 5 ++-
4 files changed, 87 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/clk_fixed_factor.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index 1d011ded7c..cb8d686e46 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -203,6 +203,14 @@
#clock-cells = <0>;
clock-frequency = <1234>;
};
+
+ clk_fixed_factor: clk-fixed-factor {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clock-div = <3>;
+ clock-mult = <2>;
+ clocks = <&clk_fixed>;
+ };
};
clk_sandbox: clk-sbox {
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index de3d60ed05..1d9d725cae 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -4,7 +4,9 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
-obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_rate.o
+obj-$(CONFIG_$(SPL_TPL_)CLK) += clk_fixed_factor.o
obj-y += imx/
obj-y += tegra/
diff --git a/drivers/clk/clk_fixed_factor.c b/drivers/clk/clk_fixed_factor.c
new file mode 100644
index 00..3487c11729
--- /dev/null
+++ b/drivers/clk/clk_fixed_factor.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Author: Anup Patel
+ */
+
+#include
+#include
+#include
+#include
+
+struct clk_fixed_factor {
+ struct clk parent;
+ unsigned int div;
+ unsigned int mult;
+};
+
+#define to_clk_fixed_factor(dev) \
+ ((struct clk_fixed_factor *)dev_get_platdata(dev))
+
+static ulong clk_fixed_factor_get_rate(struct clk *clk)
+{
+ uint64_t ret;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(clk->dev);
+
+ if (clk->id != 0)
+ return -EINVAL;
+
+ ret = clk_get_rate(&ff->parent);
+ if (IS_ERR_VALUE(ret))
+ return ret;
+
+ do_div(ret, ff->div);
+
+ return ret * ff->mult;
+}
+
+const struct clk_ops clk_fixed_factor_ops = {
+ .get_rate = clk_fixed_factor_get_rate,
+};
+
+static int clk_fixed_factor_ofdata_to_platdata(struct udevice *dev)
+{
+ int err;
+ struct clk_fixed_factor *ff = to_clk_fixed_factor(dev);
+
+ err = clk_get_by_index(dev, 0, &ff->parent);
+ if (err)
+ return err;
+
+ ff->div = dev_read_u32_default(dev, "clock-div", 1);
+ ff->mult = dev_read_u32_default(dev, "clock-mult", 1);
+
+ return 0;
+}
+
+static const struct udevice_id clk_fixed_factor_match[] = {
+ {
+ .compatible = "fixed-factor-clock",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(clk_fixed_factor) = {
+ .name = "fixed_factor_clock",
+ .id = UCLASS_CLK,
+ .of_match = clk_fixed_factor_match,
+ .ofdata_to_platdata = clk_fixed_factor_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct clk_fixed_factor),
+ .ops = &clk_fixed_factor_ops,
+};
diff --git a/test/dm/clk.c b/test/dm/clk.c
index 898c034e27..112d5cbbc9 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -12,12 +12,15 @@
static int dm_test_clk(struct unit_test_state *uts)
{
- struct udevice *dev_fixed, *dev_clk, *dev_test;
+ struct udevice *dev_fixed, *dev_fixed_factor, *dev_clk, *dev_test;
ulong rate;
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed",
&dev_fixed));
+ ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-fixed-factor",
+ &dev_fixed_factor));
+
ut_assertok(uclass_get_device_by_name(UCLASS_CLK, "clk-sbox",
&dev_clk));
ut_asserteq(0, sandbox_clk_query_enable(dev_clk, SANDBOX_CLK_ID_SPI));
--
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[U-Boot] [PATCH v7 08/15] clk: Add SiFive FU540 PRCI clock driver
Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf --- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/sifive/Kconfig| 19 + drivers/clk/sifive/Makefile | 5 + .../clk/sifive/analogbits-wrpll-cln28hpc.h| 101 +++ drivers/clk/sifive/fu540-prci.c | 604 ++ drivers/clk/sifive/wrpll-cln28hpc.c | 390 +++ include/dt-bindings/clk/sifive-fu540-prci.h | 29 + 8 files changed, 1150 insertions(+) create mode 100644 drivers/clk/sifive/Kconfig create mode 100644 drivers/clk/sifive/Makefile create mode 100644 drivers/clk/sifive/analogbits-wrpll-cln28hpc.h create mode 100644 drivers/clk/sifive/fu540-prci.c create mode 100644 drivers/clk/sifive/wrpll-cln28hpc.c create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 51c931b906..ff60fc5c45 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -105,6 +105,7 @@ source "drivers/clk/mvebu/Kconfig" source "drivers/clk/owl/Kconfig" source "drivers/clk/renesas/Kconfig" source "drivers/clk/sunxi/Kconfig" +source "drivers/clk/sifive/Kconfig" source "drivers/clk/tegra/Kconfig" source "drivers/clk/uniphier/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 6a4ff9143b..de3d60ed05 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ +obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o diff --git a/drivers/clk/sifive/Kconfig b/drivers/clk/sifive/Kconfig new file mode 100644 index 00..81fc9f8fda --- /dev/null +++ b/drivers/clk/sifive/Kconfig @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0 + +config CLK_ANALOGBITS_WRPLL_CLN28HPC + bool + +config CLK_SIFIVE + bool "SiFive SoC driver support" + depends on CLK + help + SoC drivers for SiFive Linux-capable SoCs. + +config CLK_SIFIVE_FU540_PRCI + bool "PRCI driver for SiFive FU540 SoCs" + depends on CLK_SIFIVE + select CLK_ANALOGBITS_WRPLL_CLN28HPC + help + Supports the Power Reset Clock interface (PRCI) IP block found in + FU540 SoCs. If this kernel is meant to run on a SiFive FU540 SoC, + enable this driver. diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile new file mode 100644 index 00..1155e07e37 --- /dev/null +++ b/drivers/clk/sifive/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-$(CONFIG_CLK_ANALOGBITS_WRPLL_CLN28HPC)+= wrpll-cln28hpc.o + +obj-$(CONFIG_CLK_SIFIVE_FU540_PRCI)+= fu540-prci.o diff --git a/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h new file mode 100644 index 00..4432e24749 --- /dev/null +++ b/drivers/clk/sifive/analogbits-wrpll-cln28hpc.h @@ -0,0 +1,101 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Copyright (C) 2018 SiFive, Inc. + * Wesley Terpstra + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H +#define __LINUX_CLK_ANALOGBITS_WRPLL_CLN28HPC_H + +#include + +/* DIVQ_VALUES: number of valid DIVQ values */ +#define DIVQ_VALUES6 + +/* + * Bit definitions for struct analogbits_wrpll_cfg.flags + * + * WRPLL_FLAGS_BYPASS_FLAG: if set, the PLL is either in bypass, or should be + * programmed to enter bypass + * WRPLL_FLAGS_RESET_FLAG: if set, the PLL is in reset + * WRPLL_FLAGS_INT_FEEDBACK_FLAG: if set, the PLL is configured for internal + * feedback mode + * WRPLL_FLAGS_EXT_FEEDBACK_FLAG: if set, the PLL is configured for external + * feedback mode (not yet supported by this driver) + * + * The flags WRPLL_FLAG
[U-Boot] [PATCH v7 12/15] cpu: Bind timer driver for boot hart
From: Atish Patra
Currently, timer driver is bound only for hart0.
There is no mandatory requirement that hart0 should always
come up. In fact, HiFive Unleashed SoC hart0 doesn't boot
in S-mode because it only has M-mode.
The timer driver should be bound for boot hart.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Alexander Graf
Reviewed-by: Lukas Auer
Reviewed-by: Bin Meng
---
drivers/cpu/riscv_cpu.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
index 5e15df590e..f77c126499 100644
--- a/drivers/cpu/riscv_cpu.c
+++ b/drivers/cpu/riscv_cpu.c
@@ -10,6 +10,8 @@
#include
#include
+DECLARE_GLOBAL_DATA_PTR;
+
static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
{
const char *isa;
@@ -62,7 +64,6 @@ static int riscv_cpu_bind(struct udevice *dev)
/* save the hart id */
plat->cpu_id = dev_read_addr(dev);
-
/* first examine the property in current cpu node */
ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
/* if not found, then look at the parent /cpus node */
@@ -71,7 +72,7 @@ static int riscv_cpu_bind(struct udevice *dev)
&plat->timebase_freq);
/*
-* Bind riscv-timer driver on hart 0
+* Bind riscv-timer driver on boot hart.
*
* We only instantiate one timer device which is enough for U-Boot.
* Pass the "timebase-frequency" value as the driver data for the
@@ -80,7 +81,7 @@ static int riscv_cpu_bind(struct udevice *dev)
* Return value is not checked since it's possible that the timer
* driver is not included.
*/
- if (!plat->cpu_id && plat->timebase_freq) {
+ if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
drv = lists_driver_lookup_name("riscv_timer");
if (!drv) {
debug("Cannot find the timer driver, not included?\n");
--
2.17.1
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[U-Boot] [PATCH v7 14/15] doc: Add a readme guide for SiFive FU540
From: Atish Patra
The readme guide describes the procedure to build, flash and boot Linux
using U-Boot on HiFive Unleashed. It also explains the current state of
U-boot support and future action items.
Signed-off-by: Atish Patra
Signed-off-by: Anup Patel
Reviewed-by: Lukas Auer
---
doc/README.sifive-fu540 | 303
1 file changed, 303 insertions(+)
create mode 100644 doc/README.sifive-fu540
diff --git a/doc/README.sifive-fu540 b/doc/README.sifive-fu540
new file mode 100644
index 00..fd9f2a8e46
--- /dev/null
+++ b/doc/README.sifive-fu540
@@ -0,0 +1,303 @@
+FU540-C000 RISC-V SoC
+=
+The FU540-C000 is the world’s first 4+1 64-bit RISC‑V SoC from SiFive.
+
+The HiFive Unleashed development platform is based on FU540-C000 and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+
+TODO:
+1. SPI driver is still missing. So MMC card can't be used in U-Boot as of now.
+2. U-Boot expects the serial console device entry to be present under /chosen
+ DT node. Example:
+ chosen {
+stdout-path = "/soc/serial@1001:115200";
+ };
+
+ Without a serial console U-Boot will panic.
+
+Building
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation enviornment variable.
+ a. export ARCH=riscv
+ b. export CROSS_COMPILE=
+3. make sifive_fu540_defconfig
+4. make
+
+Flashing
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage (M-mode) firmware/bootloader (e.g OpenSBI or BBL) is required to
+load the u-boot.bin into memory and provide runtime services. The u-boot.bin
+can be given as a payload to the prior stage (M-mode) firmware/bootloader.
+
+The description of steps required to build the firmware is beyond the scope of
+this document. Please refer OpenSBI or BBL documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+(Note: BBL git repo is at https://github.com/riscv/riscv-pk.git)
+
+Once the prior stage firmware/bootloader binary is generated, it should be
+copied to the first partition of the sdcard.
+
+sudo dd if= of=/dev/disk2s1 bs=1024
+
+Booting
+===
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unleashed board
+===
+U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
+
+CPU: rv64imafdc
+Model: sifive,hifive-unleashed-a00
+DRAM: 8 GiB
+In:serial@1001
+Out: serial@1001
+Err: serial@1001
+Net:
+Warning: ethernet@1009 (eth0) using random MAC address - b6:75:4d:48:50:94
+eth0: ethernet@1009
+Hit any key to stop autoboot: 0
+=> version
+U-Boot 2019.01-00019-gc7953536-dirty (Jan 22 2019 - 11:05:40 -0800)
+
+riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-3-ga0787e9) 8.2.0
+GNU ld (GNU Binutils) 2.31.1
+=>
+===
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+==
+=> setenv ethaddr 70:B3:D5:92:F0:C2
+=> setenv ipaddr 10.196.157.189
+=> setenv serverip 10.11.143.218
+=> setenv gatewayip 10.196.156.1
+=> setenv netmask 255.255.252.0
+=> bdinfo
+boot_params = 0x
+DRAM bank = 0x
+-> start= 0x8000
+-> size = 0x0002
+relocaddr = 0xfff9
+reloc off = 0x7fd9
+ethaddr = 70:B3:D5:92:F0:C2
+IP addr = 10.196.157.189
+baudrate= 115200 bps
+=> tftpboot uImage
+ethernet@1009: PHY present at 0
+ethernet@1009: Starting autonegotiation...
+ethernet@1009: Autonegotiation complete
+ethernet@1009: link up, 1000Mbps full-duplex (lpa: 0x3800)
+Using ethernet@1009 device
+TFTP from server 10.11.143.218; our IP address is 10.196.157.189; sending
through gateway 10.196.156.1
+Filename 'uImage'.
+Load address: 0x8020
+Loading: #
+ #
+ #
+ #
+ #
+ #
+ #
+ #
+ #
+ #
+
[U-Boot] [PATCH v7 15/15] riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
This patch enables CONFIG_SYS_BOOT_RAMDISK_HIGH for RISC-V because bootm will update initrd location in DTB only if CONFIG_SYS_BOOT_RAMDISK_HIGH is enabled. If we don't enable this option then bootm assumes DTB already has initrd details which is not the case most of the time. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Lukas Auer --- arch/riscv/include/asm/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/include/asm/config.h b/arch/riscv/include/asm/config.h index 81bc975d2e..156cb94dc0 100644 --- a/arch/riscv/include/asm/config.h +++ b/arch/riscv/include/asm/config.h @@ -8,5 +8,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif -- 2.17.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] Kconfig: Migrate CONFIG_BUILD_TARGET
Hi Chris, On 11.02.19 02:11, Chris Packham wrote: Hi Jagan, I've just tried this out on x530 and db-88f6820-amc (both ARCH_MVEBU). On Fri, Jan 18, 2019 at 8:23 PM Jagan Teki wrote: Migrate CONFIG_BUILD_TARGET into Kconfig. Signed-off-by: Jagan Teki --- diff --git a/Kconfig b/Kconfig index aff7b2e00a..15b79259a8 100644 --- a/Kconfig +++ b/Kconfig @@ -224,6 +224,19 @@ config BUILD_ROM which are not shipped in the U-Boot source tree. Please, see doc/README.x86 for details. +config BUILD_TARGET + string "Build target special images" + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD It looks like this doesn't work as expected. Perhaps because SPL_BUILD is a bit special. Should this hang of CONFIG_SPL or CONFIG_SUPPORT_SPL instead? Baruch already spotted this problem and did send a patch to fix this issue: http://patchwork.ozlabs.org/patch/1037973/ Seems to be identical to yours I'll pick it up quickly to fix this build problem. Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 0/7] Align U-Boot I2C DM bus ID handling with Linux
Hello Michal,
Am 08.02.2019 um 12:24 schrieb Michal Simek:
On 08. 02. 19 12:14, Michal Simek wrote:
On 08. 02. 19 10:57, Heiko Schocher wrote:
Hello Michael,
Am 31.01.2019 um 16:30 schrieb Michal Simek:
U-Boot with I2C_DM enabled is not capable to list i2c busses connected
to i2c mux. For getting this work there is a need to find out highest
alias ID and use this uniq number for new buses connected to I2C mux.
This series is making this happen.
There is only one missing piece which is that also i2c controllers which
are not listed in DT are not using this feature.
Removing setting up aliases from i2c mux code and unifying it in the
same code ensures that numbering schema is proper if no alias is
specified.
ZynqMP> i2c bus
Bus 0: i2c@ff02
20: gpio@20, offset len 1, flags 0
21: gpio@21, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 1: i2c@ff02->i2c-mux@75->i2c@0
Bus 2: i2c@ff02->i2c-mux@75->i2c@1
Bus 3: i2c@ff02->i2c-mux@75->i2c@2
Bus 4: i2c@ff03 (active 4)
74: i2c-mux@74, offset len 1, flags 0
75: i2c-mux@75, offset len 1, flags 0
Bus 5: i2c@ff03->i2c-mux@74->i2c@0 (active 5)
54: eeprom@54, offset len 1, flags 0
Bus 6: i2c@ff03->i2c-mux@74->i2c@1
Bus 7: i2c@ff03->i2c-mux@74->i2c@2
Bus 8: i2c@ff03->i2c-mux@74->i2c@3
Bus 9: i2c@ff03->i2c-mux@74->i2c@4
Bus 10: i2c@ff03->i2c-mux@75->i2c@0
Bus 11: i2c@ff03->i2c-mux@75->i2c@1
Bus 12: i2c@ff03->i2c-mux@75->i2c@2
Bus 13: i2c@ff03->i2c-mux@75->i2c@3
Bus 14: i2c@ff03->i2c-mux@75->i2c@4
Bus 15: i2c@ff03->i2c-mux@75->i2c@5
Bus 16: i2c@ff03->i2c-mux@75->i2c@6
Bus 17: i2c@ff03->i2c-mux@75->i2c@7
Thanks,
Michal
Changes in v2:
- Update kernel-doc binding
- Return -1 in case of error. -1 means that the next free alias is 0.
- New patch
- New patch
- Use dev_read_alias_highest_id()
- Use uclass private data
- Use private uclass data
- Fix headers
- Change patch description to focus only on bus name
Michal Simek (7):
dm: core: Add of_alias_get_highest_id()
fdt: Introduce fdtdec_get_alias_highest_id()
dm: core: Introduce dev_read_alias_highest_id()
dm: core: Add tests for dev_read_alias_highest_id()
i2c: dm: Record maximum id of devices before probing devices
i2c: Fill req_seq in i2c_post_bind()
i2c: mux: Generate longer i2c mux name
drivers/core/of_access.c | 18 ++
drivers/core/read.c | 8 ++
drivers/i2c/i2c-uclass.c | 50
+++---
drivers/i2c/muxes/i2c-mux-uclass.c | 29 +++---
include/dm/of_access.h | 10
include/dm/read.h | 16
include/fdtdec.h | 13 ++
lib/fdtdec.c | 33 +
test/dm/test-fdt.c | 23 ++
9 files changed, 194 insertions(+), 6 deletions(-)
I just applied your patches and triggered a build on travis:
It shows error for omap boards:
https://travis-ci.org/hsdenx/u-boot-i2c/jobs/490393822
I try to find time to look into it, but may you have time too?
This should be the fix. (I tried that on omap35_logic_somlv_defconfig)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index 6f3fca2d2326..391fb1289983 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -655,8 +655,12 @@ int i2c_uclass_init(struct uclass *class)
if (!priv)
return -ENOMEM;
+#if CONFIG_IS_ENABLED(OF_CONTROL)
/* Get the last allocated alias. */
priv->max_id = dev_read_alias_highest_id("i2c");
+#else
+ priv->max_id = -1;
+#endif
debug("%s: highest alias id is %d\n", __func__, priv->max_id);
SPL has no OF_CONTROL and also no LIBFDT that's why it is trying to call
it.
:-) that sentence doesn't make sense. Correction:
...that's why it shouldn't be called.
;-)
Maybe it should be enough to have dependency on OF_LIBFDT but Kconfig is
saying that OF_LIBFDT is bool setup to y when OF_CONTROL is enabled.
And in Makefile fdtdec is enabled
obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
or just
obj-$(CONFIG_OF_LIBFDT) += fdtdec.o
Anyway it should be likely enough to have dependency just on OF_LIBFDT.
Ok, do you want to send a v3 of the patch:
dm: core: Add of_alias_get_highest_id()
or is it OK for you, if I add the above fix to this patch directly?
bye,
Heiko
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Re: [U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
On Tue, 2019-02-05 at 09:51 +0100, Marek Vasut wrote:
> On 2/1/19 5:50 PM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> > >
> > > On 2/1/19 4:59 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Thu, 2019-01-31 at 15:54 +0100, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee
> > > > > >
> > > > > > Add default fitImage file bundling FPGA bitstreams for
> > > > > > Arria10.
> > > > > >
> > > > > > Signed-off-by: Tien Fong Chee
> > > > > > ---
> > > > > > board/altera/arria10-socdk/fit_spl_fpga.its | 31
> > > > > > +
> > > > > > 1 file changed, 31 insertions(+)
> > > > > > create mode 100644 board/altera/arria10-
> > > > > > socdk/fit_spl_fpga.its
> > > > > >
> > > > > > diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its
> > > > > > b/board/altera/arria10-socdk/fit_spl_fpga.its
> > > > > > new file mode 100644
> > > > > > index 000..46b125c
> > > > > > --- /dev/null
> > > > > > +++ b/board/altera/arria10-socdk/fit_spl_fpga.its
> > > > > > @@ -0,0 +1,31 @@
> > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > + /*
> > > > > > + * Copyright (C) 2019 Intel Corporation
> > > > > > + *
> > > > > > + */
> > > > > > +
> > > > > > +/dts-v1/;
> > > > > > +
> > > > > > +/ {
> > > > > > + description = "FIT image with FPGA bistream";
> > > > > > + #address-cells = <1>;
> > > > > > +
> > > > > > + images {
> > > > > > + fpga-2 {
> > > > > Why is fpga-2 before fpga-1 ?
> > > > 1. The main purpose is for solving the performance issue as i
> > > > described
> > > > in cover letter. We can decide the absolute data position for
> > > > core
> > > > image, and ensure it is in allignment.
> > > Where does the alignment problem happen exactly ?
> > The allignment problem happen in get_contents function, line 373,
> > at
> > fs/fat/fat.c .
> But then you're trying to work around a memcpy performance pentalty
> in
> VFAT code by frobbing with file position within a fitImage ? This can
> not work, since the file alignment within fitImage is not guaranteed
Yes, setting the absolute data position for the large core rbf file in
fitImage.
so, when generating the fitImage through mkimage, you need to set the
absolute position as argument to -p. Absolute data position is always
fixed offset based on fitImage base.
>
> >
> > This happens only when reading offset from a file,
> > that's why absolute position is very important to set the right
> > offset
> > for the core image. The performance penalty can be significantly
> > incurred with large size core image.
> >
> > filesize -= actsize;
> > actsize -= pos;
> > memcpy(buffer, tmp_buffer + pos, actsize);
> > free(tmp_buffer);
> > *gotsize += actsize;
> > if (!filesize)
> > return 0;
> > buffer += actsize; <= buffer sometimes is altered to
> > unaligned
> >
> > This function is basically finding the cluster where the pos
> > resides
> > in, adjusting the pos, actsize and file size accordingly when the
> > base
> > being changed from beginning of the file to the beginning of the
> > cluster where the pos resides in.
> >
> > Then copying the actsize size of content from pos to the end of the
> > cluster to the buffer above, and updating buffer to the next write.
> > The
> > updated buffer can be unaligned especially the pos is not being set
> > properly, hence we need the absolute position to fix that.
> >
> > When the unaligned buffer is passed as argument to the get_cluster
> > function, you would see the print out of "FAT: Misaligned buffer
> > address" at line 264 in that function. A very slow disk_read would
> > be
> > implemented to transfer the sector by sector content to the
> > unaligned
> > buffer.
> Can this be fixed then ?
I have tried few ideas, no one of them work.
Could you help to take a look?
>
> >
> > >
> > >
> > > Anyway, you cannot rely on this, the alignment within the
> > > fitImage
> > > may
> > > be changed just by using different strings in the ITS file.
> > No change for absolute position, it is always same offset based on
> > the
> > beginning of a FIT.
> Try adding a few properties here and there and/or changing the length
> of
> some of the strings, you'll see the file offset changes.
Absolute data position is always fixed offset from base of fitImage
regardless how many properties are added or changing. But, there is
potential the overlapping would be happended if data position is too
close with fit.
>
> >
> > >
> > >
> > > >
> > > >
> > > > 2. Users know where is the data position for core, so easy for
> > > > them
> > > > to
> > > > program themself with series commands on U-Boot console.
> > > You should use imxtract to pull out the file from fitImage and
>
[U-Boot] cl-som-am57x_defconfig will be dropped
Hi Uri, I see following warnings when building configs/cl-som-am57x_defconfig[1] which means board has not be moved to U-Boot Driver Model and Device Tree. Do you have plans to move configs/cl-som-am57x_defconfig to DM and enable CONFIG_DM and other DM framework? This is coming in the way of dropping all non DM code from drivers and this config will be dropped in 2019.04. [1]: = WARNING == This board does not use CONFIG_DM_MMC. Please update the board to use CONFIG_DM_MMC before the v2019.04 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SCSI. Please update the storage controller to use CONFIG_DM_SCSI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. -- Regards Vignesh ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/2] Kconfig: Migrate CONFIG_BUILD_TARGET
On Mon, Feb 11, 2019 at 7:06 PM Stefan Roese wrote: > > Hi Chris, > > On 11.02.19 02:11, Chris Packham wrote: > > Hi Jagan, > > > > I've just tried this out on x530 and db-88f6820-amc (both ARCH_MVEBU). > > > > On Fri, Jan 18, 2019 at 8:23 PM Jagan Teki > > wrote: > >> > >> Migrate CONFIG_BUILD_TARGET into Kconfig. > >> > >> Signed-off-by: Jagan Teki > >> --- > > > > > >> diff --git a/Kconfig b/Kconfig > >> index aff7b2e00a..15b79259a8 100644 > >> --- a/Kconfig > >> +++ b/Kconfig > >> @@ -224,6 +224,19 @@ config BUILD_ROM > >>which are not shipped in the U-Boot source tree. > >>Please, see doc/README.x86 for details. > >> > >> +config BUILD_TARGET > >> + string "Build target special images" > >> + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA > >> + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD > > > > It looks like this doesn't work as expected. Perhaps because SPL_BUILD > > is a bit special. Should this hang of CONFIG_SPL or CONFIG_SUPPORT_SPL > > instead? > > Baruch already spotted this problem and did send a patch to > fix this issue: > > http://patchwork.ozlabs.org/patch/1037973/ > > Seems to be identical to yours I'll pick it up quickly to fix > this build problem. OK thanks. I didn't search before sending. I've marked my patch as superseded in patchwork. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4 v3] pci: pci_mvebu: Add DM_PCI support and move CONFIG_PCI_MVEBU to defconfig
Hi Bin,
On 11.02.19 04:25, Bin Meng wrote:
Hi Stefan,
On Thu, Jan 31, 2019 at 10:41 PM Bin Meng wrote:
Hi Stefan,
On Fri, Jan 25, 2019 at 6:53 PM Stefan Roese wrote:
This patch adds DM_PCI support to the MVEBU PCIe driver. This is
necessary, since all PCI drivers have to be moved to DM (driver model)
until the v2019.07 release.
To not break git bisect'ablility, this patch also moves CONFIG_PCI_MVEBU
from config headers to the defconfig files.
Signed-off-by: Stefan Roese
Cc: Dirk Eibach
Cc: Mario Six
Cc: Chris Packham
Cc: Phil Sutter
Cc: Marek Behún
Cc: VlaoMao
---
v3:
- Add x530 defconfig / config/foo.h changes
- Remove misleading function comment
- Use PCI_DEV instead of PCI_SLOT
- Introduce mvebu_pcie_ofdata_to_platdata() to remove most functions
from the loop in mvebu_pcie_bind(). This also enables to usage of
a udevice pointer for the newly introduced function pci_get_devfn()
v2:
- Completely configure the controller based on DT properties. Now
port and lane are read from the DT nodes and also the tgt and
attr values are generated using the DT similar to how this is
done in the Linux driver version. All A38x / XP specific defines
can now be removed from this driver because of this.
- Please note that now the board specific dts file needs to enable
the used PCIe ports, as this is also done in Linux.
configs/clearfog_defconfig | 1 +
configs/controlcenterdc_defconfig | 3 +
configs/db-88f6820-amc_defconfig| 1 +
configs/db-88f6820-gp_defconfig | 1 +
configs/db-mv784mp-gp_defconfig | 1 +
configs/ds414_defconfig | 1 +
configs/theadorable_debug_defconfig | 2 +
configs/turris_omnia_defconfig | 3 +-
configs/x530_defconfig | 3 +-
drivers/pci/Kconfig | 9 +
drivers/pci/pci_mvebu.c | 470
include/configs/clearfog.h | 1 -
include/configs/controlcenterdc.h | 3 -
include/configs/db-88f6820-amc.h| 1 -
include/configs/db-88f6820-gp.h | 1 -
include/configs/db-mv784mp-gp.h | 1 -
include/configs/ds414.h | 1 -
include/configs/theadorable.h | 7 -
include/configs/turris_omnia.h | 1 -
include/configs/x530.h | 1 -
scripts/config_whitelist.txt| 1 -
21 files changed, 296 insertions(+), 217 deletions(-)
[snip]
+static int mvebu_get_tgt_attr(ofnode node, int devfn,
+ unsigned long type,
+ unsigned int *tgt,
+ unsigned int *attr)
+{
+ const int na = 3, ns = 2;
+ const __be32 *range;
+ int rlen, nranges, rangesz, pna, i;
+
+ *tgt = -1;
+ *attr = -1;
+
+ range = ofnode_get_property(node, "ranges", &rlen);
+ if (!range)
+ return -EINVAL;
+
+ pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
Why? U-Boot has of_n_addr_cells() API.
Is this comment addressed?
I did send an answer ~ one week ago:
https://www.mail-archive.com/u-boot@lists.denx.de/msg314633.html
I'll send a patch to add the comment shortly.
Thanks,
Stefan
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[U-Boot] [PATCH] pci: pci_mvebu: Add comment about missing of_n_addr_cells() call
This patch adds a comment to explain the use of the hardcoded value for the number of address cells in mvebu_get_tgt_attr(). This should help to rework this function, once CONFIG_OF_LIVE is enabled for MVEBU in general. Signed-off-by: Stefan Roese Cc: Bin Meng --- drivers/pci/pci_mvebu.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c index 6026fa67f9..e21dc10c2f 100644 --- a/drivers/pci/pci_mvebu.c +++ b/drivers/pci/pci_mvebu.c @@ -369,6 +369,12 @@ static int mvebu_get_tgt_attr(ofnode node, int devfn, if (!range) return -EINVAL; + /* +* Linux uses of_n_addr_cells() to get the number of address cells +* here. Currently this function is only available in U-Boot when +* CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in +* general, lets't hardcode the "pna" value in the U-Boot code. +*/ pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */ rangesz = pna + na + ns; nranges = rlen / sizeof(__be32) / rangesz; -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4] misc: fs_loader: Add support for initializing block device
On Fri, 2019-02-01 at 23:06 -0700, Simon Glass wrote: On Thu, 31 Jan 2019 at 04:34, mailto:tien.fong.c...@intel.com>> wrote: > > From: Tien Fong Chee > mailto:tien.fong.c...@intel.com>> > > Firmware loader would encounter problem if the block device is accessed > before initializing it. This patch would adding the support of probing > block device and initializing block before the block device is accessed by > firmware loader. > > Signed-off-by: Tien Fong Chee > mailto:tien.fong.c...@intel.com>> > > --- > > changes in v4 > - Removed header mmc.h > - Dropped extra blank line > > changes in v3: > - Initializing block device through probing the blk device > > changes in v2: > - Initializing MMC through probing the blk device > --- > drivers/misc/fs_loader.c | 23 +++ > 1 file changed, 23 insertions(+) Reviewed-by: Simon Glass mailto:s...@chromium.org>> (I'm not sure you need to check for DM being enabled, but OK) Thanks. No strong opinion on this :) . ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mmc: Do not poll using CMD13 when changing timing
Hi Marek,
> When using CMD6 to switch eMMC card timing from HS200/HS400 to
> HS/legacy, do not poll for the completion status using CMD13, but
> rather wait 50mS.
Nit: mS -> ms
>
> Once the card receives the CMD6 and starts executing it, the bus is in
> undefined state until both the card finishes executing the command and
> until the controller switches the bus to matching timing
> configuration. During this time, it is not possible to transport any
> commands or data across the bus, which includes the CMD13.
Just out of curiosity - is this 50ms time written in some spec? Or is
it only specific to Renesas HS200/HS400 ?
>
> Signed-off-by: Marek Vasut
> Cc: Jaehoon Chung
> ---
> NOTE: Linux does the same thing.
> ---
> drivers/mmc/mmc.c | 28
> 1 file changed, 20 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
> index c7730c9233..ababacf65a 100644
> --- a/drivers/mmc/mmc.c
> +++ b/drivers/mmc/mmc.c
> @@ -720,7 +720,8 @@ static int mmc_send_ext_csd(struct mmc *mmc, u8
> *ext_csd) return err;
> }
>
> -int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
> +static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
> + bool send_status)
> {
> struct mmc_cmd cmd;
> int timeout = 1000;
> @@ -736,19 +737,29 @@ int mmc_switch(struct mmc *mmc, u8 set, u8
> index, u8 value) while (retries > 0) {
> ret = mmc_send_cmd(mmc, &cmd, NULL);
>
> - /* Waiting for the ready status */
> - if (!ret) {
> - ret = mmc_send_status(mmc, timeout);
> - return ret;
> + if (ret) {
> + retries--;
> + continue;
> + }
> +
> + if (!send_status) {
> + mdelay(50);
> + return 0;
> }
>
> - retries--;
> + /* Waiting for the ready status */
> + return mmc_send_status(mmc, timeout);
> }
>
> return ret;
>
> }
>
> +int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
> +{
> + return __mmc_switch(mmc, set, index, value, true);
> +}
> +
> #if !CONFIG_IS_ENABLED(MMC_TINY)
> static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
> bool hsdowngrade)
> @@ -780,8 +791,9 @@ static int mmc_set_card_speed(struct mmc *mmc,
> enum bus_mode mode, default:
> return -EINVAL;
> }
> - err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
> EXT_CSD_HS_TIMING,
> - speed_bits);
> +
> + err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
> EXT_CSD_HS_TIMING,
> +speed_bits, !hsdowngrade);
> if (err)
> return err;
>
Best regards,
Lukasz Majewski
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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[U-Boot] [PATCH v3 1/2] fs: fat: dynamically allocate memory for temporary buffer
From: Tien Fong Chee
Drop the statically allocated get_contents_vfatname_block and
dynamically allocate a buffer only if required. This saves
64KiB of memory.
Signed-off-by: Stefan Agner
Signed-off-by: Tien Fong Chee
---
changes for v3
- Removed the cast on actsize
---
fs/fat/fat.c | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index ecfa255..ea11250 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -306,9 +306,6 @@ get_cluster(fsdata *mydata, __u32 clustnum, __u8 *buffer,
unsigned long size)
* into 'buffer'.
* Update the number of bytes read in *gotsize or return -1 on fatal errors.
*/
-__u8 get_contents_vfatname_block[MAX_CLUSTSIZE]
- __aligned(ARCH_DMA_MINALIGN);
-
static int get_contents(fsdata *mydata, dir_entry *dentptr, loff_t pos,
__u8 *buffer, loff_t maxsize, loff_t *gotsize)
{
@@ -351,15 +348,24 @@ static int get_contents(fsdata *mydata, dir_entry
*dentptr, loff_t pos,
/* align to beginning of next cluster if any */
if (pos) {
+ __u8 *tmp_buffer;
+
actsize = min(filesize, (loff_t)bytesperclust);
- if (get_cluster(mydata, curclust, get_contents_vfatname_block,
- (int)actsize) != 0) {
+ tmp_buffer = malloc_cache_aligned(actsize);
+ if (!tmp_buffer) {
+ debug("Error: allocating buffer\n");
+ return -ENOMEM;
+ }
+
+ if (get_cluster(mydata, curclust, tmp_buffer, actsize) != 0) {
printf("Error reading cluster\n");
+ free(tmp_buffer);
return -1;
}
filesize -= actsize;
actsize -= pos;
- memcpy(buffer, get_contents_vfatname_block + pos, actsize);
+ memcpy(buffer, tmp_buffer + pos, actsize);
+ free(tmp_buffer);
*gotsize += actsize;
if (!filesize)
return 0;
--
2.2.0
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[U-Boot] [PATCH v3 2/2] fs: fat: Reduce default max clustersize 64KiB from malloc pool
From: Tien Fong Chee
Release cluster block immediately when no longer use would help to reduce
64KiB memory allocated to the memory pool.
Signed-off-by: Tien Fong Chee
---
changes for v3
- Dropped the if conditional because free(NULL) is valid.
---
fs/fat/fat.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/fs/fat/fat.c b/fs/fat/fat.c
index ea11250..26ae101 100644
--- a/fs/fat/fat.c
+++ b/fs/fat/fat.c
@@ -1151,7 +1151,15 @@ int file_fat_read_at(const char *filename, loff_t pos,
void *buffer,
goto out_free_both;
debug("reading %s at pos %llu\n", filename, pos);
- ret = get_contents(&fsdata, itr->dent, pos, buffer, maxsize, actread);
+
+ /* For saving default max clustersize memory allocated to malloc pool */
+ dir_entry *dentptr = itr->dent;
+
+ free(itr);
+
+ itr = NULL;
+
+ ret = get_contents(&fsdata, dentptr, pos, buffer, maxsize, actread);
out_free_both:
free(fsdata.fatbuf);
--
2.2.0
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Re: [U-Boot] [PATCH v2 0/7] Align U-Boot I2C DM bus ID handling with Linux
On 11. 02. 19 7:20, Heiko Schocher wrote:
> Hello Michal,
>
> Am 08.02.2019 um 12:24 schrieb Michal Simek:
>> On 08. 02. 19 12:14, Michal Simek wrote:
>>> On 08. 02. 19 10:57, Heiko Schocher wrote:
Hello Michael,
Am 31.01.2019 um 16:30 schrieb Michal Simek:
> U-Boot with I2C_DM enabled is not capable to list i2c busses connected
> to i2c mux. For getting this work there is a need to find out highest
> alias ID and use this uniq number for new buses connected to I2C mux.
> This series is making this happen.
>
> There is only one missing piece which is that also i2c controllers
> which
> are not listed in DT are not using this feature.
>
> Removing setting up aliases from i2c mux code and unifying it in the
> same code ensures that numbering schema is proper if no alias is
> specified.
>
> ZynqMP> i2c bus
> Bus 0: i2c@ff02
> 20: gpio@20, offset len 1, flags 0
> 21: gpio@21, offset len 1, flags 0
> 75: i2c-mux@75, offset len 1, flags 0
> Bus 1: i2c@ff02->i2c-mux@75->i2c@0
> Bus 2: i2c@ff02->i2c-mux@75->i2c@1
> Bus 3: i2c@ff02->i2c-mux@75->i2c@2
> Bus 4: i2c@ff03 (active 4)
> 74: i2c-mux@74, offset len 1, flags 0
> 75: i2c-mux@75, offset len 1, flags 0
> Bus 5: i2c@ff03->i2c-mux@74->i2c@0 (active 5)
> 54: eeprom@54, offset len 1, flags 0
> Bus 6: i2c@ff03->i2c-mux@74->i2c@1
> Bus 7: i2c@ff03->i2c-mux@74->i2c@2
> Bus 8: i2c@ff03->i2c-mux@74->i2c@3
> Bus 9: i2c@ff03->i2c-mux@74->i2c@4
> Bus 10: i2c@ff03->i2c-mux@75->i2c@0
> Bus 11: i2c@ff03->i2c-mux@75->i2c@1
> Bus 12: i2c@ff03->i2c-mux@75->i2c@2
> Bus 13: i2c@ff03->i2c-mux@75->i2c@3
> Bus 14: i2c@ff03->i2c-mux@75->i2c@4
> Bus 15: i2c@ff03->i2c-mux@75->i2c@5
> Bus 16: i2c@ff03->i2c-mux@75->i2c@6
> Bus 17: i2c@ff03->i2c-mux@75->i2c@7
>
> Thanks,
> Michal
>
> Changes in v2:
> - Update kernel-doc binding
> - Return -1 in case of error. -1 means that the next free alias is 0.
> - New patch
> - New patch
> - Use dev_read_alias_highest_id()
> - Use uclass private data
> - Use private uclass data
> - Fix headers
> - Change patch description to focus only on bus name
>
> Michal Simek (7):
> dm: core: Add of_alias_get_highest_id()
> fdt: Introduce fdtdec_get_alias_highest_id()
> dm: core: Introduce dev_read_alias_highest_id()
> dm: core: Add tests for dev_read_alias_highest_id()
> i2c: dm: Record maximum id of devices before probing devices
> i2c: Fill req_seq in i2c_post_bind()
> i2c: mux: Generate longer i2c mux name
>
> drivers/core/of_access.c | 18 ++
> drivers/core/read.c | 8 ++
> drivers/i2c/i2c-uclass.c | 50
> +++---
> drivers/i2c/muxes/i2c-mux-uclass.c | 29 +++---
> include/dm/of_access.h | 10
> include/dm/read.h | 16
> include/fdtdec.h | 13 ++
> lib/fdtdec.c | 33 +
> test/dm/test-fdt.c | 23 ++
> 9 files changed, 194 insertions(+), 6 deletions(-)
>
I just applied your patches and triggered a build on travis:
It shows error for omap boards:
https://travis-ci.org/hsdenx/u-boot-i2c/jobs/490393822
I try to find time to look into it, but may you have time too?
>>>
>>> This should be the fix. (I tried that on omap35_logic_somlv_defconfig)
>>>
>>> diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
>>> index 6f3fca2d2326..391fb1289983 100644
>>> --- a/drivers/i2c/i2c-uclass.c
>>> +++ b/drivers/i2c/i2c-uclass.c
>>> @@ -655,8 +655,12 @@ int i2c_uclass_init(struct uclass *class)
>>> if (!priv)
>>> return -ENOMEM;
>>>
>>> +#if CONFIG_IS_ENABLED(OF_CONTROL)
>>> /* Get the last allocated alias. */
>>> priv->max_id = dev_read_alias_highest_id("i2c");
>>> +#else
>>> + priv->max_id = -1;
>>> +#endif
>>>
>>> debug("%s: highest alias id is %d\n", __func__, priv->max_id);
>>>
>>>
>>> SPL has no OF_CONTROL and also no LIBFDT that's why it is trying to call
>>> it.
>>
>> :-) that sentence doesn't make sense. Correction:
>> ...that's why it shouldn't be called.
>
> ;-)
>
>> Maybe it should be enough to have dependency on OF_LIBFDT but Kconfig is
>> saying that OF_LIBFDT is bool setup to y when OF_CONTROL is enabled.
>> And in Makefile fdtdec is enabled
>>
>> obj-$(CONFIG_$(SPL_TPL_)OF_CONTROL) += fdtdec.o
>> or just
>> obj-$(CONFIG_OF_LIBFDT) += fdtdec.o
>>
>> Anyway it should be likely enough to ha
[U-Boot] [PATCH v2 00/13] net: Add Allwinner EMAC CLK, RESET support
This is v2 version for Allwinner EMAC CLK, RESET support, which was initially be a part of previous series[1]. Changes for v2: - rebase on master - add dm tests for new clk and reset functions. Any inputs? Jagan. [1] https://patchwork.ozlabs.org/patch/959351/ Jagan Teki (13): clk: sunxi: Implement A10 EMAC clocks net: sunxi_emac: Add CLK support net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle clk: Get the CLK by index without device clk: Use clk_get_by_index_tail() test/dm: clk: Add clk_get_by_index[_nodev] test reset: Get the RESET by index without device test/dm: reset: Add reset_get_by_index[_nodev] test clk: sunxi: Implement EMAC, GMAC clocks, resets net: sun8i_emac: Add CLK and RESET support clk: sunxi: h3: Implement EPHY CLK and RESET net: sun8i_emac: Add EPHY CLK and RESET support board: sunxi: gmac: Remove Ethernet clock and reset board/sunxi/gmac.c | 8 -- drivers/clk/clk-uclass.c | 84 +++- drivers/clk/sunxi/clk_a10.c | 1 + drivers/clk/sunxi/clk_a10s.c | 1 + drivers/clk/sunxi/clk_a31.c | 2 + drivers/clk/sunxi/clk_a64.c | 2 + drivers/clk/sunxi/clk_a83t.c | 2 + drivers/clk/sunxi/clk_h3.c | 6 ++ drivers/clk/sunxi/clk_h6.c | 4 + drivers/clk/sunxi/clk_r40.c | 3 + drivers/net/sun8i_emac.c | 182 +++ drivers/net/sunxi_emac.c | 28 -- drivers/reset/reset-uclass.c | 53 ++ image.map| 4 + include/clk.h| 15 +++ include/reset.h | 16 +++ test/dm/clk.c| 21 test/dm/reset.c | 22 + 18 files changed, 338 insertions(+), 116 deletions(-) create mode 100644 image.map -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 02/13] net: sunxi_emac: Add CLK support
Add CLk support for sunxi_emac to enable AHB_EMAC clock
via CLK framework.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/net/sunxi_emac.c | 28 ++--
image.map| 4
2 files changed, 26 insertions(+), 6 deletions(-)
create mode 100644 image.map
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8dbd3c50c1..9a5f7fd3c7 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -6,6 +6,7 @@
*/
#include
+#include
#include
#include
#include
@@ -157,6 +158,7 @@ struct sunxi_sramc_regs {
struct emac_eth_dev {
struct emac_regs *regs;
+ struct clk clk;
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
@@ -500,14 +502,12 @@ static int _sunxi_emac_eth_send(struct emac_eth_dev
*priv, void *packet,
return 0;
}
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
struct emac_regs *regs = priv->regs;
- int pin;
+ int pin, ret;
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
@@ -517,10 +517,16 @@ static void sunxi_emac_board_setup(struct emac_eth_dev
*priv)
sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
/* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+ ret = clk_enable(&priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable emac clock\n");
+ return ret;
+ }
/* Set MII clock */
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+
+ return 0;
}
static int sunxi_emac_eth_start(struct udevice *dev)
@@ -557,9 +563,19 @@ static int sunxi_emac_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->regs = (struct emac_regs *)pdata->iobase;
- sunxi_emac_board_setup(priv);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to get emac clock\n");
+ return ret;
+ }
+
+ ret = sunxi_emac_board_setup(priv);
+ if (ret)
+ return ret;
return sunxi_emac_init_phy(priv, dev);
}
diff --git a/image.map b/image.map
new file mode 100644
index 00..a0b4894f93
--- /dev/null
+++ b/image.map
@@ -0,0 +1,4 @@
+ImagePosOffset Size Name
+ 0007050a main-section
+ 6000 blob
+8000 8000 0006850a u-boot-img
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 01/13] clk: sunxi: Implement A10 EMAC clocks
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a10.c | 1 +
drivers/clk/sunxi/clk_a10s.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index b8b57e2b31..15ffe5ecb3 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -22,6 +22,7 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB_MMC3] = GATE(0x060, BIT(11)),
+ [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index c6fcede822..33d41d47b0 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -19,6 +19,7 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_MMC0] = GATE(0x060, BIT(8)),
[CLK_AHB_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_AHB_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 03/13] net: sun8i_emac: Retrieve GMAC clock via 'syscon' phandle
Unlike other Allwinner SoC's R40 GMAC clock control register
is locate in CCU, but rest located via syscon itself. Since
the phandle property for current code look for 'syscon' and
it will grab the respective ccu or syscon base address based
on DT property defined in respective SoC dtsi.
So, use the existing 'syscon' code even for R40 for retrieving
GMAC clock via CCU and update the register directly in
sun8i_emac_set_syscon instead of writing it separately using
ccm base.
Cc: Joe Hershberger
Cc: Lothar Felten
Signed-off-by: Jagan Teki
---
drivers/net/sun8i_emac.c | 55
1 file changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index c9798445c7..a7fb7ac405 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -285,10 +285,18 @@ static int sun8i_emac_set_syscon(struct sun8i_eth_pdata
*pdata,
int ret;
u32 reg;
- reg = readl(priv->sysctl_reg + 0x30);
+ if (priv->variant == R40_GMAC) {
+ /* Select RGMII for R40 */
+ reg = readl(priv->sysctl_reg + 0x164);
+ reg |= CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
+ CCM_GMAC_CTRL_GPIT_RGMII |
+ CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY);
- if (priv->variant == R40_GMAC)
+ writel(reg, priv->sysctl_reg + 0x164);
return 0;
+ }
+
+ reg = readl(priv->sysctl_reg + 0x30);
if (priv->variant == H3_EMAC) {
ret = sun8i_emac_set_syscon_ephy(priv, ®);
@@ -662,13 +670,6 @@ static void sun8i_emac_board_setup(struct emac_eth_dev
*priv)
/* De-assert EMAC */
setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
-
- /* Select RGMII for R40 */
- setbits_le32(&ccm->gmac_clk_cfg,
-CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
-CCM_GMAC_CTRL_GPIT_RGMII);
- setbits_le32(&ccm->gmac_clk_cfg,
-CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY));
} else {
/* Set clock gating for emac */
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
@@ -850,25 +851,23 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
udevice *dev)
return -EINVAL;
}
- if (priv->variant != R40_GMAC) {
- offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
- if (offset < 0) {
- debug("%s: cannot find syscon node\n", __func__);
- return -EINVAL;
- }
- reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
- if (!reg) {
- debug("%s: cannot find reg property in syscon node\n",
- __func__);
- return -EINVAL;
- }
- priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
-offset, reg);
- if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
- debug("%s: Cannot find syscon base address\n",
- __func__);
- return -EINVAL;
- }
+ offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
+ if (offset < 0) {
+ debug("%s: cannot find syscon node\n", __func__);
+ return -EINVAL;
+ }
+
+ reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
+ if (!reg) {
+ debug("%s: cannot find reg property in syscon node\n",
+ __func__);
+ return -EINVAL;
+ }
+ priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
+offset, reg);
+ if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
+ debug("%s: Cannot find syscon base address\n", __func__);
+ return -EINVAL;
}
pdata->phy_interface = -1;
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 09/13] clk: sunxi: Implement EMAC, GMAC clocks, resets
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_a31.c | 2 ++
drivers/clk/sunxi/clk_a64.c | 2 ++
drivers/clk/sunxi/clk_a83t.c | 2 ++
drivers/clk/sunxi/clk_h3.c | 2 ++
drivers/clk/sunxi/clk_h6.c | 4
drivers/clk/sunxi/clk_r40.c | 3 +++
6 files changed, 15 insertions(+)
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index fa6e3eeef0..4ec3c2ae89 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -17,6 +17,7 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
[CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
[CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
+ [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
[CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
[CLK_AHB1_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB1_SPI2] = GATE(0x060, BIT(22)),
@@ -57,6 +58,7 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_MMC1] = RESET(0x2c0, BIT(9)),
[RST_AHB1_MMC2] = RESET(0x2c0, BIT(10)),
[RST_AHB1_MMC3] = RESET(0x2c0, BIT(11)),
+ [RST_AHB1_EMAC] = RESET(0x2c0, BIT(17)),
[RST_AHB1_SPI0] = RESET(0x2c0, BIT(20)),
[RST_AHB1_SPI1] = RESET(0x2c0, BIT(21)),
[RST_AHB1_SPI2] = RESET(0x2c0, BIT(22)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 322d6cd557..f94e8aa754 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -16,6 +16,7 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
@@ -49,6 +50,7 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 36f7e14c45..2be87a31fd 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
@@ -47,6 +48,7 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 5f99ef7342..f5ae1e9555 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -16,6 +16,7 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
[CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
[CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
+ [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[CLK_BUS_OTG] = GATE(0x060, BIT(23)),
@@ -55,6 +56,7 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
[RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
[RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
+ [RST_BUS_EMAC] = RESET(0x2c0, BIT(17)),
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 71f0c78656..0bb00f449a 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -26,6
[U-Boot] [PATCH v2 08/13] test/dm: reset: Add reset_get_by_index[_nodev] test
Add sample dm reset test for reset_get_by_index and
reset_get_by_index_nodev functionality code.
Cc: Stephen Warren
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
test/dm/reset.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/test/dm/reset.c b/test/dm/reset.c
index c02866a2f0..47198e90ce 100644
--- a/test/dm/reset.c
+++ b/test/dm/reset.c
@@ -5,6 +5,7 @@
#include
#include
+#include
#include
#include
#include
@@ -15,6 +16,27 @@
/* This is the other reset phandle specifier handled by bulk */
#define OTHER_RESET_ID 2
+/* Base test of the reset uclass */
+static int dm_test_reset_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct reset_ctl reset_method1;
+ struct reset_ctl reset_method2;
+
+ /* Get the device using the reset device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "reset-ctl-test",
+ &dev));
+
+ /* Get the same reset port in 2 different ways and compare */
+ ut_assertok(reset_get_by_index(dev, 1, &reset_method1));
+ ut_assertok(reset_get_by_index_nodev(dev_ofnode(dev), 1,
&reset_method2));
+ ut_asserteq(reset_method1.id, reset_method2.id);
+
+ return 0;
+}
+
+DM_TEST(dm_test_reset_base, DM_TESTF_SCAN_FDT);
+
static int dm_test_reset(struct unit_test_state *uts)
{
struct udevice *dev_reset;
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 10/13] net: sun8i_emac: Add CLK and RESET support
Add CLK and RESET support for sun8i_emac driver to
enable TX clock and reset pins via CLK and RESET
framework.
Cc: Joe Hershberger
Cc: Lothar Felten
Signed-off-by: Jagan Teki
---
drivers/net/sun8i_emac.c | 57 +---
1 file changed, 42 insertions(+), 15 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index a7fb7ac405..98bd7a5823 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -14,12 +14,14 @@
#include
#include
#include
+#include
#include
#include
#include
#include
#include
#include
+#include
#include
#ifdef CONFIG_DM_GPIO
#include
@@ -135,6 +137,8 @@ struct emac_eth_dev {
phys_addr_t sysctl_reg;
struct phy_device *phydev;
struct mii_dev *bus;
+ struct clk tx_clk;
+ struct reset_ctl tx_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
@@ -647,9 +651,24 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
}
-static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
+static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+ int ret;
+
+ ret = clk_enable(&priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable TX clock\n");
+ return ret;
+ }
+
+ if (reset_valid(&priv->tx_rst)) {
+ ret = reset_deassert(&priv->tx_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert TX reset\n");
+ goto err_tx_clk;
+ }
+ }
if (priv->variant == H3_EMAC) {
/* Only H3/H5 have clock controls for internal EPHY */
@@ -664,19 +683,11 @@ static void sun8i_emac_board_setup(struct emac_eth_dev
*priv)
}
}
- if (priv->variant == R40_GMAC) {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC));
-
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC));
- } else {
- /* Set clock gating for emac */
- setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
+ return 0;
- /* De-assert EMAC */
- setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
- }
+err_tx_clk:
+ clk_disable(&priv->tx_clk);
+ return ret;
}
#if defined(CONFIG_DM_GPIO)
@@ -803,10 +814,14 @@ static int sun8i_emac_eth_probe(struct udevice *dev)
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->mac_reg = (void *)pdata->iobase;
- sun8i_emac_board_setup(priv);
+ ret = sun8i_emac_board_setup(priv);
+ if (ret)
+ return ret;
+
sun8i_emac_set_syscon(sun8i_pdata, priv);
sun8i_mdio_init(dev->name, dev);
@@ -835,8 +850,8 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice
*dev)
int offset = 0;
#ifdef CONFIG_DM_GPIO
int reset_flags = GPIOD_IS_OUT;
- int ret = 0;
#endif
+ int ret;
pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
@@ -851,6 +866,18 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
udevice *dev)
return -EINVAL;
}
+ ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
+ if (ret) {
+ dev_err(dev, "failed to get TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "failed to get TX reset\n");
+ return ret;
+ }
+
offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
if (offset < 0) {
debug("%s: cannot find syscon node\n", __func__);
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 06/13] test/dm: clk: Add clk_get_by_index[_nodev] test
Add sample dm clk test for clk_get_by_index and
clk_get_by_index_nodev functionality code.
Cc: Stephen Warren
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
test/dm/clk.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/test/dm/clk.c b/test/dm/clk.c
index 898c034e27..29ef6ef41b 100644
--- a/test/dm/clk.c
+++ b/test/dm/clk.c
@@ -4,12 +4,33 @@
*/
#include
+#include
#include
#include
#include
#include
#include
+/* Base test of the clk uclass */
+static int dm_test_clk_base(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+ struct clk clk_method1;
+ struct clk clk_method2;
+
+ /* Get the device using the clk device */
+ ut_assertok(uclass_get_device_by_name(UCLASS_MISC, "clk-test", &dev));
+
+ /* Get the same clk port in 2 different ways and compare */
+ ut_assertok(clk_get_by_index(dev, 1, &clk_method1));
+ ut_assertok(clk_get_by_index_nodev(dev_ofnode(dev), 1, &clk_method2));
+ ut_asserteq(clk_method1.id, clk_method2.id);
+
+ return 0;
+}
+
+DM_TEST(dm_test_clk_base, DM_TESTF_SCAN_FDT);
+
static int dm_test_clk(struct unit_test_state *uts)
{
struct udevice *dev_fixed, *dev_clk, *dev_test;
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 05/13] clk: Use clk_get_by_index_tail()
clk_get_by_index_tail() now handle common clk get by index
code so use it in relevant places.
Cc: Stephen Warren
Signed-off-by: Jagan Teki
Reviewed-by: Simon Glass
---
drivers/clk/clk-uclass.c | 77 +---
1 file changed, 25 insertions(+), 52 deletions(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index dc0b7809d2..aa6535c7fd 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -54,50 +54,6 @@ static int clk_of_xlate_default(struct clk *clk,
return 0;
}
-static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
- int index, struct clk *clk)
-{
- int ret;
- struct ofnode_phandle_args args;
- struct udevice *dev_clk;
- const struct clk_ops *ops;
-
- debug("%s(dev=%p, index=%d, clk=%p)\n", __func__, dev, index, clk);
-
- assert(clk);
- clk->dev = NULL;
-
- ret = dev_read_phandle_with_args(dev, prop_name, "#clock-cells", 0,
-index, &args);
- if (ret) {
- debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
- __func__, ret);
- return ret;
- }
-
- ret = uclass_get_device_by_ofnode(UCLASS_CLK, args.node, &dev_clk);
- if (ret) {
- debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
- __func__, ret);
- return ret;
- }
-
- clk->dev = dev_clk;
-
- ops = clk_dev_ops(dev_clk);
-
- if (ops->of_xlate)
- ret = ops->of_xlate(clk, &args);
- else
- ret = clk_of_xlate_default(clk, &args);
- if (ret) {
- debug("of_xlate() failed: %d\n", ret);
- return ret;
- }
-
- return clk_request(dev_clk, clk);
-}
-
static int clk_get_by_index_tail(int ret, ofnode node,
struct ofnode_phandle_args *args,
const char *list_name, int index,
@@ -197,10 +153,11 @@ bulk_get_err:
static int clk_set_default_parents(struct udevice *dev)
{
+ struct ofnode_phandle_args args;
struct clk clk, parent_clk;
int index;
int num_parents;
- int ret;
+ int ret, err;
num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents",
"#clock-cells");
@@ -211,8 +168,13 @@ static int clk_set_default_parents(struct udevice *dev)
}
for (index = 0; index < num_parents; index++) {
- ret = clk_get_by_indexed_prop(dev, "assigned-clock-parents",
- index, &parent_clk);
+ err = dev_read_phandle_with_args(dev, "assigned-clock-parents",
+"#clock-cells", 0,
+index, &args);
+
+ ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args,
+ "assigned-clock-parents",
+ index > 0, &parent_clk);
/* If -ENOENT, this is a no-op entry */
if (ret == -ENOENT)
continue;
@@ -223,8 +185,13 @@ static int clk_set_default_parents(struct udevice *dev)
return ret;
}
- ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
- index, &clk);
+ err = dev_read_phandle_with_args(dev, "assigned-clocks",
+"#clock-cells", 0,
+index, &args);
+
+ ret = clk_get_by_index_tail(err, dev_ofnode(dev), &args,
+ "assigned-clocks",
+ index > 0, &clk);
if (ret) {
debug("%s: could not get assigned clock %d for %s\n",
__func__, index, dev_read_name(dev));
@@ -252,11 +219,12 @@ static int clk_set_default_parents(struct udevice *dev)
static int clk_set_default_rates(struct udevice *dev)
{
+ struct ofnode_phandle_args args;
struct clk clk;
int index;
int num_rates;
int size;
- int ret = 0;
+ int err, ret = 0;
u32 *rates = NULL;
size = dev_read_size(dev, "assigned-clock-rates");
@@ -277,8 +245,13 @@ static int clk_set_default_rates(struct udevice *dev)
if (!rates[index])
continue;
- ret = clk_get_by_indexed_prop(dev, "assigned-clocks",
- index, &clk);
+ err = dev_read_phandle_with_args(dev, "assigned-clocks",
+"#clock-cells", 0,
+
[U-Boot] [PATCH v2 04/13] clk: Get the CLK by index without device
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()
Cc: Simon Glass
Cc: Stephen Warren
Signed-off-by: Jagan Teki
---
drivers/clk/clk-uclass.c | 61 +++-
include/clk.h| 15 ++
2 files changed, 75 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index 844b87cc33..dc0b7809d2 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -98,9 +98,68 @@ static int clk_get_by_indexed_prop(struct udevice *dev,
const char *prop_name,
return clk_request(dev_clk, clk);
}
+static int clk_get_by_index_tail(int ret, ofnode node,
+struct ofnode_phandle_args *args,
+const char *list_name, int index,
+struct clk *clk)
+{
+ struct udevice *dev_clk;
+ const struct clk_ops *ops;
+
+ assert(clk);
+ clk->dev = NULL;
+ if (ret)
+ goto err;
+
+ ret = uclass_get_device_by_ofnode(UCLASS_CLK, args->node, &dev_clk);
+ if (ret) {
+ debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ clk->dev = dev_clk;
+
+ ops = clk_dev_ops(dev_clk);
+
+ if (ops->of_xlate)
+ ret = ops->of_xlate(clk, args);
+ else
+ ret = clk_of_xlate_default(clk, args);
+ if (ret) {
+ debug("of_xlate() failed: %d\n", ret);
+ return ret;
+ }
+
+ return clk_request(dev_clk, clk);
+err:
+ debug("%s: Node '%s', property '%s', failed to request CLK index %d:
%d\n",
+ __func__, ofnode_get_name(node), list_name, index, ret);
+ return ret;
+}
+
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk)
{
- return clk_get_by_indexed_prop(dev, "clocks", index, clk);
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "clocks", "#clock-cells", 0,
+index, &args);
+
+ return clk_get_by_index_tail(ret, dev_ofnode(dev), &args, "clocks",
+index > 0, clk);
+}
+
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "clocks", "#clock-cells", 0,
+index > 0, &args);
+
+ return clk_get_by_index_tail(ret, node, &args, "clocks",
+index > 0, clk);
}
int clk_get_bulk(struct udevice *dev, struct clk_bulk *bulk)
diff --git a/include/clk.h b/include/clk.h
index 8e366163f9..d24e99713a 100644
--- a/include/clk.h
+++ b/include/clk.h
@@ -8,6 +8,7 @@
#ifndef _CLK_H_
#define _CLK_H_
+#include
#include
#include
@@ -100,6 +101,20 @@ int clk_get_by_index_platdata(struct udevice *dev, int
index,
*/
int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
+/**
+ * clock_get_by_index_nodev - Get/request a clock by integer index
+ * without a device.
+ *
+ * This is a version of clk_get_by_index() that does not use a device.
+ *
+ * @node: The client ofnode.
+ * @index: The index of the clock to request, within the client's list of
+ * clocks.
+ * @clock A pointer to a clock struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int clk_get_by_index_nodev(ofnode node, int index, struct clk *clk);
+
/**
* clock_get_bulk - Get/request all clocks of a device.
*
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 07/13] reset: Get the RESET by index without device
Getting a RESET by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process RESET operation for child
without udevice but with ofnode.
So add reset_get_by_index_nodev() and move the common code
in reset_get_by_index_tail() to use for reset_get_by_index()
Cc: Stephen Warren
Cc: Simon Glass
Signed-off-by: Jagan Teki
---
drivers/reset/reset-uclass.c | 53
include/reset.h | 16 +++
2 files changed, 52 insertions(+), 17 deletions(-)
diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c
index 89e39c6b5a..ee1a423ffb 100644
--- a/drivers/reset/reset-uclass.c
+++ b/drivers/reset/reset-uclass.c
@@ -29,41 +29,34 @@ static int reset_of_xlate_default(struct reset_ctl
*reset_ctl,
return 0;
}
-int reset_get_by_index(struct udevice *dev, int index,
- struct reset_ctl *reset_ctl)
+static int reset_get_by_index_tail(int ret, ofnode node,
+ struct ofnode_phandle_args *args,
+ const char *list_name, int index,
+ struct reset_ctl *reset_ctl)
{
- struct ofnode_phandle_args args;
- int ret;
struct udevice *dev_reset;
struct reset_ops *ops;
- debug("%s(dev=%p, index=%d, reset_ctl=%p)\n", __func__, dev, index,
- reset_ctl);
+ assert(reset_ctl);
reset_ctl->dev = NULL;
-
- ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
- index, &args);
- if (ret) {
- debug("%s: fdtdec_parse_phandle_with_args() failed: %d\n",
- __func__, ret);
+ if (ret)
return ret;
- }
- ret = uclass_get_device_by_ofnode(UCLASS_RESET, args.node,
+ ret = uclass_get_device_by_ofnode(UCLASS_RESET, args->node,
&dev_reset);
if (ret) {
debug("%s: uclass_get_device_by_ofnode() failed: %d\n",
__func__, ret);
- debug("%s %d\n", ofnode_get_name(args.node), args.args[0]);
+ debug("%s %d\n", ofnode_get_name(args->node), args->args[0]);
return ret;
}
ops = reset_dev_ops(dev_reset);
reset_ctl->dev = dev_reset;
if (ops->of_xlate)
- ret = ops->of_xlate(reset_ctl, &args);
+ ret = ops->of_xlate(reset_ctl, args);
else
- ret = reset_of_xlate_default(reset_ctl, &args);
+ ret = reset_of_xlate_default(reset_ctl, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
return ret;
@@ -78,6 +71,32 @@ int reset_get_by_index(struct udevice *dev, int index,
return 0;
}
+int reset_get_by_index(struct udevice *dev, int index,
+ struct reset_ctl *reset_ctl)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = dev_read_phandle_with_args(dev, "resets", "#reset-cells", 0,
+index, &args);
+
+ return reset_get_by_index_tail(ret, dev_ofnode(dev), &args, "resets",
+ index > 0, reset_ctl);
+}
+
+int reset_get_by_index_nodev(ofnode node, int index,
+struct reset_ctl *reset_ctl)
+{
+ struct ofnode_phandle_args args;
+ int ret;
+
+ ret = ofnode_parse_phandle_with_args(node, "resets", "#reset-cells", 0,
+index > 0, &args);
+
+ return reset_get_by_index_tail(ret, node, &args, "resets",
+ index > 0, reset_ctl);
+}
+
int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk)
{
int i, ret, err, count;
diff --git a/include/reset.h b/include/reset.h
index 65aa7a4ce5..57bbc0b49d 100644
--- a/include/reset.h
+++ b/include/reset.h
@@ -6,6 +6,7 @@
#ifndef _RESET_H
#define _RESET_H
+#include
#include
/**
@@ -99,6 +100,21 @@ struct reset_ctl_bulk {
int reset_get_by_index(struct udevice *dev, int index,
struct reset_ctl *reset_ctl);
+/**
+ * reset_get_by_index_nodev - Get/request a reset signal by integer index
+ * without a device.
+ *
+ * This is a version of reset_get_by_index() that does not use a device.
+ *
+ * @node: The client ofnode.
+ * @index: The index of the reset signal to request, within the client's
+ * list of reset signals.
+ * @reset_ctl A pointer to a reset control struct to initialize.
+ * @return 0 if OK, or a negative error code.
+ */
+int reset_get_by_index_nodev(ofnode node, int index,
+struct reset_ctl *reset_ctl);
+
/**
* reset_get_bulk - Get/request all reset signals of a device.
*
--
2.18.0.
[U-Boot] [PATCH v2 13/13] board: sunxi: gmac: Remove Ethernet clock and reset
Since Ethernet clock and reset is now handling via CLK and RESET frameworks via driver API's remove explicit ccm writes. Signed-off-by: Jagan Teki --- board/sunxi/gmac.c | 8 1 file changed, 8 deletions(-) diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 826650c89b..d8fdf7728e 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -12,14 +12,6 @@ void eth_init_board(void) struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - /* Set up clock gating */ -#ifdef CONFIG_SUNXI_GEN_SUN6I - setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC); - setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC); -#else - setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC); -#endif - /* Set MII clock */ #ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | -- 2.18.0.321.gffc6fa0e3 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 12/13] net: sun8i_emac: Add EPHY CLK and RESET support
Add EPHY CLK and RESET support for sun8i_emac driver to
enable EPHY TX clock and EPHY reset pins via CLK and RESET
framework.
Cc: Joe Hershberger
Cc: Lothar Felten
Signed-off-by: Jagan Teki
---
drivers/net/sun8i_emac.c | 72 ++--
1 file changed, 55 insertions(+), 17 deletions(-)
diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index 98bd7a5823..28347cb543 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -138,7 +138,9 @@ struct emac_eth_dev {
struct phy_device *phydev;
struct mii_dev *bus;
struct clk tx_clk;
+ struct clk ephy_clk;
struct reset_ctl tx_rst;
+ struct reset_ctl ephy_rst;
#ifdef CONFIG_DM_GPIO
struct gpio_desc reset_gpio;
#endif
@@ -653,7 +655,6 @@ static int sun8i_eth_write_hwaddr(struct udevice *dev)
static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
int ret;
ret = clk_enable(&priv->tx_clk);
@@ -670,16 +671,20 @@ static int sun8i_emac_board_setup(struct emac_eth_dev
*priv)
}
}
- if (priv->variant == H3_EMAC) {
- /* Only H3/H5 have clock controls for internal EPHY */
- if (priv->use_internal_phy) {
- /* Set clock gating for ephy */
- setbits_le32(&ccm->bus_gate4,
-BIT(AHB_GATE_OFFSET_EPHY));
-
- /* Deassert EPHY */
- setbits_le32(&ccm->ahb_reset2_cfg,
-BIT(AHB_RESET_OFFSET_EPHY));
+ /* Only H3/H5 have clock controls for internal EPHY */
+ if (clk_valid(&priv->ephy_clk)) {
+ ret = clk_enable(&priv->ephy_clk);
+ if (ret) {
+ dev_err(dev, "failed to enable EPHY TX clock\n");
+ return ret;
+ }
+ }
+
+ if (reset_valid(&priv->ephy_rst)) {
+ ret = reset_deassert(&priv->ephy_rst);
+ if (ret) {
+ dev_err(dev, "failed to deassert EPHY TX clock\n");
+ return ret;
}
}
@@ -839,6 +844,42 @@ static const struct eth_ops sun8i_emac_eth_ops = {
.stop = sun8i_emac_eth_stop,
};
+static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
+{
+ int node, ret;
+
+ /* look for mdio-mux node for internal PHY node */
+ node = fdt_path_offset(gd->fdt_blob,
+ "/soc/ethernet@1c3/mdio-mux/mdio@1/ethernet-phy@1");
+ if (node < 0) {
+ debug("failed to get mdio-mux with internal PHY\n");
+ return node;
+ }
+
+ ret = fdt_node_check_compatible(gd->fdt_blob, node,
+ "allwinner,sun8i-h3-mdio-internal");
+ if (ret < 0) {
+ debug("failed to find mdio-internal node\n");
+ return ret;
+ }
+
+ ret = clk_get_by_index_nodev(offset_to_ofnode(node), 0,
&priv->ephy_clk);
+ if (ret) {
+ dev_err(dev, "failed to get EPHY TX clock\n");
+ return ret;
+ }
+
+ ret = reset_get_by_index_nodev(offset_to_ofnode(node), 0,
&priv->ephy_rst);
+ if (ret) {
+ dev_err(dev, "failed to get EPHY TX reset\n");
+ return ret;
+ }
+
+ priv->use_internal_phy = true;
+
+ return 0;
+}
+
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
{
struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
@@ -920,12 +961,9 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct
udevice *dev)
}
if (priv->variant == H3_EMAC) {
- int parent = fdt_parent_offset(gd->fdt_blob, offset);
-
- if (parent >= 0 &&
- !fdt_node_check_compatible(gd->fdt_blob, parent,
- "allwinner,sun8i-h3-mdio-internal"))
- priv->use_internal_phy = true;
+ ret = sun8i_get_ephy_nodes(priv);
+ if (ret)
+ return ret;
}
priv->interface = pdata->phy_interface;
--
2.18.0.321.gffc6fa0e3
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[U-Boot] [PATCH v2 11/13] clk: sunxi: h3: Implement EPHY CLK and RESET
EPHY CLK and RESET is availble in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respetive
clock and reset reg and bits.
Cc: Joe Hershberger
Signed-off-by: Jagan Teki
---
drivers/clk/sunxi/clk_h3.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f5ae1e9555..6111a13f1c 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -34,6 +34,8 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
[CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
+ [CLK_BUS_EPHY] = GATE(0x070, BIT(0)),
+
[CLK_SPI0] = GATE(0x0a0, BIT(31)),
[CLK_SPI1] = GATE(0x0a4, BIT(31)),
@@ -69,6 +71,8 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
[RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
+ [RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
--
2.18.0.321.gffc6fa0e3
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Re: [U-Boot] [PATCH] Kconfig: fix BUILD_TARGET for ARCH_MVEBU
On Thu, Feb 7, 2019 at 4:52 PM Baruch Siach wrote:
>
> Commit dc146ca11187 ("Kconfig: Migrate CONFIG_BUILD_TARGET") made the
> mvebu default build target depend on CONFIG_SPL_BUILD. Unfortunately,
> there is no such Kconfig symbol. Use the CONFIG_SPL symbol instead to
> fix that.
>
> Cc: Jagan Teki
> Signed-off-by: Baruch Siach
> ---
> Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Kconfig b/Kconfig
> index 2a48f5325663..512c7beb89f9 100644
> --- a/Kconfig
> +++ b/Kconfig
> @@ -227,7 +227,7 @@ config BUILD_ROM
> config BUILD_TARGET
> string "Build target special images"
> default "u-boot-with-spl.sfp" if ARCH_SOCFPGA
> - default "u-boot-spl.kwb" if ARCH_MVEBU && SPL_BUILD
> + default "u-boot-spl.kwb" if ARCH_MVEBU && SPL
Reviewed-by: Jagan Teki
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Re: [U-Boot] [RFT 6/8] power: regulator: s2mps11: Add enable delay
Hi Krzysztof,
> According to datasheet, the output on LDO regulators will start
> appearing after 10-15 us.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> drivers/power/regulator/s2mps11_regulator.c | 9 -
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/power/regulator/s2mps11_regulator.c
> b/drivers/power/regulator/s2mps11_regulator.c index
> 723d27f67c9a..1f1581852ee2 100644 ---
> a/drivers/power/regulator/s2mps11_regulator.c +++
> b/drivers/power/regulator/s2mps11_regulator.c @@ -551,7 +551,14 @@
> static int ldo_get_enable(struct udevice *dev)
> static int ldo_set_enable(struct udevice *dev, bool enable)
> {
> - return s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable);
> + int ret;
> +
> + ret = s2mps11_ldo_enable(dev, PMIC_OP_SET, &enable);
> +
> + /* Wait the "enable delay" for voltage to start to rise */
> + udelay(15);
I assume, that this value is the same as in the Linux driver?
> +
> + return ret;
> }
>
> static int ldo_get_mode(struct udevice *dev)
Best regards,
Lukasz Majewski
--
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lu...@denx.de
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Re: [U-Boot] [RFT 8/8] arm: dts: exynos: Add ramp delay property to LDO regulators to Odroid XU3 family
Hi Krzysztof,
> Add startup time to LDO regulators of S2MPS11 PMIC on Odroid
> XU3/XU4/HC1 family of boards to be sure the voltage is proper before
> relying on the regulator.
>
> The datasheet for all the S2MPS1x family is inconsistent here and does
> not specify unambiguously the value of ramp delay for LDO. It
> mentions 30 mV/us in one timing diagram but then omits it completely
> in LDO regulator characteristics table (it is specified for bucks).
>
> However the vendor kernels for Galaxy S5 and Odroid XU3 use values of
> 12 mV/us or 24 mV/us.
>
> Without the ramp delay value the consumers do not wait for voltage
> settle after changing it. Although the proper value of ramp delay for
> LDOs is unknown, it seems safer to use at least some value from
> reference kernel than to leave it unset.
>
> Signed-off-by: Krzysztof Kozlowski
Reviewed-by: Lukasz Majewski
> ---
> arch/arm/dts/exynos5422-odroidxu3.dts | 19 +++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/dts/exynos5422-odroidxu3.dts
> b/arch/arm/dts/exynos5422-odroidxu3.dts index
> 9dfae90667cf..04ecc404f907 100644 ---
> a/arch/arm/dts/exynos5422-odroidxu3.dts +++
> b/arch/arm/dts/exynos5422-odroidxu3.dts @@ -45,6 +45,7 @@
> regulator-name = "vdd_ldo1";
> regulator-min-microvolt =
> <100>; regulator-max-microvolt = <100>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -52,18 +53,21 @@
> regulator-name = "vddq_mmc0";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; };
>
> ldo4_reg: LDO4 {
> regulator-name = "vdd_adc";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; };
>
> ldo5_reg: LDO5 {
> regulator-name = "vdd_ldo5";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -71,6 +75,7 @@
> regulator-name = "vdd_ldo6";
> regulator-min-microvolt =
> <100>; regulator-max-microvolt = <100>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -78,6 +83,7 @@
> regulator-name = "vdd_ldo7";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -85,6 +91,7 @@
> regulator-name = "vdd_ldo8";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -92,6 +99,7 @@
> regulator-name = "vdd_ldo9";
> regulator-min-microvolt =
> <300>; regulator-max-microvolt = <300>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -99,6 +107,7 @@
> regulator-name = "vdd_ldo10";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -106,6 +115,7 @@
> regulator-name = "vdd_ldo11";
> regulator-min-microvolt =
> <100>; regulator-max-microvolt = <100>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -113,6 +123,7 @@
> regulator-name = "vdd_ldo12";
> regulator-min-microvolt =
> <180>; regulator-max-microvolt = <180>;
> + regulator-ramp-delay =
> <12000>; regulator-always-on;
> };
>
> @@ -120,12 +131,14 @@
> regulator-name = "vdd
Re: [U-Boot] [RFT 1/8] exynos: Redo detection of revision when all resources are ready
Hi Krzysztof,
> Detection of board type is done early - before power setup. In case
> of Odroid XU3/XU4/HC1 family, the detection is done using ADC which
> is supplied by LDO4/VDD_ADC regulator. This regulator could be turned
> off (e.g. by kernel before reboot); If ADC is used early, the
> regulators are not yet available and the detection won't work.
>
> Try to detect the revision again, once power is brought up.
>
> This is necessary to fix the detection of Odroid HC1 after reboot, if
> kernel turned off the LDO4 regulator. Otherwise the board is not
> detected
But such approach seems not to be the optimal one (as we perform
detection twice - with default LDO4 enabled after power on and after
soft reset).
I would expect to enable the LDO4 regulator in the early code (I2C
would be probably necessary) and then read ADC value properly once.
(I also guess that the "work-by-chance" approach is caused by default
settings of PMIC after power on).
As fair as I remember, TI is able to read the EEPROM via I2C in the
very early u-boot (MLO to be precise) code and then make the decision
regarding the platform.
Maybe it would be possible to do the same with Samsung?
And another thought - if the set_board_type() can be called latter and
it works - why cannot we move it to this latter point and execute
exactly once?
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> board/samsung/common/board.c | 19 ++-
> 1 file changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/board/samsung/common/board.c
> b/board/samsung/common/board.c index 6fd26a3a9198..1e2dabe68d11 100644
> --- a/board/samsung/common/board.c
> +++ b/board/samsung/common/board.c
> @@ -147,6 +147,11 @@ int board_early_init_f(void)
> {
> int err;
> #ifdef CONFIG_BOARD_TYPES
> + /*
> + * It is done early so power might not be set up yet. In
> such case
> + * specific revision detection with ADC might not work and
> need to me
> + * redone later.
> + */
> set_board_type();
> #endif
> err = board_uart_init();
> @@ -166,9 +171,21 @@ int board_early_init_f(void)
> #if defined(CONFIG_POWER) || defined(CONFIG_DM_PMIC)
> int power_init_board(void)
> {
> + int ret;
> +
> set_ps_hold_ctrl();
>
> - return exynos_power_init();
> + ret = exynos_power_init();
> +
> +#ifdef CONFIG_BOARD_TYPES
> + /*
> + * Since power is on, redo the board detection (external
> peripherals
> + * are on).
> + */
> + set_board_type();
> +#endif
> +
> + return ret;
> }
> #endif
>
Best regards,
Lukasz Majewski
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[U-Boot] [PATCH] configs: at91: remove SPL_GENERATE_ATMEL_PMECC_HEADER from non-nand configs
From: Eugen Hristev SPL_GENERATE_ATMEL_PMECC_HEADER will generate a header for the SPL for NAND information. The initial stage 1 bootloader will use this header in case the NAND flash doesn't support commands to retrieve sector size, etc. However this header is bad for different boot media, like MMC or SPI. In case SD_BOOT or SPI_BOOT is used, remove the config for this. Signed-off-by: Eugen Hristev --- It's time to fix this after the patches by Derald Woods: "49ad40298cc56" ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to Kconfig which expose the nand PMECC header to Kconfig configs/at91sam9n12ek_mmc_defconfig | 1 - configs/at91sam9n12ek_spiflash_defconfig| 1 - configs/at91sam9x5ek_mmc_defconfig | 1 - configs/at91sam9x5ek_spiflash_defconfig | 1 - configs/sama5d36ek_cmp_mmc_defconfig| 1 - configs/sama5d36ek_cmp_spiflash_defconfig | 1 - configs/sama5d3_xplained_mmc_defconfig | 1 - configs/sama5d3xek_mmc_defconfig| 1 - configs/sama5d3xek_spiflash_defconfig | 1 - configs/sama5d4_xplained_mmc_defconfig | 1 - configs/sama5d4_xplained_spiflash_defconfig | 1 - configs/sama5d4ek_mmc_defconfig | 1 - configs/sama5d4ek_spiflash_defconfig| 1 - 13 files changed, 13 deletions(-) diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 853a264..6b2cfe9 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -41,7 +41,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index 273f91c..6388935 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -41,7 +41,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 5deabaf..ff86f93 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 5f06231..d0eebcd 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index ced445f..3026cab 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 1f1fc8e..04ca6a8 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -43,7 +43,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index ab5aedc..f0995da 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -61,7 +61,6 @@ CONFIG_DM_MMC=y CONFIG_GENERIC_ATMEL_MCI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index 404af1f..548b0b8 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -68,7 +68,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 43db387..824fa27 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -63,7 +63,6 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_NAND=y CONFIG_NAND_ATMEL=y CONFIG_PMECC_CAP=4 -CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_DM_SPI_FLASH=y CONFIG
Re: [U-Boot] [PATCH v2] mtd: add spi flash id s25fl064l
On Fri, Feb 8, 2019 at 3:33 PM Heiko Schocher wrote: > > Add support for SPANSION s25fl064l > > Signed-off-by: Heiko Schocher > --- Applied to u-boot-spi/next ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 0/4] spi-flash: switch to "jedec, spi-nor" binding
On Sun, Feb 10, 2019 at 3:46 PM Neil Armstrong wrote: > > There is no reason not to use the Linux "jedec,spi-nor" binding in u-boot. > This patchset : > - switches all DTS/DTSI files to "jedec,spi-nor" > - remove the "spi-flash" compatible from sf-probe > - switch GENERIC_SPI_FLASH to jedec,spi-nor in fdtdec > - switches dt bindings examples files to "jedec,spi-nor" > > Changes since v3: > - collected tags > - dropped patch 1 > - updated for new boards > > Changes since v2: > - collected tags > - extracted x86 dts changed and merged it with the fdtdec change > - updated for new boards > > Neil Armstrong (4): > dts: switch spi-flash to jedec, spi-nor compatible > x86: dts: switch spi-flash to jedec, spi-nor compatible > mtd: sf_probe: remove spi-flash compatible > doc: device-tree-bindings: switch from spi-flash to jedec, spi-nor Reviewed-by: Jagan Teki Applied to u-boot-spi/next ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] sun50i: h5: Orange Pi Zero Plus: Fix SdCard detection
On Sun, Jan 13, 2019 at 10:12 PM Hauke Mehrtens wrote:
>
> The Detection pin is at PF6 and not at PH13 like defined before. I
> checked the schematics and now I am am not seeing this error message any
> more:
> Loading Environment from FAT... Card did not respond to voltage select!
>
> CONFIG_MMC_SUNXI_SLOT_EXTRA is also not needed because the second MCC
> slot is for the Wifi card.
>
> Fixes: 76d69eb01de ("sun50i: h5: Add initial Orange Pi Zero Plus support")
> Signed-off-by: Hauke Mehrtens
> ---
Applied to u-boot-sunxi/master
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[U-Boot] [PATCH] pci: Add comment to mention difference in DEVFN usage in U-Boot vs Linux
This patch adds a comment to the header with the PCI_foo macros related to DEVFN to explain the difference in U-Boot vs Linux. Signed-off-by: Stefan Roese Cc: Simon Glass Cc: Bin Meng --- include/pci.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/pci.h b/include/pci.h index 041f8e3747..93fdd8fe6a 100644 --- a/include/pci.h +++ b/include/pci.h @@ -499,9 +499,20 @@ static inline void pci_set_region(struct pci_region *reg, typedef int pci_dev_t; #define PCI_BUS(d) (((d) >> 16) & 0xff) + +/* + * Please note the difference in DEVFN usage in U-Boot vs Linux. U-Boot + * uses DEVFN in bits 15-8 but Linux instead expects DEVFN in bits 7-0. + * Please see the Linux header include/uapi/linux/pci.h for more details. + * This is relevant for the following macros: + * PCI_DEV, PCI_FUNC, PCI_DEVFN + * The U-Boot macro PCI_DEV is equivalent to the Linux PCI_SLOT version with + * the remark from above (input d in bits 15-8 instead of 7-0. + */ #define PCI_DEV(d) (((d) >> 11) & 0x1f) #define PCI_FUNC(d)(((d) >> 8) & 0x7) #define PCI_DEVFN(d, f)((d) << 11 | (f) << 8) + #define PCI_MASK_BUS(bdf) ((bdf) & 0x) #define PCI_ADD_BUS(bus, devfn)(((bus) << 16) | (devfn)) #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f)) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 01/15] riscv: Enable create symlink using kconfig
On Mon, Feb 11, 2019 at 1:41 PM Anup Patel wrote: > > We select CREATE_ARCH_SYMLINK for RISC-V so that we can have > include/asm/arch linked to include/asm/arch-xyz. > > Signed-off-by: Anup Patel > --- > arch/Kconfig | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v7 04/15] riscv: Add place-holder asm/arch/clk.h for driver compilation
On Mon, Feb 11, 2019 at 1:41 PM Anup Patel wrote: > > Some of the drivers (such as Cadence MACB ethernet driver) expect > asm/arch/clk.h to be provided by arch support so we add place-holder > asm/arch-generic/clk.h for RISC-V generic CPU. > > Signed-off-by: Anup Patel > Reviewed-by: Lukas Auer > --- > arch/riscv/include/asm/arch-generic/clk.h | 14 ++ > 1 file changed, 14 insertions(+) > create mode 100644 arch/riscv/include/asm/arch-generic/clk.h > Reviewed-by: Bin Meng ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
