[U-Boot] [PATCH 3/3] arm: mvebu: db-88f6820-gp: Enabel BLK and DM support
This patch enables CONFIG_BLK and some DM enabled drivers on db-88f6820-gp to remove these compile warnings: = WARNING == This board does not use CONFIG_DM_MMC. Please update the board to use CONFIG_DM_MMC before the v2019.04 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does use CONFIG_LIBATA but has CONFIG_AHCI not enabled. Please update the storage controller driver to use CONFIG_AHCI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. Signed-off-by: Stefan Roese --- configs/db-88f6820-gp_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/db-88f6820-gp_defconfig b/configs/db-88f6820-gp_defconfig index 6ee3151861..b8f036e317 100644 --- a/configs/db-88f6820-gp_defconfig +++ b/configs/db-88f6820-gp_defconfig @@ -13,6 +13,7 @@ CONFIG_DEBUG_UART_CLOCK=25000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set @@ -47,7 +48,8 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=5000 CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/3] arm: mvebu: db-88f6720: Enable CONFIG_BLK
This patch enables CONFIG_BLK to remove this compile warning: = WARNING == This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. Signed-off-by: Stefan Roese --- configs/db-88f6720_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/db-88f6720_defconfig b/configs/db-88f6720_defconfig index 25421407e2..c1a430cf3b 100644 --- a/configs/db-88f6720_defconfig +++ b/configs/db-88f6720_defconfig @@ -44,6 +44,7 @@ CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=5000 CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BLK=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_SPI_FLASH=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/3] arm: mvebu: clearfog: Enable BLK and DM support
This patch enables CONFIG_BLK and some DM enabled drivers on clearfog to remove these compile warnings: = WARNING == This board does not use CONFIG_DM_MMC. Please update the board to use CONFIG_DM_MMC before the v2019.04 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. = WARNING == This board does use CONFIG_LIBATA but has CONFIG_AHCI not enabled. Please update the storage controller driver to use CONFIG_AHCI before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. Signed-off-by: Stefan Roese --- configs/clearfog_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/clearfog_defconfig b/configs/clearfog_defconfig index 05b19b31c0..6e6fd2c78e 100644 --- a/configs/clearfog_defconfig +++ b/configs/clearfog_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=25000 CONFIG_DEBUG_UART=y +CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_INFO_QUIET=y @@ -40,11 +41,12 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-388-clearfog" CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_OF_TRANSLATE=y -CONFIG_SCSI_AHCI=y +CONFIG_AHCI_MVEBU=y CONFIG_DM_GPIO=y CONFIG_DM_PCA953X=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_MVTWSI=y +CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_SDMA=y CONFIG_MMC_SDHCI_MV=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 2/3] arm: dts: Stratix10: Add SDRAM node
Add SDRAM device tree node.
Signed-off-by: Ley Foon Tan
---
arch/arm/dts/socfpga_stratix10.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
index d1ae2fabae..bd68a78a37 100755
--- a/arch/arm/dts/socfpga_stratix10.dtsi
+++ b/arch/arm/dts/socfpga_stratix10.dtsi
@@ -258,6 +258,15 @@
u-boot,dm-pre-reloc;
};
+ sdr: sdr@f8000400 {
+compatible = "altr,sdr-ctl-s10";
+reg = <0xf8000400 0x80>,
+ <0xf801 0x190>,
+ <0xf8011000 0x500>;
+resets = <&rst DDRSCH_RESET>;
+u-boot,dm-pre-reloc;
+};
+
spi0: spi@ffda4000 {
compatible = "snps,dw-apb-ssi";
#address-cells = <1>;
--
2.19.0
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[U-Boot] [PATCH v4 1/3] ddr: altera: Compile ALTERA SDRAM in SPL only
Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan --- Makefile | 2 +- arch/arm/mach-socfpga/Kconfig | 4 ++-- drivers/Makefile | 2 +- drivers/ddr/altera/Kconfig| 5 +++-- drivers/ddr/altera/Makefile | 2 +- include/configs/socfpga_stratix10_socdk.h | 2 +- scripts/config_whitelist.txt | 1 + 7 files changed, 10 insertions(+), 8 deletions(-) diff --git a/Makefile b/Makefile index 66a09ac900..53c7709d22 100644 --- a/Makefile +++ b/Makefile @@ -713,7 +713,7 @@ libs-y += drivers/spi/ libs-$(CONFIG_FMAN_ENET) += drivers/net/fm/ libs-$(CONFIG_SYS_FSL_DDR) += drivers/ddr/fsl/ libs-$(CONFIG_SYS_FSL_MMDC) += drivers/ddr/fsl/ -libs-$(CONFIG_ALTERA_SDRAM) += drivers/ddr/altera/ +libs-$(CONFIG_$(SPL_)ALTERA_SDRAM) += drivers/ddr/altera/ libs-y += drivers/serial/ libs-y += drivers/usb/dwc3/ libs-y += drivers/usb/common/ diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 5e87371f8c..d4d878d3be 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -9,7 +9,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool - select ALTERA_SDRAM + select SPL_ALTERA_SDRAM select SPL_BOARD_INIT if SPL select CLK select SPL_CLK if SPL @@ -28,7 +28,7 @@ config TARGET_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_GEN5 bool - select ALTERA_SDRAM + select SPL_ALTERA_SDRAM config TARGET_SOCFPGA_STRATIX10 bool diff --git a/drivers/Makefile b/drivers/Makefile index a7bba3ed56..e501ae8d04 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,7 +34,7 @@ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT) += ddr/fsl/ obj-$(CONFIG_ARMADA_38X) += ddr/marvell/a38x/ obj-$(CONFIG_ARMADA_XP) += ddr/marvell/axp/ -obj-$(CONFIG_ALTERA_SDRAM) += ddr/altera/ +obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/ power/pmic/ obj-$(CONFIG_SPL_POWER_SUPPORT) += power/regulator/ diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 8f60b56eb8..83c1ab5e07 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,5 +1,6 @@ -config ALTERA_SDRAM - bool "SoCFPGA DDR SDRAM driver" +config SPL_ALTERA_SDRAM + bool "SoCFPGA DDR SDRAM driver in SPL" + depends on SPL depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select RAM if TARGET_SOCFPGA_GEN5 select SPL_RAM if TARGET_SOCFPGA_GEN5 diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 3615b617ec..341ac0d73b 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -6,7 +6,7 @@ # (C) Copyright 2010, Thomas Chou # Copyright (C) 2014 Altera Corporation -ifdef CONFIG_ALTERA_SDRAM +ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h index 31c267f55d..9d1bc8e8d5 100644 --- a/include/configs/socfpga_stratix10_socdk.h +++ b/include/configs/socfpga_stratix10_socdk.h @@ -132,7 +132,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); /* * SDRAM controller */ -#define CONFIG_ALTERA_SDRAM +#define CONFIG_SPL_ALTERA_SDRAM /* * Serial / UART configurations diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 421362d953..f0c755fc83 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1826,6 +1826,7 @@ CONFIG_SPLASH_SCREEN_ALIGN CONFIG_SPLASH_SOURCE CONFIG_SPLL_FREQ CONFIG_SPL_ +CONFIG_SPL_ALTERA_SDRAM CONFIG_SPL_ATMEL_SIZE CONFIG_SPL_BOARD_LOAD_IMAGE CONFIG_SPL_BOOTROM_SAVE -- 2.19.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 3/3] arm: socfpga: Move Stratix 10 SDRAM driver to DM
Convert Stratix 10 SDRAM driver to device model.
Get rid of call to socfpga_per_reset() and use reset
framework.
SPL is changed from calling function in SDRAM driver
directly to just probing UCLASS_RAM.
Move sdram_s10.h from arch to driver/ddr/altera directory.
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/spl_s10.c | 16 +-
configs/socfpga_stratix10_defconfig | 1 +
drivers/ddr/altera/Kconfig| 6 +-
drivers/ddr/altera/sdram_s10.c| 243 --
.../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
include/configs/socfpga_stratix10_socdk.h | 5 -
scripts/config_whitelist.txt | 1 -
7 files changed, 183 insertions(+), 93 deletions(-)
rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h
(97%)
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c
index a141ffe82a..ec65e1ce64 100644
--- a/arch/arm/mach-socfpga/spl_s10.c
+++ b/arch/arm/mach-socfpga/spl_s10.c
@@ -15,9 +15,9 @@
#include
#include
#include
-#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -175,11 +175,15 @@ void board_init_f(ulong dummy)
clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
- debug("DDR: Initializing Hard Memory Controller\n");
- if (sdram_mmr_init_full(0)) {
- puts("DDR: Initialization failed.\n");
- hang();
- }
+#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
+ struct udevice *dev;
+
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM init failed: %d\n", ret);
+ hang();
+ }
+#endif
mbox_init();
diff --git a/configs/socfpga_stratix10_defconfig
b/configs/socfpga_stratix10_defconfig
index 4848013b21..c85a0f785a 100644
--- a/configs/socfpga_stratix10_defconfig
+++ b/configs/socfpga_stratix10_defconfig
@@ -32,6 +32,7 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_ALTERA_SDRAM=y
CONFIG_DM_GPIO=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 83c1ab5e07..2b1c1be3b5 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -1,8 +1,8 @@
config SPL_ALTERA_SDRAM
bool "SoCFPGA DDR SDRAM driver in SPL"
depends on SPL
- depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select RAM if TARGET_SOCFPGA_GEN5
- select SPL_RAM if TARGET_SOCFPGA_GEN5
+ depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 ||
TARGET_SOCFPGA_STRATIX10
+ select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
+ select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c
index e4d4a02ca2..56cbbac9fe 100644
--- a/drivers/ddr/altera/sdram_s10.c
+++ b/drivers/ddr/altera/sdram_s10.c
@@ -5,17 +5,31 @@
*/
#include
+#include
#include
#include
#include
-#include
+#include
+#include
+#include "sdram_s10.h"
#include
#include
-#include
#include
#include
+#include
#include
+struct altera_sdram_priv {
+ struct ram_info info;
+ struct reset_ctl_bulk resets;
+};
+
+struct altera_sdram_platdata {
+ void __iomem *hmc;
+ void __iomem *ddr_sch;
+ void __iomem *iomhc;
+};
+
DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_system_manager *sysmgr_regs =
@@ -51,25 +65,26 @@ u32 ddr_config[] = {
DDR_CONFIG(1, 4, 10, 17),
};
-static u32 hmc_readl(u32 reg)
+static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
+ return readl(plat->iomhc + reg);
}
-static u32 hmc_ecc_readl(u32 reg)
+static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
{
- return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return readl(plat->hmc + reg);
}
-static u32 hmc_ecc_writel(u32 data, u32 reg)
+static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
+ u32 data, u32 reg)
{
- return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
+ return writel(data, plat->hmc + reg);
}
-static u32 ddr_sch_writel(u32 data, u32 reg)
+static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
+ u32 reg)
{
- return writel(data,
- (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
+ return writel(data, plat->ddr_sch + reg);
}
int match_ddr_conf(u32 ddr_conf)
@@ -83,37 +98,38 @@ int match_ddr_conf(u32 ddr_conf)
return 0;
}
-static int emif_clear(void)
+static int emif_clear(s
[U-Boot] [PATCH v4 0/3] Move Stratix 10 SDRAM driver to DM
Compile ALTERA_SDRAM driver in SPL only and move Stratix 10 SDRAM driver to DM.
v3 -> v4:
- Add CONFIG_SPL_ALTERA_SDRAM to config_whitelist.txt in patch [1/3] and remove
it in patch [3/3]
- Remove _remove().
- Update commit message in patch [2/3]
v2->v3:
---
- Compile ALTERA_SDRAM driver in SPL only
- Separate dts change to new patch
- Change to use #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
- Add _remove()
- Remove #ifdef CONFIG_SPL_BUILD checking in sdram_s10.c
History:
[v1]: https://patchwork.ozlabs.org/patch/1066765/
[v2]: https://patchwork.ozlabs.org/patch/1089957/
[v3]: https://patchwork.ozlabs.org/cover/1093091/
Ley Foon Tan (3):
ddr: altera: Compile ALTERA SDRAM in SPL only
arm: dts: Stratix10: Add SDRAM node
arm: socfpga: Move Stratix 10 SDRAM driver to DM
Makefile | 2 +-
arch/arm/dts/socfpga_stratix10.dtsi | 9 +
arch/arm/mach-socfpga/Kconfig | 4 +-
arch/arm/mach-socfpga/spl_s10.c | 16 +-
configs/socfpga_stratix10_defconfig | 1 +
drivers/Makefile | 2 +-
drivers/ddr/altera/Kconfig| 11 +-
drivers/ddr/altera/Makefile | 2 +-
drivers/ddr/altera/sdram_s10.c| 243 --
.../mach => drivers/ddr/altera}/sdram_s10.h | 4 -
include/configs/socfpga_stratix10_socdk.h | 5 -
11 files changed, 200 insertions(+), 99 deletions(-)
rename {arch/arm/mach-socfpga/include/mach => drivers/ddr/altera}/sdram_s10.h
(97%)
--
2.19.0
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Re: [U-Boot] [PATCH 1/1] arm: mvebu: Add CRS305-1G-4S board
Hi Luka,
On 02.05.19 18:35, Luka Kovacic wrote:
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some
of the
other simillar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently
retrieved
from the stock bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip support and
writing env to SPI flash.
arch/arm/dts: Remove unused parameters in DTS for crs305-1g-4s
arch/arm/mach-mvebu: Set the proper processor for crs305-1g-4s (98DX3236)
A few comments:
Could you please add the custodian / maintainer to Cc. In this case
of MVEBU platforms its me (get_maintainer can help). Also, you failed
to add a "Signed-off-by" tag to the patch. Its definitely needed to
add at least this tag from the patch author. And also please break
the lines at a reasonable size (e.g. 72 chars) in the commit text.
---
arch/arm/dts/Makefile | 3 +-
.../dts/armada-xp-crs305-1g-4s-u-boot.dtsi| 13 +++
arch/arm/dts/armada-xp-crs305-1g-4s.dts | 110 ++
arch/arm/mach-mvebu/Kconfig | 7 ++
board/mikrotik/crs305-1g-4s/.gitignore| 1 +
board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 ++
board/mikrotik/crs305-1g-4s/Makefile | 14 +++
board/mikrotik/crs305-1g-4s/README| 23
board/mikrotik/crs305-1g-4s/binary.0 | 11 ++
board/mikrotik/crs305-1g-4s/crs305-1g-4s.c| 68 +++
board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 ++
configs/crs305-1g-4s_defconfig| 51
include/configs/crs305-1g-4s.h| 37 ++
13 files changed, 356 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s.dts
create mode 100644 board/mikrotik/crs305-1g-4s/.gitignore
create mode 100644 board/mikrotik/crs305-1g-4s/MAINTAINERS
create mode 100644 board/mikrotik/crs305-1g-4s/Makefile
create mode 100644 board/mikrotik/crs305-1g-4s/README
create mode 100644 board/mikrotik/crs305-1g-4s/binary.0
create mode 100644 board/mikrotik/crs305-1g-4s/crs305-1g-4s.c
create mode 100644 board/mikrotik/crs305-1g-4s/kwbimage.cfg.in
create mode 100644 configs/crs305-1g-4s_defconfig
create mode 100644 include/configs/crs305-1g-4s.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02958..f463485149 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -161,7 +161,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
- armada-xp-db-xc3-24g4xg.dtb
+ armada-xp-db-xc3-24g4xg.dtb \
+ armada-xp-crs305-1g-4s.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
new file mode 100644
index 00..8576a02730
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&spi0 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s.dts
b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
new file mode 100644
index 00..1116f5c96c
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CRS305-1G-4S board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf100 (instead of the default
+ * 0xd000). The 0xf100 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3236.dtsi"
+#include "armada-xp-crs305-1g-4s-u-boot.dtsi"
+
+/ {
+ model = "CRS305-1G-4S";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260",
"marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x 0 0x2000>; /* 512 MB */
+ };
+};
+
+&L2 {
+ arm,parity-enable;
+ ma
Re: [U-Boot] [PATCH u-boot-marvell v3 14/17] arm: mvebu: turris_omnia: add RESET button handling
On 02.05.19 16:53, Marek Behún wrote: There is a Factory RESET button on the back side of the Turris Omnia router. When user presses this button before powering the device up and keeps it pressed, the microcontroller prevents the main CPU from booting and counts how long the RESET button is being pressed (and indicates this by lighting up front LEDs). The idea behind this is that the user can boot the device into several Factory RESET modes. This patch adds support for U-Boot to read into which Factory RESET mode the user booted the device. The value is an integer stored into the omnia_reset environment variable. It is 0 if the button was not pressed at all during power up, otherwise it is the number identifying the Factory RESET mode. This patch also changes bootcmd to a special hardcoded value if Factory RESET button was pressed during device powerup. This special bootcmd value sets the colors of all the LEDs on the front panel to green and then tries to load the rescue image from the SPI flash memory and boot it. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Pull request for UEFI sub-system for v2019.07-rc2
The following changes since commit b4ee6daad7a2604ca9466b2ba48de86cc27d381f: Merge tag 'u-boot-imx-20190426' of git://git.denx.de/u-boot-imx (2019-05-01 07:25:51 -0400) are available in the Git repository at: git://git.denx.de/u-boot-efi.git tags/efi-2019-07-rc2 for you to fetch changes up to 4ccf678f37731d8ec09eae8dca5f4cbe84132a52: lib: uuid: Fix unseeded PRNG on RANDOM_UUID=y (2019-05-02 18:17:50 +0200) Pull request for UEFI sub-system for v2019.07-rc2 This pull request provides error fixes for the handling of GPT partitions and for the UEFI subsystem. Travis CI showed no errors: https://travis-ci.org/xypron2/u-boot/builds/527383078 Primary key fingerprint: 6DC4 F9C7 1F29 A6FA 06B7 6D33 C481 DBBC 2C05 1AC4 AKASHI Takahiro (2): efi_loader: set OsIndicationsSupported at init cmd: efidebug: rework "boot dump" sub-command using GetNextVariableName() Eugeniu Rosca (4): disk: efi: Fix memory leak on 'gpt guid' disk: efi: Fix memory leak on 'gpt verify' cmd: gpt: fix and tidy up help message lib: uuid: Fix unseeded PRNG on RANDOM_UUID=y Heinrich Schuchardt (7): efi_loader: parameter check CreateEventEx() efi_loader: FreePages() must fail with pages = 0 efi_loader: optional data in load options are binary efi_loader: memory leak in append value efi_loader: implement support of exit data efi_selftest: test exit_data efi_loader: description of efi_add_handle() cmd/bootefi.c | 15 ++-- cmd/efidebug.c | 106 cmd/gpt.c | 12 +-- cmd/nvedit_efi.c| 5 +- disk/part_efi.c | 6 ++ include/efi_loader.h| 7 +- include/efi_selftest.h | 2 +- lib/efi_loader/efi_bootmgr.c| 15 ++-- lib/efi_loader/efi_boottime.c | 57 - lib/efi_loader/efi_memory.c | 2 +- lib/efi_loader/efi_setup.c | 11 +++ lib/efi_selftest/efi_selftest_miniapp_exit.c| 17 ++-- lib/efi_selftest/efi_selftest_startimage_exit.c | 15 +++- lib/uuid.c | 2 + 14 files changed, 204 insertions(+), 68 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot-marvell v3 16/17] arm: mvebu: turris_omnia: add GPIO support to defconfig
On 02.05.19 16:53, Marek Behún wrote: Add support for the gpio command and driver for the I2C connected pca9538 controller, to be able to determine if SFP module is present in the Turris Omnia router. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot-marvell v3 17/17] arm: mvebu: turris_omnia: enable defconfig options needed by vendor
On 02.05.19 16:53, Marek Behún wrote: This options will be enabled by default by CZ.NIC shipped U-Boot. Enable them in defconfig. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 2/2] sunxi: Enable EMAC on the Bananapi M3
From: Chen-Yu Tsai The Bananapi M3 has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DCDC1 through SW @ 3.3V. The board is designed to use 3.3V with RGMII, instead of the standard reduced voltage of 2.5V we see everywhere. DLDO3, which provides the I/O voltages, is raised to match. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai --- Changes in v3: - Rebased on sunxi/master Changes in v2: - Dropped clk/reset related changes in favor of DM CLK / RESET support - Raised DLDO3 for RGMII I/O on Bananapi M3 to 3.3V per design configs/Sinovoip_BPI_M3_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 79743a9c9a51..b9ab00cb8a29 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -21,8 +21,10 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-bananapi-m3" +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DCDC5_VOLT=1200 -CONFIG_AXP_DLDO3_VOLT=2500 +CONFIG_AXP_DLDO3_VOLT=3300 CONFIG_AXP_SW_ON=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 0/2] sunxi: Enable EMAC on A83T boards using Realtek RTL8211E PHY
From: Chen-Yu Tsai Hi everyone, This series enables EMAC (Ethernet controller) on two A83T boards, the Cubietruck Plus and Bananapi M3. This series is now based on sunxi/next, which has patches that convert sun8i-emac to use the common CLK and DM_RESET framework. The two patches enable the sun8i-emac and Realtek PHY driver in their respective defconfigs. The device trees already have the EMAC enabled. For the Bananapi M3, the regulator providing the I/O voltages is raised to 3.3V. This was tested with the "dhcp" command followed by using the "ping" command to ping an external IP, in this case 8.8.8.8. Regards ChenYu Changes in v3: - Rebased on sunxi/master Changes in v2: - Dropped clk/reset related changes in favor of DM CLK / RESET support - Raised DLDO3 for RGMII I/O on Bananapi M3 to 3.3V per design Chen-Yu Tsai (2): sunxi: Enable EMAC on the Cubietruck Plus sunxi: Enable EMAC on the Bananapi M3 configs/Cubietruck_plus_defconfig | 2 ++ configs/Sinovoip_BPI_M3_defconfig | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/2] sunxi: Enable EMAC on the Cubietruck Plus
From: Chen-Yu Tsai The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are powered by DLDO3 @ 2.5V. This patch enables the EMAC and Realtek PHY drivers in the defconfig. The device tree file already has the EMAC enabled. Signed-off-by: Chen-Yu Tsai --- Changes in v3: None Changes in v2: None configs/Cubietruck_plus_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 869bffcfca0c..044af12779c6 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -20,6 +20,8 @@ CONFIG_CONSOLE_MUX=y # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_SPL_EFI_PARTITION is not set CONFIG_DEFAULT_DEVICE_TREE="sun8i-a83t-cubietruck-plus" +CONFIG_PHY_REALTEK=y +CONFIG_SUN8I_EMAC=y CONFIG_AXP_DLDO3_VOLT=2500 CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_AXP_FLDO1_VOLT=1200 -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] Raspberry Pi's MAC address locked to the first device the SD card boots on
We've had a problem the past few days that we've traced back to U-Boot. We're generating images using Yocto with Mender's update routine. The issue is the first time a clean image is booted on a Raspberry Pi, the mac address gets permanently saved to the ethaddr env variable. It's a combination of this line: https://github.com/u-boot/u-boot/blob/b4ee6daad7a2604ca9466b2ba48de86cc27d381f/board/raspberrypi/rpi/rpi.c#L348 and what I'm pretty sure is Mender doing a "saveenv" on first boot. If you move the SD card to a different Raspberry Pi, it will boot up with the mac address of the first Raspberry Pi. I'm not sure what the best long-term solution will be but I can make a patch for my purposes to just always set ethaddr to usbethaddr. So I guess i'm emailing this in to report an issue and maybe help anyone else who runs into this issue. -- Tim Froehlich Embedded Linux Engineer tfroehl...@archsys.io 215-218-8955 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] board/BuR/zynq/brsmarc2: initial commit
On Thu, May 02, 2019 at 08:34:32PM +0200, Hannes Schmelzer wrote:
>
> On 5/2/19 6:06 PM, Michal Simek wrote:
> >Hi,
> Hi Michal,
> >On 02. 05. 19 5:14, Hannes Schmelzer wrote:
> >>diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> >>index dfa5b02..2b00129 100644
> >>--- a/arch/arm/dts/Makefile
> >>+++ b/arch/arm/dts/Makefile
> >>@@ -208,6 +208,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> >>zynq-zc770-xm011-x16.dtb \
> >>zynq-zc770-xm012.dtb \
> >>zynq-zc770-xm013.dtb \
> >>+ zynq-brsmarc2.dtb \
> >>+ zynq-brsmarc2_r512.dtb \
> >Can't you detect it if you have 512M version?
> >u-boot itself has code for these kind of detection.
> >
> >long get_ram_size(long *base, long maxsize)
> I actually think not,
> because i need different ps7_init stuff for the two different RAM chips.
> (timing, adress lines, ...) But i will check if i even can drop the two
> different dts files.
> >
> >>+/ {
> >>+ model = "BRSMARC2 Zynq SoM";
> >>+ compatible = "xlnx,zynq-7000";
> >>+
> >>+ fset: factory-settings {
> >>+ bl-version = "";
> >>+ order-no= "";
> >>+ cpu-order-no= "";
> >>+ hw-revision = "";
> >>+ serial-no = <0>;
> >>+ device-id = <0x0>;
> >>+ parent-id = <0x0>;
> >>+ hw-variant = <0x0>;
> >>+ hw-platform = <0x0>;
> >>+ fram-offset = <0x0>;
> >>+ fram-size = <0x0>;
> >>+ cache-disable = <0x0>;
> >>+ cpu-clock = <0x0>;
> >>+ };
> >What's this? No compatible string. This looks quite hacky.
> This are factory settings, used by the OS (in this case vxWorks),
> to identify on which hardware it runs, and have per device unique stuff
> (serial number).
> But you're right, it would be nice to have here some compatible string,
> i will change this. Today we just search for the node "factory-setting".
> A more comfortable ways would be vxFdtNodeOffsetByCompatible()
> >
> >>+
> >>+ aliases {
> >>+ ethernet0 = &gem0;
> >>+ ethernet1 = &gem1;
> >>+ i2c0 = &i2c0;
> >>+ serial0 = &uart0;
> >>+ spi0 = &qspi;
> >>+ mmc0 = &sdhci0;
> >>+ fset = &fset;
> >>+ can0 = &can0;
> >>+ can1 = &can1;
> >>+ };
> >>+
> >>+ memory {
> >>+ device_type = "memory";
> >>+ reg = <0x0 0x1000>;
> >>+ };
> >>+
> >>+ board {
> >>+ status = "okay";
> >>+ compatible = "bur,brsmarc2-som";
> >>+ usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
> >>+ usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>;
> >>+ powerdown-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
> >>+ reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
> >>+ };
> >Where is mainline dt binding for this?
> Nowhere, because u-boot nor linux does use this,
> this is only for the vxWorks OS.
This is what I kinda figured was the case. We now have some interesting
times ahead of us as yes, we normally think about DTS reviews in terms
of Linux. But this is all for a board that uses vxWorks. Perhaps the
best thing to do here is note (and for all of the other boards too, but
you can wait for general feedback before v3'ing them all) in the dts
comment that it's for vxWorks as people tend to assume a DTS file is for
Linux (even with many counter examples).
[snip]
> >>+ uart5: serial@40200A00 {
> >>+ status = "disabled";
> >>+ compatible = "ns16550a", "bur,DdVxSf16x5xIO";
> >>+ bur,hwtree = "IF21";
> >>+ reg = <0x40200A00 0x40>;
> >>+ interrupt-parent = <&intc>;
> >>+ interrupts = <0 90 4>;
> >>+ };
> >all these PL stuff can't go to mainline.
> Please explain me the reason why this PL stuff cannot go mainline?
> Maybe a solution cold be to drop those in the mainline dts and then
> patch it again into it on the local branch. But that would be a way which
> i don't prefer.
So, now that we're clear this is for vxWorks, "PL stuff" ? The only
thing I see here that's not spelled out (but based on cursory
examination of the kernel, implied as normal) is interrupt-parent as a
property.
> >>+&gem0 {
> >>+ status = "okay";
> >>+ phy-mode = "rgmii-id";
> >>+ phy-handle = <ðernet_phy0>;
> >>+ mac-address = [ 00 00 00 00 00 00 ];
> >0 mac is wrong.
> No, this zeros are placeholder.
> The real MAC-Adresses are get into the dts during u-boot's fdt_fixup(...).
> They come from environment, and th environment is setup from some
> u-boot script.
But we shouldn't need the node here to set the property is I think the
point.
[snip]
> >>+"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
> >>+"dtbaddr=0x400\0" \
> >>+"loadaddr=0x200\0" \
> >>+"fpgaaddr=fdt get value fpgabase /fp
Re: [U-Boot] [PATCH v2] board/BuR/zynq/brsmarc2: initial commit
On 5/2/19 6:06 PM, Michal Simek wrote:
Hi,
Hi Michal,
On 02. 05. 19 5:14, Hannes Schmelzer wrote:
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02..2b00129 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -208,6 +208,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm011-x16.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brsmarc2_r512.dtb \
Can't you detect it if you have 512M version?
u-boot itself has code for these kind of detection.
long get_ram_size(long *base, long maxsize)
I actually think not,
because i need different ps7_init stuff for the two different RAM chips.
(timing, adress lines, ...) But i will check if i even can drop the two
different dts files.
+/ {
+ model = "BRSMARC2 Zynq SoM";
+ compatible = "xlnx,zynq-7000";
+
+ fset: factory-settings {
+ bl-version = "";
+ order-no= "";
+ cpu-order-no= "";
+ hw-revision = "";
+ serial-no = <0>;
+ device-id = <0x0>;
+ parent-id = <0x0>;
+ hw-variant = <0x0>;
+ hw-platform = <0x0>;
+ fram-offset = <0x0>;
+ fram-size = <0x0>;
+ cache-disable = <0x0>;
+ cpu-clock = <0x0>;
+ };
What's this? No compatible string. This looks quite hacky.
This are factory settings, used by the OS (in this case vxWorks),
to identify on which hardware it runs, and have per device unique stuff
(serial number).
But you're right, it would be nice to have here some compatible string,
i will change this. Today we just search for the node "factory-setting".
A more comfortable ways would be vxFdtNodeOffsetByCompatible()
+
+ aliases {
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ fset = &fset;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x1000>;
+ };
+
+ board {
+ status = "okay";
+ compatible = "bur,brsmarc2-som";
+ usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
+ usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+ };
Where is mainline dt binding for this?
Nowhere, because u-boot nor linux does use this,
this is only for the vxWorks OS.
+
+ fpga: fpga@4000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ compatible = "bur,zynqPL", "simple-bus";
is bur even recoreded for your company.
No think not, i didn't know so far that this is necessary.
But this is a very good input. Can you give me some hint where i have to
go for it?
compatible is wrong.
No, compatible is correct. Because i have my own (bur,) zynqPL driver in
vxWorks
to handle the FPGA stuff.
+ reg = <0x4020 0x1/* version registers */
+ 0x4024 0x1>; /* misc registers */
+ bur,upddest = &spi_flash;
+ bur,updaddr = <0x10>;
+ bur,updsize = <0x20>;
likely undocumented
Right, actually i have no real good documentation along the source of
the opposite.
The vxWorks driver who handles update in flash.
+
+ plk: plk@8000 {
+ status = "disabled";
+ compatible = "bur,DdVxIoEplSMP";
ditto
+ bur,hwtree = "IF9";
+ reg = <0x8000 0x8000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 68 4>,
+<0 84 4>;
+ local-mac-address = [ 00 60 65 aa ab ac ];
+ };
+
+ x2x: x2x@4010 {
+ status = "disabled";
+ compatible = "bur,xlk";
ditoo.
+ bur,hwtree = "IF10";
+ reg = <0x4010 0x8000
+ 0x40108000 0x8000>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 65 4>;
+ };
+
+ uart2: serial@40200800 {
+ status = "disabled";
+ compatible = "ns16550a", "bur,DdVxSf16x5xIO";
+ bur,hwtree = "IF8";
+ reg = <0x40200800 0x40>;
+
[U-Boot] [PATCH v2 2/3] Remove fit-dtb.blob* in clean target.
Support for compressed fit-dtb.blob was added in:
commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
U-Boot")
Adjust Makefile to also clean compressed blobs.
Signed-off-by: Vagrant Cascadian
---
Changes in v2:
- Mention commit where compressed fit-dtb.blob were introduced.
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index d6a6ef19ab..68f2327bea 100644
--- a/Makefile
+++ b/Makefile
@@ -1779,7 +1779,7 @@ CLEAN_DIRS += $(MODVERDIR) \
$(filter-out include, $(shell ls -1 $d 2>/dev/null
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- boot* u-boot* MLO* SPL System.map fit-dtb.blob
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob*
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
--
2.20.1
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[U-Boot] [PATCH v2 3/3] Set time and umask on fit-dtb.blob to ensure reproducibile builds.
Support for compressed fit-dtb.blob was added in:
commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
U-Boot")
When building compressed (lzop, gzip) fit-dtb.blob images, the
compression tool may embed the time or umask in the image.
Work around this by manually setting the time of the source file using
SOURCE_DATE_EPOCH and a hard-coded 0600 umask.
With gzip, this could be accomplished by using -n/--no-name, but lzop
has no current workaround:
https://bugs.debian.org/896520
This is essentially the same fix applied to multi-dtb fit SPL images in:
commit 8664ab7debab ("Set time and umask on multi-dtb fit images to
ensure reproducibile builds.")
Signed-off-by: Vagrant Cascadian
---
Changes in v2:
- Add reference to similar fix in multi-dtb fit SPL images
- Mention commit where compressed fit-dtb.blob were introduced.
Makefile | 4
1 file changed, 4 insertions(+)
diff --git a/Makefile b/Makefile
index 68f2327bea..cff5ea4c5f 100644
--- a/Makefile
+++ b/Makefile
@@ -1047,6 +1047,10 @@ fit-dtb.blob.lzo: fit-dtb.blob
fit-dtb.blob: dts/dt.dtb FORCE
$(call if_changed,mkimage)
+ifneq ($(SOURCE_DATE_EPOCH),)
+ touch -d @$(SOURCE_DATE_EPOCH) fit-dtb.blob
+ chmod 0600 fit-dtb.blob
+endif
MKIMAGEFLAGS_fit-dtb.blob = -f auto -A $(ARCH) -T firmware -C none -O u-boot \
-a 0 -e 0 -E \
--
2.20.1
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[U-Boot] [PATCH v2 0/3] Tidy up support for compressed fit-dtb.blob.
Support for compressed fit-dtb.blob was added in:
commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
U-Boot")
This introduces reproducibility issues as the timestamp and umask may
be embedded in the output when using gzip, lzop or possibly other
compression tools if added later. The included patch works around this
by setting the date and umask on the file when SOURCE_DATE_EPOCH is
set.
This is essentially the same fix applied to multi-dtb fit SPL images in:
commit 8664ab7debab ("Set time and umask on multi-dtb fit images to
ensure reproducibile builds.")
The compressed files were not added to gitignore or the clean targets,
and the other two patches in this series adds them.
Changes in v2:
- Mention commit where compressed fit-dtb.blob were introduced.
- Mention commit where compressed fit-dtb.blob were introduced.
- Add reference to similar fix in multi-dtb fit SPL images
- Mention commit where compressed fit-dtb.blob were introduced.
Vagrant Cascadian (3):
Add fit-dtb.blob* to .gitignore.
Remove fit-dtb.blob* in clean target.
Set time and umask on fit-dtb.blob to ensure reproducibile builds.
.gitignore | 2 +-
Makefile | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
--
2.20.1
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[U-Boot] [PATCH v2 1/3] Add fit-dtb.blob* to .gitignore.
Support for compressed fit-dtb.blob was added in:
commit 95f4bbd581cf ("lib: fdt: Allow LZO and GZIP DT compression in
U-Boot")
Adjust .gitignore to also exclude compressed blobs.
Signed-off-by: Vagrant Cascadian
---
Changes in v2:
- Mention commit where compressed fit-dtb.blob were introduced.
.gitignore | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.gitignore b/.gitignore
index c2afcfbca2..d8b7b77844 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,7 +35,7 @@
#
# Top-level generic files
#
-fit-dtb.blob
+fit-dtb.blob*
/MLO*
/SPL*
/System.map
--
2.20.1
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[U-Boot] [BUG] Linux kernel oops when booting from U-Boot via GRUB-EFI on qemu-x86_defconfig
Today I tried to boot Debian Buster on qemu-x86_defconfig via GRUB-efi and got an oops in drivers/firmware/efi/runtime-wrappers.c when trying to enter SetVariable(). Did this ever work? [0.210599] Calibrating delay loop (skipped) preset value.. 3992.42 BogoMIPS (lpj=7984856) [0.211971] pid_max: default: 32768 minimum: 301 [0.212950] BUG: unable to handle kernel paging request at bff585b8 [0.214101] *pdpt = *pde = 024608c0 [0.214591] Oops: [#1] SMP NOPTI [0.214591] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.19.0-4-686-pae #1 Debian 4.19.28-2 [0.214591] Hardware name: emulation qemu-x86/qemu-x86, BIOS 2019.07-rc1-00108-g97105c097a-dirty 05/02/2019 [0.214591] EIP: virt_efi_set_variable_nonblocking+0x56/0xb0 [0.214591] Code: 8b 15 4c 56 a4 d8 83 c8 01 b9 48 00 00 00 90 90 ff 15 fc 56 8b d8 89 45 f0 a1 a0 47 94 d8 8b 40 38 ff 75 0c ff 75 08 57 56 53 <8b> 40 38 e8 5a e4 16 0f [0.214591] EAX: bff58580 EBX: d86989b8 ECX: 0048 EDX: [0.214591] ESI: d88a3f30 EDI: 0007 EBP: d88a3f20 ESP: d88a3efc [0.214591] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210202 [0.214591] CR0: 80050033 CR2: bff585b8 CR3: 18a3c000 CR4: 06b0 [0.214591] Call Trace: [0.214591] ? virt_efi_reset_system+0xa0/0xa0 [0.214591] efi_delete_dummy_variable+0x4f/0x70 [0.214591] efi_enter_virtual_mode+0x455/0x462 [0.214591] start_kernel+0x3c5/0x45f [0.214591] i386_start_kernel+0xac/0xb0 [0.214591] startup_32_smp+0x164/0x168 [0.214591] Modules linked in: [0.214591] CR2: bff585b8 [0.214591] ---[ end trace be120570f6f2d3a7 ]--- [0.214591] EIP: virt_efi_set_variable_nonblocking+0x56/0xb0 [0.214591] Code: 8b 15 4c 56 a4 d8 83 c8 01 b9 48 00 00 00 90 90 ff 15 fc 56 8b d8 89 45 f0 a1 a0 47 94 d8 8b 40 38 ff 75 0c ff 75 08 57 56 53 <8b> 40 38 e8 5a e4 16 0f [0.214591] EAX: bff58580 EBX: d86989b8 ECX: 0048 EDX: [0.214591] ESI: d88a3f30 EDI: 0007 EBP: d88a3f20 ESP: d8a43dfc [0.214591] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068 EFLAGS: 00210202 [0.214591] CR0: 80050033 CR2: bff585b8 CR3: 18a3c000 CR4: 06b0 [0.214591] Kernel panic - not syncing: Attempted to kill the idle task! [0.214591] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Best regards Heinrich ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 0/1] [RESEND] Add MikroTik CRS305-1G-4S+IN board support
This patch adds support for the MikroTik CRS305-1G-4S+IN switch. CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some of the other simillar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently retrieved from the stock bootloader and compiled into the kwb image. The board has 4x SFP+ cages, Gigabit Ethernet (AR8033 PHY), 16 MB SPI flash (Winbond) and UART. This port currently supports booting from UART using kwboot and SPI flash, saving the environment to the SPI flash and loading the kernel from the SPI flash. I am planning to add Gigabit Ethernet support later, in a new set of patches. Luka Kovacic (1): arm: mvebu: Add CRS305-1G-4S board arch/arm/dts/Makefile | 3 +- .../dts/armada-xp-crs305-1g-4s-u-boot.dtsi| 13 +++ arch/arm/dts/armada-xp-crs305-1g-4s.dts | 110 ++ arch/arm/mach-mvebu/Kconfig | 7 ++ board/mikrotik/crs305-1g-4s/.gitignore| 1 + board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 ++ board/mikrotik/crs305-1g-4s/Makefile | 14 +++ board/mikrotik/crs305-1g-4s/README| 23 board/mikrotik/crs305-1g-4s/binary.0 | 11 ++ board/mikrotik/crs305-1g-4s/crs305-1g-4s.c| 68 +++ board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 ++ configs/crs305-1g-4s_defconfig| 51 include/configs/crs305-1g-4s.h| 37 ++ 13 files changed, 356 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s.dts create mode 100644 board/mikrotik/crs305-1g-4s/.gitignore create mode 100644 board/mikrotik/crs305-1g-4s/MAINTAINERS create mode 100644 board/mikrotik/crs305-1g-4s/Makefile create mode 100644 board/mikrotik/crs305-1g-4s/README create mode 100644 board/mikrotik/crs305-1g-4s/binary.0 create mode 100644 board/mikrotik/crs305-1g-4s/crs305-1g-4s.c create mode 100644 board/mikrotik/crs305-1g-4s/kwbimage.cfg.in create mode 100644 configs/crs305-1g-4s_defconfig create mode 100644 include/configs/crs305-1g-4s.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] [RESEND] arm: mvebu: Add CRS305-1G-4S board
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some
of the
other simillar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently
retrieved
from the stock bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip support and
writing env to SPI flash.
arch/arm/dts: Remove unused parameters in DTS for crs305-1g-4s
arch/arm/mach-mvebu: Set the proper processor for crs305-1g-4s (98DX3236)
Signed-off-by: Luka Kovacic
---
arch/arm/dts/Makefile | 3 +-
.../dts/armada-xp-crs305-1g-4s-u-boot.dtsi| 13 +++
arch/arm/dts/armada-xp-crs305-1g-4s.dts | 110 ++
arch/arm/mach-mvebu/Kconfig | 7 ++
board/mikrotik/crs305-1g-4s/.gitignore| 1 +
board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 ++
board/mikrotik/crs305-1g-4s/Makefile | 14 +++
board/mikrotik/crs305-1g-4s/README| 23
board/mikrotik/crs305-1g-4s/binary.0 | 11 ++
board/mikrotik/crs305-1g-4s/crs305-1g-4s.c| 68 +++
board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 ++
configs/crs305-1g-4s_defconfig| 51
include/configs/crs305-1g-4s.h| 37 ++
13 files changed, 356 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s.dts
create mode 100644 board/mikrotik/crs305-1g-4s/.gitignore
create mode 100644 board/mikrotik/crs305-1g-4s/MAINTAINERS
create mode 100644 board/mikrotik/crs305-1g-4s/Makefile
create mode 100644 board/mikrotik/crs305-1g-4s/README
create mode 100644 board/mikrotik/crs305-1g-4s/binary.0
create mode 100644 board/mikrotik/crs305-1g-4s/crs305-1g-4s.c
create mode 100644 board/mikrotik/crs305-1g-4s/kwbimage.cfg.in
create mode 100644 configs/crs305-1g-4s_defconfig
create mode 100644 include/configs/crs305-1g-4s.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02958..f463485149 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -161,7 +161,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
- armada-xp-db-xc3-24g4xg.dtb
+ armada-xp-db-xc3-24g4xg.dtb \
+ armada-xp-crs305-1g-4s.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
new file mode 100644
index 00..8576a02730
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&spi0 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s.dts
b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
new file mode 100644
index 00..1116f5c96c
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CRS305-1G-4S board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf100 (instead of the default
+ * 0xd000). The 0xf100 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3236.dtsi"
+#include "armada-xp-crs305-1g-4s-u-boot.dtsi"
+
+/ {
+ model = "CRS305-1G-4S";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260",
"marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x 0 0x2000>; /* 512 MB */
+ };
+};
+
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width= <16>;
+ devbus,turn-off-ps = <6>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
Re: [U-Boot] [PATCH 1/3] Add fit-dtb.blob* to .gitignore to also exclude compressed blobs.
On 2019-05-02, Marek Vasut wrote: > On 5/2/19 2:42 AM, Vagrant Cascadian wrote: >> Signed-off-by: Vagrant Cascadian >> --- > > Commit message is missing on this and 2/3 patch , otherwise the series > looks good, thanks. I'm not sure what more to add that isn't already in the subject line... should I break it up into two lines: Add fit-dtb.blob* to .gitignore. Also excludes compressed blobs. ? I guess I could also mention the commit where compressed blobs were introduced... that would drag it out a bit longer. Thanks! live well, vagrant >> .gitignore | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/.gitignore b/.gitignore >> index c2afcfbca2..d8b7b77844 100644 >> --- a/.gitignore >> +++ b/.gitignore >> @@ -35,7 +35,7 @@ >> # >> # Top-level generic files >> # >> -fit-dtb.blob >> +fit-dtb.blob* >> /MLO* >> /SPL* >> /System.map >> > > > -- > Best regards, > Marek Vasut signature.asc Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/1] arm: mvebu: Add CRS305-1G-4S board
CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some
of the
other simillar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently
retrieved
from the stock bootloader and compiled into the kwb image.
Adds support for U-Boot, enable UART, SPI, Winbond SPI flash chip support and
writing env to SPI flash.
arch/arm/dts: Remove unused parameters in DTS for crs305-1g-4s
arch/arm/mach-mvebu: Set the proper processor for crs305-1g-4s (98DX3236)
---
arch/arm/dts/Makefile | 3 +-
.../dts/armada-xp-crs305-1g-4s-u-boot.dtsi| 13 +++
arch/arm/dts/armada-xp-crs305-1g-4s.dts | 110 ++
arch/arm/mach-mvebu/Kconfig | 7 ++
board/mikrotik/crs305-1g-4s/.gitignore| 1 +
board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 ++
board/mikrotik/crs305-1g-4s/Makefile | 14 +++
board/mikrotik/crs305-1g-4s/README| 23
board/mikrotik/crs305-1g-4s/binary.0 | 11 ++
board/mikrotik/crs305-1g-4s/crs305-1g-4s.c| 68 +++
board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 ++
configs/crs305-1g-4s_defconfig| 51
include/configs/crs305-1g-4s.h| 37 ++
13 files changed, 356 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s.dts
create mode 100644 board/mikrotik/crs305-1g-4s/.gitignore
create mode 100644 board/mikrotik/crs305-1g-4s/MAINTAINERS
create mode 100644 board/mikrotik/crs305-1g-4s/Makefile
create mode 100644 board/mikrotik/crs305-1g-4s/README
create mode 100644 board/mikrotik/crs305-1g-4s/binary.0
create mode 100644 board/mikrotik/crs305-1g-4s/crs305-1g-4s.c
create mode 100644 board/mikrotik/crs305-1g-4s/kwbimage.cfg.in
create mode 100644 configs/crs305-1g-4s_defconfig
create mode 100644 include/configs/crs305-1g-4s.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02958..f463485149 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -161,7 +161,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-38x-controlcenterdc.dtb \
armada-385-atl-x530.dtb \
armada-385-atl-x530DP.dtb \
- armada-xp-db-xc3-24g4xg.dtb
+ armada-xp-db-xc3-24g4xg.dtb \
+ armada-xp-crs305-1g-4s.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
new file mode 100644
index 00..8576a02730
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&spi0 {
+ u-boot,dm-pre-reloc;
+
+ spi-flash@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
diff --git a/arch/arm/dts/armada-xp-crs305-1g-4s.dts
b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
new file mode 100644
index 00..1116f5c96c
--- /dev/null
+++ b/arch/arm/dts/armada-xp-crs305-1g-4s.dts
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for CRS305-1G-4S board
+ *
+ * Copyright (C) 2016 Allied Telesis Labs
+ *
+ * Based on armada-xp-db.dts
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf100 (instead of the default
+ * 0xd000). The 0xf100 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include "armada-xp-98dx3236.dtsi"
+#include "armada-xp-crs305-1g-4s-u-boot.dtsi"
+
+/ {
+ model = "CRS305-1G-4S";
+ compatible = "marvell,armadaxp-98dx3236", "marvell,armadaxp-mv78260",
"marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200 earlyprintk";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x 0 0x2000>; /* 512 MB */
+ };
+};
+
+&L2 {
+ arm,parity-enable;
+ marvell,ecc-enable;
+};
+
+&devbus_bootcs {
+ status = "okay";
+
+ /* Device Bus parameters are required */
+
+ /* Read parameters */
+ devbus,bus-width= <16>;
+ devbus,turn-off-ps = <6>;
+ devbus,badr-skew-ps = <0>;
+ devbus,acc-first-ps = <124000>;
+ devbus,acc-next-ps = <248000>;
+ devbus,rd-setup-ps = <0>;
+ devbus,rd-hold-ps = <0>;
+
+ /* Write parameters
[U-Boot] [PATCH 0/1] Add MikroTik CRS305-1G-4S+IN board support
This patch adds support for the MikroTik CRS305-1G-4S+IN switch. CRS305-1G-4S has a switch chip with an integrated CPU (98DX3236) and like some of the other simillar boards requires bin_hdr. bin_hdr (DDR3 init stage) is currently retrieved from the stock bootloader and compiled into the kwb image. The board has 4x SFP+ cages, Gigabit Ethernet (AR8033 PHY), 16 MB SPI flash (Winbond) and UART. This port currently supports booting from UART using kwboot and SPI flash, saving the environment to the SPI flash and loading the kernel from the SPI flash. I am planning to add Gigabit Ethernet support later, in a new set of patches. Luka Kovacic (1): arm: mvebu: Add CRS305-1G-4S board arch/arm/dts/Makefile | 3 +- .../dts/armada-xp-crs305-1g-4s-u-boot.dtsi| 13 +++ arch/arm/dts/armada-xp-crs305-1g-4s.dts | 110 ++ arch/arm/mach-mvebu/Kconfig | 7 ++ board/mikrotik/crs305-1g-4s/.gitignore| 1 + board/mikrotik/crs305-1g-4s/MAINTAINERS | 7 ++ board/mikrotik/crs305-1g-4s/Makefile | 14 +++ board/mikrotik/crs305-1g-4s/README| 23 board/mikrotik/crs305-1g-4s/binary.0 | 11 ++ board/mikrotik/crs305-1g-4s/crs305-1g-4s.c| 68 +++ board/mikrotik/crs305-1g-4s/kwbimage.cfg.in | 12 ++ configs/crs305-1g-4s_defconfig| 51 include/configs/crs305-1g-4s.h| 37 ++ 13 files changed, 356 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s-u-boot.dtsi create mode 100644 arch/arm/dts/armada-xp-crs305-1g-4s.dts create mode 100644 board/mikrotik/crs305-1g-4s/.gitignore create mode 100644 board/mikrotik/crs305-1g-4s/MAINTAINERS create mode 100644 board/mikrotik/crs305-1g-4s/Makefile create mode 100644 board/mikrotik/crs305-1g-4s/README create mode 100644 board/mikrotik/crs305-1g-4s/binary.0 create mode 100644 board/mikrotik/crs305-1g-4s/crs305-1g-4s.c create mode 100644 board/mikrotik/crs305-1g-4s/kwbimage.cfg.in create mode 100644 configs/crs305-1g-4s_defconfig create mode 100644 include/configs/crs305-1g-4s.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] Add fit-dtb.blob* to .gitignore to also exclude compressed blobs.
On 5/2/19 6:44 PM, Vagrant Cascadian wrote: > On 2019-05-02, Marek Vasut wrote: >> On 5/2/19 2:42 AM, Vagrant Cascadian wrote: >>> Signed-off-by: Vagrant Cascadian >>> --- >> >> Commit message is missing on this and 2/3 patch , otherwise the series >> looks good, thanks. > > I'm not sure what more to add that isn't already in the subject > line... should I break it up into two lines: > > Add fit-dtb.blob* to .gitignore. > > Also excludes compressed blobs. I think so ... and that it's the same you applied to the SPL part maybe ? -- Best regards, Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] WaRP7 nok on master
Hi Lukas, On Thu, May 2, 2019 at 1:58 PM Auer, Lukas wrote: > Yes, I will send a patch for this. Do you prefer setting the default > value for i.MX in one place (in arch/arm/mach-imx/Kconfig) or > individually for each sub-family (for example in arch/arm/mach- > imx/mx7/Kconfig for i.MX7)? I think we can set it in one place. Thanks ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] WaRP7 nok on master
Hi Fabio, On Thu, 2019-05-02 at 11:08 -0300, Fabio Estevam wrote: > Hi Lukas, > > On Thu, May 2, 2019 at 7:21 AM Auer, Lukas > wrote: > > > I was able to reproduce the issue on my side. With the patch, U-Boot > > probes the drivers for devices under simple-bus device tree nodes in > > the pre-relocation device model. The default value of > > CONFIG_SYS_MALLOC_LEN (0x400) leaves U-Boot with not enough memory to > > do this, causing it to hang. If it is increased, for example to 0x1000, > > everything works again. > > > > Let me know, how you want to fix this. If you want, I can send a patch > > to increase CONFIG_SYS_MALLOC_LEN for the i.MX parts. > > I guess you mean CONFIG_SYS_MALLOC_F_LEN instead? > Oops yes, that's what I meant. > Could you please send a patch setting CONFIG_SYS_MALLOC_F_LEN as > 0x2000 by default for i.MX? > > 0x1000 seems not to be enough: > http://git.denx.de/?p=u-boot.git;a=commitdiff;h=8b9cba0295dcdce5eb8bb10d79f6dafb5a167349;hp=b7de88cd5cb8c213fb158b37fcf0662c1d2332cd Yes, I will send a patch for this. Do you prefer setting the default value for i.MX in one place (in arch/arm/mach-imx/Kconfig) or individually for each sub-family (for example in arch/arm/mach- imx/mx7/Kconfig for i.MX7)? Thanks, Lukas ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 15/18] x86: Update the memory map a little
The memory map currently omits the environment and the MRC region. Add these in for completeness. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: None doc/README.x86 | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/README.x86 b/doc/README.x86 index d5224b75367..8e0a3f36edf 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -195,6 +195,8 @@ Flash map for samus / broadwell: ffedSYS_TEXT_BASE ffeaX86_REFCODE_ADDR ffe7SPL_TEXT_BASE + ffbf8000CONFIG_ENV_OFFSET (environemnt offset) + ffberw-mrc-cache (Memory-reference-code cache) ffa0 ff801000intel-me (address set by descriptor.bin) ff80intel-descriptor -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 49/50] x86: Add a way to jump from TPL to SPL
Hi Bin, On Wed, 1 May 2019 at 10:17, Bin Meng wrote: > > Hi Simon, > > On Fri, Apr 26, 2019 at 12:00 PM Simon Glass wrote: > > > > When TPL finishes it needs to jump to SPL with the stack set up correctly. > > Add a function to handle this. > > > > Signed-off-by: Simon Glass > > --- > > > > Changes in v2: > > - Add a new patch allowing jumping from TPL to SPL > > > > arch/x86/cpu/start.S | 13 + > > 1 file changed, 13 insertions(+) > > > > Reviewed-by: Bin Meng > > But I don't see any patch in this series that makes use of this new > jump_to_spl()? This is called from arch/x86/lib/tpl.c: x86: Add a simple TPL implementation Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 13/18] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. Unfortunately this has a dramatic impact on the pre-relocation memory used on x86 platforms (increasing it by 2KB) since it increases the overhead for each PCI device from 220 bytes to 412 bytes. The offending line is in UCLASS_DRIVER(pci): .per_device_auto_alloc_size = sizeof(struct pci_controller), This means that all PCI devices have the controller struct associated with them. The solution is to move the regions[] member out of the array, makes its size dynamic, or split UCLASS_PCI into controllers and non-controllers, as the comment suggests. For now, revert the commit to get things running again. Reviewed-by: Bin Meng Signed-off-by: Simon Glass --- Changes in v3: None Changes in v2: None include/pci.h | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/include/pci.h b/include/pci.h index 066238a9c3c..508f7bca81c 100644 --- a/include/pci.h +++ b/include/pci.h @@ -546,11 +546,7 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#ifdef CONFIG_NR_DRAM_BANKS -#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7) -#else -#define MAX_PCI_REGIONS 7 -#endif +#define MAX_PCI_REGIONS7 #define INDIRECT_TYPE_NO_PCIE_LINK 1 -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 18/18] x86: samus: Add a target to boot through TPL
Add a version of samus which supports booting from TPL to SPL and then to U-Boot. This allows TPL to select from an A or B SPL to support verified boot with field upgrade. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: - Sort defconfig and adjust it to build after rebase on maste board/google/Kconfig | 8 +++ board/google/chromebook_samus/Kconfig | 14 +++- board/google/chromebook_samus/MAINTAINERS | 7 ++ configs/chromebook_samus_tpl_defconfig| 82 +++ include/configs/chromebook_samus.h| 2 + 5 files changed, 111 insertions(+), 2 deletions(-) create mode 100644 configs/chromebook_samus_tpl_defconfig diff --git a/board/google/Kconfig b/board/google/Kconfig index d98a5e818fc..679a0f10239 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -52,6 +52,14 @@ config TARGET_CHROMEBOOK_SAMUS Chrome OS EC connected on LPC, and it provides a 2560x1700 high resolution touch-enabled LCD display. +config TARGET_CHROMEBOOK_SAMUS_TPL + bool "Chromebook samus booting from TPL" + help + This is a version of Samus which boots into TPL, then to SPL and + U-Boot proper. This is useful where verified boot must select + between different A/B versions of SPL/U-Boot, to allow upgrading of + almost all U-Boot code in the field. + endchoice source "board/google/chromebook_link/Kconfig" diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig index afbfe53deb4..90c23cba1be 100644 --- a/board/google/chromebook_samus/Kconfig +++ b/board/google/chromebook_samus/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_SAMUS +if TARGET_CHROMEBOOK_SAMUS || TARGET_CHROMEBOOK_SAMUS_TPL config SYS_BOARD default "chromebook_samus" @@ -10,7 +10,8 @@ config SYS_SOC default "broadwell" config SYS_CONFIG_NAME - default "chromebook_samus" + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS + default "chromebook_samus" if TARGET_CHROMEBOOK_SAMUS_TPL config SYS_TEXT_BASE default 0xffe0 @@ -39,3 +40,12 @@ config SYS_CAR_SIZE default 0x4 endif + +if TARGET_CHROMEBOOK_SAMUS_TPL + +config BOARD_SPECIFIC_OPTIONS_TPL # dummy + def_bool y + select SPL + select TPL + +endif diff --git a/board/google/chromebook_samus/MAINTAINERS b/board/google/chromebook_samus/MAINTAINERS index 5500e46b408..ca4b16500af 100644 --- a/board/google/chromebook_samus/MAINTAINERS +++ b/board/google/chromebook_samus/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_samus/ F: include/configs/chromebook_samus.h F: configs/chromebook_samus_defconfig + +CHROMEBOOK SAMUS TPL BOARD +M: Simon Glass +S: Maintained +F: board/google/chromebook_samus/ +F: include/configs/chromebook_samus.h +F: configs/chromebook_samus_tpl_defconfig diff --git a/configs/chromebook_samus_tpl_defconfig b/configs/chromebook_samus_tpl_defconfig new file mode 100644 index 000..6ebfaa83a19 --- /dev/null +++ b/configs/chromebook_samus_tpl_defconfig @@ -0,0 +1,82 @@ +CONFIG_X86=y +CONFIG_SYS_TEXT_BASE=0xffed +CONFIG_SYS_MALLOC_F_LEN=0x1a00 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_VENDOR_GOOGLE=y +CONFIG_TARGET_CHROMEBOOK_SAMUS_TPL=y +CONFIG_DEBUG_UART=y +CONFIG_HAVE_MRC=y +CONFIG_HAVE_REFCODE=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_MISC_INIT_R=y +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_LAST_STAGE_INIT=y +CONFIG_BLOBLIST=y +CONFIG_BLOBLIST_SIZE=0x1000 +CONFIG_BLOBLIST_ADDR=0xff7c +CONFIG_HANDOFF=y +CONFIG_SPL_TEXT_BASE=0xffe7 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI=y +CONFIG_SPL_PCH_SUPPORT=y +CONFIG_TPL_PCI=y +CONFIG_TPL_PCH_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_PART=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_CMD_SOUND=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MAC_PARTITION=y +# CONFIG_SPL_MAC_PARTITION is not set +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_ISO_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus" +# CONFIG_NET is not set +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_TPL_MISC=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SYS_NS16550=y +CONFIG_SOUND=y +CONFIG_SOUND_I8254=y +CONFIG_SOUND_RT5677=y +CONFIG
[U-Boot] [PATCH v3 14/18] x86: Enable the RTC on all boards
With the move to Kconfig this option should be set in Kconfig, not in the config header file. Move it. Signed-off-by: Simon Glass --- Changes in v3: - Drop unnecessary change to chromebook_link_defconfig Changes in v2: - Add new patch to enable the RTC in Kconfig arch/Kconfig | 1 + include/configs/x86-common.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/Kconfig b/arch/Kconfig index a1d1ac301d6..2a93b72dbc4 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -165,6 +165,7 @@ config X86 imply USB_ETHER_SMSC95XX imply USB_HOST_ETHER imply PCH + imply RTC_MC146818 # Thing to enable for when SPL/TPL are enabled: SPL imply SPL_DM diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 4180b25f977..7fcf76a6bf2 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -36,7 +36,6 @@ /*--- * Real Time Clock Configuration */ -#define CONFIG_RTC_MC146818 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 #define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 05/18] x86: sysreset: Implement the get_last() method
Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
drivers/sysreset/sysreset_x86.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index ca892b305e2..072f7948efa 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -98,6 +98,11 @@ static int x86_sysreset_request(struct udevice *dev, enum
sysreset_t type)
return -EINPROGRESS;
}
+static int x86_sysreset_get_last(struct udevice *dev)
+{
+ return SYSRESET_POWER;
+}
+
#ifdef CONFIG_EFI_LOADER
void __efi_runtime EFIAPI efi_reset_system(
enum efi_reset_type reset_type,
@@ -140,6 +145,7 @@ static const struct udevice_id x86_sysreset_ids[] = {
static struct sysreset_ops x86_sysreset_ops = {
.request = x86_sysreset_request,
+ .get_last = x86_sysreset_get_last,
};
U_BOOT_DRIVER(x86_sysreset) = {
--
2.21.0.1020.gf2820cf01a-goog
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Re: [U-Boot] [PATCH v2 05/50] cros_ec: Use a hyphen in the uclass name
Hi Bin,
On Wed, 1 May 2019 at 06:00, Bin Meng wrote:
>
> Hi Simon,
>
> On Fri, Apr 26, 2019 at 11:59 AM Simon Glass wrote:
> >
> > Device-tree rules require that aliases use a hyphen rather than a
> > underscore. Update the uclass name to fit with this.
> >
> > This allows device-tree aliases to be used to refer to cros-ec devices,
> > for example:
> >
> > aliases {
> > cros-ec0 = &ec;
> > cros-ec1 = &pd;
> > };
>
> Thanks for adding the explanation here. But I was wondering since this
> is required by DT rules for the aliases node, do we have to require
> all UCLASS_DRIVERs to have name with hyphen instead of underscore?
It might be good to have this rule, in case people want to use aliases.
Regards,
Simon
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[U-Boot] [PATCH v3 16/18] x86: broadwell: Update PCH to work in TPL
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Add a new patch to update PCH to work in TPL
arch/x86/cpu/broadwell/pch.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/broadwell/pch.c b/arch/x86/cpu/broadwell/pch.c
index e61efa7b16c..a48945adf11 100644
--- a/arch/x86/cpu/broadwell/pch.c
+++ b/arch/x86/cpu/broadwell/pch.c
@@ -599,10 +599,16 @@ static int broadwell_pch_init(struct udevice *dev)
static int broadwell_pch_probe(struct udevice *dev)
{
- if (!(gd->flags & GD_FLG_RELOC))
- return broadwell_pch_early_init(dev);
- else
+ if (CONFIG_IS_ENABLED(X86_32BIT_INIT)) {
+ if (!(gd->flags & GD_FLG_RELOC))
+ return broadwell_pch_early_init(dev);
+ else
+ return broadwell_pch_init(dev);
+ } else if (IS_ENABLED(CONFIG_SPL) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
return broadwell_pch_init(dev);
+ } else {
+ return 0;
+ }
}
static int broadwell_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
--
2.21.0.1020.gf2820cf01a-goog
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[U-Boot] [PATCH v3 12/18] x86: samus: Increase the pre-reloc memory again
This is again too small, so increase it slightly. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: None configs/chromebook_samus_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configs/chromebook_samus_defconfig b/configs/chromebook_samus_defconfig index d0749f14fc9..91d9fdf9615 100644 --- a/configs/chromebook_samus_defconfig +++ b/configs/chromebook_samus_defconfig @@ -1,6 +1,6 @@ CONFIG_X86=y CONFIG_SYS_TEXT_BASE=0xFFE0 -CONFIG_SYS_MALLOC_F_LEN=0x1c00 +CONFIG_SYS_MALLOC_F_LEN=0x1d00 CONFIG_NR_DRAM_BANKS=8 CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0x3f8 -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 07/18] x86: samus: Update device tree for SPL
Add tags to allow required nodes to be present in SPL / TPL. Also enable
the sysreset driver.
Signed-off-by: Simon Glass
---
Changes in v3:
- Remove unneeded pch-reset node
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 33 +++
1 file changed, 29 insertions(+), 4 deletions(-)
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index 35211ed81b1..33df0e1f718 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -17,6 +17,7 @@
spi0 = &spi;
usb0 = &usb_0;
usb1 = &usb_1;
+ cros-ec0 = &cros_ec;
};
config {
@@ -73,6 +74,7 @@
/* Put this first: it is the default */
gpio_unused: gpio-unused {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -80,6 +82,7 @@
};
gpio_acpi_sci: acpi-sci {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
invert;
@@ -87,6 +90,7 @@
};
gpio_acpi_smi: acpi-smi {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
invert;
@@ -94,12 +98,14 @@
};
gpio_input: gpio-input {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
};
gpio_input_invert: gpio-input-invert {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -107,9 +113,11 @@
};
gpio_native: gpio-native {
+ u-boot,dm-pre-reloc;
};
gpio_out_high: gpio-out-high {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
output-value = <1>;
@@ -118,6 +126,7 @@
};
gpio_out_low: gpio-out-low {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
output-value = <0>;
@@ -126,6 +135,7 @@
};
gpio_pirq: gpio-pirq {
+ u-boot,dm-pre-reloc;
mode-gpio;
direction = ;
owner = ;
@@ -133,6 +143,7 @@
};
soc_gpio@0 {
+ u-boot,dm-pre-reloc;
config =
<0 &gpio_unused 0>, /* unused */
<1 &gpio_unused 0>, /* unused */
@@ -250,8 +261,10 @@
spd {
#address-cells = <1>;
#size-cells = <0>;
+ u-boot,dm-pre-reloc;
samsung_4 {
reg = <6>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -291,6 +304,7 @@
* columns 10, density 4096 mb, x32
*/
reg = <8>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 11 05 0b
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -326,6 +340,7 @@
};
samsung_8 {
reg = <10>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -365,6 +380,7 @@
* columns 11, density 4096 mb, x16
*/
reg = <12>;
+ u-boot,dm-pre-reloc;
data = [91 20 f1 03 04 12 05 0a
03 11 01 08 0a 00 50 01
78 78 90 50 90 11 50 e0
@@ -404,6 +420,7 @@
[U-Boot] [PATCH v3 11/18] x86: Fix device-tree indentation
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/u-boot.dtsi | 147 +++
1 file changed, 73 insertions(+), 74 deletions(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 6b176339aed..daeb168b65f 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -23,42 +23,41 @@
#ifdef CONFIG_ROM_SIZE
&rom {
- filename = "u-boot.rom";
- end-at-4gb;
- sort-by-offset;
- pad-byte = <0xff>;
- size = ;
+ filename = "u-boot.rom";
+ end-at-4gb;
+ sort-by-offset;
+ pad-byte = <0xff>;
+ size = ;
#ifdef CONFIG_HAVE_INTEL_ME
- intel-descriptor {
- filename = CONFIG_FLASH_DESCRIPTOR_FILE;
- };
- intel-me {
- filename = CONFIG_INTEL_ME_FILE;
- };
+ intel-descriptor {
+ filename = CONFIG_FLASH_DESCRIPTOR_FILE;
+ };
+ intel-me {
+ filename = CONFIG_INTEL_ME_FILE;
+ };
#endif
#ifdef CONFIG_TPL
- u-boot-tpl-with-ucode-ptr {
- offset = ;
- };
- u-boot-tpl-dtb {
- };
- u-boot-spl {
- offset = ;
- };
- u-boot-spl-dtb {
- };
- u-boot {
- offset = ;
- };
+ u-boot-tpl-with-ucode-ptr {
+ offset = ;
+ };
+ u-boot-tpl-dtb {
+ };
+ u-boot-spl {
+ offset = ;
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot {
+ offset = ;
+ };
#elif defined(CONFIG_SPL)
- u-boot-spl-with-ucode-ptr {
- offset = ;
- };
-
- u-boot-dtb-with-ucode2 {
- type = "u-boot-dtb-with-ucode";
- };
- u-boot {
+ u-boot-spl-with-ucode-ptr {
+ offset = ;
+ };
+ u-boot-dtb-with-ucode2 {
+ type = "u-boot-dtb-with-ucode";
+ };
+ u-boot {
/*
* TODO(s...@chromium.org):
* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
@@ -68,67 +67,67 @@
* We need a better solution, perhaps a separate Kconfig.
*/
#if CONFIG_SYS_TEXT_BASE == 0x111
- offset = <0xfff0>;
+ offset = <0xfff0>;
#else
- offset = ;
+ offset = ;
#endif
- };
+ };
#else
- u-boot-with-ucode-ptr {
- offset = ;
- };
+ u-boot-with-ucode-ptr {
+ offset = ;
+ };
#endif
- u-boot-dtb-with-ucode {
- };
- u-boot-ucode {
- align = <16>;
- };
+ u-boot-dtb-with-ucode {
+ };
+ u-boot-ucode {
+ align = <16>;
+ };
#ifdef CONFIG_HAVE_MRC
- intel-mrc {
- offset = ;
- };
+ intel-mrc {
+ offset = ;
+ };
#endif
#ifdef CONFIG_HAVE_FSP
- intel-fsp {
- filename = CONFIG_FSP_FILE;
- offset = ;
- };
+ intel-fsp {
+ filename = CONFIG_FSP_FILE;
+ offset = ;
+ };
#endif
#ifdef CONFIG_HAVE_CMC
- intel-cmc {
- filename = CONFIG_CMC_FILE;
- offset = ;
- };
+ intel-cmc {
+ filename = CONFIG_CMC_FILE;
+ offset = ;
+ };
#endif
#ifdef CONFIG_HAVE_VGA_BIOS
- intel-vga {
- filename = CONFIG_VGA_BIOS_FILE;
- offset = ;
- };
+ intel-vga {
+ filename = CONFIG_VGA_BIOS_FILE;
+ offset = ;
+ };
#endif
#ifdef CONFIG_HAVE_VBT
- intel-vbt {
- filename = CONFIG_VBT_FILE;
- offset = ;
- };
+ intel-vbt {
+ filename = CONFIG_VBT_FILE;
+ offset = ;
+ };
#endif
#ifdef CONFIG_HAVE_REFCODE
- intel-refcode {
- offset = ;
- };
+ intel-refcode {
+ offset = ;
+ };
#endif
#ifdef CONFIG_TPL
- x86-start16-tpl {
- offset = ;
- };
+ x86-start16-tpl {
+ offset = ;
+ };
#elif defined(CONFIG_SPL)
- x86-start16-spl {
- offset = ;
- };
+ x86-st
[U-Boot] [PATCH v3 17/18] x86: Add a way to jump from TPL to SPL
When TPL finishes it needs to jump to SPL with the stack set up correctly. Add a function to handle this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: - Add a new patch allowing jumping from TPL to SPL arch/x86/cpu/start.S | 13 + 1 file changed, 13 insertions(+) diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 30fa7def464..4a82add76b7 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -190,6 +190,19 @@ board_init_f_r_trampoline: /* Re-enter U-Boot by calling board_init_f_r() */ callboard_init_f_r +#ifdef CONFIG_TPL +.globl jump_to_spl +.type jump_to_spl, @function +jump_to_spl: + /* Reset stack to the top of CAR space */ + movl$(CONFIG_SYS_CAR_ADDR + CONFIG_SYS_CAR_SIZE - 4), %esp +#ifdef CONFIG_DCACHE_RAM_MRC_VAR_SIZE + subl$CONFIG_DCACHE_RAM_MRC_VAR_SIZE, %esp +#endif + + jmp *%eax +#endif + die: hlt jmp die -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 08/18] x86: samus: Update device tree for verified boot
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/chromebook_samus.dts | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/x86/dts/chromebook_samus.dts
b/arch/x86/dts/chromebook_samus.dts
index 33df0e1f718..d6a1df63ece 100644
--- a/arch/x86/dts/chromebook_samus.dts
+++ b/arch/x86/dts/chromebook_samus.dts
@@ -9,6 +9,12 @@
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+#ifdef CONFIG_CHROMEOS
+#include "chromeos-x86.dtsi"
+#include "flashmap-x86-ro.dtsi"
+#include "flashmap-8mb-rw.dtsi"
+#endif
+
/ {
model = "Google Samus";
compatible = "google,samus", "intel,broadwell";
@@ -581,7 +587,7 @@
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
- spi-flash@0 {
+ fwstore_spi: spi-flash@0 {
u-boot,dm-pre-reloc;
#size-cells = <1>;
#address-cells = <1>;
@@ -670,6 +676,10 @@
u-boot,dm-pre-reloc;
reg = <0xfed4 0x5000>;
compatible = "infineon,slb9635lpc";
+ secdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,tpm-secdata";
+ };
};
microcode {
@@ -693,3 +703,13 @@
};
};
+
+&rtc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nvdata {
+ u-boot,dm-pre-reloc;
+ compatible = "google,cmos-nvdata";
+ reg = <0x26>;
+ };
+};
--
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[U-Boot] [PATCH v3 09/18] x86: Update device tree for TPL
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Add a comment about the hard-coded text base
arch/x86/dts/u-boot.dtsi | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 1050236330a..9cf733806a5 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -22,7 +22,21 @@
filename = CONFIG_INTEL_ME_FILE;
};
#endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+ u-boot-tpl-with-ucode-ptr {
+ offset = ;
+ };
+ u-boot-tpl-dtb {
+ };
+ u-boot-spl {
+ offset = ;
+ };
+ u-boot-spl-dtb {
+ };
+ u-boot {
+ offset = ;
+ };
+#elif defined(CONFIG_SPL)
u-boot-spl-with-ucode-ptr {
offset = ;
};
@@ -31,7 +45,19 @@
type = "u-boot-dtb-with-ucode";
};
u-boot {
+ /*
+* TODO(s...@chromium.org):
+* Normally we use CONFIG_SYS_TEXT_BASE as the flash offset. But
+* for boards with textbase in SDRAM we cannot do this. Just use
+* an assumed-valid value (1MB before the end of flash) here so
+* that we can actually build an image for coreboot, etc.
+* We need a better solution, perhaps a separate Kconfig.
+*/
+#if CONFIG_SYS_TEXT_BASE == 0x111
offset = <0xfff0>;
+#else
+ offset = ;
+#endif
};
#else
u-boot-with-ucode-ptr {
@@ -77,7 +103,11 @@
offset = ;
};
#endif
-#ifdef CONFIG_SPL
+#ifdef CONFIG_TPL
+ x86-start16-tpl {
+ offset = ;
+ };
+#elif defined(CONFIG_SPL)
x86-start16-spl {
offset = ;
};
--
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[U-Boot] [PATCH v3 06/18] x86: Add documention on the samus flashmap
There are quite a few variables which control where things appear in the final ROM image. Add a flashmap in the documentation to make this easier to figure out. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- Changes in v3: None Changes in v2: None doc/README.x86 | 14 ++ 1 file changed, 14 insertions(+) diff --git a/doc/README.x86 b/doc/README.x86 index fa49cb8b8a2..d5224b75367 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -185,6 +185,20 @@ If you are using em100, then this command will flash write -Boot: em100 -s -d filename.rom -c W25Q64CV -r +Flash map for samus / broadwell: + + f800SYS_X86_START16 + RESET_SEG_START + fffd8000TPL_TEXT_BASE + fffaX86_MRC_ADDR + fff9VGA_BIOS_ADDR + ffedSYS_TEXT_BASE + ffeaX86_REFCODE_ADDR + ffe7SPL_TEXT_BASE + ffa0 + ff801000intel-me (address set by descriptor.bin) + ff80intel-descriptor + --- Intel Crown Bay specific instructions for bare mode: -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 10/18] x86: Update device tree for Chromium OS verified boot
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2: None
arch/x86/dts/u-boot.dtsi | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi
index 9cf733806a5..6b176339aed 100644
--- a/arch/x86/dts/u-boot.dtsi
+++ b/arch/x86/dts/u-boot.dtsi
@@ -6,9 +6,23 @@
#include
-#ifdef CONFIG_ROM_SIZE
+#ifdef CONFIG_CHROMEOS
/ {
binman {
+ multiple-images;
+ rom: rom {
+ };
+ };
+};
+#else
+/ {
+ rom: binman {
+ };
+};
+#endif
+
+#ifdef CONFIG_ROM_SIZE
+&rom {
filename = "u-boot.rom";
end-at-4gb;
sort-by-offset;
@@ -116,6 +130,5 @@
offset = ;
};
#endif
- };
};
#endif
--
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[U-Boot] [PATCH v3 03/18] x86: sysreset: Separate out the EFI code
The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.
Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3: None
Changes in v2:
- Add new patch to separate out the EFI code in sysreset
drivers/sysreset/sysreset_x86.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index 009f3766027..d484ec5de49 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -12,8 +12,7 @@
#include
#include
-static __efi_runtime int x86_sysreset_request(struct udevice *dev,
- enum sysreset_t type)
+static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
int value;
@@ -39,11 +38,18 @@ void __efi_runtime EFIAPI efi_reset_system(
efi_status_t reset_status,
unsigned long data_size, void *reset_data)
{
+ int value;
+
+ /*
+* inline this code since we are not caused in the context of a
+* udevice and passing NULL to x86_sysreset_request() is too horrible.
+*/
if (reset_type == EFI_RESET_COLD ||
reset_type == EFI_RESET_PLATFORM_SPECIFIC)
- x86_sysreset_request(NULL, SYSRESET_COLD);
- else if (reset_type == EFI_RESET_WARM)
- x86_sysreset_request(NULL, SYSRESET_WARM);
+ value = SYS_RST | RST_CPU | FULL_RST;
+ else /* assume EFI_RESET_WARM since we cannot return an error */
+ value = SYS_RST | RST_CPU;
+ outb(value, IO_PORT_RESET);
/* TODO EFI_RESET_SHUTDOWN */
--
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[U-Boot] [PATCH v3 04/18] x86: sysreset: Implement power-off if available
On modern x86 devices we can power the system off using the power-
management features of the PCH. Add an implementation for this.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v3:
- Use acpi_s3.h header for constants (and tidy up header order)
- Fix multi-line comment format
Changes in v2:
- Add new patch to implement power-off if available
drivers/sysreset/sysreset_x86.c | 79 -
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/sysreset/sysreset_x86.c b/drivers/sysreset/sysreset_x86.c
index d484ec5de49..ca892b305e2 100644
--- a/drivers/sysreset/sysreset_x86.c
+++ b/drivers/sysreset/sysreset_x86.c
@@ -7,14 +7,75 @@
#include
#include
+#include
+#include
#include
+#include
#include
#include
-#include
+
+struct x86_sysreset_platdata {
+ struct udevice *pch;
+};
+
+/*
+ * Power down the machine by using the power management sleep control
+ * of the chipset. This will currently only work on Intel chipsets.
+ * However, adapting it to new chipsets is fairly simple. You will
+ * have to find the IO address of the power management register block
+ * in your southbridge, and look up the appropriate SLP_TYP_S5 value
+ * from your southbridge's data sheet.
+ *
+ * This function never returns.
+ */
+int pch_sysreset_power_off(struct udevice *dev)
+{
+ struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+ struct pch_pmbase_info pm;
+ u32 reg32;
+ int ret;
+
+ if (!plat->pch)
+ return -ENOENT;
+ ret = pch_ioctl(plat->pch, PCH_REQ_PMBASE_INFO, &pm, sizeof(pm));
+ if (ret)
+ return ret;
+
+ /*
+* Mask interrupts or system might stay in a coma, not executing code
+* anymore, but not powered off either.
+*/
+ asm("cli");
+
+ /*
+* Avoid any GPI waking the system from S5* or the system might stay in
+* a coma
+*/
+ outl(0x, pm.base + pm.gpio0_en_ofs);
+
+ /* Clear Power Button Status */
+ outw(PWRBTN_STS, pm.base + pm.pm1_sts_ofs);
+
+ /* PMBASE + 4, Bit 10-12, Sleeping Type, * set to 111 -> S5, soft_off */
+ reg32 = inl(pm.base + pm.pm1_cnt_ofs);
+
+ /* Set Sleeping Type to S5 (poweroff) */
+ reg32 &= ~(SLP_EN | SLP_TYP);
+ reg32 |= SLP_TYP_S5;
+ outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+ /* Now set the Sleep Enable bit */
+ reg32 |= SLP_EN;
+ outl(reg32, pm.base + pm.pm1_cnt_ofs);
+
+ for (;;)
+ asm("hlt");
+}
static int x86_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
int value;
+ int ret;
switch (type) {
case SYSRESET_WARM:
@@ -23,6 +84,11 @@ static int x86_sysreset_request(struct udevice *dev, enum
sysreset_t type)
case SYSRESET_COLD:
value = SYS_RST | RST_CPU | FULL_RST;
break;
+ case SYSRESET_POWER_OFF:
+ ret = pch_sysreset_power_off(dev);
+ if (ret)
+ return ret;
+ return -EINPROGRESS;
default:
return -ENOSYS;
}
@@ -57,6 +123,15 @@ void __efi_runtime EFIAPI efi_reset_system(
}
#endif
+static int x86_sysreset_probe(struct udevice *dev)
+{
+ struct x86_sysreset_platdata *plat = dev_get_platdata(dev);
+
+ /* Locate the PCH if there is one. It isn't essential */
+ uclass_first_device(UCLASS_PCH, &plat->pch);
+
+ return 0;
+}
static const struct udevice_id x86_sysreset_ids[] = {
{ .compatible = "x86,reset" },
@@ -72,4 +147,6 @@ U_BOOT_DRIVER(x86_sysreset) = {
.id = UCLASS_SYSRESET,
.of_match = x86_sysreset_ids,
.ops = &x86_sysreset_ops,
+ .probe = x86_sysreset_probe,
+ .platdata_auto_alloc_size = sizeof(struct x86_sysreset_platdata),
};
--
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[U-Boot] [PATCH v3 01/18] cros_ec: Use a hyphen in the uclass name
Device-tree rules require that aliases use a hyphen rather than a
underscore. Update the uclass name to fit with this.
This allows device-tree aliases to be used to refer to cros-ec devices,
for example:
aliases {
cros-ec0 = &ec;
cros-ec1 = &pd;
};
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Update the commit message to explain the implications on aliases
drivers/misc/cros_ec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c
index 565de040fe9..382f8262863 100644
--- a/drivers/misc/cros_ec.c
+++ b/drivers/misc/cros_ec.c
@@ -1482,7 +1482,7 @@ int cros_ec_set_lid_shutdown_mask(struct udevice *dev,
int enable)
UCLASS_DRIVER(cros_ec) = {
.id = UCLASS_CROS_EC,
- .name = "cros_ec",
+ .name = "cros-ec",
.per_device_auto_alloc_size = sizeof(struct cros_ec_dev),
.post_bind = dm_scan_fdt_dev,
.flags = DM_UC_FLAG_ALLOC_PRIV_DMA,
--
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[U-Boot] [PATCH v3 02/18] x86: Add a simple TPL implementation
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Reviewed-by: Bin Meng
Signed-off-by: Simon Glass
---
Changes in v3:
- Rebase to x86/master
Changes in v2: None
arch/x86/include/asm/spl.h| 17 -
arch/x86/lib/Makefile | 9 ++-
arch/x86/lib/spl.c| 44 ++-
arch/x86/lib/tpl.c| 118 ++
include/configs/chromebook_link.h | 3 -
include/configs/qemu-x86.h| 5 --
6 files changed, 183 insertions(+), 13 deletions(-)
create mode 100644 arch/x86/lib/tpl.c
diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h
index 8cf59d14e7c..27432b28979 100644
--- a/arch/x86/include/asm/spl.h
+++ b/arch/x86/include/asm/spl.h
@@ -2,6 +2,19 @@
/*
* Copyright (C) 2017 Google, Inc
* Written by Simon Glass
- *
- * This file is required for SPL to build, but is empty.
*/
+
+#ifndef __asm_spl_h
+#define __asm_spl_h
+
+#define CONFIG_SPL_BOARD_LOAD_IMAGE
+
+enum {
+ BOOT_DEVICE_SPI = 10,
+ BOOT_DEVICE_BOARD,
+ BOOT_DEVICE_CROS_VBOOT,
+};
+
+void jump_to_spl(ulong entry);
+
+#endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 56fd680033b..436252dd831 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -43,7 +43,14 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_ZBOOT)+= zimage.o
endif
obj-$(CONFIG_HAVE_FSP) += fsp/
-obj-$(CONFIG_SPL_BUILD) += spl.o
+
+ifdef CONFIG_SPL_BUILD
+ifdef CONFIG_TPL_BUILD
+obj-y += tpl.o
+else
+obj-y += spl.o
+endif
+endif
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += div64.o
diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c
index 7d290740bfa..5d5d1a9ca74 100644
--- a/arch/x86/lib/spl.c
+++ b/arch/x86/lib/spl.c
@@ -5,8 +5,10 @@
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -20,6 +22,7 @@ __weak int arch_cpu_init_dm(void)
static int x86_spl_init(void)
{
+#ifndef CONFIG_TPL
/*
* TODO(s...@chromium.org): We use this area of RAM for the stack
* and global_data in SPL. Once U-Boot starts up and releocates it
@@ -27,6 +30,7 @@ static int x86_spl_init(void)
* place it immediately below CONFIG_SYS_TEXT_BASE.
*/
char *ptr = (char *)0x11;
+#endif
int ret;
debug("%s starting\n", __func__);
@@ -35,27 +39,44 @@ static int x86_spl_init(void)
debug("%s: spl_init() failed\n", __func__);
return ret;
}
+#ifdef CONFIG_TPL
+ /* Do a mini-init if TPL has already done the full init */
+ ret = x86_cpu_reinit_f();
+#else
ret = arch_cpu_init();
+#endif
if (ret) {
debug("%s: arch_cpu_init() failed\n", __func__);
return ret;
}
+#ifndef CONFIG_TPL
ret = arch_cpu_init_dm();
if (ret) {
debug("%s: arch_cpu_init_dm() failed\n", __func__);
return ret;
}
+#endif
preloader_console_init();
+#ifndef CONFIG_TPL
ret = print_cpuinfo();
if (ret) {
debug("%s: print_cpuinfo() failed\n", __func__);
return ret;
}
+#endif
ret = dram_init();
if (ret) {
debug("%s: dram_init() failed\n", __func__);
return ret;
}
+ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
+ ret = mrccache_spl_save();
+ if (ret)
+ debug("%s: Failed to write to mrccache (err=%d)\n",
+ __func__, ret);
+ }
+
+#ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
/* TODO(s...@chromium.org): Consider calling cpu_init_r() here */
@@ -80,9 +101,11 @@ static int x86_spl_init(void)
(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
CONFIG_XIP_ROM_SIZE);
if (ret) {
- debug("%s: SPI cache setup failed\n", __func__);
+ debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
return ret;
}
+ mtrr_commit(true);
+#endif
return 0;
}
@@ -96,9 +119,17 @@ void board_init_f(ulong flags)
debug("Error %d\n", ret);
hang();
}
-
+#ifdef CONFIG_TPL
+ gd->bd = malloc(sizeof(*gd->bd));
+ if (!gd->bd) {
+ printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
+ hang();
+ }
+ board_init_r(gd, 0);
+#else
/* Uninit CAR and jump to board_init_f_r() */
board_init_f_r_trampoline(gd->start_addr_sp);
+#endif
}
void board_init_f_r(void)
@@ -144,6 +175,7 @@ int spl_spi_load_image(void)
return -EPERM;
}
+#ifdef CONFIG_X86_RUN_64BIT
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
int ret;
@@ -154,3 +186,11 @@ void __noreturn jump_t
[U-Boot] [PATCH v3 00/18] x86: Add support for booting from TPL
At present SPL is used on 64-bit platforms, to allow SPL to be built as a 32-bit program and U-Boot proper to be built as 64-bit. However it is useful to be able to use SPL on any x86 platform, where U-Boot needs to be updated in the field. Then SPL can select which U-Boot to run (A or B) and most of the code can be updated. Similarly, using TPL allows both SPL and U-Boot to be updated. This is the best approach, since it means that all of U-Boot proper as well as SPL (in particular SDRAM init) can be updated in the field. This provides for the smallest possible amount of read-only (non-updateable) code: just the TPL code. This series contains a number of changes to allow x86 boards to use TPL, SPL and U-Boot proper. As a test, it is enabled for samus with a new chromebook_samus_tpl board. Changes in v3: - Rebase to x86/master - Use acpi_s3.h header for constants (and tidy up header order) - Fix multi-line comment format - Remove unneeded pch-reset node - Drop unnecessary change to chromebook_link_defconfig Changes in v2: - Update the commit message to explain the implications on aliases - Add new patch to separate out the EFI code in sysreset - Add new patch to implement power-off if available - Add a comment about the hard-coded text base - Add new patch to enable the RTC in Kconfig - Add a new patch to update PCH to work in TPL - Add a new patch allowing jumping from TPL to SPL - Sort defconfig and adjust it to build after rebase on maste Simon Glass (18): cros_ec: Use a hyphen in the uclass name x86: Add a simple TPL implementation x86: sysreset: Separate out the EFI code x86: sysreset: Implement power-off if available x86: sysreset: Implement the get_last() method x86: Add documention on the samus flashmap x86: samus: Update device tree for SPL x86: samus: Update device tree for verified boot x86: Update device tree for TPL x86: Update device tree for Chromium OS verified boot x86: Fix device-tree indentation x86: samus: Increase the pre-reloc memory again Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS" x86: Enable the RTC on all boards x86: Update the memory map a little x86: broadwell: Update PCH to work in TPL x86: Add a way to jump from TPL to SPL x86: samus: Add a target to boot through TPL arch/Kconfig | 1 + arch/x86/cpu/broadwell/pch.c | 12 +- arch/x86/cpu/start.S | 13 ++ arch/x86/dts/chromebook_samus.dts | 55 +++- arch/x86/dts/u-boot.dtsi | 162 ++ arch/x86/include/asm/spl.h| 17 ++- arch/x86/lib/Makefile | 9 +- arch/x86/lib/spl.c| 44 +- arch/x86/lib/tpl.c| 118 board/google/Kconfig | 8 ++ board/google/chromebook_samus/Kconfig | 14 +- board/google/chromebook_samus/MAINTAINERS | 7 + configs/chromebook_samus_defconfig| 2 +- configs/chromebook_samus_tpl_defconfig| 82 +++ doc/README.x86| 16 +++ drivers/misc/cros_ec.c| 2 +- drivers/sysreset/sysreset_x86.c | 101 +- include/configs/chromebook_link.h | 3 - include/configs/chromebook_samus.h| 2 + include/configs/qemu-x86.h| 5 - include/configs/x86-common.h | 1 - include/pci.h | 6 +- 22 files changed, 583 insertions(+), 97 deletions(-) create mode 100644 arch/x86/lib/tpl.c create mode 100644 configs/chromebook_samus_tpl_defconfig -- 2.21.0.1020.gf2820cf01a-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 45/50] Revert "pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS"
Hi Thierry, On Thu, 2 May 2019 at 03:25, Thierry Reding wrote: > > On Thu, May 02, 2019 at 12:09:49AM +0800, Bin Meng wrote: > > +Thierry > > > > On Fri, Apr 26, 2019 at 12:00 PM Simon Glass wrote: > > > > > > This reverts commit aec4298ccb337106fd0115b91d846a022fdf301d. > > > > > > Unfortunately this has a dramatic impact on the pre-relocation memory > > > used on x86 platforms (increasing it by 2KB) since it increases the > > > overhead for each PCI device from 220 bytes to 412 bytes. > > > > > > The offending line is in UCLASS_DRIVER(pci): > > > > > > .per_device_auto_alloc_size = sizeof(struct pci_controller), > > > > > > This means that all PCI devices have the controller struct associated > > > with them. The solution is to move the regions[] member out of the array, > > > makes its size dynamic, or split UCLASS_PCI into controllers and > > > non-controllers, as the comment suggests. > > > > > > For now, revert the commit to get things running again. > > > > > > Signed-off-by: Simon Glass > > > --- > > > > > > Changes in v2: None > > > > > > include/pci.h | 6 +- > > > 1 file changed, 1 insertion(+), 5 deletions(-) > > > > > > > Reviewed-by: Bin Meng > > Ugh... so we're trading one regression for another? Can we not live with > the 2 KiB increase on x86 until this has been properly fixed? Currently > this will cause Jetson TX2 to crash if it starts using PCI. Unfortunately this breaks several boards since we are out of memory. I think this needs a better solution to reduce the memory usage down to sensible levels. This is something I should have considered when implementing the PCI uclass, but unfortunately I did not. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 4/4] lib: uuid: Fix unseeded PRNG on RANDOM_UUID=y
On 5/2/19 2:27 PM, Eugeniu Rosca wrote:
The random uuid values (enabled via CONFIG_RANDOM_UUID=y) on our
platform are always the same. Below is consistent on each cold boot:
=> ### interrupt autoboot
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=d117f98e-6f2c-d04b-a5b2-331a19f91cb2
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=ad5ec4b6-2d9f-8544-9417-fe3bd1c9b1b3
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=cceb0b18-39cb-d547-9db7-03b405fa77d4
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=d4981a2b-0478-544e-9607-7fd3c651068d
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=6d6c9a36-e919-264d-a9ee-bd00379686c7
While the uuids do change on every 'gpt write' command, the values
appear to be taken from the same pool, in the same order.
Assuming U-Boot with RANDOM_UUID=y is deployed on a large number of
devices, all those devices would essentially expose the same UUID,
breaking the assumption of system/RFS/application designers who rely
on UUID as being globally unique (e.g. a database using UUID as key
would alias/mix up entries/records due to duplicated UUID).
The root cause seems to be simply _not_ seeding PRNG before generating
a random value. It turns out this belongs to an established class of
PRNG-specific problems, commonly known as "unseeded randomness", for
which I am able to find below bugs/CVE/CWE:
- https://bugzilla.redhat.com/show_bug.cgi?id=CVE-2015-0285
("CVE-2015-0285 openssl: handshake with unseeded PRNG")
- https://bugzilla.redhat.com/show_bug.cgi?id=CVE-2015-9019
("CVE-2015-9019 libxslt: math.random() in xslt uses unseeded
randomness")
- https://cwe.mitre.org/data/definitions/336.html
("CWE-336: Same Seed in Pseudo-Random Number Generator (PRNG)")
The first revision [1] of this patch updated the seed based on the
output of get_timer(), similar to [4].
There are two problems with this approach:
- get_timer() has a poor _ms_ resolution
- when gen_rand_uuid() is called in a loop, get_timer() returns the
same result, leading to the same seed being passed to srand(),
leading to the same uuid being generated for several partitions
with different names
The above drawbacks have been addressed in the second version [2].
In its third revision (current), the patch reworded the description
and summary line to emphasize it is a *fix* rather than an improvement.
Testing [3] consisted of running 'gpt write mmc 1 $partitions' in a
loop on R-Car3 for several minutes, collecting 8844 randomly generated
UUIDS. Two consecutive cold boots are concatenated in the log.
As a result, all uuid values are unique (scripted check).
Thanks to Roman, who reported the issue and provided support in fixing.
[1] https://patchwork.ozlabs.org/patch/1091802/
[2] https://patchwork.ozlabs.org/patch/1092945/
[3] https://gist.github.com/erosca/2820be9d554f76b982edd48474d0e7ca
[4] commit da384a9d7628 ("net: rename and refactor eth_rand_ethaddr() function")
Reported-by: Roman Stratiienko
Signed-off-by: Eugeniu Rosca
Reviewed-by: Heinrich Schuchardt
--
v3:
- Reworked the patch summary line and description to emphasize this is
a fix rather than an improvement by precisely pointing out the root
cause and mentioning related CVE/CWE.
v2:
- https://patchwork.ozlabs.org/patch/1092945/
- Replaced get_timer(0) with get_ticks() and added rand() to seed value
- Performed extensive testing on R-Car3 (ARMv8). See:
https://gist.github.com/erosca/2820be9d554f76b982edd48474d0e7ca
v1:
- https://patchwork.ozlabs.org/patch/1092944/
---
lib/uuid.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/uuid.c b/lib/uuid.c
index fa20ee39fc32..2d4d6ef7e461 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -238,6 +238,8 @@ void gen_rand_uuid(unsigned char *uuid_bin)
unsigned int *ptr = (unsigned int *)&uuid;
int i;
+ srand(get_ticks() + rand());
+
/* Set all fields randomly */
for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
*(ptr + i) = cpu_to_be32(rand());
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Re: [U-Boot] [PATCH v2] board/BuR/brsmarc1: initial commit
On 5/2/19 2:46 PM, Felix Brack wrote: Hi Hannes, Hi Felix, On 02.05.19 14:09, Hannes Schmelzer wrote: This commit adds support for the B&R brsmarc1 SoM. The SoM is based on TI's AM335x SoC. Mainly vxWorks 6.9.4.x is running on the board, doing some PLC stuff on various carrier boards. Signed-off-by: Hannes Schmelzer --- Changes in v2: - fix style issue in arch/arm/mach-omap2/am33xx/Kconfig - fix SDPX tag in Make-files/rules arch/arm/dts/Makefile | 1 + arch/arm/dts/am335x-brsmarc1.dts | 408 + arch/arm/mach-omap2/Kconfig| 1 + arch/arm/mach-omap2/am33xx/Kconfig | 4 + board/BuR/brsmarc1/Kconfig | 15 ++ board/BuR/brsmarc1/MAINTAINERS | 6 + board/BuR/brsmarc1/Makefile| 10 + board/BuR/brsmarc1/board.c | 168 +++ board/BuR/brsmarc1/config.mk | 33 +++ board/BuR/brsmarc1/mux.c | 266 configs/brsmarc1_defconfig | 107 ++ include/configs/brsmarc1.h | 87 12 files changed, 1106 insertions(+) create mode 100644 arch/arm/dts/am335x-brsmarc1.dts create mode 100644 board/BuR/brsmarc1/Kconfig create mode 100644 board/BuR/brsmarc1/MAINTAINERS create mode 100644 board/BuR/brsmarc1/Makefile create mode 100644 board/BuR/brsmarc1/board.c create mode 100644 board/BuR/brsmarc1/config.mk create mode 100644 board/BuR/brsmarc1/mux.c create mode 100644 configs/brsmarc1_defconfig create mode 100644 include/configs/brsmarc1.h diff --git a/board/BuR/brsmarc1/mux.c b/board/BuR/brsmarc1/mux.c new file mode 100644 index 000..33c214d --- /dev/null +++ b/board/BuR/brsmarc1/mux.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * mux.c + * + * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1) + * + * Copyright (C) 2017 Hannes Schmelzer + * B&R Industrial Automation GmbH - http://www.br-automation.com + * + */ + +#include +#include +#include +#include +#include +#include + Is there any particular reason for not using the existing pinctrl driver to do all this pin configuration? Many thanks for your input. Not really a (known) reason why not using this driver. Maybe i just wasn't aware of it. Started in 2013 with first am335x board, and the style about pinmux setup wasn't changed over time . Only reason for not changing this NOW is, that i have this boards already in production and passed internal testing. But i will look into the pinctrl driver, then convert the board and bring in that changes within next (internal) release. After that i will provide some patch for changing that on all BuR am335x boards (brxre1, brppt1, brsmarc1). regards Felix ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot cheers, Hannes ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2 v2] fit: Support compression for non-kernel components (e.g. FDT)
Hi Julius,
On Thu, 18 Apr 2019 at 15:09, Julius Werner wrote:
>
> This patch adds support for compressing non-kernel image nodes in a FIT
> image (kernel nodes could already be compressed previously). This can
> reduce the size of FIT images and therefore improve boot times
> (especially when an image bundles many different kernel FDTs). The
> images will automatically be decompressed on load.
>
> This patch does not support extracting compatible strings from
> compressed FDTs, so it's not very helpful in conjunction with
> CONFIG_FIT_BEST_MATCH yet, but it can already be used in environments
> that select the configuration to load explicitly.
>
> Signed-off-by: Julius Werner
> ---
> common/image-fit.c | 83 +++---
> 1 file changed, 49 insertions(+), 34 deletions(-)
We should get a test together for this. There is an existing
test_fit.py which might be expanded, or perhaps create a new one and
share some code.
>
> diff --git a/common/image-fit.c b/common/image-fit.c
> index ac901e131c..006e828b79 100644
> --- a/common/image-fit.c
> +++ b/common/image-fit.c
> @@ -22,6 +22,7 @@
> DECLARE_GLOBAL_DATA_PTR;
> #endif /* !USE_HOSTCC*/
>
> +#include
> #include
> #include
> #include
> @@ -1576,6 +1577,13 @@ int fit_conf_find_compat(const void *fit, const void
> *fdt)
> kfdt_name);
> continue;
> }
> +
> + if (!fit_image_check_comp(fit, kfdt_noffset, IH_COMP_NONE)) {
> + debug("Can't extract compat from \"%s\"
> (compressed)\n",
> + kfdt_name);
> + continue;
> + }
> +
> /*
> * Get a pointer to this configuration's fdt.
> */
> @@ -1795,11 +1803,12 @@ int fit_image_load(bootm_headers_t *images, ulong
> addr,
> const char *fit_uname_config;
> const char *fit_base_uname_config;
> const void *fit;
> - const void *buf;
> + void *buf;
> + void *loadbuf;
> size_t size;
> int type_ok, os_ok;
> - ulong load, data, len;
> - uint8_t os;
> + ulong load, load_end, data, len;
> + uint8_t os, comp;
> #ifndef USE_HOSTCC
> uint8_t os_arch;
> #endif
> @@ -1895,12 +1904,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
> images->os.arch = os_arch;
> #endif
>
> - if (image_type == IH_TYPE_FLATDT &&
> - !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
> - puts("FDT image is compressed");
> - return -EPROTONOSUPPORT;
> - }
> -
> bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL);
> type_ok = fit_image_check_type(fit, noffset, image_type) ||
> fit_image_check_type(fit, noffset, IH_TYPE_FIRMWARE) ||
> @@ -1931,7 +1934,8 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
> bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ALL_OK);
>
> /* get image data address and length */
> - if (fit_image_get_data_and_size(fit, noffset, &buf, &size)) {
> + if (fit_image_get_data_and_size(fit, noffset,
> + (const void **)&buf, &size)) {
> printf("Could not find %s subimage data!\n", prop_name);
> bootstage_error(bootstage_id + BOOTSTAGE_SUB_GET_DATA);
> return -ENOENT;
> @@ -1939,30 +1943,15 @@ int fit_image_load(bootm_headers_t *images, ulong
> addr,
>
> #if !defined(USE_HOSTCC) && defined(CONFIG_FIT_IMAGE_POST_PROCESS)
> /* perform any post-processing on the image data */
> - board_fit_image_post_process((void **)&buf, &size);
> + board_fit_image_post_process(&buf, &size);
> #endif
>
> len = (ulong)size;
>
> - /* verify that image data is a proper FDT blob */
> - if (image_type == IH_TYPE_FLATDT && fdt_check_header(buf)) {
> - puts("Subimage data is not a FDT");
> - return -ENOEXEC;
> - }
> -
> bootstage_mark(bootstage_id + BOOTSTAGE_SUB_GET_DATA_OK);
>
> - /*
> -* Work-around for eldk-4.2 which gives this warning if we try to
> -* cast in the unmap_sysmem() call:
> -* warning: initialization discards qualifiers from pointer target
> type
> -*/
> - {
> - void *vbuf = (void *)buf;
> -
> - data = map_to_sysmem(vbuf);
> - }
> -
We don't support gcc 4.2 now so this code can be simplified to the
line you have below, but perhaps this should be in a separate patch?
> + data = map_to_sysmem(buf);
> + load = data;
> if (load_op == FIT_LOAD_IGNORED) {
> /* Don't load */
> } else if (fit_image_get_load(fit, noffset, &load)) {
> @@ -1974,8 +1963,6 @@ int fit_image_load(bootm_headers_t *images, ulong addr,
> }
> } else if (load_op != FIT_LOAD_OPT
Re: [U-Boot] [PATCH] board: toradex: drop support.arm maintainer email
Hi Tom Sorry, this is a v2 and the only change is Stefan's ack being added. Please apply, thanks! Cheers Marcel On Thu, 2019-05-02 at 17:14 +0200, Marcel Ziswiler wrote: > From: Marcel Ziswiler > > Drop Toradex ARM Support from maintainer > email > list as this just clogs our support ticketing system. > > Signed-off-by: Marcel Ziswiler > Acked-by: Stefan Agner > > --- > > board/toradex/colibri-imx6ull/MAINTAINERS | 1 - > board/toradex/colibri_imx7/MAINTAINERS| 1 - > 2 files changed, 2 deletions(-) > > diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS > b/board/toradex/colibri-imx6ull/MAINTAINERS > index 7cda555984..626c1f94f9 100644 > --- a/board/toradex/colibri-imx6ull/MAINTAINERS > +++ b/board/toradex/colibri-imx6ull/MAINTAINERS > @@ -1,6 +1,5 @@ > Colibri iMX6ULL > M: Stefan Agner > -M: Toradex ARM Support > W: http://developer.toradex.com/software/linux/linux-software > W: https://www.toradex.com/community > S: Maintained > diff --git a/board/toradex/colibri_imx7/MAINTAINERS > b/board/toradex/colibri_imx7/MAINTAINERS > index f55f8045f4..cd0f9c9b2d 100644 > --- a/board/toradex/colibri_imx7/MAINTAINERS > +++ b/board/toradex/colibri_imx7/MAINTAINERS > @@ -1,6 +1,5 @@ > Colibri iMX7 > M: Stefan Agner > -M: Toradex ARM Support > W: http://developer.toradex.com/software/linux/linux-software > W: https://www.toradex.com/community > S: Maintained ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/6] imx8qm: fix cpu frequency reporting
CPU frequency reporting failed with the following error message being
printed:
sc_pm_get_clock_rate: resource:507 clk:2: res:3
Could not read CPU frequency: -22
CPU: NXP i.MX8QM RevB A53 at 0 MHz
Fix this by differentiating between the A35 as found on the i.MX 8QXP
and the A53 as found on the i.MX 8QM SoCs.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Max Krummenacher
---
Changes in v2: None
arch/arm/mach-imx/imx8/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index 12716e7e9e..12596c6387 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -654,8 +654,10 @@ static ulong imx8_get_cpu_rate(void)
{
ulong rate;
int ret;
+ int type = is_cortex_a35() ? SC_R_A35 : is_cortex_a53() ?
+ SC_R_A53 : SC_R_A72;
- ret = sc_pm_get_clock_rate(-1, SC_R_A35, SC_PM_CLK_CPU,
+ ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
(sc_pm_clock_rate_t *)&rate);
if (ret) {
printf("Could not read CPU frequency: %d\n", ret);
--
2.20.1
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[U-Boot] [PATCH v2 3/6] clk: imx8qm: fix usdhc2 clocks
Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b03 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v2: None drivers/clk/imx/clk-imx8qm.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/imx/clk-imx8qm.c b/drivers/clk/imx/clk-imx8qm.c index 6b5561e178..a6b09d2109 100644 --- a/drivers/clk/imx/clk-imx8qm.c +++ b/drivers/clk/imx/clk-imx8qm.c @@ -80,6 +80,12 @@ ulong imx8_clk_get_rate(struct clk *clk) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_UART0_IPG_CLK: case IMX8QM_UART0_CLK: resource = SC_R_UART_0; @@ -185,6 +191,12 @@ ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: @@ -273,6 +285,12 @@ int __imx8_clk_enable(struct clk *clk, bool enable) resource = SC_R_SDHC_1; pm_clk = SC_PM_CLK_PER; break; + case IMX8QM_SDHC2_IPG_CLK: + case IMX8QM_SDHC2_CLK: + case IMX8QM_SDHC2_DIV: + resource = SC_R_SDHC_2; + pm_clk = SC_PM_CLK_PER; + break; case IMX8QM_ENET0_IPG_CLK: case IMX8QM_ENET0_AHB_CLK: case IMX8QM_ENET0_REF_DIV: -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 5/6] imx8: fuse: fix fuse driver
This fixes the i.MX 8 fuse driver to actually build for i.MX 8QM as well. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher --- Changes in v2: None drivers/misc/imx8/fuse.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 29d2256a22..2f2fad2c17 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -15,13 +15,11 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_ECC_WORD_START_10x10 #define FSL_ECC_WORD_END_1 0x10F -#ifdef CONFIG_IMX8QXP #define FSL_ECC_WORD_START_20x220 #define FSL_ECC_WORD_END_2 0x31F #define FSL_QXP_FUSE_GAP_START 0x110 #define FSL_QXP_FUSE_GAP_END0x21F -#endif #define FSL_SIP_OTP_READ 0xc20A #define FSL_SIP_OTP_WRITE0xc20B -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/6] arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4
From: Marcel Ziswiler
Add support for i2c0, i2c1, i2c2, i2c3 and i2c4.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Max Krummenacher
---
Changes in v2: None
arch/arm/dts/fsl-imx8qm.dtsi | 75
1 file changed, 75 insertions(+)
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index db01959990..af060db3a1 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -29,6 +29,11 @@
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
};
memory@8000 {
@@ -224,6 +229,76 @@
};
};
+ i2c0: i2c@5a80 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a80 0x0 0x4000>;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_I2C0_CLK>,
+<&clk IMX8QM_I2C0_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_I2C0_CLK>;
+ assigned-clock-rates = <2400>;
+ power-domains = <&pd_dma_lpi2c0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@5a81 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a81 0x0 0x4000>;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_I2C1_CLK>,
+<&clk IMX8QM_I2C1_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_I2C1_CLK>;
+ assigned-clock-rates = <2400>;
+ power-domains = <&pd_dma_lpi2c1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@5a82 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a82 0x0 0x4000>;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_I2C2_CLK>,
+<&clk IMX8QM_I2C2_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_I2C2_CLK>;
+ assigned-clock-rates = <2400>;
+ power-domains = <&pd_dma_lpi2c2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@5a83 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a83 0x0 0x4000>;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_I2C3_CLK>,
+<&clk IMX8QM_I2C3_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_I2C3_CLK>;
+ assigned-clock-rates = <2400>;
+ power-domains = <&pd_dma_lpi2c3>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@5a84 {
+ compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+ reg = <0x0 0x5a84 0x0 0x4000>;
+ interrupts = ;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_I2C4_CLK>,
+<&clk IMX8QM_I2C4_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_I2C4_CLK>;
+ assigned-clock-rates = <2400>;
+ power-domains = <&pd_dma_lpi2c4>;
+ status = "disabled";
+ };
+
gpio0: gpio@5d08 {
compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
reg = <0x0 0x5d08 0x0 0x1>;
--
2.20.1
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[U-Boot] [PATCH v2 6/6] board: toradex: add apalis imx8qm 4gb wb it v1.0b module support
From: Marcel Ziswiler
This commit adds initial support for the Toradex Apalis iMX8QM 4GB WB IT
V1.0B module. Unlike the V1.0A early access samples exclusively booting
from SD card, they are now strapped to boot from eFuses which are
factory fused to properly boot from their on-module eMMC. U-Boot
supports either booting from the on-module eMMC or may be used for
recovery purpose using the universal update utility (uuu) aka mfgtools
3.0.
Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Gigabit Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QM as of yet.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Max Krummenacher
---
Changes in v2:
- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as
suggested by Max.
- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config()
stuff not applicable to the Micrel PHY we are using as suggested by Max.
- Drop CONFIG_FEC_XCV_TYPE in favour of device tree configuration therof
as suggested by Max.
arch/arm/dts/Makefile | 1 +
arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 128
arch/arm/dts/fsl-imx8qm-apalis.dts | 615
arch/arm/mach-imx/imx8/Kconfig | 6 +
board/toradex/apalis-imx8qm/Kconfig | 30 +
board/toradex/apalis-imx8qm/MAINTAINERS | 9 +
board/toradex/apalis-imx8qm/Makefile| 6 +
board/toradex/apalis-imx8qm/README | 66 +++
board/toradex/apalis-imx8qm/apalis-imx8qm.c | 149 +
board/toradex/apalis-imx8qm/imximage.cfg| 24 +
configs/apalis-imx8qm_defconfig | 56 ++
include/configs/apalis-imx8qm.h | 177 ++
12 files changed, 1267 insertions(+)
create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts
create mode 100644 board/toradex/apalis-imx8qm/Kconfig
create mode 100644 board/toradex/apalis-imx8qm/MAINTAINERS
create mode 100644 board/toradex/apalis-imx8qm/Makefile
create mode 100644 board/toradex/apalis-imx8qm/README
create mode 100644 board/toradex/apalis-imx8qm/apalis-imx8qm.c
create mode 100644 board/toradex/apalis-imx8qm/imximage.cfg
create mode 100644 configs/apalis-imx8qm_defconfig
create mode 100644 include/configs/apalis-imx8qm.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 598dc213e3..2c1cf3122a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -576,6 +576,7 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
+ fsl-imx8qm-apalis.dtb \
fsl-imx8qm-mek.dtb \
fsl-imx8qxp-colibri.dtb \
fsl-imx8qxp-mek.dtb
diff --git a/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
new file mode 100644
index 00..7b1a9550e4
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio3 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio4 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio5 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio6 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio7 {
+ u-boot,dm-spl;
+};
+
+&pd_conn {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch0 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch1 {
+ u-boot,dm-spl;
+};
+
+&pd_conn_sdch2 {
+ u-boot,dm-spl;
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&gpio6 {
+ u-boot,dm-spl;
+};
+
+&gpio7 {
+ u-boot,dm-spl;
+};
+
+&lpuart0 {
+ u-boot,dm-spl;
+};
+
+&lpuart1 {
+ u-boot,dm-spl;
+};
+
+&lpuart2 {
+ u-boot,dm-spl;
+};
+
+&lpuart3 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm-apalis.dts
b/arch/arm/dts/fsl-imx8qm-apalis.dts
new file mode 100644
index 00..9b1f8aa32d
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qm-apalis.dts
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2017-2019 Toradex
+ */
+
+/dts-v1/;
+
+/* First 128KB is for PSCI ATF. */
+/memreserve/ 0x8000 0x0002;
+
+#include "fsl-imx8qm.dtsi"
+#include "fsl-imx8qm-apalis-u-boot.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX8QM";
+ compatible = "toradex,apalis-imx8qm", "fsl,imx8qm";
+
+ chosen {
+ bootargs = "consol
[U-Boot] [PATCH v2 0/6] apalis imx8qm 4gb wb it v1.0b module support
This series adds support for more lpuart instances, support for i2c0, i2c1, i2c2, i2c3, i2c4, fixes support for uSDHC2, fixes CPU frequency reporting, fixes fuse driver and last but not least introduces support for the Toradex Apalis iMX8QM 4GB WB IT V1.0B module. This series is available together with the last few clean-up patches and the Colibri iMX8QXP patch series on our git server [1] as well. [1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next Changes in v2: - Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as suggested by Max. - Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config() stuff not applicable to the Micrel PHY we are using as suggested by Max. - Drop CONFIG_FEC_XCV_TYPE in favour of device tree configuration therof as suggested by Max. Marcel Ziswiler (6): arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4 arm: dts: imx8qm: add support for i2c0, i2c1, i2c2, i2c3 and i2c4 clk: imx8qm: fix usdhc2 clocks imx8qm: fix cpu frequency reporting imx8: fuse: fix fuse driver board: toradex: add apalis imx8qm 4gb wb it v1.0b module support arch/arm/dts/Makefile | 1 + arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi | 128 arch/arm/dts/fsl-imx8qm-apalis.dts | 615 arch/arm/dts/fsl-imx8qm.dtsi| 155 + arch/arm/mach-imx/imx8/Kconfig | 6 + arch/arm/mach-imx/imx8/cpu.c| 4 +- board/toradex/apalis-imx8qm/Kconfig | 30 + board/toradex/apalis-imx8qm/MAINTAINERS | 9 + board/toradex/apalis-imx8qm/Makefile| 6 + board/toradex/apalis-imx8qm/README | 66 +++ board/toradex/apalis-imx8qm/apalis-imx8qm.c | 149 + board/toradex/apalis-imx8qm/imximage.cfg| 24 + configs/apalis-imx8qm_defconfig | 56 ++ drivers/clk/imx/clk-imx8qm.c| 18 + drivers/misc/imx8/fuse.c| 2 - include/configs/apalis-imx8qm.h | 177 ++ 16 files changed, 1443 insertions(+), 3 deletions(-) create mode 100644 arch/arm/dts/fsl-imx8qm-apalis-u-boot.dtsi create mode 100644 arch/arm/dts/fsl-imx8qm-apalis.dts create mode 100644 board/toradex/apalis-imx8qm/Kconfig create mode 100644 board/toradex/apalis-imx8qm/MAINTAINERS create mode 100644 board/toradex/apalis-imx8qm/Makefile create mode 100644 board/toradex/apalis-imx8qm/README create mode 100644 board/toradex/apalis-imx8qm/apalis-imx8qm.c create mode 100644 board/toradex/apalis-imx8qm/imximage.cfg create mode 100644 configs/apalis-imx8qm_defconfig create mode 100644 include/configs/apalis-imx8qm.h -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 1/6] arm: dts: imx8qm: add lpuart1, lpuart2, lpuart3, lpuart4
From: Marcel Ziswiler
Add support for lpuart1, lpuart2, lpuart3 and lpuart4.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Max Krummenacher
---
Changes in v2: None
arch/arm/dts/fsl-imx8qm.dtsi | 80
1 file changed, 80 insertions(+)
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index b39c40bd98..db01959990 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -22,6 +22,10 @@
ethernet0 = &fec1;
ethernet1 = &fec2;
serial0 = &lpuart0;
+ serial1 = &lpuart1;
+ serial2 = &lpuart2;
+ serial3 = &lpuart3;
+ serial4 = &lpuart4;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
mmc2 = &usdhc3;
@@ -193,6 +197,30 @@
power-domains = <&pd_dma>;
wakeup-irq = <345>;
};
+ pd_dma_lpuart1: PD_DMA_UART1 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ wakeup-irq = <346>;
+ };
+ pd_dma_lpuart2: PD_DMA_UART2 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ wakeup-irq = <347>;
+ };
+ pd_dma_lpuart3: PD_DMA_UART3 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ wakeup-irq = <348>;
+ };
+ pd_dma_lpuart4: PD_DMA_UART4 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_dma>;
+ wakeup-irq = <349>;
+ };
};
};
@@ -297,6 +325,58 @@
status = "disabled";
};
+ lpuart1: serial@5a07 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a07 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&clk IMX8QM_UART1_CLK>,
+<&clk IMX8QM_UART1_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_UART1_CLK>;
+ assigned-clock-rates = <8000>;
+ power-domains = <&pd_dma_lpuart1>;
+ status = "disabled";
+ };
+
+ lpuart2: serial@5a08 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a08 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&clk IMX8QM_UART2_CLK>,
+<&clk IMX8QM_UART2_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_UART2_CLK>;
+ assigned-clock-rates = <8000>;
+ power-domains = <&pd_dma_lpuart2>;
+ status = "disabled";
+ };
+
+ lpuart3: serial@5a09 {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a09 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&clk IMX8QM_UART3_CLK>,
+<&clk IMX8QM_UART3_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_UART3_CLK>;
+ assigned-clock-rates = <8000>;
+ power-domains = <&pd_dma_lpuart3>;
+ status = "disabled";
+ };
+
+ lpuart4: serial@5a0a {
+ compatible = "fsl,imx8qm-lpuart";
+ reg = <0x0 0x5a0a 0x0 0x1000>;
+ interrupts = ;
+ clocks = <&clk IMX8QM_UART4_CLK>,
+<&clk IMX8QM_UART4_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_UART4_CLK>;
+ assigned-clock-rates = <8000>;
+ power-domains = <&pd_dma_lpuart4>;
+ status = "disabled";
+ };
+
usdhc1: usdhc@5b01 {
compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc";
interrupt-parent = <&gic>;
--
2.20.1
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[U-Boot] [PATCH v6 2/2] board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support
From: Marcel Ziswiler
This commit adds initial support for the Toradex Colibri iMX8QXP 2GB WB
IT V1.0B module. Unlike the V1.0A early access samples exclusively
booting from SD card, they are now strapped to boot from eFuses which
are factory fused to properly boot from their on-module eMMC. U-Boot
supports either booting from the on-module eMMC or may be used for
recovery purpose using the universal update utility (uuu) aka mfgtools
3.0.
Functionality wise the following is known to be working:
- eMMC and MMC/SD card
- Ethernet
- GPIOs
- I2C
Unfortunately, there is no USB functionality for the i.MX 8QXP as of
yet.
Signed-off-by: Marcel Ziswiler
Reviewed-by: Igor Opaniuk
---
Changes in v6:
- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as
suggested by Max during review of Apalis iMX8QM.
- Drop anyway commented out board_gpio_init() stuff.
- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config()
stuff not applicable to the Micrel PHY we are using as suggested by
Max during review of Apalis iMX8QM.
Changes in v5:
- Keep alphabetical order of device trees in Makefile.
- Order targets in Kconfig alphabetically.
- Fix indentation in SPDX.
- Remove stale includes from board file.
- Take into account ahab-container being platform specific.
- Use vidargs instead of multiple discrete video= in configuration.
- Fix console baudrate specification.
- Remove redundant CONFIG_SYS_MMC_ENV_DEV define and add some clarifying
comment.
- Fix product name being Colibri iMX8X in a comment.
- Remove obsolete CONFIG_NR_DRAM_BANKS.
Changes in v4:
- Fixed SPDX as well as using SZ_ macros where applicable as suggested
by Igor.
- Fixed superfluous trailing line continuation introduced by commit
0d331c035a09 ("imx: support i.MX8QM MEK board") in the Makefile plus
sorted stuff alphabetically again.
- Applied changes similar to commit 3b9ac5415084 ("imx: 8qxp_mek: fix
fdt_file and console"). However, note that using ${baudrate} in
console= like that won't actually work!
- Applied changes similar to commit e5b8f7e665aa ("imx8qxp: mek: enable
dm-spl for pm").
Changes in v3:
- Added Igor's reviewed-by tag.
Changes in v2:
- Changed imx-atf git clone command to include initial branch
information as suggested by Igor.
- Sorted board file includes alphabetically as suggested by Igor.
- Got rid of SPL configuration in legacy header file as suggested by
Igor and the whole use of SPL on i.MX 8X anyway neither works well
nor makes any much sense at all.
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 117 +++
arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++
arch/arm/mach-imx/imx8/Kconfig| 12 +-
board/toradex/colibri-imx8qxp/Kconfig | 30 ++
board/toradex/colibri-imx8qxp/MAINTAINERS | 9 +
board/toradex/colibri-imx8qxp/Makefile| 6 +
board/toradex/colibri-imx8qxp/README | 66
.../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 160 +
board/toradex/colibri-imx8qxp/imximage.cfg| 24 ++
configs/colibri-imx8qxp_defconfig | 53 +++
include/configs/colibri-imx8qxp.h | 210 +++
12 files changed, 1014 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
create mode 100644 board/toradex/colibri-imx8qxp/Makefile
create mode 100644 board/toradex/colibri-imx8qxp/README
create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
create mode 100644 configs/colibri-imx8qxp_defconfig
create mode 100644 include/configs/colibri-imx8qxp.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e56a39e0b1..598dc213e3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -576,8 +576,9 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += \
- fsl-imx8qxp-mek.dtb \
fsl-imx8qm-mek.dtb \
+ fsl-imx8qxp-colibri.dtb \
+ fsl-imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
diff --git a/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
new file mode 100644
index 00..5b061f94ba
--- /dev/null
+++ b/arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Copyright 2019 Toradex AG
+ */
+
+&{/imx8qx-pm} {
+
+ u-boot,dm-spl;
+};
+
+&mu {
+ u-boot,dm-spl;
+};
+
+&clk {
+ u-boot,dm-spl;
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+&pd_lsio {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio0 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio1 {
+ u-boot,dm-spl;
+};
+
+&pd_lsio_gpio2 {
+ u-bo
[U-Boot] [PATCH v6 0/2] colibri imx8qxp 2gb wb it v1.0b module support
This series fixes building for i.MX8 without SPL and adds support for
more lpuart instances, cleans-up and extends the Toradex SKU handling
and last but not least introduces support for the Toradex Colibri
iMX8QXP 2GB WB IT V1.0B module.
This series is available together with the last few clean-up patches
on our git server [1] as well.
[1] http://git.toradex.com/cgit/u-boot-toradex.git/log/?h=for-next
Changes in v6:
- Use firmware-imx-8.0 matching NXP's sumo-4.14.78-1.0.0_ga BSP as
suggested by Max during review of Apalis iMX8QM.
- Drop anyway commented out board_gpio_init() stuff.
- Drop Qualcomm (formwerly Atheros) AR8031 specific board_phy_config()
stuff not applicable to the Micrel PHY we are using as suggested by
Max during review of Apalis iMX8QM.
Changes in v5:
- Keep alphabetical order of device trees in Makefile.
- Order targets in Kconfig alphabetically.
- Fix indentation in SPDX.
- Remove stale includes from board file.
- Take into account ahab-container being platform specific.
- Use vidargs instead of multiple discrete video= in configuration.
- Fix console baudrate specification.
- Remove redundant CONFIG_SYS_MMC_ENV_DEV define and add some clarifying
comment.
- Fix product name being Colibri iMX8X in a comment.
- Remove obsolete CONFIG_NR_DRAM_BANKS.
Changes in v4:
- Fixed SPDX as well as using SZ_ macros where applicable as suggested
by Igor.
- Fixed superfluous trailing line continuation introduced by commit
0d331c035a09 ("imx: support i.MX8QM MEK board") in the Makefile plus
sorted stuff alphabetically again.
- Applied changes similar to commit 3b9ac5415084 ("imx: 8qxp_mek: fix
fdt_file and console"). However, note that using ${baudrate} in
console= like that won't actually work!
- Applied changes similar to commit e5b8f7e665aa ("imx8qxp: mek: enable
dm-spl for pm").
Changes in v3:
- Added Igor's reviewed-by tag.
Changes in v2:
- Changed imx-atf git clone command to include initial branch
information as suggested by Igor.
- Sorted board file includes alphabetically as suggested by Igor.
- Got rid of SPL configuration in legacy header file as suggested by
Igor and the whole use of SPL on i.MX 8X anyway neither works well
nor makes any much sense at all.
Marcel Ziswiler (2):
imx: fix building for i.mx8 without spl
board: toradex: add colibri imx8qxp 2gb wb it v1.0b module support
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi | 117 +++
arch/arm/dts/fsl-imx8qxp-colibri.dts | 328 ++
arch/arm/mach-imx/Makefile| 2 +
arch/arm/mach-imx/imx8/Kconfig| 12 +-
board/toradex/colibri-imx8qxp/Kconfig | 30 ++
board/toradex/colibri-imx8qxp/MAINTAINERS | 9 +
board/toradex/colibri-imx8qxp/Makefile| 6 +
board/toradex/colibri-imx8qxp/README | 66
.../toradex/colibri-imx8qxp/colibri-imx8qxp.c | 160 +
board/toradex/colibri-imx8qxp/imximage.cfg| 24 ++
configs/colibri-imx8qxp_defconfig | 53 +++
include/configs/colibri-imx8qxp.h | 210 +++
13 files changed, 1016 insertions(+), 4 deletions(-)
create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri-u-boot.dtsi
create mode 100644 arch/arm/dts/fsl-imx8qxp-colibri.dts
create mode 100644 board/toradex/colibri-imx8qxp/Kconfig
create mode 100644 board/toradex/colibri-imx8qxp/MAINTAINERS
create mode 100644 board/toradex/colibri-imx8qxp/Makefile
create mode 100644 board/toradex/colibri-imx8qxp/README
create mode 100644 board/toradex/colibri-imx8qxp/colibri-imx8qxp.c
create mode 100644 board/toradex/colibri-imx8qxp/imximage.cfg
create mode 100644 configs/colibri-imx8qxp_defconfig
create mode 100644 include/configs/colibri-imx8qxp.h
--
2.20.1
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[U-Boot] [PATCH v6 1/2] imx: fix building for i.mx8 without spl
From: Marcel Ziswiler
Building with Travis CI complained and stopped with the following error:
+cc1: fatal error: opening output file spl/u-boot-spl.cfgout: No such
file or directory
+compilation terminated.
This fixes commit caceb739ea07 ("imx: build flash.bin for i.MX8") which
took SPL being enabled on i.MX8 for granted.
Reported-by: Stefano Babic
Signed-off-by: Marcel Ziswiler
Reviewed-by: Peng Fan
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/mach-imx/Makefile | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 37675d0558..6531c67fc6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -107,7 +107,9 @@ IMX_CONFIG = $(CONFIG_IMX_CONFIG:"%"=%)
ifeq ($(CONFIG_ARCH_IMX8), y)
CNTR_DEPFILES := $(srctree)/tools/imx_cntr_image.sh
IMAGE_TYPE := imx8image
+ifeq ($(CONFIG_SPL_BUILD),y)
SPL_DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o
spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG); if [ -f spl/u-boot-spl.cfgout
]; then $(CNTR_DEPFILES) spl/u-boot-spl.cfgout; echo $$?; fi)
+endif
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout
$(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES)
u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
--
2.20.1
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[U-Boot] [PATCH] board: toradex: drop support.arm maintainer email
From: Marcel Ziswiler Drop Toradex ARM Support from maintainer email list as this just clogs our support ticketing system. Signed-off-by: Marcel Ziswiler Acked-by: Stefan Agner --- board/toradex/colibri-imx6ull/MAINTAINERS | 1 - board/toradex/colibri_imx7/MAINTAINERS| 1 - 2 files changed, 2 deletions(-) diff --git a/board/toradex/colibri-imx6ull/MAINTAINERS b/board/toradex/colibri-imx6ull/MAINTAINERS index 7cda555984..626c1f94f9 100644 --- a/board/toradex/colibri-imx6ull/MAINTAINERS +++ b/board/toradex/colibri-imx6ull/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX6ULL M: Stefan Agner -M: Toradex ARM Support W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained diff --git a/board/toradex/colibri_imx7/MAINTAINERS b/board/toradex/colibri_imx7/MAINTAINERS index f55f8045f4..cd0f9c9b2d 100644 --- a/board/toradex/colibri_imx7/MAINTAINERS +++ b/board/toradex/colibri_imx7/MAINTAINERS @@ -1,6 +1,5 @@ Colibri iMX7 M: Stefan Agner -M: Toradex ARM Support W: http://developer.toradex.com/software/linux/linux-software W: https://www.toradex.com/community S: Maintained -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 09/17] arm: mvebu: turris_omnia: move ATSHA204A from defconfig to Kconfig
This driver is required for Turris Omnia to read ethernet addresses.
Move the dependency from turris_omnia_defconfig to Kconfig.
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
arch/arm/mach-mvebu/Kconfig | 1 +
board/CZ.NIC/turris_omnia/turris_omnia.c | 11 ---
configs/turris_omnia_defconfig | 1 -
3 files changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 2bf829d10a..fc29c3b084 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -121,6 +121,7 @@ config TARGET_TURRIS_OMNIA
select I2C_MUX_PCA954x
select SPL_I2C_MUX
select SYS_I2C_MVTWSI
+ select ATSHA204A
config TARGET_TURRIS_MOX
bool "Support Turris Mox"
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index d4fb89f15f..640ee2a2a3 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -18,10 +18,7 @@
#include
#include
#include
-
-#ifdef CONFIG_ATSHA204A
# include
-#endif
#ifdef CONFIG_WDT_ORION
# include
@@ -388,7 +385,6 @@ int board_late_init(void)
return 0;
}
-#ifdef CONFIG_ATSHA204A
static struct udevice *get_atsha204a_dev(void)
{
static struct udevice *dev;
@@ -403,14 +399,12 @@ static struct udevice *get_atsha204a_dev(void)
return dev;
}
-#endif
int checkboard(void)
{
u32 version_num, serial_num;
int err = 1;
-#ifdef CONFIG_ATSHA204A
struct udevice *dev = get_atsha204a_dev();
if (dev) {
@@ -434,8 +428,6 @@ int checkboard(void)
}
out:
-#endif
-
if (err)
printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
else
@@ -458,7 +450,6 @@ static void increment_mac(u8 *mac)
int misc_init_r(void)
{
-#ifdef CONFIG_ATSHA204A
int err;
struct udevice *dev = get_atsha204a_dev();
u8 mac0[4], mac1[4], mac[6];
@@ -503,8 +494,6 @@ int misc_init_r(void)
eth_env_set_enetaddr("eth2addr", mac);
out:
-#endif
-
return 0;
}
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index 5086da13a5..5a09dc3033 100644
--- a/configs/turris_omnia_defconfig
+++ b/configs/turris_omnia_defconfig
@@ -47,7 +47,6 @@ CONFIG_AHCI_MVEBU=y
CONFIG_SATA=y
CONFIG_SCSI=y
CONFIG_SCSI_AHCI=y
-CONFIG_ATSHA204A=y
CONFIG_DM_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_MV=y
--
2.21.0
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[U-Boot] [PATCH u-boot-marvell v3 07/17] arm: mvebu: turris_omnia: refactor I2C accessing code
Refactor code which accesses the microcontroller and EEPROM via I2C.
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 205 ---
1 file changed, 109 insertions(+), 96 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 055ebad000..6b8fa53c98 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -32,18 +32,25 @@
DECLARE_GLOBAL_DATA_PTR;
-#define OMNIA_I2C_EEPROM_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
-#define OMNIA_I2C_EEPROM 0x54
-#define OMNIA_I2C_EEPROM_CONFIG_ADDR 0x0
-#define OMNIA_I2C_EEPROM_ADDRLEN 2
+#define OMNIA_I2C_BUS_NAME "i2c@11000->i2cmux@70->i2c@0"
+
+#define OMNIA_I2C_MCU_CHIP_ADDR0x2a
+#define OMNIA_I2C_MCU_CHIP_LEN 1
+
+#define OMNIA_I2C_EEPROM_CHIP_ADDR 0x54
+#define OMNIA_I2C_EEPROM_CHIP_LEN 2
#define OMNIA_I2C_EEPROM_MAGIC 0x0341a034
-#define OMNIA_I2C_MCU_DM_NAME "i2c@11000->i2cmux@70->i2c@0"
-#define OMNIA_I2C_MCU_ADDR_STATUS 0x1
-#define OMNIA_I2C_MCU_SATA 0x20
-#define OMNIA_I2C_MCU_CARDDET 0x10
-#define OMNIA_I2C_MCU 0x2a
-#define OMNIA_I2C_MCU_WDT_ADDR 0x0b
+enum mcu_commands {
+ CMD_GET_STATUS_WORD = 0x01,
+ CMD_GET_RESET = 0x09,
+ CMD_WATCHDOG_STATE = 0x0b,
+};
+
+enum status_word_bits {
+ CARD_DET_STSBIT = 0x0010,
+ MSATA_IND_STSBIT= 0x0020,
+};
#define OMNIA_ATSHA204_OTP_VERSION 0
#define OMNIA_ATSHA204_OTP_SERIAL 1
@@ -85,48 +92,97 @@ static struct serdes_map board_serdes_map_sata[] = {
{SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}
};
-static bool omnia_detect_sata(void)
+static struct udevice *omnia_get_i2c_chip(const char *name, uint addr,
+ uint offset_len)
{
struct udevice *bus, *dev;
- int ret, retry = 3;
- u16 mode;
-
- puts("SERDES0 card detect: ");
+ int ret;
- if (uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_MCU_DM_NAME, &bus))
{
- puts("Cannot find MCU bus!\n");
- return false;
+ ret = uclass_get_device_by_name(UCLASS_I2C, OMNIA_I2C_BUS_NAME, &bus);
+ if (ret) {
+ printf("Cannot get I2C bus %s: uclass_get_device_by_name
failed: %i\n",
+ OMNIA_I2C_BUS_NAME, ret);
+ return NULL;
}
- ret = i2c_get_chip(bus, OMNIA_I2C_MCU, 1, &dev);
+ ret = i2c_get_chip(bus, addr, offset_len, &dev);
if (ret) {
- puts("Cannot get MCU chip!\n");
- return false;
+ printf("Cannot get %s I2C chip: i2c_get_chip failed: %i\n",
+ name, ret);
+ return NULL;
}
- for (; retry > 0; --retry) {
- ret = dm_i2c_read(dev, OMNIA_I2C_MCU_ADDR_STATUS, (uchar *)
&mode, 2);
- if (!ret)
- break;
- }
+ return dev;
+}
+
+static int omnia_mcu_read(u8 cmd, void *buf, int len)
+{
+ struct udevice *chip;
+
+ chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+ OMNIA_I2C_MCU_CHIP_LEN);
+ if (!chip)
+ return -ENODEV;
+
+ return dm_i2c_read(chip, cmd, buf, len);
+}
- if (!retry) {
- puts("I2C read failed! Default PEX\n");
+#ifndef CONFIG_SPL_BUILD
+static int omnia_mcu_write(u8 cmd, const void *buf, int len)
+{
+ struct udevice *chip;
+
+ chip = omnia_get_i2c_chip("MCU", OMNIA_I2C_MCU_CHIP_ADDR,
+ OMNIA_I2C_MCU_CHIP_LEN);
+ if (!chip)
+ return -ENODEV;
+
+ return dm_i2c_write(chip, cmd, buf, len);
+}
+
+static bool disable_mcu_watchdog(void)
+{
+ int ret;
+
+ puts("Disabling MCU watchdog... ");
+
+ ret = omnia_mcu_write(CMD_WATCHDOG_STATE, "\x00", 1);
+ if (ret) {
+ printf("omnia_mcu_write failed: %i\n", ret);
return false;
}
- if (!(mode & OMNIA_I2C_MCU_CARDDET)) {
- puts("NONE\n");
+ puts("disabled\n");
+
+ return true;
+}
+#endif
+
+static bool omnia_detect_sata(void)
+{
+ int ret;
+ u16 stsword;
+
+ puts("MiniPCIe/mSATA card detection... ");
+
+ ret = omnia_mcu_read(CMD_GET_STATUS_WORD, &stsword, sizeof(stsword));
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, defaulting to MiniPCIe
card\n",
+ ret);
return false;
}
- if (mode & OMNIA_I2C_MCU_SATA) {
- puts("SATA\n");
- return true;
- } else {
- puts("PEX\n");
+ if (!(stsword & CARD_DET_STSBIT)) {
+ puts("none\n");
return false;
[U-Boot] [PATCH u-boot-marvell v3 12/17] arm: mvebu: turris_*: remove watchdog include
Since board watchdog is now unified and not handled in board files, remove the unnecessary includes. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_mox/turris_mox.c | 4 board/CZ.NIC/turris_omnia/turris_omnia.c | 4 2 files changed, 8 deletions(-) diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 8a4872343b..3818e3752a 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -16,10 +16,6 @@ #include #include -#ifdef CONFIG_WDT_ARMADA_37XX -#include -#endif - #include "mox_sp.h" #define MAX_MOX_MODULES10 diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index 54efd2d4c9..b073a985a5 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -20,10 +20,6 @@ #include # include -#ifdef CONFIG_WDT_ORION -# include -#endif - #include "../drivers/ddr/marvell/a38x/ddr3_init.h" #include <../serdes/a38x/high_speed_env_spec.h> -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 06/17] arm: mvebu: turris_omnia: add SCSI as boot target
If SCSI is enabled, U-Boot should try to boot also from SCSI device on Turris Omnia. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- include/configs/turris_omnia.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 5a7539c9be..5b9639e050 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -90,9 +90,16 @@ #define BOOT_TARGET_DEVICES_USB(func) #endif +#ifdef CONFIG_SCSI +#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) +#else +#define BOOT_TARGET_DEVICES_SCSI(func) +#endif + #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_USB(func) \ + BOOT_TARGET_DEVICES_SCSI(func) \ func(PXE, pxe, na) \ func(DHCP, dhcp, na) -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 13/17] arm: mvebu: turris_omnia: fix regdomain env var setting
The regdomain environment variable is set according to value read from EEPROM. This has to be done in board_late_init, after the environment variables are read from SPI. Select CONFIG_BOARD_LATE_INIT in Kconfig for the Turris Omnia target. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- board/CZ.NIC/turris_omnia/turris_omnia.c | 1 - 1 file changed, 1 deletion(-) diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c b/board/CZ.NIC/turris_omnia/turris_omnia.c index b073a985a5..af43ee23d9 100644 --- a/board/CZ.NIC/turris_omnia/turris_omnia.c +++ b/board/CZ.NIC/turris_omnia/turris_omnia.c @@ -364,7 +364,6 @@ int board_init(void) #ifndef CONFIG_SPL_BUILD disable_mcu_watchdog(); - set_regdomain(); #endif return 0; -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 08/17] arm: mvebu: turris_omnia: fix checkpatch warnings
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 6b8fa53c98..d4fb89f15f 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -290,12 +290,12 @@ static struct mv_ddr_topology_map board_topology_map_2g =
{
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
- static int mem = 0;
+ static int mem;
struct omnia_eeprom oep;
/* Get the board config from EEPROM */
- if (mem == 0) {
- if(!omnia_read_eeprom(&oep))
+ if (!mem) {
+ if (!omnia_read_eeprom(&oep))
goto out;
printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
@@ -368,7 +368,7 @@ int board_early_init_f(void)
int board_init(void)
{
- /* adress of boot parameters */
+ /* address of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
#ifndef CONFIG_SPL_BUILD
@@ -391,9 +391,9 @@ int board_late_init(void)
#ifdef CONFIG_ATSHA204A
static struct udevice *get_atsha204a_dev(void)
{
- static struct udevice *dev = NULL;
+ static struct udevice *dev;
- if (dev != NULL)
+ if (dev)
return dev;
if (uclass_get_device_by_name(UCLASS_MISC, "atsha204a@64", &dev)) {
@@ -420,13 +420,13 @@ int checkboard(void)
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
OMNIA_ATSHA204_OTP_VERSION,
-(u8 *) &version_num);
+(u8 *)&version_num);
if (err)
goto out;
err = atsha204a_read(dev, ATSHA204A_ZONE_OTP, false,
OMNIA_ATSHA204_OTP_SERIAL,
-(u8 *) &serial_num);
+(u8 *)&serial_num);
if (err)
goto out;
--
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[U-Boot] [PATCH u-boot-marvell v3 10/17] arm: mvebu: turris_omnia: refactor more code
Refactor RAM size reading from EEPROM in preparation for next patch.
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 58
1 file changed, 28 insertions(+), 30 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 640ee2a2a3..8571541b0a 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -236,6 +236,31 @@ static bool omnia_read_eeprom(struct omnia_eeprom *oep)
return true;
}
+static int omnia_get_ram_size_gb(void)
+{
+ static int ram_size;
+ struct omnia_eeprom oep;
+
+ if (!ram_size) {
+ /* Get the board config from EEPROM */
+ if (omnia_read_eeprom(&oep)) {
+ debug("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
+
+ if (oep.ramsize == 0x2)
+ ram_size = 2;
+ else
+ ram_size = 1;
+ } else {
+ /* Hardcoded fallback */
+ puts("Memory config from EEPROM read failed!\n");
+ puts("Falling back to default 1 GiB!\n");
+ ram_size = 1;
+ }
+ }
+
+ return ram_size;
+}
+
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure
@@ -287,37 +312,10 @@ static struct mv_ddr_topology_map board_topology_map_2g =
{
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
{
- static int mem;
- struct omnia_eeprom oep;
-
- /* Get the board config from EEPROM */
- if (!mem) {
- if (!omnia_read_eeprom(&oep))
- goto out;
-
- printf("Memory config in EEPROM: 0x%02x\n", oep.ramsize);
-
- if (oep.ramsize == 0x2)
- mem = 2;
- else
- mem = 1;
- }
-
-out:
- /* Hardcoded fallback */
- if (mem == 0) {
- puts("WARNING: Memory config from EEPROM read failed.\n");
- puts("Falling back to default 1GiB map.\n");
- mem = 1;
- }
-
- /* Return the board topology as defined in the board code */
- if (mem == 1)
- return &board_topology_map_1g;
- if (mem == 2)
+ if (omnia_get_ram_size_gb() == 2)
return &board_topology_map_2g;
-
- return &board_topology_map_1g;
+ else
+ return &board_topology_map_1g;
}
#ifndef CONFIG_SPL_BUILD
--
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[U-Boot] [PATCH u-boot-marvell v3 11/17] arm: mvebu: turris_omnia: print board info as Turris Mox
Unify the way how Omnia and Mox print board information (RAM size and
serial number).
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 8571541b0a..54efd2d4c9 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -426,11 +426,13 @@ int checkboard(void)
}
out:
+ printf("Turris Omnia:\n");
+ printf(" RAM size: %i MiB\n", omnia_get_ram_size_gb() * 1024);
if (err)
- printf("Board: Turris Omnia (ver N/A). SN: N/A\n");
+ printf(" Serial Number: unknown\n");
else
- printf("Board: Turris Omnia SNL %08X%08X\n",
- be32_to_cpu(version_num), be32_to_cpu(serial_num));
+ printf(" Serial Number: %08X%08X\n", be32_to_cpu(version_num),
+ be32_to_cpu(serial_num));
return 0;
}
--
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[U-Boot] [PATCH u-boot-marvell v3 17/17] arm: mvebu: turris_omnia: enable defconfig options needed by vendor
This options will be enabled by default by CZ.NIC shipped U-Boot. Enable them in defconfig. Signed-off-by: Marek Behún --- configs/turris_omnia_defconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index bba14bbcaf..f3ce56f6d7 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -22,6 +22,15 @@ CONFIG_MISC_INIT_R=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y +CONFIG_FIT=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +# CONFIG_FIT_SIGNATURE is not set +CONFIG_FIT_VERBOSE=y +# CONFIG_FIT_BEST_MATCH is not set +CONFIG_CMD_LZMADEC=y +CONFIG_CMD_AES=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SHA1SUM=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 05/17] arm: mvebu: turris_omnia: move I2C dependencies to Kconfig
The I2C dependencies are defined in include/configs/turris_omnia.h, because Turris Omnia won't boot correctly without I2C support. Move these dependencies to Kconfig, so that they are selected if Turris Omnia is selected as target. Signed-off-by: Marek Behún Reviewed-by: Heiko Schocher Reviewed-by: Stefan Roese --- arch/arm/mach-mvebu/Kconfig| 5 + include/configs/turris_omnia.h | 11 --- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index f99bd3bf65..2bf829d10a 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -116,6 +116,11 @@ config TARGET_DB_88F6820_AMC config TARGET_TURRIS_OMNIA bool "Support Turris Omnia" select 88F6820 + select DM_I2C + select I2C_MUX + select I2C_MUX_PCA954x + select SPL_I2C_MUX + select SYS_I2C_MVTWSI config TARGET_TURRIS_MOX bool "Support Turris Mox" diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 5e692e6829..5a7539c9be 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -18,17 +18,6 @@ */ #define CONFIG_SYS_TCLK25000 /* 250MHz */ -/* - * Commands configuration - */ - -/* I2C support */ -#define CONFIG_DM_I2C -#define CONFIG_I2C_MUX -#define CONFIG_I2C_MUX_PCA954x -#define CONFIG_SPL_I2C_MUX -#define CONFIG_SYS_I2C_MVTWSI - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 16/17] arm: mvebu: turris_omnia: add GPIO support to defconfig
Add support for the gpio command and driver for the I2C connected pca9538 controller, to be able to determine if SFP module is present in the Turris Omnia router. Signed-off-by: Marek Behún --- configs/turris_omnia_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 5a09dc3033..bba14bbcaf 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -23,6 +23,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_I2C_SUPPORT=y CONFIG_SPL_SPI_LOAD=y # CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y @@ -47,6 +48,10 @@ CONFIG_AHCI_MVEBU=y CONFIG_SATA=y CONFIG_SCSI=y CONFIG_SCSI_AHCI=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_DM_GPIO=y +# CONFIG_MVEBU_GPIO is not set +CONFIG_DM_PCA953X=y CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MV=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 15/17] i2c: mvtwsi: fix reading status register after interrupt
The twsi_wait function reads the control register for interrupt flag,
and if interrupt flag is present, it immediately reads status register.
On our device this sometimes causes bad value being read from status
register, as if the value was not yet updated.
My theory is that the controller does approximately this:
1. sets interrupt flag in control register,
2. sets the value of status register,
3. causes an interrupt
In U-Boot we do not use interrupts, so I think that it is possible that
sometimes the status register in the twsi_wait function is read between
points 1 and 2.
The bug does not appear if I add a small delay before reading status
register.
Wait 100ns (which in U-Boot currently means 1 us, because ndelay(i)
function calls udelay(DIV_ROUND_UP(i, 1000))) before reading the status
register.
Signed-off-by: Marek Behún
Reviewed-by: Heiko Schocher
Reviewed-by: Stefan Roese
Cc: Mario Six
Cc: Baruch Siach
---
drivers/i2c/mvtwsi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 74ac0a4aa7..0a2dafcec6 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -271,6 +271,17 @@ static int twsi_wait(struct mvtwsi_registers *twsi, int
expected_status,
do {
control = readl(&twsi->control);
if (control & MVTWSI_CONTROL_IFLG) {
+ /*
+* On Armada 38x it seems that the controller works as
+* if it first set the MVTWSI_CONTROL_IFLAG in the
+* control register and only after that it changed the
+* status register.
+* This sometimes caused weird bugs which only appeared
+* on selected I2C speeds and even then only sometimes.
+* We therefore add here a simple ndealy(100), which
+* seems to fix this weird bug.
+*/
+ ndelay(100);
status = readl(&twsi->status);
if (status == expected_status)
return 0;
--
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[U-Boot] [PATCH u-boot-marvell v3 14/17] arm: mvebu: turris_omnia: add RESET button handling
There is a Factory RESET button on the back side of the Turris Omnia
router. When user presses this button before powering the device up and
keeps it pressed, the microcontroller prevents the main CPU from booting
and counts how long the RESET button is being pressed (and indicates
this by lighting up front LEDs).
The idea behind this is that the user can boot the device into several
Factory RESET modes.
This patch adds support for U-Boot to read into which Factory RESET mode
the user booted the device. The value is an integer stored into the
omnia_reset environment variable. It is 0 if the button was not pressed
at all during power up, otherwise it is the number identifying the
Factory RESET mode.
This patch also changes bootcmd to a special hardcoded value if Factory
RESET button was pressed during device powerup. This special bootcmd
value sets the colors of all the LEDs on the front panel to green and
then tries to load the rescue image from the SPI flash memory and boot
it.
Signed-off-by: Marek Behún
---
arch/arm/mach-mvebu/Kconfig | 1 +
board/CZ.NIC/turris_omnia/turris_omnia.c | 38
2 files changed, 39 insertions(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index fc29c3b084..a832e1dc8c 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -116,6 +116,7 @@ config TARGET_DB_88F6820_AMC
config TARGET_TURRIS_OMNIA
bool "Support Turris Omnia"
select 88F6820
+ select BOARD_LATE_INIT
select DM_I2C
select I2C_MUX
select I2C_MUX_PCA954x
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index af43ee23d9..ad6e29021e 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -328,6 +328,43 @@ static int set_regdomain(void)
printf("Regdomain set to %s\n", rd);
return env_set("regdomain", rd);
}
+
+/*
+ * default factory reset bootcommand on Omnia first sets all the front LEDs
+ * to green and then tries to load the rescue image from SPI flash memory and
+ * boot it
+ */
+#define OMNIA_FACTORY_RESET_BOOTCMD \
+ "i2c dev 2; " \
+ "i2c mw 0x2a.1 0x3 0x1c 1; " \
+ "i2c mw 0x2a.1 0x4 0x1c 1; " \
+ "mw.l 0x0100 0x00ff000c; " \
+ "i2c write 0x0100 0x2a.1 0x5 4 -s; " \
+ "setenv bootargs \"$bootargs omniarescue=$omnia_reset\"; " \
+ "sf probe; " \
+ "sf read 0x100 0x10 0x70; " \
+ "bootm 0x100; " \
+ "bootz 0x100"
+
+static void handle_reset_button(void)
+{
+ int ret;
+ u8 reset_status;
+
+ ret = omnia_mcu_read(CMD_GET_RESET, &reset_status, 1);
+ if (ret) {
+ printf("omnia_mcu_read failed: %i, reset status unknown!\n",
+ ret);
+ return;
+ }
+
+ env_set_ulong("omnia_reset", reset_status);
+
+ if (reset_status) {
+ printf("RESET button was pressed, overwriting bootcmd!\n");
+ env_set("bootcmd", OMNIA_FACTORY_RESET_BOOTCMD);
+ }
+}
#endif
int board_early_init_f(void)
@@ -373,6 +410,7 @@ int board_late_init(void)
{
#ifndef CONFIG_SPL_BUILD
set_regdomain();
+ handle_reset_button();
#endif
return 0;
--
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[U-Boot] [PATCH u-boot-marvell v3 03/17] arm: mvebu: turris_omnia: use AHCI and SATA driver model
Enable AHCI, SCSI and SATA for compliance with the driver model migration. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_omnia_defconfig | 7 +++ 1 file changed, 7 insertions(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index 2ad2f6e431..5086da13a5 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -26,6 +26,8 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +CONFIG_CMD_SATA=y +CONFIG_CMD_SCSI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -39,6 +41,11 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_USE_ENV_SPI_MAX_HZ=y CONFIG_ENV_SPI_MAX_HZ=5000 CONFIG_SPL_OF_TRANSLATE=y +CONFIG_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_AHCI_MVEBU=y +CONFIG_SATA=y +CONFIG_SCSI=y CONFIG_SCSI_AHCI=y CONFIG_ATSHA204A=y CONFIG_DM_MMC=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 01/17] arm: mvebu: turris_omnia: remove redundant code
The i2c slave disabling is done by mvtwsi driver and is not needed here.
Signed-off-by: Marek Behún
Acked-by: Heiko Schocher
Reviewed-by: Stefan Roese
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index 4c08f810a2..055ebad000 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -50,8 +50,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define OMNIA_ATSHA204_OTP_MAC03
#define OMNIA_ATSHA204_OTP_MAC14
-#define MVTWSI_ARMADA_DEBUG_REG0x8c
-
/*
* Those values and defines are taken from the Marvell U-Boot version
* "u-boot-2013.01-2014_T3.0"
@@ -297,8 +295,6 @@ static int set_regdomain(void)
int board_early_init_f(void)
{
- u32 i2c_debug_reg;
-
/* Configure MPP */
writel(0x, MVEBU_MPP_BASE + 0x00);
writel(0x, MVEBU_MPP_BASE + 0x04);
@@ -321,15 +317,6 @@ int board_early_init_f(void)
writel(OMNIA_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
writel(OMNIA_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
- /*
-* Disable I2C debug mode blocking 0x64 I2C address.
-* Note: that would be redundant once Turris Omnia migrates to DM_I2C,
-* because the mvtwsi driver includes equivalent code.
-*/
- i2c_debug_reg = readl(MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
- i2c_debug_reg &= ~(1<<18);
- writel(i2c_debug_reg, MVEBU_TWSI_BASE + MVTWSI_ARMADA_DEBUG_REG);
-
return 0;
}
--
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[U-Boot] [PATCH u-boot-marvell v3 04/17] arm: mvebu: turris_omnia: remove legacy macros from board header
These are not needed if MMC and SCSI DM drivers are used. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- include/configs/turris_omnia.h | 14 -- 1 file changed, 14 deletions(-) diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h index 0e65a12345..5e692e6829 100644 --- a/include/configs/turris_omnia.h +++ b/include/configs/turris_omnia.h @@ -29,20 +29,6 @@ #define CONFIG_SPL_I2C_MUX #define CONFIG_SYS_I2C_MVTWSI -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASEMVEBU_SDIO_BASE - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID2 -#define CONFIG_SYS_SCSI_MAX_LUN1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ -CONFIG_SYS_SCSI_MAX_LUN) - /* USB/EHCI configuration */ #define CONFIG_EHCI_IS_TDI -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 00/17] Fixes for Turris Omnia
Hi, this is the third version of my fixes for Turris Omnia. Added since v2: - patch 16: adds GPIO support so that boot script can recognize if SFP module is inserted and select appropriate device tree for kernel - patch 17: enable CONFIG_FIT and other options needed by vendor Changes since v2: - added Reviewed-by tags for first 13 patches (sorry Stefan, I already did it before reading your email that Patchwork does this automatically) - patch 14 (Factory RESET button handling): remove the Kconfig options, this functionality is now always enabled - patch 15: added comment as requested by Heiko Marek Behún (17): arm: mvebu: turris_omnia: remove redundant code arm: mvebu: turris_omnia: add XHCI to defconfig arm: mvebu: turris_omnia: use AHCI and SATA driver model arm: mvebu: turris_omnia: remove legacy macros from board header arm: mvebu: turris_omnia: move I2C dependencies to Kconfig arm: mvebu: turris_omnia: add SCSI as boot target arm: mvebu: turris_omnia: refactor I2C accessing code arm: mvebu: turris_omnia: fix checkpatch warnings arm: mvebu: turris_omnia: move ATSHA204A from defconfig to Kconfig arm: mvebu: turris_omnia: refactor more code arm: mvebu: turris_omnia: print board info as Turris Mox arm: mvebu: turris_*: remove watchdog include arm: mvebu: turris_omnia: fix regdomain env var setting arm: mvebu: turris_omnia: add RESET button handling i2c: mvtwsi: fix reading status register after interrupt arm: mvebu: turris_omnia: add GPIO support to defconfig arm: mvebu: turris_omnia: enable defconfig options needed by vendor arch/arm/mach-mvebu/Kconfig | 7 + board/CZ.NIC/turris_mox/turris_mox.c | 4 - board/CZ.NIC/turris_omnia/turris_omnia.c | 348 --- configs/turris_omnia_defconfig | 24 +- drivers/i2c/mvtwsi.c | 11 + include/configs/turris_omnia.h | 32 +-- 6 files changed, 233 insertions(+), 193 deletions(-) -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH u-boot-marvell v3 02/17] arm: mvebu: turris_omnia: add XHCI to defconfig
Add XHCI_HOST and XHCI_MVEBU to defconfig, so that user's can by default boot from USB on Turris Omnia. Signed-off-by: Marek Behún Reviewed-by: Stefan Roese --- configs/turris_omnia_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig index a528a9b5bc..2ad2f6e431 100644 --- a/configs/turris_omnia_defconfig +++ b/configs/turris_omnia_defconfig @@ -58,5 +58,7 @@ CONFIG_KIRKWOOD_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MVEBU=y CONFIG_WDT=y CONFIG_WDT_ORION=y -- 2.21.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3] ARM: am335x: Add phyCORE AM335x R2 support
On 5/2/19 11:52 AM, Niel Fourie wrote:
[...]
> +++ b/board/phytec/phycore_am335x_r2/board.c
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * board.c
> + *
> + * Board functions for Phytec phyCORE-AM335x R2 (pcl060) based boards
> + *
> + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
> + * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
> + * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
> + * Copyright (C) 2019 DENX Software Engineering GmbH
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "board.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_SPL_BUILD
> +
> +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
> +
> +#if CONFIG_IS_ENABLED(OS_BOOT)
> +int spl_start_uboot(void)
> +{
> + return 1;
Can this be removed completely ?
> +}
> +#endif
> +
> +/* DDR RAM defines */
> +#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
> +
> +#define OSC (V_OSCK / 100)
> +const struct dpll_params dpll_ddr = {
> + DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
> +
> +const struct dpll_params *get_dpll_ddr_params(void)
> +{
> + return &dpll_ddr;
> +}
> +
> +const struct ctrl_ioregs ioregs = {
> + .cm0ioctl = 0x18B,
> + .cm1ioctl = 0x18B,
> + .cm2ioctl = 0x18B,
> + .dt0ioctl = 0x18B,
> + .dt1ioctl = 0x18B,
> +};
> +
> +static const struct cmd_control ddr3_cmd_ctrl_data = {
> + .cmd0csratio = 0x80,
> + .cmd0iclkout = 0x0,
> +
> + .cmd1csratio = 0x80,
> + .cmd1iclkout = 0x0,
> +
> + .cmd2csratio = 0x80,
> + .cmd2iclkout = 0x0,
> +};
> +
> +enum {
> + PHYCORE_R2_MT41K128M16JT_256MB,
> + PHYCORE_R2_MT41K256M16TW107IT_512MB,
> + PHYCORE_R2_MT41K512M16HA125IT_1024MB,
> +};
> +
> +struct am335x_sdram_timings {
> + struct emif_regs ddr3_emif_reg_data;
> + struct ddr_data ddr3_data;
> +};
> +
> +static struct am335x_sdram_timings physom_timings[] = {
> + [PHYCORE_R2_MT41K128M16JT_256MB] = {
> + .ddr3_emif_reg_data = {
> + .sdram_config = 0x61C052B2,
> + .ref_ctrl = 0x0C30,
> + .sdram_tim1 = 0x0AAAD4DB,
> + .sdram_tim2 = 0x26437FDA,
> + .sdram_tim3 = 0x501F83FF,
> + .zq_config = 0x50074BE4,
> + .emif_ddr_phy_ctlr_1 = 0x7,
> + .ocp_config = 0x003d3d3d,
There's one tab too many .
> + },
> + .ddr3_data = {
> + .datardsratio0 = 0x36,
> + .datawdsratio0 = 0x38,
> + .datafwsratio0 = 0x99,
> + .datawrsratio0 = 0x73,
> + },
> + },
[...]
> +void scale_vcores_generic(int freq)
> +{
> + int sil_rev, mpu_vdd;
> +
> + /*
> + * We use a TPS65910 PMIC. For all MPU frequencies we support we use a
> + * CORE voltage of 1.10V. For MPU voltage we need to switch based on
> + * the frequency we are running at.
> + */
> +#if defined(CONFIG_DM_I2C)
Can we not support non-DM i2c ?
> + if (power_tps65910_init(0))
> + return;
> +#else
And drop this part ?
> + if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
> + return;
> +#endif
[...]
--
Best regards,
Marek Vasut
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Re: [U-Boot] WaRP7 nok on master
Hi Lukas, On Thu, May 2, 2019 at 7:21 AM Auer, Lukas wrote: > I was able to reproduce the issue on my side. With the patch, U-Boot > probes the drivers for devices under simple-bus device tree nodes in > the pre-relocation device model. The default value of > CONFIG_SYS_MALLOC_LEN (0x400) leaves U-Boot with not enough memory to > do this, causing it to hang. If it is increased, for example to 0x1000, > everything works again. > > Let me know, how you want to fix this. If you want, I can send a patch > to increase CONFIG_SYS_MALLOC_LEN for the i.MX parts. I guess you mean CONFIG_SYS_MALLOC_F_LEN instead? Could you please send a patch setting CONFIG_SYS_MALLOC_F_LEN as 0x2000 by default for i.MX? 0x1000 seems not to be enough: http://git.denx.de/?p=u-boot.git;a=commitdiff;h=8b9cba0295dcdce5eb8bb10d79f6dafb5a167349;hp=b7de88cd5cb8c213fb158b37fcf0662c1d2332cd ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] cmd: pxe: add board specific PXE default path
The list of PXE default paths contains ARCH and SOC specific paths, but
one PXE server can serve different board with the same ARCH and SOC.
This is the case for Turris Omnia and Turris Mox, where ARCH=arm and
SOC=mvebu.
If CONFIG_SYS_BOARD is defined, also try "default-$ARCH-$SOC-$BOARD"
path.
Signed-off-by: Marek Behún
---
cmd/pxe.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/cmd/pxe.c b/cmd/pxe.c
index 274555319b..127751642e 100644
--- a/cmd/pxe.c
+++ b/cmd/pxe.c
@@ -22,6 +22,9 @@
const char *pxe_default_paths[] = {
#ifdef CONFIG_SYS_SOC
+#ifdef CONFIG_SYS_BOARD
+ "default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC "-" CONFIG_SYS_BOARD,
+#endif
"default-" CONFIG_SYS_ARCH "-" CONFIG_SYS_SOC,
#endif
"default-" CONFIG_SYS_ARCH,
--
2.21.0
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[U-Boot] [PATCH] fs: btrfs: fix btrfs methods return values on failure
The btrfs implementation methods .ls(), .size() and .read() returns 1 on
failure, but the command handlers expect values <0 on failure.
For example if given a nonexistent path, the load command currently
returns success, and hush scripting does not work.
Fix this by setting return values of these methods to -1 instead of 1 on
failure.
Signed-off-by: Marek Behún
---
fs/btrfs/btrfs.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/fs/btrfs/btrfs.c b/fs/btrfs/btrfs.c
index 6f35854823..cb7e182742 100644
--- a/fs/btrfs/btrfs.c
+++ b/fs/btrfs/btrfs.c
@@ -119,17 +119,17 @@ int btrfs_ls(const char *path)
if (inr == -1ULL) {
printf("Cannot lookup path %s\n", path);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_DIR) {
printf("Not a directory: %s\n", path);
- return 1;
+ return -1;
}
if (btrfs_readdir(&root, inr, readdir_callback)) {
printf("An error occured while listing directory %s\n", path);
- return 1;
+ return -1;
}
return 0;
@@ -158,12 +158,12 @@ int btrfs_size(const char *file, loff_t *size)
if (inr == -1ULL) {
printf("Cannot lookup file %s\n", file);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_REG_FILE) {
printf("Not a regular file: %s\n", file);
- return 1;
+ return -1;
}
*size = inode.size;
@@ -183,12 +183,12 @@ int btrfs_read(const char *file, void *buf, loff_t
offset, loff_t len,
if (inr == -1ULL) {
printf("Cannot lookup file %s\n", file);
- return 1;
+ return -1;
}
if (type != BTRFS_FT_REG_FILE) {
printf("Not a regular file: %s\n", file);
- return 1;
+ return -1;
}
if (!len)
@@ -200,7 +200,7 @@ int btrfs_read(const char *file, void *buf, loff_t offset,
loff_t len,
rd = btrfs_file_read(&root, inr, offset, len, buf);
if (rd == -1ULL) {
printf("An error occured while reading file %s\n", file);
- return 1;
+ return -1;
}
*actread = rd;
--
2.21.0
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Re: [U-Boot] [PATCH v2] board/BuR/brsmarc1: initial commit
Hi Hannes,
On 02.05.19 14:09, Hannes Schmelzer wrote:
> This commit adds support for the B&R brsmarc1 SoM.
>
> The SoM is based on TI's AM335x SoC.
> Mainly vxWorks 6.9.4.x is running on the board,
> doing some PLC stuff on various carrier boards.
>
> Signed-off-by: Hannes Schmelzer
>
> ---
>
> Changes in v2:
> - fix style issue in arch/arm/mach-omap2/am33xx/Kconfig
> - fix SDPX tag in Make-files/rules
>
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/am335x-brsmarc1.dts | 408
> +
> arch/arm/mach-omap2/Kconfig| 1 +
> arch/arm/mach-omap2/am33xx/Kconfig | 4 +
> board/BuR/brsmarc1/Kconfig | 15 ++
> board/BuR/brsmarc1/MAINTAINERS | 6 +
> board/BuR/brsmarc1/Makefile| 10 +
> board/BuR/brsmarc1/board.c | 168 +++
> board/BuR/brsmarc1/config.mk | 33 +++
> board/BuR/brsmarc1/mux.c | 266
> configs/brsmarc1_defconfig | 107 ++
> include/configs/brsmarc1.h | 87
> 12 files changed, 1106 insertions(+)
> create mode 100644 arch/arm/dts/am335x-brsmarc1.dts
> create mode 100644 board/BuR/brsmarc1/Kconfig
> create mode 100644 board/BuR/brsmarc1/MAINTAINERS
> create mode 100644 board/BuR/brsmarc1/Makefile
> create mode 100644 board/BuR/brsmarc1/board.c
> create mode 100644 board/BuR/brsmarc1/config.mk
> create mode 100644 board/BuR/brsmarc1/mux.c
> create mode 100644 configs/brsmarc1_defconfig
> create mode 100644 include/configs/brsmarc1.h
>
> diff --git a/board/BuR/brsmarc1/mux.c b/board/BuR/brsmarc1/mux.c
> new file mode 100644
> index 000..33c214d
> --- /dev/null
> +++ b/board/BuR/brsmarc1/mux.c
> @@ -0,0 +1,266 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * mux.c
> + *
> + * Pinmux Setting for B&R BRSMARC1 Board (HW-Rev. 1)
> + *
> + * Copyright (C) 2017 Hannes Schmelzer
> + * B&R Industrial Automation GmbH - http://www.br-automation.com
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
Is there any particular reason for not using the existing pinctrl driver
to do all this pin configuration?
> +static struct module_pin_mux spi0_pin_mux[] = {
> + /* SPI0_SCLK */
> + {OFFSET(spi0_sclk), MODE(0) | PULLUDEN | RXACTIVE},
> + /* SPI0_D0 */
> + {OFFSET(spi0_d0), MODE(0) | PULLUDEN | RXACTIVE},
> + /* SPI0_D1 */
> + {OFFSET(spi0_d1), MODE(0) | PULLUDEN | RXACTIVE},
> + /* SPI0_CS0 */
> + {OFFSET(spi0_cs0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
> + /* SPI0_CS1 */
> + {OFFSET(spi0_cs1), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
> + {-1},
> +};
> +
> +static struct module_pin_mux spi1_pin_mux[] = {
> + /* SPI1_SCLK */
> + {OFFSET(mcasp0_aclkx), MODE(3) | PULLUDEN | RXACTIVE},
> + /* SPI1_D0 */
> + {OFFSET(mcasp0_fsx),MODE(3) | PULLUDEN | RXACTIVE},
> + /* SPI1_D1 */
> + {OFFSET(mcasp0_axr0), MODE(3) | PULLUDEN | RXACTIVE},
> + /* SPI1_CS0 */
> + {OFFSET(mcasp0_ahclkr), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
> + /* SPI1_CS1 */
> + {OFFSET(xdma_event_intr0), MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE},
> + {-1},
> +};
> +
> +static struct module_pin_mux dcan0_pin_mux[] = {
> + /* DCAN0 TX */
> + {OFFSET(uart1_ctsn),MODE(2) | PULLUDEN | PULLUP_EN},
> + /* DCAN0 RX */
> + {OFFSET(uart1_rtsn),MODE(2) | RXACTIVE},
> + {-1},
> +};
> +
> +static struct module_pin_mux dcan1_pin_mux[] = {
> + /* DCAN1 TX */
> + {OFFSET(uart0_ctsn),MODE(2) | PULLUDEN | PULLUP_EN},
> + /* DCAN1 RX */
> + {OFFSET(uart0_rtsn),MODE(2) | RXACTIVE},
> + {-1},
> +};
> +
> +static struct module_pin_mux gpios[] = {
> + /* GPIO0_7 - LVDS_EN */
> + {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO0_20 - BKLT_PWM (timer7) */
> + {OFFSET(xdma_event_intr1), (MODE(4) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO2_4 - DISON */
> + {OFFSET(gpmc_wen), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO1_24 - RGB_EN */
> + {OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO1_28 - nPD */
> + {OFFSET(gpmc_be1n), (MODE(7) | PULLUDEN | PULLUP_EN)},
> + /* GPIO2_5 - Watchdog */
> + {OFFSET(gpmc_be0n_cle), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO2_0 - ResetOut */
> + {OFFSET(gpmc_csn3), (MODE(7) | PULLUDEN | PULLUP_EN)},
> + /* GPIO2_2 - BKLT_EN */
> + {OFFSET(gpmc_advn_ale), (MODE(7) | PULLUDDIS | PULLDOWN_EN)},
> + /* GPIO1_17 - GPIO0 */
> + {OFFSET(gpmc_a1), (MODE(7) | PULLUDDIS | RXACTIVE)},
> + /* GPIO1_18 - GPIO1 */
> + {OFFSET(gpmc_a2), (MODE(7) | PULLUDDIS | RXACTIVE)},
> + /* GPIO1_19 - GPIO2 */
> + {OFFSET(gpmc_a3), (MODE(7) | PULLUDDIS | RXACTIVE)},
> + /* GPIO1_22 - GPIO3 */
> + {OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS | RXACTIVE)},
> + /* GPIO1_23 - GPIO4 */
> + {OFFSET
[U-Boot] [PATCH v2 4/4] lib: uuid: Fix unseeded PRNG on RANDOM_UUID=y
The random uuid values (enabled via CONFIG_RANDOM_UUID=y) on our
platform are always the same. Below is consistent on each cold boot:
=> ### interrupt autoboot
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=d117f98e-6f2c-d04b-a5b2-331a19f91cb2
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=ad5ec4b6-2d9f-8544-9417-fe3bd1c9b1b3
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=cceb0b18-39cb-d547-9db7-03b405fa77d4
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=d4981a2b-0478-544e-9607-7fd3c651068d
=> env default -a; gpt write mmc 1 $partitions; print uuid_gpt_misc
...
uuid_gpt_misc=6d6c9a36-e919-264d-a9ee-bd00379686c7
While the uuids do change on every 'gpt write' command, the values
appear to be taken from the same pool, in the same order.
Assuming U-Boot with RANDOM_UUID=y is deployed on a large number of
devices, all those devices would essentially expose the same UUID,
breaking the assumption of system/RFS/application designers who rely
on UUID as being globally unique (e.g. a database using UUID as key
would alias/mix up entries/records due to duplicated UUID).
The root cause seems to be simply _not_ seeding PRNG before generating
a random value. It turns out this belongs to an established class of
PRNG-specific problems, commonly known as "unseeded randomness", for
which I am able to find below bugs/CVE/CWE:
- https://bugzilla.redhat.com/show_bug.cgi?id=CVE-2015-0285
("CVE-2015-0285 openssl: handshake with unseeded PRNG")
- https://bugzilla.redhat.com/show_bug.cgi?id=CVE-2015-9019
("CVE-2015-9019 libxslt: math.random() in xslt uses unseeded
randomness")
- https://cwe.mitre.org/data/definitions/336.html
("CWE-336: Same Seed in Pseudo-Random Number Generator (PRNG)")
The first revision [1] of this patch updated the seed based on the
output of get_timer(), similar to [4].
There are two problems with this approach:
- get_timer() has a poor _ms_ resolution
- when gen_rand_uuid() is called in a loop, get_timer() returns the
same result, leading to the same seed being passed to srand(),
leading to the same uuid being generated for several partitions
with different names
The above drawbacks have been addressed in the second version [2].
In its third revision (current), the patch reworded the description
and summary line to emphasize it is a *fix* rather than an improvement.
Testing [3] consisted of running 'gpt write mmc 1 $partitions' in a
loop on R-Car3 for several minutes, collecting 8844 randomly generated
UUIDS. Two consecutive cold boots are concatenated in the log.
As a result, all uuid values are unique (scripted check).
Thanks to Roman, who reported the issue and provided support in fixing.
[1] https://patchwork.ozlabs.org/patch/1091802/
[2] https://patchwork.ozlabs.org/patch/1092945/
[3] https://gist.github.com/erosca/2820be9d554f76b982edd48474d0e7ca
[4] commit da384a9d7628 ("net: rename and refactor eth_rand_ethaddr() function")
Reported-by: Roman Stratiienko
Signed-off-by: Eugeniu Rosca
--
v3:
- Reworked the patch summary line and description to emphasize this is
a fix rather than an improvement by precisely pointing out the root
cause and mentioning related CVE/CWE.
v2:
- https://patchwork.ozlabs.org/patch/1092945/
- Replaced get_timer(0) with get_ticks() and added rand() to seed value
- Performed extensive testing on R-Car3 (ARMv8). See:
https://gist.github.com/erosca/2820be9d554f76b982edd48474d0e7ca
v1:
- https://patchwork.ozlabs.org/patch/1092944/
---
lib/uuid.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/lib/uuid.c b/lib/uuid.c
index fa20ee39fc32..2d4d6ef7e461 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -238,6 +238,8 @@ void gen_rand_uuid(unsigned char *uuid_bin)
unsigned int *ptr = (unsigned int *)&uuid;
int i;
+ srand(get_ticks() + rand());
+
/* Set all fields randomly */
for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
*(ptr + i) = cpu_to_be32(rand());
--
2.21.0
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[U-Boot] [PATCH v2 3/4] cmd: gpt: fix and tidy up help message
Apply the following changes:
- Guard the 'gpt read' command by 'ifdef CONFIG_CMD_GPT_RENAME',
since 'gpt read' is not available on CMD_GPT_RENAME=n
- Prefix the {read,swap,rename} commands with one space for consistency
- Prefix the 'guid' commands with 'gpt' for consistency
Signed-off-by: Eugeniu Rosca
Reviewed-by: Heinrich Schuchardt
--
v2:
- Added Reviewed-by: Heinrich Schuchardt
v1:
- https://patchwork.ozlabs.org/patch/1092944/
---
cmd/gpt.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 638870352f40..33cda513969f 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -876,21 +876,21 @@ U_BOOT_CMD(gpt, CONFIG_SYS_MAXARGS, 1, do_gpt,
" Example usage:\n"
" gpt write mmc 0 $partitions\n"
" gpt verify mmc 0 $partitions\n"
- " read \n"
- "- read GPT into a data structure for manipulation\n"
- " guid \n"
+ " gpt guid \n"
"- print disk GUID\n"
- " guid \n"
+ " gpt guid \n"
"- set environment variable to disk GUID\n"
" Example usage:\n"
" gpt guid mmc 0\n"
" gpt guid mmc 0 varname\n"
#ifdef CONFIG_CMD_GPT_RENAME
"gpt partition renaming commands:\n"
- "gpt swap\n"
+ " gpt read \n"
+ "- read GPT into a data structure for manipulation\n"
+ " gpt swap\n"
"- change all partitions named name1 to name2\n"
" and vice-versa\n"
- "gpt rename\n"
+ " gpt rename\n"
"- rename the specified partition\n"
" Example usage:\n"
" gpt swap mmc 0 foo bar\n"
--
2.21.0
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[U-Boot] [PATCH v2 2/4] disk: efi: Fix memory leak on 'gpt verify'
Below is what happens on R-Car H3ULCB-KF using clean U-Boot
v2019.04-00810-g6aebc0d11a10 and r8a7795_ulcb_defconfig:
=> ### interrupt autoboot
=> gpt verify mmc 1
No partition list provided - only basic check
Verify GPT: success!
=> ### keep calling 'gpt verify mmc 1'
=> ### on 58th call, we are out of memory:
=> gpt verify mmc 1
alloc_read_gpt_entries: ERROR: Can't allocate 0X4000 bytes for GPT Entries
GPT: Failed to allocate memory for PTE
gpt_verify_headers: *** ERROR: Invalid Backup GPT ***
Verify GPT: error!
This is caused by calling is_gpt_valid() twice (hence allocating pte
also twice via alloc_read_gpt_entries()) while freeing pte only _once_
in the caller of gpt_verify_headers(). Fix that by freeing the pte
allocated and populated for primary GPT _before_ allocating and
populating the pte for backup GPT. The latter will be freed by the
caller of gpt_verify_headers().
With the fix applied, the reproduction scenario [1-2] has been run
hundreds of times in a loop w/o running into OOM.
[1] gpt verify mmc 1
[2] gpt verify mmc 1 $partitions
Fixes: cef68bf9042dda ("gpt: part: Definition and declaration of GPT
verification functions")
Signed-off-by: Eugeniu Rosca
Reviewed-by: Heinrich Schuchardt
--
v2:
- Added Reviewed-by: Heinrich Schuchardt
v1:
- https://patchwork.ozlabs.org/patch/1092943/
---
disk/part_efi.c | 4
1 file changed, 4 insertions(+)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 812d14cdd871..c0fa753339c8 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -698,6 +698,10 @@ int gpt_verify_headers(struct blk_desc *dev_desc,
gpt_header *gpt_head,
__func__);
return -1;
}
+
+ /* Free pte before allocating again */
+ free(*gpt_pte);
+
if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
gpt_head, gpt_pte) != 1) {
printf("%s: *** ERROR: Invalid Backup GPT ***\n",
--
2.21.0
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[U-Boot] [PATCH v2 1/4] disk: efi: Fix memory leak on 'gpt guid'
Below is what happens on R-Car H3ULCB-KF using clean U-Boot
v2019.04-00810-g6aebc0d11a10 and r8a7795_ulcb_defconfig:
=> ### interrupt autoboot
=> gpt guid mmc 1
21200400-0804-0146-9dcc-a8c51255994f
success!
=> ### keep calling 'gpt guid mmc 1'
=> ### on 59th call, we are out of memory:
=> gpt guid mmc 1
alloc_read_gpt_entries: ERROR: Can't allocate 0X4000 bytes for GPT Entries
GPT: Failed to allocate memory for PTE
get_disk_guid: *** ERROR: Invalid GPT ***
alloc_read_gpt_entries: ERROR: Can't allocate 0X4000 bytes for GPT Entries
GPT: Failed to allocate memory for PTE
get_disk_guid: *** ERROR: Invalid Backup GPT ***
error!
After some inspection, it looks like get_disk_guid(), added via v2017.09
commit 73d6d18b7147c9 ("GPT: add accessor function for disk GUID"),
unlike other callers of is_gpt_valid(), doesn't free the memory pointed
out by 'gpt_entry *gpt_pte'. The latter is allocated by is_gpt_valid()
via alloc_read_gpt_entries().
With the fix applied, the reproduction scenario has been run hundreds
of times ('while true; do gpt guid mmc 1; done') w/o running into OOM.
Fixes: 73d6d18b7147c9 ("GPT: add accessor function for disk GUID")
Signed-off-by: Eugeniu Rosca
Reviewed-by: Heinrich Schuchardt
--
v2:
- Added Reviewed-by: Heinrich Schuchardt
v1:
- https://patchwork.ozlabs.org/patch/1092942/
---
disk/part_efi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 239455b8161e..812d14cdd871 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -209,6 +209,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid)
guid_bin = gpt_head->disk_guid.b;
uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID);
+ /* Remember to free pte */
+ free(gpt_pte);
return 0;
}
--
2.21.0
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[U-Boot] [PATCH v2 0/4] Misc EFI/GPT/UUID fixes
This is a collection of fixes addressing issues on R-Car H3ULCB-KF.
All have been tested on H3ULCB-KF and boot-tested on sandbox.
Changes in v2:
- Reworded the description and summary line of
("lib: uuid: Improve randomness of uuid values on RANDOM_UUID=y")
to emphasize it is a fix rather than an improvement.
- No code changes.
Eugeniu Rosca (4):
disk: efi: Fix memory leak on 'gpt guid'
disk: efi: Fix memory leak on 'gpt verify'
cmd: gpt: fix and tidy up help message
lib: uuid: Fix unseeded PRNG on RANDOM_UUID=y
cmd/gpt.c | 12 ++--
disk/part_efi.c | 6 ++
lib/uuid.c | 2 ++
3 files changed, 14 insertions(+), 6 deletions(-)
--
2.21.0
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[U-Boot] [PATCH v2] board/BuR/zynq/brsmarc2: initial commit
This commit adds the first of a few more Xilinx ZYNQ based SoM boards.
The SoM is based on Xilinx Zynq 7000 SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.
Signed-off-by: Hannes Schmelzer
---
Changes in v2:
- fix SDPX tag in Make-files/rules
arch/arm/dts/Makefile | 2 +
arch/arm/dts/zynq-brsmarc2.dts | 15 +
arch/arm/dts/zynq-brsmarc2.dtsi | 278 ++
arch/arm/dts/zynq-brsmarc2_r512.dts | 16 +
board/BuR/zynq/.gitignore | 1 +
board/BuR/zynq/MAINTAINERS | 6 +
board/BuR/zynq/Makefile | 16 +
board/BuR/zynq/brsmarc2/board.c | 84 +++
board/BuR/zynq/brsmarc2/ps7_init_gpl.c | 814
board/BuR/zynq/brsmarc2_r512/board.c| 2 +
board/BuR/zynq/brsmarc2_r512/ps7_init_gpl.c | 813 +++
board/BuR/zynq/config.mk| 49 ++
board/BuR/zynq/take_vivadoHandoff.sh| 36 ++
board/BuR/zynq/uncrustify.cfg | 91
configs/brsmarc2_defconfig | 72 +++
configs/brsmarc2_r512_defconfig | 72 +++
include/configs/brsmarc2.h | 166 ++
17 files changed, 2533 insertions(+)
create mode 100644 arch/arm/dts/zynq-brsmarc2.dts
create mode 100644 arch/arm/dts/zynq-brsmarc2.dtsi
create mode 100644 arch/arm/dts/zynq-brsmarc2_r512.dts
create mode 100644 board/BuR/zynq/.gitignore
create mode 100644 board/BuR/zynq/MAINTAINERS
create mode 100644 board/BuR/zynq/Makefile
create mode 100644 board/BuR/zynq/brsmarc2/board.c
create mode 100644 board/BuR/zynq/brsmarc2/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/brsmarc2_r512/board.c
create mode 100644 board/BuR/zynq/brsmarc2_r512/ps7_init_gpl.c
create mode 100644 board/BuR/zynq/config.mk
create mode 100755 board/BuR/zynq/take_vivadoHandoff.sh
create mode 100644 board/BuR/zynq/uncrustify.cfg
create mode 100644 configs/brsmarc2_defconfig
create mode 100644 configs/brsmarc2_r512_defconfig
create mode 100644 include/configs/brsmarc2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02..2b00129 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -208,6 +208,8 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm011-x16.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb \
+ zynq-brsmarc2.dtb \
+ zynq-brsmarc2_r512.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
zynq-zybo.dtb \
diff --git a/arch/arm/dts/zynq-brsmarc2.dts b/arch/arm/dts/zynq-brsmarc2.dts
new file mode 100644
index 000..5ad5113
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R BRSMARC2 board base DTS file
+ *
+ * Copyright (C) 2018 B&R Industrial Automation GmbH
+ *
+ */
+/dts-v1/;
+#include "zynq-brsmarc2.dtsi"
+/ {
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x1000>;
+ };
+};
diff --git a/arch/arm/dts/zynq-brsmarc2.dtsi b/arch/arm/dts/zynq-brsmarc2.dtsi
new file mode 100644
index 000..d1aeffd
--- /dev/null
+++ b/arch/arm/dts/zynq-brsmarc2.dtsi
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * B&R BRSMARC2 board base DTS file
+ *
+ * Copyright (C) 2017 B&R Industrial Automation GmbH
+ * Copyright (C) 2011 - 2015 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ */
+
+/include/ "zynq-7000.dtsi"
+#include
+#include
+
+/ {
+ model = "BRSMARC2 Zynq SoM";
+ compatible = "xlnx,zynq-7000";
+
+ fset: factory-settings {
+ bl-version = "";
+ order-no= "";
+ cpu-order-no= "";
+ hw-revision = "";
+ serial-no = <0>;
+ device-id = <0x0>;
+ parent-id = <0x0>;
+ hw-variant = <0x0>;
+ hw-platform = <0x0>;
+ fram-offset = <0x0>;
+ fram-size = <0x0>;
+ cache-disable = <0x0>;
+ cpu-clock = <0x0>;
+ };
+
+ aliases {
+ ethernet0 = &gem0;
+ ethernet1 = &gem1;
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ spi0 = &qspi;
+ mmc0 = &sdhci0;
+ fset = &fset;
+ can0 = &can0;
+ can1 = &can1;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x1000>;
+ };
+
+ board {
+ status = "okay";
+ compatible = "bur,brsmarc2-som";
+ usb0mux-gpios = <&gpio0 68 GPIO_ACTIVE_HIGH>;
+ usb1mux-gpios = <&gpio0 69 GPIO_ACTIVE_HIGH>;
+ powerdown-gpios
[U-Boot] [PATCH v2] board/BuR/brppt2: initial commit
This commit adds support for the brppt2 board. The board is based on the
i.mx6 dual-lite SoC.
Signed-off-by: Hannes Schmelzer
---
Changes in v2:
- fix SDPX tag in Make-files/rules
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/imx6dl-brppt2.dts | 278 +
arch/arm/mach-imx/mx6/Kconfig | 19 ++
board/BuR/brppt2/Kconfig | 18 ++
board/BuR/brppt2/MAINTAINERS | 6 +
board/BuR/brppt2/Makefile | 8 +
board/BuR/brppt2/board.c | 542 +
board/BuR/brppt2/config.mk | 36 +++
configs/brppt2_defconfig | 92 +++
include/configs/brppt2.h | 125 ++
10 files changed, 1126 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/imx6dl-brppt2.dts
create mode 100644 board/BuR/brppt2/Kconfig
create mode 100644 board/BuR/brppt2/MAINTAINERS
create mode 100644 board/BuR/brppt2/Makefile
create mode 100644 board/BuR/brppt2/board.c
create mode 100644 board/BuR/brppt2/config.mk
create mode 100644 configs/brppt2_defconfig
create mode 100644 include/configs/brppt2.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02..288c3e8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -529,7 +529,8 @@ dtb-$(CONFIG_MX6QDL) += \
imx6dl-sabreauto.dtb \
imx6dl-sabresd.dtb \
imx6qp-sabreauto.dtb \
- imx6qp-sabresd.dtb
+ imx6qp-sabresd.dtb \
+ imx6dl-brppt2.dtb
dtb-$(CONFIG_TARGET_WANDBOARD) += \
imx6dl-wandboard-revb1.dtb
diff --git a/arch/arm/dts/imx6dl-brppt2.dts b/arch/arm/dts/imx6dl-brppt2.dts
new file mode 100644
index 000..4f1c52b
--- /dev/null
+++ b/arch/arm/dts/imx6dl-brppt2.dts
@@ -0,0 +1,278 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 B&R Industrial Automation GmbH
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-u-boot.dtsi"
+#include
+#include
+
+/ {
+ model = "PPT50";
+ compatible = "fsl,imx6dl";
+
+ config {
+ u-boot,spl-payload-offset = <0x10>;
+ };
+
+ fset: factory-settings {
+ bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+ order-no= "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+ hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789";
+ serial-no = <0>;
+ device-id = <0x0>;
+ parent-id = <0x0>;
+ hw-variant = <0x0>;
+ };
+
+ aliases {
+ ds1timing0 = &timing0;
+ ds1timing1 = &timing1;
+ ds1bkl = &backlight;
+ fset = &fset;
+ mxcfb0 = &mxcfb0;
+ touch0 = &touch0;
+ touch1 = &touch1;
+ touch2 = &touch2;
+ display_regulator = &display_regulator;
+ ldb = &ldb;
+ mmc0 = &usdhc4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ mxcfb0: fb@0 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "ldb";
+ interface_pix_fmt = "RGB24";
+ default_bpp = <32>;
+ int_clk = <0>;
+ late_init = <0>;
+ rotation = <0>;
+ status = "okay";
+ };
+
+ lcd@0 {
+ compatible = "fsl,lcd";
+ vlcd-supply = <&display_regulator>;
+ ipu_id = <0>;
+ disp_id = <0>;
+ default_ifmt = "RGB24";
+ status = "disabled";
+
+ display-timings {
+ native-mode = <&timing1>;
+ timing1: lcd {
+ };
+ };
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm4 0 500>;
+ brightness-levels = <0 1 2 3 4 5 6 7
+ 8 9 10 11 12 13 14 15
+16 17 18 19 20 21 22 23
+24 25 26 27 28 29 30 31
+32 33 34 35 36 37 38 39
+40 41 42 43 44 45 46 47
+48 49 50 51 52 53 54 55
+56 57 58 59 60 61 62 63
+64 65 66 67 68 69 70 71
+72 73 74 75 76 77 78 79
+80 81 82 83 84 85 86 87
+88 89 90 91 92 93 94 95
+96 97 98 99 100>;
+
[U-Boot] [PATCH v2] board/BuR/brsmarc1: initial commit
This commit adds support for the B&R brsmarc1 SoM.
The SoM is based on TI's AM335x SoC.
Mainly vxWorks 6.9.4.x is running on the board,
doing some PLC stuff on various carrier boards.
Signed-off-by: Hannes Schmelzer
---
Changes in v2:
- fix style issue in arch/arm/mach-omap2/am33xx/Kconfig
- fix SDPX tag in Make-files/rules
arch/arm/dts/Makefile | 1 +
arch/arm/dts/am335x-brsmarc1.dts | 408 +
arch/arm/mach-omap2/Kconfig| 1 +
arch/arm/mach-omap2/am33xx/Kconfig | 4 +
board/BuR/brsmarc1/Kconfig | 15 ++
board/BuR/brsmarc1/MAINTAINERS | 6 +
board/BuR/brsmarc1/Makefile| 10 +
board/BuR/brsmarc1/board.c | 168 +++
board/BuR/brsmarc1/config.mk | 33 +++
board/BuR/brsmarc1/mux.c | 266
configs/brsmarc1_defconfig | 107 ++
include/configs/brsmarc1.h | 87
12 files changed, 1106 insertions(+)
create mode 100644 arch/arm/dts/am335x-brsmarc1.dts
create mode 100644 board/BuR/brsmarc1/Kconfig
create mode 100644 board/BuR/brsmarc1/MAINTAINERS
create mode 100644 board/BuR/brsmarc1/Makefile
create mode 100644 board/BuR/brsmarc1/board.c
create mode 100644 board/BuR/brsmarc1/config.mk
create mode 100644 board/BuR/brsmarc1/mux.c
create mode 100644 configs/brsmarc1_defconfig
create mode 100644 include/configs/brsmarc1.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dfa5b02..8ac057a 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -250,6 +250,7 @@ dtb-$(CONFIG_AM33XX) += \
am335x-brppt1-nand.dtb \
am335x-brppt1-spi.dtb \
am335x-brxre1.dtb \
+ am335x-brsmarc1.dtb \
am335x-draco.dtb \
am335x-evm.dtb \
am335x-evmsk.dtb \
diff --git a/arch/arm/dts/am335x-brsmarc1.dts b/arch/arm/dts/am335x-brsmarc1.dts
new file mode 100644
index 000..e5e2761
--- /dev/null
+++ b/arch/arm/dts/am335x-brsmarc1.dts
@@ -0,0 +1,408 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2017 B&R Industrial Automation GmbH
+ * http://www.br-automation.com
+ *
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+
+/ {
+ model = "BRSMARC1 SoM";
+ compatible = "ti,am33xx";
+
+ fset: factory-settings {
+ bl-version = "";
+ order-no= "";
+ cpu-order-no= "";
+ hw-revision = "";
+ serial-no = <0>;
+ device-id = <0x0>;
+ parent-id = <0x0>;
+ hw-variant = <0x0>;
+ hw-platform = <0x7>;
+ fram-offset = <0x100>;
+ fram-size = <0x1F00>;
+ cache-disable = <0x0>;
+ cpu-clock = <0x0>;
+ };
+
+ chosen {
+ bootargs = "console=ttyO0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ aliases {
+ fset = &fset;
+ mmc = &mmc2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ touch0 = &burtouch0;
+ screen0 = &lcdscreen0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x8000 0x1000>; /* 256 MB */
+ };
+
+ vmmcsd_fixed: fixedregulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vmmcsd_fixed";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ lcdscreen0: lcdscreen@0 {
+ /*backlight = <&tps_bl>; */
+ compatible = "ti,tilcdc,panel";
+ status = "okay";
+
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz= <16>;
+ bpp = <32>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order= <0>;
+ fifo-th = <0>;
+ rotation= <0>;
+ pupdelay= <0>;
+ pondelay= <0>;
+ pwrpin = <0x00B1>;
+ brightdrv = <0>;
+ brightfdim = <100>;
+ brightdef = <50>;
+ };
+
+ display-timings {
+ default {
+ clock-frequency = <0>;
+ hactive = <0>;
+ vactive = <0>;
+ hfront-porch= <0>;
+
Re: [U-Boot] [PATCH v3] ARM: am335x: Add phyCORE AM335x R2 support
Hello Niel,
Am 02.05.2019 um 11:52 schrieb Niel Fourie:
Support for Phytech phyCORE AM335x R2 SOM (PCL060) on the Phytec
phyBOARD-Wega AM335x.
CPU : AM335X-GP rev 2.1
Model: Phytec AM335x phyBOARD-WEGA
DRAM: 256 MiB
NAND: 256 MiB
MMC: OMAP SD/MMC: 0
eth0: ethernet@4a10
Working:
- Eth0
- i2C
- MMC/SD
- NAND
- UART
- USB (host)
Device trees were taken from Linux mainline revision
37624b58542fb9f2d9a70e6ea006ef8a5f66c30b
Signed-off-by: Niel Fourie
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/am335x-phycore-som.dtsi | 322 +
arch/arm/dts/am335x-wega-rdk-u-boot.dtsi | 40 +++
arch/arm/dts/am335x-wega-rdk.dts | 23 ++
arch/arm/dts/am335x-wega.dtsi | 230 +++
arch/arm/mach-omap2/Kconfig| 1 +
arch/arm/mach-omap2/am33xx/Kconfig | 7 +
board/phytec/phycore_am335x_r2/Kconfig | 15 +
board/phytec/phycore_am335x_r2/MAINTAINERS | 7 +
board/phytec/phycore_am335x_r2/Makefile| 11 +
board/phytec/phycore_am335x_r2/board.c | 263 +
board/phytec/phycore_am335x_r2/board.h | 24 ++
board/phytec/phycore_am335x_r2/mux.c | 117
configs/phycore-am335x-r2-wega_defconfig | 79 +
include/configs/phycore_am335x_r2.h| 130 +
15 files changed, 1271 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/am335x-phycore-som.dtsi
create mode 100644 arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
create mode 100644 arch/arm/dts/am335x-wega-rdk.dts
create mode 100644 arch/arm/dts/am335x-wega.dtsi
create mode 100644 board/phytec/phycore_am335x_r2/Kconfig
create mode 100644 board/phytec/phycore_am335x_r2/MAINTAINERS
create mode 100644 board/phytec/phycore_am335x_r2/Makefile
create mode 100644 board/phytec/phycore_am335x_r2/board.c
create mode 100644 board/phytec/phycore_am335x_r2/board.h
create mode 100644 board/phytec/phycore_am335x_r2/mux.c
create mode 100644 configs/phycore-am335x-r2-wega_defconfig
create mode 100644 include/configs/phycore_am335x_r2.h
[...]
diff --git a/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
new file mode 100644
index 00..b7678e98ff
--- /dev/null
+++ b/arch/arm/dts/am335x-wega-rdk-u-boot.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 DENX Software Engineering GmbH
+ */
+
+/ {
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootargs = "console=ttyO0,115200 earlyprintk";
+ stdout-path = &uart0;
+ };
+
+ ocp {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ };
+
+ memory@8000 {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+ };
+};
could we move the entries for "ocp" and "memory" to
arch/arm/dts/am33xx-u-boot.dtsi ?
I think, this values are so common, that other am33xx based boards needs
them too ...
+&scm {
+ u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
+};
May this one too?
Beside of this nitpick:
Reviewed-by: Heiko Schocher
bye,
Heiko
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-52 Fax: +49-8142-66989-80 Email: h...@denx.de
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