Loading u-boot binary from the u-boot command line

[scd rjcom]

I need to to test the modified u-boot binary. I want to test it without
writing it on the NOR flash, that already has a working u-boot.

Can I load the modified u-boot binary from the currently running u-boot
command line?

please pull u-boot-samsung master

[Minkyu Kang]

Dear Tom,

The following changes since commit ee6726be4f0dccb612f0193c62ca149164c8a5af:

  Merge tag 'ti-v2021.04-rc1' of
https://gitlab.denx.de/u-boot/custodians/u-boot-ti (2021-01-12 09:32:48
-0500)

are available in the Git repository at:

  g...@gitlab.denx.de:u-boot/custodians/u-boot-samsung.git

for you to fetch changes up to 0a80955fc6e03ebbe1f98c5fa3c89fb33f23c23e:

  mmc: exynos_dw_mmc: remove unused function (2021-01-13 13:49:38 +0900)


Jaehoon Chung (2):
  samsung: arndale: remove board_mmc_init function
  mmc: exynos_dw_mmc: remove unused function

 arch/arm/mach-exynos/include/mach/dwmmc.h |  2 --
 board/samsung/arndale/arndale.c   | 13 -
 drivers/mmc/exynos_dw_mmc.c   | 56

 3 files changed, 71 deletions(-)

-- 
Thanks,
Minkyu Kang.

Re: [PATCH v2 08/21] sunxi: introduce support for H616 clocks

[Jernej Škrabec]

Dne petek, 22. januar 2021 ob 02:17:30 CET je Andre Przywara napisal(a):
> On Mon, 11 Jan 2021 21:11:40 +0100
> 
> Jernej Skrabec  wrote:
> > H616 has mostly the same clocks as H6 with some small differences. Just
> > reuse H6 clocks for H616 and handle differences with macros.
> > 
> > Reviewed-by: Samuel Holland 
> > Signed-off-by: Jernej Skrabec 
> > ---
> > 
> >  .../include/asm/arch-sunxi/clock_sun50i_h6.h   | 18 +-
> >  arch/arm/mach-sunxi/clock_sun50i_h6.c  |  8 ++--
> >  2 files changed, 23 insertions(+), 3 deletions(-)
> > 
> > diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> > b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h index
> > e83e84ab6cab..62abfc4ef6bd 100644
> > --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> > +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> > @@ -230,6 +230,7 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_PLL1_CTRL_EN   BIT(31)
> >  #define CCM_PLL1_LOCK_EN   BIT(29)
> >  #define CCM_PLL1_LOCK  BIT(28)
> > 
> > +#define CCM_PLL1_OUT_ENBIT(27)
> > 
> >  #define CCM_PLL1_CLOCK_TIME_2  (2 << 24)
> >  #define CCM_PLL1_CTRL_P(p) ((p) << 16)
> >  #define CCM_PLL1_CTRL_N(n) ((n) << 8)
> > 
> > @@ -238,6 +239,7 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_PLL5_CTRL_EN   BIT(31)
> >  #define CCM_PLL5_LOCK_EN   BIT(29)
> >  #define CCM_PLL5_LOCK  BIT(28)
> > 
> > +#define CCM_PLL5_OUT_ENBIT(27)
> > 
> >  #define CCM_PLL5_CTRL_N(n) ((n) << 8)
> >  #define CCM_PLL5_CTRL_DIV1(div1)   ((div1) << 0)
> >  #define CCM_PLL5_CTRL_DIV2(div0)   ((div0) << 1)
> > 
> > @@ -252,7 +254,6 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_PLL6_CTRL_DIV1_MASK(0x1 << 
CCM_PLL6_CTRL_DIV1_SHIFT)
> >  #define CCM_PLL6_CTRL_DIV2_SHIFT   1
> >  #define CCM_PLL6_CTRL_DIV2_MASK(0x1 << 
CCM_PLL6_CTRL_DIV2_SHIFT)
> > 
> > -#define CCM_PLL6_DEFAULT   0xa0006300
> > 
> >  /* cpu_axi bit field*/
> >  #define CCM_CPU_AXI_MUX_MASK   (0x3 << 24)
> > 
> > @@ -262,6 +263,9 @@ struct sunxi_ccm_reg {
> > 
> >  #define CCM_CPU_AXI_AXI_MASK   0x3
> >  #define CCM_CPU_AXI_DEFAULT_FACTORS0x301
> > 
> > +#ifdef CONFIG_MACH_SUN50I_H6
> > +#define CCM_PLL6_DEFAULT   0xa0006300
> > +
> > 
> >  /* psi_ahb1_ahb2 bit field */
> >  #define CCM_PSI_AHB1_AHB2_DEFAULT  0x03000102
> > 
> > @@ -270,6 +274,18 @@ struct sunxi_ccm_reg {
> > 
> >  /* apb1 bit field */
> >  #define CCM_APB1_DEFAULT   0x03000102
> > 
> > +#elif CONFIG_MACH_SUN50I_H616
> > +#define CCM_PLL6_DEFAULT   0xa8003100
> > +
> > +/* psi_ahb1_ahb2 bit field */
> > +#define CCM_PSI_AHB1_AHB2_DEFAULT  0x0302
> 
> Why is this twice as fast, compared to the H6? It's based on the same
> PERI0(1X), which should be 600 MHz for both the H6 and H616, right?
> 
> Is that the reset config or set up by the BROM? Or is that coming from
> some BSP source?

Actually I just dumped register when Android was running.

Best regards,
Jernej

> 
> > +
> > +/* ahb3 bit field */
> > +#define CCM_AHB3_DEFAULT   0x0302
> > +
> > +/* apb1 bit field */
> > +#define CCM_APB1_DEFAULT   0x03000102
> > +#endif
> > 
> >  /* apb2 bit field */
> >  #define APB2_CLK_SRC_OSC24M(0x0 << 24)
> > 
> > diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 6bd466915c11..daca02019bab
> > 100644
> > --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> > @@ -68,6 +68,9 @@ void clock_set_pll1(unsigned int clk)
> > 
> > /* clk = 24*n/p, p is ignored if clock is >288MHz */
> > writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 
|
> > 
> > +#ifdef CONFIG_MACH_SUN50I_H616
> > +  CCM_PLL1_OUT_EN |
> > +#endif
> > 
> >CCM_PLL1_CTRL_N(clk / 2400), &ccm->pll1_cfg);
> > 
> > while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
> > 
> > @@ -83,6 +86,7 @@ unsigned int clock_get_pll6(void)
> > 
> >  {
> >  
> > struct sunxi_ccm_reg *const ccm =
> > 
> > (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> > 
> > +   int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) 4 : 2;
> 
> This is missing the question mark, but that gets fixed up in a later
> patch, so I assume it's a rebase artifact. Will fix it up while
> committing.
> 
> Cheers,
> Andre
> 
> > uint32_t rval = readl(&ccm->pll6_cfg);
> > int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
> > 
> > @@ -90,8 +94,8 @@ unsigned int clock_get_pll6(void)
> > 
> > CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
> > 
> > int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
> > 
> > CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
> > 
> > -   /* The register defines PLL6-4X, not plain PLL6 */
> > -   return 2400 / 4 * n / div1 / div2;
> > +   /* The register

Re: [PATCH] cmd: efidebug: always check return code from get_variable()

[Heinrich Schuchardt]

On 1/22/21 2:42 AM, AKASHI Takahiro wrote:

CID 316364 says:

Null pointer dereferences  (FORWARD_NULL)
printf("Result total size: 0x%x\n", result->variable_total_size);

at do_efi_capsule_res().

The code is basically safe because a buffer for "result" is allocated
by malloc() and filled up by the second get_variable(), which fails any way
if the allocation has failed.

But the first (and second) get_variable() possibly returns an error other
than EFI_SUCCESS. We always need to check the return code from
get_variable() before accessing the data in "result".

While this change won't suppress CID 316364, the resulting code is much
safer.

Signed-off-by: AKASHI Takahiro 


Reviewed-by: Heinrich Schuchardt 


---
  cmd/efidebug.c | 12 +++-
  1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 9a2d4ddd5ef4..83bc2196a5a9 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -189,14 +189,16 @@ static int do_efi_capsule_res(struct cmd_tbl *cmdtp, int 
flag,
ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
if (ret == EFI_BUFFER_TOO_SMALL) {
result = malloc(size);
+   if (!result)
+   return CMD_RET_FAILURE;
ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
result));
-   if (ret != EFI_SUCCESS) {
-   free(result);
-   printf("Failed to get %ls\n", var_name16);
+   }
+   if (ret != EFI_SUCCESS) {
+   free(result);
+   printf("Failed to get %ls\n", var_name16);

-   return CMD_RET_FAILURE;
-   }
+   return CMD_RET_FAILURE;
}

printf("Result total size: 0x%x\n", result->variable_total_size);

Re: [PATCH] efi_loader: capsule: fix SIZEOF_MISMATCH warning

[Heinrich Schuchardt]

On 1/22/21 2:43 AM, AKASHI Takahiro wrote:

CID 316361 says:

Passing argument "count * 8UL /* sizeof (*files) */" to
function "dlmalloc" and then casting the return value to "u16 **" is
suspicious. In this particular case "sizeof (u16 **)" happens to be equal
to "sizeof (u16 *)", but this is not a portable assumption.

767 tmp_files = malloc(count * sizeof(*files));


The change in this patch fixes the ambiguity.

Signed-off-by: AKASHI Takahiro 
Fixes: CID 316361


Reviewed-by: Heinrich Schuchardt 


---
  lib/efi_loader/efi_capsule.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index dad1b0fcf7c0..95413c50f89a 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -764,7 +764,7 @@ static efi_status_t efi_capsule_scan_dir(u16 ***files, 
unsigned int *num)
goto err;

/* make a list */
-   tmp_files = malloc(count * sizeof(*files));
+   tmp_files = malloc(count * sizeof(tmp_files[0]));
if (!tmp_files) {
ret = EFI_OUT_OF_RESOURCES;
goto err;

Re: [PATCH] tools: mkeficapsule: fill reserved members of structure

[Heinrich Schuchardt]

On 1/22/21 2:43 AM, AKASHI Takahiro wrote:

Fill reserved members of efi_firmware_management_capsule_image_header
structure with zero's for safety.

Signed-off-by: AKASHI Takahiro 
Fixes: CID 316354


Reviewed-by: Heinrich Schuchardt 


---
  tools/mkeficapsule.c | 3 +++
  1 file changed, 3 insertions(+)

diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 270943fc90ae..36f693f09644 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -310,6 +310,9 @@ static int create_fwbin(char *path, char *bin, efi_guid_t 
*guid,
image.version = 0x0003;
memcpy(&image.update_image_type_id, guid, sizeof(*guid));
image.update_image_index = index;
+   image.reserved[0] = 0;
+   image.reserved[1] = 0;
+   image.reserved[2] = 0;
image.update_image_size = bin_stat.st_size;
image.update_vendor_code_size = 0; /* none */
image.update_hardware_instance = instance;

configure and build the u-boot for BCM953012HR

[scd rjcom]

How do I configure and build the u-boot for BCM953012HR (Broadcom Northstar
Reference
board)?

Is there a compatible board/config for the BCM953012HR Board?

[PATCH] tools: mkeficapsule: fill reserved members of structure

[AKASHI Takahiro]

Fill reserved members of efi_firmware_management_capsule_image_header
structure with zero's for safety.

Signed-off-by: AKASHI Takahiro 
Fixes: CID 316354
---
 tools/mkeficapsule.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 270943fc90ae..36f693f09644 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -310,6 +310,9 @@ static int create_fwbin(char *path, char *bin, efi_guid_t 
*guid,
image.version = 0x0003;
memcpy(&image.update_image_type_id, guid, sizeof(*guid));
image.update_image_index = index;
+   image.reserved[0] = 0;
+   image.reserved[1] = 0;
+   image.reserved[2] = 0;
image.update_image_size = bin_stat.st_size;
image.update_vendor_code_size = 0; /* none */
image.update_hardware_instance = instance;
-- 
2.28.0

[PATCH] efi_loader: capsule: fix SIZEOF_MISMATCH warning

[AKASHI Takahiro]

CID 316361 says:
> Passing argument "count * 8UL /* sizeof (*files) */" to
> function "dlmalloc" and then casting the return value to "u16 **" is
> suspicious. In this particular case "sizeof (u16 **)" happens to be equal
> to "sizeof (u16 *)", but this is not a portable assumption.
> > 767 tmp_files = malloc(count * sizeof(*files));

The change in this patch fixes the ambiguity.

Signed-off-by: AKASHI Takahiro 
Fixes: CID 316361
---
 lib/efi_loader/efi_capsule.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c
index dad1b0fcf7c0..95413c50f89a 100644
--- a/lib/efi_loader/efi_capsule.c
+++ b/lib/efi_loader/efi_capsule.c
@@ -764,7 +764,7 @@ static efi_status_t efi_capsule_scan_dir(u16 ***files, 
unsigned int *num)
goto err;
 
/* make a list */
-   tmp_files = malloc(count * sizeof(*files));
+   tmp_files = malloc(count * sizeof(tmp_files[0]));
if (!tmp_files) {
ret = EFI_OUT_OF_RESOURCES;
goto err;
-- 
2.28.0

[PATCH] cmd: efidebug: always check return code from get_variable()

[AKASHI Takahiro]

CID 316364 says:
> Null pointer dereferences  (FORWARD_NULL)
>   printf("Result total size: 0x%x\n", result->variable_total_size);
at do_efi_capsule_res().

The code is basically safe because a buffer for "result" is allocated
by malloc() and filled up by the second get_variable(), which fails any way
if the allocation has failed.

But the first (and second) get_variable() possibly returns an error other
than EFI_SUCCESS. We always need to check the return code from
get_variable() before accessing the data in "result".

While this change won't suppress CID 316364, the resulting code is much
safer.

Signed-off-by: AKASHI Takahiro 
---
 cmd/efidebug.c | 12 +++-
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/cmd/efidebug.c b/cmd/efidebug.c
index 9a2d4ddd5ef4..83bc2196a5a9 100644
--- a/cmd/efidebug.c
+++ b/cmd/efidebug.c
@@ -189,14 +189,16 @@ static int do_efi_capsule_res(struct cmd_tbl *cmdtp, int 
flag,
ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size, NULL));
if (ret == EFI_BUFFER_TOO_SMALL) {
result = malloc(size);
+   if (!result)
+   return CMD_RET_FAILURE;
ret = EFI_CALL(RT->get_variable(var_name16, &guid, NULL, &size,
result));
-   if (ret != EFI_SUCCESS) {
-   free(result);
-   printf("Failed to get %ls\n", var_name16);
+   }
+   if (ret != EFI_SUCCESS) {
+   free(result);
+   printf("Failed to get %ls\n", var_name16);
 
-   return CMD_RET_FAILURE;
-   }
+   return CMD_RET_FAILURE;
}
 
printf("Result total size: 0x%x\n", result->variable_total_size);
-- 
2.28.0

Re: [linux-sunxi] Re: [PATCH v2 05/21] sunxi: prcm: Add memory map for H6 like SoCs

[Samuel Holland]

On 1/21/21 7:14 PM, Andre Przywara wrote:
> On Mon, 11 Jan 2021 21:11:37 +0100
> Jernej Skrabec  wrote:
> 
>> There was no need to have prcm definitions for H6 and similar SoCs till
>> now. However, support R_I2C will be needed soon in SPL.
>>
>> Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h.
>> One of those files will be selected in common prcm.h based on defined
>> macros.
>>
>> This commit doesn't do any functional change.
> 
> That looks alright.
> prcm.h and prcm_sun6i.h are identical, apart from the header guards.
> I could verify most of the sun50i PRCM fields by comparing to the Linux
> CCU_R driver, but not all of them.
> Out of curiosity, where do those offsets actually come from? Some BSP
> code? And they are actually SUN50I_H6 aka. "NCAT" specific, right?

Compare:

https://github.com/orangepi-xunlong/linux-orangepi/blob/orange-pi-4.9-sun50iw9/drivers/clk/sunxi/clk-sun50iw6.h#L148

https://github.com/orangepi-xunlong/linux-orangepi/blob/orange-pi-4.9-sun50iw9/drivers/clk/sunxi/clk-sun50iw9.h#L158

(This, and experimentation, is also where my "0x20c is the highest
clock-gate-related register" comment on the DTS came from).

Cheers,
Samuel

Re: Boot failure triggered by USB on rockpro64-rk3399 and pinebook-pro-rk3399

[Jonathan Gray]

U-Boot 2020.07 worked, broken on rockpro64 by

commit 3ae64582fb8ceead4fc464cd2055eb3eaef78ccc (refs/bisect/bad)
Author: Jagan Teki 
Date:   Mon Jul 20 14:53:09 2020 +0530

rockchip: rockpro64: Enable USB3.0 Host

Enable USB3.0 Host support for RockPro64 boards.

Signed-off-by: Jagan Teki 
Reviewed-by: Kever Yang 

according to Kurt Miller who bisected this when the same problem was
encountered booting OpenBSD.  I don't have any rk3399 myself.

https://marc.info/?l=openbsd-ports&m=161005506031482&w=2
https://marc.info/?l=openbsd-ports&m=161012461223737&w=2

We ended up disabling CONFIG_USE_PREBOOT in rk3399 targets to fix
booting via non-usb as well.

On Thu, Jan 21, 2021 at 11:37:16AM +0800, Kever Yang wrote:
> Hi Vagrant,
> 
>     Do you know which version is the last version that works in this case?
> 
>     The firmware is from eMMC and it's wired for USB to affect the boot
> process.
> 
> Thanks,
> 
> - Kever
> 
> On 2021/1/21 上午8:08, Vagrant Cascadian wrote:
> > It seems rockpro64-rk3399 and pinebook-pro-rk3399 fail to boot when usb
> > is started. It hangs indefinitely at:
> > 
> >## Flattened Device Tree blob at 01f0
> >   Booting using the fdt blob at 0x1f0
> > 
> > I have observed this also using 2020.10 on rockpro64-rk3399, though on
> > pinebook-pro-rk3399 usb does not work and so it basically avoids
> > triggering the issue.
> > 
> > Setting CONFIG_USE_PREBOOT=n in the config works around the problem,
> > though obviously by breaking usb keyboard support or booting from USB
> > devices.
> > 
> > 
> > Related bugs in Debian and manjaro:
> > 
> >https://bugs.debian.org/973323
> >https://bugs.debian.org/980434
> >
> > https://gitlab.manjaro.org/manjaro-arm/packages/core/uboot-rockpro64/-/issues/4
> > 
> > 
> > Boot log:
> > 
> > U-Boot 2021.01+dfsg-1 (Jan 17 2021 - 03:50:13 +)
> > 
> > SoC: Rockchip rk3399
> > Reset cause: POR
> > Model: Pine64 RockPro64 v2.1
> > DRAM:  3.9 GiB
> > PMIC:  RK808
> > MMC:   mmc@fe31: 2, mmc@fe32: 1, sdhci@fe33: 0
> > Loading Environment from SPIFlash... SF: Detected gd25q128 with page size 
> > 256 Bytes, erase size 4 KiB, total 16 MiB
> > *** Warning - bad CRC, using default environment
> > 
> > In:serial
> > Out:   serial
> > Err:   serial
> > Model: Pine64 RockPro64 v2.1
> > Net:   eth0: ethernet@fe30
> > starting USB...
> > Bus usb@fe38: USB EHCI 1.00
> > Bus usb@fe3a: USB OHCI 1.0
> > Bus usb@fe3c: USB EHCI 1.00
> > Bus usb@fe3e: USB OHCI 1.0
> > Bus dwc3: usb maximum-speed not found
> > Register 2000140 NbrPorts 2
> > Starting the controller
> > USB XHCI 1.10
> > scanning bus usb@fe38 for devices... 1 USB Device(s) found
> > scanning bus usb@fe3a for devices... 1 USB Device(s) found
> > scanning bus usb@fe3c for devices... 1 USB Device(s) found
> > scanning bus usb@fe3e for devices... 1 USB Device(s) found
> > scanning bus dwc3 for devices... 1 USB Device(s) found
> > scanning usb for storage devices... 0 Storage Device(s) found
> > Hit any key to stop autoboot:  0
> > => printenv preboot
> > preboot=usb start
> > => usb reset
> > resetting USB...
> > Bus usb@fe38: USB EHCI 1.00
> > Bus usb@fe3a: USB OHCI 1.0
> > Bus usb@fe3c: USB EHCI 1.00
> > Bus usb@fe3e: USB OHCI 1.0
> > Bus dwc3: usb maximum-speed not found
> > Register 2000140 NbrPorts 2
> > Starting the controller
> > USB XHCI 1.10
> > scanning bus usb@fe38 for devices... 1 USB Device(s) found
> > scanning bus usb@fe3a for devices... 1 USB Device(s) found
> > scanning bus usb@fe3c for devices... 1 USB Device(s) found
> > scanning bus usb@fe3e for devices... 1 USB Device(s) found
> > scanning bus dwc3 for devices... 1 USB Device(s) found
> > scanning usb for storage devices... 0 Storage Device(s) found
> > => boot
> > Card did not respond to voltage select! : -110
> > switch to partitions #0, OK
> > mmc1 is current device
> > Scanning mmc 1:1...
> > Found /extlinux/extlinux.conf
> > Retrieving file: /extlinux/extlinux.conf
> > 144 bytes read in 5 ms (27.3 KiB/s)
> > 1:  Debian-Installer
> > Retrieving file: /initrd.gz
> > 28995285 bytes read in 1287 ms (21.5 MiB/s)
> > Retrieving file: /vmlinuz
> > 26922864 bytes read in 1195 ms (21.5 MiB/s)
> > Retrieving file: /dtbs/rockchip/rk3399-rockpro64.dtb
> > 56849 bytes read in 13 ms (4.2 MiB/s)
> > Moving Image from 0x208 to 0x220, end=3c5
> > ## Flattened Device Tree blob at 01f0
> > Booting using the fdt blob at 0x1f0
> > 
> > 
> > 
> > live well,
> >vagrant
> 
> 
> 

Re: [PATCH v2 10/21] sunxi: add support for R_I2C on H616

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:42 +0100
Jernej Skrabec  wrote:

> This port is needed for communication with PMIC. SPL uses it to set DRAM
> voltage on H616 boards.
> 
> Reviewed-by: Samuel Holland 
> Signed-off-by: Jernej Skrabec 

Compared the bits against the manual.

Reviewed-by: Andre Przywara 

Thanks!
Andre

> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
>  board/sunxi/board.c| 4 
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index cdb7dbd5b8e5..de77bf638e21 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -220,6 +220,7 @@ enum sunxi_gpio_number {
>  #define SUN8I_A23_GPL_R_TWI  3
>  #define SUN8I_GPL_R_UART 2
>  #define SUN50I_GPL_R_TWI 2
> +#define SUN50I_H616_GPL_R_TWI3
>  
>  #define SUN9I_GPN_R_RSB  3
>  
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 40fdd5da0477..14d31c719ece 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -196,6 +196,10 @@ void i2c_init_board(void)
>   clock_twi_onoff(5, 1);
>   sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
>   sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
> +#elif CONFIG_MACH_SUN50I_H616
> + clock_twi_onoff(5, 1);
> + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN50I_H616_GPL_R_TWI);
> + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN50I_H616_GPL_R_TWI);
>  #else
>   clock_twi_onoff(5, 1);
>   sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);

Re: [PATCH v2 09/21] sunxi: add support for H616 uart0

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:41 +0100
Jernej Skrabec  wrote:

> This port is used for debug terminal on all known H616 boards.
> 
> Reviewed-by: Samuel Holland 
> Signed-off-by: Jernej Skrabec 

Compared the bits against the manual.

Reviewed-by: Andre Przywara 

Cheers,
Andre

> ---
>  arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
>  arch/arm/mach-sunxi/board.c| 4 
>  2 files changed, 5 insertions(+)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h 
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index f817d328f432..cdb7dbd5b8e5 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -206,6 +206,7 @@ enum sunxi_gpio_number {
>  #define SUN6I_GPH_UART0  2
>  #define SUN9I_GPH_UART0  2
>  #define SUN50I_H6_GPH_UART0  2
> +#define SUN50I_H616_GPH_UART02
>  
>  #define SUNXI_GPI_SDC3   2
>  #define SUN7I_GPI_TWI3   3
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
> index 8ed9a87c1195..a883edd24107 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -116,6 +116,10 @@ static int gpio_init(void)
>   sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
>   sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
>   sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H616)
> + sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
> + sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
> + sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
>  #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
>   sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
>   sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);

Re: [PATCH v2 08/21] sunxi: introduce support for H616 clocks

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:40 +0100
Jernej Skrabec  wrote:

> H616 has mostly the same clocks as H6 with some small differences. Just
> reuse H6 clocks for H616 and handle differences with macros.
> 
> Reviewed-by: Samuel Holland 
> Signed-off-by: Jernej Skrabec 
> ---
>  .../include/asm/arch-sunxi/clock_sun50i_h6.h   | 18 +-
>  arch/arm/mach-sunxi/clock_sun50i_h6.c  |  8 ++--
>  2 files changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h 
> b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> index e83e84ab6cab..62abfc4ef6bd 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> @@ -230,6 +230,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL1_CTRL_EN BIT(31)
>  #define CCM_PLL1_LOCK_EN BIT(29)
>  #define CCM_PLL1_LOCKBIT(28)
> +#define CCM_PLL1_OUT_EN  BIT(27)
>  #define CCM_PLL1_CLOCK_TIME_2(2 << 24)
>  #define CCM_PLL1_CTRL_P(p)   ((p) << 16)
>  #define CCM_PLL1_CTRL_N(n)   ((n) << 8)
> @@ -238,6 +239,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL5_CTRL_EN BIT(31)
>  #define CCM_PLL5_LOCK_EN BIT(29)
>  #define CCM_PLL5_LOCKBIT(28)
> +#define CCM_PLL5_OUT_EN  BIT(27)
>  #define CCM_PLL5_CTRL_N(n)   ((n) << 8)
>  #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0)
>  #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1)
> @@ -252,7 +254,6 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL6_CTRL_DIV1_MASK  (0x1 << 
> CCM_PLL6_CTRL_DIV1_SHIFT)
>  #define CCM_PLL6_CTRL_DIV2_SHIFT 1
>  #define CCM_PLL6_CTRL_DIV2_MASK  (0x1 << 
> CCM_PLL6_CTRL_DIV2_SHIFT)
> -#define CCM_PLL6_DEFAULT 0xa0006300
>  
>  /* cpu_axi bit field*/
>  #define CCM_CPU_AXI_MUX_MASK (0x3 << 24)
> @@ -262,6 +263,9 @@ struct sunxi_ccm_reg {
>  #define CCM_CPU_AXI_AXI_MASK 0x3
>  #define CCM_CPU_AXI_DEFAULT_FACTORS  0x301
>  
> +#ifdef CONFIG_MACH_SUN50I_H6
> +#define CCM_PLL6_DEFAULT 0xa0006300
> +
>  /* psi_ahb1_ahb2 bit field */
>  #define CCM_PSI_AHB1_AHB2_DEFAULT0x03000102
>  
> @@ -270,6 +274,18 @@ struct sunxi_ccm_reg {
>  
>  /* apb1 bit field */
>  #define CCM_APB1_DEFAULT 0x03000102
> +#elif CONFIG_MACH_SUN50I_H616
> +#define CCM_PLL6_DEFAULT 0xa8003100
> +
> +/* psi_ahb1_ahb2 bit field */
> +#define CCM_PSI_AHB1_AHB2_DEFAULT0x0302

Why is this twice as fast, compared to the H6? It's based on the same
PERI0(1X), which should be 600 MHz for both the H6 and H616, right?

Is that the reset config or set up by the BROM? Or is that coming from
some BSP source?

> +
> +/* ahb3 bit field */
> +#define CCM_AHB3_DEFAULT 0x0302
> +
> +/* apb1 bit field */
> +#define CCM_APB1_DEFAULT 0x03000102
> +#endif
>  
>  /* apb2 bit field */
>  #define APB2_CLK_SRC_OSC24M  (0x0 << 24)
> diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c 
> b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> index 6bd466915c11..daca02019bab 100644
> --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> @@ -68,6 +68,9 @@ void clock_set_pll1(unsigned int clk)
>  
>   /* clk = 24*n/p, p is ignored if clock is >288MHz */
>   writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
> +#ifdef CONFIG_MACH_SUN50I_H616
> +CCM_PLL1_OUT_EN |
> +#endif
>  CCM_PLL1_CTRL_N(clk / 2400), &ccm->pll1_cfg);
>   while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
>  
> @@ -83,6 +86,7 @@ unsigned int clock_get_pll6(void)
>  {
>   struct sunxi_ccm_reg *const ccm =
>   (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> + int m = IS_ENABLED(CONFIG_MACH_SUN50I_H6) 4 : 2;

This is missing the question mark, but that gets fixed up in a later
patch, so I assume it's a rebase artifact. Will fix it up while
committing.

Cheers,
Andre

>  
>   uint32_t rval = readl(&ccm->pll6_cfg);
>   int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT);
> @@ -90,8 +94,8 @@ unsigned int clock_get_pll6(void)
>   CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
>   int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >>
>   CCM_PLL6_CTRL_DIV2_SHIFT) + 1;
> - /* The register defines PLL6-4X, not plain PLL6 */
> - return 2400 / 4 * n / div1 / div2;
> + /* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
> + return 2400 / m * n / div1 / div2;
>  }
>  
>  int clock_twi_onoff(int port, int state)

Re: [PATCH v2 06/21] sunxi: Add support for I2C on H6 like SoCs

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:38 +0100
Jernej Skrabec  wrote:

> I2C support, especially R_I2C port, will be needed in future. Upcoming
> support for H616 will need R_I2C to adjust DRAM voltage.
> 
> Reviewed-by: Samuel Holland 
> Signed-off-by: Jernej Skrabec 

Reviewed-by: Andre Przywara 

Thanks!
Andre

> ---
>  .../include/asm/arch-sunxi/clock_sun50i_h6.h  |  1 +
>  arch/arm/mach-sunxi/Kconfig   |  2 +-
>  arch/arm/mach-sunxi/clock_sun50i_h6.c | 29 +++
>  3 files changed, 31 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h 
> b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> index 426069fc69a4..e83e84ab6cab 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
> @@ -297,6 +297,7 @@ struct sunxi_ccm_reg {
>  
>  /* Module gate/reset shift*/
>  #define RESET_SHIFT  (16)
> +#define GATE_SHIFT   (0)
>  
>  /* DRAM clock bit field */
>  #define DRAM_MOD_RESET   BIT(30)
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index bd82c0ef3ee4..b23ed695cd1c 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -730,7 +730,7 @@ config I2C3_ENABLE
>   See I2C0_ENABLE help text.
>  endif
>  
> -if SUNXI_GEN_SUN6I
> +if SUNXI_GEN_SUN6I || SUN50I_GEN_H6
>  config R_I2C_ENABLE
>   bool "Enable the PRCM I2C/TWI controller"
>   # This is used for the pmic on H3
> diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c 
> b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> index ba8a26eb0d36..6bd466915c11 100644
> --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
> +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
> @@ -2,6 +2,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  #ifdef CONFIG_SPL_BUILD
>  void clock_init_safe(void)
> @@ -92,3 +93,31 @@ unsigned int clock_get_pll6(void)
>   /* The register defines PLL6-4X, not plain PLL6 */
>   return 2400 / 4 * n / div1 / div2;
>  }
> +
> +int clock_twi_onoff(int port, int state)
> +{
> + struct sunxi_ccm_reg *const ccm =
> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> + struct sunxi_prcm_reg *const prcm =
> + (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
> + u32 value, *ptr;
> + int shift;
> +
> + value = BIT(GATE_SHIFT) | BIT (RESET_SHIFT);
> +
> + if (port == 5) {
> + shift = 0;
> + ptr = &prcm->twi_gate_reset;
> + } else {
> + shift = port;
> + ptr = &ccm->twi_gate_reset;
> + }
> +
> + /* set the apb clock gate and reset for twi */
> + if (state)
> + setbits_le32(ptr, value << shift);
> + else
> + clrbits_le32(ptr, value << shift);
> +
> + return 0;
> +}

Re: [PATCH v2 05/21] sunxi: prcm: Add memory map for H6 like SoCs

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:37 +0100
Jernej Skrabec  wrote:

> There was no need to have prcm definitions for H6 and similar SoCs till
> now. However, support R_I2C will be needed soon in SPL.
> 
> Move old definitions to prcm_sun6i.h and add new ones in prcm_sun50i.h.
> One of those files will be selected in common prcm.h based on defined
> macros.
> 
> This commit doesn't do any functional change.

That looks alright.
prcm.h and prcm_sun6i.h are identical, apart from the header guards.
I could verify most of the sun50i PRCM fields by comparing to the Linux
CCU_R driver, but not all of them.
Out of curiosity, where do those offsets actually come from? Some BSP
code? And they are actually SUN50I_H6 aka. "NCAT" specific, right?

Anyway, the interesting part (R_I2C clock gate offset) is correct, so:

> Signed-off-by: Jernej Skrabec 

Reviewed-by: Andre Przywara 

Thanks,
Andre

> ---
>  arch/arm/include/asm/arch-sunxi/prcm.h| 249 +-
>  arch/arm/include/asm/arch-sunxi/prcm_sun50i.h |  47 
>  arch/arm/include/asm/arch-sunxi/prcm_sun6i.h  | 247 +
>  3 files changed, 304 insertions(+), 239 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun50i.h
>  create mode 100644 arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h 
> b/arch/arm/include/asm/arch-sunxi/prcm.h
> index 767d1ff98d74..5106076f5e91 100644
> --- a/arch/arm/include/asm/arch-sunxi/prcm.h
> +++ b/arch/arm/include/asm/arch-sunxi/prcm.h
> @@ -1,247 +1,18 @@
>  /* SPDX-License-Identifier: GPL-2.0+ */
>  /*
> - * Sunxi A31 Power Management Unit register definition.
> + * (C) Copyright 2020 Jernej Skrabec 
>   *
> - * (C) Copyright 2013 Oliver Schinagl 
> - * http://linux-sunxi.org
> - * Allwinner Technology Co., Ltd. 
> - * Berg Xing 
> - * Tom Cubie 
> + * Sunxi platform prcm register definition.
>   */
>  
>  #ifndef _SUNXI_PRCM_H
>  #define _SUNXI_PRCM_H
>  
> -#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4)
> -#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3)
> -#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1)
> -#define PRCM_CPUS_CFG_PRE_DIV(n) \
> - __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n))
> -#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8)
> -#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f)
> -#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1)
> -#define PRCM_CPUS_CFG_POST_DIV(n) \
> - __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n))
> -#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16)
> -#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3)
> -#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0
> -#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1
> -#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2
> -#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3
> -#define PRCM_CPUS_CFG_CLK_SRC_LOSC \
> - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC)
> -#define PRCM_CPUS_CFG_CLK_SRC_HOSC \
> - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC)
> -#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \
> - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6)
> -#define PRCM_CPUS_CFG_CLK_SRC_PDIV \
> - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV)
> -
> -#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0)
> -#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3)
> -#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1)
> -#define PRCM_APB0_RATIO_DIV(n) \
> - __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n))
> -
> -#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0)
> -#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1)
> -
> -#define PRCM_APB0_GATE_PIO (0x1 << 0)
> -#define PRCM_APB0_GATE_IR (0x1 << 1)
> -#define PRCM_APB0_GATE_TIMER01 (0x1 << 2)
> -#define PRCM_APB0_GATE_P2WI (0x1 << 3)   /* sun6i */
> -#define PRCM_APB0_GATE_RSB (0x1 << 3)/* sun8i */
> -#define PRCM_APB0_GATE_UART (0x1 << 4)
> -#define PRCM_APB0_GATE_1WIRE (0x1 << 5)
> -#define PRCM_APB0_GATE_I2C (0x1 << 6)
> -
> -#define PRCM_APB0_RESET_PIO (0x1 << 0)
> -#define PRCM_APB0_RESET_IR (0x1 << 1)
> -#define PRCM_APB0_RESET_TIMER01 (0x1 << 2)
> -#define PRCM_APB0_RESET_P2WI (0x1 << 3)
> -#define PRCM_APB0_RESET_UART (0x1 << 4)
> -#define PRCM_APB0_RESET_1WIRE (0x1 << 5)
> -#define PRCM_APB0_RESET_I2C (0x1 << 6)
> -
> -#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0)
> -#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1)
> -#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4)
> -#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \
> - __PRCM_PLL_CTRL_USB_CLK_SRC(0x3)
> -#define __PRCM_PLL_CTRL_USB_CLK_0 0x0
> -#define __PRCM_PLL_CTRL_USB_CLK_1 0x1
> -#define __PRCM_PLL_CTRL_USB_CLK_2 0x2
> -#define __PRCM_PLL_CTRL_USB_CLK_3 0x3
> -#define PRCM_PLL_CTRL_USB_CLK_0 \
> - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0)
> -#define PRCM_PLL_CTRL_USB_CLK_1 \
> - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1)
> -#define PRCM_PLL_CTRL_USB_CLK_2 \
> - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2)
> -#define PRCM_PLL_CTRL_USB_CLK_3 \
> - 

Re: [PATCH v2 02/21] sunxi: Introduce common symbol for H6 like SoCs

[Andre Przywara]

On Mon, 11 Jan 2021 21:11:34 +0100
Jernej Skrabec  wrote:

> It turns out that there are at least 2 other SoCs which have basically
> the same memory map, similar clocks and other features as H6. It's very
> likely that we'll see more such SoCs in the future. In order to ease
> porting to new SoCs and lower ifdef clutter, introduce common symbol for
> them.
> 
> Signed-off-by: Jernej Skrabec 

Confirmed to be the correct transformations.

Reviewed-by: Andre Przywara 

Thanks!
Andre


> ---
>  arch/arm/include/asm/arch-sunxi/boot0.h |  2 +-
>  arch/arm/include/asm/arch-sunxi/clock.h |  2 +-
>  arch/arm/include/asm/arch-sunxi/cpu.h   |  2 +-
>  arch/arm/include/asm/arch-sunxi/timer.h |  2 +-
>  arch/arm/mach-sunxi/Kconfig | 19 +--
>  arch/arm/mach-sunxi/Makefile|  2 +-
>  arch/arm/mach-sunxi/board.c |  4 ++--
>  arch/arm/mach-sunxi/rmr_switch.S|  2 +-
>  common/spl/Kconfig  |  4 ++--
>  include/configs/sun50i.h|  2 +-
>  10 files changed, 24 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h 
> b/arch/arm/include/asm/arch-sunxi/boot0.h
> index 46d0f0666c2b..e8e8e38f0556 100644
> --- a/arch/arm/include/asm/arch-sunxi/boot0.h
> +++ b/arch/arm/include/asm/arch-sunxi/boot0.h
> @@ -39,7 +39,7 @@
>   .word   0xf57ff06f  // isb sy
>   .word   0xe320f003  // wfi
>   .word   0xeafd  // b   @wfi
> -#ifndef CONFIG_MACH_SUN50I_H6
> +#ifndef CONFIG_SUN50I_GEN_H6
>   .word   0x017000a0  // writeable RVBAR mapping address
>  #else
>   .word   0x09010040  // writeable RVBAR mapping address
> diff --git a/arch/arm/include/asm/arch-sunxi/clock.h 
> b/arch/arm/include/asm/arch-sunxi/clock.h
> index 5994130e6b54..cbbe5c7a1e68 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock.h
> @@ -16,7 +16,7 @@
>  /* clock control module regs definition */
>  #if defined(CONFIG_MACH_SUN8I_A83T)
>  #include 
> -#elif defined(CONFIG_MACH_SUN50I_H6)
> +#elif defined(CONFIG_SUN50I_GEN_H6)
>  #include 
>  #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
>defined(CONFIG_MACH_SUN50I)
> diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h 
> b/arch/arm/include/asm/arch-sunxi/cpu.h
> index 8b57d24e2f0c..b08f2023748c 100644
> --- a/arch/arm/include/asm/arch-sunxi/cpu.h
> +++ b/arch/arm/include/asm/arch-sunxi/cpu.h
> @@ -8,7 +8,7 @@
>  
>  #if defined(CONFIG_MACH_SUN9I)
>  #include 
> -#elif defined(CONFIG_MACH_SUN50I_H6)
> +#elif defined(CONFIG_SUN50I_GEN_H6)
>  #include 
>  #else
>  #include 
> diff --git a/arch/arm/include/asm/arch-sunxi/timer.h 
> b/arch/arm/include/asm/arch-sunxi/timer.h
> index 6f138d04b806..bb5626d893bb 100644
> --- a/arch/arm/include/asm/arch-sunxi/timer.h
> +++ b/arch/arm/include/asm/arch-sunxi/timer.h
> @@ -76,7 +76,7 @@ struct sunxi_timer_reg {
>   struct sunxi_tgp tgp[4];
>   u8 res5[8];
>   u32 cpu_cfg;
> -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
> +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6)
>   u8 res3[16];
>   struct sunxi_wdog wdog[5];  /* We have 5 watchdogs */
>  #endif
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 49ef217f08c0..bd82c0ef3ee4 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -82,7 +82,7 @@ config SUN8I_RSB
>  config SUNXI_SRAM_ADDRESS
>   hex
>   default 0x1 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
> - default 0x2 if MACH_SUN50I_H6
> + default 0x2 if SUN50I_GEN_H6
>   default 0x0
>   ---help---
>   Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
> @@ -108,6 +108,15 @@ config SUNXI_GEN_SUN6I
>   separate ahb reset control registers, custom pmic bus, new style
>   watchdog, etc.
>  
> +config SUN50I_GEN_H6
> + bool
> + select FIT
> + select SPL_LOAD_FIT
> + select SUPPORT_SPL
> + ---help---
> + Select this for sunxi SoCs which have H6 like peripherals, clocks
> + and memory map.
> +
>  config SUNXI_DRAM_DW
>   bool
>   ---help---
> @@ -302,11 +311,9 @@ config MACH_SUN50I_H5
>  config MACH_SUN50I_H6
>   bool "sun50i (Allwinner H6)"
>   select ARM64
> - select SUPPORT_SPL
> - select FIT
>   select PHY_SUN4I_USB
> - select SPL_LOAD_FIT
>   select DRAM_SUN50I_H6
> + select SUN50I_GEN_H6
>  
>  endchoice
>  
> @@ -756,7 +763,7 @@ config VIDEO_SUNXI
>   depends on !MACH_SUN8I_V3S
>   depends on !MACH_SUN9I
>   depends on !MACH_SUN50I
> - depends on !MACH_SUN50I_H6
> + depends on !SUN50I_GEN_H6
>   select VIDEO
>   imply VIDEO_DT_SIMPLEFB
>   default y
> @@ -989,7 +996,7 @@ config SPL_STACK_R_ADDR
>   default 0x4fe0 if MACH_SUN8I
>   default 0x2fe0 if MACH_SUN9I
>   default 0x4fe0 if MACH_SUN50I
> - default

[PATCH 11/11] binman: Print a debug message when binman selects a node

[Simon Glass]

Add some debugging to indicate which node the binman library is looking
at.

Signed-off-by: Simon Glass 
---

 lib/binman.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/lib/binman.c b/lib/binman.c
index f415df30545..6040ec89241 100644
--- a/lib/binman.c
+++ b/lib/binman.c
@@ -145,6 +145,8 @@ int binman_init(void)
if (ret)
return log_msg_ret("node", -ENOENT);
binman_set_rom_offset(ROM_OFFSET_NONE);
+   log_debug("binman: Selected image node '%s'\n",
+ ofnode_get_name(binman->image));
 
return 0;
 }
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 10/11] Add a symlink for ctype.h

[Simon Glass]

Libraries that link with U-Boot typically may expect to be able to include
ctype.h but this file is in a different place in U-Boot. Add a symlink to
make this work.

Signed-off-by: Simon Glass 
---

 include/ctype.h | 1 +
 1 file changed, 1 insertion(+)
 create mode 12 include/ctype.h

diff --git a/include/ctype.h b/include/ctype.h
new file mode 12
index 000..9e43f9c6c6c
--- /dev/null
+++ b/include/ctype.h
@@ -0,0 +1 @@
+linux/ctype.h
\ No newline at end of file
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 09/11] dm: core: Update ofnode_read_fmap_entry() to read hashes

[Simon Glass]

At present this function uses the old format for reading hashes. Add
support for the current format.

Add a test while we are here.

Signed-off-by: Simon Glass 
---

 arch/sandbox/dts/test.dts | 10 ++
 drivers/core/of_extra.c   | 21 -
 test/dm/Makefile  |  1 +
 test/dm/of_extra.c| 38 ++
 4 files changed, 61 insertions(+), 9 deletions(-)
 create mode 100644 test/dm/of_extra.c

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index f86cd0d3b27..e95f4631bf2 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -90,6 +90,16 @@
wp-ro {
image-pos = <0xf000>;
size = <0x1000>;
+   used = <0x884>;
+   compress = "lz4";
+   uncomp-size = <0xcf8>;
+   hash {
+   algo = "sha256";
+   value = [00 01 02 03 04 05 06 07
+   08 09 0a 0b 0c 0d 0e 0f
+   10 11 12 13 14 15 16 17
+   18 19 1a 1b 1c 1d 1e 1f];
+   };
};
rw {
image-pos = <0x1>;
diff --git a/drivers/core/of_extra.c b/drivers/core/of_extra.c
index 6420e6ec448..653344529e6 100644
--- a/drivers/core/of_extra.c
+++ b/drivers/core/of_extra.c
@@ -14,16 +14,17 @@
 int ofnode_read_fmap_entry(ofnode node, struct fmap_entry *entry)
 {
const char *prop;
+   ofnode subnode;
 
if (ofnode_read_u32(node, "image-pos", &entry->offset)) {
debug("Node '%s' has bad/missing 'image-pos' property\n",
  ofnode_get_name(node));
-   return log_ret(-ENOENT);
+   return log_msg_ret("image-pos", -ENOENT);
}
if (ofnode_read_u32(node, "size", &entry->length)) {
debug("Node '%s' has bad/missing 'size' property\n",
  ofnode_get_name(node));
-   return log_ret(-ENOENT);
+   return log_msg_ret("size", -ENOENT);
}
entry->used = ofnode_read_s32_default(node, "used", entry->length);
prop = ofnode_read_string(node, "compress");
@@ -31,18 +32,20 @@ int ofnode_read_fmap_entry(ofnode node, struct fmap_entry 
*entry)
if (!strcmp(prop, "lz4"))
entry->compress_algo = FMAP_COMPRESS_LZ4;
else
-   return log_msg_ret("Unknown compression algo",
-  -EINVAL);
+   return log_msg_ret("compression algo", -EINVAL);
} else {
entry->compress_algo = FMAP_COMPRESS_NONE;
}
entry->unc_length = ofnode_read_s32_default(node, "uncomp-size",
entry->length);
-   prop = ofnode_read_string(node, "hash");
-   if (prop)
-   entry->hash_size = strlen(prop);
-   entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE;
-   entry->hash = (uint8_t *)prop;
+   subnode = ofnode_find_subnode(node, "hash");
+   if (ofnode_valid(subnode)) {
+   prop = ofnode_read_prop(subnode, "value", &entry->hash_size);
+
+   /* Assume it is sha256 */
+   entry->hash_algo = prop ? FMAP_HASH_SHA256 : FMAP_HASH_NONE;
+   entry->hash = (uint8_t *)prop;
+   }
 
return 0;
 }
diff --git a/test/dm/Makefile b/test/dm/Makefile
index 46e076ed099..32104f7a5b3 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -41,6 +41,7 @@ obj-y += fdtdec.o
 obj-$(CONFIG_UT_DM) += nop.o
 obj-y += ofnode.o
 obj-y += ofread.o
+obj-y += of_extra.o
 obj-$(CONFIG_OSD) += osd.o
 obj-$(CONFIG_DM_VIDEO) += panel.o
 obj-$(CONFIG_DM_PCI) += pci.o
diff --git a/test/dm/of_extra.c b/test/dm/of_extra.c
new file mode 100644
index 000..b19cd3787d8
--- /dev/null
+++ b/test/dm/of_extra.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ * Written by Simon Glass 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static int dm_test_ofnode_read_fmap_entry(struct unit_test_state *uts)
+{
+   const char hash_expect[] = {
+   0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+   0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+   0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+   0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
+   };
+   struct fmap_entry entry;
+   ofnode node;
+
+   node = ofnode_path("/cros-ec/flash/wp-ro");
+   ut_assertok(ofnode_read_fmap_entry(node, &entry));
+   ut_asserteq(0xf000, entry.offset);
+   ut_ass

[PATCH 07/11] clk: x86: Correct the driver name

[Simon Glass]

The current driver name does not match its compatible string, so
of-platdata does not work correctly. Fix it.

Signed-off-by: Simon Glass 
---

 drivers/clk/intel/clk_intel.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/intel/clk_intel.c b/drivers/clk/intel/clk_intel.c
index b633934d90a..46ccbb1d834 100644
--- a/drivers/clk/intel/clk_intel.c
+++ b/drivers/clk/intel/clk_intel.c
@@ -29,8 +29,8 @@ static const struct udevice_id intel_clk_ids[] = {
{ }
 };
 
-U_BOOT_DRIVER(clk_intel) = {
-   .name   = "clk_intel",
+U_BOOT_DRIVER(intel_apl_clk) = {
+   .name   = "intel_apl_clk",
.id = UCLASS_CLK,
.of_match   = intel_clk_ids,
.ops= &intel_clk_ops,
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 08/11] dm: core: Add a comment about pinctrl_select_state()

[Simon Glass]

The use of pinctrl in the core of driver model is useful but can provoke
some strange behaviour. Add a comment to aid debugging.

Signed-off-by: Simon Glass 
---

 drivers/core/device.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/core/device.c b/drivers/core/device.c
index aeab3836ed7..8629df8defb 100644
--- a/drivers/core/device.c
+++ b/drivers/core/device.c
@@ -462,6 +462,15 @@ int device_probe(struct udevice *dev)
 * continue regardless of the result of pinctrl. Don't process pinctrl
 * settings for pinctrl devices since the device may not yet be
 * probed.
+*
+* This call can produce some non-intuitive results. For example, on an
+* x86 device where dev is the main PCI bus, the pinctrl device may be
+* child or grandchild of that bus, meaning that the child will be
+* probed here. If the child happens to be the P2SB and the pinctrl
+* device is a child of that, then both the pinctrl and P2SB will be
+* probed by this call. This works because the DM_FLAG_ACTIVATED flag
+* is set just above. However, the PCI bus' probe() method and
+* associated uclass methods have not yet been called.
 */
if (dev->parent && device_get_uclass_id(dev) != UCLASS_PINCTRL)
pinctrl_select_state(dev, "default");
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 06/11] clk: Add debugging for return values

[Simon Glass]

Use the log_msg_ret() mechanism to get error-return information when
clocks fail to probe, etc.

Signed-off-by: Simon Glass 
---

 drivers/clk/clk-uclass.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/clk-uclass.c b/drivers/clk/clk-uclass.c
index b75056718bf..d5c4e3cbe51 100644
--- a/drivers/clk/clk-uclass.c
+++ b/drivers/clk/clk-uclass.c
@@ -83,7 +83,7 @@ static int clk_get_by_index_tail(int ret, ofnode node,
if (ret) {
debug("%s: uclass_get_device_by_of_offset failed: err=%d\n",
  __func__, ret);
-   return ret;
+   return log_msg_ret("get", ret);
}
 
clk->dev = dev_clk;
@@ -96,14 +96,15 @@ static int clk_get_by_index_tail(int ret, ofnode node,
ret = clk_of_xlate_default(clk, args);
if (ret) {
debug("of_xlate() failed: %d\n", ret);
-   return ret;
+   return log_msg_ret("xlate", ret);
}
 
return clk_request(dev_clk, clk);
 err:
debug("%s: Node '%s', property '%s', failed to request CLK index %d: 
%d\n",
  __func__, ofnode_get_name(node), list_name, index, ret);
-   return ret;
+
+   return log_msg_ret("prop", ret);
 }
 
 static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name,
@@ -122,7 +123,7 @@ static int clk_get_by_indexed_prop(struct udevice *dev, 
const char *prop_name,
if (ret) {
debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n",
  __func__, ret);
-   return ret;
+   return log_ret(ret);
}
 
 
@@ -470,6 +471,7 @@ int clk_free(struct clk *clk)
 ulong clk_get_rate(struct clk *clk)
 {
const struct clk_ops *ops;
+   int ret;
 
debug("%s(clk=%p)\n", __func__, clk);
if (!clk_valid(clk))
@@ -479,7 +481,11 @@ ulong clk_get_rate(struct clk *clk)
if (!ops->get_rate)
return -ENOSYS;
 
-   return ops->get_rate(clk);
+   ret = ops->get_rate(clk);
+   if (ret)
+   return log_ret(ret);
+
+   return 0;
 }
 
 struct clk *clk_get_parent(struct clk *clk)
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 04/11] sandbox: Disable I2C emulators in SPL

[Simon Glass]

These cannot work with of-platdata since they currently need the
devicetree at runtime. Disable the emulators and the sandbox I2C driver
that needs them. We can enable these later, if needed for testing.

Switch the of_plat_parent test over to use a simple bus instead.

Signed-off-by: Simon Glass 
---

 arch/sandbox/dts/sandbox.dtsi | 10 +++---
 configs/sandbox_spl_defconfig |  1 -
 drivers/i2c/Makefile  |  2 ++
 test/dm/of_platdata.c |  8 
 4 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi
index d842f021760..dc933f3bfc7 100644
--- a/arch/sandbox/dts/sandbox.dtsi
+++ b/arch/sandbox/dts/sandbox.dtsi
@@ -260,10 +260,14 @@
stringarray = "pre-proper";
};
 
-   spl-test7 {
+   test-bus {
+   compatible = "simple-bus";
u-boot,dm-spl;
-   compatible = "sandbox,spl-test";
-   stringarray = "spl";
+   spl-test7 {
+   u-boot,dm-spl;
+   compatible = "sandbox,spl-test";
+   stringarray = "spl";
+   };
};
 
square {
diff --git a/configs/sandbox_spl_defconfig b/configs/sandbox_spl_defconfig
index d193b18f47e..61dae34a6a2 100644
--- a/configs/sandbox_spl_defconfig
+++ b/configs/sandbox_spl_defconfig
@@ -101,7 +101,6 @@ CONFIG_SYSCON=y
 CONFIG_SPL_SYSCON=y
 CONFIG_DEVRES=y
 CONFIG_DEBUG_DEVRES=y
-# CONFIG_SPL_SIMPLE_BUS is not set
 CONFIG_ADC=y
 CONFIG_ADC_SANDBOX=y
 CONFIG_AXI=y
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 1aac5c481e2..29aab0f9e30 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -39,7 +39,9 @@ obj-$(CONFIG_SYS_I2C_RCAR_I2C) += rcar_i2c.o
 obj-$(CONFIG_SYS_I2C_RCAR_IIC) += rcar_iic.o
 obj-$(CONFIG_SYS_I2C_ROCKCHIP) += rk_i2c.o
 obj-$(CONFIG_SYS_I2C_S3C24X0) += s3c24x0_i2c.o exynos_hs_i2c.o
+ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
+endif
 obj-$(CONFIG_SYS_I2C_SH) += sh_i2c.o
 obj-$(CONFIG_SYS_I2C_SOFT) += soft_i2c.o
 obj-$(CONFIG_SYS_I2C_STM32F7) += stm32f7_i2c.o
diff --git a/test/dm/of_platdata.c b/test/dm/of_platdata.c
index cfc43a5b038..26c50922c56 100644
--- a/test/dm/of_platdata.c
+++ b/test/dm/of_platdata.c
@@ -210,11 +210,11 @@ DM_TEST(dm_test_of_plat_phandle, UT_TESTF_SCAN_PDATA);
 /* Test that device parents are correctly set up */
 static int dm_test_of_plat_parent(struct unit_test_state *uts)
 {
-   struct udevice *rtc, *i2c;
+   struct udevice *dev, *bus;
 
-   ut_assertok(uclass_first_device_err(UCLASS_RTC, &rtc));
-   ut_assertok(uclass_first_device_err(UCLASS_I2C, &i2c));
-   ut_asserteq_ptr(i2c, dev_get_parent(rtc));
+   ut_assertok(uclass_first_device_err(UCLASS_SIMPLE_BUS, &bus));
+   ut_assertok(device_first_child_err(bus, &dev));
+   ut_asserteq_ptr(bus, dev_get_parent(dev));
 
return 0;
 }
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 05/11] dm: core: Don't inline dev_read...() calls with of-platdata

[Simon Glass]

At present if these calls are used with of-platdata, a confusing error is
produced, referring to a function not actually called by the code causing
the problem.

Fix this by not inlining, so that the error mentions the dev_read_...()
function and it is more obvious what is going on.

Signed-off-by: Simon Glass 
---

 include/dm/read.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/dm/read.h b/include/dm/read.h
index c875e11a132..f6f8b875d1c 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -30,8 +30,7 @@ static inline const struct device_node *dev_np(const struct 
udevice *dev)
 }
 #endif
 
-#ifndef CONFIG_DM_DEV_READ_INLINE
-
+#if !defined(CONFIG_DM_DEV_READ_INLINE) || CONFIG_IS_ENABLED(OF_PLATDATA)
 /**
  * dev_read_u32() - read a 32-bit integer from a device's DT property
  *
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 03/11] i2c: desigware: Add an alias for Intel Apollo Lake

[Simon Glass]

Add an alias so that this driver can be used in TPL on coral.

Signed-off-by: Simon Glass 
---

 drivers/i2c/designware_i2c_pci.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c
index ec0cdf62207..9e387737b6e 100644
--- a/drivers/i2c/designware_i2c_pci.c
+++ b/drivers/i2c/designware_i2c_pci.c
@@ -192,6 +192,8 @@ static const struct udevice_id designware_i2c_pci_ids[] = {
{ }
 };
 
+DM_DRIVER_ALIAS(i2c_designware_pci, intel_apl_i2c)
+
 U_BOOT_DRIVER(i2c_designware_pci) = {
.name   = "i2c_designware_pci",
.id = UCLASS_I2C,
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 02/11] x86: coral: Support TPM and RTC in SPL

[Simon Glass]

Update the devicetree so that the TPM and RTC can be used in SPL. Also
enable the pins used for getting the memory configuration settings while
we are here.

Signed-off-by: Simon Glass 
---

 arch/x86/dts/chromebook_coral.dts| 20 +++-
 arch/x86/include/asm/arch-apollolake/iomap.h |  3 +++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/x86/dts/chromebook_coral.dts 
b/arch/x86/dts/chromebook_coral.dts
index bfbdd517d1f..2ffe3b423c3 100644
--- a/arch/x86/dts/chromebook_coral.dts
+++ b/arch/x86/dts/chromebook_coral.dts
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /dts-v1/;
 
+#include 
 #include 
 
 /include/ "skeleton.dtsi"
@@ -99,6 +100,7 @@
clk: clock {
compatible = "intel,apl-clk";
#clock-cells = <1>;
+   u-boot,dm-pre-reloc;
};
 
cpus {
@@ -139,6 +141,7 @@
};
 
acpi_gpe: general-purpose-events {
+   u-boot,dm-pre-reloc;
reg = ;
compatible = "intel,acpi-gpe";
interrupt-controller;
@@ -417,8 +420,10 @@
};
 
i2c_2: i2c2@16,2 {
-   compatible = "intel,apl-i2c";
+   compatible = "intel,apl-i2c", "snps,designware-i2c-pci";
reg = <0x0200b210 0 0 0 0>;
+   early-regs = ;
+   u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <40>;
@@ -429,6 +434,7 @@
tpm: tpm@50 {
reg = <0x50>;
compatible = "google,cr50";
+   u-boot,dm-pre-reloc;
u-boot,i2c-offset-len = <0>;
ready-gpios = <&gpio_n 28 GPIO_ACTIVE_LOW>;
interrupts-extended = <&acpi_gpe GPIO_28_IRQ
@@ -589,6 +595,7 @@
u-boot,dm-pre-reloc;
cros_ec: cros-ec {
u-boot,dm-pre-proper;
+   u-boot,dm-vpl;
compatible = "google,cros-ec-lpc";
reg = <0x204 1 0x200 1 0x880 0x80>;
 
@@ -664,6 +671,11 @@
PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1)   /* LPC_AD3 */
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1) /* LPC_CLKRUN_N */
PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1) /* LPC_FRAME_N */
+
+   PAD_CFG_GPI(GPIO_101, NONE, DEEP) /* FST_IO2 -- MEM_CONFIG0 */
+   PAD_CFG_GPI(GPIO_102, NONE, DEEP) /* FST_IO3 -- MEM_CONFIG1 */
+   PAD_CFG_GPI(GPIO_38, NONE, DEEP) /* LPSS_UART0_RXD - 
MEM_CONFIG2*/
+   PAD_CFG_GPI(GPIO_45, NONE, DEEP) /* LPSS_UART1_CTS - 
MEM_CONFIG3 */
>;
 };
 
@@ -1217,3 +1229,9 @@
PAD_CFG_GPI(GPIO_73, UP_20K, DEEP)   /* GP_CAMERASB11 */
>;
 };
+
+&rtc {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/x86/include/asm/arch-apollolake/iomap.h 
b/arch/x86/include/asm/arch-apollolake/iomap.h
index 21c5f33021a..a4ea1507073 100644
--- a/arch/x86/include/asm/arch-apollolake/iomap.h
+++ b/arch/x86/include/asm/arch-apollolake/iomap.h
@@ -33,6 +33,9 @@
 #define SRAM_SIZE_2(4 * KiB)
 #endif
 
+/* Early address for I2C port 2 */
+#define IOMAP_I2C2_BASE(0xfe02 + 2 * 0x1000)
+
 /*
  * Use UART2. To use UART1 you need to set '2' to '1', change device tree 
serial
  * node name and 'reg' property, and update CONFIG_DEBUG_UART_BASE.
-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 00/11] More minor clean-ups and improvements

[Simon Glass]

This series includes a collection of small things noticed while bringing
up verified boot on Coral.


Simon Glass (11):
  spl: Tidy up SPL/TPL malloc sizes
  x86: coral: Support TPM and RTC in SPL
  i2c: desigware: Add an alias for Intel Apollo Lake
  sandbox: Disable I2C emulators in SPL
  dm: core: Don't inline dev_read...() calls with of-platdata
  clk: Add debugging for return values
  clk: x86: Correct the driver name
  dm: core: Add a comment about pinctrl_select_state()
  dm: core: Update ofnode_read_fmap_entry() to read hashes
  Add a symlink for ctype.h
  binman: Print a debug message when binman selects a node

 Kconfig  | 13 ---
 arch/sandbox/dts/sandbox.dtsi| 10 --
 arch/sandbox/dts/test.dts| 10 ++
 arch/x86/dts/chromebook_coral.dts| 20 ++-
 arch/x86/include/asm/arch-apollolake/iomap.h |  3 ++
 configs/sandbox_spl_defconfig|  1 -
 drivers/clk/clk-uclass.c | 16 ++---
 drivers/clk/intel/clk_intel.c|  4 +--
 drivers/core/device.c|  9 +
 drivers/core/of_extra.c  | 21 ++-
 drivers/i2c/Makefile |  2 ++
 drivers/i2c/designware_i2c_pci.c |  2 ++
 include/ctype.h  |  1 +
 include/dm/read.h|  3 +-
 lib/binman.c |  2 ++
 test/dm/Makefile |  1 +
 test/dm/of_extra.c   | 38 
 test/dm/of_platdata.c|  8 ++---
 18 files changed, 132 insertions(+), 32 deletions(-)
 create mode 12 include/ctype.h
 create mode 100644 test/dm/of_extra.c

-- 
2.30.0.280.ga3ce27912f-goog

[PATCH 01/11] spl: Tidy up SPL/TPL malloc sizes

[Simon Glass]

The current help talks about relocation which doesn't apply to SPL and
TPL. Update it to avoid confusion.

Also make the TPL size default to the same as the SPL size, since this is
more likely to be a useful value than the one used by U-Boot proper, which
may be quite a bit larger.

Signed-off-by: Simon Glass 
---

 Kconfig | 13 -
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/Kconfig b/Kconfig
index 6dc20ed25b2..86f0a39bb08 100644
--- a/Kconfig
+++ b/Kconfig
@@ -217,22 +217,25 @@ config SYS_MALLOC_LEN
  TODO: Use for other architectures
 
 config SPL_SYS_MALLOC_F_LEN
-   hex "Size of malloc() pool in SPL before relocation"
+   hex "Size of malloc() pool in SPL"
depends on SYS_MALLOC_F && SPL
default 0x2800 if RCAR_GEN3
default SYS_MALLOC_F_LEN
help
- Before relocation, memory is very limited on many platforms. Still,
+ In SPL memory is very limited on many platforms. Still,
  we can provide a small malloc() pool if needed. Driver model in
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.
 
+ It is possible to enable CONFIG_SYS_SPL_MALLOC_START to start a new
+ malloc() region in SDRAM once it is inited.
+
 config TPL_SYS_MALLOC_F_LEN
-   hex "Size of malloc() pool in TPL before relocation"
+   hex "Size of malloc() pool in TPL"
depends on SYS_MALLOC_F && TPL
-   default SYS_MALLOC_F_LEN
+   default SPL_SYS_MALLOC_F_LEN
help
- Before relocation, memory is very limited on many platforms. Still,
+ In TPL memory is very limited on many platforms. Still,
  we can provide a small malloc() pool if needed. Driver model in
  particular needs this to operate, so that it can allocate the
  initial serial device and any others that are needed.
-- 
2.30.0.280.ga3ce27912f-goog

Re: Pull request: u-boot-rockchip-20210121

[Tom Rini]

On Thu, Jan 21, 2021 at 06:07:17PM +0800, Kever Yang wrote:

> Hi Tom,
> 
> Please pull the rockchip updates/fixes:
> - New board: rk3328 NanoPi R2S board;
> - Fix init voltage for some rk3399 boards;
> - enable rng for rk3399 by default;
> - set default to SPI bus 1 for SPI-flash for some board;
> - add dwc PCIe controller driver on rockchip platform;
> 
> Gitlab ci:
> https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip/pipelines/5992
> 
> Thanks,
> - Kever
> 
> The following changes since commit 83433fdab4920e206700bca33b9040c7978afc9d:
> 
>   Merge branch '2021-01-20-fs-fixes' (2021-01-20 16:45:43 -0500)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git 
> tags/u-boot-rockchip-20210121
> 
> for you to fetch changes up to 9ddc0787bd660214366e386ce689dd78299ac9d0:
> 
>   pci: Add Rockchip dwc based PCIe controller driver (2021-01-21 12:00:45 
> +0800)
> 

Applied to u-boot/master, thanks!

-- 
Tom


signature.asc
Description: PGP signature

Re: Xilinx ZynqMP SPL boot: psu_init_gpl.c code corrupts U-Boot memory

[Robert Hancock]

Hi Michal,

On Thu, 2021-01-21 at 09:41 +0100, Michal Simek wrote:
> Hi,
> 
> On 1/20/21 9:25 PM, Robert Hancock wrote:
> > I've been trying to get the U-Boot SPL to work on a Xilinx ZCU102
> > development board. I have been testing with U-Boot 2021.01, and using
> > the generated psu_init_gpl HW initialization code generated by Vivado
> > 2020.2, rather than the versions in the U-Boot tree, as we are
> > expecting to make changes to the configuration as we move to our own
> > board design.
> > 
> > The issue I was seeing is that the SPL seemingly locking up or crashing
> > early in the boot process, just after the SPL banner was printed. I've
> > CCed "Major A" as he reported something similar on the mailing list in
> > March ('ZynqMP boot: no messages from SPL other than "Debug uart
> > enabled"') but I didn't see a resoution posted.
> > 
> > After groveling around with the Xilinx JTAG debugger for a day or so, I
> > figured out that the problem was that the SPL ended up reading from an
> > invalid pointer address somewhere during the driver model
> > initialization process, and crashing. After using memory watchpoints to
> > identify where the bogus value was being written to the pointer storage
> > location, the memory write was actually coming from the Vivado 2020.2-
> > generated psu_init_gpl code. The offending code is in a function called
> > serdes_illcalib_pcie_gen1 and looks like this:
> > 
> >   if (gen2_calib != 1) 
> >   {
> > ill1_val[loop] = ((0x04 + meancount[loop]*8) % 0x100);
> > ill12_val[loop] = ((0x04 + meancount[loop]*8) >= 0x100) ?
> > 0x10 : 0x00;
> > Xil_Out32(0xFFFE+loop*4,iterresult[loop]);
> > Xil_Out32(0xFFFE0010+loop*4,iterresult[loop+4]);
> > Xil_Out32(0xFFFE0020+loop*4,bistpasscount[loop]);
> > Xil_Out32(0xFFFE0030+loop*4,meancount[loop]);
> >   }
> >   if (gen2_calib == 1) 
> >   {
> > ill1_val[loop] = ((0x104 + meancount[loop]*8) % 0x100);
> > ill12_val[loop] = ((0x104 + meancount[loop]*8) >= 0x200) ?
> > 0x02 : 0x01;
> > Xil_Out32(0xFFFE0040+loop*4,iterresult[loop]);
> > Xil_Out32(0xFFFE0050+loop*4,iterresult[loop+4]);
> > Xil_Out32(0xFFFE0060+loop*4,bistpasscount[loop]);
> > Xil_Out32(0xFFFE0070+loop*4,meancount[loop]);
> >   }
> > 
> > Those writes to 0xFFFE are to on-chip memory addresses, not any
> > hardware register, so I have no idea what this is trying to achieve.
> > Possibly this is some debug code to store some calibration results that
> > was left in by mistake? Those addresses may not be used in the Xilinx
> > FSBL, but overwriting them in the U-Boot SPL wreaks havoc.
> > 
> > For now, I've worked around it by hacking the Xil_Out32 implementation
> > provided by U-Boot in board/xilinx/zynqmp/xil_io.h to trap and ignore
> > writes to memory addresses in the OCRAM range (0xFFFC to
> > 0x). With that in place, things seem to be working. Probably
> > this should be addressed in the Vivado psu_init code generator, but we
> > may need some workaround like this to avoid those using the affected
> > Xilinx tool versions from hitting this issue?
> > 
> 
> I can't see any code like this in u-boot code. I can't see context of
> this code that's why simply don't know what it does and why.

I can email the psu_init_gpl code I have privately if you need it - the code is
almost 1MB so too large for the list or the usual Pastebin etc. it seems.
However, you can see similar code in this file from ZCU102 in the Xilinx
embeddedsw repo:

https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_apps/zynqmp_fsbl/misc/zcu102/psu_init_gpl.c

That has writes to 0xFFFE addresses in the serdes_illcalib_pcie_gen1
function, like mine has, as well as in its serdes_illcalib which don't seem to
be in the version I have. Looking at the git history, it appears those writes
were added in a commit that updated the file for the 2020.2 tools release, so
that may have been when this was introduced.

I don't see any such writes in the psu_init_gpl files in the U-Boot repo, I am
guessing because those were all generated using older tool versions that didn't
have this behavior.

Interestingly, looking at the 2020.2 Petalinux BSP for ZCU102 in its provided
xilinx-zcu102-2020.2/project-spec/hw-description/psu_init_gpl.c file, those
memory writes are there but have been commented out. Not sure if it somehow
generated that way or if someone realized that issue and did that manually?


> And also not sure what you want me to do with this. Please suggest.

The main purpose was to let the community know of this issue as others working
with ZynqMP hardware may run into this with the current Xilinx tools.

I have this patch locally to work around this issue right now. We may want
something like this in U-Boot as even if the Xilinx tools are eventually
updated to not do these writes, people using a

Re: arm: rk3399: add support nanopi r4s

[alex tian]

>From 0c1b6b9c696f7bbdb91119af033e598e4b8d2f81 Mon Sep 17 00:00:00 2001
From: Xiaobo Tian 
Date: Sat, 26 Dec 2020 00:13:37 +0800
Subject: [PATCH] arm: rk3399: add support nanopi r4s
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

SoC – Rockchip RK3399 hexa-core processor with dual-Core Cortex-A72 up to
2.0GHz, quad-core Cortex-A53 up to 1.5GHz, Mali-T864 GPU with OpenGL
ES1.1/2.0/3.0/3.1, OpenCL, DX11, and AFBC support, 4K VP9 and 4K 10-bit
H265/H264 60fps video decoder
System Memory – 1GB DDR3 or 4GB LPDDR4
Storage – MicroSD card slot
Networking – 2x GbE(RTL8211E 1Gbps - RTL8111H 1Gbps), including one native
Gigabit Ethernet, and one PCIe Gigabit Ethernet
USB – 2x USB 3.0 Type-A ports, USB 2.0 via 4-pin header
Expansion – 2×5-pin header with 1x SPI, 1x I2C
Debugging – 3-pin debug UART header
Misc- 1x power LED, and 3x user LEDs (SYS, LAN, WAN), user button, 2-pin
RTC battery connector, 5V fan connector
Power Supply
5V/3A via USB-C connector or pin header
RK808-D PMIC and independent DC/DC enabling DVFS, software power-down, RTC
wake-up, system sleep mode
Dimensions – 66 x 66 mm (8-layer PCB)
Temperature Range – -20°C to 70°C
The detailed information for NanoPi R4S <
https://wiki.friendlyarm.com/wiki/index.php/NanoPi_R4S>

Signed-off-by: Xiaobo Tian 
---
 arch/arm/dts/Makefile  |   1 +
 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi |   7 ++
 arch/arm/dts/rk3399-nanopi-r4s.dts | 120 +
 configs/nanopi-r4s-rk3399_defconfig|  62 +++
 4 files changed, 190 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-nanopi-r4s.dts
 create mode 100644 configs/nanopi-r4s-rk3399_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e320c2254e..507b1e4ec9 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -92,6 +92,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \
  rk3288-evb.dtb \
  rk3288-firefly.dtb \
  rk3288-miqi.dtb \
+ rk3399-nanopi-r4s.dtb \
  rk3288-phycore-rdk.dtb \
  rk3288-popmetal.dtb \
  rk3288-rock2-square.dtb \
diff --git a/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
new file mode 100644
index 00..05f785e662
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4s-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Xiaobo 
+ */
+
+#include "rk3399-nanopi4-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
diff --git a/arch/arm/dts/rk3399-nanopi-r4s.dts
b/arch/arm/dts/rk3399-nanopi-r4s.dts
new file mode 100644
index 00..5c65447f0e
--- /dev/null
+++ b/arch/arm/dts/rk3399-nanopi-r4s.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 FriendlyElec Computer Tech. Co., Ltd.
+ * (http://www.friendlyarm.com)
+ *
+ * Copyright (C) 2020 Xiaobo 
+ */
+
+/dts-v1/;
+#include "rk3399-nanopi4.dtsi"
+
+/ {
+ model = "FriendlyElec NanoPi R4S";
+ compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
+
+ vdd_5v: vdd-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "vdd_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ fan: pwm-fan {
+ compatible = "pwm-fan";
+ /* FIXME: adjust leveles for the connected fan */
+ cooling-levels = <0 12 18 255>;
+ #cooling-cells = <2>;
+ fan-supply = <&vdd_5v>;
+ pwms = <&pwm1 0 5 0>;
+ };
+};
+
+&cpu_thermal {
+ trips {
+ cpu_warm: cpu_warm {
+ temperature = <55000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+
+ cpu_hot: cpu_hot {
+ temperature = <65000>;
+ hysteresis = <2000>;
+ type = "active";
+ };
+ };
+
+ cooling-maps {
+ map2 {
+ trip = <&cpu_warm>;
+ cooling-device = <&fan THERMAL_NO_LIMIT 1>;
+ };
+
+ map3 {
+ trip = <&cpu_hot>;
+ cooling-device = <&fan 2 THERMAL_NO_LIMIT>;
+ };
+ };
+};
+
+&emmc_phy {
+ status = "disabled";
+};
+
+&fusb0 {
+ status = "disabled";
+};
+
+&leds {
+ lan_led: led-1 {
+ gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
+ label = "nanopi-r4s:green:lan";
+ };
+
+ wan_led: led-2 {
+ gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>;
+ label = "nanopi-r4s:green:wan";
+ };
+};
+
+&leds_gpio {
+ rockchip,pins =
+ <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
+};
+
+&pcie0 {
+ max-link-speed = <1>;
+ num-lanes = <1>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+};
+
+&sdhci {
+ status = "disabled";
+};
+
+&sdio0 {
+ status = "disabled";
+};
+
+&sdmmc {
+ host-index-min = <1>;
+};
+
+&u2phy0_host {
+ phy-supply = <&vdd_5v>;
+};
+
+&u2phy1_host {
+ status = "disabled";
+};
+
+&usbdrd_dwc3_0 {
+ dr_mode = "host";
+};
+
+&vcc3v3_sys {
+ vin-supply = <&vcc5v0_sys>;
+};
diff --git a/configs/nanopi-r4s-rk3399_defconfig
b/configs/nanopi-r4s-rk3399_defconfig
new file mode 100644
index 00..0a3c28b012
--- /dev/null
+++ b/configs/nanopi-r4s-rk3399_defconfig
@@ -0,0 +1,62 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SYS_TEXT_BASE=0x0020
+CONFIG_ENV

Xilinx ZynqMP SPL boot: psu_init_gpl.c code corrupts U-Boot memory

[Robert Hancock]

I've been trying to get the U-Boot SPL to work on a Xilinx ZCU102
development board. I have been testing with U-Boot 2021.01, and using
the generated psu_init_gpl HW initialization code generated by Vivado
2020.2, rather than the versions in the U-Boot tree, as we are
expecting to make changes to the configuration as we move to our own
board design.

The issue I was seeing is that the SPL seemingly locking up or crashing
early in the boot process, just after the SPL banner was printed. I've
CCed "Major A" as he reported something similar on the mailing list in
March ('ZynqMP boot: no messages from SPL other than "Debug uart
enabled"') but I didn't see a resoution posted.

After groveling around with the Xilinx JTAG debugger for a day or so, I
figured out that the problem was that the SPL ended up reading from an
invalid pointer address somewhere during the driver model
initialization process, and crashing. After using memory watchpoints to
identify where the bogus value was being written to the pointer storage
location, the memory write was actually coming from the Vivado 2020.2-
generated psu_init_gpl code. The offending code is in a function called
serdes_illcalib_pcie_gen1 and looks like this:

  if (gen2_calib != 1) 
  {
ill1_val[loop] = ((0x04 + meancount[loop]*8) % 0x100);
ill12_val[loop] = ((0x04 + meancount[loop]*8) >= 0x100) ?
0x10 : 0x00;
Xil_Out32(0xFFFE+loop*4,iterresult[loop]);
Xil_Out32(0xFFFE0010+loop*4,iterresult[loop+4]);
Xil_Out32(0xFFFE0020+loop*4,bistpasscount[loop]);
Xil_Out32(0xFFFE0030+loop*4,meancount[loop]);
  }
  if (gen2_calib == 1) 
  {
ill1_val[loop] = ((0x104 + meancount[loop]*8) % 0x100);
ill12_val[loop] = ((0x104 + meancount[loop]*8) >= 0x200) ?
0x02 : 0x01;
Xil_Out32(0xFFFE0040+loop*4,iterresult[loop]);
Xil_Out32(0xFFFE0050+loop*4,iterresult[loop+4]);
Xil_Out32(0xFFFE0060+loop*4,bistpasscount[loop]);
Xil_Out32(0xFFFE0070+loop*4,meancount[loop]);
  }

Those writes to 0xFFFE are to on-chip memory addresses, not any
hardware register, so I have no idea what this is trying to achieve.
Possibly this is some debug code to store some calibration results that
was left in by mistake? Those addresses may not be used in the Xilinx
FSBL, but overwriting them in the U-Boot SPL wreaks havoc.

For now, I've worked around it by hacking the Xil_Out32 implementation
provided by U-Boot in board/xilinx/zynqmp/xil_io.h to trap and ignore
writes to memory addresses in the OCRAM range (0xFFFC to
0x). With that in place, things seem to be working. Probably
this should be addressed in the Vivado psu_init code generator, but we
may need some workaround like this to avoid those using the affected
Xilinx tool versions from hitting this issue?

-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com

Re: imx8mp evk - boot stucks at BL31

[Elmar Psilog]

On 21.01.21 07:37, Elmar Psilog wrote:

I am on a imx8.mp evk board. I could build and start loader (SPL, UBOOT,
DT, ATF/BL31, mkimage) from the freescale git. Due to some problems I
switched to mainland Uboot 2021-1. I found SPL/ATF is booting, but it
stops with:

NOTICE: BL31: 

If I replace in imx-mkimage just the file u-boot-nodtb.bin with NXP's
uboot, than it boots (it shows the U-Boot-2020.04 banner). So something
went wrong with 2021-1 uboot or its default config. What can this be? I
enabled log level 7, but nothing to be seen.

(BTW: When enables loglevel >6 for SPL, SPL fails in DDR training. In
NXP 20.04 SPL I couldn't compile with SPL log support)


On Denx-Git I found Uboot boots imx8mp-evk with 2020.07, but not with
2020.10 - even not first RC).

[PATCH] cmd: pxe_utils: fix ipappend ip config empty vars

[Artem Lapkin]

PROBLEM: If ipaddr, serverip, gatewayip or netmask variable undefined
we can have for example ip=192.168.2.33::192.168.2.1:255.255.255.0
yes its works same for linux kernel, but im think no need print 

SUGGESTED SOLUTION:
if some variable was undefined we need just print empty place like this
ip=192.168.2.33::192.168.2.1:255.255.255.0

Signed-off-by: Artem Lapkin 

---
 cmd/pxe_utils.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/cmd/pxe_utils.c b/cmd/pxe_utils.c
index 8716e782..2049c0f3 100644
--- a/cmd/pxe_utils.c
+++ b/cmd/pxe_utils.c
@@ -395,9 +395,12 @@ static int label_boot(struct cmd_tbl *cmdtp, struct 
pxe_label *label)
}
 
if (label->ipappend & 0x1) {
+   char *a = env_get("ipaddr");
+   char *b = env_get("serverip");
+   char *c = env_get("gatewayip");
+   char *d = env_get("netmask");
sprintf(ip_str, " ip=%s:%s:%s:%s",
-   env_get("ipaddr"), env_get("serverip"),
-   env_get("gatewayip"), env_get("netmask"));
+   a ? a : "", b ? b : "", c ? c : "", d ? d : "");
}
 
 #ifdef CONFIG_CMD_NET
-- 
2.25.1

imx8mp evk - boot stucks at BL31

[Elmar Psilog]

I am on a imx8.mp evk board. I could build and start loader (SPL, UBOOT,
DT, ATF/BL31, mkimage) from the freescale git. Due to some problems I
switched to mainland Uboot 2021-1. I found SPL/ATF is booting, but it
stops with:

NOTICE: BL31: 

If I replace in imx-mkimage just the file u-boot-nodtb.bin with NXP's
uboot, than it boots (it shows the U-Boot-2020.04 banner). So something
went wrong with 2021-1 uboot or its default config. What can this be? I
enabled log level 7, but nothing to be seen.

(BTW: When enables loglevel >6 for SPL, SPL fails in DDR training. In
NXP 20.04 SPL I couldn't compile with SPL log support)

[PATCH 1/1] doc: document echo command

[Heinrich Schuchardt]

Provide a man-page for the echo command.

Signed-off-by: Heinrich Schuchardt 
---
 doc/usage/echo.rst  | 65 +
 doc/usage/index.rst |  1 +
 2 files changed, 66 insertions(+)
 create mode 100644 doc/usage/echo.rst

diff --git a/doc/usage/echo.rst b/doc/usage/echo.rst
new file mode 100644
index 00..e11c35c2a9
--- /dev/null
+++ b/doc/usage/echo.rst
@@ -0,0 +1,65 @@
+echo command
+
+
+Synopsis
+
+
+::
+
+echo [-n] [args ...]
+
+Description
+---
+
+The echo command prints its arguments to the console separated by spaces.
+
+-n
+Do not print a line feed after the last argument.
+
+args
+Arguments to be printed. The arguments are evaluated before being passed to
+the command.
+
+Examples
+
+
+Strings are parsed before the arguments are passed to the echo command:
+
+::
+
+=> echo "a" 'b' c
+a b c
+=>
+
+Observe how variables included in strings are handled:
+
+::
+
+=> setenv var X; echo "a)" ${var} 'b)' '${var}' c) ${var}
+a) X b) ${var} c) X
+=>
+
+
+-n suppresses the line feed:
+
+::
+
+=> echo -n 1 2 3; echo a b c
+1 2 3a b c
+=> echo -n 1 2 3
+1 2 3=>
+
+A more complex example:
+
+::
+
+=> for i in a b c; do for j in 1 2 3; do echo -n "${i}${j}, "; done; echo; 
done;
+a1, a2, a3,
+b1, b2, b3,
+c1, c2, c3,
+=>
+
+Return value
+
+
+The return value $? is always set to 0 (true).
diff --git a/doc/usage/index.rst b/doc/usage/index.rst
index 6f49652758..317db3b449 100644
--- a/doc/usage/index.rst
+++ b/doc/usage/index.rst
@@ -17,6 +17,7 @@ Shell commands
bootefi
bootmenu
button
+   echo
exit
for
mbr
--
2.29.2

[PATCH] test: unit test for echo command

[Heinrich Schuchardt]

Provide a unit test for the unit command

Signed-off-by: Heinrich Schuchardt 
---
 test/cmd/Makefile|  3 +++
 test/cmd/test_echo.c | 57 
 2 files changed, 60 insertions(+)
 create mode 100644 test/cmd/test_echo.c

diff --git a/test/cmd/Makefile b/test/cmd/Makefile
index 758bc14273..5451e9ea90 100644
--- a/test/cmd/Makefile
+++ b/test/cmd/Makefile
@@ -2,6 +2,9 @@
 #
 # Copyright (c) 2013 Google, Inc

+ifdef CONFIG_HUSH_PARSER
+obj-$(CONFIG_CONSOLE_RECORD) += test_echo.o
+endif
 obj-y += mem.o
 obj-$(CONFIG_CMD_MEM_SEARCH) += mem_search.o
 obj-$(CONFIG_CMD_PWM) += pwm.o
diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c
new file mode 100644
index 00..4183cf75bb
--- /dev/null
+++ b/test/cmd/test_echo.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Tests for echo command
+ *
+ * Copyright 2020, Heinrich Schuchadt 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct test_data {
+   char *cmd;
+   char *expected;
+};
+
+static struct test_data echo_data[] = {
+   {"echo 1 2 3",
+"1 2 3"},
+   /* Test new line handling */
+   {"echo -n 1 2 3; echo a b c",
+"1 2 3a b c"},
+   /*
+* Test handling of environment variables.
+*
+* j, q, x are among the least frequent letters in English.
+* Hence no collision for the variable name jQx is expected.
+*/
+   {"setenv jQx X; echo \"a)\" ${jQx} 'b)' '${jQx}' c) ${jQx}; setenv jQx",
+"a) X b) ${jQx} c) X"},
+   /* Test handling of shell variables. */
+   {"setenv jQx; for jQx in 1 2 3; do echo -n \"${jQx}, \"; done; echo;",
+"1, 2, 3, "},
+};
+
+static int lib_test_hush_echo(struct unit_test_state *uts)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(echo_data); ++i) {
+   console_record_reset_enable();
+   ut_assertok(run_command(echo_data[i].cmd, 0));
+   gd->flags &= ~GD_FLG_RECORD;
+   console_record_readline(uts->actual_str,
+   sizeof(uts->actual_str));
+   ut_asserteq_str(echo_data[i].expected, uts->actual_str);
+   ut_assertok(ut_check_console_end(uts));
+   }
+   return 0;
+}
+
+LIB_TEST(lib_test_hush_echo, 0);
--
2.29.2

Re: [PATCH v2 11/12] x86: coral: Add sysinfo ops

[Simon Glass]

Hi Bin,

On Wed, 20 Jan 2021 at 23:54, Bin Meng  wrote:
>
> Hi Simon,
>
> On Thu, Jan 21, 2021 at 10:07 AM Simon Glass  wrote:
> >
> > These ops are missing at present which is not permitted. Add an empty
> > operation struct.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> > Changes in v2:
> > - Add new patch to fix crash on coral
> >
> >  board/google/chromebook_coral/coral.c | 5 +
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/board/google/chromebook_coral/coral.c 
> > b/board/google/chromebook_coral/coral.c
> > index 34b2c2ac5d5..f9fb3f163f0 100644
> > --- a/board/google/chromebook_coral/coral.c
> > +++ b/board/google/chromebook_coral/coral.c
> > @@ -8,6 +8,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -143,6 +144,9 @@ struct acpi_ops coral_acpi_ops = {
> > .inject_dsdt= chromeos_acpi_gpio_generate,
> >  };
> >
> > +struct sysinfo_ops coral_sysinfo_ops = {
> > +};
> > +
> >  #if !CONFIG_IS_ENABLED(OF_PLATDATA)
> >  static const struct udevice_id coral_ids[] = {
> > { .compatible = "google,coral" },
> > @@ -154,5 +158,6 @@ U_BOOT_DRIVER(coral_drv) = {
> > .name   = "coral",
> > .id = UCLASS_SYSINFO,
> > .of_match   = of_match_ptr(coral_ids),
> > +   .ops= &coral_sysinfo_ops,
> > ACPI_OPS_PTR(&coral_acpi_ops)
> >  };
>
> Shouldn't we fix sysinfo-uclass to test op against NULL? That way we
> relax the driver a little bit.

In general I don't like missing out the operations struct. If the
uclass requires operations then the drivers should provide them. It is
true that the operation struct is currently empty, but I've sent
patches to add to it.

Checking for missing operations must be done in every uclass
operation, so it adds to code size.

Regards,
Simon

Re: [PATCH 1/1] dm: core: describe uclass_root_s

[Simon Glass]

Hi Heinrich,

On Mon, 18 Jan 2021 at 20:18, Heinrich Schuchardt  wrote:
>
> Am 19. Januar 2021 01:49:28 MEZ schrieb Simon Glass :
> >Hi Bin,
> >
> >On Sat, 16 Jan 2021 at 03:59, Bin Meng  wrote:
> >>
> >> On Sat, Jan 16, 2021 at 6:13 PM Heinrich Schuchardt
> > wrote:
> >> >
> >> > make htmldocs creates a warning:
> >> >
> >> > ./include/asm-generic/global_data.h:443:
> >> > warning: Function parameter or member 'uclass_root_s'
> >> > not described in 'global_data'
> >> >
> >> > Correct the member descriptions.
> >> >
> >> > Fixes: 8a715530bb1f ("dm: core: Allow the uclass list to move")
> >> > Signed-off-by: Heinrich Schuchardt 
> >> > ---
> >> >  include/asm-generic/global_data.h | 8 
> >> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >> >
> >> > diff --git a/include/asm-generic/global_data.h
> >b/include/asm-generic/global_data.h
> >> > index efa09a1943..9fa9a17003 100644
> >> > --- a/include/asm-generic/global_data.h
> >> > +++ b/include/asm-generic/global_data.h
> >> > @@ -198,13 +198,13 @@ struct global_data {
> >> >  */
> >> > struct udevice *dm_root_f;
> >> > /**
> >> > -* @uclass_root: head of core tree
> >> > +* @uclass_root_s: static head of core tree, if uclasses
> >are in
> >> > +* read-only memory and cannot be adjusted to use
> >@uclass_root as a
> >> > +* list head.
> >> >  */
> >> > struct list_head uclass_root_s;
> >>
> >> _s stands for static?
> >>
> >> If so, I suspect the comment was just the opposite?
> >
> >Yes. I inserted the new variable but did not move the comment...
> >
>
> Hello Simon,
>
> do you mean the patch is wrong?
>
> What should the comments look like?


>
> Best regards
>
> Heinrich
>
>
> >
> >>
> >> > /**
> >> > -* @uclass_root: pointer to head of core tree, if uclasses
> >are in
> >> > -* read-only memory and cannot be adjusted to use
> >@uclass_root as a
> >> > -* list head.
> >> > +* @uclass_root: pointer to the head of core tree

uclass_root is used when described in the removed lines above.

When uclasses are in read-only memory, uclass_root_s is not used and
uclass_root points to the root node generated by dtoc
When not in read-only memory, uclass_root_s is used to hold the uclass
root, and uclass_root points to &uclass_root_s.


> >> >  */
> >> > struct list_head *uclass_root;
> >> >  # if CONFIG_IS_ENABLED(OF_PLATDATA)
> >> > --
> >>
>

Regards,
Simon

Re: [PATCH v2 12/12] smbios: Allow a few values to come from sysinfo

[Simon Glass]

Hi Bin,

On Wed, 20 Jan 2021 at 23:55, Bin Meng  wrote:
>
> On Thu, Jan 21, 2021 at 10:07 AM Simon Glass  wrote:
> >
> > While static configuration is useful it cannot cover every case. Sometimes
> > board revisions are encoded in resistor straps and must be read at
> > runtime.
> >
> > The easiest way to provide this information is via sysinfo, since the
> > board can then provide a driver to read whatever is needed.
> >
> > Add some standard sysinfo options for this, and use them to obtain the
> > required information.
> >
> > Signed-off-by: Simon Glass 
> > ---
> >
> > (no changes since v1)
> >
> >  include/sysinfo.h | 11 +++
> >  lib/smbios.c  | 32 +---
> >  2 files changed, 40 insertions(+), 3 deletions(-)
> >
> > diff --git a/include/sysinfo.h b/include/sysinfo.h
> > index 6e021253524..743f3554659 100644
> > --- a/include/sysinfo.h
> > +++ b/include/sysinfo.h
> > @@ -31,6 +31,17 @@
> >   * to read the serial number.
> >   */
> >
> > +/** enum sysinfo_id - Standard IDs defined by U-Boot */
> > +enum sysinfo_id {
> > +   SYSINFO_ID_NONE,
> > +
> > +   SYSINFO_ID_SMBIOS_SYSTEM_VERSION,
> > +   SYSINFO_ID_SMBIOS_BASEBOARD_VERSION,
> > +
> > +   /* First value available for downstream/board used */
> > +   SYSINFO_ID_USER = 0x1000,
> > +};
> > +
> >  struct sysinfo_ops {
> > /**
> >  * detect() - Run the hardware info detection procedure for this
> > diff --git a/lib/smbios.c b/lib/smbios.c
> > index d46569b09f4..9bdde0b953f 100644
> > --- a/lib/smbios.c
> > +++ b/lib/smbios.c
> > @@ -10,6 +10,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #ifdef CONFIG_CPU
> > @@ -106,15 +107,26 @@ static int smbios_add_string(struct smbios_ctx *ctx, 
> > const char *str)
> >  }
> >
> >  /**
> > - * smbios_add_prop() - Add a property from the device tree
> > + * smbios_add_prop_si() - Add a property from the devicetree or sysinfo
> > + *
> > + * Sysinfo is used if available, with a fallback to devicetree
> >   *
> >   * @start: string area start address
> >   * @node:  node containing the information to write (ofnode_null() if 
> > none)
> >   * @prop:  property to write
> >   * @return 0 if not found, else SMBIOS string number (1 or more)
> >   */
> > -static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop)
> > +static int smbios_add_prop_si(struct smbios_ctx *ctx, const char *prop,
> > + int sysinfo_id)
> >  {
> > +   if (sysinfo_id && ctx->dev) {
> > +   char val[80];
>
> Is 80 the limitation defined by sysinfo drivers? Can this be a macro?

I found this limitation in the SMBIOS spec.

Yes I will make it a macro.

>
> > +   int ret;
> > +
> > +   ret = sysinfo_get_str(ctx->dev, sysinfo_id, sizeof(val), 
> > val);
> > +   if (!ret)
> > +   return smbios_add_string(ctx, val);
> > +   }
> > if (IS_ENABLED(CONFIG_OF_CONTROL)) {
> > const char *str;
> >
> > @@ -126,6 +138,17 @@ static int smbios_add_prop(struct smbios_ctx *ctx, 
> > const char *prop)
> > return 0;
> >  }
> >
> > +/**
> > + * smbios_add_prop() - Add a property from the devicetree
> > + *
> > + * @prop:  property to write
> > + * @return 0 if not found, else SMBIOS string number (1 or more)
> > + */
> > +static int smbios_add_prop(struct smbios_ctx *ctx, const char *prop)
> > +{
> > +   return smbios_add_prop_si(ctx, prop, SYSINFO_ID_NONE);
> > +}
> > +
> >  static void set_eos(struct smbios_ctx *ctx, char *eos)
> >  {
> > ctx->eos = eos;
> > @@ -239,7 +262,8 @@ static int smbios_write_type1(ulong *current, int 
> > handle,
> > set_eos(ctx, t->eos);
> > t->manufacturer = smbios_add_prop(ctx, "manufacturer");
> > t->product_name = smbios_add_prop(ctx, "product");
> > -   t->version = smbios_add_prop(ctx, "version");
> > +   t->version = smbios_add_prop_si(ctx, "version",
> > +   SYSINFO_ID_SMBIOS_SYSTEM_VERSION);
> > if (serial_str) {
> > t->serial_number = smbios_add_string(ctx, serial_str);
> > strncpy((char *)t->uuid, serial_str, sizeof(t->uuid));
> > @@ -268,6 +292,8 @@ static int smbios_write_type2(ulong *current, int 
> > handle,
> > set_eos(ctx, t->eos);
> > t->manufacturer = smbios_add_prop(ctx, "manufacturer");
> > t->product_name = smbios_add_prop(ctx, "product");
> > +   t->version = smbios_add_prop_si(ctx, "version",
> > +   
> > SYSINFO_ID_SMBIOS_BASEBOARD_VERSION);
> > t->asset_tag_number = smbios_add_prop(ctx, "asset-tag");
> > t->feature_flags = SMBIOS_BOARD_FEATURE_HOSTING;
> > t->board_type = SMBIOS_BOARD_MOTHERBOARD;
> > --
>
> Reviewed-by: Bin Meng 

Regards,
Simon

[PATCH 3/3] ARM: at91: spl: add spl_early_init for sama52d platforms

[Greg Gallagher]

The dm root node is needed early in the spl to allow the timer to be
used.  This change calls spl_early_init to initialize the dm root node.

Signed-off-by: Greg Gallagher 
---

 arch/arm/mach-at91/spl_atmel.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c
index 23588e79f9..217ed12e31 100644
--- a/arch/arm/mach-at91/spl_atmel.c
+++ b/arch/arm/mach-at91/spl_atmel.c
@@ -103,6 +103,13 @@ void board_init_f(ulong dummy)
 {
int ret;
 
+   if (IS_ENABLED(CONFIG_OF_CONTROL)) {
+   ret = spl_early_init();
+   if (ret) {
+   debug("spl_early_init() failed: %d\n", ret);
+   hang();
+   }
+   }
switch_to_main_crystal_osc();
 
 #ifdef CONFIG_SAMA5D2
-- 
2.25.1

[PATCH 2/3] configs: sama5d27_som1_ek: Set FDT filename based on defconfig

[Greg Gallagher]

Make the FDT file name based on the default on that is specified in the
defconfig file.

Signed-off-by: Greg Gallagher 
---

 include/configs/sama5d27_som1_ek.h | 7 ++-
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/include/configs/sama5d27_som1_ek.h 
b/include/configs/sama5d27_som1_ek.h
index 3358149e66..8942d15934 100644
--- a/include/configs/sama5d27_som1_ek.h
+++ b/include/configs/sama5d27_som1_ek.h
@@ -27,14 +27,11 @@
 
 #define CONFIG_SYS_LOAD_ADDR   0x2200 /* load address */
 
-/* NAND flash */
-
-/* SPI flash */
-
 #undef CONFIG_BOOTCOMMAND
 #ifdef CONFIG_SD_BOOT
 /* bootstrap + u-boot + env in sd card */
-#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 
0x2100 at91-sama5d27_som1_ek.dtb; " \
+#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 
0x2100 " \
+   CONFIG_DEFAULT_DEVICE_TREE ".dtb; " \
"fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 
0x2200 zImage; " \
"bootz 0x2200 - 0x2100"
 #endif
-- 
2.25.1

[PATCH 1/3] board: Atmel: Add SAMA5D27 giant board

[Greg Gallagher]

Giant board is a tiny SBC based on the Adafruit Feather form factor,
created by groboards it contains a SAMA5D2 processor (SAMA5D27),
128 MB of RAM and a microSD card for storage.

Signed-off-by: Greg Gallagher 
---

 arch/arm/dts/Makefile |   3 +-
 arch/arm/dts/at91-sama5d27_giantboard.dts | 128 ++
 board/atmel/sama5d27_som1_ek/MAINTAINERS  |   6 +
 configs/sama5d27_giantboard_defconfig |  97 
 4 files changed, 233 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/at91-sama5d27_giantboard.dts
 create mode 100644 configs/sama5d27_giantboard_defconfig

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e320c2254e..8a6a8bcee3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -905,7 +905,8 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
 
 dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
-   at91-sama5d27_som1_ek.dtb
+   at91-sama5d27_som1_ek.dtb   \
+   at91-sama5d27_giantboard.dtb
 
 dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
at91-sama5d27_wlsom1_ek.dtb
diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts 
b/arch/arm/dts/at91-sama5d27_giantboard.dts
new file mode 100644
index 00..e81ca60ca0
--- /dev/null
+++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
+ *
+ * Copyright (C) 2020 Greg Gallagher 
+ *
+ * Derived from at91-sama5d27_som1_ek.dts
+ *
+ * Copyright (C) 2017 Microchip Corporation
+ *   Wenyou Yang 
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+
+/ {
+   model = "Giant Board";
+   compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2", 
"atmel,sama5";
+
+   memory {
+   reg = <0x2000 0x800>;
+   };
+
+   chosen {
+   u-boot,dm-pre-reloc;
+   stdout-path = &uart1;
+   };
+
+   ahb {
+   sdmmc1: sdio-host@b000 {
+   bus-width = <4>;
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default 
&pinctrl_sdmmc1_ck_cd_default>;
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   };
+
+   apb {
+
+   uart1: serial@f802 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_uart1_default>;
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   };
+
+   i2c0: i2c@f8028000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c0_default>;
+   status = "okay";
+   };
+
+   i2c1: i2c@fc028000 {
+   pinctrl-names = "default";
+   pinctrl-0 = <&pinctrl_i2c1_default>;
+   status = "okay";
+
+   pmic@5b {
+   compatible = "active-semi,act8945a";
+   reg = <0x5b>;
+   active-semi,vsel-low;
+   status = "okay";
+   };
+   };
+
+   pit: timer@f8048030 {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   };
+
+   sfr: sfr@f803 {
+   status = "okay";
+   u-boot,dm-pre-reloc;
+   };
+
+   pioA: gpio@fc038000 {
+   pinctrl {
+
+   pinctrl_sdmmc1_cmd_dat_default: 
sdmmc1_cmd_dat_default {
+   pinmux = ,
+
,
+
,
+
,
+
;
+   bias-pull-up;
+   u-boot,dm-pre-reloc;
+   };
+
+   pinctrl_sdmmc1_ck_cd_default: 
sdmmc1_ck_cd_default {
+   pinmux = ,
+;
+   bias-disable;
+   u-boot,dm-pre-reloc;
+   };
+
+   pinctrl_uart1_default: uar

[PATCH 2/2] pinctrl: stm32: bind only the enabled GPIO subnode

[Patrick Delaunay]

Bind only the enabled GPIO subnode, to avoid to probe the node
"gpio-controller" present in SOC dtsi (disabled by default) but
not enabled in the included pincontrol dtsi file.

For example, in stm32mp15xxac-pinctrl.dtsi 2 gpio bank are absent:
 gpioj: gpio@5000b000
 gpiok: gpio@5000c000

Then these GPIO are absent in output of command "dm tree" and
"gpio status -a"

Signed-off-by: Patrick Delaunay 
---

 drivers/pinctrl/pinctrl_stm32.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 374f76d881..6c98538f56 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -409,6 +409,9 @@ static int stm32_pinctrl_bind(struct udevice *dev)
dev_for_each_subnode(node, dev) {
dev_dbg(dev, "bind %s\n", ofnode_get_name(node));
 
+   if (!ofnode_is_enabled(node))
+   continue;
+
ofnode_get_property(node, "gpio-controller", &ret);
if (ret < 0)
continue;
-- 
2.17.1

[PATCH 1/2] pinctrl: stm32: correct management pin display of OTYPE

[Patrick Delaunay]

OTYPE can be used for output or for alternate function to select
PP = push-pull or OP = open-drain mode, according reference manual
(Table 81. Port bit configuration table).

This patch removes this indication for input pins and adds it
for AF and output pins for pinmux command output.

Fixes: b305dbc08b08 ("pinctrl: stm32: display bias information for all pins")

Signed-off-by: Patrick Delaunay 
---

 drivers/pinctrl/pinctrl_stm32.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index a1f53a793b..374f76d881 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -56,7 +56,7 @@ static const char * const pinmux_bias[] = {
[STM32_GPIO_PUPD_DOWN] = "pull-down",
 };
 
-static const char * const pinmux_input[] = {
+static const char * const pinmux_otype[] = {
[STM32_GPIO_OTYPE_PP] = "push-pull",
[STM32_GPIO_OTYPE_OD] = "open-drain",
 };
@@ -216,7 +216,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
selector, gpio_idx, mode);
priv = dev_get_priv(gpio_dev);
pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK;
-
+   otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
 
switch (mode) {
case GPIOF_UNKNOWN:
@@ -227,18 +227,16 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice 
*dev,
break;
case GPIOF_FUNC:
af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx);
-   snprintf(buf, size, "%s %d %s", pinmux_mode[mode], af_num,
-pinmux_bias[pupd]);
+   snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num,
+pinmux_otype[otype], pinmux_bias[pupd]);
break;
case GPIOF_OUTPUT:
-   snprintf(buf, size, "%s %s %s",
-pinmux_mode[mode], pinmux_bias[pupd],
-label ? label : "");
+   snprintf(buf, size, "%s %s %s %s",
+pinmux_mode[mode], pinmux_otype[otype],
+pinmux_bias[pupd], label ? label : "");
break;
case GPIOF_INPUT:
-   otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK;
-   snprintf(buf, size, "%s %s %s %s",
-pinmux_mode[mode], pinmux_input[otype],
+   snprintf(buf, size, "%s %s %s", pinmux_mode[mode],
 pinmux_bias[pupd], label ? label : "");
break;
}
-- 
2.17.1

[PATCH 0/2] pinctrl: stm32: correction for pinmux status

[Patrick Delaunay]

This serie solve 2 issues found in output of command
"pinmux status -a" when I test the serie [1].

[1] "gpio: Update and simplify the uclass API"
http://patchwork.ozlabs.org/project/uboot/list/?series=225585



Patrick Delaunay (2):
  pinctrl: stm32: correct management pin display of OTYPE
  pinctrl: stm32: bind only the enabled GPIO subnode

 drivers/pinctrl/pinctrl_stm32.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

-- 
2.17.1

Re: [PATCH v2 00/15] gpio: Update and simplify the uclass API

[Patrick DELAUNAY]

Hi Simon,

On 1/21/21 4:11 AM, Simon Glass wrote:

At present the GPIO uclass mirrors what was in U-Boot before driver model.
It works well in most cases but is becoming cumbersome with things like
pull-up/down and drive strength. In those cases it is easier for the
driver to deal with all the flags at one, rather than piece by piece.

In fact the current API does not officially have a method for adjusting
anything other than the direction flags. While set_dir_flags() and
get_dir_flags() do in fact support changing other flags, this is not
documented.

Secondly, set_dir_flags actually ORs the current flags with the new ones
so it is not possible to clear flags. It seems better to use a clr/set
interface (bit clear followed by OR) to provide more flexibility.

Finally, direction_input() and direction_output() are really just the same
thing as set_dir_flags(), with a different name. We currently use the
latter if available, failing back to the former. But it makes sense to
deprecate the old methods.

This series makes the above changes. Existing drivers are mostly left
alone, since they should continue to operate as is. The sandbox driver is
updated to add the required new tests and the x86 driver is switched over
to the new API.

The STM32 driver should be checked to make sure the open source/open drain
features still work as intended.

Changes in v2:
- Use set_flags() instead of update_flags()
- Fix 'provide' typo while we are here
- Make operation of set_flags() deterministic
- Swap newf and flags in sb_gpio_set_flags()

Simon Glass (15):
   gpio: Disable functions not used with of-platdata
   dm: gpio: Rename set_dir_flags() method to update_flags()
   dm: gpio: Rename get_dir_flags() method to get_flags()
   gpio: Rename dm_gpio_get_dir_flags() to dm_gpio_get_flags()
   gpio: Drop dm_gpio_set_dir()
   gpio: sandbox: Rename GPIO dir_flags to flags
   gpio: sandbox: Use a separate flag for the value
   gpio: sandbox: Fully separate pin value from output value
   gpio: sandbox: Make sandbox_gpio_set_flags() set all flags
   dm: gpio: Add a way to update flags
   gpio: Replace direction_input() and direction_output()
   gpio: Use an 'ops' variable everywhere
   gpio: x86: Drop the deprecated methods in intel_gpio
   gpio: sandbox: Track whether a GPIO is driven
   gpio: Add a way to read 3-way strapping pins

  arch/sandbox/include/asm/gpio.h   |  17 +-
  arch/x86/include/asm/intel_pinctrl_defs.h |   5 +
  drivers/gpio/gpio-uclass.c| 228 ++-
  drivers/gpio/intel_gpio.c |  72 +++---
  drivers/gpio/sandbox.c| 138 
  drivers/gpio/stm32_gpio.c |  14 +-
  drivers/pinctrl/pinctrl-stmfx.c   |  14 +-
  include/asm-generic/gpio.h| 130 +--
  test/dm/gpio.c| 261 +++---
  9 files changed, 663 insertions(+), 216 deletions(-)



The open source/ open drain works correctly

But I found a issue for GPIOD_ACTIVE_LOW management in STM32

drivers after the serie corrected by the next patch


Tested with gpio hog on DK2 board (to force directly flags by DT)

 arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi

+
+&gpioi {
+    test1 {
+        gpio-hog;
+        input;
+        gpios = <0 0>;
+    };
+    test2 {
+        gpio-hog;
+        input;
+        gpios = <1 GPIO_PULL_UP>;
+    };
+    test3 {
+        gpio-hog;
+        input;
+        gpios = <2 GPIO_PULL_DOWN>;
+    };
+    test4 {
+        gpio-hog;
+        output-low;
+        gpios = <3 (GPIO_OPEN_DRAIN)>;
+    };
+    test5 {
+        gpio-hog;
+        output-low;
+        gpios = <4 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+    };
+    test6 {
+        gpio-hog;
+        output-high;
+        gpios = <5 (GPIO_OPEN_DRAIN | GPIO_PULL_DOWN)>;
+    };
+    test7 {
+        gpio-hog;
+        output-high;
+        gpios = <6 0>;
+    };
+    test8 {
+        gpio-hog;
+        output-low;
+        gpios = <7 0>;
+    };
+    test9 {
+        gpio-hog;
+        output-high;
+        gpios = <8 GPIO_ACTIVE_LOW>;
+    };
+    test10 {
+        gpio-hog;
+        output-low;
+        gpios = <9 GPIO_ACTIVE_LOW>;
+    };
+};

Then

STM32MP> pinmux status -a
--

pin-controller@50002000:

GPIOI0    : gpio input  test1.gpio-hog
GPIOI1    : gpio input pull-up test2.gpio-hog
GPIOI2    : gpio input pull-down test3.gpio-hog
GPIOI3    : gpio output open-drain  test4.gpio-hog
GPIOI4    : gpio output open-drain pull-up test5.gp
GPIOI5    : gpio output open-drain pull-down test6.
GPIOI6    : gpio output push-pull  test7.gpio-hog
GPIOI7    : gpio output push-pull  test8.gpio-hog
GPIOI8    : gpio output push-pull  test9.gpio-hog
GPIOI9    : gpio output push-pull  test10.gpio-hog
GPIOI10   : analog
GPIOI11   : analog




And


STM32MP> gpio status -a


Bank GPIOI:
GPIOI0: input: 0 [x] test1.gpio-hog
GPIOI1: input: 1 [x] test2.gpio-hog
GPIOI2: input: 0 [x] test3.gpio-hog
GPIOI3: output

Re: [PATCH 1/1] sandbox: keep time offset when resetting

[Simon Glass]

Hi Heinrich,

On Thu, 21 Jan 2021 at 02:19, Heinrich Schuchardt  wrote:
>
> On 07.01.21 13:35, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Wed, 30 Dec 2020 at 10:07, Heinrich Schuchardt  
> > wrote:
> >>
> >> The UEFI Self Certification Test (SCT) checks the SetTime() service with
> >> the following steps:
> >>
> >> * set date
> >> * reset
> >> * check date matches
> >>
> >> To be compliant the sandbox should keep the offset to the host RTC during
> >> resets. The implementation uses the environment variable
> >> UBOOT_SB_TIME_OFFSET to persist the offset.
> >>
> >> Signed-off-by: Heinrich Schuchardt 
> >> ---
> >>  arch/sandbox/cpu/os.c  | 25 +
> >>  doc/arch/sandbox.rst   |  7 +++
> >>  drivers/rtc/i2c_rtc_emul.c |  4 +++-
> >>  include/os.h   | 18 ++
> >>  4 files changed, 53 insertions(+), 1 deletion(-)
> >
> > Sandbox writes driver settings to a state file that can be read on
> > start-up. Is that suitable here?
>
> The sandbox only reads the state from file when using the -r and only
> writes the state to while when using the -w option.
>
> This should be documented in
> https://u-boot.readthedocs.io/en/latest/arch/sandbox.html?highlight=sandbox#command-line-options
>
> The RTC offset needs to be kept irrespective of command line arguments
> during resets. I could not find a simpler way then using an environment
> variable.

Given the way that reset works (relaunching the ELF app) I don't know
of a better way either. I suppose you could launch it with the RTC
offset as a command-line parameter?

>
> We could additionally persist the offset in the state file. Is this what
> you ask for? For my testing purposes I don't need it.

I don't think so. It is designed for passing driver / state
information between U-Boot phases. I suppose it should be used for
persisting state across reset too, since in principle the emulated
hardware does not change just because sandbox has reset. But in that
case we don't really need to write a file, just keep it in memory
somewhere. Or at most we could write a temporary file.

Reviewed-by: Simon Glass 

Regards,
Simon

[PATCH 7/7] bdinfo: Change to use bdinfo_print_num_ll() where the number could be 64-bit

[Bin Meng]

From: Bin Meng 

There are some calls to bdinfo_print_num_l() with parameters that
could be a 64-bit value on a 32-bit system. Change those calls to
use bdinfo_print_num_ll() instead.

Signed-off-by: Bin Meng 
---

 arch/arm/lib/bdinfo.c | 8 
 cmd/bdinfo.c  | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 4a98cb7ef5..c905783bdc 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -18,14 +18,14 @@ void arch_print_bdinfo(void)
bdinfo_print_num_l("arch_number", bd->bi_arch_number);
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
-   bdinfo_print_num_l("Secure ram",
-  gd->arch.secure_ram &
-  MEM_RESERVE_SECURE_ADDR_MASK);
+   bdinfo_print_num_ll("Secure ram",
+   gd->arch.secure_ram &
+   MEM_RESERVE_SECURE_ADDR_MASK);
}
 #endif
 #ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram)
-   bdinfo_print_num_l("Reserved ram", gd->arch.resv_ram);
+   bdinfo_print_num_ll("Reserved ram", gd->arch.resv_ram);
 #endif
 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr);
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 996546faf3..dfd50ae849 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -55,8 +55,8 @@ static void print_bi_dram(const struct bd_info *bd)
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
bdinfo_print_num_l("DRAM bank", i);
-   bdinfo_print_num_l("-> start",  bd->bi_dram[i].start);
-   bdinfo_print_num_l("-> size",   bd->bi_dram[i].size);
+   bdinfo_print_num_ll("-> start", bd->bi_dram[i].start);
+   bdinfo_print_num_ll("-> size",  bd->bi_dram[i].size);
}
}
 }
-- 
2.25.1

[PATCH 6/7] bdinfo: Rename function names to be clearer

[Bin Meng]

From: Bin Meng 

At present we have bdinfo_print_num() to print unsigned long numbers.
We also have print_phys_addr() which accept numbers that might be
64-bit on a 32-bit platform.

Rename these 2 functions to be clearer:

bdinfo_print_num() => bdinfo_print_num_l()
print_phys_addr()  => bdinfo_print_num_ll()

While we are here, make bdinfo_print_num_ll() public so that it can
be used outside cmd/bdinfo.c in the future.

Signed-off-by: Bin Meng 
---

 arch/arm/lib/bdinfo.c | 16 ++--
 arch/m68k/lib/bdinfo.c|  2 +-
 arch/powerpc/lib/bdinfo.c |  4 +--
 cmd/bdinfo.c  | 52 +++
 include/init.h|  3 ++-
 5 files changed, 39 insertions(+), 38 deletions(-)

diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index 25bc6e80f4..4a98cb7ef5 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -15,23 +15,23 @@ void arch_print_bdinfo(void)
 {
struct bd_info *bd = gd->bd;
 
-   bdinfo_print_num("arch_number", bd->bi_arch_number);
+   bdinfo_print_num_l("arch_number", bd->bi_arch_number);
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
-   bdinfo_print_num("Secure ram",
-gd->arch.secure_ram &
-MEM_RESERVE_SECURE_ADDR_MASK);
+   bdinfo_print_num_l("Secure ram",
+  gd->arch.secure_ram &
+  MEM_RESERVE_SECURE_ADDR_MASK);
}
 #endif
 #ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram)
-   bdinfo_print_num("Reserved ram", gd->arch.resv_ram);
+   bdinfo_print_num_l("Reserved ram", gd->arch.resv_ram);
 #endif
 #if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
-   bdinfo_print_num("TLB addr", gd->arch.tlb_addr);
+   bdinfo_print_num_l("TLB addr", gd->arch.tlb_addr);
 #endif
-   bdinfo_print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
-   bdinfo_print_num("sp start ", gd->start_addr_sp);
+   bdinfo_print_num_l("irq_sp", gd->irq_sp);   /* irq stack pointer */
+   bdinfo_print_num_l("sp start ", gd->start_addr_sp);
/*
 * TODO: Currently only support for davinci SOC's is added.
 * Remove this check once all the board implement this.
diff --git a/arch/m68k/lib/bdinfo.c b/arch/m68k/lib/bdinfo.c
index 404e5f19ed..92ea175202 100644
--- a/arch/m68k/lib/bdinfo.c
+++ b/arch/m68k/lib/bdinfo.c
@@ -38,7 +38,7 @@ void arch_print_bdinfo(void)
 
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
 #if defined(CONFIG_SYS_MBAR)
-   bdinfo_print_num("mbar", bd->bi_mbar_base);
+   bdinfo_print_num_l("mbar", bd->bi_mbar_base);
 #endif
bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
if (IS_ENABLED(CONFIG_PCI))
diff --git a/arch/powerpc/lib/bdinfo.c b/arch/powerpc/lib/bdinfo.c
index 36c9c99ee6..b14e75b68a 100644
--- a/arch/powerpc/lib/bdinfo.c
+++ b/arch/powerpc/lib/bdinfo.c
@@ -47,9 +47,9 @@ void arch_print_bdinfo(void)
 
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
 #if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
-   bdinfo_print_num("immr_base", bd->bi_immr_base);
+   bdinfo_print_num_l("immr_base", bd->bi_immr_base);
 #endif
-   bdinfo_print_num("bootflags", bd->bi_bootflags);
+   bdinfo_print_num_l("bootflags", bd->bi_bootflags);
bdinfo_print_mhz("intfreq", bd->bi_intfreq);
 #ifdef CONFIG_ENABLE_36BIT_PHYS
if (IS_ENABLED(CONFIG_PHYS_64BIT))
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index 8d8daa6336..996546faf3 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -18,11 +18,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void bdinfo_print_num(const char *name, ulong value)
+void bdinfo_print_num_l(const char *name, ulong value)
 {
printf("%-12s= 0x%0*lx\n", name, 2 * (int)sizeof(value), value);
 }
 
+void bdinfo_print_num_ll(const char *name, unsigned long long value)
+{
+   printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), value);
+}
+
 static void print_eth(int idx)
 {
char name[10], *val;
@@ -36,12 +41,6 @@ static void print_eth(int idx)
printf("%-12s= %s\n", name, val);
 }
 
-static void print_phys_addr(const char *name, phys_addr_t value)
-{
-   printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong),
-  (unsigned long long)value);
-}
-
 void bdinfo_print_mhz(const char *name, unsigned long hz)
 {
char buf[32];
@@ -55,9 +54,9 @@ static void print_bi_dram(const struct bd_info *bd)
 
for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
if (bd->bi_dram[i].size) {
-   bdinfo_print_num("DRAM bank",   i);
-   bdinfo_print_num("-> start",bd->bi_dram[i].start);
-   bdinfo_print_num("-> size", bd->bi_dram[i].size);
+   bdinfo_print_num_l("DRAM bank", i);
+   bdinfo_print_num_l("-> start",  bd->bi_

[PATCH 5/7] riscv: Change phys_addr_t and phys_size_t to 64-bit

[Bin Meng]

From: Bin Meng 

phys_addr_t and phys_size_t are currently defined as `unsigned long`,
but RV32 supports 34-bit physical address, hence both phys_addr_t and
phys_size_t should be defined to 64-bit using `unsigned long long`.

Signed-off-by: Bin Meng 
---

 arch/riscv/include/asm/types.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/include/asm/types.h b/arch/riscv/include/asm/types.h
index b800b2d221..49f7a5d6b3 100644
--- a/arch/riscv/include/asm/types.h
+++ b/arch/riscv/include/asm/types.h
@@ -35,8 +35,8 @@ typedef u64 dma_addr_t;
 typedef u32 dma_addr_t;
 #endif
 
-typedef unsigned long phys_addr_t;
-typedef unsigned long phys_size_t;
+typedef unsigned long long phys_addr_t;
+typedef unsigned long long phys_size_t;
 
 #endif /* __KERNEL__ */
 
-- 
2.25.1

[PATCH 4/7] fdtdec: Cast prior_stage_fdt_address with uintptr_t

[Bin Meng]

From: Bin Meng 

At present prior_stage_fdt_address is declared as phys_addr_t. On
a 32-bit platform where phys_addr_t can be 64-bit, assigning its
value to gd->fdt_blob which is a pointer, can cause warnings.

Cast it to uintptr_t before the assignment.

Signed-off-by: Bin Meng 
---

 lib/fdtdec.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 0ab7105fef..4abc7e00fd 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -1571,7 +1571,7 @@ int fdtdec_setup(void)
return -1;
}
 # elif defined(CONFIG_OF_PRIOR_STAGE)
-   gd->fdt_blob = (void *)prior_stage_fdt_address;
+   gd->fdt_blob = (void *)(uintptr_t)prior_stage_fdt_address;
 # endif
 # ifndef CONFIG_SPL_BUILD
/* Allow the early environment to override the fdt address */
-- 
2.25.1

[PATCH 3/7] serial: sifive: Cast dev_read_addr() with uintptr_t

[Bin Meng]

From: Bin Meng 

dev_read_addr() returns fdt_addr_t which is now a 64-bit address.
In a 32-bit build, this causes the following warning seen when
building serial_sifive.c:

warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

Cast the return value with uintptr_t.

Signed-off-by: Bin Meng 
---

 drivers/serial/serial_sifive.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_sifive.c b/drivers/serial/serial_sifive.c
index d26fe7e770..97bf20c967 100644
--- a/drivers/serial/serial_sifive.c
+++ b/drivers/serial/serial_sifive.c
@@ -178,7 +178,7 @@ static int sifive_serial_of_to_plat(struct udevice *dev)
 {
struct sifive_uart_plat *plat = dev_get_plat(dev);
 
-   plat->regs = (struct uart_sifive *)dev_read_addr(dev);
+   plat->regs = (struct uart_sifive *)(uintptr_t)dev_read_addr(dev);
if (IS_ERR(plat->regs))
return PTR_ERR(plat->regs);
 
-- 
2.25.1

[PATCH 1/7] riscv: Adjust board_get_usable_ram_top() for 32-bit

[Bin Meng]

From: Bin Meng 

When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().

While gd->ram_top should not be declared as type `unsigned long`,
which will be updated in a future patch, the current logic in
board_get_usable_ram_top() can be updated to cover both 64-bit
and 32-bit RISC-V.

Signed-off-by: Bin Meng 
---

 arch/riscv/cpu/fu540/dram.c   | 7 +++
 arch/riscv/cpu/generic/dram.c | 7 +++
 2 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c
index 1dc77efeca..259da65a54 100644
--- a/arch/riscv/cpu/fu540/dram.c
+++ b/arch/riscv/cpu/fu540/dram.c
@@ -22,7 +22,6 @@ int dram_init_banksize(void)
 
 ulong board_get_usable_ram_top(ulong total_size)
 {
-#ifdef CONFIG_64BIT
/*
 * Ensure that we run from first 4GB so that all
 * addresses used by U-Boot are 32bit addresses.
@@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
 * devices work fine because DMA mapping APIs will
 * provide 32bit DMA addresses only.
 */
-   if (gd->ram_top > SZ_4G)
-   return SZ_4G;
-#endif
+   if (gd->ram_top >= SZ_4G)
+   return SZ_4G - 1;
+
return gd->ram_top;
 }
diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c
index 1dc77efeca..259da65a54 100644
--- a/arch/riscv/cpu/generic/dram.c
+++ b/arch/riscv/cpu/generic/dram.c
@@ -22,7 +22,6 @@ int dram_init_banksize(void)
 
 ulong board_get_usable_ram_top(ulong total_size)
 {
-#ifdef CONFIG_64BIT
/*
 * Ensure that we run from first 4GB so that all
 * addresses used by U-Boot are 32bit addresses.
@@ -31,8 +30,8 @@ ulong board_get_usable_ram_top(ulong total_size)
 * devices work fine because DMA mapping APIs will
 * provide 32bit DMA addresses only.
 */
-   if (gd->ram_top > SZ_4G)
-   return SZ_4G;
-#endif
+   if (gd->ram_top >= SZ_4G)
+   return SZ_4G - 1;
+
return gd->ram_top;
 }
-- 
2.25.1

[PATCH 2/7] global_data.h: Change ram_top type to phys_addr_t

[Bin Meng]

From: Bin Meng 

It's possible to have ram_top above 4 GiB in a 32-bit system, hence
we need to declare ram_top as `phys_addr_t`.

Signed-off-by: Bin Meng 
---

 include/asm-generic/global_data.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/asm-generic/global_data.h 
b/include/asm-generic/global_data.h
index 19f70393b4..c19b32a82d 100644
--- a/include/asm-generic/global_data.h
+++ b/include/asm-generic/global_data.h
@@ -147,7 +147,7 @@ struct global_data {
/**
 * @ram_top: top address of RAM used by U-Boot
 */
-   unsigned long ram_top;
+   phys_addr_t ram_top;
/**
 * @relocaddr: start address of U-Boot in RAM
 *
-- 
2.25.1

[PATCH 0/7] Allow booting a 32-bit system with a top memory address beyond 4 GiB

[Bin Meng]

When testing QEMU RISC-V 'virt' machine with a 2 GiB memory
configuration, it was discovered gd->ram_top is assigned to
value zero in setup_dest_addr().

While 2 GiB QEMU RISC-V 'virt' happens to work with U-Boot today,
increasing more memory doesn't make a bootable system. There are
various places in U-Boot that prevents such from working.

While this is seen and tested on RISC-V, it's not RISC-V centric,
but a generic issue that may affect all architectures.


Bin Meng (7):
  riscv: Adjust board_get_usable_ram_top() for 32-bit
  global_data.h: Change ram_top type to phys_addr_t
  serial: sifive: Cast dev_read_addr() with uintptr_t
  fdtdec: Cast prior_stage_fdt_address with uintptr_t
  riscv: Change phys_addr_t and phys_size_t to 64-bit
  bdinfo: Rename function names to be clearer
  bdinfo: Change to use bdinfo_print_num_ll() where the number could be
64-bit

 arch/arm/lib/bdinfo.c | 16 +-
 arch/m68k/lib/bdinfo.c|  2 +-
 arch/powerpc/lib/bdinfo.c |  4 +--
 arch/riscv/cpu/fu540/dram.c   |  7 ++---
 arch/riscv/cpu/generic/dram.c |  7 ++---
 arch/riscv/include/asm/types.h|  4 +--
 cmd/bdinfo.c  | 52 +++
 drivers/serial/serial_sifive.c|  2 +-
 include/asm-generic/global_data.h |  2 +-
 include/init.h|  3 +-
 lib/fdtdec.c  |  2 +-
 11 files changed, 50 insertions(+), 51 deletions(-)

-- 
2.25.1

Re: [scan-ad...@coverity.com: New Defects reported by Coverity Scan for Das U-Boot]

[Heinrich Schuchardt]

On 21.01.21 12:36, Sughosh Ganu wrote:
>
>
> On Thu, 21 Jan 2021 at 00:34, Tom Rini  > wrote:
>
> I decided to run Coverity part-way through the merge window this time
> and here's what's been found so far.
>
> - Forwarded message from scan-ad...@coverity.com
>  -
>
> Date: Mon, 18 Jan 2021 17:53:19 + (UTC)
> From: scan-ad...@coverity.com 
> To: tom.r...@gmail.com 
> Subject: New Defects reported by Coverity Scan for Das U-Boot
>
> Hi,
>
> Please find the latest report on new defect(s) introduced to Das
> U-Boot found with Coverity Scan.
>
> 23 new defect(s) introduced to Das U-Boot found with Coverity Scan.
> 2 defect(s), reported by Coverity Scan earlier, were marked fixed in
> the recent build analyzed by Coverity Scan.
>
> New defect(s) Reported-by: Coverity Scan
> Showing 20 of 23 defect(s)
>
> ** CID 316356:  Resource leaks  (RESOURCE_LEAK)
> /tools/mkeficapsule.c: 225 in add_public_key()
>
>
> 
>  
>
>
> 
> 
> *** CID 316356:  Resource leaks  (RESOURCE_LEAK)
> /tools/mkeficapsule.c: 225 in add_public_key()
> 219             if (ret < 0) {
> 220                     fprintf(stderr, "%s: Unable to add public
> key to the FDT\n",
> 221                             __func__);
> 222                     goto err;
> 223             }
> 224     
> >>>     CID 316356:  Resource leaks  (RESOURCE_LEAK)
> >>>     Handle variable "srcfd" going out of scope leaks the handle.
> 225             return 0;
> 226     
> 227     err:
> 228             if (sptr)
> 229                     munmap(sptr, src_size);
> 230     
>
>
> I think these should not cause any issues, since the function return
> results in the process termination in both the scenarios of success and
> failure. But i will post a patch to handle these errors to keep the
> resource handling consistent.

Looking at line 234f:

    if (srcfd >= 0)
close(srcfd);

The comparison is wrong. It should be:

    if (srcfd != -1)
close(srcfd);

The open.2 man-page says that only -1 signals an error. According to the
man-page -2 is a legal value for a file descriptor.

The initialization of destfd is wrong:

141:
int destfd = 0;

In case of an error opening srcfd this leads to closing file descriptor
0 which relates to the console input. You should use:

int destfd = -1;

and

    if (destfd != -1)
close(destfd);

Best regards

Heinrich

Re: [PATCH 1/2] board: Atmel: Add SAMA5D27 giant board

[Greg Gallagher]

On Thu, Jan 21, 2021 at 2:19 AM  wrote:

> On 21.01.2021 00:38, Greg Gallagher wrote:
> > Giant board is a tiny SBC based on the Adafruit Feather form factor,
> > created by groboards it contains a SAMA5D2 processor (SAMA5D27),
> > 128 MB of RAM and a microSD card for storage.
> >
> > Signed-off-by: Greg Gallagher 
> > ---
>
> Hi Greg,
>
> This patch [1/2] ARM: at91: spl: add spl_early_init for sama52d platforms
>
> has disappeared from your series. Do you still need it and forgot to
> send it ?
>
> Thank you for the patch,
> Eugen
> >
> >   arch/arm/dts/Makefile |   3 +-
> >   arch/arm/dts/at91-sama5d27_giantboard.dts | 128 ++
> >   board/atmel/sama5d27_som1_ek/MAINTAINERS  |   6 +
> >   configs/sama5d27_giantboard_defconfig |  97 
> >   4 files changed, 233 insertions(+), 1 deletion(-)
> >   create mode 100644 arch/arm/dts/at91-sama5d27_giantboard.dts
> >   create mode 100644 configs/sama5d27_giantboard_defconfig
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index e320c2254e..8a6a8bcee3 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -905,7 +905,8 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
> >  at91-sama5d2_xplained.dtb
> >
> >   dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
> > -   at91-sama5d27_som1_ek.dtb
> > +   at91-sama5d27_som1_ek.dtb   \
> > +   at91-sama5d27_giantboard.dtb
> >
> >   dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
> >  at91-sama5d27_wlsom1_ek.dtb
> > diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts
> b/arch/arm/dts/at91-sama5d27_giantboard.dts
> > new file mode 100644
> > index 00..e81ca60ca0
> > --- /dev/null
> > +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
> > @@ -0,0 +1,128 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
> > + *
> > + * Copyright (C) 2020 Greg Gallagher 
> > + *
> > + * Derived from at91-sama5d27_som1_ek.dts
> > + *
> > + * Copyright (C) 2017 Microchip Corporation
> > + *   Wenyou Yang 
> > + */
> > +/dts-v1/;
> > +#include "sama5d2.dtsi"
> > +#include "sama5d2-pinfunc.h"
> > +
> > +/ {
> > +   model = "Giant Board";
> > +   compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2",
> "atmel,sama5";
> > +
> > +   memory {
> > +   reg = <0x2000 0x800>;
> > +   };
> > +
> > +   chosen {
> > +   u-boot,dm-pre-reloc;
> > +   stdout-path = &uart1;
> > +   };
> > +
> > +   ahb {
> > +   sdmmc1: sdio-host@b000 {
> > +   bus-width = <4>;
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default
> &pinctrl_sdmmc1_ck_cd_default>;
> > +   status = "okay";
> > +   u-boot,dm-pre-reloc;
> > +   };
> > +
> > +   apb {
> > +
> > +   uart1: serial@f802 {
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&pinctrl_uart1_default>;
> > +   status = "okay";
> > +   u-boot,dm-pre-reloc;
> > +   };
> > +
> > +   i2c0: i2c@f8028000 {
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&pinctrl_i2c0_default>;
> > +   status = "okay";
> > +   };
> > +
> > +   i2c1: i2c@fc028000 {
> > +   pinctrl-names = "default";
> > +   pinctrl-0 = <&pinctrl_i2c1_default>;
> > +   status = "okay";
> > +
> > +   pmic@5b {
> > +   compatible =
> "active-semi,act8945a";
> > +   reg = <0x5b>;
> > +   active-semi,vsel-low;
> > +   status = "okay";
> > +   };
> > +   };
> > +
> > +   pit: timer@f8048030 {
> > +   status = "okay";
> > +   u-boot,dm-pre-reloc;
> > +   };
> > +
> > +   sfr: sfr@f803 {
> > +   status = "okay";
> > +   u-boot,dm-pre-reloc;
> > +   };
> > +
> > +   pioA: gpio@fc038000 {
> > +   pinctrl {
> > +
> > +   pinctrl_sdmmc1_cmd_dat_default:
> sdmmc1_cmd_dat_default {
> > +   pinmux =
> ,
> > +
> ,
> > +
> ,
> > +
> ,
> > +
> ;
> > +   bias-pu

Re: [PATCH] mkeficapsule: Free up resources used for adding public key to dtb

[Heinrich Schuchardt]

On 21.01.21 12:52, Sughosh Ganu wrote:
> Fix the issues flagged by Coverity on resources not being released in
> the add_public_key function.
>
> Signed-off-by: Sughosh Ganu 
> ---
>  tools/mkeficapsule.c | 13 +++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
> index 270943fc90..caf0a1b231 100644
> --- a/tools/mkeficapsule.c
> +++ b/tools/mkeficapsule.c
> @@ -150,6 +150,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (srcfd == -1) {
>   fprintf(stderr, "%s: Can't open %s: %s\n",
>   __func__, pkey_file, strerror(errno));
> + ret = -1;
>   goto err;
>   }
>
> @@ -157,6 +158,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (ret == -1) {
>   fprintf(stderr, "%s: Can't stat %s: %s\n",
>   __func__, pkey_file, strerror(errno));
> + ret = -1;
>   goto err;
>   }
>
> @@ -167,6 +169,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if ((sptr == MAP_FAILED) || (errno != 0)) {
>   fprintf(stderr, "%s: Failed to mmap %s:%s\n",
>   __func__, pkey_file, strerror(errno));
> + ret = -1;
>   goto err;
>   }
>
> @@ -175,6 +178,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (destfd == -1) {
>   fprintf(stderr, "%s: Can't open %s: %s\n",
>   __func__, dtb_file, strerror(errno));
> + ret = -1;
>   goto err;
>   }
>
> @@ -189,6 +193,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (ftruncate(destfd, dtb.st_size)) {
>   fprintf(stderr, "%s: Can't expand %s: %s\n",
>   __func__, dtb_file, strerror(errno));
> + ret = -1;
>   goto err;;

Thanks for providing the patch.

Please, remove the duplicate semicolon here.

main() should return the constant EXIT_FAILURE (glibc defines this as 1)
if a failure occurs, not -1.

scripts/checkpatch.pl -f tools/mkeficapsule.c
reports some other style issues:

CHECK: Unnecessary parentheses around 'sptr == MAP_FAILED'
#167: FILE: tools/mkeficapsule.c:167:
+   if ((sptr == MAP_FAILED) || (errno != 0)) {

CHECK: Unnecessary parentheses around 'errno != 0'
#167: FILE: tools/mkeficapsule.c:167:
+   if ((sptr == MAP_FAILED) || (errno != 0)) {

WARNING: Statements terminations use 1 semicolon
#192: FILE: tools/mkeficapsule.c:192:
+   goto err;;

CHECK: Unnecessary parentheses around 'dptr == MAP_FAILED'
#199: FILE: tools/mkeficapsule.c:199:
+   if ((dptr == MAP_FAILED) || (errno != 0)) {

CHECK: Unnecessary parentheses around 'errno != 0'
#199: FILE: tools/mkeficapsule.c:199:
+   if ((dptr == MAP_FAILED) || (errno != 0)) {


In U-Boot we prefer to avoid terms like (errno != 0) in a logical statement:

if (dptr == MAP_FAILED || errno) {

But it is completely unnecessary to check errno at all here because
errno is only set if mmap() returns MAP_FAILED (see the mmap()
man-page). So the line should be:

192
if (dptr == MAP_FAILED) {

Now you can remove the following line:

195:
-   errno = 0;

Best regards

Heinrich

>   }
>
> @@ -199,11 +204,13 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if ((dptr == MAP_FAILED) || (errno != 0)) {
>   fprintf(stderr, "%s: Failed to mmap %s:%s\n",
>   __func__, dtb_file, strerror(errno));
> + ret = -1;
>   goto err;
>   }
>
>   if (fdt_check_header(dptr)) {
>   fprintf(stderr, "%s: Invalid FDT header\n", __func__);
> + ret = -1;
>   goto err;
>   }
>
> @@ -211,6 +218,7 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (ret) {
>   fprintf(stderr, "%s: Cannot expand FDT: %s\n",
>   __func__, fdt_strerror(ret));
> + ret = -1;
>   goto err;
>   }
>
> @@ -219,10 +227,11 @@ static int add_public_key(const char *pkey_file, const 
> char *dtb_file,
>   if (ret < 0) {
>   fprintf(stderr, "%s: Unable to add public key to the FDT\n",
>   __func__);
> + ret = -1;
>   goto err;
>   }
>
> - return 0;
> + ret = 0;
>
>  err:
>   if (sptr)
> @@ -237,7 +246,7 @@ err:
>   if (destfd >= 0)
>   close(destfd);
>
> - return -1;
> + return ret;
>  }
>
>  static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
>

Re: [patch v3 3/9] ockchip: video: edp: Change interrupt polarity configuration

[Kever Yang]

Hi Arnaud,
Please correct the typo in subject line.

Thanks,
- Kever

Arnaud Patard  于2020年11月20日周五 下午9:30写道：

> The linux code is setting polarity configuration to 3 but
> uboot code is setting it to 1. Change the configuration to match the
> linux configuration
>
> Signed-off-by: Arnaud Patard 
> Index: u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
> ===
> --- u-boot.orig/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
> +++ u-boot/arch/arm/include/asm/arch-rockchip/edp_rk3288.h
> @@ -297,7 +297,9 @@ check_member(rk3288_edp, pll_reg_5, 0xa0
>
>  /* int_ctl */
>  #define SOFT_INT_CTRL  (0x1 << 2)
> -#define INT_POL(0x1 << 0)
> +#define INT_POL1   (0x1 << 1)
> +#define INT_POL0   (0x1 << 0)
> +#define INT_POL(INT_POL0 |
> INT_POL1)
>
>  /* sys_ctl_1 */
>  #define DET_STA(0x1 << 2)
>
>
>

Re: [patch v3 4/9] ockchip: video: vop: Reserve efi fb memory

[Kever Yang]

Hi Arnaud,

First, please correct the typo in the subject line.

Arnaud Patard  于2020年11月20日周五 下午9:31写道：

> When booting with EFI and graphics, the memory used for framebuffer
> has to be reserved, otherwise it may leads to kernel memory
> overwrite.
>
> Signed-off-by: Arnaud Patard 
> Index: u-boot/drivers/video/rockchip/rk_vop.c
> ===
> --- u-boot.orig/drivers/video/rockchip/rk_vop.c
> +++ u-boot/drivers/video/rockchip/rk_vop.c
> @@ -20,6 +20,8 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -394,6 +396,13 @@ int rk_vop_probe(struct udevice *dev)
> if (!(gd->flags & GD_FLG_RELOC))
> return 0;
>
> +   plat->base = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size -
> plat->size;
>
This is a change to plat->base value, do we have to do this?
If we have to use this address for EFI, I would like this code not to
change for board
without EFI_LOADER support.

Thanks,
- Kever

> +
> +#if defined(CONFIG_EFI_LOADER)
> +   debug("Adding to EFI map %d @ %lx\n", plat->size, plat->base);
> +   efi_add_memory_map(plat->base, plat->size,
> EFI_RESERVED_MEMORY_TYPE);
> +#endif
> +
> priv->regs = (struct rk3288_vop *)dev_read_addr(dev);
>
> /*
>
>
>

Re: [patch v3 7/9] rockchip: video: vop: Fix format of fbbase in debug string

[Kever Yang]

Hi Arnaud,

Arnaud Patard  于2020年11月20日周五 下午9:32写道：

> The debug string printing the device name, framebuffer address and of node
> is using %lu as format for the framebuffer address, which is not so nice.
> Change it to %lx.
>
> Signed-off-by: Arnaud Patard 
> Index: u-boot/drivers/video/rockchip/rk_vop.c
> ===
> --- u-boot.orig/drivers/video/rockchip/rk_vop.c
> +++ u-boot/drivers/video/rockchip/rk_vop.c
> @@ -239,7 +239,7 @@ static int rk_display_init(struct udevic
> ofnode remote;
> const char *compat;
>
> -   debug("%s(%s, %lu, %s)\n", __func__,
> +   debug("%s(%s, %lx, %s)\n", __func__,
>

Please use 0x%lx instead.

Thanks,
- Kever

>   dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
>
> ret = ofnode_read_u32(ep_node, "remote-endpoint", &remote_phandle);
>
>
>

Re: [patch v3 9/9] rockchip: videp: vop: Add reset support

[Kever Yang]

Hi Arnaud,
Please update the typo at subject line, /videp/video/
Other change looks good to me, you can add my review tag after update:
Reviewed-by: Kever Yang

Thanks,
- Kever

Arnaud Patard  于2020年11月20日周五 下午9:32写道：

> In order to ensure that the VOP registers are in correct state,
> add missing support for the VOP reset lines found in the device-tree
>
> Signed-off-by: Arnaud Patard 
> Index: u-boot/drivers/video/rockchip/rk_vop.c
> ===
> --- u-boot.orig/drivers/video/rockchip/rk_vop.c
> +++ u-boot/drivers/video/rockchip/rk_vop.c
> @@ -8,9 +8,11 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -36,14 +38,16 @@ enum vop_pol {
> DCLK_INVERT= 3
>  };
>
> -static void rkvop_enable(struct rk3288_vop *regs, ulong fbbase,
> +static void rkvop_enable(struct udevice *dev, struct rk3288_vop *regs,
> ulong fbbase,
>  int fb_bits_per_pixel,
> -const struct display_timing *edid)
> +const struct display_timing *edid,
> +struct reset_ctl *dclk_rst)
>  {
> u32 lb_mode;
> u32 rgb_mode;
> u32 hactive = edid->hactive.typ;
> u32 vactive = edid->vactive.typ;
> +   int ret;
>
> writel(V_ACT_WIDTH(hactive - 1) | V_ACT_HEIGHT(vactive - 1),
>®s->win0_act_info);
> @@ -91,6 +95,18 @@ static void rkvop_enable(struct rk3288_v
>
> writel(fbbase, ®s->win0_yrgb_mst);
> writel(0x01, ®s->reg_cfg_done); /* enable reg config */
> +
> +   ret = reset_assert(dclk_rst);
> +   if (ret) {
> +   dev_warn(dev, "failed to assert dclk reset (ret=%d)\n",
> ret);
> +   return;
> +   }
> +   udelay(20);
> +
> +   ret = reset_deassert(dclk_rst);
> +   if (ret)
> +   dev_warn(dev, "failed to deassert dclk reset (ret=%d)\n",
> ret);
> +
>  }
>
>  static void rkvop_set_pin_polarity(struct udevice *dev,
> @@ -238,6 +254,7 @@ static int rk_display_init(struct udevic
> enum video_log2_bpp l2bpp;
> ofnode remote;
> const char *compat;
> +   struct reset_ctl dclk_rst;
>
> debug("%s(%s, %lx, %s)\n", __func__,
>   dev_read_name(dev), fbbase, ofnode_get_name(ep_node));
> @@ -354,7 +371,14 @@ static int rk_display_init(struct udevic
> }
>
> rkvop_mode_set(dev, &timing, vop_id);
> -   rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
> +
> +   ret = reset_get_by_name(dev, "dclk", &dclk_rst);
> +   if (ret) {
> +   dev_err(dev, "failed to get dclk reset (ret=%d)\n", ret);
> +   return ret;
> +   }
> +
> +   rkvop_enable(dev, regs, fbbase, 1 << l2bpp, &timing, &dclk_rst);
>
> ret = display_enable(disp, 1 << l2bpp, &timing);
> if (ret)
> @@ -391,11 +415,31 @@ int rk_vop_probe(struct udevice *dev)
> struct rk_vop_priv *priv = dev_get_priv(dev);
> int ret = 0;
> ofnode port, node;
> +   struct reset_ctl ahb_rst;
>
> /* Before relocation we don't need to do anything */
> if (!(gd->flags & GD_FLG_RELOC))
> return 0;
>
> +   ret = reset_get_by_name(dev, "ahb", &ahb_rst);
> +   if (ret) {
> +   dev_err(dev, "failed to get ahb reset (ret=%d)\n", ret);
> +   return ret;
> +   }
> +
> +   ret = reset_assert(&ahb_rst);
> +   if (ret) {
> +   dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
> +   return ret;
> +   }
> +   udelay(20);
> +
> +   ret = reset_deassert(&ahb_rst);
> +   if (ret) {
> +   dev_err(dev, "failed to deassert ahb reset (ret=%d)\n",
> ret);
> +   return ret;
> +   }
> +
> plat->base = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size -
> plat->size;
>
>  #if defined(CONFIG_EFI_LOADER)
>
>
>

Re: [PATCH v2 01/21] mmc: sdhci: Add helper functions for UHS modes

[Aswath Govindraju]

Hi Jaehoon,

On 21/01/21 10:40 am, Jaehoon Chung wrote:
> Hi Aswath,
> 
> On 1/21/21 1:13 PM, Aswath Govindraju wrote:
>> Hi Jaehoon,
>>
>> On 21/01/21 4:26 am, Jaehoon Chung wrote:
>>> Hi Aswath,
>>>
>>> On 1/19/21 9:35 PM, Aswath Govindraju wrote:
 Hi Jaehoon,

 On 05/11/20 4:03 am, Jaehoon Chung wrote:
> On 11/5/20 4:05 AM, Faiz Abbas wrote:
>> Jaehoon,
>>
>> On 21/10/20 5:08 pm, Jaehoon Chung wrote:
>>> Hi Faiz,
>>>
>>> On 10/16/20 8:08 PM, Faiz Abbas wrote:
 Add a set_voltage() function which handles the switch from 3.3V to 1.8V
 for SD card UHS modes.

 Signed-off-by: Faiz Abbas 
 ---
  drivers/mmc/sdhci.c | 51 +
  include/sdhci.h |  1 +
  2 files changed, 52 insertions(+)

 diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
 index 7673219fb3..a69f058191 100644
 --- a/drivers/mmc/sdhci.c
 +++ b/drivers/mmc/sdhci.c
 @@ -20,6 +20,7 @@
  #include 
  #include 
  #include 
 +#include 
  
  static void sdhci_reset(struct sdhci_host *host, u8 mask)
  {
 @@ -556,6 +557,56 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  }
  
 +#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
 +static void sdhci_set_voltage(struct sdhci_host *host)
 +{
 +  struct mmc *mmc = (struct mmc *)host->mmc;
 +  u32 ctrl;
 +
 +  ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
 +
 +  switch (mmc->signal_voltage) {
 +  case MMC_SIGNAL_VOLTAGE_330:
 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
 +  if (mmc->vqmmc_supply) {
 +  regulator_set_enable(mmc->vqmmc_supply, false);
 +  regulator_set_value(mmc->vqmmc_supply, 330);
>>>
>>> Doesn't need to consider about fail to set its value?
>>
>> You're right. I'll handle the failure case in v3.
>>
>>>
 +  regulator_set_enable(mmc->vqmmc_supply, true);
 +  }
 +#endif
 +  mdelay(5);
>>>
>>> For what purpose about mdelay(5)?
>>
>> I'm following this from the kernel implementation here:
>> https://protect2.fireeye.com/v1/url?k=8b617b16-d4fa420c-8b60f059-0cc47a6cba04-71d56f4128587abb&q=1&e=02f975f3-5191-4501-a554-a58145bd6ac1&u=https%3A%2F%2Fgithub.com%2Ftorvalds%2Flinux%2Fblob%2Fmaster%2Fdrivers%2Fmmc%2Fhost%2Fsdhci.c%23L2547
>>
>> Not sure if this a part of the spec or not though.
>
> Thanks for sharing info. :)
>
>>
>>>
>>>
 +  if (IS_SD(mmc)) {
 +  ctrl &= ~SDHCI_CTRL_VDD_180;
 +  sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 +  }
 +  break;
 +  case MMC_SIGNAL_VOLTAGE_180:
 +#if CONFIG_IS_ENABLED(DM_REGULATOR)
 +  if (mmc->vqmmc_supply) {
 +  regulator_set_enable(mmc->vqmmc_supply, false);
 +  regulator_set_value(mmc->vqmmc_supply, 180);
 +  regulator_set_enable(mmc->vqmmc_supply, true);
 +  }
 +#endif
 +  if (IS_SD(mmc)) {
 +  ctrl |= SDHCI_CTRL_VDD_180;
 +  sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
 +  }
 +  break;
 +  default:
 +  /* No signal voltage switch required */
 +  return;
 +  }
 +}
 +#else
 +static void sdhci_set_voltage(struct sdhci_host *host) { }
 +#endif
 +void sdhci_set_control_reg(struct sdhci_host *host)
>>>
>>> this function is called as callback function in sdhci_set_ios(). 
>>> it's strange... set_control_reg callback is for host specific control 
>>> register.
>>>
>>> I think that it doesn't need to assign to callback.
>>
>> This is the default set_control_reg() implementation which is defined
>> in the sdhci spec. Any host that that wants default implementation
>> case assign this as their callback.
>>
>> Hosts that have custom implementations can add in their own drivers.
>
> Yes..but when i have checked your code. It doesn't need to assign to 
> callback for your driver.
> If sdhci_set_control_reg() is common function about all sdhci-xx driver, 
> then it can be just added in sdhci_set_ios().
>> callback is for sdhci-xx specific progress.
>
> In my opinion,
>
> static int sdhci_set_ios() 
> {
> ...
>   sdhci_set_control_re

[PATCH v3 20/20] configs: am65x_evm: Add configs for UHS modes

[Aswath Govindraju]

From: Faiz Abbas 

Add configs for voltage switching and UHS modes for the SD card
and HS200 for the eMMC.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 configs/am65x_evm_a53_defconfig | 8 
 configs/am65x_evm_r5_defconfig  | 2 ++
 2 files changed, 10 insertions(+)

diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index 941073ce7f19..2ab978b6f37b 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -96,12 +96,17 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_KEYBOARD=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -133,6 +138,9 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
 CONFIG_RESET_TI_SCI=y
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 96c4351196d2..b9b11010a105 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -85,6 +85,8 @@ CONFIG_K3_SEC_PROXY=y
 CONFIG_K3_AVS0=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
-- 
2.17.1

Re: Pull request: u-boot-rockchip-20210121

[Kever Yang]

Hi Arnaud,

On 2021/1/21 下午7:39, Arnaud Patard (Rtp) wrote:

Kever Yang  writes:

Hi,


Hi Tom,

Please pull the rockchip updates/fixes:
- New board: rk3328 NanoPi R2S board;
- Fix init voltage for some rk3399 boards;
- enable rng for rk3399 by default;
- set default to SPI bus 1 for SPI-flash for some board;
- add dwc PCIe controller driver on rockchip platform;

I don't remember getting any mail about my patches related to edp on
pinebook pro patchset
(https://patchwork.ozlabs.org/project/uboot/list/?series=215793).

Did I miss something something  ?


Sorry, I was plan to reply, but busy at other things and forgot.

Too many typo at subjects in different patches, will need to update.


Thanks,

- Kever



Thanks,
Arnaud

[PATCH v3 19/20] arm: dts: k3-am654-base-board: Limit Sd card to High speed modes

[Aswath Govindraju]

From: Faiz Abbas 

There's an issue with the base board in which the power cycle
circuit takes way longer to power down than expected by mmc core.
code. This prevents the card from enumerating in UHS modes.

Disable UHS modes for this board until a new board revision fixes
the issue.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am654-base-board.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/k3-am654-base-board.dts 
b/arch/arm/dts/k3-am654-base-board.dts
index 33a1b9fdc4b7..830526a1e473 100644
--- a/arch/arm/dts/k3-am654-base-board.dts
+++ b/arch/arm/dts/k3-am654-base-board.dts
@@ -144,6 +144,7 @@
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
+   sdhci-caps-mask = <0x7 0x0>;
disable-wp;
 };
 
-- 
2.17.1

[PATCH v3 18/20] arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values

[Aswath Govindraju]

From: Faiz Abbas 

Add the appropriate itapdly and clkbuf-sel values required for
some lower speed modes.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am65-main.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index d151e27028cd..a7b03dc66908 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -109,6 +109,11 @@
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x5>;
ti,otap-del-sel-hs400 = <0x0>;
+   ti,itap-del-sel-legacy = <0xa>;
+   ti,itap-del-sel-mmc-hs = <0x1>;
+   ti,itap-del-sel-sdr12 = <0xa>;
+   ti,itap-del-sel-sdr25 = <0x1>;
+   ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
};
@@ -130,6 +135,10 @@
ti,otap-del-sel-ddr50 = <0x4>;
ti,otap-del-sel-ddr52 = <0x4>;
ti,otap-del-sel-hs200 = <0x7>;
+   ti,itap-del-sel-legacy = <0xa>;
+   ti,itap-del-sel-mmc-hs = <0x1>;
+   ti,itap-del-sel-sdr12 = <0xa>;
+   ti,itap-del-sel-sdr25 = <0x1>;
ti,clkbuf-sel = <0x7>;
ti,trm-icp = <0x8>;
dma-coherent;
-- 
2.17.1

[PATCH v3 17/20] configs: j7200_evm: Add support for UHS modes

[Aswath Govindraju]

From: Faiz Abbas 

Add configs to support UHS modes for the SD card and HS200 for the eMMC.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 configs/j7200_evm_a72_defconfig | 8 
 configs/j7200_evm_r5_defconfig  | 1 +
 2 files changed, 9 insertions(+)

diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index 1d2526b5f1b2..162bcc8753ff 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -111,11 +111,16 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -143,6 +148,9 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_REMOTEPROC_TI_K3_R5F=y
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 3820fc508b38..b20698fd0ed1 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
-- 
2.17.1

[PATCH v3 16/20] configs: j721e_evm: Add support for UHS modes

[Aswath Govindraju]

From: Faiz Abbas 

Add configs to support UHS modes for the SD card and HS200 for the eMMC.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 configs/j721e_evm_a72_defconfig | 8 
 configs/j721e_evm_r5_defconfig  | 1 +
 2 files changed, 9 insertions(+)

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 982e3df2f224..e14005c39dd8 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -108,11 +108,16 @@ CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
 CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -141,6 +146,9 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
 CONFIG_SPL_RAM=y
 CONFIG_REMOTEPROC_TI_K3_DSP=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 41285481005c..7b4f0afce61f 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -89,6 +89,7 @@ CONFIG_K3_AVS0=y
 CONFIG_ESM_PMIC=y
 CONFIG_DM_MMC=y
 CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
-- 
2.17.1

[PATCH v3 15/20] arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes

[Aswath Govindraju]

From: Faiz Abbas 

Add support for UHS modes by adding the regulators to power cycle
and voltage switch the card. Also add pinmuxes required for each
node

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-j7200-common-proc-board.dts   | 49 ++-
 arch/arm/dts/k3-j7200-main.dtsi   |  1 +
 .../arm/dts/k3-j7200-r5-common-proc-board.dts | 15 ++
 3 files changed, 63 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts 
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index cc3d933cbb51..20974aff5929 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -7,6 +7,7 @@
 
 #include 
 #include "k3-j7200-som-p0.dtsi"
+#include 
 
 / {
chosen {
@@ -20,6 +21,29 @@
remoteproc2 = &main_r5fss0_core0;
remoteproc3 = &main_r5fss0_core1;
};
+
+   vdd_mmc1: fixedregulator-sd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_mmc1";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   enable-active-high;
+   gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+   };
+
+   vdd_sd_dv: gpio-regulator-vdd-sd-dv {
+   compatible = "regulator-gpio";
+   regulator-name = "vdd_sd_dv";
+   pinctrl-names = "default";
+   pinctrl-0 = <&vdd_sd_dv_pins_default>;
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
+   states = <180 0x0
+ 330 0x1>;
+   };
 };
 
 &wkup_pmx0 {
@@ -69,6 +93,25 @@
>;
};
 
+   main_mmc1_pins_default: main_mmc1_pins_default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+   J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+   J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+   J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+   J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+   J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+   J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+   J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) 
TIMER_IO0.MMC1_SDCD */
+   >;
+   };
+
+   vdd_sd_dv_pins_default: vdd_sd_dv_pins_default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0xd0, PIN_INPUT, 7) /* (T5) 
SPI0_D1.GPIO0_55 */
+   >;
+   };
+
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS 
*/
@@ -140,10 +183,12 @@
 
 &main_sdhci1 {
/* SD card */
+   pinctrl-0 = <&main_mmc1_pins_default>;
+   pinctrl-names = "default";
+   vmmc-supply = <&vdd_mmc1>;
+   vqmmc-supply = <&vdd_sd_dv>;
ti,driver-strength-ohm = <50>;
disable-wp;
-   no-1-8-v;
-   sdhci-caps-mask = <0x800F 0x0>;
 };
 
 &main_i2c0 {
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index b722204c44ac..8150ff6332c2 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -253,6 +253,7 @@
ti,otap-del-sel-sdr50 = <0xc>;
ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
+   ti,clkbuf-sel = <0x7>;
dma-coherent;
};
 
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts 
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 2ac887b180c9..04914320609c 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -162,6 +162,19 @@
>;
};
 
+   main_mmc1_pins_default: main_mmc1_pins_default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
+   J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
+   J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
+   J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
+   J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
+   J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
+   J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
+   J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) 
TIMER_IO0.MMC1_SDCD */
+   >;
+   };
+
main_usbss0_pins_default: main_usbss0_pins_default {
   

[PATCH v3 14/20] arm: dts: k3-j7200-main: Add support for gpio0

[Aswath Govindraju]

From: Faiz Abbas 

Add support for the main_gpio0 node

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-j7200-main.dtsi | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index c25f03cf23d9..b722204c44ac 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -197,6 +197,28 @@
clock-names = "fclk";
};
 
+   main_gpio0: gpio@60 {
+   compatible = "ti,j721e-gpio", "ti,keystone-gpio";
+   reg = <0x0 0x0060 0x0 0x100>;
+   gpio-controller;
+   #gpio-cells = <2>;
+   interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
+<105 1 IRQ_TYPE_EDGE_RISING>,
+<105 2 IRQ_TYPE_EDGE_RISING>,
+<105 3 IRQ_TYPE_EDGE_RISING>,
+<105 4 IRQ_TYPE_EDGE_RISING>,
+<105 5 IRQ_TYPE_EDGE_RISING>,
+<105 6 IRQ_TYPE_EDGE_RISING>,
+<105 7 IRQ_TYPE_EDGE_RISING>;
+   interrupt-controller;
+   #interrupt-cells = <2>;
+   ti,ngpio = <69>;
+   ti,davinci-gpio-unbanked = <0>;
+   power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 105 0>;
+   clock-names = "gpio";
+   };
+
main_sdhci0: sdhci@4f8 {
compatible = "ti,j721e-sdhci-8bit";
reg = <0x0 0x04f8 0x0 0x260>, <0x0 0x4f88000 0x0 0x134>;
-- 
2.17.1

[PATCH v3 13/20] arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD card

[Aswath Govindraju]

From: Faiz Abbas 

Add support for regulators to power cycle and switch IO voltage to the
SD card. This enables support for UHS modes.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-j721e-common-proc-board.dts | 32 +
 1 file changed, 32 insertions(+)

diff --git a/arch/arm/dts/k3-j721e-common-proc-board.dts 
b/arch/arm/dts/k3-j721e-common-proc-board.dts
index 496a15e1d1ac..6b29200bba85 100644
--- a/arch/arm/dts/k3-j721e-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-common-proc-board.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include "k3-j721e-som-p0.dtsi"
+#include 
 
 / {
chosen {
@@ -24,6 +25,29 @@
remoteproc7 = &c66_1;
remoteproc8 = &c71_0;
};
+
+   vdd_mmc1: fixedregulator-sd {
+   compatible = "regulator-fixed";
+   regulator-name = "vdd_mmc1";
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   enable-active-high;
+   gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
+   };
+
+   vdd_sd_dv_alt: gpio-regulator-TLV71033 {
+   compatible = "regulator-gpio";
+   pinctrl-names = "default";
+   pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
+   regulator-name = "tlv71033";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <330>;
+   regulator-boot-on;
+   gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
+   states = <180 0x0
+ 330 0x1>;
+   };
 };
 
 &wkup_uart0 {
@@ -79,6 +103,12 @@
J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
>;
};
+
+   vdd_sd_dv_alt_pins_default: vdd_sd_dv_alt_pins_default {
+   pinctrl-single,pins = <
+   J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) 
SPI1_CS1.GPIO0_117 */
+   >;
+   };
 };
 
 &main_sdhci0 {
@@ -92,6 +122,8 @@
pinctrl-names = "default";
pinctrl-0 = <&main_mmc1_pins_default>;
ti,driver-strength-ohm = <50>;
+   vmmc-supply = <&vdd_mmc1>;
+   vqmmc-supply = <&vdd_sd_dv_alt>;
 };
 
 &main_pmx0 {
-- 
2.17.1

[PATCH v3 12/20] arm: dts: k3-j721e-main: Update otap-delay values

[Aswath Govindraju]

From: Faiz Abbas 

Update otap delay values to match with the latest Data Manual[1].

[1] https://www.ti.com/lit/gpn/dra829v

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-j721e-main.dtsi | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/k3-j721e-main.dtsi b/arch/arm/dts/k3-j721e-main.dtsi
index 33db74a267a6..e08e74370611 100644
--- a/arch/arm/dts/k3-j721e-main.dtsi
+++ b/arch/arm/dts/k3-j721e-main.dtsi
@@ -235,11 +235,14 @@
ti,trm-icp = <0x8>;
dma-coherent;
mmc-ddr-1_8v;
-   ti,otap-del-sel-legacy = <0x0>;
-   ti,otap-del-sel-mmc-hs = <0x0>;
+   ti,otap-del-sel-legacy = <0xf>;
+   ti,otap-del-sel-mmc-hs = <0xf>;
ti,otap-del-sel-ddr52 = <0x5>;
ti,otap-del-sel-hs200 = <0x6>;
ti,otap-del-sel-hs400 = <0x0>;
+   ti,itap-del-sel-legacy = <0x10>;
+   ti,itap-del-sel-mmc-hs = <0xa>;
+   ti,itap-del-sel-ddr52 = <0x3>;
};
 
main_sdhci1: sdhci@4fb {
@@ -256,7 +259,6 @@
ti,otap-del-sel-sdr12 = <0xf>;
ti,otap-del-sel-sdr25 = <0xf>;
ti,otap-del-sel-sdr50 = <0xc>;
-   ti,otap-del-sel-sdr104 = <0x5>;
ti,otap-del-sel-ddr50 = <0xc>;
ti,trm-icp = <0x8>;
dma-coherent;
-- 
2.17.1

[PATCH v3 11/20] arm: dts: k3-am65: Fix mmc nodes

[Aswath Govindraju]

From: Faiz Abbas 

Because of fundamental interface issues in am65x pg1, only the
initial sdhci1 node at 25 MHz was added in the u-boot.dtsi
from which both the base-board.dts and r5-base-board.dts
inherit the node. Move the node out to k3-am65-main.dtsi
where it belongs and add the board specific properties
in base-board.dts and r5-base-board.dts

This ensures dts compatibility with the kernel dts in the
base-board.dts and enables the SD card interface at 50 MHz
and High Speed mode

While we are here, also fix the main_mmc0_pins_default
property to be included and inherit from the base-board.dts
instead of the u-boot.dtsi

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 arch/arm/dts/k3-am65-main.dtsi   | 22 +++
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 67 +++-
 arch/arm/dts/k3-am654-base-board.dts | 25 
 arch/arm/dts/k3-am654-r5-base-board.dts  | 20 +-
 4 files changed, 74 insertions(+), 60 deletions(-)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi
index 028f57379b9f..d151e27028cd 100644
--- a/arch/arm/dts/k3-am65-main.dtsi
+++ b/arch/arm/dts/k3-am65-main.dtsi
@@ -113,6 +113,28 @@
dma-coherent;
};
 
+   sdhci1: sdhci@4fa {
+   compatible = "ti,am654-sdhci-5.1";
+   reg = <0x0 0x4fa 0x0 0x260>, <0x0 0x4fb 0x0 0x134>;
+   power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
+   clocks = <&k3_clks 48 0>, <&k3_clks 48 1>;
+   clock-names = "clk_ahb", "clk_xin";
+   interrupts = ;
+   ti,otap-del-sel-legacy = <0x0>;
+   ti,otap-del-sel-mmc-hs = <0x0>;
+   ti,otap-del-sel-sd-hs = <0x0>;
+   ti,otap-del-sel-sdr12 = <0x0>;
+   ti,otap-del-sel-sdr25 = <0x0>;
+   ti,otap-del-sel-sdr50 = <0x8>;
+   ti,otap-del-sel-sdr104 = <0x7>;
+   ti,otap-del-sel-ddr50 = <0x4>;
+   ti,otap-del-sel-ddr52 = <0x4>;
+   ti,otap-del-sel-hs200 = <0x7>;
+   ti,clkbuf-sel = <0x7>;
+   ti,trm-icp = <0x8>;
+   dma-coherent;
+   };
+
main_i2c0: i2c@200 {
compatible = "ti,am654-i2c", "ti,omap4-i2c";
reg = <0x0 0x200 0x0 0x100>;
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi 
b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
index 727bc3e8a0e3..b030d750f2a1 100644
--- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi
@@ -21,28 +21,6 @@
 
 &cbass_main{
u-boot,dm-spl;
-
-   sdhci1: sdhci@04FA {
-   compatible = "ti,am654-sdhci-5.1";
-   reg = <0x0 0x4FA 0x0 0x1000>,
- <0x0 0x4FB 0x0 0x400>;
-   clocks =<&k3_clks 48 0>, <&k3_clks 48 1>;
-   clock-names = "clk_ahb", "clk_xin";
-   power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
-   max-frequency = <2500>;
-   ti,otap-del-sel-legacy = <0x0>;
-   ti,otap-del-sel-mmc-hs = <0x0>;
-   ti,otap-del-sel-sd-hs = <0x0>;
-   ti,otap-del-sel-sdr12 = <0x0>;
-   ti,otap-del-sel-sdr25 = <0x0>;
-   ti,otap-del-sel-sdr50 = <0x8>;
-   ti,otap-del-sel-sdr104 = <0x7>;
-   ti,otap-del-sel-ddr50 = <0x4>;
-   ti,otap-del-sel-ddr52 = <0x4>;
-   ti,otap-del-sel-hs200 = <0x7>;
-   ti,trm-icp = <0x8>;
-   };
-
 };
 
 &cbass_mcu {
@@ -109,38 +87,6 @@
u-boot,dm-spl;
};
 
-   main_mmc0_pins_default: main_mmc0_pins_default {
-   pinctrl-single,pins = <
-   AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0)  /* 
(B25) MMC0_CLK */
-   AM65X_IOPAD(0x01aC, PIN_INPUT_PULLUP, 0)/* 
(B27) MMC0_CMD */
-   AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0)/* 
(A26) MMC0_DAT0 */
-   AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0)/* 
(E25) MMC0_DAT1 */
-   AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0)/* 
(C26) MMC0_DAT2 */
-   AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0)/* 
(A25) MMC0_DAT3 */
-   AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0)/* 
(E24) MMC0_DAT4 */
-   AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0)/* 
(A24) MMC0_DAT5 */
-   AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0)/* 
(B26) MMC0_DAT6 */
-   AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0)/* 
(D25) MMC0_DAT7 */
-   AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0)/* 
(A23) MMC0_SDCD */
-   AM65X_IOPAD(0x01b0, PIN_INPUT, 0)   /* 
(C25) MMC0_DS */
-   >;
-   u-boot,dm-spl;
-   };
-
-   main_mmc1_pins_default:

[PATCH v3 10/20] mmc: am654_sdhci: Use sdhci_set_control_reg()

[Aswath Govindraju]

From: Faiz Abbas 

Use the generic sdhci_set_control_reg() instead of duplicating
in platform driver.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 18 ++
 1 file changed, 2 insertions(+), 16 deletions(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 5dea3eb1be4e..11dcde134c5f 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -151,21 +151,6 @@ struct am654_driver_data {
u32 flags;
 };
 
-static void am654_sdhci_set_control_reg(struct sdhci_host *host)
-{
-   struct mmc *mmc = (struct mmc *)host->mmc;
-   u32 reg;
-
-   if (IS_SD(host->mmc) &&
-   mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
-   reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
-   reg |= SDHCI_CTRL_VDD_180;
-   sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
-   }
-
-   sdhci_set_uhs_timing(host);
-}
-
 static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
 unsigned int speed)
 {
@@ -433,7 +418,7 @@ const struct sdhci_ops am654_sdhci_ops = {
 #endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &am654_sdhci_set_ios_post,
-   .set_control_reg= &am654_sdhci_set_control_reg,
+   .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
 };
 
@@ -476,6 +461,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
 #endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &j721e_4bit_sdhci_set_ios_post,
+   .set_control_reg= sdhci_set_control_reg,
.write_b= am654_sdhci_write_b,
 };
 
-- 
2.17.1

[PATCH v3 09/20] mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modes

[Aswath Govindraju]

From: Faiz Abbas 

According to the AM654x Data Manual[1], the setup timing in lower speed
modes can only be met if the controller uses a falling edge data launch.

To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be
cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25
speed modes.

Use the sdhci writeb callback to implement this condition.

[1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/Kconfig   |  1 +
 drivers/mmc/am654_sdhci.c | 25 +++--
 2 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 14d79139864a..f8ea92172e44 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -526,6 +526,7 @@ config MMC_SDHCI_AM654
depends on MMC_SDHCI
depends on DM_MMC && OF_CONTROL && BLK
depends on REGMAP
+   select MMC_SDHCI_IO_ACCESSORS
help
  Support for Secure Digital Host Controller Interface (SDHCI)
  controllers present on TI's AM654 SOCs.
diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 9549420c6582..5dea3eb1be4e 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -369,6 +369,26 @@ static int am654_sdhci_deferred_probe(struct sdhci_host 
*host)
return sdhci_probe(dev);
 }
 
+static void am654_sdhci_write_b(struct sdhci_host *host, u8 val, int reg)
+{
+   if (reg == SDHCI_HOST_CONTROL) {
+   switch (host->mmc->selected_mode) {
+   /*
+* According to the data manual, HISPD bit
+* should not be set in these speed modes.
+*/
+   case SD_HS:
+   case MMC_HS:
+   case UHS_SDR12:
+   case UHS_SDR25:
+   val &= ~SDHCI_CTRL_HISPD;
+   default:
+   break;
+   }
+   }
+
+   writeb(val, host->ioaddr + reg);
+}
 #ifdef MMC_SUPPORTS_TUNING
 #define ITAP_MAX   32
 static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
@@ -414,6 +434,7 @@ const struct sdhci_ops am654_sdhci_ops = {
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &am654_sdhci_set_ios_post,
.set_control_reg= &am654_sdhci_set_control_reg,
+   .write_b= am654_sdhci_write_b,
 };
 
 const struct am654_driver_data am654_drv_data = {
@@ -455,6 +476,7 @@ const struct sdhci_ops j721e_4bit_sdhci_ops = {
 #endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &j721e_4bit_sdhci_set_ios_post,
+   .write_b= am654_sdhci_write_b,
 };
 
 const struct am654_driver_data j721e_4bit_drv_data = {
@@ -532,6 +554,7 @@ static int am654_sdhci_probe(struct udevice *dev)
host->max_clk = clock;
host->mmc = &plat->mmc;
host->mmc->dev = dev;
+   host->ops = drv_data->ops;
ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
  AM654_SDHCI_MIN_FREQ);
if (ret)
@@ -541,8 +564,6 @@ static int am654_sdhci_probe(struct udevice *dev)
if (ret)
return ret;
 
-   host->ops = drv_data->ops;
-
/* Update ops based on SoC revision */
soc = soc_device_match(am654_sdhci_soc_attr);
if (soc && soc->data) {
-- 
2.17.1

[PATCH v3 08/20] mmc: am654_sdhci: Add support for software tuning

[Aswath Govindraju]

From: Faiz Abbas 

With the new SW tuning App note[1], a custom tuning algorithm is
required for eMMC HS200, HS400 and SD card UHS modes. The algorithm
involves running through the 32 possible input tap delay values and
sending the appropriate tuning command (CMD19/21) for each of them
to get a fail or pass result for each of the values. Typically, the
range will have a small contiguous failing window. Considering the
tuning range as a circular buffer, the algorithm then sets a final
tuned value directly opposite to the failing window.

[1] https://www.ti.com/lit/pdf/spract9

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 45 +++
 1 file changed, 45 insertions(+)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index e86ef1a8b218..9549420c6582 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -9,6 +9,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -368,7 +369,48 @@ static int am654_sdhci_deferred_probe(struct sdhci_host 
*host)
return sdhci_probe(dev);
 }
 
+#ifdef MMC_SUPPORTS_TUNING
+#define ITAP_MAX   32
+static int am654_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
+{
+   struct udevice *dev = mmc->dev;
+   struct am654_sdhci_plat *plat = dev_get_plat(dev);
+   int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len;
+   u32 itap;
+
+   /* Enable ITAPDLY */
+   regmap_update_bits(plat->base, PHY_CTRL4, ITAPDLYENA_MASK,
+  1 << ITAPDLYENA_SHIFT);
+
+   for (itap = 0; itap < ITAP_MAX; itap++) {
+   am654_sdhci_write_itapdly(plat, itap);
+
+   cur_val = !mmc_send_tuning(mmc, opcode, NULL);
+   if (cur_val && !prev_val)
+   pass_window = itap;
+
+   if (!cur_val)
+   fail_len++;
+
+   prev_val = cur_val;
+   }
+   /*
+* Having determined the length of the failing window and start of
+* the passing window calculate the length of the passing window and
+* set the final value halfway through it considering the range as a
+* circular buffer
+*/
+   pass_len = ITAP_MAX - fail_len;
+   itap = (pass_window + (pass_len >> 1)) % ITAP_MAX;
+   am654_sdhci_write_itapdly(plat, itap);
+
+   return 0;
+}
+#endif
 const struct sdhci_ops am654_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+   .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &am654_sdhci_set_ios_post,
.set_control_reg= &am654_sdhci_set_control_reg,
@@ -408,6 +450,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host 
*host)
 }
 
 const struct sdhci_ops j721e_4bit_sdhci_ops = {
+#ifdef MMC_SUPPORTS_TUNING
+   .platform_execute_tuning = am654_sdhci_execute_tuning,
+#endif
.deferred_probe = am654_sdhci_deferred_probe,
.set_ios_post   = &j721e_4bit_sdhci_set_ios_post,
 };
-- 
2.17.1

[PATCH v3 06/20] mmc: am654_sdhci: Add support for input tap delay

[Aswath Govindraju]

From: Faiz Abbas 

DLL need only be enabled for speed modes and clock frequencies at or
above 50 MHz. For speed modes that don't enable the DLL, we need to
configure a static input delay value. This involves reading an optional
itap-del-sel-* value from the device tree and configuring it for the
appropriate speed mode.

Therefore, move all dll configurations to their own functions and gate it
with 50 MHz speed and a minimum mode. If both these conditions are not
satisfied then configure delay chain modes.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 241 +-
 1 file changed, 161 insertions(+), 80 deletions(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 5790fa3d0dbf..b82558254ebb 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -62,6 +62,16 @@
 #define CALDONE_MASK   BIT(CALDONE_SHIFT)
 #define RETRIM_SHIFT   17
 #define RETRIM_MASKBIT(RETRIM_SHIFT)
+#define SELDLYTXCLK_SHIFT  17
+#define SELDLYTXCLK_MASK   BIT(SELDLYTXCLK_SHIFT)
+#define SELDLYRXCLK_SHIFT  16
+#define SELDLYRXCLK_MASK   BIT(SELDLYRXCLK_SHIFT)
+#define ITAPDLYSEL_SHIFT   0
+#define ITAPDLYSEL_MASKGENMASK(4, 0)
+#define ITAPDLYENA_SHIFT   8
+#define ITAPDLYENA_MASKBIT(ITAPDLYENA_SHIFT)
+#define ITAPCHGWIN_SHIFT   9
+#define ITAPCHGWIN_MASKBIT(ITAPCHGWIN_SHIFT)
 
 #define DRIVER_STRENGTH_50_OHM 0x0
 #define DRIVER_STRENGTH_33_OHM 0x1
@@ -70,6 +80,7 @@
 #define DRIVER_STRENGTH_40_OHM 0x4
 
 #define AM654_SDHCI_MIN_FREQ   40
+#define CLOCK_TOO_SLOW_HZ  5000
 
 struct am654_sdhci_plat {
struct mmc_config cfg;
@@ -77,6 +88,7 @@ struct am654_sdhci_plat {
struct regmap *base;
bool non_removable;
u32 otap_del_sel[MMC_MODES_END];
+   u32 itap_del_sel[MMC_MODES_END];
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
@@ -89,22 +101,45 @@ struct am654_sdhci_plat {
 };
 
 struct timing_data {
-   const char *binding;
+   const char *otap_binding;
+   const char *itap_binding;
u32 capability;
 };
 
 static const struct timing_data td[] = {
-   [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
-   [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
-   [SD_HS]  = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
-   [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
-   [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
-   [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
-   [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
-   [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
-   [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
-   [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
-   [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
+   [MMC_LEGACY]= {"ti,otap-del-sel-legacy",
+  "ti,itap-del-sel-legacy",
+  0},
+   [MMC_HS]= {"ti,otap-del-sel-mmc-hs",
+  "ti,itap-del-sel-mms-hs",
+  MMC_CAP(MMC_HS)},
+   [SD_HS] = {"ti,otap-del-sel-sd-hs",
+  "ti,itap-del-sel-sd-hs",
+  MMC_CAP(SD_HS)},
+   [UHS_SDR12] = {"ti,otap-del-sel-sdr12",
+  "ti,itap-del-sel-sdr12",
+  MMC_CAP(UHS_SDR12)},
+   [UHS_SDR25] = {"ti,otap-del-sel-sdr25",
+  "ti,itap-del-sel-sdr25",
+  MMC_CAP(UHS_SDR25)},
+   [UHS_SDR50] = {"ti,otap-del-sel-sdr50",
+  NULL,
+  MMC_CAP(UHS_SDR50)},
+   [UHS_SDR104]= {"ti,otap-del-sel-sdr104",
+  NULL,
+  MMC_CAP(UHS_SDR104)},
+   [UHS_DDR50] = {"ti,otap-del-sel-ddr50",
+  NULL,
+  MMC_CAP(UHS_DDR50)},
+   [MMC_DDR_52]= {"ti,otap-del-sel-ddr52",
+  "ti,itap-del-sel-ddr52",
+  MMC_CAP(MMC_DDR_52)},
+   [MMC_HS_200]= {"ti,otap-del-sel-hs200",
+  NULL,
+  MMC_CAP(MMC_HS_200)},
+   [MMC_HS_400]= {"ti,otap-del-sel-hs400",
+  NULL,
+  MMC_CAP(MMC_HS_400)},
 };
 
 struct am654_driver_data {
@@ -127,12 +162,99 @@ static void am654_sdhci_set_control_reg(struct sdhci_host 
*host)
sdhci_set_uhs_timing(host);
 }
 
+static int am654_sdhci_setup_dll(struct am654_sdhci_plat *plat,
+unsigned int speed)
+{
+   int sel50, sel100, freqsel;
+   u32 mask, val;
+   int ret;
+
+   /* Disable delay chain mode */
+   regmap_update_bits(plat->base, PH

[PATCH v3 07/20] mmc: am654_sdhci: Add support for writing to clkbuf_sel

[Aswath Govindraju]

From: Faiz Abbas 

Add support for writing new clock buffer select property for both
the am654x and j721e 4 bit IPs

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index b82558254ebb..e86ef1a8b218 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -48,6 +48,8 @@
 #define SEL100_MASKBIT(SEL100_SHIFT)
 #define FREQSEL_SHIFT  8
 #define FREQSEL_MASK   GENMASK(10, 8)
+#define CLKBUFSEL_SHIFT0
+#define CLKBUFSEL_MASK GENMASK(2, 0)
 #define DLL_TRIM_ICP_SHIFT 4
 #define DLL_TRIM_ICP_MASK  GENMASK(7, 4)
 #define DR_TY_SHIFT20
@@ -92,6 +94,7 @@ struct am654_sdhci_plat {
u32 trm_icp;
u32 drv_strength;
u32 strb_sel;
+   u32 clkbuf_sel;
u32 flags;
 #define DLL_PRESENTBIT(0)
 #define IOMUX_PRESENT  BIT(1)
@@ -295,6 +298,9 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
am654_sdhci_setup_delay_chain(plat, mode);
}
 
+   regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+  plat->clkbuf_sel);
+
return 0;
 }
 
@@ -395,6 +401,9 @@ static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host 
*host)
val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
 
+   regmap_update_bits(plat->base, PHY_CTRL5, CLKBUFSEL_MASK,
+  plat->clkbuf_sel);
+
return 0;
 }
 
@@ -548,6 +557,8 @@ static int am654_sdhci_of_to_plat(struct udevice *dev)
}
}
 
+   dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
+
ret = mmc_of_parse(dev, cfg);
if (ret)
return ret;
-- 
2.17.1

[PATCH v3 05/20] mmc: am654_sdhci: Add support for AM65x SR2.0

[Aswath Govindraju]

From: Faiz Abbas 

Add Support for AM65x PG2.0. Use the SoC bus framework to fixup
the platform data and do DLL calibration if the revision is 1.0

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 30 ++
 1 file changed, 30 insertions(+)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 1e0654183811..5790fa3d0dbf 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -12,6 +12,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -292,6 +293,11 @@ const struct sdhci_ops am654_sdhci_ops = {
 };
 
 const struct am654_driver_data am654_drv_data = {
+   .ops = &am654_sdhci_ops,
+   .flags = DLL_PRESENT | IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT,
+};
+
+const struct am654_driver_data am654_sr1_drv_data = {
.ops = &am654_sdhci_ops,
.flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
 STRBSEL_4_BIT,
@@ -326,6 +332,11 @@ const struct am654_driver_data j721e_4bit_drv_data = {
.flags = IOMUX_PRESENT,
 };
 
+const struct soc_attr am654_sdhci_soc_attr[] = {
+   { .family = "AM65X", .revision = "SR1.0", .data = &am654_sr1_drv_data},
+   {/* sentinel */}
+};
+
 static int sdhci_am654_get_otap_delay(struct udevice *dev,
  struct mmc_config *cfg)
 {
@@ -365,6 +376,8 @@ static int am654_sdhci_probe(struct udevice *dev)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct sdhci_host *host = dev_get_priv(dev);
struct mmc_config *cfg = &plat->cfg;
+   const struct soc_attr *soc;
+   const struct am654_driver_data *soc_drv_data;
struct clk clk;
unsigned long clock;
int ret;
@@ -394,6 +407,14 @@ static int am654_sdhci_probe(struct udevice *dev)
return ret;
 
host->ops = drv_data->ops;
+
+   /* Update ops based on SoC revision */
+   soc = soc_device_match(am654_sdhci_soc_attr);
+   if (soc && soc->data) {
+   soc_drv_data = soc->data;
+   host->ops = soc_drv_data->ops;
+   }
+
host->mmc->priv = host;
upriv->mmc = host->mmc;
 
@@ -458,9 +479,18 @@ static int am654_sdhci_bind(struct udevice *dev)
struct am654_driver_data *drv_data =
(struct am654_driver_data *)dev_get_driver_data(dev);
struct am654_sdhci_plat *plat = dev_get_plat(dev);
+   const struct soc_attr *soc;
+   const struct am654_driver_data *soc_drv_data;
 
plat->flags = drv_data->flags;
 
+   /* Update flags based on SoC revision */
+   soc = soc_device_match(am654_sdhci_soc_attr);
+   if (soc && soc->data) {
+   soc_drv_data = soc->data;
+   plat->flags = soc_drv_data->flags;
+   }
+
return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 }
 
-- 
2.17.1

[PATCH v3 04/20] mmc: am654_sdhci: Add flag for PHY calibration

[Aswath Govindraju]

From: Faiz Abbas 

Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB
flag to indicate the same.

Also move the write of trm_icp and driver strength to the set_clock()
function to match the kernel configuration flow.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 26 ++
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index e0136dff9711..1e0654183811 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,6 +84,7 @@ struct am654_sdhci_plat {
 #define IOMUX_PRESENT  BIT(1)
 #define FREQSEL_2_BIT  BIT(2)
 #define STRBSEL_4_BIT  BIT(3)
+#define DLL_CALIB  BIT(4)
 };
 
 struct timing_data {
@@ -195,6 +196,15 @@ static int am654_sdhci_set_ios_post(struct sdhci_host 
*host)
   freqsel << FREQSEL_SHIFT);
}
 
+   /* Configure DLL TRIM */
+   mask = DLL_TRIM_ICP_MASK;
+   val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
+
+   /* Configure DLL driver strength */
+   mask |= DR_TY_MASK;
+   val |= plat->drv_strength << DR_TY_SHIFT;
+   regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
+
/* Enable DLL */
regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
   0x1 << ENDLL_SHIFT);
@@ -221,7 +231,7 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
 
-   if (plat->flags & DLL_PRESENT) {
+   if (plat->flags & DLL_CALIB) {
regmap_read(plat->base, PHY_STAT1, &val);
if (~val & CALDONE_MASK) {
/* Calibrate IO lines */
@@ -233,15 +243,6 @@ int am654_sdhci_init(struct am654_sdhci_plat *plat)
if (ret)
return ret;
}
-
-   /* Configure DLL TRIM */
-   mask = DLL_TRIM_ICP_MASK;
-   val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
-
-   /* Configure DLL driver strength */
-   mask |= DR_TY_MASK;
-   val |= plat->drv_strength << DR_TY_SHIFT;
-   regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
}
 
/* Enable pins by setting IO mux to 0 */
@@ -292,12 +293,13 @@ const struct sdhci_ops am654_sdhci_ops = {
 
 const struct am654_driver_data am654_drv_data = {
.ops = &am654_sdhci_ops,
-   .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
+   .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | DLL_CALIB |
+STRBSEL_4_BIT,
 };
 
 const struct am654_driver_data j721e_8bit_drv_data = {
.ops = &am654_sdhci_ops,
-   .flags = DLL_PRESENT,
+   .flags = DLL_PRESENT | DLL_CALIB,
 };
 
 static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
-- 
2.17.1

[PATCH v3 03/20] mmc: am654_sdhci: Convert flag fields to BIT macro

[Aswath Govindraju]

From: Faiz Abbas 

Convert the flags field defines to use the BIT() macro.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index 33f658fba719..e0136dff9711 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -80,10 +80,10 @@ struct am654_sdhci_plat {
u32 drv_strength;
u32 strb_sel;
u32 flags;
-#define DLL_PRESENT(1 << 0)
-#define IOMUX_PRESENT  (1 << 1)
-#define FREQSEL_2_BIT  (1 << 2)
-#define STRBSEL_4_BIT  (1 << 3)
+#define DLL_PRESENTBIT(0)
+#define IOMUX_PRESENT  BIT(1)
+#define FREQSEL_2_BIT  BIT(2)
+#define STRBSEL_4_BIT  BIT(3)
 };
 
 struct timing_data {
-- 
2.17.1

[PATCH v3 02/20] mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post()

[Aswath Govindraju]

From: Faiz Abbas 

There are some speed modes that work without switching the dll on.
Unconditionally switch off the DLL before setting clock frequency to
support this case. The software will automatically enable DLL for speed
modes that require it. This also means the dll_on priv data member is no
longer required.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/am654_sdhci.c | 10 +-
 1 file changed, 1 insertion(+), 9 deletions(-)

diff --git a/drivers/mmc/am654_sdhci.c b/drivers/mmc/am654_sdhci.c
index baa935e0d5b0..33f658fba719 100644
--- a/drivers/mmc/am654_sdhci.c
+++ b/drivers/mmc/am654_sdhci.c
@@ -84,7 +84,6 @@ struct am654_sdhci_plat {
 #define IOMUX_PRESENT  (1 << 1)
 #define FREQSEL_2_BIT  (1 << 2)
 #define STRBSEL_4_BIT  (1 << 3)
-   bool dll_on;
 };
 
 struct timing_data {
@@ -141,12 +140,7 @@ static int am654_sdhci_set_ios_post(struct sdhci_host 
*host)
val &= ~SDHCI_CLOCK_CARD_EN;
sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
 
-   /* power off phy */
-   if (plat->dll_on) {
-   regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
-
-   plat->dll_on = false;
-   }
+   regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
 
/* restart clock */
sdhci_set_clock(host->mmc, speed);
@@ -212,8 +206,6 @@ static int am654_sdhci_set_ios_post(struct sdhci_host *host)
 val & DLLRDY_MASK, 1000, 100);
if (ret)
return ret;
-
-   plat->dll_on = true;
}
 
return 0;
-- 
2.17.1

[PATCH v3 01/20] mmc: sdhci: Add helper functions for UHS modes

[Aswath Govindraju]

From: Faiz Abbas 

Add a set_voltage() function which handles the switch from 3.3V to 1.8V
for SD card UHS modes.

Signed-off-by: Faiz Abbas 
Signed-off-by: Aswath Govindraju 
---
 drivers/mmc/sdhci.c | 80 +
 include/sdhci.h |  1 +
 2 files changed, 81 insertions(+)

diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 06289343124e..e7e3e22d1a7e 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -20,6 +20,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static void sdhci_reset(struct sdhci_host *host, u8 mask)
 {
@@ -509,6 +510,85 @@ void sdhci_set_uhs_timing(struct sdhci_host *host)
sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
 }
 
+#if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
+static void sdhci_set_voltage(struct sdhci_host *host)
+{
+   struct mmc *mmc = (struct mmc *)host->mmc;
+   u32 ctrl;
+   int ret;
+
+   ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+   switch (mmc->signal_voltage) {
+   case MMC_SIGNAL_VOLTAGE_330:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   if (mmc->vqmmc_supply) {
+   ret = regulator_set_enable(mmc->vqmmc_supply, false);
+   if (ret) {
+   pr_err("failed to disable vqmmc-supply: %d\n", 
ret);
+   return;
+   }
+
+   ret = regulator_set_value(mmc->vqmmc_supply, 330);
+   if (ret) {
+   pr_err("failed to set vqmmc-voltage to 3.3V: 
%d\n", ret);
+   return;
+   }
+
+   ret = regulator_set_enable(mmc->vqmmc_supply, true);
+   if (ret) {
+   pr_err("failed to enable vqmmc-supply: %d\n", 
ret);
+   return;
+   }
+   }
+#endif
+   mdelay(5);
+   if (IS_SD(mmc)) {
+   ctrl &= ~SDHCI_CTRL_VDD_180;
+   sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+   }
+   break;
+   case MMC_SIGNAL_VOLTAGE_180:
+#if CONFIG_IS_ENABLED(DM_REGULATOR)
+   if (mmc->vqmmc_supply) {
+   regulator_set_enable(mmc->vqmmc_supply, false);
+   if (ret) {
+   pr_err("failed to disable vqmmc-supply: %d\n", 
ret);
+   return;
+   }
+
+   regulator_set_value(mmc->vqmmc_supply, 180);
+   if (ret) {
+   pr_err("failed to set vqmmc-voltage to 1.8V: 
%d\n", ret);
+   return;
+   }
+
+   regulator_set_enable(mmc->vqmmc_supply, true);
+   if (ret) {
+   pr_err("failed to enable vqmmc-supply: %d\n", 
ret);
+   return;
+   }
+   }
+#endif
+   if (IS_SD(mmc)) {
+   ctrl |= SDHCI_CTRL_VDD_180;
+   sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+   }
+   break;
+   default:
+   /* No signal voltage switch required */
+   return;
+   }
+}
+#else
+static void sdhci_set_voltage(struct sdhci_host *host) { }
+#endif
+void sdhci_set_control_reg(struct sdhci_host *host)
+{
+   sdhci_set_voltage(host);
+   sdhci_set_uhs_timing(host);
+}
+
 #ifdef CONFIG_DM_MMC
 static int sdhci_set_ios(struct udevice *dev)
 {
diff --git a/include/sdhci.h b/include/sdhci.h
index 3e5a64981857..0f820c6d2669 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -491,6 +491,7 @@ void sdhci_set_uhs_timing(struct sdhci_host *host);
 /* Export the operations to drivers */
 int sdhci_probe(struct udevice *dev);
 int sdhci_set_clock(struct mmc *mmc, unsigned int clock);
+void sdhci_set_control_reg(struct sdhci_host *host);
 extern const struct dm_mmc_ops sdhci_ops;
 #else
 #endif
-- 
2.17.1

[PATCH v3 00/20] Add support for MMC higher speed modes for TI's am65x, j721e and j7200 platforms

[Aswath Govindraju]

The following patches add support for higher speeds in the SD card and
eMMC for TI's am65x, j721e, j7200 platforms.

With these patches, the following max speeds are supported:
j721e: DDR50, HS200
j7200: SDR104, HS200
am65x: SDR104*, HS200


changes since v2:
1. Added print statements in case of failure for regulator_set_enable and
   regulator_set_value function calls in patch 1
2. Removed patch 18 (in v2) as it has been applied by commit [1]
3. renamed the function  dev_get_platdata() to dev_get_plat in patch 8
4. rebased all the patches in series

changes since v1:
1. Added patches to support UHS modes for the SD card even in am654x
   platforms.
2. Fixed an issue with patch 1 that was breaking builds on some platforms.

* There's an issue with the am65x base board such that the power cycle
circuit to the card takes way longer than the wait time in mmc core.  Until
this is fixed, am654x-evm and -idk will only support High speed mode at
3.3V (see patch 20) but this shouldn't block us from adding UHS modes in
the dtsi as well as in the configs so other boards can still take advantage
of the higher speed. UHS modes have been tested by adding the appropriate
delay in the power cycle circuit.

[1] - commit 67507e4aab5b ("sandbox: Fix up building for of-platdata")

Link to v1:
https://patchwork.ozlabs.org/project/uboot/list/?series=206622


Faiz Abbas (20):
  mmc: sdhci: Add helper functions for UHS modes
  mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of
ios_post()
  mmc: am654_sdhci: Convert flag fields to BIT macro
  mmc: am654_sdhci: Add flag for PHY calibration
  mmc: am654_sdhci: Add support for AM65x SR2.0
  mmc: am654_sdhci: Add support for input tap delay
  mmc: am654_sdhci: Add support for writing to clkbuf_sel
  mmc: am654_sdhci: Add support for software tuning
  mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed
modes
  mmc: am654_sdhci: Use sdhci_set_control_reg()
  arm: dts: k3-am65: Fix mmc nodes
  arm: dts: k3-j721e-main: Update otap-delay values
  arm: dts: k3-j721e-common-proc-board: Add support for UHS modes for SD
card
  arm: dts: k3-j7200-main: Add support for gpio0
  arm: dts: k3-j7200-common-proc-board: Enable support for UHS modes
  configs: j721e_evm: Add support for UHS modes
  configs: j7200_evm: Add support for UHS modes
  arm: dts: k3-am65-main: Add itapdly and clkbuf-sel values
  arm: dts: k3-am654-base-board: Limit Sd card to High speed modes
  configs: am65x_evm: Add configs for UHS modes

 arch/arm/dts/k3-am65-main.dtsi|  31 ++
 arch/arm/dts/k3-am654-base-board-u-boot.dtsi  |  67 +--
 arch/arm/dts/k3-am654-base-board.dts  |  26 ++
 arch/arm/dts/k3-am654-r5-base-board.dts   |  20 +-
 arch/arm/dts/k3-j7200-common-proc-board.dts   |  49 ++-
 arch/arm/dts/k3-j7200-main.dtsi   |  23 ++
 .../arm/dts/k3-j7200-r5-common-proc-board.dts |  15 +
 arch/arm/dts/k3-j721e-common-proc-board.dts   |  32 ++
 arch/arm/dts/k3-j721e-main.dtsi   |   8 +-
 configs/am65x_evm_a53_defconfig   |   8 +
 configs/am65x_evm_r5_defconfig|   2 +
 configs/j7200_evm_a72_defconfig   |   8 +
 configs/j7200_evm_r5_defconfig|   1 +
 configs/j721e_evm_a72_defconfig   |   8 +
 configs/j721e_evm_r5_defconfig|   1 +
 drivers/mmc/Kconfig   |   1 +
 drivers/mmc/am654_sdhci.c | 384 +-
 drivers/mmc/sdhci.c   |  80 
 include/sdhci.h   |   1 +
 19 files changed, 592 insertions(+), 173 deletions(-)

-- 
2.17.1

[PATCH v2 3/3] PowerPC: keymile: Add support for kmcent2 board

[Niel Fourie]

Add basic support for the Hitachi Power Grids kmcent2 board, based
on the NXP QorIQ T1040 SoC.

Signed-off-by: Valentin Longchamp 
Signed-off-by: Rainer Boschung 
Signed-off-by: Niel Fourie 
Cc: Holger Brunck 
Cc: Heiko Schocher 
Cc: Priyanka Jain 
Cc: Stefan Roese 
---
Changes in v2:
- Sorted header includes as far as possible
- Removed all  includes
- Fixed block comment formatting
- Removed unnecessary #ifdefs
- Used if with IS_ENABLED() instead of #ifdefs where possible
- Moved MTDPARTS_DEFAULT/MTDIDS_DEFAULT to defconfig
- Fixed misc other formatting issues

 arch/powerpc/cpu/mpc85xx/Kconfig |   4 +
 arch/powerpc/dts/Makefile|   1 +
 arch/powerpc/dts/kmcent2-u-boot.dtsi |  97 +
 board/keymile/Kconfig|   1 +
 board/keymile/common/ivm.c   |   5 +
 board/keymile/kmcent2/Kconfig|  17 +
 board/keymile/kmcent2/MAINTAINERS|   8 +
 board/keymile/kmcent2/Makefile   |  15 +
 board/keymile/kmcent2/ddr.c  |  88 +
 board/keymile/kmcent2/kmcent2.c  | 353 ++
 board/keymile/kmcent2/law.c  |  24 ++
 board/keymile/kmcent2/tlb.c  | 104 ++
 configs/kmcent2_defconfig|  92 +
 include/configs/kmcent2.h| 513 +++
 14 files changed, 1322 insertions(+)
 create mode 100644 arch/powerpc/dts/kmcent2-u-boot.dtsi
 create mode 100644 board/keymile/kmcent2/Kconfig
 create mode 100644 board/keymile/kmcent2/MAINTAINERS
 create mode 100644 board/keymile/kmcent2/Makefile
 create mode 100644 board/keymile/kmcent2/ddr.c
 create mode 100644 board/keymile/kmcent2/kmcent2.c
 create mode 100644 board/keymile/kmcent2/law.c
 create mode 100644 board/keymile/kmcent2/tlb.c
 create mode 100644 configs/kmcent2_defconfig
 create mode 100644 include/configs/kmcent2.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 54c7fd9522..c1a3770671 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -256,6 +256,10 @@ config TARGET_KMP204X
bool "Support kmp204x"
select VENDOR_KM
 
+config TARGET_KMCENT2
+   bool "Support kmcent2"
+   select VENDOR_KM
+
 config TARGET_XPEDITE520X
bool "Support xpedite520x"
select ARCH_MPC8548
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 266d345f72..3ecda36538 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 
+dtb-$(CONFIG_TARGET_KMCENT2) += kmcent2.dtb
 dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb
 dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb
 dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb
diff --git a/arch/powerpc/dts/kmcent2-u-boot.dtsi 
b/arch/powerpc/dts/kmcent2-u-boot.dtsi
new file mode 100644
index 00..ab76a9f122
--- /dev/null
+++ b/arch/powerpc/dts/kmcent2-u-boot.dtsi
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * (C) Copyright 2021  Niel Fourie 
+ */
+
+#include 
+
+/ {
+
+   aliases {
+   spi0 = "/soc@ffe00/spi@11";
+   i2c0 = "/soc@ffe00/i2c@118000";
+   i2c1 = "/soc@ffe00/i2c@118000/mux@70/i2c@0";
+   i2c2 = "/soc@ffe00/i2c@118000/mux@70/i2c@1";
+   i2c3 = "/soc@ffe00/i2c@118000/mux@70/i2c@7";
+   i2c4 = "/soc@ffe00/i2c@118100";
+   /delete-property/ pci1;
+   /delete-property/ pci2;
+   /delete-property/ pci3;
+   };
+
+   chosen {
+   stdout-path = "/soc@ffe00/serial@11c500";
+   };
+
+   soc@ffe00 {
+   u-boot,dm-pre-reloc;
+   spi@11 {
+   /* This documents where km_fpgacfg should be appear */
+   fpga@0 {
+   compatible = "keymile,fpga-conf";
+   reg = <0>;
+   spi-max-frequency = <2500>;
+   };
+   };
+
+   sdhc@114000 {
+   status = "okay";
+   };
+
+   i2c@118000 {
+   u-boot,dm-pre-reloc;
+   mux@70 {
+   i2c@1 { /* IVM bus */
+   reg = <1>;
+   #address-cells = <1>;
+   #size-cells = <0>;
+   };
+   };
+   };
+
+   serial@11c500 {
+   u-boot,dm-pre-reloc;
+   clock-frequency = <2>;
+   };
+
+   fman@40 {
+   ethernet@e {
+   phy-connection-type = "sgmii";
+   };
+
+   ethernet@e2000 {
+   phy-connection-type = "sgmii";
+   };
+
+ 

[PATCH v2 2/3] keymile: common: update to set_env_hex(), fix "pram" radix

[Niel Fourie]

Replace instances of sprintf()/set_env() for setting hexadecimal
values with set_env_hex().

In set_km_env() the "pram" variable was set to an hexadecimal
value, while initr_mem() expects an unsigned decimal, so use
set_env_ulong() instead.

Signed-off-by: Niel Fourie 
Cc: Holger Brunck 
Cc: Heiko Schocher 
Cc: Priyanka Jain 
Cc: Stefan Roese 
---
Changes in v2:
- Replaced all relevant sprintf()/set_env() instances with
  set_env_hex()/set_env_ulong(), instead of only correcting
  the sprintf() formatting for "pram" radix to "%ul"

 board/keymile/common/common.c | 22 ++
 1 file changed, 6 insertions(+), 16 deletions(-)

diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index df507e2790..71af1751ef 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 int set_km_env(void)
 {
-   uchar buf[32];
unsigned int pnvramaddr;
unsigned int pram;
unsigned int varaddr;
@@ -51,8 +50,7 @@ int set_km_env(void)
 
pnvramaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM
- CONFIG_KM_PNVRAM;
-   sprintf((char *)buf, "0x%x", pnvramaddr);
-   env_set("pnvramaddr", (char *)buf);
+   env_set_hex("pnvramaddr", pnvramaddr);
 
/* try to read rootfssize (ram image) from environment */
p = env_get("rootfssize");
@@ -60,16 +58,13 @@ int set_km_env(void)
strict_strtoul(p, 16, &rootfssize);
pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
CONFIG_KM_PNVRAM) / 0x400;
-   sprintf((char *)buf, "0x%x", pram);
-   env_set("pram", (char *)buf);
+   env_set_ulong("pram", pram);
 
varaddr = gd->ram_size - CONFIG_KM_RESERVED_PRAM - CONFIG_KM_PHRAM;
-   sprintf((char *)buf, "0x%x", varaddr);
-   env_set("varaddr", (char *)buf);
+   env_set_hex("varaddr", varaddr);
 
kernelmem = gd->ram_size - 0x400 * pram;
-   sprintf((char *)buf, "0x%x", kernelmem);
-   env_set("kernelmem", (char *)buf);
+   env_set_hex("kernelmem", kernelmem);
 
return 0;
 }
@@ -243,7 +238,6 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int 
flag, int argc,
p = env_get("hwkey");
if (p)
rc = strict_strtoul(p, 16, &envhwkey);
-
if (rc != 0) {
printf("strict_strtoul returns error: %d", rc);
return rc;
@@ -305,15 +299,11 @@ static int do_checkboardidhwk(struct cmd_tbl *cmdtp, int 
flag, int argc,
 * set the values in environment variables.
 */
if (bid == ivmbid && hwkey == ivmhwkey) {
-   char buf[10];
-
found = 1;
envbid   = bid;
envhwkey = hwkey;
-   sprintf(buf, "%lx", bid);
-   env_set("boardid", buf);
-   sprintf(buf, "%lx", hwkey);
-   env_set("hwkey", buf);
+   env_set_hex("boardid", bid);
+   env_set_hex("hwkey", hwkey);
}
} /* end while( ! found ) */
}
-- 
2.29.2

[PATCH v2 1/3] PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10

[Niel Fourie]

Pulled in the kmcent2.dts and all its dependents from Linux 5.10,
commit 2c85ebc57b3e upstream. Replaced the license text with
SPDX License Identifiers.

Signed-off-by: Niel Fourie 
Reviewed-by: Stefan Roese 
Cc: Holger Brunck 
Cc: Heiko Schocher 
Cc: Priyanka Jain 
Cc: Stefan Roese 
---
Changes in v2:
- Reviewed by Stefan Roese 

 arch/powerpc/dts/elo3-dma-0.dtsi   |  55 ++
 arch/powerpc/dts/elo3-dma-1.dtsi   |  55 ++
 arch/powerpc/dts/kmcent2.dts   | 338 
 arch/powerpc/dts/qoriq-bman1.dtsi  |  14 +
 arch/powerpc/dts/qoriq-duart-0.dtsi|  24 +
 arch/powerpc/dts/qoriq-duart-1.dtsi|  24 +
 arch/powerpc/dts/qoriq-esdhc-0.dtsi|  13 +
 arch/powerpc/dts/qoriq-espi-0.dtsi |  14 +
 arch/powerpc/dts/qoriq-mpic.dtsi   |  79 +++
 arch/powerpc/dts/qoriq-qman3.dtsi  |  14 +
 arch/powerpc/dts/qoriq-sata2-0.dtsi|  12 +
 arch/powerpc/dts/qoriq-sata2-1.dtsi|  12 +
 arch/powerpc/dts/qoriq-sec5.0-0.dtsi   |  83 +++
 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi  |  14 +
 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi |  14 +
 arch/powerpc/dts/t1040si-post.dtsi | 727 +
 arch/powerpc/dts/t104xsi-pre.dtsi  |  88 +++
 17 files changed, 1580 insertions(+)
 create mode 100644 arch/powerpc/dts/elo3-dma-0.dtsi
 create mode 100644 arch/powerpc/dts/elo3-dma-1.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2.dts
 create mode 100644 arch/powerpc/dts/qoriq-bman1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-esdhc-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-espi-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-mpic.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-qman3.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sec5.0-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
 create mode 100644 arch/powerpc/dts/t1040si-post.dtsi
 create mode 100644 arch/powerpc/dts/t104xsi-pre.dtsi

diff --git a/arch/powerpc/dts/elo3-dma-0.dtsi b/arch/powerpc/dts/elo3-dma-0.dtsi
new file mode 100644
index 00..c3f7737256
--- /dev/null
+++ b/arch/powerpc/dts/elo3-dma-0.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x10 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma0: dma@100300 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "fsl,elo3-dma";
+   reg = <0x100300 0x4>,
+ <0x100600 0x4>;
+   ranges = <0x0 0x100100 0x500>;
+   dma-channel@0 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x0 0x80>;
+   interrupts = <28 2 0 0>;
+   };
+   dma-channel@80 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x80 0x80>;
+   interrupts = <29 2 0 0>;
+   };
+   dma-channel@100 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x100 0x80>;
+   interrupts = <30 2 0 0>;
+   };
+   dma-channel@180 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x180 0x80>;
+   interrupts = <31 2 0 0>;
+   };
+   dma-channel@300 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x300 0x80>;
+   interrupts = <76 2 0 0>;
+   };
+   dma-channel@380 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x380 0x80>;
+   interrupts = <77 2 0 0>;
+   };
+   dma-channel@400 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x400 0x80>;
+   interrupts = <78 2 0 0>;
+   };
+   dma-channel@480 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x480 0x80>;
+   interrupts = <79 2 0 0>;
+   };
+};
diff --git a/arch/powerpc/dts/elo3-dma-1.dtsi b/arch/powerpc/dts/elo3-dma-1.dtsi
new file mode 100644
index 00..a61c88649c
--- /dev/null
+++ b/arch/powerpc/dts/elo3-dma-1.dtsi
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * QorIQ Elo3 DMA device tree stub [ controller @ offset 0x101000 ]
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ */
+
+dma1: dma@101300 {
+   #address-cells = <1>;
+   #size-cells = <1>;
+   compatible = "fsl,elo3-dma";
+   reg = <0x101300 0x4>,
+ <0x101600 0x4>;
+   ranges = <0x0 0x101100 0x500>;
+   dma-channel@0 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x0 0x80>;
+   interrupts = <32 2 0 0>;
+   };
+   dma-channel@80 {
+   compatible = "fsl,eloplus-dma-channel";
+   reg = <0x80 0x80>;
+ 

[PATCH v2 0/3] PowerPC: keymile: Add support for kmcent2 board

[Niel Fourie]

This patch series adds basic support for the Hitachi Power Grids
(previously Keymile and ABB) kmcent2 board, based on the NXP QorIQ
T1040 SoC.

Patch 1/3 pulls in the device trees from Linux 5.10
Patch 2/3 fixes a minor bug common to all the Keymile boards.
Patch 3/3 finally adds the U-boot support for the kmcent2

Changes in v2:
- DTs pulled in from Linux reviewed
- In common.c, use set_env_hex()/set_env_ulong()
- Sort header includes, remove  includes
- Removed unnecessary #ifdefs
- Moved MTDPARTS_DEFAULT/MTDIDS_DEFAULT to defconfig

Niel Fourie (3):
  PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10
  keymile: common: update to set_env_hex(), fix "pram" radix
  PowerPC: keymile: Add support for kmcent2 board

 arch/powerpc/cpu/mpc85xx/Kconfig   |   4 +
 arch/powerpc/dts/Makefile  |   1 +
 arch/powerpc/dts/elo3-dma-0.dtsi   |  55 ++
 arch/powerpc/dts/elo3-dma-1.dtsi   |  55 ++
 arch/powerpc/dts/kmcent2-u-boot.dtsi   |  97 
 arch/powerpc/dts/kmcent2.dts   | 338 
 arch/powerpc/dts/qoriq-bman1.dtsi  |  14 +
 arch/powerpc/dts/qoriq-duart-0.dtsi|  24 +
 arch/powerpc/dts/qoriq-duart-1.dtsi|  24 +
 arch/powerpc/dts/qoriq-esdhc-0.dtsi|  13 +
 arch/powerpc/dts/qoriq-espi-0.dtsi |  14 +
 arch/powerpc/dts/qoriq-mpic.dtsi   |  79 +++
 arch/powerpc/dts/qoriq-qman3.dtsi  |  14 +
 arch/powerpc/dts/qoriq-sata2-0.dtsi|  12 +
 arch/powerpc/dts/qoriq-sata2-1.dtsi|  12 +
 arch/powerpc/dts/qoriq-sec5.0-0.dtsi   |  83 +++
 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi  |  14 +
 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi |  14 +
 arch/powerpc/dts/t1040si-post.dtsi | 727 +
 arch/powerpc/dts/t104xsi-pre.dtsi  |  88 +++
 board/keymile/Kconfig  |   1 +
 board/keymile/common/common.c  |  22 +-
 board/keymile/common/ivm.c |   5 +
 board/keymile/kmcent2/Kconfig  |  17 +
 board/keymile/kmcent2/MAINTAINERS  |   8 +
 board/keymile/kmcent2/Makefile |  15 +
 board/keymile/kmcent2/ddr.c|  88 +++
 board/keymile/kmcent2/kmcent2.c| 353 
 board/keymile/kmcent2/law.c|  24 +
 board/keymile/kmcent2/tlb.c| 104 
 configs/kmcent2_defconfig  |  92 
 include/configs/kmcent2.h  | 513 +
 32 files changed, 2908 insertions(+), 16 deletions(-)
 create mode 100644 arch/powerpc/dts/elo3-dma-0.dtsi
 create mode 100644 arch/powerpc/dts/elo3-dma-1.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2-u-boot.dtsi
 create mode 100644 arch/powerpc/dts/kmcent2.dts
 create mode 100644 arch/powerpc/dts/qoriq-bman1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-duart-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-esdhc-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-espi-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-mpic.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-qman3.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sata2-1.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-sec5.0-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-dr-0.dtsi
 create mode 100644 arch/powerpc/dts/qoriq-usb2-mph-0.dtsi
 create mode 100644 arch/powerpc/dts/t1040si-post.dtsi
 create mode 100644 arch/powerpc/dts/t104xsi-pre.dtsi
 create mode 100644 board/keymile/kmcent2/Kconfig
 create mode 100644 board/keymile/kmcent2/MAINTAINERS
 create mode 100644 board/keymile/kmcent2/Makefile
 create mode 100644 board/keymile/kmcent2/ddr.c
 create mode 100644 board/keymile/kmcent2/kmcent2.c
 create mode 100644 board/keymile/kmcent2/law.c
 create mode 100644 board/keymile/kmcent2/tlb.c
 create mode 100644 configs/kmcent2_defconfig
 create mode 100644 include/configs/kmcent2.h

-- 
2.29.2

Re: [PATCH 3/3] PowerPC: keymile: Add support for kmcent2 board

[Niel Fourie]

Hi Stefan

On 19/01/2021 16:31, Stefan Roese wrote:




diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c
index 60b89fe348..608406dacd 100644
--- a/board/keymile/common/ivm.c
+++ b/board/keymile/common/ivm.c
@@ -321,6 +321,11 @@ static int ivm_populate_env(unsigned char *buf, 
int len, int mac_address_offset)

  process_mac(valbuf, page2, mac_address_offset, true);
  env_set((char *)"eth1addr", (char *)valbuf);
  #endif
+#if defined(CONFIG_TARGET_KMCENT2)


Can't you switch to using if (IS_ENABLED(CONFIG_TARGET_KMCENT2)) instead
adding more #ifdef's to this code?


Makes sense, changed that.




+/* 3rd ethernet interface */
+    process_mac(valbuf, page2, 2, true);
+    env_set((char *)"eth4addr", (char *)valbuf);
+#endif


eth_env_set_enetaddr() ?


This one is tricky, as process_mac() already formatted the mac address 
as a string (using the "%pM" format string) already, while 
eth_env_set_enetaddr() again applies the "%pM" format string to its input.


There are three other instances of the process_mac()/env_set() as above 
in this file, which would need to be changed along with process_mac() 
itself (to not apply "%pM"), so that eth_env_set_enetaddr() can be used. 
Should I do this for all the cases?





diff --git a/board/keymile/kmcent2/ddr.c b/board/keymile/kmcent2/ddr.c
new file mode 100644
index 00..2b4e58795a
--- /dev/null
+++ b/board/keymile/kmcent2/ddr.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung 
+ *
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ */
+
+#include 


Please don't include common.h any more. Simon has worked hard to move
things out of common.h so that it should not be used any more.


Thanks, I did not know of this, will apply everywhere.


+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 


Sort header includes?


Thanks, will apply everywhere. I hit a couple of snags, though. Above,
fsl_ddr_dimm_params.h depends on generic_spd_eeprom_t defined in 
fsl_ddr_sdram.h, so I kept those two in that order.


Also in law.c, asm/fsl_law.h need config.h before it to compile.


+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DQSn_POS(n)    (3 - (((n) - 1) % 4)) * 8
+#define DQSn_START(n, start)    ((start) << DQSn_POS(n))


Empty line please.


Fixed



diff --git a/board/keymile/kmcent2/kmcent2.c 
b/board/keymile/kmcent2/kmcent2.c

new file mode 100644
index 00..3d6bd8328e
--- /dev/null
+++ b/board/keymile/kmcent2/kmcent2.c




Nitpicking: The official coding style for multi line comment is this:

 /*
  * CFE_RST (front phy):
  * reset at power-up, unit and core reset, deasset reset w/o WD
  */

Please consistant in this file.


Thanks, fixed everywhere.




+#if defined(CONFIG_HUSH_INIT_VAR)
+int hush_init_var(void)
+{
+    ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
+    return 0;
+}
+#endif


Is hush disabled in any case? If not, remove the #ifdef please.


+
+#if defined(CONFIG_LAST_STAGE_INIT)


Again, is CONFIG_LAST_STAGE_INIT ever disabled?


Good point, thanks. I removed the #ifdefs for CONFIG_LAST_STAGE_INIT, 
CONFIG_LAST_STAGE_INIT, CONFIG_SYS_DPAA_FMAN and CONFIG_POST.





diff --git a/board/keymile/kmcent2/tlb.c b/board/keymile/kmcent2/tlb.c
new file mode 100644
index 00..8a726fbd17
--- /dev/null
+++ b/board/keymile/kmcent2/tlb.c
@@ -0,0 +1,120 @@





+#if defined(CONFIG_SYS_MRAM_BASE)
+    SET_TLB_ENTRY(1, CONFIG_SYS_MRAM_BASE, SYS_MRAM_BASE_PHYS,
+  MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+  0, 12, BOOKE_PAGESZ_128M, 1),
+#endif
+    /* BFTIC */
+#if defined(SYS_BFTIC_BASE)


Really? "SYS_BFTIC_BASE" or "CONFIG_SYS_BFTIC_BASE" ?


Well spotted! It turns out SYS_BFTIC_BASE, as CONFIG_SYS_BFTIC_BASE is 
not in config_whitelist.txt, and renaming it was the compromise. The 
code originally predates the disallowing of ad-hoc CONFIGs... I hope 
this is okay?



And here as well, if some of these defines are always set or never,
please remove the #ifdef's or the complete block if never set.


Thanks. Applied this to tlb.c and law.c.


+    SET_TLB_ENTRY(1, SYS_BFTIC_BASE, SYS_BFTIC_BASE_PHYS,
+  MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+  0, 13, BOOKE_PAGESZ_128M, 1),
+#endif





diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
new file mode 100644
index 00..a0f3a09057
--- /dev/null
+++ b/include/configs/kmcent2.h
@@ -0,0 +1,537 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2016 Keymile AG
+ * Rainer Boschung 
+ *
+ */
+
+#ifndef __KMCENT2_H
+#define __KMCENT2_H
+
+#define CONFIG_HOSTNAME    "kmcent2"
+#define KM_BOARD_NAME    CONFIG_HOSTNAME
+
+#define CONFIG_KM_UBI_PARTITION_NAME_BOOT    "ubi0"
+#define CONFIG_KM_UBI_PARTITION_NAME_APP    "ubi1"
+#define MTDIDS_DEFAULT    "nor0=fe800.nor,nand0=ffa00.flash"
+
+#define MTDPARTS_DEFAULT    "mtdparts="    \
+    "fe800.nor:"

Re: [PATCH 2/3] keymile: common: Fix pram variable radix

[Niel Fourie]

Hi Stefan

On 19/01/2021 16:13, Stefan Roese wrote:

Hi Niel,

On 08.01.21 11:53, Niel Fourie wrote:

In set_km_env() the pram variable was set to an hexadecimal value,
while initr_mem() expects an unsigned decimal. Set the pram variable
to an unsigned decimal instead.

Signed-off-by: Niel Fourie 
Cc: Holger Brunck 
Cc: Heiko Schocher 
Cc: Priyanka Jain 
---
  board/keymile/common/common.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board/keymile/common/common.c 
b/board/keymile/common/common.c

index 03c7ce9da7..106787efd5 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -60,7 +60,7 @@ int set_km_env(void)
  strict_strtoul(p, 16, &rootfssize);
  pram = (rootfssize + CONFIG_KM_RESERVED_PRAM + CONFIG_KM_PHRAM +
  CONFIG_KM_PNVRAM) / 0x400;
-    sprintf((char *)buf, "0x%x", pram);
+    sprintf((char *)buf, "%u", pram);
  env_set("pram", (char *)buf);


Why don't you switch to using a different env_set_foo() API instead?
Like env_set_ulong() in this case? Or env_set_hex() in the HEX case.
This could also be done for some other env_set cases in this file as
well to reduce code size and complexity.


Thank you for the suggestion, I realised I was simply trying to change 
as little as possible.


I replaced all instances of sprintf()/env_set() for numerical values in 
this file to env_set_hex()/env_set_ulong() instead.


I also considered use env_get_hex() where applicable, but it uses 
simple_strtoul() instead of strict_strtoul(), therefore changing the 
behaviour, so I left it as-is instead.


Best regards,
Niel Fourie

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lu...@denx.de

Re: [PATCH 1/3] PowerPC: dts: Pulled in kmcent2 dts files from Linux 5.10

[Niel Fourie]

Hi Stefan,

On 19/01/2021 16:06, Stefan Roese wrote:

Hi Niel,

On 08.01.21 11:53, Niel Fourie wrote:

Pulled in the kmcent2.dts and all its dependents from Linux 5.10,
commit 2c85ebc57b3e upstream. Replaced the license text with
SPDX License Identifiers.


I assume that you did not change the license itself (e.g. change MIT to
GPL etc) but only moved from non SPDX to SPDX indentifiers?


Yes, the licenses themselves were not changed, just replaced with SPDX 
identifiers.


I would suggest to also submit these changes to the Linux kernel (if
not done already). So that the files are identical in the next release
revision.

Is no license is changed:

Reviewed-by: Stefan Roese 


Thanks!



Best regards,
Niel Fourie

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-21 Fax: +49-8142-66989-80  Email: lu...@denx.de

[PATCH] mkeficapsule: Free up resources used for adding public key to dtb

[Sughosh Ganu]

Fix the issues flagged by Coverity on resources not being released in
the add_public_key function.

Signed-off-by: Sughosh Ganu 
---
 tools/mkeficapsule.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
index 270943fc90..caf0a1b231 100644
--- a/tools/mkeficapsule.c
+++ b/tools/mkeficapsule.c
@@ -150,6 +150,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if (srcfd == -1) {
fprintf(stderr, "%s: Can't open %s: %s\n",
__func__, pkey_file, strerror(errno));
+   ret = -1;
goto err;
}
 
@@ -157,6 +158,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if (ret == -1) {
fprintf(stderr, "%s: Can't stat %s: %s\n",
__func__, pkey_file, strerror(errno));
+   ret = -1;
goto err;
}
 
@@ -167,6 +169,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if ((sptr == MAP_FAILED) || (errno != 0)) {
fprintf(stderr, "%s: Failed to mmap %s:%s\n",
__func__, pkey_file, strerror(errno));
+   ret = -1;
goto err;
}
 
@@ -175,6 +178,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if (destfd == -1) {
fprintf(stderr, "%s: Can't open %s: %s\n",
__func__, dtb_file, strerror(errno));
+   ret = -1;
goto err;
}
 
@@ -189,6 +193,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if (ftruncate(destfd, dtb.st_size)) {
fprintf(stderr, "%s: Can't expand %s: %s\n",
__func__, dtb_file, strerror(errno));
+   ret = -1;
goto err;;
}
 
@@ -199,11 +204,13 @@ static int add_public_key(const char *pkey_file, const 
char *dtb_file,
if ((dptr == MAP_FAILED) || (errno != 0)) {
fprintf(stderr, "%s: Failed to mmap %s:%s\n",
__func__, dtb_file, strerror(errno));
+   ret = -1;
goto err;
}
 
if (fdt_check_header(dptr)) {
fprintf(stderr, "%s: Invalid FDT header\n", __func__);
+   ret = -1;
goto err;
}
 
@@ -211,6 +218,7 @@ static int add_public_key(const char *pkey_file, const char 
*dtb_file,
if (ret) {
fprintf(stderr, "%s: Cannot expand FDT: %s\n",
__func__, fdt_strerror(ret));
+   ret = -1;
goto err;
}
 
@@ -219,10 +227,11 @@ static int add_public_key(const char *pkey_file, const 
char *dtb_file,
if (ret < 0) {
fprintf(stderr, "%s: Unable to add public key to the FDT\n",
__func__);
+   ret = -1;
goto err;
}
 
-   return 0;
+   ret = 0;
 
 err:
if (sptr)
@@ -237,7 +246,7 @@ err:
if (destfd >= 0)
close(destfd);
 
-   return -1;
+   return ret;
 }
 
 static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
-- 
2.17.1

Re: Pull request: u-boot-rockchip-20210121

[Rtp]

Kever Yang  writes:

Hi,

> Hi Tom,
>
> Please pull the rockchip updates/fixes:
> - New board: rk3328 NanoPi R2S board;
> - Fix init voltage for some rk3399 boards;
> - enable rng for rk3399 by default;
> - set default to SPI bus 1 for SPI-flash for some board;
> - add dwc PCIe controller driver on rockchip platform;

I don't remember getting any mail about my patches related to edp on
pinebook pro patchset 
(https://patchwork.ozlabs.org/project/uboot/list/?series=215793).

Did I miss something something  ?

Thanks,
Arnaud

Re: [scan-ad...@coverity.com: New Defects reported by Coverity Scan for Das U-Boot]

[Sughosh Ganu]

On Thu, 21 Jan 2021 at 00:34, Tom Rini  wrote:

> I decided to run Coverity part-way through the merge window this time
> and here's what's been found so far.
>
> - Forwarded message from scan-ad...@coverity.com -
>
> Date: Mon, 18 Jan 2021 17:53:19 + (UTC)
> From: scan-ad...@coverity.com
> To: tom.r...@gmail.com
> Subject: New Defects reported by Coverity Scan for Das U-Boot
>
> Hi,
>
> Please find the latest report on new defect(s) introduced to Das U-Boot
> found with Coverity Scan.
>
> 23 new defect(s) introduced to Das U-Boot found with Coverity Scan.
> 2 defect(s), reported by Coverity Scan earlier, were marked fixed in the
> recent build analyzed by Coverity Scan.
>
> New defect(s) Reported-by: Coverity Scan
> Showing 20 of 23 defect(s)
>
> ** CID 316356:  Resource leaks  (RESOURCE_LEAK)
> /tools/mkeficapsule.c: 225 in add_public_key()
>
>



>
>
> 
> *** CID 316356:  Resource leaks  (RESOURCE_LEAK)
> /tools/mkeficapsule.c: 225 in add_public_key()
> 219 if (ret < 0) {
> 220 fprintf(stderr, "%s: Unable to add public key to
> the FDT\n",
> 221 __func__);
> 222 goto err;
> 223 }
> 224
> >>> CID 316356:  Resource leaks  (RESOURCE_LEAK)
> >>> Handle variable "srcfd" going out of scope leaks the handle.
> 225 return 0;
> 226
> 227 err:
> 228 if (sptr)
> 229 munmap(sptr, src_size);
> 230
>

I think these should not cause any issues, since the function return
results in the process termination in both the scenarios of success and
failure. But i will post a patch to handle these errors to keep the
resource handling consistent.

-sughosh

Re: [PATCH 1/2] board: Atmel: Add SAMA5D27 giant board

[Eugen.Hristev]

On 21.01.2021 00:38, Greg Gallagher wrote:
> Giant board is a tiny SBC based on the Adafruit Feather form factor,
> created by groboards it contains a SAMA5D2 processor (SAMA5D27),
> 128 MB of RAM and a microSD card for storage.
> 
> Signed-off-by: Greg Gallagher 
> ---

Hi Greg,

This patch [1/2] ARM: at91: spl: add spl_early_init for sama52d platforms

has disappeared from your series. Do you still need it and forgot to 
send it ?

Thank you for the patch,
Eugen
> 
>   arch/arm/dts/Makefile |   3 +-
>   arch/arm/dts/at91-sama5d27_giantboard.dts | 128 ++
>   board/atmel/sama5d27_som1_ek/MAINTAINERS  |   6 +
>   configs/sama5d27_giantboard_defconfig |  97 
>   4 files changed, 233 insertions(+), 1 deletion(-)
>   create mode 100644 arch/arm/dts/at91-sama5d27_giantboard.dts
>   create mode 100644 configs/sama5d27_giantboard_defconfig
> 
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index e320c2254e..8a6a8bcee3 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -905,7 +905,8 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
>  at91-sama5d2_xplained.dtb
> 
>   dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \
> -   at91-sama5d27_som1_ek.dtb
> +   at91-sama5d27_som1_ek.dtb   \
> +   at91-sama5d27_giantboard.dtb
> 
>   dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \
>  at91-sama5d27_wlsom1_ek.dtb
> diff --git a/arch/arm/dts/at91-sama5d27_giantboard.dts 
> b/arch/arm/dts/at91-sama5d27_giantboard.dts
> new file mode 100644
> index 00..e81ca60ca0
> --- /dev/null
> +++ b/arch/arm/dts/at91-sama5d27_giantboard.dts
> @@ -0,0 +1,128 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * at91-sama5d27_giantboard.dts - Device Tree file for Giant Board
> + *
> + * Copyright (C) 2020 Greg Gallagher 
> + *
> + * Derived from at91-sama5d27_som1_ek.dts
> + *
> + * Copyright (C) 2017 Microchip Corporation
> + *   Wenyou Yang 
> + */
> +/dts-v1/;
> +#include "sama5d2.dtsi"
> +#include "sama5d2-pinfunc.h"
> +
> +/ {
> +   model = "Giant Board";
> +   compatible = "atmel,sama5d27-giantboard", "atmel,sama5d2", 
> "atmel,sama5";
> +
> +   memory {
> +   reg = <0x2000 0x800>;
> +   };
> +
> +   chosen {
> +   u-boot,dm-pre-reloc;
> +   stdout-path = &uart1;
> +   };
> +
> +   ahb {
> +   sdmmc1: sdio-host@b000 {
> +   bus-width = <4>;
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default 
> &pinctrl_sdmmc1_ck_cd_default>;
> +   status = "okay";
> +   u-boot,dm-pre-reloc;
> +   };
> +
> +   apb {
> +
> +   uart1: serial@f802 {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&pinctrl_uart1_default>;
> +   status = "okay";
> +   u-boot,dm-pre-reloc;
> +   };
> +
> +   i2c0: i2c@f8028000 {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&pinctrl_i2c0_default>;
> +   status = "okay";
> +   };
> +
> +   i2c1: i2c@fc028000 {
> +   pinctrl-names = "default";
> +   pinctrl-0 = <&pinctrl_i2c1_default>;
> +   status = "okay";
> +
> +   pmic@5b {
> +   compatible = "active-semi,act8945a";
> +   reg = <0x5b>;
> +   active-semi,vsel-low;
> +   status = "okay";
> +   };
> +   };
> +
> +   pit: timer@f8048030 {
> +   status = "okay";
> +   u-boot,dm-pre-reloc;
> +   };
> +
> +   sfr: sfr@f803 {
> +   status = "okay";
> +   u-boot,dm-pre-reloc;
> +   };
> +
> +   pioA: gpio@fc038000 {
> +   pinctrl {
> +
> +   pinctrl_sdmmc1_cmd_dat_default: 
> sdmmc1_cmd_dat_default {
> +   pinmux = 
> ,
> +
> ,
> +
> ,
> +
> ,
> +
> ;
> +   bias-pull-up;
> +   u-boot,dm

Re: [PATCH 15/15] gpio: Add a way to read 3-way strapping pins

[Patrick DELAUNAY]

Hi Simon,

On 1/15/21 3:05 PM, Simon Glass wrote:

Using the internal vs. external pull resistors it is possible to get
27 different combinations from 3 strapping pins. Add an implementation
of this.

This involves updating the sandbox GPIO driver to model external and
(weaker) internal pull resistors. The get_value() method now takes account
of what is driving a pin:

sandbox: GPIOD_EXT_DRIVEN - in which case GPIO_EXT_HIGH provides the
   value
outside source - in which case GPIO_EXT_PULL_UP/DOWN indicates the
   external state and we work the final state using those flags and
   the internal GPIOD_PULL_UP/DOWN flags

Of course the outside source does not really exist in sandbox. We are just
modelling it for test purpose.

Signed-off-by: Simon Glass 
---

  arch/sandbox/include/asm/gpio.h |  5 +-
  drivers/gpio/gpio-uclass.c  | 78 ++
  drivers/gpio/sandbox.c  | 13 +++--
  include/asm-generic/gpio.h  | 37 +
  test/dm/gpio.c  | 98 +
  5 files changed, 226 insertions(+), 5 deletions(-)

diff --git a/arch/sandbox/include/asm/gpio.h b/arch/sandbox/include/asm/gpio.h
index edf78cb4131..097abfb299c 100644
--- a/arch/sandbox/include/asm/gpio.h
+++ b/arch/sandbox/include/asm/gpio.h
@@ -26,8 +26,11 @@
  /* Our own private GPIO flags, which musn't conflict with GPIOD_... */
  #define GPIOD_EXT_HIGHBIT(20) /* external source is high 
(else low) */
  #define GPIOD_EXT_DRIVEN  BIT(21) /* external source is driven */
+#define GPIOD_EXT_PULL_UP  BIT(22) /* GPIO has external pull-up */
+#define GPIOD_EXT_PULL_DOWNBIT(23) /* GPIO has external pull-down */
  
-#define GPIOD_SANDBOX_MASK	GENMASK(21, 20)

+#define GPIOD_EXT_PULL (BIT(21) | BIT(22))
+#define GPIOD_SANDBOX_MASK GENMASK(23, 20)
  
  /**

   * Return the simulated value of a GPIO (used only in sandbox test code)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c
index 77b40263bbd..984c07d1dfa 100644
--- a/drivers/gpio/gpio-uclass.c
+++ b/drivers/gpio/gpio-uclass.c
@@ -3,6 +3,8 @@
   * Copyright (c) 2013 Google, Inc
   */
  
+#define LOG_CATEGORY	UCLASS_GPIO

+


define for LOG feature could be a separate patch ?

to support CONFIG_LOG with existing debug() macro


  #include 
  #include 
  #include 
@@ -20,6 +22,7 @@
  #include 
  #include 
  #include 
+#include 
  
  DECLARE_GLOBAL_DATA_PTR;
  
@@ -708,6 +711,21 @@ int dm_gpio_set_dir_flags(struct gpio_desc *desc, ulong flags)

return dm_gpio_clrset_flags(desc, 0, flags);
  }
  
+int dm_gpios_clrset_flags(struct gpio_desc *desc, int count, ulong clr,

+ ulong set)
+{
+   int ret;
+   int i;
+
+   for (i = 0; i < count; i++) {
+   ret = dm_gpio_clrset_flags(&desc[i], clr, set);
+   if (ret)
+   return log_ret(ret);
+   }
+
+   return 0;
+}
+
  int dm_gpio_get_flags(struct gpio_desc *desc, ulong *flagsp)
  {
struct udevice *dev = desc->dev;
@@ -974,6 +992,66 @@ int dm_gpio_get_values_as_int(const struct gpio_desc 
*desc_list, int count)
return vector;
  }
  
+int dm_gpio_get_values_as_int_base3(struct gpio_desc *desc_list,

+   int count)
+{
+   static const char tristate[] = "01z";
+   enum {
+   PULLUP,
+   PULLDOWN,
+
+   NUM_OPTIONS,
+   };
+   int vals[NUM_OPTIONS];
+   uint mask;
+   uint vector = 0;
+   int ret, i;
+


return error if overflow for the the request count ?

when size_of(int) / 3 < count.



+   for (i = 0; i < NUM_OPTIONS; i++) {
+   uint flags = GPIOD_IS_IN;
+
+   flags |= (i == PULLDOWN) ? GPIOD_PULL_DOWN : GPIOD_PULL_UP;
+   ret = dm_gpios_clrset_flags(desc_list, count, GPIOD_MASK_PULL,
+   flags);
+   if (ret)
+   return log_msg_ret("pu", ret);
+
+   /* Give the lines time to settle */
+   udelay(10);
+
+   ret = dm_gpio_get_values_as_int(desc_list, count);
+   if (ret < 0)
+   return log_msg_ret("get1", ret);
+   vals[i] = ret;
+   }
+
+   log_debug("values: %x %x, count = %d\n", vals[0], vals[1], count);
+   for (i = count - 1, mask = 1 << i; i >= 0; i--, mask >>= 1) {
+   uint pd = vals[PULLDOWN] & mask ? 1 : 0;
+   uint pu = vals[PULLUP] & mask ? 1 : 0;
+   uint digit;
+
+   /*
+* Get value with internal pulldown active. If this is 1 then
+* there is a stronger external pullup, which we call 1. If not
+* then call it 0.
+*/
+   digit = pd;
+
+   /*
+* If the values differ then the pin is floating so we call
+* this a 2.
+