Re: [PATCH u-boot-dm] fdt_support: Add fdt_for_each_node_by_compatible() helper macro
Please find a few minor comments below...
On 1/7/22 11:13, Marek Behún wrote:
From: Marek Behún
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.
Convert various usages of
off = fdt_node_offset_by_compatible(fdt, start, compat);
while (off > 0) {
code();
off = fdt_node_offset_by_compatible(fdt, off, compat);
}
and similar, to
fdt_for_each_node_by_compatible(off, fdt, start, compat)
code();
Signed-off-by: Marek Behún
---
This currently applies on marvell/next, so only after that is merged
it can be applied elsewhere.
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 9 ++---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 +
arch/arm/mach-tegra/gpu.c | 5 +
arch/mips/mach-octeon/octeon_fdt.c | 11 ++-
arch/powerpc/cpu/mpc85xx/liodn.c | 9 ++---
board/Marvell/octeon_ebb7304/board.c | 9 +++--
board/congatec/cgtqmx8/spl.c | 7 ++-
board/freescale/lx2160a/lx2160a.c | 5 +
common/fdt_support.c | 22 --
drivers/misc/fsl_portals.c | 6 +-
drivers/net/fm/fdt.c | 3 +--
drivers/pci/pcie_layerscape_fixup_common.c | 12 ++--
drivers/phy/marvell/comphy_a3700.c | 10 +-
drivers/video/meson/simplefb_common.c | 7 ++-
drivers/video/sunxi/simplefb_common.c | 5 ++---
include/fdt_support.h | 6 ++
16 files changed, 41 insertions(+), 90 deletions(-)
Diffstat looks nice. :)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4ec0dbf516..ddceab29d2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -161,14 +161,9 @@ void fsl_fdt_disable_usb(void *blob)
* controller is used, SYSCLK must meet the additional requirement
* of 100 MHz.
*/
- if (CONFIG_SYS_CLK_FREQ != 1) {
- off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
- while (off != -FDT_ERR_NOTFOUND) {
+ if (CONFIG_SYS_CLK_FREQ != 1)
+ fdt_for_each_node_by_compatible (off, blob, -1, "snps,dwc3")
Again here the question:
Why are adding the space before the "(" here? This does not seem the
common and preferred coding style AFAICT.
Other that this:
Reviewed-by: Stefan Roese
Thanks,
Stefan
fdt_status_disabled(blob, off);
- off = fdt_node_offset_by_compatible(blob, off,
- "snps,dwc3");
- }
- }
}
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 82c5a8b123..b74387e731 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -116,8 +116,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
int noff, len, icid;
const u32 *prop;
- noff = fdt_node_offset_by_compatible(blob, -1, compat);
- while (noff > 0) {
+ fdt_for_each_node_by_compatible (noff, blob, -1, compat) {
prop = fdt_getprop(blob, noff, "cell-index", &len);
if (!prop) {
printf("WARNING missing cell-index for fman port\n");
@@ -137,8 +136,6 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
}
fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
-
- noff = fdt_node_offset_by_compatible(blob, noff, compat);
}
}
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index 13ffade040..3ce51e8526 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -46,11 +46,8 @@ int tegra_gpu_enable_node(void *blob, const char *compat)
if (!_configured)
return 0;
- offset = fdt_node_offset_by_compatible(blob, -1, compat);
- while (offset != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_node_by_compatible (offset, blob, -1, compat)
fdt_status_okay(blob, offset);
- offset = fdt_node_offset_by_compatible(blob, offset, compat);
- }
return 0;
}
diff --git a/arch/mips/mach-octeon/octeon_fdt.c
b/arch/mips/mach-octeon/octeon_fdt.c
index 199f692516..1338b67611 100644
--- a/arch/mips/mach-octeon/octeon_fdt.c
+++ b/arch/mips/mach-octeon/octeon_fdt.c
@@ -424,12 +424,8 @@ void __octeon_fixup_fdt_mac_addr(void)
}
/* Assign 78XX addresses in the order they appear in the device tree. */
- node = fdt_node_offset_by_compatible(working_fdt, -1,
"cavium,octeon-7890-bgx-port");
- while (node != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_node_by_compatible (node, working_fdt, -1,
"cavium,oc
In arm64 case, how is fdt address passed to x0 before switching to linux?
Hello experts,
I'm doing debug for arm64 linux booting using u-boot-spl.
Because I can use only 8MB on-chip ram in place of DDR located at 0x8000
for now,
I modified the spl code so that kernel image is placed at 0x8008 and fdt
is located at 0x8070. (memcopy-ied from FIT image loaded at 0x8010).
I'm sure the cpu has switched to linux but don't see kernel messages.
Because I can't use debugger for actual board now, I'm using qemu to find
what's wrong using the emulation. So far the behavior is the same with the
FPGA board.
Now, the x0 register is supposed to point to fdt when linux is entered, but
I found the x0 value was not set before switching to linux.
I think this malfunction came from the modifications I made to the source
made for our special situation.
I searched common/spl/spl.c and arch/arm/lib/spl.c but couldn't find where
x0 register is set.
(the spl_image->fdt_address has been already set to 0x8070 already).
<< common/spl/spl.c >>
#ifdef CONFIG_SPL_OS_BOOT // set to yes
case IH_OS_LINUX:
debug("Jumping to Linux\n");
#if defined(CONFIG_SYS_SPL_ARGS_ADDR) // not set
spl_fixup_fdt((void *)CONFIG_SYS_SPL_ARGS_ADDR);
#endif
spl_board_prepare_for_linux();
jump_to_image_linux(&spl_image);
#endif
<< arch/arm/lib/spl.c >>
#ifdef CONFIG_SPL_OS_BOOT // set to yes
#ifdef CONFIG_ARM64 // set to yes
void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
{
debug("Entering kernel arg pointer: 0x%p\n", spl_image->arg);
cleanup_before_linux();
armv8_switch_to_el2((u64)spl_image->arg, 0, 0, 0,
spl_image->entry_point, ES_TO_AARCH64);
}
#else
void __noreturn jump_to_image_linux(struct spl_image_info *spl_image)
{
unsigned long machid = 0x;
#ifdef CONFIG_MACH_TYPE
machid = CONFIG_MACH_TYPE;
#endif
Where in the u-boot-spl code is the x0 register set with fdt address?
Any comment/advice will be really appreciated.
Thank you!
Chan Kim
Re: [PATCH u-boot-dm] fdt_support: Add fdt_for_each_node_by_compatible() helper macro
Hi Marek, On 1/7/22 12:33, Marek Behún wrote: Hello Simon, Stefan, this patch is for u-boot-dm, but will apply only after marvell/next is merged. Could we perhaps review it and let Stefan apply it on marvell/next? I'm fine with this (when my minor comment is addressed), if Simon and others are also okay with this patch. Thanks, Stefan
Re: [PATCH 2/2] ARM: mvebu: x530: Add option for ECC
On Mon, 10 Jan 2022, 8:37 PM Stefan Roese, wrote:
> On 1/6/22 04:08, Chris Packham wrote:
> > Some older x530 boards have layout issues that cause problems for DDR.
> > These are usually seen as training failures but can also cause problems
> > after training has completed. Add an option to enable ECC leaving the
> > default as N which will work with both old and new boards.
> >
> > Signed-off-by: Chris Packham
>
> Just checking: Most likely you don't have the possibility to detect the
> board version at runtime?
>
Not in a way that can be done without working RAM. For our internal fork we
maintain 2 defconfigs one with ECC one without. We can manage via the BOM
which boards get which bootloader.
> If this is not possible:
>
> Reviewed-by: Stefan Roese
>
> Thanks,
> Stefan
>
> > ---
> >
> > arch/arm/mach-mvebu/Kconfig | 1 +
> > board/alliedtelesis/x530/Kconfig | 20
> > board/alliedtelesis/x530/x530.c | 8 +++-
> > 3 files changed, 28 insertions(+), 1 deletion(-)
> > create mode 100644 board/alliedtelesis/x530/Kconfig
> >
> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> > index d23cc0c760f1..7388ade98d52 100644
> > --- a/arch/arm/mach-mvebu/Kconfig
> > +++ b/arch/arm/mach-mvebu/Kconfig
> > @@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX
> >
> > source "board/solidrun/clearfog/Kconfig"
> > source "board/kobol/helios4/Kconfig"
> > +source "board/alliedtelesis/x530/Kconfig"
> >
> > endif
> > diff --git a/board/alliedtelesis/x530/Kconfig
> b/board/alliedtelesis/x530/Kconfig
> > new file mode 100644
> > index ..5c1ae36aebaa
> > --- /dev/null
> > +++ b/board/alliedtelesis/x530/Kconfig
> > @@ -0,0 +1,20 @@
> > +menu "x530 configuration"
> > + depends on TARGET_X530
> > +
> > +config X530_ECC
> > + bool "Enable DDR3 ECC"
> > + help
> > + Some of the older x530 board have layout issues which cause
> problems
> > + for the DDR which usually exhibit as DDR training failures or
> > + problems accessing DDR after training.
> > +
> > + The known affected boards are:
> > +
> > + * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm)
> > + * 844-001948-00 (GS980MX/28)
> > + * 844-002008-00 (x530L-52GTX, x530L-52GPX)
> > + * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm)
> > +
> > + If you have a newer board you can set Y here, otherwise say N.
> > +
> > +endmenu
> > diff --git a/board/alliedtelesis/x530/x530.c
> b/board/alliedtelesis/x530/x530.c
> > index 866b6e68cc16..de20684f4353 100644
> > --- a/board/alliedtelesis/x530/x530.c
> > +++ b/board/alliedtelesis/x530/x530.c
> > @@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map
> **serdes_map_array, u8 *count)
> > return 0;
> > }
> >
> > +#if CONFIG_IS_ENABLED(X530_ECC)
> > + #define BUS_MASK BUS_MASK_32BIT_ECC
> > +#else
> > + #define BUS_MASK BUS_MASK_32BIT
> > +#endif
> > +
> > /*
> >* Define the DDR layout / topology here in the board file. This will
> >* be used by the DDR3 init code in the SPL U-Boot version to configure
> > @@ -66,7 +72,7 @@ static struct mv_ddr_topology_map board_topology_map =
> {
> > 0, 0, /* cas_l cas_wl */
> > MV_DDR_TEMP_LOW,/* temperature */
> > MV_DDR_TIM_2T} }, /* timing */
> > - BUS_MASK_32BIT_ECC, /* subphys mask */
> > + BUS_MASK, /* subphys mask */
> > MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
> > NOT_COMBINED, /* ddr twin-die combined */
> > { {0} },/* raw spd data */
> >
>
> Viele Grüße,
> Stefan Roese
>
> --
> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
>
Re: [PATCH 8/8] video: Convert UTF-8 input stream to the 437 code page
/On 1/10/22 01:56, Andre Przywara wrote:
The bitmap fonts (VGA 8x16 and friends) we import from Linux use the
437 code page to map their glyphs. For U-Boot's own purposes this is
probably fine, but UEFI applications output Unicode, which only matches
in the very basic first 127 characters.
Add a function that converts UTF-8 character sequences into the
respective CP437 code point, as far as the characters defined in there
allow this. This includes quite some international and box drawing
characters, which are used by UEFI applications.
Signed-off-by: Andre Przywara
---
drivers/video/Makefile| 1 +
drivers/video/utf8_cp437.c| 169 ++
drivers/video/vidconsole-uclass.c | 6 +-
include/video_console.h | 9 ++
4 files changed, 184 insertions(+), 1 deletion(-)
create mode 100644 drivers/video/utf8_cp437.c
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 8956b5f9b00..5f9823dff9e 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_DISPLAY) += display-uclass.o
obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
obj-$(CONFIG_DM_VIDEO) += video_bmp.o
+obj-$(CONFIG_DM_VIDEO) += utf8_cp437.o
obj-$(CONFIG_PANEL) += panel-uclass.o
obj-$(CONFIG_DM_PANEL_HX8238D) += hx8238d.o
obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
diff --git a/drivers/video/utf8_cp437.c b/drivers/video/utf8_cp437.c
new file mode 100644
index 000..cab68b92b6e
--- /dev/null
+++ b/drivers/video/utf8_cp437.c
A translation from Unicode to CP437 is needed in the FAT driver (but
missing), in Unicode Collation Protocol and here in video. So this
functionality should live in lib/charset.c.
Please, have a look at efi_fat_to_str() in
lib/efi_loader/efi_unicode_collation.c. We should avoid code duplication.
Maybe we should drop CP1250 support to make our effort simpler? No
defconfig uses it.
@@ -0,0 +1,169 @@
+/*
+ * Convert UTF-8 bytes into a code page 437 character.
+ * Based on the table in the Code_page_437 Wikipedia page.
+ */
+
+#include
+
+uint8_t code_points_00a0[] = {
+ 255, 173, 155, 156, 7, 157, 7, 21,
+ 7, 7, 166, 174, 170, 7, 7, 7,
+ 248, 241, 253, 7, 7, 230, 20, 250,
+ 7, 7, 167, 175, 172, 171, 7, 168,
+ 7, 7, 7, 7, 142, 143, 146, 128,
+ 7, 144, 7, 7, 7, 7, 7, 7,
+ 7, 165, 7, 7, 7, 7, 153, 7,
+ 7, 7, 7, 7, 154, 7, 7, 225,
+ 133, 160, 131, 7, 132, 134, 145, 135,
+ 138, 130, 136, 137, 141, 161, 140, 139,
+ 7, 164, 149, 162, 147, 7, 148, 246,
+ 7, 151, 163, 150, 129, 7, 7, 152,
+};
+
+uint8_t code_points_2550[] = {
+ 205, 186, 213, 214, 201, 184, 183, 187,
+ 212, 211, 200, 190, 189, 188, 198, 199,
+ 204, 181, 182, 185, 209, 210, 203, 207,
+ 208, 202, 216, 215, 206
+};
+
+static uint8_t utf8_convert_11bit(uint16_t code)
+{
+ switch (code) {
+ case 0x0192: return 159;
+ case 0x0393: return 226;
+ case 0x0398: return 233;
+ case 0x03A3: return 228;
+ case 0x03A6: return 232;
+ case 0x03A9: return 234;
+ case 0x03B1: return 224;
+ case 0x03B4: return 235;
+ case 0x03B5: return 238;
+ case 0x03C0: return 227;
+ case 0x03C3: return 229;
+ case 0x03C4: return 231;
+ case 0x03C6: return 237;
+ }
+
+ return 0;
+};
+
+static uint8_t utf8_convert_2xxx(uint16_t code)
This is duplicate to include/cp437.h
+{
+ switch (code) {
+ case 0x2022: return 7;
+ case 0x203C: return 19;
+ case 0x207F: return 252;
+ case 0x20A7: return 158;
+ case 0x2190: return 27;
+ case 0x2191: return 24;
+ case 0x2192: return 26;
+ case 0x2193: return 25;
+ case 0x2194: return 29;
+ case 0x2195: return 18;
+ case 0x21A8: return 23;
+ case 0x2219: return 249;
+ case 0x221A: return 251;
+ case 0x221E: return 236;
+ case 0x221F: return 28;
+ case 0x2229: return 239;
+ case 0x2248: return 247;
+ case 0x2261: return 240;
+ case 0x2264: return 243;
+ case 0x2265: return 242;
+ case 0x2310: return 169;
+ case 0x2320: return 244;
+ case 0x2321: return 245;
+ case 0x2500: return 196;
+ case 0x2502: return 179;
+ case 0x250C: return 218;
+ case 0x2510: return 191;
+ case 0x2514: return 192;
+ case 0x2518: return 217;
+ case 0x251C: return 195;
+ case 0x2524: return 180;
+ case 0x252C: return 194;
+ case 0x2534: return 193;
+ case 0x253C: return 197;
+ case 0x2580: return 223;
+ case 0x2584: return 220;
+ case 0x2588: return 219;
+ case 0x258C: return 221;
+ case 0x2590: return 222;
+ case 0x2591: return 176;
+ case 0x2592: return 177;
+ case
Re: [PATCH u-boot-marvell v2] arm: mvebu: turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob
On Monday 10 January 2022 08:43:17 Stefan Roese wrote:
> > + /* If mSATA card is not present, disable SATA DT node */
> > + if (!mode_sata) {
> > + fdt_for_each_node_by_compatible (node, blob, -1,
> > +"marvell,armada-380-ahci") {
>
> Why are adding the space before the "(" here? This does not seem the
> common and preferred coding style AFAICT.
Hello Stefan! Just to note that I'm adding this space too when writing
for-loops. E.g.:
for (i = 0; i < 10; i++) {
...
}
or:
fdt_for_each_node_by_compatible (node, blob, -1, compatible) {
...
}
> > + if (!fdtdec_get_is_enabled(blob, node))
> > + continue;
> > +
> > + if (fdt_status_disabled(blob, node) < 0)
> > + printf("Cannot disable SATA DT node!\n");
> > + else
> > + debug("Disabled SATA DT node\n");
> > +
> > + break;
> > + }
> > +
> > + return;
> > + }
Re: [PATCH u-boot-marvell v2] arm: mvebu: turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob
On 1/10/22 10:06, Pali Rohár wrote:
On Monday 10 January 2022 08:43:17 Stefan Roese wrote:
+ /* If mSATA card is not present, disable SATA DT node */
+ if (!mode_sata) {
+ fdt_for_each_node_by_compatible (node, blob, -1,
+"marvell,armada-380-ahci") {
Why are adding the space before the "(" here? This does not seem the
common and preferred coding style AFAICT.
Hello Stefan! Just to note that I'm adding this space too when writing
for-loops. E.g.:
for (i = 0; i < 10; i++) {
...
}
or:
fdt_for_each_node_by_compatible (node, blob, -1, compatible) {
...
}
Right. But we already have multiple of these for () helpers in U-Boot
and Linux. And AFACIT all are used without this space:
[stefan@ryzen u-boot (master)]$ git grep for_each drivers/
drivers/block/blkcache.c: list_for_each_entry(node, &block_cache, lh)
drivers/block/blkcache.c: list_for_each_safe(entry, n, &block_cache) {
drivers/button/button-adc.c:dev_for_each_subnode(node, dev->parent) {
drivers/button/button-adc.c:dev_for_each_subnode(node, parent) {
drivers/button/button-gpio.c: dev_for_each_subnode(node, parent) {
drivers/clk/clk-uclass.c: list_for_each_entry(child_dev,
&clk->dev->child_head, sibling_node) {
drivers/clk/clk_stm32mp1.c: ofnode_for_each_subnode(subnode, node) {
drivers/core/device-remove.c: list_for_each_entry_safe(pos, n,
&dev->child_head, sibling_node) {
drivers/core/device-remove.c: list_for_each_entry_safe(pos, n,
&dev->child_head, sibling_node) {
drivers/core/device.c: list_for_each_entry_safe(pos, n,
&dev->parent->child_head,
drivers/core/device.c: list_for_each_entry(uc, gd->uclass_root,
sibling_node) {
So I would prefer to also use this new helper without the extra space as
well.
Thanks,
Stefan
Re: [PATCH 7/8] efi_selftest: Add box drawing character selftest
On 1/10/22 01:56, Andre Przywara wrote:
UEFI applications rely on Unicode output capability, and might use that
for drawing pseudo-graphical interfaces using Unicode defined box
drawing characters.
Add a simple test to display the most basic box characters, which would
need to be checked manually on the screen for correctness.
To facilitate this, add a three second delay after the output at this
point.
Signed-off-by: Andre Przywara
---
lib/efi_selftest/efi_selftest_textoutput.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/lib/efi_selftest/efi_selftest_textoutput.c
b/lib/efi_selftest/efi_selftest_textoutput.c
index a437732496b..1542c187de7 100644
--- a/lib/efi_selftest/efi_selftest_textoutput.c
+++ b/lib/efi_selftest/efi_selftest_textoutput.c
@@ -123,6 +123,17 @@ static int execute(void)
efi_st_error("OutputString failed for international chars\n");
return EFI_ST_FAILURE;
}
+ ret = con_out->output_string(con_out, L"┌─┬─┐\n");
+ ret |= con_out->output_string(con_out, L"│ │ │\n");
+ ret |= con_out->output_string(con_out, L"├─┼─┤\n");
+ ret |= con_out->output_string(con_out, L"│ │ │\n");
+ ret |= con_out->output_string(con_out, L"└─┴─┘\n");
%s/L"/u"/
Unicode characters in code are not supported by all tools. The
interpretation may further depend on the users locale. Please, use \u
escape sequences. A single output_string() call is enough. A notice for
the user might be helpful. So I suggest:
This should render as four boxes with text
┌─┬───┐
│ left top│ right top │
├─┼───┤
│ left bottom │ right bottom │
└─┴───┘
const u16 text[] =
u"This should render as four boxes with text\n"
u"\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
u"\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502"
u" left top\u2502 right top \u2502\n\u251c\u2500"
u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
u"\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
u"\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 "
u"left bottom \u2502 right bottom \u2502\n\u2514\u2500\u2500\u2500"
u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534"
u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
u"\u2500\u2500\u2500\u2500\u2518\n";
Best regards
Heinrich
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("OutputString failed for box drawing chars\n");
+ return EFI_ST_FAILURE;
+ }
+ con_out->output_string(con_out, L"waiting for admiration...\n");
+ EFI_CALL(systab.boottime->stall(300));
efi_st_printf("\n");
return EFI_ST_SUCCESS;
Re: [PATCH 6/8] efi-selftest: Add international characters test
On 1/10/22 01:56, Andre Przywara wrote:
UEFI relies entirely on unicode output, which actual fonts displayed on
the screen might not be ready for.
Add a test displaying some international characters, to reveal missing
glyphs, especially in our builtin fonts.
This would be needed to be manually checked on the screen for
correctness.
Signed-off-by: Andre Przywara
---
lib/efi_selftest/efi_selftest_textoutput.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/lib/efi_selftest/efi_selftest_textoutput.c
b/lib/efi_selftest/efi_selftest_textoutput.c
index a87f65e197f..a437732496b 100644
--- a/lib/efi_selftest/efi_selftest_textoutput.c
+++ b/lib/efi_selftest/efi_selftest_textoutput.c
@@ -118,6 +118,11 @@ static int execute(void)
efi_st_printf("Unicode not handled properly\n");
return EFI_ST_FAILURE;
}
+ ret = con_out->output_string(con_out, L"Österreich Edelweiß Smørrebrød Smörgås
Niño René >Ἑλλάς<\n");
%s/L"/u"/
Please, don't use UTF-8 in code as some tools don't support it. Instead
use \u escape codes:
const u16 text[] =
u"\u00d6\sterreich Edelwei\u00df \Sm\u00f8rrebr\u00f8d Sm\u00f6rg"
u"\u00e5s Ni\u00f1o Ren\u00e9 >\u1f19\u03bb\u03bb\u03ac\u03c2<\n";
Best regards
Heinrich
+ if (ret != EFI_ST_SUCCESS) {
+ efi_st_error("OutputString failed for international chars\n");
+ return EFI_ST_FAILURE;
+ }
efi_st_printf("\n");
return EFI_ST_SUCCESS;
Re: [PATCH 1/8] video: Add cursor support for DM_VIDEO consoles
On 1/10/22 01:56, Andre Przywara wrote:
So far the DM_VIDEO console is completely lacking any cursor, which makes
typing and correcting quite irritating.
Add a simple cursor display by writing a SPACE glyph in the background
colour to the next character position on the screen. Any typed character
will naturally overwrite it, so we need to only explicitly clear it if
the next character will appear somewhere else (newline, backspace).
Does this work with (non-monospaced) Truetype fonts?
Moving backwards in Truetype is awkward.
Best regards
Heinrich
Signed-off-by: Andre Przywara
---
drivers/video/console_normal.c| 1 +
drivers/video/vidconsole-uclass.c | 42 +++
include/video_console.h | 1 +
3 files changed, 44 insertions(+)
diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
index 04f022491e5..bfd3aab8d24 100644
--- a/drivers/video/console_normal.c
+++ b/drivers/video/console_normal.c
@@ -160,6 +160,7 @@ static int console_normal_probe(struct udevice *dev)
vc_priv->y_charsize = VIDEO_FONT_HEIGHT;
vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH;
vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT;
+ vc_priv->cursor_visible = true;
return 0;
}
diff --git a/drivers/video/vidconsole-uclass.c
b/drivers/video/vidconsole-uclass.c
index f42db40d4cd..420fd86f9ac 100644
--- a/drivers/video/vidconsole-uclass.c
+++ b/drivers/video/vidconsole-uclass.c
@@ -70,6 +70,26 @@ static int vidconsole_entry_start(struct udevice *dev)
return ops->entry_start(dev);
}
+static void draw_cursor(struct udevice *dev, bool state)
+{
+ struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
+ struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
+ u32 tmp;
+
+ if (!priv->cursor_visible)
+ return;
+
+ if (state) {
+ tmp = vid_priv->colour_bg;
+ vid_priv->colour_bg = vid_priv->colour_fg;
+ }
+
+ vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ' ');
+
+ if (state)
+ vid_priv->colour_bg = tmp;
+}
+
/* Move backwards one space */
static int vidconsole_back(struct udevice *dev)
{
@@ -77,6 +97,8 @@ static int vidconsole_back(struct udevice *dev)
struct vidconsole_ops *ops = vidconsole_get_ops(dev);
int ret;
+ draw_cursor(dev, false);
+
if (ops->backspace) {
ret = ops->backspace(dev);
if (ret != -ENOSYS)
@@ -103,6 +125,8 @@ static void vidconsole_newline(struct udevice *dev)
const int rows = CONFIG_CONSOLE_SCROLL_LINES;
int i, ret;
+ draw_cursor(dev, false);
+
priv->xcur_frac = priv->xstart_frac;
priv->ycur += priv->y_charsize;
@@ -342,6 +366,14 @@ static void vidconsole_escape_char(struct udevice *dev, char ch)
break;
}
+ case 'l':
+ draw_cursor(dev, false);
+ priv->cursor_visible = 0;
+ break;
+ case 'h':
+ priv->cursor_visible = 1;
+ draw_cursor(dev, true);
+ break;
case 'J': {
int mode;
@@ -516,6 +548,11 @@ int vidconsole_put_char(struct udevice *dev, char ch)
struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
int ret;
+ /*
+* We don't need to clear the cursor since we are going to overwrite
+* that character anyway.
+*/
+
if (priv->escape) {
vidconsole_escape_char(dev, ch);
return 0;
@@ -530,6 +567,7 @@ int vidconsole_put_char(struct udevice *dev, char ch)
/* beep */
break;
case '\r':
+ draw_cursor(dev, false);
priv->xcur_frac = priv->xstart_frac;
break;
case '\n':
@@ -537,6 +575,7 @@ int vidconsole_put_char(struct udevice *dev, char ch)
vidconsole_entry_start(dev);
break;
case '\t': /* Tab (8 chars alignment) */
+ draw_cursor(dev, false);
priv->xcur_frac = ((priv->xcur_frac / priv->tab_width_frac)
+ 1) * priv->tab_width_frac;
@@ -554,6 +593,8 @@ int vidconsole_put_char(struct udevice *dev, char ch)
break;
}
+ draw_cursor(dev, true);
+
return 0;
}
@@ -620,6 +661,7 @@ static int vidconsole_pre_probe(struct udevice *dev)
struct video_priv *vid_priv = dev_get_uclass_priv(vid);
priv->xsize_frac = VID_TO_POS(vid_priv->xsize);
+ priv->cursor_visible = false;
return 0;
}
diff --git a/include/video_console.h b/include/video_console.h
index 06b798ef10c..a908f1412e8 100644
--- a/include/video_console.h
+++ b/include/video_console.h
@@ -83,6 +83,7 @@ struct vidconsole_priv {
int escape_len;
int row_saved;
int col_saved;
+ bool cursor_visible;
ch
[RFC] imx: imx8qm-rom7720: switch to binman
Switch to use binman to pack images
---
Run into this issue on the first try to get binman working:
make[1]: Nothing to be done for 'SPL'.
BINMAN flash.bin
MKIMAGE flash.bin
Error: spl/u-boot-spl.cfgout[16] - Invalid command (LOADER)
arch/arm/mach-imx/Makefile:190: recipe for target 'flash.bin' failed
make[1]: *** [flash.bin] Error 1
make[1]: *** Deleting file 'flash.bin'
Makefile:1519: recipe for target 'flash.bin' failed
make: *** [flash.bin] Error 2
Some clue howto fix that?
arch/arm/dts/imx8qm-rom7720-a1.dts| 1 +
arch/arm/dts/imx8qm-u-boot.dtsi | 95 +++
arch/arm/mach-imx/imx8/Kconfig| 1 +
.../advantech/imx8qm_rom7720_a1/imximage.cfg | 16 +---
configs/imx8qm_rom7720_a1_4G_defconfig| 2 +-
5 files changed, 100 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi
diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts
b/arch/arm/dts/imx8qm-rom7720-a1.dts
index d1f2fff869..332d441c6d 100644
--- a/arch/arm/dts/imx8qm-rom7720-a1.dts
+++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
@@ -10,6 +10,7 @@
/memreserve/ 0x8000 0x0002;
#include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
/ {
model = "Advantech iMX8QM Qseven series";
diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi
new file mode 100644
index 00..77e5cd6989
--- /dev/null
+++ b/arch/arm/dts/imx8qm-u-boot.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+
+};
+
+&binman {
+ u-boot-nodtb {
+ filename = "u-boot-nodtb.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ };
+
+ flash {
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x10";
+
+ blob {
+ filename = "u-boot-nodtb.bin";
+ };
+
+ };
+
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = ;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ load = ;
+
+ uboot_blob: blob-ext {
+ filename = "u-boot-nodtb.bin";
+ };
+ };
+
+ atf {
+ description = "ARM Trusted Firmware";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x8000>;
+ entry = <0x8000>;
+
+ atf_blob: blob-ext {
+ filename = "bl31.bin";
+ };
+ };
+
+ fdt {
+ description = "imx8qm-rom7720-a1";
+ type = "flat_dt";
+ compression = "none";
+
+ uboot_fdt_blob: blob-ext {
+ filename = "u-boot.dtb";
+ };
+ };
+ };
+
+ configurations {
+ default = "conf";
+
+ conf {
+ description = "imx8qm-rom7720-a1";
+ firmware = "uboot";
+ loadables = "atf";
+ fdt = "fdt";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c6..b42b985cdf 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -81,6 +81,7 @@ config TARGET_CONGA_QMX8
config TARGET_IMX8QM_ROM7720_A1
bool "Support i.MX8QM ROM-7720-A1"
+ select BINMAN
select BOARD_LATE_INIT
[PATCH u-boot-dm v2] fdt_support: Add fdt_for_each_node_by_compatible() helper macro
From: Marek Behún
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.
Convert various usages of
off = fdt_node_offset_by_compatible(fdt, start, compat);
while (off > 0) {
code();
off = fdt_node_offset_by_compatible(fdt, off, compat);
}
and similar, to
fdt_for_each_node_by_compatible(off, fdt, start, compat)
code();
Signed-off-by: Marek Behún
Reviewed-by: Stefan Roese
---
Simon, as in v1, this applies on top of marvell/next and we have another
patch for marvell/next that depends on this.
Could we let him apply it there after it is reviewed?
Thanks.
Changes since v1:
- removed extra space after macro name:
fdt_for_each_node_by_compatible (...)
to
fdt_for_each_node_by_compatible(...)
as requested by Stefan
---
arch/arm/cpu/armv8/fsl-layerscape/fdt.c| 9 ++---
arch/arm/cpu/armv8/fsl-layerscape/icid.c | 5 +
arch/arm/mach-tegra/gpu.c | 5 +
arch/mips/mach-octeon/octeon_fdt.c | 11 ++-
arch/powerpc/cpu/mpc85xx/liodn.c | 9 ++---
board/Marvell/octeon_ebb7304/board.c | 9 +++--
board/congatec/cgtqmx8/spl.c | 7 ++-
board/freescale/lx2160a/lx2160a.c | 5 +
common/fdt_support.c | 22 --
drivers/misc/fsl_portals.c | 6 +-
drivers/net/fm/fdt.c | 3 +--
drivers/pci/pcie_layerscape_fixup_common.c | 12 ++--
drivers/phy/marvell/comphy_a3700.c | 10 +-
drivers/video/meson/simplefb_common.c | 7 ++-
drivers/video/sunxi/simplefb_common.c | 5 ++---
include/fdt_support.h | 6 ++
16 files changed, 41 insertions(+), 90 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 4ec0dbf516..85c7b1f46b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -161,14 +161,9 @@ void fsl_fdt_disable_usb(void *blob)
* controller is used, SYSCLK must meet the additional requirement
* of 100 MHz.
*/
- if (CONFIG_SYS_CLK_FREQ != 1) {
- off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
- while (off != -FDT_ERR_NOTFOUND) {
+ if (CONFIG_SYS_CLK_FREQ != 1)
+ fdt_for_each_node_by_compatible(off, blob, -1, "snps,dwc3")
fdt_status_disabled(blob, off);
- off = fdt_node_offset_by_compatible(blob, off,
- "snps,dwc3");
- }
- }
}
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 82c5a8b123..25cd82f16e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -116,8 +116,7 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
int noff, len, icid;
const u32 *prop;
- noff = fdt_node_offset_by_compatible(blob, -1, compat);
- while (noff > 0) {
+ fdt_for_each_node_by_compatible(noff, blob, -1, compat) {
prop = fdt_getprop(blob, noff, "cell-index", &len);
if (!prop) {
printf("WARNING missing cell-index for fman port\n");
@@ -137,8 +136,6 @@ void fdt_fixup_fman_port_icid_by_compat(void *blob, int
smmu_ph,
}
fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
-
- noff = fdt_node_offset_by_compatible(blob, noff, compat);
}
}
diff --git a/arch/arm/mach-tegra/gpu.c b/arch/arm/mach-tegra/gpu.c
index 13ffade040..36538e7f96 100644
--- a/arch/arm/mach-tegra/gpu.c
+++ b/arch/arm/mach-tegra/gpu.c
@@ -46,11 +46,8 @@ int tegra_gpu_enable_node(void *blob, const char *compat)
if (!_configured)
return 0;
- offset = fdt_node_offset_by_compatible(blob, -1, compat);
- while (offset != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_node_by_compatible(offset, blob, -1, compat)
fdt_status_okay(blob, offset);
- offset = fdt_node_offset_by_compatible(blob, offset, compat);
- }
return 0;
}
diff --git a/arch/mips/mach-octeon/octeon_fdt.c
b/arch/mips/mach-octeon/octeon_fdt.c
index 199f692516..5c5a14e87a 100644
--- a/arch/mips/mach-octeon/octeon_fdt.c
+++ b/arch/mips/mach-octeon/octeon_fdt.c
@@ -424,12 +424,8 @@ void __octeon_fixup_fdt_mac_addr(void)
}
/* Assign 78XX addresses in the order they appear in the device tree. */
- node = fdt_node_offset_by_compatible(working_fdt, -1,
"cavium,octeon-7890-bgx-port");
- while (node != -FDT_ERR_NOTFOUND) {
+ fdt_for_each_node_by_compatible(node, working_fdt, -1,
"cavium,octeon-7890-bgx-port")
octeo
[PATCH u-boot-marvell v2] arm: mvebu: turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob
From: Pali Rohár
On of the MiniPCIe ports on Turris Omnia is also a mSATA port. Whether
it works in SATA or PCIe mode is determined by a strapping pin, which
value is read from the MCU.
We already determine which type of card is connected when configuring
SerDeses.
But until now we left both SATA and PCIe port 0 nodes in device tree
enabled, and so the SATA driver is probed in U-Boot / Linux even if we
know there is no mSATA card, and similarly PCIe driver tries to link on
port 0 even if we know there is mSATA card, not a PCIe card.
Fixup device tree blob to disable SATA node if mSATA card is not
present, and to disable PCIe port 0 node if mSATA card is present.
Do this for U-Boot's DT blob before relocation and also for kernel DT
blob before booting.
This ensures that software does not try to use SATA or PCIe HW when
corresponding PHY is not configured.
Signed-off-by: Pali Rohár
[ refactored and fixed some issues ]
Signed-off-by: Marek Behún
---
Changes since v1:
- removed extra space after macro name:
fdt_for_each_node_by_compatible (...)
to
fdt_for_each_node_by_compatible(...)
as requested by Stefan
---
board/CZ.NIC/turris_omnia/turris_omnia.c | 91 +++-
configs/turris_omnia_defconfig | 1 +
2 files changed, 90 insertions(+), 2 deletions(-)
diff --git a/board/CZ.NIC/turris_omnia/turris_omnia.c
b/board/CZ.NIC/turris_omnia/turris_omnia.c
index ae24d14b76..33cec6587e 100644
--- a/board/CZ.NIC/turris_omnia/turris_omnia.c
+++ b/board/CZ.NIC/turris_omnia/turris_omnia.c
@@ -490,6 +490,86 @@ void spl_board_init(void)
}
}
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP) || IS_ENABLED(CONFIG_OF_BOARD_SETUP)
+
+static void fixup_serdes_0_nodes(void *blob)
+{
+ bool mode_sata;
+ int node;
+
+ /*
+* Determine if SerDes 0 is configured to SATA mode.
+* We do this instead of calling omnia_detect_sata() to avoid another
+* call to the MCU. By this time the common PHYs are initialized (it is
+* done in SPL), so we can read this common PHY register.
+*/
+ mode_sata = (readl(MVEBU_REGISTER(0x183fc)) & GENMASK(3, 0)) == 2;
+
+ /*
+* We're either adding status = "disabled" property, or changing
+* status = "okay" to status = "disabled". In both cases we'll need more
+* space. Increase the size a little.
+*/
+ if (fdt_increase_size(blob, 32) < 0) {
+ printf("Cannot increase FDT size!\n");
+ return;
+ }
+
+ /* If mSATA card is not present, disable SATA DT node */
+ if (!mode_sata) {
+ fdt_for_each_node_by_compatible(node, blob, -1,
+ "marvell,armada-380-ahci") {
+ if (!fdtdec_get_is_enabled(blob, node))
+ continue;
+
+ if (fdt_status_disabled(blob, node) < 0)
+ printf("Cannot disable SATA DT node!\n");
+ else
+ debug("Disabled SATA DT node\n");
+
+ break;
+ }
+
+ return;
+ }
+
+ /* Otherwise disable PCIe port 0 DT node (MiniPCIe / mSATA port) */
+ fdt_for_each_node_by_compatible(node, blob, -1,
+ "marvell,armada-370-pcie") {
+ int port;
+
+ if (!fdtdec_get_is_enabled(blob, node))
+ continue;
+
+ fdt_for_each_subnode (port, blob, node) {
+ if (!fdtdec_get_is_enabled(blob, port))
+ continue;
+
+ if (fdtdec_get_int(blob, port, "marvell,pcie-port",
+ -1) != 0)
+ continue;
+
+ if (fdt_status_disabled(blob, port) < 0)
+ printf("Cannot disable PCIe port 0 DT node!\n");
+ else
+ debug("Disabled PCIe port 0 DT node\n");
+
+ return;
+ }
+ }
+}
+
+#endif
+
+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+ fixup_serdes_0_nodes(blob);
+
+ return 0;
+}
+#endif
+
int board_init(void)
{
/* address of boot parameters */
@@ -694,7 +774,7 @@ static bool fixup_mtd_partitions(void *blob, int offset,
struct mtd_info *mtd)
return true;
}
-int ft_board_setup(void *blob, struct bd_info *bd)
+static void fixup_spi_nor_partitions(void *blob)
{
struct mtd_info *mtd;
int node;
@@ -711,12 +791,19 @@ int ft_board_setup(void *blob, struct bd_info *bd)
goto fail;
put_mtd_device(mtd);
- return 0;
+ return;
fail:
printf("Failed fixing SPI NOR partitions!\n");
if (!IS_ERR_OR_NULL(mtd))
put_mtd_device(mtd);
+}
+
+int ft_board_setup(void *blob, s
Re: [PATCH 8/8] video: Convert UTF-8 input stream to the 437 code page
On Mon, 10 Jan 2022 09:18:45 +0100
Heinrich Schuchardt wrote:
Hi Heinrich,
> /On 1/10/22 01:56, Andre Przywara wrote:
> > The bitmap fonts (VGA 8x16 and friends) we import from Linux use the
> > 437 code page to map their glyphs. For U-Boot's own purposes this is
> > probably fine, but UEFI applications output Unicode, which only matches
> > in the very basic first 127 characters.
> >
> > Add a function that converts UTF-8 character sequences into the
> > respective CP437 code point, as far as the characters defined in there
> > allow this. This includes quite some international and box drawing
> > characters, which are used by UEFI applications.
> >
> > Signed-off-by: Andre Przywara
> > ---
> > drivers/video/Makefile| 1 +
> > drivers/video/utf8_cp437.c| 169 ++
> > drivers/video/vidconsole-uclass.c | 6 +-
> > include/video_console.h | 9 ++
> > 4 files changed, 184 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/video/utf8_cp437.c
> >
> > diff --git a/drivers/video/Makefile b/drivers/video/Makefile
> > index 8956b5f9b00..5f9823dff9e 100644
> > --- a/drivers/video/Makefile
> > +++ b/drivers/video/Makefile
> > @@ -14,6 +14,7 @@ obj-$(CONFIG_DISPLAY) += display-uclass.o
> > obj-$(CONFIG_VIDEO_MIPI_DSI) += dsi-host-uclass.o
> > obj-$(CONFIG_DM_VIDEO) += video-uclass.o vidconsole-uclass.o
> > obj-$(CONFIG_DM_VIDEO) += video_bmp.o
> > +obj-$(CONFIG_DM_VIDEO) += utf8_cp437.o
> > obj-$(CONFIG_PANEL) += panel-uclass.o
> > obj-$(CONFIG_DM_PANEL_HX8238D) += hx8238d.o
> > obj-$(CONFIG_SIMPLE_PANEL) += simple_panel.o
> > diff --git a/drivers/video/utf8_cp437.c b/drivers/video/utf8_cp437.c
> > new file mode 100644
> > index 000..cab68b92b6e
> > --- /dev/null
> > +++ b/drivers/video/utf8_cp437.c
>
> A translation from Unicode to CP437 is needed in the FAT driver (but
> missing), in Unicode Collation Protocol and here in video. So this
> functionality should live in lib/charset.c.
> Please, have a look at efi_fat_to_str() in
> lib/efi_loader/efi_unicode_collation.c. We should avoid code duplication.
Ah, didn't know, thanks for the heads up! Happy to move the code in there,
and will also look for prior art.
> Maybe we should drop CP1250 support to make our effort simpler? No
> defconfig uses it.
I need to have a closer look.
>
> > @@ -0,0 +1,169 @@
> > +/*
> > + * Convert UTF-8 bytes into a code page 437 character.
> > + * Based on the table in the Code_page_437 Wikipedia page.
> > + */
> > +
> > +#include
> > +
> > +uint8_t code_points_00a0[] = {
> > + 255, 173, 155, 156, 7, 157, 7, 21,
> > + 7, 7, 166, 174, 170, 7, 7, 7,
> > + 248, 241, 253, 7, 7, 230, 20, 250,
> > + 7, 7, 167, 175, 172, 171, 7, 168,
> > + 7, 7, 7, 7, 142, 143, 146, 128,
> > + 7, 144, 7, 7, 7, 7, 7, 7,
> > + 7, 165, 7, 7, 7, 7, 153, 7,
> > + 7, 7, 7, 7, 154, 7, 7, 225,
> > + 133, 160, 131, 7, 132, 134, 145, 135,
> > + 138, 130, 136, 137, 141, 161, 140, 139,
> > + 7, 164, 149, 162, 147, 7, 148, 246,
> > + 7, 151, 163, 150, 129, 7, 7, 152,
> > +};
> > +
> > +uint8_t code_points_2550[] = {
> > + 205, 186, 213, 214, 201, 184, 183, 187,
> > + 212, 211, 200, 190, 189, 188, 198, 199,
> > + 204, 181, 182, 185, 209, 210, 203, 207,
> > + 208, 202, 216, 215, 206
> > +};
> > +
> > +static uint8_t utf8_convert_11bit(uint16_t code)
> > +{
> > + switch (code) {
> > + case 0x0192: return 159;
> > + case 0x0393: return 226;
> > + case 0x0398: return 233;
> > + case 0x03A3: return 228;
> > + case 0x03A6: return 232;
> > + case 0x03A9: return 234;
> > + case 0x03B1: return 224;
> > + case 0x03B4: return 235;
> > + case 0x03B5: return 238;
> > + case 0x03C0: return 227;
> > + case 0x03C3: return 229;
> > + case 0x03C4: return 231;
> > + case 0x03C6: return 237;
> > + }
> > +
> > + return 0;
> > +};
> > +
> > +static uint8_t utf8_convert_2xxx(uint16_t code)
>
>
> This is duplicate to include/cp437.h
But this is the other way around, isn't it? The above is from CP437 to
UCS-2, this one here is from UCS-2 to CP437 (and it's misnamed).
But I can certainly move it in there.
> > +{
> > + switch (code) {
> > + case 0x2022: return 7;
> > + case 0x203C: return 19;
> > + case 0x207F: return 252;
> > + case 0x20A7: return 158;
> > + case 0x2190: return 27;
> > + case 0x2191: return 24;
> > + case 0x2192: return 26;
> > + case 0x2193: return 25;
> > + case 0x2194: return 29;
> > + case 0x2195: return 18;
> > + case 0x21A8: return 23;
> > + case 0x2219: return 249;
> > + case 0x221A: return 251;
> > + case 0x221E: return 236;
> > + case 0x221F: return 28;
> > + case 0x2229: return 239;
> > + case 0x2248: return 247;
> > + case 0x2261: return 240;
> > + case 0x2264: return 243;
> > + case 0x2265: return 242;
> > + case 0x2310: return 169;
> > + case 0x2320: return 24
Re: [PATCH 7/8] efi_selftest: Add box drawing character selftest
On Mon, 10 Jan 2022 10:23:20 +0100
Heinrich Schuchardt wrote:
Hi Heinrich,
> On 1/10/22 01:56, Andre Przywara wrote:
> > UEFI applications rely on Unicode output capability, and might use that
> > for drawing pseudo-graphical interfaces using Unicode defined box
> > drawing characters.
> >
> > Add a simple test to display the most basic box characters, which would
> > need to be checked manually on the screen for correctness.
> > To facilitate this, add a three second delay after the output at this
> > point.
> >
> > Signed-off-by: Andre Przywara
> > ---
> > lib/efi_selftest/efi_selftest_textoutput.c | 11 +++
> > 1 file changed, 11 insertions(+)
> >
> > diff --git a/lib/efi_selftest/efi_selftest_textoutput.c
> > b/lib/efi_selftest/efi_selftest_textoutput.c
> > index a437732496b..1542c187de7 100644
> > --- a/lib/efi_selftest/efi_selftest_textoutput.c
> > +++ b/lib/efi_selftest/efi_selftest_textoutput.c
> > @@ -123,6 +123,17 @@ static int execute(void)
> > efi_st_error("OutputString failed for international chars\n");
> > return EFI_ST_FAILURE;
> > }
> > + ret = con_out->output_string(con_out, L"┌─┬─┐\n");
> > + ret |= con_out->output_string(con_out, L"│ │ │\n");
> > + ret |= con_out->output_string(con_out, L"├─┼─┤\n");
> > + ret |= con_out->output_string(con_out, L"│ │ │\n");
> > + ret |= con_out->output_string(con_out, L"└─┴─┘\n");
>
> %s/L"/u"/
>
> Unicode characters in code are not supported by all tools. The
> interpretation may further depend on the users locale. Please, use \u
> escape sequences. A single output_string() call is enough. A notice for
> the user might be helpful. So I suggest:
>
> This should render as four boxes with text
> ┌─┬───┐
> │ left top│ right top │
> ├─┼───┤
> │ left bottom │ right bottom │
> └─┴───┘
>
> const u16 text[] =
> u"This should render as four boxes with text\n"
> u"\u250c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
> u"\u2500\u2500\u2500\u252c\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
> u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2510\n\u2502"
> u" left top\u2502 right top \u2502\n\u251c\u2500"
> u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
> u"\u2500\u253c\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
> u"\u2500\u2500\u2500\u2500\u2500\u2500\u2524\n\u2502 "
> u"left bottom \u2502 right bottom \u2502\n\u2514\u2500\u2500\u2500"
> u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2534"
> u"\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500"
> u"\u2500\u2500\u2500\u2500\u2518\n";
Ha, very good, thanks for the hints! And for typing all those numbers!
I was wondering about UTF-8 in source, but since my ancient Slackware could
deal with it, I deemed it safe ;-)
Will fix it accordingly!
Cheers,
Andre
> > + if (ret != EFI_ST_SUCCESS) {
> > + efi_st_error("OutputString failed for box drawing chars\n");
> > + return EFI_ST_FAILURE;
> > + }
> > + con_out->output_string(con_out, L"waiting for admiration...\n");
> > + EFI_CALL(systab.boottime->stall(300));
> > efi_st_printf("\n");
> >
> > return EFI_ST_SUCCESS;
>
Re: [PATCH v7 2/2] board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
Hi Heiko, On Mon, Jan 10, 2022 at 4:50 AM Heiko Thiery wrote: > > The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor. > > Signed-off-by: Heiko Thiery Reviewed-by: Fabio Estevam
Re: [PATCH v7 1/2] arm: dts: imx8mq: Add Kontron pitx-imx8m
On Mon, Jan 10, 2022 at 4:50 AM Heiko Thiery wrote: > > This adds the device tree for the Kontron pitx-imx8m Board. It is a copy > of the device tree from the linux kernel sources. It is also good to mention the Linux kernel version that was used. Reviewed-by: Fabio Estevam
Re: [PATCH 1/8] video: Add cursor support for DM_VIDEO consoles
On Mon, 10 Jan 2022 10:41:14 +0100
Heinrich Schuchardt wrote:
Hi,
> On 1/10/22 01:56, Andre Przywara wrote:
> > So far the DM_VIDEO console is completely lacking any cursor, which makes
> > typing and correcting quite irritating.
> >
> > Add a simple cursor display by writing a SPACE glyph in the background
> > colour to the next character position on the screen. Any typed character
> > will naturally overwrite it, so we need to only explicitly clear it if
> > the next character will appear somewhere else (newline, backspace).
>
> Does this work with (non-monospaced) Truetype fonts?
> Moving backwards in Truetype is awkward.
I don't know, I need to try this again. I think I tried TrueType (before
adding wide character bitmap support), but ran into some issues, might
well be due to the proportional fonts only.
In general I think *proper* cursor support can be tricky and tedious, so
this version here is deliberately made simple, to have at least *some*
cursor.
Shall we enable this code only for monospace fonts (both TT and bitmap)?
Cheers,
Andre
> > Signed-off-by: Andre Przywara
> > ---
> > drivers/video/console_normal.c| 1 +
> > drivers/video/vidconsole-uclass.c | 42 +++
> > include/video_console.h | 1 +
> > 3 files changed, 44 insertions(+)
> >
> > diff --git a/drivers/video/console_normal.c b/drivers/video/console_normal.c
> > index 04f022491e5..bfd3aab8d24 100644
> > --- a/drivers/video/console_normal.c
> > +++ b/drivers/video/console_normal.c
> > @@ -160,6 +160,7 @@ static int console_normal_probe(struct udevice *dev)
> > vc_priv->y_charsize = VIDEO_FONT_HEIGHT;
> > vc_priv->cols = vid_priv->xsize / VIDEO_FONT_WIDTH;
> > vc_priv->rows = vid_priv->ysize / VIDEO_FONT_HEIGHT;
> > + vc_priv->cursor_visible = true;
> >
> > return 0;
> > }
> > diff --git a/drivers/video/vidconsole-uclass.c
> > b/drivers/video/vidconsole-uclass.c
> > index f42db40d4cd..420fd86f9ac 100644
> > --- a/drivers/video/vidconsole-uclass.c
> > +++ b/drivers/video/vidconsole-uclass.c
> > @@ -70,6 +70,26 @@ static int vidconsole_entry_start(struct udevice *dev)
> > return ops->entry_start(dev);
> > }
> >
> > +static void draw_cursor(struct udevice *dev, bool state)
> > +{
> > + struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
> > + struct video_priv *vid_priv = dev_get_uclass_priv(dev->parent);
> > + u32 tmp;
> > +
> > + if (!priv->cursor_visible)
> > + return;
> > +
> > + if (state) {
> > + tmp = vid_priv->colour_bg;
> > + vid_priv->colour_bg = vid_priv->colour_fg;
> > + }
> > +
> > + vidconsole_putc_xy(dev, priv->xcur_frac, priv->ycur, ' ');
> > +
> > + if (state)
> > + vid_priv->colour_bg = tmp;
> > +}
> > +
> > /* Move backwards one space */
> > static int vidconsole_back(struct udevice *dev)
> > {
> > @@ -77,6 +97,8 @@ static int vidconsole_back(struct udevice *dev)
> > struct vidconsole_ops *ops = vidconsole_get_ops(dev);
> > int ret;
> >
> > + draw_cursor(dev, false);
> > +
> > if (ops->backspace) {
> > ret = ops->backspace(dev);
> > if (ret != -ENOSYS)
> > @@ -103,6 +125,8 @@ static void vidconsole_newline(struct udevice *dev)
> > const int rows = CONFIG_CONSOLE_SCROLL_LINES;
> > int i, ret;
> >
> > + draw_cursor(dev, false);
> > +
> > priv->xcur_frac = priv->xstart_frac;
> > priv->ycur += priv->y_charsize;
> >
> > @@ -342,6 +366,14 @@ static void vidconsole_escape_char(struct udevice
> > *dev, char ch)
> >
> > break;
> > }
> > + case 'l':
> > + draw_cursor(dev, false);
> > + priv->cursor_visible = 0;
> > + break;
> > + case 'h':
> > + priv->cursor_visible = 1;
> > + draw_cursor(dev, true);
> > + break;
> > case 'J': {
> > int mode;
> >
> > @@ -516,6 +548,11 @@ int vidconsole_put_char(struct udevice *dev, char ch)
> > struct vidconsole_priv *priv = dev_get_uclass_priv(dev);
> > int ret;
> >
> > + /*
> > +* We don't need to clear the cursor since we are going to overwrite
> > +* that character anyway.
> > +*/
> > +
> > if (priv->escape) {
> > vidconsole_escape_char(dev, ch);
> > return 0;
> > @@ -530,6 +567,7 @@ int vidconsole_put_char(struct udevice *dev, char ch)
> > /* beep */
> > break;
> > case '\r':
> > + draw_cursor(dev, false);
> > priv->xcur_frac = priv->xstart_frac;
> > break;
> > case '\n':
> > @@ -537,6 +575,7 @@ int vidconsole_put_char(struct udevice *dev, char ch)
> > vidconsole_entry_start(dev);
> > break;
> > case '\t': /* Tab (8 chars alignment) */
> > + draw_cursor(dev, false);
> > priv->xcur_frac = ((priv->xcur_frac / priv->tab_width_frac)
> > + 1) * priv->tab_width_frac;
[PATCH v8 00/15] Add CAAM driver model support
This patchset adds the support for following: 1) CAAM Driver model for all i.MX, layerscape, PPC platforms. 2) Added crypto node in device tree files. 3) fix build issue for mx6sabre: Remove SPL DTB related configs and SPL_OF_CONTROL. 4) improve hwrng performance in kernel. i.MX platforms: i.MX6, i.MX7, i.MX7ULP, i.MX8MM/MN/MP/MQ, i.MX8QM/QXP Layerscape platforms: LS1021, LS1012, LS1028, LS1043, LS1046, LS1088, LS2088, LX2160, LX2162 Powerpc platforms: P3041, P4080, P5040, P2041, T1024, T1042, T2080, T4240 changes since v7: - rebase to latest master - corrected the order of include files as per coding style in jr.c. https://www.denx.de/wiki/U-Boot/CodingStyle - added brackets around #defines for -ve number in jr.h - added comments for struct caam_regs added in jr.h changes since v6: - rebase to latest master - added caam_jr_ioctl() operation which calls run_descriptor_jr(). - removed CONFIG_ARCH_IMX8 config from JR driver. - removed FSL_BLOB config changes since v5: - rebase to latest master - updated BIT() macro for JRDID in drivers/crypto/fsl/jr.h - removed auto select FSL_BLOB from CMD_BLOB config. - removed patch for blob key encryption key(bkek), random number generation. - updated patch description for improving hwrng performance in kernel. - removed sec_init() from kontron/sl28. - for LS1028A architecture, enable CAAM only for LS1028AQDS and LS1028ARDB. changes since v4: - rebase to latest master - updated caam_jr_probe() with livetree APIs. - imx8m: moved jr0 disable code to *-uboot.dtsi files. changes since v3: - rebase to latest master - fixed build error when new file arch/powerpc/include/asm/u-boot-ppc.h is included from assembly files. - removed arch/arm/dts/fsl-ls1028a.dtsi as it is conflicting with the series https://lore.kernel.org/u-boot/20211013161427.612033-1-mich...@walle.cc/ Gaurav Jain (13): crypto/fsl: Add support for CAAM Job ring driver model i.MX8M: crypto: updated device tree for supporting DM in SPL crypto/fsl: i.MX8M: Enable Job ring driver model. i.MX6: Enable Job ring driver model. i.MX7: Enable Job ring driver model. i.MX7ULP: Enable Job ring driver model. i.MX8: Add crypto node in device tree crypto/fsl: i.MX8: Enable Job ring driver model. Layerscape: Add crypto node in device tree Layerscape: Enable Job ring driver model. PPC: Add crypto node in device tree PPC: Enable Job ring driver model. update CAAM MAINTAINER Ye Li (2): mx6sabre: Remove unnecessary SPL configs crypto/fsl: Improve hwrng performance in kernel MAINTAINERS | 6 + arch/arm/Kconfig | 13 +- arch/arm/cpu/armv7/ls102xa/Kconfig| 3 + arch/arm/cpu/armv7/ls102xa/cpu.c | 16 + arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 + arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +- arch/arm/dts/fsl-imx8dx.dtsi | 61 ++- arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 +- arch/arm/dts/fsl-imx8qm.dtsi | 61 ++- arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 +- arch/arm/dts/fsl-ls1012a.dtsi | 46 +- arch/arm/dts/fsl-ls1043a.dtsi | 45 +- arch/arm/dts/fsl-ls1046a.dtsi | 44 ++ arch/arm/dts/fsl-ls1088a.dtsi | 39 ++ arch/arm/dts/fsl-ls2080a.dtsi | 39 ++ arch/arm/dts/fsl-lx2160a.dtsi | 41 +- arch/arm/dts/imx7ulp.dtsi | 24 + arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 +- arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 +- arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 +- arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4 + arch/arm/dts/ls1021a.dtsi | 40 ++ arch/arm/include/asm/arch-imx8/imx-regs.h | 5 +- arch/arm/include/asm/arch-imx8m/imx-regs.h| 1 + arch/arm/mach-imx/cmd_dek.c | 1 + arch/arm/mach-imx/imx8/Kconfig| 7 + arch/arm/mach-imx/imx8/cpu.c | 16 +- arch/arm/mach-imx/imx8m/Kconfig | 18 + arch/arm/mach-imx/imx8m/soc.c | 10 +- arch/arm/mach-imx/mx6/Kconfig | 15 + arch/arm/mach-imx/mx6/soc.c | 12 +- arch/arm/mach-imx/mx7/Kconfig | 2 + arch/arm/mach-imx/mx7/soc.c | 11 +- arch/arm/mach-imx/mx7ulp/Kconfig | 3 + arch/arm/mach-imx/mx7ulp/soc.c| 16 + arch/powerpc/cpu/mpc85xx/Kconfig | 33 ++ arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +- arch/powerpc/dts/p2041si-post.dtsi| 1 + arch/powerpc/dts/p3041si-post.dtsi| 1 + arch/powerpc/dts/p4080si-post.dtsi| 1 + arch/powerpc/dts/p5040si-post.dtsi| 1 + arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 +++ arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +++ arch/powerpc/dts/qoriq-sec5.2-0.dtsi
[PATCH v8 01/15] crypto/fsl: Add support for CAAM Job ring driver model
added device tree support for job ring driver.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
drivers/crypto/fsl/jr.c | 323 ++--
drivers/crypto/fsl/jr.h | 31 +++-
2 files changed, 240 insertions(+), 114 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index 22b649219e..8103987425 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2014 Freescale Semiconductor, Inc.
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
* Based on CAAM driver in drivers/crypto/caam in Linux
*/
@@ -11,7 +11,6 @@
#include
#include
#include
-#include "fsl_sec.h"
#include "jr.h"
#include "jobdesc.h"
#include "desc_constr.h"
@@ -21,7 +20,10 @@
#include
#include
#endif
+#include
#include
+#include
+#include
#include
#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
@@ -35,20 +37,29 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = {
#endif
};
+#if CONFIG_IS_ENABLED(DM)
+struct udevice *caam_dev;
+#else
#define SEC_ADDR(idx) \
(ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \
(ulong)(SEC_ADDR(idx) + \
(CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET))
+struct caam_regs caam_st;
+#endif
-struct jobring jr0[CONFIG_SYS_FSL_MAX_NUM_OF_SEC];
+static inline u32 jr_start_reg(u8 jrid)
+{
+ return (1 << jrid);
+}
-static inline void start_jr0(uint8_t sec_idx)
+static inline void start_jr(struct caam_regs *caam)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
+ ccsr_sec_t *sec = caam->sec;
u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
u32 scfgr = sec_in32(&sec->scfgr);
+ u32 jrstart = jr_start_reg(caam->jrid);
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
/* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
@@ -56,23 +67,16 @@ static inline void start_jr0(uint8_t sec_idx)
*/
if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
(scfgr & SEC_SCFGR_VIRT_EN))
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
} else {
/* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
- sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
+ sec_out32(&sec->jrstartr, jrstart);
}
}
-static inline void jr_reset_liodn(uint8_t sec_idx)
+static inline void jr_disable_irq(struct jr_regs *regs)
{
- ccsr_sec_t *sec = (void *)SEC_ADDR(sec_idx);
- sec_out32(&sec->jrliodnr[0].ls, 0);
-}
-
-static inline void jr_disable_irq(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
uint32_t jrcfg = sec_in32(®s->jrcfg1);
jrcfg = jrcfg | JR_INTMASK;
@@ -80,10 +84,10 @@ static inline void jr_disable_irq(uint8_t sec_idx)
sec_out32(®s->jrcfg1, jrcfg);
}
-static void jr_initregs(uint8_t sec_idx)
+static void jr_initregs(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx);
- struct jobring *jr = &jr0[sec_idx];
+ struct jr_regs *regs = caam->regs;
+ struct jobring *jr = &caam->jr[sec_idx];
caam_dma_addr_t ip_base = virt_to_phys((void *)jr->input_ring);
caam_dma_addr_t op_base = virt_to_phys((void *)jr->output_ring);
@@ -103,16 +107,16 @@ static void jr_initregs(uint8_t sec_idx)
sec_out32(®s->irs, JR_SIZE);
if (!jr->irq)
- jr_disable_irq(sec_idx);
+ jr_disable_irq(regs);
}
-static int jr_init(uint8_t sec_idx)
+static int jr_init(uint8_t sec_idx, struct caam_regs *caam)
{
- struct jobring *jr = &jr0[sec_idx];
+ struct jobring *jr = &caam->jr[sec_idx];
memset(jr, 0, sizeof(struct jobring));
- jr->jq_id = DEFAULT_JR_ID;
+ jr->jq_id = caam->jrid;
jr->irq = DEFAULT_IRQ;
#ifdef CONFIG_FSL_CORENET
@@ -134,53 +138,8 @@ static int jr_init(uint8_t sec_idx)
memset(jr->input_ring, 0, JR_SIZE * sizeof(caam_dma_addr_t));
memset(jr->output_ring, 0, jr->op_size);
- start_jr0(sec_idx);
-
- jr_initregs(sec_idx);
-
- return 0;
-}
-
-static int jr_sw_cleanup(uint8_t sec_idx)
-{
- struct jobring *jr = &jr0[sec_idx];
-
- jr->head = 0;
- jr->tail = 0;
- jr->read_idx = 0;
- jr->write_idx = 0;
- memset(jr->info, 0, sizeof(jr->info));
- memset(jr->input_ring, 0, jr->size * sizeof(caam_dma_addr_t));
- memset(jr->output_ring, 0, jr->size * sizeof(struct op_ring));
-
- return 0;
-}
-
-static int jr_hw_reset(uint8_t sec_idx)
-{
- struct jr_regs *regs = (struct jr_regs *)SEC_JR0_ADDR(sec_idx
[PATCH v8 02/15] i.MX8M: crypto: updated device tree for supporting DM in SPL
disabled use of JR0 in SPL and uboot, as JR0 is reserved
for secure boot.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/dts/imx8mm-evk-u-boot.dtsi | 19 ++-
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi | 19 ++-
arch/arm/dts/imx8mp-evk-u-boot.dtsi | 19 ++-
arch/arm/dts/imx8mq-evk-u-boot.dtsi | 4
4 files changed, 58 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
index 6b459831e7..e5682ca165 100644
--- a/arch/arm/dts/imx8mm-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mm-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
@@ -68,6 +68,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
index 1d3844437d..d8df863083 100644
--- a/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
/ {
@@ -104,6 +104,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&usdhc1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
index ab849ebaac..f3f83ba303 100644
--- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
@@ -67,6 +67,23 @@
u-boot,dm-spl;
};
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr0 {
+ u-boot,dm-spl;
+ status = "disabled";
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
&i2c1 {
u-boot,dm-spl;
};
diff --git a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
index 6f9c81462e..8f1f942215 100644
--- a/arch/arm/dts/imx8mq-evk-u-boot.dtsi
+++ b/arch/arm/dts/imx8mq-evk-u-boot.dtsi
@@ -10,3 +10,7 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&sec_jr0 {
+ status = "disabled";
+};
--
2.17.1
[PATCH v8 03/15] crypto/fsl: i.MX8M: Enable Job ring driver model.
i.MX8MM/MN/MP/MQ - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/Kconfig | 2 +-
arch/arm/include/asm/arch-imx8m/imx-regs.h | 1 +
arch/arm/mach-imx/imx8m/Kconfig| 18 ++
arch/arm/mach-imx/imx8m/soc.c | 10 +-
board/freescale/imx8mm_evk/spl.c | 9 -
board/freescale/imx8mn_evk/spl.c | 8 ++--
board/freescale/imx8mp_evk/spl.c | 13 +++--
board/freescale/imx8mq_evk/spl.c | 9 +++--
drivers/crypto/fsl/jr.c| 14 +++---
scripts/config_whitelist.txt | 1 +
10 files changed, 73 insertions(+), 12 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index f7f03837fe..550f884077 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -815,7 +815,7 @@ config ARCH_IMX8M
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index b800da13a1..ff8de53f67 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -72,6 +72,7 @@
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CONFIG_SYS_FSL_JR1_OFFSET (0x2000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d6a869068a..95506afd17 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -39,6 +39,10 @@ config TARGET_IMX8MQ_EVK
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@@ -52,6 +56,10 @@ config TARGET_IMX8MM_EVK
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@@ -91,6 +99,9 @@ config TARGET_IMX8MN_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@@ -98,6 +109,9 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select FSL_CAAM
+ select MISC
+ select SPL_CRYPTO if SPL
config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
@@ -105,6 +119,10 @@ config TARGET_IMX8MP_EVK
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index 863508776d..0f9bd77354 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2017-2019, 2021 NXP
*
* Peng Fan
*/
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -1197,6 +1198,13 @@ static void acquire_buildinfo(void)
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
acquire_buildinfo();
return 0;
diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c
index 4ef7f6f180..c81128f442 100644
--- a/board/freescale/imx8mm_evk/spl.c
+++ b/board/freescale/imx8mm_evk/spl.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2019 NXP
+ * Copyright 2019, 2021 NXP
*/
#include
@@ -51,6 +51,13 @@ static void spl_dram_init(void)
void spl_board_init(void)
{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
puts("Normal Boot\n");
}
diff --git a/
[PATCH v8 04/15] mx6sabre: Remove unnecessary SPL configs
From: Ye Li Because we don't use SPL_DM on mx6sabresd and mx6sabreauto, so it is unnecessary to have SPL DTB related configs and SPL_OF_CONTROL enabled. Signed-off-by: Ye Li Reviewed-by: Fabio Estevam Reviewed-by: Gaurav Jain --- configs/mx6sabreauto_defconfig | 2 -- configs/mx6sabresd_defconfig | 4 2 files changed, 6 deletions(-) diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index c5cdc3ac17..2b8b4f6b9f 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -60,10 +60,8 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6dl-sabreauto imx6q-sabreauto imx6qp-sabreauto" CONFIG_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 6733038060..f40401d279 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -63,12 +63,8 @@ CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y # CONFIG_SPL_EFI_PARTITION is not set CONFIG_OF_CONTROL=y -CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIST="imx6q-sabresd imx6qp-sabresd imx6dl-sabresd" CONFIG_MULTI_DTB_FIT=y -CONFIG_SPL_MULTI_DTB_FIT=y -CONFIG_SPL_OF_LIST="imx6dl-sabresd imx6q-sabresd imx6qp-sabresd" -CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -- 2.17.1
[PATCH v8 05/15] i.MX6: Enable Job ring driver model.
i.MX6,i.MX6SX,i.MX6UL - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/mach-imx/mx6/Kconfig | 15 +++
arch/arm/mach-imx/mx6/soc.c | 12
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 98df4d4e42..05d3fab6cb 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -354,6 +354,9 @@ config TARGET_MX6SABREAUTO
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
@@ -364,6 +367,9 @@ config TARGET_MX6SABRESD
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
@@ -386,6 +392,9 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
select SUPPORT_SPL
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
@@ -404,6 +413,9 @@ config TARGET_MX6UL_9X9_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
@@ -413,6 +425,9 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"
diff --git a/arch/arm/mach-imx/mx6/soc.c b/arch/arm/mach-imx/mx6/soc.c
index aacfc854a2..fa6c3778bb 100644
--- a/arch/arm/mach-imx/mx6/soc.c
+++ b/arch/arm/mach-imx/mx6/soc.c
@@ -4,6 +4,7 @@
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include
@@ -23,7 +24,6 @@
#include
#include
#include
-#include
#include
#include
@@ -734,9 +734,13 @@ static void setup_serial_number(void)
int arch_misc_init(void)
{
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
setup_serial_number();
return 0;
}
--
2.17.1
[PATCH v8 06/15] i.MX7: Enable Job ring driver model.
i.MX7D - added support for JR driver model.
removed sec_init() call, sec is initialized based on
job ring information processed from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/Kconfig | 2 +-
arch/arm/mach-imx/mx7/Kconfig | 2 ++
arch/arm/mach-imx/mx7/soc.c | 11 +++
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 550f884077..516e1b5a8f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -883,7 +883,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 0cad825287..b2d532dacd 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -68,6 +68,8 @@ config TARGET_MX7DSABRESD
select DM_THERMAL
select MX7D
imply CMD_DM
+ select FSL_CAAM
+ select MISC
config TARGET_PICO_IMX7D
bool "pico-imx7d"
diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
index 21690072e1..6c991a6cb1 100644
--- a/arch/arm/mach-imx/mx7/soc.c
+++ b/arch/arm/mach-imx/mx7/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include
@@ -19,7 +20,6 @@
#include
#include
#include
-#include
#include
#include
@@ -337,6 +337,9 @@ int arch_cpu_init(void)
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
+ struct udevice *dev;
+ int ret;
+
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
struct tag_serialnr serialnr;
char serial_string[0x20];
@@ -353,9 +356,9 @@ int arch_misc_init(void)
env_set("serial#", serial_string);
#endif
-#ifdef CONFIG_FSL_CAAM
- sec_init();
-#endif
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
return 0;
}
--
2.17.1
[PATCH v8 07/15] i.MX7ULP: Enable Job ring driver model.
added crypto node in device tree.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/Kconfig | 2 +-
arch/arm/dts/imx7ulp.dtsi| 24
arch/arm/mach-imx/mx7ulp/Kconfig | 3 +++
arch/arm/mach-imx/mx7ulp/soc.c | 16
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 516e1b5a8f..524a2204eb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -870,7 +870,7 @@ config ARCH_MX7ULP
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
- select SYS_FSL_HAS_SEC if IMX_HAB
+ select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 7bcd2cc346..494b9d98b2 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -1,5 +1,6 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -198,6 +199,29 @@
};
};
+ crypto: crypto@4024 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x4024 0x1>;
+ ranges = <0 0x4024 0x1>;
+ clocks = <&clks IMX7ULP_CLK_CAAM>,
+<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
+ clock-names = "aclk", "ipg";
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = ;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = ;
+ };
+ };
+
tpm5: tpm@4026 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x4026 0x1000>;
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index 2ffac9cf7c..fbd2de5e3d 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -25,6 +25,9 @@ config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
endchoice
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index c90ce22404..c1e55e7260 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include
@@ -15,6 +16,7 @@
#include
#include
#include
+#include
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
@@ -80,6 +82,20 @@ int arch_cpu_init(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
--
2.17.1
[PATCH v8 08/15] i.MX8: Add crypto node in device tree
i.MX8(QM/QXP) - updated device tree for supporting DM in SPL.
disabled use of JR1 in SPL and uboot, as JR1 is reserved
for SECO FW.
Signed-off-by: Gaurav Jain
Reviewed-by: Ye Li
---
arch/arm/dts/fsl-imx8dx.dtsi | 61 +++-
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi | 34 -
arch/arm/dts/fsl-imx8qm.dtsi | 61 +++-
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi | 34 -
4 files changed, 186 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/fsl-imx8dx.dtsi b/arch/arm/dts/fsl-imx8dx.dtsi
index 7d95cf0b7d..63a56699b5 100644
--- a/arch/arm/dts/fsl-imx8dx.dtsi
+++ b/arch/arm/dts/fsl-imx8dx.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include
@@ -261,6 +261,30 @@
power-domains = <&pd_dma>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = ;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr2: PD_CAAM_JR2 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ pd_caam_jr3: PD_CAAM_JR3 {
+ reg = ;
+ #power-domain-cells = <0>;
+ power-domains = <&pd_caam>;
+ };
+ };
};
i2c0: i2c@5a80 {
@@ -609,6 +633,41 @@
};
};
};
+
+ crypto: caam@0x3140 {
+ compatible = "fsl,sec-v4.0";
+ reg = <0 0x3140 0 0x40>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x3140 0x40>;
+ fsl,first-jr-index = <2>;
+ fsl,sec-era = <9>;
+
+ sec_jr1: jr1@0x2 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2 0x1000>;
+ interrupts = ;
+ power-domains = <&pd_caam_jr1>;
+ status = "disabled";
+ };
+
+ sec_jr2: jr2@3 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3 0x1000>;
+ interrupts = ;
+ power-domains = <&pd_caam_jr2>;
+ status = "okay";
+ };
+
+ sec_jr3: jr3@4 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4 0x1000>;
+ interrupts = ;
+ power-domains = <&pd_caam_jr3>;
+ status = "okay";
+ };
+ };
};
&A35_0 {
diff --git a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
index 9e0d264b71..a95209e141 100644
--- a/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
+++ b/arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
@@ -80,6 +80,22 @@
u-boot,dm-spl;
};
+&pd_caam {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr1 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr2 {
+ u-boot,dm-spl;
+};
+
+&pd_caam_jr3 {
+ u-boot,dm-spl;
+};
+
&gpio0 {
u-boot,dm-spl;
};
@@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
+
+&crypto {
+ u-boot,dm-spl;
+};
+
+&sec_jr1 {
+ u-boot,dm-spl;
+};
+
+&sec_jr2 {
+ u-boot,dm-spl;
+};
+
+&sec_jr3 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/fsl-imx8qm.dtsi b/arch/arm/dts/fsl-imx8qm.dtsi
index 88aeaf65b3..517fb13cad 100644
--- a/arch/arm/dts/fsl-imx8qm.dtsi
+++ b/arch/arm/dts/fsl-imx8qm.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include
@@ -235,6 +235,30 @@
wakeup-irq = <349>;
};
};
+
+ pd_caam: PD_CAAM {
+ compatible = "nxp,imx8-pd";
+ reg = ;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_caam_jr1: PD_CAAM_JR1 {
+ reg = ;
+
[PATCH v8 09/15] crypto/fsl: i.MX8: Enable Job ring driver model.
i.MX8(QM/QXP) - added support for JR driver model.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Signed-off-by: Horia Geantă
Reviewed-by: Ye Li
---
arch/arm/Kconfig | 3 ++
arch/arm/include/asm/arch-imx8/imx-regs.h | 5 ++-
arch/arm/mach-imx/cmd_dek.c | 1 +
arch/arm/mach-imx/imx8/Kconfig| 7
arch/arm/mach-imx/imx8/cpu.c | 16 +++-
board/freescale/imx8qm_mek/spl.c | 6 ++-
board/freescale/imx8qxp_mek/spl.c | 6 ++-
drivers/crypto/fsl/Kconfig| 2 +-
drivers/crypto/fsl/jr.c | 47 ++-
include/fsl_sec.h | 12 +++---
10 files changed, 89 insertions(+), 16 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 524a2204eb..7ce2bbc954 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -804,6 +804,9 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
+ select SYS_FSL_HAS_SEC
+ select SYS_FSL_SEC_COMPAT_4
+ select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h
b/arch/arm/include/asm/arch-imx8/imx-regs.h
index ed6e05e556..2d64b0604b 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d
#define USB_PHY0_BASE_ADDR 0x5b10
+#define CONFIG_SYS_FSL_SEC_ADDR (0x3140)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 89da89c51d..04c4b20a84 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index b43739e5c6..f969833bab 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -8,6 +8,7 @@ config AHAB_BOOT
config IMX8
bool
+ select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
@@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
@@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
+ select FSL_CAAM
+ select ARCH_MISC_INIT
+ select SPL_CRYPTO if SPL
endchoice
diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c
index ee5cc47903..5140c93a37 100644
--- a/arch/arm/mach-imx/imx8/cpu.c
+++ b/arch/arm/mach-imx/imx8/cpu.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*/
#include
@@ -89,6 +89,20 @@ int arch_cpu_init_dm(void)
return 0;
}
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
+
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();
diff --git a/board/freescale/imx8qm_mek/spl.c b/board/freescale/imx8qm_mek/spl.c
index 944ba745c0..332a662dee 100644
--- a/board/freescale/imx8qm_mek/spl.c
+++ b/board/freescale/imx8qm_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier:GPL-2.0+
*/
#include
@@ -24,6 +24,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLASS_MISC, &dev);
for (; dev; uclass_find_next_device(&dev)) {
diff --git a/board/freescale/imx8qxp_mek/spl.c
b/board/freescale/imx8qxp_mek/spl.c
index ae6b64ff6e..2fa6840056 100644
--- a/board/freescale/imx8qxp_mek/spl.c
+++ b/board/freescale/imx8qxp_mek/spl.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Copyright 2018 NXP
+ * Copyright 2018, 2021 NXP
*
- * SPDX-License-Identifier:GPL-2.0+
*/
#include
@@ -39,6 +39,8 @@ void spl_board_init(void)
{
struct udevice *dev;
+ uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(imx8_scu), &dev);
+
uclass_find_first_device(UCLAS
[PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
From: Ye Li
RNG parameters are reconfigured.
- For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
number of entropy samples that will be taken during Entropy generation.
- self-test registers(Monobit Limit, Poker Range, Run Length Limit)
are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
TRNG time is caluculated based on sample size.
time required to generate entropy is reduced and
hwrng performance improved from 0.3 kB/s to 1.3 kB/s.
Signed-off-by: Ye Li
Acked-by: Gaurav Jain >
---
drivers/crypto/fsl/jr.c | 102 +---
include/fsl_sec.h | 1 +
2 files changed, 87 insertions(+), 16 deletions(-)
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
index a84440ab10..e5346a84a4 100644
--- a/drivers/crypto/fsl/jr.c
+++ b/drivers/crypto/fsl/jr.c
@@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
*/
static void kick_trng(int ent_delay, ccsr_sec_t *sec)
{
+ u32 samples = 512; /* number of bits to generate and test */
+ u32 mono_min = 195;
+ u32 mono_max = 317;
+ u32 mono_range = mono_max - mono_min;
+ u32 poker_min = 1031;
+ u32 poker_max = 1600;
+ u32 poker_range = poker_max - poker_min + 1;
+ u32 retries= 2;
+ u32 lrun_max = 32;
+ s32 run_1_min = 27;
+ s32 run_1_max = 107;
+ s32 run_1_range = run_1_max - run_1_min;
+ s32 run_2_min = 7;
+ s32 run_2_max = 62;
+ s32 run_2_range = run_2_max - run_2_min;
+ s32 run_3_min = 0;
+ s32 run_3_max = 39;
+ s32 run_3_range = run_3_max - run_3_min;
+ s32 run_4_min = -1;
+ s32 run_4_max = 26;
+ s32 run_4_range = run_4_max - run_4_min;
+ s32 run_5_min = -1;
+ s32 run_5_max = 18;
+ s32 run_5_range = run_5_max - run_5_min;
+ s32 run_6_min = -1;
+ s32 run_6_max = 17;
+ s32 run_6_range = run_6_max - run_6_min;
+ u32 val;
+
struct rng4tst __iomem *rng =
(struct rng4tst __iomem *)&sec->rng;
- u32 val;
- /* put RNG4 into program mode */
- sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
- /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
-* length (in system clocks) of each Entropy sample taken
-* */
+ /* Put RNG in program mode */
+ /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
+* properly invalidate the entropy in the entropy register and
+* force re-generation.
+*/
+ sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+
+ /* Configure the RNG Entropy Delay
+* Performance-wise, it does not make sense to
+* set the delay to a value that is lower
+* than the last one that worked (i.e. the state handles
+* were instantiated properly. Thus, instead of wasting
+* time trying to set the values controlling the sample
+* frequency, the function simply returns.
+*/
val = sec_in32(&rng->rtsdctl);
- val = (val & ~RTSDCTL_ENT_DLY_MASK) |
- (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
+ val &= RTSDCTL_ENT_DLY_MASK;
+ val >>= RTSDCTL_ENT_DLY_SHIFT;
+ if (ent_delay < val) {
+ /* Put RNG4 into run mode */
+ sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
+ return;
+ }
+
+ val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
sec_out32(&rng->rtsdctl, val);
- /* min. freq. count, equal to 1/4 of the entropy sample length */
- sec_out32(&rng->rtfreqmin, ent_delay >> 2);
- /* disable maximum frequency count */
- sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
+
+ /*
+* Recommended margins (min,max) for freq. count:
+* freq_mul = RO_freq / TRNG_clk_freq
+* rtfrqmin = (ent_delay x freq_mul) >> 1;
+* rtfrqmax = (ent_delay x freq_mul) << 3;
+* Given current deployments of CAAM in i.MX SoCs, and to simplify
+* the configuration, we consider [1,16] to be a safe interval
+* for the freq_mul and the limits of the interval are used to compute
+* rtfrqmin, rtfrqmax
+*/
+ sec_out32(&rng->rtfreqmin, ent_delay >> 1);
+ sec_out32(&rng->rtfreqmax, ent_delay << 7);
+
+ sec_out32(&rng->rtscmisc, (retries << 16) | lrun_max);
+ sec_out32(&rng->rtpkrmax, poker_max);
+ sec_out32(&rng->rtpkrrng, poker_range);
+ sec_out32(&rng->rsvd1[0], (mono_range << 16) | mono_max);
+ sec_out32(&rng->rsvd1[1], (run_1_range << 16) | run_1_max);
+ sec_out32(&rng->rsvd1[2], (run_2_range << 16) | run_2_max);
+ sec_out32(&rng->rsvd1[3], (run_3_range << 16) | run_3_max);
+ sec_out32(&rng->rsvd1[4], (run_4_range << 16) | run_4_max);
+ sec_out32(&rng->rsvd1[5], (run_5_range << 16) | run_5_max);
+ se
[PATCH v8 11/15] Layerscape: Add crypto node in device tree
LS(1021/1012/1028/1043/1046/1088/2088), LX2160 - updated device tree
Signed-off-by: Gaurav Jain
Reviewed-by: Priyanka Jain
---
arch/arm/dts/fsl-ls1012a.dtsi | 46 ++-
arch/arm/dts/fsl-ls1043a.dtsi | 45 +-
arch/arm/dts/fsl-ls1046a.dtsi | 44 +
arch/arm/dts/fsl-ls1088a.dtsi | 39 +
arch/arm/dts/fsl-ls2080a.dtsi | 39 +
arch/arm/dts/fsl-lx2160a.dtsi | 41 ++-
arch/arm/dts/ls1021a.dtsi | 40 ++
7 files changed, 291 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..1cdcc99c1e 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@@ -71,6 +71,50 @@
bus-width = <4>;
};
+ crypto: crypto@170 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+"fsl,sec-v4.0";
+ fsl,sec-era = <8>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x170 0x10>;
+ reg = <0x00 0x170 0x0 0x10>;
+ interrupts = <0 75 0x4>;
+ dma-coherent;
+
+ sec_jr0: jr@1 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-ring";
+ reg= <0x1 0x1>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@2 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-ring";
+ reg= <0x2 0x1>;
+ interrupts = <0 72 0x4>;
+ };
+
+ sec_jr2: jr@3 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-ring";
+ reg= <0x3 0x1>;
+ interrupts = <0 73 0x4>;
+ };
+
+ sec_jr3: jr@4 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-ring";
+ reg= <0x4 0x1>;
+ interrupts = <0 74 0x4>;
+ };
+ };
+
gpio0: gpio@230 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x230 0x0 0x1>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..72877d2ff5 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu
@@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
+ crypto: crypto@170 {
+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
+"fsl,sec-v4.0";
+ fsl,sec-era = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x00 0x170 0x10>;
+ reg = <0x00 0x170 0x0 0x10>;
+ interrupts = <0 75 0x4>;
+
+ sec_jr0: jr@1 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-ring";
+ reg= <0x1 0x1>;
+ interrupts = <0 71 0x4>;
+ };
+
+ sec_jr1: jr@2 {
+ compatible = "fsl,sec-v5.4-job-ring",
+"fsl,sec-v5.0-job-ring",
+"fsl,sec-v4.0-job-
[PATCH v8 12/15] Layerscape: Enable Job ring driver model.
LS(1021/1012/1028/1043/1046/1088/2088), LX2160, LX2162
platforms are enabled with JR driver model.
removed sec_init() call from board files.
removed CONFIG_FSL_CAAM from defconfig files.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Priyanka Jain
---
arch/arm/Kconfig| 4
arch/arm/cpu/armv7/ls102xa/Kconfig | 3 +++
arch/arm/cpu/armv7/ls102xa/cpu.c| 16
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 17 +
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 10 +-
board/freescale/ls1012afrdm/ls1012afrdm.c | 7 +--
board/freescale/ls1012aqds/ls1012aqds.c | 6 +-
board/freescale/ls1012ardb/ls1012ardb.c | 6 +-
board/freescale/ls1021aiot/ls1021aiot.c | 6 ++
board/freescale/ls1021aqds/ls1021aqds.c | 6 +-
board/freescale/ls1021atsn/ls1021atsn.c | 7 ++-
board/freescale/ls1021atwr/ls1021atwr.c | 8 ++--
board/freescale/ls1028a/ls1028a.c | 6 +-
board/freescale/ls1043ardb/ls1043ardb.c | 6 +-
board/freescale/ls1046afrwy/ls1046afrwy.c | 7 +--
board/freescale/ls1046aqds/ls1046aqds.c | 7 +--
board/freescale/ls1046ardb/ls1046ardb.c | 6 +-
board/freescale/ls1088a/ls1088a.c | 6 +-
board/freescale/ls2080aqds/ls2080aqds.c | 6 +-
board/freescale/ls2080ardb/ls2080ardb.c | 9 +
board/freescale/lx2160a/lx2160a.c | 5 -
board/kontron/sl28/sl28.c | 3 ---
configs/ls1021aiot_qspi_defconfig | 1 -
configs/ls1021aqds_nor_defconfig| 1 -
configs/ls1021aqds_qspi_defconfig | 1 -
configs/ls1021atsn_qspi_defconfig | 1 -
configs/ls1021atwr_nor_defconfig| 1 -
.../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 +
configs/ls1028ardb_tfa_defconfig| 1 -
configs/ls1043ardb_tfa_defconfig| 1 -
configs/ls1046afrwy_tfa_defconfig | 1 -
configs/ls1046aqds_tfa_defconfig| 1 -
configs/ls1046ardb_tfa_defconfig| 1 -
configs/ls2088aqds_tfa_defconfig| 1 -
configs/ls2088ardb_tfa_defconfig| 1 -
configs/lx2160aqds_tfa_defconfig| 1 -
configs/lx2160ardb_tfa_defconfig| 1 -
configs/lx2162aqds_tfa_defconfig| 1 -
38 files changed, 68 insertions(+), 105 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7ce2bbc954..30a34bdd08 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select MISC
help
Support for Freescale LS1028AQDS platform
The LS1028A Development System (QDS) is a high-performance
@@ -1518,6 +1520,8 @@ config TARGET_LS1028ARDB
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select GPIO_EXTRA_HEADER
+ select FSL_CAAM
+ select MISC
help
Support for Freescale LS1028ARDB platform
The LS1028A Development System (RDB) is a high-performance
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f919d02db4..ca006e069f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -21,6 +21,9 @@ config ARCH_LS1021A
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_I2C_MXC
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_PCI
imply SCSI
imply SCSI_AHCI
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index d863c9625a..4904592703 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
+ * Copyright 2021 NXP
*/
#include
@@ -20,6 +21,7 @@
#include
#include
#include
+#include
#include "fsl_epu.h"
@@ -397,3 +399,17 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
+
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf("Failed to initialize %s: %d\n", dev->name, ret);
+
+ return 0;
+}
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 1a057f7059..75d9876dfc 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8
[PATCH v8 13/15] PPC: Add crypto node in device tree
device tree imported from linux kernel.
c500bee1c5b2 (tag: v5.14-rc4) Linux 5.14-rc4
Signed-off-by: Gaurav Jain
Reviewed-by: Priyanka Jain
---
arch/powerpc/dts/p2041si-post.dtsi | 1 +
arch/powerpc/dts/p3041si-post.dtsi | 1 +
arch/powerpc/dts/p4080si-post.dtsi | 1 +
arch/powerpc/dts/p5040si-post.dtsi | 1 +
arch/powerpc/dts/qoriq-sec4.0-0.dtsi | 74 ++
arch/powerpc/dts/qoriq-sec4.2-0.dtsi | 83 +
arch/powerpc/dts/qoriq-sec5.2-0.dtsi | 92
arch/powerpc/dts/t1023si-post.dtsi | 1 +
arch/powerpc/dts/t1042si-post.dtsi | 1 +
arch/powerpc/dts/t2080si-post.dtsi | 1 +
arch/powerpc/dts/t4240si-post.dtsi | 1 +
11 files changed, 257 insertions(+)
create mode 100644 arch/powerpc/dts/qoriq-sec4.0-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec4.2-0.dtsi
create mode 100644 arch/powerpc/dts/qoriq-sec5.2-0.dtsi
diff --git a/arch/powerpc/dts/p2041si-post.dtsi
b/arch/powerpc/dts/p2041si-post.dtsi
index 01ab395950..8819199646 100644
--- a/arch/powerpc/dts/p2041si-post.dtsi
+++ b/arch/powerpc/dts/p2041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p3041si-post.dtsi
b/arch/powerpc/dts/p3041si-post.dtsi
index 21f322f06f..a3e8088d25 100644
--- a/arch/powerpc/dts/p3041si-post.dtsi
+++ b/arch/powerpc/dts/p3041si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p4080si-post.dtsi
b/arch/powerpc/dts/p4080si-post.dtsi
index 7c3f2fb92e..56b79b14f4 100644
--- a/arch/powerpc/dts/p4080si-post.dtsi
+++ b/arch/powerpc/dts/p4080si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/p5040si-post.dtsi
b/arch/powerpc/dts/p5040si-post.dtsi
index 1efad2d017..fae3ed31a5 100644
--- a/arch/powerpc/dts/p5040si-post.dtsi
+++ b/arch/powerpc/dts/p5040si-post.dtsi
@@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
+/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
diff --git a/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
new file mode 100644
index 00..ff348d70f1
--- /dev/null
+++ b/arch/powerpc/dts/qoriq-sec4.0-0.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
+/*
+ * QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x30 ]
+ *
+ * Copyright 2011 Freescale Semiconductor Inc.
+ */
+
+crypto: crypto@30 {
+ compatible = "fsl,sec-v4.0";
+ fsl,sec-era = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30 0x1>;
+ ranges = <0 0x30 0x1>;
+ interrupts = <92 2 0 0>;
+
+ sec_jr0: jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2 0 0>;
+ };
+
+ sec_jr1: jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2 0 0>;
+ };
+
+ sec_jr2: jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2 0 0>;
+ };
+
+ sec_jr3: jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2 0 0>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic_a: rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20 0x100 0x80>;
+ };
+
+ rtic_b: rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20 0x200 0x80>;
+ };
+
+ rtic_c: rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20 0x300 0x80>;
+ };
+
+ rtic_d: rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20 0x500 0x80>;
+ };
+ };
+};
+
+sec_mon: sec_mon@314000 {
+ compatible = "fsl,sec-v4.0-mon";
+ reg = <0x314000 0x1000>;
+ interrupts = <93 2 0 0>;
+};
diff --git a/arch/powerpc/dts/qoriq-sec4.2-0.dtsi
b/arch/powerpc/dts/qoriq-sec
[PATCH v8 14/15] PPC: Enable Job ring driver model.
removed sec_init() call and CONFIG_FSL_CAAM from defconfig.
sec is initialized based on job ring information processed
from device tree.
Signed-off-by: Gaurav Jain
Reviewed-by: Priyanka Jain
---
arch/powerpc/cpu/mpc85xx/Kconfig | 33 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 --
arch/powerpc/include/asm/u-boot-ppc.h | 17 ++
arch/powerpc/include/asm/u-boot.h | 1 +
configs/P2041RDB_defconfig| 1 -
configs/P3041DS_defconfig | 1 -
configs/P4080DS_defconfig | 1 -
configs/P5040DS_defconfig | 1 -
configs/T1024RDB_defconfig| 1 -
configs/T1042D4RDB_defconfig | 1 -
configs/T2080QDS_defconfig| 1 -
configs/T2080RDB_defconfig| 1 -
configs/T2080RDB_revD_defconfig | 1 -
configs/T4240RDB_defconfig| 1 -
14 files changed, 66 insertions(+), 12 deletions(-)
create mode 100644 arch/powerpc/include/asm/u-boot-ppc.h
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 836aeddbe2..b05c372086 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -25,6 +25,9 @@ config TARGET_P3041DS
select PHYS_64BIT
select ARCH_P3041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -33,6 +36,9 @@ config TARGET_P4080DS
select PHYS_64BIT
select ARCH_P4080
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -41,6 +47,9 @@ config TARGET_P5040DS
select PHYS_64BIT
select ARCH_P5040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -102,6 +111,9 @@ config TARGET_P2041RDB
select ARCH_P2041
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply FSL_SATA
@@ -117,6 +129,9 @@ config TARGET_T1024RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_EEPROM
imply PANIC_HANG
@@ -126,6 +141,9 @@ config TARGET_T1042RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
config TARGET_T1042D4RDB
bool "Support T1042D4RDB"
@@ -133,6 +151,9 @@ config TARGET_T1042D4RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T1042RDB_PI
@@ -141,6 +162,9 @@ config TARGET_T1042RDB_PI
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply PANIC_HANG
config TARGET_T2080QDS
@@ -151,6 +175,9 @@ config TARGET_T2080QDS
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
config TARGET_T2080RDB
@@ -159,6 +186,9 @@ config TARGET_T2080RDB
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
@@ -168,6 +198,9 @@ config TARGET_T4240RDB
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
+ select FSL_CAAM
+ select MISC
+ select ARCH_MISC_INIT
imply CMD_SATA
imply PANIC_HANG
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index e920e01b25..728c6447a8 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include
#endif
+#include
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@@ -974,8 +975,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
- sec_init();
-
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@@ -1014,6 +1013,20 @@ int cpu_init_r(void)
return 0;
}
+#ifdef CONFIG_ARCH_MISC_INIT
+int arch_misc_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr),
&dev);
+ if (ret)
+ printf
[PATCH v8 15/15] update CAAM MAINTAINER
updated CAAM driver files maintainer. Signed-off-by: Gaurav Jain --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 90666ce376..622725aa64 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1312,3 +1312,9 @@ T:git https://source.denx.de/u-boot/u-boot.git F: configs/tools-only_defconfig F: * F: */ + +CAAM +M: Gaurav Jain +S: Maintained +F: drivers/crypto/fsl/ +F: include/fsl_sec.h -- 2.17.1
Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
Hi, please keep me on CC for these series, as there were comments from me on previous versions. Thanks. .. > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 7ce2bbc954..30a34bdd08 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS > select ARCH_SUPPORT_TFABOOT > select BOARD_LATE_INIT > select GPIO_EXTRA_HEADER > + select FSL_CAAM > + select MISC This looks wrong. FSL_CAAM should depend on MISC, no? > help > Support for Freescale LS1028AQDS platform > The LS1028A Development System (QDS) is a high-performance > @@ -1518,6 +1520,8 @@ config TARGET_LS1028ARDB > select ARCH_SUPPORT_TFABOOT > select BOARD_LATE_INIT > select GPIO_EXTRA_HEADER > + select FSL_CAAM > + select MISC > help > Support for Freescale LS1028ARDB platform > The LS1028A Development System (RDB) is a high-performance > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig > b/arch/arm/cpu/armv7/ls102xa/Kconfig > index f919d02db4..ca006e069f 100644 > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig > @@ -21,6 +21,9 @@ config ARCH_LS1021A > select SYS_FSL_SRDS_1 > select SYS_HAS_SERDES > select SYS_I2C_MXC > + select FSL_CAAM While above you added that dependency to an indivdual board, here you are adding that dependency to all boards using this architecture. The same is true for all the other "config ARCH_*" symbols. What if someone wants to build a bootloader without CAAM support? This should really go into the defconfigs for these boards. -michael
Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
I tested this patch and tried to run it on my LicheePi Nano. It works, but I found there is WARNINGs when compile the code: --- include/configs/sunxi-common.h:128:0: warning: "CONFIG_ENV_SECT_SIZE" redefined #define CONFIG_ENV_SECT_SIZE 0x1000 In file included from ././include/linux/kconfig.h:4:0, from :0: include/generated/autoconf.h:296:0: note: this is the location of the previous definition #define CONFIG_ENV_SECT_SIZE 0x1 In file included from include/configs/suniv.h:12:0, from include/config.h:4, from include/common.h:16, from lib/slre.c:24: And I think the problem is the CONFIG_ENV_SECT_SIZE should be (and required to) defined in the config file rather than at include/configs/sunxi-common.h:128
[PATCH v7 2/2] board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor.
Signed-off-by: Heiko Thiery
---
v7:
- add external blob entry for HDMI firmware
v6:
- increase PHY_ANEG_TIMEOUT
- spl: print boot source on startup
- spl: remove PMIC output
- enable CONFIG_CMD_TIME
v5:
- save env in eMMC boot partition 0
v4: update board integration
- migrate to IMX_CONFIG
- convert config options to Kconfig
- CONFIG_POWER_I2C
- CONFIG_SPL_POWER_I2C
- CONFIG_POWER_LEGACY
- CONFIG_SYS_LOAD_ADDR
- CONFIG_SYS_I2C_MXC
- CONFIG_SYS_I2C_LEGACY
- CONFIG_SYS_I2C_MXC_I2C1
- CONFIG_SYS_I2C_MXC_I2C2
- CONFIG_SYS_I2C_MXC_I2C3
- CONFIG_SYS_LOAD_ADDR
- CONFIG_MXC_GPIO
v3:
- enable EFI capsule support
- add update FIT image creation to binman config
- change env offset to fit into eMMC boot partition
v2:
- add support for 2/4GB variant
- enable config options
- CONFIG_CMD_GPT
- CONFIG_DM_ETH_PHY
- CONFIG_EFI_SET_TIME
- add pxefile_addr_r env variable
.../dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi | 169 ++
arch/arm/mach-imx/imx8m/Kconfig |7 +
board/kontron/pitx_imx8m/Kconfig | 15 +
board/kontron/pitx_imx8m/MAINTAINERS |7 +
board/kontron/pitx_imx8m/Makefile |8 +
board/kontron/pitx_imx8m/imximage.cfg |5 +
board/kontron/pitx_imx8m/lpddr4_timing_2gb.c | 1853 +
board/kontron/pitx_imx8m/lpddr4_timing_4gb.c | 1853 +
board/kontron/pitx_imx8m/pitx_imx8m.c | 156 ++
board/kontron/pitx_imx8m/spl.c| 327 +++
configs/kontron_pitx_imx8m_defconfig | 87 +
doc/board/kontron/index.rst |1 +
doc/board/kontron/pitx-imx8m.rst | 67 +
include/configs/kontron_pitx_imx8m.h | 111 +
14 files changed, 4666 insertions(+)
create mode 100644 arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
create mode 100644 board/kontron/pitx_imx8m/Kconfig
create mode 100644 board/kontron/pitx_imx8m/MAINTAINERS
create mode 100644 board/kontron/pitx_imx8m/Makefile
create mode 100644 board/kontron/pitx_imx8m/imximage.cfg
create mode 100644 board/kontron/pitx_imx8m/lpddr4_timing_2gb.c
create mode 100644 board/kontron/pitx_imx8m/lpddr4_timing_4gb.c
create mode 100644 board/kontron/pitx_imx8m/pitx_imx8m.c
create mode 100644 board/kontron/pitx_imx8m/spl.c
create mode 100644 configs/kontron_pitx_imx8m_defconfig
create mode 100644 doc/board/kontron/pitx-imx8m.rst
create mode 100644 include/configs/kontron_pitx_imx8m.h
diff --git a/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
new file mode 100644
index 00..e367b5d5df
--- /dev/null
+++ b/arch/arm/dts/imx8mq-kontron-pitx-imx8m-u-boot.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+#include
+
+/ {
+ binman: binman {
+ multiple-images;
+ };
+};
+
+&binman {
+ u-boot-spl-ddr {
+ filename = "u-boot-spl-ddr.bin";
+ pad-byte = <0xff>;
+ align-size = <4>;
+ align = <4>;
+
+ u-boot-spl {
+ align-end = <4>;
+ };
+
+ blob_1: blob-ext@1 {
+ filename = "lpddr4_pmu_train_1d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_2: blob-ext@2 {
+ filename = "lpddr4_pmu_train_1d_dmem.bin";
+ size = <0x4000>;
+ };
+
+ blob_3: blob-ext@3 {
+ filename = "lpddr4_pmu_train_2d_imem.bin";
+ size = <0x8000>;
+ };
+
+ blob_4: blob-ext@4 {
+ filename = "lpddr4_pmu_train_2d_dmem.bin";
+ size = <0x4000>;
+ };
+ };
+
+ spl {
+ filename = "spl.bin";
+
+ mkimage {
+ args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
0x7e1000";
+
+ blob {
+ filename = "u-boot-spl-ddr.bin";
+ };
+
+ hdmi_firmware: blob-ext {
+ filename = "signed_hdmi_imx8m.bin";
+ };
+
+ };
+
+ };
+
+ itb {
+ filename = "u-boot.itb";
+
+ fit {
+ description = "Configuration to load ATF before U-Boot";
+ #address-cells = <1>;
+ fit,external-offset = ;
+
+ images {
+ uboot {
+ description = "U-Boot (64-bit)";
+ type = "standalone";
+ arch = "arm64";
+ compression = "none";
+ l
[RFC PATCH] dts: automatically build necessary .dtb files
When building for a custom board, it is quite common to maintain a private branch which include some defconfig and .dts files. But to hook up those .dts files requires modifying a file "belonging" to upstream U-Boot, the arch/*/dts/Makefile. Forward-porting that branch to a newer upstream then often results in a conflict which, while it is trivial to resolve by hand, makes it harder to have a CI do "try to build our board against latest upstream". The .config usually includes information on precisely what .dtb(s) are needed, so to avoid having to modify the Makefile, simply add the files in (SPL_)OF_LIST to dtb-y. A technicality is that (SPL_)OF_LIST is not always defined, so rework the Kconfig symbols so that (SPL_)OF_LIST is always defined (when (SPL_)OF_CONTROL), but only prompted for in the cases which used to be their "depends on". nios2 and microblaze already have something like this in their dts/Makefile, and the rationale in commit 41f59f68539 is similar to the above. So this simply generalizes existing practice. Followup patches could remove the logic in those two makefiles, just as there's potential for moving some common boilerplate from all the arch/*/dts/Makefile files to the new scripts/Makefile.dts. Signed-off-by: Rasmus Villemoes --- arch/arc/dts/Makefile| 2 ++ arch/arm/dts/Makefile| 2 ++ arch/m68k/dts/Makefile | 2 ++ arch/microblaze/dts/Makefile | 2 ++ arch/mips/dts/Makefile | 2 ++ arch/nds32/dts/Makefile | 2 ++ arch/nios2/dts/Makefile | 2 ++ arch/powerpc/dts/Makefile| 2 ++ arch/riscv/dts/Makefile | 2 ++ arch/sandbox/dts/Makefile| 2 ++ arch/sh/dts/Makefile | 2 ++ arch/x86/dts/Makefile| 2 ++ arch/xtensa/dts/Makefile | 2 ++ dts/Kconfig | 8 scripts/Makefile.dts | 3 +++ 15 files changed, 33 insertions(+), 4 deletions(-) create mode 100644 scripts/Makefile.dts diff --git a/arch/arc/dts/Makefile b/arch/arc/dts/Makefile index 515fe1fe53..532a8131c5 100644 --- a/arch/arc/dts/Makefile +++ b/arch/arc/dts/Makefile @@ -8,6 +8,8 @@ dtb-$(CONFIG_TARGET_EMSDP) += emsdp.dtb dtb-$(CONFIG_TARGET_HSDK) += hsdk.dtb hsdk-4xd.dtb dtb-$(CONFIG_TARGET_IOT_DEVKIT) += iot_devkit.dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3e2a9c9d7..ef58be0381 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1163,6 +1163,8 @@ dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile index fdd435bc34..7988522eb9 100644 --- a/arch/m68k/dts/Makefile +++ b/arch/m68k/dts/Makefile @@ -18,6 +18,8 @@ dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/microblaze/dts/Makefile b/arch/microblaze/dts/Makefile index 4690dc1b9f..427a8f9aac 100644 --- a/arch/microblaze/dts/Makefile +++ b/arch/microblaze/dts/Makefile @@ -2,6 +2,8 @@ dtb-y += $(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)).dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 215283cfa0..95144b24dc 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -34,6 +34,8 @@ dtb-$(CONFIG_SOC_JR2) += jr2_pcb110.dtb jr2_pcb111.dtb serval2_pcb112.dtb dtb-$(CONFIG_SOC_SERVALT) += servalt_pcb116.dtb dtb-$(CONFIG_SOC_SERVAL) += serval_pcb105.dtb serval_pcb106.dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/nds32/dts/Makefile b/arch/nds32/dts/Makefile index a8e23ad9ad..5a09e3b45b 100644 --- a/arch/nds32/dts/Makefile +++ b/arch/nds32/dts/Makefile @@ -2,6 +2,8 @@ dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb dtb-$(CONFIG_TARGET_ADP_AE3XX) += ae3xx.dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/nios2/dts/Makefile b/arch/nios2/dts/Makefile index 0014acfdfb..2b29fa90f6 100644 --- a/arch/nios2/dts/Makefile +++ b/arch/nios2/dts/Makefile @@ -2,6 +2,8 @@ dtb-y += $(CONFIG_DEFAULT_DEVICE_TREE:"%"=%).dtb +include $(srctree)/scripts/Makefile.dts + targets += $(dtb-y) DTC_FLAGS += -R 4 -p 0x1000 diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index ceaa8ce5c8..6f0e4d69f2 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -29,6 +29,8 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GA
[RESEND PATCH v1] net: emaclite: fix underflow bug
This commit fixes a corner case when length < first_read. which would cause the last argument of xemaclite_alignedread to be a very large unsigned integer, resulting in an underflow Signed-off-by: Tianrui Wei --- drivers/net/xilinx_emaclite.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/xilinx_emaclite.c b/drivers/net/xilinx_emaclite.c index 43fc36dc6a..3b8f0f4678 100644 --- a/drivers/net/xilinx_emaclite.c +++ b/drivers/net/xilinx_emaclite.c @@ -526,7 +526,7 @@ try_again: } /* Read the rest of the packet which is longer then first read */ - if (length != first_read) + if (length >= first_read) xemaclite_alignedread(addr + first_read, etherrxbuff + first_read, length - first_read); -- 2.34.1
RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
Hello Gaurav,
Cc: Michael Walle
> -Original Message-
> From: U-Boot On Behalf Of Gaurav Jain
> Sent: Monday, January 10, 2022 1:27 PM
> To: u-boot@lists.denx.de
> Cc: Stefano Babic ; Fabio Estevam ; Peng
> Fan
> ; Simon Glass ; Priyanka Jain
> ; Ye Li ; Horia Geanta
> ; Ji Luo ; Franck Lenormand
> ; Silvano Di Ninno ; Sahil
> malhotra ; Pankaj Gupta ; Varun
> Sethi ; NXP i . MX U-Boot Team ; Shengzhou
> Liu ; Mingkai Hu ; Rajesh Bhagat
> ; Meenakshi Aggarwal ;
> Wasim
> Khan ; Alison Wang ; Pramod Kumar
> ; Tang Yuantian ; Adrian Alonso
> ; Vladimir Oltean
> Subject: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
>
> From: Ye Li
>
> RNG parameters are reconfigured.
> - For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
> is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
> number of entropy samples that will be taken during Entropy generation.
> - self-test registers(Monobit Limit, Poker Range, Run Length Limit)
> are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
>
> TRNG time is caluculated based on sample size.
Typo: caluculated -> calculated
> time required to generate entropy is reduced and
> hwrng performance improved from 0.3 kB/s to 1.3 kB/s.
Is there any degradation in passed/failed FIPS 140-2 test count? Can you
provide some results from at least rngtest run?
>
> Signed-off-by: Ye Li
> Acked-by: Gaurav Jain >
> ---
> drivers/crypto/fsl/jr.c | 102 +---
> include/fsl_sec.h | 1 +
> 2 files changed, 87 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c
> index a84440ab10..e5346a84a4 100644
> --- a/drivers/crypto/fsl/jr.c
> +++ b/drivers/crypto/fsl/jr.c
> @@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
> */
> static void kick_trng(int ent_delay, ccsr_sec_t *sec)
> {
> + u32 samples = 512; /* number of bits to generate and test */
> + u32 mono_min = 195;
> + u32 mono_max = 317;
> + u32 mono_range = mono_max - mono_min;
> + u32 poker_min = 1031;
> + u32 poker_max = 1600;
> + u32 poker_range = poker_max - poker_min + 1;
> + u32 retries= 2;
> + u32 lrun_max = 32;
> + s32 run_1_min = 27;
> + s32 run_1_max = 107;
> + s32 run_1_range = run_1_max - run_1_min;
> + s32 run_2_min = 7;
> + s32 run_2_max = 62;
> + s32 run_2_range = run_2_max - run_2_min;
> + s32 run_3_min = 0;
> + s32 run_3_max = 39;
> + s32 run_3_range = run_3_max - run_3_min;
> + s32 run_4_min = -1;
> + s32 run_4_max = 26;
> + s32 run_4_range = run_4_max - run_4_min;
> + s32 run_5_min = -1;
> + s32 run_5_max = 18;
> + s32 run_5_range = run_5_max - run_5_min;
> + s32 run_6_min = -1;
> + s32 run_6_max = 17;
> + s32 run_6_range = run_6_max - run_6_min;
I have a feeling that this whole block of local variables can be
simplified. I'm not sure it is required to list this so detailed.
You can attempt to define those values in header file and use
macros to compute bound conditions, rather than allocating this on
the stack here.
> + u32 val;
> +
> struct rng4tst __iomem *rng =
> (struct rng4tst __iomem *)&sec->rng;
> - u32 val;
>
> - /* put RNG4 into program mode */
> - sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
> - /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
> - * length (in system clocks) of each Entropy sample taken
> - * */
> + /* Put RNG in program mode */
> + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
> + * properly invalidate the entropy in the entropy register and
> + * force re-generation.
> + */
> + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> +
> + /* Configure the RNG Entropy Delay
> + * Performance-wise, it does not make sense to
> + * set the delay to a value that is lower
> + * than the last one that worked (i.e. the state handles
> + * were instantiated properly. Thus, instead of wasting
> + * time trying to set the values controlling the sample
> + * frequency, the function simply returns.
> + */
> val = sec_in32(&rng->rtsdctl);
> - val = (val & ~RTSDCTL_ENT_DLY_MASK) |
> - (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
> + val &= RTSDCTL_ENT_DLY_MASK;
> + val >>= RTSDCTL_ENT_DLY_SHIFT;
> + if (ent_delay < val) {
> + /* Put RNG4 into run mode */
> + sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> + return;
> + }
> +
> + val = (ent_delay << RTSDCTL_ENT_DLY_SHIFT) | samples;
> sec_out32(&rng->rtsdctl, val);
> - /* min. freq. count, equal to 1/4 of the entropy sample length */
> - sec_out32(&rng->rtfreqmin, ent_delay >> 2);
> - /* disable maximum frequency count */
> - sec_out32(&rng->rtfreqmax, RTFRQMAX_DISABLE);
> +
> + /*
>
Re: SYS_MMC_ENV_DEV wrong depend?
On Sun, Jan 09, 2022 at 10:20:03PM +, Nuno Gonçalves wrote: > Hi Tom, > > With 7d080773347c1f6e0e896d9284134a2a411155d6 you committed that > config SYS_MMC_ENV_DEV depends on ENV_IS_IN_FAT (in addition to > others). I don't see how they are related. Maybe this was a bad copy > and paste? > > When ENV_IS_IN_FAT then ENV_FAT_INTERFACE and ENV_FAT_DEVICE_AND_PART > are used instead. It's quite possible I made a mistake. It's also possible there is, or at least was, some platforms defaulting ENV_FAT_xxx to SYS_MMC_ENV_xxx so they needed to be converted. Patches to clean this up slightly welcome, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCHv3] net: uclass: Save generated ethernet MAC addresses to the environment
On Fri, Jan 07, 2022 at 04:08:34PM +0100, Michal Simek wrote:
> so 27. 11. 2021 v 20:37 odesílatel Ramon Fried napsal:
> >
> > On Mon, Nov 22, 2021 at 3:45 PM Tom Rini wrote:
> > >
> > > From: Michal Simek
> > >
> > > When a MAC address is randomly generated we currently only update the
> > > appropriate data structure. For consistency and to re-align with
> > > historic usage, it should be also saved to the appropriate environment
> > > variable as well.
> > >
> > > Cc: Wolfgang Denk
> > > Signed-off-by: Michal Simek
> > > Reviewed-by: Ramon Fried
> > > [trini: Update Kconfig, handle legacy networking case as well]
> > > Signed-off-by: Tom Rini
> > > ---
> > > Changes in v3:
> > > - Update Kconfig help text with Wolfgang's suggestion
> > > - Reword the commit message to hopefully be clearer
> > >
> > > Changes in v2:
> > > - Update Kconfig help text to reflect this change.
> > > - Update the legacy path to match.
> > > ---
> > > net/Kconfig | 9 +
> > > net/eth-uclass.c | 2 ++
> > > net/eth_legacy.c | 2 ++
> > > 3 files changed, 9 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/net/Kconfig b/net/Kconfig
> > > index 7a2d14501881..cabe93c6bd29 100644
> > > --- a/net/Kconfig
> > > +++ b/net/Kconfig
> > > @@ -27,10 +27,11 @@ config BOOTP_SEND_HOSTNAME
> > > config NET_RANDOM_ETHADDR
> > > bool "Random ethaddr if unset"
> > > help
> > > - Selecting this will allow the Ethernet interface to function
> > > - even when the ethaddr variable for that interface is unset.
> > > - A new MAC address will be generated on every boot and it will
> > > - not be added to the environment.
> > > + Selecting this will allow the Ethernet interface to function
> > > even
> > > + when the ethaddr variable for that interface is unset. In this
> > > case,
> > > + a random MAC address in the locally administered address space
> > > is
> > > + generated. It will be saved to the appropriate environment
> > > variable,
> > > + too.
> > >
> > > config NETCONSOLE
> > > bool "NetConsole support"
> > > diff --git a/net/eth-uclass.c b/net/eth-uclass.c
> > > index 0da0e85be031..58c308f33276 100644
> > > --- a/net/eth-uclass.c
> > > +++ b/net/eth-uclass.c
> > > @@ -583,6 +583,8 @@ static int eth_post_probe(struct udevice *dev)
> > > net_random_ethaddr(pdata->enetaddr);
> > > printf("\nWarning: %s (eth%d) using random MAC address -
> > > %pM\n",
> > >dev->name, dev_seq(dev), pdata->enetaddr);
> > > + eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
> > > + pdata->enetaddr);
> > > #else
> > > printf("\nError: %s address not set.\n",
> > >dev->name);
> > > diff --git a/net/eth_legacy.c b/net/eth_legacy.c
> > > index f383ccce0b92..e7f53b958b2e 100644
> > > --- a/net/eth_legacy.c
> > > +++ b/net/eth_legacy.c
> > > @@ -164,6 +164,8 @@ int eth_write_hwaddr(struct eth_device *dev, const
> > > char *base_name,
> > > net_random_ethaddr(dev->enetaddr);
> > > printf("\nWarning: %s (eth%d) using random MAC address -
> > > %pM\n",
> > >dev->name, eth_number, dev->enetaddr);
> > > + eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
> > > + pdata->enetaddr);
> > > #else
> > > printf("\nError: %s address not set.\n",
> > >dev->name);
> > > --
> > > 2.25.1
> > >
> > Acked-by: Ramon Fried
>
> Ramon/Tom: Did anybody take this patch? Or you want me to take it?
I don't think I picked it up, and I'm fine with it coming via your tree.
--
Tom
signature.asc
Description: PGP signature
Re: [PATCHv3] net: uclass: Save generated ethernet MAC addresses to the environment
On 1/10/22 15:03, Tom Rini wrote:
On Fri, Jan 07, 2022 at 04:08:34PM +0100, Michal Simek wrote:
so 27. 11. 2021 v 20:37 odesílatel Ramon Fried napsal:
On Mon, Nov 22, 2021 at 3:45 PM Tom Rini wrote:
From: Michal Simek
When a MAC address is randomly generated we currently only update the
appropriate data structure. For consistency and to re-align with
historic usage, it should be also saved to the appropriate environment
variable as well.
Cc: Wolfgang Denk
Signed-off-by: Michal Simek
Reviewed-by: Ramon Fried
[trini: Update Kconfig, handle legacy networking case as well]
Signed-off-by: Tom Rini
---
Changes in v3:
- Update Kconfig help text with Wolfgang's suggestion
- Reword the commit message to hopefully be clearer
Changes in v2:
- Update Kconfig help text to reflect this change.
- Update the legacy path to match.
---
net/Kconfig | 9 +
net/eth-uclass.c | 2 ++
net/eth_legacy.c | 2 ++
3 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/net/Kconfig b/net/Kconfig
index 7a2d14501881..cabe93c6bd29 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -27,10 +27,11 @@ config BOOTP_SEND_HOSTNAME
config NET_RANDOM_ETHADDR
bool "Random ethaddr if unset"
help
- Selecting this will allow the Ethernet interface to function
- even when the ethaddr variable for that interface is unset.
- A new MAC address will be generated on every boot and it will
- not be added to the environment.
+ Selecting this will allow the Ethernet interface to function even
+ when the ethaddr variable for that interface is unset. In this case,
+ a random MAC address in the locally administered address space is
+ generated. It will be saved to the appropriate environment variable,
+ too.
config NETCONSOLE
bool "NetConsole support"
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 0da0e85be031..58c308f33276 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -583,6 +583,8 @@ static int eth_post_probe(struct udevice *dev)
net_random_ethaddr(pdata->enetaddr);
printf("\nWarning: %s (eth%d) using random MAC address -
%pM\n",
dev->name, dev_seq(dev), pdata->enetaddr);
+ eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
+ pdata->enetaddr);
#else
printf("\nError: %s address not set.\n",
dev->name);
diff --git a/net/eth_legacy.c b/net/eth_legacy.c
index f383ccce0b92..e7f53b958b2e 100644
--- a/net/eth_legacy.c
+++ b/net/eth_legacy.c
@@ -164,6 +164,8 @@ int eth_write_hwaddr(struct eth_device *dev, const char
*base_name,
net_random_ethaddr(dev->enetaddr);
printf("\nWarning: %s (eth%d) using random MAC address -
%pM\n",
dev->name, eth_number, dev->enetaddr);
+ eth_env_set_enetaddr_by_index("eth", dev_seq(dev),
+ pdata->enetaddr);
#else
printf("\nError: %s address not set.\n",
dev->name);
--
2.25.1
Acked-by: Ramon Fried
Ramon/Tom: Did anybody take this patch? Or you want me to take it?
I don't think I picked it up, and I'm fine with it coming via your tree.
Applied.
M
RE: [RFC] imx: imx8qm-rom7720: switch to binman
Hello Oliver,
> -Original Message-
> From: Oliver Graute
> Sent: Monday, January 10, 2022 11:31 AM
> To: Oliver Graute ; Stefano Babic
> ; Fabio Estevam ; NXP i.MX U-Boot Team
>
> Cc: aford...@gmail.com; peng@nxp.com; marcel.ziswi...@toradex.com;
> thar...@gateworks.com; ZHIZHIKIN Andrey
> ;
> u-boot@lists.denx.de
> Subject: [RFC] imx: imx8qm-rom7720: switch to binman
>
> Switch to use binman to pack images
Please don't forget S-o-B, checkpatch does complain about it. ;)
>
> ---
>
> Run into this issue on the first try to get binman working:
>
> make[1]: Nothing to be done for 'SPL'.
> BINMAN flash.bin
> MKIMAGE flash.bin
> Error: spl/u-boot-spl.cfgout[16] - Invalid command (LOADER)
> arch/arm/mach-imx/Makefile:190: recipe for target 'flash.bin' failed
> make[1]: *** [flash.bin] Error 1
> make[1]: *** Deleting file 'flash.bin'
> Makefile:1519: recipe for target 'flash.bin' failed
> make: *** [flash.bin] Error 2
>
> Some clue howto fix that?
This might be due to the fact that you're using the same u-boot-nodtb.bin
binary twice: once in binman section, and once in ITB. You can try to rename
the binman entry to a different name, this might do the trick. See [1] for
sample of imx8mq_evk conversion.
>
> arch/arm/dts/imx8qm-rom7720-a1.dts| 1 +
> arch/arm/dts/imx8qm-u-boot.dtsi | 95 +++
> arch/arm/mach-imx/imx8/Kconfig| 1 +
> .../advantech/imx8qm_rom7720_a1/imximage.cfg | 16 +---
> configs/imx8qm_rom7720_a1_4G_defconfig| 2 +-
Is there any documentation available for this board that
needs adaptions with new build instructions? I was not able
to locate any doc for this board at all...
> 5 files changed, 100 insertions(+), 15 deletions(-)
> create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi
>
> diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts b/arch/arm/dts/imx8qm-rom7720-
> a1.dts
> index d1f2fff869..332d441c6d 100644
> --- a/arch/arm/dts/imx8qm-rom7720-a1.dts
> +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
> @@ -10,6 +10,7 @@
> /memreserve/ 0x8000 0x0002;
>
> #include "fsl-imx8qm.dtsi"
> +#include "imx8qm-u-boot.dtsi"
>
> / {
> model = "Advantech iMX8QM Qseven series";
> diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi
> new file mode 100644
> index 00..77e5cd6989
> --- /dev/null
> +++ b/arch/arm/dts/imx8qm-u-boot.dtsi
> @@ -0,0 +1,95 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +/ {
> + binman: binman {
> + multiple-images;
> + };
> +
> +};
> +
> +&binman {
> + u-boot-nodtb {
> + filename = "u-boot-nodtb.bin";
> + pad-byte = <0xff>;
> + align-size = <4>;
> + align = <4>;
> +
> + u-boot-spl {
> + align-end = <4>;
> + };
What I see is missing in this section is SECO and SCFW binaries.
Can i.MX8QM boot without those? Otherwise generated image will be unusable.
> +
> + };
> +
> + flash {
> + mkimage {
> + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
> 0x10";
> +
> + blob {
> + filename = "u-boot-nodtb.bin";
> + };
> +
> + };
> +
> + };
> +
> + itb {
> + filename = "u-boot.itb";
> +
> + fit {
> + description = "Configuration to load ATF before
> U-Boot";
> + #address-cells = <1>;
> + fit,external-offset = ;
> +
> + images {
> + uboot {
> + description = "U-Boot (64-bit)";
> + type = "standalone";
> + arch = "arm64";
> + compression = "none";
> + load = ;
> +
> + uboot_blob: blob-ext {
> + filename = "u-boot-nodtb.bin";
> + };
> + };
> +
> + atf {
> + description = "ARM Trusted Firmware";
> + type = "firmware";
> + arch = "arm64";
> + compression = "none";
> + load = <0x8000>;
> + entry = <0x8000>;
> +
> + atf_blob: blob-ext {
> + filename = "bl31.bin";
> + };
> + };
> +
> + fdt {
> +
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. Our code drops the const qualifier leading to In file included from tools/lib/rsa/rsa-sign.c:1: ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: ./tools/../lib/rsa/rsa-sign.c:631:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 631 | rsa = EVP_PKEY_get0_RSA(pkey); | ^ Add a type conversion. Signed-off-by: Heinrich Schuchardt --- lib/rsa/rsa-sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 44f21416ce..3b6e5f0f86 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) goto err_get_pub_key; - rsa = EVP_PKEY_get0_RSA(pkey); + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); I think it's the wrong path to discard const qualifiers, whether unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the downstream users to do the same. Alex ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); if (ret) goto err_get_params;
Save bootargs from 1st stage bootloader like linux does
I'm working on a project to bring mainline linux kernels to android phones. I'm planning to use u-boot as a secondary stage bootloader packed in android boot image, so that linux kernel is replaced with u-boot, and initramfs is replaced with FIT image. This approach allows to use u-boot on a phone without much pain with storage drivers. Obviously, u-boot should know initramfs load address. It can be obtained from initrd-start device tree option. However, on arm64 address to the right device tree is provided in x0 CPU register. Would you accept a patch to preserve boot args on arm64?
[PATCH 1/2] board: sl28: disable random MAC address generation
Nowadays, u-boot (when CONFIG_NET_RANDOM_ETHADDR is set) will set enetaddr to a random value if not set and then pass the randomly generated MAC address to linux. This is bad for the following reasons: (1) it makes it impossible for linux to detect this error (2) linux won't trigger any fallback mechanism for the case where it didn't find any valid MAC address (3) a saveenv will store this randomly generated MAC address in the environment Probably, the user will also be unaware that something is wrong. He will just get different MAC addresses on each reboot, asking himself why this is the case. As this board usually have a serial port, the user can just fix this by setting the MAC address manually in the environment. Also disable the netconsole just in case, because it cannot be guaranteed that it will work in any case. After all, this was just a convenience option, because the bootloader - right now - doesn't have the ability to read the MAC address, which is stored in the OTP. But it is far more important to have a clear view of whats wrong with a board and that means we can no longer use this Kconfig option. Signed-off-by: Michael Walle --- configs/kontron_sl28_defconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 31a1083b0a..53cae506fc 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -57,8 +57,6 @@ CONFIG_OF_LIST="" CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_NETCONSOLE=y CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_SCSI_AHCI=y CONFIG_SATA_CEVA=y -- 2.30.2
[PATCH 2/2] board: sl28: use fit image generator
Simplify the binman config and fdt nodes by using the "@..-SEQ"
substitutions and CONFIG_OF_LIST.
Signed-off-by: Michael Walle
---
.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 128 ++
configs/kontron_sl28_defconfig| 2 +-
2 files changed, 10 insertions(+), 120 deletions(-)
diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
index d4b833284e..2dcb3c2a58 100644
--- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi
@@ -27,6 +27,7 @@
fit {
offset = ;
description = "FIT image with multiple configurations";
+ fit,fdt-list = "of-list";
images {
uboot {
@@ -41,95 +42,20 @@
};
};
- fdt-1 {
- description =
"fsl-ls1028a-kontron-sl28";
+ @fdt-SEQ {
+ description = "NAME";
type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename =
"arch/arm/dts/fsl-ls1028a-kontron-sl28.dtb";
- };
- };
-
- fdt-2 {
- description =
"fsl-ls1028a-kontron-sl28-var1";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename =
"arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dtb";
- };
- };
-
- fdt-3 {
- description =
"fsl-ls1028a-kontron-sl28-var2";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename =
"arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dtb";
- };
- };
-
- fdt-4 {
- description =
"fsl-ls1028a-kontron-sl28-var3";
- type = "flat_dt";
- arch = "arm";
compression = "none";
-
- blob {
- filename =
"arch/arm/dts/fsl-ls1028a-kontron-sl28-var3.dtb";
- };
- };
-
- fdt-5 {
- description =
"fsl-ls1028a-kontron-sl28-var4";
- type = "flat_dt";
- arch = "arm";
- compression = "none";
-
- blob {
- filename =
"arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dtb";
- };
};
};
configurations {
- default = "conf-1";
-
- conf-1 {
- description =
"fsl-ls1028a-kontron-sl28";
- firmware = "uboot";
- fdt = "fdt-1";
- };
-
- conf-2 {
- description =
"fsl-ls1028a-kontron-sl28-var1";
- firmware = "uboot";
- fdt = "fdt-2";
- };
-
- conf-3 {
- description =
"fsl-ls1028a-kontron-sl28-var2";
- firmware = "uboot";
- fdt = "fdt-3";
- };
-
- conf-4 {
- description =
"fsl-ls1028a-kontron-sl28-var3";
- firmware = "uboot";
- loadables = "uboot";
-
[PATCH v6 0/2] arm: imx8m: add support for Advantech RSB-3720
From: "Ying-Chun Liu (PaulLiu)" Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Ying-Chun Liu (PaulLiu) (2): arm: dts: add imx8mp-rsb3720-a1 dts file arm: imx8m: add support for Advantech RSB-3720 v2: update dts v3: remove unnecessary code. move board code to board/advantech v4: rebase to latest master branch. v5: fix commit description v6: update dts arch/arm/dts/Makefile |3 + arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi| 161 ++ arch/arm/dts/imx8mp-rsb3720-a1.dts| 805 +++ arch/arm/mach-imx/imx8m/Kconfig | 15 + board/advantech/imx8mp_rsb3720a1/Kconfig | 14 + board/advantech/imx8mp_rsb3720a1/MAINTAINERS |7 + board/advantech/imx8mp_rsb3720a1/Makefile | 24 + .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 213 ++ .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg | 11 + .../lpddr4_timing_rsb3720a1_4G.c | 1848 .../lpddr4_timing_rsb3720a1_6G.c | 1875 + board/advantech/imx8mp_rsb3720a1/spl.c| 260 +++ configs/imx8mp_rsb3720a1_4G_defconfig | 163 ++ configs/imx8mp_rsb3720a1_6G_defconfig | 164 ++ include/configs/imx8mp_rsb3720.h | 233 ++ 15 files changed, 5796 insertions(+) create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1.dts create mode 100644 board/advantech/imx8mp_rsb3720a1/Kconfig create mode 100644 board/advantech/imx8mp_rsb3720a1/MAINTAINERS create mode 100644 board/advantech/imx8mp_rsb3720a1/Makefile create mode 100644 board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c create mode 100644 board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/spl.c create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig create mode 100644 include/configs/imx8mp_rsb3720.h -- 2.34.1
[PATCH v6 1/2] arm: dts: add imx8mp-rsb3720-a1 dts file
From: "Ying-Chun Liu (PaulLiu)"
Add board dts for Advantech's imx8mp-rsb3720-a1
Signed-off-by: Darren Huang
Signed-off-by: Kevin12.Chen
Signed-off-by: Phill.Liu
Signed-off-by: Tim Liang
Signed-off-by: wei.zeng
Signed-off-by: Ying-Chun Liu (PaulLiu)
Cc: uboot-imx
---
v2: update dts
v4: rebase to latest master branch
v5: fix commit description
v6: update dts
---
arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi | 161 +
arch/arm/dts/imx8mp-rsb3720-a1.dts | 805 +
2 files changed, 966 insertions(+)
create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mp-rsb3720-a1.dts
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
new file mode 100644
index 00..2848b24f65
--- /dev/null
+++ b/arch/arm/dts/imx8mp-rsb3720-a1-u-boot.dtsi
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdog1>;
+ u-boot,dm-spl;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+};
+
+®_usdhc2_vmmc {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc3 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&gpio3 {
+ u-boot,dm-spl;
+};
+
+&gpio4 {
+ u-boot,dm-spl;
+};
+
+&gpio5 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&uart3 {
+ u-boot,dm-spl;
+};
+
+&i2c1 {
+ u-boot,dm-spl;
+};
+
+&i2c2 {
+ u-boot,dm-spl;
+};
+
+&i2c3 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_i2c1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pca9450@25} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pca9450@25/regulators} {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC1>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc2 {
+ u-boot,dm-spl;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&usdhc3 {
+ u-boot,dm-spl;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>;
+};
+
+&binman {
+ itb {
+ fit {
+ images {
+ fip {
+ description = "Trusted Firmware FIP";
+ type = "firmware";
+ arch = "arm64";
+ compression = "none";
+ load = <0x4031>;
+
+ fip_blob: blob-ext{
+ filename = "fip.bin";
+ };
+ };
+ };
+
+ configurations {
+ conf {
+ loadables = "atf", "fip";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/imx8mp-rsb3720-a1.dts
b/arch/arm/dts/imx8mp-rsb3720-a1.dts
new file mode 100644
index 00..1ef1c0c99e
--- /dev/null
+++ b/arch/arm/dts/imx8mp-rsb3720-a1.dts
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2019 NXP
+ * Copyright 2022 Linaro
+ */
+
+/dts-v1/;
+
+#include
+#include "imx8mp.dtsi"
+
+/ {
+ model = "Advantech i.MX8MPlus RSB3720A1 board";
+ compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
+
+ aliases {
+ rtc0 = &s35390a;
+ rtc1 = &snvs_rtc;
+ };
+
+ chosen {
+ stdout-path = &uart3;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0xc000>,
+ <0x1 0x 0 0xc000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ rpmsg_reserved: rpmsg@0x5580 {
+
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: > > > On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: > > The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. > > Our code drops the const qualifier leading to > > > > In file included from tools/lib/rsa/rsa-sign.c:1: > > ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: > > ./tools/../lib/rsa/rsa-sign.c:631:13: warning: > > assignment discards ‘const’ qualifier from pointer target type > > [-Wdiscarded-qualifiers] > >631 | rsa = EVP_PKEY_get0_RSA(pkey); > >| ^ > > > > Add a type conversion. > > > > Signed-off-by: Heinrich Schuchardt > > --- > > lib/rsa/rsa-sign.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c > > index 44f21416ce..3b6e5f0f86 100644 > > --- a/lib/rsa/rsa-sign.c > > +++ b/lib/rsa/rsa-sign.c > > @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, > > void *keydest) > > if (ret) > > goto err_get_pub_key; > > - rsa = EVP_PKEY_get0_RSA(pkey); > > + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); > > I think it's the wrong path to discard const qualifiers, whether unwillingly > or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the > downstream users to do the same. So, how do we trigger this warning, exactly? The line here has been in place for several releases, but only with fe68a67a5f11 and removing legacy paths did this become the only option. Of course, CI isn't kicking this problem right now. But CI is Ubuntu 18.04, and while post v2022.01 we should at least move up to 20.04, I'm guessing this gets hit with something recent like 20.04, or Debian 11 or what will be Ubuntu 22.04. Should we take the cast now, and fix this up properly post release? -- Tom signature.asc Description: PGP signature
Re: Save bootargs from 1st stage bootloader like linux does
Seems like this is already supported with save_boot_params function пн, 10 янв. 2022 г. в 18:01, Dzmitry Sankouski : > I'm working on a project to bring mainline linux kernels to android phones. > I'm planning to use u-boot as a secondary stage bootloader packed in > android boot image, > so that linux kernel is replaced with u-boot, and initramfs is replaced > with FIT image. > > This approach allows to use u-boot on a phone without much pain with > storage drivers. > > Obviously, u-boot should know initramfs load address. It can be obtained > from initrd-start > device tree option. However, on arm64 address to the right device tree is > provided in x0 CPU > register. > > Would you accept a patch to preserve boot args on arm64? > > >
Re: [RFC] imx: imx8qm-rom7720: switch to binman
On 10/01/22, ZHIZHIKIN Andrey wrote: > Hello Oliver, > > > -Original Message- > > From: Oliver Graute > > Sent: Monday, January 10, 2022 11:31 AM > > To: Oliver Graute ; Stefano Babic > > ; Fabio Estevam ; NXP i.MX U-Boot Team > > > > Cc: aford...@gmail.com; peng@nxp.com; marcel.ziswi...@toradex.com; > > thar...@gateworks.com; ZHIZHIKIN Andrey > > ; > > u-boot@lists.denx.de > > Subject: [RFC] imx: imx8qm-rom7720: switch to binman > > > > Switch to use binman to pack images > > Please don't forget S-o-B, checkpatch does complain about it. ;) will do it on next submission > > > > --- > > > > Run into this issue on the first try to get binman working: > > > > make[1]: Nothing to be done for 'SPL'. > > BINMAN flash.bin > > MKIMAGE flash.bin > > Error: spl/u-boot-spl.cfgout[16] - Invalid command (LOADER) > > arch/arm/mach-imx/Makefile:190: recipe for target 'flash.bin' failed > > make[1]: *** [flash.bin] Error 1 > > make[1]: *** Deleting file 'flash.bin' > > Makefile:1519: recipe for target 'flash.bin' failed > > make: *** [flash.bin] Error 2 > > > > Some clue howto fix that? > > This might be due to the fact that you're using the same u-boot-nodtb.bin > binary twice: once in binman section, and once in ITB. You can try to rename > the binman entry to a different name, this might do the trick. See [1] for > sample of imx8mq_evk conversion. ok I think I fixed that. I dropped additionally the following statements: make u-boot.bin make flash.bin just make is enough here or? But still get this warning even if CONFIG_SPL_FIT_GENERATOR is disabled. make imx8qm_rom7720_a1_4G_defconfig && make # # configuration written to .config # scripts/kconfig/conf --syncconfig Kconfig CFG u-boot.cfg GEN include/autoconf.mk GEN include/autoconf.mk.dep CFG spl/u-boot.cfg GEN spl/include/autoconf.mk = WARNING == This board uses CONFIG_SPL_FIT_GENERATOR. Please migrate to binman instead, to avoid the proliferation of arch-specific scripts with no tests. > Is there any documentation available for this board that > needs adaptions with new build instructions? I was not able > to locate any doc for this board at all... You find the doc here: doc/board/advantech/imx8qm-rom7720-a1.rst > > What I see is missing in this section is SECO and SCFW binaries. > Can i.MX8QM boot without those? Otherwise generated image will be unusable. you are right. This is still missing. Can you point me to a example with SECO and SCFW? > This binman configuration suggests that there are 2 binaries that > should be populated onto the bootable media: flash.bin and > u-boot.itb. Can you please convert them to use a single binary? > Sample code for this is also in [1]. > > Link: [1]: > https://lore.kernel.org/u-boot/20211203161802.12699-1-andrey.zhizhi...@leica-geosystems.com/ thx for your suggestions Best regards, Oliver
Re: [RFC] imx: imx8qm-rom7720: switch to binman
Hi Oliver
On Mon, 2022-01-10 at 14:29 +, ZHIZHIKIN Andrey wrote:
> Hello Oliver,
>
> > -Original Message-
> > From: Oliver Graute
> > Sent: Monday, January 10, 2022 11:31 AM
> > To: Oliver Graute ; Stefano Babic
> > ; Fabio Estevam ; NXP i.MX U-Boot Team
> >
> > Cc: aford...@gmail.com; peng@nxp.com; marcel.ziswi...@toradex.com;
> > thar...@gateworks.com; ZHIZHIKIN Andrey
> > ;
> > u-boot@lists.denx.de
> > Subject: [RFC] imx: imx8qm-rom7720: switch to binman
> >
> > Switch to use binman to pack images
>
> Please don't forget S-o-B, checkpatch does complain about it. ;)
> >
> > ---
> >
> > Run into this issue on the first try to get binman working:
> >
> > make[1]: Nothing to be done for 'SPL'.
You may need something similar to [1]
> > BINMAN flash.bin
> > MKIMAGE flash.bin
> > Error: spl/u-boot-spl.cfgout[16] - Invalid command (LOADER)
> > arch/arm/mach-imx/Makefile:190: recipe for target 'flash.bin' failed
> > make[1]: *** [flash.bin] Error 1
> > make[1]: *** Deleting file 'flash.bin'
> > Makefile:1519: recipe for target 'flash.bin' failed
> > make: *** [flash.bin] Error 2
> >
> > Some clue howto fix that?
>
> This might be due to the fact that you're using the same u-boot-nodtb.bin
> binary twice: once in binman
> section, and once in ITB. You can try to rename the binman entry to a
> different name, this might do the
> trick. See [1] for sample of imx8mq_evk conversion.
Yep, adding the imx-boot/flash.bin binman section combining them two should
avoid this.
To be honest, even on imx8mm it currently fails if doing make flash.bin rather
than just make which will call
BINMAN ALL. I guess, that might be some kind of a remnant resp. clash with
before binman stuff.
⬢[zim@toolbox u-boot.git]$ make verdin-imx8mm_defconfig
⬢[zim@toolbox u-boot.git]$ make -j12 flash.bin
...
BINMAN flash.bin
MKIMAGE flash.bin
./tools/mkimage: Can't open spl/u-boot-spl-ddr.bin: No such file or directory
make[1]: *** [arch/arm/mach-imx/Makefile:167: flash.bin] Error 1
make[1]: *** Deleting file 'flash.bin'
make: *** [Makefile:1521: flash.bin] Error 2
> > arch/arm/dts/imx8qm-rom7720-a1.dts | 1 +
> > arch/arm/dts/imx8qm-u-boot.dtsi | 95 +++
> > arch/arm/mach-imx/imx8/Kconfig | 1 +
> > .../advantech/imx8qm_rom7720_a1/imximage.cfg | 16 +---
> > configs/imx8qm_rom7720_a1_4G_defconfig | 2 +-
>
> Is there any documentation available for this board that
> needs adaptions with new build instructions? I was not able
> to locate any doc for this board at all...
>
> > 5 files changed, 100 insertions(+), 15 deletions(-)
> > create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi
> >
> > diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts
> > b/arch/arm/dts/imx8qm-rom7720-
> > a1.dts
> > index d1f2fff869..332d441c6d 100644
> > --- a/arch/arm/dts/imx8qm-rom7720-a1.dts
> > +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
> > @@ -10,6 +10,7 @@
> > /memreserve/ 0x8000 0x0002;
> >
> > #include "fsl-imx8qm.dtsi"
> > +#include "imx8qm-u-boot.dtsi"
> >
> > / {
> > model = "Advantech iMX8QM Qseven series";
> > diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi
> > b/arch/arm/dts/imx8qm-u-boot.dtsi
> > new file mode 100644
> > index 00..77e5cd6989
> > --- /dev/null
> > +++ b/arch/arm/dts/imx8qm-u-boot.dtsi
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright 2021 NXP
> > + */
> > +
> > +/ {
> > + binman: binman {
> > + multiple-images;
> > + };
> > +
Please avoid such empty lines before closing curly braces.
> > +};
> > +
> > +&binman {
> > + u-boot-nodtb {
> > + filename = "u-boot-nodtb.bin";
> > + pad-byte = <0xff>;
> > + align-size = <4>;
> > + align = <4>;
> > +
> > + u-boot-spl {
> > + align-end = <4>;
> > + };
>
> What I see is missing in this section is SECO and SCFW binaries.
>
> Can i.MX8QM boot without those? Otherwise generated image will be unusable.
>
> > +
> > + };
> > +
> > + flash {
> > + mkimage {
> > + args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e
> > 0x10";
> > +
> > + blob {
> > + filename = "u-boot-nodtb.bin";
> > + };
> > +
> > + };
> > +
> > + };
> > +
> > + itb {
> > + filename = "u-boot.itb";
> > +
> > + fit {
> > + description = "Configuration to load ATF before
> > U-Boot";
> > + #address-cells = <1>;
> > + fit,external-offset = ;
> > +
> > + images {
> > + uboot {
> > + description = "U-Boot (64-bit)";
> > + type = "standalone";
> > +
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On 1/10/22 16:06, Tom Rini wrote: On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. Our code drops the const qualifier leading to In file included from tools/lib/rsa/rsa-sign.c:1: ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: ./tools/../lib/rsa/rsa-sign.c:631:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 631 | rsa = EVP_PKEY_get0_RSA(pkey); | ^ Add a type conversion. Signed-off-by: Heinrich Schuchardt --- lib/rsa/rsa-sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 44f21416ce..3b6e5f0f86 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) goto err_get_pub_key; - rsa = EVP_PKEY_get0_RSA(pkey); + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); I think it's the wrong path to discard const qualifiers, whether unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the downstream users to do the same. So, how do we trigger this warning, exactly? The line here has been in place for several releases, but only with fe68a67a5f11 and removing legacy paths did this become the only option. Of course, CI isn't kicking this problem right now. But CI is Ubuntu 18.04, and while post v2022.01 we should at least move up to 20.04, I'm guessing this gets hit with something recent like 20.04, or Debian 11 or what will be Ubuntu 22.04. Should we take the cast now, and fix this up properly post release? I am using OpenSSLv3 as delivered by Ubuntu Jammy. Building sandbox_defconfig shows the warning. Best regards Heinrich
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On Mon, Jan 10, 2022 at 05:11:29PM +0100, Heinrich Schuchardt wrote: > On 1/10/22 16:06, Tom Rini wrote: > > On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: > > > > > > > > > On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: > > > > The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. > > > > Our code drops the const qualifier leading to > > > > > > > > In file included from tools/lib/rsa/rsa-sign.c:1: > > > > ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: > > > > ./tools/../lib/rsa/rsa-sign.c:631:13: warning: > > > > assignment discards ‘const’ qualifier from pointer target type > > > > [-Wdiscarded-qualifiers] > > > > 631 | rsa = EVP_PKEY_get0_RSA(pkey); > > > > | ^ > > > > > > > > Add a type conversion. > > > > > > > > Signed-off-by: Heinrich Schuchardt > > > > --- > > > >lib/rsa/rsa-sign.c | 2 +- > > > >1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c > > > > index 44f21416ce..3b6e5f0f86 100644 > > > > --- a/lib/rsa/rsa-sign.c > > > > +++ b/lib/rsa/rsa-sign.c > > > > @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info > > > > *info, void *keydest) > > > > if (ret) > > > > goto err_get_pub_key; > > > > - rsa = EVP_PKEY_get0_RSA(pkey); > > > > + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); > > > > > > I think it's the wrong path to discard const qualifiers, whether > > > unwillingly > > > or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the > > > downstream users to do the same. > > > > So, how do we trigger this warning, exactly? The line here has been in > > place for several releases, but only with fe68a67a5f11 and removing > > legacy paths did this become the only option. Of course, CI isn't > > kicking this problem right now. But CI is Ubuntu 18.04, and while post > > v2022.01 we should at least move up to 20.04, I'm guessing this gets hit > > with something recent like 20.04, or Debian 11 or what will be Ubuntu > > 22.04. > > > > Should we take the cast now, and fix this up properly post release? > > I am using OpenSSLv3 as delivered by Ubuntu Jammy. Building > sandbox_defconfig shows the warning. Right, so what will be 22.04. I'm OK I think taking the cast for today if you'll clean up the code as suggested for post release. -- Tom signature.asc Description: PGP signature
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On 1/10/22 17:12, Tom Rini wrote: On Mon, Jan 10, 2022 at 05:11:29PM +0100, Heinrich Schuchardt wrote: On 1/10/22 16:06, Tom Rini wrote: On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. Our code drops the const qualifier leading to In file included from tools/lib/rsa/rsa-sign.c:1: ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: ./tools/../lib/rsa/rsa-sign.c:631:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 631 | rsa = EVP_PKEY_get0_RSA(pkey); | ^ Add a type conversion. Signed-off-by: Heinrich Schuchardt --- lib/rsa/rsa-sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 44f21416ce..3b6e5f0f86 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) goto err_get_pub_key; - rsa = EVP_PKEY_get0_RSA(pkey); + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); I think it's the wrong path to discard const qualifiers, whether unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the downstream users to do the same. So, how do we trigger this warning, exactly? The line here has been in place for several releases, but only with fe68a67a5f11 and removing legacy paths did this become the only option. Of course, CI isn't kicking this problem right now. But CI is Ubuntu 18.04, and while post v2022.01 we should at least move up to 20.04, I'm guessing this gets hit with something recent like 20.04, or Debian 11 or what will be Ubuntu 22.04. Should we take the cast now, and fix this up properly post release? I am using OpenSSLv3 as delivered by Ubuntu Jammy. Building sandbox_defconfig shows the warning. Right, so what will be 22.04. I'm OK I think taking the cast for today if you'll clean up the code as suggested for post release. In 3a8b919932fdf07b6f I added #define OPENSSL_API_COMPAT 0x10101000L. Would we also have to move to the current API? But that might create problems in old releases. Best regards Heinrich
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On Mon, Jan 10, 2022 at 05:22:15PM +0100, Heinrich Schuchardt wrote: > On 1/10/22 17:12, Tom Rini wrote: > > On Mon, Jan 10, 2022 at 05:11:29PM +0100, Heinrich Schuchardt wrote: > > > On 1/10/22 16:06, Tom Rini wrote: > > > > On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: > > > > > > > > > > > > > > > On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: > > > > > > The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. > > > > > > Our code drops the const qualifier leading to > > > > > > > > > > > > In file included from tools/lib/rsa/rsa-sign.c:1: > > > > > > ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: > > > > > > ./tools/../lib/rsa/rsa-sign.c:631:13: warning: > > > > > > assignment discards ‘const’ qualifier from pointer target type > > > > > > [-Wdiscarded-qualifiers] > > > > > > 631 | rsa = EVP_PKEY_get0_RSA(pkey); > > > > > > | ^ > > > > > > > > > > > > Add a type conversion. > > > > > > > > > > > > Signed-off-by: Heinrich Schuchardt > > > > > > > > > > > > --- > > > > > > lib/rsa/rsa-sign.c | 2 +- > > > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > > > > > diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c > > > > > > index 44f21416ce..3b6e5f0f86 100644 > > > > > > --- a/lib/rsa/rsa-sign.c > > > > > > +++ b/lib/rsa/rsa-sign.c > > > > > > @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info > > > > > > *info, void *keydest) > > > > > > if (ret) > > > > > > goto err_get_pub_key; > > > > > > - rsa = EVP_PKEY_get0_RSA(pkey); > > > > > > + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); > > > > > > > > > > I think it's the wrong path to discard const qualifiers, whether > > > > > unwillingly > > > > > or by type punning. I suggest making 'rsa' a "const RSA *" and fixing > > > > > the > > > > > downstream users to do the same. > > > > > > > > So, how do we trigger this warning, exactly? The line here has been in > > > > place for several releases, but only with fe68a67a5f11 and removing > > > > legacy paths did this become the only option. Of course, CI isn't > > > > kicking this problem right now. But CI is Ubuntu 18.04, and while post > > > > v2022.01 we should at least move up to 20.04, I'm guessing this gets hit > > > > with something recent like 20.04, or Debian 11 or what will be Ubuntu > > > > 22.04. > > > > > > > > Should we take the cast now, and fix this up properly post release? > > > > > > I am using OpenSSLv3 as delivered by Ubuntu Jammy. Building > > > sandbox_defconfig shows the warning. > > > > Right, so what will be 22.04. I'm OK I think taking the cast for today > > if you'll clean up the code as suggested for post release. > > > > In 3a8b919932fdf07b6f I added #define OPENSSL_API_COMPAT 0x10101000L. Which is OpenSSL 1.1.0 API, right? > Would we also have to move to the current API? But that might create > problems in old releases. How old of a release would it be a problem for? We dropped support for older than 1.1.0 with fe68a67a5f11. -- Tom signature.asc Description: PGP signature
Re: [RFC] imx: imx8qm-rom7720: switch to binman
On Mon, Jan 10, 2022 at 9:34 AM Marcel Ziswiler
wrote:
> Hi Oliver
>
> On Mon, 2022-01-10 at 14:29 +, ZHIZHIKIN Andrey wrote:
> > Hello Oliver,
> >
> > > -Original Message-
> > > From: Oliver Graute
> > > Sent: Monday, January 10, 2022 11:31 AM
> > > To: Oliver Graute ; Stefano Babic
> > > ; Fabio Estevam ; NXP i.MX U-Boot
> Team
> > >
> > > Cc: aford...@gmail.com; peng@nxp.com; marcel.ziswi...@toradex.com;
> > > thar...@gateworks.com; ZHIZHIKIN Andrey <
> andrey.zhizhi...@leica-geosystems.com>;
> > > u-boot@lists.denx.de
> > > Subject: [RFC] imx: imx8qm-rom7720: switch to binman
> > >
> > > Switch to use binman to pack images
> >
> > Please don't forget S-o-B, checkpatch does complain about it. ;)
> > >
> > > ---
> > >
> > > Run into this issue on the first try to get binman working:
> > >
> > > make[1]: Nothing to be done for 'SPL'.
>
> You may need something similar to [1]
>
> > > BINMAN flash.bin
> > > MKIMAGE flash.bin
> > > Error: spl/u-boot-spl.cfgout[16] - Invalid command (LOADER)
> > > arch/arm/mach-imx/Makefile:190: recipe for target 'flash.bin' failed
> > > make[1]: *** [flash.bin] Error 1
> > > make[1]: *** Deleting file 'flash.bin'
> > > Makefile:1519: recipe for target 'flash.bin' failed
> > > make: *** [flash.bin] Error 2
> > >
> > > Some clue howto fix that?
> >
> > This might be due to the fact that you're using the same
> u-boot-nodtb.bin binary twice: once in binman
> > section, and once in ITB. You can try to rename the binman entry to a
> different name, this might do the
> > trick. See [1] for sample of imx8mq_evk conversion.
>
> Yep, adding the imx-boot/flash.bin binman section combining them two
> should avoid this.
>
> To be honest, even on imx8mm it currently fails if doing make flash.bin
> rather than just make which will call
> BINMAN ALL. I guess, that might be some kind of a remnant resp. clash with
> before binman stuff.
>
> ⬢[zim@toolbox u-boot.git]$ make verdin-imx8mm_defconfig
> ⬢[zim@toolbox u-boot.git]$ make -j12 flash.bin
> ...
> BINMAN flash.bin
> MKIMAGE flash.bin
> ./tools/mkimage: Can't open spl/u-boot-spl-ddr.bin: No such file or
> directory
>
When I got this error, I had to double check the imximage-8mm-lpddr4.cfg
file referenced from the Kconfig. Beacon has a custom one [1] that doesn't
point to spl, and that made this error go away.
[1]
https://source.denx.de/u-boot/u-boot/-/blob/master/board/beacon/imx8mm/imximage-8mm-lpddr4.cfg
> make[1]: *** [arch/arm/mach-imx/Makefile:167: flash.bin] Error 1
> make[1]: *** Deleting file 'flash.bin'
> make: *** [Makefile:1521: flash.bin] Error 2
>
> > > arch/arm/dts/imx8qm-rom7720-a1.dts| 1 +
> > > arch/arm/dts/imx8qm-u-boot.dtsi | 95 +++
> > > arch/arm/mach-imx/imx8/Kconfig| 1 +
> > > .../advantech/imx8qm_rom7720_a1/imximage.cfg | 16 +---
> > > configs/imx8qm_rom7720_a1_4G_defconfig| 2 +-
> >
> > Is there any documentation available for this board that
> > needs adaptions with new build instructions? I was not able
> > to locate any doc for this board at all...
> >
> > > 5 files changed, 100 insertions(+), 15 deletions(-)
> > > create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi
> > >
> > > diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts
> b/arch/arm/dts/imx8qm-rom7720-
> > > a1.dts
> > > index d1f2fff869..332d441c6d 100644
> > > --- a/arch/arm/dts/imx8qm-rom7720-a1.dts
> > > +++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
> > > @@ -10,6 +10,7 @@
> > > /memreserve/ 0x8000 0x0002;
> > >
> > > #include "fsl-imx8qm.dtsi"
> > > +#include "imx8qm-u-boot.dtsi"
> > >
> > > / {
> > > model = "Advantech iMX8QM Qseven series";
> > > diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi
> b/arch/arm/dts/imx8qm-u-boot.dtsi
> > > new file mode 100644
> > > index 00..77e5cd6989
> > > --- /dev/null
> > > +++ b/arch/arm/dts/imx8qm-u-boot.dtsi
> > > @@ -0,0 +1,95 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/*
> > > + * Copyright 2021 NXP
> > > + */
> > > +
> > > +/ {
> > > + binman: binman {
> > > + multiple-images;
> > > + };
> > > +
>
> Please avoid such empty lines before closing curly braces.
>
> > > +};
> > > +
> > > +&binman {
> > > + u-boot-nodtb {
> > > + filename = "u-boot-nodtb.bin";
> > > + pad-byte = <0xff>;
> > > + align-size = <4>;
> > > + align = <4>;
> > > +
> > > + u-boot-spl {
> > > + align-end = <4>;
> > > + };
> >
> > What I see is missing in this section is SECO and SCFW binaries.
> >
> > Can i.MX8QM boot without those? Otherwise generated image will be
> unusable.
> >
> > > +
> > > + };
> > > +
> > > + flash {
> > > + mkimage {
> > > + args = "-n spl/u-boot-spl.cfgout -T imx8mimage
> -e
> > > 0x10";
> > > +
> > > + blob {
> > > + filename = "u-boot-no
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On 1/10/22 17:29, Tom Rini wrote: On Mon, Jan 10, 2022 at 05:22:15PM +0100, Heinrich Schuchardt wrote: On 1/10/22 17:12, Tom Rini wrote: On Mon, Jan 10, 2022 at 05:11:29PM +0100, Heinrich Schuchardt wrote: On 1/10/22 16:06, Tom Rini wrote: On Mon, Jan 10, 2022 at 09:00:29AM -0600, Alex G. wrote: On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. Our code drops the const qualifier leading to In file included from tools/lib/rsa/rsa-sign.c:1: ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: ./tools/../lib/rsa/rsa-sign.c:631:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 631 | rsa = EVP_PKEY_get0_RSA(pkey); | ^ Add a type conversion. Signed-off-by: Heinrich Schuchardt --- lib/rsa/rsa-sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 44f21416ce..3b6e5f0f86 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) goto err_get_pub_key; - rsa = EVP_PKEY_get0_RSA(pkey); + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); I think it's the wrong path to discard const qualifiers, whether unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the downstream users to do the same. So, how do we trigger this warning, exactly? The line here has been in place for several releases, but only with fe68a67a5f11 and removing legacy paths did this become the only option. Of course, CI isn't kicking this problem right now. But CI is Ubuntu 18.04, and while post v2022.01 we should at least move up to 20.04, I'm guessing this gets hit with something recent like 20.04, or Debian 11 or what will be Ubuntu 22.04. Should we take the cast now, and fix this up properly post release? I am using OpenSSLv3 as delivered by Ubuntu Jammy. Building sandbox_defconfig shows the warning. Right, so what will be 22.04. I'm OK I think taking the cast for today if you'll clean up the code as suggested for post release. In 3a8b919932fdf07b6f I added #define OPENSSL_API_COMPAT 0x10101000L. Which is OpenSSL 1.1.0 API, right? Would we also have to move to the current API? But that might create problems in old releases. How old of a release would it be a problem for? We dropped support for older than 1.1.0 with fe68a67a5f11. According to https://www.openssl.org/policies/releasestrat.html Open SSL version 1.1.1 will be supported until 2023-09-11 (LTS). We will have to keep OPENSSL_API_COMPAT up to that date. For building against OpenSSL 3 without warning we need to fix the problem with const. And yes propagating const throughout our code will be a cleaner solution. Best regards Heinrich
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
Hi, On Mon, 10 Jan 2022 at 08:00, Alex G. wrote: > > > > On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: > > The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. > > Our code drops the const qualifier leading to > > > > In file included from tools/lib/rsa/rsa-sign.c:1: > > ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: > > ./tools/../lib/rsa/rsa-sign.c:631:13: warning: > > assignment discards ‘const’ qualifier from pointer target type > > [-Wdiscarded-qualifiers] > >631 | rsa = EVP_PKEY_get0_RSA(pkey); > >| ^ > > > > Add a type conversion. > > > > Signed-off-by: Heinrich Schuchardt > > --- > > lib/rsa/rsa-sign.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c > > index 44f21416ce..3b6e5f0f86 100644 > > --- a/lib/rsa/rsa-sign.c > > +++ b/lib/rsa/rsa-sign.c > > @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, > > void *keydest) > > if (ret) > > goto err_get_pub_key; > > > > - rsa = EVP_PKEY_get0_RSA(pkey); > > + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); > > I think it's the wrong path to discard const qualifiers, whether > unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" > and fixing the downstream users to do the same. It looks like just a case of changing some function signatures in that file. Heinrich, what do you think? Regards, SImon > > Alex > > > ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); > > if (ret) > > goto err_get_params; > >
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On 1/10/22 17:48, Simon Glass wrote: Hi, On Mon, 10 Jan 2022 at 08:00, Alex G. wrote: On 1/9/22 8:39 AM, Heinrich Schuchardt wrote: The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. Our code drops the const qualifier leading to In file included from tools/lib/rsa/rsa-sign.c:1: ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: ./tools/../lib/rsa/rsa-sign.c:631:13: warning: assignment discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 631 | rsa = EVP_PKEY_get0_RSA(pkey); | ^ Add a type conversion. Signed-off-by: Heinrich Schuchardt --- lib/rsa/rsa-sign.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c index 44f21416ce..3b6e5f0f86 100644 --- a/lib/rsa/rsa-sign.c +++ b/lib/rsa/rsa-sign.c @@ -628,7 +628,7 @@ int rsa_add_verify_data(struct image_sign_info *info, void *keydest) if (ret) goto err_get_pub_key; - rsa = EVP_PKEY_get0_RSA(pkey); + rsa = (RSA *)EVP_PKEY_get0_RSA(pkey); I think it's the wrong path to discard const qualifiers, whether unwillingly or by type punning. I suggest making 'rsa' a "const RSA *" and fixing the downstream users to do the same. It looks like just a case of changing some function signatures in that file. Heinrich, what do you think? Alex' suggestion is fine. I just did not want to create a lot of changes on release day. Best regards Heinrich Regards, SImon Alex ret = rsa_get_params(rsa, &exponent, &n0_inv, &modulus, &r_squared); if (ret) goto err_get_params;
[PATCH v6 2/2] arm: imx8m: add support for Advantech RSB-3720
From: "Ying-Chun Liu (PaulLiu)" Add initial support for Advantech RSB-3720 board. The initial support includes: - MMC - eMMC - I2C - FEC - Serial console Signed-off-by: Darren Huang Signed-off-by: Kevin12.Chen Signed-off-by: Phill.Liu Signed-off-by: Tim Liang Signed-off-by: wei.zeng Signed-off-by: Ying-Chun Liu (PaulLiu) Cc: uboot-imx Cc: Peng Fan (OSS) --- v3: remove unnecessary code. move board code to board/advantech v4: rebase to latest master branch --- arch/arm/dts/Makefile |3 + arch/arm/mach-imx/imx8m/Kconfig | 15 + board/advantech/imx8mp_rsb3720a1/Kconfig | 14 + board/advantech/imx8mp_rsb3720a1/MAINTAINERS |7 + board/advantech/imx8mp_rsb3720a1/Makefile | 24 + .../imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 213 ++ .../imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg | 11 + .../lpddr4_timing_rsb3720a1_4G.c | 1848 .../lpddr4_timing_rsb3720a1_6G.c | 1875 + board/advantech/imx8mp_rsb3720a1/spl.c| 260 +++ configs/imx8mp_rsb3720a1_4G_defconfig | 163 ++ configs/imx8mp_rsb3720a1_6G_defconfig | 164 ++ include/configs/imx8mp_rsb3720.h | 233 ++ 13 files changed, 4830 insertions(+) create mode 100644 board/advantech/imx8mp_rsb3720a1/Kconfig create mode 100644 board/advantech/imx8mp_rsb3720a1/MAINTAINERS create mode 100644 board/advantech/imx8mp_rsb3720a1/Makefile create mode 100644 board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c create mode 100644 board/advantech/imx8mp_rsb3720a1/imximage-8mp-lpddr4.cfg create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_4G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/lpddr4_timing_rsb3720a1_6G.c create mode 100644 board/advantech/imx8mp_rsb3720a1/spl.c create mode 100644 configs/imx8mp_rsb3720a1_4G_defconfig create mode 100644 configs/imx8mp_rsb3720a1_6G_defconfig create mode 100644 include/configs/imx8mp_rsb3720.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b3e2a9c9d7..b11f936a90 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1158,6 +1158,9 @@ dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb +ifneq ($(CONFIG_TARGET_IMX8MP_RSB3720A1_4G)$(CONFIG_TARGET_IMX8MP_RSB3720A1_6G),) +dtb-y += imx8mp-rsb3720-a1.dtb +endif dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index d6a869068a..f0d3eefa02 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -160,8 +160,23 @@ config TARGET_IMX8MM_CL_IOT_GATE_OPTEE select IMX8MM select SUPPORT_SPL select IMX8M_LPDDR4 + +config TARGET_IMX8MP_RSB3720A1_4G + bool "Support i.MX8MP RSB3720A1 4G" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 + +config TARGET_IMX8MP_RSB3720A1_6G + bool "Support i.MX8MP RSB3720A1 6G" + select BINMAN + select IMX8MP + select SUPPORT_SPL + select IMX8M_LPDDR4 endchoice +source "board/advantech/imx8mp_rsb3720a1/Kconfig" source "board/beacon/imx8mm/Kconfig" source "board/beacon/imx8mn/Kconfig" source "board/compulab/imx8mm-cl-iot-gate/Kconfig" diff --git a/board/advantech/imx8mp_rsb3720a1/Kconfig b/board/advantech/imx8mp_rsb3720a1/Kconfig new file mode 100644 index 00..4486ed6d33 --- /dev/null +++ b/board/advantech/imx8mp_rsb3720a1/Kconfig @@ -0,0 +1,14 @@ +if TARGET_IMX8MP_RSB3720A1_4G || TARGET_IMX8MP_RSB3720A1_6G + +config SYS_BOARD + default "imx8mp_rsb3720a1" + +config SYS_VENDOR + default "advantech" + +config SYS_CONFIG_NAME + default "imx8mp_rsb3720" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/advantech/imx8mp_rsb3720a1/MAINTAINERS b/board/advantech/imx8mp_rsb3720a1/MAINTAINERS new file mode 100644 index 00..bc967af4f5 --- /dev/null +++ b/board/advantech/imx8mp_rsb3720a1/MAINTAINERS @@ -0,0 +1,7 @@ +i.MX8MP RSB3720 BOARD +M: Ying-Chun Liu (PaulLiu) +S: Maintained +F: board/advantech/imx8mp_rsb3720a1/ +F: include/configs/imx8mp_rsb3720a1.h +F: configs/imx8mp_rsb3720a1_4G_defconfig +F: configs/imx8mp_rsb3720a1_6G_defconfig diff --git a/board/advantech/imx8mp_rsb3720a1/Makefile b/board/advantech/imx8mp_rsb3720a1/Makefile new file mode 100644 index 00..eb6b18b04a --- /dev/null +++ b/board/advantech/imx8mp_rsb3720a1/Makefile @@ -0,0 +1,24 @@ +# +# Copyright 2019 NXP +# Copyright 2022 Linaro +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_TARGET_IMX8MP_RSB3720A1_6G +obj-y += imx8mp_rsb3720a1.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_rsb3720a1_6G.o +endif +endif + +ifdef CONFIG_TARGET_IMX8MP_RSB3720
RE: [PATCH v2] net: fsl_mdio: Fix busy flag polling register
> -Original Message-
> From: Markus Koch
> Sent: Friday, January 7, 2022 19:49
> To: Camelia Alexandra Groza (OSS) ;
> joe.hershber...@ni.com; rfried@gmail.com; Ioana Ciornei
>
> Cc: Madalin Bucur (OSS) ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH v2] net: fsl_mdio: Fix busy flag polling register
>
> On 1/7/22 17:23, Camelia Alexandra Groza (OSS) wrote:
> >> -Original Message-
> >> From: U-Boot On Behalf Of Markus
> Koch
> >> Sent: Tuesday, January 4, 2022 17:42
> >> To: Ioana Ciornei ; joe.hershber...@ni.com;
> >> rfried@gmail.com
> >> Cc: Madalin Bucur (OSS) ; Camelia
> Alexandra
> >> Groza ; u-boot@lists.denx.de; Markus Koch
> >>
> >> Subject: [PATCH v2] net: fsl_mdio: Fix busy flag polling register
> >>
> >> NXP's mEMAC reference manual, Chapter 6.5.5 "MDIO Ethernet
> >> Management
> >> Interface usage", specifies to poll the BSY (0) bit in the CFG/STAT
> >> register to wait until a transaction has finished, not bit 31 in the
> >> data register.
> >>
> >> In the Linux kernel, this has already been fixed in commit 26eee0210ad7
> >> ("net/fsl: fix a bug in xgmac_mdio").
> >>
> >> Signed-off-by: Markus Koch
> >
> > I am ok with the change for the mEMAC driver but MDIO_DATA_BSY is still
> > used by the fsl_ls_mdio driver. The MDIO driver suffers from the same
> issue.
> >
> > Please send a v3 and either patch both drivers or don't remove the define.
> > Also, if removing the define, please mention it explicitly in the patch
> > description.
>
> I'll change the other driver as well.
>
> There's also the fm/tgec_phy driver that uses the same construct, but it has
> its own define for MDIO_DATA_BSY. Should I also change that? I think it
> corresponds to Linux' xgmac_mdio.c which also uses the STAT_BSY register,
> but
> I don't have a datasheet to verify the register definition.
The TGEC controller has BUSY bits mirroring each other in both the
MDIO_DATA and MDIO_CFG_STAT registers. The tgec_phy driver doesn't need
changing.
Regards,
Camelia
> Thanks,
> Markus
>
> > Thanks,
> > Camelia
> >
> >> ---
> >>
> >> Changed to use the mdio_stat register. Thanks, Ioana!
> >>
> >> drivers/net/fm/memac_phy.c | 2 +-
> >> include/fsl_memac.h| 1 -
> >> 2 files changed, 1 insertion(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/net/fm/memac_phy.c b/drivers/net/fm/memac_phy.c
> >> index 72b500a6d1..3ddae97e09 100644
> >> --- a/drivers/net/fm/memac_phy.c
> >> +++ b/drivers/net/fm/memac_phy.c
> >> @@ -64,7 +64,7 @@ static int memac_wait_until_done(struct
> >> memac_mdio_controller *regs)
> >> {
> >>unsigned int timeout = MAX_NUM_RETRIES;
> >>
> >> - while ((memac_in_32(®s->mdio_data) & MDIO_DATA_BSY) &&
> >> timeout--)
> >> + while ((memac_in_32(®s->mdio_stat) & MDIO_STAT_BSY) &&
> >> timeout--)
> >>;
> >>
> >>if (!timeout) {
> >> diff --git a/include/fsl_memac.h b/include/fsl_memac.h
> >> index d067f1511c..6ac1e558b9 100644
> >> --- a/include/fsl_memac.h
> >> +++ b/include/fsl_memac.h
> >> @@ -254,7 +254,6 @@ struct memac_mdio_controller {
> >> #define MDIO_CTL_READ(1 << 15)
> >>
> >> #define MDIO_DATA(x) (x & 0x)
> >> -#define MDIO_DATA_BSY (1 << 31)
> >>
> >> struct fsl_enet_mac;
> >>
> >> --
> >> 2.34.1
> >
[PATCH 0/2] fix dumpimage for fit images
dumpimage does not work properly when an image includes "@" because signing would fail. However, this should be supported because it is enabled by default (even when signing is disabled). This patch series tries to fix this by just printing a warning instead of failing completely. Stefan Eichenberger (2): tools/fitimage: remove redundant format check tools/fitimage: make sure dumpimage still works when "@" are detected tools/fit_common.c | 12 ++-- tools/fit_image.c | 5 - 2 files changed, 10 insertions(+), 7 deletions(-) -- 2.32.0
[PATCH 1/2] tools/fitimage: remove redundant format check
fit_extract_contents does a fit_check_format even thought it was already
checked during imagetool_verify_print_header.
Therefore, this check is not necessary. This commit removes the
redundancy.
Signed-off-by: Stefan Eichenberger
---
tools/fit_image.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index f4f372ba62..62e1796ce5 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -884,11 +884,6 @@ static int fit_extract_contents(void *ptr, struct
image_tool_params *params)
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
- if (fit_check_format(fit, IMAGE_SIZE_INVAL)) {
- printf("Bad FIT image format\n");
- return -1;
- }
-
/* Find images parent node offset */
images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH);
if (images_noffset < 0) {
--
2.32.0
[PATCH 2/2] tools/fitimage: make sure dumpimage still works when "@" are detected
fit_verify_header fails if it detects unit addresses "@". However, this
will break tools like dumpimage on fit images which worked with previous
versions of the tool (e.g. 2020.04 vs 2021.07). As an example the output
of:
dumpimage -l
is:
FIT description: U-Boot fitImage for Linux Distribution
Created: Thu Jan 1 01:00:00 1970
Image 0 (kernel@1)
Description: Linux kernel
Created: Thu Jan 1 01:00:00 1970
Type: Kernel Image
Compression: gzip compressed
Data Size:6442456 Bytes = 6291.46 KiB = 6.14 MiB
Architecture: AArch64
OS: Linux
Load Address: 0x8008
Entry Point: 0x8008
Hash algo:sha256
Hash value: ...
Image 1 (fdt@freescale_fsl-s32g274a-evb.dtb)
Description: Flattened Device Tree blob
Created: Thu Jan 1 01:00:00 1970
Type: Flat Device Tree
Compression: uncompressed
Data Size:39661 Bytes = 38.73 KiB = 0.04 MiB
Architecture: AArch64
Hash algo:sha256
Hash value: ...
Default Configuration: 'conf@freescale_fsl-s32g274a-evb.dtb'
Configuration 0 (conf@freescale_fsl-s32g274a-evb.dtb)
Description: 1 Linux kernel, FDT blob
Kernel: kernel@1
FDT: fdt@freescale_fsl-s32g274a-evb.dtb
Hash algo:sha256
Hash value: unavailable
But with newer version it shows:
dumpimage -l
GP Header: Size d00dfeed LoadAddr 62f0a4
This commit will output a warning that unit addresses were detected but
will not fail:
dumpimage -l
Image contains unit addresses @, this will break signing
...
Signed-off-by: Stefan Eichenberger
---
tools/fit_common.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/tools/fit_common.c b/tools/fit_common.c
index 52b63296f8..5c8920de54 100644
--- a/tools/fit_common.c
+++ b/tools/fit_common.c
@@ -26,10 +26,18 @@
int fit_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
- if (fdt_check_header(ptr) != EXIT_SUCCESS ||
- fit_check_format(ptr, IMAGE_SIZE_INVAL))
+ int ret;
+
+ if (fdt_check_header(ptr) != EXIT_SUCCESS)
return EXIT_FAILURE;
+ ret = fit_check_format(ptr, IMAGE_SIZE_INVAL);
+ if (ret) {
+ if (ret != -EADDRNOTAVAIL)
+ return EXIT_FAILURE;
+ fprintf(stderr, "Image contains unit addresses @, this will
break signing\n");
+ }
+
return EXIT_SUCCESS;
}
--
2.32.0
Re: [PATCH] .mailmap: add Atish Patra, Anup Patel
On Sun, Jan 09, 2022 at 06:51:27PM +0100, Heinrich Schuchardt wrote: > Both have left Western Digital. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] lib/rsa: avoid -Wdiscarded-qualifiers
On Sun, Jan 09, 2022 at 03:39:40PM +0100, Heinrich Schuchardt wrote: > The return type of EVP_PKEY_get0_RSA() is const struct rsa_st *. > Our code drops the const qualifier leading to > > In file included from tools/lib/rsa/rsa-sign.c:1: > ./tools/../lib/rsa/rsa-sign.c: In function ‘rsa_add_verify_data’: > ./tools/../lib/rsa/rsa-sign.c:631:13: warning: > assignment discards ‘const’ qualifier from pointer target type > [-Wdiscarded-qualifiers] > 631 | rsa = EVP_PKEY_get0_RSA(pkey); > | ^ > > Add a type conversion. > > Signed-off-by: Heinrich Schuchardt Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
[ANN] U-Boot v2022.01 released
Hey all, It is release day and here is v2022.01. With this release we are now at the fourth of our 2 years past a number of DM migration deadlines. We're now at the point where conversion to CONFIG_DM itself must have been done, and I think nothing is tripping up on that deadline anymore, which is good. Note that we're introducing now a migration deadline of v2022.10 for using CONFIG_DM_KEYBOARD (and the warning will show up once next is merged to master, this is the last release without a deadline enforced). I want to again call attention to in general is the number of CONFIG symbols that need to be migrated to Kconfig still. If you maintain a board or SoC, please check for symbols specific to your area of code that aren't migrated yet and see how to move them. The tools/moveconfig.py tool can handle a lot of cases. If it's tricky please reach out. In terms of a changelog, git log --merges v2022.01-rc4..v2022.01 contains what I've pulled since the last RC or: git log --merges v2021.10..v2022.01 for changes since the last full release. As always, more details in pull requests (or the tags referenced by them) will result in more details here. With this, the merge window is now open and I'll be merging in the next branch shortly. v2022.04 is scheduled for release on Monday, April 4th 2022 and the merge window closes on January 31st. Thanks all! -- Tom signature.asc Description: PGP signature
[PATCH v3 0/3] Apple M1 power management controller support
This series adds support for the power management controller found on Apple SoCs based on the device tree bindings submitted to upstream Linux. This is needed to enable power domains for devices that haven't been enabled by earlier boot stages. ChangeLog: v3: - Extend Kconfig description - Add comment on driver priv struct member - Update device trees v2: - Drop unrelated changes from device tree update Mark Kettenis (3): arm: dts: apple: Update Apple M1 device trees arm: dts: apple: Add u-boot,dm-pre-reloc properties power: domain: Add Apple pmgr driver arch/arm/Kconfig|3 + arch/arm/dts/Makefile |5 +- arch/arm/dts/t8103-j274-u-boot.dtsi |1 + arch/arm/dts/t8103-j274.dts | 176 ++--- arch/arm/dts/t8103-j293-u-boot.dtsi |1 + arch/arm/dts/t8103-j293.dts | 135 ++-- arch/arm/dts/t8103-j313-u-boot.dtsi |1 + arch/arm/dts/t8103-j313.dts | 111 +++ arch/arm/dts/t8103-j456-u-boot.dtsi |1 + arch/arm/dts/t8103-j456.dts | 117 +++ arch/arm/dts/t8103-j457-u-boot.dtsi |1 + arch/arm/dts/t8103-j457.dts | 105 +++ arch/arm/dts/t8103-jxxx.dtsi| 143 arch/arm/dts/t8103-pmgr.dtsi| 1138 +++ arch/arm/dts/t8103-u-boot.dtsi | 25 + arch/arm/dts/t8103.dtsi | 675 +--- drivers/power/domain/Kconfig|9 + drivers/power/domain/Makefile |1 + drivers/power/domain/apple-pmgr.c | 113 +++ 19 files changed, 2340 insertions(+), 421 deletions(-) create mode 100644 arch/arm/dts/t8103-j274-u-boot.dtsi create mode 100644 arch/arm/dts/t8103-j293-u-boot.dtsi create mode 100644 arch/arm/dts/t8103-j313-u-boot.dtsi create mode 100644 arch/arm/dts/t8103-j313.dts create mode 100644 arch/arm/dts/t8103-j456-u-boot.dtsi create mode 100644 arch/arm/dts/t8103-j456.dts create mode 100644 arch/arm/dts/t8103-j457-u-boot.dtsi create mode 100644 arch/arm/dts/t8103-j457.dts create mode 100644 arch/arm/dts/t8103-jxxx.dtsi create mode 100644 arch/arm/dts/t8103-pmgr.dtsi create mode 100644 arch/arm/dts/t8103-u-boot.dtsi create mode 100644 drivers/power/domain/apple-pmgr.c -- 2.34.1
[PATCH v3 2/3] arm: dts: apple: Add u-boot,dm-pre-reloc properties
These are necessary to make sure the power domains needed for the
serial console are availble in the pre-relocation phase.
Signed-off-by: Mark Kettenis
Reviewed-by: Jaehoon Chung
Reviewed-by: Simon Glass
---
arch/arm/dts/t8103-j274-u-boot.dtsi | 1 +
arch/arm/dts/t8103-j293-u-boot.dtsi | 1 +
arch/arm/dts/t8103-j313-u-boot.dtsi | 1 +
arch/arm/dts/t8103-j456-u-boot.dtsi | 1 +
arch/arm/dts/t8103-j457-u-boot.dtsi | 1 +
arch/arm/dts/t8103-u-boot.dtsi | 25 +
6 files changed, 30 insertions(+)
create mode 100644 arch/arm/dts/t8103-j274-u-boot.dtsi
create mode 100644 arch/arm/dts/t8103-j293-u-boot.dtsi
create mode 100644 arch/arm/dts/t8103-j313-u-boot.dtsi
create mode 100644 arch/arm/dts/t8103-j456-u-boot.dtsi
create mode 100644 arch/arm/dts/t8103-j457-u-boot.dtsi
create mode 100644 arch/arm/dts/t8103-u-boot.dtsi
diff --git a/arch/arm/dts/t8103-j274-u-boot.dtsi
b/arch/arm/dts/t8103-j274-u-boot.dtsi
new file mode 100644
index 00..6c8dd5a56f
--- /dev/null
+++ b/arch/arm/dts/t8103-j274-u-boot.dtsi
@@ -0,0 +1 @@
+#include "t8103-u-boot.dtsi"
diff --git a/arch/arm/dts/t8103-j293-u-boot.dtsi
b/arch/arm/dts/t8103-j293-u-boot.dtsi
new file mode 100644
index 00..6c8dd5a56f
--- /dev/null
+++ b/arch/arm/dts/t8103-j293-u-boot.dtsi
@@ -0,0 +1 @@
+#include "t8103-u-boot.dtsi"
diff --git a/arch/arm/dts/t8103-j313-u-boot.dtsi
b/arch/arm/dts/t8103-j313-u-boot.dtsi
new file mode 100644
index 00..6c8dd5a56f
--- /dev/null
+++ b/arch/arm/dts/t8103-j313-u-boot.dtsi
@@ -0,0 +1 @@
+#include "t8103-u-boot.dtsi"
diff --git a/arch/arm/dts/t8103-j456-u-boot.dtsi
b/arch/arm/dts/t8103-j456-u-boot.dtsi
new file mode 100644
index 00..6c8dd5a56f
--- /dev/null
+++ b/arch/arm/dts/t8103-j456-u-boot.dtsi
@@ -0,0 +1 @@
+#include "t8103-u-boot.dtsi"
diff --git a/arch/arm/dts/t8103-j457-u-boot.dtsi
b/arch/arm/dts/t8103-j457-u-boot.dtsi
new file mode 100644
index 00..6c8dd5a56f
--- /dev/null
+++ b/arch/arm/dts/t8103-j457-u-boot.dtsi
@@ -0,0 +1 @@
+#include "t8103-u-boot.dtsi"
diff --git a/arch/arm/dts/t8103-u-boot.dtsi b/arch/arm/dts/t8103-u-boot.dtsi
new file mode 100644
index 00..43f552979d
--- /dev/null
+++ b/arch/arm/dts/t8103-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+
+&serial0 {
+ u-boot,dm-pre-reloc;
+};
+
+&pmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&ps_sio_busif {
+ u-boot,dm-pre-reloc;
+};
+
+&ps_sio {
+ u-boot,dm-pre-reloc;
+};
+
+&ps_uart_p {
+ u-boot,dm-pre-reloc;
+};
+
+&ps_uart0 {
+ u-boot,dm-pre-reloc;
+};
--
2.34.1
[PATCH v3 1/3] arm: dts: apple: Update Apple M1 device trees
This synchronizes the device trees with those that are in the
process of being upstreamed into Linux. This is mostly the
current state of the device trees on the asahilinux branch
with a few extra bits used by OpenBSD. This includes device
trees for machines that were still missing.
There are still some differences that will hopefully be resolved
soon.
Signed-off-by: Mark Kettenis
Reviewed-by: Jaehoon Chung
Reviewed-by: Simon Glass
---
ChangeLog:
v3: - Update device trees
arch/arm/dts/Makefile|5 +-
arch/arm/dts/t8103-j274.dts | 176 +++---
arch/arm/dts/t8103-j293.dts | 135 ++--
arch/arm/dts/t8103-j313.dts | 111
arch/arm/dts/t8103-j456.dts | 117
arch/arm/dts/t8103-j457.dts | 105
arch/arm/dts/t8103-jxxx.dtsi | 143 +
arch/arm/dts/t8103-pmgr.dtsi | 1138 ++
arch/arm/dts/t8103.dtsi | 675
9 files changed, 2184 insertions(+), 421 deletions(-)
create mode 100644 arch/arm/dts/t8103-j313.dts
create mode 100644 arch/arm/dts/t8103-j456.dts
create mode 100644 arch/arm/dts/t8103-j457.dts
create mode 100644 arch/arm/dts/t8103-jxxx.dtsi
create mode 100644 arch/arm/dts/t8103-pmgr.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aeaec7136f..1b65e65eb8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -34,7 +34,10 @@ dtb-$(CONFIG_TARGET_A7Y17LTE) += exynos78x0-axy17lte.dtb
dtb-$(CONFIG_ARCH_APPLE) += \
t8103-j274.dtb \
- t8103-j293.dtb
+ t8103-j293.dtb \
+ t8103-j313.dtb \
+ t8103-j456.dtb \
+ t8103-j457.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-evm.dtb \
diff --git a/arch/arm/dts/t8103-j274.dts b/arch/arm/dts/t8103-j274.dts
index aef1ae29b6..9bc592bcdb 100644
--- a/arch/arm/dts/t8103-j274.dts
+++ b/arch/arm/dts/t8103-j274.dts
@@ -10,126 +10,120 @@
/dts-v1/;
#include "t8103.dtsi"
+#include "t8103-jxxx.dtsi"
/ {
compatible = "apple,j274", "apple,t8103", "apple,arm-platform";
model = "Apple Mac mini (M1, 2020)";
aliases {
- serial0 = &serial0;
- ethernet0 = ð0;
- wifi0 = &wifi0;
- };
-
- chosen {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- stdout-path = "serial0";
-
- framebuffer0: framebuffer@0 {
- compatible = "apple,simple-framebuffer",
"simple-framebuffer";
- reg = <0 0 0 0>; /* To be filled by loader */
- /* Format properties will be added by loader */
- status = "disabled";
- };
- };
-
- memory@8 {
- device_type = "memory";
- reg = <0x8 0 0x2 0>; /* To be filled by loader */
+ ethernet0 = ðernet0;
};
};
-&serial0 {
- status = "okay";
+&wifi0 {
+ brcm,board-type = "apple,atlantisb";
};
-&pcie0_dart_0 {
- status = "okay";
-};
+/*
+ * Provide labels for the USB type C ports.
+ */
-&pcie0_dart_1 {
- status = "okay";
+&typec0 {
+ label = "USB-C Back-left";
};
-&pcie0_dart_2 {
- status = "okay";
+&typec1 {
+ label = "USB-C Back-right";
};
-&pcie0 {
- status = "okay";
-
- pci0: pci@0,0 {
- device_type = "pci";
- reg = <0x0 0x0 0x0 0x0 0x0>;
- pwren-gpios = <&smc 13 0>;
- reset-gpios = <&pinctrl_ap 152 0>;
- max-link-speed = <2>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-
- pci1: pci@1,0 {
- device_type = "pci";
- reg = <0x800 0x0 0x0 0x0 0x0>;
- reset-gpios = <&pinctrl_ap 153 0>;
- max-link-speed = <2>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-
- pci2: pci@2,0 {
- device_type = "pci";
- reg = <0x1000 0x0 0x0 0x0 0x0>;
- reset-gpios = <&pinctrl_ap 33 0>;
- max-link-speed = <1>;
-
- #address-cells = <3>;
- #size-cells = <2>;
- ranges;
- };
-};
+/*
+ * Force the bus number assignments so that we can declare some of the
+ * on-board devices and properties that are populated by the bootloader
+ * (such as MAC addresses).
+ */
-&pci0 {
- wifi0: network@0,0 {
- reg = <0x1 0x0 0x0 0x0 0x0>;
- local-mac-address = [00 00 00 00 00 00];
- };
+&port01 {
+ bus-range = <2 2>;
};
-&pci2 {
- eth0: ethernet@0,0 {
+&port02 {
+ bus-range = <3 3>;
+ ethernet0: ethernet@0,0 {
reg = <0x3 0x0 0x0 0x0 0x0>;
- local-mac-address = [00 00 00 00 00 00];
+ /* To be filled by the loader */
+ local-mac-address = [00 10 18 00 00 00];
[PATCH v3 3/3] power: domain: Add Apple pmgr driver
This driver supports power domains for the power management
controller found on Apple SoCs.
Signed-off-by: Mark Kettenis
Reviewed-by: Jaehoon Chung
Reviewed-by: Simon Glass
---
ChangeLog:
v3: - Extend Kconfig description
- Add comment on driver priv struct member
arch/arm/Kconfig | 3 +
drivers/power/domain/Kconfig | 9 +++
drivers/power/domain/Makefile | 1 +
drivers/power/domain/apple-pmgr.c | 113 ++
4 files changed, 126 insertions(+)
create mode 100644 drivers/power/domain/apple-pmgr.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 78c6b2e92d..44954977b6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -942,6 +942,9 @@ config ARCH_APPLE
select OF_CONTROL
select PINCTRL
select POSITION_INDEPENDENT
+ select POWER_DOMAIN
+ select REGMAP
+ select SYSCON
select SYSRESET
select SYSRESET_WATCHDOG
select SYSRESET_WATCHDOG_AUTO
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index 99b3f9ae71..9aea5fcdf0 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -9,6 +9,15 @@ config POWER_DOMAIN
domains). This may be used to save power. This API provides the
means to control such power management hardware.
+config APPLE_PMGR_POWER_DOMAIN
+ bool "Enable the Apple PMGR power domain driver"
+ depends on POWER_DOMAIN
+ default y if ARCH_APPLE
+ help
+ Enable support for manipulating power domains on Apple SoCs.
+ This driver is needed to power on parts of the SoC that have
+ not been powered on by previous boot stages.
+
config BCM6328_POWER_DOMAIN
bool "Enable the BCM6328 power domain driver"
depends on POWER_DOMAIN && ARCH_BMIPS
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 3d1e5f073c..530ae35671 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_$(SPL_)POWER_DOMAIN) += power-domain-uclass.o
+obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o
imx8-power-domain.o
obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
diff --git a/drivers/power/domain/apple-pmgr.c
b/drivers/power/domain/apple-pmgr.c
new file mode 100644
index 00..d25f136b9d
--- /dev/null
+++ b/drivers/power/domain/apple-pmgr.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2021 Mark Kettenis
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define APPLE_PMGR_PS_TARGET GENMASK(3, 0)
+#define APPLE_PMGR_PS_ACTUAL GENMASK(7, 4)
+
+#define APPLE_PMGR_PS_ACTIVE 0xf
+#define APPLE_PMGR_PS_PWRGATE 0x0
+
+#define APPLE_PMGR_PS_SET_TIMEOUT_US 100
+
+struct apple_pmgr_priv {
+ struct regmap *regmap;
+ u32 offset; /* offset within regmap for this domain */
+};
+
+static int apple_pmgr_request(struct power_domain *power_domain)
+{
+ return 0;
+}
+
+static int apple_pmgr_rfree(struct power_domain *power_domain)
+{
+ return 0;
+}
+
+static int apple_pmgr_ps_set(struct power_domain *power_domain, u32 pstate)
+{
+ struct apple_pmgr_priv *priv = dev_get_priv(power_domain->dev);
+ uint reg;
+
+ regmap_update_bits(priv->regmap, priv->offset, APPLE_PMGR_PS_TARGET,
+ FIELD_PREP(APPLE_PMGR_PS_TARGET, pstate));
+
+ return regmap_read_poll_timeout(
+ priv->regmap, priv->offset, reg,
+ (FIELD_GET(APPLE_PMGR_PS_ACTUAL, reg) == pstate), 1,
+ APPLE_PMGR_PS_SET_TIMEOUT_US);
+}
+
+static int apple_pmgr_on(struct power_domain *power_domain)
+{
+ return apple_pmgr_ps_set(power_domain, APPLE_PMGR_PS_ACTIVE);
+}
+
+static int apple_pmgr_off(struct power_domain *power_domain)
+{
+ return 0;
+}
+
+static int apple_pmgr_of_xlate(struct power_domain *power_domain,
+ struct ofnode_phandle_args *args)
+{
+ if (args->args_count != 0) {
+ debug("Invalid args_count: %d\n", args->args_count);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id apple_pmgr_ids[] = {
+ { .compatible = "apple,pmgr-pwrstate" },
+ { /* sentinel */ }
+};
+
+static int apple_pmgr_probe(struct udevice *dev)
+{
+ struct apple_pmgr_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = dev_power_domain_on(dev);
+ if (ret)
+ return ret;
+
+ priv->regmap = syscon_get_regmap(dev->parent);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ ret = dev_read_u32(dev, "reg", &priv->offset);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+struct power_domain_ops apple_pmgr_op
Re: [PATCH 0/4] Apple M1 watchdog timer
> From: Mark Kettenis > Date: Sun, 14 Nov 2021 12:19:39 +0100 > > This series adds a driver for the watchdog timer found on Apple's > M1 SoC and replaces the reset_cpu() function in the board file > with sysreset. The driver is based on the Linux binding proposed > in [1]. > > [1] > https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2023094732.73889-1-s...@svenpeter.dev/ > > Mark Kettenis (3): > watchdog: Add a driver for the Apple watchdog > arm: dts: apple: Add watchdog timer node > arm: apple: Use watchdog timer for system reset Hi Stefan, This series is delegated to you in patchwork[1]. Not sure why though. But if watchdogs are indeed your thing, can you have a look now that 2022.01 is out of the door? Thanks, Mark [1] https://patchwork.ozlabs.org/project/uboot/list/?series=271919
Re: [PATCH 1/6] cmd: exception: arm64: fix undefined, add faults
> Date: Sun, 9 Jan 2022 23:19:10 +
> From: Andre Przywara
>
> On Sun, 9 Jan 2022 23:47:32 +0100 (CET)
> Mark Kettenis wrote:
>
> Hi Mark,
>
> (I knew I forgot to CC: one person ...)
>
> > > Date: Sun, 9 Jan 2022 22:35:27 +
> > > From: Andre Przywara
> > >
> > > Hi Heinrich,
> > >
> > > > On 1/9/22 22:31, Andre Przywara wrote:
> > > > > On Sun, 9 Jan 2022 20:08:41 +0100
> > > > > Heinrich Schuchardt wrote:
> > > > >
> > > > >> On 1/9/22 18:30, Andre Przywara wrote:
> > > > >>> The arm64 version of the exception command was just defining the
> > > > >>> undefined exception, but actually copied the AArch32 instruction.
> > > > >>>
> > > > >>> Replace that with an encoding that is guaranteed to be and stay
> > > > >>> undefined. Also add instructions to trigger unaligned access faults
> > > > >>> and
> > > > >>> a breakpoint.
> > > > >>> This brings ARM64 on par with ARM(32) for the exception command.
> > > > >>>
> > > > >>> Signed-off-by: Andre Przywara
> > > > >>> ---
> > > > >>>cmd/arm/exception64.c | 42
> > > > >>> ++
> > > > >>>1 file changed, 38 insertions(+), 4 deletions(-)
> > > > >>>
> > > > >>> diff --git a/cmd/arm/exception64.c b/cmd/arm/exception64.c
> > > > >>> index d5de50a0803..1a9730e6aec 100644
> > > > >>> --- a/cmd/arm/exception64.c
> > > > >>> +++ b/cmd/arm/exception64.c
> > > > >>> @@ -12,14 +12,46 @@ static int do_undefined(struct cmd_tbl *cmdtp,
> > > > >>> int flag, int argc,
> > > > >>> char *const argv[])
> > > > >>>{
> > > > >>> /*
> > > > >>> -* 0xe7f...f. is undefined in ARM mode
> > > > >>> -* 0xde.. is undefined in Thumb mode
> > > > >>> +* Instructions starting with the upper 16 bits all 0 are
> > > > >>> permanently
> > > > >>> +* undefined. The lower 16 bits can be used for some kind of
> > > > >>> immediate.
> > > > >>> +* --- ARMv8 ARM (ARM DDI 0487G.a C6.2.339: "UDF")
> > > > >>> */
> > > > >>> - asm volatile (".word 0xe7f7defb\n");
> > > > >>> + asm volatile (".word 0x1234\n");
> > > > >>> +
> > > > >>> + return CMD_RET_FAILURE;
> > > > >>> +}
> > > > >>> +
> > > > >>> +static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc,
> > > > >>> + char *const argv[])
> > > > >>> +{
> > > > >>> + /*
> > > > >>> +* The load acquire instruction requires the data source to be
> > > > >>> +* naturally aligned, and will fault even if strict alignment
> > > > >>> fault
> > > > >>> +* checking is disabled.
> > > > >>> +* --- ARMv8 ARM (ARM DDI 0487G.a B2.5.2: "Alignment of data
> > > > >>> accesses")
> > > > >>
> > > > >> According to DI0487G_b_armv8_arm.pdf available at
> > > > >> https://developer.arm.com/documentation/ddi0487/latest the
> > > > >> generation of
> > > > >> an alignment fault for ldar depends on FEAT_LSE2 (Large System
> > > > >> Extensions v2) which is mandatory for ARMv8.4. See p. B2-161.
> > > > >
> > > > > Well found, but I wonder if that matters for the SoCs running U-Boot.
> > > > > It looks like the Apple M1 is the only one so far and will probably
> > > > > stay for a while.
> > > >
> > > > Developers are using U-Boot on Apple M1 already.
> > >
> > > Yeah, sorry, I didn't realise that the M1 is fully v8.4 compliant. Most
> > > other SoCs I checked are v8.2/v8.3 + some 8.4 features, at most. The
> > > Cortex-A76/Neoverse-N1 for instance does not have LSE2.
> > >
> > > > > But I can of course check ID_AA64MMFR2_EL1.AT before executing the
> > > > > LDAR,
> > > > > and will ask around for a better method to provoke unaligned
> > > > > accesses.
> > > >
> > > > It is sufficient if you update the comment for this function. Returning
> > > > CMD_RET_FAILURE as return value if unaligned access is supported is
> > > > fine. Cf. cmd/riscv/exception.c. (On RISC-V OpenSBI emulates unaligned
> > > > access.)
> > >
> > > Well, I now have the check and a message, always returning FAILURE in
> > > this case. Let me see if people in the office have a better idea...
> > >
> > > > Maybe we should also add a comment in doc/usage/exception.rst.
> > >
> > > By the way: this was triggered by my need to check SError generation. I
> > > don't know of a nice architectural way to trigger an SError (yet), but
> > > some SoCs happily generate one by accessing unimplemented memory regions
> > > (beyond DRAM, for instance). So I could trigger it on my Juno board
> > > with a specific address, but not on an Allwinner board so far.
> > > Do you think it's worthwhile to have a platform specific address in
> > > Kconfig to implement the serror exception sub-command?
> >
> > Well, on the M1 writing to the serial port output register with the
> > wrong width (8 bits instead of 32 bits) triggered an SError while
> > still producing output. But once the OS booted, it did panic with an
> > SError. Which indeed caused some head scratching like you described.
[BUG] sandbox: NO_SDL=1 gcc: error: arch/sandbox/cpu/sdl.o: No such file or directory
Hello Simon, compiling with SDL fails on Alpine Linux: https://gitlab.alpinelinux.org/alpine/aports/-/issues/13411 So I tried NO_SDL: make sandbox_defconfig NO_SDL=1 make menuconfig # CONFIG_ETH_SANDBOX_RAW=n make -j4 NO_SDL=1 But I got an error gcc: error: arch/sandbox/cpu/sdl.o: No such file or directory Can't we make CONFIG_SANDBOX_SDL a Kconfig symbol to get rid of the command line symbol? We already have CONFIG_SANDBOX_VIDEO_SDL. Do we need two symbols? Best regards Heinrich
[PATCH 1/1] doc: Building on Alpine Linux
Describe the required packages for building U-Boot on Alpine Linux Signed-off-by: Heinrich Schuchardt --- doc/build/gcc.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/doc/build/gcc.rst b/doc/build/gcc.rst index cdd7970032..5299b8a18a 100644 --- a/doc/build/gcc.rst +++ b/doc/build/gcc.rst @@ -51,6 +51,16 @@ Depending on the build targets further packages maybe needed. zypper install bc bison flex gcc libopenssl-devel libSDL2-devel make \ ncurses-devel python3-devel python3-pytest swig +Alpine Linux + + +For building U-Boot on Alpine Linx at least the following packages are needed: + +.. code-block:: bash + +apk add alpine-sdk bc bison dtc flex linux-headers ncurses-dev \ + openssl-dev python3 py3-setuptools python3-dev sdl2 + Prerequisites - -- 2.33.1
[PATCH 1/1] sandbox: compatibility of os_get_filesize()
U-Boot define loff_t as long long. But the header
/usr/include/linux/types.h may not define it.
This has lead to a build error on Alpine Linux.
So let's use long long instead of loff_t for
the size parameter of function os_get_filesize().
Reported-by: Milan P. Stanić
Signed-off-by: Heinrich Schuchardt
---
arch/sandbox/cpu/os.c | 10 --
include/os.h | 2 +-
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c
index 6837bfceaf..40ebe322ae 100644
--- a/arch/sandbox/cpu/os.c
+++ b/arch/sandbox/cpu/os.c
@@ -624,7 +624,13 @@ const char *os_dirent_get_typename(enum os_dirent_t type)
return os_dirent_typename[OS_FILET_UNKNOWN];
}
-int os_get_filesize(const char *fname, loff_t *size)
+/*
+ * For compatibility reasons avoid loff_t here.
+ * U-Boot defines loff_t as long long.
+ * But /usr/include/linux/types.h may not define it at all.
+ * Alpine Linux being one example.
+ */
+int os_get_filesize(const char *fname, long long *size)
{
struct stat buf;
int ret;
@@ -667,7 +673,7 @@ int os_read_ram_buf(const char *fname)
{
struct sandbox_state *state = state_get_current();
int fd, ret;
- loff_t size;
+ long long size;
ret = os_get_filesize(fname, &size);
if (ret < 0)
diff --git a/include/os.h b/include/os.h
index 4cbcbd93a7..10e198cf50 100644
--- a/include/os.h
+++ b/include/os.h
@@ -266,7 +266,7 @@ const char *os_dirent_get_typename(enum os_dirent_t type);
* @size: size of file is returned if no error
* Return: 0 on success or -1 if an error ocurred
*/
-int os_get_filesize(const char *fname, loff_t *size);
+int os_get_filesize(const char *fname, long long *size);
/**
* os_putc() - write a character to the controlling OS terminal
--
2.33.1
Re: [RESEND PATCH v3 01/12] mmc: fsl_esdhc_imx: make BLK as hard requirement of DM_MMC
Dear Sean,
On 1/5/22 1:16 AM, Sean Anderson wrote:
> [ fsl_esdhc commit 41dec2fe99512e941261594f522b2e7d485c314b ]
>
> U-boot prefers DM_MMC + BLK for MMC. Now eSDHC driver has already
> support it, so let's force to use it.
>
> - Drop non-BLK support for DM_MMC introduced by below patch.
> 66fa035 mmc: fsl_esdhc: fix probe issue without CONFIG_BLK enabled
>
> - Support only DM_MMC + BLK (assuming BLK is always enabled for DM_MMC).
>
> - Use DM_MMC instead of BLK for conditional compile.
Thanks for resend this. But it can't apply your patch from patchwork directly.
https://patchwork.ozlabs.org/project/uboot/patch/17862939-c7b1-310e-d98e-ce68f776e...@seco.com/
If you're ok, I will apply after modified your patch.
Best Regards,
Jaehoon Chung
>
> Signed-off-by: Yangbo Lu
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v3:
> - Drop Kconfig BLK dependency
>
> drivers/mmc/fsl_esdhc_imx.c | 33 +
> 1 file changed, 1 insertion(+), 32 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c
> index 4c06361bee..85cd72a796 100644
> --- a/drivers/mmc/fsl_esdhc_imx.c
> +++ b/drivers/mmc/fsl_esdhc_imx.c
> @@ -39,10 +39,6 @@
> #include
> #include
> -#if !CONFIG_IS_ENABLED(BLK)
> -#include "mmc_private.h"
> -#endif
> -
> #ifndef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
> #ifdef CONFIG_FSL_USDHC
> #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE 1
> @@ -58,7 +54,6 @@ DECLARE_GLOBAL_DATA_PTR;
> IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
> IRQSTATEN_DINT)
> #define MAX_TUNING_LOOP 40
> -#define ESDHC_DRIVER_STAGE_VALUE 0x
> struct fsl_esdhc {
> uint dsaddr; /* SDMA system address register */
> @@ -157,7 +152,7 @@ struct fsl_esdhc_priv {
> unsigned int clock;
> unsigned int mode;
> unsigned int bus_width;
> -#if !CONFIG_IS_ENABLED(BLK)
> +#if !CONFIG_IS_ENABLED(DM_MMC)
> struct mmc *mmc;
> #endif
> struct udevice *dev;
> @@ -1510,9 +1505,6 @@ static int fsl_esdhc_probe(struct udevice *dev)
> struct esdhc_soc_data *data =
> (struct esdhc_soc_data *)dev_get_driver_data(dev);
> struct mmc *mmc;
> -#if !CONFIG_IS_ENABLED(BLK)
> - struct blk_desc *bdesc;
> -#endif
> int ret;
> #if CONFIG_IS_ENABLED(OF_PLATDATA)
> @@ -1611,25 +1603,6 @@ static int fsl_esdhc_probe(struct udevice *dev)
> mmc = &plat->mmc;
> mmc->cfg = &plat->cfg;
> mmc->dev = dev;
> -#if !CONFIG_IS_ENABLED(BLK)
> - mmc->priv = priv;
> -
> - /* Setup dsr related values */
> - mmc->dsr_imp = 0;
> - mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
> - /* Setup the universal parts of the block interface just once */
> - bdesc = mmc_get_blk_desc(mmc);
> - bdesc->if_type = IF_TYPE_MMC;
> - bdesc->removable = 1;
> - bdesc->devnum = mmc_get_next_devnum();
> - bdesc->block_read = mmc_bread;
> - bdesc->block_write = mmc_bwrite;
> - bdesc->block_erase = mmc_berase;
> -
> - /* setup initial part type */
> - bdesc->part_type = mmc->cfg->part_type;
> - mmc_list_add(mmc);
> -#endif
> upriv->mmc = mmc;
> @@ -1740,14 +1713,12 @@ static const struct udevice_id fsl_esdhc_ids[] = {
> { /* sentinel */ }
> };
> -#if CONFIG_IS_ENABLED(BLK)
> static int fsl_esdhc_bind(struct udevice *dev)
> {
> struct fsl_esdhc_plat *plat = dev_get_plat(dev);
> return mmc_bind(dev, &plat->mmc, &plat->cfg);
> }
> -#endif
> U_BOOT_DRIVER(fsl_esdhc) = {
> .name = "fsl_esdhc",
> @@ -1755,9 +1726,7 @@ U_BOOT_DRIVER(fsl_esdhc) = {
> .of_match = fsl_esdhc_ids,
> .of_to_plat = fsl_esdhc_of_to_plat,
> .ops = &fsl_esdhc_ops,
> -#if CONFIG_IS_ENABLED(BLK)
> .bind = fsl_esdhc_bind,
> -#endif
> .probe = fsl_esdhc_probe,
> .plat_auto = sizeof(struct fsl_esdhc_plat),
> .priv_auto = sizeof(struct fsl_esdhc_priv),
Re: [PATCH 2/2] ARM: mvebu: x530: Add option for ECC
On Mon, Jan 10, 2022 at 9:10 PM Chris Packham wrote:
>
>
>
> On Mon, 10 Jan 2022, 8:37 PM Stefan Roese, wrote:
>>
>> On 1/6/22 04:08, Chris Packham wrote:
>> > Some older x530 boards have layout issues that cause problems for DDR.
>> > These are usually seen as training failures but can also cause problems
>> > after training has completed. Add an option to enable ECC leaving the
>> > default as N which will work with both old and new boards.
>> >
>> > Signed-off-by: Chris Packham
>>
>> Just checking: Most likely you don't have the possibility to detect the
>> board version at runtime?
>
>
> Not in a way that can be done without working RAM. For our internal fork we
> maintain 2 defconfigs one with ECC one without. We can manage via the BOM
> which boards get which bootloader.
>
>>
>> If this is not possible:
>>
>> Reviewed-by: Stefan Roese
>>
>> Thanks,
>> Stefan
>>
>> > ---
>> >
>> > arch/arm/mach-mvebu/Kconfig | 1 +
>> > board/alliedtelesis/x530/Kconfig | 20
>> > board/alliedtelesis/x530/x530.c | 8 +++-
>> > 3 files changed, 28 insertions(+), 1 deletion(-)
>> > create mode 100644 board/alliedtelesis/x530/Kconfig
>> >
>> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
>> > index d23cc0c760f1..7388ade98d52 100644
>> > --- a/arch/arm/mach-mvebu/Kconfig
>> > +++ b/arch/arm/mach-mvebu/Kconfig
>> > @@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX
>> >
>> > source "board/solidrun/clearfog/Kconfig"
>> > source "board/kobol/helios4/Kconfig"
>> > +source "board/alliedtelesis/x530/Kconfig"
>> >
>> > endif
>> > diff --git a/board/alliedtelesis/x530/Kconfig
>> > b/board/alliedtelesis/x530/Kconfig
>> > new file mode 100644
>> > index ..5c1ae36aebaa
>> > --- /dev/null
>> > +++ b/board/alliedtelesis/x530/Kconfig
>> > @@ -0,0 +1,20 @@
>> > +menu "x530 configuration"
>> > + depends on TARGET_X530
>> > +
>> > +config X530_ECC
>> > + bool "Enable DDR3 ECC"
>> > + help
>> > + Some of the older x530 board have layout issues which cause
>> > problems
>> > + for the DDR which usually exhibit as DDR training failures or
>> > + problems accessing DDR after training.
>> > +
>> > + The known affected boards are:
>> > +
>> > + * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm)
>> > + * 844-001948-00 (GS980MX/28)
>> > + * 844-002008-00 (x530L-52GTX, x530L-52GPX)
>> > + * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm)
>> > +
>> > + If you have a newer board you can set Y here, otherwise say N.
>> > +
>> > +endmenu
>> > diff --git a/board/alliedtelesis/x530/x530.c
>> > b/board/alliedtelesis/x530/x530.c
>> > index 866b6e68cc16..de20684f4353 100644
>> > --- a/board/alliedtelesis/x530/x530.c
>> > +++ b/board/alliedtelesis/x530/x530.c
>> > @@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map
>> > **serdes_map_array, u8 *count)
>> > return 0;
>> > }
>> >
>> > +#if CONFIG_IS_ENABLED(X530_ECC)
>> > + #define BUS_MASK BUS_MASK_32BIT_ECC
>> > +#else
>> > + #define BUS_MASK BUS_MASK_32BIT
>> > +#endif
>> > +
Hmm this doesn't actually appear to be working as intended. When the
SPL is built I end up with CONFIG_IS_ENABLED(X530_ECC) == 0 even when
I set it to y. Do I need to define a SPL version of this Kconfig
symbol?
>> > /*
>> >* Define the DDR layout / topology here in the board file. This will
>> >* be used by the DDR3 init code in the SPL U-Boot version to configure
>> > @@ -66,7 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
>> > 0, 0, /* cas_l cas_wl */
>> > MV_DDR_TEMP_LOW,/* temperature */
>> > MV_DDR_TIM_2T} }, /* timing */
>> > - BUS_MASK_32BIT_ECC, /* subphys mask */
>> > + BUS_MASK, /* subphys mask */
>> > MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
>> > NOT_COMBINED, /* ddr twin-die combined */
>> > { {0} },/* raw spd data */
>> >
>>
>> Viele Grüße,
>> Stefan Roese
>>
>> --
>> DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
>> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
>> Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de
Re: [PATCH 2/2] ARM: mvebu: x530: Add option for ECC
On Tue, Jan 11, 2022 at 02:37:53PM +1300, Chris Packham wrote: > On Mon, Jan 10, 2022 at 9:10 PM Chris Packham wrote: > > > > > > > > On Mon, 10 Jan 2022, 8:37 PM Stefan Roese, wrote: > >> > >> On 1/6/22 04:08, Chris Packham wrote: > >> > Some older x530 boards have layout issues that cause problems for DDR. > >> > These are usually seen as training failures but can also cause problems > >> > after training has completed. Add an option to enable ECC leaving the > >> > default as N which will work with both old and new boards. > >> > > >> > Signed-off-by: Chris Packham > >> > >> Just checking: Most likely you don't have the possibility to detect the > >> board version at runtime? > > > > > > Not in a way that can be done without working RAM. For our internal fork we > > maintain 2 defconfigs one with ECC one without. We can manage via the BOM > > which boards get which bootloader. > > > >> > >> If this is not possible: > >> > >> Reviewed-by: Stefan Roese > >> > >> Thanks, > >> Stefan > >> > >> > --- > >> > > >> > arch/arm/mach-mvebu/Kconfig | 1 + > >> > board/alliedtelesis/x530/Kconfig | 20 > >> > board/alliedtelesis/x530/x530.c | 8 +++- > >> > 3 files changed, 28 insertions(+), 1 deletion(-) > >> > create mode 100644 board/alliedtelesis/x530/Kconfig > >> > > >> > diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig > >> > index d23cc0c760f1..7388ade98d52 100644 > >> > --- a/arch/arm/mach-mvebu/Kconfig > >> > +++ b/arch/arm/mach-mvebu/Kconfig > >> > @@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX > >> > > >> > source "board/solidrun/clearfog/Kconfig" > >> > source "board/kobol/helios4/Kconfig" > >> > +source "board/alliedtelesis/x530/Kconfig" > >> > > >> > endif > >> > diff --git a/board/alliedtelesis/x530/Kconfig > >> > b/board/alliedtelesis/x530/Kconfig > >> > new file mode 100644 > >> > index ..5c1ae36aebaa > >> > --- /dev/null > >> > +++ b/board/alliedtelesis/x530/Kconfig > >> > @@ -0,0 +1,20 @@ > >> > +menu "x530 configuration" > >> > + depends on TARGET_X530 > >> > + > >> > +config X530_ECC > >> > + bool "Enable DDR3 ECC" > >> > + help > >> > + Some of the older x530 board have layout issues which cause > >> > problems > >> > + for the DDR which usually exhibit as DDR training failures or > >> > + problems accessing DDR after training. > >> > + > >> > + The known affected boards are: > >> > + > >> > + * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm) > >> > + * 844-001948-00 (GS980MX/28) > >> > + * 844-002008-00 (x530L-52GTX, x530L-52GPX) > >> > + * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm) > >> > + > >> > + If you have a newer board you can set Y here, otherwise say N. > >> > + > >> > +endmenu > >> > diff --git a/board/alliedtelesis/x530/x530.c > >> > b/board/alliedtelesis/x530/x530.c > >> > index 866b6e68cc16..de20684f4353 100644 > >> > --- a/board/alliedtelesis/x530/x530.c > >> > +++ b/board/alliedtelesis/x530/x530.c > >> > @@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map > >> > **serdes_map_array, u8 *count) > >> > return 0; > >> > } > >> > > >> > +#if CONFIG_IS_ENABLED(X530_ECC) > >> > + #define BUS_MASK BUS_MASK_32BIT_ECC > >> > +#else > >> > + #define BUS_MASK BUS_MASK_32BIT > >> > +#endif > >> > + > > Hmm this doesn't actually appear to be working as intended. When the > SPL is built I end up with CONFIG_IS_ENABLED(X530_ECC) == 0 even when > I set it to y. Do I need to define a SPL version of this Kconfig > symbol? If you're using CONFIG_IS_ENABLED, then yes. It doesn't always make sense to use CONFIG_IS_ENABLED or other macros rather than just #ifdef checks. -- Tom signature.asc Description: PGP signature
[PATCH V8] arm: add initial support for the Phytium Pomelo Board
From: weichangzheng
This adds platform code and the device tree for the Phytium Pomelo Board.
The initial support comprises the UART and the PCIE.
Signed-off-by: weichangzheng
Changes since v1:
updated to DT
Changes since v2:
Modify some explicit types and macro
Changes since v3:
Modify some SDRAM related macro definitions and distro_bootcmd
Changes since v4:
Modify distro_bootcmd
Changes since v5:
Modify the CPU node description of the DT
Changes since v6:
Modify DT
Changes since v7:
Modify DT
---
arch/arm/Kconfig | 20
arch/arm/dts/Makefile| 1 +
arch/arm/dts/phytium-pomelo.dts | 111 +
board/phytium/pomelo/Kconfig | 12 +++
board/phytium/pomelo/MAINTAINERS | 8 ++
board/phytium/pomelo/Makefile| 14 +++
board/phytium/pomelo/cpu.h | 73 ++
board/phytium/pomelo/ddr.c | 161 +++
board/phytium/pomelo/pcie.c | 60
board/phytium/pomelo/pll.c | 73 ++
board/phytium/pomelo/pomelo.c| 118 ++
board/phytium/pomelo/sec.c | 37 +++
configs/pomelo_defconfig | 18
include/configs/pomelo.h | 44 +
14 files changed, 750 insertions(+)
create mode 100644 arch/arm/dts/phytium-pomelo.dts
create mode 100644 board/phytium/pomelo/Kconfig
create mode 100644 board/phytium/pomelo/MAINTAINERS
create mode 100644 board/phytium/pomelo/Makefile
create mode 100644 board/phytium/pomelo/cpu.h
create mode 100644 board/phytium/pomelo/ddr.c
create mode 100644 board/phytium/pomelo/pcie.c
create mode 100644 board/phytium/pomelo/pll.c
create mode 100644 board/phytium/pomelo/pomelo.c
create mode 100644 board/phytium/pomelo/sec.c
create mode 100644 configs/pomelo_defconfig
create mode 100644 include/configs/pomelo.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0448787b8b..029af85fcb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1818,6 +1818,25 @@ config TARGET_DURIAN
Support for durian platform.
It has 2GB Sdram, uart and pcie.
+config TARGET_POMELO
+ bool "Support Phytium Pomelo Platform"
+ select ARM64
+ select DM
+ select AHCI
+ select SCSI_AHCI
+ select AHCI_PCI
+ select BLK
+ select PCI
+ select DM_PCI
+ select SCSI
+ select DM_SCSI
+ select DM_SERIAL
+ select DM_ETH if NET
+ imply CMD_PCI
+ help
+ Support for pomelo platform.
+ It has 8GB Sdram, uart and pcie.
+
config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
@@ -2038,6 +2057,7 @@ source "board/toradex/colibri_pxa270/Kconfig"
source "board/variscite/dart_6ul/Kconfig"
source "board/vscom/baltos/Kconfig"
source "board/phytium/durian/Kconfig"
+source "board/phytium/pomelo/Kconfig"
source "board/xen/xenguest_arm64/Kconfig"
source "board/keymile/Kconfig"
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9fb38682e6..45d0340bd3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1107,6 +1107,7 @@ dtb-$(CONFIG_TARGET_MX53PPD) += imx53-ppd.dtb
dtb-$(CONFIG_TARGET_TOTAL_COMPUTE) += total_compute.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
+dtb-$(CONFIG_TARGET_POMELO) += phytium-pomelo.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
diff --git a/arch/arm/dts/phytium-pomelo.dts b/arch/arm/dts/phytium-pomelo.dts
new file mode 100644
index 00..77e3e9e21f
--- /dev/null
+++ b/arch/arm/dts/phytium-pomelo.dts
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Phytium Pomelo board
+ * Copyright (C) 2021, Phytium Ltd.
+ * lixinde
+ * weichangzheng
+ */
+/dts-v1/;
+
+/ {
+ model = "Phytium Pomelo Board";
+ compatible = "phytium,d2000-pomelo", "phytium,d2000";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "phytium,ftc663", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "phytium,ftc663", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "phytium,ftc663", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@101 {
+ devic
[PATCH v2] ARM: mvebu: x530: Add option for ECC
Some older x530 boards have layout issues that cause problems for DDR.
These are usually seen as training failures but can also cause problems
after training has completed. Add an option to enable ECC leaving the
default as N which will work with both old and new boards.
Signed-off-by: Chris Packham
Reviewed-by: Stefan Roese
---
Changes in v2:
- Define Kconfig symbol for SPL.
arch/arm/mach-mvebu/Kconfig | 1 +
board/alliedtelesis/x530/Kconfig | 25 +
board/alliedtelesis/x530/x530.c | 8 +++-
3 files changed, 33 insertions(+), 1 deletion(-)
create mode 100644 board/alliedtelesis/x530/Kconfig
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index d23cc0c760f1..7388ade98d52 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX
source "board/solidrun/clearfog/Kconfig"
source "board/kobol/helios4/Kconfig"
+source "board/alliedtelesis/x530/Kconfig"
endif
diff --git a/board/alliedtelesis/x530/Kconfig b/board/alliedtelesis/x530/Kconfig
new file mode 100644
index ..9e676f17f39c
--- /dev/null
+++ b/board/alliedtelesis/x530/Kconfig
@@ -0,0 +1,25 @@
+menu "x530 configuration"
+ depends on TARGET_X530
+
+config X530_ECC
+ bool "Enable DDR3 ECC"
+ help
+ Some of the older x530 board have layout issues which cause problems
+ for the DDR which usually exhibit as DDR training failures or
+ problems accessing DDR after training.
+
+ The known affected boards are:
+
+ * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm)
+ * 844-001948-00 (GS980MX/28)
+ * 844-002008-00 (x530L-52GTX, x530L-52GPX)
+ * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm)
+
+ If you have a newer board you can set Y here, otherwise say N.
+
+config SPL_X530_ECC
+ bool
+ depends on X530_ECC
+ default X530_ECC
+
+endmenu
diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c
index 866b6e68cc16..de20684f4353 100644
--- a/board/alliedtelesis/x530/x530.c
+++ b/board/alliedtelesis/x530/x530.c
@@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map
**serdes_map_array, u8 *count)
return 0;
}
+#if CONFIG_IS_ENABLED(X530_ECC)
+ #define BUS_MASK BUS_MASK_32BIT_ECC
+#else
+ #define BUS_MASK BUS_MASK_32BIT
+#endif
+
/*
* Define the DDR layout / topology here in the board file. This will
* be used by the DDR3 init code in the SPL U-Boot version to configure
@@ -66,7 +72,7 @@ static struct mv_ddr_topology_map board_topology_map = {
0, 0, /* cas_l cas_wl */
MV_DDR_TEMP_LOW,/* temperature */
MV_DDR_TIM_2T} }, /* timing */
- BUS_MASK_32BIT_ECC, /* subphys mask */
+ BUS_MASK, /* subphys mask */
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
NOT_COMBINED, /* ddr twin-die combined */
{ {0} },/* raw spd data */
--
2.34.1
[PATCH 0/2] fw_env: two minor code cleanups
From: Rafał Miłecki Hi, I'm a long time OpenWrt developer and just recently I started working with some devices using U-Boot. I was trying to understand how environment variables are read in user space and I had some problems understanding fw_env_open() logic. I eventually got it but I thought I may help further developers by simpliifying its code a bit. I hope you may find those patches useful and review / apply them. Rafał Miłecki (2): fw_env: make flash_io() take buffer as an argument fw_env: simplify logic & code paths in the fw_env_open() tools/env/fw_env.c | 104 +++-- 1 file changed, 44 insertions(+), 60 deletions(-) -- 2.31.1
[PATCH 1/2] fw_env: make flash_io() take buffer as an argument
From: Rafał Miłecki
It's usually easier to understand code & follow it if all arguments are
passed explicitly. Many coding styles also discourage using global
variables.
Behaviour of flash_io() was a bit unintuitive as it was writing to a
buffer referenced in a global struct. That required developers to
remember how it works and sometimes required hacking "environment"
global struct variable to read data into a proper buffer.
Signed-off-by: Rafał Miłecki
---
tools/env/fw_env.c | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index 3da75be783..f90293d7ce 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -346,7 +346,7 @@ static int ubi_write(int fd, const void *buf, size_t count)
return 0;
}
-static int flash_io(int mode);
+static int flash_io(int mode, void *buf, size_t count);
static int parse_config(struct env_opts *opts);
#if defined(CONFIG_FILE)
@@ -516,7 +516,7 @@ int fw_env_flush(struct env_opts *opts)
*environment.crc = crc32(0, (uint8_t *) environment.data, ENV_SIZE);
/* write environment back to flash */
- if (flash_io(O_RDWR)) {
+ if (flash_io(O_RDWR, environment.data, ENV_SIZE)) {
fprintf(stderr, "Error: can't write fw_env to flash\n");
return -1;
}
@@ -1185,7 +1185,8 @@ static int flash_flag_obsolete(int dev, int fd, off_t
offset)
return rc;
}
-static int flash_write(int fd_current, int fd_target, int dev_target)
+static int flash_write(int fd_current, int fd_target, int dev_target, void
*buf,
+ size_t count)
{
int rc;
@@ -1212,11 +1213,10 @@ static int flash_write(int fd_current, int fd_target,
int dev_target)
if (IS_UBI(dev_target)) {
if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0)
return -1;
- return ubi_write(fd_target, environment.image, CUR_ENVSIZE);
+ return ubi_write(fd_target, buf, count);
}
- rc = flash_write_buf(dev_target, fd_target, environment.image,
-CUR_ENVSIZE);
+ rc = flash_write_buf(dev_target, fd_target, buf, count);
if (rc < 0)
return rc;
@@ -1235,17 +1235,17 @@ static int flash_write(int fd_current, int fd_target,
int dev_target)
return 0;
}
-static int flash_read(int fd)
+static int flash_read(int fd, void *buf, size_t count)
{
int rc;
if (IS_UBI(dev_current)) {
DEVTYPE(dev_current) = MTD_ABSENT;
- return ubi_read(fd, environment.image, CUR_ENVSIZE);
+ return ubi_read(fd, buf, count);
}
- rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
+ rc = flash_read_buf(dev_current, fd, buf, count,
DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
return -1;
@@ -1291,7 +1291,7 @@ err:
return rc;
}
-static int flash_io_write(int fd_current)
+static int flash_io_write(int fd_current, void *buf, size_t count)
{
int fd_target = -1, rc, dev_target;
const char *dname, *target_temp = NULL;
@@ -1322,7 +1322,7 @@ static int flash_io_write(int fd_current)
fd_target = fd_current;
}
- rc = flash_write(fd_current, fd_target, dev_target);
+ rc = flash_write(fd_current, fd_target, dev_target, buf, count);
if (fsync(fd_current) && !(errno == EINVAL || errno == EROFS)) {
fprintf(stderr,
@@ -1377,7 +1377,7 @@ static int flash_io_write(int fd_current)
return rc;
}
-static int flash_io(int mode)
+static int flash_io(int mode, void *buf, size_t count)
{
int fd_current, rc;
@@ -1391,9 +1391,9 @@ static int flash_io(int mode)
}
if (mode == O_RDWR) {
- rc = flash_io_write(fd_current);
+ rc = flash_io_write(fd_current, buf, count);
} else {
- rc = flash_read(fd_current);
+ rc = flash_read(fd_current, buf, count);
}
if (close(fd_current)) {
@@ -1455,7 +1455,7 @@ int fw_env_open(struct env_opts *opts)
}
dev_current = 0;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, environment.data, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
@@ -1490,7 +1490,7 @@ int fw_env_open(struct env_opts *opts)
* other pointers in environment still point inside addr0
*/
environment.image = addr1;
- if (flash_io(O_RDONLY)) {
+ if (flash_io(O_RDONLY, environment.data, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
--
2.31.1
[PATCH 2/2] fw_env: simplify logic & code paths in the fw_env_open()
From: Rafał Miłecki
Environment variables can be stored in two formats:
1. Single entry with header containing CRC32
2. Two entries with extra flags field in each entry header
For that reason fw_env_open() has two main code paths and there are
pointers for CRC32/flags/data.
Previous implementation was a bit hard to follow:
1. It was checking for used format twice (in reversed order each time)
2. It was setting "environment" global struct fields to some temporary
values that required extra comments explaining it
This change simplifies that code:
1. It introduces two clear code paths
2. It sets "environment" global struct fields values only once it really
knows them
To be fair there are *two* crc32() calls now and an extra pointer
variable but that should be cheap enough and worth it.
Signed-off-by: Rafał Miłecki
---
tools/env/fw_env.c | 76 ++
1 file changed, 30 insertions(+), 46 deletions(-)
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index f90293d7ce..05f292dd28 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1421,9 +1421,6 @@ int fw_env_open(struct env_opts *opts)
int ret;
- struct env_image_single *single;
- struct env_image_redundant *redundant;
-
if (!opts)
opts = &default_opts;
@@ -1439,40 +1436,36 @@ int fw_env_open(struct env_opts *opts)
goto open_cleanup;
}
- /* read environment from FLASH to local buffer */
- environment.image = addr0;
-
- if (have_redund_env) {
- redundant = addr0;
- environment.crc = &redundant->crc;
- environment.flags = &redundant->flags;
- environment.data = redundant->data;
- } else {
- single = addr0;
- environment.crc = &single->crc;
- environment.flags = NULL;
- environment.data = single->data;
- }
-
dev_current = 0;
- if (flash_io(O_RDONLY, environment.data, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, addr0, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
- crc0 = crc32(0, (uint8_t *)environment.data, ENV_SIZE);
-
- crc0_ok = (crc0 == *environment.crc);
if (!have_redund_env) {
+ struct env_image_single *single = addr0;
+
+ crc0 = crc32(0, (uint8_t *)single->data, ENV_SIZE);
+ crc0_ok = (crc0 == single->crc);
if (!crc0_ok) {
fprintf(stderr,
"Warning: Bad CRC, using default
environment\n");
- memcpy(environment.data, default_environment,
+ memcpy(single->data, default_environment,
sizeof(default_environment));
environment.dirty = 1;
}
+
+ environment.crc = &single->crc;
+ environment.flags = NULL;
+ environment.data = single->data;
} else {
- flag0 = *environment.flags;
+ struct env_image_redundant *redundant0 = addr0;
+ struct env_image_redundant *redundant1;
+
+ crc0 = crc32(0, (uint8_t *)redundant0->data, ENV_SIZE);
+ crc0_ok = (crc0 == redundant0->crc);
+
+ flag0 = redundant0->flags;
dev_current = 1;
addr1 = calloc(1, CUR_ENVSIZE);
@@ -1483,14 +1476,9 @@ int fw_env_open(struct env_opts *opts)
ret = -ENOMEM;
goto open_cleanup;
}
- redundant = addr1;
+ redundant1 = addr1;
- /*
-* have to set environment.image for flash_read(), careful -
-* other pointers in environment still point inside addr0
-*/
- environment.image = addr1;
- if (flash_io(O_RDONLY, environment.data, CUR_ENVSIZE)) {
+ if (flash_io(O_RDONLY, addr1, CUR_ENVSIZE)) {
ret = -EIO;
goto open_cleanup;
}
@@ -1518,18 +1506,12 @@ int fw_env_open(struct env_opts *opts)
goto open_cleanup;
}
- crc1 = crc32(0, (uint8_t *)redundant->data, ENV_SIZE);
+ crc1 = crc32(0, (uint8_t *)redundant1->data, ENV_SIZE);
- crc1_ok = (crc1 == redundant->crc);
- flag1 = redundant->flags;
+ crc1_ok = (crc1 == redundant1->crc);
+ flag1 = redundant1->flags;
- /*
-* environment.data still points to ((struct
-* env_image_redundant *)addr0)->data. If the two
-* environments differ, or one has bad crc, force a
-* write-out by marking the environment dirty.
-*/
- if (memcmp(environment.dat
[RESEND PATCH v2] board: gateworks: venice: add imx8mn-gw7902 support
The GW7902 is based on the i.MX 8M Mini / Nano SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller
- LTE CAT M1 modem
- USB 2.0 HUB
- M.2 Socket with USB2.0, PCIe, and dual-SIM
- IMX8M FEC
- PCIe based GbE
- RS232/RS485/RS422 serial transceiver
- GPS
- CAN bus
- WiFi / Bluetooth
- MIPI header (DSI/CSI/GPIO/PWM/I2S)
- PMIC
To add support for the i.MX8M Nano GW7902:
- Add imx8mn-venice dts/defconfig/include
- Add imx8mn-gw7902 dts
- Add imx8mn-2gb lpddr4 dram configs
- Add misc support for IMX8M Nano SoC
- rename imx8mm-venice.c to venice.c as it is no longer imx8mm specific
- update README with differences for IMX8MN vs IMX8MM
Signed-off-by: Tim Harvey
---
v2:
- resend due to patch missing from patchwork
- rebase on origin/master
- remove unused fdt_pack_reg function
---
arch/arm/dts/Makefile |2 +
arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi | 29 +
arch/arm/dts/imx8mn-venice-gw7902.dts | 888 ++
arch/arm/dts/imx8mn-venice-u-boot.dtsi| 222 +++
arch/arm/dts/imx8mn-venice.dts| 152 ++
arch/arm/mach-imx/imx8m/Kconfig |7 +
board/gateworks/venice/Kconfig| 15 +
board/gateworks/venice/MAINTAINERS|6 +-
board/gateworks/venice/Makefile | 10 +-
board/gateworks/venice/README |3 +-
board/gateworks/venice/gsc.c | 13 +
.../gateworks/venice/imximage-8mn-lpddr4.cfg | 10 +
board/gateworks/venice/lpddr4_timing.h|5 +
...lpddr4_timing.c => lpddr4_timing_imx8mm.c} |0
.../lpddr4_timing_imx8mn_2gb_dual_die.c | 1444
.../lpddr4_timing_imx8mn_2gb_single_die.c | 1445 +
board/gateworks/venice/spl.c | 31 +-
.../venice/{imx8mm_venice.c => venice.c} |0
configs/imx8mn_venice_defconfig | 114 ++
include/configs/imx8mn_venice.h | 114 ++
20 files changed, 4503 insertions(+), 7 deletions(-)
create mode 100644 arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-venice-gw7902.dts
create mode 100644 arch/arm/dts/imx8mn-venice-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mn-venice.dts
create mode 100644 board/gateworks/venice/imximage-8mn-lpddr4.cfg
rename board/gateworks/venice/{lpddr4_timing.c => lpddr4_timing_imx8mm.c}
(100%)
create mode 100644 board/gateworks/venice/lpddr4_timing_imx8mn_2gb_dual_die.c
create mode 100644 board/gateworks/venice/lpddr4_timing_imx8mn_2gb_single_die.c
rename board/gateworks/venice/{imx8mm_venice.c => venice.c} (100%)
create mode 100644 configs/imx8mn_venice_defconfig
create mode 100644 include/configs/imx8mn_venice.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b3e2a9c9d77b..d1a6667953f1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -903,6 +903,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \
+ imx8mn-venice.dtb \
+ imx8mn-venice-gw7902.dtb \
imx8mq-evk.dtb \
imx8mm-beacon-kit.dtb \
imx8mn-beacon-kit.dtb \
diff --git a/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
new file mode 100644
index ..f6f0aa7cb5c0
--- /dev/null
+++ b/arch/arm/dts/imx8mn-venice-gw7902-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+#include "imx8mn-venice-u-boot.dtsi"
+
+&fec1 {
+ phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <1>;
+ phy-reset-post-delay = <1>;
+};
+
+&pinctrl_fec1 {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b} {
+ u-boot,dm-spl;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@4b/regulators} {
+ u-boot,dm-spl;
+};
+
+&pinctrl_pmic {
+ u-boot,dm-spl;
+};
+
diff --git a/arch/arm/dts/imx8mn-venice-gw7902.dts
b/arch/arm/dts/imx8mn-venice-gw7902.dts
new file mode 100644
index ..06ee4cf79480
--- /dev/null
+++ b/arch/arm/dts/imx8mn-venice-gw7902.dts
@@ -0,0 +1,888 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2021 Gateworks Corporation
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+#include
+
+#include "imx8mn.dtsi"
+
+/ {
+ model = "Gateworks Venice GW7902 i.MX8MN board";
+ compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
+
+ aliases {
+ usb0 = &usbotg1;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x0 0x4000 0 0x8000>;
+ };
+
+ can20m: can20m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2000>;
+ clock-output-names = "can20m";
+ };
+
+ gpio-keys {
+
RE: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
Hi Michael > -Original Message- > From: Michael Walle > Sent: Monday, January 10, 2022 6:13 PM > To: Gaurav Jain > Cc: Shengzhou Liu ; Varun Sethi ; > Adrian Alonso ; Alison Wang > ; Andy Tang ; > feste...@gmail.com; Franck Lenormand ; Horia > Geanta ; Ji Luo ; Meenakshi > Aggarwal ; Mingkai Hu > ; olte...@gmail.com; Pankaj Gupta > ; Peng Fan ; Pramod Kumar > ; Priyanka Jain ; Rajesh > Bhagat ; Sahil Malhotra ; > sba...@denx.de; Silvano Di Ninno ; > s...@chromium.org; u-boot@lists.denx.de; dl-uboot-imx ; > Wasim Khan ; Ye Li ; Michael Walle > > Subject: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model. > > Caution: EXT Email > > Hi, > > please keep me on CC for these series, as there were comments from me on > previous versions. Thanks. > > .. > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > > 7ce2bbc954..30a34bdd08 100644 > > --- a/arch/arm/Kconfig > > +++ b/arch/arm/Kconfig > > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS > > select ARCH_SUPPORT_TFABOOT > > select BOARD_LATE_INIT > > select GPIO_EXTRA_HEADER > > + select FSL_CAAM > > + select MISC > > This looks wrong. FSL_CAAM should depend on MISC, no? FSL_CAAM is to enable the CAAM driver. Caam driver is developed using misc uclass and MISC config is required to enable DM for misc uclass. Some platforms do not have driver model support so in that case CAAM can function without misc. > > > help > > Support for Freescale LS1028AQDS platform > > The LS1028A Development System (QDS) is a high-performance @@ > > -1518,6 +1520,8 @@ config TARGET_LS1028ARDB > > select ARCH_SUPPORT_TFABOOT > > select BOARD_LATE_INIT > > select GPIO_EXTRA_HEADER > > + select FSL_CAAM > > + select MISC > > help > > Support for Freescale LS1028ARDB platform > > The LS1028A Development System (RDB) is a high-performance > > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig > > b/arch/arm/cpu/armv7/ls102xa/Kconfig > > index f919d02db4..ca006e069f 100644 > > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig > > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig > > @@ -21,6 +21,9 @@ config ARCH_LS1021A > > select SYS_FSL_SRDS_1 > > select SYS_HAS_SERDES > > select SYS_I2C_MXC > > + select FSL_CAAM > > While above you added that dependency to an indivdual board, here you are > adding that dependency to all boards using this architecture. The same is true > for all the other "config ARCH_*" symbols. What if someone wants to build a > bootloader without CAAM support? This should really go into the defconfigs for > these boards. CAAM is only initialized at boot which does not imply to use caam in every operation. Regards Gaurav Jain > > -michael
RE: [EXT] RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in kernel
Hi Andrey
For now I will remove this particular patch from my series and will send a
separate patch addressing your comments.
Regards
Gaurav Jain
> -Original Message-
> From: ZHIZHIKIN Andrey
> Sent: Monday, January 10, 2022 7:31 PM
> To: Gaurav Jain ; u-boot@lists.denx.de
> Cc: Stefano Babic ; Fabio Estevam ;
> Peng Fan ; Simon Glass ; Priyanka
> Jain ; Ye Li ; Horia Geanta
> ; Ji Luo ; Franck Lenormand
> ; Silvano Di Ninno ;
> Sahil Malhotra ; Pankaj Gupta
> ; Varun Sethi ; dl-uboot-imx
> ; Shengzhou Liu ; Mingkai Hu
> ; Rajesh Bhagat ; Meenakshi
> Aggarwal ; Wasim Khan
> ; Alison Wang ; Pramod
> Kumar ; Andy Tang ;
> Adrian Alonso ; Vladimir Oltean
> ; mich...@walle.cc
> Subject: [EXT] RE: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in
> kernel
>
> Caution: EXT Email
>
> Hello Gaurav,
>
> Cc: Michael Walle
>
> > -Original Message-
> > From: U-Boot On Behalf Of Gaurav Jain
> > Sent: Monday, January 10, 2022 1:27 PM
> > To: u-boot@lists.denx.de
> > Cc: Stefano Babic ; Fabio Estevam
> > ; Peng Fan ; Simon Glass
> > ; Priyanka Jain ; Ye Li
> > ; Horia Geanta ; Ji Luo
> > ; Franck Lenormand ; Silvano
> > Di Ninno ; Sahil malhotra
> > ; Pankaj Gupta ; Varun
> > Sethi ; NXP i . MX U-Boot Team ;
> > Shengzhou Liu ; Mingkai Hu
> > ; Rajesh Bhagat ;
> Meenakshi
> > Aggarwal ; Wasim Khan
> > ; Alison Wang ; Pramod
> Kumar
> > ; Tang Yuantian ; Adrian
> > Alonso ; Vladimir Oltean
> > Subject: [PATCH v8 10/15] crypto/fsl: Improve hwrng performance in
> > kernel
> >
> > From: Ye Li
> >
> > RNG parameters are reconfigured.
> > - For TRNG to generate 256 bits of entropy, RNG TRNG Seed Control register
> > is configured to have reduced SAMP_SIZE from default 2500 to 512. it is
> > number of entropy samples that will be taken during Entropy generation.
> > - self-test registers(Monobit Limit, Poker Range, Run Length Limit)
> > are synchronized with new RTSDCTL[SAMP_SIZE] of 512.
> >
> > TRNG time is caluculated based on sample size.
>
> Typo: caluculated -> calculated
>
> > time required to generate entropy is reduced and hwrng performance
> > improved from 0.3 kB/s to 1.3 kB/s.
>
> Is there any degradation in passed/failed FIPS 140-2 test count? Can you
> provide
> some results from at least rngtest run?
>
> >
> > Signed-off-by: Ye Li
> > Acked-by: Gaurav Jain >
> > ---
> > drivers/crypto/fsl/jr.c | 102 +---
> > include/fsl_sec.h | 1 +
> > 2 files changed, 87 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index
> > a84440ab10..e5346a84a4 100644
> > --- a/drivers/crypto/fsl/jr.c
> > +++ b/drivers/crypto/fsl/jr.c
> > @@ -603,30 +603,100 @@ static u8 get_rng_vid(ccsr_sec_t *sec)
> > */
> > static void kick_trng(int ent_delay, ccsr_sec_t *sec) {
> > + u32 samples = 512; /* number of bits to generate and test */
> > + u32 mono_min = 195;
> > + u32 mono_max = 317;
> > + u32 mono_range = mono_max - mono_min;
> > + u32 poker_min = 1031;
> > + u32 poker_max = 1600;
> > + u32 poker_range = poker_max - poker_min + 1;
> > + u32 retries= 2;
> > + u32 lrun_max = 32;
> > + s32 run_1_min = 27;
> > + s32 run_1_max = 107;
> > + s32 run_1_range = run_1_max - run_1_min;
> > + s32 run_2_min = 7;
> > + s32 run_2_max = 62;
> > + s32 run_2_range = run_2_max - run_2_min;
> > + s32 run_3_min = 0;
> > + s32 run_3_max = 39;
> > + s32 run_3_range = run_3_max - run_3_min;
> > + s32 run_4_min = -1;
> > + s32 run_4_max = 26;
> > + s32 run_4_range = run_4_max - run_4_min;
> > + s32 run_5_min = -1;
> > + s32 run_5_max = 18;
> > + s32 run_5_range = run_5_max - run_5_min;
> > + s32 run_6_min = -1;
> > + s32 run_6_max = 17;
> > + s32 run_6_range = run_6_max - run_6_min;
>
> I have a feeling that this whole block of local variables can be simplified.
> I'm not
> sure it is required to list this so detailed.
>
> You can attempt to define those values in header file and use macros to
> compute bound conditions, rather than allocating this on the stack here.
>
> > + u32 val;
> > +
> > struct rng4tst __iomem *rng =
> > (struct rng4tst __iomem *)&sec->rng;
> > - u32 val;
> >
> > - /* put RNG4 into program mode */
> > - sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
> > - /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
> > - * length (in system clocks) of each Entropy sample taken
> > - * */
> > + /* Put RNG in program mode */
> > + /* Setting both RTMCTL:PRGM and RTMCTL:TRNG_ACC causes TRNG to
> > + * properly invalidate the entropy in the entropy register and
> > + * force re-generation.
> > + */
> > + sec_setbits32(&rng->rtmctl, RTMCTL_PRGM | RTMCTL_ACC);
> > +
> > + /* Configure the RNG Entropy Delay
> > + * Performance-wise, it does not make sense to
> > +
Re: [PATCH 2/2] ARM: mvebu: x530: Add option for ECC
On 1/11/22 02:37, Chris Packham wrote: On Mon, Jan 10, 2022 at 9:10 PM Chris Packham wrote: On Mon, 10 Jan 2022, 8:37 PM Stefan Roese, wrote: On 1/6/22 04:08, Chris Packham wrote: Some older x530 boards have layout issues that cause problems for DDR. These are usually seen as training failures but can also cause problems after training has completed. Add an option to enable ECC leaving the default as N which will work with both old and new boards. Signed-off-by: Chris Packham Just checking: Most likely you don't have the possibility to detect the board version at runtime? Not in a way that can be done without working RAM. For our internal fork we maintain 2 defconfigs one with ECC one without. We can manage via the BOM which boards get which bootloader. If this is not possible: Reviewed-by: Stefan Roese Thanks, Stefan --- arch/arm/mach-mvebu/Kconfig | 1 + board/alliedtelesis/x530/Kconfig | 20 board/alliedtelesis/x530/x530.c | 8 +++- 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 board/alliedtelesis/x530/Kconfig diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig index d23cc0c760f1..7388ade98d52 100644 --- a/arch/arm/mach-mvebu/Kconfig +++ b/arch/arm/mach-mvebu/Kconfig @@ -341,5 +341,6 @@ config SECURED_MODE_CSK_INDEX source "board/solidrun/clearfog/Kconfig" source "board/kobol/helios4/Kconfig" +source "board/alliedtelesis/x530/Kconfig" endif diff --git a/board/alliedtelesis/x530/Kconfig b/board/alliedtelesis/x530/Kconfig new file mode 100644 index ..5c1ae36aebaa --- /dev/null +++ b/board/alliedtelesis/x530/Kconfig @@ -0,0 +1,20 @@ +menu "x530 configuration" + depends on TARGET_X530 + +config X530_ECC + bool "Enable DDR3 ECC" + help + Some of the older x530 board have layout issues which cause problems + for the DDR which usually exhibit as DDR training failures or + problems accessing DDR after training. + + The known affected boards are: + + * 844-001897-00 (x530-28GTXm, x530-28GPXm, GS980MX/28PSm) + * 844-001948-00 (GS980MX/28) + * 844-002008-00 (x530L-52GTX, x530L-52GPX) + * 844-001974-00 (x530-52GTXm, x530-52GPXm, GS980MX/52PSm) + + If you have a newer board you can set Y here, otherwise say N. + +endmenu diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index 866b6e68cc16..de20684f4353 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -45,6 +45,12 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) return 0; } +#if CONFIG_IS_ENABLED(X530_ECC) + #define BUS_MASK BUS_MASK_32BIT_ECC +#else + #define BUS_MASK BUS_MASK_32BIT +#endif + Hmm this doesn't actually appear to be working as intended. When the SPL is built I end up with CONFIG_IS_ENABLED(X530_ECC) == 0 even when I set it to y. Do I need to define a SPL version of this Kconfig symbol? AFAIK, IS_ENABLED(CONFIG_X530_ECC) would be a solution here. There is no need for a new SPL Kconfig option this way. Please give it a try. Thanks, Stefan
Re: [PATCH 0/4] Apple M1 watchdog timer
Hi Marc, On 1/10/22 21:25, Mark Kettenis wrote: From: Mark Kettenis Date: Sun, 14 Nov 2021 12:19:39 +0100 This series adds a driver for the watchdog timer found on Apple's M1 SoC and replaces the reset_cpu() function in the board file with sysreset. The driver is based on the Linux binding proposed in [1]. [1] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/2023094732.73889-1-s...@svenpeter.dev/ Mark Kettenis (3): watchdog: Add a driver for the Apple watchdog arm: dts: apple: Add watchdog timer node arm: apple: Use watchdog timer for system reset Hi Stefan, This series is delegated to you in patchwork[1]. Not sure why though. I'm the "unofficial" watchdog custodian since a few years. Perhaps its time to make this a bit more "official". But if watchdogs are indeed your thing, can you have a look now that 2022.01 is out of the door? Yes, its on my list - will get to it shortly. Sorry for the delay. Thanks, Stefan
Re: [PATCH] omap: timer: implement timer_get_boot_us
Hi
Gentle ping.
>
> To make the OMAP DM timer driver useful for the timing of
> bootstages, we need to implement timer_get_boot_us(..).
>
> Signed-off-by: Christian Gmeiner
> ---
> drivers/timer/omap-timer.c | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/timer/omap-timer.c b/drivers/timer/omap-timer.c
> index 721e385fd1..25a6108fef 100644
> --- a/drivers/timer/omap-timer.c
> +++ b/drivers/timer/omap-timer.c
> @@ -83,6 +83,27 @@ static int omap_timer_of_to_plat(struct udevice *dev)
> return 0;
> }
>
> +#if CONFIG_IS_ENABLED(BOOTSTAGE)
> +ulong timer_get_boot_us(void)
> +{
> + u64 ticks = 0;
> + u32 rate = 1;
> + u64 us;
> + int ret;
> +
> + ret = dm_timer_init();
> + if (!ret) {
> + /* The timer is available */
> + rate = timer_get_rate(gd->timer);
> + timer_get_count(gd->timer, &ticks);
> + } else {
> + return 0;
> + }
> +
> + us = (ticks * 1000) / rate;
> + return us;
> +}
> +#endif
>
> static const struct timer_ops omap_timer_ops = {
> .get_count = omap_timer_get_count,
> --
> 2.33.1
>
--
greets
--
Christian Gmeiner, MSc
https://christian-gmeiner.info/privacypolicy
imx: imx8mm: imx8mm-kontron-n801x-s: does not start work
Hi all,
I wanted to test the newly introduced kontron-sl-mx8mm_defconfig but
it does not work.
I already found two converted config options that are missing in that defconfig:
+CONFIG_SPL_MMC=y
+CONFIG_SPL_SERIAL=y
With that the output appears but the u-boot hangs when trying to find
the binman node in the dtb.
--- >8
U-Boot SPL 2022.01-00323-g56915a34d1 (Jan 11 2022 - 08:11:03 +0100)
Kontron SL i.MX8MM (N801X) module, 1 GB RAM detected
Touch controller detected, assuming LVDS panel...
Normal Boot
WDT: Not starting watchdog@3028
Trying to boot from MMC2
NOTICE: BL31: v2.4(release):v2.4
NOTICE: BL31: Built : 09:46:16, Jan 10 2022
U-Boot 2022.01-00323-g56915a34d1 (Jan 11 2022 - 08:11:03 +0100)
CPU: Freescale i.MX8MMQ rev1.0 1600 MHz (running at 1200 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 47C
Reset cause: POR
Model: Kontron i.MX8MM N801X S LVDS
DRAM: 1 GiB
binman_init failed:-2
initcall sequence 7ffcef80 failed at call 4021f200 (err=-2)
### ERROR ### Please RESET the board ###
--- >8
Does anyone have an idea what goes wrong?
I already disabled BINMAN_FDT an the u-boot start but when printing
the fdt node I do not see the binman node:
>8
=> fdt addr $fdtcontroladdr
=> fdt list
/ {
interrupt-parent = <0x0001>;
#address-cells = <0x0002>;
#size-cells = <0x0002>;
model = "Kontron i.MX8MM N801X S LVDS";
compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
fit-images {
};
aliases {
};
cpus {
};
opp-table {
};
clock-osc-32k {
};
clock-osc-24m {
};
clock-ext1 {
};
clock-ext2 {
};
clock-ext3 {
};
clock-ext4 {
};
psci {
};
pmu {
};
timer {
};
thermal-zones {
};
usbphynop1 {
};
usbphynop2 {
};
soc@0 {
};
memory@4000 {
};
chosen {
};
clock-osc-can {
};
leds {
};
pwm-beeper {
};
regulator-rst-eth2 {
};
regulator-5v {
};
backlight {
};
regpanel-pwr {
};
regpanel-rst {
};
regpanel-stby {
};
regpanel-hinv {
};
regpanel-vinv {
};
regulator-24v {
};
};
=>
>8
Thanks
--
Heiko
Re: [EXT] Re: [PATCH v8 12/15] Layerscape: Enable Job ring driver model.
Hi Guarav, Am 2022-01-11 06:41, schrieb Gaurav Jain: > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index > 7ce2bbc954..30a34bdd08 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -1504,6 +1504,8 @@ config TARGET_LS1028AQDS > select ARCH_SUPPORT_TFABOOT > select BOARD_LATE_INIT > select GPIO_EXTRA_HEADER > + select FSL_CAAM > + select MISC This looks wrong. FSL_CAAM should depend on MISC, no? FSL_CAAM is to enable the CAAM driver. Caam driver is developed using misc uclass and MISC config is required to enable DM for misc uclass. Some platforms do not have driver model support so in that case CAAM can function without misc. then it's "select MISC if DM" in "config FSL_CAAM". > help > Support for Freescale LS1028AQDS platform > The LS1028A Development System (QDS) is a high-performance @@ > -1518,6 +1520,8 @@ config TARGET_LS1028ARDB > select ARCH_SUPPORT_TFABOOT > select BOARD_LATE_INIT > select GPIO_EXTRA_HEADER > + select FSL_CAAM > + select MISC > help > Support for Freescale LS1028ARDB platform > The LS1028A Development System (RDB) is a high-performance > diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig > b/arch/arm/cpu/armv7/ls102xa/Kconfig > index f919d02db4..ca006e069f 100644 > --- a/arch/arm/cpu/armv7/ls102xa/Kconfig > +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig > @@ -21,6 +21,9 @@ config ARCH_LS1021A > select SYS_FSL_SRDS_1 > select SYS_HAS_SERDES > select SYS_I2C_MXC > + select FSL_CAAM While above you added that dependency to an indivdual board, here you are adding that dependency to all boards using this architecture. The same is true for all the other "config ARCH_*" symbols. What if someone wants to build a bootloader without CAAM support? This should really go into the defconfigs for these boards. CAAM is only initialized at boot which does not imply to use caam in every operation. I don't understand. You're including the CAAM driver here unconditionally, even if it's not needed. That is, it is increasing the binary size for every board which is using one of these SoCs. Please move it to the defconfigs. -michael
[PATCH v2 00/20] J721S2: Add initial support
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform, providing advanced system integration in automotive ADAS applications and industrial applications requiring AI at the network edge. This SoC extends the Jacinto 7 family of SoCs with focus on lowering system costs and power while providing interfaces, memory architecture and compute performance for single and multi-sensor applications. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, three clusters of lockstep capable dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x floating point Vector DSP. * 3D GPU: Automotive grade IMG BXS-4-64 * Vision Processing Accelerator (VPAC) with image signal processor and Depth and Motion Processing Accelerator (DMPAC) * Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface. * Two Ethernet ports with RGMII support. * Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems, * Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller, QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals. * Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL management. * Chips and Media Wave521CL H.264/H.265 encode/decode engine See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021) for further details: http://www.ti.com/lit/pdf/spruj28 bootlog: - https://pastebin.ubuntu.com/p/WDpTxGHcGD/ Changes since v1: - Removed unused serial aliases - Assigned serial2 alias for main uart8 instance - Moved aliases to respective board files Aswath Govindraju (10): ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance ram: k3-ddrss: Add support for multiple instances of DDR subsystems ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems dt-bindings: ti-serdes-mux: Add defines for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 arm: dts: Add initial support for J721S2 SoC arm: dts: Add initial support for J721S2 System on Module arm: dts: Add support for A72 specific J721S2 Common Processor Board arm: dts: k3-j721s2: Add r5 specific dt support arm: dts: k3-j721s2-ddr: Add DDR support David Huang (9): arm: K3: Add basic support for J721S2 SoC definition drivers: dma: Add support for J721S2 clk: clk-k3: Add support for J721S2 SoC power: domain: ti: Add support for J721S2 SoC ram: k3-ddrss: Add support for J721S2 SoC soc: ti: k3-socinfo: Add entry for J721S2 SoC board: ti: j721s2: Add board support for J721S2 configs: j721s2_evm_r5_defconfig: Add R5 SPL specific defconfig configs: j721s2_evm_a72_defconfig: Add A72 specific defconfig Nishanth Menon (1): remoteproc: k3_system_controller: Support optional boot_notification channel arch/arm/dts/Makefile |2 + .../k3-j721s2-common-proc-board-u-boot.dtsi | 149 + arch/arm/dts/k3-j721s2-common-proc-board.dts | 430 ++ arch/arm/dts/k3-j721s2-ddr-evm-lp4-4266.dtsi | 4387 arch/arm/dts/k3-j721s2-ddr.dtsi | 4440 + arch/arm/dts/k3-j721s2-main.dtsi | 937 arch/arm/dts/k3-j721s2-mcu-wakeup.dtsi| 302 ++ .../dts/k3-j721s2-r5-common-proc-board.dts| 198 + arch/arm/dts/k3-j721s2-som-p0.dtsi| 173 + arch/arm/dts/k3-j721s2.dtsi | 167 + arch/arm/mach-k3/Kconfig | 11 +- arch/arm/mach-k3/Makefile |1 + arch/arm/mach-k3/arm64-mmu.c | 53 + arch/arm/mach-k3/include/mach/hardware.h |4 + .../mach-k3/include/mach/j721s2_hardware.h| 60 + arch/arm/mach-k3/include/mach/j721s2_spl.h| 46 + arch/arm/mach-k3/include/mach/spl.h |4 + arch/arm/mach-k3/j721s2/Makefile |5 + arch/arm/mach-k3/j721s2/clk-data.c| 403 ++ arch/arm/mach-k3/j721s2/dev-data.c| 85 + arch/arm/mach-k3/j721s2_init.c| 312 ++ board/ti/j721s2/Kconfig | 63 + board/ti/j721s2/MAINTAINERS |7 + board/ti/j721s2/Makefile |8 + board/ti/j721s2/evm.c | 180 + configs/j721s2_evm_a72_defconfig | 207 + configs/j721s2_evm_r5_defconfig | 171 + .../remoteproc/k3-system-controller.txt |3 + drivers/clk/ti/clk-k3.c |5 + drivers/dma/ti/Makefile |1 + drivers/dma/ti/k3-psil-j721s2.c | 167 + drivers/dma/ti/k3-psil-priv.h |1 + drivers/dma/ti/k3-psil.c |2 + drivers/firmware/ti_sci_static_data.h | 40 +- drivers/power/domain/ti-power-domain.c|5 + drivers/ram/Kconfig | 12 + drivers/ram/k3-ddrss/Makefile |4 + drivers/ram/k3-ddrss/k3-ddrss.c | 296 +- drivers/ram/k3-ddrss/lpddr4
[PATCH v2 01/20] remoteproc: k3_system_controller: Support optional boot_notification channel
From: Nishanth Menon
If there is an optional boot notification channel that an SoC uses
separate from the rx path, use the same.
Signed-off-by: Nishanth Menon
---
.../remoteproc/k3-system-controller.txt | 3 +++
drivers/remoteproc/k3_system_controller.c | 20 ++-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
index 32f4720b0d17..33dc46812ed4 100644
--- a/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
+++ b/doc/device-tree-bindings/remoteproc/k3-system-controller.txt
@@ -13,6 +13,9 @@ Required properties:
"rx" for Receive channel
- mboxes: Corresponding phandles to mailbox channels.
+Optional properties:
+
+- mbox-names: "boot_notify" for Optional alternate boot notification
channel.
Example:
diff --git a/drivers/remoteproc/k3_system_controller.c
b/drivers/remoteproc/k3_system_controller.c
index 89cb90207dcb..e2affe69c678 100644
--- a/drivers/remoteproc/k3_system_controller.c
+++ b/drivers/remoteproc/k3_system_controller.c
@@ -77,14 +77,18 @@ struct k3_sysctrler_desc {
* struct k3_sysctrler_privdata - Structure representing System Controller
data.
* @chan_tx: Transmit mailbox channel
* @chan_rx: Receive mailbox channel
+ * @chan_boot_notify: Boot notification channel
* @desc: SoC description for this instance
* @seq_nr:Counter for number of messages sent.
+ * @has_boot_notify: Has separate boot notification channel
*/
struct k3_sysctrler_privdata {
struct mbox_chan chan_tx;
struct mbox_chan chan_rx;
+ struct mbox_chan chan_boot_notify;
struct k3_sysctrler_desc *desc;
u32 seq_nr;
+ bool has_boot_notify;
};
static inline
@@ -223,7 +227,8 @@ static int k3_sysctrler_start(struct udevice *dev)
debug("%s(dev=%p)\n", __func__, dev);
/* Receive the boot notification. Note that it is sent only once. */
- ret = mbox_recv(&priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
+ ret = mbox_recv(priv->has_boot_notify ? &priv->chan_boot_notify :
+ &priv->chan_rx, &msg, priv->desc->max_rx_timeout_us);
if (ret) {
dev_err(dev, "%s: Boot Notification response failed. ret =
%d\n",
__func__, ret);
@@ -272,6 +277,19 @@ static int k3_of_to_priv(struct udevice *dev,
return ret;
}
+ /* Some SoCs may have a optional channel for boot notification. */
+ priv->has_boot_notify = 1;
+ ret = mbox_get_by_name(dev, "boot_notify", &priv->chan_boot_notify);
+ if (ret == -ENODATA) {
+ dev_dbg(dev, "%s: Acquiring optional Boot_notify failed. ret =
%d. Using Rx\n",
+ __func__, ret);
+ priv->has_boot_notify = 0;
+ } else if (ret) {
+ dev_err(dev, "%s: Acquiring boot_notify channel failed. ret =
%d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
--
2.17.1
[PATCH v2 02/20] ram: k3-ddrss: lpddr4_structs_if.h: Add a pointer to ddr instance
Add a pointer to ddr instance int the lpddr4_privatedata_s structure for
supporting mutliple instances of DDR in the drivers.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/lpddr4_structs_if.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
index e41cbb7ff488..f2f1210c3c4e 100644
--- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
+++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
@@ -24,6 +24,7 @@ struct lpddr4_privatedata_s {
lpddr4_infocallback infohandler;
lpddr4_ctlcallback ctlinterrupthandler;
lpddr4_phyindepcallback phyindepinterrupthandler;
+ void *ddr_instance;
};
struct lpddr4_debuginfo_s {
--
2.17.1
[PATCH v2 03/20] ram: k3-ddrss: Add support for multiple instances of DDR subsystems
The current driver only supports single instance of DRR subsystem. Add
support for probing multiple instances of DDR subsystem.
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 138
1 file changed, 87 insertions(+), 51 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 95b5cf9128b0..96084d0b83d9 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -30,6 +30,9 @@
#define DDRSS_V2A_R1_MAT_REG 0x0020
#define DDRSS_ECC_CTRL_REG 0x0120
+#define SINGLE_DDR_SUBSYSTEM 0x1
+#define MULTI_DDR_SUBSYSTEM0x2
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -42,14 +45,12 @@ struct k3_ddrss_desc {
u32 ddr_freq2;
u32 ddr_fhs_cnt;
struct udevice *vtt_supply;
+ u32 instance;
+ lpddr4_obj *driverdt;
+ lpddr4_config config;
+ lpddr4_privatedata pd;
};
-static lpddr4_obj *driverdt;
-static lpddr4_config config;
-static lpddr4_privatedata pd;
-
-static struct k3_ddrss_desc *ddrss;
-
struct reginitdata {
u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
@@ -83,15 +84,16 @@ struct reginitdata {
offset = offset * 10 + (*i - '0'); } \
} while (0)
-static u32 k3_lpddr4_read_ddr_type(void)
+static u32 k3_lpddr4_read_ddr_type(const lpddr4_privatedata *pd)
{
u32 status = 0U;
u32 offset = 0U;
u32 regval = 0U;
u32 dram_class = 0U;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
- status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
+ status = ddrss->driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val);
if (status > 0U) {
printf("%s: Failed to read DRAM_CLASS\n", __func__);
hang();
@@ -102,23 +104,23 @@ static u32 k3_lpddr4_read_ddr_type(void)
return dram_class;
}
-static void k3_lpddr4_freq_update(void)
+static void k3_lpddr4_freq_update(struct k3_ddrss_desc *ddrss)
{
unsigned int req_type, counter;
for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
true, 1, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
req_type = readl(ddrss->ddrss_ctrl_mmr +
-CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
+CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10) & 0x03;
- debug("%s: received freq change req: req type = %d, req no. =
%d\n",
- __func__, req_type, counter);
+ debug("%s: received freq change req: req type = %d, req no. =
%d, instance = %d\n",
+ __func__, req_type, counter, ddrss->instance);
if (req_type == 1)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
@@ -132,31 +134,32 @@ static void k3_lpddr4_freq_update(void)
printf("%s: Invalid freq request type\n", __func__);
writel(0x1, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS, 0x80,
+ CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS +
ddrss->instance * 0x10, 0x80,
false, 10, false)) {
printf("Timeout during frequency handshake\n");
hang();
}
writel(0x0, ddrss->ddrss_ctrl_mmr +
- CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS);
+ CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS + ddrss->instance *
0x10);
}
}
-static void k3_lpddr4_ack_freq_upd_req(void)
+static void k3_lpddr4_ack_freq_upd_req(const lpddr4_privatedata *pd)
{
u32 dram_class;
+ struct k3_ddrss_desc *ddrss = (struct k3_ddrss_desc *)pd->ddr_instance;
debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
- dram_class = k3_lpddr4_read_ddr_type();
+ dram_class = k3_lpddr4_read_ddr_type(pd);
switch (dram_class) {
case DENALI_CTL_0_DRAM_CLASS_DDR4:
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
- k3_lpddr4_freq_update();
+
[PATCH v2 04/20] ram: k3-ddrss: Add support for configuring MSMC subsystem in case of Multiple DDR subsystems
In Multi DDR subystems with interleaving support, the following needs to
configured,
- interleaving granular size and region
- EMIFs to be enabled
- EMIFs with ecc to be enabled
- EMIF separated or interleaved
- number of cycles of unsuccessful EMIF arbitration to wait before
arbitrating for a different EMIF port, by default set to 3
Add support for configuring all the above by using a MSMC device
Signed-off-by: Aswath Govindraju
---
drivers/ram/k3-ddrss/k3-ddrss.c | 158
1 file changed, 158 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 96084d0b83d9..25e3976e6569 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -33,6 +33,75 @@
#define SINGLE_DDR_SUBSYSTEM 0x1
#define MULTI_DDR_SUBSYSTEM0x2
+#define MULTI_DDR_CFG0 0x00114100
+#define MULTI_DDR_CFG1 0x00114104
+#define DDR_CFG_LOAD0x00114110
+
+enum intrlv_gran {
+ GRAN_128B,
+ GRAN_512B,
+ GRAN_2KB,
+ GRAN_4KB,
+ GRAN_16KB,
+ GRAN_32KB,
+ GRAN_512KB,
+ GRAN_1GB,
+ GRAN_1_5GB,
+ GRAN_2GB,
+ GRAN_3GB,
+ GRAN_4GB,
+ GRAN_6GB,
+ GRAN_8GB,
+ GRAN_16GB
+};
+
+enum intrlv_size {
+ SIZE_0,
+ SIZE_128MB,
+ SIZE_256MB,
+ SIZE_512MB,
+ SIZE_1GB,
+ SIZE_2GB,
+ SIZE_3GB,
+ SIZE_4GB,
+ SIZE_6GB,
+ SIZE_8GB,
+ SIZE_12GB,
+ SIZE_16GB,
+ SIZE_32GB
+};
+
+struct k3_ddrss_data {
+ u32 flags;
+};
+
+enum ecc_enable {
+ DISABLE_ALL = 0,
+ ENABLE_0,
+ ENABLE_1,
+ ENABLE_ALL
+};
+
+enum emif_config {
+ INTERLEAVE_ALL = 0,
+ SEPR0,
+ SEPR1
+};
+
+enum emif_active {
+ EMIF_0 = 1,
+ EMIF_1,
+ EMIF_ALL
+};
+
+struct k3_msmc {
+ enum intrlv_gran gran;
+ enum intrlv_size size;
+ enum ecc_enable enable;
+ enum emif_config config;
+ enum emif_active active;
+};
+
struct k3_ddrss_desc {
struct udevice *dev;
void __iomem *ddrss_ss_cfg;
@@ -512,3 +581,92 @@ U_BOOT_DRIVER(k3_ddrss) = {
.probe = k3_ddrss_probe,
.priv_auto = sizeof(struct k3_ddrss_desc),
};
+
+static int k3_msmc_set_config(struct k3_msmc *msmc)
+{
+ u32 ddr_cfg0 = 0;
+ u32 ddr_cfg1 = 0;
+
+ ddr_cfg0 |= msmc->gran << 24;
+ ddr_cfg0 |= msmc->size << 16;
+ /* heartbeat_per, bit[4:0] setting to 3 is advisable */
+ ddr_cfg0 |= 3;
+
+ /* Program MULTI_DDR_CFG0 */
+ writel(ddr_cfg0, MULTI_DDR_CFG0);
+
+ ddr_cfg1 |= msmc->enable << 16;
+ ddr_cfg1 |= msmc->config << 8;
+ ddr_cfg1 |= msmc->active;
+
+ /* Program MULTI_DDR_CFG1 */
+ writel(ddr_cfg1, MULTI_DDR_CFG1);
+
+ /* Program DDR_CFG_LOAD */
+ writel(0x6000, DDR_CFG_LOAD);
+
+ return 0;
+}
+
+static int k3_msmc_probe(struct udevice *dev)
+{
+ struct k3_msmc *msmc = dev_get_priv(dev);
+ int ret = 0;
+
+ /* Read the granular size from DT */
+ ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran);
+ if (ret) {
+ dev_err(dev, "missing intrlv-gran property");
+ return -EINVAL;
+ }
+
+ /* Read the interleave region from DT */
+ ret = dev_read_u32(dev, "intrlv-size", &msmc->size);
+ if (ret) {
+ dev_err(dev, "missing intrlv-size property");
+ return -EINVAL;
+ }
+
+ /* Read ECC enable config */
+ ret = dev_read_u32(dev, "ecc-enable", &msmc->enable);
+ if (ret) {
+ dev_err(dev, "missing ecc-enable property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF configuration */
+ ret = dev_read_u32(dev, "emif-config", &msmc->config);
+ if (ret) {
+ dev_err(dev, "missing emif-config property");
+ return -EINVAL;
+ }
+
+ /* Read EMIF active */
+ ret = dev_read_u32(dev, "emif-active", &msmc->active);
+ if (ret) {
+ dev_err(dev, "missing emif-active property");
+ return -EINVAL;
+ }
+
+ ret = k3_msmc_set_config(msmc);
+ if (ret) {
+ dev_err(dev, "error setting msmc config");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id k3_msmc_ids[] = {
+ { .compatible = "ti,j721s2-msmc"},
+ {}
+};
+
+U_BOOT_DRIVER(k3_msmc) = {
+ .name = "k3_msmc",
+ .of_match = k3_msmc_ids,
+ .id = UCLASS_MISC,
+ .probe = k3_msmc_probe,
+ .priv_auto = sizeof(struct k3_msmc),
+ .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF,
+};
--
2.17.1
