Re: [PATCH v3 1/9] nand: atmel: Add DM based NAND driver

[Balamanikandan.Gunasundar]

On 25/10/22 4:36 pm, Michael Nazzareno Trimarchi wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the 
> content is safe
> 
> Hi
> 
> On Tue, Oct 25, 2022 at 12:52 PM Balamanikandan Gunasundar
>  wrote:
>>
>> This implementation is ported from the rework done by Boris Brezillon
>> in Linux. This porting is done based on linux-5.4-at91. The driver is
>> tested in sam9x60ek, sama5d3_xplained, sam9x75eb and sama7g54-ddr3-eb.
>>
>> Changes done includes
>>
>> - Adapt GPIO descriptor apis for U-Boot. Use gpio_request_by_name_nodev,
>>dm_gpio_get_value etc.
>> - Use U_BOOT_DRIVER instead of platform_driver.
>> - Replace struct platform_device with struct udevice
>> - Check the status of nfc exec operation by polling the status
>>register instead of interrupt based handling
>> - DMA operations not supported. Remove it
>> - Adapt DT parsing to U-Boot APIs
>>
>> Signed-off-by: Balamanikandan Gunasundar 
>> 
>>
>> Signed-off-by: Balamanikandan Gunasundar 
>> 
> 
> Kindle, fix signed off and describe change from V2 to V3
> 
> Michael
> 

Hi Michael,

I described all the v3 changes in the cover letter. Is it OK if I 
describe the changes in each patch specifically.

Bala.

>> ---
>>   drivers/mtd/nand/raw/Kconfig |8 +
>>   drivers/mtd/nand/raw/Makefile|1 +
>>   drivers/mtd/nand/raw/atmel/Makefile  |4 +
>>   drivers/mtd/nand/raw/atmel/nand-controller.c | 2286 ++
>>   4 files changed, 2299 insertions(+)
>>   create mode 100644 drivers/mtd/nand/raw/atmel/Makefile
>>   create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c
>>
>>
> 
> 
> --
> Michael Nazzareno Trimarchi
> Co-Founder & Chief Executive Officer
> M. +39 347 913 2170
> mich...@amarulasolutions.com
> __
> 
> Amarula Solutions BV
> Joop Geesinkweg 125, 1114 AB, Amsterdam, NL
> T. +31 (0)85 111 9172
> i...@amarulasolutions.com
> www.amarulasolutions.com

Re: [PATCH] treewide: Remove the unnecessary space before semicolon

[Stefan Roese]

On 26.10.22 06:40, Bin Meng wrote:

%s/return ;/return;

Signed-off-by: Bin Meng 
---

  arch/powerpc/cpu/mpc85xx/cpu_init.c   | 2 +-
  arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 2 +-
  arch/powerpc/cpu/mpc85xx/fdt.c| 6 +++---
  arch/powerpc/cpu/mpc85xx/liodn.c  | 4 ++--
  arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 2 +-
  arch/powerpc/cpu/mpc85xx/portals.c| 8 
  arch/powerpc/cpu/mpc85xx/tlb.c| 2 +-
  arch/powerpc/cpu/mpc8xxx/fdt.c| 2 +-
  arch/powerpc/cpu/mpc8xxx/law.c| 2 +-
  arch/powerpc/lib/bootm.c  | 4 ++--
  board/ti/evm/evm.c| 2 +-
  drivers/ddr/fsl/util.c| 2 +-
  drivers/net/fm/init.c | 4 ++--
  13 files changed, 21 insertions(+), 21 deletions(-)


Nice.

Reviewed by: Stefan Roese 

Thanks,
Stefan


diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 92a7e608ce..90f024d0a7 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -446,7 +446,7 @@ ulong cpu_init_f(void)
  /* Implement a dummy function for those platforms w/o SERDES */
  static void __fsl_serdes__init(void)
  {
-   return ;
+   return;
  }
  __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
  
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c

index 1bba216371..e6347cfd2d 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -76,7 +76,7 @@ void setup_ifc(void)
ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
  
-	return ;

+   return;
  }
  #endif
  
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c

index c8ad6a1b01..61d8aa7f4c 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -271,13 +271,13 @@ static inline void ft_fixup_l2cache(void *blob)
  
  	if (ph == NULL) {

debug("no next-level-cache property\n");
-   return ;
+   return;
}
  
  	off = fdt_node_offset_by_phandle(blob, *ph);

if (off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
-   return ;
+   return;
}
  
  	ft_fixup_l2cache_compatible(blob, off);

@@ -373,7 +373,7 @@ next:
l3_off = fdt_node_offset_by_phandle(blob, l3_off);
if (l3_off < 0) {
printf("%s: %s\n", __func__, fdt_strerror(off));
-   return ;
+   return;
}
ft_fixup_l3cache(blob, l3_off);
}
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index a084002494..34974c92bd 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -111,7 +111,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
  #endif
default:
printf("Error: Invalid device type to %s\n", __FUNCTION__);
-   return ;
+   return;
}
  
  	base = (liodn_bases[dev].id[0] << 16) | liodn_bases[dev].id[0];

@@ -232,7 +232,7 @@ static void fdt_fixup_srio_liodn(void *blob, struct 
srio_liodn_id_table *tbl)
/* search for srio node, if doesn't exist just return - nothing todo */
srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio");
if (srio_off < 0)
-   return ;
+   return;
  
  	for (i = 0; i < srio_liodn_tbl_sz; i++) {

int off, portid = tbl[i].portid;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c 
b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
index 2a5c3e3200..38f30afdfc 100644
--- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c
@@ -45,7 +45,7 @@ void fsl_serdes_init(void)
  
  	if (srds1_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {

printf("Invalid PORDEVSR[IO_SEL] = %d\n", srds1_cfg);
-   return ;
+   return;
}
  
  	for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {

diff --git a/arch/powerpc/cpu/mpc85xx/portals.c 
b/arch/powerpc/cpu/mpc85xx/portals.c
index 52e2124fb9..6b4cbddcdf 100644
--- a/arch/powerpc/cpu/mpc85xx/portals.c
+++ b/arch/powerpc/cpu/mpc85xx/portals.c
@@ -21,7 +21,7 @@ void fdt_portal(void *blob, const char *compat, const char 
*container,
  
  	off = fdt_node_offset_by_compatible(blob, -1, compat);

if (off < 0)
-   return ;
+   return;
  
  	off = fdt_parent_offset(blob, off);

/* if non-zero assume we have a container */
@@ -35,7 +35,7 @@ void fdt_portal(void *blob, const char *compat, const char 
*container,
range = fdt_getprop_w(blob, off, "ranges", );
if (range == NULL) {

Re: imx8 regression: cyclic_register for watchdog@30280000 failed

[Stefan Roese]

Hi Tim,

On 25.10.22 18:32, Tim Harvey wrote:

Greetings,

I've noticed a regression since the merge of the cyclic framework use
for watchdog on my imx8m boards:

cyclic_register for watchdog@3028 failed
WDT:   Failed to start watchdog@3028


Could you please post the complete bootlog? Which board(s) are these
(defconfig)?


A bisect lead me to the following 3 sequential patches:
29caf9305b6f cyclic: Use schedule() instead of WATCHDOG_RESET()
^^^ bad
881d4108257a cyclic: Introduce schedule() function
^^^ unbuildable
c2fd0ca1a822 watchdog: Integrate watchdog triggering into the cyclic framework
^^^ unbootable

Before I did in much deeper has anyone else run into and/or resolved
this? I'm wondering if something is missing from defconfig?


I'll look into this today.

Thanks,
Stefan

Re: Please pull u-boot-watchdog/master

[Stefan Roese]

Hi Tom,

On 24.10.22 13:43, Stefan Roese wrote:

Hi Tom,

please pull the following watchdog related changes:


- nuvoton: add expire function for generic reset (Jim)
- handle watchdogs during keyed autoboot (Rasmus)
- cyclic: Don't disable cylic function upon exceeding CPU time (Stefan)
- ulp wdog: Updates to support iMX93 and DM (Alice)


Here the Azure build, without any issues:

https://dev.azure.com/sr0718/u-boot/_build/results?buildId=273=results


ping about this MR.

Thanks,
Stefan


Thanks,
Stefan


The following changes since commit 
7723828c97bc107d2fba976fc50403ac8747f1bc:


   Merge branch '2022-10-21-enforce-some-DM-migrations' (2022-10-21 
15:32:45 -0400)


are available in the Git repository at:

   g...@source.denx.de:u-boot/custodians/u-boot-watchdog.git

for you to fetch changes up to 5e112c7ca8ee45860e27f23059d9a319ba8eb6d3:

   watchdog: ulp_wdog: add driver model for ulp watchdog driver 
(2022-10-24 11:10:21 +0200)



Alice Guo (3):
   watchdog: ulp_wdog: Update watchdog driver for imx93
   watchdog: ulp_wdog: enable watchdog interrupt on imx93
   watchdog: ulp_wdog: add driver model for ulp watchdog driver

Jim Liu (1):
   wdt: nuvoton: add expire function for generic reset

Rasmus Villemoes (3):
   watchdog: introduce a u-boot,autostart property
   sandbox: add SIGALRM-based watchdog device
   sandbox.dtsi: add a sandbox,alarm-wdt instance

Stefan Roese (1):
   cyclic: Don't disable cylic function upon exceeding CPU time

Ye Li (1):
   ulp_wdog: Update ulp wdog driver for 32bits command

  arch/sandbox/cpu/os.c    |  17 +++
  arch/sandbox/dts/sandbox.dtsi    |   6 +
  common/cyclic.c  |  12 +-
  configs/sandbox64_defconfig  |   2 +
  configs/sandbox_defconfig    |   2 +
  doc/device-tree-bindings/watchdog/common.txt |   9 +-
  drivers/watchdog/Kconfig |   8 ++
  drivers/watchdog/Makefile    |   1 +
  drivers/watchdog/npcm_wdt.c  |   6 +
  drivers/watchdog/sandbox_alarm-wdt.c |  79 +
  drivers/watchdog/ulp_wdog.c  | 159 
+++

  drivers/watchdog/wdt-uclass.c    |  15 ++-
  include/cyclic.h |   2 +
  include/os.h |  17 +++
  14 files changed, 297 insertions(+), 38 deletions(-)
  create mode 100644 drivers/watchdog/sandbox_alarm-wdt.c


Viele Grüße,
Stefan Roese

--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: s...@denx.de

Re: [PATCH v3 1/2] x86: fsp: Depend on DM_RTC

[Bin Meng]

Hi Sean,

On Wed, Oct 26, 2022 at 7:35 AM Simon Glass  wrote:
>
> Hi,
>
> On Mon, 24 Oct 2022 at 22:57, Stefan Roese  wrote:
> >
> > On 24.10.22 18:49, Bin Meng wrote:
> > > On Mon, Oct 24, 2022 at 11:42 PM Sean Anderson  
> > > wrote:
> > >>
> > >> FSP support requires DM_RTC for rtc_write32. Select it.
> > >>
> > >> Fixes: ba65808e7d0 ("x86: fsp: Save stack address to CMOS for next S3 
> > >> boot")

Please drop this "Fixes" tag.

> > >> Signed-off-by: Sean Anderson 
> > >> ---
> > >> This seems like it would never have worked. Does fsp_save_s3_stack even
> > >
> > > This was working before. Did you test it on x86 that now it is broken?
>
> I think it is better to select these options rather than rely on
> boards to do so. I suspect that 'moveconfig.py -s' will remove some
> things from defconfigs.
>
> Reviewed-by: Simon Glass 
>
> > >
> > > +Stefan
> >
> > I don't have access to this FSP x86 target any more, so can't test
> > anything any more.
> >
> > Thanks,
> > Stefan
> >

Regards,
Bin

Re: [PATCH v2] serial: mxc: Keep the original FIFO empty check

[Fabio Estevam]

Hi Tim,

On 25/10/2022 20:23, Tim Harvey wrote:


Fabio,

This resolves the issue. Why would the kernel not suffer from this as
well? We are essentially saying if the FIFO is not full but also not
empty we need to wait so do we have a FIFO size of 1 or something
here as opposed to the kernel?


The FIFO has a fixed size of 32 chars.

Kernel uses TXTL, which "controls the threshold at which a maskable 
interrupt is generated by the

TxFIFO".

We do not use interrupts in U-Boot. Prior to Johannes' patch, we only
checked for the TXFIFO empty condition, which avoided sending data when 
nothing was

available inside the FIFO (under-run condition).

Johannes' patch handles over-run condition.

My patch guarantees that both over-run and under-run conditions are 
handled.


When the number of chars in the FIFO is 1, 2, 3,...30, the transmission
can safely happen. Special cases are FIFO empty and FIFO full, which
returns -EAGAIN to the serial core.

Regards,

Fabio Estevam
--
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-60 Fax: (+49)-8142-66989-80 Email: 
feste...@denx.de

Re: commit 787f04bb6a - imx: add USB2_BOOT type

[Rasmus Villemoes]

On 18/10/2022 02.43, Peng Fan wrote:
> + Stefano & Fabio
> 


 Is there any chance you could make some information on that ROM API
 public so it's possible for outsiders to understand what's going on?
> 
> What could only help is to ask the ROM team to see whether they have
> plan to public the ROM API details and when. Otherwise you could only
> read the code to understand how it works.
> 
>>>
>>> Could you please try below changes to check whether it fixes your issue?
>>
>> Well, it seems very likely it would, but could you _please_ answer the
>> real question so we as a community has a chance of evaluating whether
>> that's the proper fix or something else entirely is needed. And so that
>> in the future we as a community would have a chance of objecting to
>> including 787f04bb6a in the first place.
> 
> You could help reviewing if you have time.

Don't you see the absurdity of on the one hand saying that the only way
to understand the ROM API is to study the U-Boot side of the code, and
on the other hand asking others to review changes to said code?

If the API could be understood from merely reading existing U-Boot code,
than that code is by definition perfect and won't need to be changed.

Now that I know there is a dedicated ROM team, let me rephrase:

Is there any chance you could reach out to said ROM team and ask if they
could make some information on the API public?

[The "you" in the previous questions have always meant NXP, not you
personally.]

Rasmus

Re: [PATCH 1/1] cli: always show cursor

[Simon Glass]

Hi Heinrich,

On Sat, 22 Oct 2022 at 03:21, Heinrich Schuchardt
 wrote:
>
> We may enter the command line interface in a state where on the remote
> console the cursor is not shown. Send an escape sequence to enable it.
>
> Signed-off-by: Heinrich Schuchardt 
> ---
>  common/main.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/common/main.c b/common/main.c
> index 682f3359ea..4e7e7b17d6 100644
> --- a/common/main.c
> +++ b/common/main.c
> @@ -7,6 +7,7 @@
>  /* #define DEBUG   */
>
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -66,6 +67,9 @@ void main_loop(void)
>
> autoboot_command(s);
>
> +   if (!CONFIG_IS_ENABLED(DM_VIDEO) || CONFIG_IS_ENABLED(VIDEO_ANSI))
> +   printf(ANSI_CURSOR_SHOW "\n");

Could we create a library which emits these codes? Like ansi_cursor_show() ?

> +
> cli_loop();
> panic("No CLI available");
>  }
> --
> 2.37.2
>

Regards,
Simon

Re: [PATCH v3 6/6] test: add test for eficonfig secure boot key management

[Simon Glass]

Hi Heinrich,

On Wed, 19 Oct 2022 at 15:39, Heinrich Schuchardt  wrote:
>
> On 10/19/22 15:17, Simon Glass wrote:
> > iHi Heinrich,
> >
> > On Fri, 14 Oct 2022 at 22:43, Heinrich Schuchardt  
> > wrote:
> >>
> >> On 10/15/22 03:10, Simon Glass wrote:
> >>> Hi Ilias,
> >>>
> >>> On Fri, 14 Oct 2022 at 09:59, Ilias Apalodimas
> >>>  wrote:
> 
>  Hi Simon,
> 
>  On Fri, 14 Oct 2022 at 18:56, Simon Glass  wrote:
> >
> > Hi,
> >
> > On Fri, 14 Oct 2022 at 00:58, Masahisa Kojima
> >  wrote:
> >>
> >> Provide a unit test for the eficonfig secure boot key
> >> management menu.
> >>
> >> Signed-off-by: Masahisa Kojima 
> >> ---
> >> No change since v2
> >>
> >> newly created in v2
> >>
> >>test/py/tests/test_eficonfig/conftest.py  |  84 +++-
> >>test/py/tests/test_eficonfig/defs.py  |  14 +
> >>.../test_eficonfig/test_eficonfig_sbkey.py| 472 
> >> ++
> >>3 files changed, 568 insertions(+), 2 deletions(-)
> >>create mode 100644 test/py/tests/test_eficonfig/defs.py
> >>create mode 100644 
> >> test/py/tests/test_eficonfig/test_eficonfig_sbkey.py
> >
> > Please can this test be in C? Also, using down-arrow to select menus
> > is brittle. Add a function to select the one you want, e.g. by name.
> >
> 
>  Is there a very specific reason why we should do stuff like that in C?
> >>>
> >>> Yes, see here.
> >>>
> Python is way easier to extend and test in our case.
> >>>
> >>> In what way? It seems a lot more complicated, plus the brittle nature
> >>> of this test suggests it will be a hassle to maintain.
> >>>
> >>> https://u-boot.readthedocs.io/en/latest/develop/tests_writing.html#python-or-c
> >>>
> >>> There is a pending update here too:
> >>>
> >>> https://patchwork.ozlabs.org/project/uboot/patch/20221013122927.636867-15-...@chromium.org/
> >>
> >> The discussion touches different aspects:
> >>
> >> ** What does it take to make a GUI easily testable? **
> >>
> >> Relying on cursor movement for testing is fragile. This is why GUIs
> >> often assign to each executable element the following:
> >>
> >> * Access key, e.g  
> >> A key combination that when entered will have the the same
> >> effect as selecting the GUI item
> >> * Access string, '@SAVE'
> >> A string that when typed into the command field will have
> >> the same effect as selecting the GUI item
> >>
> >> Let's look at U-Boot's menu entry definition:
> >>
> >> struct bootmenu_entry {
> >>   unsigned short int num;  // unique number 0 .. MAX_COUNT
> >>   char key[3]; // key identifier of number
> >>   char *title; // title of entry
> >>   char *command;   // hush command of entry
> >>   enum boot_type type; // boot type of entry
> >>   u16 bootorder;   // order for each boot type
> >>   struct bootmenu_data *menu;  // this bootmenu
> >>   struct bootmenu_entry *next; // next menu entry (num+1)
> >> }
> >>
> >> Our structure lacks an accessor element that can be used to select a
> >> menu item without using cursor actions.
> >>
> >> Compound keystrokes like  are send as multiple bytes on the
> >> console, e.g. 1b 5b 31 37 3b 35 7e.
> >>
> >> We may define a field shortcut of type char *. If the string is received
> >> by the menu loop, let it activate the matching menu entry. Let cursor
> >> actions (up, down, enter, space '+', '-') interrupt matching the
> >> shortcut string.
> >>
> >> Instead we could also use a convention for the title:
> >>
> >> If a letter in the title is preceded by '&', this is the shortcut key.
> >> This letter will be shown highlighted in the menu and the ampersand will
> >> not be shown.
> >>
> >> This is probably easier to implement.
> >>
> >> Adding the shortcut facility will allow both for easier testing and
> >> faster navigation.
> >>
> >> ** Choice of programming language **
> >>
> >> Several aspects control the choice of the programming language for tests:
> >>
> >> - Testing single library functions is only possible in C.
> >> - Checking contents of internal structures is only possible in C.
> >> - Testing the U-Boot's CLI is easily accessible in our Python framework.
> >> - Preparation of complex test data is easier to do in Python.
> >> - Mixed language tests should be avoided if not strictly necessary.
> >> It is much easier to maintain a single code source for a test.
> >>
> >> ** What to do for secure boot key management? **
> >>
> >> Secure boot key management requires complex preparation which fits well
> >> into out Python testing framework.
> >>
> >> Once we provide shortcut keys to U-Boot menus the entries will be easily
> >> accessible from Python.
> >>
> >> As we want to avoid complexity due to mixed language tests we should
> >> stick to Python for testing key management at the user level.
> >
> > The 

Re: [u-boot][PATCH v2 2/4] scripts: Makefile.spl: Enable memory drivers to be built for SPL

[Simon Glass]

Hi Tom,

On Thu, 20 Oct 2022 at 06:29, Tom Rini  wrote:
>
> On Thu, Oct 20, 2022 at 03:23:42PM +0300, Roger Quadros wrote:
> > Hi Tom,
> >
> > On 19/10/2022 15:54, Tom Rini wrote:
> > > On Wed, Oct 19, 2022 at 11:17:35AM +0300, Roger Quadros wrote:
> > >>
> > >>
> > >> On 18/10/2022 20:40, Tom Rini wrote:
> > >>> On Thu, Oct 06, 2022 at 04:23:58PM +0300, Roger Quadros wrote:
> >  We will need ti-gpmc driver for SPL. Allow memory drivers
> >  do be built for SPL.
> > 
> >  Signed-off-by: Roger Quadros 
> >  ---
> >   scripts/Makefile.spl | 1 +
> >   1 file changed, 1 insertion(+)
> > 
> >  diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
> >  index 3bafeb4fe9..110076b22f 100644
> >  --- a/scripts/Makefile.spl
> >  +++ b/scripts/Makefile.spl
> >  @@ -114,6 +114,7 @@ libs-$(CONFIG_PARTITIONS) += disk/
> >   endif
> > 
> >   libs-y += drivers/
> >  +libs-y += drivers/memory/
> >   libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/dwc3/
> >   libs-$(CONFIG_SPL_USB_GADGET) += drivers/usb/cdns3/
> >   libs-y += dts/
> > >>>
> > >>> This ends up being the wrong approach as it then pulls in
> > >>> drivers/memory/stm32-fmc2-ebi.o on all of those platforms, in SPL, which
> > >>> is not what's intended. We need an SPL_MEMORY symbol and then gate the
> > >>> directory on that.
> > >>>
> >
> > I have a question about how CONFIG_SPL_MEMORY works together with 
> > CONFIG_MEMORY.
> >
> > Do we use CONFIG_SPL_MEMORY only to gate the drivers/memory directory 
> > inclusion?
> > Then continue to use CONFIG_MEMORY and others to enable/disable driver
> > build for both non-SPL and SPL case?
> >
> > So drivers/memory/Makefile remains as it is?
>
> Well, for consistency code should use IS_ENABLED(MEMORY) which will be
> true for CONFIG_MEMORY or CONFIG_SPL_MEMORY.

nit: CONFIG_IS_ENABLED(MEMORY)

Perhaps we can look at my Kconfig series so it can become
CONFIG(MEMORY) and we can drop all the SPL_TPL_ stuff in Makefiles?

Regards,
SImon

Re: [PATCH v3 1/2] x86: fsp: Depend on DM_RTC

[Simon Glass]

Hi,

On Mon, 24 Oct 2022 at 22:57, Stefan Roese  wrote:
>
> On 24.10.22 18:49, Bin Meng wrote:
> > On Mon, Oct 24, 2022 at 11:42 PM Sean Anderson  
> > wrote:
> >>
> >> FSP support requires DM_RTC for rtc_write32. Select it.
> >>
> >> Fixes: ba65808e7d0 ("x86: fsp: Save stack address to CMOS for next S3 
> >> boot")
> >> Signed-off-by: Sean Anderson 
> >> ---
> >> This seems like it would never have worked. Does fsp_save_s3_stack even
> >
> > This was working before. Did you test it on x86 that now it is broken?

I think it is better to select these options rather than rely on
boards to do so. I suspect that 'moveconfig.py -s' will remove some
things from defconfigs.

Reviewed-by: Simon Glass 

> >
> > +Stefan
>
> I don't have access to this FSP x86 target any more, so can't test
> anything any more.
>
> Thanks,
> Stefan
>
> >> get called in SPL? Maybe it should be converted to use dm_rtc_write
> >> instead.
> >>
> >> Changes in v3:
> >> - New
> >>
> >>   arch/x86/Kconfig | 2 ++
> >>   1 file changed, 2 insertions(+)
> >>
> >> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> >> index 7cbfd6c9720..ed8216d9ad0 100644
> >> --- a/arch/x86/Kconfig
> >> +++ b/arch/x86/Kconfig
> >> @@ -362,6 +362,8 @@ config HAVE_FSP
> >>  depends on !EFI
> >>  select USE_HOB
> >>  select HAS_ROM
> >> +   select DM_RTC
> >> +   select SPL_DM_RTC
> >>  help
> >>Select this option to add an Firmware Support Package binary to
> >>the resulting U-Boot image. It is a binary blob which U-Boot 
> >> uses
> >> --
> >
> > Regards,
> > Bin
Regards,
Simon

Re: [PATCH] rtc: add ht1380 driver

[Simon Glass]

Hi Sergei,

On Tue, 25 Oct 2022 at 08:24, Sergei Antonov  wrote:
>
> Support Holtek HT1380/HT1381 Serial Timekeeper Chip.
> Datasheet:
> https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf
>
> Signed-off-by: Sergei Antonov 
> ---
>  drivers/rtc/Kconfig  |   7 +
>  drivers/rtc/Makefile |   1 +
>  drivers/rtc/ht1380.c | 303 +++
>  3 files changed, 311 insertions(+)
>  create mode 100644 drivers/rtc/ht1380.c

Looks good, just some minor things.

>
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 23963271928a..f62ee43b0f89 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -220,4 +220,11 @@ config RTC_ZYNQMP
>   Say "yes" here to support the on chip real time clock
>   present on Xilinx ZynqMP SoC.
>
> +config RTC_HT1380
> +   bool "Enable Holtek HT1380/HT1381 RTC driver"
> +   depends on DM_RTC && DM_GPIO
> +   help
> + Say "yes" here to get support for Holtek HT1380/HT1381
> + Serial Timekeeper Chip.

What features does it have? Needs a bit more detail.

> +
>  endmenu
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index d621be622848..d04ac8fb0938 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o
>  obj-$(CONFIG_RTC_DS3232) += ds3232.o
>  obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o
>  obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
> +obj-$(CONFIG_RTC_HT1380) += ht1380.o
>  obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
>  obj-$(CONFIG_RTC_IMXDI) += imxdi.o
>  obj-$(CONFIG_RTC_ISL1208) += isl1208.o
> diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c
> new file mode 100644
> index ..af28b5f25fcd
> --- /dev/null
> +++ b/drivers/rtc/ht1380.c
> @@ -0,0 +1,303 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Holtek HT1380/HT1381 Serial Timekeeper Chip
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +struct ht1380_priv {
> +   struct gpio_desc rst_desc;
> +   struct gpio_desc clk_desc;
> +   struct gpio_desc dat_desc;
> +};
> +
> +enum registers {
> +   SEC,
> +   MIN,
> +   HOUR,
> +   MDAY,
> +   MONTH,
> +   WDAY,
> +   YEAR,
> +   WP,
> +   N_REGS
> +};
> +
> +static const int BURST = 0xBE;
> +static const int READ = 1;
> +
> +static void ht1380_half_period_delay(void)
> +{
> +   /* Delay for half a period. 1 us complies with the 500 KHz maximum
> +  input serial clock limit given by the datasheet. */

/*
 * Delay for half...
 * second line
 */

Please fix globally.

> +   udelay(1);
> +}
> +
> +static int ht1380_send_byte(struct ht1380_priv *priv, int byte)
> +{
> +   int ret;
> +
> +   for (int bit = 0; bit < 8; bit++) {
> +   ret = dm_gpio_set_value(>dat_desc, byte >> bit & 1);
> +   if (ret)
> +   break;
> +   ht1380_half_period_delay();
> +
> +   ret = dm_gpio_set_value(>clk_desc, 1);
> +   if (ret)
> +   break;
> +   ht1380_half_period_delay();
> +
> +   ret = dm_gpio_set_value(>clk_desc, 0);
> +   if (ret)
> +   break;
> +   }
> +
> +   return ret;
> +}
> +
> +static int ht1380_reset_off(struct ht1380_priv *priv)
> +{
> +   const unsigned int T_CC = 4; /* us, Reset to Clock Setup */
> +   int ret;
> +
> +   /* Go out of RESET state.
> +  Make sure we make the minimal delay required by the datasheet. */
> +   ret = dm_gpio_set_value(>rst_desc, 1);
> +   udelay(T_CC);

blank line before return

> +   return ret;
> +}
> +
> +static int ht1380_reset_on(struct ht1380_priv *priv)

function comment - does it stay in reset state or automatically exit?

> +{
> +   const unsigned int T_CWH = 4; /* us, Reset Inactive Time */
> +   int ret;
> +
> +   /* Enter RESET state.
> +  Make sure we make the minimal delay required by the datasheet. */
> +   ret = dm_gpio_set_value(>rst_desc, 0);
> +   udelay(T_CWH);
> +   return ret;
> +}
> +
> +static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm)
> +{
> +   struct ht1380_priv *priv = dev_get_priv(dev);
> +   int ret, i, bit, reg[N_REGS];
> +
> +   ret = dm_gpio_set_value(>clk_desc, 0);
> +   if (ret)
> +   return ret;
> +
> +   ret = dm_gpio_set_dir_flags(>dat_desc, GPIOD_IS_OUT);
> +   if (ret)
> +   return ret;
> +
> +   ret = ht1380_reset_off(priv);
> +   if (ret)
> +   goto exit;
> +
> +   ret = ht1380_send_byte(priv, BURST + READ);
> +   if (ret)
> +   goto exit;
> +
> +   ret = dm_gpio_set_dir_flags(>dat_desc, GPIOD_IS_IN);
> +   if (ret)
> +   goto exit;
> +
> +   for (i = 0; i < N_REGS; i++) {
> +   reg[i] = 0;
> +
> +   for (bit = 0; bit < 8; bit++) {
> + 

Re: [PATCH v1 2/3] drivers: timer: add timer driver for ARMv7 based Tegra devices

[Simon Glass]

Hi Svyatoslav,

On Mon, 24 Oct 2022 at 00:26, Svyatoslav Ryhel  wrote:
>
> Add timer support for T20/T30/T114 and T124 based devices.
> Driver is based on DM, has device tree support and can be
> used on SPL and early boot stage.
>
> Tested-by: Andreas Westman Dorcsak  # ASUS TF600T T30
> Tested-by: Jonas Schwöbel  # Surface RT T30
> Tested-by: Robert Eckelmann  # ASUS TF101 T20
> Tested-by: Svyatoslav Ryhel  # LG P895 T30
> Co-developed-by: Jonas Schwöbel 
> Signed-off-by: Jonas Schwöbel 
> Signed-off-by: Svyatoslav Ryhel 
> ---
>  drivers/timer/Kconfig   |   8 +++
>  drivers/timer/Makefile  |   1 +
>  drivers/timer/tegra-timer.c | 124 
>  3 files changed, 133 insertions(+)
>  create mode 100644 drivers/timer/tegra-timer.c
>
> diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
> index fd8745ffc2..702ffd3084 100644
> --- a/drivers/timer/Kconfig
> +++ b/drivers/timer/Kconfig
> @@ -244,6 +244,14 @@ config STM32_TIMER
>   Select this to enable support for the timer found on
>   STM32 devices.
>
> +config TEGRA_TIMER
> +   bool "Tegra timer support"
> +   depends on TIMER
> +   select TIMER_EARLY
> +   help
> + Select this to enable support for the timer found on
> + Tegra devices.
> +
>  config X86_TSC_TIMER
> bool "x86 Time-Stamp Counter (TSC) timer support"
> depends on TIMER && X86
> diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
> index 7bfb7749e9..ccbff05d43 100644
> --- a/drivers/timer/Makefile
> +++ b/drivers/timer/Makefile
> @@ -26,6 +26,7 @@ obj-$(CONFIG_SANDBOX_TIMER)   += sandbox_timer.o
>  obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o
>  obj-$(CONFIG_STI_TIMER)+= sti-timer.o
>  obj-$(CONFIG_STM32_TIMER)  += stm32_timer.o
> +obj-$(CONFIG_TEGRA_TIMER)  += tegra-timer.o
>  obj-$(CONFIG_X86_TSC_TIMER)+= tsc_timer.o
>  obj-$(CONFIG_MTK_TIMER)+= mtk_timer.o
>  obj-$(CONFIG_MCHP_PIT64B_TIMER)+= mchp-pit64b-timer.o
> diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c
> new file mode 100644
> index 00..cda460921f
> --- /dev/null
> +++ b/drivers/timer/tegra-timer.c
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2022 Svyatoslav Ryhel 
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +#include 
> +
> +#define TEGRA_OSC_CLK_ENB_L_SET(NV_PA_CLK_RST_BASE + 0x320)
> +#define TEGRA_OSC_SET_CLK_ENB_TMR  BIT(5)
> +
> +#define TEGRA_TIMER_USEC_CNTR  (NV_PA_TMRUS_BASE + 0)
> +#define TEGRA_TIMER_USEC_CFG   (NV_PA_TMRUS_BASE + 4)
> +
> +#define TEGRA_TIMER_RATE   100 /* 1 MHz */
> +
> +u64 notrace timer_early_get_count(void)
> +{
> +   /* At this stage raw timer is used */
> +   return readl(TEGRA_TIMER_USEC_CNTR);
> +}
> +
> +unsigned long notrace timer_early_get_rate(void)
> +{
> +   return TEGRA_TIMER_RATE;
> +}
> +
> +#if CONFIG_IS_ENABLED(BOOTSTAGE)
> +ulong timer_get_boot_us(void)
> +{
> +   u64 ticks = 0;
> +   int ret;
> +
> +   ret = dm_timer_init();

You cannot necessarily call this here...does it work when bootstage is enabled?

Regards,
Simon

Re: [PATCH v2] cmd: mtd: check if a block has to be skipped or erased

[Simon Glass]

Hi,

On Mon, 24 Oct 2022 at 03:35, Dario Binacchi
 wrote:
>
> From: Mikhail Kshevetskiy 
>
> As reported by patch [1], the `mtd erase' command should not erase bad
> blocks.
> To force bad block erasing you have to use the `mtd erase.dontskipbad'
> command.
>
> This patch tries to fix the same issue without modifying code taken
> from the linux kernel, in order to make further upgrades easier.
>
> [1] 
> https://lore.kernel.org/all/20221006031501.110290-2-mikhail.kshevets...@iopsys.eu/
> Suggested-by: Michael Trimarchi 
> Co-developed-by: Michael Trimarchi 
> Signed-off-by: Michael Trimarchi 
> Co-developed-by: Dario Binacchi 
> Signed-off-by: Dario Binacchi 
> Tested-by: Mikhail Kshevetskiy 
> Signed-off-by: Mikhail Kshevetskiy 
>
> ---
>
> Changes in v2:
> - Change the commit author
> - Do not continue to erase if scrub option is enabled and a bad block
>   was found but return from the function.
> - Update the patch tags.
>
>  cmd/mtd.c | 17 +++--
>  1 file changed, 15 insertions(+), 2 deletions(-)

Can we get some tests in test/dm/mtd.c?

Regards,
Simon

Re: [PATCH] xen: pvblock: Use uclass_probe_all

[Simon Glass]

On Sat, 22 Oct 2022 at 08:33, Michal Suchanek  wrote:
>
> Also eliminate useless code and variables.
>
> Signed-off-by: Michal Suchanek 
> ---
>
>  drivers/xen/pvblock.c | 9 ++---
>  1 file changed, 2 insertions(+), 7 deletions(-)
>

Reviewed-by: Simon Glass 

Re: [PATCH] lib: fix buggy strcmp and strncmp

[Rasmus Villemoes]

On 05/10/2022 11.09, Rasmus Villemoes wrote:
> There are two problems with both strcmp and strncmp:
> 

Hi Tom

Could you consider applying this now to give it ample time to soak
before release? I'm pretty confident it's correct.

Rasmus

Re: [PATCH 3/6] net: (actually/better) deal with CVE-2022-{30790, 30552}

[Rasmus Villemoes]

On 20/10/2022 17.32, Artur Łącki wrote:
> I tested these patches with my exploit. At the moment it looks like the
> vulnerability has been fixed.

Thanks for testing. Can I/we add a "Tested-by: Artur Łącki
"?

Rasmus

Re: [PATCH v2] serial: mxc: Keep the original FIFO empty check

[Tim Harvey]

On Tue, Oct 25, 2022 at 3:57 PM Fabio Estevam  wrote:
>
> From: Fabio Estevam 
>
> Tim Harvey reported that since commit c7878a0483c5 ("serial: mxc:
> have putc use the TXFIFO"), console messages put inside board_init()
> are no longer printed correctly.
>
> This change added a check to handle the UART FIFO full condition and
> removed the UART FIFO empty check, which causes the problem.
>
> To avoid console corruption, add back the original UART FIFO empty
> check so that when the FIFO is empty, mxc_serial_putc() returns -EAGAIN
> to the core serial-uclass.c.
>
> This way the serial core can properly handle the UART empty condition
> by not doing character transmission when -EAGAIN is returned.
>
> Fixes: c7878a0483c5 ("serial: mxc: have putc use the TXFIFO")
> Reported-by: Tim Harvey 
> Signed-off-by: Fabio Estevam 
> ---
> Changes since v1:
> - Add the check for FIFO full and FIFO empty.
>
>  drivers/serial/serial_mxc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index 4cf79c1ca24f..d3fbe76065ec 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, const 
> char ch)
> struct mxc_serial_plat *plat = dev_get_plat(dev);
> struct mxc_uart *const uart = plat->reg;
>
> -   if (readl(>ts) & UTS_TXFULL)
> +   if ((readl(>ts) & UTS_TXFULL) || !(readl(>ts) & 
> UTS_TXEMPTY))
> return -EAGAIN;
>
> writel(ch, >txd);
> --
> 2.25.1
>

Fabio,

This resolves the issue. Why would the kernel not suffer from this as
well? We are essentially saying if the FIFO is not full but also not
empty we need to wait so do we have a FIFO size of 1 or something
here as opposed to the kernel?

Best Regards,

Tim

[PATCH v2] serial: mxc: Keep the original FIFO empty check

[Fabio Estevam]

From: Fabio Estevam 

Tim Harvey reported that since commit c7878a0483c5 ("serial: mxc:
have putc use the TXFIFO"), console messages put inside board_init()
are no longer printed correctly.

This change added a check to handle the UART FIFO full condition and
removed the UART FIFO empty check, which causes the problem.

To avoid console corruption, add back the original UART FIFO empty
check so that when the FIFO is empty, mxc_serial_putc() returns -EAGAIN
to the core serial-uclass.c.

This way the serial core can properly handle the UART empty condition 
by not doing character transmission when -EAGAIN is returned.

Fixes: c7878a0483c5 ("serial: mxc: have putc use the TXFIFO")
Reported-by: Tim Harvey 
Signed-off-by: Fabio Estevam 
---
Changes since v1:
- Add the check for FIFO full and FIFO empty.

 drivers/serial/serial_mxc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4cf79c1ca24f..d3fbe76065ec 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, const char 
ch)
struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;
 
-   if (readl(>ts) & UTS_TXFULL)
+   if ((readl(>ts) & UTS_TXFULL) || !(readl(>ts) & 
UTS_TXEMPTY))
return -EAGAIN;
 
writel(ch, >txd);
-- 
2.25.1

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Fabio Estevam]

Hi Tim,

On 25/10/2022 18:37, Tim Harvey wrote:


Fabio and Pali,

Seems reasonable but this does not resolve the problem. Whatever I
print in board_init gets cutoff by the print from dm_announce.


Should we check for both TXFULL and TXEMPTY conditions?

--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, 
const char ch)

struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;

-   if (readl(>ts) & UTS_TXFULL)
+   if ((readl(>ts) & UTS_TXFULL) || !(readl(>ts) & 
UTS_TXEMPTY))

return -EAGAIN;

writel(ch, >txd);

Re: [PATCH] drivers: pci: pcie_dw_common: add upper-limit to iATU

[Ben Dooks]

On 20/10/2022 17:13, Bin Meng wrote:

Hi Ben,

On Thu, Oct 20, 2022 at 11:51 PM Ben Dooks  wrote:


The 4.6 spec added an upper 32bits to the ATU limit, and since this
driver is already assuming the unrolled feature added in the 4.8
specification this really should be set.

This is causing a bug with testing against the QEMU model as it


I guess you are testing QEMU sifive_u machine with some mods to add a
DW PCIe controller, with U-Boot sifive_unmatched defconfig?

Could you please document the QEMU command line in the commit message?


Your guess is wrong, I'm not currently using the sifive_u. This is a
test projec to test some of the work we've been doing updating the
dw-pcie code for future work.

I'll try and sort out adding this to the sifive_u as an option but I
expect that won't be until next week.

I am wondering whether to add a flag to say use viewport 2 for
the config, as logging from the dw-pcie model is showing a lot of
updates to windows setting, then restoring the IO view and I am
guessing people aren't configuring minimal settings on the Synopsys
designs...


defaults the viewports to fully open and not setting this causes
the config viewport to become most of memory (obviously stopping
the emulated system working correctly)

Signed-off-by: Ben Dooks 
---
  drivers/pci/pcie_dw_common.c | 2 ++
  drivers/pci/pcie_dw_common.h | 1 +
  2 files changed, 3 insertions(+)

diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c
index e66fb1490a..9f8b016d11 100644
--- a/drivers/pci/pcie_dw_common.c
+++ b/drivers/pci/pcie_dw_common.c
@@ -73,6 +73,8 @@ int pcie_dw_prog_outbound_atu_unroll(struct pcie_dw *pci, int 
index,
  upper_32_bits(cpu_addr));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LIMIT,
  lower_32_bits(cpu_addr + size - 1));
+   dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_LIMIT,
+upper_32_bits(cpu_addr + size - 1));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_LOWER_TARGET,
  lower_32_bits(pci_addr));
 dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_UPPER_TARGET,
diff --git a/drivers/pci/pcie_dw_common.h b/drivers/pci/pcie_dw_common.h
index 60bf966d5e..8ec6834fa1 100644
--- a/drivers/pci/pcie_dw_common.h
+++ b/drivers/pci/pcie_dw_common.h
@@ -32,6 +32,7 @@
  #define PCIE_ATU_UNR_LIMIT 0x10
  #define PCIE_ATU_UNR_LOWER_TARGET  0x14
  #define PCIE_ATU_UNR_UPPER_TARGET  0x18
+#define PCIE_ATU_UNR_UPPER_LIMIT   0x20

  #define PCIE_ATU_REGION_INDEX2 (0x2 << 0)
  #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
--


Regards,
Bin

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Fabio Estevam]

Hi Tim,

On 25/10/2022 18:37, Tim Harvey wrote:


Fabio and Pali,

Seems reasonable but this does not resolve the problem. Whatever I
print in board_init gets cutoff by the print from dm_announce.


You are right.

I managed to reproduce it:

--- a/board/warp7/warp7.c
+++ b/board/warp7/warp7.c
@@ -71,6 +71,7 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

+   printf("*** 
0123456789012345678901234567890123456789\n");

return 0;
 }


It does not print correctly:

U-Boot 2022.10-00796-gf9d16f2c0daf-dirty (Oct 25 2022 - 18:46:05 -0300)

CPU:   Freescale i.MX7S rev1.2 800 MHz (running at 792 MHz)
CPU:   Extended Commercial temperature grade (-20C to 105C) at 49C
Reset cause: POR
Model: Element14 Warp i.MX7 Board
Board: WARP7 in secure mode OPTEE DRAM 0x9d00-0xa000
DRAM:  464 MiB
�Core:  73 devices, 17 uclasses, devicetree: separate3456789
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC:   FSL_SDHC: 3, FSL_SDHC: 0
Loading Environment from MMC... OK
In:serial@3086
Out:   serial@3086
Err:   serial@3086
SEC0:  RNG instantiated
Net:   No ethernet found.
Hit any key to stop autoboot:  0

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Pali Rohár]

On Tuesday 25 October 2022 17:37:01 Fabio Estevam wrote:
> Hi Pali,
> 
> On 25/10/2022 17:23, Pali Rohár wrote:
> 
> > Hello! I do not have any MXC hardware but I see there one issue.
> > mxc_serial_putc() function probably should not return -EAGAIN when
> > device is busy. But instead it should wait until it is ready.
> > 
> > Could you try to change code to following?
> > 
> > while (readl(>ts) & UTS_TXFULL)
> > ;
> > 
> > writel(ch, >txd);
> 
> Your analysis looks correct.
> 
> The kernel does like this:
> 
> static void imx_uart_console_putchar(struct uart_port *port, unsigned char
> ch)
> {
>   struct imx_port *sport = (struct imx_port *)port;
> 
>   while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
>   barrier();
> 
>   imx_uart_writel(sport, ch, URTX0);
> }
> 
> Thanks

Well, "waiting for HW to be ready" vs. "returning -EAGAIN" is serial API
detail. Kernel (or other implementation) may have different API and
driver always have to implement what API expects. So aligning return
value with kernel is not the argument for fixing issue.


Anyway, I think that my change is not correct.

serial-uclass.c is already calling:

do {
err = ops->putc(dev, ch);
} while (err == -EAGAIN);

Which means that function is called again.

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Tim Harvey]

On Tue, Oct 25, 2022 at 1:37 PM Fabio Estevam  wrote:
>
> Hi Pali,
>
> On 25/10/2022 17:23, Pali Rohár wrote:
>
> > Hello! I do not have any MXC hardware but I see there one issue.
> > mxc_serial_putc() function probably should not return -EAGAIN when
> > device is busy. But instead it should wait until it is ready.
> >
> > Could you try to change code to following?
> >
> > while (readl(>ts) & UTS_TXFULL)
> > ;
> >
> > writel(ch, >txd);
>
> Your analysis looks correct.
>
> The kernel does like this:
>
> static void imx_uart_console_putchar(struct uart_port *port, unsigned
> char ch)
> {
> struct imx_port *sport = (struct imx_port *)port;
>
> while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
> barrier();
>
> imx_uart_writel(sport, ch, URTX0);
> }
>
> Thanks

Fabio and Pali,

Seems reasonable but this does not resolve the problem. Whatever I
print in board_init gets cutoff by the print from dm_announce.

Tim

[PATCH] serial: mxc: Wait until TX FIFO is not full

[Fabio Estevam]

From: Fabio Estevam 

Tim Harvey reported the console garbage on imx6 since
commit c7878a0483c5 ("serial: mxc: have putc use the TXFIFO").

Do as suggested by Pali Rohár where the the driver should
not return -EAGAIN when the TX FIFO  is full.

It should keep waiting until the TX FIFO is no longer full.

This also aligns with the implementation of the imx serial driver
in the kernel:

static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
{
struct imx_port *sport = (struct imx_port *)port;

while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
barrier();

imx_uart_writel(sport, ch, URTX0);
}

Fixes: c7878a0483c5 ("serial: mxc: have putc use the TXFIFO")
Reported-by: Tim Harvey 
Suggested-by: Pali Rohár 
Signed-off-by: Fabio Estevam 
---
 drivers/serial/serial_mxc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4cf79c1ca24f..332219fa87fc 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -311,8 +311,8 @@ static int mxc_serial_putc(struct udevice *dev, const char 
ch)
struct mxc_serial_plat *plat = dev_get_plat(dev);
struct mxc_uart *const uart = plat->reg;
 
-   if (readl(>ts) & UTS_TXFULL)
-   return -EAGAIN;
+   while (readl(>ts) & UTS_TXFULL)
+   barrier();
 
writel(ch, >txd);
 
-- 
2.25.1

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Fabio Estevam]

Hi Pali,

On 25/10/2022 17:23, Pali Rohár wrote:


Hello! I do not have any MXC hardware but I see there one issue.
mxc_serial_putc() function probably should not return -EAGAIN when
device is busy. But instead it should wait until it is ready.

Could you try to change code to following?

while (readl(>ts) & UTS_TXFULL)
;

writel(ch, >txd);


Your analysis looks correct.

The kernel does like this:

static void imx_uart_console_putchar(struct uart_port *port, unsigned 
char ch)

{
struct imx_port *sport = (struct imx_port *)port;

while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
barrier();

imx_uart_writel(sport, ch, URTX0);
}

Thanks

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Pali Rohár]

On Tuesday 25 October 2022 12:18:56 Tim Harvey wrote:
> On Tue, Sep 6, 2022 at 5:15 AM Johannes Schneider
>  wrote:
> >
> > only waiting for TXEMPTY leads to corrupted messages going over the
> > wire - which is fixed by making use of the FIFO
> >
> > this change is following the linux kernel uart driver
> > (drivers/tty/serial/imx.c), which also checks UTS_TXFULL
> > instead of UTS_TXEMPTY
> >
> > Signed-off-by: Johannes Schneider 
> > Reviewed-by: Peng Fan 
> > Reviewed-by: Fabio Estevam 
> > ---
> >
> > (no changes since v1)
> >
> >  drivers/serial/serial_mxc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> > index ee17a960d4..af1fd1ea9b 100644
> > --- a/drivers/serial/serial_mxc.c
> > +++ b/drivers/serial/serial_mxc.c
> > @@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, const 
> > char ch)
> > struct mxc_serial_plat *plat = dev_get_plat(dev);
> > struct mxc_uart *const uart = plat->reg;
> >
> > -   if (!(readl(>ts) & UTS_TXEMPTY))
> > +   if (readl(>ts) & UTS_TXFULL)
> > return -EAGAIN;
> >
> > writel(ch, >txd);
> > --
> > 2.25.1
> >
> 
> Johannes,
> 
> Since this patch I find an issue with an IMX6 board of mine gwventana:
> 
> Prior to this patch the board boots with:
> DRAM:  1 GiB
> GSCv2   : v52 0x9981 RST:VIN WDT:disabled board_temp:43C
> RTC : 1970-01-01   0:56:15 UTC
> Core:  67 devices, 22 uclasses, devicetree: separate
> WDT:   Started watchdog@20bc000 with servicing every 1000ms (60s timeout)
> NAND:  2048 MiB
> ...
> 
> and following this patch I get:
> ...
> DRAM:  1 GiB
> GSCv2   : v52 0x9981 RST:VIN WDT:disabled board_temp:29C
> RTC : 1970-01-01   ~�KW�'$H�$V�W��Y.KH�� uclasses, devicetree: separate
> WDT:   Started watchdog@20bc000 with servicing every 1000ms (60s timeout)
> NAND:  2048 MiB
> ...
> 
> The RTC line is displayed from drivers/misc/gsc.c and the Core: comes
> from dm_announce. Somehow in between the FIFO does not get drained
> before dm_announce gets called.
> 
> Adding a delay after the RTC print or reverting this patch.
> 
> Any ideas?
> 
> Best Regards,
> 
> Tim

Hello! I do not have any MXC hardware but I see there one issue.
mxc_serial_putc() function probably should not return -EAGAIN when
device is busy. But instead it should wait until it is ready.

Could you try to change code to following?

while (readl(>ts) & UTS_TXFULL)
;

writel(ch, >txd);

Re: [PATCH v2 1/4] riscv: dts: Update memory configuration

[Conor.Dooley]

On 22/10/2022 12:21, Conor Dooley wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the 
> content is safe
> 
> On Fri, Oct 21, 2022 at 12:29:19PM +0530, Padmarao Begari wrote:
>> In the v2022.10 Icicle reference design, the seg registers are going to be
> 
> Hey Padmarao,
> Since the release was done the other day I think that this should be
> s/are going to be/have been
> 
>> changed, resulting in a required change to the memory map.
>> A small 4MB reservation is made at the end of 32-bit DDR to provide some
>> memory for the HSS to use, so that it can cache its payload between
>> reboots of a specific context.
>>
>> Co-developed-by: Conor Dooley 
>> Signed-off-by: Conor Dooley 
>> Signed-off-by: Padmarao Begari 
>> Reviewed-by: Conor Dooley 
>> ---
>>  arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 70 
>>  1 file changed, 14 insertions(+), 56 deletions(-)
>>
>> diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts 
>> b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> index 287ef3d23b..876c475069 100644
>> --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> +++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
>> @@ -1,6 +1,6 @@
>>  // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>  /*
>> - * Copyright (C) 2021 Microchip Technology Inc.
>> + * Copyright (C) 2021-2022 Microchip Technology Inc.
>>   * Padmarao Begari 
>>   */
>>
>> @@ -28,70 +28,28 @@
>>   timebase-frequency = ;
>>   };
> 
> FWIW I think we should add the compatible that the linux dt has,
> signifying that this memory layout is compatible with the v2022.10
> release and later (w/ appropriate line-wrapping ofc):
> compatible = "microchip,mpfs-icicle-reference-rtlv2210", 
> "microchip,mpfs-icicle-kit", "microchip,mpfs";
> 
> Other than that:
> Reviewed-by: Conor Dooley 
> 
>>
>> - reserved-memory {
>> - ranges;
>> - #size-cells = <2>;
>> - #address-cells = <2>;
>> -
>> - fabricbuf0: fabricbuf@0 {
>> - compatible = "shared-dma-pool";
>> - reg = <0x0 0xae00 0x0 0x200>;
>> - label = "fabricbuf0-ddr-c";
>> - };
>> -
>> - fabricbuf1: fabricbuf@1 {
>> - compatible = "shared-dma-pool";
>> - reg = <0x0 0xc000 0x0 0x800>;
>> - label = "fabricbuf1-ddr-nc";
>> - };
>> -
>> - fabricbuf2: fabricbuf@2 {
>> - compatible = "shared-dma-pool";
>> - reg = <0x0 0xd800 0x0 0x800>;
>> - label = "fabricbuf2-ddr-nc-wcb";
>> - };
>> - };
>> -
>> - udmabuf0 {
>> - compatible = "ikwzm,u-dma-buf";
>> - device-name = "udmabuf-ddr-c0";
>> - minor-number = <0>;
>> - size = <0x0 0x200>;
>> - memory-region = <>;
>> - sync-mode = <3>;
>> - };
>> -
>> - udmabuf1 {
>> - compatible = "ikwzm,u-dma-buf";
>> - device-name = "udmabuf-ddr-nc0";
>> - minor-number = <1>;
>> - size = <0x0 0x800>;
>> - memory-region = <>;
>> - sync-mode = <3>;
>> - };
>> -
>> - udmabuf2 {
>> - compatible = "ikwzm,u-dma-buf";
>> - device-name = "udmabuf-ddr-nc-wcb0";
>> - minor-number = <2>;
>> - size = <0x0 0x800>;
>> - memory-region = <>;
>> - sync-mode = <3>;
>> - };
>> -
>>   ddrc_cache_lo: memory@8000 {
>>   device_type = "memory";
>> - reg = <0x0 0x8000 0x0 0x2e00>;
>> - clocks = < CLK_DDRC>;
>> + reg = <0x0 0x8000 0x0 0x4000>;
>>   status = "okay";
>>   };
>>
>>   ddrc_cache_hi: memory@10 {

Sorry for not noticing prior, but this should bee changed too to match
the reg property shouldn't it..

>>   device_type = "memory";
>> - reg = <0x10 0x0 0x0 0x4000>;
>> - clocks = < CLK_DDRC>;
>> + reg = <0x10 0x4000 0x0 0x4000>;
>>   status = "okay";
>>   };
>> +
>> + reserved-memory {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + hss_payload: region@BFC0 {
>> + reg = <0x0 0xBFC0 0x0 0x40>;
>> + no-map;
>> + };
>> + };
>>  };
>>
>>   {
>> --
>> 2.25.1
>>

Re: [PATCH v5 2/2] serial: mxc: have putc use the TXFIFO

[Tim Harvey]

On Tue, Sep 6, 2022 at 5:15 AM Johannes Schneider
 wrote:
>
> only waiting for TXEMPTY leads to corrupted messages going over the
> wire - which is fixed by making use of the FIFO
>
> this change is following the linux kernel uart driver
> (drivers/tty/serial/imx.c), which also checks UTS_TXFULL
> instead of UTS_TXEMPTY
>
> Signed-off-by: Johannes Schneider 
> Reviewed-by: Peng Fan 
> Reviewed-by: Fabio Estevam 
> ---
>
> (no changes since v1)
>
>  drivers/serial/serial_mxc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index ee17a960d4..af1fd1ea9b 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -311,7 +311,7 @@ static int mxc_serial_putc(struct udevice *dev, const 
> char ch)
> struct mxc_serial_plat *plat = dev_get_plat(dev);
> struct mxc_uart *const uart = plat->reg;
>
> -   if (!(readl(>ts) & UTS_TXEMPTY))
> +   if (readl(>ts) & UTS_TXFULL)
> return -EAGAIN;
>
> writel(ch, >txd);
> --
> 2.25.1
>

Johannes,

Since this patch I find an issue with an IMX6 board of mine gwventana:

Prior to this patch the board boots with:
DRAM:  1 GiB
GSCv2   : v52 0x9981 RST:VIN WDT:disabled board_temp:43C
RTC : 1970-01-01   0:56:15 UTC
Core:  67 devices, 22 uclasses, devicetree: separate
WDT:   Started watchdog@20bc000 with servicing every 1000ms (60s timeout)
NAND:  2048 MiB
...

and following this patch I get:
...
DRAM:  1 GiB
GSCv2   : v52 0x9981 RST:VIN WDT:disabled board_temp:29C
RTC : 1970-01-01   ~�KW�'$H�$V�W��Y.KH�� uclasses, devicetree: separate
WDT:   Started watchdog@20bc000 with servicing every 1000ms (60s timeout)
NAND:  2048 MiB
...

The RTC line is displayed from drivers/misc/gsc.c and the Core: comes
from dm_announce. Somehow in between the FIFO does not get drained
before dm_announce gets called.

Adding a delay after the RTC print or reverting this patch.

Any ideas?

Best Regards,

Tim

Re: [PATCH v4 3/6] efi_loader: Add SPI I/O protocol support

[Tom Rini]

On Tue, Oct 25, 2022 at 05:39:48PM +0100, Paul Barker wrote:
> Hi Ilias,
> 
> On 24/10/2022 12:54, Ilias Apalodimas wrote:
> > Hi Paul, 
> > 
> > I think the series overall is in a good state,  but we are trying to figure
> > out if we can avoid defining SPI uuid's in the DT.  OTOH U-Boot uses the DT
> > for it's config so that might be okay...
> 
> What may make sense is to prefix the DT property names with `u-boot,`.
> i.e. they'd become:
> 
> * u-boot,uefi-spi-vendor
> * u-boot,uefi-spi-part-number
> * u-boot,uefi-spi-io-guid

Note that this still means updating the upstream yaml file that
describes the binding.

-- 
Tom


signature.asc
Description: PGP signature

arm: hello_world example application not working on RPI1

[Patrick Zacharias]

Hello,

I tried getting examples/standalone/hello_world to run as of
1e892ef0b59a4a04971ac23619b95917020b3e18

I installed the Ubuntu (20.04 LTS) ARM toolchain (I tried it with a
Linaro toolchain as well) and built the source code using

"make rpi_defconfig"

Afterwards, I used menuconfig to enable the build of the examples.

I created a boot.scr file using following script:

"fatload mmc 0:1 $loadaddr /uEnv.txt
env import -t $loadaddr $filesize
run bootcmd"

and converted it using mkimage.

The content of the uEnv.txt is as following:

"bootcmd=mmc rescan; echo Test ${loadaddr} end; load mmc 0:1 0x0c10
hello_world.bin; go 0x0c10"

I copied u-boot.bin, boot.scr and uEnv.txt to the SD card (over the
existing parition created by Raspbian). And adjusted the config.txt to read:

"kernel=u-boot.bin"

U-Boot shows up, however after the program loaded (and go is executed),
the Raspberry Pi freezes.

I tried this with tftp as well and with and without ELF files (using
"bootelf"). The result remains the same.

Booting the EFI applications using "bootefi" works.

Additionally, when trying to build U-Boot using clang-12, I ran into two
errors.

The first one was in arch/arm/lib/relocate.S,
where it complains about the symbol "relocate_vectors" first being
declared as weak, then again as global.

"error: relocate_vectors changed binding to STB_GLOBAL"

To fix this, I removed the .weak line and renamed ENTRY to WEAK.

Afterwards, U-Boot itself built, but the hello_world application didn't
find any of the exported functions. (EXPORT_FUNC is probably just a stub
for clang?)

Greetings,
Patrick

[PATCH] riscv: Rename Andes PLIC to PLICSW

[Yu Chien Peter Lin]

As PLICSW is used to trigger the software interrupt, we should rename
Andes PLIC configuration and file name to reflect the usage. This patch
also updates PLMT and PLICSW compatible strings to be consistent with
OpenSBI fdt driver.

Signed-off-by: Yu Chien Peter Lin 
---
 arch/riscv/Kconfig|  6 ++---
 arch/riscv/cpu/ax25/Kconfig   |  2 +-
 arch/riscv/dts/ae350-u-boot.dtsi  |  2 +-
 arch/riscv/dts/ae350_32.dts   |  6 ++---
 arch/riscv/dts/ae350_64.dts   |  6 ++---
 arch/riscv/include/asm/global_data.h  |  4 +--
 arch/riscv/include/asm/syscon.h   |  2 +-
 arch/riscv/lib/Makefile   |  2 +-
 .../lib/{andes_plic.c => andes_plicsw.c}  | 26 +--
 9 files changed, 28 insertions(+), 28 deletions(-)
 rename arch/riscv/lib/{andes_plic.c => andes_plicsw.c} (76%)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 8f9578171d..4d64e9be3f 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -199,7 +199,7 @@ config SIFIVE_CACHE
help
  This enables the operations to configure SiFive cache
 
-config ANDES_PLIC
+config ANDES_PLICSW
bool
depends on RISCV_MMODE || SPL_RISCV_MMODE
select REGMAP
@@ -207,8 +207,8 @@ config ANDES_PLIC
select SPL_REGMAP if SPL
select SPL_SYSCON if SPL
help
- The Andes PLIC block holds memory-mapped claim and pending registers
- associated with software interrupt.
+ The Andes PLICSW block holds memory-mapped claim and pending
+ registers associated with software interrupt.
 
 config SMP
bool "Symmetric Multi-Processing"
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 941d963ece..4a7295d30c 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -4,7 +4,7 @@ config RISCV_NDS
imply CPU
imply CPU_RISCV
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
-   imply ANDES_PLIC if (RISCV_MMODE || SPL_RISCV_MMODE)
+   imply ANDES_PLICSW if (RISCV_MMODE || SPL_RISCV_MMODE)
imply ANDES_PLMT_TIMER if (RISCV_MMODE || SPL_RISCV_MMODE)
imply SPL_CPU
imply SPL_OPENSBI
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index 0d4201cfae..7011f59831 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -36,7 +36,7 @@
soc {
u-boot,dm-spl;
 
-   plic1: interrupt-controller@e640 {
+   plicsw: interrupt-controller@e640 {
u-boot,dm-spl;
};
 
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 083f676333..96ef8bd8dd 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -146,8 +146,8 @@
_intc 11 _intc 9>;
};
 
-   plic1: interrupt-controller@e640 {
-   compatible = "riscv,plic1";
+   plicsw: interrupt-controller@e640 {
+   compatible = "andestech,plicsw";
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe640 0x40>;
@@ -159,7 +159,7 @@
};
 
plmt0@e600 {
-   compatible = "riscv,plmt0";
+   compatible = "andestech,plmt0";
interrupts-extended = <_intc 7
_intc 7
_intc 7
diff --git a/arch/riscv/dts/ae350_64.dts b/arch/riscv/dts/ae350_64.dts
index 74cff9122d..cddbaec98a 100644
--- a/arch/riscv/dts/ae350_64.dts
+++ b/arch/riscv/dts/ae350_64.dts
@@ -146,8 +146,8 @@
_intc 11 _intc 9>;
};
 
-   plic1: interrupt-controller@e640 {
-   compatible = "riscv,plic1";
+   plicsw: interrupt-controller@e640 {
+   compatible = "andestech,plicsw";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe640 0x0 0x40>;
@@ -159,7 +159,7 @@
};
 
plmt0@e600 {
-   compatible = "riscv,plmt0";
+   compatible = "andestech,plmt0";
interrupts-extended = <_intc 7
_intc 7
_intc 7
diff --git a/arch/riscv/include/asm/global_data.h 
b/arch/riscv/include/asm/global_data.h
index 858594a191..6fdc86dd8b 100644
--- a/arch/riscv/include/asm/global_data.h
+++ b/arch/riscv/include/asm/global_data.h
@@ -21,8 +21,8 @@ struct arch_global_data {
 #if CONFIG_IS_ENABLED(SIFIVE_CLINT)
void __iomem *clint;/* clint base address */
 #endif
-#ifdef CONFIG_ANDES_PLIC
- 

[PATCH] arm64: dts: meson: nanopi-k2: readd PHY reset properties

[Christian Hewitt]

The sync of device-tree/bindings in 11a48a5a18c6 ("Linux 5.6-rc2") causes
Ethernet to break on some GXBB boards; the PHY seems to need proper reset
timing to function in u-boot and Linux. Re-add the old PHY reset binding
for dwmac until we support new bindings in the PHY node. This borrows the
same fix applied to the Odroid C2 board [0].

[0] https://lists.denx.de/pipermail/u-boot/2021-April/446658.html

Fixes: dd5f2351e99a ("arm64: dts: meson: sync dt and bindings from v5.6-rc2")
Signed-off-by: Christian Hewitt 
---
 arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi 
b/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi
index c35158d7e9..2a245bbe7f 100644
--- a/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi
+++ b/arch/arm/dts/meson-gxbb-nanopi-k2-u-boot.dtsi
@@ -5,3 +5,10 @@
  */
 
 #include "meson-gx-u-boot.dtsi"
+
+ {
+   snps,reset-gpio = < GPIOZ_14 0>;
+   snps,reset-delays-us = <0 1 100>;
+   snps,reset-active-low;
+};
+
-- 
2.17.1

Re: [PATCH v4 3/6] efi_loader: Add SPI I/O protocol support

[Paul Barker]

Hi Ilias,

On 24/10/2022 12:54, Ilias Apalodimas wrote:
> Hi Paul, 
> 
> I think the series overall is in a good state,  but we are trying to figure
> out if we can avoid defining SPI uuid's in the DT.  OTOH U-Boot uses the DT
> for it's config so that might be okay...

What may make sense is to prefix the DT property names with `u-boot,`.
i.e. they'd become:

* u-boot,uefi-spi-vendor
* u-boot,uefi-spi-part-number
* u-boot,uefi-spi-io-guid

For the sandbox tests it makes sense to keep the configuration in
arch/sandbox/dts/test.dts. However for a real device such as the
SanCloud BBE it makes sense to keep the dts file in line with the Linux
kernel dts file and add the configuration to a new file
arch/arm/dts/am335x-sancloud-bbe-lite-u-boot.dtsi which will be picked
up by the build system. That keeps the configuration separate from the
upstream dts file and matches what we do for properties like
`u-boot,dm-spl`.

Does that sound like a good way forward?

> 
> [...]
> 
>> +{
>> +struct efi_spi_peripheral *peripheral = bus->peripheral_list;
>> +
>> +while (peripheral) {
>> +struct efi_spi_peripheral *next =
>> +peripheral->next_spi_peripheral;
>> +destroy_efi_spi_peripheral(peripheral);
>> +peripheral = next;
>> +}
>> +free(bus->friendly_name);
>> +free(bus);
>> +}
>> +
>> +static efi_status_t efi_spi_new_handle(const efi_guid_t *guid, void *proto)
>> +{
>> +efi_status_t status;
>> +efi_handle_t handle;
>> +
>> +status = efi_create_handle();
>> +if (status != EFI_SUCCESS) {
>> +printf("Failed to create EFI handle\n");
>> +goto fail_1;
>> +}
>> +
>> +status = efi_add_protocol(handle, guid, proto);
> 
> Apologies for this it's my fault,  but can you replace efi_add_protocol ->
> efi_install_multiple_protocol_interfaces?
> commit 05c4c9e21ae6 ("efi_loader: define internal implementations of 
> install/uninstallmultiple")
> has some details on why.  A bit annoying but the change is straightforward

I'll change this for v5.

> 
>> +if (status != EFI_SUCCESS) {
>> +printf("Failed to add protocol\n");
>> +goto fail_2;
>> +}
>> +
>> +return EFI_SUCCESS;
>> +
>> +fail_2:
>> +efi_delete_handle(handle);
> 
> Same here, just uninstall the protocol

As above.

> 
>> +fail_1:
>> +return status;
>> +}
>> +
>> +static void
>> +efi_spi_init_part(struct efi_spi_part *part,
>> +  struct spi_slave *target,
>> +  efi_string_t vendor_utf16,
>> +  efi_string_t part_number_utf16
>> +)
>> +{
>> +part->vendor = vendor_utf16;
>> +part->part_number = part_number_utf16;
>> +part->min_clock_hz = 0;
>> +part->max_clock_hz = target->max_hz;
>> +part->chip_select_polarity =
>> +(target->mode & SPI_CS_HIGH) ? true : false;
>> +}
>> +
>  
> 
> Thanks!
> /Ilias

Thanks,

-- 
Paul Barker
Principal Software Engineer
SanCloud Ltd

e: paul.bar...@sancloud.com
w: https://sancloud.com/

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imx8 regression: cyclic_register for watchdog@30280000 failed

[Tim Harvey]

Greetings,

I've noticed a regression since the merge of the cyclic framework use
for watchdog on my imx8m boards:

cyclic_register for watchdog@3028 failed
WDT:   Failed to start watchdog@3028

A bisect lead me to the following 3 sequential patches:
29caf9305b6f cyclic: Use schedule() instead of WATCHDOG_RESET()
^^^ bad
881d4108257a cyclic: Introduce schedule() function
^^^ unbuildable
c2fd0ca1a822 watchdog: Integrate watchdog triggering into the cyclic framework
^^^ unbootable

Before I did in much deeper has anyone else run into and/or resolved
this? I'm wondering if something is missing from defconfig?

Best Regards,

Tim

Re: Pull request: u-boot-spi/master

[Tom Rini]

On Tue, Oct 25, 2022 at 05:56:18PM +0530, Jagan Teki wrote:

> Hi Tom,
> 
> Please pull this PR.
> 
> Summary:
> - Add s28hl512t, s28hl01gt (Takahiro)
> - Rework s25hx_t_post_bfpt_fixup() (Takahiro)
> 
> CI:
> https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/13925
> 
> thanks,
> Jagan.
> 
> The following changes since commit 7723828c97bc107d2fba976fc50403ac8747f1bc:
> 
>   Merge branch '2022-10-21-enforce-some-DM-migrations' (2022-10-21 15:32:45 
> -0400)
> 
> are available in the Git repository at:
> 
>   https://source.denx.de/u-boot/custodians/u-boot-spi.git master
> 
> for you to fetch changes up to 622b5d356136f9172db7fe7ba240cd9e45097a19:
> 
>   cmd: sf: Handle unaligned 'update' start offset (2022-10-25 10:17:33 +0530)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v5] imx: imx8qm: cgtqmx8: switch to binman

[Fabio Estevam]

Hi Oliver,

On Tue, Oct 25, 2022 at 12:31 PM Oliver Graute  wrote:

> Now Running into this issue:
>
>   MKIMAGE u-boot.img
>   MKIMAGE u-boot-dtb.img
>   LD  u-boot.elf
> make[1]: Für das Ziel „SPL“ ist nichts zu tun.
>   BINMAN  all
> binman: Section '/binman/u-boot-spl-ddr': Symbol 
> '_binman_u_boot_any_prop_image_pos'
>in entry '/binman/u-boot-spl-ddr/u-boot-spl/u-boot-spl-nodtb': Entry 
> 'u-boot-any' not found in list 
> (u-boot-spl-nodtb,u-boot-spl-dtb,u-boot-spl,main-section)
> Makefile:1109: recipe for target 'all' failed
> make: *** [all] Error 1
>
> some hints?

I suggest sending the two patches as a series: 1/2 and 2/2 as it is
easier to review.

Looks like you missed passing @fdt-SEQ like it is done on
arch/arm/dts/imx8mm-u-boot.dtsi.

Re: [PATCH 1/3] imx: imx8mm_beacon: Eliminate a few extras to free up SPL space

[Tim Harvey]

On Mon, Oct 24, 2022 at 6:29 PM Peng Fan  wrote:
>
>
>
> On 10/25/2022 4:47 AM, Tim Harvey wrote:
> > On Mon, Oct 24, 2022 at 1:26 PM Adam Ford  wrote:
> >>
> >> On Mon, Oct 24, 2022 at 2:57 PM Tim Harvey  wrote:
> >>>
> >>> On Sat, Oct 22, 2022 at 7:28 AM Adam Ford  wrote:
> 
>  There are a few functions which are not essential for use in
>  SPL, but they take up enough space to make other preferred
>  features not fit.  Remove the extras.
> 
>  Signed-off-by: Adam Ford 
> 
>  diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c
>  index a93cc93878..b0e9d918da 100644
>  --- a/board/beacon/imx8mm/spl.c
>  +++ b/board/beacon/imx8mm/spl.c
>  @@ -44,11 +44,6 @@ static void spl_dram_init(void)
>   ddr_init(_timing);
>    }
> 
>  -void spl_board_init(void)
>  -{
>  -   debug("Normal Boot\n");
>  -}
>  -
>    #ifdef CONFIG_SPL_LOAD_FIT
>    int board_fit_config_name_match(const char *name)
>    {
>  diff --git a/configs/imx8mm_beacon_defconfig 
>  b/configs/imx8mm_beacon_defconfig
>  index e37ce01c19..f6a1012d8a 100644
>  --- a/configs/imx8mm_beacon_defconfig
>  +++ b/configs/imx8mm_beacon_defconfig
>  @@ -29,7 +29,6 @@ CONFIG_DEFAULT_FDT_FILE="imx8mm-beacon-kit.dtb"
>    CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
>    CONFIG_SPL_BSS_START_ADDR=0x91
>    CONFIG_SPL_BSS_MAX_SIZE=0x2000
>  -CONFIG_SPL_BOARD_INIT=y
>    # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
>    CONFIG_SPL_STACK=0x92
>    CONFIG_SYS_SPL_MALLOC=y
>  @@ -88,12 +87,9 @@ CONFIG_DM_PCA953X=y
>    CONFIG_DM_I2C=y
>    CONFIG_SUPPORT_EMMC_BOOT=y
>    CONFIG_MMC_IO_VOLTAGE=y
>  -CONFIG_SPL_MMC_IO_VOLTAGE=y
>    CONFIG_MMC_UHS_SUPPORT=y
>  -CONFIG_SPL_MMC_UHS_SUPPORT=y
>    CONFIG_MMC_HS400_ES_SUPPORT=y
>    CONFIG_MMC_HS400_SUPPORT=y
>  -CONFIG_SPL_MMC_HS400_SUPPORT=y
>    CONFIG_FSL_USDHC=y
>    CONFIG_MTD=y
>    CONFIG_DM_MTD=y
>  @@ -113,14 +109,12 @@ CONFIG_PINCTRL_IMX8M=y
>    CONFIG_POWER_DOMAIN=y
>    CONFIG_IMX8M_POWER_DOMAIN=y
>    CONFIG_DM_PMIC=y
>  +# CONFIG_SPL_PMIC_CHILDREN is not set
>    CONFIG_DM_PMIC_BD71837=y
>    CONFIG_SPL_DM_PMIC_BD71837=y
>    CONFIG_DM_REGULATOR=y
>  -CONFIG_SPL_DM_REGULATOR=y
>    CONFIG_DM_REGULATOR_BD71837=y
>  -CONFIG_SPL_DM_REGULATOR_BD71837=y
>    CONFIG_DM_REGULATOR_FIXED=y
>  -CONFIG_SPL_DM_REGULATOR_FIXED=y
>    CONFIG_DM_REGULATOR_GPIO=y
>    CONFIG_DM_SERIAL=y
>    CONFIG_MXC_UART=y
>  --
>  2.34.1
> 
> >>>
> >>> Adam,
> >>>
> >>> I'm looking at your patches as I'm also trying to strip down the
> >>> imx8mm-venice SPL so that I can fit DM USB support. It seems that
> >>> all/most of the imx8m boards have a spl_board_init() which calls
> >>> arch_misc_init(). I'm curious why your not calling that function?
> >>
> >> As of right now, we're not using the CAAM which is initialized in
> >> arch_misc_init.  If/When we do, we'll likely have to pull that in.
> >>
> >
> > ok - makes sense.
> >
> >>>
> >>> Another config that I've found to save a lot of space for imx8m
> >>> without any negative impact I can see is CONFIG_SPL_MMC_TINY=y
> >>
> >> I experimented a bit with that too, but I hadn't fully tested
> >> switching between booting between MMC1 and MMC2, so I wasn't quite
> >> ready to enable it, but I'll spend some more time with it to see how
> >> much more space I can shave off SPL.
> >> Getting rid of the PMIC children in SPL helped me quite a bit.
> >
> > I see. It appears to save about 2K and Fabio's imx8mm clk reduction
> > series that made it in saves another 800 bytes or so.
> >
> > Regardless I'm still oversize for imx8mm-venice by 2K bytes and
> > looking for things to prune. My issue is that I have 4 DRAM configs to
> > support which suck up 3K each I believe.
>
> Why has so many DRAM configs? Use one image to support multiple boards?
>
> Regards,
> Peng.
>

Peng,

Yes, imx8mm_venice_defconfig covers 6 different dtbs and 4 different
DRAM configs (512MiB, 1GiB, 2GiB, 4GiB) which bloats the SPL to the
point that I can't add SDP support... specifically DM USB.

Tim

Re: [PATCH v5] imx: imx8qm: cgtqmx8: switch to binman

[Oliver Graute]

On 25/10/22, Oliver Graute wrote:
> Switch to use binman to pack images
> 
> Signed-off-by: Oliver Graute 
> Reviewed-by: Fabio Estevam 
> Reviewed-by: Simon Glass 

I missed 

Reviewed-by: Peng Fan 
> 
> ---
> Changes for v5
>  - added CONFIG_FIT_EXTERNAL_OFFSET
> 
> Changes for v4
>  - rebased on master
> 
> Changes for v3
>  -added Reviewed-by
>  - rebased on master
> 
>  arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
>  arch/arm/mach-imx/imx8/Kconfig  | 1 +
>  board/congatec/cgtqmx8/imximage.cfg | 4 ++--
>  configs/cgtqmx8_defconfig   | 3 ++-
>  doc/board/congatec/cgtqmx8.rst  | 3 +--
>  5 files changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
> index 555c357f6f..919d00644f 100644
> --- a/arch/arm/dts/imx8qm-cgtqmx8.dts
> +++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
> @@ -12,6 +12,7 @@
>  /memreserve/ 0x8000 0x0002;
>  
>  #include "fsl-imx8qm.dtsi"
> +#include "imx8qm-u-boot.dtsi"
>  
>  / {
>   model = "Congatec QMX8 Qseven series";
> diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
> index ba2a38c7f7..a0036a32b5 100644
> --- a/arch/arm/mach-imx/imx8/Kconfig
> +++ b/arch/arm/mach-imx/imx8/Kconfig
> @@ -76,6 +76,7 @@ config TARGET_IMX8QM_MEK
>  
>  config TARGET_CONGA_QMX8
>   bool "Support congatec conga-QMX8 board"
> + select BINMAN
>   select BOARD_LATE_INIT
>   select SUPPORT_SPL
>   select IMX8QM
> diff --git a/board/congatec/cgtqmx8/imximage.cfg 
> b/board/congatec/cgtqmx8/imximage.cfg
> index 5ecde0c530..43035088e3 100644
> --- a/board/congatec/cgtqmx8/imximage.cfg
> +++ b/board/congatec/cgtqmx8/imximage.cfg
> @@ -4,8 +4,8 @@
>   */
>  
>  
> -/* Boot from SD, sector size 0x400 */
> -BOOT_FROM SD 0x400
> +BOOT_FROMsd
> +
>  /* SoC type IMX8QM */
>  SOC_TYPE IMX8QM
>  /* Append seco container image */
> diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
> index ddc65a06b9..fb43de624b 100644
> --- a/configs/cgtqmx8_defconfig
> +++ b/configs/cgtqmx8_defconfig
> @@ -20,8 +20,9 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
>  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
>  CONFIG_REMAKE_ELF=y
>  CONFIG_FIT=y
> +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
>  CONFIG_SPL_LOAD_FIT=y
> -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
> +# CONFIG_USE_SPL_FIT_GENERATOR is not set
>  CONFIG_OF_BOARD_SETUP=y
>  CONFIG_BOOTDELAY=3
>  CONFIG_USE_BOOTCOMMAND=y
> diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst
> index bccdef2f16..16711a844d 100644
> --- a/doc/board/congatec/cgtqmx8.rst
> +++ b/doc/board/congatec/cgtqmx8.rst
> @@ -57,8 +57,7 @@ Build U-Boot
>   $ export ATF_LOAD_ADDR=0x8000
>   $ export BL33_LOAD_ADDR=0x8002
>   $ make cgtqmx8_defconfig
> - $ make u-boot.bin
> - $ make flash.bin
> + $ make
>  
>  Flash the binary into the SD card
>  -
> -- 
> 2.17.1
> 

Now Running into this issue:

  MKIMAGE u-boot.img
  MKIMAGE u-boot-dtb.img
  LD  u-boot.elf
make[1]: Für das Ziel „SPL“ ist nichts zu tun.
  BINMAN  all
binman: Section '/binman/u-boot-spl-ddr': Symbol 
'_binman_u_boot_any_prop_image_pos'
   in entry '/binman/u-boot-spl-ddr/u-boot-spl/u-boot-spl-nodtb': Entry 
'u-boot-any' not found in list 
(u-boot-spl-nodtb,u-boot-spl-dtb,u-boot-spl,main-section)
Makefile:1109: recipe for target 'all' failed
make: *** [all] Error 1

some hints?

Best Regards,

Oliver

[PATCH v5] imx: imx8qm: cgtqmx8: switch to binman

[Oliver Graute]

Switch to use binman to pack images

Signed-off-by: Oliver Graute 
Reviewed-by: Fabio Estevam 
Reviewed-by: Simon Glass 

---
Changes for v5
 - added CONFIG_FIT_EXTERNAL_OFFSET

Changes for v4
 - rebased on master

Changes for v3
 -added Reviewed-by
 - rebased on master

 arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
 arch/arm/mach-imx/imx8/Kconfig  | 1 +
 board/congatec/cgtqmx8/imximage.cfg | 4 ++--
 configs/cgtqmx8_defconfig   | 3 ++-
 doc/board/congatec/cgtqmx8.rst  | 3 +--
 5 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/arm/dts/imx8qm-cgtqmx8.dts b/arch/arm/dts/imx8qm-cgtqmx8.dts
index 555c357f6f..919d00644f 100644
--- a/arch/arm/dts/imx8qm-cgtqmx8.dts
+++ b/arch/arm/dts/imx8qm-cgtqmx8.dts
@@ -12,6 +12,7 @@
 /memreserve/ 0x8000 0x0002;
 
 #include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
 
 / {
model = "Congatec QMX8 Qseven series";
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index ba2a38c7f7..a0036a32b5 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -76,6 +76,7 @@ config TARGET_IMX8QM_MEK
 
 config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
+   select BINMAN
select BOARD_LATE_INIT
select SUPPORT_SPL
select IMX8QM
diff --git a/board/congatec/cgtqmx8/imximage.cfg 
b/board/congatec/cgtqmx8/imximage.cfg
index 5ecde0c530..43035088e3 100644
--- a/board/congatec/cgtqmx8/imximage.cfg
+++ b/board/congatec/cgtqmx8/imximage.cfg
@@ -4,8 +4,8 @@
  */
 
 
-/* Boot from SD, sector size 0x400 */
-BOOT_FROM SD 0x400
+BOOT_FROM  sd
+
 /* SoC type IMX8QM */
 SOC_TYPE IMX8QM
 /* Append seco container image */
diff --git a/configs/cgtqmx8_defconfig b/configs/cgtqmx8_defconfig
index ddc65a06b9..fb43de624b 100644
--- a/configs/cgtqmx8_defconfig
+++ b/configs/cgtqmx8_defconfig
@@ -20,8 +20,9 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
 CONFIG_REMAKE_ELF=y
 CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_BOOTDELAY=3
 CONFIG_USE_BOOTCOMMAND=y
diff --git a/doc/board/congatec/cgtqmx8.rst b/doc/board/congatec/cgtqmx8.rst
index bccdef2f16..16711a844d 100644
--- a/doc/board/congatec/cgtqmx8.rst
+++ b/doc/board/congatec/cgtqmx8.rst
@@ -57,8 +57,7 @@ Build U-Boot
  $ export ATF_LOAD_ADDR=0x8000
  $ export BL33_LOAD_ADDR=0x8002
  $ make cgtqmx8_defconfig
- $ make u-boot.bin
- $ make flash.bin
+ $ make
 
 Flash the binary into the SD card
 -
-- 
2.17.1

[PATCH v4] imx: imx8qm-rom7720: switch to binman

[Oliver Graute]

Switch to use binman to pack images

Signed-off-by: Oliver Graute 
---
Changes for v4
 - remove hardcoded dtb filename
 - added CONFIG_FIT_EXTERNAL_OFFSET

Changes for v3
 - just rebased to master

Changes for v2
 - just rebased to master

 arch/arm/dts/imx8qm-rom7720-a1.dts|   1 +
 arch/arm/dts/imx8qm-u-boot.dtsi   | 131 ++
 arch/arm/mach-imx/imx8/Kconfig|   1 +
 .../advantech/imx8qm_rom7720_a1/imximage.cfg  |   4 +-
 configs/imx8qm_rom7720_a1_4G_defconfig|   3 +-
 doc/board/advantech/imx8qm-rom7720-a1.rst |   3 +-
 6 files changed, 138 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/imx8qm-u-boot.dtsi

diff --git a/arch/arm/dts/imx8qm-rom7720-a1.dts 
b/arch/arm/dts/imx8qm-rom7720-a1.dts
index d1f2fff869..332d441c6d 100644
--- a/arch/arm/dts/imx8qm-rom7720-a1.dts
+++ b/arch/arm/dts/imx8qm-rom7720-a1.dts
@@ -10,6 +10,7 @@
 /memreserve/ 0x8000 0x0002;
 
 #include "fsl-imx8qm.dtsi"
+#include "imx8qm-u-boot.dtsi"
 
 / {
model = "Advantech iMX8QM Qseven series";
diff --git a/arch/arm/dts/imx8qm-u-boot.dtsi b/arch/arm/dts/imx8qm-u-boot.dtsi
new file mode 100644
index 00..9b382f4d11
--- /dev/null
+++ b/arch/arm/dts/imx8qm-u-boot.dtsi
@@ -0,0 +1,131 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 NXP
+ */
+
+/ {
+   binman: binman {
+   multiple-images;
+   };
+};
+
+ {
+   u-boot-spl-ddr {
+   align = <4>;
+   align-size = <4>;
+   filename = "u-boot-spl-ddr.bin";
+   pad-byte = <0xff>;
+
+   u-boot-spl {
+   align-end = <4>;
+   filename = "u-boot-spl.bin";
+   };
+   };
+
+   spl {
+   filename = "spl.bin";
+
+   mkimage {
+   args = "-n spl/u-boot-spl.cfgout -T imx8image -e 
0x10";
+
+   blob {
+   filename = "u-boot-spl-ddr.bin";
+   };
+   };
+   };
+
+   itb {
+   filename = "u-boot.itb";
+
+   fit {
+   description = "Configuration to load ATF before U-Boot";
+   fit,external-offset = ;
+   fit,fdt-list = "of-list";
+   #address-cells = <1>;
+
+   images {
+   uboot {
+   arch = "arm64";
+   compression = "none";
+   description = "U-Boot (64-bit)";
+   load = ;
+   type = "standalone";
+
+   uboot-blob {
+   filename = "u-boot-nodtb.bin";
+   type = "blob-ext";
+   };
+   };
+
+   atf {
+   arch = "arm64";
+   compression = "none";
+   description = "ARM Trusted Firmware";
+   entry = <0x0091>;
+   load =  <0x00091000>;
+   type = "firmware";
+
+   atf-blob {
+   filename = "bl31.bin";
+   type = "atf-bl31";
+   };
+   };
+
+   scfw {
+   arch = "arm64";
+   compression = "none";
+   description = "System Controler 
Firmware";
+   type = "firmware";
+
+   scfw_blob {
+   filename = 
"mx8qm-val-scfw-tcm.bin";
+   type = "blob-ext";
+   };
+   };
+
+   seco {
+   arch = "arm64";
+   compression = "none";
+   description = "Seco Firmware";
+   type = "firmware";
+
+   seco_blob {
+   filename = 
"mx8qm-ahab-container.img";
+   type = "blob-ext";
+   };
+   };
+
+   fdt {
+   type = "flat_dt";
+

Re: [PATCH] arm64: dts: meson: nanopi-k2: readd PHY reset properties

[Neil Armstrong]

Hi,

On Tue, 25 Oct 2022 14:32:05 +, Christian Hewitt wrote:
> The sync of device-tree/bindings in 11a48a5a18c6 ("Linux 5.6-rc2") causes
> Ethernet to break on some GXBB boards; the PHY seems to need proper reset
> timing to function in u-boot and Linux. Re-add the old PHY reset binding
> for dwmac until we support new bindings in the PHY node. This borrows the
> same fix applied to the Odroid C2 board [0].
> 
> [0] https://lists.denx.de/pipermail/u-boot/2021-April/446658.html
> 
> [...]

Thanks, Applied to https://source.denx.de/u-boot/custodians/u-boot-amlogic 
(u-boot-amlogic-test)

[1/1] arm64: dts: meson: nanopi-k2: readd PHY reset properties
  
https://source.denx.de/u-boot/custodians/u-boot-amlogic/-/commit/7b70f68977578360d9c47bb25d6d1937075153b4

-- 
Neil

Re: question about uboot mt7620 RAM_VERSION

[Stefan Roese]

Hi Kang-sen,

On 25.10.22 15:25, Kang-sen Lu wrote:

Thanks for your reply.

I cloned the uboot source code from here:
https://github.com/tessel/uboot-mt7620 



I built the uboot.bin for RAM_VERSION. If I select option 8 at power up 
with the uboot from zbtlink, the new uboot.bin will hang. But if I 
caused saveenv() to happen, by changing tftp filename artificially, the 
uboot.bin for RAM_VERSION will start and run properly, by the uboot from 
zbtlink.


Sorry, this is the ancient U-Boot version. I thought you were talking
about the mainline U-Boot version, which I ported for MT7620/80 some
years ago (with many extensions and fixes by Weijie later on).

I don't remember the details of this ancient MT7620 U-Boot version
and frankly don't want to dig into this (again).


Maybe Weijie can comment on the experimental result?


Maybe.


Thanks.

Kang-sen

BTW: How does uboot developer usually run the RAM_VERSION uboot.bin, I 
am curious. Is it loaded with tftp server, or something else?


Yes. This is very handy and frequently done. Load the RAM version
into RAM to the TEXT_BASE address and start it from there via the
"go" command.

BTW: Please keep the ML on Cc. It might be that someone else has
some answers. Or that this topic is interesting for other
people as well.

Thanks,
Stefan

On Tue, Oct 25, 2022 at 12:46 AM Stefan Roese > wrote:


Hi Kang-sen,

On 24.10.22 19:58, Kang-sen Lu wrote:
 > I am wondering if you have read my reply on 10/18. It is very
strange to
 > find that unless I had uboot to do a saveenv, the RAM_VERSION
uboot.bin
 > would not run properly in DRAM.

Frankly, I don't really understand this message. It's not clear to
me, what you are doing and what is working and what is failing.

I thought you were trying to boot the current mainline U-Boot RAM
version u-boot.bin. If yes, which build target did you use? What
does it show on the serial console?

Thanks,
Stefan

 > Thanks.
 >
 > Kang-sen
 >
 > On Tue, Oct 18, 2022 at 10:05 AM Kang-sen Lu mailto:k...@waav.com>
 > >> wrote:
 >
 >     Hi, Stefan:
 >
 >     Thanks for your reply.
 >
 >     The uboot in the zbtlink mt7620 router has the signatures
follows:
 >
 >     U-Boot 1.1.3 (Nov  9 2016 - 15:34:50)
 >
 >     SoC:MediaTek MT7620
 >     DRAM:  Memory Testing..131072K OK. is 128 MB
 >     relocate_code Pointer at: 87fb
 >     enable ephy clock...done. rf reg 29 = 5
 >     SSC disabled.
 >     spi_wait_nsec: 29
 >     spi device id: ef 40 18 0 0 (4018)
 >     Flash: W25Q128BV
 >
 >     I would like to share my strange experience about RAM version
uboot
 >     for mt7620. By pure luck, I found that when I tried to load a
newly
 >     built uboot with startup menu option 8, unless I change the
 >     filename, say, from uboot.bin to uboot1.bin, the newly loaded
uboot
 >     would not startup properly in RAM.
 >
 >     I don't have the knowledge to find out why this variable
"modifies"
 >     to be none-zero is so important to the execution of uboot in RAM.
 >     Maybe some expert in this group can easily figure that out.
 >
 >     Thanks.
 >
 >     Kang-sen
 >
 >     On Tue, Oct 18, 2022 at 7:53 AM Stefan Roese mailto:s...@denx.de>
 >     >> wrote:
 >
 >         Hi Kang-sen,
 >
 >         (added Weijie Gao to Cc)
 >
 >         On 17.10.22 14:11, Kang-sen Lu wrote:
 >          >   I am building uboot.bin for mt7620 router.
 >          >
 >          > I used start menu option 8, a hidden one choice, to load
 >         uboot.bin through
 >          > tftp.
 >          >
 >          > The tftp transfer is OK. But when the new uboot
starts, it hang.
 >
 >         So which mainline U-Boot build target did you use? Don't
you see
 >         any output on the serial console at all?
 >
 >          > I am wondering if the RAM_VERSION for mt7620 still works.
 >
 >         In mainline U-Boot this is usually handled this way. The
SPL U-Boot
 >         version is responsible for the low-level HW init, like
DRAM/DDR init
 >         etc. It's hard to impossible to chainload this SPL part
from a
 >         running U-Boot version.
 >
 >         The "RAM_VERSION" is usually the main U-Boot proper image
 >         "u-boot.bin".
 >         So in general you are using the correct file here. Even
though I
 >         have
 >         not idea, if the build target is correct for your "mt7620
router".
 >
 >         Thanks,
 >         Stefan
 >

Viele Grüße,
Stefan Roese

-- 
DENX Software Engineering GmbH,     

[PATCH] imx8m: Select BINMAN via SoC level

[Fabio Estevam]

From: Fabio Estevam 

Since all imx8m boards have been converted to use binman, select
binman via SoC level rather than making the selection for each board.

Signed-off-by: Fabio Estevam 
---
 arch/arm/mach-imx/imx8m/Kconfig | 33 +
 1 file changed, 1 insertion(+), 32 deletions(-)

diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 8cd7c7a8dd8b..c7a272ec18f5 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -2,6 +2,7 @@ if ARCH_IMX8M
 
 config IMX8M
bool
+   select BINMAN
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
 
@@ -31,13 +32,11 @@ choice
 
 config TARGET_IMX8MQ_CM
bool "Ronetix iMX8MQ-CM SoM"
-   select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
 
 config TARGET_IMX8MQ_EVK
bool "imx8mq_evk"
-   select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
select FSL_CAAM
@@ -46,20 +45,17 @@ config TARGET_IMX8MQ_EVK
 
 config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
-   select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
 
 config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
-   select BINMAN
select IMX8MM
select IMX8M_LPDDR4
select SUPPORT_SPL
 
 config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -69,7 +65,6 @@ config TARGET_IMX8MM_EVK
 
 config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -88,14 +83,12 @@ config TARGET_IMX8MM_ICORE_MX8MM
 
 config TARGET_IMX8MM_MX8MENLO
bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
 
 config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -104,7 +97,6 @@ config TARGET_IMX8MM_VENICE
 
 config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -114,21 +106,18 @@ config TARGET_KONTRON_MX8MM
 
 config TARGET_IMX8MN_BSH_SMM_S2
bool "imx8mn-bsh-smm-s2"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
 
 config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
 
 config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -137,7 +126,6 @@ config TARGET_IMX8MN_EVK
 
 config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
@@ -146,7 +134,6 @@ config TARGET_IMX8MN_DDR4_EVK
 
 config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -155,14 +142,12 @@ config TARGET_IMX8MN_VENICE
 
 config TARGET_IMX8MP_DH_DHCOM_PDK2
bool "DH electronics DHCOM Premium Developer Kit (2) i.MX8M Plus"
-   select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
 
 config TARGET_IMX8MP_ICORE_MX8MP
bool "Engicam i.Core MX8M Plus SOM"
-   select BINMAN
select IMX8MP
select IMX8M_LPDDR4
select SUPPORT_SPL
@@ -176,7 +161,6 @@ config TARGET_IMX8MP_ICORE_MX8MP
 
 config TARGET_IMX8MP_EVK
bool "imx8mp LPDDR4 EVK board"
-   select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -186,7 +170,6 @@ config TARGET_IMX8MP_EVK
 
 config TARGET_IMX8MP_VENICE
bool "Support Gateworks Venice iMX8M Plus module"
-   select BINMAN
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
@@ -195,68 +178,58 @@ config TARGET_IMX8MP_VENICE
 
 config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
-   select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
 
 config TARGET_IMX8MN_VAR_SOM
bool "imx8mn_var_som"
-   select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
 
 config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
-   select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
 
 config TARGET_VERDIN_IMX8MM
bool "Support Toradex Verdin iMX8M Mini module"
-   select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
 
 config 

Re: [PATCH v3] imx: imx8qm-rom7720: switch to binman

[Oliver Graute]

On 25/10/22, Fabio Estevam wrote:
> Hi Oliver,
> 
> On Fri, Oct 7, 2022 at 10:14 AM Oliver Graute
>  wrote:
> 
> > +   fdt {
> > +   filename = "imx8qm-rom7720-a1";
> 
> Please do not hardcode this dtb filename inside the common
> imx8qm-u-boot.dtsi file.

OK I'll remove the line
> 
> You can look at arch/arm/dts/imx8mm-u-boot.dtsi  as a reference.

OK

> 
> > +   type = "flat_dt";
> > +   compression = "none";
> > +
> > +   uboot_fdt_blob {
> > +   filename = "u-boot.dtb";
> > +   type = "blob-ext";
> > +   };
> > +   };
> > +   };
> > +
> > +   configurations {
> > +   default = "conf";
> > +
> > +   conf {
> > +   filename = "imx8qm-rom7720-a1";
> 
> Same here.

Ok

> 
> Also, could you please try converting all imx8mq/qxp boards to binman?

ok I'll try this. 

> Thanks

Best regards,

Oliver

[PATCH] rtc: add ht1380 driver

[Sergei Antonov]

Support Holtek HT1380/HT1381 Serial Timekeeper Chip.
Datasheet:
https://www.holtek.com.tw/documents/10179/11842/ht1380_1v130.pdf

Signed-off-by: Sergei Antonov 
---
 drivers/rtc/Kconfig  |   7 +
 drivers/rtc/Makefile |   1 +
 drivers/rtc/ht1380.c | 303 +++
 3 files changed, 311 insertions(+)
 create mode 100644 drivers/rtc/ht1380.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 23963271928a..f62ee43b0f89 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -220,4 +220,11 @@ config RTC_ZYNQMP
  Say "yes" here to support the on chip real time clock
  present on Xilinx ZynqMP SoC.
 
+config RTC_HT1380
+   bool "Enable Holtek HT1380/HT1381 RTC driver"
+   depends on DM_RTC && DM_GPIO
+   help
+ Say "yes" here to get support for Holtek HT1380/HT1381
+ Serial Timekeeper Chip.
+
 endmenu
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index d621be622848..d04ac8fb0938 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_RTC_DS3231) += ds3231.o
 obj-$(CONFIG_RTC_DS3232) += ds3232.o
 obj-$(CONFIG_RTC_EMULATION) += emul_rtc.o
 obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o
+obj-$(CONFIG_RTC_HT1380) += ht1380.o
 obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o
 obj-$(CONFIG_RTC_IMXDI) += imxdi.o
 obj-$(CONFIG_RTC_ISL1208) += isl1208.o
diff --git a/drivers/rtc/ht1380.c b/drivers/rtc/ht1380.c
new file mode 100644
index ..af28b5f25fcd
--- /dev/null
+++ b/drivers/rtc/ht1380.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Holtek HT1380/HT1381 Serial Timekeeper Chip
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+struct ht1380_priv {
+   struct gpio_desc rst_desc;
+   struct gpio_desc clk_desc;
+   struct gpio_desc dat_desc;
+};
+
+enum registers {
+   SEC,
+   MIN,
+   HOUR,
+   MDAY,
+   MONTH,
+   WDAY,
+   YEAR,
+   WP,
+   N_REGS
+};
+
+static const int BURST = 0xBE;
+static const int READ = 1;
+
+static void ht1380_half_period_delay(void)
+{
+   /* Delay for half a period. 1 us complies with the 500 KHz maximum
+  input serial clock limit given by the datasheet. */
+   udelay(1);
+}
+
+static int ht1380_send_byte(struct ht1380_priv *priv, int byte)
+{
+   int ret;
+
+   for (int bit = 0; bit < 8; bit++) {
+   ret = dm_gpio_set_value(>dat_desc, byte >> bit & 1);
+   if (ret)
+   break;
+   ht1380_half_period_delay();
+
+   ret = dm_gpio_set_value(>clk_desc, 1);
+   if (ret)
+   break;
+   ht1380_half_period_delay();
+
+   ret = dm_gpio_set_value(>clk_desc, 0);
+   if (ret)
+   break;
+   }
+
+   return ret;
+}
+
+static int ht1380_reset_off(struct ht1380_priv *priv)
+{
+   const unsigned int T_CC = 4; /* us, Reset to Clock Setup */
+   int ret;
+
+   /* Go out of RESET state.
+  Make sure we make the minimal delay required by the datasheet. */
+   ret = dm_gpio_set_value(>rst_desc, 1);
+   udelay(T_CC);
+   return ret;
+}
+
+static int ht1380_reset_on(struct ht1380_priv *priv)
+{
+   const unsigned int T_CWH = 4; /* us, Reset Inactive Time */
+   int ret;
+
+   /* Enter RESET state.
+  Make sure we make the minimal delay required by the datasheet. */
+   ret = dm_gpio_set_value(>rst_desc, 0);
+   udelay(T_CWH);
+   return ret;
+}
+
+static int ht1380_rtc_get(struct udevice *dev, struct rtc_time *tm)
+{
+   struct ht1380_priv *priv = dev_get_priv(dev);
+   int ret, i, bit, reg[N_REGS];
+
+   ret = dm_gpio_set_value(>clk_desc, 0);
+   if (ret)
+   return ret;
+
+   ret = dm_gpio_set_dir_flags(>dat_desc, GPIOD_IS_OUT);
+   if (ret)
+   return ret;
+
+   ret = ht1380_reset_off(priv);
+   if (ret)
+   goto exit;
+
+   ret = ht1380_send_byte(priv, BURST + READ);
+   if (ret)
+   goto exit;
+
+   ret = dm_gpio_set_dir_flags(>dat_desc, GPIOD_IS_IN);
+   if (ret)
+   goto exit;
+
+   for (i = 0; i < N_REGS; i++) {
+   reg[i] = 0;
+
+   for (bit = 0; bit < 8; bit++) {
+   ht1380_half_period_delay();
+
+   ret = dm_gpio_set_value(>clk_desc, 1);
+   if (ret)
+   goto exit;
+   ht1380_half_period_delay();
+
+   reg[i] |= dm_gpio_get_value(>dat_desc) << bit;
+   ret = dm_gpio_set_value(>clk_desc, 0);
+   if (ret)
+   goto exit;
+   }
+   }
+
+   ret = -EINVAL;
+
+   /* Correctness check: some bits are always zero */
+   if ((reg[MIN] & 0x80) || (reg[HOUR] & 0x40) || (reg[MDAY] & 0xC0) ||
+ 

Re: [PATCH v3] imx: imx8qm-rom7720: switch to binman

[Fabio Estevam]

Hi Oliver,

On Fri, Oct 7, 2022 at 10:14 AM Oliver Graute
 wrote:

> +   fdt {
> +   filename = "imx8qm-rom7720-a1";

Please do not hardcode this dtb filename inside the common
imx8qm-u-boot.dtsi file.

You can look at arch/arm/dts/imx8mm-u-boot.dtsi  as a reference.

> +   type = "flat_dt";
> +   compression = "none";
> +
> +   uboot_fdt_blob {
> +   filename = "u-boot.dtb";
> +   type = "blob-ext";
> +   };
> +   };
> +   };
> +
> +   configurations {
> +   default = "conf";
> +
> +   conf {
> +   filename = "imx8qm-rom7720-a1";

Same here.

Also, could you please try converting all imx8mq/qxp boards to binman?

Thanks

Re: [PATCH v15 14/15] mkeficapsule: Add support for setting OEM flags in capsule header

[Etienne Carriere]

Hello Sughosh,


For the v15 series: Tested-by: Etienne Carriere 

Best regards,
Etienne


On Fri, 21 Oct 2022 at 14:47, Sughosh Ganu  wrote:
>
> Add support for setting OEM flags in the capsule header. As per the
> UEFI specification, bits 0-15 of the flags member of the capsule
> header can be defined per capsule GUID.
>
> The oemflags will be used for the FWU Multi Bank update feature, as
> specified by the Dependable Boot specification[1]. Bit
> 15 of the flags member will be used to determine if the
> acceptance/rejection of the updated images is to be done by the
> firmware or an external component like the OS.
>
> [1] - 
> https://git.codelinaro.org/linaro/dependable-boot/mbfw/uploads/6f7ddfe3be24e18d4319e108a758d02e/mbfw.pdf
>
> Signed-off-by: Sughosh Ganu 
> Reviewed-by: Ilias Apalodimas 
> Acked-by: Etienne Carriere 
> ---
> Changes since V14:
> * Add a range check for the oemflags passed as suggested by Etienne
>
>  doc/mkeficapsule.1   |  4 
>  tools/mkeficapsule.c | 22 +++---
>  2 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1
> index 77ca061efd..6fb2dd0810 100644
> --- a/doc/mkeficapsule.1
> +++ b/doc/mkeficapsule.1
> @@ -72,6 +72,10 @@ Generate a firmware acceptance empty capsule
>  .BI "-R\fR,\fB --fw-revert "
>  Generate a firmware revert empty capsule
>
> +.TP
> +.BI "-o\fR,\fB --capoemflag "
> +Capsule OEM flag, value between 0x to 0x
> +
>  .TP
>  .BR -h ", " --help
>  Print a help message
> diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c
> index 25bfb39e5b..b71537beee 100644
> --- a/tools/mkeficapsule.c
> +++ b/tools/mkeficapsule.c
> @@ -29,7 +29,7 @@ static const char *tool_name = "mkeficapsule";
>  efi_guid_t efi_guid_fm_capsule = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID;
>  efi_guid_t efi_guid_cert_type_pkcs7 = EFI_CERT_TYPE_PKCS7_GUID;
>
> -static const char *opts_short = "g:i:I:v:p:c:m:dhAR";
> +static const char *opts_short = "g:i:I:v:p:c:m:o:dhAR";
>
>  enum {
> CAPSULE_NORMAL_BLOB = 0,
> @@ -47,6 +47,7 @@ static struct option options[] = {
> {"dump-sig", no_argument, NULL, 'd'},
> {"fw-accept", no_argument, NULL, 'A'},
> {"fw-revert", no_argument, NULL, 'R'},
> +   {"capoemflag", required_argument, NULL, 'o'},
> {"help", no_argument, NULL, 'h'},
> {NULL, 0, NULL, 0},
>  };
> @@ -65,6 +66,7 @@ static void print_usage(void)
> "\t-d, --dump_sig  dump signature (*.p7)\n"
> "\t-A, --fw-accept  firmware accept capsule, requires GUID, 
> no image blob\n"
> "\t-R, --fw-revert  firmware revert capsule, takes no GUID, 
> no image blob\n"
> +   "\t-o, --capoemflag Capsule OEM Flag, an integer between 
> 0x and 0x\n"
> "\t-h, --help  print a help message\n",
> tool_name);
>  }
> @@ -387,6 +389,7 @@ static void free_sig_data(struct auth_context *ctx)
>   * @mcount:Monotonic count in authentication information
>   * @private_file:  Path to a private key file
>   * @cert_file: Path to a certificate file
> + * @oemflags:  Capsule OEM Flags, bits 0-15
>   *
>   * This function actually does the job of creating an uefi capsule file.
>   * All the arguments must be supplied.
> @@ -399,7 +402,8 @@ static void free_sig_data(struct auth_context *ctx)
>   */
>  static int create_fwbin(char *path, char *bin, efi_guid_t *guid,
> unsigned long index, unsigned long instance,
> -   uint64_t mcount, char *privkey_file, char *cert_file)
> +   uint64_t mcount, char *privkey_file, char *cert_file,
> +   uint16_t oemflags)
>  {
> struct efi_capsule_header header;
> struct efi_firmware_management_capsule_header capsule;
> @@ -464,6 +468,8 @@ static int create_fwbin(char *path, char *bin, efi_guid_t 
> *guid,
> header.header_size = sizeof(header);
> /* TODO: The current implementation ignores flags */
> header.flags = CAPSULE_FLAGS_PERSIST_ACROSS_RESET;
> +   if (oemflags)
> +   header.flags |= oemflags;
> header.capsule_image_size = sizeof(header)
> + sizeof(capsule) + sizeof(uint64_t)
> + sizeof(image)
> @@ -635,6 +641,7 @@ int main(int argc, char **argv)
> unsigned char uuid_buf[16];
> unsigned long index, instance;
> uint64_t mcount;
> +   unsigned long oemflags;
> char *privkey_file, *cert_file;
> int c, idx;
>
> @@ -646,6 +653,7 @@ int main(int argc, char **argv)
> cert_file = NULL;
> dump_sig = 0;
> capsule_type = CAPSULE_NORMAL_BLOB;
> +   oemflags = 0;
> for (;;) {
> c = getopt_long(argc, argv, opts_short, options, );
> if (c == -1)
> @@ -709,6 +717,14 @@ int main(int argc, char **argv)
> 

Re: [GIT PULL] please pull fsl-qoriq-2022-10-18

[Tom Rini]

On Tue, Oct 25, 2022 at 01:10:45AM +, Peng Fan wrote:

> Hi Tom,
> 
> Please pull fsl-qoriq-2022-10-18
> 
> CI: 
> https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq/-/pipelines/13836

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH v3] imx: imx8qm: cgtqmx8: switch to binman

[Oliver Graute]

On 25/10/22, Stefano Babic wrote:
> On 25.10.22 10:50, Oliver Graute wrote:
> > On 24/10/22, Stefano Babic wrote:
> > > On 24.10.22 13:59, Oliver Graute wrote:
> > > > On 24/10/22, Stefano Babic wrote:
> > > > > On 24.10.22 13:37, Fabio Estevam wrote:
> > > > > > Hi Stefano and Oliver,
> > > > > > 
> > > > > > On Tue, May 3, 2022 at 7:49 AM Oliver Graute
> > > > > >  wrote:
> > > > > > > 
> > > > > > > Switch to use binman to pack images
> > > > > > > 
> > > > > > > Signed-off-by: Oliver Graute 
> > > > > > > Reviewed-by: Fabio Estevam 
> > > > > > > Reviewed-by: Simon Glass 
> > > > > > > ---
> > > > > > > Changes for v3
> > > > > > > -added Reviewed-by
> > > > > > > -rebased on master
> > > > > > > 
> > > > > > > arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
> > > > > > > arch/arm/mach-imx/imx8/Kconfig  | 1 +
> > > > > > > board/congatec/cgtqmx8/imximage.cfg | 4 ++--
> > > > > > > configs/cgtqmx8_defconfig   | 2 +-
> > > > > > > doc/board/congatec/cgtqmx8.rst  | 3 +--
> > > > > > > 5 files changed, 6 insertions(+), 5 deletions(-)
> > > > > > 
> > > > > > Just realized that v3 does not include imx8qm-u-boot.dtsi and this 
> > > > > > breaks CI.
> > > > > > 
> > > > > 
> > > > > Right - as well as V4, this is what I tried to merge and breaks. I 
> > > > > have drop
> > > > > it.
> > > > > 
> > > > > > The previous v2 did include it:
> > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220221090139.10066-1-oliver.gra...@kococonnector.com/
> > > > > 
> > > > > Thanks for noting this - Oliver, can you check and repost a V5, then ?
> > > > 
> > > > The arch/arm/dts/imx8qm-u-boot.dtsi  is applied on the binman Patch for
> > > > "PATCH v3 imx: imx8qm-rom7720: switch to binman"
> > > > 
> > > > So if you first apply the patches for the imx8qm-rom7720 Board it 
> > > > should work.
> > > 
> > > 
> > > Ok, thanks for tipp - I apply both and will test again
> > 
> > I saw the CI Pipeline failing. Perhaps the reason is a
> > missing CONFIG_FIT_EXTERNAL_OFFSET?
> > 
> 
> I see this, but just applying the two patches, multiple boards are broken:
> imx8qm_rom7720_a1_4G cgtqmx8 imx8qm_mek imx8qxp_mek deneb giedi
> 
> 
> > +++ b/configs/cgtqmx8_defconfig
> > @@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> >   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
> >   CONFIG_REMAKE_ELF=y
> >   CONFIG_FIT=y
> > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> >   CONFIG_SPL_LOAD_FIT=y
> >   # CONFIG_USE_SPL_FIT_GENERATOR is not set
> > 
> > Can you confirm?
> > 
> 
> I let CI run just to see if cgtqmx8 is fixed.

For imx8qm_rom7720 the CONFIG_FIT_EXTERNAL_OFFSET is also missing

--- a/configs/imx8qm_rom7720_a1_4G_defconfig
+++ b/configs/imx8qm_rom7720_a1_4G_defconfig
@@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
 CONFIG_REMAKE_ELF=y
 CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_BOOTDELAY=3


Best regards,

Oliver

Re: [GIT PULL] Please pull u-boot-mmc master

[Tom Rini]

On Tue, Oct 25, 2022 at 09:55:06AM +0900, Jaehoon Chung wrote:

> Dear Tom,
> 
> 
> Please pull u-boot-mmc master into u-boot master branch.
> If there is any problem, let me know, plz.
> 
> Best Regards,
> Jaehoon Chung
> 
> CI: https://source.denx.de/u-boot/custodians/u-boot-mmc/-/pipelines/13923
> 
> 
> The following changes since commit 7723828c97bc107d2fba976fc50403ac8747f1bc:
> 
>   Merge branch '2022-10-21-enforce-some-DM-migrations' (2022-10-21 15:32:45 
> -0400)
> 
> are available in the Git repository at:
> 
>   g...@source.denx.de:u-boot/custodians/u-boot-mmc.git master
> 
> for you to fetch changes up to 337af54a36c6409b7eeb49619c796178b3c22372:
> 
>   mmc: Fix static checker warnings (2022-10-24 18:02:54 +0900)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: Pull request: u-boot-imx u-boot-imx-20220919

[Tom Rini]

On Mon, Oct 24, 2022 at 03:56:47PM +0200, Stefano Babic wrote:

> Hi Tom,
> 
> please pull from u-boot-imx, thanks !
> 
> The following changes since commit 3724ddf157aab3bd009c1da234b9a1af1621b544:
> 
>   Merge branch '2022-10-18-TI-platform-updates' (2022-10-18 18:13:39 -0400)
> 
> are available in the Git repository at:
> 
>   https://gitlab.denx.de/u-boot/custodians/u-boot-imx.git
> tags/u-boot-imx-20221024
> 
> for you to fetch changes up to 0f5caf351c18b212b856f68a8b9d8ea150cc9fa1:
> 
>   configs: verdin-imx8mp: enable caam (2022-10-24 13:43:21 +0200)
> 

Applied to u-boot/master, thanks!

-- 
Tom


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Re: [PATCH 1/2] dm: core: Fix iteration over driver_info records

[Paul Barker]

On 15/10/2022 18:53, Simon Glass wrote:
> Hi Paul,
> 
> On Sat, 15 Oct 2022 at 03:19, Paul Barker  wrote:
>>
>> We should only perform additional iteration steps when needed to
>> initialize the parent of a device. Other binding errors (such as a
>> missing driver) should not lead to additional iteration steps.
>>
>> Unnecessary iteration steps can cause issues when memory is tightly
>> constrained (such as in the TPL/SPL) since device_bind_by_name()
>> unconditionally allocates memory for a struct udevice. On the SanCloud
>> BBE this led to boot failure caused by memory exhaustion in the SPL
>> when booting from SPI flash.
>>
>> Signed-off-by: Paul Barker 
>> ---
>>  drivers/core/lists.c | 17 ++---
>>  1 file changed, 6 insertions(+), 11 deletions(-)
> 
> Are you able to construct a test for this? See test/dm/core.c or test-fdt.c

I can't see how to construct a test case for this issue. What I observed
was the SPL crashing during the pre-relocation lists_bind_drivers() call
due to exhaustion of the available memory. On the AM335x SoC this is 64k
of on-board SRAM which is available before main DRAM is initialised. I
can't see how to reproduce this issue within the u-boot test framework
as significantly more memory is available when running the u-boot
sandbox and so memory exhaustion does not occur. If there are other side
effects than memory leaking here then I'm not familiar enough with the
u-boot device model to spot them.

Each call to bind_drivers_pass() calls device_bind_by_name() for every
driver_info record, with no way of checking whether a particular
driver_info record has already been handled by a previous call to
bind_drivers_pass(). This leaks memory as each call to
device_bind_by_name() allocates a new device object.

> 
> Also, I think bind_drivers_pass() needs a function comment that
> describes in detail what is going on.

Agreed, I'll see what I can add when I revisit this.

> 
> Would it be possible to achieve the same effect while keeping that
> function the same as now?  See below.
> 
>>
>> diff --git a/drivers/core/lists.c b/drivers/core/lists.c
>> index c49695b24f00..82d479564121 100644
>> --- a/drivers/core/lists.c
>> +++ b/drivers/core/lists.c
>> @@ -51,13 +51,13 @@ struct uclass_driver *lists_uclass_lookup(enum uclass_id 
>> id)
>> return NULL;
>>  }
>>
>> -static int bind_drivers_pass(struct udevice *parent, bool pre_reloc_only)
>> +static bool bind_drivers_pass(struct udevice *parent, bool pre_reloc_only,
>> + int *result)
>>  {
>> struct driver_info *info =
>> ll_entry_start(struct driver_info, driver_info);
>> const int n_ents = ll_entry_count(struct driver_info, driver_info);
>> bool missing_parent = false;
>> -   int result = 0;
>> int idx;
>>
>> /*
>> @@ -98,12 +98,12 @@ static int bind_drivers_pass(struct udevice *parent, 
>> bool pre_reloc_only)
>> drt->dev = dev;
>> } else if (ret != -EPERM) {
>> dm_warn("No match for driver '%s'\n", entry->name);
>> -   if (!result || ret != -ENOENT)
>> -   result = ret;
>> +   if (!*result || ret != -ENOENT)
>> +   *result = ret;
>> }
>> }
>>
>> -   return result ? result : missing_parent ? -EAGAIN : 0;
>> +   return missing_parent;
>>  }
>>
>>  int lists_bind_drivers(struct udevice *parent, bool pre_reloc_only)
>> @@ -117,13 +117,8 @@ int lists_bind_drivers(struct udevice *parent, bool 
>> pre_reloc_only)
>>  * always succeed on the first pass.
>>  */
>> for (pass = 0; pass < 10; pass++) {
>> -   int ret;
>> -
>> -   ret = bind_drivers_pass(parent, pre_reloc_only);
>> -   if (!ret)
>> +   if (!bind_drivers_pass(parent, pre_reloc_only, ))
>> break;
>> -   if (ret != -EAGAIN && !result)
>> -   result = ret;
> 
> If there were something like this, could we drop the other changes?
> 
> if (ret) {
>if (ret == -EAGAIN)
>   continue;
>else if (!result)
> 
>   result = ret;
> }

I don't think this works exactly, as we want to break when (ret ==
-EAGAIN) instead of continue. However I have a variant which I think is
working which I can send as a v2.

> 
>> }
>>
>> return result;
>> --
>> 2.25.1
>>

-- 
Paul Barker
Principal Software Engineer
SanCloud Ltd

e: paul.bar...@sancloud.com
w: https://sancloud.com/

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Re: [PATCH 2/2] net:xilinx_axi: check PCS/PMA PHY status in setup_phy

[Michal Simek]

Also add missing space in subject.

On 10/17/22 13:19, Andy Chiu wrote:

Both PCS/PMA PHY and the external PHY need to have a valid link status
in order to have Ethernet traffic. Check and wait this status at
setup_phy() so that we could diagnose if there is a PHY issue.

Signed-off-by: Andy Chiu 
Reviewed-by: Greentime Hu 
---
  drivers/net/xilinx_axi_emac.c | 43 +++
  1 file changed, 43 insertions(+)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 447e1d4c9c..257ab4661e 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -336,6 +336,44 @@ static int axiemac_phy_init(struct udevice *dev)
return 0;
  }
  
+static int pcs_pma_startup(struct axidma_priv *priv)

+{
+   u32 rc;
+   u32 retry_cnt = 0;


group them together.


+   u16 mii_reg;
+
+   rc = phyread(priv, priv->pcsaddr, MII_BMCR, _reg);
+   if (rc)
+   goto failed_mdio;
+
+   if (!(mii_reg & BMCR_ANENABLE)) {
+   mii_reg |= BMCR_ANENABLE;
+   if (phywrite(priv, priv->pcsaddr, MII_BMCR, mii_reg))
+   goto failed_mdio;
+   }
+
+   /* Check the internal PHY status and warn user if the internal PHY is
+* not resetted


reset


+*/
+   printf("axiemac: waiting for link status of the PCS/PMA PHY");


I think that you likely not need to see this message in normal run. I would move 
it to debug. Keep only error message.


ZynqMP> ping 192.168.10.20
ethernet@8000 Waiting for PHY auto negotiation to complete. done
axiemac: waiting for link status of the PCS/PMA PHY.Done
Using ethernet@8000 device
host 192.168.10.20 is alive


+   while (retry_cnt * 10 < PHY_ANEG_TIMEOUT) {
+   rc = phyread(priv, priv->pcsaddr, MII_BMSR, _reg);
+   if ((mii_reg & BMSR_LSTATUS) && mii_reg != 0x && !rc) {
+   printf(".Done\n");
+   return 0;
+   }
+
+   printf(".");


genphy_update_link() is using
 if ((i++ % 10) == 0)
 printf(".");



+   retry_cnt++;
+   mdelay(10);
+   }
+   printf("\n\tWarning, PCS/PMA PHY is not ready, link is down\n");


newline. Are you sure about \n\t . I can't see any advantage of it.


+   return 1;


newline here.


+failed_mdio:
+   printf("axiemac: MDIO to the PCS/PMA PHY has failed\n");


newline


+   return 1;
+}
+
  /* Setting axi emac and phy to proper setting */
  static int setup_phy(struct udevice *dev)
  {
@@ -367,6 +405,11 @@ static int setup_phy(struct udevice *dev)
   phydev->dev->name);
return 0;
}
+   if (priv->interface == PHY_INTERFACE_MODE_SGMII ||
+   priv->interface == PHY_INTERFACE_MODE_1000BASEX) {
+   if (pcs_pma_startup(priv))
+   return 0;
+   }
if (!phydev->link) {
printf("%s: No link.\n", phydev->dev->name);
return 0;


M

Re: [PATCH] efi_loader: Let networking support depend on NETDEVICES

[Jan Kiszka]

On 24.10.22 22:47, Heinrich Schuchardt wrote:
> On 10/15/22 08:31, Heinrich Schuchardt wrote:
>> On 10/14/22 18:10, Jan Kiszka wrote:
>>> From: Jan Kiszka 
>>>
>>> CONFIG_NET does not imply that there are actually network devices
>>> available, only CONFIG_NETDEVICES does. Changing to this dependenc
>> CONFIG_NETDEVICES=y does not imply that any network driver is selected
>> it is just a tighter prerequisite than CONFIG_NET.
>>
>>> obsoletes the check in Kconfig because NETDEVICES means DM_ETH.
>>>
>>> Suggested-by: Tom Rini 
>>> Signed-off-by: Jan Kiszka 
>>
>> Thanks for the patch.
>>
>> It is good to get rid of the dependency for CONFIG_EFI_LOADER.
>>
>> Reviewed-by: Heinrich Schuchardt 
> 
> For LicheePi_Zero_defconfig this patch results in:
> 
> arm-linux-gnueabi-ld.bfd: net/bootp.o: in function `dhcp_handler':
> net/bootp.c:1080: undefined reference to `efi_net_set_dhcp_ack'
> 
> I guess we should add:
> 
> diff --git a/net/bootp.c b/net/bootp.c
> index b260d5d09e..6c01e38153 100644
> --- a/net/bootp.c
> +++ b/net/bootp.c
> @@ -1077,7 +1077,9 @@ static void dhcp_handler(uchar *pkt, unsigned
> dest, struct in_addr sip,
>     strlen(CONFIG_SYS_BOOTFILE_PREFIX)) == 0) {
>  #endif /* CONFIG_SYS_BOOTFILE_PREFIX */
>     dhcp_packet_process_options(bp);
> -   efi_net_set_dhcp_ack(pkt, len);
> +   if (CONFIG_IS_ENABLED(EFI_LOADER) &&
> +   CONFIG_IS_ENABLED(NET_DEVICES))
> +   efi_net_set_dhcp_ack(pkt, len);
> 
> As this was already incorrect before your patch:
> 
> Fixes: 0efe1bcf5c2c ("efi_loader: Add network access support")
> 
> Best regards
> 
> Heinrich

Will you send this, or should I submit a v2 of my patch with this included?

Jan

-- 
Siemens AG, Technology
Competence Center Embedded Linux

Re: [PATCH v3] imx: imx8qm: cgtqmx8: switch to binman

[Tom Rini]

On Tue, Oct 25, 2022 at 02:07:55PM +0200, Stefano Babic wrote:
> On 25.10.22 11:28, Stefano Babic wrote:
> > On 25.10.22 10:50, Oliver Graute wrote:
> > > On 24/10/22, Stefano Babic wrote:
> > > > On 24.10.22 13:59, Oliver Graute wrote:
> > > > > On 24/10/22, Stefano Babic wrote:
> > > > > > On 24.10.22 13:37, Fabio Estevam wrote:
> > > > > > > Hi Stefano and Oliver,
> > > > > > > 
> > > > > > > On Tue, May 3, 2022 at 7:49 AM Oliver Graute
> > > > > > >  wrote:
> > > > > > > > 
> > > > > > > > Switch to use binman to pack images
> > > > > > > > 
> > > > > > > > Signed-off-by: Oliver Graute 
> > > > > > > > Reviewed-by: Fabio Estevam 
> > > > > > > > Reviewed-by: Simon Glass 
> > > > > > > > ---
> > > > > > > > Changes for v3
> > > > > > > >     -added Reviewed-by
> > > > > > > >     -rebased on master
> > > > > > > > 
> > > > > > > >     arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
> > > > > > > >     arch/arm/mach-imx/imx8/Kconfig  | 1 +
> > > > > > > >     board/congatec/cgtqmx8/imximage.cfg | 4 ++--
> > > > > > > >     configs/cgtqmx8_defconfig   | 2 +-
> > > > > > > >     doc/board/congatec/cgtqmx8.rst  | 3 +--
> > > > > > > >     5 files changed, 6 insertions(+), 5 deletions(-)
> > > > > > > 
> > > > > > > Just realized that v3 does not include
> > > > > > > imx8qm-u-boot.dtsi and this breaks CI.
> > > > > > > 
> > > > > > 
> > > > > > Right - as well as V4, this is what I tried to merge and
> > > > > > breaks. I have drop
> > > > > > it.
> > > > > > 
> > > > > > > The previous v2 did include it:
> > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20220221090139.10066-1-oliver.gra...@kococonnector.com/
> > > > > > 
> > > > > > Thanks for noting this - Oliver, can you check and repost a V5, 
> > > > > > then ?
> > > > > 
> > > > > The arch/arm/dts/imx8qm-u-boot.dtsi  is applied on the binman Patch 
> > > > > for
> > > > > "PATCH v3 imx: imx8qm-rom7720: switch to binman"
> > > > > 
> > > > > So if you first apply the patches for the imx8qm-rom7720
> > > > > Board it should work.
> > > > 
> > > > 
> > > > Ok, thanks for tipp - I apply both and will test again
> > > 
> > > I saw the CI Pipeline failing. Perhaps the reason is a
> > > missing CONFIG_FIT_EXTERNAL_OFFSET?
> > > 
> > 
> > I see this, but just applying the two patches, multiple boards are broken:
> > imx8qm_rom7720_a1_4G cgtqmx8 imx8qm_mek imx8qxp_mek deneb giedi
> > 
> > 
> > > +++ b/configs/cgtqmx8_defconfig
> > > @@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > >   CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
> > >   CONFIG_REMAKE_ELF=y
> > >   CONFIG_FIT=y
> > > +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
> > >   CONFIG_SPL_LOAD_FIT=y
> > >   # CONFIG_USE_SPL_FIT_GENERATOR is not set
> > > 
> > > Can you confirm?
> > > 
> > 
> > I let CI run just to see if cgtqmx8 is fixed.
> 
> So this seems to fix the Congatec board. Rather, all DTS for i.MX8 are built
> together, and other boards have not switched to binman. I feel this
> dependency too hard. Should we maybe split the targets in
> arch/arm/dts/Makefile ? All DTS are build according to CONFIG_ARCH_IMX8, so
> congatec DTS is compiled even in case of deneb and gied.
> 
> See https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13928.

IMHO at this point we need to just untested-convert those last
outstanding board or boards, or remove them. This migration has been
dragging on and on and I'm sure I've mailed the board maintainers a few
times.

-- 
Tom


signature.asc
Description: PGP signature

Pull request: u-boot-spi/master

[Jagan Teki]

Hi Tom,

Please pull this PR.

Summary:
- Add s28hl512t, s28hl01gt (Takahiro)
- Rework s25hx_t_post_bfpt_fixup() (Takahiro)

CI:
https://source.denx.de/u-boot/custodians/u-boot-spi/-/pipelines/13925

thanks,
Jagan.

The following changes since commit 7723828c97bc107d2fba976fc50403ac8747f1bc:

  Merge branch '2022-10-21-enforce-some-DM-migrations' (2022-10-21 15:32:45 
-0400)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-spi.git master

for you to fetch changes up to 622b5d356136f9172db7fe7ba240cd9e45097a19:

  cmd: sf: Handle unaligned 'update' start offset (2022-10-25 10:17:33 +0530)


Marek Vasut (1):
  cmd: sf: Handle unaligned 'update' start offset

Takahiro Kuwano (8):
  mtd: spi-nor-core: Rename s28hs512t prefix
  mtd: spi-nor-core: Rename configuration macro for S28 support
  mtd: spi-nor-ids: Add s28hl512t, s28hl01gt, and s28hs01gt IDs
  mtd: spi-nor-core: Default to addr_width of 3 for configurable widths
  mtd: spi-nor-core: Track flash's internal address mode
  mtd: spi-nor-core: Rework spansion_read/write_any_reg() to use 
addr_mode_nbytes
  mtd: spi-nor-core: Rework s25hx_t_post_bfpt_fixup() for flash's internal 
address mode
  mtd: spi-nor-core: Fix index value for SCCR dwords

 cmd/sf.c | 18 +---
 configs/j721s2_evm_a72_defconfig |  2 +-
 configs/j721s2_evm_r5_defconfig  |  2 +-
 drivers/mtd/spi/Kconfig  | 10 ++---
 drivers/mtd/spi/spi-nor-core.c   | 92 
 drivers/mtd/spi/spi-nor-ids.c|  5 ++-
 include/linux/mtd/spi-nor.h  |  5 +++
 7 files changed, 83 insertions(+), 51 deletions(-)

Re: [PATCH v3] imx: imx8qm: cgtqmx8: switch to binman

[Stefano Babic]

On 25.10.22 11:28, Stefano Babic wrote:

On 25.10.22 10:50, Oliver Graute wrote:

On 24/10/22, Stefano Babic wrote:

On 24.10.22 13:59, Oliver Graute wrote:

On 24/10/22, Stefano Babic wrote:

On 24.10.22 13:37, Fabio Estevam wrote:

Hi Stefano and Oliver,

On Tue, May 3, 2022 at 7:49 AM Oliver Graute
 wrote:


Switch to use binman to pack images

Signed-off-by: Oliver Graute 
Reviewed-by: Fabio Estevam 
Reviewed-by: Simon Glass 
---
Changes for v3
    -added Reviewed-by
    -rebased on master

    arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
    arch/arm/mach-imx/imx8/Kconfig  | 1 +
    board/congatec/cgtqmx8/imximage.cfg | 4 ++--
    configs/cgtqmx8_defconfig   | 2 +-
    doc/board/congatec/cgtqmx8.rst  | 3 +--
    5 files changed, 6 insertions(+), 5 deletions(-)


Just realized that v3 does not include imx8qm-u-boot.dtsi and this 
breaks CI.




Right - as well as V4, this is what I tried to merge and breaks. I 
have drop

it.


The previous v2 did include it:
https://patchwork.ozlabs.org/project/uboot/patch/20220221090139.10066-1-oliver.gra...@kococonnector.com/


Thanks for noting this - Oliver, can you check and repost a V5, then ?


The arch/arm/dts/imx8qm-u-boot.dtsi  is applied on the binman Patch for
"PATCH v3 imx: imx8qm-rom7720: switch to binman"

So if you first apply the patches for the imx8qm-rom7720 Board it 
should work.



Ok, thanks for tipp - I apply both and will test again


I saw the CI Pipeline failing. Perhaps the reason is a
missing CONFIG_FIT_EXTERNAL_OFFSET?



I see this, but just applying the two patches, multiple boards are broken:
imx8qm_rom7720_a1_4G cgtqmx8 imx8qm_mek imx8qxp_mek deneb giedi



+++ b/configs/cgtqmx8_defconfig
@@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
  CONFIG_REMAKE_ELF=y
  CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  CONFIG_SPL_LOAD_FIT=y
  # CONFIG_USE_SPL_FIT_GENERATOR is not set

Can you confirm?



I let CI run just to see if cgtqmx8 is fixed.


So this seems to fix the Congatec board. Rather, all DTS for i.MX8 are 
built together, and other boards have not switched to binman. I feel 
this dependency too hard. Should we maybe split the targets in 
arch/arm/dts/Makefile ? All DTS are build according to CONFIG_ARCH_IMX8, 
so congatec DTS is compiled even in case of deneb and gied.


See https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/13928.

Best regards,
Stefano



Stefano



--
=
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=

Re: [PATCH v3 1/9] nand: atmel: Add DM based NAND driver

[Michael Nazzareno Trimarchi]

Hi

On Tue, Oct 25, 2022 at 12:52 PM Balamanikandan Gunasundar
 wrote:
>
> This implementation is ported from the rework done by Boris Brezillon
> in Linux. This porting is done based on linux-5.4-at91. The driver is
> tested in sam9x60ek, sama5d3_xplained, sam9x75eb and sama7g54-ddr3-eb.
>
> Changes done includes
>
> - Adapt GPIO descriptor apis for U-Boot. Use gpio_request_by_name_nodev,
>   dm_gpio_get_value etc.
> - Use U_BOOT_DRIVER instead of platform_driver.
> - Replace struct platform_device with struct udevice
> - Check the status of nfc exec operation by polling the status
>   register instead of interrupt based handling
> - DMA operations not supported. Remove it
> - Adapt DT parsing to U-Boot APIs
>
> Signed-off-by: Balamanikandan Gunasundar 
> 
>
> Signed-off-by: Balamanikandan Gunasundar 
> 

Kindle, fix signed off and describe change from V2 to V3

Michael

> ---
>  drivers/mtd/nand/raw/Kconfig |8 +
>  drivers/mtd/nand/raw/Makefile|1 +
>  drivers/mtd/nand/raw/atmel/Makefile  |4 +
>  drivers/mtd/nand/raw/atmel/nand-controller.c | 2286 ++
>  4 files changed, 2299 insertions(+)
>  create mode 100644 drivers/mtd/nand/raw/atmel/Makefile
>  create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c
>
> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
> index ce67d1abde..4d023e2893 100644
> --- a/drivers/mtd/nand/raw/Kconfig
> +++ b/drivers/mtd/nand/raw/Kconfig
> @@ -37,6 +37,14 @@ config SYS_NAND_USE_FLASH_BBT
> help
>   Enable the BBT (Bad Block Table) usage.
>
> +config DM_NAND_ATMEL
> +   bool "Support Atmel NAND controller with DM support"
> +   select SYS_NAND_SELF_INIT
> +   imply SYS_NAND_USE_FLASH_BBT
> +   help
> + Enable this driver for NAND flash platforms using an Atmel NAND
> + controller.
> +
>  config NAND_ATMEL
> bool "Support Atmel NAND controller"
> select SYS_NAND_SELF_INIT
> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
> index a398aa9d88..42c1fb25b4 100644
> --- a/drivers/mtd/nand/raw/Makefile
> +++ b/drivers/mtd/nand/raw/Makefile
> @@ -48,6 +48,7 @@ ifdef NORMAL_DRIVERS
>  obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
>
>  obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
> +obj-$(CONFIG_DM_NAND_ATMEL) += atmel/
>  obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
>  obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
>  obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
> diff --git a/drivers/mtd/nand/raw/atmel/Makefile 
> b/drivers/mtd/nand/raw/atmel/Makefile
> new file mode 100644
> index 00..6708416983
> --- /dev/null
> +++ b/drivers/mtd/nand/raw/atmel/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_DM_NAND_ATMEL)+= atmel-nand-controller.o
> +
> +atmel-nand-controller-objs := nand-controller.o
> diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c 
> b/drivers/mtd/nand/raw/atmel/nand-controller.c
> new file mode 100644
> index 00..9873d11254
> --- /dev/null
> +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
> @@ -0,0 +1,2286 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2022 ATMEL
> + * Copyright 2017 Free Electrons
> + *
> + * Author: Boris Brezillon 
> + *
> + * Derived from the atmel_nand.c driver which contained the following
> + * copyrights:
> + *
> + *   Copyright 2003 Rick Bronson
> + *
> + *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
> + * Copyright 2001 Thomas Gleixner (gleix...@autronix.de)
> + *
> + *   Derived from drivers/mtd/spia.c (removed in v3.8)
> + * Copyright 2000 Steven J. Hill (sjh...@cotw.com)
> + *
> + *
> + *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
> + * Richard Genoud (richard.gen...@gmail.com), Adeneo Copyright 2007
> + *
> + *   Derived from Das U-Boot source code
> + * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
> + * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
> + *
> + *   Add Programmable Multibit ECC support for various AT91 SoC
> + * Copyright 2012 ATMEL, Hong Xu
> + *
> + *   Add Nand Flash Controller support for SAMA5 SoC
> + * Copyright 2013 ATMEL, Josh Wu (josh...@atmel.com)
> + *
> + *   Port from Linux
> + * Balamanikandan Gunasundar(balamanikandan.gunasun...@microchip.com)
> + * Copyright (C) 2022 Microchip Technology Inc.
> + *
> + * A few words about the naming convention in this file. This convention
> + * applies to structure and function names.
> + *
> + * Prefixes:
> + *
> + * - atmel_nand_: all generic structures/functions
> + * - atmel_smc_nand_: all structures/functions specific to the SMC interface
> + *   (at91sam9 and avr32 SoCs)
> + * - atmel_hsmc_nand_: all structures/functions specific to the HSMC 
> interface
> + *(sama5 SoCs and later)
> + * - atmel_nfc_: all structures/functions used to manipulate the NFC 
> sub-block
> + *  that is available in the 

[PATCH] rockchip: puma: fix GPT table corruption when saving U-Boot environment

[Quentin Schulz]

From: Quentin Schulz 

The GPT table is taking the first 34 sectors, which amounts to 0x4400
bytes. Saving the environment below this address in storage will corrupt
the GPT table.

While technically the table ends at 0x4400, some tools (e.g. bmaptool)
are rounding everything to the logical block size (0x1000), so it is
safer to make it point to 0x5000 so that the environment could still
persist when flashing a sparse image with bmaptool or similar tools.

Obviously, the default 0x4000 environment size does not work anymore, so
let's set it to 0x3000 so it does fill the gap between the GPT table
(rounded to 0x1000) and the start of the idbloader.img.

Fixes: 56f580d3eb8d ("rockchip: dts: rk3399-puma: put environment (in MMC/SD 
configurations) before SPL")
Cc: Quentin Schulz 
Signed-off-by: Quentin Schulz 
---
To: Simon Glass 
To: Philipp Tomsich 
To: Kever Yang 
To: Klaus Goger 
Cc: u-boot@lists.denx.de
---
 arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi | 2 +-
 configs/puma-rk3399_defconfig   | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi 
b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
index f8335c74a7..d2349ae90e 100644
--- a/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
@@ -15,7 +15,7 @@
 / {
config {
u-boot,spl-payload-offset = <0x8>; /* @ 512KB */
-   u-boot,mmc-env-offset = <0x4000>;  /* @  16KB */
+   u-boot,mmc-env-offset = <0x5000>;  /* @  20KB */
u-boot,efi-partition-entries-offset = <0x20>; /* 2MB */
u-boot,boot-led = "module_led";
sysreset-gpio = < RK_PA6 GPIO_ACTIVE_HIGH>;
diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 34186d1caa..91f31b37e8 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -5,6 +5,7 @@ CONFIG_ARCH_ROCKCHIP=y
 CONFIG_SYS_TEXT_BASE=0x0020
 CONFIG_SPL_GPIO=y
 CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x3000
 CONFIG_ENV_OFFSET=0x3F8000
 CONFIG_DEFAULT_DEVICE_TREE="rk3399-puma-haikou"
 CONFIG_ROCKCHIP_RK3399=y

---
base-commit: 1e892ef0b59a4a04971ac23619b95917020b3e18
change-id: 20221025-upstream-puma-mmc-env-gpt-6f42cd038fdd

Best regards,
-- 
Quentin Schulz 

[PATCH v3 9/9] board: sam9x60ek: remove nand init from board file

[Balamanikandan Gunasundar]

Move this out of board file as this is done by the DM based NAND flash
driver. The EBI chip select configuration, iomux and timings are
handled by the driver

Signed-off-by: Balamanikandan Gunasundar 

---
 board/atmel/sam9x60ek/sam9x60ek.c | 59 ---
 include/configs/sam9x60ek.h   |  5 ---
 2 files changed, 64 deletions(-)

diff --git a/board/atmel/sam9x60ek/sam9x60ek.c 
b/board/atmel/sam9x60ek/sam9x60ek.c
index 7035fab878..d8d2c3a18f 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -24,62 +24,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 void at91_prepare_cpu_var(void);
 
-#ifdef CONFIG_CMD_NAND
-static void sam9x60ek_nand_hw_init(void)
-{
-   struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
-   struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
-   unsigned int csa;
-
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1);   /* NAND OE */
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1);   /* NAND WE */
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0);   /* NAND ALE */
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0);   /* NAND CLE */
-   /* Enable NandFlash */
-   at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
-   /* Configure RDY/BSY */
-   at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
-   at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
-
-   at91_periph_clk_enable(ATMEL_ID_PIOD);
-
-   /* Enable CS3 */
-   csa = readl(>ebicsa);
-   csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
-
-   /* Configure IO drive */
-   csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
-
-   writel(csa, >ebicsa);
-
-   /* Configure SMC CS3 for NAND/SmartMedia */
-   writel(AT91_SMC_SETUP_NWE(4), >cs[3].setup);
-
-   writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
-  AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
-  >cs[3].pulse);
-
-   writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
-  >cs[3].cycle);
-
-   writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
-#ifdef CONFIG_SYS_NAND_DBW_16
-  AT91_SMC_MODE_DBW_16 |
-#else /* CONFIG_SYS_NAND_DBW_8 */
-  AT91_SMC_MODE_DBW_8 |
-#endif
-  AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
-  >cs[3].mode);
-}
-#endif
-
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
@@ -122,9 +66,6 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 
-#ifdef CONFIG_CMD_NAND
-   sam9x60ek_nand_hw_init();
-#endif
return 0;
 }
 
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index b9b56d9f1a..72c089512f 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -29,11 +29,6 @@
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_SYS_NAND_BASE   0x4000
-#define CONFIG_SYS_NAND_MASK_ALE   BIT(21)
-#define CONFIG_SYS_NAND_MASK_CLE   BIT(22)
-#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
-#define CONFIG_SYS_NAND_READY_PIN  AT91_PIN_PD5
 #endif
 
 #endif
-- 
2.25.1

[PATCH v3 8/9] ARM: dts: at91: sam9x60ek: Enable NAND support

[Balamanikandan Gunasundar]

Enable the EBI and NAND flash controller. Define the pinctrl and
partition table

Signed-off-by: Balamanikandan Gunasundar 

---
 arch/arm/dts/sam9x60ek.dts | 103 +
 1 file changed, 103 insertions(+)

diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index eb44868a3e..1a02e2cb79 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -80,6 +80,44 @@
};
 
pinctrl {
+   nand {
+   pinctrl_nand_oe_we: nand-oe-we-0 {
+   atmel,pins =
+   ;
+   };
+
+   pinctrl_nand_rb: nand-rb-0 {
+   atmel,pins =
+   ;
+   };
+
+   pinctrl_nand_cs: nand-cs-0 {
+   atmel,pins =
+   ;
+   };
+   };
+
+   ebi {
+   pinctrl_ebi_data_0_7: ebi-data-lsb-0 {
+   atmel,pins =
+   ;
+   };
+
+   pinctrl_ebi_addr_nand: ebi-addr-0 {
+   atmel,pins =
+   ;
+   };
+   };
+
pinctrl_qspi: qspi {
atmel,pins =
;
+   status = "okay";
+
+   nand_controller: nand-controller {
+   pinctrl-names = "default";
+   pinctrl-0 = <_nand_oe_we _nand_cs 
_nand_rb>;
+   status = "okay";
+
+   nand@3 {
+   reg = <0x3 0x0 0x80>;
+   rb-gpios = < 5 GPIO_ACTIVE_HIGH>;
+   cs-gpios = < 4 GPIO_ACTIVE_HIGH>;
+   nand-bus-width = <8>;
+   nand-ecc-mode = "hw";
+   nand-ecc-strength = <8>;
+   nand-ecc-step-size = <512>;
+   nand-on-flash-bbt;
+   label = "atmel_nand";
+
+   partitions {
+   compatible = "fixed-partitions";
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   at91bootstrap@0 {
+   label = "at91bootstrap";
+   reg = <0x0 0x4>;
+   };
+
+   uboot@4 {
+   label = "u-boot";
+   reg = <0x4 0xc>;
+   };
+
+   ubootenvred@10 {
+   label = "U-Boot Env Redundant";
+   reg = <0x10 0x4>;
+   };
+
+   ubootenv@14 {
+   label = "U-Boot Env";
+   reg = <0x14 0x4>;
+   };
+
+   dtb@18 {
+   label = "device tree";
+   reg = <0x18 0x8>;
+   };
+
+   kernel@20 {
+   label = "kernel";
+   reg = <0x20 0x60>;
+   };
+
+   rootfs@80 {
+   label = "rootfs";
+   reg = <0x80 0x1f80>;
+   };
+   };
+   };
+   };
+};
+
  {
phy-mode = "rmii";
status = "okay";
-- 
2.25.1

[PATCH v3 5/9] mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation

[Balamanikandan Gunasundar]

Add helper functions for atmel Static Memory Controller. The functions
are required to configure SMC. This file is inherited from the work
done by Boris Brezillon for Linux

Signed-off-by: Balamanikandan Gunasundar 

---
 drivers/Kconfig  |   2 +
 drivers/Makefile |   1 +
 drivers/mfd/Kconfig  |   4 +
 drivers/mfd/Makefile |   1 +
 drivers/mfd/atmel-smc.c  | 364 +++
 include/linux/mfd/syscon/atmel-smc.h | 119 +
 6 files changed, 491 insertions(+)
 create mode 100644 drivers/mfd/Kconfig
 create mode 100644 drivers/mfd/Makefile
 create mode 100644 drivers/mfd/atmel-smc.c
 create mode 100644 include/linux/mfd/syscon/atmel-smc.h

diff --git a/drivers/Kconfig b/drivers/Kconfig
index 8b6fead351..ffc06ed65e 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -60,6 +60,8 @@ source "drivers/mailbox/Kconfig"
 
 source "drivers/memory/Kconfig"
 
+source "drivers/mfd/Kconfig"
+
 source "drivers/misc/Kconfig"
 
 source "drivers/mmc/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 9d9f69a3c9..d5325d7395 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -102,6 +102,7 @@ obj-$(CONFIG_QE) += qe/
 obj-$(CONFIG_U_QE) += qe/
 obj-y += mailbox/
 obj-y += memory/
+obj-y += mfd/
 obj-y += mtd/
 obj-y += pwm/
 obj-y += reset/
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
new file mode 100644
index 00..ae53b02f27
--- /dev/null
+++ b/drivers/mfd/Kconfig
@@ -0,0 +1,4 @@
+config MFD_ATMEL_SMC
+   bool "Atmel Static Memory Controller driver"
+   help
+   Say yes here to support Atmel Static Memory Controller driver.
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
new file mode 100644
index 00..4454815a98
--- /dev/null
+++ b/drivers/mfd/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_MFD_ATMEL_SMC) += atmel-smc.o
diff --git a/drivers/mfd/atmel-smc.c b/drivers/mfd/atmel-smc.c
new file mode 100644
index 00..15296f71a1
--- /dev/null
+++ b/drivers/mfd/atmel-smc.c
@@ -0,0 +1,364 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Atmel SMC (Static Memory Controller) helper functions.
+ *
+ * Copyright (C) 2022 Microchip Technology Inc.
+ * Copyright (C) 2017 Free Electrons
+ *
+ * Author: Boris Brezillon 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * atmel_smc_cs_conf_init - initialize a SMC CS conf
+ * @conf: the SMC CS conf to initialize
+ *
+ * Set all fields to 0 so that one can start defining a new config.
+ */
+void atmel_smc_cs_conf_init(struct atmel_smc_cs_conf *conf)
+{
+   memset(conf, 0, sizeof(*conf));
+}
+EXPORT_SYMBOL_GPL(atmel_smc_cs_conf_init);
+
+/**
+ * atmel_smc_cs_encode_ncycles - encode a number of MCK clk cycles in the
+ *  format expected by the SMC engine
+ * @ncycles: number of MCK clk cycles
+ * @msbpos: position of the MSB part of the timing field
+ * @msbwidth: width of the MSB part of the timing field
+ * @msbfactor: factor applied to the MSB
+ * @encodedval: param used to store the encoding result
+ *
+ * This function encodes the @ncycles value as described in the datasheet
+ * (section "SMC Setup/Pulse/Cycle/Timings Register"). This is a generic
+ * helper which called with different parameter depending on the encoding
+ * scheme.
+ *
+ * If the @ncycles value is too big to be encoded, -ERANGE is returned and
+ * the encodedval is contains the maximum val. Otherwise, 0 is returned.
+ */
+static int atmel_smc_cs_encode_ncycles(unsigned int ncycles,
+  unsigned int msbpos,
+  unsigned int msbwidth,
+  unsigned int msbfactor,
+  unsigned int *encodedval)
+{
+   unsigned int lsbmask = GENMASK(msbpos - 1, 0);
+   unsigned int msbmask = GENMASK(msbwidth - 1, 0);
+   unsigned int msb, lsb;
+   int ret = 0;
+
+   msb = ncycles / msbfactor;
+   lsb = ncycles % msbfactor;
+
+   if (lsb > lsbmask) {
+   lsb = 0;
+   msb++;
+   }
+
+   /*
+* Let's just put the maximum we can if the requested setting does
+* not fit in the register field.
+* We still return -ERANGE in case the caller cares.
+*/
+   if (msb > msbmask) {
+   msb = msbmask;
+   lsb = lsbmask;
+   ret = -ERANGE;
+   }
+
+   *encodedval = (msb << msbpos) | lsb;
+
+   return ret;
+}
+
+/**
+ * atmel_smc_cs_conf_set_timing - set the SMC CS conf Txx parameter to a
+ *   specific value
+ * @conf: SMC CS conf descriptor
+ * @shift: the position of the Txx field in the TIMINGS register
+ * @ncycles: value (expressed in MCK clk cycles) to assign to this Txx
+ *  parameter
+ *
+ * This function encodes the @ncycles value as described in the datasheet
+ * (section "SMC Timings Register"), and then 

[PATCH v3 7/9] ARM: dts: at91: sam9x60: Add nodes for EBI and NAND

[Balamanikandan Gunasundar]

Add new bindings for EBI and NAND controller

Signed-off-by: Balamanikandan Gunasundar 

---
 arch/arm/dts/sam9x60.dtsi | 42 +++
 1 file changed, 42 insertions(+)

diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a5c429eb3a..17224ef771 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -69,6 +69,32 @@
#size-cells = <1>;
ranges;
 
+   ebi: ebi@1000 {
+   compatible = "microchip,sam9x60-ebi";
+   #address-cells = <2>;
+   #size-cells = <1>;
+   atmel,smc = <>;
+   microchip,sfr = <>;
+   reg = <0x1000 0x6000>;
+   ranges = <0x0 0x0 0x1000 0x1000
+ 0x1 0x0 0x2000 0x1000
+ 0x2 0x0 0x3000 0x1000
+ 0x3 0x0 0x4000 0x1000
+ 0x4 0x0 0x5000 0x1000
+ 0x5 0x0 0x6000 0x1000>;
+   clocks = < PMC_TYPE_CORE 11>;
+   status = "disabled";
+
+   nand_controller: nand-controller {
+   compatible = 
"microchip,sam9x60-nand-controller";
+   ecc-engine = <>;
+   #address-cells = <2>;
+   #size-cells = <1>;
+   ranges;
+   status = "disabled";
+   };
+   };
+
sdhci0: sdhci-host@8000 {
compatible = "microchip,sam9x60-sdhci";
reg = <0x8000 0x300>;
@@ -119,6 +145,11 @@
status = "disabled";
};
 
+   sfr: sfr@f805 {
+   compatible = "microchip,sam9x60-sfr", "syscon";
+   reg = <0xf805 0x100>;
+   };
+
dbgu: serial@f200 {
compatible = "atmel,at91sam9260-dbgu", 
"atmel,at91sam9260-usart";
reg = <0xf200 0x200>;
@@ -182,6 +213,17 @@
};
};
 
+   pmecc: ecc-engine@e000 {
+   compatible = "microchip,sam9x60-pmecc", 
"atmel,at91sam9g45-pmecc";
+   reg = <0xe000 0x300>,
+ <0xe600 0x100>;
+   };
+
+   smc: smc@ea00 {
+   compatible = "microchip,sam9x60-smc", 
"atmel,at91sam9260-smc", "syscon";
+   reg = <0xea00 0x100>;
+   };
+
pioA: gpio@f400 {
compatible = "atmel,at91sam9x5-gpio", 
"atmel,at91rm9200-gpio";
reg = <0xf400 0x200>;
-- 
2.25.1

[PATCH v3 6/9] configs: at91: sam9x60ek: Enable DM based nand driver

[Balamanikandan Gunasundar]

Enable Device model supported NAND driver and remove legacy Atmel NAND
driver.

Signed-off-by: Balamanikandan Gunasundar 

---
 configs/sam9x60ek_mmc_defconfig   | 9 ++---
 configs/sam9x60ek_nandflash_defconfig | 9 ++---
 configs/sam9x60ek_qspiflash_defconfig | 8 +---
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig
index 20b27649bf..94cd2eae51 100644
--- a/configs/sam9x60ek_mmc_defconfig
+++ b/configs/sam9x60ek_mmc_defconfig
@@ -52,6 +52,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_FAT=y
 CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
@@ -61,15 +63,16 @@ CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MICROCHIP_FLEXCOM=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ATMEL=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
-CONFIG_NAND_ATMEL=y
-CONFIG_ATMEL_NAND_HW_PMECC=y
-CONFIG_PMECC_CAP=8
+CONFIG_DM_NAND_ATMEL=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=5000
diff --git a/configs/sam9x60ek_nandflash_defconfig 
b/configs/sam9x60ek_nandflash_defconfig
index 8a7f2e0641..e5757d55cc 100644
--- a/configs/sam9x60ek_nandflash_defconfig
+++ b/configs/sam9x60ek_nandflash_defconfig
@@ -54,6 +54,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_NAND=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
@@ -63,14 +65,15 @@ CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MICROCHIP_FLEXCOM=y
 CONFIG_GENERIC_ATMEL_MCI=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
 # CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_ATMEL_NAND_HW_PMECC=y
-CONFIG_PMECC_CAP=8
+CONFIG_DM_NAND_ATMEL=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SF_DEFAULT_SPEED=5000
diff --git a/configs/sam9x60ek_qspiflash_defconfig 
b/configs/sam9x60ek_qspiflash_defconfig
index 51449f0233..14a8f63bc7 100644
--- a/configs/sam9x60ek_qspiflash_defconfig
+++ b/configs/sam9x60ek_qspiflash_defconfig
@@ -54,6 +54,8 @@ CONFIG_OF_CONTROL=y
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_SPI_MAX_HZ=5000
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
 CONFIG_CLK=y
 CONFIG_CLK_CCF=y
 CONFIG_CLK_AT91=y
@@ -63,6 +65,8 @@ CONFIG_CPU=y
 CONFIG_AT91_GPIO=y
 CONFIG_DM_I2C=y
 CONFIG_SYS_I2C_AT91=y
+CONFIG_ATMEL_EBI=y
+CONFIG_MFD_ATMEL_SMC=y
 CONFIG_I2C_EEPROM=y
 CONFIG_MICROCHIP_FLEXCOM=y
 CONFIG_GENERIC_ATMEL_MCI=y
@@ -70,9 +74,7 @@ CONFIG_MTD=y
 CONFIG_DM_MTD=y
 CONFIG_MTD_RAW_NAND=y
 # CONFIG_SYS_NAND_USE_FLASH_BBT is not set
-CONFIG_NAND_ATMEL=y
-CONFIG_ATMEL_NAND_HW_PMECC=y
-CONFIG_PMECC_CAP=8
+CONFIG_DM_NAND_ATMEL=y
 CONFIG_SYS_NAND_ONFI_DETECTION=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_MACRONIX=y
-- 
2.25.1

[PATCH v3 4/9] memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver

[Balamanikandan Gunasundar]

The EBI is used to access peripherals like NAND, SRAM, NOR etc. Add
this driver to probe the nand flash controller. This is a dummy driver
and not yet a complete device driver for EBI.

Signed-off-by: Balamanikandan Gunasundar 

---
 MAINTAINERS|  1 +
 drivers/memory/Kconfig |  7 +++
 drivers/memory/Makefile|  1 +
 drivers/memory/atmel_ebi.c | 37 +
 4 files changed, 46 insertions(+)
 create mode 100644 drivers/memory/atmel_ebi.c

diff --git a/MAINTAINERS b/MAINTAINERS
index cb4d44584d..d06d9dc6f5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -393,6 +393,7 @@ T:  git 
https://source.denx.de/u-boot/custodians/u-boot-atmel.git
 F: arch/arm/mach-at91/
 F: board/atmel/
 F: drivers/cpu/at91_cpu.c
+F: drivers/memory/atmel-ebi.c
 F: drivers/misc/microchip_flexcom.c
 F: drivers/timer/atmel_tcb_timer.c
 F: include/dt-bindings/mfd/atmel-flexcom.h
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 7271892763..759151a452 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -24,4 +24,11 @@ config TI_AEMIF
  of 256M bytes of any of these memories can be accessed at a given
  time via four chip selects with 64M byte access per chip select.
 
+config ATMEL_EBI
+   bool "Support for Atmel EBI"
+   help
+ Driver for Atmel EBI controller. This is a dummy
+ driver. Doesn't provide an access to EBI controller. Select
+ this option to enable the NAND flash controller driver
+
 endmenu
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index fec52efb60..1d24009e86 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -1,3 +1,4 @@
 
 obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
+obj-$(CONFIG_ATMEL_EBI) += atmel_ebi.o
 obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
diff --git a/drivers/memory/atmel_ebi.c b/drivers/memory/atmel_ebi.c
new file mode 100644
index 00..4739eef1b7
--- /dev/null
+++ b/drivers/memory/atmel_ebi.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+static int atmel_ebi_probe(struct udevice *dev)
+{
+   int ret;
+   struct udevice *ndev;
+
+   ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(atmel_nand_controller),
+ );
+   if (ret)
+   printf("Failed to probe nand driver (err = %d)\n", ret);
+
+   return ret;
+}
+
+static const struct udevice_id atmel_ebi_match[] = {
+   {.compatible = "microchip,sam9x60-ebi"},
+   {.compatible = "atmel,sama5d3-ebi"},
+   { /* Sentinel */ }
+};
+
+U_BOOT_DRIVER(atmel_ebi) = {
+   .name = "atmel_ebi",
+   .id = UCLASS_NOP,
+   .of_match = atmel_ebi_match,
+   .probe = atmel_ebi_probe,
+   .bind = dm_scan_fdt_dev,
+};
-- 
2.25.1

[PATCH v3 2/9] nand: atmel: Add pmecc driver

[Balamanikandan Gunasundar]

Add driver for atmel pmecc. This implementation is ported from
Linux. The reference taken is linux-5.4-at91.

Signed-off-by: Balamanikandan Gunasundar 

---
 drivers/mtd/nand/raw/atmel/Makefile |   3 +-
 drivers/mtd/nand/raw/atmel/pmecc.c  | 965 
 drivers/mtd/nand/raw/atmel/pmecc.h  |  94 +++
 3 files changed, 1061 insertions(+), 1 deletion(-)
 create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c
 create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h

diff --git a/drivers/mtd/nand/raw/atmel/Makefile 
b/drivers/mtd/nand/raw/atmel/Makefile
index 6708416983..e044ff55ba 100644
--- a/drivers/mtd/nand/raw/atmel/Makefile
+++ b/drivers/mtd/nand/raw/atmel/Makefile
@@ -1,4 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_DM_NAND_ATMEL)+= atmel-nand-controller.o
+obj-$(CONFIG_DM_NAND_ATMEL)+= atmel-nand-controller.o atmel-pmecc.o
 
 atmel-nand-controller-objs := nand-controller.o
+atmel-pmecc-objs   := pmecc.o
diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c 
b/drivers/mtd/nand/raw/atmel/pmecc.c
new file mode 100644
index 00..e2e3f1ee6b
--- /dev/null
+++ b/drivers/mtd/nand/raw/atmel/pmecc.c
@@ -0,0 +1,965 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2017 ATMEL
+ * Copyright 2017 Free Electrons
+ *
+ * Author: Boris Brezillon 
+ *
+ * Derived from the atmel_nand.c driver which contained the following
+ * copyrights:
+ *
+ *   Copyright 2003 Rick Bronson
+ *
+ *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
+ * Copyright 2001 Thomas Gleixner (gleix...@autronix.de)
+ *
+ *   Derived from drivers/mtd/spia.c (removed in v3.8)
+ * Copyright 2000 Steven J. Hill (sjh...@cotw.com)
+ *
+ *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
+ * Richard Genoud (richard.gen...@gmail.com), Adeneo Copyright 2007
+ *
+ *   Derived from Das U-Boot source code
+ * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
+ *  Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ *   Add Programmable Multibit ECC support for various AT91 SoC
+ * Copyright 2012 ATMEL, Hong Xu
+ *
+ *   Add Nand Flash Controller support for SAMA5 SoC
+ * Copyright 2013 ATMEL, Josh Wu (josh...@atmel.com)
+ *
+ * The PMECC is an hardware assisted BCH engine, which means part of the
+ * ECC algorithm is left to the software. The hardware/software repartition
+ * is explained in the "PMECC Controller Functional Description" chapter in
+ * Atmel datasheets, and some of the functions in this file are directly
+ * implementing the algorithms described in the "Software Implementation"
+ * sub-section.
+ *
+ * TODO: it seems that the software BCH implementation in lib/bch.c is already
+ * providing some of the logic we are implementing here. It would be smart
+ * to expose the needed lib/bch.c helpers/functions and re-use them here.
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "pmecc.h"
+#include 
+#include 
+#include 
+#include 
+
+/* Galois field dimension */
+#define PMECC_GF_DIMENSION_13  13
+#define PMECC_GF_DIMENSION_14  14
+
+/* Primitive Polynomial used by PMECC */
+#define PMECC_GF_13_PRIMITIVE_POLY 0x201b
+#define PMECC_GF_14_PRIMITIVE_POLY 0x4443
+
+#define PMECC_LOOKUP_TABLE_SIZE_5120x2000
+#define PMECC_LOOKUP_TABLE_SIZE_1024   0x4000
+
+/* Time out value for reading PMECC status register */
+#define PMECC_MAX_TIMEOUT_MS   100
+
+/* PMECC Register Definitions */
+#define ATMEL_PMECC_CFG0x0
+#define PMECC_CFG_BCH_STRENGTH(x)  (x)
+#define PMECC_CFG_BCH_STRENGTH_MASKGENMASK(2, 0)
+#define PMECC_CFG_SECTOR512(0 << 4)
+#define PMECC_CFG_SECTOR1024   BIT(4)
+#define PMECC_CFG_NSECTORS(x)  ((fls(x) - 1) << 8)
+#define PMECC_CFG_READ_OP  (0 << 12)
+#define PMECC_CFG_WRITE_OP BIT(12)
+#define PMECC_CFG_SPARE_ENABLE BIT(16)
+#define PMECC_CFG_AUTO_ENABLE  BIT(20)
+
+#define ATMEL_PMECC_SAREA  0x4
+#define ATMEL_PMECC_SADDR  0x8
+#define ATMEL_PMECC_EADDR  0xc
+
+#define ATMEL_PMECC_CLK0x10
+#define PMECC_CLK_133MHZ   (2 << 0)
+
+#define ATMEL_PMECC_CTRL   0x14
+#define PMECC_CTRL_RST BIT(0)
+#define PMECC_CTRL_DATABIT(1)
+#define PMECC_CTRL_USERBIT(2)
+#define PMECC_CTRL_ENABLE  BIT(4)
+#define PMECC_CTRL_DISABLE BIT(5)
+
+#define ATMEL_PMECC_SR 0x18
+#define PMECC_SR_BUSY  BIT(0)
+#define PMECC_SR_ENABLEBIT(4)
+
+#define ATMEL_PMECC_IER0x1c
+#define ATMEL_PMECC_IDR 

[PATCH v3 3/9] mfd: syscon: Add atmel-matrix registers definition

[Balamanikandan Gunasundar]

This file is copied from Linux. AT91 SoCs have a memory range reserved
for internal bus configuration. Expose those registers so that drivers
can make use of the matrix syscon declared in at91 DTs.

Signed-off-by: Balamanikandan Gunasundar 

---
 include/linux/mfd/syscon/atmel-matrix.h | 112 
 1 file changed, 112 insertions(+)
 create mode 100644 include/linux/mfd/syscon/atmel-matrix.h

diff --git a/include/linux/mfd/syscon/atmel-matrix.h 
b/include/linux/mfd/syscon/atmel-matrix.h
new file mode 100644
index 00..dd228cab67
--- /dev/null
+++ b/include/linux/mfd/syscon/atmel-matrix.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ *  Copyright (C) 2014 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ */
+
+#ifndef _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+#define _LINUX_MFD_SYSCON_ATMEL_MATRIX_H
+
+#define AT91SAM9260_MATRIX_MCFG0x00
+#define AT91SAM9260_MATRIX_SCFG0x40
+#define AT91SAM9260_MATRIX_PRS 0x80
+#define AT91SAM9260_MATRIX_MRCR0x100
+#define AT91SAM9260_MATRIX_EBICSA  0x11c
+
+#define AT91SAM9261_MATRIX_MRCR0x0
+#define AT91SAM9261_MATRIX_SCFG0x4
+#define AT91SAM9261_MATRIX_TCR 0x24
+#define AT91SAM9261_MATRIX_EBICSA  0x30
+#define AT91SAM9261_MATRIX_USBPUCR 0x34
+
+#define AT91SAM9263_MATRIX_MCFG0x00
+#define AT91SAM9263_MATRIX_SCFG0x40
+#define AT91SAM9263_MATRIX_PRS 0x80
+#define AT91SAM9263_MATRIX_MRCR0x100
+#define AT91SAM9263_MATRIX_TCR 0x114
+#define AT91SAM9263_MATRIX_EBI0CSA 0x120
+#define AT91SAM9263_MATRIX_EBI1CSA 0x124
+
+#define AT91SAM9RL_MATRIX_MCFG 0x00
+#define AT91SAM9RL_MATRIX_SCFG 0x40
+#define AT91SAM9RL_MATRIX_PRS  0x80
+#define AT91SAM9RL_MATRIX_MRCR 0x100
+#define AT91SAM9RL_MATRIX_TCR  0x114
+#define AT91SAM9RL_MATRIX_EBICSA   0x120
+
+#define AT91SAM9G45_MATRIX_MCFG0x00
+#define AT91SAM9G45_MATRIX_SCFG0x40
+#define AT91SAM9G45_MATRIX_PRS 0x80
+#define AT91SAM9G45_MATRIX_MRCR0x100
+#define AT91SAM9G45_MATRIX_TCR 0x110
+#define AT91SAM9G45_MATRIX_DDRMPR  0x118
+#define AT91SAM9G45_MATRIX_EBICSA  0x128
+
+#define AT91SAM9N12_MATRIX_MCFG0x00
+#define AT91SAM9N12_MATRIX_SCFG0x40
+#define AT91SAM9N12_MATRIX_PRS 0x80
+#define AT91SAM9N12_MATRIX_MRCR0x100
+#define AT91SAM9N12_MATRIX_EBICSA  0x118
+
+#define AT91SAM9X5_MATRIX_MCFG 0x00
+#define AT91SAM9X5_MATRIX_SCFG 0x40
+#define AT91SAM9X5_MATRIX_PRS  0x80
+#define AT91SAM9X5_MATRIX_MRCR 0x100
+#define AT91SAM9X5_MATRIX_EBICSA   0x120
+
+#define SAMA5D3_MATRIX_MCFG0x00
+#define SAMA5D3_MATRIX_SCFG0x40
+#define SAMA5D3_MATRIX_PRS 0x80
+#define SAMA5D3_MATRIX_MRCR0x100
+
+#define AT91_MATRIX_MCFG(o, x) ((o) + ((x) * 0x4))
+#define AT91_MATRIX_ULBT   GENMASK(2, 0)
+#define AT91_MATRIX_ULBT_INFINITE  (0 << 0)
+#define AT91_MATRIX_ULBT_SINGLE(1 << 0)
+#define AT91_MATRIX_ULBT_FOUR  (2 << 0)
+#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91_MATRIX_ULBT_SIXTEEN   (4 << 0)
+
+#define AT91_MATRIX_SCFG(o, x) ((o) + ((x) * 0x4))
+#define AT91_MATRIX_SLOT_CYCLE GENMASK(7,  0)
+#define AT91_MATRIX_DEFMSTR_TYPE   GENMASK(17, 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_NONE  (0 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_LAST  (1 << 16)
+#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91_MATRIX_FIXED_DEFMSTR  GENMASK(20, 18)
+#define AT91_MATRIX_ARBT   GENMASK(25, 24)
+#define AT91_MATRIX_ARBT_ROUND_ROBIN   (0 << 24)
+#define AT91_MATRIX_ARBT_FIXED_PRIORITY(1 << 24)
+
+#define AT91_MATRIX_ITCM_SIZE  GENMASK(3, 0)
+#define AT91_MATRIX_ITCM_0 (0 << 0)
+#define AT91_MATRIX_ITCM_16(5 << 0)
+#define AT91_MATRIX_ITCM_32(6 << 0)
+#define AT91_MATRIX_ITCM_64(7 << 0)
+#defineAT91_MATRIX_DTCM_SIZE   GENMASK(7, 4)
+#defineAT91_MATRIX_DTCM_0  (0 << 4)
+#defineAT91_MATRIX_DTCM_16 (5 << 4)
+#define AT91_MATRIX_DTCM_32(6 << 4)
+#define AT91_MATRIX_DTCM_64

[PATCH v3 1/9] nand: atmel: Add DM based NAND driver

[Balamanikandan Gunasundar]

This implementation is ported from the rework done by Boris Brezillon
in Linux. This porting is done based on linux-5.4-at91. The driver is
tested in sam9x60ek, sama5d3_xplained, sam9x75eb and sama7g54-ddr3-eb.

Changes done includes

- Adapt GPIO descriptor apis for U-Boot. Use gpio_request_by_name_nodev,
  dm_gpio_get_value etc.
- Use U_BOOT_DRIVER instead of platform_driver.
- Replace struct platform_device with struct udevice
- Check the status of nfc exec operation by polling the status
  register instead of interrupt based handling
- DMA operations not supported. Remove it
- Adapt DT parsing to U-Boot APIs

Signed-off-by: Balamanikandan Gunasundar 


Signed-off-by: Balamanikandan Gunasundar 

---
 drivers/mtd/nand/raw/Kconfig |8 +
 drivers/mtd/nand/raw/Makefile|1 +
 drivers/mtd/nand/raw/atmel/Makefile  |4 +
 drivers/mtd/nand/raw/atmel/nand-controller.c | 2286 ++
 4 files changed, 2299 insertions(+)
 create mode 100644 drivers/mtd/nand/raw/atmel/Makefile
 create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c

diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index ce67d1abde..4d023e2893 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -37,6 +37,14 @@ config SYS_NAND_USE_FLASH_BBT
help
  Enable the BBT (Bad Block Table) usage.
 
+config DM_NAND_ATMEL
+   bool "Support Atmel NAND controller with DM support"
+   select SYS_NAND_SELF_INIT
+   imply SYS_NAND_USE_FLASH_BBT
+   help
+ Enable this driver for NAND flash platforms using an Atmel NAND
+ controller.
+
 config NAND_ATMEL
bool "Support Atmel NAND controller"
select SYS_NAND_SELF_INIT
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index a398aa9d88..42c1fb25b4 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -48,6 +48,7 @@ ifdef NORMAL_DRIVERS
 obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
 
 obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
+obj-$(CONFIG_DM_NAND_ATMEL) += atmel/
 obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
 obj-$(CONFIG_NAND_BRCMNAND) += brcmnand/
 obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
diff --git a/drivers/mtd/nand/raw/atmel/Makefile 
b/drivers/mtd/nand/raw/atmel/Makefile
new file mode 100644
index 00..6708416983
--- /dev/null
+++ b/drivers/mtd/nand/raw/atmel/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_DM_NAND_ATMEL)+= atmel-nand-controller.o
+
+atmel-nand-controller-objs := nand-controller.o
diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c 
b/drivers/mtd/nand/raw/atmel/nand-controller.c
new file mode 100644
index 00..9873d11254
--- /dev/null
+++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
@@ -0,0 +1,2286 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 ATMEL
+ * Copyright 2017 Free Electrons
+ *
+ * Author: Boris Brezillon 
+ *
+ * Derived from the atmel_nand.c driver which contained the following
+ * copyrights:
+ *
+ *   Copyright 2003 Rick Bronson
+ *
+ *   Derived from drivers/mtd/nand/autcpu12.c (removed in v3.8)
+ * Copyright 2001 Thomas Gleixner (gleix...@autronix.de)
+ *
+ *   Derived from drivers/mtd/spia.c (removed in v3.8)
+ * Copyright 2000 Steven J. Hill (sjh...@cotw.com)
+ *
+ *
+ *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
+ * Richard Genoud (richard.gen...@gmail.com), Adeneo Copyright 2007
+ *
+ *   Derived from Das U-Boot source code
+ * (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
+ * Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
+ *
+ *   Add Programmable Multibit ECC support for various AT91 SoC
+ * Copyright 2012 ATMEL, Hong Xu
+ *
+ *   Add Nand Flash Controller support for SAMA5 SoC
+ * Copyright 2013 ATMEL, Josh Wu (josh...@atmel.com)
+ *
+ *   Port from Linux
+ * Balamanikandan Gunasundar(balamanikandan.gunasun...@microchip.com)
+ * Copyright (C) 2022 Microchip Technology Inc.
+ *
+ * A few words about the naming convention in this file. This convention
+ * applies to structure and function names.
+ *
+ * Prefixes:
+ *
+ * - atmel_nand_: all generic structures/functions
+ * - atmel_smc_nand_: all structures/functions specific to the SMC interface
+ *   (at91sam9 and avr32 SoCs)
+ * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
+ *(sama5 SoCs and later)
+ * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
+ *  that is available in the HSMC block
+ * - _nand_: all SoC specific structures/functions
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "pmecc.h"
+
+#define NSEC_PER_SEC10L
+
+#define ATMEL_HSMC_NFC_CFG 

[PATCH v3 0/9] Add DM support for atmel NAND driver

[Balamanikandan Gunasundar]

Change include:

- Adapt GPIO descriptor apis for U-Boot. Use
  gpio_request_by_name_nodev, dm_gpio_get_value etc.
- Use U_BOOT_DRIVER instead of platform_driver.
- Replace struct platform_device with struct udevice
- Check the status of nfc exec operation by polling the status
  register instead of interrupt based handling
- DMA operations not supported. Remove it
- Adapt DT parsing to U-Boot APIs

Note:

I need some advise or help in alligning the DT with Linux as per the
discussion.
https://lore.kernel.org/all/CABGWkvoLDez=ywzpxgo2s+gvs0audceuaysa8zo_+wgvf4l...@mail.gmail.com/

v3:

- Do not check return values while requesting optional gpio pins
  (cs-gpios and rb-gpios)
- Commit message for adding SMC helper function reworded
- The unwanted indentation in the DT is fixed. The changes are made on
  top of "275943dba4 ARM: dts: at91: sam9x60ek: fix indentation for
  pinctrl sub-nodes"

v2:

- Add linux reference version in the commit message from which the
  driver is ported from
- Reword the commit message to describe the changes clearly

Balamanikandan Gunasundar (9):
  nand: atmel: Add DM based NAND driver
  nand: atmel: Add pmecc driver
  mfd: syscon: Add atmel-matrix registers definition
  memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver
  mfd: syscon: atmel-smc: Add new helpers to ease SMC regs manipulation
  configs: at91: sam9x60ek: Enable DM based nand driver
  ARM: dts: at91: sam9x60: Add nodes for EBI and NAND
  ARM: dts: at91: sam9x60ek: Enable NAND support
  board: sam9x60ek: remove nand init from board file

 MAINTAINERS  |1 +
 arch/arm/dts/sam9x60.dtsi|   42 +
 arch/arm/dts/sam9x60ek.dts   |  103 +
 board/atmel/sam9x60ek/sam9x60ek.c|   59 -
 configs/sam9x60ek_mmc_defconfig  |9 +-
 configs/sam9x60ek_nandflash_defconfig|9 +-
 configs/sam9x60ek_qspiflash_defconfig|8 +-
 drivers/Kconfig  |2 +
 drivers/Makefile |1 +
 drivers/memory/Kconfig   |7 +
 drivers/memory/Makefile  |1 +
 drivers/memory/atmel_ebi.c   |   37 +
 drivers/mfd/Kconfig  |4 +
 drivers/mfd/Makefile |1 +
 drivers/mfd/atmel-smc.c  |  364 +++
 drivers/mtd/nand/raw/Kconfig |8 +
 drivers/mtd/nand/raw/Makefile|1 +
 drivers/mtd/nand/raw/atmel/Makefile  |5 +
 drivers/mtd/nand/raw/atmel/nand-controller.c | 2286 ++
 drivers/mtd/nand/raw/atmel/pmecc.c   |  965 
 drivers/mtd/nand/raw/atmel/pmecc.h   |   94 +
 include/configs/sam9x60ek.h  |5 -
 include/linux/mfd/syscon/atmel-matrix.h  |  112 +
 include/linux/mfd/syscon/atmel-smc.h |  119 +
 24 files changed, 4170 insertions(+), 73 deletions(-)
 create mode 100644 drivers/memory/atmel_ebi.c
 create mode 100644 drivers/mfd/Kconfig
 create mode 100644 drivers/mfd/Makefile
 create mode 100644 drivers/mfd/atmel-smc.c
 create mode 100644 drivers/mtd/nand/raw/atmel/Makefile
 create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c
 create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c
 create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h
 create mode 100644 include/linux/mfd/syscon/atmel-matrix.h
 create mode 100644 include/linux/mfd/syscon/atmel-smc.h

-- 
2.25.1

Re: [PATCH v6 03/10] arm_ffa: introduce Arm FF-A low-level driver

[Abdellatif El Khlifi]

On Tue, Oct 25, 2022 at 11:31:11AM +0200, Jens Wiklander wrote:
> On Thu, Oct 13, 2022 at 11:38:50AM +0100, Abdellatif El Khlifi wrote:
> > Add the core driver implementing Arm Firmware Framework for Armv8-A v1.0
> > 
> > The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
> > describes interfaces (ABIs) that standardize communication
> > between the Secure World and Normal World leveraging TrustZone
> > technology.
> > 
> > This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
> > on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
> > querying the FF-A framework from the secure world.
> > 
> > 32-bit version of the ABIs is supported and 64-bit version of FFA_RXTX_MAP
> > and FFA_MSG_SEND_DIRECT_{REQ, RESP}.
> > 
> > In u-boot FF-A design, FF-A is considered as a discoverable bus.
> 
> U-Boot
> 
> > The Secure World is considered as one entity to communicate with
> > using the FF-A bus. FF-A communication is handled by one device and
> > one instance (the bus). This FF-A driver takes care of all the
> > interactions between Normal world and Secure World.
> > 
> > The driver exports its operations to be used by upper layers.
> > 
> > Exported operations:
> > 
> > - partition_info_get
> > - sync_send_receive
> > - rxtx_unmap
> > 
> > [1]: https://developer.arm.com/documentation/den0077/latest/
> > 
> > Signed-off-by: Abdellatif El Khlifi 
> > Cc: Tom Rini 
> > Cc: Simon Glass 
> > Cc: Ilias Apalodimas 
> > Cc: Jens Wiklander 
> > 
> > ---
> > 
> > Changelog:
> > ===
> > 
> > v6:
> > 
> > * drop use of EFI runtime support (We decided with Linaro to add this later)
> > * drop discovery from initcalls (discovery will be on demand by FF-A users)
> > * set the alignment of the RX/TX buffers to the larger translation granule 
> > size
> > * move FF-A RX/TX buffers unmapping at ExitBootServices() to a separate 
> > commit
> > * update the documentation and move it to doc/arch/arm64.ffa.rst
> > 
> > v4:
> > 
> > * add doc/README.ffa.drv
> > * moving the FF-A driver work to drivers/firmware/arm-ffa
> > * use less #ifdefs in lib/efi_loader/efi_boottime.c and replace
> >   #if defined by #if CONFIG_IS_ENABLED
> > * improving error handling by mapping the FF-A errors to standard errors
> >   and logs
> > * replacing panics with an error log and returning an error code
> > * improving features discovery in FFA_FEATURES by introducing
> >   rxtx_min_pages private data field
> > * add ffa_remove and ffa_unbind functions
> > * improve how the driver behaves when bus discovery is done more than
> >   once
> > 
> > v3:
> > 
> > * align the interfaces of the u-boot FF-A driver with those in the linux
> >   FF-A driver
> > * remove the FF-A helper layer
> > * make the u-boot FF-A driver independent from EFI
> > * provide an optional config that enables copying the driver data to EFI
> >   runtime section at ExitBootServices service
> > * use 64-bit version of FFA_RXTX_MAP, FFA_MSG_SEND_DIRECT_{REQ, RESP}
> > 
> > v2:
> > 
> > * make FF-A bus discoverable using device_{bind, probe} APIs
> > * remove device tree support
> > 
> > v1:
> > 
> > * introduce FF-A bus driver with device tree support
> > 
> >  MAINTAINERS   |7 +
> >  doc/arch/arm64.ffa.rst|  207 
> >  doc/arch/index.rst|1 +
> >  drivers/Kconfig   |2 +
> >  drivers/Makefile  |1 +
> >  drivers/firmware/arm-ffa/Kconfig  |   30 +
> >  drivers/firmware/arm-ffa/Makefile |6 +
> >  drivers/firmware/arm-ffa/arm-ffa-uclass.c |   16 +
> >  drivers/firmware/arm-ffa/arm_ffa_prv.h|  196 +++
> >  drivers/firmware/arm-ffa/core.c   | 1337 +
> >  include/arm_ffa.h |   93 ++
> >  include/dm/uclass-id.h|4 +
> >  12 files changed, 1900 insertions(+)
> >  create mode 100644 doc/arch/arm64.ffa.rst
> >  create mode 100644 drivers/firmware/arm-ffa/Kconfig
> >  create mode 100644 drivers/firmware/arm-ffa/Makefile
> >  create mode 100644 drivers/firmware/arm-ffa/arm-ffa-uclass.c
> >  create mode 100644 drivers/firmware/arm-ffa/arm_ffa_prv.h
> >  create mode 100644 drivers/firmware/arm-ffa/core.c
> >  create mode 100644 include/arm_ffa.h
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index a26b36c7c2..496f47a516 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -248,6 +248,13 @@ F: drivers/net/cortina_ni.h
> >  F: drivers/net/phy/ca_phy.c
> >  F: configs/cortina_presidio-asic-pnand_defconfig
> >  
> > +ARM FF-A
> > +M: Abdellatif El Khlifi 
> > +S: Maintained
> > +F: doc/arch/arm64.ffa.rst
> > +F: drivers/firmware/arm-ffa/
> > +F: include/arm_ffa.h
> > +
> >  ARM FREESCALE IMX
> >  M: Stefano Babic 
> >  M: Fabio Estevam 
> > diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
> > new file mode 100644
> > index 00..e98d2cf2b3
> > --- /dev/null
> > +++ 

RE: [PATCH v5 4/5] drivers: power: pmic: Enable use of rn5t567 PMIC in SPL

[Jaehoon Chung]

> -Original Message-
> From: Martyn Welch [mailto:martyn.we...@collabora.com]
> Sent: Tuesday, October 25, 2022 6:55 PM
> To: uboot-...@nxp.com; sba...@denx.de; Jaehoon Chung 
> Cc: Martyn Welch ; Simon Glass 
> ; u-
> b...@lists.denx.de
> Subject: [PATCH v5 4/5] drivers: power: pmic: Enable use of rn5t567 PMIC in 
> SPL
> 
> From: Martyn Welch 
> 
> The support added later in this series tweaks the PMIC voltages in the
> SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
> cleanly.
> 
> Signed-off-by: Martyn Welch 
> Reviewed-by: Simon Glass 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v3:
>  - New patch (replaces addition of legacy support for rn5t567)
> 
> Changes in v4:
>  - None
> 
> Changes in v5:
>  - Rebase to current master branch
> 
>  drivers/power/pmic/Kconfig  | 8 
>  drivers/power/pmic/Makefile | 2 +-
>  2 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
> index 0478f2aa1d..628d3a94bc 100644
> --- a/drivers/power/pmic/Kconfig
> +++ b/drivers/power/pmic/Kconfig
> @@ -300,6 +300,14 @@ config PMIC_RN5T567
>   regulators Real-Time Clock and 4 GPIOs. This driver provides
>   register access only.
> 
> +config SPL_PMIC_RN5T567
> + bool "Enable driver for Ricoh RN5T567 PMIC in SPL"
> + depends on SPL_DM_PMIC
> + ---help---
> + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
> + regulators Real-Time Clock and 4 GPIOs. This driver provides
> + register access only.
> +
>  config PMIC_TPS65090
>   bool "Enable driver for Texas Instruments TPS65090 PMIC"
>   ---help---
> diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
> index e1d3545490..58c6507c58 100644
> --- a/drivers/power/pmic/Makefile
> +++ b/drivers/power/pmic/Makefile
> @@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o
>  obj-$(CONFIG_PMIC_MAX8997) += max8997.o
>  obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o
>  obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o
> -obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
> +obj-$(CONFIG_$(SPL_)PMIC_RN5T567) += rn5t567.o
>  obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
>  obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
>  obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
> --
> 2.35.1

RE: [PATCH v5 3/5] drivers: power: pmic: Add support for rn5t568 PMIC

[Jaehoon Chung]

> -Original Message-
> From: Martyn Welch [mailto:martyn.we...@collabora.com]
> Sent: Tuesday, October 25, 2022 6:55 PM
> To: uboot-...@nxp.com; sba...@denx.de; Jaehoon Chung 
> Cc: Martyn Welch ; u-boot@lists.denx.de
> Subject: [PATCH v5 3/5] drivers: power: pmic: Add support for rn5t568 PMIC
> 
> Add support for the rn5t568 PMIC to the rn5t567 driver.
> 
> Signed-off-by: Martyn Welch 

Reviewed-by: Jaehoon Chung 

Best Regards,
Jaehoon Chung

> ---
> 
> Changes in v2:
>  - None
> 
> Changes in v3:
>  - None
> 
> Changes in v4:
>  - None
> 
> Changes in v5:
>  - None
> 
>  drivers/power/pmic/rn5t567.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c
> index d9a8298ebb..9d103dd840 100644
> --- a/drivers/power/pmic/rn5t567.c
> +++ b/drivers/power/pmic/rn5t567.c
> @@ -53,6 +53,7 @@ static struct dm_pmic_ops rn5t567_ops = {
> 
>  static const struct udevice_id rn5t567_ids[] = {
>   { .compatible = "ricoh,rn5t567" },
> + { .compatible = "ricoh,rn5t568" },
>   { }
>  };
> 
> --
> 2.35.1

Re: [PATCH 1/2] net:xilinx_axi: add PCS/PMA PHY

[Michal Simek]

Please add one more space in subject.
net:xilinx_axi: add PCS/PMA PHY

On 10/17/22 13:19, Andy Chiu wrote:

If we bridge an external PHY to Xilinx's PCS/PMA PHY and would like to
get and set the real status of the PHY facing the external world. Then
we should phy_connect() to the external PHY instead of the PCS/PMA one.
Thus, we add a pcs-phy DT entry, which have been merged in Linux, and
leave the configuration of it to the driver itself.

Unlike Linux, where the PCS/PMA PHY is managed by phylink, managing the
PCS/PMA PHY is only internal to the driver in U-Boot. The PCS/PMA PHY
pressents only when the phy-mode is configured as SGMII or 1000Base-X,
so it is always 1 Gbps and full-duplex and we may skip passing link
information out.

Signed-off-by: Andy Chiu 
Reviewed-by: Greentime Hu 
---
  drivers/net/xilinx_axi_emac.c | 26 --
  1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index 04277b1269..447e1d4c9c 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -107,6 +107,7 @@ struct axidma_plat {
struct eth_pdata eth_pdata;
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
+   int pcsaddr;
int phyaddr;
u8 eth_hasnobuf;
int phy_of_handle;
@@ -117,6 +118,7 @@ struct axidma_plat {
  struct axidma_priv {
struct axidma_reg *dmatx;
struct axidma_reg *dmarx;
+   int pcsaddr;
int phyaddr;
struct axi_regs *iobase;
phy_interface_t interface;
@@ -299,6 +301,13 @@ static int axiemac_phy_init(struct udevice *dev)
if (IS_ENABLED(CONFIG_DM_ETH_PHY))
priv->phyaddr = eth_phy_get_addr(dev);
  
+	/*

+* Set address of PCS/PMA PHY to the one pointed by phy-handle for
+* backward compatibility.
+*/
+   if (priv->phyaddr != -1 && priv->pcsaddr == 0)
+   priv->pcsaddr = priv->phyaddr;
+
if (priv->phyaddr == -1) {
/* Detect the PHY address */
for (i = 31; i >= 0; i--) {
@@ -342,12 +351,12 @@ static int setup_phy(struct udevice *dev)
 * after DMA and ethernet resets and hence
 * check and clear if set.
 */
-   ret = phyread(priv, priv->phyaddr, MII_BMCR, );
+   ret = phyread(priv, priv->pcsaddr, MII_BMCR, );
if (ret)
return 0;
if (temp & BMCR_ISOLATE) {
temp &= ~BMCR_ISOLATE;
-   ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
+   ret = phywrite(priv, priv->pcsaddr, MII_BMCR, temp);
if (ret)
return 0;
}
@@ -778,6 +787,7 @@ static int axi_emac_probe(struct udevice *dev)
  
  	if (priv->mactype == EMAC_1G) {

priv->eth_hasnobuf = plat->eth_hasnobuf;
+   priv->pcsaddr = plat->pcsaddr;
priv->phyaddr = plat->phyaddr;
priv->phy_of_handle = plat->phy_of_handle;
priv->interface = pdata->phy_interface;
@@ -855,6 +865,8 @@ static int axi_emac_of_to_plat(struct udevice *dev)
  
  	if (plat->mactype == EMAC_1G) {

plat->phyaddr = -1;
+   /* PHYAD 0 always redirects to the PCS/PMA PHY */
+   plat->pcsaddr = 0;
  
  		offset = fdtdec_lookup_phandle(gd->fdt_blob, node,

   "phy-handle");
@@ -872,6 +884,16 @@ static int axi_emac_of_to_plat(struct udevice *dev)
  
  		plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,

 "xlnx,eth-hasnobuf");
+
+   if (pdata->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+   pdata->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+   offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
+  "pcs-phy");


Based on
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/net/xilinx_axienet.txt?h=v6.1-rc2#n72

you should be using pcs-handle instead of pcs-phy.

Thanks,
Michal

[PATCH v5 5/5] arm: imx8mp: Initial MSC SM2S iMX8MP support

[Martyn Welch]

Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.

Signed-off-by: Martyn Welch 
---

Changes in v2:
 - Renamed FDT to closer match kernel
 - Sync with kernel FDT
 - Update for changes made in U-Boot

Changes in v3:
 - Use imx8mp-u-boot.dtsi
 - Switch to use of DM PMIC support in SPL

Changes in v4:
 - Rebased to latest imx master branch

Changes in v5:
 - Rebased on latest master branch
 - Add MAINTAINERS entry
 - Migrate symbols to Kbuild config
 - Simplify header file

 MAINTAINERS   |9 +
 arch/arm/dts/Makefile |1 +
 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi  |   65 +
 arch/arm/dts/imx8mp-msc-sm2s.dts  |  820 
 arch/arm/mach-imx/imx8m/Kconfig   |8 +
 board/msc/sm2s_imx8mp/Kconfig |   15 +
 board/msc/sm2s_imx8mp/Makefile|   12 +
 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg |8 +
 board/msc/sm2s_imx8mp/lpddr4_timing.c | 1842 +
 board/msc/sm2s_imx8mp/sm2s_imx8mp.c   |   60 +
 board/msc/sm2s_imx8mp/spl.c   |  273 +++
 configs/msc_sm2s_imx8mp_defconfig |  105 +
 include/configs/msc_sm2s_imx8mp.h |   64 +
 13 files changed, 3282 insertions(+)
 create mode 100644 arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
 create mode 100644 arch/arm/dts/imx8mp-msc-sm2s.dts
 create mode 100644 board/msc/sm2s_imx8mp/Kconfig
 create mode 100644 board/msc/sm2s_imx8mp/Makefile
 create mode 100644 board/msc/sm2s_imx8mp/imximage-8mp-lpddr4.cfg
 create mode 100644 board/msc/sm2s_imx8mp/lpddr4_timing.c
 create mode 100644 board/msc/sm2s_imx8mp/sm2s_imx8mp.c
 create mode 100644 board/msc/sm2s_imx8mp/spl.c
 create mode 100644 configs/msc_sm2s_imx8mp_defconfig
 create mode 100644 include/configs/msc_sm2s_imx8mp.h

diff --git a/MAINTAINERS b/MAINTAINERS
index cb4d44584d..256e464aff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -398,6 +398,15 @@ F: drivers/timer/atmel_tcb_timer.c
 F: include/dt-bindings/mfd/atmel-flexcom.h
 F: drivers/timer/mchp-pit64b-timer.c
 
+ARM MSC SM2S IMX8MP SOM
+M: Martyn Welch 
+M: Ian Ray 
+S: Maintained
+F: arch/arm/dts/imx8mp-msc-sm2s*
+F: board/msc/sm2s_imx8mp/
+F: configs/msc_sm2s_imx8mp_defconfig
+F: include/configs/msc_sm2s_imx8mp.h
+
 ARM NEXELL S5P4418
 M: Stefan Bosch 
 S: Maintained
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 30e69b9f67..510b8afc02 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -976,6 +976,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
+   imx8mp-msc-sm2s.dtb \
imx8mp-phyboard-pollux-rdk.dtb \
imx8mp-venice.dtb \
imx8mp-venice-gw74xx.dtb \
diff --git a/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi 
b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
new file mode 100644
index 00..cf591adf5a
--- /dev/null
+++ b/arch/arm/dts/imx8mp-msc-sm2s-u-boot.dtsi
@@ -0,0 +1,65 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019 NXP
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+   model = "MSC SM2S-IMX8MPLUS";
+   compatible = "avnet,sm2s-imx8mp", "fsl,imx8mp";
+
+   wdt-reboot {
+   compatible = "wdt-reboot";
+   wdt = <>;
+   u-boot,dm-spl;
+   };
+};
+
+_usdhc2_vmmc {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
+
+_i2c6 {
+   u-boot,dm-spl;
+};
+
+ {
+   u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mp-msc-sm2s.dts b/arch/arm/dts/imx8mp-msc-sm2s.dts
new file mode 100644
index 00..5dbec71747
--- /dev/null
+++ b/arch/arm/dts/imx8mp-msc-sm2s.dts
@@ -0,0 +1,820 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022 Avnet Embedded GmbH
+ */
+
+/dts-v1/;
+
+#include "imx8mp.dtsi"
+#include 
+
+/ {
+   aliases {
+   rtc0 = _rtc;
+   rtc1 = _rtc;
+   };
+
+   chosen {
+   stdout-path = 
+   };
+
+   reg_usb0_host_vbus: regulator-usb0-vbus {
+   compatible = "regulator-fixed";
+   regulator-name = "usb0_host_vbus";
+   pinctrl-names = "default";
+   pinctrl-0 = <_usb0_vbus>;
+   regulator-min-microvolt = <500>;
+   regulator-max-microvolt = <500>;
+   gpio = < 12 GPIO_ACTIVE_HIGH>;
+   enable-active-high;
+   };
+
+   reg_usb1_host_vbus: regulator-usb1-vbus {
+   compatible = "regulator-fixed";
+   regulator-name = "usb1_host_vbus";
+   pinctrl-names = "default";
+

[PATCH v5 4/5] drivers: power: pmic: Enable use of rn5t567 PMIC in SPL

[Martyn Welch]

From: Martyn Welch 

The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.

Signed-off-by: Martyn Welch 
Reviewed-by: Simon Glass 
---

Changes in v3:
 - New patch (replaces addition of legacy support for rn5t567)

Changes in v4:
 - None

Changes in v5:
 - Rebase to current master branch

 drivers/power/pmic/Kconfig  | 8 
 drivers/power/pmic/Makefile | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index 0478f2aa1d..628d3a94bc 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -300,6 +300,14 @@ config PMIC_RN5T567
regulators Real-Time Clock and 4 GPIOs. This driver provides
register access only.
 
+config SPL_PMIC_RN5T567
+   bool "Enable driver for Ricoh RN5T567 PMIC in SPL"
+   depends on SPL_DM_PMIC
+   ---help---
+   The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO
+   regulators Real-Time Clock and 4 GPIOs. This driver provides
+   register access only.
+
 config PMIC_TPS65090
bool "Enable driver for Texas Instruments TPS65090 PMIC"
---help---
diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
index e1d3545490..58c6507c58 100644
--- a/drivers/power/pmic/Makefile
+++ b/drivers/power/pmic/Makefile
@@ -22,7 +22,7 @@ obj-$(CONFIG_$(SPL_)PMIC_AXP) += axp.o
 obj-$(CONFIG_PMIC_MAX8997) += max8997.o
 obj-$(CONFIG_PMIC_QCOM) += pmic_qcom.o
 obj-$(CONFIG_$(SPL_TPL_)PMIC_RK8XX) += rk8xx.o
-obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
+obj-$(CONFIG_$(SPL_)PMIC_RN5T567) += rn5t567.o
 obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
 obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o
 obj-$(CONFIG_DM_PMIC_TPS65910) += pmic_tps65910_dm.o
-- 
2.35.1

[PATCH v5 3/5] drivers: power: pmic: Add support for rn5t568 PMIC

[Martyn Welch]

Add support for the rn5t568 PMIC to the rn5t567 driver.

Signed-off-by: Martyn Welch 
---

Changes in v2:
 - None

Changes in v3:
 - None

Changes in v4:
 - None

Changes in v5:
 - None

 drivers/power/pmic/rn5t567.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567.c
index d9a8298ebb..9d103dd840 100644
--- a/drivers/power/pmic/rn5t567.c
+++ b/drivers/power/pmic/rn5t567.c
@@ -53,6 +53,7 @@ static struct dm_pmic_ops rn5t567_ops = {
 
 static const struct udevice_id rn5t567_ids[] = {
{ .compatible = "ricoh,rn5t567" },
+   { .compatible = "ricoh,rn5t568" },
{ }
 };
 
-- 
2.35.1

[PATCH v5 2/5] ARM: imx: imx8mp: Enable support for i2c5 and i2c6 on i.MX8MP

[Martyn Welch]

The i.MX8MP SoC contains 2 more i2c buses. Add support for the
configuration of these buses.

Signed-off-by: Martyn Welch 
---

Changes in v2:
 - None

Changes in v3:
 - None

Changes in v4:
 - None

Changes in v5:
 - None

 arch/arm/include/asm/arch-imx8m/imx-regs.h |  4 
 arch/arm/mach-imx/i2c-mxv7.c   |  6 ++
 arch/arm/mach-imx/imx8m/clock_imx8mm.c | 12 +---
 3 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index c46d4f7e00..6595d97f0a 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -44,6 +44,10 @@
 #define I2C3_BASE_ADDR 0x30A4
 #define I2C4_BASE_ADDR 0x30A5
 #define UART4_BASE_ADDR0x30A6
+#ifdef CONFIG_IMX8MP
+#define I2C5_BASE_ADDR  0x30AD
+#define I2C6_BASE_ADDR  0x30AE
+#endif
 #define USDHC1_BASE_ADDR   0x30B4
 #define USDHC2_BASE_ADDR   0x30B5
 #define QSPI0_AMBA_BASE 0x0800
diff --git a/arch/arm/mach-imx/i2c-mxv7.c b/arch/arm/mach-imx/i2c-mxv7.c
index 85d648b56e..a5866cf9f7 100644
--- a/arch/arm/mach-imx/i2c-mxv7.c
+++ b/arch/arm/mach-imx/i2c-mxv7.c
@@ -70,6 +70,12 @@ static void * const i2c_bases[] = {
 #ifdef I2C4_BASE_ADDR
(void *)I2C4_BASE_ADDR,
 #endif
+#ifdef I2C5_BASE_ADDR
+   (void *)I2C5_BASE_ADDR,
+#endif
+#ifdef I2C6_BASE_ADDR
+   (void *)I2C6_BASE_ADDR,
+#endif
 };
 
 /* i2c_index can be from 0 - 3 */
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c 
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 4db55f8608..64ad57e9b3 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -36,11 +36,17 @@ void enable_ocotp_clk(unsigned char enable)
 
 int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
-   /* 0 - 3 is valid i2c num */
-   if (i2c_num > 3)
+   u8 i2c_ccgr[6] = {
+   CCGR_I2C1, CCGR_I2C2, CCGR_I2C3, CCGR_I2C4,
+#if (IS_ENABLED(CONFIG_IMX8MP))
+   CCGR_I2C5_8MP, CCGR_I2C6_8MP
+#endif
+   };
+
+   if (i2c_num > ARRAY_SIZE(i2c_ccgr))
return -EINVAL;
 
-   clock_enable(CCGR_I2C1 + i2c_num, !!enable);
+   clock_enable(i2c_ccgr[i2c_num], !!enable);
 
return 0;
 }
-- 
2.35.1

[PATCH v5 1/5] imx8m: USDHC3 base address definition for i.MX8MP

[Martyn Welch]

The i.MX8MP also has USDHC3, allow access to the relvant base address
definition.

Signed-off-by: Martyn Welch 
---

Changes in v2:
 - None

Changes in v3:
 - None

Changes in v4:
 - None

Changes in v5:
 - None

 arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h 
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 29d5baaab8..c46d4f7e00 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -47,7 +47,7 @@
 #define USDHC1_BASE_ADDR   0x30B4
 #define USDHC2_BASE_ADDR   0x30B5
 #define QSPI0_AMBA_BASE 0x0800
-#ifdef CONFIG_IMX8MM
+#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MP)
 #define USDHC3_BASE_ADDR   0x30B6
 #endif
 #define UART_BASE_ADDR(n)  (   \
-- 
2.35.1

Re: [PATCH v5 4/5] eficonfig: add UEFI Secure Boot Key enrollment interface

[Masahisa Kojima]

Hi Etienne,

On Tue, 25 Oct 2022 at 17:15, Etienne Carriere
 wrote:
>
> Hello Kojima-san,
>
> On Tue, 25 Oct 2022 at 05:17, Masahisa Kojima
>  wrote:
> >
> > This commit adds the menu-driven UEFI Secure Boot Key
> > enrollment interface. User can enroll the PK, KEK, db
> > and dbx by selecting EFI Signature Lists file.
> > After the PK is enrolled, UEFI Secure Boot is enabled and
> > EFI Signature Lists file must be signed by KEK or PK.
> >
> > Signed-off-by: Masahisa Kojima 
> > ---
> > No change since v4
> >
> > Changes in v4:
> > - add CONFIG_EFI_MM_COMM_TEE dependency
> > - fix error handling
> >
> > Changes in v3:
> > - fix error handling
> >
> > Changes in v2:
> > - allow to enroll .esl file
> > - fix typos
> > - add function comments
> >
> >  cmd/Makefile  |   5 +
> >  cmd/eficonfig.c   |   3 +
> >  cmd/eficonfig_sbkey.c | 357 ++
> >  include/efi_config.h  |   5 +
> >  4 files changed, 370 insertions(+)
> >  create mode 100644 cmd/eficonfig_sbkey.c
> >
> > diff --git a/cmd/Makefile b/cmd/Makefile
> > index c95e09d058..e43ef22e98 100644
> > --- a/cmd/Makefile
> > +++ b/cmd/Makefile
> > @@ -66,6 +66,11 @@ obj-$(CONFIG_CMD_EEPROM) += eeprom.o
> >  obj-$(CONFIG_EFI) += efi.o
> >  obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
> >  obj-$(CONFIG_CMD_EFICONFIG) += eficonfig.o
> > +ifdef CONFIG_CMD_EFICONFIG
> > +ifdef CONFIG_EFI_MM_COMM_TEE
> > +obj-$(CONFIG_EFI_SECURE_BOOT) += eficonfig_sbkey.o
> > +endif
> > +endif
> >  obj-$(CONFIG_CMD_ELF) += elf.o
> >  obj-$(CONFIG_CMD_EROFS) += erofs.o
> >  obj-$(CONFIG_HUSH_PARSER) += exit.o
> > diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
> > index c765b795d0..0b643a046c 100644
> > --- a/cmd/eficonfig.c
> > +++ b/cmd/eficonfig.c
> > @@ -2447,6 +2447,9 @@ static const struct eficonfig_item 
> > maintenance_menu_items[] = {
> > {"Edit Boot Option", eficonfig_process_edit_boot_option},
> > {"Change Boot Order", eficonfig_process_change_boot_order},
> > {"Delete Boot Option", eficonfig_process_delete_boot_option},
> > +#if (CONFIG_IS_ENABLED(EFI_SECURE_BOOT) && 
> > CONFIG_IS_ENABLED(EFI_MM_COMM_TEE))
> > +   {"Secure Boot Configuration", eficonfig_process_secure_boot_config},
> > +#endif
> > {"Quit", eficonfig_process_quit},
> >  };
> >
> > diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c
> > new file mode 100644
> > index 00..32a39eb7ba
> > --- /dev/null
> > +++ b/cmd/eficonfig_sbkey.c
> > @@ -0,0 +1,357 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *  Menu-driven UEFI Secure Boot Key Maintenance
> > + *
> > + *  Copyright (c) 2022 Masahisa Kojima, Linaro Limited
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +enum efi_sbkey_signature_type {
> > +   SIG_TYPE_X509 = 0,
> > +   SIG_TYPE_HASH,
> > +   SIG_TYPE_CRL,
> > +   SIG_TYPE_RSA2048,
> > +};
> > +
> > +struct eficonfig_sigtype_to_str {
> > +   efi_guid_t sig_type;
> > +   char *str;
> > +   enum efi_sbkey_signature_type type;
> > +};
> > +
> > +static const struct eficonfig_sigtype_to_str sigtype_to_str[] = {
> > +   {EFI_CERT_X509_GUID,"X509", 
> > SIG_TYPE_X509},
> > +   {EFI_CERT_SHA256_GUID,  "SHA256",   
> > SIG_TYPE_HASH},
> > +   {EFI_CERT_X509_SHA256_GUID, "X509_SHA256 CRL",  
> > SIG_TYPE_CRL},
> > +   {EFI_CERT_X509_SHA384_GUID, "X509_SHA384 CRL",  
> > SIG_TYPE_CRL},
> > +   {EFI_CERT_X509_SHA512_GUID, "X509_SHA512 CRL",  
> > SIG_TYPE_CRL},
> > +   /* U-Boot does not support the following signature types */
> > +/* {EFI_CERT_RSA2048_GUID, "RSA2048",  
> > SIG_TYPE_RSA2048}, */
> > +/* {EFI_CERT_RSA2048_SHA256_GUID,  "RSA2048_SHA256",   
> > SIG_TYPE_RSA2048}, */
> > +/* {EFI_CERT_SHA1_GUID,"SHA1", 
> > SIG_TYPE_HASH}, */
> > +/* {EFI_CERT_RSA2048_SHA_GUID, "RSA2048_SHA",  
> > SIG_TYPE_RSA2048 }, */
> > +/* {EFI_CERT_SHA224_GUID,  "SHA224",   
> > SIG_TYPE_HASH}, */
> > +/* {EFI_CERT_SHA384_GUID,  "SHA384",   
> > SIG_TYPE_HASH}, */
> > +/* {EFI_CERT_SHA512_GUID,  "SHA512",   
> > SIG_TYPE_HASH}, */
> > +};
> > +
> > +/**
> > + * is_secureboot_enabled() - check UEFI Secure Boot is enabled
> > + *
> > + * Return: true when UEFI Secure Boot is enabled, false otherwise
> > + */
> > +static bool is_secureboot_enabled(void)
> > +{
> > +   efi_status_t ret;
> > +   u8 secure_boot;
> > +   efi_uintn_t size;
> > +
> > +   size = sizeof(secure_boot);
> > +   ret = efi_get_variable_int(u"SecureBoot", _global_variable_guid,
> > +  NULL, , _boot, NULL);
> > +
> > +   return secure_boot == 1;
>
> This should test 'ret{ against 

Re: [PATCH v5 4/5] eficonfig: add UEFI Secure Boot Key enrollment interface

[Masahisa Kojima]

Hi Heinrich,

On Tue, 25 Oct 2022 at 17:12, Heinrich Schuchardt  wrote:
>
> On 10/25/22 05:16, Masahisa Kojima wrote:
> > This commit adds the menu-driven UEFI Secure Boot Key
> > enrollment interface. User can enroll the PK, KEK, db
> > and dbx by selecting EFI Signature Lists file.
> > After the PK is enrolled, UEFI Secure Boot is enabled and
> > EFI Signature Lists file must be signed by KEK or PK.
> >
> > Signed-off-by: Masahisa Kojima 
> > ---
> > No change since v4
> >
> > Changes in v4:
> > - add CONFIG_EFI_MM_COMM_TEE dependency
> > - fix error handling
> >
> > Changes in v3:
> > - fix error handling
> >
> > Changes in v2:
> > - allow to enroll .esl file
> > - fix typos
> > - add function comments
> >
> >   cmd/Makefile  |   5 +
> >   cmd/eficonfig.c   |   3 +
> >   cmd/eficonfig_sbkey.c | 357 ++
> >   include/efi_config.h  |   5 +
> >   4 files changed, 370 insertions(+)
> >   create mode 100644 cmd/eficonfig_sbkey.c
> >
> > diff --git a/cmd/Makefile b/cmd/Makefile
> > index c95e09d058..e43ef22e98 100644
> > --- a/cmd/Makefile
> > +++ b/cmd/Makefile
> > @@ -66,6 +66,11 @@ obj-$(CONFIG_CMD_EEPROM) += eeprom.o
> >   obj-$(CONFIG_EFI) += efi.o
> >   obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
> >   obj-$(CONFIG_CMD_EFICONFIG) += eficonfig.o
> > +ifdef CONFIG_CMD_EFICONFIG
> > +ifdef CONFIG_EFI_MM_COMM_TEE
> > +obj-$(CONFIG_EFI_SECURE_BOOT) += eficonfig_sbkey.o
> > +endif
> > +endif
> >   obj-$(CONFIG_CMD_ELF) += elf.o
> >   obj-$(CONFIG_CMD_EROFS) += erofs.o
> >   obj-$(CONFIG_HUSH_PARSER) += exit.o
> > diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
> > index c765b795d0..0b643a046c 100644
> > --- a/cmd/eficonfig.c
> > +++ b/cmd/eficonfig.c
> > @@ -2447,6 +2447,9 @@ static const struct eficonfig_item 
> > maintenance_menu_items[] = {
> >   {"Edit Boot Option", eficonfig_process_edit_boot_option},
> >   {"Change Boot Order", eficonfig_process_change_boot_order},
> >   {"Delete Boot Option", eficonfig_process_delete_boot_option},
> > +#if (CONFIG_IS_ENABLED(EFI_SECURE_BOOT) && 
> > CONFIG_IS_ENABLED(EFI_MM_COMM_TEE))
> > + {"Secure Boot Configuration", eficonfig_process_secure_boot_config},
> > +#endif
> >   {"Quit", eficonfig_process_quit},
> >   };
> >
> > diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c
> > new file mode 100644
> > index 00..32a39eb7ba
> > --- /dev/null
> > +++ b/cmd/eficonfig_sbkey.c
> > @@ -0,0 +1,357 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + *  Menu-driven UEFI Secure Boot Key Maintenance
> > + *
> > + *  Copyright (c) 2022 Masahisa Kojima, Linaro Limited
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +enum efi_sbkey_signature_type {
> > + SIG_TYPE_X509 = 0,
> > + SIG_TYPE_HASH,
> > + SIG_TYPE_CRL,
> > + SIG_TYPE_RSA2048,
> > +};
> > +
> > +struct eficonfig_sigtype_to_str {
> > + efi_guid_t sig_type;
> > + char *str;
> > + enum efi_sbkey_signature_type type;
> > +};
> > +
> > +static const struct eficonfig_sigtype_to_str sigtype_to_str[] = {
> > + {EFI_CERT_X509_GUID,"X509", 
> > SIG_TYPE_X509},
> > + {EFI_CERT_SHA256_GUID,  "SHA256",   
> > SIG_TYPE_HASH},
> > + {EFI_CERT_X509_SHA256_GUID, "X509_SHA256 CRL",  SIG_TYPE_CRL},
> > + {EFI_CERT_X509_SHA384_GUID, "X509_SHA384 CRL",  SIG_TYPE_CRL},
> > + {EFI_CERT_X509_SHA512_GUID, "X509_SHA512 CRL",  SIG_TYPE_CRL},
> > + /* U-Boot does not support the following signature types */
> > +/*   {EFI_CERT_RSA2048_GUID, "RSA2048",  
> > SIG_TYPE_RSA2048}, */
> > +/*   {EFI_CERT_RSA2048_SHA256_GUID,  "RSA2048_SHA256",   
> > SIG_TYPE_RSA2048}, */
> > +/*   {EFI_CERT_SHA1_GUID,"SHA1", 
> > SIG_TYPE_HASH}, */
> > +/*   {EFI_CERT_RSA2048_SHA_GUID, "RSA2048_SHA",  
> > SIG_TYPE_RSA2048 }, */
> > +/*   {EFI_CERT_SHA224_GUID,  "SHA224",   
> > SIG_TYPE_HASH}, */
> > +/*   {EFI_CERT_SHA384_GUID,  "SHA384",   
> > SIG_TYPE_HASH}, */
> > +/*   {EFI_CERT_SHA512_GUID,  "SHA512",   
> > SIG_TYPE_HASH}, */
> > +};
> > +
> > +/**
> > + * is_secureboot_enabled() - check UEFI Secure Boot is enabled
> > + *
> > + * Return:   true when UEFI Secure Boot is enabled, false otherwise
> > + */
> > +static bool is_secureboot_enabled(void)
> > +{
>
> This function should be in lib/.

As Etienne commented, I will call the exported efi_secure_boot_enabled().

>
> > + efi_status_t ret;
> > + u8 secure_boot;
> > + efi_uintn_t size;
> > +
> > + size = sizeof(secure_boot);
> > + ret = efi_get_variable_int(u"SecureBoot", _global_variable_guid,
> > +NULL, , _boot, NULL);
> > +
> > + return secure_boot == 1;
> > +}
> > +
> > +/**
> > + 

Re: [PATCH] xilinx: common: Remove zynq_board_read_rom_ethaddr()

[Michal Simek]

On 10/17/22 11:48, Venkatesh Yadav Abbarapu wrote:

Removing the zynq_board_read_rom_ethaddr() function as
xlnx,eeprom is not used anymore. As all board dts to use
nvmem alias instead of xlnx,eeprom.

Signed-off-by: Venkatesh Yadav Abbarapu 
---

  arch/arm/mach-zynq/include/mach/sys_proto.h   |  2 --
  arch/arm/mach-zynqmp/include/mach/sys_proto.h |  1 -
  board/xilinx/common/board.c   | 28 ---
  drivers/net/zynq_gem.c| 16 ---
  4 files changed, 47 deletions(-)

diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h 
b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 1dc16d479e..268ec50ad8 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -17,6 +17,4 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph);
  extern void zynq_ddrc_init(void);
  extern unsigned int zynq_get_silicon_version(void);
  
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);

-
  #endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h 
b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 9fffb4e541..c6733ed1bb 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -46,7 +46,6 @@ enum {
TCM_SPLIT,
  };
  
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);

  unsigned int zynqmp_get_silicon_version(void);
  
  int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);

diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 99fdbac639..59d87f2352 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -54,34 +54,6 @@ struct efi_capsule_update_info update_info = {
  u8 num_image_type_guids = ARRAY_SIZE(fw_images);
  #endif /* EFI_HAVE_CAPSULE_SUPPORT */
  
-#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)

-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
-{
-   int ret = -EINVAL;
-   struct udevice *dev;
-   ofnode eeprom;
-
-   eeprom = ofnode_get_chosen_node("xlnx,eeprom");
-   if (!ofnode_valid(eeprom))
-   return -ENODEV;
-
-   debug("%s: Path to EEPROM %s\n", __func__,
- ofnode_read_chosen_string("xlnx,eeprom"));
-
-   ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, );
-   if (ret)
-   return ret;
-
-   ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
-   if (ret)
-   debug("%s: I2C EEPROM MAC address read failed\n", __func__);
-   else
-   debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
-
-   return ret;
-}
-#endif
-
  #define EEPROM_HEADER_MAGIC   0xdaaddeed
  #define EEPROM_HDR_MANUFACTURER_LEN   16
  #define EEPROM_HDR_NAME_LEN   16
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3f4357ec80..507b19b759 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -662,21 +662,6 @@ static void zynq_gem_halt(struct udevice *dev)
ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
  }
  
-__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)

-{
-   return -ENOSYS;
-}
-
-static int zynq_gem_read_rom_mac(struct udevice *dev)
-{
-   struct eth_pdata *pdata = dev_get_plat(dev);
-
-   if (!pdata)
-   return -ENOSYS;
-
-   return zynq_board_read_rom_ethaddr(pdata->enetaddr);
-}
-
  static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
int devad, int reg)
  {
@@ -884,7 +869,6 @@ static const struct eth_ops zynq_gem_ops = {
.free_pkt   = zynq_gem_free_pkt,
.stop   = zynq_gem_halt,
.write_hwaddr   = zynq_gem_setup_mac,
-   .read_rom_hwaddr= zynq_gem_read_rom_mac,
  };
  
  static int zynq_gem_of_to_plat(struct udevice *dev)



applied.
M

Re: [PATCH 3/3] timer: xilinx-timer: use timer_conv_64() to fix timer wrap around

[Michal Simek]

On 10/12/22 07:36, Ovidiu Panait wrote:

Current xilinx_timer_get_count() implementation does not take into account
the periodic 32-bit wrap arounds, as it directly returns the 32-bit counter
register value. The roll-overs cause problems in the upper timer layers, as
generic timer code expects an incrementing 64-bit value from get_count() to
work correctly.

Add the missing 64-bit up-conversion to fix random hangs/delays in
__udelay().

Fixes: a36d86720f ("microblaze: Convert axi timer to DM driver")
Signed-off-by: Ovidiu Panait 
---

  drivers/timer/xilinx-timer.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
index 75b4473b63..172fd9f929 100644
--- a/drivers/timer/xilinx-timer.c
+++ b/drivers/timer/xilinx-timer.c
@@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev)
  
  	regmap_read(priv->regs, TIMER_COUNTER_OFFSET, );
  
-	return value;

+   return timer_conv_64(value);
  }
  
  static int xilinx_timer_probe(struct udevice *dev)


Applied all.
M

Re: [PATCH v6 03/10] arm_ffa: introduce Arm FF-A low-level driver

[Jens Wiklander]

On Thu, Oct 13, 2022 at 11:38:50AM +0100, Abdellatif El Khlifi wrote:
> Add the core driver implementing Arm Firmware Framework for Armv8-A v1.0
> 
> The Firmware Framework for Arm A-profile processors (FF-A v1.0) [1]
> describes interfaces (ABIs) that standardize communication
> between the Secure World and Normal World leveraging TrustZone
> technology.
> 
> This driver uses 64-bit registers as per SMCCCv1.2 spec and comes
> on top of the SMCCC layer. The driver provides the FF-A ABIs needed for
> querying the FF-A framework from the secure world.
> 
> 32-bit version of the ABIs is supported and 64-bit version of FFA_RXTX_MAP
> and FFA_MSG_SEND_DIRECT_{REQ, RESP}.
> 
> In u-boot FF-A design, FF-A is considered as a discoverable bus.

U-Boot

> The Secure World is considered as one entity to communicate with
> using the FF-A bus. FF-A communication is handled by one device and
> one instance (the bus). This FF-A driver takes care of all the
> interactions between Normal world and Secure World.
> 
> The driver exports its operations to be used by upper layers.
> 
> Exported operations:
> 
> - partition_info_get
> - sync_send_receive
> - rxtx_unmap
> 
> [1]: https://developer.arm.com/documentation/den0077/latest/
> 
> Signed-off-by: Abdellatif El Khlifi 
> Cc: Tom Rini 
> Cc: Simon Glass 
> Cc: Ilias Apalodimas 
> Cc: Jens Wiklander 
> 
> ---
> 
> Changelog:
> ===
> 
> v6:
> 
> * drop use of EFI runtime support (We decided with Linaro to add this later)
> * drop discovery from initcalls (discovery will be on demand by FF-A users)
> * set the alignment of the RX/TX buffers to the larger translation granule 
> size
> * move FF-A RX/TX buffers unmapping at ExitBootServices() to a separate commit
> * update the documentation and move it to doc/arch/arm64.ffa.rst
> 
> v4:
> 
> * add doc/README.ffa.drv
> * moving the FF-A driver work to drivers/firmware/arm-ffa
> * use less #ifdefs in lib/efi_loader/efi_boottime.c and replace
>   #if defined by #if CONFIG_IS_ENABLED
> * improving error handling by mapping the FF-A errors to standard errors
>   and logs
> * replacing panics with an error log and returning an error code
> * improving features discovery in FFA_FEATURES by introducing
>   rxtx_min_pages private data field
> * add ffa_remove and ffa_unbind functions
> * improve how the driver behaves when bus discovery is done more than
>   once
> 
> v3:
> 
> * align the interfaces of the u-boot FF-A driver with those in the linux
>   FF-A driver
> * remove the FF-A helper layer
> * make the u-boot FF-A driver independent from EFI
> * provide an optional config that enables copying the driver data to EFI
>   runtime section at ExitBootServices service
> * use 64-bit version of FFA_RXTX_MAP, FFA_MSG_SEND_DIRECT_{REQ, RESP}
> 
> v2:
> 
> * make FF-A bus discoverable using device_{bind, probe} APIs
> * remove device tree support
> 
> v1:
> 
> * introduce FF-A bus driver with device tree support
> 
>  MAINTAINERS   |7 +
>  doc/arch/arm64.ffa.rst|  207 
>  doc/arch/index.rst|1 +
>  drivers/Kconfig   |2 +
>  drivers/Makefile  |1 +
>  drivers/firmware/arm-ffa/Kconfig  |   30 +
>  drivers/firmware/arm-ffa/Makefile |6 +
>  drivers/firmware/arm-ffa/arm-ffa-uclass.c |   16 +
>  drivers/firmware/arm-ffa/arm_ffa_prv.h|  196 +++
>  drivers/firmware/arm-ffa/core.c   | 1337 +
>  include/arm_ffa.h |   93 ++
>  include/dm/uclass-id.h|4 +
>  12 files changed, 1900 insertions(+)
>  create mode 100644 doc/arch/arm64.ffa.rst
>  create mode 100644 drivers/firmware/arm-ffa/Kconfig
>  create mode 100644 drivers/firmware/arm-ffa/Makefile
>  create mode 100644 drivers/firmware/arm-ffa/arm-ffa-uclass.c
>  create mode 100644 drivers/firmware/arm-ffa/arm_ffa_prv.h
>  create mode 100644 drivers/firmware/arm-ffa/core.c
>  create mode 100644 include/arm_ffa.h
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index a26b36c7c2..496f47a516 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -248,6 +248,13 @@ F:   drivers/net/cortina_ni.h
>  F:   drivers/net/phy/ca_phy.c
>  F:   configs/cortina_presidio-asic-pnand_defconfig
>  
> +ARM FF-A
> +M:   Abdellatif El Khlifi 
> +S:   Maintained
> +F:   doc/arch/arm64.ffa.rst
> +F:   drivers/firmware/arm-ffa/
> +F:   include/arm_ffa.h
> +
>  ARM FREESCALE IMX
>  M:   Stefano Babic 
>  M:   Fabio Estevam 
> diff --git a/doc/arch/arm64.ffa.rst b/doc/arch/arm64.ffa.rst
> new file mode 100644
> index 00..e98d2cf2b3
> --- /dev/null
> +++ b/doc/arch/arm64.ffa.rst
> @@ -0,0 +1,207 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Arm FF-A Driver
> +===
> +
> +Summary
> +---
> +
> +FF-A stands for Firmware Framework for Arm A-profile processors.
> +
> +FF-A specifies interfaces that enable a pair of software sandboxes to
> +communicate with each 

Re: [PATCH v3] imx: imx8qm: cgtqmx8: switch to binman

[Stefano Babic]

On 25.10.22 10:50, Oliver Graute wrote:

On 24/10/22, Stefano Babic wrote:

On 24.10.22 13:59, Oliver Graute wrote:

On 24/10/22, Stefano Babic wrote:

On 24.10.22 13:37, Fabio Estevam wrote:

Hi Stefano and Oliver,

On Tue, May 3, 2022 at 7:49 AM Oliver Graute
 wrote:


Switch to use binman to pack images

Signed-off-by: Oliver Graute 
Reviewed-by: Fabio Estevam 
Reviewed-by: Simon Glass 
---
Changes for v3
-added Reviewed-by
-rebased on master

arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
arch/arm/mach-imx/imx8/Kconfig  | 1 +
board/congatec/cgtqmx8/imximage.cfg | 4 ++--
configs/cgtqmx8_defconfig   | 2 +-
doc/board/congatec/cgtqmx8.rst  | 3 +--
5 files changed, 6 insertions(+), 5 deletions(-)


Just realized that v3 does not include imx8qm-u-boot.dtsi and this breaks CI.



Right - as well as V4, this is what I tried to merge and breaks. I have drop
it.


The previous v2 did include it:
https://patchwork.ozlabs.org/project/uboot/patch/20220221090139.10066-1-oliver.gra...@kococonnector.com/


Thanks for noting this - Oliver, can you check and repost a V5, then ?


The arch/arm/dts/imx8qm-u-boot.dtsi  is applied on the binman Patch for
"PATCH v3 imx: imx8qm-rom7720: switch to binman"

So if you first apply the patches for the imx8qm-rom7720 Board it should work.



Ok, thanks for tipp - I apply both and will test again


I saw the CI Pipeline failing. Perhaps the reason is a
missing CONFIG_FIT_EXTERNAL_OFFSET?



I see this, but just applying the two patches, multiple boards are broken:
imx8qm_rom7720_a1_4G cgtqmx8 imx8qm_mek imx8qxp_mek deneb giedi



+++ b/configs/cgtqmx8_defconfig
@@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
  CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
  CONFIG_REMAKE_ELF=y
  CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
  CONFIG_SPL_LOAD_FIT=y
  # CONFIG_USE_SPL_FIT_GENERATOR is not set

Can you confirm?



I let CI run just to see if cgtqmx8 is fixed.

Stefano

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=
DENX Software Engineering GmbH,  Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, 82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de
=

Re: [PATCH v3] imx: imx8qm: cgtqmx8: switch to binman

[Oliver Graute]

On 24/10/22, Stefano Babic wrote:
> On 24.10.22 13:59, Oliver Graute wrote:
> > On 24/10/22, Stefano Babic wrote:
> > > On 24.10.22 13:37, Fabio Estevam wrote:
> > > > Hi Stefano and Oliver,
> > > > 
> > > > On Tue, May 3, 2022 at 7:49 AM Oliver Graute
> > > >  wrote:
> > > > > 
> > > > > Switch to use binman to pack images
> > > > > 
> > > > > Signed-off-by: Oliver Graute 
> > > > > Reviewed-by: Fabio Estevam 
> > > > > Reviewed-by: Simon Glass 
> > > > > ---
> > > > > Changes for v3
> > > > >-added Reviewed-by
> > > > >-rebased on master
> > > > > 
> > > > >arch/arm/dts/imx8qm-cgtqmx8.dts | 1 +
> > > > >arch/arm/mach-imx/imx8/Kconfig  | 1 +
> > > > >board/congatec/cgtqmx8/imximage.cfg | 4 ++--
> > > > >configs/cgtqmx8_defconfig   | 2 +-
> > > > >doc/board/congatec/cgtqmx8.rst  | 3 +--
> > > > >5 files changed, 6 insertions(+), 5 deletions(-)
> > > > 
> > > > Just realized that v3 does not include imx8qm-u-boot.dtsi and this 
> > > > breaks CI.
> > > > 
> > > 
> > > Right - as well as V4, this is what I tried to merge and breaks. I have 
> > > drop
> > > it.
> > > 
> > > > The previous v2 did include it:
> > > > https://patchwork.ozlabs.org/project/uboot/patch/20220221090139.10066-1-oliver.gra...@kococonnector.com/
> > > 
> > > Thanks for noting this - Oliver, can you check and repost a V5, then ?
> > 
> > The arch/arm/dts/imx8qm-u-boot.dtsi  is applied on the binman Patch for
> > "PATCH v3 imx: imx8qm-rom7720: switch to binman"
> > 
> > So if you first apply the patches for the imx8qm-rom7720 Board it should 
> > work.
> 
> 
> Ok, thanks for tipp - I apply both and will test again

I saw the CI Pipeline failing. Perhaps the reason is a
missing CONFIG_FIT_EXTERNAL_OFFSET?

+++ b/configs/cgtqmx8_defconfig
@@ -20,6 +20,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8020
 CONFIG_REMAKE_ELF=y
 CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
 CONFIG_SPL_LOAD_FIT=y
 # CONFIG_USE_SPL_FIT_GENERATOR is not set

Can you confirm?

 Best regards,

 Oliver

Re: [PATCH] Revert "pinctrl: zynqmp: Add support for output-enable and bias-high-impedance"

[Michal Simek]

On 10/13/22 13:05, Michal Simek wrote:

This reverts commit 123462e5e534d6e17b1b7d2006734bbe54b03e0a.

On systems with older PMUFW using these pinctrl properties can cause system
hang because there is missing feature autodetection.
When it is implemented support for these two properties should go back.

Signed-off-by: Michal Simek 
---

https://lore.kernel.org/all/9b7fac69-265e-52f2-21e4-83d9da0f2...@amd.com/
---
  drivers/pinctrl/pinctrl-zynqmp.c | 9 -
  1 file changed, 9 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 52d428f566fc..7c5a02db1b98 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -467,10 +467,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, 
unsigned int pin,
 pin);
break;
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-   param = PM_PINCTRL_CONFIG_TRI_STATE;
-   arg = PM_PINCTRL_TRI_STATE_ENABLE;
-   ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
-   break;
case PIN_CONFIG_LOW_POWER_MODE:
/*
 * This cases are mentioned in dts but configurable
@@ -479,11 +475,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, 
unsigned int pin,
 */
ret = 0;
break;
-   case PIN_CONFIG_OUTPUT_ENABLE:
-   param = PM_PINCTRL_CONFIG_TRI_STATE;
-   arg = PM_PINCTRL_TRI_STATE_DISABLE;
-   ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
-   break;
default:
dev_warn(dev, "unsupported configuration parameter '%u'\n",
 param);


Applied.
M

Re: [PATCH] arm64: zynqmp: Disable watchdog by default for virt platform

[Michal Simek]

On 10/12/22 11:35, Michal Simek wrote:

Disable watchdog based on request in past that not all Linux rootfs have
proper utilities ready to service it. Enable it if your rootfs have proper
watchdog handling.

Signed-off-by: Michal Simek 
---

  configs/xilinx_zynqmp_virt_defconfig | 2 --
  1 file changed, 2 deletions(-)

diff --git a/configs/xilinx_zynqmp_virt_defconfig 
b/configs/xilinx_zynqmp_virt_defconfig
index 150a4d43bc86..9765116a4f58 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -83,7 +83,6 @@ CONFIG_CMD_SF_TEST=y
  CONFIG_CMD_SPI=y
  CONFIG_CMD_USB=y
  CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_WDT=y
  CONFIG_BOOTP_MAY_FAIL=y
  CONFIG_BOOTP_BOOTFILESIZE=y
  CONFIG_CMD_TFTPPUT=y
@@ -232,7 +231,6 @@ CONFIG_SPLASH_SCREEN=y
  CONFIG_BMP_16BPP=y
  CONFIG_BMP_24BPP=y
  CONFIG_BMP_32BPP=y
-CONFIG_WDT=y
  CONFIG_PANIC_HANG=y
  CONFIG_TPM=y
  CONFIG_SPL_GZIP=y


applied.
M

Re: [PATCH] microblaze: Make extended addressing support default

[Michal Simek]

On 10/12/22 11:03, Michal Simek wrote:

From: T Karthik Reddy 

Axi qspi controller supports 32-bit & 24-bit addressing modes
for micron, macronix & spansion flash parts. But for winbond
flashes it only supports 24-bit addressing mode.
Enable CONFIG_SPI_FLASH_BAR to use extended addressing mode
to make 32-bit addressing mode work on all flashes.

Signed-off-by: T Karthik Reddy 
Acked-by: Ashok Reddy Soma 
Signed-off-by: Michal Simek 
---

  configs/microblaze-generic_defconfig | 1 +
  1 file changed, 1 insertion(+)

diff --git a/configs/microblaze-generic_defconfig 
b/configs/microblaze-generic_defconfig
index 0f650e59073f..c993cca3c5cb 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -80,6 +80,7 @@ CONFIG_FLASH_CFI_MTD=y
  CONFIG_SYS_FLASH_PROTECTION=y
  CONFIG_SYS_FLASH_CFI=y
  CONFIG_SYS_MAX_FLASH_SECT=2048
+CONFIG_SPI_FLASH_BAR=y
  CONFIG_SPI_FLASH_ISSI=y
  CONFIG_SPI_FLASH_MACRONIX=y
  CONFIG_SPI_FLASH_SPANSION=y


Applied.
M

Re: [PATCH] ARM: zynq: DT: Enable all FCLKs by default

[Michal Simek]

On 10/12/22 11:30, Michal Simek wrote:

From: Christian Kohn 

The fclk-enable property is set to 0 which disables all FCLKs.
Enable all FCLKs so they can be used as clock sources in the
programmable logic.

Signed-off-by: Christian Kohn 
Acked-by: Soren Brinkmann 
Signed-off-by: Michal Simek 
---

  arch/arm/dts/zynq-7000.dtsi | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index edc147d63f1e..f72ef526f057 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -340,7 +340,7 @@
u-boot,dm-pre-reloc;
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
-   fclk-enable = <0>;
+   fclk-enable = <0xf>;
clock-output-names = "armpll", "ddrpll", "iopll", 
"cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", 
"ddr3x",
"dci", "lqspi", "smc", "pcap", "gem0", 
"gem1",


Applied.
M

Re: [PATCH] arm64: versal: Add missing BOOT_MODE_POR_X macros

[Michal Simek]

On 10/12/22 10:47, Michal Simek wrote:

The commit bf8dae5fcf40 ("spi: cadence-qspi: reset qspi flash for versal
platform") added reference to BOOT_MODE_POR_X but forget to add them.

Signed-off-by: Michal Simek 
---

  arch/arm/mach-versal/include/mach/hardware.h | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-versal/include/mach/hardware.h 
b/arch/arm/mach-versal/include/mach/hardware.h
index 000af974e867..aa41155e9dc7 100644
--- a/arch/arm/mach-versal/include/mach/hardware.h
+++ b/arch/arm/mach-versal/include/mach/hardware.h
@@ -97,3 +97,5 @@ struct crp_regs {
  #define MIO_PIN_120xF1060030
  #define BANK0_OUTPUT  0xF1020040
  #define BANK0_TRI 0xF1060200
+#define BOOT_MODE_POR_00xF1020204
+#define BOOT_MODE_POR_10xF1020208


Applied.
M

Re: [PATCH v5 4/5] eficonfig: add UEFI Secure Boot Key enrollment interface

[Etienne Carriere]

Hello Kojima-san,

On Tue, 25 Oct 2022 at 05:17, Masahisa Kojima
 wrote:
>
> This commit adds the menu-driven UEFI Secure Boot Key
> enrollment interface. User can enroll the PK, KEK, db
> and dbx by selecting EFI Signature Lists file.
> After the PK is enrolled, UEFI Secure Boot is enabled and
> EFI Signature Lists file must be signed by KEK or PK.
>
> Signed-off-by: Masahisa Kojima 
> ---
> No change since v4
>
> Changes in v4:
> - add CONFIG_EFI_MM_COMM_TEE dependency
> - fix error handling
>
> Changes in v3:
> - fix error handling
>
> Changes in v2:
> - allow to enroll .esl file
> - fix typos
> - add function comments
>
>  cmd/Makefile  |   5 +
>  cmd/eficonfig.c   |   3 +
>  cmd/eficonfig_sbkey.c | 357 ++
>  include/efi_config.h  |   5 +
>  4 files changed, 370 insertions(+)
>  create mode 100644 cmd/eficonfig_sbkey.c
>
> diff --git a/cmd/Makefile b/cmd/Makefile
> index c95e09d058..e43ef22e98 100644
> --- a/cmd/Makefile
> +++ b/cmd/Makefile
> @@ -66,6 +66,11 @@ obj-$(CONFIG_CMD_EEPROM) += eeprom.o
>  obj-$(CONFIG_EFI) += efi.o
>  obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
>  obj-$(CONFIG_CMD_EFICONFIG) += eficonfig.o
> +ifdef CONFIG_CMD_EFICONFIG
> +ifdef CONFIG_EFI_MM_COMM_TEE
> +obj-$(CONFIG_EFI_SECURE_BOOT) += eficonfig_sbkey.o
> +endif
> +endif
>  obj-$(CONFIG_CMD_ELF) += elf.o
>  obj-$(CONFIG_CMD_EROFS) += erofs.o
>  obj-$(CONFIG_HUSH_PARSER) += exit.o
> diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
> index c765b795d0..0b643a046c 100644
> --- a/cmd/eficonfig.c
> +++ b/cmd/eficonfig.c
> @@ -2447,6 +2447,9 @@ static const struct eficonfig_item 
> maintenance_menu_items[] = {
> {"Edit Boot Option", eficonfig_process_edit_boot_option},
> {"Change Boot Order", eficonfig_process_change_boot_order},
> {"Delete Boot Option", eficonfig_process_delete_boot_option},
> +#if (CONFIG_IS_ENABLED(EFI_SECURE_BOOT) && 
> CONFIG_IS_ENABLED(EFI_MM_COMM_TEE))
> +   {"Secure Boot Configuration", eficonfig_process_secure_boot_config},
> +#endif
> {"Quit", eficonfig_process_quit},
>  };
>
> diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c
> new file mode 100644
> index 00..32a39eb7ba
> --- /dev/null
> +++ b/cmd/eficonfig_sbkey.c
> @@ -0,0 +1,357 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + *  Menu-driven UEFI Secure Boot Key Maintenance
> + *
> + *  Copyright (c) 2022 Masahisa Kojima, Linaro Limited
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +enum efi_sbkey_signature_type {
> +   SIG_TYPE_X509 = 0,
> +   SIG_TYPE_HASH,
> +   SIG_TYPE_CRL,
> +   SIG_TYPE_RSA2048,
> +};
> +
> +struct eficonfig_sigtype_to_str {
> +   efi_guid_t sig_type;
> +   char *str;
> +   enum efi_sbkey_signature_type type;
> +};
> +
> +static const struct eficonfig_sigtype_to_str sigtype_to_str[] = {
> +   {EFI_CERT_X509_GUID,"X509", 
> SIG_TYPE_X509},
> +   {EFI_CERT_SHA256_GUID,  "SHA256",   
> SIG_TYPE_HASH},
> +   {EFI_CERT_X509_SHA256_GUID, "X509_SHA256 CRL",  SIG_TYPE_CRL},
> +   {EFI_CERT_X509_SHA384_GUID, "X509_SHA384 CRL",  SIG_TYPE_CRL},
> +   {EFI_CERT_X509_SHA512_GUID, "X509_SHA512 CRL",  SIG_TYPE_CRL},
> +   /* U-Boot does not support the following signature types */
> +/* {EFI_CERT_RSA2048_GUID, "RSA2048",  
> SIG_TYPE_RSA2048}, */
> +/* {EFI_CERT_RSA2048_SHA256_GUID,  "RSA2048_SHA256",   
> SIG_TYPE_RSA2048}, */
> +/* {EFI_CERT_SHA1_GUID,"SHA1", 
> SIG_TYPE_HASH}, */
> +/* {EFI_CERT_RSA2048_SHA_GUID, "RSA2048_SHA",  
> SIG_TYPE_RSA2048 }, */
> +/* {EFI_CERT_SHA224_GUID,  "SHA224",   
> SIG_TYPE_HASH}, */
> +/* {EFI_CERT_SHA384_GUID,  "SHA384",   
> SIG_TYPE_HASH}, */
> +/* {EFI_CERT_SHA512_GUID,  "SHA512",   
> SIG_TYPE_HASH}, */
> +};
> +
> +/**
> + * is_secureboot_enabled() - check UEFI Secure Boot is enabled
> + *
> + * Return: true when UEFI Secure Boot is enabled, false otherwise
> + */
> +static bool is_secureboot_enabled(void)
> +{
> +   efi_status_t ret;
> +   u8 secure_boot;
> +   efi_uintn_t size;
> +
> +   size = sizeof(secure_boot);
> +   ret = efi_get_variable_int(u"SecureBoot", _global_variable_guid,
> +  NULL, , _boot, NULL);
> +
> +   return secure_boot == 1;

This should test 'ret{ against EFI_SUCCESS and EFI_NOT_FOUND.
I think the logic should be:
  if (ret == EFI_SUCCESS) { return secure_boot == 1; }
  else if (ret == EFI_NOT_FOUND) { return false; }
  else { /* enforce secure bool policy on error */ return true; }

That said, there is the exported efi_secure_boot_enabled() that should
be reliable, i think.


> +}
> +
> +/**
> + * create_time_based_payload() - 

Re: [PATCH v5 4/5] eficonfig: add UEFI Secure Boot Key enrollment interface

[Heinrich Schuchardt]

On 10/25/22 05:16, Masahisa Kojima wrote:

This commit adds the menu-driven UEFI Secure Boot Key
enrollment interface. User can enroll the PK, KEK, db
and dbx by selecting EFI Signature Lists file.
After the PK is enrolled, UEFI Secure Boot is enabled and
EFI Signature Lists file must be signed by KEK or PK.

Signed-off-by: Masahisa Kojima 
---
No change since v4

Changes in v4:
- add CONFIG_EFI_MM_COMM_TEE dependency
- fix error handling

Changes in v3:
- fix error handling

Changes in v2:
- allow to enroll .esl file
- fix typos
- add function comments

  cmd/Makefile  |   5 +
  cmd/eficonfig.c   |   3 +
  cmd/eficonfig_sbkey.c | 357 ++
  include/efi_config.h  |   5 +
  4 files changed, 370 insertions(+)
  create mode 100644 cmd/eficonfig_sbkey.c

diff --git a/cmd/Makefile b/cmd/Makefile
index c95e09d058..e43ef22e98 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -66,6 +66,11 @@ obj-$(CONFIG_CMD_EEPROM) += eeprom.o
  obj-$(CONFIG_EFI) += efi.o
  obj-$(CONFIG_CMD_EFIDEBUG) += efidebug.o
  obj-$(CONFIG_CMD_EFICONFIG) += eficonfig.o
+ifdef CONFIG_CMD_EFICONFIG
+ifdef CONFIG_EFI_MM_COMM_TEE
+obj-$(CONFIG_EFI_SECURE_BOOT) += eficonfig_sbkey.o
+endif
+endif
  obj-$(CONFIG_CMD_ELF) += elf.o
  obj-$(CONFIG_CMD_EROFS) += erofs.o
  obj-$(CONFIG_HUSH_PARSER) += exit.o
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index c765b795d0..0b643a046c 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -2447,6 +2447,9 @@ static const struct eficonfig_item 
maintenance_menu_items[] = {
{"Edit Boot Option", eficonfig_process_edit_boot_option},
{"Change Boot Order", eficonfig_process_change_boot_order},
{"Delete Boot Option", eficonfig_process_delete_boot_option},
+#if (CONFIG_IS_ENABLED(EFI_SECURE_BOOT) && CONFIG_IS_ENABLED(EFI_MM_COMM_TEE))
+   {"Secure Boot Configuration", eficonfig_process_secure_boot_config},
+#endif
{"Quit", eficonfig_process_quit},
  };

diff --git a/cmd/eficonfig_sbkey.c b/cmd/eficonfig_sbkey.c
new file mode 100644
index 00..32a39eb7ba
--- /dev/null
+++ b/cmd/eficonfig_sbkey.c
@@ -0,0 +1,357 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ *  Menu-driven UEFI Secure Boot Key Maintenance
+ *
+ *  Copyright (c) 2022 Masahisa Kojima, Linaro Limited
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+enum efi_sbkey_signature_type {
+   SIG_TYPE_X509 = 0,
+   SIG_TYPE_HASH,
+   SIG_TYPE_CRL,
+   SIG_TYPE_RSA2048,
+};
+
+struct eficonfig_sigtype_to_str {
+   efi_guid_t sig_type;
+   char *str;
+   enum efi_sbkey_signature_type type;
+};
+
+static const struct eficonfig_sigtype_to_str sigtype_to_str[] = {
+   {EFI_CERT_X509_GUID,"X509",   
SIG_TYPE_X509},
+   {EFI_CERT_SHA256_GUID,  "SHA256", SIG_TYPE_HASH},
+   {EFI_CERT_X509_SHA256_GUID, "X509_SHA256 CRL",SIG_TYPE_CRL},
+   {EFI_CERT_X509_SHA384_GUID, "X509_SHA384 CRL",SIG_TYPE_CRL},
+   {EFI_CERT_X509_SHA512_GUID, "X509_SHA512 CRL",SIG_TYPE_CRL},
+   /* U-Boot does not support the following signature types */
+/* {EFI_CERT_RSA2048_GUID, "RSA2048",
SIG_TYPE_RSA2048}, */
+/* {EFI_CERT_RSA2048_SHA256_GUID,  "RSA2048_SHA256", 
SIG_TYPE_RSA2048}, */
+/* {EFI_CERT_SHA1_GUID,"SHA1",   
SIG_TYPE_HASH}, */
+/* {EFI_CERT_RSA2048_SHA_GUID, "RSA2048_SHA",
SIG_TYPE_RSA2048 }, */
+/* {EFI_CERT_SHA224_GUID,  "SHA224", SIG_TYPE_HASH}, */
+/* {EFI_CERT_SHA384_GUID,  "SHA384", SIG_TYPE_HASH}, */
+/* {EFI_CERT_SHA512_GUID,  "SHA512", SIG_TYPE_HASH}, */
+};
+
+/**
+ * is_secureboot_enabled() - check UEFI Secure Boot is enabled
+ *
+ * Return: true when UEFI Secure Boot is enabled, false otherwise
+ */
+static bool is_secureboot_enabled(void)
+{


This function should be in lib/.


+   efi_status_t ret;
+   u8 secure_boot;
+   efi_uintn_t size;
+
+   size = sizeof(secure_boot);
+   ret = efi_get_variable_int(u"SecureBoot", _global_variable_guid,
+  NULL, , _boot, NULL);
+
+   return secure_boot == 1;
+}
+
+/**
+ * create_time_based_payload() - create payload for time based authenticate 
variable
+ *
+ * @db:pointer to the original signature database
+ * @new_db:pointer to the authenticated variable payload
+ * @size:  pointer to payload size
+ * Return: status code
+ */
+static efi_status_t create_time_based_payload(void *db, void **new_db, 
efi_uintn_t *size)
+{
+   efi_status_t ret;
+   struct efi_time time;
+   efi_uintn_t total_size;
+   struct efi_variable_authentication_2 *auth;
+
+   *new_db = NULL;
+
+   /*
+* SetVariable() call with 
EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS
+   

[PATCH 1/3] arm64: dts: rk3399: sync rk3399.dtsi from 6.1-rc1

[Peter Robinson]

Sync rk3399.dtsi and associated bindings includes. Fix up building
of clk/rockchip/clk_rk3399.c for the changes as well as adjusting
the rk3399-u-boot.dtsi for the new upstream pieces.

Signed-off-by: Peter Robinson 
---
 arch/arm/dts/rk3399-opp.dtsi |   6 +-
 arch/arm/dts/rk3399-u-boot.dtsi  |  36 ++--
 arch/arm/dts/rk3399.dtsi | 200 ---
 drivers/clk/rockchip/clk_rk3399.c|   2 +-
 include/dt-bindings/clock/rk3399-cru.h   |  24 +--
 include/dt-bindings/power/rk3399-power.h |   1 +
 6 files changed, 206 insertions(+), 63 deletions(-)

diff --git a/arch/arm/dts/rk3399-opp.dtsi b/arch/arm/dts/rk3399-opp.dtsi
index da41cd81ebb..fee5e711127 100644
--- a/arch/arm/dts/rk3399-opp.dtsi
+++ b/arch/arm/dts/rk3399-opp.dtsi
@@ -4,7 +4,7 @@
  */
 
 / {
-   cluster0_opp: opp-table0 {
+   cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -35,7 +35,7 @@
};
};
 
-   cluster1_opp: opp-table1 {
+   cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
 
@@ -74,7 +74,7 @@
};
};
 
-   gpu_opp_table: opp-table2 {
+   gpu_opp_table: opp-table-2 {
compatible = "operating-points-v2";
 
opp00 {
diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi
index 3c1a15fe51b..2fa8f25a3e1 100644
--- a/arch/arm/dts/rk3399-u-boot.dtsi
+++ b/arch/arm/dts/rk3399-u-boot.dtsi
@@ -20,38 +20,12 @@
reg = <0x0 0xff62 0x0 0x100>;
};
 
-   dfi: dfi@ff63 {
-   u-boot,dm-pre-reloc;
-   reg = <0x00 0xff63 0x00 0x4000>;
-   compatible = "rockchip,rk3399-dfi";
-   rockchip,pmu = <>;
-   clocks = < PCLK_DDR_MON>;
-   clock-names = "pclk_ddr_mon";
-   };
-
rng: rng@ff8b8000 {
compatible = "rockchip,cryptov1-rng";
reg = <0x0 0xff8b8000 0x0 0x1000>;
status = "okay";
};
 
-   dmc: dmc {
-   u-boot,dm-pre-reloc;
-   compatible = "rockchip,rk3399-dmc";
-   devfreq-events = <>;
-   interrupts = ;
-   clocks = < SCLK_DDRCLK>;
-   clock-names = "dmc_clk";
-   reg = <0x0 0xffa8 0x0 0x0800
-  0x0 0xffa80800 0x0 0x1800
-  0x0 0xffa82000 0x0 0x2000
-  0x0 0xffa84000 0x0 0x1000
-  0x0 0xffa88000 0x0 0x0800
-  0x0 0xffa88800 0x0 0x1800
-  0x0 0xffa8a000 0x0 0x2000
-  0x0 0xffa8c000 0x0 0x1000>;
-   };
-
pmusgrf: syscon@ff33 {
u-boot,dm-pre-reloc;
compatible = "rockchip,rk3399-pmusgrf", "syscon";
@@ -88,6 +62,16 @@
u-boot,dm-pre-reloc;
 };
 
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
+ {
+   u-boot,dm-pre-reloc;
+   status = "okay";
+};
+
 _phy {
u-boot,dm-pre-reloc;
 };
diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi
index 3871c7fd83b..92c2207e686 100644
--- a/arch/arm/dts/rk3399.dtsi
+++ b/arch/arm/dts/rk3399.dtsi
@@ -124,6 +124,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <_SLEEP _SLEEP>;
+
+   thermal-idle {
+   #cooling-cells = <2>;
+   duration-us = <1>;
+   exit-latency-us = <500>;
+   };
};
 
cpu_b1: cpu@101 {
@@ -136,6 +142,12 @@
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <436>;
cpu-idle-states = <_SLEEP _SLEEP>;
+
+   thermal-idle {
+   #cooling-cells = <2>;
+   duration-us = <1>;
+   exit-latency-us = <500>;
+   };
};
 
idle-states {
@@ -166,6 +178,15 @@
ports = <_out>, <_out>;
};
 
+   dmc: memory-controller {
+   compatible = "rockchip,rk3399-dmc";
+   rockchip,pmu = <>;
+   devfreq-events = <>;
+   clocks = < SCLK_DDRC>;
+   clock-names = "dmc_clk";
+   status = "disabled";
+   };
+
pmu_a53 {
compatible = "arm,cortex-a53-pmu";
interrupts = ;
@@ -361,6 +382,54 @@
status = "disabled";
};
 
+   debug@fe43 {
+   compatible = "arm,coresight-cpu-debug", "arm,primecell";
+   reg = <0 0xfe43 0 0x1000>;
+   

[PATCH 2/3] arm64: dts: rk3399: Add upstream Pinephone Pro dts

[Peter Robinson]

Initial support for the PinePhone Pro has now landed upstream in
Linux 6.1 RC1 so sync the dts from upstream for initial support.

Signed-off-by: Peter Robinson 
---
 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3399-pinephone-pro.dts | 398 ++
 2 files changed, 399 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 965895bc2a3..624c4f997c3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -153,6 +153,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-nanopi-r4s.dtb \
rk3399-orangepi.dtb \
rk3399-pinebook-pro.dtb \
+   rk3399-pinephone-pro.dtb \
rk3399-puma-haikou.dtb \
rk3399-roc-pc.dtb \
rk3399-roc-pc-mezzanine.dtb \
diff --git a/arch/arm/dts/rk3399-pinephone-pro.dts 
b/arch/arm/dts/rk3399-pinephone-pro.dts
new file mode 100644
index 000..2e058c31502
--- /dev/null
+++ b/arch/arm/dts/rk3399-pinephone-pro.dts
@@ -0,0 +1,398 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Martijn Braam 
+ * Copyright (c) 2021 Kamil Trzciński 
+ */
+
+/*
+ * PinePhone Pro datasheet:
+ * 
https://files.pine64.org/doc/PinePhonePro/PinephonePro-Schematic-V1.0-20211127.pdf
+ */
+
+/dts-v1/;
+#include 
+#include "rk3399.dtsi"
+#include "rk3399-opp.dtsi"
+
+/ {
+   model = "Pine64 PinePhonePro";
+   compatible = "pine64,pinephone-pro", "rockchip,rk3399";
+   chassis-type = "handset";
+
+   aliases {
+   mmc0 = 
+   mmc1 = 
+   mmc2 = 
+   };
+
+   chosen {
+   stdout-path = "serial2:115200n8";
+   };
+
+   gpio-keys {
+   compatible = "gpio-keys";
+   pinctrl-names = "default";
+   pinctrl-0 = <_pin>;
+
+   key-power {
+   debounce-interval = <20>;
+   gpios = < RK_PA5 GPIO_ACTIVE_LOW>;
+   label = "Power";
+   linux,code = ;
+   wakeup-source;
+   };
+   };
+
+   vcc_sys: vcc-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vcc3v3_sys: vcc3v3-sys-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcc3v3_sys";
+   regulator-always-on;
+   regulator-boot-on;
+   regulator-min-microvolt = <330>;
+   regulator-max-microvolt = <330>;
+   vin-supply = <_sys>;
+   };
+
+   vcca1v8_s3: vcc1v8-s3-regulator {
+   compatible = "regulator-fixed";
+   regulator-name = "vcca1v8_s3";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <_sys>;
+   regulator-always-on;
+   regulator-boot-on;
+   };
+
+   vcc1v8_codec: vcc1v8-codec-regulator {
+   compatible = "regulator-fixed";
+   enable-active-high;
+   gpio = < RK_PA4 GPIO_ACTIVE_HIGH>;
+   pinctrl-names = "default";
+   pinctrl-0 = <_codec_en>;
+   regulator-name = "vcc1v8_codec";
+   regulator-min-microvolt = <180>;
+   regulator-max-microvolt = <180>;
+   vin-supply = <_sys>;
+   };
+};
+
+_l0 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l1 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l2 {
+   cpu-supply = <_cpu_l>;
+};
+
+_l3 {
+   cpu-supply = <_cpu_l>;
+};
+
+_b0 {
+   cpu-supply = <_cpu_b>;
+};
+
+_b1 {
+   cpu-supply = <_cpu_b>;
+};
+
+_phy {
+   status = "okay";
+};
+
+ {
+   clock-frequency = <40>;
+   i2c-scl-rising-time-ns = <168>;
+   i2c-scl-falling-time-ns = <4>;
+   status = "okay";
+
+   rk818: pmic@1c {
+   compatible = "rockchip,rk818";
+   reg = <0x1c>;
+   interrupt-parent = <>;
+   interrupts = ;
+   #clock-cells = <1>;
+   clock-output-names = "xin32k", "rk808-clkout2";
+   pinctrl-names = "default";
+   pinctrl-0 = <_int_l>;
+   rockchip,system-power-controller;
+   wakeup-source;
+
+   vcc1-supply = <_sys>;
+   vcc2-supply = <_sys>;
+   vcc3-supply = <_sys>;
+   vcc4-supply = <_sys>;
+   vcc6-supply = <_sys>;
+   vcc7-supply = <_sys>;
+   vcc8-supply = <_sys>;
+   vcc9-supply = <_sys>;
+
+   regulators {
+   vdd_cpu_l: DCDC_REG1 {
+   regulator-name = "vdd_cpu_l";
+   regulator-always-on;
+   regulator-boot-on;
+ 

[PATCH 0/3] Initial support for Pinephone Pro

[Peter Robinson]

This adds initial support for the PINE64 Pinephone Pro. It's a rebase
to upstream core rk3399 DT pieces, and the addition of the upstream
PPP DT from 6.1-rc1 and the U-Boot pieces are based on my work on
the Pinebook Pro.

Peter Robinson (3):
  arm64: dts: rk3399: sync rk3399.dtsi from 6.1-rc1
  arm64: dts: rk3399: Add upstream Pinephone Pro dts
  rockchip: Add initial support for the PINE64 Pinephone Pro

 arch/arm/dts/Makefile |   1 +
 arch/arm/dts/rk3399-opp.dtsi  |   6 +-
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  39 ++
 arch/arm/dts/rk3399-pinephone-pro.dts | 398 ++
 arch/arm/dts/rk3399-u-boot.dtsi   |  36 +-
 arch/arm/dts/rk3399.dtsi  | 200 -
 arch/arm/mach-rockchip/rk3399/Kconfig |   8 +
 board/pine64/pinephone-pro-rk3399/Kconfig |  15 +
 board/pine64/pinephone-pro-rk3399/MAINTAINERS |   8 +
 board/pine64/pinephone-pro-rk3399/Makefile|   1 +
 .../pinephone-pro-rk3399.c|  76 
 configs/pinephone-pro-rk3399_defconfig| 104 +
 drivers/clk/rockchip/clk_rk3399.c |   2 +-
 include/configs/pinephone-pro-rk3399.h|  19 +
 include/dt-bindings/clock/rk3399-cru.h|  24 +-
 include/dt-bindings/power/rk3399-power.h  |   1 +
 16 files changed, 875 insertions(+), 63 deletions(-)
 create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
 create mode 100644 arch/arm/dts/rk3399-pinephone-pro.dts
 create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
 create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
 create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
 create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
 create mode 100644 configs/pinephone-pro-rk3399_defconfig
 create mode 100644 include/configs/pinephone-pro-rk3399.h

-- 
2.38.1

[PATCH 3/3] rockchip: Add initial support for the PINE64 Pinephone Pro

[Peter Robinson]

The Pinephone Pro is another device by PINE64. It's closely related
to the Pinebook Pro of which this initial support is derived from.

Specification:
- A variant of the Rockchip RK3399
- A 6 inch 720*1440 DSI display
- Front and rear cameras
- Type-C interface with alt mode display (DP 1.2) and PD charging
- 4GB LPDDR4 RAM
- 128GB eMMC
- mSD card slot
- An AP6255 module for 802.11ac WiFi and Bluetooth 5
- Quectel EG25-G 4G/LTE modem

Signed-off-by: Peter Robinson 
---
 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi |  39 +++
 arch/arm/mach-rockchip/rk3399/Kconfig |   8 ++
 board/pine64/pinephone-pro-rk3399/Kconfig |  15 +++
 board/pine64/pinephone-pro-rk3399/MAINTAINERS |   8 ++
 board/pine64/pinephone-pro-rk3399/Makefile|   1 +
 .../pinephone-pro-rk3399.c|  76 +
 configs/pinephone-pro-rk3399_defconfig| 104 ++
 include/configs/pinephone-pro-rk3399.h|  19 
 8 files changed, 270 insertions(+)
 create mode 100644 arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
 create mode 100644 board/pine64/pinephone-pro-rk3399/Kconfig
 create mode 100644 board/pine64/pinephone-pro-rk3399/MAINTAINERS
 create mode 100644 board/pine64/pinephone-pro-rk3399/Makefile
 create mode 100644 board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
 create mode 100644 configs/pinephone-pro-rk3399_defconfig
 create mode 100644 include/configs/pinephone-pro-rk3399.h

diff --git a/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi 
b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
new file mode 100644
index 000..c9f1f4af635
--- /dev/null
+++ b/arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Peter Robinson 
+ */
+
+#include "rk3399-u-boot.dtsi"
+#include "rk3399-sdram-lpddr4-100.dtsi"
+
+/ {
+   chosen {
+   u-boot,spl-boot-order = "same-as-spl", , 
+   };
+
+   config {
+   u-boot,spl-payload-offset = <0x6>; /* @ 384KB */
+   };
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   status = "okay";
+};
+
+ {
+   max-frequency = <2500>;
+   u-boot,dm-pre-reloc;
+};
+
+ {
+   max-frequency = <2000>;
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig 
b/arch/arm/mach-rockchip/rk3399/Kconfig
index b48feeb3466..d01063ac98b 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -39,6 +39,13 @@ config TARGET_PINEBOOK_PRO_RK3399
  with 4Gb RAM, onboard eMMC, USB-C, a USB3 and USB2 port,
  1920*1080 screen and all the usual laptop features.
 
+config TARGET_PINEPHONE_PRO_RK3399
+   bool "PinePhone Pro"
+   help
+ PinePhone Pro is a phone based on a variant of the Rockchip
+ rk3399 SoC with 4Gb RAM, onboard eMMC, USB-C, headphone jack,
+ 720x1440 screen and a Quectel 4G/LTE modem.
+
 config TARGET_PUMA_RK3399
bool "Theobroma Systems RK3399-Q7 (Puma)"
help
@@ -165,6 +172,7 @@ endif # BOOTCOUNT_LIMIT
 source "board/firefly/roc-pc-rk3399/Kconfig"
 source "board/google/gru/Kconfig"
 source "board/pine64/pinebook-pro-rk3399/Kconfig"
+source "board/pine64/pinephone-pro-rk3399/Kconfig"
 source "board/pine64/rockpro64_rk3399/Kconfig"
 source "board/rockchip/evb_rk3399/Kconfig"
 source "board/theobroma-systems/puma_rk3399/Kconfig"
diff --git a/board/pine64/pinephone-pro-rk3399/Kconfig 
b/board/pine64/pinephone-pro-rk3399/Kconfig
new file mode 100644
index 000..13d6465ae6e
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_PINEPHONE_PRO_RK3399
+
+config SYS_BOARD
+   default "pinephone-pro-rk3399"
+
+config SYS_VENDOR
+   default "pine64"
+
+config SYS_CONFIG_NAME
+   default "pinephone-pro-rk3399"
+
+config BOARD_SPECIFIC_OPTIONS
+   def_bool y
+
+endif
diff --git a/board/pine64/pinephone-pro-rk3399/MAINTAINERS 
b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
new file mode 100644
index 000..c923ff1be32
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/MAINTAINERS
@@ -0,0 +1,8 @@
+PINEPHONE_PRO
+M: Peter Robinson 
+S: Maintained
+F: board/pine64/rk3399-pinephone-pro/
+F: include/configs/rk3399-pinephone-pro.h
+F: arch/arm/dts/rk3399-pinephone-pro.dts
+F: arch/arm/dts/rk3399-pinephone-pro-u-boot.dtsi
+F: configs/pinephone-pro-rk3399_defconfig
diff --git a/board/pine64/pinephone-pro-rk3399/Makefile 
b/board/pine64/pinephone-pro-rk3399/Makefile
new file mode 100644
index 000..8d9203053e5
--- /dev/null
+++ b/board/pine64/pinephone-pro-rk3399/Makefile
@@ -0,0 +1 @@
+obj-y  += pinephone-pro-rk3399.o
diff --git a/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c 
b/board/pine64/pinephone-pro-rk3399/pinephone-pro-rk3399.c
new file mode 100644
index 000..eb639cd0d07
--- /dev/null
+++ 

[PATCH v1 5/6] clk: microchip: mpfs: fix criticality of peripheral clocks

[Conor Dooley]

Sync the critical clocks in the U-Boot driver with those marked as
critical in Linux. The Linux driver has an explanation of why each clock
is considered to be critical, so import that too.

Fixes: 2f27c9219e ("clk: Add Microchip PolarFire SoC clock driver")
Signed-off-by: Conor Dooley 
---
 drivers/clk/microchip/mpfs_clk_periph.c | 28 ++---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/drivers/clk/microchip/mpfs_clk_periph.c 
b/drivers/clk/microchip/mpfs_clk_periph.c
index e23eb552c3..ddeccb9145 100644
--- a/drivers/clk/microchip/mpfs_clk_periph.c
+++ b/drivers/clk/microchip/mpfs_clk_periph.c
@@ -114,13 +114,27 @@ static ulong mpfs_periph_clk_recalc_rate(struct clk *hw)
.periph.flags = _flags, \
}
 
+/*
+ * Critical clocks:
+ * - CLK_ENVM: reserved by hart software services (hss) superloop monitor/m 
mode interrupt
+ *   trap handler
+ * - CLK_MMUART0: reserved by the hss
+ * - CLK_DDRC: provides clock to the ddr subsystem
+ * - CLK_RTC: the onboard RTC's AHB bus clock must be kept running as the rtc 
will stop
+ *   if the AHB interface clock is disabled
+ * - CLK_FICx: these provide the processor side clocks to the "FIC" (Fabric 
InterConnect)
+ *   clock domain crossers which provide the interface to the FPGA fabric. 
Disabling them
+ *   causes the FPGA fabric to go into reset.
+ * - CLK_ATHENA: The athena clock is FIC4, which is reserved for the Athena 
TeraFire.
+ */
+
 static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
CLK_PERIPH(CLK_ENVM, "clk_periph_envm", CLK_AHB, 0, CLK_IS_CRITICAL),
CLK_PERIPH(CLK_MAC0, "clk_periph_mac0", CLK_AHB, 1, 0),
CLK_PERIPH(CLK_MAC1, "clk_periph_mac1", CLK_AHB, 2, 0),
CLK_PERIPH(CLK_MMC, "clk_periph_mmc", CLK_AHB, 3, 0),
CLK_PERIPH(CLK_TIMER, "clk_periph_timer", CLK_RTCREF, 4, 0),
-   CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, 0),
+   CLK_PERIPH(CLK_MMUART0, "clk_periph_mmuart0", CLK_AHB, 5, 
CLK_IS_CRITICAL),
CLK_PERIPH(CLK_MMUART1, "clk_periph_mmuart1", CLK_AHB, 6, 0),
CLK_PERIPH(CLK_MMUART2, "clk_periph_mmuart2", CLK_AHB, 7, 0),
CLK_PERIPH(CLK_MMUART3, "clk_periph_mmuart3", CLK_AHB, 8, 0),
@@ -132,17 +146,17 @@ static struct mpfs_periph_hw_clock mpfs_periph_clks[] = {
CLK_PERIPH(CLK_CAN0, "clk_periph_can0", CLK_AHB, 14, 0),
CLK_PERIPH(CLK_CAN1, "clk_periph_can1", CLK_AHB, 15, 0),
CLK_PERIPH(CLK_USB, "clk_periph_usb", CLK_AHB, 16, 0),
-   CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, 0),
+   CLK_PERIPH(CLK_RTC, "clk_periph_rtc", CLK_AHB, 18, CLK_IS_CRITICAL),
CLK_PERIPH(CLK_QSPI, "clk_periph_qspi", CLK_AHB, 19, 0),
CLK_PERIPH(CLK_GPIO0, "clk_periph_gpio0", CLK_AHB, 20, 0),
CLK_PERIPH(CLK_GPIO1, "clk_periph_gpio1", CLK_AHB, 21, 0),
CLK_PERIPH(CLK_GPIO2, "clk_periph_gpio2", CLK_AHB, 22, 0),
CLK_PERIPH(CLK_DDRC, "clk_periph_ddrc", CLK_AHB, 23, CLK_IS_CRITICAL),
-   CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, 0),
-   CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, 0),
-   CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, 0),
-   CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, 0),
-   CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, 0),
+   CLK_PERIPH(CLK_FIC0, "clk_periph_fic0", CLK_AXI, 24, CLK_IS_CRITICAL),
+   CLK_PERIPH(CLK_FIC1, "clk_periph_fic1", CLK_AXI, 25, CLK_IS_CRITICAL),
+   CLK_PERIPH(CLK_FIC2, "clk_periph_fic2", CLK_AXI, 26, CLK_IS_CRITICAL),
+   CLK_PERIPH(CLK_FIC3, "clk_periph_fic3", CLK_AXI, 27, CLK_IS_CRITICAL),
+   CLK_PERIPH(CLK_ATHENA, "clk_periph_athena", CLK_AXI, 28, 
CLK_IS_CRITICAL),
CLK_PERIPH(CLK_CFM, "clk_periph_cfm", CLK_AHB, 29, 0),
 };
 
-- 
2.38.0

[PATCH v1 2/6] clk: microchip: mpfs: convert parent rate acquistion to get_get_rate()

[Conor Dooley]

Currently the clock driver for PolarFire SoC takes a very naive approach
to the relationship between clocks. It reads the dt to get an input
clock, assumes that that is fixed frequency, reads the "clock-frequency"
property & uses that to set up both the "cfg" and "periph" clocks.

Simplifying for the sake of incremental fixes, the "correct" parentage for
the clocks currently supported in U-Boot is that the "cfg" clocks should
be children of the fixed frequency clock in the dt. The AHB clock is one
of these "cfg" clocks and is the parent of the "periph" clocks.

Instead of passing the clock rate of the fixed-frequency clock to the
"cfg" and "periph" registration functions and the name of the parents,
pass their actual parents & use clk_get_rate() to determine their parents
rates.

The "periph" clocks are purely gate clocks and should not be reading the
AHB clocks registers to determine their rates, as they can simply report
the output of clk_get_rate() on their parent.

Signed-off-by: Conor Dooley 
---
 drivers/clk/microchip/Makefile  |  2 +-
 drivers/clk/microchip/mpfs_clk.c| 18 --
 drivers/clk/microchip/mpfs_clk.h| 12 
 drivers/clk/microchip/mpfs_clk_cfg.c|  7 +++
 drivers/clk/microchip/mpfs_clk_periph.c | 16 
 5 files changed, 20 insertions(+), 35 deletions(-)

diff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile
index 904b345d75..329b2c0c93 100644
--- a/drivers/clk/microchip/Makefile
+++ b/drivers/clk/microchip/Makefile
@@ -1 +1 @@
-obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o
+obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o
diff --git a/drivers/clk/microchip/mpfs_clk.c b/drivers/clk/microchip/mpfs_clk.c
index 67828c9bf4..7ba1218b56 100644
--- a/drivers/clk/microchip/mpfs_clk.c
+++ b/drivers/clk/microchip/mpfs_clk.c
@@ -11,34 +11,32 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include "mpfs_clk.h"
 
 static int mpfs_clk_probe(struct udevice *dev)
 {
-   int ret;
+   struct clk *parent_clk = dev_get_priv(dev);
+   struct clk clk_ahb = { .id = CLK_AHB };
void __iomem *base;
-   u32 clk_rate;
-   const char *parent_clk_name;
-   struct clk *clk = dev_get_priv(dev);
+   int ret;
 
base = dev_read_addr_ptr(dev);
if (!base)
return -EINVAL;
 
-   ret = clk_get_by_index(dev, 0, clk);
+   ret = clk_get_by_index(dev, 0, parent_clk);
if (ret)
return ret;
 
-   dev_read_u32(clk->dev, "clock-frequency", _rate);
-   parent_clk_name = clk->dev->name;
-
-   ret = mpfs_clk_register_cfgs(base, clk_rate, parent_clk_name);
+   ret = mpfs_clk_register_cfgs(base, parent_clk);
if (ret)
return ret;
 
-   ret = mpfs_clk_register_periphs(base, clk_rate, "clk_ahb");
+   clk_request(dev, _ahb);
+   ret = mpfs_clk_register_periphs(base, _ahb);
 
return ret;
 }
diff --git a/drivers/clk/microchip/mpfs_clk.h b/drivers/clk/microchip/mpfs_clk.h
index 442562a5e7..35cfeac92e 100644
--- a/drivers/clk/microchip/mpfs_clk.h
+++ b/drivers/clk/microchip/mpfs_clk.h
@@ -11,22 +11,18 @@
  * mpfs_clk_register_cfgs() - register configuration clocks
  *
  * @base: base address of the mpfs system register.
- * @clk_rate: the mpfs pll clock rate.
- * @parent_name: a pointer to parent clock name.
+ * @parent: a pointer to parent clock.
  * Return: zero on success, or a negative error code.
  */
-int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
-  const char *parent_name);
+int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent);
 /**
  * mpfs_clk_register_periphs() - register peripheral clocks
  *
  * @base: base address of the mpfs system register.
- * @clk_rate: the mpfs pll clock rate.
- * @parent_name: a pointer to parent clock name.
+ * @parent: a pointer to parent clock.
  * Return: zero on success, or a negative error code.
  */
-int mpfs_clk_register_periphs(void __iomem *base, u32 clk_rate,
- const char *parent_name);
+int mpfs_clk_register_periphs(void __iomem *base, struct clk *parent);
 /**
  * divider_get_val() - get the clock divider value
  *
diff --git a/drivers/clk/microchip/mpfs_clk_cfg.c 
b/drivers/clk/microchip/mpfs_clk_cfg.c
index fefddd1413..5739fd66e8 100644
--- a/drivers/clk/microchip/mpfs_clk_cfg.c
+++ b/drivers/clk/microchip/mpfs_clk_cfg.c
@@ -117,8 +117,7 @@ static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
 };
 
-int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
-  const char *parent_name)
+int mpfs_clk_register_cfgs(void __iomem *base, struct clk *parent)
 {
int ret;
int i, id, num_clks;
@@ -129,9 +128,9 @@ int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
for (i = 0; i < num_clks; i++) {
hw = 

[PATCH v1 6/6] riscv: dts: fix the mpfs's reference clock frequency

[Conor Dooley]

The initial devicetree for PolarFire SoC incorrectly created a fixed
frequency clock in the devicetree to represent the msspll, but the
msspll is not a fixed frequency clock. The actual reference clock on a
board is either 125 or 100 MHz, 125 MHz in the case of the icicle kit.
Swap the incorrect representation of the msspll out for the actual
reference clock.

Fixes: dd4ee416a6 ("riscv: dts: Add device tree for Microchip Icicle Kit")
Signed-off-by: Conor Dooley 
---
 arch/riscv/dts/microchip-mpfs-icicle-kit.dts |  4 
 arch/riscv/dts/microchip-mpfs.dtsi   | 14 ++
 2 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts 
b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
index e1fbedc507..7d87b181db 100644
--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
@@ -53,6 +53,10 @@
};
 };
 
+ {
+   clock-frequency = <12500>;
+};
+
  {
status = "okay";
 };
diff --git a/arch/riscv/dts/microchip-mpfs.dtsi 
b/arch/riscv/dts/microchip-mpfs.dtsi
index 4f449a3a93..891dd0918b 100644
--- a/arch/riscv/dts/microchip-mpfs.dtsi
+++ b/arch/riscv/dts/microchip-mpfs.dtsi
@@ -170,6 +170,11 @@
};
};
 
+   refclk: refclk {
+   compatible = "fixed-clock";
+   #clock-cells = <0>;
+   };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -225,16 +230,9 @@
_intc HART_INT_M_EXT _intc 
HART_INT_S_EXT>;
};
 
-   refclk: refclk {
-   compatible = "fixed-clock";
-   #clock-cells = <0>;
-   clock-frequency = <6>;
-   clock-output-names = "msspllclk";
-   };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
-   reg = <0x0 0x20002000 0x0 0x1000>;
+   reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 
0x1000>;
reg-names = "mss_sysreg";
clocks = <>;
#clock-cells = <1>;
-- 
2.38.0