Re: [PATCH 2/2] CI: Make use of buildman requirements.txt
Hi Tom Thanks for these patches! On 27/04/23 01:14, Tom Rini wrote: Now that buildman has a requirements.txt file we need to make use of it. Signed-off-by: Tom Rini --- .azure-pipelines.yml | 3 +++ .gitlab-ci.yml | 4 2 files changed, 7 insertions(+) However, while trying to ensure CI/CD coverage, I'm running into this " error 'No module named 'jsonschema'" for am62ax [1], any idea why after building successfully for other devices? [1] https://dev.azure.com/u-boot/u-boot/_build/results?buildId=6236=logs=6fe7c803-7a3b-5b46-f057-c1c62fd89ba1=22dc4ac5-ae35-5978-08ac-5f386151834e=fae48c67-4bb5-5f06-119f-00d23f780e3c -- Thanking You Neha Malcom Francis
[PATCH] configs: j7200: correct mmc offset
This patch corrects the MMC raw mode sector offset as
per documentation.
https://software-dl.ti.com/jacinto7/esd/processor-sdk-linux-j7200/08_06_00_11/exports/docs/j7200/linux/Foundational_Components/U-Boot/UG-Memory.html
Section: eMMC layout
Without this correct offset eMMC boot with UDA partition will fail.
Fixes: f8c1e893c82 (configs: j7200_evm_a72: Add Initial suppot)
Fixes: 02dff65efe7 (configs: j7200_evm_r5: Add initial support)
Fixes: 360c7f46f39 (configs: Add configs for J7200 High Security EVM)
Way to test with eMMC UDA partition
=> mmc dev 0 0
=> fatload mmc 1 ${loadaddr} tiboot3.bin
=> mmc write ${loadaddr} 0x0 0x800
=> fatload mmc 1 ${loadaddr} tispl.bin
=> mmc write ${loadaddr} 0x800 0x1000
=> fatload mmc 1 ${loadaddr} u-boot.img
=> mmc write ${loadaddr} 0x1800 0x2000
=> mmc partconf 0 1 7 1
=> mmc bootbus 0 2 0 0
Cc: Bhavya Kapoor
Cc: Diwakar Dhyani
Cc: KEERTHY
Signed-off-by: Udit Kumar
---
configs/j7200_evm_a72_defconfig| 2 +-
configs/j7200_evm_r5_defconfig | 2 +-
configs/j7200_hs_evm_a72_defconfig | 2 +-
configs/j7200_hs_evm_r5_defconfig | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index fa5ea2aecd..8a810f8f48 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -46,7 +46,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x80
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig
index 00ec48b83b..908cfaf402 100644
--- a/configs/j7200_evm_r5_defconfig
+++ b/configs/j7200_evm_r5_defconfig
@@ -43,7 +43,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8400
CONFIG_SYS_SPL_MALLOC_SIZE=0x100
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
diff --git a/configs/j7200_hs_evm_a72_defconfig
b/configs/j7200_hs_evm_a72_defconfig
index d9560727ed..c234a58a7a 100644
--- a/configs/j7200_hs_evm_a72_defconfig
+++ b/configs/j7200_hs_evm_a72_defconfig
@@ -47,7 +47,7 @@ CONFIG_SPL_STACK_R=y
CONFIG_SYS_SPL_MALLOC=y
CONFIG_SYS_SPL_MALLOC_SIZE=0x80
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
diff --git a/configs/j7200_hs_evm_r5_defconfig
b/configs/j7200_hs_evm_r5_defconfig
index 94a6523f06..74015db1af 100644
--- a/configs/j7200_hs_evm_r5_defconfig
+++ b/configs/j7200_hs_evm_r5_defconfig
@@ -43,7 +43,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8400
CONFIG_SYS_SPL_MALLOC_SIZE=0x100
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
-CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_EXT4=y
--
2.34.1
Re: [PATCH v2 24/30] sandbox: Provide an EFI link script for PE
Hi Simon,
On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote:
>
> Add another case for sandbox, when it is built on Windows.
>
> Signed-off-by: Simon Glass
> ---
>
> (no changes since v1)
>
> arch/sandbox/config.mk | 4 +-
> arch/x86/lib/crt0_x86_64_efi.S | 2 +
> arch/x86/lib/pe_x86_64_efi.lds | 83 ++
> 3 files changed, 88 insertions(+), 1 deletion(-)
> create mode 100644 arch/x86/lib/pe_x86_64_efi.lds
>
> diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
> index c97c39d4301b..d397ae3fe29b 100644
> --- a/arch/sandbox/config.mk
> +++ b/arch/sandbox/config.mk
> @@ -44,7 +44,9 @@ cmd_u-boot-spl = (cd $(obj) && $(CC) -o $(SPL_BIN) -Wl,-T
> u-boot-spl.lds \
> -Wl,--no-whole-archive \
> $(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot-spl.map -Wl,--gc-sections)
>
> -ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
> +ifneq ($(MSYS_VERSION),0)
> +EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/pe_x86_64_efi.lds
> +else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86_64))
> EFI_LDS := ${SRCDIR}/../../../arch/x86/lib/elf_x86_64_efi.lds
> EFI_TARGET := --target=efi-app-x86_64
> else ifeq ($(HOST_ARCH),$(HOST_ARCH_X86))
> diff --git a/arch/x86/lib/crt0_x86_64_efi.S b/arch/x86/lib/crt0_x86_64_efi.S
> index 47ed5af97228..cd61b4bdd82f 100644
> --- a/arch/x86/lib/crt0_x86_64_efi.S
> +++ b/arch/x86/lib/crt0_x86_64_efi.S
> @@ -15,6 +15,7 @@
> _start:
> subq $8, %rsp
>
> +#ifndef __CYGWIN__
I think this should be __MSYS2__?
> pushq %rcx
> pushq %rdx
>
> @@ -28,6 +29,7 @@ _start:
>
> testq %rax, %rax
> jnz .exit
> +#endif
>
> call efi_main
> .exit:
> diff --git a/arch/x86/lib/pe_x86_64_efi.lds b/arch/x86/lib/pe_x86_64_efi.lds
> new file mode 100644
> index ..1ee08f6e662e
> --- /dev/null
> +++ b/arch/x86/lib/pe_x86_64_efi.lds
> @@ -0,0 +1,83 @@
> +/* SPDX-License-Identifier: BSD-2-Clause */
> +/*
> + * U-Boot EFI linker script
> + *
> + * Modified from usr/lib32/elf_x86_64_efi.lds in gnu-efi
> + */
> +
> +OUTPUT_FORMAT("pe-x86-64", "pe-x86-64", "pe-x86-64")
> +OUTPUT_ARCH(i386:x86-64)
> +ENTRY(_start)
> +SECTIONS
> +{
> + image_base = .;
> + .hash : { *(.hash) }/* this MUST come first, EFI expects it */
> + . = ALIGN(4096);
> + .eh_frame : {
> + *(.eh_frame)
> + }
> +
> + . = ALIGN(4096);
> +
> + .text : {
> + *(.text)
> + *(.text.*)
> + *(.gnu.linkonce.t.*)
> + }
> +
> + . = ALIGN(4096);
> +
> + .reloc : {
> + *(.reloc)
> + }
> +
> + . = ALIGN(4096);
> +
> + .data : {
> + *(.rodata*)
> + *(.got.plt)
> + *(.got)
> + *(.data*)
> + *(.sdata)
> + /* the EFI loader doesn't seem to like a .bss section, so we
> stick
> +* it all into .data: */
> + *(.sbss)
> + *(.scommon)
> + *(.dynbss)
> + *(.bss*)
> + *(COMMON)
> + *(.rel.local)
> +
> + /* U-Boot lists and device tree */
> + . = ALIGN(8);
> + *(SORT(__u_boot_list*));
> + . = ALIGN(8);
> + *(.dtb*);
> + }
> +
> + . = ALIGN(4096);
> + .dynamic : { *(.dynamic) }
> + . = ALIGN(4096);
> +
> + .rela : {
> + *(.rela.data*)
> + *(.rela.got)
> + *(.rela.stab)
> +*(.rela__u_boot_list*)
> + }
> +
> + . = ALIGN(4096);
> + .dynsym : { *(.dynsym) }
> + . = ALIGN(4096);
> + .dynstr : { *(.dynstr) }
> + . = ALIGN(4096);
> +
> +/DISCARD/ : { *(.eh_frame) }
> +
> + .ignored.reloc : {
> + *(.rela.reloc)
> + *(.note.GNU-stack)
> + }
> +
> + .comment 0 : { *(.comment) }
> +}
> --
Regards,
Bin
Re: [PATCH v2 23/30] sandbox: Augment the linker script for MSYS2
Hi Simon,
On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote:
>
> We need to place the linker lists, etc. in the .rdata section but this
> is not possible with the default linker script. We can only add new
> sections, which causes Windows to give an "Exec format error" error.
>
> Add a rule to create a new linker script, by obtaining the one from
> the linker and adding some things to the end of the .rdata section.
I am not sure I understand this. So the arch/sandbox/cpu/u-boot.lds
does not work for MSYS2?
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Add an awk script to augment the built-in link script
>
> Makefile | 17 -
> arch/sandbox/config.mk| 19 ++-
> arch/sandbox/cpu/u-boot-pe.lds.in | 25 +
> scripts/add_to_rdata.awk | 25 +
> 4 files changed, 80 insertions(+), 6 deletions(-)
> create mode 100644 arch/sandbox/cpu/u-boot-pe.lds.in
> create mode 100644 scripts/add_to_rdata.awk
>
> diff --git a/Makefile b/Makefile
> index a328652f0f23..760c143049aa 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -1734,6 +1734,12 @@ else
> u-boot-keep-syms-lto :=
> endif
>
> +ifeq ($(MSYS_VERSION),0)
> +add_ld_script := -T u-boot.lds
> +else
> +add_ld_script := u-boot.lds
MSYS2 does not need "-T"?
> +endif
> +
> # Rule to link u-boot
> # May be overridden by arch/$(ARCH)/config.mk
> ifeq ($(LTO_ENABLE),y)
> @@ -1742,7 +1748,7 @@ quiet_cmd_u-boot__ ?= LTO $@
> $(CC) -nostdlib -nostartfiles
> \
> $(LTO_FINAL_LDFLAGS) $(c_flags)
> \
> $(KBUILD_LDFLAGS:%=-Wl,%) $(LDFLAGS_u-boot:%=-Wl,%) -o $@
> \
> - -T u-boot.lds $(u-boot-init)
> \
> + $(add_ld_script) $(u-boot-init)
> \
> -Wl,--whole-archive
> \
> $(u-boot-main)
> \
> $(u-boot-keep-syms-lto)
> \
> @@ -1753,7 +1759,7 @@ quiet_cmd_u-boot__ ?= LTO $@
> else
> quiet_cmd_u-boot__ ?= LD $@
>cmd_u-boot__ ?= $(LD) $(KBUILD_LDFLAGS) $(LDFLAGS_u-boot) -o $@
> \
> - -T u-boot.lds $(u-boot-init)
> \
> + $(add_ld_script) $(u-boot-init)
> \
> --whole-archive
> \
> $(u-boot-main)
> \
> --no-whole-archive
> \
> @@ -1905,10 +1911,11 @@ endif
> # prepare2 creates a makefile if using a separate output directory
> prepare2: prepare3 outputmakefile cfg
>
> +# Allow the linker script to be generated from LDSCRIPT_IN
> prepare1: prepare2 $(version_h) $(timestamp_h) $(dt_h) $(env_h) \
> - include/config/auto.conf
> -ifeq ($(wildcard $(LDSCRIPT)),)
> - @echo >&2 " Could not find linker script."
> + include/config/auto.conf $(if $(LDSCRIPT_IN),$(LDSCRIPT))
> +ifeq ($(wildcard $(LDSCRIPT))$(LDSCRIPT_IN),)
> + @echo >&2 " Could not find linker script $(LDSCRIPT)"
> @/bin/false
> endif
>
> diff --git a/arch/sandbox/config.mk b/arch/sandbox/config.mk
> index 2d184c5f652a..c97c39d4301b 100644
> --- a/arch/sandbox/config.mk
> +++ b/arch/sandbox/config.mk
> @@ -1,4 +1,4 @@
> -# SPDX-License-Identifier: GPL-2.0+
> + # SPDX-License-Identifier: GPL-2.0+
> # Copyright (c) 2011 The Chromium OS Authors.
>
> PLATFORM_CPPFLAGS += -D__SANDBOX__ -U_FORTIFY_SOURCE
> @@ -71,3 +71,20 @@ EFI_CRT0 := crt0_sandbox_efi.o
> EFI_RELOC := reloc_sandbox_efi.o
> AFLAGS_crt0_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
> CFLAGS_reloc_sandbox_efi.o += -DHOST_ARCH="$(HOST_ARCH)"
> +
> +ifneq ($(MSYS_VERSION),0)
> +LDSCRIPT := $(objtree)/u-boot-pe.lds
> +
> +AWK_RDATA := ${srctree}/scripts/add_to_rdata.awk
> +LDSCRIPT_IN := ${srctree}/arch/sandbox/cpu/u-boot-pe.lds.in
> +
> +quiet_cmd_gen_lds = GEN LDS $@
> +cmd_gen_lds = echo "int main() { return 0; }" | $(CC) -x c - -Wl,-verbose | \
> + awk -f $(AWK_RDATA) -v INFILE=$< >$@
> +
> +# Write out the contents of INFILE immediately before the close of the .rdata
> +# block
> +$(LDSCRIPT): $(LDSCRIPT_IN) $(AWK_RDATA) FORCE
> + $(call if_changed,gen_lds)
> +
> +endif
> diff --git a/arch/sandbox/cpu/u-boot-pe.lds.in
> b/arch/sandbox/cpu/u-boot-pe.lds.in
> new file mode 100644
> index ..0ec7ef3bb350
> --- /dev/null
> +++ b/arch/sandbox/cpu/u-boot-pe.lds.in
> @@ -0,0 +1,25 @@
> + /* U-Boot additions from here on */
> + . = ALIGN(4);
> + KEEP(*(SORT(__u_boot_list*)));
> +
> +
[PATCH 14/14] arch: arm: dts: k3-j7200: Add MCSPI nodes
From: Vaishnav Achath
Upstream Linux commit id 8f6c475f4ca7a
J7200 has 8 MCSPI instances in the main domain and 3 instances
in the MCU domain. Add the DT nodes for all the 11 instances and
keep them disabled. MAIN_MCSPI4 is connected as a slave to MCU_MCSPI2
by default at power-up, MAIN_MCSPI4 and MCU_MCSPI2 are not pinned out
externally.
Signed-off-by: Vaishnav Achath
Reviewed-by: Keerthy
Link: https://lore.kernel.org/r/20230321082827.14274-3-vaishna...@ti.com
Signed-off-by: Nishanth Menon
---
arch/arm/dts/k3-j7200-main.dtsi | 88 +++
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 33 ++
2 files changed, 121 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index 3dfbeca4ef..be8034bf5b 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -798,6 +798,94 @@
clock-names = "gpio";
};
+ main_spi0: spi@210 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0210 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 266 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 266 1>;
+ status = "disabled";
+ };
+
+ main_spi1: spi@211 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0211 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 267 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 267 1>;
+ status = "disabled";
+ };
+
+ main_spi2: spi@212 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0212 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 268 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 268 1>;
+ status = "disabled";
+ };
+
+ main_spi3: spi@213 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0213 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 269 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 269 1>;
+ status = "disabled";
+ };
+
+ main_spi4: spi@214 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0214 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 270 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 270 1>;
+ status = "disabled";
+ };
+
+ main_spi5: spi@215 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0215 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 271 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 271 1>;
+ status = "disabled";
+ };
+
+ main_spi6: spi@216 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0216 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 272 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 272 1>;
+ status = "disabled";
+ };
+
+ main_spi7: spi@217 {
+ compatible = "ti,am654-mcspi","ti,omap4-mcspi";
+ reg = <0x00 0x0217 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 273 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 273 1>;
+ status = "disabled";
+ };
+
watchdog0: watchdog@220 {
compatible = "ti,j7-rti-wdt";
reg = <0x0 0x220 0x0 0x100>;
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index e302c3d6ac..3328f4bc6f 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -453,6 +453,39 @@
status = "disabled";
};
+ mcu_spi0: spi@4030 {
+ compatible = "ti,am654-mcspi", "ti,omap4-mcspi";
+ reg = <0x00 0x04030 0x00 0x400>;
+ interrupts = ;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <_pds 274 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <_clks 274 0>;
+ status =
[PATCH 13/14] arch: arm: dts: k3-j7200 rearrange bootph property in various node
To align with kernel and remove duplication rearrange boothm node.
Signed-off-by: Udit Kumar
---
.../k3-j7200-common-proc-board-u-boot.dtsi| 45 ---
arch/arm/dts/k3-j7200-common-proc-board.dts | 3 ++
arch/arm/dts/k3-j7200-main.dtsi | 3 ++
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 2 +
arch/arm/dts/k3-j7200-som-p0.dtsi | 1 +
5 files changed, 9 insertions(+), 45 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index e5ae8f44ed..fa3baf242b 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -3,14 +3,6 @@
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
-_main {
- bootph-pre-ram;
-};
-
-_navss {
- bootph-pre-ram;
-};
-
_mcu_wakeup {
bootph-pre-ram;
@@ -62,10 +54,6 @@
};
};
-_proxy_main {
- bootph-pre-ram;
-};
-
{
bootph-pre-ram;
k3_sysreset: sysreset-controller {
@@ -86,22 +74,6 @@
bootph-pre-ram;
};
-_pmx0 {
- bootph-pre-ram;
-};
-
-_pmx0 {
- bootph-pre-ram;
-};
-
-_uart0 {
- bootph-pre-ram;
-};
-
-_uart0 {
- bootph-pre-ram;
-};
-
_sdhci0 {
bootph-pre-ram;
};
@@ -129,19 +101,6 @@
bootph-pre-ram;
};
-_fss0_hpb0_pins_default {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
-
-_mux {
- bootph-pre-ram;
-};
-
_ln_ctrl {
u-boot,mux-autoprobe;
};
@@ -150,10 +109,6 @@
u-boot,mux-autoprobe;
};
- {
- bootph-pre-ram;
-};
-
_r5fss0 {
ti,cluster-mode = <0>;
};
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 77f9922260..9e6edecbde 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -183,6 +183,7 @@
};
_uart0 {
+ bootph-pre-ram;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_uart0_pins_default>;
@@ -190,6 +191,7 @@
};
_uart0 {
+ bootph-pre-ram;
status = "okay";
/* Shared with ATF on this platform */
power-domains = <_pds 146 TI_SCI_PD_SHARED>;
@@ -338,6 +340,7 @@
};
{
+ bootph-pre-ram;
serdes0_pcie_link: phy@0 {
reg = <0>;
cdns,num-lanes = <2>;
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index fb9e4842c1..3dfbeca4ef 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -13,6 +13,7 @@
};
_main {
+ bootph-pre-ram;
msmc_ram: sram@7000 {
compatible = "mmio-sram";
reg = <0x00 0x7000 0x00 0x10>;
@@ -84,6 +85,7 @@
};
main_navss: bus@3000 {
+ bootph-pre-ram;
compatible = "simple-mfd";
#address-cells = <2>;
#size-cells = <2>;
@@ -119,6 +121,7 @@
};
secure_proxy_main: mailbox@32c0 {
+ bootph-pre-ram;
compatible = "ti,am654-secure-proxy";
#mbox-cells = <1>;
reg-names = "target_data", "rt", "scfg";
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 7ed6c31c7c..e302c3d6ac 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -454,6 +454,7 @@
};
fss: syscon@4700 {
+ bootph-pre-ram;
compatible = "syscon", "simple-mfd";
reg = <0x00 0x4700 0x00 0x100>;
#address-cells = <2>;
@@ -461,6 +462,7 @@
ranges;
hbmc_mux: hbmc-mux {
+ bootph-pre-ram;
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4 0x2>; /* HBMC select */
diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi
b/arch/arm/dts/k3-j7200-som-p0.dtsi
index 7776f2d0ba..db1d749b52 100644
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
@@ -84,6 +84,7 @@
_pmx0 {
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (B6)
MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C8)
MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
--
2.34.1
[PATCH 12/14] arch: arm: dts: k3-j7200: cleanup hmbc node
move bootph to common file and remove duplicated
properties of node.
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 7 ---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 8 ++--
2 files changed, 2 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 6ac68720ed..e5ae8f44ed 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -137,13 +137,6 @@
bootph-pre-ram;
};
- {
- bootph-pre-ram;
-
- flash@0,0 {
- bootph-pre-ram;
- };
-};
_mux {
bootph-pre-ram;
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 30fb359489..f852df00e9 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -157,16 +157,12 @@
{
status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <_fss0_hpb0_pins_default>;
- reg = <0x0 0x4704 0x0 0x100>,
- <0x0 0x5000 0x0 0x800>;
+ bootph-pre-ram;
ranges = <0x0 0x0 0x0 0x5000 0x400>, /* 64MB Flash on CS0 */
<0x1 0x0 0x0 0x5400 0x80>; /* 8MB flash on CS1 */
flash@0,0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x0 0x400>;
+ bootph-pre-ram;
};
};
--
2.34.1
[PATCH 11/14] arch: arm: dts: k3-j7200: removed unused clock node
remove non used 19Mhz clock node
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 6 --
1 file changed, 6 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index c247ad1b2e..30fb359489 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -43,12 +43,6 @@
bootph-pre-ram;
};
- clk_19_2mhz: dummy_clock_19_2mhz {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <1920>;
- bootph-pre-ram;
- };
};
{
--
2.34.1
[PATCH 10/14] arch: arm: dts: k3-7200: cleanup r5 i2c node
This patch cleans up duplicated main_i2c node from r5 file.
Since this node needs bootph property, So add in common file.
Signed-off-by: Udit Kumar
---
.../k3-j7200-common-proc-board-u-boot.dtsi| 16 ---
arch/arm/dts/k3-j7200-common-proc-board.dts | 2 ++
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 20 ---
3 files changed, 2 insertions(+), 36 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 4c92223d2c..6ac68720ed 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -110,22 +110,6 @@
bootph-pre-ram;
};
-_i2c0 {
- bootph-pre-ram;
-};
-
-_i2c0 {
- bootph-pre-ram;
-};
-
-_i2c0_pins_default {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
-};
-
_cpsw {
reg = <0x0 0x4600 0x0 0x20>,
<0x0 0x40f00200 0x0 0x8>;
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 4fd2bb5bd6..77f9922260 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -243,6 +243,7 @@
_i2c0 {
status = "okay";
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <_i2c0_pins_default>;
clock-frequency = <40>;
@@ -255,6 +256,7 @@
};
exp2: gpio@22 {
+ bootph-pre-ram;
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 144c00efbe..c247ad1b2e 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -161,26 +161,6 @@
bootph-pre-ram;
};
-_i2c0 {
- pinctrl-names = "default";
- pinctrl-0 = <_i2c0_pins_default>;
- clock-frequency = <40>;
-
- exp1: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- exp2: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
{
status = "okay";
pinctrl-names = "default";
--
2.34.1
[PATCH 09/14] arch: arm: dts: k3-j7200: remove duplicate usb nodes
This patch remove duplicated USB node from r5 board dts
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi | 8
arch/arm/dts/k3-j7200-common-proc-board.dts | 1 +
arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 12
3 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 9b89813743..4c92223d2c 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -139,14 +139,6 @@
};
};
-_usbss0_pins_default {
- bootph-pre-ram;
-};
-
- {
- bootph-pre-ram;
- ti,usb2-only;
-};
{
dr_mode = "peripheral";
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 8cdc17dd01..4fd2bb5bd6 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -313,6 +313,7 @@
};
{
+ bootph-pre-ram;
pinctrl-names = "default";
pinctrl-0 = <_usbss0_pins_default>;
ti,vbus-divider;
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 8fbbf59cf2..144c00efbe 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -181,18 +181,6 @@
};
};
- {
- pinctrl-names = "default";
- pinctrl-0 = <_usbss0_pins_default>;
- ti,vbus-divider;
- ti,usb2-only;
-};
-
- {
- dr_mode = "otg";
- maximum-speed = "high-speed";
-};
-
{
status = "okay";
pinctrl-names = "default";
--
2.34.1
[PATCH 08/14] arch: arm: dts: k3-j7200 cleanup r5 and uboot dts
remove Alias and chosen properties
Signed-off-by: Udit Kumar
---
.../dts/k3-j7200-common-proc-board-u-boot.dtsi| 15 ---
arch/arm/dts/k3-j7200-r5-common-proc-board.dts| 6 --
2 files changed, 21 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index 789dc54617..9b89813743 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -3,21 +3,6 @@
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
*/
-/ {
- chosen {
- stdout-path = "serial2:115200n8";
- tick-timer =
- };
-
- aliases {
- ethernet0 = _port1;
- i2c0 = _i2c0;
- i2c1 = _i2c0;
- i2c2 = _i2c1;
- i2c3 = _i2c0;
- };
-};
-
_main {
bootph-pre-ram;
};
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index f8750229ad..8fbbf59cf2 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -10,13 +10,7 @@
#include "k3-j721e-ddr.dtsi"
/ {
- aliases {
- remoteproc0 =
- remoteproc1 = _0;
- };
-
chosen {
- stdout-path = _uart0;
tick-timer =
firmware-loader = _loader0;
};
--
2.34.1
[PATCH 07/14] arch: arm: dts: k3-j7200 move wkup_pmx to common file
This patch move wkup_pmx into common file, along
with cleanup of duplicated pin mux under wkup_pmx.
Also remove double define for mcu_uart.
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 24 +++-
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 55 ---
arch/arm/dts/k3-j7200-som-p0.dtsi | 3 +
3 files changed, 26 insertions(+), 56 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 98d1fde4db..8cdc17dd01 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -80,6 +80,26 @@
};
};
+_pmx0 {
+ bootph-pre-ram;
+ mcu_uart0_pins_default: mcu_uart0_pins_default {
+ bootph-pre-ram;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20)
MCU_UART0_RXD */
+ J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19)
MCU_UART0_TXD */
+ J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20)
MCU_UART0_CTSn */
+ J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21)
MCU_UART0_RTSn */
+ >;
+ };
+ wkup_uart0_pins_default: wkup_uart0_pins_default {
+ bootph-pre-ram;
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14)
WKUP_UART0_RXD */
+ J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14)
WKUP_UART0_TXD */
+ >;
+ };
+};
+
_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
@@ -164,7 +184,9 @@
_uart0 {
status = "okay";
- /* Default pinmux */
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart0_pins_default>;
+ clock-frequency = <9600>;
};
_uart0 {
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 9b42e4d2ca..f8750229ad 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -106,52 +106,6 @@
ti,secure-host;
};
-_pmx0 {
- bootph-pre-ram;
- wkup_uart0_pins_default: wkup_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14)
WKUP_UART0_RXD */
- J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14)
WKUP_UART0_TXD */
- >;
- };
-
- mcu_uart0_pins_default: mcu_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20)
WKUP_GPIO0_13.MCU_UART0_RXD */
- J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19)
WKUP_GPIO0_12.MCU_UART0_TXD */
- J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20)
WKUP_GPIO0_14.MCU_UART0_CTSn */
- J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21)
WKUP_GPIO0_15.MCU_UART0_RTSn */
- >;
- };
-
- mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20)
MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
- J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21)
MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
- J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19)
MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
- J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22)
MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
- J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19)
MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
- J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21)
MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
- J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20)
MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
- J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19)
MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
- J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20)
MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
- J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20)
MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
- J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21)
MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
- J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21)
MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
- J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22)
MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
- J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21)
MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
- >;
- };
-
- wkup_gpio_pins_default: wkup-gpio-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14)
WKUP_GPIO0_6 */
- >;
- };
-};
[PATCH 06/14] arch: arm: dts: k3-j7200 move main_pmx to common file
This patch moves pin mux from r5 dts to common dts file.
Along with removing duplicated defines.
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 16 --
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 51 +--
arch/arm/dts/k3-j7200-som-p0.dtsi | 3 ++
3 files changed, 17 insertions(+), 53 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 63633e4f6c..98d1fde4db 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -107,10 +107,15 @@
};
_pmx0 {
- main_i2c0_pins_default: main-i2c0-pins-default {
+ bootph-pre-ram;
+
+ main_uart0_pins_default: main_uart0_pins_default {
+ bootph-pre-ram;
pinctrl-single,pins = <
- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL
*/
- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA
*/
+ J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
+ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
+ J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3)
SPI0_CS0.UART0_CTSn */
+ J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5)
SPI0_CS1.UART0_RTSn */
>;
};
@@ -122,6 +127,7 @@
};
main_mmc1_pins_default: main-mmc1-pins-default {
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
@@ -142,7 +148,9 @@
};
_pmx1 {
+ bootph-pre-ram;
main_usbss0_pins_default: main-usbss0-pins-default {
+ bootph-pre-ram;
pinctrl-single,pins = <
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
@@ -163,6 +171,8 @@
status = "okay";
/* Shared with ATF on this platform */
power-domains = <_pds 146 TI_SCI_PD_SHARED>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_uart0_pins_default>;
};
_uart1 {
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index 9d9ffcbb89..9b42e4d2ca 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -5,7 +5,7 @@
/dts-v1/;
-#include "k3-j7200-som-p0.dtsi"
+#include "k3-j7200-common-proc-board.dts"
#include "k3-j7200-ddr-evm-lp4-2666.dtsi"
#include "k3-j721e-ddr.dtsi"
@@ -152,47 +152,6 @@
};
};
-_pmx0 {
- bootph-pre-ram;
-
- main_uart0_pins_default: main_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
- J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
- J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3)
SPI0_CS0.UART0_CTSn */
- J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5)
SPI0_CS1.UART0_RTSn */
- >;
- };
-
- main_i2c0_pins_default: main-i2c0-pins-default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL
*/
- J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA
*/
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
- J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
- J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
- J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
- J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
- J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
- J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1)
TIMER_IO0.MMC1_SDCD */
- >;
- };
-
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS
*/
- >;
- };
-};
-
_uart0 {
bootph-pre-ram;
pinctrl-names = "default";
@@ -210,14 +169,6 @@
clock-frequency = <9600>;
};
-_uart0 {
- status = "okay";
- power-domains = <_pds 146 TI_SCI_PD_SHARED>;
- pinctrl-names = "default";
- pinctrl-0 = <_uart0_pins_default>;
- status = "okay";
-};
-
_sdhci0 {
/delete-property/ power-domains;
/delete-property/ assigned-clocks;
diff --git
[PATCH 05/14] arch: arm: dts: k3-j7200: Configure pinctrl for timer IO pad
There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.
There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.
The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.6.3.1 Timers Overview".
For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For the even numbered timers, the CASCADE_EN bit does not do
anything. The timer cascade input routing options are shown in TRM
"Figure 12-3224. Timers Overview". For handling beyond multiplexing, the
driver support for timer cascading should be likely be handled via the
clock framework.
Cc: Nishanth Menon
Cc: Vignesh Raghavendra
Cc: Tony Lindgren
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-main.dtsi | 18 ++
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 18 ++
2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index 54795db9c3..fb9e4842c1 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -304,6 +304,24 @@
};
};
+ /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+ main_timerio_input: pinctrl@104200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104200 0x0 0x50>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x01ff>;
+ };
+
+ /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+ main_timerio_output: pinctrl@104280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x104280 0x0 0x20>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x001f>;
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 02c2493064..7ed6c31c7c 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -183,6 +183,24 @@
reg = <0x00 0x4314 0x00 0x4>;
};
+ /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+ mcu_timerio_input: pinctrl@40f04200 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04200 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x000F>;
+ };
+
+ /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+ mcu_timerio_output: pinctrl@40f04280 {
+ compatible = "pinctrl-single";
+ reg = <0x0 0x40f04280 0x0 0x28>;
+ #pinctrl-cells = <1>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x000F>;
+ };
+
wkup_pmx0: pinctrl@4301c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
--
2.34.1
[PATCH 04/14] arch: arm: dts: k3-j7200: Add general purpose timers
There are 20 general purpose timers on j7200 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional ten
timers in the MCU domain.
MCU timer 0 is used by R5 uboot as always on. So change properties
in u-boot specific files
Signed-off-by: Udit Kumar
---
.../k3-j7200-common-proc-board-u-boot.dtsi| 7 +
arch/arm/dts/k3-j7200-main.dtsi | 240 ++
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 130 ++
3 files changed, 377 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index f57c2306ba..789dc54617 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -30,7 +30,14 @@
bootph-pre-ram;
timer1: timer@4040 {
+ /delete-property/ clocks;
+ /delete-property/ clock-name;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ power-domains;
+ /delete-property/ ti,timer-pwm;
compatible = "ti,omap5430-timer";
+ status = "okay";
reg = <0x0 0x4040 0x0 0x80>;
ti,timer-alwon;
clock-frequency = <25000>;
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index 138381f43c..54795db9c3 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -795,6 +795,246 @@
assigned-clock-parents = <_clks 253 5>;
};
+ main_timer0: timer@240 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x240 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 49 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 49 1>;
+ assigned-clock-parents = <_clks 49 2>;
+ power-domains = <_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer1: timer@241 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x241 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 50 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 50 1>;
+ assigned-clock-parents = <_clks 50 2>;
+ power-domains = <_pds 50 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer2: timer@242 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x242 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 51 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 51 1>;
+ assigned-clock-parents = <_clks 51 2>;
+ power-domains = <_pds 49 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer3: timer@243 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x243 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 52 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 52 1>;
+ assigned-clock-parents = <_clks 52 2>;
+ power-domains = <_pds 52 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer4: timer@244 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x244 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 53 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 53 1>;
+ assigned-clock-parents = <_clks 53 2>;
+ power-domains = <_pds 53 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer5: timer@245 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x245 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 54 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 54 1>;
+ assigned-clock-parents = <_clks 54 2>;
+ power-domains = <_pds 54 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer6: timer@246 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x246 0x00 0x400>;
+ interrupts = ;
+ clocks = <_clks 55 1>;
+ clock-names = "fck";
+ assigned-clocks = <_clks 55 1>;
+ assigned-clock-parents = <_clks 55 2>;
+ power-domains = <_pds 55 TI_SCI_PD_EXCLUSIVE>;
+ ti,timer-pwm;
+ };
+
+ main_timer7: timer@247 {
+ compatible = "ti,am654-timer";
+ reg = <0x00 0x247 0x00 0x400>;
+ interrupts = ;
+
[PATCH 03/14] arch: arm: dts: k3-j7200-som: Enable I2C
Upstream linux patch posted at
https://lore.kernel.org/all/20230419040007.3022780-3-u-kum...@ti.com/
This patch enables wkup_i2c0 node in board dts file
along with pin mux and speed.
Also enables underneath eeprom CAV24C256WE.
J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
https://www.ti.com/lit/ds/symlink/dra821u.pdf
J7200 User Guide (Section 4.3, Table 4-2) :
https://www.ti.com/lit/ug/spruiw7a/spruiw7a.pdf
Signed-off-by: Udit Kumar
---
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 7 ---
arch/arm/dts/k3-j7200-som-p0.dtsi | 21 +++
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
index e62f9218e8..9d9ffcbb89 100644
--- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts
@@ -126,13 +126,6 @@
>;
};
- wkup_i2c0_pins_default: wkup-i2c0-pins-default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20)
WKUP_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21)
WKUP_I2C0_SDA */
- >;
- };
-
mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20)
MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi
b/arch/arm/dts/k3-j7200-som-p0.dtsi
index fa44ed4c17..2694241547 100644
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
@@ -118,6 +118,15 @@
};
};
+_pmx2 {
+ wkup_i2c0_pins_default: wkup-i2c0-pins-default {
+ pinctrl-single,pins = <
+ J721E_WKUP_IOPAD(0x98, PIN_INPUT_PULLUP, 0) /* (F20)
WKUP_I2C0_SCL */
+ J721E_WKUP_IOPAD(0x9c, PIN_INPUT_PULLUP, 0) /* (H21)
WKUP_I2C0_SDA */
+ >;
+ };
+};
+
_pmx0 {
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
@@ -214,6 +223,18 @@
};
};
+_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c0_pins_default>;
+ clock-frequency = <40>;
+
+ eeprom@50 {
+ compatible = "atmel,24c256";
+ reg = <0x50>;
+ };
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_fss0_ospi0_pins_default>;
--
2.34.1
[PATCH 02/14] arch: arm: dts: k3-j7200: Fix physical address of pin
From: Keerthy
wkup_pmx splits into multiple regions. Like
wkup_pmx0 -> 13 pins (WKUP_PADCONFIG 0 - 12)
wkup_pmx1 -> 2 pins (WKUP_PADCONFIG 14 - 15)
wkup_pmx2 -> 59 pins (WKUP_PADCONFIG 26 - 84)
wkup_pmx3 -> 8 pins (WKUP_PADCONFIG 93 - 100)
With this split, pin offset needs to be adjusted to
match with new pmx for all pins above wkup_pmx0.
Example a pin under wkup_pmx1 should start from 0 instead of
old offset(0x38 WKUP_PADCONFIG 14 offset)
J7200 Datasheet (Table 6-106, Section 6.4 Pin Multiplexing) :
https://www.ti.com/lit/ds/symlink/dra821u.pdf
Signed-off-by: Keerthy
Signed-off-by: Udit Kumar
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 28 ++---
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index 0d39d6b8cc..63633e4f6c 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -83,25 +83,25 @@
_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /*
MCU_RGMII1_TX_CTL */
- J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /*
MCU_RGMII1_RX_CTL */
- J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD3 */
- J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD2 */
- J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD1 */
- J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD0 */
- J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /*
MCU_RGMII1_RD3 */
- J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /*
MCU_RGMII1_RD2 */
- J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /*
MCU_RGMII1_RD1 */
- J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /*
MCU_RGMII1_RD0 */
- J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /*
MCU_RGMII1_TXC */
- J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /*
MCU_RGMII1_RXC */
+ J721E_WKUP_IOPAD(0x, PIN_OUTPUT, 0) /*
MCU_RGMII1_TX_CTL */
+ J721E_WKUP_IOPAD(0x0004, PIN_INPUT, 0) /*
MCU_RGMII1_RX_CTL */
+ J721E_WKUP_IOPAD(0x0008, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD3 */
+ J721E_WKUP_IOPAD(0x000c, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD2 */
+ J721E_WKUP_IOPAD(0x0010, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD1 */
+ J721E_WKUP_IOPAD(0x0014, PIN_OUTPUT, 0) /*
MCU_RGMII1_TD0 */
+ J721E_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /*
MCU_RGMII1_RD3 */
+ J721E_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /*
MCU_RGMII1_RD2 */
+ J721E_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /*
MCU_RGMII1_RD1 */
+ J721E_WKUP_IOPAD(0x002c, PIN_INPUT, 0) /*
MCU_RGMII1_RD0 */
+ J721E_WKUP_IOPAD(0x0018, PIN_OUTPUT, 0) /*
MCU_RGMII1_TXC */
+ J721E_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /*
MCU_RGMII1_RXC */
>;
};
mcu_mdio_pins_default: mcu-mdio1-pins-default {
pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1)
MCU_MDIO0_MDC */
- J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4)
MCU_MDIO0_MDIO */
+ J721E_WKUP_IOPAD(0x0034, PIN_OUTPUT, 0) /* (L1)
MCU_MDIO0_MDC */
+ J721E_WKUP_IOPAD(0x0030, PIN_INPUT, 0) /* (L4)
MCU_MDIO0_MDIO */
>;
};
};
--
2.34.1
[PATCH 01/14] arm: dts: k3-j7200: Update devicetree to sync with v6.3-rc6
From: Nishanth Menon
Sync with Kernel.org v6.3-rc6 tag.
Signed-off-by: Nishanth Menon
---
arch/arm/dts/k3-j7200-common-proc-board.dts | 63 +++---
arch/arm/dts/k3-j7200-main.dtsi | 72 +++--
arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 59 +++--
arch/arm/dts/k3-j7200-som-p0.dtsi | 46 +
arch/arm/dts/k3-j7200.dtsi | 10 ++-
5 files changed, 154 insertions(+), 96 deletions(-)
diff --git a/arch/arm/dts/k3-j7200-common-proc-board.dts
b/arch/arm/dts/k3-j7200-common-proc-board.dts
index d14f3c18b6..0d39d6b8cc 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board.dts
+++ b/arch/arm/dts/k3-j7200-common-proc-board.dts
@@ -12,6 +12,9 @@
#include
/ {
+ compatible = "ti,j7200-evm", "ti,j7200";
+ model = "Texas Instruments J7200 EVM";
+
chosen {
stdout-path = "serial2:115200n8";
bootargs = "console=ttyS2,115200n8
earlycon=ns16550a,mmio32,0x0280";
@@ -77,7 +80,7 @@
};
};
-_pmx0 {
+_pmx2 {
mcu_cpsw_pins_default: mcu-cpsw-pins-default {
pinctrl-single,pins = <
J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /*
MCU_RGMII1_TX_CTL */
@@ -131,15 +134,17 @@
>;
};
- main_usbss0_pins_default: main-usbss0-pins-default {
+ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
- J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS
*/
+ J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5)
SPI0_D1.GPIO0_55 */
>;
};
+};
- vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
+_pmx1 {
+ main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
- J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5)
SPI0_D1.GPIO0_55 */
+ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
};
@@ -149,51 +154,27 @@
status = "reserved";
};
+_uart0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
_uart0 {
+ status = "okay";
/* Shared with ATF on this platform */
power-domains = <_pds 146 TI_SCI_PD_SHARED>;
};
+_uart1 {
+ status = "okay";
+ /* Default pinmux */
+};
+
_uart2 {
/* MAIN UART 2 is used by R5F firmware */
status = "reserved";
};
-_uart3 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart4 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart5 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart6 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart7 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart8 {
- /* UART not brought out */
- status = "disabled";
-};
-
-_uart9 {
- /* UART not brought out */
- status = "disabled";
-};
-
_gpio2 {
status = "disabled";
};
@@ -229,6 +210,7 @@
};
_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_i2c0_pins_default>;
clock-frequency = <40>;
@@ -256,6 +238,7 @@
* The i2c1 of the CPB (as it is labeled) is not connected to j7200.
*/
_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <_i2c1_pins_default>;
clock-frequency = <40>;
diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi
index e8a41d09b4..138381f43c 100644
--- a/arch/arm/dts/k3-j7200-main.dtsi
+++ b/arch/arm/dts/k3-j7200-main.dtsi
@@ -32,7 +32,7 @@
#size-cells = <1>;
ranges = <0x00 0x00 0x0010 0x1c000>;
- serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0
lane0/1 select */
@@ -54,7 +54,10 @@
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x00 0x0180 0x00 0x1>, /* GICD */
- <0x00 0x0190 0x00 0x10>; /* GICR */
+ <0x00 0x0190 0x00 0x10>, /* GICR */
+ <0x00 0x6f00 0x00 0x2000>,/* GICC */
+ <0x00 0x6f01 0x00 0x1000>,/* GICH */
+ <0x00 0x6f02 0x00 0x2000>;/* GICV */
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = ;
@@ -139,6 +142,7 @@
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <_navss_intr>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@
[PATCH 00/14] arm: dts: k3-j7200: Sync with kernel.org
Nishanth Menon posted a series to sync between uboot and kernel dt for AM64 SOC. https://lore.kernel.org/u-boot/20230414075726.387461-1...@ti.com/ This patch series extend that work to J7200 SOC. Linux device tree changes for J7200 are posted to Linux list https://lore.kernel.org/all/20230426103219.1565266-1-u-kum...@ti.com/ Keerthy (1): arch: arm: dts: k3-j7200: Fix physical address of pin Nishanth Menon (1): arm: dts: k3-j7200: Update devicetree to sync with v6.3-rc6 Udit Kumar (11): arch: arm: dts: k3-j7200-som: Enable I2C arch: arm: dts: k3-j7200: Add general purpose timers arch: arm: dts: k3-j7200: Configure pinctrl for timer IO pad arch: arm: dts: k3-j7200 move main_pmx to common file arch: arm: dts: k3-j7200 move wkup_pmx to common file arch: arm: dts: k3-j7200 cleanup r5 and uboot dts arch: arm: dts: k3-j7200: remove duplicate usb nodes arch: arm: dts: k3-7200: cleanup r5 i2c node arch: arm: dts: k3-j7200: removed unused clock node arch: arm: dts: k3-j7200: cleanup hmbc node arch: arm: dts: k3-j7200 rearrange bootph property in various node Vaishnav Achath (1): arch: arm: dts: k3-j7200: Add MCSPI nodes .../k3-j7200-common-proc-board-u-boot.dtsi| 98 +--- arch/arm/dts/k3-j7200-common-proc-board.dts | 133 +++--- arch/arm/dts/k3-j7200-main.dtsi | 421 +- arch/arm/dts/k3-j7200-mcu-wakeup.dtsi | 242 +- .../arm/dts/k3-j7200-r5-common-proc-board.dts | 165 +-- arch/arm/dts/k3-j7200-som-p0.dtsi | 74 ++- arch/arm/dts/k3-j7200.dtsi| 10 +- 7 files changed, 778 insertions(+), 365 deletions(-) -- 2.34.1
Re: [PATCH 1/4] doc: signature: update algorithms support description
Hi Simon,
On Tue, May 02 2023, Simon Glass wrote:
> On Mon, 1 May 2023 at 22:47, Baruch Siach wrote:
>>
>> U-Boot supports more hash and verification algorithms these days.
>>
>> Signed-off-by: Baruch Siach
>> ---
>> doc/uImage.FIT/signature.txt | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> Reviewed-by: Simon Glass
Thanks.
> Would you be interested in moving this documentation to doc/develop in
> the rST format?
I hope to find some time to help with that.
baruch
--
~. .~ Tk Open Systems
=}ooO--U--Ooo{=
- bar...@tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
Re: [PATCH v2 22/30] Makefile: Correct the ans1_compiler rule for MSYS2
Hi Simon, On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote: > > Add the required extension to the Makefile rule. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Use EXEEXT instead of ELFEXT > > Makefile | 1 + > scripts/Makefile.build | 2 +- > 2 files changed, 2 insertions(+), 1 deletion(-) > > diff --git a/Makefile b/Makefile > index 240562dff00b..a328652f0f23 100644 > --- a/Makefile > +++ b/Makefile > @@ -48,6 +48,7 @@ ifeq ($(MSYS_VERSION),0) > export LIBEXT := so > else > export LIBEXT := dll To make such handling consistent, please make LIBEXT be .so and .dll (including the dot like exe) > +export EXEEXT := .exe > endif > > # Avoid funny character set dependencies > diff --git a/scripts/Makefile.build b/scripts/Makefile.build > index 97dd4a64f6ef..a494e2f105b8 100644 > --- a/scripts/Makefile.build > +++ b/scripts/Makefile.build > @@ -309,7 +309,7 @@ quiet_cmd_asn1_compiler = ASN.1 $@ >cmd_asn1_compiler = $(objtree)/tools/asn1_compiler $< \ > $(subst .h,.c,$@) $(subst .c,.h,$@) > > -$(obj)/%.asn1.c $(obj)/%.asn1.h: $(src)/%.asn1 $(objtree)/tools/asn1_compiler > +$(obj)/%.asn1.c $(obj)/%.asn1.h: $(src)/%.asn1 > $(objtree)/tools/asn1_compiler$(EXEEXT) > $(call cmd,asn1_compiler) > > # Build the compiled-in targets > -- Otherwise, Reviewed-by: Bin Meng
Re: [PATCH v2 21/30] Makefile: Disable unsupported compiler options with PE
Hi Simon, On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote: > > The MSYS2 compiler does not support some of these options. Drop them to > avoid build errors. I think the commit message is better reworded to something like: Test some linker options as some toolchains like MSYS2 do not support them. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Use cc-option and ld-option instead > > Makefile | 2 +- > scripts/Makefile.lib | 5 - > 2 files changed, 5 insertions(+), 2 deletions(-) > > diff --git a/Makefile b/Makefile > index 2453a80eca62..240562dff00b 100644 > --- a/Makefile > +++ b/Makefile > @@ -819,7 +819,7 @@ KBUILD_CPPFLAGS += $(KCPPFLAGS) > KBUILD_AFLAGS += $(KAFLAGS) > KBUILD_CFLAGS += $(KCFLAGS) > > -KBUILD_LDFLAGS += -z noexecstack > +KBUILD_LDFLAGS += $(call ld-option,-znoexecstack) > KBUILD_LDFLAGS += $(call ld-option,--no-warn-rwx-segments) > > KBUILD_HOSTCFLAGS += $(if $(CONFIG_TOOLS_DEBUG),-g) > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib > index 7b27224b5d44..aaae37d50a43 100644 > --- a/scripts/Makefile.lib > +++ b/scripts/Makefile.lib > @@ -425,7 +425,10 @@ cmd_efi_objcopy = $(OBJCOPY) -j .header -j .text -j > .sdata -j .data -j \ > $(obj)/%.efi: $(obj)/%_efi.so > $(call cmd,efi_objcopy) > > -KBUILD_EFILDFLAGS = -nostdlib -zexecstack -znocombreloc -znorelro > +KBUILD_EFILDFLAGS := -nostdlib > +KBUILD_EFILDFLAGS += $(call ld-option,-zexecstack) > +KBUILD_EFILDFLAGS += $(call ld-option,-znocombreloc) > +KBUILD_EFILDFLAGS += $(call ld-option,-znorelro) > KBUILD_EFILDFLAGS += $(call ld-option,--no-warn-rwx-segments) > quiet_cmd_efi_ld = LD $@ > cmd_efi_ld = $(LD) $(KBUILD_EFILDFLAGS) -T $(EFI_LDS_PATH) \ > -- Otherwise, Reviewed-by: Bin Meng
Re: [PATCH v2 20/30] sandbox: Fix up setting of monitor_len on MSYS2
Hi Simon, On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote: > > The required linker symbols are not present. For now just return 0 in > this case. Is it possible to add _end in the Sandbox linker script? > > Signed-off-by: Simon Glass > --- > > (no changes since v1) > > common/board_f.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Regards, Bin
Re: [PATCH v2 19/30] sandbox: Drop signal handling for MSYS2
Hi Simon, On Sun, Apr 30, 2023 at 9:30 AM Simon Glass wrote: > > The Linux register format used on Linux (and perhaps other OSes) is not > used on Windows, so disable this feature. > > Signed-off-by: Simon Glass > --- > > Changes in v2: > - Update commit message to mention other OSes > - Check for __MSYS__ instead of __linux > > arch/sandbox/cpu/os.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c > index e76568ebdd32..522fe8a6f2b1 100644 > --- a/arch/sandbox/cpu/os.c > +++ b/arch/sandbox/cpu/os.c > @@ -288,7 +288,7 @@ static void os_signal_handler(int sig, siginfo_t *info, > void *con) > ucontext_t __maybe_unused *context = con; > unsigned long pc; > > -#if defined(__x86_64__) > +#if defined(__x86_64__) && !defined(__MSYS__) I think we need to comment out all places in os.c that use signal handlers, e.g.: sigatcion() does not exist on Windows. Or we consider rewriting signal related codes in a portable way, e.g.: Windows only has signal() API. > pc = context->uc_mcontext.gregs[REG_RIP]; > #elif defined(__aarch64__) > pc = context->uc_mcontext.pc; > -- Regards, Bin
Re: [PATCH v3] console: usb: kbd: Limit poll frequency to improve performance
Hi Filip,
On Tue, 2 May 2023 at 12:43, Filip Žaludek wrote:
>
>
>
> Hi Simon, Michal, Marek,
>
>
>
> On 4/26/23 03:04, Simon Glass wrote:
> > Hi Filip,
> >
> > On Tue, 25 Apr 2023 at 06:36, Filip Žaludek
> > wrote:
> >>
> >>
> >>
> >> Hi Simon,
> >>
> >>
> >> On 4/19/23 03:49, Simon Glass wrote:
> >>> Hi Filip,
> >>>
> >>> On Tue, 11 Apr 2023 at 14:24, Filip Žaludek
> >>> wrote:
>
>
>
> On 2/8/23 20:01, Mark Kettenis wrote:
> >> Date: Wed, 8 Feb 2023 19:45:36 +0100
> >> From: Michal Suchánek
> >>
> >> Hello,
> >>
> >> On Wed, Jan 18, 2023 at 05:01:12PM +0100, Filip Žaludek wrote:
> >>>
> >>>
> >>> Hi Michal,
> >>>
> >>> thanks for testing! Do you consider keyboard as working once it
> >>> is detected without
> >>> 'usb_kbd usb_kbd: Timeout poll on interrupt endpoint', or judging
> >>> from subsequent
> >>> typing? Note that issue is reproducible only in about 20% of reboots.
> >>
> >> I rely on keyboard input to boot so if it was 20% broken I would
> >> notice.
> >> I don't use the rPi all that much so if it was broken only a few
> >> % of the time there is a chance I would miss it.
> >>
> >> However, for me not typing on the keyboard during usb detection it is
> >> 100% not detected, typing on it during usb detection it is 100%
> >> detected.
> >>
> >> The timeout is limitation of the dwc2 controller handling of usb hubs.
> >>
> >> There might be a possibility to improve the driver so that it handles
> >> the condition but it might be that the Linux driver relies on a
> >> separate
> >> thread handling the controller which is not acceptable for u-boot.
> >>
> >> I am not usb expert and definitely not dwc2 expert so I cannot do more
> >> than workaround the current driver limitation.
> >>
> >>> For me I can always enter 'U-Boot>' shell, but then keyboard usually
> >>> does not work.
> >>> And yes, resetting the usb controller with pressing a key afterwards
> >>> will
> >>> finally break the keyboard. ('usb reset' typed from keyboard)
> >>> If you are Prague located I am ready to demonstrate what I am talking
> >>> about.
> >>>
> >>> Simon's keyboard detection is somewhat interfered by 'SanDisk USB
> >>> Extreme Pro' detection,
> >>> printed complaints but keyboard still works..
> >>> 'usb_kbd usb_kbd: Timeout poll on interrupt endpoint' and 'Failed to
> >>> get keyboard state from device 0c40:8000'
> >>> Btw. why from 0c40:8000 (ELMCU 2.4GHz receiver) when wired keyboard
> >>> is 046d:c31c (Logitech Keyboard K120)?
> >>>
> >>> What is supposed scenario for RPi3/u-boot/grub usb keyboard
> >>> equipped users wanting to boot non-default?
> >>> Enter 'U-Boot>' shell to detect keyboard; type boot; select desired
> >>> grub entry..?
> >>>
> >>> Reverting either from the two makes it non issue for me:
> >>> 'dwc2: use the nonblock argument in submit_int_msg'
> >>> commit 9dcab2c4d2cb50ab1864c818b82a72393c160236
> >>
> >> Without this booting from USB is not feasible because reading every
> >> block from the USB drive waits for the keyboard to time out.
> >>
> >>> 'console: usb: kbd: Limit poll frequency to improve performance'
> >>> commit 96991e652f541323a03c5b7e075d54a117091618
> >>
> >> No idea about this one, for me it doea not give any substantial
> >> difference in behavior.
> >
> > Reverting that commit leads to a significant slowdown loading a kernel
> > from disk with a usb keyboard connected. The slowdown is somewhat
> > hardware dependent but on some systems loading the OpenBSD/arm64
> > kernel would take minutes instead of seconds.
>
>
>
> More updates to usb keyboard/RPi3/dwc2 controller issue:
>
>I was following my former observation about printing characters from semi
> random places [usb.c, usb_hub.c, device.c, usb-uclass.c, dwc2.c] what
> works as workaround. I realized this is only when printing to vidconsole,
> not to serial. After disabling video_sync() and/or flush_dcache_range()
> from corresponding vidconsole print functions, printing is no longer
> workaround. This behavior seem to be due to cache coherency.
>
>
>
> Do you have any objections against elephant in porcelain proposal?
> Not able to narrow it down more to single source code line.
> With this keyboard works for me even when touching it only during 15s grub
> timeout.
> It is not for sure that cache coherency problem is from dwc2, but afaik there
> are no other complaints to usb keyboard.
> Performance degradation not observed..
>
>
> %< -
> diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
> index 23060fc369..f95314ff1b 100644
> --- a/drivers/usb/host/dwc2.c
> +++ b/drivers/usb/host/dwc2.c
> @@ -814,6 +814,7 @@
Re: [PATCH v2 4/4] common: spl: Add spl NVMe boot support
Hi Mayuresh,
On Tue, 2 May 2023 at 10:19, Mayuresh Chitale wrote:
>
> Add support to load the next stage image from an NVMe disk which may
> be formatted as an EXT or FAT filesystem.
>
> Signed-off-by: Mayuresh Chitale
> ---
> arch/riscv/include/asm/spl.h | 1 +
> common/spl/Kconfig | 10 +++
> common/spl/Makefile | 1 +
> common/spl/spl_nvme.c| 52
> 4 files changed, 64 insertions(+)
> create mode 100644 common/spl/spl_nvme.c
>
> diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
> index 2898a770ee..9c0bf9755c 100644
> --- a/arch/riscv/include/asm/spl.h
> +++ b/arch/riscv/include/asm/spl.h
> @@ -20,6 +20,7 @@ enum {
> BOOT_DEVICE_SPI,
> BOOT_DEVICE_USB,
> BOOT_DEVICE_SATA,
> + BOOT_DEVICE_NVME,
> BOOT_DEVICE_I2C,
> BOOT_DEVICE_BOARD,
> BOOT_DEVICE_DFU,
> diff --git a/common/spl/Kconfig b/common/spl/Kconfig
> index a42774c76d..021c4997a7 100644
> --- a/common/spl/Kconfig
> +++ b/common/spl/Kconfig
> @@ -1283,6 +1283,16 @@ config SPL_NVME_BOOT_DEVICE
> depends on SPL_NVME
> default 0x0
>
> +config SYS_NVME_EXT_BOOT_PARTITION
> + hex "NVMe ext boot partition number"
> + depends on SPL_NVME
> + default 0x2
> +
> +config SYS_NVME_FAT_BOOT_PARTITION
> + hex "NVMe boot partition number"
> + depends on SPL_NVME
> + default 0x1
> +
> config SPL_SERIAL
> bool "Support serial"
> select SPL_PRINTF
> diff --git a/common/spl/Makefile b/common/spl/Makefile
> index 13db3df993..4bcc3d7e68 100644
> --- a/common/spl/Makefile
> +++ b/common/spl/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
> obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
> obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
> obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o
> +obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o
> obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o
> obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
> obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
> diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c
> new file mode 100644
> index 00..c99e0aefc7
> --- /dev/null
> +++ b/common/spl/spl_nvme.c
> @@ -0,0 +1,52 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2023
> + * Ventana Micro Systems Inc.
> + *
> + * Derived work from spl_sata.c
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +static int spl_nvme_load_image(struct spl_image_info *spl_image,
> + struct spl_boot_device *bootdev)
> +{
> + int ret;
> + struct blk_desc *blk_desc;
> +
> + ret = pci_init();
> + if (ret < 0)
> + goto out;
> +
> + ret = nvme_scan_namespace();
> + if (ret < 0)
> + goto out;
> +
> + blk_show_device(UCLASS_NVME, CONFIG_SPL_NVME_BOOT_DEVICE);
> + blk_desc = blk_get_devnum_by_uclass_id(UCLASS_NVME,
> + CONFIG_SPL_NVME_BOOT_DEVICE);
> + if (IS_ENABLED(CONFIG_SPL_FS_EXT4)) {
> + ret = spl_load_image_ext(spl_image, bootdev, blk_desc,
> +CONFIG_SYS_NVME_EXT_BOOT_PARTITION,
> +CONFIG_SPL_PAYLOAD);
> + if (!ret)
> + return ret;
> + }
> +
> + if (IS_ENABLED(CONFIG_SPL_FS_FAT))
> + ret = spl_load_image_fat(spl_image, bootdev, blk_desc,
> +CONFIG_SYS_NVME_FAT_BOOT_PARTITION,
> +CONFIG_SPL_PAYLOAD);
> + else
> + ret = -ENOSYS;
> +
> +out:
> + return ret;
> +}
> +
> +SPL_LOAD_IMAGE_METHOD("NVME", 0, BOOT_DEVICE_NVME, spl_nvme_load_image);
> --
> 2.34.1
>
All of this code looks generic except:
UCLASS_NVME
CONFIG_SPL_NVME_BOOT_DEVICE
CONFIG_SYS_NVME_EXT_BOOT_PARTITION
so please move the code inside your new function into a generic file
like spl_blk_fs.c or similar and pass these parameters to it. Then we
can use the same function for other device types.
Regards,
SImon
Re: [PATCH v2 2/4] nvme: pci: Enable for SPL
Hi Mayuresh,
On Tue, 2 May 2023 at 10:19, Mayuresh Chitale wrote:
>
> Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP
> for SPL which is required to auto configure the PCIe devices.
>
> Signed-off-by: Mayuresh Chitale
> ---
> drivers/Makefile | 1 +
> drivers/nvme/Makefile| 2 +-
> drivers/pci/Kconfig | 7 +++
> drivers/pci/pci-uclass.c | 3 ++-
> 4 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 58be410135..dc559ea7f7 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
> obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
> obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
> obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
> +obj-$(CONFIG_$(SPL_)NVME) += nvme/
> obj-$(CONFIG_XEN) += xen/
> obj-$(CONFIG_$(SPL_)FPGA) += fpga/
> obj-y += bus/
> diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile
> index fa7b619446..fd3e68a91d 100644
> --- a/drivers/nvme/Makefile
> +++ b/drivers/nvme/Makefile
> @@ -4,4 +4,4 @@
>
> obj-y += nvme-uclass.o nvme.o nvme_show.o
> obj-$(CONFIG_NVME_APPLE) += nvme_apple.o
> -obj-$(CONFIG_NVME_PCI) += nvme_pci.o
> +obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..ecab6ddc7e 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -40,6 +40,13 @@ config PCI_PNP
> help
> Enable PCI memory and I/O space resource allocation and assignment.
>
> +config SPL_PCI_PNP
> + bool "Enable Plug & Play support for PCI"
> + default n
> + help
> + Enable PCI memory and I/O space resource allocation and assignment.
> + This is required to auto configure the enumerated devices.
> +
> config PCI_REGION_MULTI_ENTRY
> bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
> help
> diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
> index 9343cfc62a..dff63a68ce 100644
> --- a/drivers/pci/pci-uclass.c
> +++ b/drivers/pci/pci-uclass.c
> @@ -1140,7 +1140,8 @@ static int pci_uclass_post_probe(struct udevice *bus)
> if (ret)
> return log_msg_ret("bind", ret);
>
> - if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
> + if ((CONFIG_IS_ENABLED(PCI_PNP) || CONFIG_IS_ENABLED(SPL_PCI_PNP)) &&
The CONFIG_IS_ENABLED() macro checks SPL_PCI_PNP when used in an SPL
build, so you should not need this change.
> + ll_boot_init() &&
> (!hose->skip_auto_config_until_reloc ||
> (gd->flags & GD_FLG_RELOC))) {
> ret = pci_auto_config_devices(bus);
> --
> 2.34.1
>
Regards,
Simon
Re: [PATCH 4/4] doc: signature: trim the future work list
On Mon, 1 May 2023 at 22:47, Baruch Siach wrote: > > Since U-Boot supports more RSA/SHA variants, as well as ECDSA, remove > these items from the TODO list. > > Signed-off-by: Baruch Siach > --- > doc/uImage.FIT/signature.txt | 2 -- > 1 file changed, 2 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 3/4] doc: signature: describe how to enable ECDSA
On Mon, 1 May 2023 at 22:47, Baruch Siach wrote: > Missing commit message > Signed-off-by: Baruch Siach > --- > doc/uImage.FIT/signature.txt | 1 + > 1 file changed, 1 insertion(+) > Reviewed-by: Simon Glass
Re: [PATCH 2/4] doc: signature: update algorithm addition description
On Mon, 1 May 2023 at 22:47, Baruch Siach wrote: > > U-Boot now uses the U_BOOT_CRYPTO_ALGO() macro. > > Signed-off-by: Baruch Siach > --- > doc/uImage.FIT/signature.txt | 8 > 1 file changed, 4 insertions(+), 4 deletions(-) > Reviewed-by: Simon Glass
Re: [PATCH 1/4] doc: signature: update algorithms support description
On Mon, 1 May 2023 at 22:47, Baruch Siach wrote: > > U-Boot supports more hash and verification algorithms these days. > > Signed-off-by: Baruch Siach > --- > doc/uImage.FIT/signature.txt | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass Would you be interested in moving this documentation to doc/develop in the rST format? Regards, Simon
Re: SHA verification fails on signed images
Hi Andy, On Tue, 2 May 2023 at 11:13, Andy Pandy wrote: > > Hi there, > > I have a FIT image that boots fine, but when I sign it, with the following > command, it fails to boot: > > mkimage -k keys -r -o sha256,rsa2048 -F image.fit > > It fails while checking sha256, Bad hash value for 'hash' hash node in ... > > I get similar error when I test it on my host: > > tools/fit_check_sign -f image.fit -k u-boot-spl.dtb > > After debugging, I found that after signing the image, data gets imbedded > into images structure with data = <...> field, but data-offset, data-size > fields (used for external reference) are not removed, and that's why when > verifying the signatures fit_image_get_data_and_size() function gets > confused when finds data-offset settings and calculates sha256 on the wrong > data. > > I checked my other projects, with older version of uboot, and I can confirm > that there after signing a FIT image data-offset, data-size fields got > removed and data field appeared with data. > > I am experiencing the issue with the recent head of the mater branch of > u-boot. > > Did I miss something or is it a bug? It is sort-of a bug, or at least a missing feature. It is not possible to update an external FIT back to an 'internal' one. You could try using the -E flag. If that works, then we should update the docs (please send patch). If not perhaps the best fix for now is to generate an error. The problem is that updating the metadata for an image that has already been signed is difficult, since you need to keep the original property ordering, etc. Typical usage is to only specify -E once all the signing is done. Regards, Simon
[PATCH 5/5] board: gateworks: venice: update board doc to show other emmc parts
Update the venice board documentation to show how to install to the various eMMC hardware partitions available as the same binary firmware can be placed in either user/boot0/boot1 without build-time config changes. Note that the boot offsets differ depending on the SoC and the eMMC hardware partition. Signed-off-by: Tim Harvey --- doc/board/gateworks/imx8mm_venice.rst | 4 +++- doc/board/gateworks/imx8mn_venice.rst | 4 +++- doc/board/gateworks/imx8mp_venice.rst | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/doc/board/gateworks/imx8mm_venice.rst b/doc/board/gateworks/imx8mm_venice.rst index f1e7e4994458..ea78dfd7ae6b 100644 --- a/doc/board/gateworks/imx8mm_venice.rst +++ b/doc/board/gateworks/imx8mm_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x42 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x42 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0x42 $blkcnt # or emmc boot1 hw part diff --git a/doc/board/gateworks/imx8mn_venice.rst b/doc/board/gateworks/imx8mn_venice.rst index 7ba953a4a85c..7015f4ef31c7 100644 --- a/doc/board/gateworks/imx8mn_venice.rst +++ b/doc/board/gateworks/imx8mn_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part diff --git a/doc/board/gateworks/imx8mp_venice.rst b/doc/board/gateworks/imx8mp_venice.rst index 632cd742d1f8..a219caadff26 100644 --- a/doc/board/gateworks/imx8mp_venice.rst +++ b/doc/board/gateworks/imx8mp_venice.rst @@ -47,4 +47,6 @@ Update eMMC => tftpboot $loadaddr flash.bin => setexpr blkcnt $filesize + 0x1ff && setexpr blkcnt $blkcnt / 0x200 - => mmc dev 2 && mmc write $loadaddr 0x40 $blkcnt + => mmc dev 2 0 && mmc write $loadaddr 0x40 $blkcnt # emmc user hw part + => mmc dev 2 1 && mmc write $loadaddr 0 $blkcnt # or emmc boot0 hw part + => mmc dev 2 2 && mmc write $loadaddr 0 $blkcnt # or emmc boot1 hw part -- 2.25.1
[PATCH 4/5] board: gateworks: venice: move env location
To allow U-Boot to fit within emmc boot partitions move the env from just under 16MiB to just under 4MiB as some emmc devices used on venice boards have 4MiB boot partitions. This still leaves plenty of room for U-Boot. Signed-off-by: Tim Harvey --- configs/imx8mm_venice_defconfig | 4 ++-- configs/imx8mn_venice_defconfig | 4 ++-- configs/imx8mp_venice_defconfig | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index ad5b7616f30a..427d0572c5fe 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff +CONFIG_ENV_OFFSET=0x3f CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mm-venice" CONFIG_SPL_TEXT_BASE=0x7E1000 @@ -17,7 +17,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x92 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SYS_LOAD_ADDR=0x4820 CONFIG_SYS_MEMTEST_START=0x4000 CONFIG_SYS_MEMTEST_END=0x8000 diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 0742fa759b08..26c264512a13 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff +CONFIG_ENV_OFFSET=0x3f CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mn-venice" CONFIG_SPL_TEXT_BASE=0x912000 @@ -17,7 +17,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x98 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 CONFIG_SYS_LOAD_ADDR=0x4820 CONFIG_SYS_MEMTEST_START=0x4000 diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index ae0c0120d107..8b5a8c86e6f7 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x8000 -CONFIG_ENV_OFFSET=0xff +CONFIG_ENV_OFFSET=0x3f CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx8mp-venice" CONFIG_SPL_TEXT_BASE=0x92 @@ -17,7 +17,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL_STACK=0x96 CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0xff8000 +CONFIG_ENV_OFFSET_REDUND=0x3f8000 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800 CONFIG_SYS_LOAD_ADDR=0x4048 CONFIG_SYS_MEMTEST_START=0x4000 -- 2.25.1
[PATCH 1/5] board: gateworks: venice: dynamically determine U-Boot raw sector
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to adjust for
IMX8MN and IMX8MP when booting from an eMMC boot partition due
to IMX BOOTROM v2 using an SPL offset of 0 for boot partitions
and 32K for the user partition.
In order to allow the same firmware to run on both user and boot
hardware partitions adjust raw_sect dynamically at runtime.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/spl.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/gateworks/venice/spl.c b/board/gateworks/venice/spl.c
index 4eb7bdfcee67..50056da3ee0f 100644
--- a/board/gateworks/venice/spl.c
+++ b/board/gateworks/venice/spl.c
@@ -327,6 +327,21 @@ int spl_board_boot_device(enum boot_device boot_dev_spl)
}
}
+unsigned long spl_mmc_get_uboot_raw_sector(struct mmc *mmc, unsigned long
raw_sect)
+{
+ if (!IS_SD(mmc)) {
+ switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+ case 1:
+ case 2:
+ if (IS_ENABLED(CONFIG_IMX8MN) ||
IS_ENABLED(CONFIG_IMX8MP))
+ raw_sect -= 32 * 2;
+ break;
+ }
+ }
+
+ return raw_sect;
+}
+
const char *spl_board_loader_name(u32 boot_device)
{
switch (boot_device) {
--
2.25.1
[PATCH 2/5] board: gateworks: venice: dynamically determine U-Boot env partition
Determine the U-Boot env hardware partition depending on the boot
device.
This allows the same boot firmware image to be placed on user, boot0,
or boot1 without changing CONFIG_SYS_MMC_ENV_PART.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/venice.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index ca62f0be6d25..7aca75503846 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -7,6 +7,7 @@
#include
#include
#include
+#include
#include
#include
@@ -139,6 +140,20 @@ int board_mmc_get_env_dev(int devno)
return devno;
}
+uint mmc_get_env_part(struct mmc *mmc)
+{
+ if (!IS_SD(mmc)) {
+ switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+ case 1:
+ return 1;
+ case 2:
+ return 2;
+ }
+ }
+
+ return 0;
+}
+
int ft_board_setup(void *fdt, struct bd_info *bd)
{
const char *base_model = eeprom_get_baseboard_model();
--
2.25.1
[PATCH 3/5] board: gateworks: venice: dynamically update the update_firmware script
The update_firmware script is intended to update the boot firmware but
the details including the offset and hardware partition are dependent
on the boot device.
Specifically:
- IMX8MM/IMX8MP (BOOTROM v2) the offset is 32KiB for SD and eMMC user
hardware partition and 0KiB for eMMC boot partitions.
- IMX8MM the offset is 33KiB for SD and eMMC regardless of hardware
partition.
Dynamically set soc, dev, bootpart, and bootblk env vars at runtime
and use these in the update_firmware script. Remove the splblk env var
from config files as its no longer needed.
Signed-off-by: Tim Harvey
---
board/gateworks/venice/venice.c | 71 +++
board/gateworks/venice/venice.env | 6 +--
include/configs/imx8mm_venice.h | 1 -
include/configs/imx8mn_venice.h | 1 -
include/configs/imx8mp_venice.h | 1 -
5 files changed, 74 insertions(+), 6 deletions(-)
diff --git a/board/gateworks/venice/venice.c b/board/gateworks/venice/venice.c
index 7aca75503846..803582c55b99 100644
--- a/board/gateworks/venice/venice.c
+++ b/board/gateworks/venice/venice.c
@@ -6,10 +6,12 @@
#include
#include
#include
+#include
#include
#include
#include
#include
+#include
#include "eeprom.h"
@@ -94,10 +96,12 @@ int board_init(void)
int board_late_init(void)
{
const char *str;
+ struct mmc *mmc = NULL;
char env[32];
int ret, i;
u8 enetaddr[6];
char fdt[64];
+ int bootdev;
/* Set board serial/model */
if (!env_get("serial#"))
@@ -132,6 +136,73 @@ int board_late_init(void)
i++;
} while (!ret);
+ /*
+* set bootdev/bootblk/bootpart (used in firmware_update script)
+* dynamically depending on boot device and SoC
+*/
+ bootdev = -1;
+ switch (get_boot_device()) {
+ case SD1_BOOT:
+ case MMC1_BOOT: /* SDHC1 */
+ bootdev = 0;
+ break;
+ case SD2_BOOT:
+ case MMC2_BOOT: /* SDHC2 */
+ bootdev = 1;
+ break;
+ case SD3_BOOT:
+ case MMC3_BOOT: /* SDHC3 */
+ bootdev = 2;
+ break;
+ default:
+ break;
+ }
+ if (bootdev != -1)
+ mmc = find_mmc_device(bootdev);
+ if (mmc) {
+ int bootblk;
+
+ if (IS_ENABLED(CONFIG_IMX8MN) || IS_ENABLED(CONFIG_IMX8MP))
+ bootblk = 32 * SZ_1K / 512;
+ else
+ bootblk = 33 * SZ_1K / 512;
+ mmc_init(mmc);
+ if (!IS_SD(mmc)) {
+ int bootpart;
+
+ switch (EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config)) {
+ case 1: /* boot0 */
+ bootpart = 1;
+ break;
+ case 2: /* boot1 */
+ bootpart = 2;
+ break;
+ case 7: /* user */
+ default:
+ bootpart = 0;
+ break;
+ }
+ /* IMX8MP/IMX8MN BOOTROM v2 uses offset=0 for boot
parts */
+ if ((IS_ENABLED(CONFIG_IMX8MN) ||
IS_ENABLED(CONFIG_IMX8MP)) &&
+ (bootpart == 1 || bootpart == 2))
+ bootblk = 0;
+ env_set_hex("bootpart", bootpart);
+ env_set_hex("bootblk", bootblk);
+ } else { /* SD */
+ env_set("bootpart", "");
+ env_set_hex("bootblk", bootblk);
+ }
+ env_set_hex("dev", bootdev);
+ }
+
+ /* override soc=imx8m to provide a more specific soc name */
+ if (IS_ENABLED(CONFIG_IMX8MN))
+ env_set("soc", "imx8mn");
+ else if (IS_ENABLED(CONFIG_IMX8MP))
+ env_set("soc", "imx8mp");
+ else if (IS_ENABLED(CONFIG_IMX8MM))
+ env_set("soc", "imx8mm");
+
return 0;
}
diff --git a/board/gateworks/venice/venice.env
b/board/gateworks/venice/venice.env
index 2054c029a3e9..a0d6c43325cf 100644
--- a/board/gateworks/venice/venice.env
+++ b/board/gateworks/venice/venice.env
@@ -8,11 +8,11 @@ bootm_size=0x1000
dev=2
preboot=gsc wd-disable
console=ttymxc1,115200
-update_firmware=tftpboot $loadaddr $image &&
+update_firmware=tftpboot $loadaddr $dir/venice-$soc-flash.bin &&
setexpr blkcnt $filesize + 0x1ff &&
setexpr blkcnt $blkcnt / 0x200 &&
- mmc dev $dev &&
- mmc write $loadaddr $splblk $blkcnt
+ mmc dev $dev $bootpart &&
+ mmc write $loadaddr $bootblk $blkcnt
loadfdt=if $fsload $fdt_addr_r $dir/$fdt_file1;
then echo loaded $fdt_file1;
elif $fsload $fdt_addr_r $dir/$fdt_file2;
diff --git a/include/configs/imx8mm_venice.h
[PATCH 0/5] allow boot firmware to go in user/boot0/boot1
The Gateworks Venice board family uses a combination of imx8mm, imx8mn, and imx8mp SoC's. Because boot firmware for these are not binary compatible and have different flash offsets it is highly desirable to place boot firmware in an emmc boot partition instead of the current user hardware partition to minimize unintended corruption of boot firmware by flashing the wrong image or to the wrong location. This series of patches allows the same boot firmware to be placed in either boot0, boot1, or user hardware partition by detecting the boot device and adjusting env device as well as u-boot sector. Additionally the firmware script is updated to automate device, offset, and soc. Tim Harvey (5): board: gateworks: venice: dynamically determine U-Boot raw sector board: gateworks: venice: dynamically determine U-Boot env partition board: gateworks: venice: dynamically update the update_firmware script board: gateworks: venice: move env location board: gateworks: venice: update board doc to show other emmc parts board/gateworks/venice/spl.c | 15 + board/gateworks/venice/venice.c | 86 +++ board/gateworks/venice/venice.env | 6 +- configs/imx8mm_venice_defconfig | 4 +- configs/imx8mn_venice_defconfig | 4 +- configs/imx8mp_venice_defconfig | 4 +- doc/board/gateworks/imx8mm_venice.rst | 4 +- doc/board/gateworks/imx8mn_venice.rst | 4 +- doc/board/gateworks/imx8mp_venice.rst | 4 +- include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_venice.h | 1 - 12 files changed, 119 insertions(+), 15 deletions(-) -- 2.25.1
Re: [PATCH v2] arch: arm: mach-k3: Delete tifs node in DT fixup
On 12:57-20230502, Kumar, Udit wrote: > > On 5/1/2023 8:16 PM, Andrew Davis wrote: > > On 4/26/23 9:13 AM, Kumar, Udit wrote: > > > Hi Neha, > > > > > > On 4/26/2023 5:31 PM, Neha Malcom Francis wrote: > > > > Hi Udit > > > > > > > > On 26/04/23 16:09, Kumar, Udit wrote: > > > > > Hi Neha, > > > > > > > > > > > Hi Udit, > > > > > > > > > > [..] > > > > > > > > > > > > > > > > > > > > > I do have a general doubt; why do we have only atf-sram > > > > > > > > sub-node in > > > > > > > > msmc_sram in all other devices (j721e, j7200 and > > > > > > > > am65) except j721s2? > > > > > > > > > > > > > > let me know, which source code you are referring to > > > > > > > > > > > > > > > > > > > In U-Boot, for j721e, j7200 and am65; they *only* contain atf-sram? > > > > > > > > > > For u-boot please see > > > > > > > > > > https://elixir.bootlin.com/u-boot/latest/source/arch/arm/dts/k3-j721s2-main.dtsi#L16 > > > > > > > > > > > > > > > > > I could see for j721s2 as well, in uboot[0] and Linux[1] > > > > > [..] > > > > > > > > > > > > > What I mean to ask is, why aren't there tifs or l3cache subnodes > > > > in j721e, j7200 and am65? > > > > > > > I think, above platform is doing in right way, > > > > > > AFAIK, if we have to provide then we can provide size of this. > > > > > > l3-cache can not be addressable. > > > > > > > > > So the history here is we used to have the SRAM node in DT sized > > to the actual size in hardware. L3 cache size can be set at boot > > time (in SYSFW board-config file), and that uses up some of the > > SRAM, so the end address moves in. We could represent this as > > a reserved node inside the full SRAM node, or by shrinking the > > SRAM node and hiding this. Same story for TIFS and ATF, they > > use some variable amount of the end of SRAM. > > > Ah, I have other view. > > We shrunk SRAM size already, having reserved node on top of SRAM > > is good as removing this. How about we do this: a) Start by discussing in k.org with a patch as to how we think it should be and what the rationale is. b) SRAM size fixup is a consequence of firmware being flexible.. Since, the tifs reserved sram etc, base description exists even after "hardware reconfiguration", u-boot may adjust, but not delete such nodes. "reserved" is part of complete description and indication that this specific OS is not supposed to use this region. That region is protected by firewall and mechanisms to make such access fail, but that is the point of "reserved" nodes. c) Standardize this across the SoCs that use MSMC (WITHOUT BREAKING FORWARD AND BACKWARD COMPATIBILITY of u-boot vs dtb). -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
Re: [PATCH v2 1/3] net: dhcp6: Add DHCPv6 (DHCP for IPv6)
On 2023-04-25 12:03 p.m., Ramon Fried wrote:
On Fri, Apr 7, 2023 at 9:55 PM Simon Glass wrote:
Hi,
On Fri, 7 Apr 2023 at 18:56, wrote:
From: Sean Edmond
Adds DHCPv6 protocol to u-boot.
Allows for address assignement with DHCPv6 4-message exchange
(SOLICIT->ADVERTISE->REQUEST->REPLY). Includes DHCPv6 options
required by RFC 8415. Also adds DHCPv6 options required
for PXE boot.
Possible enhancements:
- Duplicate address detection on DHCPv6 assigned address
- IPv6 address assignement through SLAAC
- Sending/parsing other DHCPv6 options (NTP, DNS, etc...)
Signed-off-by: Sean Edmond
---
include/net.h | 8 +-
net/Makefile | 1 +
net/dhcpv6.c | 735 ++
net/dhcpv6.h | 212 +++
net/net.c | 12 +
5 files changed, 966 insertions(+), 2 deletions(-)
create mode 100644 net/dhcpv6.c
create mode 100644 net/dhcpv6.h
This looks good to me. I just have a few nits below. With those fixed:
Reviewed-by: Simon Glass
diff --git a/include/net.h b/include/net.h
index 399af5e064..cac818e292 100644
--- a/include/net.h
+++ b/include/net.h
@@ -484,6 +484,10 @@ extern charnet_hostname[32]; /* Our hostname
*/
#ifdef CONFIG_NET
extern charnet_root_path[CONFIG_BOOTP_MAX_ROOT_PATH_LEN]; /* Our root
path */
#endif
+#if defined(CONFIG_DHCP6_PXE_DHCP_OPTION)
You can drop this #ifdef as any reference to a non-existent var will
give a build error.
+/* Indicates whether the pxe path prefix / config file was specified in dhcp
option */
+extern char *pxelinux_configfile;
+#endif
/** END OF BOOTP EXTENTIONS **/
extern u8 net_ethaddr[ARP_HLEN]; /* Our ethernet
address */
extern u8 net_server_ethaddr[ARP_HLEN]; /* Boot server enet
address */
@@ -504,8 +508,8 @@ extern ushort net_native_vlan;/* Our
Native VLAN */
extern int net_restart_wrap; /* Tried all network devices */
enum proto_t {
- BOOTP, RARP, ARP, TFTPGET, DHCP, PING, PING6, DNS, NFS, CDP, NETCONS,
- SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI, WGET
+ BOOTP, RARP, ARP, TFTPGET, DHCP, DHCP6, PING, PING6, DNS, NFS, CDP,
+ NETCONS, SNTP, TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP, NCSI,
WGET
};
extern charnet_boot_file_name[1024];/* Boot File name */
diff --git a/net/Makefile b/net/Makefile
index bea000b206..5968110170 100644
--- a/net/Makefile
+++ b/net/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_IPV6) += net6.o
obj-$(CONFIG_CMD_NFS) += nfs.o
obj-$(CONFIG_CMD_PING) += ping.o
obj-$(CONFIG_CMD_PING6) += ping6.o
+obj-$(CONFIG_CMD_DHCP6) += dhcpv6.o
obj-$(CONFIG_CMD_PCAP) += pcap.o
obj-$(CONFIG_CMD_RARP) += rarp.o
obj-$(CONFIG_CMD_SNTP) += sntp.o
diff --git a/net/dhcpv6.c b/net/dhcpv6.c
new file mode 100644
index 00..9204909c1f
--- /dev/null
+++ b/net/dhcpv6.c
@@ -0,0 +1,735 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) Microsoft Corporation
+ * Author: Sean Edmond
+ *
+ */
+
+/* Simple DHCP6 network layer implementation. */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "dhcpv6.h"
+#include
+#include
+#include "net_rand.h"
Please fix header order:
https://u-boot.readthedocs.io/en/latest/develop/codingstyle.html#include-files
+
+#define PORT_DHCP6_S 547 /* DHCP6 server UDP port */
+#define PORT_DHCP6_C 546 /* DHCP6 client UDP port */
+
+/* default timeout parameters (in ms) */
+#define SOL_MAX_DELAY_MS 1000
+#define SOL_TIMEOUT_MS 1000
+#define SOL_MAX_RT_MS 360
+#define REQ_TIMEOUT_MS 1000
+#define REQ_MAX_RT_MS 3
+#define REQ_MAX_RC 10
+#define MAX_WAIT_TIME_MS 6
+
+/* global variable to track any updates from DHCP6 server */
+int updated_sol_max_rt_ms = SOL_MAX_RT_MS;
+
+static void dhcp6_timeout_handler(void);
+static void dhcp6_state_machine(bool timeout, uchar *rx_pkt, unsigned int len);
+static void dhcp6_parse_options(uchar *rx_pkt, unsigned int len);
Rather than forward decls can you reorder the functions?
+
+struct dhcp6_sm_params sm_params;
+
+/*
+ * Handle DHCP received packets (set as UDP handler)
+ */
Please check single-line comment style
+static void dhcp6_handler(uchar *pkt, unsigned int dest, struct in_addr sip,
+ unsigned int src, unsigned int len)
+{
+ /* return if ports don't match DHCPv6 ports */
+ if (dest != PORT_DHCP6_C || src != PORT_DHCP6_S)
+ return;
+
+ dhcp6_state_machine(false, pkt, len);
+}
+
[..]
+ case DHCP6_OPTION_OPT_BOOTFILE_URL:
+ debug("DHCP6_OPTION_OPT_BOOTFILE_URL FOUND\n");
+ copy_filename(net_boot_file_name, option_ptr,
option_len + 1);
+ debug("net_boot_file_name: %s\n", net_boot_file_name);
+
+ /* copy
Re: [PATCH] board: gateworks: venice: add eraseenv command
On Tue, May 2, 2023 at 2:46 PM Tim Harvey wrote: > > Add eraseenv command and remove the unnecessary env command. > > Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam
Re: [PATCH] board: gateworks: venice: add GPIO name lookup
On Tue, May 2, 2023 at 2:45 PM Tim Harvey wrote: > > Add GPIO name lookup so that you can act on GPIO's by name vs controller > id: > > Before: > u-boot=> gpio input pci_wdis# > GPIO: 'pci_wdis#' not found > Command 'gpio' failed: Error -22 > > After: > u-boot=> gpio input pci_wdis# > gpio: pin pci_wdis# (gpio 103) value is 1 > > Signed-off-by: Tim Harvey Reviewed-by: Fabio Estevam
[PATCH 2/2] pci: apple: Add support for M2 Pro/Max
The PCIe controller on the M2 Pro/Max is different from the one
found on earlier Apple SoCs. Some registers moved and te meaning
of the bits in some other registers changed. But they are still
similar enough to handle both controllers in the same driver.
Signed-off-by: Mark Kettenis
---
drivers/pci/pcie_apple.c | 100 +++
1 file changed, 71 insertions(+), 29 deletions(-)
diff --git a/drivers/pci/pcie_apple.c b/drivers/pci/pcie_apple.c
index b934fdbc35..21bafba3b0 100644
--- a/drivers/pci/pcie_apple.c
+++ b/drivers/pci/pcie_apple.c
@@ -37,14 +37,18 @@
#define CORE_RC_STAT_READY BIT(0)
#define CORE_FABRIC_STAT 0x04000
#define CORE_FABRIC_STAT_MASK0x001F001F
-#define CORE_LANE_CFG(port)(0x84000 + 0x4000 * (port))
-#define CORE_LANE_CFG_REFCLK0REQ BIT(0)
-#define CORE_LANE_CFG_REFCLK1REQ BIT(1)
-#define CORE_LANE_CFG_REFCLK0ACK BIT(2)
-#define CORE_LANE_CFG_REFCLK1ACK BIT(3)
-#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
-#define CORE_LANE_CTL(port)(0x84004 + 0x4000 * (port))
-#define CORE_LANE_CTL_CFGACC BIT(15)
+
+#define CORE_PHY_DEFAULT_BASE(port)(0x84000 + 0x4000 * (port))
+
+#define PHY_LANE_CFG 0x0
+#define PHY_LANE_CFG_REFCLK0REQ BIT(0)
+#define PHY_LANE_CFG_REFCLK1REQ BIT(1)
+#define PHY_LANE_CFG_REFCLK0ACK BIT(2)
+#define PHY_LANE_CFG_REFCLK1ACK BIT(3)
+#define PHY_LANE_CFG_REFCLKEN(BIT(9) | BIT(10))
+#define PHY_LANE_CFG_REFCLKCGEN (BIT(30) | BIT(31))
+#define PHY_LANE_CTL 0x4
+#define PHY_LANE_CTL_CFGACC BIT(15)
#define PORT_LTSSMCTL 0x00080
#define PORT_LTSSMCTL_START BIT(0)
@@ -116,11 +120,32 @@
#define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
#define PORT_PREFMEM_ENABLE0x00994
+struct reg_info {
+ u32 phy_lane_ctl;
+ u32 port_refclk;
+ u32 port_perst;
+};
+
+const struct reg_info t8103_hw = {
+ .phy_lane_ctl = PHY_LANE_CTL,
+ .port_refclk = PORT_REFCLK,
+ .port_perst = PORT_PERST,
+};
+
+#define PORT_T602X_PERST 0x082c
+
+const struct reg_info t602x_hw = {
+ .phy_lane_ctl = 0,
+ .port_refclk = 0,
+ .port_perst = PORT_T602X_PERST,
+};
+
struct apple_pcie_priv {
struct udevice *dev;
void __iomem*base;
void __iomem*cfg_base;
struct list_headports;
+ const struct reg_info *hw;
};
struct apple_pcie_port {
@@ -128,6 +153,7 @@ struct apple_pcie_port {
struct gpio_descreset;
ofnode np;
void __iomem*base;
+ void __iomem*phy;
struct list_headentry;
int idx;
};
@@ -187,33 +213,32 @@ static int apple_pcie_setup_refclk(struct apple_pcie_priv
*pcie,
u32 stat;
int res;
- res = readl_poll_sleep_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat,
- stat & CORE_RC_PHYIF_STAT_REFCLK,
- 100, 5);
- if (res < 0)
- return res;
+ if (pcie->hw->phy_lane_ctl)
+ rmw_set(PHY_LANE_CTL_CFGACC, port->phy +
pcie->hw->phy_lane_ctl);
- rmw_set(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
- rmw_set(CORE_LANE_CFG_REFCLK0REQ, pcie->base +
CORE_LANE_CFG(port->idx));
+ rmw_set(PHY_LANE_CFG_REFCLK0REQ, port->phy + PHY_LANE_CFG);
- res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
- stat, stat & CORE_LANE_CFG_REFCLK0ACK,
+ res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
+ stat, stat & PHY_LANE_CFG_REFCLK0ACK,
100, 5);
if (res < 0)
return res;
- rmw_set(CORE_LANE_CFG_REFCLK1REQ, pcie->base +
CORE_LANE_CFG(port->idx));
- res = readl_poll_sleep_timeout(pcie->base + CORE_LANE_CFG(port->idx),
- stat, stat & CORE_LANE_CFG_REFCLK1ACK,
+ rmw_set(PHY_LANE_CFG_REFCLK1REQ, port->phy + PHY_LANE_CFG);
+ res = readl_poll_sleep_timeout(port->phy + PHY_LANE_CFG,
+ stat, stat & PHY_LANE_CFG_REFCLK1ACK,
100, 5);
if (res < 0)
return res;
- rmw_clear(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
+ if (pcie->hw->phy_lane_ctl)
+ rmw_clear(PHY_LANE_CTL_CFGACC, port->phy +
pcie->hw->phy_lane_ctl);
+
+ rmw_set(PHY_LANE_CFG_REFCLKEN, port->phy + PHY_LANE_CFG);
- rmw_set(CORE_LANE_CFG_REFCLKEN, pcie->base + CORE_LANE_CFG(port->idx));
- rmw_set(PORT_REFCLK_EN, port->base + PORT_REFCLK);
+
[PATCH 1/2] arm: apple: Add initial Apple M2 Pro/Max support
Apple's M2 Pro/Max SoC are somewhat similar to the M1 Pro/Max but
need a tweaked memory map. USB, NVMe, UART and WDT are working
with the existing drivers.
Signed-off-by: Mark Kettenis
---
arch/arm/mach-apple/board.c | 109 +++-
1 file changed, 106 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 1604642312..d501948118 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -343,6 +343,107 @@ static struct mm_region t6002_mem_map[] = {
}
};
+/* Apple M2 Pro/Max */
+
+static struct mm_region t6020_mem_map[] = {
+ {
+ /* I/O */
+ .virt = 0x28000,
+ .phys = 0x28000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x34000,
+ .phys = 0x34000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x38000,
+ .phys = 0x38000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x58000,
+ .phys = 0x58000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5a000,
+ .phys = 0x5a000,
+ .size = SZ_512M,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+PTE_BLOCK_INNER_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* PCIE */
+ .virt = 0x5c000,
+ .phys = 0x5c000,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) |
+PTE_BLOCK_INNER_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x7,
+ .phys = 0x7,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xb,
+ .phys = 0xb,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0xf,
+ .phys = 0xf,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* I/O */
+ .virt = 0x13,
+ .phys = 0x13,
+ .size = SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+PTE_BLOCK_NON_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* RAM */
+ .virt = 0x100,
+ .phys = 0x100,
+ .size = 16UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+PTE_BLOCK_INNER_SHARE
+ }, {
+ /* Framebuffer */
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) |
+PTE_BLOCK_INNER_SHARE |
+PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
struct mm_region *mem_map;
int board_init(void)
@@ -379,12 +480,14 @@ void build_mem_map(void)
if (of_machine_is_compatible("apple,t8103") ||
of_machine_is_compatible("apple,t8112"))
mem_map = t8103_mem_map;
- else if (of_machine_is_compatible("apple,t6000"))
- mem_map = t6000_mem_map;
- else if (of_machine_is_compatible("apple,t6001"))
+ else if (of_machine_is_compatible("apple,t6000") ||
+of_machine_is_compatible("apple,t6001"))
mem_map = t6000_mem_map;
else if (of_machine_is_compatible("apple,t6002"))
mem_map = t6002_mem_map;
+ else if
[PATCH 0/2] Apple M2 Pro/Max support
These new SoCs are similar to the M1 Pro/Max but do have a slightly different memory map. They also have a new PCIe controller. Mark Kettenis (2): arm: apple: Add initial Apple M2 Pro/Max support pci: apple: Add support for M2 Pro/Max arch/arm/mach-apple/board.c | 109 +++- drivers/pci/pcie_apple.c| 100 +++-- 2 files changed, 177 insertions(+), 32 deletions(-) -- 2.40.0
[PATCH v3 3/3] Load option with short device path for boot vars
The boot variables automatically generated for removable medias
should be with short form of device path without device nodes.
This is a requirement for the case that a removable media is
plugged into a different port but is still able to work with the
existing boot variables.
Signed-off-by: Raymond Mao
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
efi_bootmgr_update_media_device_boot_option which means no boot
options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
individual patches for each changed functionality
cmd/bootmenu.c| 2 +-
cmd/eficonfig.c | 2 +-
include/efi_loader.h | 2 +-
lib/efi_loader/efi_bootmgr.c | 16 +---
lib/efi_loader/efi_disk.c | 2 +-
lib/efi_loader/efi_variable.c | 2 +-
lib/efi_loader/efi_variable_tee.c | 2 +-
7 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 01daddca7b..058b47c69a 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -351,7 +351,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
* UEFI specification requires booting from removal media using
* a architecture-specific default image name such as
BOOTAA64.EFI.
*/
- efi_ret = efi_bootmgr_update_media_device_boot_option();
+ efi_ret = efi_bootmgr_update_media_device_boot_option(true);
if (efi_ret != EFI_SUCCESS && efi_ret != EFI_NOT_FOUND)
goto cleanup;
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index 82a80306f4..38371bfea6 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -2313,7 +2313,7 @@ static int do_eficonfig(struct cmd_tbl *cmdtp, int flag,
int argc, char *const a
if (ret != EFI_SUCCESS)
return CMD_RET_FAILURE;
- ret = efi_bootmgr_update_media_device_boot_option();
+ ret = efi_bootmgr_update_media_device_boot_option(true);
if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
return ret;
diff --git a/include/efi_loader.h b/include/efi_loader.h
index 31ca1f5d1d..0a69f08d6c 100644
--- a/include/efi_loader.h
+++ b/include/efi_loader.h
@@ -522,7 +522,7 @@ efi_status_t efi_bootmgr_append_bootorder(u16 index);
efi_status_t efi_bootmgr_get_unused_bootoption(u16 *buf,
efi_uintn_t buf_size, u32
*index);
/* Generate the media device boot option */
-efi_status_t efi_bootmgr_update_media_device_boot_option(void);
+efi_status_t efi_bootmgr_update_media_device_boot_option(bool short_path);
/* Delete selected boot option */
efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index);
/* search the boot option index in BootOrder */
diff --git a/lib/efi_loader/efi_bootmgr.c b/lib/efi_loader/efi_bootmgr.c
index c329428973..c4bc8b354f 100644
--- a/lib/efi_loader/efi_bootmgr.c
+++ b/lib/efi_loader/efi_bootmgr.c
@@ -354,11 +354,13 @@ error:
* @opt: pointer to the media boot option structure
* @volume_handles:pointer to the efi handles
* @count: number of efi handle
+ * @short_path:use short form device path for matching
* Return: status code
*/
static efi_status_t efi_bootmgr_enumerate_boot_option(struct
eficonfig_media_boot_option *opt,
efi_handle_t
*volume_handles,
- efi_status_t count)
+ efi_status_t count,
+ bool short_path)
{
u32 i;
struct efi_handler *handler;
@@ -387,6 +389,13 @@ static efi_status_t
efi_bootmgr_enumerate_boot_option(struct eficonfig_media_boo
p = dev_name;
utf8_utf16_strncpy(, buf, strlen(buf));
+ /* use short form device path */
+ if (short_path) {
+ device_path = efi_dp_shorten(device_path);
+ if (!device_path)
+ continue;
+ }
+
lo.label = dev_name;
lo.attributes = LOAD_OPTION_ACTIVE;
lo.file_path = device_path;
@@ -651,9 +660,10 @@ efi_status_t efi_bootmgr_delete_boot_option(u16 boot_index)
* - If the device is not attached to the system, the associated BOOT
variable
* is automatically deleted.
*
+ * @short_path:use short form device path for matching
* Return: status code
*/
-efi_status_t efi_bootmgr_update_media_device_boot_option(void)
+efi_status_t efi_bootmgr_update_media_device_boot_option(bool short_path)
{
u32 i;
efi_status_t ret;
@@ -673,7 +683,7 @@ efi_status_t
efi_bootmgr_update_media_device_boot_option(void)
goto out;
/* enumerate all devices supporting EFI_SIMPLE_FILE_SYSTEM_PROTOCOL */
-
[PATCH v3 2/3] Boot var automatic management for removable medias
Changes for complying to EFI spec §3.5.1.1
'Removable Media Boot Behavior'.
Boot variables can be automatically generated during a removable
media is probed. At the same time, unused boot variables will be
detected and removed.
Signed-off-by: Raymond Mao
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
efi_bootmgr_update_media_device_boot_option which means no boot
options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
individual patches for each changed functionality
lib/efi_loader/efi_disk.c | 7 +++
lib/efi_loader/efi_variable.c | 10 +-
lib/efi_loader/efi_variable_tee.c | 5 +
3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/lib/efi_loader/efi_disk.c b/lib/efi_loader/efi_disk.c
index d2256713a8..ca5f07f2ec 100644
--- a/lib/efi_loader/efi_disk.c
+++ b/lib/efi_loader/efi_disk.c
@@ -687,6 +687,13 @@ int efi_disk_probe(void *ctx, struct event *event)
return -1;
}
+ /* only do the boot option management when UEFI sub-system is
initialized */
+ if (efi_obj_list_initialized == EFI_SUCCESS) {
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+ return -1;
+ }
+
return 0;
}
diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c
index be95ed44e6..fe71144358 100644
--- a/lib/efi_loader/efi_variable.c
+++ b/lib/efi_loader/efi_variable.c
@@ -476,6 +476,14 @@ efi_status_t efi_init_variables(void)
log_err("Invalid EFI variable seed\n");
}
+ ret = efi_init_secure_state();
+ if (ret != EFI_SUCCESS)
+ return ret;
- return efi_init_secure_state();
+ /* update boot option management after variable service initialized */
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+ return ret;
+
+ return EFI_SUCCESS;
}
diff --git a/lib/efi_loader/efi_variable_tee.c
b/lib/efi_loader/efi_variable_tee.c
index dfef18435d..2995d4a583 100644
--- a/lib/efi_loader/efi_variable_tee.c
+++ b/lib/efi_loader/efi_variable_tee.c
@@ -748,5 +748,10 @@ efi_status_t efi_init_variables(void)
if (ret != EFI_SUCCESS)
return ret;
+ /* update boot option management after variable service initialized */
+ ret = efi_bootmgr_update_media_device_boot_option();
+ if (ret != EFI_SUCCESS && ret != EFI_NOT_FOUND)
+ return ret;
+
return EFI_SUCCESS;
}
--
2.25.1
[PATCH v3 1/3] Move bootorder and bootoption apis to lib
Rename and move bootorder and bootoption apis from cmd to lib
for re-use between eficonfig and bootmgr
Signed-off-by: Raymond Mao
---
Changes in v2
- Ignore EFI_NOT_FOUND returned from
efi_bootmgr_update_media_device_boot_option which means no boot
options scanned.
Changes in v3
- Split the patch into moving and renaming functions and
individual patches for each changed functionality
cmd/bootmenu.c | 2 +-
cmd/eficonfig.c | 408 +--
include/efi_config.h | 5 -
include/efi_loader.h | 11 +
lib/efi_loader/efi_bootmgr.c | 380
lib/efi_loader/efi_helper.c | 25 +++
6 files changed, 423 insertions(+), 408 deletions(-)
diff --git a/cmd/bootmenu.c b/cmd/bootmenu.c
index 6baeedc69f..01daddca7b 100644
--- a/cmd/bootmenu.c
+++ b/cmd/bootmenu.c
@@ -351,7 +351,7 @@ static struct bootmenu_data *bootmenu_create(int delay)
* UEFI specification requires booting from removal media using
* a architecture-specific default image name such as
BOOTAA64.EFI.
*/
- efi_ret = eficonfig_generate_media_device_boot_option();
+ efi_ret = efi_bootmgr_update_media_device_boot_option();
if (efi_ret != EFI_SUCCESS && efi_ret != EFI_NOT_FOUND)
goto cleanup;
diff --git a/cmd/eficonfig.c b/cmd/eficonfig.c
index 720f52b48b..82a80306f4 100644
--- a/cmd/eficonfig.c
+++ b/cmd/eficonfig.c
@@ -1134,43 +1134,6 @@ out:
return ret;
}
-/**
- * eficonfig_get_unused_bootoption() - get unused "Boot" index
- *
- * @buf: pointer to the buffer to store boot option variable name
- * @buf_size: buffer size
- * @index: pointer to store the index in the BootOrder variable
- * Return: status code
- */
-efi_status_t eficonfig_get_unused_bootoption(u16 *buf, efi_uintn_t buf_size,
-unsigned int *index)
-{
- u32 i;
- efi_status_t ret;
- efi_uintn_t size;
-
- if (buf_size < u16_strsize(u"Boot"))
- return EFI_BUFFER_TOO_SMALL;
-
- for (i = 0; i <= 0x; i++) {
- size = 0;
- efi_create_indexed_name(buf, buf_size, "Boot", i);
- ret = efi_get_variable_int(buf, _global_variable_guid,
- NULL, , NULL, NULL);
- if (ret == EFI_BUFFER_TOO_SMALL)
- continue;
- else
- break;
- }
-
- if (i > 0x)
- return EFI_OUT_OF_RESOURCES;
-
- *index = i;
-
- return EFI_SUCCESS;
-}
-
/**
* eficonfig_set_boot_option() - set boot option
*
@@ -1208,46 +1171,6 @@ static efi_status_t eficonfig_set_boot_option(u16
*varname, struct efi_device_pa
return ret;
}
-/**
- * eficonfig_append_bootorder() - append new boot option in BootOrder variable
- *
- * @index: "Boot" index to append to BootOrder variable
- * Return: status code
- */
-efi_status_t eficonfig_append_bootorder(u16 index)
-{
- u16 *bootorder;
- efi_status_t ret;
- u16 *new_bootorder = NULL;
- efi_uintn_t last, size, new_size;
-
- /* append new boot option */
- bootorder = efi_get_var(u"BootOrder", _global_variable_guid, );
- last = size / sizeof(u16);
- new_size = size + sizeof(u16);
- new_bootorder = calloc(1, new_size);
- if (!new_bootorder) {
- ret = EFI_OUT_OF_RESOURCES;
- goto out;
- }
- memcpy(new_bootorder, bootorder, size);
- new_bootorder[last] = index;
-
- ret = efi_set_variable_int(u"BootOrder", _global_variable_guid,
- EFI_VARIABLE_NON_VOLATILE |
- EFI_VARIABLE_BOOTSERVICE_ACCESS |
- EFI_VARIABLE_RUNTIME_ACCESS,
- new_size, new_bootorder, false);
- if (ret != EFI_SUCCESS)
- goto out;
-
-out:
- free(bootorder);
- free(new_bootorder);
-
- return ret;
-}
-
/**
* create_boot_option_entry() - create boot option entry
*
@@ -1619,7 +1542,7 @@ static efi_status_t
eficonfig_process_add_boot_option(void *data)
if (!bo)
return EFI_OUT_OF_RESOURCES;
- ret = eficonfig_get_unused_bootoption(varname, sizeof(varname),
>boot_index);
+ ret = efi_bootmgr_get_unused_bootoption(varname, sizeof(varname),
>boot_index);
if (ret != EFI_SUCCESS)
return ret;
@@ -1627,7 +1550,7 @@ static efi_status_t
eficonfig_process_add_boot_option(void *data)
if (ret != EFI_SUCCESS)
goto out;
- ret = eficonfig_append_bootorder((u16)bo->boot_index);
+ ret = efi_bootmgr_append_bootorder((u16)bo->boot_index);
if (ret != EFI_SUCCESS)
goto out;
@@ -1656,31 +1579,6 @@ static
Re: [RFC PATCH v1 6/7] clk: treewide: switch to clock dump from clk_ops
Hello Michal,
On Tue, May 02, 2023 at 04:02:00PM +0200, Michal Simek wrote:
>
>
> On 4/27/23 22:37, Igor Prusov wrote:
> > Switch to using new dump operation in clock provider drivers instead of
> > overriding soc_clk_dump.
> >
> > Signed-off-by: Igor Prusov
> > ---
> > arch/mips/mach-pic32/cpu.c | 23 ---
> > drivers/clk/aspeed/clk_ast2600.c | 13 -
> > drivers/clk/clk_k210.c | 11 +++-
> > drivers/clk/clk_pic32.c| 39 ++
> > drivers/clk/clk_versal.c | 7 -
> > drivers/clk/clk_zynq.c | 19 -
> > drivers/clk/clk_zynqmp.c | 13 -
> > drivers/clk/imx/clk-imx8.c | 11 +++-
> > drivers/clk/mvebu/armada-37xx-periph.c | 5 +++-
> > drivers/clk/stm32/clk-stm32mp1.c | 29 ++-
> > 10 files changed, 83 insertions(+), 87 deletions(-)
> >
> > diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
> > index de449e3c6a..2875a1ec7c 100644
> > --- a/arch/mips/mach-pic32/cpu.c
> > +++ b/arch/mips/mach-pic32/cpu.c
> > @@ -148,26 +148,3 @@ const char *get_core_name(void)
> > return str;
> > }
> > #endif
> > -#ifdef CONFIG_CMD_CLK
> > -
> > -int soc_clk_dump(void)
> > -{
> > - int i;
> > -
> > - printf("PLL Speed: %lu MHz\n",
> > - CLK_MHZ(rate(PLLCLK)));
> > -
> > - printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
> > -
> > - printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
> > -
> > - for (i = PB1CLK; i <= PB7CLK; i++)
> > - printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
> > - CLK_MHZ(rate(i)));
> > -
> > - for (i = REF1CLK; i <= REF5CLK; i++)
> > - printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
> > - CLK_MHZ(rate(i)));
> > - return 0;
> > -}
> > -#endif
> > diff --git a/drivers/clk/aspeed/clk_ast2600.c
> > b/drivers/clk/aspeed/clk_ast2600.c
> > index b3cc8392fa..08db21d394 100644
> > --- a/drivers/clk/aspeed/clk_ast2600.c
> > +++ b/drivers/clk/aspeed/clk_ast2600.c
> > @@ -1109,6 +1109,7 @@ struct aspeed_clks {
> > const char *name;
> > };
> > +#if IS_ENABLED(CONFIG_CMD_CLK)
> > static struct aspeed_clks aspeed_clk_names[] = {
> > { ASPEED_CLK_HPLL, "hpll" },
> > { ASPEED_CLK_MPLL, "mpll" },
> > @@ -1123,18 +1124,12 @@ static struct aspeed_clks aspeed_clk_names[] = {
> > { ASPEED_CLK_HUARTX, "huxclk" },
> > };
> > -int soc_clk_dump(void)
> > +int ast2600_clk_dump(struct udevice *dev)
>
> static? apply for all below too.
Indeed, will fix in v2, thanks!
>
> M
--
Best Regards,
Igor Prusov
[PATCH v2 2/3] X86: Add support for distro boot
From: Thomas Mittelstaedt Enable distro boot feature for U-Boot at VirtualBox described at https://source.denx.de/u-boot/u-boot/-/blob/master/doc/develop/distro.rst Signed-off-by: Thomas Mittelstaedt --- configs/efi-x86_payload64_defconfig | 12 +--- include/configs/efi-x86_payload.h | 11 +++ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 30a7f31dac..a4cfe95890 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -8,33 +8,23 @@ CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DISTRO_DEFAULTS=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" -CONFIG_USE_BOOTCOMMAND=y CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_LAST_STAGE_INIT=y -CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y -CONFIG_CMD_PART=y CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y # CONFIG_CMD_NFS is not set -CONFIG_CMD_PING=y CONFIG_CMD_TIME=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y CONFIG_MAC_PARTITION=y -CONFIG_ISO_PARTITION=y -CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FAT=y CONFIG_ENV_FAT_INTERFACE="scsi" diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h index c72b067c36..e1cd8eb316 100644 --- a/include/configs/efi-x86_payload.h +++ b/include/configs/efi-x86_payload.h @@ -6,6 +6,17 @@ /* * board/config.h - configuration options, board specific */ +#ifndef CONFIG_SPL_BUILD + +#define BOOT_TARGET_SCSI(func) \ + func(SCSI, scsi, 0) + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_SCSI(func) + +#include + +#endif #ifndef __CONFIG_H #define __CONFIG_H -- 2.30.2
[PATCH v2 3/3] X86: pxeboot: bugfix: Set variable for size of initrd
From: Thomas Mittelstaedt
The problem was, that zboot() didn't work because of missing
ramdisc size.
Signed-off-by: Thomas Mittelstaedt
---
boot/pxe_utils.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c
index 3a1e50f2b1..87c32b6e62 100644
--- a/boot/pxe_utils.c
+++ b/boot/pxe_utils.c
@@ -554,7 +554,7 @@ static int label_boot(struct pxe_context *ctx, struct
pxe_label *label)
label->name);
goto cleanup;
}
-
+ strcpy(initrd_filesize, simple_xtoa(size));
initrd_addr_str = env_get("ramdisk_addr_r");
size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
initrd_addr_str, size);
--
2.30.2
[PATCH v2 1/3] X86: Add support for SCSI devices
From: Thomas Mittelstaedt U-Boot at VirtualBox must load Linux and boot configuration from disk devices. Here the discs at AHCI (scsi) bus are used to load the need boot data. Signed-off-by: Thomas Mittelstaedt --- configs/efi-x86_payload64_defconfig | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/configs/efi-x86_payload64_defconfig b/configs/efi-x86_payload64_defconfig index 5cde04a5ac..30a7f31dac 100644 --- a/configs/efi-x86_payload64_defconfig +++ b/configs/efi-x86_payload64_defconfig @@ -7,11 +7,11 @@ CONFIG_VENDOR_EFI=y CONFIG_TARGET_EFI_PAYLOAD=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y +CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" CONFIG_USE_BOOTCOMMAND=y -CONFIG_BOOTCOMMAND="ext2load scsi 0:3 0100 /boot/vmlinuz; zboot 0100" CONFIG_PRE_CONSOLE_BUFFER=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_DISPLAY_BOARDINFO_LATE=y @@ -22,7 +22,6 @@ CONFIG_CMD_IDE=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y CONFIG_CMD_USB=y -# CONFIG_CMD_SETEXPR is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y # CONFIG_CMD_NFS is not set @@ -37,6 +36,9 @@ CONFIG_MAC_PARTITION=y CONFIG_ISO_PARTITION=y CONFIG_EFI_PARTITION=y CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_INTERFACE="scsi" +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y CONFIG_BOOTFILE="bzImage" -- 2.30.2
[PATCH v2 0/3] Enable U-Boot at Virtualbox to boot images
From: Thomas Mittelstaedt The changes are needed to get U-Boot to be started at VirtualBox images supporting distro boot capability. Atm the patch "pci: coreboot: Don't read regions when booting" from Simon Glass is not integrated yet. So AHCI and IDE devices are not handled correctly without this patch. (https://patchwork.ozlabs.org/project/uboot/patch/20230220194927.476708-8-...@chromium.org/) Changes since v1: - Remove prompt change commit - Add details in commit messages - defconfig now handled with savedefconfig option at make - Unneccessary option CONFIG_CMD_SETEXPR no more set - First patch was set with mtt2hi and thomas.mittelsta...@bosch.com. Now set with my usual id Thomas Mittelstaedt Thomas Mittelstaedt (3): X86: Add support for SCSI devices X86: Add support for distro boot X86: pxeboot: bugfix: Set variable for size of initrd boot/pxe_utils.c| 2 +- configs/efi-x86_payload64_defconfig | 18 +- include/configs/efi-x86_payload.h | 11 +++ 3 files changed, 17 insertions(+), 14 deletions(-) -- 2.30.2
AW: [PATCH 4/4] X86: pxeboot: bugfix: Set variable for size of initrd
> -Ursprüngliche Nachricht-
> Von: Heinrich Schuchardt
> Gesendet: Dienstag, 2. Mai 2023 12:15
> An: Mittelstaedt Thomas (XC-CT/EBV3) ; u-
> b...@lists.denx.de
> Cc: Simon Glass ; Niel Armstrong
> ; Patrick Delaunay ;
> Ramon Fried ; Marek Vasut ; Manuel
> Traut ; Bin Meng
> Betreff: Re: [PATCH 4/4] X86: pxeboot: bugfix: Set variable for size of initrd
>
> On 5/2/23 11:49, thomas.mittelsta...@bosch.com wrote:
> > From: mtt2hi
> >
> > The problem was, that zboot() didn't work because of missing ramdisc
> > size.
>
> Can we create a test for this?
We could test it, if all would be fine.
Atm this function seems only to be called by distroboot implementation. And
this is not activated yet.
But for the first time a code walk trough seems to be more appropriate.
At line 551/552 the initrd is loaded to memory and the size is saved to
variable size.
My correction at 557 stores a string representing the size to variable
initrd_filesize
At line 725 initrd_filesize is set to parameters of function zboot().
So it must fail without the correction.
>
> Best regards
>
> Heirnich
>
> >
> > Signed-off-by: mtt2hi
> > ---
> > boot/pxe_utils.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/boot/pxe_utils.c b/boot/pxe_utils.c index
> > 3a1e50f2b1..87c32b6e62 100644
> > --- a/boot/pxe_utils.c
> > +++ b/boot/pxe_utils.c
> > @@ -554,7 +554,7 @@ static int label_boot(struct pxe_context *ctx, struct
> pxe_label *label)
> >label->name);
> > goto cleanup;
> > }
> > -
> > + strcpy(initrd_filesize, simple_xtoa(size));
> > initrd_addr_str = env_get("ramdisk_addr_r");
> > size = snprintf(initrd_str, sizeof(initrd_str), "%s:%lx",
> > initrd_addr_str, size);
[PATCH v2 0/9] spi: bcm63xx-hsspi: driver and doc updates
This patch series is the u-boot port from the recently accepted kernel Broadcom HSSPI driver patch series here [1]. It includes the accumulative updates and fixes for the driver from Broadcom. It also added a new driver for the updated SPI controller found in the new BCMBCA SoC. The device tree document is converted to yaml format and updated accordingly. [1]: https://lore.kernel.org/all/20230207065826.285013-1-william.zh...@broadcom.com/ Changes in v2: - Add Álvaro Fernández Rojas as another maintainer William Zhang (9): dt-bindings: spi: Add bcm63xx-hsspi controller support ARM: dts: broadcom: bcmbca: Add spi controller node arm64: dts: broadcom: bcmbca: Add spi controller node spi: bcm63xx-hsspi: Enable SPI drivers by default spi: bcm63xx-hsspi: Add new compatible string support spi: bcm63xx-hsspi: Fix multi-bit mode setting spi: bcm63xx-hsspi: Add prepend mode support spi: bcmbca-hsspi: Add driver for newer HSSPI controller MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers MAINTAINERS | 9 + arch/arm/Kconfig | 2 + arch/arm/dts/bcm47622.dtsi| 18 + arch/arm/dts/bcm4908.dtsi | 17 + arch/arm/dts/bcm4912.dtsi | 20 + arch/arm/dts/bcm63138.dtsi| 18 + arch/arm/dts/bcm63146.dtsi| 19 + arch/arm/dts/bcm63148.dtsi| 18 + arch/arm/dts/bcm63158.dtsi| 15 +- arch/arm/dts/bcm63178.dtsi| 19 + arch/arm/dts/bcm6756.dtsi | 19 + arch/arm/dts/bcm6813.dtsi | 20 + arch/arm/dts/bcm6846.dtsi | 18 + arch/arm/dts/bcm6855.dtsi | 27 +- arch/arm/dts/bcm6856.dtsi | 23 +- arch/arm/dts/bcm6858.dtsi | 23 +- arch/arm/dts/bcm6878.dtsi | 19 + arch/arm/dts/bcm947622.dts| 4 + arch/arm/dts/bcm94908.dts | 4 + arch/arm/dts/bcm94912.dts | 4 + arch/arm/dts/bcm963138.dts| 4 + arch/arm/dts/bcm963146.dts| 4 + arch/arm/dts/bcm963148.dts| 4 + arch/arm/dts/bcm963158.dts| 4 + arch/arm/dts/bcm963178.dts| 4 + arch/arm/dts/bcm96756.dts | 4 + arch/arm/dts/bcm96813.dts | 4 + arch/arm/dts/bcm96846.dts | 4 + arch/arm/dts/bcm96855.dts | 4 + arch/arm/dts/bcm96856.dts | 4 + arch/arm/dts/bcm96858.dts | 4 + arch/arm/dts/bcm96878.dts | 4 + arch/arm/mach-bcmbca/Kconfig | 26 ++ .../spi/brcm,bcm63xx-hsspi.yaml | 134 ++ drivers/spi/Kconfig | 13 +- drivers/spi/Makefile | 1 + drivers/spi/bcm63xx_hsspi.c | 277 +++- drivers/spi/bcmbca_hsspi.c| 414 ++ 38 files changed, 1160 insertions(+), 69 deletions(-) create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml create mode 100644 drivers/spi/bcmbca_hsspi.c -- 2.37.3
[PATCH v2 8/9] spi: bcmbca-hsspi: Add driver for newer HSSPI controller
The newer BCMBCA SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI controller that add the capability to allow the driver to control chip select explicitly. Driver can control and keep cs low between the transfers natively. Hence the dummy cs workaround or prepend mode found in the bcm63xx-hsspi driver are no longer needed and this new driver is much cleaner. Port from linux patch: Link: https://lore.kernel.org/r/20230209200246.141520-15-william.zh...@broadcom.com Signed-off-by: William Zhang --- Changes in v2: None arch/arm/mach-bcmbca/Kconfig | 15 ++ drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/bcmbca_hsspi.c | 414 +++ 4 files changed, 439 insertions(+) create mode 100644 drivers/spi/bcmbca_hsspi.c diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 6441ed5929d2..60b36c4bb0f6 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -27,6 +27,7 @@ config BCM4912 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM63138 bool "Support for Broadcom 63138 Family" @@ -75,6 +76,7 @@ config BCM6756 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6813 bool "Support for Broadcom 6813 Family" @@ -82,6 +84,7 @@ config BCM6813 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI config BCM6846 bool "Support for Broadcom 6846 Family" @@ -97,6 +100,7 @@ config BCM6855 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCMBCA_HSSPI help Broadcom BCM6855 is a triple core Cortex A7 based xPON Gateway SoC. This SoC family includes BCM6855x, BCM68252 and BCM6753. @@ -131,6 +135,17 @@ config BCM6878 select PL01X_SERIAL select BCM63XX_HSSPI +config HAVE_SPI_CS_CTRL + bool "SoC supports SPI chip select control" + default y if BCM4912 + default y if BCM6756 + default y if BCM6855 + default y if BCM6813 + default n + help + Enable this option if SoC supports SPI chip select control explicitly + through software. + source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" source "arch/arm/mach-bcmbca/bcm4912/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 47a261f1e1b8..6b26915f9bb2 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -107,6 +107,15 @@ config BCM63XX_HSSPI access the SPI NOR flash on platforms embedding this Broadcom SPI core. +config BCMBCA_HSSPI + bool "BCMBCA HSSPI driver" + depends on ARCH_BCMBCA && HAVE_SPI_CS_CTRL + help + This enables support for the High Speed SPI controller present on + newer Broadcom BCMBCA SoCs. These SoCs include an updated SPI controller + that adds the capability to allow the driver to control chip select + explicitly. + config BCM63XX_SPI bool "BCM6348 SPI driver" depends on ARCH_BMIPS diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 95dba9ac4559..c27b3327c337 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_ATH79_SPI) += ath79_spi.o obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o +obj-$(CONFIG_BCMBCA_HSSPI) += bcmbca_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o obj-$(CONFIG_BCMSTB_SPI) += bcmstb_spi.o obj-$(CONFIG_CF_SPI) += cf_spi.o diff --git a/drivers/spi/bcmbca_hsspi.c b/drivers/spi/bcmbca_hsspi.c new file mode 100644 index ..fbe315a7d45d --- /dev/null +++ b/drivers/spi/bcmbca_hsspi.c @@ -0,0 +1,414 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017 Álvaro Fernández Rojas + * + * Derived from linux/drivers/spi/spi-bcm63xx-hsspi.c: + * Copyright (C) 2000-2010 Broadcom Corporation + * Copyright (C) 2012-2013 Jonas Gorski + * Copyright (C) 2021 Broadcom Ltd + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define HSSPI_PP 0 + +#define SPI_MAX_SYNC_CLOCK 3000 + +/* SPI Control register */ +#define SPI_CTL_REG0x000 +#define SPI_CTL_CS_POL_SHIFT 0 +#define SPI_CTL_CS_POL_MASK(0xff << SPI_CTL_CS_POL_SHIFT) +#define SPI_CTL_CLK_GATE_SHIFT 16 +#define SPI_CTL_CLK_GATE_MASK BIT(SPI_CTL_CLK_GATE_SHIFT) +#define SPI_CTL_CLK_POL_SHIFT 17 +#define SPI_CTL_CLK_POL_MASK BIT(SPI_CTL_CLK_POL_SHIFT) + +/* SPI Interrupts registers */ +#define SPI_IR_STAT_REG0x008 +#define SPI_IR_ST_MASK_REG 0x00c +#define SPI_IR_MASK_REG
[PATCH v2 6/9] spi: bcm63xx-hsspi: Fix multi-bit mode setting
Currently the driver always sets the controller to dual data bit mode
for both tx and rx data in the profile mode control register even for
single data bit transfer. Luckily the opcode is set correctly according
to SPI transfer data bit width so it does not actually cause issues.
This change fixes the problem by setting tx and rx data bit mode field
correctly according to the actual SPI transfer tx and rx data bit width.
Fixes: 29cc4368ad4b ("dm: spi: add BCM63xx HSSPI driver")
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-11-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 495feba02262..0d12c345b1dd 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -221,7 +221,7 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev, unsigned
int bitlen,
size_t data_bytes = bitlen / 8;
size_t step_size = HSSPI_FIFO_SIZE;
uint16_t opcode = 0;
- uint32_t val;
+ uint32_t val = SPI_PFL_MODE_FILL_MASK;
const uint8_t *tx = dout;
uint8_t *rx = din;
@@ -240,14 +240,17 @@ static int bcm63xx_hsspi_xfer(struct udevice *dev,
unsigned int bitlen,
step_size -= HSSPI_FIFO_OP_SIZE;
/* dual mode */
- if ((opcode == HSSPI_FIFO_OP_CODE_R && plat->mode == SPI_RX_DUAL) ||
- (opcode == HSSPI_FIFO_OP_CODE_W && plat->mode == SPI_TX_DUAL))
+ if ((opcode == HSSPI_FIFO_OP_CODE_R && (plat->mode & SPI_RX_DUAL)) ||
+ (opcode == HSSPI_FIFO_OP_CODE_W && (plat->mode & SPI_TX_DUAL))) {
opcode |= HSSPI_FIFO_OP_MBIT_MASK;
- /* profile mode */
- val = SPI_PFL_MODE_FILL_MASK |
- SPI_PFL_MODE_MDRDSZ_MASK |
- SPI_PFL_MODE_MDWRSZ_MASK;
+ /* profile mode */
+ if (plat->mode & SPI_RX_DUAL)
+ val |= SPI_PFL_MODE_MDRDSZ_MASK;
+ if (plat->mode & SPI_TX_DUAL)
+ val |= SPI_PFL_MODE_MDWRSZ_MASK;
+ }
+
if (plat->mode & SPI_3WIRE)
val |= SPI_PFL_MODE_3WIRE_MASK;
writel(val, priv->regs + SPI_PFL_MODE_REG(plat->cs));
--
2.37.3
[PATCH v2 7/9] spi: bcm63xx-hsspi: Add prepend mode support
Due to the controller limitation to keep the chip select low during the
bus idle time between the transfer, a dummy cs workaround was used when
this driver was first upstreamed to the u-boot based on linux kernel
driver. It basically picks the dummy cs as !actual_cs so typically dummy
cs is 1 when most of the case only cs 0 is used in the board design.
Then invert the polarity of both cs and tell the controller to start the
transfers using dummy cs. Assuming both cs are active low before the
inversion, effectively this keeps dummy cs high and actual cs low during
the transfer and workaround the issue.
This workaround requires that dummy cs 1 pin to is set to SPI chip
selection function in the pinmux when the transfer clock is above 25MHz.
The old chips likely have default pinmux set to chip select on the dummy
cs pin so it works but this is not case for the new Broadband BCA chips
and this workaround stop working. This is specifically an issue to
support SPI NAND and SPI NOR flash because these flash devices can
typically run at or above 100MHz.
This patch utilizes the prepend feature of the controller to combine the
multiple transfers in the same message to a single transfer when
possible. This way there is no need to keep clock low between transfers
and solve the issue without any pinmux requirement.
Multiple transfers within a SPI message may be combined into one
transfer if the following are all true:
* One or more half duplex write transfer in single bit mode
* Optional full duplex read/write at the end
* No delay and cs_change between transfers
Most of the SPI device meets this requirements such as SPI NOR, SPI NAND
flash, Broadcom SPI voice card and etc. So this change switches to the
prepend mode as the default mode. For any SPI message that does not meet
the above requirement, we switch to original dummy cs mode but limit the
clock rate to the safe 25MHz.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230209200246.141520-12-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 259 +---
1 file changed, 242 insertions(+), 17 deletions(-)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 0d12c345b1dd..a24bb430cbb4 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -20,7 +20,13 @@
#define HSSPI_PP 0
-#define SPI_MAX_SYNC_CLOCK 3000
+/*
+ * The maximum frequency for SPI synchronous mode is 30MHz for some chips and
+ * 25MHz for some others. This depends on the chip layout and SPI signals
+ * distance to the pad. We use the lower of these values to cover all relevant
+ * chips.
+ */
+#define SPI_MAX_SYNC_CLOCK 2500
/* SPI Control register */
#define SPI_CTL_REG0x000
@@ -72,12 +78,16 @@
#define SPI_PFL_MODE_REG(x)(0x100 + (0x20 * (x)) + 0x08)
#define SPI_PFL_MODE_FILL_SHIFT0
#define SPI_PFL_MODE_FILL_MASK (0xff << SPI_PFL_MODE_FILL_SHIFT)
+#define SPI_PFL_MODE_MDRDST_SHIFT 8
+#define SPI_PFL_MODE_MDWRST_SHIFT 12
#define SPI_PFL_MODE_MDRDSZ_SHIFT 16
#define SPI_PFL_MODE_MDRDSZ_MASK (1 << SPI_PFL_MODE_MDRDSZ_SHIFT)
#define SPI_PFL_MODE_MDWRSZ_SHIFT 18
#define SPI_PFL_MODE_MDWRSZ_MASK (1 << SPI_PFL_MODE_MDWRSZ_SHIFT)
#define SPI_PFL_MODE_3WIRE_SHIFT 20
#define SPI_PFL_MODE_3WIRE_MASK(1 << SPI_PFL_MODE_3WIRE_SHIFT)
+#define SPI_PFL_MODE_PREPCNT_SHIFT 24
+#define SPI_PFL_MODE_PREPCNT_MASK (4 << SPI_PFL_MODE_PREPCNT_SHIFT)
/* SPI Ping-Pong FIFO registers */
#define HSSPI_FIFO_SIZE0x200
@@ -96,12 +106,21 @@
#define HSSPI_FIFO_OP_CODE_W (2 << HSSPI_FIFO_OP_CODE_SHIFT)
#define HSSPI_FIFO_OP_CODE_R (3 << HSSPI_FIFO_OP_CODE_SHIFT)
+#define HSSPI_MAX_DATA_SIZE(HSSPI_FIFO_SIZE -
HSSPI_FIFO_OP_SIZE)
+#define HSSPI_MAX_PREPEND_SIZE 15
+
+#define HSSPI_XFER_MODE_PREPEND0
+#define HSSPI_XFER_MODE_DUMMYCS1
+
struct bcm63xx_hsspi_priv {
void __iomem *regs;
ulong clk_rate;
uint8_t num_cs;
uint8_t cs_pols;
uint speed;
+ uint xfer_mode;
+ uint32_t prepend_cnt;
+ uint8_t prepend_buf[HSSPI_MAX_PREPEND_SIZE];
};
static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
@@ -143,9 +162,16 @@ static void bcm63xx_hsspi_activate_cs(struct
bcm63xx_hsspi_priv *priv,
struct dm_spi_slave_plat *plat)
{
uint32_t clr, set;
+ uint speed = priv->speed;
+
+ if (priv->xfer_mode == HSSPI_XFER_MODE_DUMMYCS &&
+ speed > SPI_MAX_SYNC_CLOCK) {
+ speed = SPI_MAX_SYNC_CLOCK;
+ debug("Force to dummy cs mode. Reduce the speed to %dHz\n",
speed);
+ }
/* profile clock */
- set =
[PATCH v2 9/9] MAINTAINERS: Add Broadcom Broadband SoC HS SPI drivers
Add entry for Broadcom Broadband SoC HS SPI drivers Signed-off-by: William Zhang --- Changes in v2: - Add Álvaro Fernández Rojas as another maintainer MAINTAINERS | 9 + 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4c17c6cb9f1e..a1d490e66ed4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -823,6 +823,15 @@ F: include/bootstd.h F: net/eth_bootdevice.c F: test/boot/ +BROADCOM Broadband SoC High Speed SPI Controller DRIVER +M: William Zhang +M: Kursad Oney +M: Álvaro Fernández Rojas +S: Maintained +F: doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml +F: drivers/spi/bcm63xx_hsspi.c +F: drivers/spi/bcmbca_hsspi.c + BTRFS M: Marek Behún R: Qu Wenruo -- 2.37.3
[PATCH v2 5/9] spi: bcm63xx-hsspi: Add new compatible string support
New compatible string brcm,bcmbca-hsspi-v1.0 is introduced based on
dts document brcm,bcm63xx-hsspi.yaml. Add it to the driver to support
this new binding.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-6-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
drivers/spi/bcm63xx_hsspi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index 4d714adc4afd..495feba02262 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -310,6 +310,7 @@ static const struct dm_spi_ops bcm63xx_hsspi_ops = {
static const struct udevice_id bcm63xx_hsspi_ids[] = {
{ .compatible = "brcm,bcm6328-hsspi", },
+ { .compatible = "brcm,bcmbca-hsspi-v1.0", },
{ /* sentinel */ }
};
--
2.37.3
[PATCH v2 4/9] spi: bcm63xx-hsspi: Enable SPI drivers by default
SPI controller is always presented in BCMBCA platform SoCs so enable the controller driver and SPI core by default. Signed-off-by: William Zhang --- Changes in v2: None arch/arm/Kconfig | 2 ++ arch/arm/mach-bcmbca/Kconfig | 11 +++ drivers/spi/Kconfig | 4 ++-- 3 files changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f0118e225419..4aa91282f649 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -650,6 +650,8 @@ config ARCH_BCMSTB config ARCH_BCMBCA bool "Broadcom broadband chip family" select DM + select DM_SPI + select SPI select OF_CONTROL imply CMD_DM diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig index 62b371612b6a..6441ed5929d2 100644 --- a/arch/arm/mach-bcmbca/Kconfig +++ b/arch/arm/mach-bcmbca/Kconfig @@ -11,6 +11,7 @@ config BCM47622 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM4908 bool "Support for Broadcom 4908 Family" @@ -18,6 +19,7 @@ config BCM4908 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM4912 bool "Support for Broadcom 4912 Family" @@ -33,6 +35,7 @@ config BCM63138 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63146 bool "Support for Broadcom 63146 Family" @@ -40,6 +43,7 @@ config BCM63146 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63148 bool "Support for Broadcom 63148 Family" @@ -47,6 +51,7 @@ config BCM63148 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM63158 bool "Support for Broadcom 63158 Family" @@ -54,6 +59,7 @@ config BCM63158 select SYS_ARCH_TIMER select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM63178 bool "Support for Broadcom 63178 Family" @@ -61,6 +67,7 @@ config BCM63178 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI config BCM6756 bool "Support for Broadcom 6756 Family" @@ -82,6 +89,7 @@ config BCM6846 select CPU_V7A select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI config BCM6855 bool "Support for Broadcom 6855 Family" @@ -99,6 +107,7 @@ config BCM6856 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6856 is a dual core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6856, BCM6836 and BCM4910. @@ -109,6 +118,7 @@ config BCM6858 select SYS_ARCH_TIMER select DM_SERIAL select BCM6345_SERIAL + select BCM63XX_HSSPI help Broadcom BCM6858 is a quad core Brahma-B53 ARMv8 based xPON Gateway SoC. This SoC family includes BCM6858, BCM49508, BCM5504X and BCM6545. @@ -119,6 +129,7 @@ config BCM6878 select CPU_V7A select DM_SERIAL select PL01X_SERIAL + select BCM63XX_HSSPI source "arch/arm/mach-bcmbca/bcm47622/Kconfig" source "arch/arm/mach-bcmbca/bcm4908/Kconfig" diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd26819..47a261f1e1b8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -101,9 +101,9 @@ config ATMEL_SPI config BCM63XX_HSSPI bool "BCM63XX HSSPI driver" - depends on (ARCH_BMIPS || BCM6856 || BCM6858 || BCM63158) + depends on (ARCH_BMIPS || ARCH_BCMBCA) help - Enable the BCM6328 HSSPI driver. This driver can be used to + Enable the BCM63XX HSSPI driver. This driver can be used to access the SPI NOR flash on platforms embedding this Broadcom SPI core. -- 2.37.3
[PATCH v2 1/9] dt-bindings: spi: Add bcm63xx-hsspi controller support
Bring the device tree binding document from Linux to u-boot
Port from linux patches:
Link:
https://lore.kernel.org/r/20230207065826.285013-2-william.zh...@broadcom.com
Link:
https://lore.kernel.org/r/20230207065826.285013-3-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
.../spi/brcm,bcm63xx-hsspi.yaml | 134 ++
1 file changed, 134 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
diff --git a/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
new file mode 100644
index ..6554978583f8
--- /dev/null
+++ b/doc/device-tree-bindings/spi/brcm,bcm63xx-hsspi.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Broadband SoC High Speed SPI controller
+
+maintainers:
+ - William Zhang
+ - Kursad Oney
+ - Jonas Gorski
+
+description: |
+ Broadcom Broadband SoC supports High Speed SPI master controller since the
+ early MIPS based chips such as BCM6328 and BCM63268. This initial rev 1.0
+ controller was carried over to recent ARM based chips, such as BCM63138,
+ BCM4908 and BCM6858. The old MIPS based chip should continue to use the
+ brcm,bcm6328-hsspi compatible string. The recent ARM based chip is required
to
+ use the brcm,bcmbca-hsspi-v1.0 as part of its compatible string list as
+ defined below to match the specific chip along with ip revision info.
+
+ This rev 1.0 controller has a limitation that can not keep the chip select
line
+ active between the SPI transfers within the same SPI message. This can
+ terminate the transaction to some SPI devices prematurely. The issue can be
+ worked around by either the controller's prepend mode or using the dummy chip
+ select workaround. Driver automatically picks the suitable mode based on
+ transfer type so it is transparent to the user.
+
+ The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI
+ controller rev 1.1 that add the capability to allow the driver to control
chip
+ select explicitly. This solves the issue in the old controller.
+
+properties:
+ compatible:
+oneOf:
+ - const: brcm,bcm6328-hsspi
+ - items:
+ - enum:
+ - brcm,bcm47622-hsspi
+ - brcm,bcm4908-hsspi
+ - brcm,bcm63138-hsspi
+ - brcm,bcm63146-hsspi
+ - brcm,bcm63148-hsspi
+ - brcm,bcm63158-hsspi
+ - brcm,bcm63178-hsspi
+ - brcm,bcm6846-hsspi
+ - brcm,bcm6856-hsspi
+ - brcm,bcm6858-hsspi
+ - brcm,bcm6878-hsspi
+ - const: brcm,bcmbca-hsspi-v1.0
+ - items:
+ - enum:
+ - brcm,bcm4912-hsspi
+ - brcm,bcm6756-hsspi
+ - brcm,bcm6813-hsspi
+ - brcm,bcm6855-hsspi
+ - const: brcm,bcmbca-hsspi-v1.1
+
+ reg:
+items:
+ - description: main registers
+ - description: miscellaneous control registers
+minItems: 1
+
+ reg-names:
+items:
+ - const: hsspi
+ - const: spim-ctrl
+minItems: 1
+
+ clocks:
+items:
+ - description: SPI master reference clock
+ - description: SPI master pll clock
+
+ clock-names:
+items:
+ - const: hsspi
+ - const: pll
+
+ interrupts:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+allOf:
+ - $ref: spi-controller.yaml#
+ - if:
+ properties:
+compatible:
+ contains:
+enum:
+ - brcm,bcm6328-hsspi
+ - brcm,bcmbca-hsspi-v1.0
+then:
+ properties:
+reg:
+ maxItems: 1
+reg-names:
+ maxItems: 1
+else:
+ properties:
+reg:
+ minItems: 2
+ maxItems: 2
+reg-names:
+ minItems: 2
+ maxItems: 2
+ required:
+- reg-names
+
+unevaluatedProperties: false
+
+examples:
+ - |
+#include
+spi@ff801000 {
+compatible = "brcm,bcm6756-hsspi", "brcm,bcmbca-hsspi-v1.1";
+reg = <0xff801000 0x1000>,
+ <0xff802610 0x4>;
+reg-names = "hsspi", "spim-ctrl";
+interrupts = ;
+clocks = <>, <_pll>;
+clock-names = "hsspi", "pll";
+num-cs = <8>;
+#address-cells = <1>;
+#size-cells = <0>;
+};
--
2.37.3
[PATCH v2 3/9] arm64: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv8 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-5-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
arch/arm/dts/bcm4908.dtsi | 17 +
arch/arm/dts/bcm4912.dtsi | 20
arch/arm/dts/bcm63146.dtsi | 19 +++
arch/arm/dts/bcm63158.dtsi | 15 ++-
arch/arm/dts/bcm6813.dtsi | 20
arch/arm/dts/bcm6856.dtsi | 23 ++-
arch/arm/dts/bcm6858.dtsi | 23 ++-
arch/arm/dts/bcm94908.dts | 4
arch/arm/dts/bcm94912.dts | 4
arch/arm/dts/bcm963146.dts | 4
arch/arm/dts/bcm963158.dts | 4
arch/arm/dts/bcm96813.dts | 4
arch/arm/dts/bcm96856.dts | 4
arch/arm/dts/bcm96858.dts | 4
14 files changed, 130 insertions(+), 35 deletions(-)
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
index 0be5cfeeffa9..fc9874623b18 100644
--- a/arch/arm/dts/bcm4908.dtsi
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -106,6 +106,12 @@
clock-frequency = <5000>;
clock-output-names = "periph";
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
bus@ff80 {
@@ -123,5 +129,16 @@
status = "disabled";
};
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4908-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <_pll _pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm4912.dtsi b/arch/arm/dts/bcm4912.dtsi
index 3d016c2ce675..b10a0ae06187 100644
--- a/arch/arm/dts/bcm4912.dtsi
+++ b/arch/arm/dts/bcm4912.dtsi
@@ -78,6 +78,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -85,6 +86,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -116,6 +123,19 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm4912-hsspi",
"brcm,bcmbca-hsspi-v1.1";
+ reg = <0x1000 0x600>, <0x2610 0x4>;
+ reg-names = "hsspi", "spim-ctrl";
+ interrupts = ;
+ clocks = <_pll _pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63146.dtsi b/arch/arm/dts/bcm63146.dtsi
index 04de96bd0a03..48226cf1a7d4 100644
--- a/arch/arm/dts/bcm63146.dtsi
+++ b/arch/arm/dts/bcm63146.dtsi
@@ -59,6 +59,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
};
+
uart_clk: uart-clk {
compatible = "fixed-factor-clock";
#clock-cells = <0>;
@@ -66,6 +67,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -98,6 +105,18 @@
#size-cells = <1>;
ranges = <0x0 0x0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63146-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <_pll _pll>;
+
[PATCH v2 2/9] ARM: dts: broadcom: bcmbca: Add spi controller node
Add support for HSSPI controller in ARMv7 chip dts files.
Port from linux patch:
Link:
https://lore.kernel.org/r/20230207065826.285013-4-william.zh...@broadcom.com
Signed-off-by: William Zhang
---
Changes in v2: None
arch/arm/dts/bcm47622.dtsi | 18 ++
arch/arm/dts/bcm63138.dtsi | 18 ++
arch/arm/dts/bcm63148.dtsi | 18 ++
arch/arm/dts/bcm63178.dtsi | 19 +++
arch/arm/dts/bcm6756.dtsi | 19 +++
arch/arm/dts/bcm6846.dtsi | 18 ++
arch/arm/dts/bcm6855.dtsi | 27 +++
arch/arm/dts/bcm6878.dtsi | 19 +++
arch/arm/dts/bcm947622.dts | 4
arch/arm/dts/bcm963138.dts | 4
arch/arm/dts/bcm963148.dts | 4
arch/arm/dts/bcm963178.dts | 4
arch/arm/dts/bcm96756.dts | 4
arch/arm/dts/bcm96846.dts | 4
arch/arm/dts/bcm96855.dts | 4
arch/arm/dts/bcm96878.dts | 4
16 files changed, 180 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/bcm47622.dtsi b/arch/arm/dts/bcm47622.dtsi
index c016e12b7372..86b1dff65aca 100644
--- a/arch/arm/dts/bcm47622.dtsi
+++ b/arch/arm/dts/bcm47622.dtsi
@@ -83,6 +83,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2>;
+ };
};
psci {
@@ -114,6 +120,18 @@
#size-cells = <1>;
ranges = <0 0xff80 0x80>;
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm47622-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <_pll _pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x12000 0x1000>;
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
index 42b442aec9f4..2a673c39ba68 100644
--- a/arch/arm/dts/bcm63138.dtsi
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -60,6 +60,12 @@
clock-div = <4>;
clock-mult = <1>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
/* ARM bus */
@@ -145,5 +151,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63138-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <_pll _pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm63148.dtsi b/arch/arm/dts/bcm63148.dtsi
index df5307b6b3af..d9aed2bd7ff0 100644
--- a/arch/arm/dts/bcm63148.dtsi
+++ b/arch/arm/dts/bcm63148.dtsi
@@ -59,6 +59,12 @@
#clock-cells = <0>;
clock-frequency = <5000>;
};
+
+ hsspi_pll: hsspi-pll {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <4>;
+ };
};
psci {
@@ -99,5 +105,17 @@
clock-names = "refclk";
status = "disabled";
};
+
+ hsspi: spi@1000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "brcm,bcm63148-hsspi",
"brcm,bcmbca-hsspi-v1.0";
+ reg = <0x1000 0x600>;
+ interrupts = ;
+ clocks = <_pll _pll>;
+ clock-names = "hsspi", "pll";
+ num-cs = <8>;
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm/dts/bcm63178.dtsi b/arch/arm/dts/bcm63178.dtsi
index cbd094dde6d0..4c94d62e1a21 100644
--- a/arch/arm/dts/bcm63178.dtsi
+++ b/arch/arm/dts/bcm63178.dtsi
@@ -70,6 +70,7 @@
#clock-cells = <0>;
clock-frequency = <2>;
Re: [PATCH v3] console: usb: kbd: Limit poll frequency to improve performance
Hi Simon, Michal, Marek,
On 4/26/23 03:04, Simon Glass wrote:
Hi Filip,
On Tue, 25 Apr 2023 at 06:36, Filip Žaludek wrote:
Hi Simon,
On 4/19/23 03:49, Simon Glass wrote:
Hi Filip,
On Tue, 11 Apr 2023 at 14:24, Filip Žaludek wrote:
On 2/8/23 20:01, Mark Kettenis wrote:
Date: Wed, 8 Feb 2023 19:45:36 +0100
From: Michal Suchánek
Hello,
On Wed, Jan 18, 2023 at 05:01:12PM +0100, Filip Žaludek wrote:
Hi Michal,
thanks for testing! Do you consider keyboard as working once it is detected
without
'usb_kbd usb_kbd: Timeout poll on interrupt endpoint', or judging from
subsequent
typing? Note that issue is reproducible only in about 20% of reboots.
I rely on keyboard input to boot so if it was 20% broken I would notice.
I don't use the rPi all that much so if it was broken only a few
% of the time there is a chance I would miss it.
However, for me not typing on the keyboard during usb detection it is
100% not detected, typing on it during usb detection it is 100%
detected.
The timeout is limitation of the dwc2 controller handling of usb hubs.
There might be a possibility to improve the driver so that it handles
the condition but it might be that the Linux driver relies on a separate
thread handling the controller which is not acceptable for u-boot.
I am not usb expert and definitely not dwc2 expert so I cannot do more
than workaround the current driver limitation.
For me I can always enter 'U-Boot>' shell, but then keyboard usually does not
work.
And yes, resetting the usb controller with pressing a key afterwards will
finally break the keyboard. ('usb reset' typed from keyboard)
If you are Prague located I am ready to demonstrate what I am talking about.
Simon's keyboard detection is somewhat interfered by 'SanDisk USB Extreme
Pro' detection,
printed complaints but keyboard still works..
'usb_kbd usb_kbd: Timeout poll on interrupt endpoint' and 'Failed to get
keyboard state from device 0c40:8000'
Btw. why from 0c40:8000 (ELMCU 2.4GHz receiver) when wired keyboard is
046d:c31c (Logitech Keyboard K120)?
What is supposed scenario for RPi3/u-boot/grub usb keyboard equipped users
wanting to boot non-default?
Enter 'U-Boot>' shell to detect keyboard; type boot; select desired grub
entry..?
Reverting either from the two makes it non issue for me:
'dwc2: use the nonblock argument in submit_int_msg'
commit 9dcab2c4d2cb50ab1864c818b82a72393c160236
Without this booting from USB is not feasible because reading every
block from the USB drive waits for the keyboard to time out.
'console: usb: kbd: Limit poll frequency to improve performance'
commit 96991e652f541323a03c5b7e075d54a117091618
No idea about this one, for me it doea not give any substantial
difference in behavior.
Reverting that commit leads to a significant slowdown loading a kernel
from disk with a usb keyboard connected. The slowdown is somewhat
hardware dependent but on some systems loading the OpenBSD/arm64
kernel would take minutes instead of seconds.
More updates to usb keyboard/RPi3/dwc2 controller issue:
I was following my former observation about printing characters from semi
random places [usb.c, usb_hub.c, device.c, usb-uclass.c, dwc2.c] what
works as workaround. I realized this is only when printing to vidconsole,
not to serial. After disabling video_sync() and/or flush_dcache_range()
from corresponding vidconsole print functions, printing is no longer
workaround. This behavior seem to be due to cache coherency.
Do you have any objections against elephant in porcelain proposal?
Not able to narrow it down more to single source code line.
With this keyboard works for me even when touching it only during 15s grub
timeout.
It is not for sure that cache coherency problem is from dwc2, but afaik there
are no other complaints to usb keyboard.
Performance degradation not observed..
%< -
diff --git a/drivers/usb/host/dwc2.c b/drivers/usb/host/dwc2.c
index 23060fc369..f95314ff1b 100644
--- a/drivers/usb/host/dwc2.c
+++ b/drivers/usb/host/dwc2.c
@@ -814,6 +814,7 @@ static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv,
struct usb_device *dev,
else
stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
+ flush_dcache_all();
mdelay(1);
return stat;
%< -
Hello,
I am about to dig more into this issue with proper tools, but failed to
configure/compile trace functionality on RPi3 due to missing references
to timer_early_get_count() and timer_early_get_rate().
You could implement a proper timer driver for rpi.
Is it possible/feasible to implement calls in CONFIG_SYS_ARCH_TIMER
and/or CONFIG_SP804_TIMER?
Yes
I am little bit missing here secret sauce, timer_early_get_count() and
timer_early_get_rate()
are not supposed to be implemented in arch/arm/cpu/armv8/generic_timer.c? But
Re: [PATCH next] rockchip: rk3588: insert u-boot, spl-boot-device into U-Boot device tree
Hi Quentin,
On 2023-05-02 18:23, Quentin Schulz wrote:
> From: Quentin Schulz
>
> It is possible to boot U-Boot proper from a different storage medium
> than the one used by the BOOTROM to load the SPL. This information is
> stored in the u-boot,spl-boot-device Device Tree property and is
> accessible from U-Boot proper so that it has knowledge at runtime where
> it was loaded from.
>
> Let's add support for this feature for rk3588 the same way it was done
> for px30 and rk3399.
Why does this need to be soc specific, why can it not be added to spl.c
or spl-boot-order.c?
The soc specific boot_devices already have BROM_BOOTSOURCE to ofpath
defined. With a BOOT_DEVICE > BROM_BOOTSOURCE > ofpath translation
helper this could be made more generic to work for all rk socs.
Regards,
Jonas
>
> Cc: Quentin Schulz
> Signed-off-by: Quentin Schulz
> ---
> arch/arm/mach-rockchip/rk3588/rk3588.c | 50
> ++
> 1 file changed, 50 insertions(+)
>
> diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
> b/arch/arm/mach-rockchip/rk3588/rk3588.c
> index 18e67b5ca9b..694177e3976 100644
> --- a/arch/arm/mach-rockchip/rk3588/rk3588.c
> +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
> @@ -162,3 +162,53 @@ int arch_cpu_init(void)
> return 0;
> }
> #endif
> +
> +#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
> +const char *spl_decode_boot_device(u32 boot_device)
> +{
> + int i;
> + static const struct {
> + u32 boot_device;
> + const char *ofpath;
> + } spl_boot_devices_tbl[] = {
> + { BOOT_DEVICE_MMC2, "/mmc@fe2e" },
> + { BOOT_DEVICE_MMC1, "/mmc@fe2c" },
> + { BOOT_DEVICE_SPI, "/spi@fe2b/flash@0" },
> + };
> +
> + for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
> + if (spl_boot_devices_tbl[i].boot_device == boot_device)
> + return spl_boot_devices_tbl[i].ofpath;
> +
> + return NULL;
> +}
> +
> +void spl_perform_fixups(struct spl_image_info *spl_image)
> +{
> + void *blob = spl_image->fdt_addr;
> + const char *boot_ofpath;
> + int chosen;
> +
> + /*
> + * Inject the ofpath of the device the full U-Boot (or Linux in
> + * Falcon-mode) was booted from into the FDT, if a FDT has been
> + * loaded at the same time.
> + */
> + if (!blob)
> + return;
> +
> + boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
> + if (!boot_ofpath) {
> + pr_err("%s: could not map boot_device to ofpath\n", __func__);
> + return;
> + }
> +
> + chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
> + if (chosen < 0) {
> + pr_err("%s: could not find/create '/chosen'\n", __func__);
> + return;
> + }
> + fdt_setprop_string(blob, chosen,
> +"u-boot,spl-boot-device", boot_ofpath);
> +}
> +#endif
>
> ---
> base-commit: 6735ab59e6fd71ced1c58d8dfb3dd6baf3690d16
> change-id: 20230502-rk3588-spl-boot-dev-efa2777cc21b
>
> Best regards,
> --
> Quentin Schulz
[PATCH v2 u-boot] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port
Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
PCIe Root Port does not have any PCIe memory, so returns zero when trying
to read from PCIe Root Port BAR0 and ignore any writes.
Signed-off-by: Pali Rohár
---
drivers/pci/pcie_fsl.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
index 4600652f2b1b..8d89a1e5919c 100644
--- a/drivers/pci/pcie_fsl.c
+++ b/drivers/pci/pcie_fsl.c
@@ -58,6 +58,14 @@ static int fsl_pcie_read_config(const struct udevice *bus,
pci_dev_t bdf,
return 0;
}
+ /* Skip Freescale PCIe controller's PEXCSRBAR register */
+ if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+ PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) == PCI_BASE_ADDRESS_0) {
+ *valuep = 0;
+ return 0;
+ }
+
val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf),
offset);
@@ -95,6 +103,12 @@ static int fsl_pcie_write_config(struct udevice *bus,
pci_dev_t bdf,
if (fsl_pcie_addr_valid(pcie, bdf))
return 0;
+ /* Skip Freescale PCIe controller's PEXCSRBAR register */
+ if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
+ PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) == PCI_BASE_ADDRESS_0)
+ return 0;
+
val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
PCI_DEV(bdf), PCI_FUNC(bdf),
offset);
--
2.20.1
[PATCH] board: gateworks: venice: add eraseenv command
Add eraseenv command and remove the unnecessary env command. Signed-off-by: Tim Harvey --- board/gateworks/venice/venice.env | 1 - configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 4 files changed, 3 insertions(+), 1 deletion(-) diff --git a/board/gateworks/venice/venice.env b/board/gateworks/venice/venice.env index f81804ca12c1..2054c029a3e9 100644 --- a/board/gateworks/venice/venice.env +++ b/board/gateworks/venice/venice.env @@ -31,4 +31,3 @@ update_rootfs=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize 10 100 update_all=tftpboot $loadaddr $image && gzwrite mmc $dev $loadaddr $filesize -erase_env=mmc dev $dev; mmc erase 0x7f08 0x40 diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index a55e0cd76b54..ad5b7616f30a 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -50,6 +50,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x1000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 4709ecace65c..0742fa759b08 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x1000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 6b6a15588cd4..ae0c0120d107 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -53,6 +53,7 @@ CONFIG_SYS_PBSIZE=2074 CONFIG_SYS_BOOTM_LEN=0x1000 # CONFIG_CMD_EXPORTENV is not set # CONFIG_CMD_IMPORTENV is not set +CONFIG_CMD_ERASEENV=y CONFIG_CRC32_VERIFY=y CONFIG_CMD_MD5SUM=y CONFIG_MD5SUM_VERIFY=y -- 2.25.1
[PATCH] board: gateworks: venice: add GPIO name lookup
Add GPIO name lookup so that you can act on GPIO's by name vs controller id: Before: u-boot=> gpio input pci_wdis# GPIO: 'pci_wdis#' not found Command 'gpio' failed: Error -22 After: u-boot=> gpio input pci_wdis# gpio: pin pci_wdis# (gpio 103) value is 1 Signed-off-by: Tim Harvey --- configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + 3 files changed, 3 insertions(+) diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index db2da79ab109..a55e0cd76b54 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -88,6 +88,7 @@ CONFIG_CLK_COMPOSITE_CCF=y CONFIG_SPL_CLK_IMX8MM=y CONFIG_CLK_IMX8MM=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index e9cb26495075..4709ecace65c 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -89,6 +89,7 @@ CONFIG_SPL_DM=y CONFIG_SPL_CLK_IMX8MN=y CONFIG_CLK_IMX8MN=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 4d0432078d56..6b6a15588cd4 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -86,6 +86,7 @@ CONFIG_SPL_DM=y CONFIG_CLK_COMPOSITE_CCF=y CONFIG_CLK_IMX8MP=y CONFIG_GPIO_HOG=y +CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_MXC_GPIO=y CONFIG_DM_I2C=y CONFIG_LED=y -- 2.25.1
SHA verification fails on signed images
Hi there, I have a FIT image that boots fine, but when I sign it, with the following command, it fails to boot: mkimage -k keys -r -o sha256,rsa2048 -F image.fit It fails while checking sha256, Bad hash value for 'hash' hash node in ... I get similar error when I test it on my host: tools/fit_check_sign -f image.fit -k u-boot-spl.dtb After debugging, I found that after signing the image, data gets imbedded into images structure with data = <...> field, but data-offset, data-size fields (used for external reference) are not removed, and that's why when verifying the signatures fit_image_get_data_and_size() function gets confused when finds data-offset settings and calculates sha256 on the wrong data. I checked my other projects, with older version of uboot, and I can confirm that there after signing a FIT image data-offset, data-size fields got removed and data field appeared with data. I am experiencing the issue with the recent head of the mater branch of u-boot. Did I miss something or is it a bug? Cheers, Andy
Re: [PATCH v2 2/3] X86: Add support for distro boot
Hi, On Tue, 2 May 2023 at 09:41, Heinrich Schuchardt wrote: > > > > Am 2. Mai 2023 17:21:29 MESZ schrieb thomas.mittelsta...@de.bosch.com: > >From: Thomas Mittelstaedt > > > >Enable distro boot feature for U-Boot at VirtualBox described at > >https://source.denx.de/u-boot/u-boot/-/blob/master/doc/develop/distro.rst > > > >Signed-off-by: Thomas Mittelstaedt > >--- > > configs/efi-x86_payload64_defconfig | 12 +--- > > include/configs/efi-x86_payload.h | 11 +++ > > 2 files changed, 12 insertions(+), 11 deletions(-) > > > >diff --git a/configs/efi-x86_payload64_defconfig > >b/configs/efi-x86_payload64_defconfig > >index 30a7f31dac..a4cfe95890 100644 > >--- a/configs/efi-x86_payload64_defconfig > >+++ b/configs/efi-x86_payload64_defconfig > >@@ -8,33 +8,23 @@ CONFIG_TARGET_EFI_PAYLOAD=y > > CONFIG_FIT=y > > CONFIG_FIT_SIGNATURE=y > > CONFIG_LEGACY_IMAGE_FORMAT=y > >+CONFIG_DISTRO_DEFAULTS=y > > CONFIG_SHOW_BOOT_PROGRESS=y > > CONFIG_USE_BOOTARGS=y > > CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > >-CONFIG_USE_BOOTCOMMAND=y > > CONFIG_PRE_CONSOLE_BUFFER=y > > CONFIG_SYS_CONSOLE_INFO_QUIET=y > > CONFIG_DISPLAY_BOARDINFO_LATE=y > > CONFIG_LAST_STAGE_INIT=y > >-CONFIG_HUSH_PARSER=y > > CONFIG_SYS_PBSIZE=532 > > CONFIG_CMD_IDE=y > > CONFIG_CMD_MMC=y > >-CONFIG_CMD_PART=y > > CONFIG_CMD_USB=y > >-CONFIG_CMD_DHCP=y > > CONFIG_BOOTP_BOOTFILESIZE=y > > # CONFIG_CMD_NFS is not set > >-CONFIG_CMD_PING=y > > CONFIG_CMD_TIME=y > >-CONFIG_CMD_EXT2=y > >-CONFIG_CMD_EXT4=y > > CONFIG_CMD_EXT4_WRITE=y > >-CONFIG_CMD_FAT=y > >-CONFIG_CMD_FS_GENERIC=y > > CONFIG_MAC_PARTITION=y > >-CONFIG_ISO_PARTITION=y > >-CONFIG_EFI_PARTITION=y > > CONFIG_ENV_OVERWRITE=y > > CONFIG_ENV_IS_IN_FAT=y > > CONFIG_ENV_FAT_INTERFACE="scsi" > >diff --git a/include/configs/efi-x86_payload.h > >b/include/configs/efi-x86_payload.h > >index c72b067c36..e1cd8eb316 100644 > >--- a/include/configs/efi-x86_payload.h > >+++ b/include/configs/efi-x86_payload.h > >@@ -6,6 +6,17 @@ > > /* > > * board/config.h - configuration options, board specific > > */ > >+#ifndef CONFIG_SPL_BUILD > >+ > >+#define BOOT_TARGET_SCSI(func) \ > > Shouldn't NVMe be added here too? This is automatic if you use bootstd. > > Best regards > > Heinrich > > >+ func(SCSI, scsi, 0) > >+ > >+#define BOOT_TARGET_DEVICES(func) \ > >+ BOOT_TARGET_SCSI(func) > >+ > >+#include > >+ > >+#endif > > > > #ifndef __CONFIG_H > > #define __CONFIG_H Please can we use bootstd instead? You should just need to enable BOOTSTD_DEFAULTS and it will work. If not, please let me know. Please also see the various improvements in[1] available at [2]. There is also a new video driver [2]. Regards, Simon [1] https://patchwork.ozlabs.org/project/uboot/list/?series=351440 [2] https://source.denx.de/u-boot/custodians/u-boot-dm/-/tree/bryc-working [3] https://patchwork.ozlabs.org/project/uboot/list/?series=352929
Re: [PATCH 3/4] X86: Add support for distro boot
Hi, On Tue, 2 May 2023 at 04:19, Heinrich Schuchardt wrote: > > On 5/2/23 11:49, thomas.mittelsta...@bosch.com wrote: > > From: mtt2hi > > Patches without commit messages cannot be accepted. > > Best regards > > Heinrich > > > > > Signed-off-by: mtt2hi > > --- > > configs/efi-x86_payload64_defconfig | 2 +- > > include/configs/efi-x86_payload.h | 11 +++ > > 2 files changed, 12 insertions(+), 1 deletion(-) > > > > diff --git a/configs/efi-x86_payload64_defconfig > > b/configs/efi-x86_payload64_defconfig > > index 12b5e58374..e6047e5fb4 100644 > > --- a/configs/efi-x86_payload64_defconfig > > +++ b/configs/efi-x86_payload64_defconfig > > @@ -11,7 +11,6 @@ CONFIG_SHOW_BOOT_PROGRESS=y > > CONFIG_USE_BOOTARGS=y > > CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" > > CONFIG_USE_BOOTCOMMAND=y > > -CONFIG_BOOTCOMMAND="ext2load scsi 0:3 0100 /boot/vmlinuz; zboot > > 0100" > > CONFIG_PRE_CONSOLE_BUFFER=y > > CONFIG_SYS_CONSOLE_INFO_QUIET=y > > CONFIG_DISPLAY_BOARDINFO_LATE=y > > @@ -59,6 +58,7 @@ CONFIG_SYS_NS16550_PORT_MAPPED=y > > CONFIG_EFI=y > > CONFIG_EFI_STUB=y > > CONFIG_EFI_STUB_64BIT=y > > +CONFIG_DISTRO_DEFAULTS=y > > CONFIG_FAT_WRITE=y > > CONFIG_ENV_FAT_INTERFACE="scsi" > > CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" > > diff --git a/include/configs/efi-x86_payload.h > > b/include/configs/efi-x86_payload.h > > index c72b067c36..e1cd8eb316 100644 > > --- a/include/configs/efi-x86_payload.h > > +++ b/include/configs/efi-x86_payload.h > > @@ -6,6 +6,17 @@ > > /* > >* board/config.h - configuration options, board specific > >*/ > > +#ifndef CONFIG_SPL_BUILD > > + > > +#define BOOT_TARGET_SCSI(func) \ > > + func(SCSI, scsi, 0) > > + > > +#define BOOT_TARGET_DEVICES(func) \ > > + BOOT_TARGET_SCSI(func) > > + > > +#include > > + > > +#endif > > > > #ifndef __CONFIG_H > > #define __CONFIG_H > Can you use bootstd instead? Regards, Simon
Re: [PATCH 1/1] cli: avoid buffer overrun
On Mon, 1 May 2023 at 20:34, Heinrich Schuchardt wrote: > > Invoking the sandbox with > > /u-boot -c ⧵0xef⧵0xbf⧵0xbd > > results in a segmentation fault. > > Function b_getch() retrieves a character from the input stream. This > character may be > 0x7f. If type char is signed, static_get() will > return a negative number and in parse_stream() we will use that > negative number as an index for array map[] resulting in a buffer > overflow. > > Reported-by: Harry Lockyer > Signed-off-by: Heinrich Schuchardt > --- > common/cli_hush.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Simon Glass
Re: [PATCH 1/1] dm: core: fix introduce uclass_get_device_by_of_path
On Mon, 1 May 2023 at 20:59, Heinrich Schuchardt
wrote:
>
> Correct the function documentation.
>
> Fixes: ca031c082700 ("dm: core: introduce uclass_get_device_by_of_path()")
> Reported-by: Tom Rini
> Signed-off-by: Heinrich Schuchardt
> ---
> include/dm/uclass.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Simon Glass
Re: [PATCH 1/1] CI: treat documentation warnings as errors
On Mon, 1 May 2023 at 21:04, Heinrich Schuchardt wrote: > > We do not want to merge documentation that produces Sphinx warnings. > > scripts/kernel-doc uses environment variable KDOC_WERROR to determine > if warnings should be treated as errors. > > Reported-by: Tom Rini > Signed-off-by: Heinrich Schuchardt > --- > .azure-pipelines.yml | 2 +- > .gitlab-ci.yml | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Simon Glass
Re: [PATCH] doc: devicetree: fix u-boot.bin filename typo
On Tue, 2 May 2023 at 04:21, Baruch Siach wrote: > > Signed-off-by: Baruch Siach > --- > doc/develop/devicetree/control.rst | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Simon Glass
Re: [PATCH u-boot 3/3] pci: auto: Remove PCI_CLASS_PROCESSOR_POWERPC autoconfig case
On Thu, Apr 20, 2023 at 09:44:25PM +0200, Pali Rohár wrote: > PCI autoconfig case for PCI_CLASS_PROCESSOR_POWERPC just prints debug > message and then calls autoconfig setup code like for any other standard > endpoint device. We do not need special debug message for it, so remove > this case and handle PCI_CLASS_PROCESSOR_POWERPC via default code path. > > Signed-off-by: Pali Rohár > Reviewed-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH u-boot 1/3] pci: mpc85xx: Do not access PCI BARs registers of BDF address 00:00.0
On Thu, Apr 20, 2023 at 09:44:23PM +0200, Pali Rohár wrote: > At BDF address 00:00.0 is fictional device which PCI configuration header > is for configuring mpc85xx PCI controller itself. PCI config space of this > device has ATMU inbound registers on position of PCI BARs. Trying to do PCI > auto configuration of this device cause rewriting ATMU inbound registers. > To avoid it, do not allow overwriting registers at BARs positions. And > because this device does not have any PCI memory, return zeros when trying > to read PCI BARs config space registers. It signals to auto configuration > tool to not allocate any PCI memory for this device. > > This information is taken from MPC8544E Reference Manual, sections > 17.3.1.3, 17.3.1.1.1, 17.3.2 and 17.3.2.11. Available at NXP website: > https://www.nxp.com/docs/en/reference-manual/MPC8544ERM.pdf > > Signed-off-by: Pali Rohár > Reviewed-by: Heiko Schocher > Tested-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH u-boot 3/3] pci: mpc85xx: Do not try to access extended PCIe registers
On Thu, Apr 13, 2023 at 10:41:46PM +0200, Pali Rohár wrote: > Driver pci_mpc85xx.c is PCI controller driver for old PCI Local Bus, > which does not support access to extended PCIe registers (above 0xff), > as opposite of the PCIe driver pcie_fsl.c for the same platform. > > So do not try to access extended PCIe registers as it cannot work. > > Signed-off-by: Pali Rohár > Reviewed-by: Heiko Schocher > Tested-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH u-boot 2/3] pci: mpc85xx: Allow 8/16-bit access to PCI config space
On Thu, Apr 13, 2023 at 10:41:45PM +0200, Pali Rohár wrote: > This Freescale mpc85xx PCI controller should support 8-bit and 16-bit read > and write access to PCI config space as described in more Freescale > reference manuals. > > This change fixes issue that 8-bit and 16-bit write to PCI config space > caused to clear adjacent bits of 32-bit PCI register. > > Signed-off-by: Pali Rohár > Reviewed-by: Heiko Schocher > Tested-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH u-boot 1/3] pci: mpc85xx: Add missing sync() after writing to PCI config space
On Thu, Apr 13, 2023 at 10:41:44PM +0200, Pali Rohár wrote: > On PowerPC we should use barrier after store operation to HW register. > > Signed-off-by: Pali Rohár > Reviewed-by: Heiko Schocher > Tested-by: Heiko Schocher Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH] mpc83xx: Don't allow W and G bits in IBATs
On Fri, Jan 27, 2023 at 02:51:06PM +0100, Christophe Leroy wrote:
> The "Programming Environments Manual for 32-Bit Implementations of the
> PowerPC™ Architecture" says "W and G bits are not defined for IBAT
> registers. Attempting to write to these bits causes boundedly-undefined
> results"
>
> The "e300 Power Architecture™ Core Family Reference Manual" says the
> same: "Neither the W or G bits of the IBAT registers should be set.
> Attempting to write to these bits causes boundedly-undefined results."
>
> Remove the possibility to set those bytes.
>
> Fixes: 30915ab95d9 ("mpc83xx: Migrate BATS config to Kconfig")
> Signed-off-by: Christophe Leroy
> Cc: Mario Six
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Re: [PATCH u-boot 2/3] pci: fsl: Do not access PCI BAR0 register of PCIe Root Port
On Thu, Apr 20, 2023 at 09:44:24PM +0200, Pali Rohár wrote:
> Freescale PCIe Root Port has PEXCSRBAR register at position of PCI BAR0.
> PCIe Root Port does not have any PCIe memory, so returns zero when trying
> to read from PCIe Root Port BAR0 and ignore any writes.
>
> Signed-off-by: Pali Rohár
> Reviewed-by: Heiko Schocher
> ---
> drivers/pci/pcie_fsl.c | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c
> index 4600652f2b1b..06601840da85 100644
> --- a/drivers/pci/pcie_fsl.c
> +++ b/drivers/pci/pcie_fsl.c
> @@ -58,6 +58,14 @@ static int fsl_pcie_read_config(const struct udevice *bus,
> pci_dev_t bdf,
> return 0;
> }
>
> + /* Skip Freescale PCIe controller's PEXCSRBAR register */
> + if (PCI_BUS(bdf) - dev_seq(bus) == 0 &&
> + PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
> + (offset & ~3) == PCI_BASE_ADDRESS_0) {
> + *value = 0;
> + return 0;
> + }
> +
> val = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf) - dev_seq(bus),
> PCI_DEV(bdf), PCI_FUNC(bdf),
> offset);
There is no "value" in this function, only "val", which in turn is local
to the function, and *valuep which we are passed by the caller, please
re-work and send v2, thanks.
--
Tom
signature.asc
Description: PGP signature
[PATCH next] rockchip: rk3588: insert u-boot,spl-boot-device into U-Boot device tree
From: Quentin Schulz
It is possible to boot U-Boot proper from a different storage medium
than the one used by the BOOTROM to load the SPL. This information is
stored in the u-boot,spl-boot-device Device Tree property and is
accessible from U-Boot proper so that it has knowledge at runtime where
it was loaded from.
Let's add support for this feature for rk3588 the same way it was done
for px30 and rk3399.
Cc: Quentin Schulz
Signed-off-by: Quentin Schulz
---
arch/arm/mach-rockchip/rk3588/rk3588.c | 50 ++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/arm/mach-rockchip/rk3588/rk3588.c
index 18e67b5ca9b..694177e3976 100644
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -162,3 +162,53 @@ int arch_cpu_init(void)
return 0;
}
#endif
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+const char *spl_decode_boot_device(u32 boot_device)
+{
+ int i;
+ static const struct {
+ u32 boot_device;
+ const char *ofpath;
+ } spl_boot_devices_tbl[] = {
+ { BOOT_DEVICE_MMC2, "/mmc@fe2e" },
+ { BOOT_DEVICE_MMC1, "/mmc@fe2c" },
+ { BOOT_DEVICE_SPI, "/spi@fe2b/flash@0" },
+ };
+
+ for (i = 0; i < ARRAY_SIZE(spl_boot_devices_tbl); ++i)
+ if (spl_boot_devices_tbl[i].boot_device == boot_device)
+ return spl_boot_devices_tbl[i].ofpath;
+
+ return NULL;
+}
+
+void spl_perform_fixups(struct spl_image_info *spl_image)
+{
+ void *blob = spl_image->fdt_addr;
+ const char *boot_ofpath;
+ int chosen;
+
+ /*
+* Inject the ofpath of the device the full U-Boot (or Linux in
+* Falcon-mode) was booted from into the FDT, if a FDT has been
+* loaded at the same time.
+*/
+ if (!blob)
+ return;
+
+ boot_ofpath = spl_decode_boot_device(spl_image->boot_device);
+ if (!boot_ofpath) {
+ pr_err("%s: could not map boot_device to ofpath\n", __func__);
+ return;
+ }
+
+ chosen = fdt_find_or_add_subnode(blob, 0, "chosen");
+ if (chosen < 0) {
+ pr_err("%s: could not find/create '/chosen'\n", __func__);
+ return;
+ }
+ fdt_setprop_string(blob, chosen,
+ "u-boot,spl-boot-device", boot_ofpath);
+}
+#endif
---
base-commit: 6735ab59e6fd71ced1c58d8dfb3dd6baf3690d16
change-id: 20230502-rk3588-spl-boot-dev-efa2777cc21b
Best regards,
--
Quentin Schulz
[PATCH v2 4/4] common: spl: Add spl NVMe boot support
Add support to load the next stage image from an NVMe disk which may
be formatted as an EXT or FAT filesystem.
Signed-off-by: Mayuresh Chitale
---
arch/riscv/include/asm/spl.h | 1 +
common/spl/Kconfig | 10 +++
common/spl/Makefile | 1 +
common/spl/spl_nvme.c| 52
4 files changed, 64 insertions(+)
create mode 100644 common/spl/spl_nvme.c
diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h
index 2898a770ee..9c0bf9755c 100644
--- a/arch/riscv/include/asm/spl.h
+++ b/arch/riscv/include/asm/spl.h
@@ -20,6 +20,7 @@ enum {
BOOT_DEVICE_SPI,
BOOT_DEVICE_USB,
BOOT_DEVICE_SATA,
+ BOOT_DEVICE_NVME,
BOOT_DEVICE_I2C,
BOOT_DEVICE_BOARD,
BOOT_DEVICE_DFU,
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index a42774c76d..021c4997a7 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1283,6 +1283,16 @@ config SPL_NVME_BOOT_DEVICE
depends on SPL_NVME
default 0x0
+config SYS_NVME_EXT_BOOT_PARTITION
+ hex "NVMe ext boot partition number"
+ depends on SPL_NVME
+ default 0x2
+
+config SYS_NVME_FAT_BOOT_PARTITION
+ hex "NVMe boot partition number"
+ depends on SPL_NVME
+ default 0x1
+
config SPL_SERIAL
bool "Support serial"
select SPL_PRINTF
diff --git a/common/spl/Makefile b/common/spl/Makefile
index 13db3df993..4bcc3d7e68 100644
--- a/common/spl/Makefile
+++ b/common/spl/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o
obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o
obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o
obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o
+obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o
obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o
obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c
new file mode 100644
index 00..c99e0aefc7
--- /dev/null
+++ b/common/spl/spl_nvme.c
@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023
+ * Ventana Micro Systems Inc.
+ *
+ * Derived work from spl_sata.c
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int spl_nvme_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ int ret;
+ struct blk_desc *blk_desc;
+
+ ret = pci_init();
+ if (ret < 0)
+ goto out;
+
+ ret = nvme_scan_namespace();
+ if (ret < 0)
+ goto out;
+
+ blk_show_device(UCLASS_NVME, CONFIG_SPL_NVME_BOOT_DEVICE);
+ blk_desc = blk_get_devnum_by_uclass_id(UCLASS_NVME,
+ CONFIG_SPL_NVME_BOOT_DEVICE);
+ if (IS_ENABLED(CONFIG_SPL_FS_EXT4)) {
+ ret = spl_load_image_ext(spl_image, bootdev, blk_desc,
+CONFIG_SYS_NVME_EXT_BOOT_PARTITION,
+CONFIG_SPL_PAYLOAD);
+ if (!ret)
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_SPL_FS_FAT))
+ ret = spl_load_image_fat(spl_image, bootdev, blk_desc,
+CONFIG_SYS_NVME_FAT_BOOT_PARTITION,
+CONFIG_SPL_PAYLOAD);
+ else
+ ret = -ENOSYS;
+
+out:
+ return ret;
+}
+
+SPL_LOAD_IMAGE_METHOD("NVME", 0, BOOT_DEVICE_NVME, spl_nvme_load_image);
--
2.34.1
[PATCH v2 3/4] spl: Support loading a FIT from ext FS
Detect a FIT when loading from an ext File system and handle it using
the FIT SPL support.
Signed-off-by: Mayuresh Chitale
---
common/spl/spl_ext.c | 33 +
1 file changed, 33 insertions(+)
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index 2bf3434439..8593aed069 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -8,6 +8,26 @@
#include
#include
#include
+#include
+
+static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset,
+ ulong size, void *buf)
+{
+ loff_t filelen = (loff_t)load->priv, actlen;
+ char *filename = (char *)load->filename;
+ int ret;
+
+ ret = ext4fs_read(buf, file_offset, filelen, );
+ if (ret < 0) {
+ if (IS_ENABLED(CONFIG_SPL_LIBCOMMON_SUPPORT)) {
+ printf("%s: error reading image %s, err - %d\n",
+ __func__, filename, ret);
+ }
+ return ret;
+ }
+
+ return actlen;
+}
int spl_load_image_ext(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev,
@@ -47,6 +67,19 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
goto end;
}
+ if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
+ image_get_magic(header) == FDT_MAGIC) {
+ struct spl_load_info load;
+
+ debug("Found FIT\n");
+ load.read = spl_fit_read;
+ load.bl_len = 1;
+ load.filename = (void *)filename;
+ load.priv = (void *)filelen;
+
+ return spl_load_simple_fit(spl_image, , 0, header);
+ }
+
err = spl_parse_image_header(spl_image, bootdev, header);
if (err < 0) {
puts("spl: ext: failed to parse image header\n");
--
2.34.1
[PATCH v2 2/4] nvme: pci: Enable for SPL
Enable NVME and PCI NVMe drivers for SPL builds. Also enable PCI_PNP
for SPL which is required to auto configure the PCIe devices.
Signed-off-by: Mayuresh Chitale
---
drivers/Makefile | 1 +
drivers/nvme/Makefile| 2 +-
drivers/pci/Kconfig | 7 +++
drivers/pci/pci-uclass.c | 3 ++-
4 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/Makefile b/drivers/Makefile
index 58be410135..dc559ea7f7 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
+obj-$(CONFIG_$(SPL_)NVME) += nvme/
obj-$(CONFIG_XEN) += xen/
obj-$(CONFIG_$(SPL_)FPGA) += fpga/
obj-y += bus/
diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile
index fa7b619446..fd3e68a91d 100644
--- a/drivers/nvme/Makefile
+++ b/drivers/nvme/Makefile
@@ -4,4 +4,4 @@
obj-y += nvme-uclass.o nvme.o nvme_show.o
obj-$(CONFIG_NVME_APPLE) += nvme_apple.o
-obj-$(CONFIG_NVME_PCI) += nvme_pci.o
+obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..ecab6ddc7e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -40,6 +40,13 @@ config PCI_PNP
help
Enable PCI memory and I/O space resource allocation and assignment.
+config SPL_PCI_PNP
+ bool "Enable Plug & Play support for PCI"
+ default n
+ help
+ Enable PCI memory and I/O space resource allocation and assignment.
+ This is required to auto configure the enumerated devices.
+
config PCI_REGION_MULTI_ENTRY
bool "Enable Multiple entries of region type MEMORY in ranges for PCI"
help
diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c
index 9343cfc62a..dff63a68ce 100644
--- a/drivers/pci/pci-uclass.c
+++ b/drivers/pci/pci-uclass.c
@@ -1140,7 +1140,8 @@ static int pci_uclass_post_probe(struct udevice *bus)
if (ret)
return log_msg_ret("bind", ret);
- if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
+ if ((CONFIG_IS_ENABLED(PCI_PNP) || CONFIG_IS_ENABLED(SPL_PCI_PNP)) &&
+ ll_boot_init() &&
(!hose->skip_auto_config_until_reloc ||
(gd->flags & GD_FLG_RELOC))) {
ret = pci_auto_config_devices(bus);
--
2.34.1
[PATCH v2 1/4] spl: Add Kconfig options for NVME
Add kconfig options to enable NVME and PCI NVMe support in SPL Signed-off-by: Mayuresh Chitale Reviewed-by: Simon Glass --- common/spl/Kconfig | 20 1 file changed, 20 insertions(+) diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2c042ad306..a42774c76d 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1263,6 +1263,26 @@ config SPL_SATA_RAW_U_BOOT_SECTOR Sector on the SATA disk to load U-Boot from, when the SATA disk is being used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes). +config SPL_NVME + bool "NVM Express device support" + depends on BLK + select HAVE_BLOCK_DEVICE + help + This option enables support for NVM Express devices. + It supports basic functions of NVMe (read/write). + +config SPL_NVME_PCI + bool "NVM Express PCI device support for SPL" + depends on SPL_PCI && SPL_NVME + help + This option enables support for NVM Express PCI devices. + This allows use of NVMe devices for loading u-boot. + +config SPL_NVME_BOOT_DEVICE + hex "NVMe boot device number" + depends on SPL_NVME + default 0x0 + config SPL_SERIAL bool "Support serial" select SPL_PRINTF -- 2.34.1
[PATCH v2 0/4] SPL NVme support
This patchset adds support to load images of the SPL's next booting stage from a NVMe device. Changes in v2: - Rebase on v2023.07-rc1 - Use uclass ID for blk APIs - Add support to load FIT images from ext filesystem Mayuresh Chitale (4): spl: Add Kconfig options for NVME nvme: pci: Enable for SPL spl: Support loading a FIT from ext FS common: spl: Add spl NVMe boot support arch/riscv/include/asm/spl.h | 1 + common/spl/Kconfig | 30 + common/spl/Makefile | 1 + common/spl/spl_ext.c | 33 +++ common/spl/spl_nvme.c| 52 drivers/Makefile | 1 + drivers/nvme/Makefile| 2 +- drivers/pci/Kconfig | 7 + drivers/pci/pci-uclass.c | 3 ++- 9 files changed, 128 insertions(+), 2 deletions(-) create mode 100644 common/spl/spl_nvme.c -- 2.34.1
Re: [PATCH] usb: ehci-mx6: replace regulator_set_enable with *_if_allowed
On Mon, May 1, 2023 at 11:51 PM Eugen Hristev
wrote:
>
> regulator_set_enable_if_allowed already handles cases when the
> regulator is already enabled, or already disabled, and does not
> treat these as errors.
> With this change, the driver can work correctly even if the regulator
> is already taken or already disabled by another consumer.
>
> Signed-off-by: Eugen Hristev
> ---
> Hi Tim,
>
> I have not tested this as I do not have a mx6 board. can you please
> try it ?
>
> Thanks,
> Eugen
Eugen,
This does resolve the issue that occurs after your refcount series [1].
However after thinking about this more and seeing Marek's responses
this wasn't an issue of multiple consumers sharing the same regulator.
Instead this particular issue was that the vbus regulator is getting
enabled twice without being disabled. Adding a print in
regulator_set_enable shows me:
--- a/drivers/power/regulator/regulator-uclass.c
+++ b/drivers/power/regulator/regulator-uclass.c
@@ -165,6 +165,7 @@ int regulator_set_enable(struct udevice *dev, bool enable)
struct dm_regulator_uclass_plat *uc_pdata;
int ret, old_enable = 0;
+printf("%s %s %s\n", __func__, dev->name, enable ? "enable" : "disable");
if (!ops || !ops->set_enable)
return -ENOSYS;
u-boot=> usb start
starting USB...
Bus usb@32e4: regulator_set_enable regulator-usb-otg1 enable
^^^ from ehci_usb_probe
Bus usb@32e5: regulator_set_enable regulator-usb-otg2 enable
^^^ from ehci_usb_probe
regulator_set_enable regulator-usb-otg2 enable
^^^ from mx6_init_after_reset - 2nd enable without a disable
So while I think this patch does make sense to cover the case where a
regulator could be shared there probably is a follow-on patch needed
to balance the regulator calls (unrelated to your series).
Marek,
Should vbus regulator enable really be in init_after_reset call?
Best Regards,
Tim
[1] https://patchwork.ozlabs.org/project/uboot/list/?series=351536
[PATCH] spl: ext: Use partition size for mount
Since commit 9905cae65e03 ("fs: ext4: check the minimal partition size
to mount"), a valid size needs to be provided when mounting
an ext filesystem. Fix the spl ext driver to use the parition size
instead of 0 when mounting the filesystem.
Signed-off-by: Mayuresh Chitale
---
common/spl/spl_ext.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c
index f117c630bf..2bf3434439 100644
--- a/common/spl/spl_ext.c
+++ b/common/spl/spl_ext.c
@@ -28,7 +28,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image,
ext4fs_set_blk_dev(block_dev, _info);
- err = ext4fs_mount(0);
+ err = ext4fs_mount(part_info.size);
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
@@ -82,7 +82,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image,
ext4fs_set_blk_dev(block_dev, _info);
- err = ext4fs_mount(0);
+ err = ext4fs_mount(part_info.size);
if (!err) {
#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
printf("%s: ext4fs mount err - %d\n", __func__, err);
--
2.34.1
Re: [PATCH v2 2/3] X86: Add support for distro boot
Am 2. Mai 2023 17:21:29 MESZ schrieb thomas.mittelsta...@de.bosch.com: >From: Thomas Mittelstaedt > >Enable distro boot feature for U-Boot at VirtualBox described at >https://source.denx.de/u-boot/u-boot/-/blob/master/doc/develop/distro.rst > >Signed-off-by: Thomas Mittelstaedt >--- > configs/efi-x86_payload64_defconfig | 12 +--- > include/configs/efi-x86_payload.h | 11 +++ > 2 files changed, 12 insertions(+), 11 deletions(-) > >diff --git a/configs/efi-x86_payload64_defconfig >b/configs/efi-x86_payload64_defconfig >index 30a7f31dac..a4cfe95890 100644 >--- a/configs/efi-x86_payload64_defconfig >+++ b/configs/efi-x86_payload64_defconfig >@@ -8,33 +8,23 @@ CONFIG_TARGET_EFI_PAYLOAD=y > CONFIG_FIT=y > CONFIG_FIT_SIGNATURE=y > CONFIG_LEGACY_IMAGE_FORMAT=y >+CONFIG_DISTRO_DEFAULTS=y > CONFIG_SHOW_BOOT_PROGRESS=y > CONFIG_USE_BOOTARGS=y > CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" >-CONFIG_USE_BOOTCOMMAND=y > CONFIG_PRE_CONSOLE_BUFFER=y > CONFIG_SYS_CONSOLE_INFO_QUIET=y > CONFIG_DISPLAY_BOARDINFO_LATE=y > CONFIG_LAST_STAGE_INIT=y >-CONFIG_HUSH_PARSER=y > CONFIG_SYS_PBSIZE=532 > CONFIG_CMD_IDE=y > CONFIG_CMD_MMC=y >-CONFIG_CMD_PART=y > CONFIG_CMD_USB=y >-CONFIG_CMD_DHCP=y > CONFIG_BOOTP_BOOTFILESIZE=y > # CONFIG_CMD_NFS is not set >-CONFIG_CMD_PING=y > CONFIG_CMD_TIME=y >-CONFIG_CMD_EXT2=y >-CONFIG_CMD_EXT4=y > CONFIG_CMD_EXT4_WRITE=y >-CONFIG_CMD_FAT=y >-CONFIG_CMD_FS_GENERIC=y > CONFIG_MAC_PARTITION=y >-CONFIG_ISO_PARTITION=y >-CONFIG_EFI_PARTITION=y > CONFIG_ENV_OVERWRITE=y > CONFIG_ENV_IS_IN_FAT=y > CONFIG_ENV_FAT_INTERFACE="scsi" >diff --git a/include/configs/efi-x86_payload.h >b/include/configs/efi-x86_payload.h >index c72b067c36..e1cd8eb316 100644 >--- a/include/configs/efi-x86_payload.h >+++ b/include/configs/efi-x86_payload.h >@@ -6,6 +6,17 @@ > /* > * board/config.h - configuration options, board specific > */ >+#ifndef CONFIG_SPL_BUILD >+ >+#define BOOT_TARGET_SCSI(func) \ Shouldn't NVMe be added here too? Best regards Heinrich >+ func(SCSI, scsi, 0) >+ >+#define BOOT_TARGET_DEVICES(func) \ >+ BOOT_TARGET_SCSI(func) >+ >+#include >+ >+#endif > > #ifndef __CONFIG_H > #define __CONFIG_H
Re: [RFC PATCH v1 6/7] clk: treewide: switch to clock dump from clk_ops
On 4/27/23 22:37, Igor Prusov wrote:
Switch to using new dump operation in clock provider drivers instead of
overriding soc_clk_dump.
Signed-off-by: Igor Prusov
---
arch/mips/mach-pic32/cpu.c | 23 ---
drivers/clk/aspeed/clk_ast2600.c | 13 -
drivers/clk/clk_k210.c | 11 +++-
drivers/clk/clk_pic32.c| 39 ++
drivers/clk/clk_versal.c | 7 -
drivers/clk/clk_zynq.c | 19 -
drivers/clk/clk_zynqmp.c | 13 -
drivers/clk/imx/clk-imx8.c | 11 +++-
drivers/clk/mvebu/armada-37xx-periph.c | 5 +++-
drivers/clk/stm32/clk-stm32mp1.c | 29 ++-
10 files changed, 83 insertions(+), 87 deletions(-)
diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
index de449e3c6a..2875a1ec7c 100644
--- a/arch/mips/mach-pic32/cpu.c
+++ b/arch/mips/mach-pic32/cpu.c
@@ -148,26 +148,3 @@ const char *get_core_name(void)
return str;
}
#endif
-#ifdef CONFIG_CMD_CLK
-
-int soc_clk_dump(void)
-{
- int i;
-
- printf("PLL Speed: %lu MHz\n",
- CLK_MHZ(rate(PLLCLK)));
-
- printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
-
- printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
-
- for (i = PB1CLK; i <= PB7CLK; i++)
- printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
- CLK_MHZ(rate(i)));
-
- for (i = REF1CLK; i <= REF5CLK; i++)
- printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
- CLK_MHZ(rate(i)));
- return 0;
-}
-#endif
diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c
index b3cc8392fa..08db21d394 100644
--- a/drivers/clk/aspeed/clk_ast2600.c
+++ b/drivers/clk/aspeed/clk_ast2600.c
@@ -1109,6 +1109,7 @@ struct aspeed_clks {
const char *name;
};
+#if IS_ENABLED(CONFIG_CMD_CLK)
static struct aspeed_clks aspeed_clk_names[] = {
{ ASPEED_CLK_HPLL, "hpll" },
{ ASPEED_CLK_MPLL, "mpll" },
@@ -1123,18 +1124,12 @@ static struct aspeed_clks aspeed_clk_names[] = {
{ ASPEED_CLK_HUARTX, "huxclk" },
};
-int soc_clk_dump(void)
+int ast2600_clk_dump(struct udevice *dev)
static? apply for all below too.
M
Re: [PATCH v5 00/17] Basic StarFive JH7110 RISC-V SoC support
On 5/2/23 15:11, Andreas Schwab wrote: On Mai 02 2023, Matthias Brugger wrote: I'm not sure I get your point. The devicetree will be passed to the kernel via a pointer in a register, the kernel does not need to load the devicetree into memory, it will use the one passed by U-Boot. But U-Boot needs to load it, and the kernel is the authority in providing it. To make it a bit clearer: Several U-Boot boot methods use the value of environment variable $fdtfile to load a device-tree from file. The same holds true for the boot.scr file created by Debian's flash-kernel package. A good solution would be to read the EEPROM to determine the exact board version, to set $fdtfile accordingly and update U-Boots control dtb as needed. Best regards Heinrich
[PATCH 6/6] corstone1000: add nvmxip, fwu-mdata and gpt options
Enable the newest features: nvmxip, fwu-metadata and
gpt. Commands to print the partition info, gpt info
and fwu metadata will be available.
Adjust also env boot script the address of the
bootbank with the new gpt layout, and also remove
the not needed kernel address bank0 and bank1
and retrieve function that would test the bank flag
before and now we are getting the info from the fwu
metadata.
Signed-off-by: Rui Miguel Silva
---
board/armltd/corstone1000/corstone1000.c | 1 +
board/armltd/corstone1000/corstone1000.env | 10 +-
configs/corstone1000_defconfig | 13 -
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/board/armltd/corstone1000/corstone1000.c
b/board/armltd/corstone1000/corstone1000.c
index a4567449f1be..01c80aaf9d77 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
#include
#include
#include
diff --git a/board/armltd/corstone1000/corstone1000.env
b/board/armltd/corstone1000/corstone1000.env
index b24ff07fc6bd..ee318b1b1c30 100644
--- a/board/armltd/corstone1000/corstone1000.env
+++ b/board/armltd/corstone1000/corstone1000.env
@@ -1,13 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0+ */
usb_pgood_delay=250
-boot_bank_flag=0x08002000
-kernel_addr_bank_0=0x083EE000
-kernel_addr_bank_1=0x0936E000
-retrieve_kernel_load_addr=
- if itest.l *${boot_bank_flag} == 0; then
- setenv kernel_addr $kernel_addr_bank_0;
- else
- setenv kernel_addr $kernel_addr_bank_1;
- fi;
+boot_bank_flag=0x08005006
kernel_addr_r=0x8820
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 5be5335bdfc1..a8a79fd10568 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -15,7 +15,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk"
-CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from
$kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc0; usb
start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
+CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ;
loadm $kernel_addr $kernel_addr_r 0xc0; usb start; usb reset; run
distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;"
CONFIG_CONSOLE_RECORD=y
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
@@ -24,11 +24,16 @@ CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=512
# CONFIG_CMD_CONSOLE is not set
+CONFIG_CMD_FWU_METADATA=y
CONFIG_CMD_BOOTZ=y
CONFIG_SYS_BOOTM_LEN=0x80
# CONFIG_CMD_XIMG is not set
+CONFIG_CMD_NVMXIP=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_LOADM=y
# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
@@ -40,6 +45,8 @@ CONFIG_OF_CONTROL=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_REGMAP=y
+CONFIG_FWU_MDATA=y
+CONFIG_FWU_MDATA_GPT_BLK=y
CONFIG_MISC=y
# CONFIG_MMC is not set
CONFIG_NVMXIP_QSPI=y
@@ -51,6 +58,10 @@ CONFIG_RAM=y
CONFIG_DM_RTC=y
CONFIG_RTC_EMULATION=y
CONFIG_DM_SERIAL=y
+CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_ISP1760=y
+CONFIG_EFI_CAPSULE_ON_DISK=y
+CONFIG_EFI_IGNORE_OSINDICATIONS=y
+CONFIG_FWU_MULTI_BANK_UPDATE=y
CONFIG_ERRNO_STR=y
--
2.40.0
[PATCH 5/6] corstone1000: set kernel_addr based on boot_idx
We need to distinguish between boot banks and from which
partition to load the kernel+initramfs to memory.
For that, fetch the boot index, fetch the correspondent
partition, calculate the correct kernel address and
then set the env variable kernel_addr with that value.
Signed-off-by: Rui Miguel Silva
---
board/armltd/corstone1000/corstone1000.c | 56 +++-
configs/corstone1000_defconfig | 1 +
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/board/armltd/corstone1000/corstone1000.c
b/board/armltd/corstone1000/corstone1000.c
index 1bead7a0a8b4..a4567449f1be 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -5,16 +5,24 @@
* Rui Miguel Silva
*/
+#include
#include
#include
#include
#include
-#include
#include
+#include
+#include
#include
#include
#include
+#define CORSTONE1000_KERNEL_PARTS 2
+#define CORSTONE1000_KERNEL_PRIMARY "kernel_primary"
+#define CORSTONE1000_KERNEL_SECONDARY "kernel_secondary"
+
+static int corstone1000_boot_idx;
+
static struct mm_region corstone1000_mem_map[] = {
{
/* CVM */
@@ -103,6 +111,52 @@ void fwu_plat_get_bootidx(uint *boot_idx)
*boot_idx = CONFIG_FWU_NUM_BANKS;
log_err("corstone1000: failed to read active index\n");
}
+}
+
+int board_late_init(void)
+{
+ struct disk_partition part_info;
+ struct udevice *dev, *bdev;
+ struct nvmxip_plat *plat;
+ struct blk_desc *desc;
+ int ret;
+
+ ret = uclass_first_device_err(UCLASS_NVMXIP, );
+ if (ret < 0) {
+ log_err("Cannot find kernel device\n");
+ return ret;
+ }
+
+ plat = dev_get_plat(dev);
+ device_find_first_child(dev, );
+ desc = dev_get_uclass_plat(bdev);
+ ret = fwu_get_active_index(_boot_idx);
+ if (ret < 0) {
+ log_err("corstone1000: failed to read boot index\n");
+ return ret;
+ }
+
+ if (!corstone1000_boot_idx)
+ ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_PRIMARY,
+ _info);
+ else
+ ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_SECONDARY,
+ _info);
+
+ if (ret < 0) {
+ log_err("failed to fetch kernel partition index: %d\n",
+ corstone1000_boot_idx);
+ return ret;
+ }
+
+ ret = 0;
+
+ ret |= env_set_hex("kernel_addr", plat->phys_base +
+ (part_info.start * part_info.blksz));
+ ret |= env_set_hex("kernel_size", part_info.size * part_info.blksz);
+
+ if (ret < 0)
+ log_err("failed to setup kernel addr and size\n");
return ret;
}
diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig
index 2d391048cd67..5be5335bdfc1 100644
--- a/configs/corstone1000_defconfig
+++ b/configs/corstone1000_defconfig
@@ -20,6 +20,7 @@ CONFIG_CONSOLE_RECORD=y
CONFIG_LOGLEVEL=7
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=512
# CONFIG_CMD_CONSOLE is not set
--
2.40.0
[PATCH 4/6] corstone1000: add boot index
it is expected that the firmware that runs before
u-boot somehow provide the information of the bank
for now we will fetch the info from the metadata
since the Secure enclave is the one responsible for
this information.
Signed-off-by: Rui Miguel Silva
---
board/armltd/corstone1000/corstone1000.c | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/board/armltd/corstone1000/corstone1000.c
b/board/armltd/corstone1000/corstone1000.c
index 6ec8e6144fb4..1bead7a0a8b4 100644
--- a/board/armltd/corstone1000/corstone1000.c
+++ b/board/armltd/corstone1000/corstone1000.c
@@ -8,6 +8,8 @@
#include
#include
#include
+#include
+#include
#include
#include
#include
@@ -87,6 +89,20 @@ int dram_init_banksize(void)
return 0;
}
-void reset_cpu(void)
+void fwu_plat_get_bootidx(uint *boot_idx)
{
+ int ret;
+
+ /*
+* in our platform, the Secure Enclave is the one who controls
+* all the boot tries and status, so, every time we get here
+* we know that the we are booting from the active index
+*/
+ ret = fwu_get_active_index(boot_idx);
+ if (ret < 0) {
+ *boot_idx = CONFIG_FWU_NUM_BANKS;
+ log_err("corstone1000: failed to read active index\n");
+ }
+
+ return ret;
}
--
2.40.0
[PATCH 3/6] corstone1000: add fwu-metadata store info
Add fwu-mdata node and handle for the reference
nvmxip-qspi.
Signed-off-by: Rui Miguel Silva
---
arch/arm/dts/corstone1000.dtsi | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi
index 533dfdf8e1ca..1e0ec075e4cd 100644
--- a/arch/arm/dts/corstone1000.dtsi
+++ b/arch/arm/dts/corstone1000.dtsi
@@ -38,7 +38,7 @@
reg = <0x8820 0x77e0>;
};
- nvmxip-qspi@0800 {
+ nvmxip: nvmxip-qspi@0800 {
compatible = "nvmxip,qspi";
reg = <0x0800 0x200>;
lba_shift = <9>;
@@ -106,6 +106,11 @@
method = "smc";
};
+ fwu-mdata {
+ compatible = "u-boot,fwu-mdata-gpt";
+ fwu-mdata-store = <>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
--
2.40.0
[PATCH 2/6] nvmxip: move header to include
Move header to include to allow external code
to get the internal bdev structures to access
block device operations.
as at it, just add the UCLASS_NVMXIP string
so we get the correct output in partitions
listing.
Signed-off-by: Rui Miguel Silva
---
{drivers/mtd/nvmxip => include}/nvmxip.h | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename {drivers/mtd/nvmxip => include}/nvmxip.h (100%)
diff --git a/drivers/mtd/nvmxip/nvmxip.h b/include/nvmxip.h
similarity index 100%
rename from drivers/mtd/nvmxip/nvmxip.h
rename to include/nvmxip.h
--
2.40.0
[PATCH 1/6] fwu_metadata: make sure structures are packed
The fwu metadata in the metadata partitions
should/are packed to guarantee that the info is
correct in all platforms. Also the size of them
are used to calculate the crc32 and that is important
to get it right.
Signed-off-by: Rui Miguel Silva
---
include/fwu_mdata.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h
index 8fda4f4ac225..c61221a91735 100644
--- a/include/fwu_mdata.h
+++ b/include/fwu_mdata.h
@@ -22,7 +22,7 @@ struct fwu_image_bank_info {
efi_guid_t image_uuid;
uint32_t accepted;
uint32_t reserved;
-};
+} __packed;
/**
* struct fwu_image_entry - information for a particular type of image
@@ -38,7 +38,7 @@ struct fwu_image_entry {
efi_guid_t image_type_uuid;
efi_guid_t location_uuid;
struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS];
-};
+} __packed;
/**
* struct fwu_mdata - FWU metadata structure for multi-bank updates
@@ -62,6 +62,6 @@ struct fwu_mdata {
uint32_t previous_active_index;
struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
-};
+} __packed;
#endif /* _FWU_MDATA_H_ */
--
2.40.0
