[PATCH v1] configs: imxrt1050-evk: enable distro bootcmd
Add support to boot from script.scr from mmc. imxrt1050-evk was not able to boot from script.scr because we did not include config_distro_bootcmd.h and set the device to mmc. Signed-off-by: Jesse Taube --- configs/imxrt1050-evk_defconfig | 2 +- include/configs/imxrt1050-evk.h | 15 ++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig index cbf9469b24..35c0364e6b 100644 --- a/configs/imxrt1050-evk_defconfig +++ b/configs/imxrt1050-evk_defconfig @@ -25,7 +25,6 @@ CONFIG_HAVE_SYS_UBOOT_START=y CONFIG_SYS_UBOOT_START=0x800023FD CONFIG_DISTRO_DEFAULTS=y CONFIG_SD_BOOT=y -# CONFIG_USE_BOOTCOMMAND is not set CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_NO_BSS_LIMIT=y @@ -40,6 +39,7 @@ CONFIG_SYS_PBSIZE=276 # CONFIG_BOOTM_PLAN9 is not set # CONFIG_BOOTM_RTEMS is not set # CONFIG_BOOTM_VXWORKS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_MII is not set # CONFIG_SPL_DOS_PARTITION is not set diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h index 2af2dde2ae..4b78d61d3f 100644 --- a/include/configs/imxrt1050-evk.h +++ b/include/configs/imxrt1050-evk.h @@ -19,10 +19,23 @@ DMAMEM_SZ_ALL) #ifdef CONFIG_VIDEO -#define CFG_EXTRA_ENV_SETTINGS \ +#define ENV_DEVICE_SETTINGS \ "stdin=serial\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" #endif +/* Config distro_bootcmd */ +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) +#include +#endif + +#define CFG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(PHYS_SDRAM) "\0" \ + "kernel_addr_r" __stringify(PHYS_SDRAM) "\0" + #endif /* __IMXRT1050_EVK_H */ -- 2.40.1
[PATCH v4] bootstd: sata: Add bootstd support for ahci sata
Add ahci sata bootdev and corresponding hunting function.
Signed-off-by: Tony Dinh
---
Changes in v4:
- Revise logic in bootmeth_script() to set devtype to sata for non-scsi
SATA device
- Rewrite sata_rescan() logic to properly remove all devices before probing
- Add description to sata_rescan() header
Changes in v3:
- Correct drivers/ata/Makefile to compile sata_bootdev only if
ahci sata is enabled.
Changes in v2:
- set devtype to sata in bootmeth_script for non-scsi SATA device.
boot/bootmeth_script.c | 14 +++--
drivers/ata/Makefile | 2 +-
drivers/ata/sata.c | 32
drivers/ata/sata_bootdev.c | 62 ++
include/sata.h | 6
5 files changed, 112 insertions(+), 4 deletions(-)
create mode 100644 drivers/ata/sata_bootdev.c
diff --git a/boot/bootmeth_script.c b/boot/bootmeth_script.c
index 58c57a2d4b..96e0ec5efa 100644
--- a/boot/bootmeth_script.c
+++ b/boot/bootmeth_script.c
@@ -190,10 +190,18 @@ static int script_boot(struct udevice *dev, struct
bootflow *bflow)
ulong addr;
int ret;
- if (desc->uclass_id == UCLASS_USB)
+ if (desc->uclass_id == UCLASS_USB) {
ret = env_set("devtype", "usb");
- else
- ret = env_set("devtype", blk_get_devtype(bflow->blk));
+ } else {
+ /* If the uclass is AHCI, but the driver is ATA
+* (not scsi), set devtype to sata
+*/
+ if (!ret && IS_ENABLED(CONFIG_SATA) &&
+ desc->uclass_id == UCLASS_AHCI)
+ ret = env_set("devtype", "sata");
+ else
+ ret = env_set("devtype", blk_get_devtype(bflow->blk));
+ }
if (!ret)
ret = env_set_hex("devnum", desc->devnum);
if (!ret)
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 6e30180b8b..0b6f91098a 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_SCSI_AHCI) += ahci.o
obj-$(CONFIG_DWC_AHSATA) += dwc_ahsata.o
obj-$(CONFIG_FSL_SATA) += fsl_sata.o
obj-$(CONFIG_LIBATA) += libata.o
-obj-$(CONFIG_SATA) += sata.o
+obj-$(CONFIG_SATA) += sata.o sata_bootdev.o
obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
obj-$(CONFIG_SATA_MV) += sata_mv.o
obj-$(CONFIG_SATA_SIL) += sata_sil.o
diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c
index ce3e9b5a40..f126b84e05 100644
--- a/drivers/ata/sata.c
+++ b/drivers/ata/sata.c
@@ -15,6 +15,8 @@
#include
#include
#include
+#include
+#include
#ifndef CONFIG_AHCI
struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
@@ -50,6 +52,36 @@ int sata_scan(struct udevice *dev)
return ops->scan(dev);
}
+int sata_rescan(bool verbose)
+{
+ int ret;
+ struct udevice *dev;
+
+ if (verbose)
+ printf("Removing devices on SATA bus...\n");
+
+ blk_unbind_all(UCLASS_AHCI);
+
+ ret = uclass_find_first_device(UCLASS_AHCI, );
+ if (ret || !dev) {
+ printf("Cannot find SATA device (err=%d)\n", ret);
+ return -ENOSYS;
+ }
+
+ ret = device_remove(dev, DM_REMOVE_NORMAL);
+ if (ret) {
+ printf("Cannot remove SATA device '%s' (err=%d)\n", dev->name,
ret);
+ return -ENOSYS;
+ }
+
+ if (verbose)
+ printf("Rescanning SATA bus for devices...\n");
+
+ ret = uclass_probe_all(UCLASS_AHCI);
+
+ return ret;
+}
+
#ifndef CONFIG_AHCI
#ifdef CONFIG_PARTITIONS
struct blk_desc *sata_get_dev(int dev)
diff --git a/drivers/ata/sata_bootdev.c b/drivers/ata/sata_bootdev.c
new file mode 100644
index 00..f638493ce0
--- /dev/null
+++ b/drivers/ata/sata_bootdev.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bootdev for sata
+ *
+ * Copyright 2023 Tony Dinh
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+static int sata_bootdev_bind(struct udevice *dev)
+{
+ struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev);
+
+ ucp->prio = BOOTDEVP_4_SCAN_FAST;
+
+ return 0;
+}
+
+static int sata_bootdev_hunt(struct bootdev_hunter *info, bool show)
+{
+ int ret;
+
+ if (IS_ENABLED(CONFIG_PCI)) {
+ ret = pci_init();
+ if (ret)
+ return ret;
+ }
+
+ ret = sata_rescan(true);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+struct bootdev_ops sata_bootdev_ops = {
+};
+
+static const struct udevice_id sata_bootdev_ids[] = {
+ { .compatible = "u-boot,bootdev-sata" },
+ { }
+};
+
+U_BOOT_DRIVER(sata_bootdev) = {
+ .name = "sata_bootdev",
+ .id = UCLASS_BOOTDEV,
+ .ops= _bootdev_ops,
+ .bind = sata_bootdev_bind,
+ .of_match = sata_bootdev_ids,
+};
+
+BOOTDEV_HUNTER(sata_bootdev_hunter) = {
+ .prio = BOOTDEVP_4_SCAN_FAST,
+
Re: [PATCH v3 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out
On Sun, 2023-09-17 at 13:47, Heinrich Schuchardt wrote:
> The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a
> prefixed header. We have referring to a vendor tool (spl_tool) for this
> task. 'mkimage -T sfspl' can generate the prefixed file.
>
> Use binman to invoke mkimage for the generation of file
> spl/u-boot-spl.bin.normal.out.
>
> Update the documentation.
>
> Signed-off-by: Heinrich Schuchardt
Tested-by: Milan P. Stanić
> ---
> v3:
> Rename binman node for SPL image.
> Use u-boot-spl instead of blob as mkimage subnode.
> v2:
> Fix a typo in a comment in tools/sfspl.c
> Add Tested-by credits
> ---
> .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 11 +++
> doc/board/starfive/visionfive2.rst | 14 ++
> 2 files changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> index 13f69da31e..55185314dd 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> @@ -103,4 +103,15 @@
> };
> };
> };
> +
> + spl-img {
> + filename = "spl/u-boot-spl.bin.normal.out";
> +
> + mkimage {
> + args = "-T sfspl";
> +
> + u-boot-spl {
> + };
> + };
> +};
> };
> diff --git a/doc/board/starfive/visionfive2.rst
> b/doc/board/starfive/visionfive2.rst
> index 941899a0a4..f5575ab68b 100644
> --- a/doc/board/starfive/visionfive2.rst
> +++ b/doc/board/starfive/visionfive2.rst
> @@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
> make starfive_visionfive2_defconfig
> make
> OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
>
> -This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> -
> -u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
> -to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
> -the below command:
> -
> - ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
> -
> -More detailed description of spl_tool,please refer spl_tool documenation.
> -(Note: spl_tool git repo is at
> https://github.com/starfive-tech/Tools/tree/master/spl_tool)
> -
> -This will generate u-boot-spl.bin.normal.out file.
> +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as
> well
> +as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
>
> Flashing
>
> --
> 2.40.1
>
[PATCH v4 4/4] rockchip: Add support to generate LZMA compressed U-boot binary
Add support for generating a LZMA-compressed U-boot binary with the
help of binman, if CONFIG_SPL_LZMA is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index 8f248f941f..c8c928c7e5 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -58,6 +58,8 @@
#endif
#if defined(CONFIG_SPL_GZIP)
compression = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compression = "lzma";
#else
compression = "none";
#endif
@@ -66,6 +68,8 @@
u-boot-nodtb {
#if defined(CONFIG_SPL_GZIP)
compress = "gzip";
+#elif defined(CONFIG_SPL_LZMA)
+ compress = "lzma";
#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
--
2.25.1
[PATCH v4 3/4] rockchip: Add support to generate GZIP compressed U-boot binary
Add support for generating a GZIP-compressed U-boot binary with the
help of binman, if CONFIG_SPL_GZIP is selected.
Signed-off-by: Manoj Sai
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- None
Changes in v2:
- New patch for v2
arch/arm/dts/rockchip-u-boot.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/dts/rockchip-u-boot.dtsi
b/arch/arm/dts/rockchip-u-boot.dtsi
index be2658e8ef..8f248f941f 100644
--- a/arch/arm/dts/rockchip-u-boot.dtsi
+++ b/arch/arm/dts/rockchip-u-boot.dtsi
@@ -56,10 +56,17 @@
#else
arch = "arm";
#endif
+#if defined(CONFIG_SPL_GZIP)
+ compression = "gzip";
+#else
compression = "none";
+#endif
load = ;
entry = ;
u-boot-nodtb {
+#if defined(CONFIG_SPL_GZIP)
+ compress = "gzip";
+#endif
};
#ifdef CONFIG_SPL_FIT_SIGNATURE
hash {
--
2.25.1
[PATCH v4 2/4] spl: fit: support for booting a LZMA-compressed U-boot binary
If LZMA Compression support is enabled, LZMA compressed U-Boot
binary will be placed at a specified RAM location which is
defined at CONFIG_SYS_LOAD_ADDR and will be assigned as the
source address.
image_decomp() function, will decompress the LZMA compressed
U-Boot binary which is placed at source address(CONFIG_SYS_LOAD_ADDR)
to the default CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Simon Glass
Reviewed-by: Kever Yang
---
Changes in v4:
- None
Changes in v3:
- added IS_ENABLED(CONFIG_SPL_LZMA) to spl_decompression_enabled() function.
- Removed extra parentheses.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 13 -
include/spl.h| 2 +-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index eb97259f57..75895ef15c 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -281,7 +281,8 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ if (spl_decompression_enabled() &&
+ (image_comp == IH_COMP_GZIP || image_comp == IH_COMP_LZMA))
src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
else
src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
@@ -329,6 +330,16 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return -EIO;
}
length = size;
+ } else if (IS_ENABLED(CONFIG_SPL_LZMA) && image_comp == IH_COMP_LZMA) {
+ size = CONFIG_SYS_BOOTM_LEN;
+ ulong loadEnd;
+
+ if (image_decomp(IH_COMP_LZMA, CONFIG_SYS_LOAD_ADDR, 0, 0,
+load_ptr, src, length, size, )) {
+ puts("Uncompressing error\n");
+ return -EIO;
+ }
+ length = loadEnd - CONFIG_SYS_LOAD_ADDR;
} else {
memcpy(load_ptr, src, length);
}
diff --git a/include/spl.h b/include/spl.h
index 3a7e448cc7..9de93a34cd 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -905,6 +905,6 @@ void spl_save_restore_data(void);
*/
static inline bool spl_decompression_enabled(void)
{
- return IS_ENABLED(CONFIG_SPL_GZIP);
+ return IS_ENABLED(CONFIG_SPL_GZIP) || IS_ENABLED(CONFIG_SPL_LZMA);
}
#endif
--
2.25.1
[PATCH v4 1/4] spl: fit: support for booting a GZIP-compressed U-boot binary
If GZIP Compression support is enabled, GZIP compressed U-Boot binary
will be at a specified RAM location which is defined at
CONFIG_SYS_LOAD_ADDR and will be assign it as the source address.
gunzip function in spl_load_fit_image ,will decompress the GZIP
compressed U-Boot binary which is placed at
source address(CONFIG_SYS_LOAD_ADDR) to the default
CONFIG_SYS_TEXT_BASE location.
spl_load_fit_image function will load the decompressed U-Boot
binary, which is placed at the CONFIG_SYS_TEXT_BASE location.
Signed-off-by: Manoj Sai
Signed-off-by: Suniel Mahesh
Reviewed-by: Kever Yang
Reviewed-by: Simon Glass
---
Changes in v4:
- None
Changes in v3:
- Replaced spl_decompression_enabled() function instead of
checking IS_ENABLED(CONFIG_SPL_GZIP).
- Removed checking IS_ENABLED(CONFIG_SPL_LZMA) in spl_decompression_enabled()
function.
Changes in v2:
- New patch for v2
common/spl/spl_fit.c | 9 ++---
include/spl.h| 10 ++
2 files changed, 16 insertions(+), 3 deletions(-)
diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c
index 730639f756..eb97259f57 100644
--- a/common/spl/spl_fit.c
+++ b/common/spl/spl_fit.c
@@ -239,14 +239,14 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
bool external_data = false;
if (IS_ENABLED(CONFIG_SPL_FPGA) ||
- (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) {
+ (IS_ENABLED(CONFIG_SPL_OS_BOOT) && spl_decompression_enabled())) {
if (fit_image_get_type(fit, node, ))
puts("Cannot get image type.\n");
else
debug("%s ", genimg_get_type_name(type));
}
- if (IS_ENABLED(CONFIG_SPL_GZIP)) {
+ if (spl_decompression_enabled()) {
fit_image_get_comp(fit, node, _comp);
debug("%s ", genimg_get_comp_name(image_comp));
}
@@ -281,7 +281,10 @@ static int spl_load_fit_image(struct spl_load_info *info,
ulong sector,
return 0;
}
- src_ptr = map_sysmem(ALIGN(load_addr, ARCH_DMA_MINALIGN), len);
+ if (spl_decompression_enabled() && image_comp == IH_COMP_GZIP)
+ src_ptr = map_sysmem(ALIGN(CONFIG_SYS_LOAD_ADDR,
ARCH_DMA_MINALIGN), len);
+ else
+ src_ptr = map_sysmem(ALIGN(load_addr,
ARCH_DMA_MINALIGN), len);
length = len;
overhead = get_aligned_image_overhead(info, offset);
diff --git a/include/spl.h b/include/spl.h
index 93e906431e..3a7e448cc7 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -897,4 +897,14 @@ struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset,
size_t size);
void board_boot_order(u32 *spl_boot_list);
void spl_save_restore_data(void);
+
+/*
+ * spl_decompression_enabled() - check decompression support is enabled for
SPL build
+ *
+ * Returns true if decompression support is enabled, else False
+ */
+static inline bool spl_decompression_enabled(void)
+{
+ return IS_ENABLED(CONFIG_SPL_GZIP);
+}
#endif
--
2.25.1
[PATCH v4 0/4] support for booting the compressed U-boot binary on Rockchip based ARM64 SOC's
This patchset adds the support on Rockchip based ARM64 SOC's that compress the U-BOOT proper along with dtb and ATF in FIT image format.Second stage bootloader(SPL) loads the compressed binaries, uncompress them and handover control to the next stage. Changes for V3 :- 1. Replaced spl_decompression_enabled() function instead of checking IS_ENABLED(CONFIG_SPL_GZIP) and IS_ENABLED(CONFIG_SPL_LZMA) in spl_fit.c. 2. Removed extra wrapping parentheses in spl_decompression_enabled(). Changes for V4 :- 1. As per the suggestion from Mr.Jonas Karlman (jo...@kwiboo.se) from PATCH v2 and v3 ,check boot time with the following RFC patch with CONFIG_SPL_FIT_SIGNATURE enabled that might impact boot time and As seen there is an improvement in boot time with both compress enabled and disabled , I have added the logs of it below. [RFC] rockchip: spl: Enable caches to speed up checksum validation https://patchwork.ozlabs.org/project/uboot/patch/20230702110055.3686457-1-jo...@kwiboo.se/ Size Comparision between compressed and uncompressed binaries :- size of uncompressed binary:- 9.0M (94,21,824 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9421824 Sep 10 22:22 u-boot-rockchip.bin size of GZIP compressed binary :- 8.6M (89,85,088 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 8985088 Jul 25 07:42 u-boot-rockchip.bin size of LZMA compressed binary :- 8.6 M (90,06,592 bytes) manoj:u-boot$ ls -lb u-boot-rockchip.bin -rw-rw-r-- 1 manoj manoj 9006592 Jul 25 07:47 u-boot-rockchip.bin Test results of Booting time using bootstage command in Uboot command prompt on roc-rk3399-pc board :- 1) Uncompressed U-BOOT : Total boot time = 12.063971 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 1,833,884 1,833,884 board_init_f 2,959,528 1,125,644 board_init_r 5,224,521 2,264,993 eth_common_init 5,523,428298,907 eth_initialize 5,523,606178 main_loop 5,523,764158 usb_start 12,063,971 6,540,207 cli_loop 2) GZIP Compressed U-BOOT : Total time = 12.824968 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 2,594,709 2,594,709 board_init_f 3,719,969 1,125,260 board_init_r 5,985,450 2,265,481 eth_common_init 6,284,371298,921 eth_initialize 6,284,549178 main_loop 6,284,708159 usb_start 12,824,968 6,540,260 cli_loop 3) LZMA Compressed U-BOOT : Total time = 17.025004 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 6,852,254 6,852,254 board_init_f 7,940,143 1,087,889 board_init_r 10,190,458 2,250,315 eth_common_init 10,487,254296,796 eth_initialize 10,487,432178 main_loop 10,487,590158 usb_start 17,025,004 6,537,414 cli_loop Test results of booting time using RFC patch from Mr.Jonas Karlman(jo...@kwiboo.se) with CONFIG_SPL_FIT_SIGNATURE enabled on roc-rk3399-pc board :- 1. Uncompressed U-BOOT : Total boot time = 10.728 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 477,024477,024 board_init_f 1,623,670 1,146,646 board_init_r 3,889,493 2,265,823 eth_common_init 4,188,402298,909 eth_initialize 4,188,579177 main_loop 4,188,738159 usb_start 10,728,000 6,539,262 cli_loop 2. GZIP Compressed U-BOOT : Total time = 10.708 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 457,663457,663 board_init_f 1,604,222 1,146,559 board_init_r 3,869,505 2,265,283 eth_common_init 4,168,410298,905 eth_initialize 4,168,587177 main_loop 4,168,745158 usb_start 10,707,997 6,539,252 cli_loop 3. LZMA Compressed U-BOOT : Total time = 10.86 seconds => bootstage report Timer summary in microseconds (10 records): MarkElapsed Stage 0 0 reset 612,427612,427 board_init_f 1,756,176 1,143,749 board_init_r 4,021,522 2,265,346 eth_common_init 4,320,433298,911 eth_initialize 4,320,610177 main_loop 4,320,768158 usb_start 10,860,001 6,539,233 cli_loop As I can seen there is an improvement in boot time with Enable caches in SPL to speed up FIT checksum validation, with the following RFC patch from Mr.Jonas. [RFC] rockchip: spl: Enable caches to speed up checksum validation https://patchwork.ozlabs.org/project/uboot/patch/20230702110055.3686457-1-jo...@kwiboo.se/ Manoj Sai (4): spl: fit: support for booting a GZIP-compressed U-boot binary spl: fit: support for booting a LZMA-compressed
[PATCH 18/19] ARM: dts: renesas: Synchronize RZ R8A774E1 RZ/G2H DTs with Linux 6.5.3
Synchronize RZ R8A774E1 RZ/G2H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts | 29 ++
arch/arm/dts/r8a774e1.dtsi | 14 +++
2 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
index 3e9ced3b2d3..146f78cb6f1 100644
--- a/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
+++ b/arch/arm/dts/r8a774e1-beacon-rzg2h-kit.dts
@@ -14,6 +14,14 @@
compatible = "beacon,beacon-rzg2h", "renesas,r8a774e1";
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 = _pmic;
serial0 =
serial1 =
serial2 =
@@ -51,24 +59,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
-
-/* Reference versaclock instead of audio_clk_a */
-_sound {
- clocks = < CPG_MOD 1005>,
-< CPG_MOD 1006>, < CPG_MOD 1007>,
-< CPG_MOD 1008>, < CPG_MOD 1009>,
-< CPG_MOD 1010>, < CPG_MOD 1011>,
-< CPG_MOD 1012>, < CPG_MOD 1013>,
-< CPG_MOD 1014>, < CPG_MOD 1015>,
-< CPG_MOD 1022>, < CPG_MOD 1023>,
-< CPG_MOD 1024>, < CPG_MOD 1025>,
-< CPG_MOD 1026>, < CPG_MOD 1027>,
-< CPG_MOD 1028>, < CPG_MOD 1029>,
-< CPG_MOD 1030>, < CPG_MOD 1031>,
-< CPG_MOD 1020>, < CPG_MOD 1021>,
-< CPG_MOD 1020>, < CPG_MOD 1021>,
-< CPG_MOD 1019>, < CPG_MOD 1018>,
-<_bb 4>, <_clk_b>,
-<_clk_c>,
-< CPG_CORE R8A774E1_CLK_S0D4>;
-};
diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi
index c5a0e7866b2..2acf4067ab2 100644
--- a/arch/arm/dts/r8a774e1.dtsi
+++ b/arch/arm/dts/r8a774e1.dtsi
@@ -1774,7 +1774,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -2471,8 +2471,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2483,6 +2483,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A774E1_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2498,8 +2500,8 @@
<0x0200 0 0xeea0 0 0xeea0 0
0x0020>,
<0x0200 0 0xc000 0 0xc000 0
0x0800>,
<0x4200 0 0xc800 0 0xc800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2510,6 +2512,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A774E1_PD_ALWAYS_ON>;
resets = < 318>;
+ iommu-map = <0 _hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.40.1
[PATCH 19/19] ARM: renesas: Align env eMMC device number with Linux 6.5.3 DT changes on R-Car Gen3 Salvator-X
Set U-Boot environment storage eMMC device number to 0, to match the new additions to DT /aliases node pulled in alongside Linux 6.5.3 DT synchronization. Signed-off-by: Marek Vasut --- configs/rcar3_salvator-x_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 6aaf24e0126..02924244c7a 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -58,7 +58,6 @@ CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-ex CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_SYS_MMC_ENV_DEV=1 CONFIG_SYS_MMC_ENV_PART=2 CONFIG_VERSION_VARIABLE=y CONFIG_REGMAP=y -- 2.40.1
[PATCH 17/19] ARM: dts: renesas: Synchronize RZ R8A774C0 RZ/G2E DTs with Linux 6.5.3
Synchronize RZ R8A774C0 RZ/G2E DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a774c0.dtsi| 11 +--
arch/arm/dts/r8a774e1-u-boot.dtsi | 1 -
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/r8a774c0.dtsi b/arch/arm/dts/r8a774c0.dtsi
index 151e32ac036..ad2e87b039a 100644
--- a/arch/arm/dts/r8a774c0.dtsi
+++ b/arch/arm/dts/r8a774c0.dtsi
@@ -49,17 +49,14 @@
opp-shared;
opp-8 {
opp-hz = /bits/ 64 <8>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
};
opp-10 {
opp-hz = /bits/ 64 <10>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
};
opp-12 {
opp-hz = /bits/ 64 <12>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
opp-suspend;
};
@@ -1317,7 +1314,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -1707,8 +1704,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x4000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -1719,6 +1716,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A774C0_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/r8a774e1-u-boot.dtsi
b/arch/arm/dts/r8a774e1-u-boot.dtsi
index e86287098ba..45ef5b78240 100644
--- a/arch/arm/dts/r8a774e1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774e1-u-boot.dtsi
@@ -30,7 +30,6 @@
/delete-node/
/delete-node/
/delete-node/ _sound;
-/delete-node/
/delete-node/ _card;
/delete-node/
/delete-node/
--
2.40.1
[PATCH 16/19] ARM: dts: renesas: Synchronize RZ R8A774B1 RZ/G2N DTs with Linux 6.5.3
Synchronize RZ R8A774B1 RZ/G2N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts | 29 ++
arch/arm/dts/r8a774b1-u-boot.dtsi | 1 -
arch/arm/dts/r8a774b1.dtsi | 14 +++
3 files changed, 17 insertions(+), 27 deletions(-)
diff --git a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
index 89d708346ba..8b9df6afffd 100644
--- a/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
+++ b/arch/arm/dts/r8a774b1-beacon-rzg2n-kit.dts
@@ -14,6 +14,14 @@
compatible = "beacon,beacon-rzg2n", "renesas,r8a774b1";
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 = _pmic;
serial0 =
serial1 =
serial2 =
@@ -46,24 +54,3 @@
clock-names = "du.0", "du.1", "du.3",
"dclkin.0", "dclkin.1", "dclkin.3";
};
-
-/* Reference versaclock instead of audio_clk_a */
-_sound {
- clocks = < CPG_MOD 1005>,
-< CPG_MOD 1006>, < CPG_MOD 1007>,
-< CPG_MOD 1008>, < CPG_MOD 1009>,
-< CPG_MOD 1010>, < CPG_MOD 1011>,
-< CPG_MOD 1012>, < CPG_MOD 1013>,
-< CPG_MOD 1014>, < CPG_MOD 1015>,
-< CPG_MOD 1022>, < CPG_MOD 1023>,
-< CPG_MOD 1024>, < CPG_MOD 1025>,
-< CPG_MOD 1026>, < CPG_MOD 1027>,
-< CPG_MOD 1028>, < CPG_MOD 1029>,
-< CPG_MOD 1030>, < CPG_MOD 1031>,
-< CPG_MOD 1020>, < CPG_MOD 1021>,
-< CPG_MOD 1020>, < CPG_MOD 1021>,
-< CPG_MOD 1019>, < CPG_MOD 1018>,
-<_bb 4>, <_clk_b>,
-<_clk_c>,
-< CPG_CORE R8A774B1_CLK_S0D4>;
-};
diff --git a/arch/arm/dts/r8a774b1-u-boot.dtsi
b/arch/arm/dts/r8a774b1-u-boot.dtsi
index 3b34f82160b..d4890ebc298 100644
--- a/arch/arm/dts/r8a774b1-u-boot.dtsi
+++ b/arch/arm/dts/r8a774b1-u-boot.dtsi
@@ -27,7 +27,6 @@
/delete-node/
/delete-node/
/delete-node/ _sound;
-/delete-node/
/delete-node/ _card;
/delete-node/
/delete-node/
diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi
index d541b48c7e3..75776decd21 100644
--- a/arch/arm/dts/r8a774b1.dtsi
+++ b/arch/arm/dts/r8a774b1.dtsi
@@ -1562,7 +1562,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -2238,8 +2238,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2250,6 +2250,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A774B1_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2265,8 +2267,8 @@
<0x0200 0 0xeea0 0 0xeea0 0
0x0020>,
<0x0200 0 0xc000 0 0xc000 0
0x0800>,
<0x4200 0 0xc800 0 0xc800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2277,6 +2279,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A774B1_PD_ALWAYS_ON>;
resets = < 318>;
+ iommu-map = <0 _hc 1 1>;
+ iommu-map-mask = <0>;
[PATCH 15/19] ARM: dts: renesas: Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3
Synchronize RZ R8A774A1 RZ/G2M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/beacon-renesom-baseboard.dtsi | 45 ++
arch/arm/dts/beacon-renesom-som.dtsi | 2 +-
arch/arm/dts/hihope-common.dtsi| 21 --
arch/arm/dts/r8a774a1-beacon-rzg2m-kit.dts | 21 --
arch/arm/dts/r8a774a1-u-boot.dtsi | 1 -
arch/arm/dts/r8a774a1.dtsi | 14 ---
6 files changed, 57 insertions(+), 47 deletions(-)
diff --git a/arch/arm/dts/beacon-renesom-baseboard.dtsi
b/arch/arm/dts/beacon-renesom-baseboard.dtsi
index 8166e3c1ff4..2e9927b9773 100644
--- a/arch/arm/dts/beacon-renesom-baseboard.dtsi
+++ b/arch/arm/dts/beacon-renesom-baseboard.dtsi
@@ -367,7 +367,7 @@
assigned-clocks = <_bb 1>, <_bb 2>,
<_bb 3>, <_bb 4>;
- assigned-clock-rates = <2400>, <2400>, <2400>,
+ assigned-clock-rates = <2400>, <2400>, <24576000>,
<24576000>;
OUT1 {
@@ -437,20 +437,6 @@
};
};
- /* 0 - lcd_reset */
- /* 1 - lcd_pwr */
- /* 2 - lcd_select */
- /* 3 - backlight-enable */
- /* 4 - Touch_shdwn */
- /* 5 - LCD_H_pol */
- /* 6 - lcd_V_pol */
- gpio_exp1: gpio@20 {
- compatible = "onnn,pca9654";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
touchscreen@26 {
compatible = "ilitek,ili2117";
reg = <0x26>;
@@ -482,6 +468,16 @@
};
};
};
+
+ gpio_exp1: gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "lcd_reset", "lcd_pwr", "lcd_select",
+ "backlight-enable", "Touch_shdwn",
+ "LCD_H_pol", "lcd_V_pol";
+ };
};
{
@@ -638,6 +634,25 @@
#clock-cells = <1>;
clock-frequency = <11289600>;
+ /* Reference versaclock instead of audio_clk_a */
+ clocks = < CPG_MOD 1005>,
+< CPG_MOD 1006>, < CPG_MOD 1007>,
+< CPG_MOD 1008>, < CPG_MOD 1009>,
+< CPG_MOD 1010>, < CPG_MOD 1011>,
+< CPG_MOD 1012>, < CPG_MOD 1013>,
+< CPG_MOD 1014>, < CPG_MOD 1015>,
+< CPG_MOD 1022>, < CPG_MOD 1023>,
+< CPG_MOD 1024>, < CPG_MOD 1025>,
+< CPG_MOD 1026>, < CPG_MOD 1027>,
+< CPG_MOD 1028>, < CPG_MOD 1029>,
+< CPG_MOD 1030>, < CPG_MOD 1031>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1020>, < CPG_MOD 1021>,
+< CPG_MOD 1019>, < CPG_MOD 1018>,
+<_bb 4>, <_clk_b>,
+<_clk_c>,
+< CPG_CORE CPG_AUDIO_CLK_I>;
+
status = "okay";
ports {
diff --git a/arch/arm/dts/beacon-renesom-som.dtsi
b/arch/arm/dts/beacon-renesom-som.dtsi
index d3fc8ffd5b4..68b04e56ae5 100644
--- a/arch/arm/dts/beacon-renesom-som.dtsi
+++ b/arch/arm/dts/beacon-renesom-som.dtsi
@@ -59,7 +59,7 @@
status = "okay";
phy0: ethernet-phy@0 {
- compatible = "ethernet-phy-id004d.d074",
+ compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
interrupt-parent = <>;
diff --git a/arch/arm/dts/hihope-common.dtsi b/arch/arm/dts/hihope-common.dtsi
index b1eb6a08029..83104af2813 100644
--- a/arch/arm/dts/hihope-common.dtsi
+++ b/arch/arm/dts/hihope-common.dtsi
@@ -3,15 +3,26 @@
* Device Tree Source for the HiHope RZ/G2H Rev.4.0 and
* HiHope RZ/G2[MN] Rev.[2.0/3.0/4.0] main board common parts
*
- * Copyright (C) 2021 Renesas Electronics Corp.
+ * Copyright (C) 2019 Renesas Electronics Corp.
*/
#include
/ {
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 = _pmic;
serial0 =
serial1 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
};
chosen {
@@ -50,7 +61,7 @@
};
};
- reg_1p8v: regulator0 {
+ reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <180>;
@@ -59,7 +70,7 @@
regulator-always-on;
};
- reg_3p3v: regulator1 {
+ reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
[PATCH 14/19] ARM: dts: renesas: Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3
Synchronize RZ R7S72100 RZ/A1 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r7s72100-gr-peach.dts | 3 ++
arch/arm/dts/r7s72100.dtsi | 56 ++
2 files changed, 45 insertions(+), 14 deletions(-)
diff --git a/arch/arm/dts/r7s72100-gr-peach.dts
b/arch/arm/dts/r7s72100-gr-peach.dts
index 70d034c26dd..105f9c71f9f 100644
--- a/arch/arm/dts/r7s72100-gr-peach.dts
+++ b/arch/arm/dts/r7s72100-gr-peach.dts
@@ -41,6 +41,9 @@
bank-width = <4>;
device-width = <1>;
+ clocks = <_clks R7S72100_CLK_SPIBSC0>;
+ power-domains = <_clocks>;
+
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/arm/dts/r7s72100.dtsi b/arch/arm/dts/r7s72100.dtsi
index 2211f88ede2..b07b71307f2 100644
--- a/arch/arm/dts/r7s72100.dtsi
+++ b/arch/arm/dts/r7s72100.dtsi
@@ -313,9 +313,9 @@
mmcif: mmc@e804c800 {
compatible = "renesas,mmcif-r7s72100",
"renesas,sh-mmcif";
reg = <0xe804c800 0x80>;
- interrupts = ;
+ interrupts = ,
+,
+;
clocks = <_clks R7S72100_CLK_MMCIF>;
power-domains = <_clocks>;
reg-io-width = <4>;
@@ -323,12 +323,12 @@
status = "disabled";
};
- sdhi0: sd@e804e000 {
+ sdhi0: mmc@e804e000 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e000 0x100>;
- interrupts = ;
+ interrupts = ,
+,
+;
clocks = <_clks R7S72100_CLK_SDHI00>,
<_clks R7S72100_CLK_SDHI01>;
@@ -339,12 +339,12 @@
status = "disabled";
};
- sdhi1: sd@e804e800 {
+ sdhi1: mmc@e804e800 {
compatible = "renesas,sdhi-r7s72100";
reg = <0xe804e800 0x100>;
- interrupts = ;
+ interrupts = ,
+,
+;
clocks = <_clks R7S72100_CLK_SDHI10>,
<_clks R7S72100_CLK_SDHI11>;
@@ -467,11 +467,12 @@
#clock-cells = <1>;
compatible = "renesas,r7s72100-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0xfcfe0438 4>;
- clocks = <_clk>, <_clk>, <_clk>, <_clk>;
+ clocks = <_clk>, <_clk>, <_clk>, <_clk>,
<_clk>, <_clk>;
clock-indices = <
R7S72100_CLK_I2C0 R7S72100_CLK_I2C1
R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+ R7S72100_CLK_SPIBSC0 R7S72100_CLK_SPIBSC1
>;
- clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+ clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3",
"spibsc0", "spibsc1";
};
mstp10_clks: mstp10_clks@fcfe043c {
@@ -498,7 +499,7 @@
clock-output-names = "sdhi00", "sdhi01", "sdhi10",
"sdhi11";
};
- pinctrl: pin-controller@fcfe3000 {
+ pinctrl: pinctrl@fcfe3000 {
compatible = "renesas,r7s72100-ports";
reg = <0xfcfe3000 0x4230>;
@@ -607,6 +608,8 @@
,
,
;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <_clks R7S72100_CLK_I2C0>;
clock-frequency = <10>;
power-domains = <_clocks>;
@@ -626,6 +629,8 @@
,
,
;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <_clks R7S72100_CLK_I2C1>;
clock-frequency = <10>;
power-domains = <_clocks>;
@@ -645,6 +650,8 @@
,
,
;
+ interrupt-names = "tei", "ri", "ti", "spi", "sti",
+ "naki", "ali", "tmoi";
clocks = <_clks R7S72100_CLK_I2C2>;
[PATCH 13/19] ARM: dts: renesas: Synchronize R-Car R8A779G0 V4H DTs with Linux 6.5.3
Synchronize R-Car R8A779G0 V4H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi | 172 +++
arch/arm/dts/r8a779g0-white-hawk.dts | 44 +
arch/arm/dts/r8a779g0.dtsi| 1006 -
3 files changed, 1216 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
index ae7522b60e5..f8537f7ea4d 100644
--- a/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779g0-white-hawk-csi-dsi.dtsi
@@ -5,7 +5,63 @@
* Copyright (C) 2022 Glider bv
*/
+#include
+
+ {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi40_in: endpoint {
+ bus-type = ;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <_out0>;
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ csi41_in: endpoint {
+ bus-type = ;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <_out1>;
+ };
+ };
+ };
+};
+
{
+ pca9654_a: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ pca9654_b: gpio@22 {
+ compatible = "onnn,pca9654";
+ reg = <0x22>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
eeprom@52 {
compatible = "rohm,br24g01", "atmel,24c01";
label = "csi-dsi-sub-board-id";
@@ -13,3 +69,119 @@
pagesize = <8>;
};
};
+
+ {
+ gmsl0: gmsl-deserializer@49 {
+ compatible = "maxim,max96712";
+ reg = <0x49>;
+ enable-gpios = <_a 0 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ max96712_out0: endpoint {
+ bus-type = ;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <_in>;
+ };
+ };
+ };
+ };
+
+ gmsl1: gmsl-deserializer@4b {
+ compatible = "maxim,max96712";
+ reg = <0x4b>;
+ enable-gpios = <_b 0 GPIO_ACTIVE_HIGH>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@4 {
+ reg = <4>;
+ max96712_out1: endpoint {
+ bus-type = ;
+ clock-lanes = <0>;
+ data-lanes = <1 2 3>;
+ remote-endpoint = <_in>;
+ };
+ };
+ };
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+};
diff --git a/arch/arm/dts/r8a779g0-white-hawk.dts
b/arch/arm/dts/r8a779g0-white-hawk.dts
index 04a2b6b83e7..eff1ef6e2cc 100644
--- a/arch/arm/dts/r8a779g0-white-hawk.dts
+++ b/arch/arm/dts/r8a779g0-white-hawk.dts
@@ -13,6 +13,33 @@
/ {
model = "Renesas White Hawk CPU and Breakout boards based on r8a779g0";
compatible = "renesas,white-hawk-breakout", "renesas,white-hawk-cpu",
"renesas,r8a779g0";
+
+ can_transceiver0: can-phy0 {
+ compatible = "nxp,tjr1443";
+ #phy-cells = <0>;
+ enable-gpios = < 3
[PATCH 12/19] ARM: dts: renesas: Synchronize R-Car R8A779F0 S4 DTs with Linux 6.5.3
Synchronize R-Car R8A779F0 S4 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779f0.dtsi | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/arch/arm/dts/r8a779f0.dtsi b/arch/arm/dts/r8a779f0.dtsi
index f20b612b2b9..1d5426e6293 100644
--- a/arch/arm/dts/r8a779f0.dtsi
+++ b/arch/arm/dts/r8a779f0.dtsi
@@ -1059,7 +1059,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee48 0 0x2>;
- renesas,ipmmu-main = <_mm 10>;
+ renesas,ipmmu-main = <_mm>;
power-domains = < R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1068,7 +1068,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xee4c 0 0x2>;
- renesas,ipmmu-main = <_mm 19>;
+ renesas,ipmmu-main = <_mm>;
power-domains = < R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1077,7 +1077,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed0 0 0x2>;
- renesas,ipmmu-main = <_mm 0>;
+ renesas,ipmmu-main = <_mm>;
power-domains = < R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1086,7 +1086,7 @@
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";
reg = <0 0xeed4 0 0x2>;
- renesas,ipmmu-main = <_mm 2>;
+ renesas,ipmmu-main = <_mm>;
power-domains = < R8A779F0_PD_ALWAYS_ON>;
#iommu-cells = <1>;
};
@@ -1108,8 +1108,7 @@
interrupt-controller;
reg = <0x0 0xf100 0 0x2>,
<0x0 0xf106 0 0x11>;
- interrupts = ;
+ interrupts = ;
};
prr: chipid@fff00044 {
@@ -1119,7 +1118,7 @@
};
thermal-zones {
- sensor_thermal1: sensor1-thermal {
+ sensor_thermal_rtcore: sensor1-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = < 0>;
@@ -1133,7 +1132,7 @@
};
};
- sensor_thermal2: sensor2-thermal {
+ sensor_thermal_apcore0: sensor2-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = < 1>;
@@ -1147,7 +1146,7 @@
};
};
- sensor_thermal3: sensor3-thermal {
+ sensor_thermal_apcore4: sensor3-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = < 2>;
@@ -1164,10 +1163,10 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = < GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>,
- < GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
| IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = < GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ < GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ < GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ < GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
ufs30_clk: ufs30-clk {
--
2.40.1
[PATCH 11/19] ARM: dts: renesas: Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3
Synchronize R-Car R8A779A0 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi | 5 +
arch/arm/dts/r8a779a0-falcon.dts | 11 ++-
arch/arm/dts/r8a779a0.dtsi| 110 --
3 files changed, 95 insertions(+), 31 deletions(-)
diff --git a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
index e06b8eda85e..dbc8dcab109 100644
--- a/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
+++ b/arch/arm/dts/r8a779a0-falcon-csi-dsi.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2021 Glider bv
*/
+#include
+
{
status = "okay";
@@ -105,6 +107,7 @@
port@4 {
reg = <4>;
max96712_out0: endpoint {
+ bus-type = ;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <_in>;
@@ -125,6 +128,7 @@
port@4 {
reg = <4>;
max96712_out1: endpoint {
+ bus-type = ;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
@@ -146,6 +150,7 @@
port@4 {
reg = <4>;
max96712_out2: endpoint {
+ bus-type = ;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
lane-polarities = <0 0 0 0 1>;
diff --git a/arch/arm/dts/r8a779a0-falcon.dts b/arch/arm/dts/r8a779a0-falcon.dts
index b2e67b82caf..63db822e5f4 100644
--- a/arch/arm/dts/r8a779a0-falcon.dts
+++ b/arch/arm/dts/r8a779a0-falcon.dts
@@ -37,8 +37,12 @@
};
};
+_clk {
+ clock-frequency = <4000>;
+};
+
{
- pinctrl-0 = <_pins>, <_pins>;
+ pinctrl-0 = <_pins>, <_pins>, <_clk_pins>;
pinctrl-names = "default";
status = "okay";
@@ -80,6 +84,11 @@
};
+ can_clk_pins: can-clk {
+ groups = "can_clk";
+ function = "can_clk";
+ };
+
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
diff --git a/arch/arm/dts/r8a779a0.dtsi b/arch/arm/dts/r8a779a0.dtsi
index ed9400f903c..4e67a035649 100644
--- a/arch/arm/dts/r8a779a0.dtsi
+++ b/arch/arm/dts/r8a779a0.dtsi
@@ -606,7 +606,8 @@
};
canfd: can@e666 {
- compatible = "renesas,r8a779a0-canfd";
+ compatible = "renesas,r8a779a0-canfd",
+"renesas,rcar-gen4-canfd";
reg = <0 0xe666 0 0x8000>;
interrupts = ,
;
@@ -656,7 +657,7 @@
avb0: ethernet@e680 {
compatible = "renesas,etheravb-r8a779a0",
-"renesas,etheravb-rcar-gen3";
+"renesas,etheravb-rcar-gen4";
reg = <0 0xe680 0 0x800>;
interrupts = ,
,
@@ -704,7 +705,7 @@
avb1: ethernet@e681 {
compatible = "renesas,etheravb-r8a779a0",
-"renesas,etheravb-rcar-gen3";
+"renesas,etheravb-rcar-gen4";
reg = <0 0xe681 0 0x800>;
interrupts = ,
,
@@ -752,7 +753,7 @@
avb2: ethernet@e682 {
compatible = "renesas,etheravb-r8a779a0",
-"renesas,etheravb-rcar-gen3";
+"renesas,etheravb-rcar-gen4";
reg = <0 0xe682 0 0x1000>;
interrupts = ,
,
@@ -800,7 +801,7 @@
avb3: ethernet@e683 {
compatible = "renesas,etheravb-r8a779a0",
-"renesas,etheravb-rcar-gen3";
+"renesas,etheravb-rcar-gen4";
reg = <0 0xe683 0 0x1000>;
interrupts = ,
,
@@ -848,7 +849,7 @@
avb4: ethernet@e684 {
compatible = "renesas,etheravb-r8a779a0",
-"renesas,etheravb-rcar-gen3";
+
[PATCH 10/19] ARM: dts: renesas: Synchronize R-Car R8A77995 D3 DTs with Linux 6.5.3
Synchronize R-Car R8A77995 D3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77995.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a77995.dtsi b/arch/arm/dts/r8a77995.dtsi
index f040d03e0a8..e25024a7b66 100644
--- a/arch/arm/dts/r8a77995.dtsi
+++ b/arch/arm/dts/r8a77995.dtsi
@@ -1037,7 +1037,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
--
2.40.1
[PATCH 09/19] ARM: dts: renesas: Synchronize R-Car R8A77990 E3 DTs with Linux 6.5.3
Synchronize R-Car R8A77990 E3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77990.dtsi | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/r8a77990.dtsi b/arch/arm/dts/r8a77990.dtsi
index 3053b4b2149..1be0b99c15e 100644
--- a/arch/arm/dts/r8a77990.dtsi
+++ b/arch/arm/dts/r8a77990.dtsi
@@ -49,17 +49,14 @@
opp-shared;
opp-8 {
opp-hz = /bits/ 64 <8>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
};
opp-10 {
opp-hz = /bits/ 64 <10>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
};
opp-12 {
opp-hz = /bits/ 64 <12>;
- opp-microvolt = <82>;
clock-latency-ns = <30>;
opp-suspend;
};
@@ -1469,7 +1466,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -1873,8 +1870,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x4000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -1885,6 +1882,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A77990_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.40.1
[PATCH 08/19] ARM: dts: renesas: Synchronize R-Car R8A77980 V3H DTs with Linux 6.5.3
Synchronize R-Car R8A77980 V3H DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/condor-common.dtsi | 1 +
arch/arm/dts/r8a77980-condor.dts | 8
arch/arm/dts/r8a77980-v3hsk.dts | 1 +
arch/arm/dts/r8a77980.dtsi | 5 -
4 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/condor-common.dtsi b/arch/arm/dts/condor-common.dtsi
index dfbe35bf46e..7c34d14dcd7 100644
--- a/arch/arm/dts/condor-common.dtsi
+++ b/arch/arm/dts/condor-common.dtsi
@@ -21,6 +21,7 @@
chosen {
stdout-path = "serial0:115200n8";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
};
d1_8v: regulator-2 {
diff --git a/arch/arm/dts/r8a77980-condor.dts b/arch/arm/dts/r8a77980-condor.dts
index 1d326552e2f..68d1f1d53b3 100644
--- a/arch/arm/dts/r8a77980-condor.dts
+++ b/arch/arm/dts/r8a77980-condor.dts
@@ -14,3 +14,11 @@
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
};
+
+ {
+ eeprom@50 {
+ compatible = "rohm,br24t01", "atmel,24c01";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+};
diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts
index d168b0e7747..77d22df25ff 100644
--- a/arch/arm/dts/r8a77980-v3hsk.dts
+++ b/arch/arm/dts/r8a77980-v3hsk.dts
@@ -122,6 +122,7 @@
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
+ rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/dts/r8a77980.dtsi b/arch/arm/dts/r8a77980.dtsi
index c4ac28a0f71..5ed2daaca1f 100644
--- a/arch/arm/dts/r8a77980.dtsi
+++ b/arch/arm/dts/r8a77980.dtsi
@@ -1386,7 +1386,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x020>,
<0x0200 0 0x3000 0 0x3000 0
0x800>,
<0x4200 0 0x3800 0 0x3800 0
0x800>;
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -1399,6 +1400,8 @@
resets = < 319>;
phys = <_phy>;
phy-names = "pcie";
+ iommu-map = <0 _vi0 5 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.40.1
[PATCH 07/19] ARM: dts: renesas: Synchronize R-Car R8A77970 V3M DTs with Linux 6.5.3
Synchronize R-Car R8A77970 V3M DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77970-eagle.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/r8a77970-eagle.dts b/arch/arm/dts/r8a77970-eagle.dts
index 004a5eacd46..405404c0843 100644
--- a/arch/arm/dts/r8a77970-eagle.dts
+++ b/arch/arm/dts/r8a77970-eagle.dts
@@ -287,6 +287,9 @@
};
{
+ pinctrl-0 = <_clk_pins>;
+ pinctrl-names = "default";
+
avb_pins: avb0 {
groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk";
function = "avb0";
@@ -316,6 +319,11 @@
groups = "scif0_data";
function = "scif0";
};
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
};
{
@@ -391,3 +399,7 @@
status = "okay";
};
+
+_clk {
+ clock-frequency = <14745600>;
+};
--
2.40.1
[PATCH 06/19] ARM: dts: renesas: Synchronize R-Car R8A77965 M3-N DTs with Linux 6.5.3
Synchronize R-Car R8A77965 M3-N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77965.dtsi | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/r8a77965.dtsi b/arch/arm/dts/r8a77965.dtsi
index 997f29521f6..c7582003849 100644
--- a/arch/arm/dts/r8a77965.dtsi
+++ b/arch/arm/dts/r8a77965.dtsi
@@ -75,13 +75,11 @@
opp-hz = /bits/ 64 <16>;
opp-microvolt = <90>;
clock-latency-ns = <30>;
- turbo-mode;
};
opp-17 {
opp-hz = /bits/ 64 <17>;
opp-microvolt = <90>;
clock-latency-ns = <30>;
- turbo-mode;
};
opp-18 {
opp-hz = /bits/ 64 <18>;
@@ -1733,7 +1731,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -2425,8 +2423,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2437,6 +2435,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A77965_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2452,8 +2452,8 @@
<0x0200 0 0xeea0 0 0xeea0 0
0x0020>,
<0x0200 0 0xc000 0 0xc000 0
0x0800>,
<0x4200 0 0xc800 0 0xc800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2464,6 +2464,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A77965_PD_ALWAYS_ON>;
resets = < 318>;
+ iommu-map = <0 _hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.40.1
[PATCH 04/19] ARM: dts: renesas: Synchronize R-Car R8A77951 H3 DTs with Linux 6.5.3
Synchronize R-Car R8A77951 H3 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77951.dtsi | 15 +-
arch/arm/dts/salvator-common.dtsi| 253 +++
arch/arm/dts/salvator-xs.dtsi| 56 +
arch/arm/dts/ulcb-audio-graph-card.dtsi | 85
arch/arm/dts/ulcb-audio-graph-card2.dtsi | 26 +++
arch/arm/dts/ulcb.dtsi | 74 ++-
6 files changed, 408 insertions(+), 101 deletions(-)
create mode 100644 arch/arm/dts/ulcb-audio-graph-card.dtsi
create mode 100644 arch/arm/dts/ulcb-audio-graph-card2.dtsi
diff --git a/arch/arm/dts/r8a77951.dtsi b/arch/arm/dts/r8a77951.dtsi
index 07c8763c1e7..6d15229d25a 100644
--- a/arch/arm/dts/r8a77951.dtsi
+++ b/arch/arm/dts/r8a77951.dtsi
@@ -75,7 +75,6 @@
opp-hz = /bits/ 64 <16>;
opp-microvolt = <90>;
clock-latency-ns = <30>;
- turbo-mode;
};
opp-17 {
opp-hz = /bits/ 64 <17>;
@@ -1998,7 +1997,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -2779,8 +2778,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x4000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2791,6 +2790,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A7795_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2806,8 +2807,8 @@
<0x0200 0 0xeea0 0 0xeea0 0
0x0020>,
<0x0200 0 0xc000 0 0xc000 0
0x0800>,
<0x4200 0 0xc800 0 0xc800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x4000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2818,6 +2819,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A7795_PD_ALWAYS_ON>;
resets = < 318>;
+ iommu-map = <0 _hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
diff --git a/arch/arm/dts/salvator-common.dtsi
b/arch/arm/dts/salvator-common.dtsi
index 23fdd1115b2..4a3d5037821 100644
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -33,9 +33,20 @@
/ {
aliases {
+ i2c0 =
+ i2c1 =
+ i2c2 =
+ i2c3 =
+ i2c4 =
+ i2c5 =
+ i2c6 =
+ i2c7 = _dvfs;
serial0 =
serial1 =
ethernet0 =
+ mmc0 =
+ mmc1 =
+ mmc2 =
};
chosen {
@@ -94,6 +105,7 @@
port {
hdmi0_con: endpoint {
+ remote-endpoint = <_dw_hdmi0_out>;
};
};
};
@@ -166,7 +178,7 @@
};
};
- reg_1p8v: regulator0 {
+ reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <180>;
@@ -175,7 +187,7 @@
regulator-always-on;
};
- reg_3p3v: regulator1 {
+ reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name
[PATCH 05/19] ARM: dts: renesas: Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ DTs with Linux 6.5.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a77960.dtsi | 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/r8a77960.dtsi b/arch/arm/dts/r8a77960.dtsi
index 1424d4ad941..17062ec506b 100644
--- a/arch/arm/dts/r8a77960.dtsi
+++ b/arch/arm/dts/r8a77960.dtsi
@@ -70,13 +70,11 @@
opp-hz = /bits/ 64 <16>;
opp-microvolt = <90>;
clock-latency-ns = <30>;
- turbo-mode;
};
opp-17 {
opp-hz = /bits/ 64 <17>;
opp-microvolt = <90>;
clock-latency-ns = <30>;
- turbo-mode;
};
opp-18 {
opp-hz = /bits/ 64 <18>;
@@ -1870,7 +1868,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>; <_sound>;
* Multi DAI : #sound-dai-cells = <1>; <_sound N>;
@@ -2567,8 +2565,8 @@
<0x0200 0 0xfe20 0 0xfe20 0
0x0020>,
<0x0200 0 0x3000 0 0x3000 0
0x0800>,
<0x4200 0 0x3800 0 0x3800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2579,6 +2577,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A7796_PD_ALWAYS_ON>;
resets = < 319>;
+ iommu-map = <0 _hc 0 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
@@ -2594,8 +2594,8 @@
<0x0200 0 0xeea0 0 0xeea0 0
0x0020>,
<0x0200 0 0xc000 0 0xc000 0
0x0800>,
<0x4200 0 0xc800 0 0xc800 0
0x0800>;
- /* Map all possible DDR as inbound ranges */
- dma-ranges = <0x4200 0 0x4000 0 0x4000 0
0x8000>;
+ /* Map all possible DDR/IOMMU as inbound ranges */
+ dma-ranges = <0x4200 0 0x 0 0x 1
0x>;
interrupts = ,
,
;
@@ -2606,6 +2606,8 @@
clock-names = "pcie", "pcie_bus";
power-domains = < R8A7796_PD_ALWAYS_ON>;
resets = < 318>;
+ iommu-map = <0 _hc 1 1>;
+ iommu-map-mask = <0>;
status = "disabled";
};
--
2.40.1
[PATCH 03/19] ARM: dts: renesas: Synchronize R-Car R8A7794 E2 DTs with Linux 6.5.3
Synchronize R-Car R8A7794 E2 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a7794.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/r8a7794.dtsi b/arch/arm/dts/r8a7794.dtsi
index 7aa781ff3bf..371dd4715dd 100644
--- a/arch/arm/dts/r8a7794.dtsi
+++ b/arch/arm/dts/r8a7794.dtsi
@@ -955,7 +955,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>;
<_sound>;
* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
--
2.40.1
[PATCH 02/19] ARM: dts: renesas: Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N DTs with Linux 6.5.3
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a7791.dtsi | 4 ++--
arch/arm/dts/r8a7793.dtsi | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index d8f91d9f42a..b9d34147628 100644
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -1223,7 +1223,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>;
<_sound>;
* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
@@ -1365,7 +1365,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
-interrupts = ;
+ interrupts = ;
dmas = < 0x03>, < 0x04>,
< 0x49>, < 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/dts/r8a7793.dtsi b/arch/arm/dts/r8a7793.dtsi
index 9ebe7bfaf0e..f51bf687f4b 100644
--- a/arch/arm/dts/r8a7793.dtsi
+++ b/arch/arm/dts/r8a7793.dtsi
@@ -988,7 +988,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>;
<_sound>;
* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
@@ -,7 +,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
ssi1: ssi-1 {
-interrupts = ;
+ interrupts = ;
dmas = < 0x03>, < 0x04>,
< 0x49>, < 0x4a>;
dma-names = "rx", "tx", "rxu", "txu";
--
2.40.1
[PATCH 01/19] ARM: dts: renesas: Synchronize R-Car R8A7790 H2 DTs with Linux 6.5.3
Synchronize R-Car R8A7790 H2 DTs with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
arch/arm/dts/r8a7790.dtsi | 85 ++-
1 file changed, 83 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/r8a7790.dtsi b/arch/arm/dts/r8a7790.dtsi
index db171e3c62f..46fb81f5062 100644
--- a/arch/arm/dts/r8a7790.dtsi
+++ b/arch/arm/dts/r8a7790.dtsi
@@ -376,6 +376,17 @@
reg = <0 0xe606 0 0x250>;
};
+ tpu: pwm@e60f {
+ compatible = "renesas,tpu-r8a7790", "renesas,tpu";
+ reg = <0 0xe60f 0 0x148>;
+ interrupts = ;
+ clocks = < CPG_MOD 304>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 304>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
cpg: clock-controller@e615 {
compatible = "renesas,r8a7790-cpg-mssr";
reg = <0 0xe615 0 0x1000>;
@@ -1037,6 +1048,76 @@
status = "disabled";
};
+ pwm0: pwm@e6e3 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e3 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@e6e31000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e31000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@e6e32000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e32000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@e6e33000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e33000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@e6e34000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e34000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@e6e35000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e35000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@e6e36000 {
+ compatible = "renesas,pwm-r8a7790", "renesas,pwm-rcar";
+ reg = <0 0xe6e36000 0 0x8>;
+ clocks = < CPG_MOD 523>;
+ power-domains = < R8A7790_PD_ALWAYS_ON>;
+ resets = < 523>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+
can0: can@e6e8 {
compatible = "renesas,can-r8a7790",
"renesas,rcar-gen2-can";
@@ -1109,7 +1190,7 @@
rcar_sound: sound@ec50 {
/*
-* #sound-dai-cells is required
+* #sound-dai-cells is required if simple-card
*
* Single DAI : #sound-dai-cells = <0>;
<_sound>;
* Multi DAI : #sound-dai-cells = <1>;
<_sound N>;
@@ -1252,7 +1333,7 @@
dma-names = "rx", "tx", "rxu", "txu";
};
[PATCH 20/20] clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3
Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774e1-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
index 617fa769dcf..28d8a8832ae 100644
--- a/drivers/clk/renesas/r8a774e1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774e1-cpg-mssr.c
@@ -48,7 +48,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774e1_core_clks[] = {
+static const struct cpg_core_clk r8a774e1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a774e1_core_clks[] = {
DEF_BASE("r", R8A774E1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774e1_mod_clks[] __initconst = {
DEF_MOD("fdp1-1",118, R8A774E1_CLK_S0D1),
DEF_MOD("fdp1-0",119, R8A774E1_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A774E1_CLK_S0D6),
@@ -286,7 +286,7 @@ static const struct mssr_mod_clk r8a774e1_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,192,1, 128,1, 16, },
--
2.40.1
[PATCH 19/20] clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3
Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774c0-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
index 802a9c0b119..4768ceb0fa6 100644
--- a/drivers/clk/renesas/r8a774c0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774c0-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774c0_core_clks[] = {
+static const struct cpg_core_clk r8a774c0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -131,7 +131,7 @@ static const struct cpg_core_clk r8a774c0_core_clks[] = {
DEF_GEN3_RCKSEL("r", R8A774C0_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
+static const struct mssr_mod_clk r8a774c0_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774C0_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A774C0_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A774C0_CLK_S3D2C),
@@ -259,7 +259,7 @@ static const struct mssr_mod_clk r8a774c0_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL divPLL1 mult/div PLL3 mult/div */
{ 1,100,3, 100,3, },
{ 1,100,3, 58,3, },
--
2.40.1
[PATCH 18/20] clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3
Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
index b5927c7892c..60f4f1da519 100644
--- a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -46,7 +46,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774b1_core_clks[] = {
+static const struct cpg_core_clk r8a774b1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -118,7 +118,7 @@ static const struct cpg_core_clk r8a774b1_core_clks[] = {
DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774b1_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
@@ -272,7 +272,7 @@ static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,192,1, 128,1, 16, },
--
2.40.1
[PATCH 17/20] clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3
Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a774a1-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
index 1f76d6b2c2e..6280061af89 100644
--- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a774a1_core_clks[] = {
+static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -121,7 +121,7 @@ static const struct cpg_core_clk r8a774a1_core_clks[] = {
DEF_BASE("r", R8A774A1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
+static const struct mssr_mod_clk r8a774a1_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A774A1_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A774A1_CLK_S3D2),
DEF_MOD("tmu2", 123, R8A774A1_CLK_S3D2),
@@ -276,7 +276,7 @@ static const struct mssr_mod_clk r8a774a1_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,192,1, 128,1, 16, },
--
2.40.1
[PATCH 16/20] clk: renesas: Synchronize R8A779G0 V4H clock tables with Linux 6.5.3
Synchronize R-Car R8A779G0 V4H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
The PLL2_VAR is not implemented yet and PLL2 is still configured
as regular PLL2 only.
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a779g0-cpg-mssr.c | 28 +++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
index 8625e8a2d36..219024a7416 100644
--- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
@@ -56,7 +56,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a779g0_core_clks[] = {
+static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -142,6 +142,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
DEF_FIXED("vcbus", R8A779G0_CLK_VCBUS, CLK_VC, 1, 1),
DEF_FIXED("vcbusd2",R8A779G0_CLK_VCBUSD2, CLK_VC, 2, 1),
DEF_DIV6P1("canfd", R8A779G0_CLK_CANFD, CLK_PLL5_DIV4, 0x878),
+ DEF_DIV6P1("csi", R8A779G0_CLK_CSI, CLK_PLL5_DIV4, 0x880),
DEF_FIXED("dsiref", R8A779G0_CLK_DSIREF,CLK_PLL5_DIV4, 48, 1),
DEF_DIV6P1("dsiext",R8A779G0_CLK_DSIEXT,CLK_PLL5_DIV4, 0x884),
@@ -156,11 +157,13 @@ static const struct cpg_core_clk r8a779g0_core_clks[] = {
DEF_GEN4_MDSEL("r", R8A779G0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211,R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb1", 212,R8A779G0_CLK_S0D4_HSC),
DEF_MOD("avb2", 213,R8A779G0_CLK_S0D4_HSC),
DEF_MOD("canfd0", 328,R8A779G0_CLK_SASYNCPERD2),
+ DEF_MOD("csi40",331,R8A779G0_CLK_CSI),
+ DEF_MOD("csi41",400,R8A779G0_CLK_CSI),
DEF_MOD("dis0", 411,R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink0", 415,R8A779G0_CLK_VIOBUSD2),
DEF_MOD("dsitxlink1", 416,R8A779G0_CLK_VIOBUSD2),
@@ -177,6 +180,8 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
DEF_MOD("i2c4", 522,R8A779G0_CLK_S0D6_PER),
DEF_MOD("i2c5", 523,R8A779G0_CLK_S0D6_PER),
DEF_MOD("irqc", 611,R8A779G0_CLK_CL16M),
+ DEF_MOD("ispcs0", 612,R8A779G0_CLK_S0D2_VIO),
+ DEF_MOD("ispcs1", 613,R8A779G0_CLK_S0D2_VIO),
DEF_MOD("msi0", 618,R8A779G0_CLK_MSO),
DEF_MOD("msi1", 619,R8A779G0_CLK_MSO),
DEF_MOD("msi2", 620,R8A779G0_CLK_MSO),
@@ -198,6 +203,22 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
DEF_MOD("tmu3", 716,R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tmu4", 717,R8A779G0_CLK_SASYNCPERD2),
DEF_MOD("tpu0", 718,R8A779G0_CLK_SASYNCPERD4),
+ DEF_MOD("vin00",730,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin01",731,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin02",800,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin03",801,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin04",802,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin05",803,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin06",804,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin07",805,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin10",806,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin11",807,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin12",808,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin13",809,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin14",810,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin15",811,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin16",812,R8A779G0_CLK_S0D4_VIO),
+ DEF_MOD("vin17",813,R8A779G0_CLK_S0D4_VIO),
DEF_MOD("vspd0",830,R8A779G0_CLK_VIOBUSD2),
DEF_MOD("vspd1",831,R8A779G0_CLK_VIOBUSD2),
DEF_MOD("wdt1:wdt0",907,R8A779G0_CLK_R),
@@ -209,6 +230,9 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] = {
DEF_MOD("pfc1", 916,R8A779G0_CLK_CL16M),
DEF_MOD("pfc2", 917,R8A779G0_CLK_CL16M),
DEF_MOD("pfc3", 918,R8A779G0_CLK_CL16M),
+ DEF_MOD("tsc", 919,R8A779G0_CLK_CL16M),
+ DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
+ DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
};
/*
--
2.40.1
[PATCH 15/20] clk: renesas: Synchronize R8A779F0 S4 clock tables with Linux 6.5.3
Synchronize R-Car R8A779F0 S4 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a779f0-cpg-mssr.c | 4 ++--
include/dt-bindings/clock/r8a779f0-cpg-mssr.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 7aac28ed496..643e8b8da97 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a779f0_core_clks[] = {
+static const struct cpg_core_clk r8a779f0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -123,7 +123,7 @@ static const struct cpg_core_clk r8a779f0_core_clks[] = {
DEF_GEN4_MDSEL("r", R8A779F0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779f0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
DEF_MOD("hscif0", 514,R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif1", 515,R8A779F0_CLK_SASYNCPERD1),
DEF_MOD("hscif2", 516,R8A779F0_CLK_SASYNCPERD1),
diff --git a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
index f2ae1c6a82d..c34be562495 100644
--- a/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
+++ b/include/dt-bindings/clock/r8a779f0-cpg-mssr.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
/*
* Copyright (C) 2021 Renesas Electronics Corp.
*/
--
2.40.1
[PATCH 11/20] clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.5.3
Synchronize R-Car R8A77980 V3H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77980-cpg-mssr.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a77980-cpg-mssr.c
b/drivers/clk/renesas/r8a77980-cpg-mssr.c
index f29727ddb90..f35032b95f1 100644
--- a/drivers/clk/renesas/r8a77980-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77980-cpg-mssr.c
@@ -47,7 +47,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77980_core_clks[] = {
+static const struct cpg_core_clk r8a77980_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -71,6 +71,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
DEF_RATE(".oco",CLK_OCO, 32768),
/* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77980_CLK_Z2,CLK_PLL2, 4, 1),
DEF_FIXED("ztr",R8A77980_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77980_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77980_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
@@ -110,7 +111,7 @@ static const struct cpg_core_clk r8a77980_core_clks[] = {
DEF_GEN3_MDSEL("r", R8A77980_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a77980_mod_clks[] = {
+static const struct mssr_mod_clk r8a77980_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77980_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A77980_CLK_S0D6),
DEF_MOD("tmu2", 123, R8A77980_CLK_S0D6),
@@ -149,11 +150,27 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
DEF_MOD("imp-ocv3", 529, R8A77980_CLK_S1D1),
DEF_MOD("imp-ocv2", 531, R8A77980_CLK_S1D1),
DEF_MOD("fcpvd0",603, R8A77980_CLK_S3D1),
+ DEF_MOD("vin15", 604, R8A77980_CLK_S2D1),
+ DEF_MOD("vin14", 605, R8A77980_CLK_S2D1),
+ DEF_MOD("vin13", 608, R8A77980_CLK_S2D1),
+ DEF_MOD("vin12", 612, R8A77980_CLK_S2D1),
+ DEF_MOD("vin11", 618, R8A77980_CLK_S2D1),
DEF_MOD("vspd0", 623, R8A77980_CLK_S3D1),
+ DEF_MOD("vin10", 625, R8A77980_CLK_S2D1),
+ DEF_MOD("vin9", 627, R8A77980_CLK_S2D1),
+ DEF_MOD("vin8", 628, R8A77980_CLK_S2D1),
DEF_MOD("csi41", 715, R8A77980_CLK_CSI0),
DEF_MOD("csi40", 716, R8A77980_CLK_CSI0),
DEF_MOD("du0", 724, R8A77980_CLK_S2D1),
DEF_MOD("lvds", 727, R8A77980_CLK_S2D1),
+ DEF_MOD("vin7", 804, R8A77980_CLK_S2D1),
+ DEF_MOD("vin6", 805, R8A77980_CLK_S2D1),
+ DEF_MOD("vin5", 806, R8A77980_CLK_S2D1),
+ DEF_MOD("vin4", 807, R8A77980_CLK_S2D1),
+ DEF_MOD("vin3", 808, R8A77980_CLK_S2D1),
+ DEF_MOD("vin2", 809, R8A77980_CLK_S2D1),
+ DEF_MOD("vin1", 810, R8A77980_CLK_S2D1),
+ DEF_MOD("vin0", 811, R8A77980_CLK_S2D1),
DEF_MOD("etheravb", 812, R8A77980_CLK_S3D2),
DEF_MOD("gether",813, R8A77980_CLK_S3D2),
DEF_MOD("imp3", 824, R8A77980_CLK_S1D1),
@@ -172,6 +189,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
DEF_MOD("gpio0", 912, R8A77980_CLK_CP),
DEF_MOD("can-fd",914, R8A77980_CLK_S3D2),
DEF_MOD("rpc-if",917, R8A77980_CLK_RPCD2),
+ DEF_MOD("i2c5", 919, R8A77980_CLK_S0D6),
DEF_MOD("i2c4", 927, R8A77980_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A77980_CLK_S0D6),
DEF_MOD("i2c2", 929, R8A77980_CLK_S3D2),
@@ -195,7 +213,7 @@ static const struct mssr_mod_clk r8a77980_mod_clks[] = {
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[4] __initconst = {
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,160,1, 160,1, 19, },
--
2.40.1
[PATCH 14/20] clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.5.3
Synchronize R-Car R8A779A0 V3U clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a779a0-cpg-mssr.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 6b7ec36ab05..652bfe4f6d3 100644
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -56,7 +56,7 @@ enum clk_ids {
DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
.offset = _offset)
-static const struct cpg_core_clk r8a779a0_core_clks[] = {
+static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -127,7 +127,7 @@ static const struct cpg_core_clk r8a779a0_core_clks[] = {
DEF_GEN4_MDSEL("r", R8A779A0_CLK_R, 29, CLK_EXTALR, 1, CLK_OCO, 1),
};
-static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
+static const struct mssr_mod_clk r8a779a0_mod_clks[] __initconst = {
DEF_MOD("avb0", 211,R8A779A0_CLK_S3D2),
DEF_MOD("avb1", 212,R8A779A0_CLK_S3D2),
DEF_MOD("avb2", 213,R8A779A0_CLK_S3D2),
@@ -165,14 +165,15 @@ static const struct mssr_mod_clk r8a779a0_mod_clks[] = {
DEF_MOD("msi3", 621,R8A779A0_CLK_MSO),
DEF_MOD("msi4", 622,R8A779A0_CLK_MSO),
DEF_MOD("msi5", 623,R8A779A0_CLK_MSO),
+ DEF_MOD("pwm0", 628,R8A779A0_CLK_S1D8),
DEF_MOD("rpc-if", 629,R8A779A0_CLK_RPCD2),
DEF_MOD("scif0",702,R8A779A0_CLK_S1D8),
DEF_MOD("scif1",703,R8A779A0_CLK_S1D8),
DEF_MOD("scif3",704,R8A779A0_CLK_S1D8),
DEF_MOD("scif4",705,R8A779A0_CLK_S1D8),
DEF_MOD("sdhi0",706,R8A779A0_CLK_SD0),
- DEF_MOD("sydm1",709,R8A779A0_CLK_S1D2),
- DEF_MOD("sydm2",710,R8A779A0_CLK_S1D2),
+ DEF_MOD("sys-dmac1",709,R8A779A0_CLK_S1D2),
+ DEF_MOD("sys-dmac2",710,R8A779A0_CLK_S1D2),
DEF_MOD("tmu0", 713,R8A779A0_CLK_CL16MCK),
DEF_MOD("tmu1", 714,R8A779A0_CLK_S1D4),
DEF_MOD("tmu2", 715,R8A779A0_CLK_S1D4),
--
2.40.1
[PATCH 13/20] clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.5.3
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77995-cpg-mssr.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c
b/drivers/clk/renesas/r8a77995-cpg-mssr.c
index 03ae863c8bc..0ef1c1d8143 100644
--- a/drivers/clk/renesas/r8a77995-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77995_core_clks[] = {
+static const struct cpg_core_clk r8a77995_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -118,7 +118,7 @@ static const struct cpg_core_clk r8a77995_core_clks[] = {
DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a77995_mod_clks[] = {
+static const struct mssr_mod_clk r8a77995_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
@@ -167,7 +167,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
DEF_MOD("mlp", 802, R8A77995_CLK_S2D1),
- DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
+ DEF_MOD("vin4", 807, R8A77995_CLK_S3D1),
DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
@@ -209,7 +209,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL divPLL1 mult/div PLL3 mult/div */
{ 1,100,3, 100,3, },
{ 1,100,3, 58, 3, },
--
2.40.1
[PATCH 12/20] clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.5.3
Synchronize R-Car R8A77990 E3 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77990-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c
b/drivers/clk/renesas/r8a77990-cpg-mssr.c
index 1864af30c8c..e5710b05933 100644
--- a/drivers/clk/renesas/r8a77990-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77990_core_clks[] = {
+static const struct cpg_core_clk r8a77990_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -132,7 +132,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] = {
DEF_GEN3_RCKSEL("r", R8A77990_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
};
-static const struct mssr_mod_clk r8a77990_mod_clks[] = {
+static const struct mssr_mod_clk r8a77990_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77990_CLK_S0D6C),
DEF_MOD("tmu3", 122, R8A77990_CLK_S3D2C),
DEF_MOD("tmu2", 123, R8A77990_CLK_S3D2C),
@@ -273,7 +273,7 @@ static const struct mssr_mod_clk r8a77990_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] __initconst = {
/* EXTAL divPLL1 mult/div PLL3 mult/div */
{ 1,100,3, 100,3, },
{ 1,100,3, 58,3, },
--
2.40.1
[PATCH 10/20] clk: renesas: Synchronize R8A77970 V3M clock tables with Linux 6.5.3
Synchronize R-Car R8A77970 V3M clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77970-cpg-mssr.c | 18 +-
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/renesas/r8a77970-cpg-mssr.c
b/drivers/clk/renesas/r8a77970-cpg-mssr.c
index f5d77df4233..32923b423fe 100644
--- a/drivers/clk/renesas/r8a77970-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77970-cpg-mssr.c
@@ -1,13 +1,12 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A77970 CPG MSSR driver
+ * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
*
- * Copyright (C) 2017-2018 Marek Vasut
+ * Copyright (C) 2017-2018 Cogent Embedded Inc.
*
- * Based on the following driver from Linux kernel:
- * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
+ * Based on r8a7795-cpg-mssr.c
*
- * Copyright (C) 2016 Glider bvba
+ * Copyright (C) 2015 Glider bvba
*/
#include
@@ -42,7 +41,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77970_core_clks[] = {
+static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -57,6 +56,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
/* Core Clock Outputs */
+ DEF_FIXED("z2", R8A77970_CLK_Z2,CLK_PLL1_DIV4, 1, 1),
DEF_FIXED("ztr",R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
DEF_FIXED("zt", R8A77970_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
@@ -87,7 +87,7 @@ static const struct cpg_core_clk r8a77970_core_clks[] = {
DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR,1, 1),
};
-static const struct mssr_mod_clk r8a77970_mod_clks[] = {
+static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
@@ -166,7 +166,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
/* EXTAL divPLL1 mult/div PLL3 mult/div */
{ 1,192,1, 96, 1, },
{ 1,192,1, 80, 1, },
--
2.40.1
[PATCH 07/20] clk: renesas: Synchronize R8A77951 H3 clock tables with Linux 6.5.3
Synchronize R-Car R8A77951 H3 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c
b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 005f6a9ecd7..0e9b9ccf979 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7795_core_clks[] = {
+static struct cpg_core_clk r8a7795_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -126,8 +126,7 @@ static const struct cpg_core_clk r8a7795_core_clks[] = {
DEF_BASE("r", R8A7795_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a7795_mod_clks[] = {
- DEF_MOD("fdp1-2",117, R8A7795_CLK_S2D1), /* ES1.x */
+static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("fdp1-1",118, R8A7795_CLK_S0D1),
DEF_MOD("fdp1-0",119, R8A7795_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7795_CLK_S0D6),
@@ -161,7 +160,6 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("pcie1", 318, R8A7795_CLK_S3D1),
DEF_MOD("pcie0", 319, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac30",326, R8A7795_CLK_S3D1),
- DEF_MOD("usb3-if1", 327, R8A7795_CLK_S3D1), /* ES1.x */
DEF_MOD("usb3-if0", 328, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac31",329, R8A7795_CLK_S3D1),
DEF_MOD("usb-dmac0", 330, R8A7795_CLK_S3D1),
@@ -186,28 +184,21 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("hscif0",520, R8A7795_CLK_S3D1),
DEF_MOD("thermal", 522, R8A7795_CLK_CP),
DEF_MOD("pwm", 523, R8A7795_CLK_S0D12),
- DEF_MOD("fcpvd3",600, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpvd2",601, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd1",602, R8A7795_CLK_S0D2),
DEF_MOD("fcpvd0",603, R8A7795_CLK_S0D2),
DEF_MOD("fcpvb1",606, R8A7795_CLK_S0D1),
DEF_MOD("fcpvb0",607, R8A7795_CLK_S0D1),
- DEF_MOD("fcpvi2",609, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpvi1",610, R8A7795_CLK_S0D1),
DEF_MOD("fcpvi0",611, R8A7795_CLK_S0D1),
- DEF_MOD("fcpf2", 613, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpf1", 614, R8A7795_CLK_S0D1),
DEF_MOD("fcpf0", 615, R8A7795_CLK_S0D1),
- DEF_MOD("fcpci1",616, R8A7795_CLK_S2D1), /* ES1.x */
- DEF_MOD("fcpci0",617, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("fcpcs", 619, R8A7795_CLK_S0D1),
- DEF_MOD("vspd3", 620, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspd2", 621, R8A7795_CLK_S0D2),
DEF_MOD("vspd1", 622, R8A7795_CLK_S0D2),
DEF_MOD("vspd0", 623, R8A7795_CLK_S0D2),
DEF_MOD("vspbc", 624, R8A7795_CLK_S0D1),
DEF_MOD("vspbd", 626, R8A7795_CLK_S0D1),
- DEF_MOD("vspi2", 629, R8A7795_CLK_S2D1), /* ES1.x */
DEF_MOD("vspi1", 630, R8A7795_CLK_S0D1),
DEF_MOD("vspi0", 631, R8A7795_CLK_S0D1),
DEF_MOD("ehci3", 700, R8A7795_CLK_S3D2),
@@ -220,7 +211,6 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD("cmm2", 709, R8A7795_CLK_S2D1),
DEF_MOD("cmm1", 710, R8A7795_CLK_S2D1),
DEF_MOD("cmm0", 711, R8A7795_CLK_S2D1),
- DEF_MOD("csi21", 713, R8A7795_CLK_CSI0), /* ES1.x */
DEF_MOD("csi20", 714, R8A7795_CLK_CSI0),
DEF_MOD("csi41", 715, R8A7795_CLK_CSI0),
DEF_MOD("csi40", 716, R8A7795_CLK_CSI0),
@@ -324,7 +314,7 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16,
[PATCH 09/20] clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.5.3
Synchronize R-Car R8A77965 M3-N clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a77965-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c
b/drivers/clk/renesas/r8a77965-cpg-mssr.c
index 58e557a95f5..8a5c1525ece 100644
--- a/drivers/clk/renesas/r8a77965-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c
@@ -50,7 +50,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a77965_core_clks[] = {
+static const struct cpg_core_clk r8a77965_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -124,7 +124,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] = {
DEF_BASE("r", R8A77965_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a77965_mod_clks[] = {
+static const struct mssr_mod_clk r8a77965_mod_clks[] __initconst = {
DEF_MOD("fdp1-0", 119,R8A77965_CLK_S0D1),
DEF_MOD("tmu4", 121,R8A77965_CLK_S0D6),
DEF_MOD("tmu3", 122,R8A77965_CLK_S3D2),
@@ -302,7 +302,7 @@ static const struct mssr_mod_clk r8a77965_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,192,1, 128,1, 16, },
--
2.40.1
[PATCH 08/20] clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux
6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7796-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c
b/drivers/clk/renesas/r8a7796-cpg-mssr.c
index 27cf62e0213..ea1f6d69062 100644
--- a/drivers/clk/renesas/r8a7796-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c
@@ -52,7 +52,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7796_core_clks[] = {
+static const struct cpg_core_clk r8a7796_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("extalr", CLK_EXTALR),
@@ -128,7 +128,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = {
DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
};
-static const struct mssr_mod_clk r8a7796_mod_clks[] = {
+static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = {
DEF_MOD("fdp1-0",119, R8A7796_CLK_S0D1),
DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6),
DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2),
@@ -299,7 +299,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = {
(((md) & BIT(19)) >> 18) | \
(((md) & BIT(17)) >> 17))
-static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
+static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst =
{
/* EXTAL divPLL1 mult/div PLL3 mult/div OSC prediv */
{ 1,192,1, 192,1, 16, },
{ 1,192,1, 128,1, 16, },
--
2.40.1
[PATCH 05/20] clk: renesas: Synchronize R8A7792 V2H clock tables with Linux 6.5.3
Synchronize R-Car R8A7792 V2H clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7792-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a7792-cpg-mssr.c
b/drivers/clk/renesas/r8a7792-cpg-mssr.c
index 5b333638ac0..496e51aa73f 100644
--- a/drivers/clk/renesas/r8a7792-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7792-cpg-mssr.c
@@ -37,7 +37,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7792_core_clks[] = {
+static const struct cpg_core_clk r8a7792_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -76,7 +76,7 @@ static const struct cpg_core_clk r8a7792_core_clks[] = {
DEF_FIXED("osc",R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
};
-static const struct mssr_mod_clk r8a7792_mod_clks[] = {
+static const struct mssr_mod_clk r8a7792_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
DEF_MOD("jpu", 106, R8A7792_CLK_M2),
DEF_MOD("tmu1", 111, R8A7792_CLK_P),
@@ -174,7 +174,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106, 200 },
{ 1, 208, 88, 200 },
{ 1, 156, 80, 150 },
--
2.40.1
[PATCH 06/20] clk: renesas: Synchronize R8A7794 E2 clock tables with Linux 6.5.3
Synchronize R-Car R8A7794 E2 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7794-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a7794-cpg-mssr.c
b/drivers/clk/renesas/r8a7794-cpg-mssr.c
index b9dd88de98e..f1828a6e543 100644
--- a/drivers/clk/renesas/r8a7794-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7794-cpg-mssr.c
@@ -38,7 +38,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7794_core_clks[] = {
+static const struct cpg_core_clk r8a7794_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -83,7 +83,7 @@ static const struct cpg_core_clk r8a7794_core_clks[] = {
DEF_DIV6P1("mmc0", R8A7794_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
};
-static const struct mssr_mod_clk r8a7794_mod_clks[] = {
+static const struct mssr_mod_clk r8a7794_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7794_CLK_MP),
DEF_MOD("vcp0", 101, R8A7794_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7794_CLK_ZS),
@@ -205,7 +205,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
*/
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 13) | \
(((md) & BIT(13)) >> 13))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[4] __initconst = {
{ 1, 208, 88, 200 },
{ 1, 156, 66, 150 },
{ 2, 240, 102, 230 },
--
2.40.1
[PATCH 04/20] clk: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N clock tables with Linux 6.5.3
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7791-cpg-mssr.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/renesas/r8a7791-cpg-mssr.c
b/drivers/clk/renesas/r8a7791-cpg-mssr.c
index fcca7be8865..dcb0fd85c52 100644
--- a/drivers/clk/renesas/r8a7791-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7791-cpg-mssr.c
@@ -1,10 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Renesas R8A7791 CPG MSSR driver
- *
- * Copyright (C) 2018 Marek Vasut
- *
- * Based on the following driver from Linux kernel:
* r8a7791 Clock Pulse Generator / Module Standby and Software Reset
*
* Copyright (C) 2015-2017 Glider bvba
@@ -43,7 +38,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7791_core_clks[] = {
+static struct cpg_core_clk r8a7791_core_clks[] __initdata = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -89,7 +84,7 @@ static const struct cpg_core_clk r8a7791_core_clks[] = {
DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7791_mod_clks[] = {
+static const struct mssr_mod_clk r8a7791_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
@@ -232,7 +227,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
--
2.40.1
[PATCH 03/20] clk: renesas: Synchronize R8A7790 H2 clock tables with Linux 6.5.3
Synchronize R-Car R8A7790 H2 clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/clk/renesas/r8a7790-cpg-mssr.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c
b/drivers/clk/renesas/r8a7790-cpg-mssr.c
index 1f3477fa6e5..686f2af0052 100644
--- a/drivers/clk/renesas/r8a7790-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c
@@ -38,7 +38,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static const struct cpg_core_clk r8a7790_core_clks[] = {
+static const struct cpg_core_clk r8a7790_core_clks[] __initconst = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
DEF_INPUT("usb_extal", CLK_USB_EXTAL),
@@ -88,7 +88,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] = {
DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
};
-static const struct mssr_mod_clk r8a7790_mod_clks[] = {
+static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = {
DEF_MOD("msiof0", 0, R8A7790_CLK_MP),
DEF_MOD("vcp1", 100, R8A7790_CLK_ZS),
DEF_MOD("vcp0", 101, R8A7790_CLK_ZS),
@@ -230,7 +230,7 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
#define CPG_PLL_CONFIG_INDEX(md) md) & BIT(14)) >> 12) | \
(((md) & BIT(13)) >> 12) | \
(((md) & BIT(19)) >> 19))
-static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
+static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = {
{ 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
{ 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
};
--
2.40.1
[PATCH 02/20] clk: renesas: Synchronize R8A779F0 S4 DT headers with Linux 6.5.3
Synchronize R-Car R8A779F0 S4 DT headers with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- include/dt-bindings/power/r8a779f0-sysc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/power/r8a779f0-sysc.h b/include/dt-bindings/power/r8a779f0-sysc.h index 0ec8ad727ed..cde1536e9ed 100644 --- a/include/dt-bindings/power/r8a779f0-sysc.h +++ b/include/dt-bindings/power/r8a779f0-sysc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0 or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ /* * Copyright (C) 2021 Renesas Electronics Corp. */ -- 2.40.1
[PATCH 01/20] clk: renesas: Synchronize R8A77951 H3 DT headers with Linux 6.5.3
Synchronize R-Car R8A77951 H3 DT headers with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- include/dt-bindings/power/r8a7795-sysc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h index eea6ad69f0b..ff532385857 100644 --- a/include/dt-bindings/power/r8a7795-sysc.h +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -30,7 +30,6 @@ #define R8A7795_PD_CA53_SCU21 #define R8A7795_PD_3DG_E 22 #define R8A7795_PD_A3IR24 -#define R8A7795_PD_A2VC0 25 /* ES1.x only */ #define R8A7795_PD_A2VC1 26 /* Always-on power area */ -- 2.40.1
[PATCH] linux/compat.h: Define empty __initconst and __initdata
Introduce two new empty macros used in various static tables in Linux.
Signed-off-by: Marek Vasut
---
include/linux/compat.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 921e698f407..f8e3570d1ad 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -271,6 +271,8 @@ typedef int wait_queue_head_t;
#define __devinit
#define __devinitdata
#define __devinitconst
+#define __initconst
+#define __initdata
#define kthread_create(...)__builtin_return_address(0)
#define kthread_stop(...) do { } while (0)
--
2.40.1
[PATCH 18/18] pinctrl: renesas: Synchronize R8A779G0 V4H PFC tables with Linux 6.5.3
Synchronize R-Car R8A779G0 V4H PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a779g0.c | 1095 +--- 1 file changed, 596 insertions(+), 499 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a779g0.c b/drivers/pinctrl/renesas/pfc-r8a779g0.c index 78a91f426d9..20498a1c2f7 100644 --- a/drivers/pinctrl/renesas/pfc-r8a779g0.c +++ b/drivers/pinctrl/renesas/pfc-r8a779g0.c @@ -52,6 +52,12 @@ PORT_GP_CFG_21(7, fn, sfx, CFG_FLAGS), \ PORT_GP_CFG_14(8, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33) +#define CPU_ALL_NOGP(fn) \ + PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB1, "VDDQ_AVB1", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_AVB2, "VDDQ_AVB2", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25), \ + PIN_NOGP_CFG(VDDQ_TSN0, "VDDQ_TSN0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_18_25) + /* GPSR0 */ #define GPSR0_18 F_(MSIOF2_RXD, IP2SR0_11_8) #define GPSR0_17 F_(MSIOF2_SCK, IP2SR0_7_4) @@ -159,54 +165,54 @@ #define GPSR3_0F_(MMC_SD_D1, IP0SR3_3_0) /* GPSR4 */ -#define GPSR4_24 FM(AVS1) -#define GPSR4_23 FM(AVS0) -#define GPSR4_22 FM(PCIE1_CLKREQ_N) -#define GPSR4_21 FM(PCIE0_CLKREQ_N) -#define GPSR4_20 FM(TSN0_TXCREFCLK) -#define GPSR4_19 FM(TSN0_TD2) -#define GPSR4_18 FM(TSN0_TD3) -#define GPSR4_17 FM(TSN0_RD2) -#define GPSR4_16 FM(TSN0_RD3) -#define GPSR4_15 FM(TSN0_TD0) -#define GPSR4_14 FM(TSN0_TD1) -#define GPSR4_13 FM(TSN0_RD1) -#define GPSR4_12 FM(TSN0_TXC) -#define GPSR4_11 FM(TSN0_RXC) -#define GPSR4_10 FM(TSN0_RD0) -#define GPSR4_9FM(TSN0_TX_CTL) -#define GPSR4_8FM(TSN0_AVTP_PPS0) -#define GPSR4_7FM(TSN0_RX_CTL) -#define GPSR4_6FM(TSN0_AVTP_CAPTURE) -#define GPSR4_5FM(TSN0_AVTP_MATCH) -#define GPSR4_4FM(TSN0_LINK) -#define GPSR4_3FM(TSN0_PHY_INT) -#define GPSR4_2FM(TSN0_AVTP_PPS1) -#define GPSR4_1FM(TSN0_MDC) -#define GPSR4_0FM(TSN0_MDIO) +#define GPSR4_24 F_(AVS1,IP3SR4_3_0) +#define GPSR4_23 F_(AVS0,IP2SR4_31_28) +#define GPSR4_22 F_(PCIE1_CLKREQ_N, IP2SR4_27_24) +#define GPSR4_21 F_(PCIE0_CLKREQ_N, IP2SR4_23_20) +#define GPSR4_20 F_(TSN0_TXCREFCLK, IP2SR4_19_16) +#define GPSR4_19 F_(TSN0_TD2,IP2SR4_15_12) +#define GPSR4_18 F_(TSN0_TD3,IP2SR4_11_8) +#define GPSR4_17 F_(TSN0_RD2,IP2SR4_7_4) +#define GPSR4_16 F_(TSN0_RD3,IP2SR4_3_0) +#define GPSR4_15 F_(TSN0_TD0,IP1SR4_31_28) +#define GPSR4_14 F_(TSN0_TD1,IP1SR4_27_24) +#define GPSR4_13 F_(TSN0_RD1,IP1SR4_23_20) +#define GPSR4_12 F_(TSN0_TXC,IP1SR4_19_16) +#define GPSR4_11 F_(TSN0_RXC,IP1SR4_15_12) +#define GPSR4_10 F_(TSN0_RD0,IP1SR4_11_8) +#define GPSR4_9F_(TSN0_TX_CTL, IP1SR4_7_4) +#define GPSR4_8F_(TSN0_AVTP_PPS0, IP1SR4_3_0) +#define GPSR4_7F_(TSN0_RX_CTL, IP0SR4_31_28) +#define GPSR4_6F_(TSN0_AVTP_CAPTURE, IP0SR4_27_24) +#define GPSR4_5F_(TSN0_AVTP_MATCH, IP0SR4_23_20) +#define GPSR4_4F_(TSN0_LINK, IP0SR4_19_16) +#define GPSR4_3F_(TSN0_PHY_INT,IP0SR4_15_12) +#define GPSR4_2F_(TSN0_AVTP_PPS1, IP0SR4_11_8) +#define GPSR4_1F_(TSN0_MDC,IP0SR4_7_4) +#define GPSR4_0F_(TSN0_MDIO, IP0SR4_3_0) /* GPSR 5 */ -#define GPSR5_20 FM(AVB2_RX_CTL) -#define GPSR5_19 FM(AVB2_TX_CTL) -#define GPSR5_18 FM(AVB2_RXC) -#define GPSR5_17 FM(AVB2_RD0) -#define GPSR5_16 FM(AVB2_TXC) -#define GPSR5_15 FM(AVB2_TD0) -#define GPSR5_14 FM(AVB2_RD1) -#define GPSR5_13 FM(AVB2_RD2) -#define GPSR5_12 FM(AVB2_TD1) -#define GPSR5_11 FM(AVB2_TD2) -#define GPSR5_10 FM(AVB2_MDIO) -#define GPSR5_9FM(AVB2_RD3) -#define GPSR5_8FM(AVB2_TD3) -#define GPSR5_7FM(AVB2_TXCREFCLK) -#define GPSR5_6FM(AVB2_MDC) -#define GPSR5_5FM(AVB2_MAGIC) -#define GPSR5_4FM(AVB2_PHY_INT) -#define GPSR5_3FM(AVB2_LINK) -#define GPSR5_2FM(AVB2_AVTP_MATCH) -#define GPSR5_1FM(AVB2_AVTP_CAPTURE) -#define GPSR5_0FM(AVB2_AVTP_PPS) +#define GPSR5_20
[PATCH 17/18] pinctrl: renesas: Synchronize R8A779F0 S4 PFC tables with Linux 6.5.3
Synchronize R-Car R8A779F0 S4 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a779f0.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779f0.c
b/drivers/pinctrl/renesas/pfc-r8a779f0.c
index e2ac9d1efde..5123e26e0ac 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779f0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779f0.c
@@ -1216,7 +1216,7 @@ static const unsigned int tsn1_avtp_pps_pins[] = {
RCAR_GP_PIN(3, 13),
};
static const unsigned int tsn1_avtp_pps_mux[] = {
- TSN0_AVTP_PPS_MARK,
+ TSN1_AVTP_PPS_MARK,
};
static const unsigned int tsn1_avtp_capture_a_pins[] = {
/* TSN1_AVTP_CAPTURE_A */
@@ -1787,7 +1787,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
MOD_SEL1_3_2
MOD_SEL1_1_0))
},
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -1899,7 +1899,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[]
= {
{ RCAR_GP_PIN(3, 17), 4, 3 }, /* TSN0_AVTP_MATCH_B */
{ RCAR_GP_PIN(3, 16), 0, 3 }, /* TSN0_AVTP_PPS */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -1914,7 +1914,7 @@ static const struct pinmux_ioctrl_reg
pinmux_ioctrl_regs[] = {
[POC1] = { 0xe60508a0, },
[POC3] = { 0xe60518a0, },
[TD0SEL1] = { 0xe6050920, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779f0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -2073,7 +2073,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779f0_pfc_ops = {
--
2.40.1
[PATCH 16/18] pinctrl: renesas: Synchronize R8A779A0 V3U PFC tables with Linux 6.5.3
Synchronize R-Car R8A779A0 V3U PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c
b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 0f570e4ea5e..3c4b03b1b4c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -3633,7 +3633,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
MOD_SEL2_3_2
/* RESERVED 1-0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -3938,7 +3938,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[]
= {
{ RCAR_GP_PIN(9, 17), 4, 3 }, /* AVB5_LINK */
{ RCAR_GP_PIN(9, 16), 0, 3 }, /* AVB5_PHY_INT */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -3965,7 +3965,7 @@ static const struct pinmux_ioctrl_reg
pinmux_ioctrl_regs[] = {
[POC8] = { 0xe60690a0, },
[POC9] = { 0xe60698a0, },
[TD1SEL0] = { 0xe6058124, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a779a0_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -4352,7 +4352,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a779a0_pfc_ops = {
--
2.40.1
[PATCH 15/18] pinctrl: renesas: Synchronize R8A77995 D3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77995 D3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77995.c | 46 --
1 file changed, 28 insertions(+), 18 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77995.c
b/drivers/pinctrl/renesas/pfc-r8a77995.c
index 06caf16c991..c0d69937ddb 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77995.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77995.c
@@ -23,7 +23,7 @@
PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
- PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn,
SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -2854,19 +2855,37 @@ static const struct pinmux_cfg_reg pinmux_config_regs[]
= {
MOD_SEL1_26
/* RESERVED 25-0 */ ))
},
- { },
+ { /* sentinel */ }
+};
+
+enum ioctrl_regs {
+ POCCTRL0,
+ POCCTRL2,
+ TDSELCTRL,
+};
+
+static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
+ [POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
+ [TDSELCTRL] = { 0xe60603c0, },
+ { /* sentinel */ }
};
+
static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
-
- *pocctrl = 0xe6060380;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return 29 - (pin - RCAR_GP_PIN(3, 0));
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
- bit = 29 - (pin - RCAR_GP_PIN(3, 0));
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -3077,15 +3096,6 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] =
{
{ /* sentinel */ }
};
-enum ioctrl_regs {
- TDSELCTRL,
-};
-
-static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
- [TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
-};
-
static const struct pinmux_bias_reg *
r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
unsigned int *puen_bit, unsigned int *pud_bit)
--
2.40.1
[PATCH 14/18] pinctrl: renesas: Synchronize R8A77990 E3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77990 E3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77990.c | 41 --
1 file changed, 25 insertions(+), 16 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77990.c
b/drivers/pinctrl/renesas/pfc-r8a77990.c
index c6c3d0988b0..215a19ef9cd 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77990.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77990.c
@@ -26,12 +26,12 @@
PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33
| SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
+ PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE_18_33
| SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -60,7 +60,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn,
SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -511,7 +512,8 @@ MOD_SEL0_1_0
FM(AVB_TD3) \
FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
FM(ASEBRK) \
- FM(MLB_REF)
+ FM(MLB_REF) \
+ FM(VDDQ_AVB0)
enum {
PINMUX_RESERVED = 0,
@@ -5006,7 +5008,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
MOD_SEL1_4
/* RESERVED 3, 2, 1, 0 */ ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5039,33 +5041,40 @@ static const struct pinmux_drive_reg
pinmux_drive_regs[] = {
{ RCAR_GP_PIN(4, 9), 17, 2 }, /* SD3_DAT7 */
{ RCAR_GP_PIN(4, 10), 14, 2 }, /* SD3_DS */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
POCCTRL0,
+ POCCTRL2,
TDSELCTRL,
};
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL0] = { 0xe6060380, },
+ [POCCTRL2] = { 0xe6060388, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77990_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
- int bit = -EINVAL;
+ switch (pin) {
+ case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 11):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ case RCAR_GP_PIN(4, 0) ... RCAR_GP_PIN(4, 10):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
+ return (pin & 0x1f) + 19;
- if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
- bit = pin & 0x1f;
+ case PIN_VDDQ_AVB0:
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
+ return 0;
- if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
- bit = (pin & 0x1f) + 19;
-
- return bit;
+ default:
+ return -EINVAL;
+ }
}
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
@@ -5273,7 +5282,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = RCAR_GP_PIN(6, 9), /* USB30_OVC */
[31] = RCAR_GP_PIN(6, 17), /* USB30_PWEN */
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77990_pfc_ops = {
--
2.40.1
[PATCH 13/18] pinctrl: renesas: Synchronize R8A77980 V3H PFC tables with Linux 6.5.3
Synchronize R-Car R8A77980 V3H PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a77980.c | 55 +- 1 file changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c index 19bd46c9e48..523faa0ac8f 100644 --- a/drivers/pinctrl/renesas/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -21,10 +21,10 @@ #include "sh_pfc.h" #define CPU_ALL_GP(fn, sfx)\ - PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ + PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ - PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN),\ - PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PORT_GP_CFG_25(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\ PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) @@ -37,7 +37,9 @@ PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST, "FSCLKST", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ - PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN) + PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ + PIN_NOGP_CFG(VDDQ_AVB, "VDDQ_AVB", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33), \ + PIN_NOGP_CFG(VDDQ_GE, "VDDQ_GE", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) /* * F_() : just information @@ -99,7 +101,7 @@ #define GPSR1_0F_(IRQ0,IP2_27_24) /* GPSR2 */ -#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) +#define GPSR2_29 F_(FSO_TOE_N, IP10_19_16) #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12) #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8) #define GPSR2_26 F_(SDA3,IP10_7_4) @@ -264,11 +266,11 @@ #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP8_31_28 FM(DIGRF_CLKOUT)FM(DIGRF_CLKEN_OUT) F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_3_0FM(IRQ4)F_(0, 0) F_(0, 0)FM(VI0_DATA12) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) -#define IP9_7_4FM(IRQ5)F_(0, 0) F_(0, 0)FM(VI0_DATA13) F_(0, 0)F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) +#define IP9_7_4FM(IRQ5)F_(0, 0) F_(0, 0)FM(VI0_DATA13) F_(0, 0)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0)
[PATCH 12/18] pinctrl: renesas: Synchronize R8A77970 V3M PFC tables with Linux 6.5.3
Synchronize R-Car R8A77970 V3M PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77970.c | 40 +-
1 file changed, 26 insertions(+), 14 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77970.c
b/drivers/pinctrl/renesas/pfc-r8a77970.c
index 04f03452336..1cc6fa4f3fc 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77970.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77970.c
@@ -21,10 +21,10 @@
#include "sh_pfc.h"
#define CPU_ALL_GP(fn, sfx)\
- PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
- PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN),\
- PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP_DOWN),\
+ PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
+ PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP_DOWN), \
PORT_GP_CFG_6(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
PORT_GP_CFG_15(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
@@ -36,7 +36,8 @@
PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
- PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
+ PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \
+ PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn,
SH_PFC_PIN_CFG_IO_VOLTAGE_25_33)
/*
* F_() : just information
@@ -172,7 +173,7 @@
#define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2)
F_(0, 0)FM(A7) FM(PWMFSW0) F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_3_0FM(DU_DG4) F_(0, 0)
F_(0, 0)FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0)
#define IP1_7_4FM(DU_DG5) F_(0, 0)
F_(0, 0)FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0)
F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0,
0) F_(0, 0)
-#define IP1_11_8 FM(DU_DG6) F_(0, 0)
F_(0, 0)FM(A10) FM(FSO_TOE_N_A) F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
+#define IP1_11_8 FM(DU_DG6) F_(0, 0)
F_(0, 0)FM(A10) FM(FSO_TOE_N_A) F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_15_12 FM(DU_DG7) F_(0, 0)
F_(0, 0)FM(A11) FM(IRQ1)F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_19_16 FM(DU_DB2) F_(0, 0)
F_(0, 0)FM(A12) FM(IRQ2)F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
#define IP1_23_20 FM(DU_DB3) F_(0, 0)
F_(0, 0)FM(A13) FM(FXR_CLKOUT1) F_(0, 0)F_(0,
0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
F_(0, 0)
@@ -2344,7 +2345,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
MOD_SEL0_1
MOD_SEL0_0 ))
},
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -2359,26 +2360,37 @@ static const struct pinmux_ioctrl_reg
pinmux_ioctrl_regs[] = {
[POCCTRL1] = { 0xe6060384 },
[POCCTRL2] = { 0xe6060388 },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77970_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
{
int bit = pin & 0x1f;
- *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
- if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
+ switch (pin) {
+ case RCAR_GP_PIN(0, 0) ... RCAR_GP_PIN(0, 21):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
return bit;
- if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
+
+ case RCAR_GP_PIN(2, 0) ... RCAR_GP_PIN(2, 9):
+ *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
[PATCH 11/18] pinctrl: renesas: Synchronize R8A77965 M3-N PFC tables with Linux 6.5.3
Synchronize R-Car R8A77965 M3-N PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77965.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77965.c
b/drivers/pinctrl/renesas/pfc-r8a77965.c
index 04e8371f51e..377143d3918 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77965.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77965.c
@@ -26,12 +26,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5809,7 +5809,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -6057,7 +6057,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[]
= {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -6068,7 +6068,7 @@ enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77965_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6325,7 +6325,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77965_pfc_ops = {
--
2.40.1
[PATCH 10/18] pinctrl: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.5.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7796.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7796.c
b/drivers/pinctrl/renesas/pfc-r8a7796.c
index 3cc4a3b366a..163d1805dfb 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7796.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7796.c
@@ -25,12 +25,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5568,7 +5568,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5816,7 +5816,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[]
= {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -5827,7 +5827,7 @@ enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a7796_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6084,7 +6084,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7796_pfc_ops = {
--
2.40.1
[PATCH 09/18] pinctrl: renesas: Synchronize R8A77951 H3 PFC tables with Linux 6.5.3
Synchronize R-Car R8A77951 H3 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a77951.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a77951.c
b/drivers/pinctrl/renesas/pfc-r8a77951.c
index d094bd7cc94..5d1c81c3eae 100644
--- a/drivers/pinctrl/renesas/pfc-r8a77951.c
+++ b/drivers/pinctrl/renesas/pfc-r8a77951.c
@@ -19,12 +19,12 @@
PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
- PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE),
\
+ PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS |
SH_PFC_PIN_CFG_IO_VOLTAGE_18_33),\
PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
@@ -5612,7 +5612,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
/* RESERVED 16-1 */
MOD_SEL2_0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_drive_reg pinmux_drive_regs[] = {
@@ -5863,7 +5863,7 @@ static const struct pinmux_drive_reg pinmux_drive_regs[]
= {
{ RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30/USB2_CH3_PWEN */
{ RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31/USB2_CH3_OVC */
} },
- { },
+ { /* sentinel */ }
};
enum ioctrl_regs {
@@ -5874,7 +5874,7 @@ enum ioctrl_regs {
static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
[POCCTRL] = { 0xe6060380, },
[TDSELCTRL] = { 0xe60603c0, },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static int r8a77951_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6131,7 +6131,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a77951_pfc_ops = {
--
2.40.1
[PATCH 08/18] pinctrl: renesas: Synchronize R8A7794 E2 PFC tables with Linux 6.5.3
Synchronize R-Car R8A7794 E2 PFC tables with Linux 6.5.3, commit 238589d0f7b421aae18c5704dc931595019fa6c7 . Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/pfc-r8a7794.c | 50 +-- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 7ed54f0cfff..e5d125ceca0 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -43,30 +43,30 @@ PORT_GP_1(5, 25, fn, sfx), \ PORT_GP_1(5, 26, fn, sfx), \ PORT_GP_1(5, 27, fn, sfx), \ - PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),\ - PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE),\ - PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ - PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ - PORT_GP_CFG_1(6, 23, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 1, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 4, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP), \ + PORT_GP_CFG_1(6, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 11, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 12, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33), \ + PORT_GP_CFG_1(6, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),\ + PORT_GP_CFG_1(6, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP),
[PATCH 07/18] pinctrl: renesas: Synchronize R8A7792 V2H PFC tables with Linux 6.5.3
Synchronize R-Car R8A7792 V2H PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7792.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7792.c
b/drivers/pinctrl/renesas/pfc-r8a7792.c
index 81cfe81c7f5..08f1f97af6e 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7792.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7792.c
@@ -2629,7 +2629,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
/* IP7_1_0 [2] */
FN_PWM0, FN_TCLK1, FN_FSO_CFE_0, 0 ))
},
- { },
+ { /* sentinel */ }
};
static const struct pinmux_bias_reg pinmux_bias_regs[] = {
--
2.40.1
[PATCH 06/18] pinctrl: renesas: Synchronize R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.5.3
Synchronize R-Car R8A7791 M2-W and R8A7793 M2-N PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7791.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7791.c
b/drivers/pinctrl/renesas/pfc-r8a7791.c
index 219333106fc..b25453ed285 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7791.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7791.c
@@ -25,7 +25,7 @@
PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 24, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 25, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_1(6, 26, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
@@ -6555,7 +6555,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
/* RESERVED [6] */ ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7791_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
@@ -6877,7 +6877,7 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = {
[30] = SH_PFC_PIN_NONE,
[31] = SH_PFC_PIN_NONE,
} },
- { /* sentinel */ },
+ { /* sentinel */ }
};
static const struct sh_pfc_soc_operations r8a7791_pfc_ops = {
--
2.40.1
[PATCH 04/18] pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels
Currently, the Renesas pin control driver supports pins that can switch
their I/O voltage levels between either 1.8V and 3.3V, or between 2.5V
and 3.3V. However, some SoCs have pins that can switch between 1.8V and
2.5V.
Add support for this by replacing the separate SH_PFC_PIN_CFG_IO_VOLTAGE
capability and voltage level flags by a 2-bit field, to cover three
possible I/O voltage switching options.
Ported from Linux kernel commit by Geert Uytterhoeven:
b88e733ac517 ("pinctrl: renesas: Add support for 1.8V/2.5V I/O voltage levels")
Signed-off-by: Geert Uytterhoeven
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc.c| 9 +++--
drivers/pinctrl/renesas/sh_pfc.h | 20 +++-
2 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index f6e8dd93374..3ac25cbd080 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -798,7 +798,7 @@ static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc,
unsigned int _pin,
return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
case PIN_CONFIG_POWER_SOURCE:
- return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
+ return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
default:
return false;
@@ -814,6 +814,7 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
unsigned _pin,
int bit, ret;
int idx = sh_pfc_get_pin_index(pfc, _pin);
const struct sh_pfc_pin *pin = >info->pins[idx];
+ unsigned int mode, hi, lo;
if (!sh_pfc_pinconf_validate(pfc, _pin, param))
return -ENOTSUPP;
@@ -851,8 +852,12 @@ static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx,
unsigned _pin,
pocctrl = (void __iomem *)(uintptr_t)addr;
+ mode = pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE_MASK;
+ lo = mode <= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 1800 : 2500;
+ hi = mode >= SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 ? 3300 : 2500;
+
val = sh_pfc_read_raw_reg(pocctrl, 32);
- if (arg == ((pin->configs & SH_PFC_PIN_VOLTAGE_18_25) ? 2500 :
3300))
+ if (arg == hi)
val |= BIT(bit);
else
val &= ~BIT(bit);
diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h
index bf40944053f..e6c21176125 100644
--- a/drivers/pinctrl/renesas/sh_pfc.h
+++ b/drivers/pinctrl/renesas/sh_pfc.h
@@ -26,19 +26,13 @@ enum {
#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
#define SH_PFC_PIN_CFG_PULL_UP_DOWN(SH_PFC_PIN_CFG_PULL_UP | \
SH_PFC_PIN_CFG_PULL_DOWN)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
-#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
-
-#define SH_PFC_PIN_VOLTAGE_18_33 (0 << 6)
-#define SH_PFC_PIN_VOLTAGE_25_33 (1 << 6)
-#define SH_PFC_PIN_VOLTAGE_18_25 (2 << 6)
-
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33(SH_PFC_PIN_CFG_IO_VOLTAGE | \
-SH_PFC_PIN_VOLTAGE_18_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33(SH_PFC_PIN_CFG_IO_VOLTAGE | \
-SH_PFC_PIN_VOLTAGE_25_33)
-#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25(SH_PFC_PIN_CFG_IO_VOLTAGE | \
-SH_PFC_PIN_VOLTAGE_18_25)
+
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_MASK GENMASK(5, 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_25(1 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_18_33(2 << 4)
+#define SH_PFC_PIN_CFG_IO_VOLTAGE_25_33(3 << 4)
+
+#define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 6)
#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
--
2.40.1
[PATCH 05/18] pinctrl: renesas: Synchronize R8A7790 H2 PFC tables with Linux 6.5.3
Synchronize R-Car R8A7790 H2 PFC tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/pfc-r8a7790.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c
b/drivers/pinctrl/renesas/pfc-r8a7790.c
index 432895ac55c..7203648bbc8 100644
--- a/drivers/pinctrl/renesas/pfc-r8a7790.c
+++ b/drivers/pinctrl/renesas/pfc-r8a7790.c
@@ -24,7 +24,7 @@
PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
- PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE |
SH_PFC_PIN_CFG_PULL_UP), \
+ PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 |
SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
PORT_GP_CFG_32(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
@@ -5824,7 +5824,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] =
{
/* SEL_I2C1 [2] */
FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
},
- { },
+ { /* sentinel */ }
};
static int r8a7790_pin_to_pocctrl(unsigned int pin, u32 *pocctrl)
--
2.40.1
[PATCH 03/18] pinctrl: renesas: Drop R8A77950 H3 ES1.x PFC table entry
Drop outstanding R8A77950 H3 ES1.x PFC table entry from sh_pfc.h . No functional change. Signed-off-by: Marek Vasut --- drivers/pinctrl/renesas/sh_pfc.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pinctrl/renesas/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h index f35fd3379a9..bf40944053f 100644 --- a/drivers/pinctrl/renesas/sh_pfc.h +++ b/drivers/pinctrl/renesas/sh_pfc.h @@ -302,7 +302,6 @@ extern const struct sh_pfc_soc_info r8a7791_pinmux_info; extern const struct sh_pfc_soc_info r8a7792_pinmux_info; extern const struct sh_pfc_soc_info r8a7793_pinmux_info; extern const struct sh_pfc_soc_info r8a7794_pinmux_info; -extern const struct sh_pfc_soc_info r8a77950_pinmux_info; extern const struct sh_pfc_soc_info r8a77951_pinmux_info; extern const struct sh_pfc_soc_info r8a77960_pinmux_info; extern const struct sh_pfc_soc_info r8a77961_pinmux_info; -- 2.40.1
[PATCH 02/18] pinctrl: renesas: Rename RZ/A1 R7S72100 PFC tables to RZ/A1
Rename pfc-r7s72100.c to pfc-rza1.c to match the file name with Linux.
Rename the Kconfig symbol to match.
No functional change.
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/Kconfig| 2 +-
drivers/pinctrl/renesas/Makefile | 2 +-
drivers/pinctrl/renesas/{pfc-r7s72100.c => pinctrl-rza1.c} | 0
3 files changed, 2 insertions(+), 2 deletions(-)
rename drivers/pinctrl/renesas/{pfc-r7s72100.c => pinctrl-rza1.c} (100%)
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0ea39b4a3f1..32f44e5bbd7 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -131,7 +131,7 @@ config PINCTRL_PFC_R8A779G0
help
Support pin multiplexing control on Renesas RCar Gen4 R8A779G0 SoCs.
-config PINCTRL_PFC_R7S72100
+config PINCTRL_RZA1
bool "Renesas RZ/A1 R7S72100 pin control driver"
depends on CPU_RZA1
default y if CPU_RZA1
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 8e59104ecf1..f9a68794eb9 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -19,5 +19,5 @@ obj-$(CONFIG_PINCTRL_PFC_R8A77995) += pfc-r8a77995.o
obj-$(CONFIG_PINCTRL_PFC_R8A779A0) += pfc-r8a779a0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779F0) += pfc-r8a779f0.o
obj-$(CONFIG_PINCTRL_PFC_R8A779G0) += pfc-r8a779g0.o
-obj-$(CONFIG_PINCTRL_PFC_R7S72100) += pfc-r7s72100.o
+obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o
diff --git a/drivers/pinctrl/renesas/pfc-r7s72100.c
b/drivers/pinctrl/renesas/pinctrl-rza1.c
similarity index 100%
rename from drivers/pinctrl/renesas/pfc-r7s72100.c
rename to drivers/pinctrl/renesas/pinctrl-rza1.c
--
2.40.1
[PATCH 01/18] pinctrl: renesas: Rename R8A7795 H3 PFC tables file name to R8A77951
Rename pfc-r8a7795.c to pfc-r8a77951.c to match the file name with Linux
and to indicate the PFC driver does not support R8A77950 H3 ES1.* .
No functional change.
Signed-off-by: Marek Vasut
---
drivers/pinctrl/renesas/Makefile | 4 ++--
drivers/pinctrl/renesas/{pfc-r8a7795.c => pfc-r8a77951.c} | 0
2 files changed, 2 insertions(+), 2 deletions(-)
rename drivers/pinctrl/renesas/{pfc-r8a7795.c => pfc-r8a77951.c} (100%)
diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile
index 1a61c39d847..8e59104ecf1 100644
--- a/drivers/pinctrl/renesas/Makefile
+++ b/drivers/pinctrl/renesas/Makefile
@@ -2,13 +2,13 @@ obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A774A1) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A774B1) += pfc-r8a77965.o
obj-$(CONFIG_PINCTRL_PFC_R8A774C0) += pfc-r8a77990.o
-obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A774E1) += pfc-r8a77951.o
obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7792) += pfc-r8a7792.o
obj-$(CONFIG_PINCTRL_PFC_R8A7793) += pfc-r8a7791.o
obj-$(CONFIG_PINCTRL_PFC_R8A7794) += pfc-r8a7794.o
-obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a7795.o
+obj-$(CONFIG_PINCTRL_PFC_R8A77951) += pfc-r8a77951.o
obj-$(CONFIG_PINCTRL_PFC_R8A77960) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77961) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77965) += pfc-r8a77965.o
diff --git a/drivers/pinctrl/renesas/pfc-r8a7795.c
b/drivers/pinctrl/renesas/pfc-r8a77951.c
similarity index 100%
rename from drivers/pinctrl/renesas/pfc-r8a7795.c
rename to drivers/pinctrl/renesas/pfc-r8a77951.c
--
2.40.1
[PULL] u-boot-sh/master
Two ethernet fixes for this release . The following changes since commit 252592214f79d8206c3cf0056a8827a0010214e0: Merge tag 'doc-2023-10-rc5' of https://source.denx.de/u-boot/custodians/u-boot-efi (2023-09-09 09:33:02 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-sh.git master for you to fetch changes up to 075e0b9050e2ec1c6a521c0a1a98be4f7feb797b: ARM: renesas: Enable DM_ETH_PHY on 64-bit R-Car boards (2023-09-17 13:56:34 +0200) Marek Vasut (2): ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs on Salvator-X boards ARM: renesas: Enable DM_ETH_PHY on 64-bit R-Car boards arch/arm/dts/salvator-common.dtsi| 2 ++ configs/r8a77970_eagle_defconfig | 1 + configs/r8a77970_v3msk_defconfig | 1 + configs/r8a77980_condor_defconfig| 1 + configs/r8a77980_v3hsk_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/r8a779a0_falcon_defconfig| 1 + configs/r8a779g0_whitehawk_defconfig | 1 + configs/rcar3_salvator-x_defconfig | 1 + configs/rcar3_ulcb_defconfig | 1 + 11 files changed, 12 insertions(+)
[PATCH] ARM: renesas: Enable DM_ETH_PHY on 64-bit R-Car boards
Enable DM_ETH_PHY to correctly release the PHY on these boards from reset. Signed-off-by: Marek Vasut --- configs/r8a77970_eagle_defconfig | 1 + configs/r8a77970_v3msk_defconfig | 1 + configs/r8a77980_condor_defconfig| 1 + configs/r8a77980_v3hsk_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/r8a779a0_falcon_defconfig| 1 + configs/r8a779g0_whitehawk_defconfig | 1 + configs/rcar3_salvator-x_defconfig | 1 + configs/rcar3_ulcb_defconfig | 1 + 10 files changed, 10 insertions(+) diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 56d62bcfd2f..4d40dbf66ac 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -71,6 +71,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index e26607a897e..61e261857e4 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -76,6 +76,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 57df450a169..b73129f9f73 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -79,6 +79,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_SH_ETHER=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig index 0025c044c0e..f48ed6caaa2 100644 --- a/configs/r8a77980_v3hsk_defconfig +++ b/configs/r8a77980_v3hsk_defconfig @@ -72,6 +72,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_SH_ETHER=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 95eb911593d..55bc3034764 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -93,6 +93,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 4b679716c62..1c1b7256a4e 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -90,6 +90,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 5350447c755..93f10552250 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -65,6 +65,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index 45471541843..1d0805c4e3e 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -63,6 +63,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 8de39c6e6d8..6aaf24e0126 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -97,6 +97,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_NVME_PCI=y CONFIG_PCI_REGION_MULTI_ENTRY=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index b8fdb5e3826..489e710e1e7 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -94,6 +94,7 @@ CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH_PHY=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -- 2.40.1
[PATCH] ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs on Salvator-X boards
Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on R-Car Gen3 Salvator-X boards. This allows software
to identify the PHY model at any time, regardless of the state of
the PHY reset line.
This is a fix for missed addition of these properties on Salvator-X
boards.
Ported from Linux kernel commit 722d55f3a9bd810f3a1a31916cc74e2915a994ce .
Signed-off-by: Marek Vasut
---
arch/arm/dts/salvator-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/salvator-common.dtsi
b/arch/arm/dts/salvator-common.dtsi
index 98bbcafc8c0..23fdd1115b2 100644
--- a/arch/arm/dts/salvator-common.dtsi
+++ b/arch/arm/dts/salvator-common.dtsi
@@ -328,6 +328,8 @@
status = "okay";
phy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-id0022.1622",
+"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <>;
--
2.40.1
[PATCH v3 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out
The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a
prefixed header. We have referring to a vendor tool (spl_tool) for this
task. 'mkimage -T sfspl' can generate the prefixed file.
Use binman to invoke mkimage for the generation of file
spl/u-boot-spl.bin.normal.out.
Update the documentation.
Signed-off-by: Heinrich Schuchardt
---
v3:
Rename binman node for SPL image.
Use u-boot-spl instead of blob as mkimage subnode.
v2:
Fix a typo in a comment in tools/sfspl.c
Add Tested-by credits
---
.../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 11 +++
doc/board/starfive/visionfive2.rst | 14 ++
2 files changed, 13 insertions(+), 12 deletions(-)
diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
index 13f69da31e..55185314dd 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
@@ -103,4 +103,15 @@
};
};
};
+
+ spl-img {
+ filename = "spl/u-boot-spl.bin.normal.out";
+
+ mkimage {
+ args = "-T sfspl";
+
+ u-boot-spl {
+ };
+ };
+};
};
diff --git a/doc/board/starfive/visionfive2.rst
b/doc/board/starfive/visionfive2.rst
index 941899a0a4..f5575ab68b 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
make starfive_visionfive2_defconfig
make
OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
-This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
-
-u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
-to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
-the below command:
-
- ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
-
-More detailed description of spl_tool,please refer spl_tool documenation.
-(Note: spl_tool git repo is at
https://github.com/starfive-tech/Tools/tree/master/spl_tool)
-
-This will generate u-boot-spl.bin.normal.out file.
+This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as well
+as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
Flashing
--
2.40.1
[PATCH v3 1/2] tools: mkimage: Add StarFive SPL image support
The StarFive JH7110 base boards require a header to be prefixed to the SPL
binary image. This has previously done with a vendor tool 'spl_tool'
published under a GPL-2-or-later license. Integrate this capability into
mkimage.
Signed-off-by: Heinrich Schuchardt
Tested-by: Chanho Park
Tested-by: Milan P. Stanić
---
v3:
no change except for Tested-by credit
v2:
no change except for Tested-by credit
---
boot/image.c| 1 +
include/image.h | 1 +
tools/Makefile | 1 +
tools/sfspl.c | 174
4 files changed, 177 insertions(+)
create mode 100644 tools/sfspl.c
diff --git a/boot/image.c b/boot/image.c
index 26f68d4c40..88b67bc3a1 100644
--- a/boot/image.c
+++ b/boot/image.c
@@ -182,6 +182,7 @@ static const table_entry_t uimage_type[] = {
{ IH_TYPE_SUNXI_TOC0, "sunxi_toc0", "Allwinner TOC0 Boot Image"
},
{ IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
Device Tree ", },
{ IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
+ { IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" },
{ -1, "", "", },
};
diff --git a/include/image.h b/include/image.h
index 01a6787d21..5f85bf84a2 100644
--- a/include/image.h
+++ b/include/image.h
@@ -231,6 +231,7 @@ enum image_type_t {
IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a
Legacy Image */
IH_TYPE_RENESAS_SPKG, /* Renesas SPKG image */
+ IH_TYPE_STARFIVE_SPL, /* StarFive SPL image */
IH_TYPE_COUNT, /* Number of image types */
};
diff --git a/tools/Makefile b/tools/Makefile
index 3d0c4b0dd6..1aa1e36137 100644
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -123,6 +123,7 @@ dumpimage-mkimage-objs := aisimage.o \
pblimage.o \
pbl_crc32.o \
renesas_spkgimage.o \
+ sfspl.o \
vybridimage.o \
stm32image.o \
$(ROCKCHIP_OBS) \
diff --git a/tools/sfspl.c b/tools/sfspl.c
new file mode 100644
index 00..ec18a0a77e
--- /dev/null
+++ b/tools/sfspl.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright Heinrich Schuchardt
+ *
+ * The StarFive JH7110 requires to prepend a header to u-boot-spl.bin
describing
+ * the payload length and CRC32.
+ *
+ * This module implements support in mkimage and dumpimage for this file
format.
+ *
+ * StarFive's spl_tool available under GPL-2.0-and-later at
+ * https://github.com/starfive-tech/Tools implements writing the same file
+ * format and served as a reference.
+ */
+
+#include
+#include
+#include
+#include
+#include "imagetool.h"
+
+#define DEFAULT_VERSION 0x01010101
+#define DEFAULT_BACKUP 0x20U
+#define DEFAULT_OFFSET 0x240
+
+/**
+ * struct spl_hdr - header for SPL on JH7110
+ *
+ * All fields are low-endian.
+ */
+struct spl_hdr {
+ /** @offset:offset to SPL header (0x240) */
+ unsigned int offset;
+ /** @bkp_offs: address of backup SPL, defaults to DEFAULT_BACKUP */
+ unsigned int bkp_offs;
+ /** @zero1: set to zero */
+ unsigned int zero1[159];
+ /** @version: header version, defaults to DEFAULT_VERSION */
+ unsigned int version;
+ /** @file_size: file size */
+ unsigned int file_size;
+ /** @hdr_size: size of the file header (0x400) */
+ unsigned int hdr_size;
+ /** @crc32: CRC32 */
+ unsigned int crc32;
+ /** @zero2: set to zero */
+ unsigned int zero2[91];
+};
+
+static int sfspl_check_params(struct image_tool_params *params)
+{
+ /* Only the RISC-V architecture is supported */
+ if (params->Aflag && params->arch != IH_ARCH_RISCV)
+ return EXIT_FAILURE;
+
+ return EXIT_SUCCESS;
+}
+
+static int sfspl_verify_header(unsigned char *buf, int size,
+ struct image_tool_params *params)
+{
+ struct spl_hdr *hdr = (void *)buf;
+ unsigned int hdr_size = le32_to_cpu(hdr->hdr_size);
+ unsigned int file_size = le32_to_cpu(hdr->file_size);
+ unsigned int crc = le32_to_cpu(hdr->crc32);
+ unsigned int crc_check;
+
+ if (size < 0 ||
+ (size_t)size < sizeof(struct spl_hdr) ||
+ (size_t)size < hdr_size + file_size) {
+ printf("Truncated file\n");
+ return EXIT_FAILURE;
+ }
+ if (hdr->version != DEFAULT_VERSION) {
+ printf("Unknown file format version\n");
+ return EXIT_FAILURE;
+ }
+ crc_check = crc32(0, [hdr_size], size - hdr_size);
+ if (crc_check != crc) {
+ printf("Incorrect CRC32\n");
+ return EXIT_FAILURE;
+ }
+
+ return
[PATCH v3 0/2] riscv: starfive: generate u-boot-spl.bin.normal.out
The StarFive JH7110 base boards require a header to be prefixed to the SPL binary image. This has previously done with a vendor tool 'spl_tool' published under a GPL-2-or-later license. Integrate this capability into mkimage. Add a binman task into the VisionFive 2 build to build the prefixed U-Boot SPL file u-boot-spl.bin.normal.out. v3: Rename binman node for SPL image. Use u-boot-spl instead of blob as mkimage subnode. v2: Fix a typo in a comment in tools/sfspl.c Add Tested-by credits Heinrich Schuchardt (2): tools: mkimage: Add StarFive SPL image support riscv: dts: starfive: generate u-boot-spl.bin.normal.out .../jh7110-starfive-visionfive-2-u-boot.dtsi | 11 ++ boot/image.c | 1 + doc/board/starfive/visionfive2.rst| 14 +- include/image.h | 1 + tools/Makefile| 1 + tools/sfspl.c | 174 ++ 6 files changed, 190 insertions(+), 12 deletions(-) create mode 100644 tools/sfspl.c -- 2.40.1
[RESEND PATCH v1 2/2] clk: Add clock driver for Amlogic A1
This patch adds basic clock driver for Amlogic A1 Family which supports
enabling/disabling some gates, getting frequencies and setting rate
with limited reparenting.
Signed-off-by: Igor Prusov
---
arch/arm/include/asm/arch-meson/clock-a1.h | 23 +
drivers/clk/meson/Kconfig | 8 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/a1.c | 681 +
4 files changed, 713 insertions(+)
create mode 100644 arch/arm/include/asm/arch-meson/clock-a1.h
create mode 100644 drivers/clk/meson/a1.c
diff --git a/arch/arm/include/asm/arch-meson/clock-a1.h
b/arch/arm/include/asm/arch-meson/clock-a1.h
new file mode 100644
index 00..f6795f5e0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-meson/clock-a1.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 - AmLogic, Inc.
+ * Copyright 2023 (C) SberDevices, Inc.
+ */
+
+#ifndef _ARCH_MESON_CLOCK_A1_H_
+#define _ARCH_MESON_CLOCK_A1_H_
+
+/*
+ * Clock controller register offsets
+ */
+#define A1_SYS_OSCIN_CTRL 0x0
+#define A1_SYS_CLK_CTRL0 0x10
+#define A1_SYS_CLK_EN0 0x1c
+#define A1_SAR_ADC_CLK_CTR 0xc0
+#define A1_SPIFC_CLK_CTRL 0xd8
+#define A1_USB_BUSCLK_CTRL 0xdc
+#define A1_SD_EMMC_CLK_CTRL0xe0
+
+#define A1_ANACTRL_FIXPLL_CTRL00x0
+
+#endif /* _ARCH_MESON_CLOCK_A1_H_ */
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index 994b44ad7a..cdc9d6f76c 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -21,3 +21,11 @@ config CLK_MESON_G12A
help
Enable clock support for the Amlogic G12A SoC family, such as
the S905X/D2
+
+config CLK_MESON_A1
+ bool "Enable clock support for Amlogic A1"
+ depends on CLK && ARCH_MESON
+ default MESON_A1
+ help
+ Enable clock support for the Amlogic A1 SoC family, such as
+ the A113L
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index a486b13e9c..d975f07aab 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_CLK_MESON_AXG) += axg.o
obj-$(CONFIG_CLK_MESON_AXG) += axg-ao.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a.o
obj-$(CONFIG_CLK_MESON_G12A) += g12a-ao.o
+obj-$(CONFIG_CLK_MESON_A1) += a1.o
diff --git a/drivers/clk/meson/a1.c b/drivers/clk/meson/a1.c
new file mode 100644
index 00..6b2b9e6925
--- /dev/null
+++ b/drivers/clk/meson/a1.c
@@ -0,0 +1,681 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2023 SberDevices, Inc.
+ * Author: Igor Prusov
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clk_meson.h"
+
+/*
+ * This driver supports both PLL and peripherals clock sources.
+ * Following operations are supported:
+ * - calculating clock frequency on a limited tree
+ * - reading muxes and dividers
+ * - enabling/disabling gates without propagation
+ * - reparenting without rate propagation, only on muxes
+ * - setting rates with limited reparenting, only on dividers with mux parent
+ */
+
+#define NR_CLKS154
+#define NR_PLL_CLKS11
+
+#define EXTERNAL_XTAL (NR_CLKS + 0)
+#define EXTERNAL_FCLK_DIV2 (NR_CLKS + 1)
+#define EXTERNAL_FCLK_DIV3 (NR_CLKS + 2)
+#define EXTERNAL_FCLK_DIV5 (NR_CLKS + 3)
+#define EXTERNAL_FCLK_DIV7 (NR_CLKS + 4)
+
+#define EXTERNAL_FIXPLL_IN (NR_PLL_CLKS + 1)
+
+#define SET_PARM_VALUE(_priv, _parm, _val) \
+ regmap_update_bits((_priv)->map, (_parm)->reg_off, \
+ SETPMASK((_parm)->width, (_parm)->shift),\
+ (_val) << (_parm)->shift)
+
+#define GET_PARM_VALUE(_priv, _parm) \
+({ \
+ uint _reg; \
+ regmap_read((_priv)->map, (_parm)->reg_off, &_reg); \
+ PARM_GET((_parm)->width, (_parm)->shift, _reg); \
+})
+
+struct meson_clk {
+ struct regmap *map;
+};
+
+enum meson_clk_type {
+ MESON_CLK_ANY = 0,
+ MESON_CLK_GATE,
+ MESON_CLK_MUX,
+ MESON_CLK_DIV,
+ MESON_CLK_FIXED_DIV,
+ MESON_CLK_EXTERNAL,
+ MESON_CLK_PLL,
+};
+
+struct meson_clk_info {
+ const char *name;
+ union {
+ const struct parm *parm;
+ u8 div;
+ };
+ const unsigned int *parents;
+ const enum meson_clk_type type;
+};
+
+struct meson_clk_data {
+ const u8 num_clocks;
+ const struct meson_clk_info **clocks;
+};
+
+#define CLK_MUX(_name, _reg, _shift, _width, ...) \
+ (&(struct meson_clk_info){ \
+
[RESEND PATCH v1 1/2] dt-bindings: clock: Add Amlogic A1 clock bindings
Add clock bindings for Amlogic A1 from linux-next next-20230821. Signed-off-by: Igor Prusov --- .../clock/amlogic,a1-peripherals-clkc.h | 168 ++ .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 +++ 2 files changed, 193 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h new file mode 100644 index 00..06f198ee76 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_PERIPHERALS_CLKC_H +#define __A1_PERIPHERALS_CLKC_H + +#define CLKID_XTAL_IN 0 +#define CLKID_FIXPLL_IN1 +#define CLKID_USB_PHY_IN 2 +#define CLKID_USB_CTRL_IN 3 +#define CLKID_HIFIPLL_IN 4 +#define CLKID_SYSPLL_IN5 +#define CLKID_DDS_IN 6 +#define CLKID_SYS 7 +#define CLKID_CLKTREE 8 +#define CLKID_RESET_CTRL 9 +#define CLKID_ANALOG_CTRL 10 +#define CLKID_PWR_CTRL 11 +#define CLKID_PAD_CTRL 12 +#define CLKID_SYS_CTRL 13 +#define CLKID_TEMP_SENSOR 14 +#define CLKID_AM2AXI_DIV 15 +#define CLKID_SPICC_B 16 +#define CLKID_SPICC_A 17 +#define CLKID_MSR 18 +#define CLKID_AUDIO19 +#define CLKID_JTAG_CTRL20 +#define CLKID_SARADC_EN21 +#define CLKID_PWM_EF 22 +#define CLKID_PWM_CD 23 +#define CLKID_PWM_AB 24 +#define CLKID_CEC 25 +#define CLKID_I2C_S26 +#define CLKID_IR_CTRL 27 +#define CLKID_I2C_M_D 28 +#define CLKID_I2C_M_C 29 +#define CLKID_I2C_M_B 30 +#define CLKID_I2C_M_A 31 +#define CLKID_ACODEC 32 +#define CLKID_OTP 33 +#define CLKID_SD_EMMC_A34 +#define CLKID_USB_PHY 35 +#define CLKID_USB_CTRL 36 +#define CLKID_SYS_DSPB 37 +#define CLKID_SYS_DSPA 38 +#define CLKID_DMA 39 +#define CLKID_IRQ_CTRL 40 +#define CLKID_NIC 41 +#define CLKID_GIC 42 +#define CLKID_UART_C 43 +#define CLKID_UART_B 44 +#define CLKID_UART_A 45 +#define CLKID_SYS_PSRAM46 +#define CLKID_RSA 47 +#define CLKID_CORESIGHT48 +#define CLKID_AM2AXI_VAD 49 +#define CLKID_AUDIO_VAD50 +#define CLKID_AXI_DMC 51 +#define CLKID_AXI_PSRAM52 +#define CLKID_RAMB 53 +#define CLKID_RAMA 54 +#define CLKID_AXI_SPIFC55 +#define CLKID_AXI_NIC 56 +#define CLKID_AXI_DMA 57 +#define CLKID_CPU_CTRL 58 +#define CLKID_ROM 59 +#define CLKID_PROC_I2C 60 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 +#define CLKID_DSPA_EN 63 +#define CLKID_DSPA_EN_NIC 64 +#define CLKID_DSPB_EN 65 +#define CLKID_DSPB_EN_NIC 66 +#define CLKID_RTC 67 +#define CLKID_CECA_32K 68 +#define CLKID_CECB_32K 69 +#define CLKID_24M 70 +#define CLKID_12M 71 +#define CLKID_FCLK_DIV2_DIVN 72 +#define CLKID_GEN 73 +#define CLKID_SARADC_SEL 74 +#define CLKID_SARADC 75 +#define CLKID_PWM_A76 +#define CLKID_PWM_B77 +#define CLKID_PWM_C78 +#define CLKID_PWM_D79 +#define CLKID_PWM_E80 +#define CLKID_PWM_F81 +#define CLKID_SPICC82 +#define CLKID_TS 83 +#define CLKID_SPIFC84 +#define CLKID_USB_BUS 85 +#define CLKID_SD_EMMC 86 +#define CLKID_PSRAM87 +#define CLKID_DMC 88 +#define CLKID_SYS_A_SEL89 +#define CLKID_SYS_A_DIV90 +#define CLKID_SYS_A91 +#define CLKID_SYS_B_SEL92 +#define CLKID_SYS_B_DIV93 +#define CLKID_SYS_B94 +#define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 +#define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 +#define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 +#define CLKID_DSPB_B_SEL 104 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_IN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define
[RESEND PATCH v1 0/2] clk: amlogic: a1: Add Amlogic A1 clock driver
This series adds dt-bindings and driver implementation for Amlogic A1 PLL and Peripherals clock controllers. Igor Prusov (2): dt-bindings: clock: Add Amlogic A1 clock bindings clk: Add clock driver for Amlogic A1 arch/arm/include/asm/arch-meson/clock-a1.h| 23 + drivers/clk/meson/Kconfig | 8 + drivers/clk/meson/Makefile| 1 + drivers/clk/meson/a1.c| 681 ++ .../clock/amlogic,a1-peripherals-clkc.h | 168 + .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 + 6 files changed, 906 insertions(+) create mode 100644 arch/arm/include/asm/arch-meson/clock-a1.h create mode 100644 drivers/clk/meson/a1.c create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h -- 2.34.1
Re: Aw: Re: [PATCH v3] board: rockchip: Add Bananapi R2Pro Board
On 2023-09-17 09:19, Frank Wunderlich wrote:
> Hi,
>
> thank you for your suggestions
>
>> Gesendet: Sonntag, 17. September 2023 um 00:51 Uhr
>> Von: "Jonas Karlman"
>> An: "Frank Wunderlich"
>> Cc: "Frank Wunderlich" , "Simon Glass"
>> , "Philipp Tomsich" , "Kever
>> Yang" , "Marek Vasut" ,
>> u-boot@lists.denx.de
>> Betreff: Re: [PATCH v3] board: rockchip: Add Bananapi R2Pro Board
>>
>> Hi Frank,
>>
>> On 2023-08-20 18:00, Frank Wunderlich wrote:
>>> From: Frank Wunderlich
>>>
>>> Add Bananapi R2 Pro board.
>>>
>>> Till now evb dts could be used, but iodomain is different
>>> (evb has 1v8 on vccio2 and vccio4 which are 3v3 on r2pro)
>>> and with iodomain driver this can cause hardware fault.
>>>
>>> Devicetree in mainline-Linux:
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
>>>
>>> Signed-off-by: Frank Wunderlich
>>> ---
>>> v3:
>>> - disable gmac0 as switch-driver is not yet ready to attach to the mac
>>> v2:
>>> - drop switch-node for now as u-boot driver works differently to linux
>>> ---
>>> arch/arm/dts/Makefile | 3 +-
>>> arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi | 23 +
>>> arch/arm/dts/rk3568-bpi-r2pro.dts | 549 ++
>>> configs/bpi-r2pro-rk3568_defconfig| 101
>>> 4 files changed, 675 insertions(+), 1 deletion(-)
>>> create mode 100644 arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
>>> create mode 100644 arch/arm/dts/rk3568-bpi-r2pro.dts
>>> create mode 100644 configs/bpi-r2pro-rk3568_defconfig
>>>
>>> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
>>> index bd518064f35f..767bf9db39fb 100644
>>> --- a/arch/arm/dts/Makefile
>>> +++ b/arch/arm/dts/Makefile
>>> @@ -182,7 +182,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
>>> rk3568-nanopi-r5s.dtb \
>>> rk3568-odroid-m1.dtb \
>>> rk3568-radxa-e25.dtb \
>>> - rk3568-rock-3a.dtb
>>> + rk3568-rock-3a.dtb \
>>> + rk3568-bpi-r2pro.dtb
>>>
>>> dtb-$(CONFIG_ROCKCHIP_RK3588) += \
>>> rk3588-edgeble-neu6a-io.dtb \
>>> diff --git a/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
>>> b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
>>> new file mode 100644
>>> index ..382a52a28b10
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
>>> @@ -0,0 +1,23 @@
>>> +// SPDX-License-Identifier: GPL-2.0+
>>> +/*
>>> + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
>>> + */
>>> +
>>> +#include "rk356x-u-boot.dtsi"
>>> +
>>> +/ {
>>> + chosen {
>>> + stdout-path =
>>> + u-boot,spl-boot-order = "same-as-spl", ,
>>
>> This is the default order in rk356x-u-boot.dtsi and can be dropped.
>>
>>> + };
>>> +};
>>> +
>>> + {
>>> + status = "okay";
>>
>> sdmmc0 is already enabled in rk3568-bpi-r2pro.dts
>>
>>> +};
>>> +
>>> + {
>>> + clock-frequency = <2400>;
>>> + bootph-pre-ram;
>>> + status = "okay";
>>> +};
>
> then i have only the uart here...right? do you remember i missed the
> -uboot.dtsi in first try and board does not find mmc in spl.
>
> do i really not need the first 2 nodes here?
The chosen node with stdout-path prop and uart2 node should probably
be the only nodes left.
If you are having issues with mmc in SPL, I would first look at pinctrl,
ensure pinctrl is enabled in SPL and that pinctrl-0 prop is defined for
your sdmmc0 and sdhci node. OF_SPL_REMOVE_PROPS should also not list
pinctrl nodes, look at defconfig for other rk356x boards, e.g.
rock-3a-rk3568_defconfig should be a good candidate and one I test
frequently.
And if that does not help and there is a regulator that is not enable by
default you may need to enable gpio and regulator pinconf nodes and
related Kconfig options for SPL.
See rk3566-quartz64-a-u-boot.dtsi where I had to enable gpio0, vcc3v3_sd
and vcc_sd_h node and related Kconfig options to have working sd-card.
>
>>> diff --git a/arch/arm/dts/rk3568-bpi-r2pro.dts
>>> b/arch/arm/dts/rk3568-bpi-r2pro.dts
>>> new file mode 100644
>>> index ..e4fcbb8a1174
>>> --- /dev/null
>>> +++ b/arch/arm/dts/rk3568-bpi-r2pro.dts
>>
>> Should be a 1:1 copy from kernel.
>
> i try to do so, but this will result in many nodes not used in uboot like the
> switch i remove in the dtsi and graphics.
> thx for pointing to the pcie driver then i can let these nodes in.
This file should be a full 1:1 copy, if you need to modify any node for
U-Boot you should do such override in -u-boot.dtsi file. You can use
/delete-property/ or /delete-node/ if you really need to remove
something that cause issues for U-Boot, else leave the nodes even if
they are not useful for U-Boot itself. Having full DT should make it
possible to EFI boot generic aarch64 distro images, e.g. fedora etc.
>
>> [...]
>>
>>> diff --git a/configs/bpi-r2pro-rk3568_defconfig
>>> b/configs/bpi-r2pro-rk3568_defconfig
>>> new file mode 100644
>>> index ..e8936261eab3
>>> --- /dev/null
>>> +++ b/configs/bpi-r2pro-rk3568_defconfig
>>> @@
Re: [PATCH v2 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out
On 2023-09-17 02:00, Heinrich Schuchardt wrote:
> On 9/17/23 00:19, Jonas Karlman wrote:
>> On 2023-09-06 14:00, Heinrich Schuchardt wrote:
>>> The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a
>>> prefixed header. We have referring to a vendor tool (spl_tool) for this
>>> task. 'mkimage -T sfspl' can generate the prefixed file.
>>>
>>> Use binman to invoke mkimage for the generation of file
>>> spl/u-boot-spl.bin.normal.out.
>>>
>>> Update the documentation.
>>>
>>> Signed-off-by: Heinrich Schuchardt
>>> Tested-by: Chanho Park
>>> ---
>>> v2:
>>> Fix a typo in a comment in tools/sfspl.c
>>> Add Tested-by credit
>>> ---
>>> .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 10 ++
>>> doc/board/starfive/visionfive2.rst | 14 ++
>>> 2 files changed, 12 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
>>> b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
>>> index 13f69da31e..defe2b605f 100644
>>> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
>>> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
>>> @@ -103,4 +103,14 @@
>>> };
>>> };
>>> };
>>> + u-boot-spl {
>>> + filename = "spl/u-boot-spl.bin.normal.out";
>>> +
>>> + mkimage {
>>> + args = "-T sfspl";
>>> + blob {
>>> + filename = "spl/u-boot-spl.bin";
>>> + };
>>> + };
>>> + };
>>
>> This should probably be:
>>
>> mkimage {
>> filename = "spl/u-boot-spl.bin.normal.out";
>> args = "-T sfspl";
>>
>> u-boot-spl {
>> };
>> };
>
> @Jonas
> If I replace the node u-boot-spl by the suggested mkimage node, I get a
> file spl/u-boot-spl.bin.normal.out which is identical to
> spl/u-boot-spl.bin. It lacks the header that mkimage should create.
You are correct, with the multiple-images prop in binman node each
subnode is treated as an image and not as an entry type node.
See tools/binman/image.py for some description of image type.
This means we need to have a wrapping image node and cannot directly
use an entry type node at top level under binman node.
>
> Replacing the blob node by a u-boot-spl node is possible. Whether it is
> better readable is a matter of taste.
The u-boot-spl entry type is meant to be used for referencing the U-Boot
SPL binary and should be preferred over a plain blob entry.
I would also suggest you name the image node something other then
u-boot-spl because it was easily confused with the entry type of same
name.
E.g. something like:
spl {
filename = "spl/u-boot-spl.bin.normal.out";
mkimage {
args = "-T sfspl";
u-boot-spl {
};
};
};
Regards,
Jonas
>
> @Simon:
> Could you, please, have a look at doc/develop/package/entries.rst. It
> seems not to fully describe how binman is controlled via the device-tree.
>
> * A blob sub-node for the mkimage node is not described.
> * A mkimage node which is not a direct subnode of binman is not mentioned.
> * Why the target filename must be outside of the mkimage node in my case
> is not evident.
>
> Maybe a more formal description of the schema in a yaml file would help.
>
> Best regards
>
> Heinrich
>
>>
>> Regards,
>> Jonas
>>
>>> };
>>> diff --git a/doc/board/starfive/visionfive2.rst
>>> b/doc/board/starfive/visionfive2.rst
>>> index 941899a0a4..f5575ab68b 100644
>>> --- a/doc/board/starfive/visionfive2.rst
>>> +++ b/doc/board/starfive/visionfive2.rst
>>> @@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
>>> make starfive_visionfive2_defconfig
>>> make
>>> OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
>>>
>>> -This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
>>> -
>>> -u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
>>> -to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
>>> -the below command:
>>> -
>>> - ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
>>> -
>>> -More detailed description of spl_tool,please refer spl_tool documenation.
>>> -(Note: spl_tool git repo is at
>>> https://github.com/starfive-tech/Tools/tree/master/spl_tool
>>> -
>>> -This will generate u-boot-spl.bin.normal.out file.
>>> +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out) as
>>> well
>>> +as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
>>>
>>> Flashing
>>>
>>
Re: [PATCH v2 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out
Il giorno dom 17 set 2023 alle ore 09:14 Massimo Pegorer
ha scritto:
>
> Il giorno dom 17 set 2023 alle ore 02:01 Heinrich Schuchardt
> ha scritto:
> >
> >
> >
> > On 9/17/23 00:19, Jonas Karlman wrote:
> > > On 2023-09-06 14:00, Heinrich Schuchardt wrote:
> > >> The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs
> > >> a
> > >> prefixed header. We have referring to a vendor tool (spl_tool) for this
> > >> task. 'mkimage -T sfspl' can generate the prefixed file.
> > >>
> > >> Use binman to invoke mkimage for the generation of file
> > >> spl/u-boot-spl.bin.normal.out.
> > >>
> > >> Update the documentation.
> > >>
> > >> Signed-off-by: Heinrich Schuchardt
> > >> Tested-by: Chanho Park
> > >> ---
> > >> v2:
> > >> Fix a typo in a comment in tools/sfspl.c
> > >> Add Tested-by credit
> > >> ---
> > >> .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 10 ++
> > >> doc/board/starfive/visionfive2.rst | 14 ++
> > >> 2 files changed, 12 insertions(+), 12 deletions(-)
> > >>
> > >> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> > >> b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> > >> index 13f69da31e..defe2b605f 100644
> > >> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> > >> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> > >> @@ -103,4 +103,14 @@
> > >> };
> > >> };
> > >> };
> > >> +u-boot-spl {
> > >> +filename = "spl/u-boot-spl.bin.normal.out";
> > >> +
> > >> +mkimage {
> > >> +args = "-T sfspl";
> > >> +blob {
> > >> +filename = "spl/u-boot-spl.bin";
> > >> +};
> > >> +};
> > >> +};
> > >
> > > This should probably be:
> > >
> > > mkimage {
> > > filename = "spl/u-boot-spl.bin.normal.out";
> > > args = "-T sfspl";
> > >
> > > u-boot-spl {
> > > };
> > > };
> >
> > @Jonas
> > If I replace the node u-boot-spl by the suggested mkimage node, I get a
> > file spl/u-boot-spl.bin.normal.out which is identical to
> > spl/u-boot-spl.bin. It lacks the header that mkimage should create.
Images and entries are different things for binman. It expects an
image at first level, while mkimage is an entry. If you wrap Jonas'
suggestion in an image declaration, you will get what you need.
Something like:
anyname {
mkimage {
filename = "spl/u-boot-spl.bin.normal.out";
args = "-T sfspl";
u-boot-spl {
};
};
};
My personal and questionable suggestions:
- Do not make binman/mkimage working in spl subfolder.
- Do not use a generic term like "normal" in filename.
- Do not use .out filename extension instead of .bin
Thus I would suggest something like:
u-boot-spl.starfive {
mkimage {
filename = "u-boot-spl.starfive.bin";
args = "-T sfspl";
u-boot-spl {
};
};
};
Regards,
Massimo
> >
> > Replacing the blob node by a u-boot-spl node is possible. Whether it is
> > better readable is a matter of taste.
>
> It is also a matter of default/standard assumptions and conventions,
> and thus opportunities. If SPL binary filename will change in the
> future for any reason, a single fix to binman would be enough for
> everybody using u-boot-spl node, while blob node users should fix each
> one of the -u-boot.dtsi files.
>
> >
> > @Simon:
> > Could you, please, have a look at doc/develop/package/entries.rst. It
> > seems not to fully describe how binman is controlled via the device-tree.
> >
> > * A blob sub-node for the mkimage node is not described.
> > * A mkimage node which is not a direct subnode of binman is not mentioned.
> > * Why the target filename must be outside of the mkimage node in my case
> > is not evident.
> >
> > Maybe a more formal description of the schema in a yaml file would help.
> >
> > Best regards
> >
> > Heinrich
> >
> > >
> > > Regards,
> > > Jonas
> > >
> > >> };
> > >> diff --git a/doc/board/starfive/visionfive2.rst
> > >> b/doc/board/starfive/visionfive2.rst
> > >> index 941899a0a4..f5575ab68b 100644
> > >> --- a/doc/board/starfive/visionfive2.rst
> > >> +++ b/doc/board/starfive/visionfive2.rst
> > >> @@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
> > >> make starfive_visionfive2_defconfig
> > >> make
> > >> OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
> > >>
> > >> -This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> > >> -
> > >> -u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
> > >> -to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
> > >> -the below command:
> > >> -
> > >> -./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
> > >> -
> > >> -More detailed description of spl_tool,please refer spl_tool
> > >> documenation.
> > >> -(Note: spl_tool git repo is at
>
Aw: Re: [PATCH v3] board: rockchip: Add Bananapi R2Pro Board
Hi,
thank you for your suggestions
> Gesendet: Sonntag, 17. September 2023 um 00:51 Uhr
> Von: "Jonas Karlman"
> An: "Frank Wunderlich"
> Cc: "Frank Wunderlich" , "Simon Glass"
> , "Philipp Tomsich" , "Kever
> Yang" , "Marek Vasut" ,
> u-boot@lists.denx.de
> Betreff: Re: [PATCH v3] board: rockchip: Add Bananapi R2Pro Board
>
> Hi Frank,
>
> On 2023-08-20 18:00, Frank Wunderlich wrote:
> > From: Frank Wunderlich
> >
> > Add Bananapi R2 Pro board.
> >
> > Till now evb dts could be used, but iodomain is different
> > (evb has 1v8 on vccio2 and vccio4 which are 3v3 on r2pro)
> > and with iodomain driver this can cause hardware fault.
> >
> > Devicetree in mainline-Linux:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
> >
> > Signed-off-by: Frank Wunderlich
> > ---
> > v3:
> > - disable gmac0 as switch-driver is not yet ready to attach to the mac
> > v2:
> > - drop switch-node for now as u-boot driver works differently to linux
> > ---
> > arch/arm/dts/Makefile | 3 +-
> > arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi | 23 +
> > arch/arm/dts/rk3568-bpi-r2pro.dts | 549 ++
> > configs/bpi-r2pro-rk3568_defconfig| 101
> > 4 files changed, 675 insertions(+), 1 deletion(-)
> > create mode 100644 arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
> > create mode 100644 arch/arm/dts/rk3568-bpi-r2pro.dts
> > create mode 100644 configs/bpi-r2pro-rk3568_defconfig
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index bd518064f35f..767bf9db39fb 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -182,7 +182,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
> > rk3568-nanopi-r5s.dtb \
> > rk3568-odroid-m1.dtb \
> > rk3568-radxa-e25.dtb \
> > - rk3568-rock-3a.dtb
> > + rk3568-rock-3a.dtb \
> > + rk3568-bpi-r2pro.dtb
> >
> > dtb-$(CONFIG_ROCKCHIP_RK3588) += \
> > rk3588-edgeble-neu6a-io.dtb \
> > diff --git a/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
> > b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
> > new file mode 100644
> > index ..382a52a28b10
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3568-bpi-r2pro-u-boot.dtsi
> > @@ -0,0 +1,23 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * (C) Copyright 2021 Rockchip Electronics Co., Ltd
> > + */
> > +
> > +#include "rk356x-u-boot.dtsi"
> > +
> > +/ {
> > + chosen {
> > + stdout-path =
> > + u-boot,spl-boot-order = "same-as-spl", ,
>
> This is the default order in rk356x-u-boot.dtsi and can be dropped.
>
> > + };
> > +};
> > +
> > + {
> > + status = "okay";
>
> sdmmc0 is already enabled in rk3568-bpi-r2pro.dts
>
> > +};
> > +
> > + {
> > + clock-frequency = <2400>;
> > + bootph-pre-ram;
> > + status = "okay";
> > +};
then i have only the uart here...right? do you remember i missed the
-uboot.dtsi in first try and board does not find mmc in spl.
do i really not need the first 2 nodes here?
> > diff --git a/arch/arm/dts/rk3568-bpi-r2pro.dts
> > b/arch/arm/dts/rk3568-bpi-r2pro.dts
> > new file mode 100644
> > index ..e4fcbb8a1174
> > --- /dev/null
> > +++ b/arch/arm/dts/rk3568-bpi-r2pro.dts
>
> Should be a 1:1 copy from kernel.
i try to do so, but this will result in many nodes not used in uboot like the
switch i remove in the dtsi and graphics.
thx for pointing to the pcie driver then i can let these nodes in.
> [...]
>
> > diff --git a/configs/bpi-r2pro-rk3568_defconfig
> > b/configs/bpi-r2pro-rk3568_defconfig
> > new file mode 100644
> > index ..e8936261eab3
> > --- /dev/null
> > +++ b/configs/bpi-r2pro-rk3568_defconfig
> > @@ -0,0 +1,101 @@
> > +CONFIG_ARM=y
> > +CONFIG_SKIP_LOWLEVEL_INIT=y
> > +CONFIG_COUNTER_FREQUENCY=2400
> > +CONFIG_ARCH_ROCKCHIP=y
> > +CONFIG_TEXT_BASE=0x00a0
> > +CONFIG_SPL_LIBCOMMON_SUPPORT=y
> > +CONFIG_SPL_LIBGENERIC_SUPPORT=y
> > +CONFIG_NR_DRAM_BANKS=2
> > +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
> > +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0
> > +CONFIG_DEFAULT_DEVICE_TREE="rk3568-bpi-r2pro"
> > +CONFIG_ROCKCHIP_RK3568=y
> > +CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
> > +CONFIG_SPL_SERIAL=y
> > +CONFIG_SPL_STACK_R_ADDR=0x60
> > +CONFIG_SPL_STACK=0x40
> > +CONFIG_DEBUG_UART_BASE=0xFE66
> > +CONFIG_DEBUG_UART_CLOCK=2400
> > +CONFIG_SYS_LOAD_ADDR=0xc00800
> > +CONFIG_DEBUG_UART=y
> > +CONFIG_FIT=y
> > +CONFIG_FIT_VERBOSE=y
> > +CONFIG_SPL_FIT_SIGNATURE=y
> > +CONFIG_SPL_LOAD_FIT=y
> > +CONFIG_LEGACY_IMAGE_FORMAT=y
> > +#CONFIG_OF_SYSTEM_SETUP=y
> > +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-bpi-r2pro"
> > +# CONFIG_DISPLAY_CPUINFO is not set
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_SPL_MAX_SIZE=0x4
> > +CONFIG_SPL_PAD_TO=0x7f8000
> > +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
> > +CONFIG_SPL_BSS_START_ADDR=0x400
> > +CONFIG_SPL_BSS_MAX_SIZE=0x4000
> > +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> > +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not
Re: [PATCH v2 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out
Il giorno dom 17 set 2023 alle ore 02:01 Heinrich Schuchardt
ha scritto:
>
>
>
> On 9/17/23 00:19, Jonas Karlman wrote:
> > On 2023-09-06 14:00, Heinrich Schuchardt wrote:
> >> The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a
> >> prefixed header. We have referring to a vendor tool (spl_tool) for this
> >> task. 'mkimage -T sfspl' can generate the prefixed file.
> >>
> >> Use binman to invoke mkimage for the generation of file
> >> spl/u-boot-spl.bin.normal.out.
> >>
> >> Update the documentation.
> >>
> >> Signed-off-by: Heinrich Schuchardt
> >> Tested-by: Chanho Park
> >> ---
> >> v2:
> >> Fix a typo in a comment in tools/sfspl.c
> >> Add Tested-by credit
> >> ---
> >> .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 10 ++
> >> doc/board/starfive/visionfive2.rst | 14 ++
> >> 2 files changed, 12 insertions(+), 12 deletions(-)
> >>
> >> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> >> b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> >> index 13f69da31e..defe2b605f 100644
> >> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> >> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> >> @@ -103,4 +103,14 @@
> >> };
> >> };
> >> };
> >> +u-boot-spl {
> >> +filename = "spl/u-boot-spl.bin.normal.out";
> >> +
> >> +mkimage {
> >> +args = "-T sfspl";
> >> +blob {
> >> +filename = "spl/u-boot-spl.bin";
> >> +};
> >> +};
> >> +};
> >
> > This should probably be:
> >
> > mkimage {
> > filename = "spl/u-boot-spl.bin.normal.out";
> > args = "-T sfspl";
> >
> > u-boot-spl {
> > };
> > };
>
> @Jonas
> If I replace the node u-boot-spl by the suggested mkimage node, I get a
> file spl/u-boot-spl.bin.normal.out which is identical to
> spl/u-boot-spl.bin. It lacks the header that mkimage should create.
>
> Replacing the blob node by a u-boot-spl node is possible. Whether it is
> better readable is a matter of taste.
It is also a matter of default/standard assumptions and conventions,
and thus opportunities. If SPL binary filename will change in the
future for any reason, a single fix to binman would be enough for
everybody using u-boot-spl node, while blob node users should fix each
one of the -u-boot.dtsi files.
>
> @Simon:
> Could you, please, have a look at doc/develop/package/entries.rst. It
> seems not to fully describe how binman is controlled via the device-tree.
>
> * A blob sub-node for the mkimage node is not described.
> * A mkimage node which is not a direct subnode of binman is not mentioned.
> * Why the target filename must be outside of the mkimage node in my case
> is not evident.
>
> Maybe a more formal description of the schema in a yaml file would help.
>
> Best regards
>
> Heinrich
>
> >
> > Regards,
> > Jonas
> >
> >> };
> >> diff --git a/doc/board/starfive/visionfive2.rst
> >> b/doc/board/starfive/visionfive2.rst
> >> index 941899a0a4..f5575ab68b 100644
> >> --- a/doc/board/starfive/visionfive2.rst
> >> +++ b/doc/board/starfive/visionfive2.rst
> >> @@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
> >> make starfive_visionfive2_defconfig
> >> make
> >> OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.bin
> >>
> >> -This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> >> -
> >> -u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
> >> -to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
> >> -the below command:
> >> -
> >> -./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
> >> -
> >> -More detailed description of spl_tool,please refer spl_tool documenation.
> >> -(Note: spl_tool git repo is at
> >> https://github.com/starfive-tech/Tools/tree/master/spl_tool)
> >> -
> >> -This will generate u-boot-spl.bin.normal.out file.
> >> +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out)
> >> as well
> >> +as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
> >>
> >> Flashing
> >>
> >
