Re: [U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework for Marvell SoCs
- "Prafulla Wadaskar" wrote:
> > -Original Message-
> > From: u-boot-boun...@lists.denx.de
> [mailto:u-boot-boun...@lists.denx.de]
> > On Behalf Of Ajay Bhargav
> > Sent: Thursday, August 04, 2011 4:21 PM
> > To: Lei Wen
> > Cc: u-boot@lists.denx.de
> > Subject: Re: [U-Boot] [PATCH v2 1/2] gpio: Add GPIO driver framework
> for
> > Marvell SoCs
> >
> > - "Lei Wen" wrote:
> >
> > > On Thu, Aug 4, 2011 at 4:51 PM, Albert ARIBAUD
> > > wrote:
> > > > Hi Simon,
> > > >
> > > > On 04/08/2011 02:04, Simon Guinot wrote:
> > > >> Hi Ajay,
> > > >>
> > > >> On Wed, Aug 03, 2011 at 10:10:00AM +0530, Ajay Bhargav wrote:
> > > >>> - "Simon Guinot" wrote:
> > > >>>
> > > >>>> AFAIK, Orion and Kirkwood SoCs don't provide bitwise
> set/clear
> > > for
> > > >>>> GPIO output/direction registers. Instead, a register must be
> > > read
> > > >>>> first to leave other bits unchanged (see __set_direction in
> > > >>>> kw_gpio.c).
> > > >>>>
> > > >>>> Is it possible to handle Armada SoCs GPIOs in a same way ?
> maybe
> > > >>>> using
> > > >>>> the pin registers (gpxx in the Armada struct gpio_reg array)
> ?
> > > >>>>
> > > >>>> If not, this code is not Marvell generic but rather specific
> for
> > > >>>> Armada
> > > >>>> SoCs and then maybe armada_gpio is a better name...
> > > >>>>
> > > >>>> Regards,
> > > >>>>
> > > >>>> Simon
> > > >>>
> > > >>> Hi Simon,
> > > >>>
> > > >>> Yes its possible to implement code that way, Armada SoC does
> have
> > > GPIO
> > > >>> registers for set/clear. what about register naming?? I think
> they
> > > are
> > > >>> different for Kirkwood and Orion.
> > > >>
> > > >> I think that the register names could be OK. But here is a
> most
> > > >> important problem: On Orion/Kirkwood SoCs, a single GPIO
> output
> > > register
> > > >> is available (no set/clear variants as for Armada). I missed
> that
> > > point
> > > >> at my first look. It is quite problematic because only two
> > > registers are
> > > >> shared between the different Marvell SoCs: level and direction.
> In
> > > fact,
> > > >> this registers are probably relevant on every machines
> providing
> > > GPIOs...
> > > >>
> > > >> Maybe that having two common registers is not enough to add
> > > >> Orion/Kirkwood support to the mvgpio driver ?
> > > > >
> > > >>> One more thing which can be done to make this code generic is
> to
> > > have
> > > >>> some macros which can be defined by individual arch for
> specific
> > > registers
> > > >>> which are going to be in use e.g.
> > > >>>
> > > >>> #define GPIO_PIN_LEVEL_REG
> > > >>> #define GPIO_DIR_REG
> > > >>> #define GPIO_PIN_SET_REG
> > > >>> #define GPIO_PIN_CLR_REG
> > > >>
> > > >> Yes, but how to handle both a single GPI0 output register and
> some
> > > GPIO
> > > >> {set,clear} output registers (in a nice way) ?
> > > >
> > > > Two distinct gipo drivers for the two marvell variants?
> > >
> > > If let I choose, I'd prefer two, since the register set is
> different.
> > >
> > > Best regards,
> > > Lei
> > >
> >
> > Hi Simon,
> >
> > For Armada minimum 3 registers are required and available for
> armada
> > 1. Direction (read/write)
> > 2. Pin level set (write only)
> > 3. Pin level clear (write only)
> >
> > @lei
> > How bout if we check for architecture and use specific code or
> defines?
> > i.e.
> > #ifdef CONFIG_KIRKWOOD
> > //KW code
> > #elif CONFIG_ARMADA100
> > //Armada code
> > #else
> > //orion or other?
> > #endif
>
> Let's avoid this, because there will be several SoC architectures that
> uses similar GPIO register definitions, like kirkwood/orion have
> similar definition and armada/mmp/pantheon/etc.. have different one.
>
> So we will end up having several #ifdefs. Ideally #ifdefs are
> discouraged for better coding practices.
>
> Instead,
> I would suggest to use macros for this code segments or alternatively
> inlined functions and those should be defined in mvgpio.h, #ifdefed
> with CPU core subversion (i.e. CONFIG_FEROCEION,
> CONFIG_SHEEVA_88SV331xV5)
>
> Regards..
> Prafulla . .
Hi Prafulla,
I think it will be better to keep two driver files. Let this patch be for
Armada/mmp/pantheon and other compatible SoCs. Should the common GPIO
struct for armada/mmp etc.. be moved out of GPIO.h to mvgpio.h?
Regards,
Ajay Bhargav
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[U-Boot] [PATCH v3 1/2] gpio: Add GPIO driver framework for Marvell SoCs
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
v3 - Added file mvgpio.h for common defines based on CPU core
subversion. Arch related stuff should be added to arch/gpio.h
Signed-off-by: Ajay Bhargav
---
drivers/gpio/Makefile |1 +
drivers/gpio/mvgpio.c | 114 +
include/mvgpio.h | 77 +
3 files changed, 192 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 include/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP)+= mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 000..0cc8ed7
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 000..768e94c
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * T
[U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h |4 ++
arch/arm/include/asm/arch-armada100/gpio.h | 54 +++
2 files changed, 58 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..aad3ed1 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,10 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_GPIO0_BASE 0xD4019000
+#define ARMD1_GPIO1_BASE 0xD4019004
+#define ARMD1_GPIO2_BASE 0xD4019008
+#define ARMD1_GPIO3_BASE 0xD4019100
/*
* Main Power Management (MPMU) Registers
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h
b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000..bd7d21a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,54 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include
+#include
+#include
+
+#define GPIO_TO_REG(gp)(gp >> 5)
+#define GPIO_TO_BIT(gp)(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ switch (bank) {
+ case 0:
+ return (struct gpio_reg *)ARMD1_GPIO0_BASE;
+ case 1:
+ return (struct gpio_reg *)ARMD1_GPIO1_BASE;
+ case 2:
+ return (struct gpio_reg *)ARMD1_GPIO2_BASE;
+ case 3:
+ return (struct gpio_reg *)ARMD1_GPIO3_BASE;
+ }
+ return 0;
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
1.7.0.4
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Re: [U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
- "Prafulla Wadaskar" wrote:
>
> I suggest below code for this function.
> {
> Const unsigned int offset[4] = {0, 4, 8, 0x100}; /* gpio register
> bank offsets */
> return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
> }
>
> Again content in this file are SoC core specific and will duplicate
> for other SoC supports like pantheon.
>
> Can you please move them to mvgpio.h within #ifdef
> CONFIG_SHEEVA_88SV331xV5?
> I think this should be the final modification for this driver
> support.
>
> Sorry for the rework.
>
> Regards..
> Prafulla . .
>
Hi Prafulla,
Can you please tell me what part of code should be moved to mvgpio.h?
I have no idea about number of banks in other SOCs with same core.
I will do the changes as per suggestion.
Thanks & Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
- "Prafulla Wadaskar" wrote:
> > -Original Message-
> > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com]
> > Sent: Wednesday, August 10, 2011 1:37 PM
> > To: Prafulla Wadaskar
> > Cc: u-boot@lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik
> > Subject: Re: [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC
> > Armada100
> >
> >
> > - "Prafulla Wadaskar" wrote:
> >
> > >
> > > I suggest below code for this function.
> > > {
> > > Const unsigned int offset[4] = {0, 4, 8, 0x100}; /* gpio
> register
> > > bank offsets */
> > > return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
> > > }
> > >
> > > Again content in this file are SoC core specific and will
> duplicate
> > > for other SoC supports like pantheon.
> > >
> > > Can you please move them to mvgpio.h within #ifdef
> > > CONFIG_SHEEVA_88SV331xV5?
> > > I think this should be the final modification for this driver
> > > support.
> > >
> > > Sorry for the rework.
> > >
> > > Regards..
> > > Prafulla . .
> > >
> >
> > Hi Prafulla,
> >
> > Can you please tell me what part of code should be moved to
> mvgpio.h?
>
> You should move entire contents of gpio.h in mvgpio.h within #ifdef
> CONFIG_SHEEVA_88SV331xV5, so just mvgpio.c,mvgpio.h,Makefile will add
> armada100 gpio driver support in more generic way.
>
> > I have no idea about number of banks in other SOCs with same core.
>
> No need to worry, at this moment this driver will be supporting
> 88SV331xv5 core only.
>
> Regards..
> Prafulla . .
>
I feel it is important to keep gpio.h in arch folder, 'coz if someone enables
GPIO command support, generic library header (asm/gpio.h) will look for
asm/arch/gpio.h file. we can simply include mvgpio.h in gpio.h incase of
armada100.
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
- "Prafulla Wadaskar" wrote:
> You should move entire contents of gpio.h in mvgpio.h within #ifdef
> CONFIG_SHEEVA_88SV331xV5, so just mvgpio.c,mvgpio.h,Makefile will add
> armada100 gpio driver support in more generic way.
>
> > I have no idea about number of banks in other SOCs with same core.
>
> No need to worry, at this moment this driver will be supporting
> 88SV331xv5 core only.
>
> Regards..
> Prafulla . .
>
I think its better to just keep Armada100 related stuff in gpio.h and
I will do the following suggested changes.
> > {
> > Const unsigned int offset[4] = {0, 4, 8, 0x100}; /* gpio register
> > bank offsets */
> > return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
> > }
Regards,
Ajay Bhargav
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[U-Boot] [PATCH v4 1/2] gpio: Add GPIO driver framework for Marvell SoCs
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
v3 - Added file mvgpio.h for common defines based on CPU core
subversion. Arch related stuff should be added to arch/gpio.h
Signed-off-by: Ajay Bhargav
---
drivers/gpio/Makefile |1 +
drivers/gpio/mvgpio.c | 114 +
include/mvgpio.h | 77 +
3 files changed, 192 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 include/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP)+= mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 000..0cc8ed7
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 000..768e94c
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * T
[U-Boot] [PATCH v4 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
v4 - updated gpio.h file, removed modification in Armada100.h
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/gpio.h | 47
1 files changed, 47 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h
b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000..dd47832
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include
+#include
+#include
+
+#define GPIO_TO_REG(gp)(gp >> 5)
+#define GPIO_TO_BIT(gp)(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ const unsigned int offset[4] = {0, 4, 8, 0x100}; /* gpio register bank
+ offset - refer
+ Appendix A.36 */
+ return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
1.7.0.4
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Re: [U-Boot] [PATCH v4 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
- "Prafulla Wadaskar" wrote: > > -Original Message- > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > Sent: Wednesday, August 10, 2011 2:47 PM > > To: Prafulla Wadaskar > > Cc: u-boot@lists.denx.de; Ajay Bhargav > > Subject: [PATCH v4 2/2] gpio: Add GPIO driver for Marvell SoC > Armada100 > > > > This patch adds support for generic GPIO driver framework for > Marvell > > SoC Armada100. > > > > v4 - updated gpio.h file, removed modification in Armada100.h > > You are not following standard patch submission practice as indicated > here > http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions > > You need to document entire change history for each patch to be > submitted below ---, this is important > Sorry for mistake.. Do i need to add history in each patch or first patch of a series patch? I mean if I am submitting 2 patches in series I define history in patch 1/2. Am I right? Thanks & Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Added function get_gpio_base
- GPIO base address added to armada100.h
Changes for v3:
- gpio register map moved to mvgpio.h
Changes for v4:
- updated gpio.h
- removed unwanted defines from armada100.h
Changes for v5:
- Coding Style cleanup
- added change history
arch/arm/include/asm/arch-armada100/gpio.h | 46
1 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h
b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000..07c44e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include
+#include
+#include
+
+#define GPIO_TO_REG(gp)(gp >> 5)
+#define GPIO_TO_BIT(gp)(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ const unsigned int offset[4] = {0, 4, 8, 0x100};
+ /* gpio register bank offset - refer Appendix A.36 */
+ return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
1.7.0.4
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[U-Boot] [PATCH v5 1/2] gpio: Add GPIO driver framework for Marvell SoCs
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- mvgpio.h removed
- function get_gpio_base moved to gpio.h
- error messages added
Changes for v3:
- Added mvgpio.h for common define based on CPU core subversion.
Changes for v4:
- not changed
Changes for v5:
- Added change history
drivers/gpio/Makefile |1 +
drivers/gpio/mvgpio.c | 114 +
include/mvgpio.h | 77 +
3 files changed, 192 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 include/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP)+= mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 000..0cc8ed7
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 000..768e94c
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the term
Re: [U-Boot] [PATCH v5 1/2] gpio: Add GPIO driver framework for Marvell SoCs
- "Lei Wen" wrote: > > You should remove these two define, or we would met build error as: > cmd_gpio.c:20: error: expected identifier before numeric constant > cmd_gpio.c: In function 'do_gpio': > cmd_gpio.c:49: error: 'GPIO_CLEAR' undeclared (first use in this > function) > cmd_gpio.c:49: error: (Each undeclared identifier is reported only > once > cmd_gpio.c:49: error: for each function it appears in.) > cmd_gpio.c:50: error: 'GPIO_TOGGLE' undeclared (first use in this > function) > > Except this, other looks good to me, and I have verify the reset of > patch on mmp3 board. > > Thanks, > Lei > Hi Lei, Thank you so much for pointing out. I tested library by simply defining MARVELL_GPIO, I forgot to test with CMD_GPIO. I will change the names and resubmit. sorry for mistake. Thanks & Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Added function get_gpio_base
- GPIO base address added to armada100.h
Changes for v3:
- gpio register map moved to mvgpio.h
Changes for v4:
- updated gpio.h
- removed unwanted defines from armada100.h
Changes for v5:
- Coding Style cleanup
- added change history
Changes for v6:
- No change
1 files changed, 46 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h
b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000..07c44e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include
+#include
+#include
+
+#define GPIO_TO_REG(gp)(gp >> 5)
+#define GPIO_TO_BIT(gp)(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ const unsigned int offset[4] = {0, 4, 8, 0x100};
+ /* gpio register bank offset - refer Appendix A.36 */
+ return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
1.7.0.4
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[U-Boot] [PATCH v6 1/2] gpio: Add GPIO driver framework for Marvell SoCs
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- mvgpio.h removed
- function get_gpio_base moved to gpio.h
- error messages added
Changes for v3:
- Added mvgpio.h for common define based on CPU core subversion.
Changes for v4:
- not changed
Changes for v5:
- Added change history
Changes for v6:
- Renamed GPIO level defines (fixes compilation issues thanks to
Lei Wen)
drivers/gpio/Makefile |1 +
drivers/gpio/mvgpio.c | 114 +
include/mvgpio.h | 77 +
3 files changed, 192 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 include/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP)+= mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 000..0cc8ed7
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 000..8bc303b
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,77 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+
Re: [U-Boot] [PATCH v6 1/2] gpio: Add GPIO driver framework for Marvell SoCs
- "Prafulla Wadaskar" wrote: > Hi Ajay > I am sorry if I missed this in my earlier reviews. > > Why you wish to keep mvgpio.h in /include folder? > I think it should be in drivers/gpio/. > > Regards.. > Prafulla . . > Hi Prafulla, gpio.h includes this file, as GPIO_LEVEL_SET/CLR are defined in mvgpio.h which may be needed by other files accessing gpios. In my case I am using gpio for PHY reset. I was thinking not to keep any magic number 1/0 for set/clr gpio pin. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v6 1/2] gpio: Add GPIO driver framework for Marvell SoCs
- "Prafulla Wadaskar" wrote: > > -Original Message- > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > Sent: Wednesday, August 17, 2011 2:18 PM > > To: Prafulla Wadaskar > > Cc: u-boot@lists.denx.de > > Subject: Re: [PATCH v6 1/2] gpio: Add GPIO driver framework for > Marvell > > SoCs > > > > > > - "Prafulla Wadaskar" wrote: > > > > > Hi Ajay > > > I am sorry if I missed this in my earlier reviews. > > > > > > Why you wish to keep mvgpio.h in /include folder? > > > I think it should be in drivers/gpio/. > > > > > > Regards.. > > > Prafulla . . > > > > > > > Hi Prafulla, > > > > gpio.h includes this file, as GPIO_LEVEL_SET/CLR are defined > > in mvgpio.h which may be needed by other files accessing gpios. > > In my case I am using gpio for PHY reset. I was thinking not to > > keep any magic number 1/0 for set/clr gpio pin. > > Hi Ajay > > In any case this gpio driver will be used by other drivers or board > specific code to configure/set/clear particular gpio. And that is > possible by just including asm/gpio.h and using standard gpio calls. > > So in any case keeping mvgpio.h in include folder does not make any > sense to me. > > If needed, layered architecture suggest to include asm/gpio.h in your > code, which will include asm/arch/gpio.h to get your architecture > specific gpio definitions, I don't think this will be needed if you > use standard API calls. > > Regards.. > Prafulla . . > got it... I kind of misundestood.. I will move it to driver/gpio will that be ok? Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v7 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
This patch adds support for generic GPIO driver framework for Marvell
SoC Armada100.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Added function get_gpio_base
- GPIO base address added to armada100.h
Changes for v3:
- gpio register map moved to mvgpio.h
Changes for v4:
- updated gpio.h
- removed unwanted defines from armada100.h
Changes for v5:
- Coding Style cleanup
- added change history
Changes for v6:
- No change
Changes for v7:
- Added GPIO level defines
arch/arm/include/asm/arch-armada100/gpio.h | 48
1 files changed, 48 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h
b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 000..9e5e7b9
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,48 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include
+#include
+
+#define GPIO_HIGH 1
+#define GPIO_LOW 0
+
+#define GPIO_TO_REG(gp)(gp >> 5)
+#define GPIO_TO_BIT(gp)(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+ const unsigned int offset[4] = {0, 4, 8, 0x100};
+ /* gpio register bank offset - refer Appendix A.36 */
+ return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
--
1.7.0.4
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[U-Boot] [PATCH v7 1/2] gpio: Add GPIO driver framework for Marvell SoCs
This patch adds generic GPIO driver framework support for Marvell SoCs.
To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands
define CONFIG_CMD_GPIO in your board configuration file.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- mvgpio.h removed
- function get_gpio_base moved to gpio.h
- error messages added
Changes for v3:
- Added mvgpio.h for common define based on CPU core subversion.
Changes for v4:
- not changed
Changes for v5:
- Added change history
Changes for v6:
- Renamed GPIO level defines (fixes compilation issues thanks to
Lei Wen)
Changes for v7:
- mvgpio.h moved to driver/gpio
drivers/gpio/Makefile |1 +
drivers/gpio/mvgpio.c | 115 +
drivers/gpio/mvgpio.h | 74 +++
3 files changed, 190 insertions(+), 0 deletions(-)
create mode 100644 drivers/gpio/mvgpio.c
create mode 100644 drivers/gpio/mvgpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97d..beca1da 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
COBJS-$(CONFIG_MARVELL_MFP)+= mvmfp.o
COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
COBJS-$(CONFIG_PCA953X)+= pca953x.o
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 000..276f206
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,115 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include "mvgpio.h"
+#include
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+ gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+ return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+ gpio_set_value(gp, value);
+ return 0;
+}
+
+int gpio_get_value(int gp)
+{
+ struct gpio_reg *gpio_reg_bank;
+ u32 gp_val;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return -EINVAL;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ gp_val = readl(&gpio_reg_bank->gplr);
+
+ return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+ struct gpio_reg *gpio_reg_bank;
+
+ if (gp >= MV_MAX_GPIO) {
+ printf("%s: Invalid GPIO %d\n", __func__, gp);
+ return;
+ }
+
+ gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+ if (value)
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr);
+ else
+ writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr);
+}
diff --git a/drivers/gpio/mvgpio.h b/drivers/gpio/mvgpio.h
new file mode 100644
index 000..9688797
--- /dev/null
+++ b/drivers/gpio/mvgpio.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C)
[U-Boot] [PATCH 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
board/Marvell/gplugd/gplugd.c | 34 +-
include/configs/gplugd.h | 15 ++-
2 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index ac5e35f..fd2e574 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,5 +104,30 @@ int board_eth_init(bd_t *bis)
return armada100_fec_initialize();
}
-#endif /* CONFIG_ARMADA100_FEC */
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n",
+ __func__);
+ return;
+ }
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ printf("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 7fa3020..b63ffd5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -80,6 +80,20 @@
#define CONFIG_ROOTPATH"/tftpboot"
#define CONFIG_SYS_IMG_NAME"uImage"
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
@@ -100,4 +114,3 @@
#define CONFIG_ENV_SIZE0x2 /* 64k */
#endif /* __CONFIG_GPLUGD_H */
-
--
1.7.0.4
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[U-Boot] [PATCH 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 39 +++
include/configs/gplugd.h| 20 +++-
4 files changed, 133 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 3d567eb..849638d 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_TIMER_BASE 0xD4014000
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO(MFP_REG(0x194) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP103_ETH_RXDV(MFP_REG(0x19C)
[U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 802 +++
drivers/net/armada100_fec.h | 225 +++
include/netdev.h|1 +
5 files changed, 1030 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..3d567eb 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,7 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_FEC_BASE 0xC080
/*
* Main Power Management (MPMU) Registers
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..67fd73d
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,802 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef ETH_DUMP_REGS
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static u8 get_random_byte(u8 seed)
+{
+ udelay(seed * 1000);
+ return (u8)(read_timer());
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val, reg_data;
+ int i = 0;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+ reg_data = readl(®s->phyadr);
+ *value = (u16) (reg_data & 0x1f);
+ return 0;
+ }
+
+ /* check parameters */
+ if (phy_addr > PHY_MASK) {
+ printf("Err..(%s) Invalid phy address: 0x%X\n",
+ __func__, phy_addr);
+ return -EINVAL;
+ }
+ if (phy_reg > PHY_MASK) {
+ printf("Err..(%s) Invalid register offset: 0x%X\n",
+ __func__, phy_reg);
+ return -EINVAL;
+ }
+
+ /* wait for the SMI register to become available */
+ for (i = 0; (val = readl(®s->smi)) & SMI_BUSY; i++) {
+
+ if (i == PHY_WAIT_ITERATIONS) {
+ printf("Error (%s) PHY busy timeout\n",
+ __func__);
+ return -1;
+
Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote: > On Monday, August 22, 2011 07:11:57 AM Ajay Bhargav wrote: > > This patch adds support for Fast Ethernet Controller driver for > > Armada100 series. > > > > Signed-off-by: Ajay Bhargav > > --- > > arch/arm/include/asm/arch-armada100/armada100.h |1 + > > drivers/net/Makefile|1 + > > drivers/net/armada100_fec.c | 802 > > +++ drivers/net/armada100_fec.h >| > > 225 +++ > > include/netdev.h|1 + > > 5 files changed, 1030 insertions(+), 0 deletions(-) > > create mode 100644 drivers/net/armada100_fec.c > > create mode 100644 drivers/net/armada100_fec.h > > > > Cheers! > Hi Marek, Thank you so much for the detailed comments :) really helpful. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote:
> On Monday, August 22, 2011 01:11:57 Ajay Bhargav wrote:
> > + writel((u32) darmdfec->htpr, ®s->htpr);
>
> do you really need to cast it yourself ? seems to show up a lot in
> this file.
>
> > +#ifdef ETH_DUMP_REGS
> > + eth_dump_regs(dev);
> > +#endif
>
> use #ifdef DEBUG
>
> > + while (cmd_sts & BUF_OWNED_BY_DMA) {
> > ...
> > + };
>
> no semi-colon needed
>
> > +int armada100_fec_initialize()
> > +{
> > ...
> > + darmdfec->regs = (void *) ARMD1_FEC_BASE;
>
> make the reg base a parameter to armada100_fec_initialize()
>
> > + darmdfec = malloc(sizeof(struct armdfec_device));
>
> sizeof(*darmdfec)
>
>
> > + while (!eth_getenv_enetaddr(s, dev->enetaddr)) {
> > + /* Generate Private MAC addr if not set */
> > + dev->enetaddr[0] = 0x00;
> > + dev->enetaddr[1] = 0x50;
> > + dev->enetaddr[2] = 0x43;
> > +#if defined(CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION)
> > + /* Generate fixed lower MAC half */
> > + dev->enetaddr[3] = 0x11;
> > + dev->enetaddr[4] = 0x22;
> > + dev->enetaddr[5] = 0x33;
> > +#else
> > + /* Generate random lower MAC half */
> > + dev->enetaddr[3] = get_random_byte((u8)read_timer());
> > + dev->enetaddr[4] = get_random_byte(dev->enetaddr[3]);
> > + dev->enetaddr[5] = get_random_byte(dev->enetaddr[4]);
> > +#endif
> > + eth_setenv_enetaddr(s, dev->enetaddr);
> > + }
>
> NAK on this whole thing. initialize dev->write_hwaddr and that is the
> only
> thing you should do. the higher eth layers will take care of calling
> that as
> necessary.
>
> > + dev->init = (void *) armdfec_init;
> > + dev->halt = (void *) armdfec_halt;
> > + dev->send = (void *) armdfec_send;
> > + dev->recv = (void *) armdfec_recv;
>
> drop the (void*) casts. either you dont need them, or your funcs here
> are
> wrong and need fixing.
>
> > +#if defined(CONFIG_PHY_BASE_ADR)
> > + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ,
> > +(u16) CONFIG_PHY_BASE_ADR);
> > +#else
> > + /* Search phy address from range 0-31 */
> > + phy_adr = ethernet_phy_detect(dev);
> > + if (phy_adr < 0) {
> > + printf("Error: PHY not detected at address range 0-31\n");
> > + return -1;
> > + } else {
> > + debug("PHY detected at addr %d\n", phy_adr);
> > + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ,
> > +(u16) phy_adr);
> > + }
> > +#endif
>
> this should be done in the armdfec_init() func, not the initialize
> func
> -mike
Hi Mike,
Thank you for comments.. I will make the required changes.
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Monday, August 22, 2011 07:11:57 AM Ajay Bhargav wrote:
> > This patch adds support for Fast Ethernet Controller driver for
> > Armada100 series.
> >
> > Signed-off-by: Ajay Bhargav
> > ---
> > arch/arm/include/asm/arch-armada100/armada100.h |1 +
> > drivers/net/Makefile|1 +
> > drivers/net/armada100_fec.c | 802
> > +++ drivers/net/armada100_fec.h
>|
> > 225 +++
> > include/netdev.h|1 +
> > 5 files changed, 1030 insertions(+), 0 deletions(-)
> > create mode 100644 drivers/net/armada100_fec.c
> > create mode 100644 drivers/net/armada100_fec.h
> >
[...]
> > +static u8 get_random_byte(u8 seed)
> > +{
> > + udelay(seed * 1000);
> > + return (u8)(read_timer());
>
> Parens not needed, anyway, don't we have any better "random()" here ?
>
I could not find random() function anywhere in the u-boot source.
[...]
> > + /* Generate random lower MAC half */
> > + dev->enetaddr[3] = get_random_byte((u8)read_timer());
> > + dev->enetaddr[4] = get_random_byte(dev->enetaddr[3]);
> > + dev->enetaddr[5] = get_random_byte(dev->enetaddr[4]);
> > +#endif
>
> Won't uboot handle this ... or aren't there some mechanisms to
> generate random
> MAC that can be reused?
>
There is a program given in tools directory for generating ethernet mac
"gen_eth_addr.c" but nothing as such in u-boot source as far as i checked.
Please let me know if I missed something to check.
Thanks & Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Tuesday, August 23, 2011 08:11:57 AM Ajay Bhargav wrote:
> > - "Marek Vasut" wrote:
> > > On Monday, August 22, 2011 07:11:57 AM Ajay Bhargav wrote:
> > > > This patch adds support for Fast Ethernet Controller driver for
> > > > Armada100 series.
> > > >
> > > > Signed-off-by: Ajay Bhargav
> > > > ---
> > > >
> > > > arch/arm/include/asm/arch-armada100/armada100.h |1 +
> > > > drivers/net/Makefile|1 +
> > > > drivers/net/armada100_fec.c | 802
> > > >
> > > > +++ drivers/net/armada100_fec.h
> > > >
> > > > 225 +++
> > > >
> > > > include/netdev.h|1 +
> > > > 5 files changed, 1030 insertions(+), 0 deletions(-)
> > > > create mode 100644 drivers/net/armada100_fec.c
> > > > create mode 100644 drivers/net/armada100_fec.h
> >
> > [...]
> >
> > > > +static u8 get_random_byte(u8 seed)
> > > > +{
> > > > + udelay(seed * 1000);
> > > > + return (u8)(read_timer());
> > >
> > > Parens not needed, anyway, don't we have any better "random()"
> here ?
> >
> > I could not find random() function anywhere in the u-boot source.
> >
> > [...]
> >
> > > > + /* Generate random lower MAC half */
> > > > + dev->enetaddr[3] = get_random_byte((u8)read_timer());
> > > > + dev->enetaddr[4] = get_random_byte(dev->enetaddr[3]);
> > > > + dev->enetaddr[5] = get_random_byte(dev->enetaddr[4]);
> > > > +#endif
> > >
> > > Won't uboot handle this ... or aren't there some mechanisms to
> > > generate random
> > > MAC that can be reused?
> >
> > There is a program given in tools directory for generating ethernet
> mac
> > "gen_eth_addr.c" but nothing as such in u-boot source as far as i
> checked.
> >
> > Please let me know if I missed something to check.
>
> Hi,
>
> I think someone NAKed this whole part with MAC randomisation and he
> was right
> about it ... you're supposed to configure the MAC properly yourself.
> Cheers
> >
> > Thanks & Regards,
> > Ajay Bhargav
>
MAC randomization is done in U-Boot by many already. I am confused... just like
i was when working with GPIO :) Is it something which has changed lately?
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Wolfgang Denk" wrote: > Dear Ajay Bhargav, > > In message > <1058764603.122757.1314095393033.javamail.r...@ahm.einfochips.com> you > wrote: > > > > > I think someone NAKed this whole part with MAC randomisation and > he was right > > > about it ... you're supposed to configure the MAC properly > yourself. > ... > > MAC randomization is done in U-Boot by many already. I am > > U-Boot is big and contains lots of poor code. And many people have a > strange skill of always picking poor examples only when copying code. > So it always makes sense to double-check. > I agree :) Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Wolfgang Denk" wrote: > Dear Ajay Bhargav, > > In message > <1058764603.122757.1314095393033.javamail.r...@ahm.einfochips.com> you > wrote: > > > > > I think someone NAKed this whole part with MAC randomisation and > he was right > > > about it ... you're supposed to configure the MAC properly > yourself. > ... > > MAC randomization is done in U-Boot by many already. I am > > U-Boot is big and contains lots of poor code. And many people have a > strange skill of always picking poor examples only when copying code. > So it always makes sense to double-check. > > > confused... just like i was when working with GPIO :) Is it > something > > which has changed lately? > > No, this has not changed lately. > > Just re-read Mike's message: > http://article.gmane.org/gmane.comp.boot-loaders.u-boot/106117 > > > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > It seems intuitively obvious to me, which means that it might be > wrong. -- Chris Torek > Dear Wolfgang, ok I just wanted to clear myself.. I do not have a dedicated hardware storage in my ethernet controller so I will just look into environment variable ethaddr, if its set I will just copy it to driver layer and if it is not set, I let the user set it. He/She may use the tools provided with U-Boot to generate a random MAC or by any mean get a MAC and store it in env which is gonna be one time unless env gets corrupt or cleared by user. Which means no MAC generation in code... Please correct me if my understanding wrong... Thanks & Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Wolfgang Denk" wrote: > Dear Ajay Bhargav, > > In message > <1570238601.123783.1314104389736.javamail.r...@ahm.einfochips.com> you > wrote: > > > > ok I just wanted to clear myself.. I do not have a dedicated > hardware > > storage in my ethernet controller so I will just look into > environment > > variable ethaddr, if its set I will just copy it to driver layer > and > > if it is not set, I let the user set it. He/She may use the tools > provided > > with U-Boot to generate a random MAC or by any mean get a MAC and > store it > > in env which is gonna be one time unless env gets corrupt or cleared > by user. > > Which means no MAC generation in code... > > > > Please correct me if my understanding wrong... > > This is correct, except for the nitpick that nobody should ever use a > truly random MAC address - if no valid MAC address is available, one > should at least make sure to pick one of the locally administered > Ethernet address pool (2nd LSB in the most significant byte of the > address must be set). > > Best regards, > > Wolfgang Denk > Dear Wolfgang, Thank you so much for clarification. I tested u-boot on board with no random MAC and its working perfectly once user set it. Thanks again... Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- armada100_fec_initialize changed to armada100_fec_register
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 39 +++
include/configs/gplugd.h| 19 +++-
4 files changed, 132 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 3d567eb..849638d 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_TIMER_BASE 0xD4014000
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP101_ETH_MDIO(MFP_REG(0x194)
[U-Boot] [PATCH v2 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
board/Marvell/gplugd/gplugd.c | 33 -
include/configs/gplugd.h | 14 ++
2 files changed, 46 insertions(+), 1 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index 4cd4086..bf3cdb4 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,5 +104,29 @@ int board_eth_init(bd_t *bis)
return armada100_fec_register();
}
-#endif /* CONFIG_ARMADA100_FEC */
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ printf("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index f3b94d8..b63ffd5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -80,6 +80,20 @@
#define CONFIG_ROOTPATH"/tftpboot"
#define CONFIG_SYS_IMG_NAME"uImage"
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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[U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- removed random MAC generation
- driver init function changed to register as per new naming convention
- code cleanup (Thanks to Wolfgang, Marek & Mike for tips)
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 761 +++
drivers/net/armada100_fec.h | 232 +++
include/netdev.h|1 +
5 files changed, 996 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..3d567eb 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,7 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_FEC_BASE 0xC080
/*
* Main Power Management (MPMU) Registers
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..e36dca6
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,761 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 reg, u32 flag, int cond)
+{
+ u32 timeout = PHY_WAIT_ITERATIONS;
+ while (--timeout) {
+ if (cond && (readl(reg) & flag))
+ break;
+ else if (!cond && !(readl(reg) & flag))
+ break;
+ udelay(PHY_WAIT_MICRO_SECONDS);
+ }
+ return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val, reg_data;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+ reg_data = readl(®s->phyadr);
+ *value = (u16) (reg_data & 0x1f);
+ return 0;
+ }
+
+ /* check parameters */
+ if (phy_addr > PHY_MASK) {
+ printf("Err..(%s) Invalid phy address: 0x%X\n",
+ __func__, phy_addr);
+ return -EINVAL;
+ }
+ if (phy_reg > PHY_MASK) {
+
Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote:
> On Wednesday, August 24, 2011 09:07:18 Ajay Bhargav wrote:
> > + darmdfec->p_rxdesc = (struct rx_desc *) memalign(PKTALIGN,
> > + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ +
> 1);
>
> memalign() returns a void*, so you shouldnt need to cast its return
> value (you
> do this a couple of times)
>
> > + /* Read mac from env if available */
> > + eth_getenv_enetaddr("ethaddr", dev->enetaddr);
>
> you shouldnt need to do this. the higher layers will take care of
> this for
> you when you set write_hwaddr
>
I do not have a hardware storage for MAC on my controller. write_hwaddr
is not needed for me.
> also, it seems like some of my previous feedback wasnt addressed ?
>
I might have missed some points. My apologies.
> > + while (cmd_sts & BUF_OWNED_BY_DMA) {
> > ...
> > + };
>
> no semi-colon needed
>
> > +int armada100_fec_initialize()
> > +{
> > ...
> > + darmdfec->regs = (void *) ARMD1_FEC_BASE;
>
> make the reg base a parameter to armada100_fec_initialize()
>
This driver is for Armada100 series and base address is same for
the whole series, so i did not feel passing it as a parameter. Can
you please tell me if there is any specific reason for the same?
> > +#if defined(CONFIG_PHY_BASE_ADR)
> > + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ,
> > + (u16) CONFIG_PHY_BASE_ADR);
> > +#else
> > + /* Search phy address from range 0-31 */
> > + phy_adr = ethernet_phy_detect(dev);
> > + if (phy_adr < 0) {
> > + printf("Error: PHY not detected at address range
> 0-31\n");
> > + return -1;
> > + } else {
> > + debug("PHY detected at addr %d\n", phy_adr);
> > + miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ,
> > + (u16) phy_adr);
> > + }
> > +#endif
>
> this should be done in the armdfec_init() func, not the initialize
> func
> -mike
Okay.. will move it there.
Thanks & Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH v2 2/3] Armada100: Enable Ethernet support for GplugD
- "Marek Vasut" wrote: [...] > > +/* Disable DCACHE */ > > +#define CONFIG_SYS_DCACHE_OFF > > ARMADA100 is still ARMv5? Then maybe you can try Hong Xu's patches for > dcache on > armv5. You'll have to modify the ethernet driver to be aware of the > dcache then > though. > > As dcache support is on the way, it might be worth it. > Yes ARMADA100 is ARMv5. I had problems with dcache enabled, driver get stuck. Can you please link me to Hong Xu's patches? Is there a problem if i keep it disabled? Thanks, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Wednesday, August 24, 2011 03:07:18 PM Ajay Bhargav wrote:
> > This patch adds support for Fast Ethernet Controller driver for
> > Armada100 series.
> >
> > Signed-off-by: Ajay Bhargav
> > ---
>
> [...]
>
[...]
> > +
> > +static int armdfec_phy_timeout(u32 reg, u32 flag, int cond)
> > +{
> > + u32 timeout = PHY_WAIT_ITERATIONS;
> > + while (--timeout) {
> > + if (cond && (readl(reg) & flag))
> > + break;
> > + else if (!cond && !(readl(reg) & flag))
>
> You can read the register into some temporary variable so you don't
> need the
> readl() at two places.
>
readl will be called only once... do i really need a temp var?
> > + break;
> > + udelay(PHY_WAIT_MICRO_SECONDS);
> > + }
> > + return !timeout;
> > +}
> > +
> > +static int smi_reg_read(const char *devname, u8 phy_addr, u8
> phy_reg,
> > + u16 *value)
> > +{
> > + struct eth_device *dev = eth_get_dev_by_name(devname);
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > + struct armdfec_reg *regs = darmdfec->regs;
> > + u32 val, reg_data;
> > +
> > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
> > + reg_data = readl(®s->phyadr);
> > + *value = (u16) (reg_data & 0x1f);
> > + return 0;
> > + }
> > +
> > + /* check parameters */
> > + if (phy_addr > PHY_MASK) {
> > + printf("Err..(%s) Invalid phy address: 0x%X\n",
> > + __func__, phy_addr);
> > + return -EINVAL;
> > + }
> > + if (phy_reg > PHY_MASK) {
> > + printf("Err..(%s) Invalid register offset: 0x%X\n",
> > + __func__, phy_reg);
> > + return -EINVAL;
> > + }
> > +
> > + /* wait for the SMI register to become available */
> > + if (armdfec_phy_timeout((u32)®s->smi, SMI_BUSY, FALSE)) {
>
> Adjust the function so you don't need the cast.
>
okay...
> > + printf("Error (%s) PHY busy timeout\n", __func__);
> > + return -1;
> > + }
> > +
> > + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_R, ®s->smi);
>
> Parentheses missing maybe ?
>
:) okay..
> > +
> > + /* now wait for the data to be valid */
> > + if (armdfec_phy_timeout((u32)®s->smi, SMI_R_VALID, TRUE)) {
> > + val = readl(®s->smi);
> > + printf("Err (%s) PHY Read timeout, val=0x%x\n", __func__, val);
> > + return -1;
> > + }
> > + val = readl(®s->smi);
> > + *value = val & 0x;
> > +
> > + return 0;
> > +}
> > +
> > +static int smi_reg_write(const char *devname,
> > +u8 phy_addr, u8 phy_reg, u16 value)
> > +{
> > + struct eth_device *dev = eth_get_dev_by_name(devname);
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > + struct armdfec_reg *regs = darmdfec->regs;
> > +
> > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
> > + clrsetbits_le32(®s->phyadr, 0x1f, value & 0x1f);
> > + return 0;
> > + }
> > +
> > + /* check parameters */
> > + if (phy_addr > PHY_MASK) {
> > + printf("Err..(%s) Invalid phy address\n", __func__);
> > + return -EINVAL;
> > + }
> > + if (phy_reg > PHY_MASK) {
> > + printf("Err..(%s) Invalid register offset\n", __func__);
> > + return -EINVAL;
> > + }
> > +
> > + /* wait for the SMI register to become available */
> > + if (armdfec_phy_timeout((u32)®s->smi, SMI_BUSY, FALSE)) {
> > + printf("Error (%s) PHY busy timeout\n", __func__);
> > + return -1;
> > + }
> > +
> > + writel(phy_addr << 16 | phy_reg << 21 | SMI_OP_W | (value &
> 0x),
> > + ®s->smi);
> > + return 0;
> > +}
> > +
> > +/*
> > + * Abort any transmit and receive operations and put DMA
> > + * in idle state. AT and AR bits are cleared upon entering
> > + * in IDLE state. So poll those bits to verify operation.
> > + */
> > +static void abortdma(struct eth_device *dev)
> > +{
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> >
Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Wednesday, August 24, 2011 05:42:06 PM Mike Frysinger wrote:
> > On Wednesday, August 24, 2011 09:07:18 Ajay Bhargav wrote:
> > > + darmdfec->p_rxdesc = (struct rx_desc *)
> memalign(PKTALIGN,
> > > + ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ +
> 1);
> >
> > memalign() returns a void*, so you shouldnt need to cast its return
> value
> > (you do this a couple of times)
> >
> > > + /* Read mac from env if available */
> > > + eth_getenv_enetaddr("ethaddr", dev->enetaddr);
> >
> > you shouldnt need to do this. the higher layers will take care of
> this for
> > you when you set write_hwaddr
> >
> > also, it seems like some of my previous feedback wasnt addressed ?
>
> I have exactly the same feeling :-(
>
> Ajay, please go through the feedback, if you don't understand
> something, just
> ask instead of hoping we won't notice ... we will, we see everything
> ;-)
>
> Cheers
>
I did go through your feedbacks.. My apologies if I missed. Marek, Its good
for me that you guys are monitoring :) it will surely help me to write a better
code :)
Thanks,
Ajay Bhargav
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Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
[...]
> > +static void abortdma(struct eth_device *dev)
> > +{
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > + struct armdfec_reg *regs = darmdfec->regs;
> > + int delay;
> > + int maxretries = 40;
> > +
> > + do {
> > + writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
> > + udelay(100);
> > +
> > + delay = 10;
> > + while ((readl(®s->sdma_cmd) &
> > + (SDMA_CMD_AR | SDMA_CMD_AT))
> > + && delay-- > 0) {
> > + udelay(10);
> > + }
> > + } while (maxretries-- > 0 && delay <= 0);
>
> Didn't I comment on this one in V1?
>
I modified it as follows... Is it more readable now? :)
while (maxretries--) {
writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
udelay(100);
delay = 10;
while ((readl(®s->sdma_cmd) & (SDMA_CMD_AR | SDMA_CMD_AT))
&& delay--)
udelay(10);
if(delay)
break;
}
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH v2 2/3] Armada100: Enable Ethernet support for GplugD
- "Marek Vasut" wrote: > On Thursday, August 25, 2011 07:15:17 AM Ajay Bhargav wrote: > > - "Marek Vasut" wrote: > > [...] > > > > > > +/* Disable DCACHE */ > > > > +#define CONFIG_SYS_DCACHE_OFF > > > > > > ARMADA100 is still ARMv5? Then maybe you can try Hong Xu's patches > for > > > dcache on > > > armv5. You'll have to modify the ethernet driver to be aware of > the > > > dcache then > > > though. > > > > > > As dcache support is on the way, it might be worth it. > > > > Yes ARMADA100 is ARMv5. I had problems with dcache enabled, driver > get > > stuck. Can you please link me to Hong Xu's patches? Is there a > problem if > > i keep it disabled? > > http://lists.denx.de/pipermail/u-boot/2011-August/098405.html Look > around this. > You'd better search for V2 of the patches or V3 in U-Boot ML archive. > > There's no problem if you keep it disabled, but eventually, you'll > have to > enable it ;-) > > Cheers Hi Marek, I searched mail list after I emailed you.. There has been a lot of discussion going on Hong Xu's patches. I think it would be better if I work on enabling dcache once the patch is mainlined. Thanks, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Thursday, August 25, 2011 01:07:32 PM Ajay Bhargav wrote:
> > - "Marek Vasut" wrote:
> >
> > [...]
> >
> > > > +static void abortdma(struct eth_device *dev)
> > > > +{
> > > > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > > > + struct armdfec_reg *regs = darmdfec->regs;
> > > > + int delay;
> > > > + int maxretries = 40;
> > > > +
> > > > + do {
> > > > + writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
> > > > + udelay(100);
> > > > +
> > > > + delay = 10;
> > > > + while ((readl(®s->sdma_cmd) &
> > > > + (SDMA_CMD_AR | SDMA_CMD_AT))
> > > > + && delay-- > 0) {
> > > > + udelay(10);
> > > > + }
> > > > + } while (maxretries-- > 0 && delay <= 0);
> > >
> > > Didn't I comment on this one in V1?
> >
> > I modified it as follows... Is it more readable now? :)
> >
> > while (maxretries--) {
> > writel(SDMA_CMD_AR | SDMA_CMD_AT, ®s->sdma_cmd);
> > udelay(100);
> >
> > delay = 10;
> > while ((readl(®s->sdma_cmd) & (SDMA_CMD_AR | SDMA_CMD_AT))
> > && delay--)
> > udelay(10);
> > if(delay)
> > break;
>
> delay = 10;
> while (--delay) {
> tmp = readl(®s->sdma_cmd);
> if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT))
> break;
> udelay(10);
> }
> if (delay)
> break;
>
> It makes the code horizontally shorter. What do you think? Btw there's
> a rule in
> U-Boot that multi-line statements must have braces.
>
Thanks Marek, Yes it looks much better :) see the plus point on working with
experts rather
running away? :D
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH v2 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote:
> On Thursday, August 25, 2011 01:10:30 Ajay Bhargav wrote:
> > - "Mike Frysinger" wrote:
> > > On Wednesday, August 24, 2011 09:07:18 Ajay Bhargav wrote:
> > > > + /* Read mac from env if available */
> > > > + eth_getenv_enetaddr("ethaddr", dev->enetaddr);
> > >
> > > you shouldnt need to do this. the higher layers will take care
> of
> > > this for
> > > you when you set write_hwaddr
> >
> > I do not have a hardware storage for MAC on my controller.
> write_hwaddr
> > is not needed for me.
>
> ok, but you should not be touching dev->enetaddr in your registration
>
> function. the main net/eth.c:eth_initialize() takes care of this for
> you.
>
> > > > +int armada100_fec_initialize()
> > > > +{
> > > > ...
> > > > + darmdfec->regs = (void *) ARMD1_FEC_BASE;
> > >
> > > make the reg base a parameter to armada100_fec_initialize()
> >
> > This driver is for Armada100 series and base address is same for
> > the whole series, so i did not feel passing it as a parameter. Can
> > you please tell me if there is any specific reason for the same?
>
> drivers should be written for the IP they control, not for specific
> SoCs or
> boards. and what people often start off with "this SoC only has one
> MAC so
> screw multi-instance" quite frequently turns into "this next SoC
> supports
> multiple MACs!".
>
> i'm not familiar with the Armada100, or the MAC IP that is in that
> SoC, but
> this story repeats itself constantly in the SoC world because people
> focus on
> the one specific SoC they have in their hand and not the bigger
> picture.
> simply witness the ARM hell that Linux is currently in and is being
> cleaned up
> through the Linaro organization.
> -mike
Hi Mike,
I got your point.. Thanks for clearing this. I will make sure that this
kind of problem does not happen in my case :)
Regards,
Ajay
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[U-Boot] [PATCH v3 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
Changes for v3:
- code cleanup; removed unwated cast
board/Marvell/gplugd/gplugd.c | 33 -
include/configs/gplugd.h | 14 ++
2 files changed, 46 insertions(+), 1 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index db4d776..a7cabcd 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,5 +104,29 @@ int board_eth_init(bd_t *bis)
return armada100_fec_register(ARMD1_FEC_BASE);
}
-#endif /* CONFIG_ARMADA100_FEC */
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index f3b94d8..b63ffd5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -80,6 +80,20 @@
#define CONFIG_ROOTPATH"/tftpboot"
#define CONFIG_SYS_IMG_NAME"uImage"
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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[U-Boot] [PATCH v3 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- armada100_fec_initialize changed to armada100_fec_register
Changes for v3:
- fec base address as argument to armada100_fec_register
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 39 +++
include/configs/gplugd.h| 19 +++-
4 files changed, 132 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 3d567eb..849638d 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_TIMER_BASE 0xD4014000
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP100_ETH_MDC (MFP_REG(0x190)
[U-Boot] [PATCH v3 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- removed random MAC generation
- driver init function changed to register as per new naming convention
- code cleanup (Thanks to Wolfgang, Marek & Mike for tips)
Changes for v3:
- code cleanup
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 759 +++
drivers/net/armada100_fec.h | 232 +++
include/netdev.h|1 +
5 files changed, 994 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..3d567eb 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,7 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_FEC_BASE 0xC080
/*
* Main Power Management (MPMU) Registers
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..9362fe1
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,759 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
+{
+ u32 timeout = PHY_WAIT_ITERATIONS;
+ u32 reg_val;
+
+ while (--timeout) {
+ reg_val = readl(reg);
+ if (cond && (reg_val & flag))
+ break;
+ else if (!cond && !(reg_val & flag))
+ break;
+ udelay(PHY_WAIT_MICRO_SECONDS);
+ }
+ return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val, reg_data;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+ reg_data = readl(®s->phyadr);
+ *value = (u16) (reg_data & 0x1f);
+ return 0;
+ }
+
+ /* check parameters */
+ if (phy_addr > PHY_MASK) {
+ printf("Err..(%s) Invalid phy address: 0x%X\n",
+ __func__, phy_addr
Re: [U-Boot] [PATCH v3 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote:
> On Friday, August 26, 2011 02:36:51 Ajay Bhargav wrote:
> > +static int add_del_hash_entry(struct armdfec_device *darmdfec, u32
> mach,
> > + u32 macl, u32 rd, u32 skip, int del)
> > +{
> > +u8 *last;
>
> local var ...
>
> > +last = (u8 *) entry;
> > +last = last + sizeof(*entry);
> > +
> > +return 0;
> > +}
>
> so what's the point of these two assignments to "last" ?
>
I forgot to delete them during cleanup of initial code. Thanks for
pointing.
> > +int armada100_fec_register(int base_addr)
>
> when it comes to addresses for memory mapped registers, we typically
> use
> "unsigned long" rather than "int"
>
yes right...
> > +darmdfec = malloc(sizeof(struct armdfec_device));
> > +if (!darmdfec)
> > +goto error;
>
> if this first one fails, we jump to:
>
> > +error:
> > +free(darmdfec->p_aligned_txbuf);
> > +free(darmdfec->p_rxbuf);
> > +free(darmdfec->p_rxdesc);
> > +free(darmdfec->htpr);
>
> looks like 4 NULL pointer derefs. so you'll need one specific path
> for the
> first malloc(), but the rest are fine.
> -mike
so you mean like this...
if(!darmdfec)
goto error;
...
error1:
free(darmdfec->p_aligned_txbuf);
free(darmdfec->p_rxbuf);
free(darmdfec->p_rxdesc);
free(darmdfec->htpr);
error:
free(darmdfec);
return -1;
Thanks,
Ajay Bhargav
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Re: [U-Boot] [PATCH v3 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Friday, August 26, 2011 08:36:51 AM Ajay Bhargav wrote:
> > This patch adds support for Fast Ethernet Controller driver for
> > Armada100 series.
> >
> > Signed-off-by: Ajay Bhargav
>
> Hi, please don't forget to CC me next time ;-)
>
Sure, I'll do that.. you and Mike both :)
> [...]
>
> > +static int smi_reg_read(const char *devname, u8 phy_addr, u8
> phy_reg,
> > + u16 *value)
> > +{
> > + struct eth_device *dev = eth_get_dev_by_name(devname);
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > + struct armdfec_reg *regs = darmdfec->regs;
> > + u32 val, reg_data;
> > +
> > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
> > + reg_data = readl(®s->phyadr);
> > + *value = (u16) (reg_data & 0x1f);
>
> Do you need this cast?
>
I thought I fixed most of the cast related issues :) looks like I missed one.
>
> Unify the error reporting please.
>
I will do that...
> It looks good, just a few nits
>
> Cheers!
>
Cheers! :)
Ajay Bhargav
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Re: [U-Boot] [PATCH v3 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote: > On Monday, August 29, 2011 01:10:49 Ajay Bhargav wrote: > > - "Mike Frysinger" wrote: > > > On Friday, August 26, 2011 02:36:51 Ajay Bhargav wrote: > > > > +darmdfec = malloc(sizeof(struct armdfec_device)); > > > > +if (!darmdfec) > > > > +goto error; > > > > > > if this first one fails, we jump to: > > > > +error: > > > > +free(darmdfec->p_aligned_txbuf); > > > > +free(darmdfec->p_rxbuf); > > > > +free(darmdfec->p_rxdesc); > > > > +free(darmdfec->htpr); > > > > > > looks like 4 NULL pointer derefs. so you'll need one specific > path > > > for the first malloc(), but the rest are fine. > > > > so you mean like this... > > > > if(!darmdfec) > > goto error; > > ... > > error1: > > free(darmdfec->p_aligned_txbuf); > > free(darmdfec->p_rxbuf); > > free(darmdfec->p_rxdesc); > > free(darmdfec->htpr); > > error: > > free(darmdfec); > > return -1; > > that's one way of fixing it > -mike Any other better way? --Ajay ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote: > On Monday, August 29, 2011 01:39:18 Ajay Bhargav wrote: > > - "Mike Frysinger" wrote: > > > On Monday, August 29, 2011 01:10:49 Ajay Bhargav wrote: > > > > - "Mike Frysinger" wrote: > > > > > On Friday, August 26, 2011 02:36:51 Ajay Bhargav wrote: > > > > > > +darmdfec = malloc(sizeof(struct armdfec_device)); > > > > > > +if (!darmdfec) > > > > > > +goto error; > > > > > > > > > > if this first one fails, we jump to: > > > > > > +error: > > > > > > +free(darmdfec->p_aligned_txbuf); > > > > > > +free(darmdfec->p_rxbuf); > > > > > > +free(darmdfec->p_rxdesc); > > > > > > +free(darmdfec->htpr); > > > > > > > > > > looks like 4 NULL pointer derefs. so you'll need one > specific > > > > > > path > > > > > > > > for the first malloc(), but the rest are fine. > > > > > > > > so you mean like this... > > > > > > > > if(!darmdfec) > > > > > > > > goto error; > > > > > > > > ... > > > > > > > > error1: > > > > free(darmdfec->p_aligned_txbuf); > > > > free(darmdfec->p_rxbuf); > > > > free(darmdfec->p_rxdesc); > > > > free(darmdfec->htpr); > > > > > > > > error: > > > > free(darmdfec); > > > > return -1; > > > > > > that's one way of fixing it > > > > Any other better way? > > since all your buffers are known fixed (at compile time) sizes, you > could > simply inline them into the structure so you only malloc() one buffer > -mike Yes.. thats another way of coding :) I will stick to previous one.. Thanks, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- removed random MAC generation
- driver init function changed to register as per new naming convention
- code cleanup (Thanks to Wolfgang, Marek & Mike for tips)
Changes for v3:
- code cleanup
Changes for v4:
- Debug and Error messages updated
- base_addr param for armada100_fec_register changed to unsigned long
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 762 +++
drivers/net/armada100_fec.h | 232 +++
include/netdev.h|1 +
5 files changed, 997 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..3d567eb 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,7 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_FEC_BASE 0xC080
/*
* Main Power Management (MPMU) Registers
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..626b50c
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,762 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
+{
+ u32 timeout = PHY_WAIT_ITERATIONS;
+ u32 reg_val;
+
+ while (--timeout) {
+ reg_val = readl(reg);
+ if (cond && (reg_val & flag))
+ break;
+ else if (!cond && !(reg_val & flag))
+ break;
+ udelay(PHY_WAIT_MICRO_SECONDS);
+ }
+ return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val, reg_data;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+ reg_data = readl(®s->phyadr);
+ *value = reg_data & 0x1f;
+ return 0;
+ }
+
+ /* check parameters */
+
[U-Boot] [PATCH v4 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
Changes for v3:
- code cleanup; removed unwated cast
Changes for v4:
- Not changed
board/Marvell/gplugd/gplugd.c | 33 -
include/configs/gplugd.h | 14 ++
2 files changed, 46 insertions(+), 1 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index db4d776..a7cabcd 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,5 +104,29 @@ int board_eth_init(bd_t *bis)
return armada100_fec_register(ARMD1_FEC_BASE);
}
-#endif /* CONFIG_ARMADA100_FEC */
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, (u16 *) &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
+#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index f3b94d8..b63ffd5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -80,6 +80,20 @@
#define CONFIG_ROOTPATH"/tftpboot"
#define CONFIG_SYS_IMG_NAME"uImage"
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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[U-Boot] [PATCH v4 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- armada100_fec_initialize changed to armada100_fec_register
Changes for v3:
- fec base address as argument to armada100_fec_register
Changes for v4:
- Not changed
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 39 +++
include/configs/gplugd.h| 19 +++-
4 files changed, 132 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 3d567eb..849638d 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_TIMER_BASE 0xD4014000
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP1
Re: [U-Boot] [PATCH v4 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Marek Vasut" wrote:
> On Tuesday, August 30, 2011 07:44:40 AM Ajay Bhargav wrote:
> > This patch adds support for Fast Ethernet Controller driver for
> > Armada100 series.
> >
> > Signed-off-by: Ajay Bhargav
>
> [...]
>
> > +static int smi_reg_read(const char *devname, u8 phy_addr, u8
> phy_reg,
> > + u16 *value)
> > +{
> > + struct eth_device *dev = eth_get_dev_by_name(devname);
> > + struct armdfec_device *darmdfec = to_darmdfec(dev);
> > + struct armdfec_reg *regs = darmdfec->regs;
> > + u32 val, reg_data;
> > +
> > + if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
> > + reg_data = readl(®s->phyadr);
>
> You use "reg_data" here and "val" below ... can't you use just one
> variable?
>
Yes.. sorry for mistake.
> [...]
>
> > +static int add_del_hash_entry(struct armdfec_device *darmdfec, u32
> mach,
> > + u32 macl, u32 rd, u32 skip, int del)
> > +{
> > + struct addr_table_entry_t *entry, *start;
> > + u32 newhi;
> > + u32 newlo;
> > + u32 i;
> > +
> > + newlo = (((mach >> 4) & 0xf) << 15)
> > + | (((mach >> 0) & 0xf) << 11)
> > + | (((mach >> 12) & 0xf) << 7)
> > + | (((mach >> 8) & 0xf) << 3)
> > + | (((macl >> 20) & 0x1) << 31)
> > + | (((macl >> 16) & 0xf) << 27)
> > + | (((macl >> 28) & 0xf) << 23)
> > + | (((macl >> 24) & 0xf) << 19)
> > + | (skip << HTESKIP) | (rd << HTERDBIT)
> > + | HTEVALID;
> > +
> > + newhi = (((macl >> 4) & 0xf) << 15)
> > + | (((macl >> 0) & 0xf) << 11)
> > + | (((macl >> 12) & 0xf) << 7)
> > + | (((macl >> 8) & 0xf) << 3)
> > + | (((macl >> 21) & 0x7) << 0);
> > +
> > + /*
> > +* Pick the appropriate table, start scanning for free/reusable
> > +* entries at the index obtained by hashing the specified MAC
> address
> > +*/
> > + start = (struct addr_table_entry_t *) (darmdfec->htpr);
> > + entry = start + hash_function(mach, macl);
> > + for (i = 0; i < HOP_NUMBER; i++) {
> > + if (!(entry->lo & HTEVALID)) {
> > + break;
> > + } else {
> > + /* if same address put in same position */
> > + if (((entry->lo & 0xfff8) == (newlo & 0xfff8))
> > + && (entry->hi == newhi))
> > + break;
> > + }
>
> What about
>
> if (!(entry->lo & HTEVALID))
> break;
>
> if (((entry->lo & 0xfff8) == (newlo & 0xfff8))
> && (entry->hi == newhi)) {
> break;
> }
>
> ? :-)
>
No.. if entry is valid, we should not modify it anyways. Deleting a valid entry
might break the hash chain.
> > + if (entry == start + 0x7ff)
> > + entry = start;
> > + else
> > + entry++;
> > + }
> > +
> > + if (((entry->lo & 0xfff8) != (newlo & 0xfff8)) &&
> > + (entry->hi != newhi) && del)
> > + return 0;
>
> Now thinking of it, are you sure about this condition ? Shouldn't the
> first && be
> || instead ? And there should be parenthesis around that ?
>
if delete is requested for an address which is not present in chain, we should
return immideatly. so && is fine there.
> > +
> > + if (i == HOP_NUMBER) {
> > + if (!del) {
> > + printf("ARMD100 FEC: (%s) table section is full\n",
> > + __func__);
> > + return -ENOSPC;
> > + } else {
> > + return 0;
> > + }
> > + }
>
> [...]
>
> > +
> > + /* 64 should work but does not -- dhcp packets NEVER get
> transmitted. */
>
> What's this about ?
>
> > + if ((mtu > MAX_PKT_SIZE) || (mtu < 64))
> > + return -EINVAL;
>
> [...]
>
> > +static int armdfec_send(struct eth_device *dev, volatile void
> *data
Re: [U-Boot] [PATCH v4 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Mike Frysinger" wrote:
> On Tuesday, August 30, 2011 01:44:40 Ajay Bhargav wrote:
> > +static void update_hash_table_mac_address(struct armdfec_device
> *darmdfec,
> > + u8 *oaddr, u8 *addr)
> > +{
> > + u32 mach;
> > + u32 macl;
> > +
> > + /* Delete old entry */
> > + if (oaddr) {
> > + mach = (oaddr[0] << 8) | oaddr[1];
> > + macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
> > + (oaddr[4] << 8) | oaddr[5];
> > + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
> > + }
> > +
> > + /* Add new entry */
> > + mach = (addr[0] << 8) | addr[1];
> > + macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
> addr[5];
> > + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
> > +}
> > ...
> > +static int armdfec_init(struct eth_device *dev, bd_t *bd)
> > +{
> > ...
> > + update_hash_table_mac_address(darmdfec, dev->enetaddr,
> dev->enetaddr);
>
> i think something got lost along the way here :)
>
> you'll probably want to have oaddr[] be a static local in
> update_hash_table_mac_address and use that to delete the old one when
> it
> differs from the new one, and then copy the new one into the static
> local.
> -mike
You can have multiple entries in Hash table for different MAC addresses.
The reason old entry is deleted because it may be possible that hash entry
in the list is skipped but not invalidated so the same entry is made valid
in the list after removing the old one and updating list with new entry.
The calculated has for a particular MAC address is going to be same.
Thanks,
Ajay Bhargav
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Re: [U-Boot] [PATCH v4 1/3] net: Adds Fast Ethernet Controller driver for Armada100
- "Ajay Bhargav" wrote:
> - "Mike Frysinger" wrote:
>
> > On Tuesday, August 30, 2011 01:44:40 Ajay Bhargav wrote:
> > > +static void update_hash_table_mac_address(struct armdfec_device
> > *darmdfec,
> > > + u8 *oaddr, u8 *addr)
> > > +{
> > > + u32 mach;
> > > + u32 macl;
> > > +
> > > + /* Delete old entry */
> > > + if (oaddr) {
> > > + mach = (oaddr[0] << 8) | oaddr[1];
> > > + macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
> > > + (oaddr[4] << 8) | oaddr[5];
> > > + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
> > > + }
> > > +
> > > + /* Add new entry */
> > > + mach = (addr[0] << 8) | addr[1];
> > > + macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
> > addr[5];
> > > + add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
> > > +}
> > > ...
> > > +static int armdfec_init(struct eth_device *dev, bd_t *bd)
> > > +{
> > > ...
> > > + update_hash_table_mac_address(darmdfec, dev->enetaddr,
> > dev->enetaddr);
> >
> > i think something got lost along the way here :)
> >
> > you'll probably want to have oaddr[] be a static local in
> > update_hash_table_mac_address and use that to delete the old one
> when
> > it
> > differs from the new one, and then copy the new one into the static
> > local.
> > -mike
>
> You can have multiple entries in Hash table for different MAC
> addresses.
> The reason old entry is deleted because it may be possible that hash
> entry
> in the list is skipped but not invalidated so the same entry is made
> valid
> in the list after removing the old one and updating list with new
> entry.
> The calculated has for a particular MAC address is going to be same.
>
> Thanks,
> Ajay Bhargav
Adding to this.. In my case, its the first entry in hash table so I do not need
to delete it, I can simply pass NULL in place of oaddr. That change I will make
in the updated patch I am going to submit.
Thanks,
Ajay Bhargav
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[U-Boot] [PATCH v5 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
Changes for v3:
- code cleanup; removed unwated cast
Changes for v4:
- Not changed
Changes for v5:
- Coding style cleanup
board/Marvell/gplugd/gplugd.c | 33 +
include/configs/gplugd.h | 14 ++
2 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index 8560b3f..9b9e33a 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,4 +104,30 @@ int board_eth_init(bd_t *bis)
return armada100_fec_register(ARMD1_FEC_BASE);
}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index f3b94d8..b63ffd5 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -80,6 +80,20 @@
#define CONFIG_ROOTPATH"/tftpboot"
#define CONFIG_SYS_IMG_NAME"uImage"
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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[U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- armada100_fec_initialize changed to armada100_fec_register
Changes for v3:
- fec base address as argument to armada100_fec_register
Changes for v4:
- Not changed
Changes for v5:
- Coding style cleanup
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 38 +++
include/configs/gplugd.h| 19 +++-
4 files changed, 131 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 3d567eb..849638d 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_TIMER_BASE 0xD4014000
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C)
[U-Boot] [PATCH v5 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- removed random MAC generation
- driver init function changed to register as per new naming convention
- code cleanup (Thanks to Wolfgang, Marek & Mike for tips)
Changes for v3:
- code cleanup
Changes for v4:
- Debug and Error messages updated
- base_addr param for armada100_fec_register changed to unsigned long
Changes for v5:
- Coding style cleanup
- removed unwanted function
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 736 +++
drivers/net/armada100_fec.h | 232 +++
include/netdev.h|1 +
5 files changed, 971 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..3d567eb 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -59,6 +59,7 @@
#define ARMD1_MPMU_BASE0xD405
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
+#define ARMD1_FEC_BASE 0xC080
/*
* Main Power Management (MPMU) Registers
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..51fd3f7
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,736 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
+{
+ u32 timeout = PHY_WAIT_ITERATIONS;
+ u32 reg_val;
+
+ while (--timeout) {
+ reg_val = readl(reg);
+ if (cond && (reg_val & flag))
+ break;
+ else if (!cond && !(reg_val & flag))
+ break;
+ udelay(PHY_WAIT_MICRO_SECONDS);
+ }
+ return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+ val = readl(®s->phyadr);
+ *value = val & 0x1f;
+ return 0;
+ }
+
+
Re: [U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet support for GplugD
- "Marek Vasut" wrote: > On Friday, September 02, 2011 07:18:40 AM Ajay Bhargav wrote: > > This patch enables ethernet support for Marvell GplugD board. > Network > > related commands works. > > > > Signed-off-by: Ajay Bhargav > > --- > > Changes for v2: > > - armada100_fec_initialize changed to armada100_fec_register > > Changes for v3: > > - fec base address as argument to armada100_fec_register > > Changes for v4: > > - Not changed > > Changes for v5: > > - Coding style cleanup > > [...] > > +/* DHCP Support */ > > +#define CONFIG_CMD_DHCP > > +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY5 > > +#define CONFIG_BOOTP_SERVERIP > > Why is this empty? > oops!? missed? :/ Prafulla, can You remove this? > #define CONFIG_BOOTP_SERVERIP or should I email again? I donno how I missed this. > Other than that, > > Acked-by: Marek Vasut > > + > > +/* Default Boot Parameters */ > > +#define CONFIG_ROOTPATH"/tftpboot" > > +#define CONFIG_SYS_IMG_NAME"uImage" > > > > /* > > * mv-common.h should be defined after CMD configs since it used > them > Thanks, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet support for GplugD
- "Wolfgang Denk" wrote: > Dear Ajay Bhargav, > > In message > <1314940721-1867-2-git-send-email-ajay.bhar...@einfochips.com> you > wrote: > > This patch enables ethernet support for Marvell GplugD board. > Network > > related commands works. > ... > > > +#define CONFIG_BOOTP_SERVERIP > > Please remove this line. > > Best regards, > > Wolfgang Denk > > -- > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de > Roses are red > Violets are blue > Some poems rhyme > Dear Wolfgang, I asked Prafulla if he can remove that unwanted line. If it is not possible then I can resubmit the patch with that change. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet support for GplugD
- "Prafulla Wadaskar" wrote: > > -Original Message- > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > Sent: Friday, September 02, 2011 10:49 AM > > To: Prafulla Wadaskar > > Cc: u-boot@lists.denx.de; vap...@gentoo.org; marek.va...@gmail.com; > Ajay > > Bhargav > > Subject: [PATCH v5 2/3] Armada100: Enable Ethernet support for > GplugD > > [...] > > #define CONFIG_CMD_I2C > > #define CONFIG_CMD_AUTOSCRIPT > > #undef CONFIG_CMD_FPGA > > -#undef CONFIG_CMD_NET > > -#undef CONFIG_CMD_NFS > > + > > +/* Disable DCACHE */ > > +#define CONFIG_SYS_DCACHE_OFF > > + > > Put below definition encapsulated in #ifdef CONFIG_CMD_NET > > > +/* Network configuration */ > > +#define CONFIG_CMD_PING > > +#define CONFIG_NET_MULTI > > +#define CONFIG_ARMADA100_FEC > > + > > +/* DHCP Support */ > > +#define CONFIG_CMD_DHCP > > +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY5 > > +#define CONFIG_BOOTP_SERVERIP > > You should remove this also during this commit. There should not be > any hard coding for serverip and ipaddr > > > + > > +/* Default Boot Parameters */ > > +#define CONFIG_ROOTPATH"/tftpboot" > > +#define CONFIG_SYS_IMG_NAME"uImage" > > Similarly these are also not necessary, you may remove those too. > > Ack for rest of the code. > > Regards.. > Prafulla . . > Hi Prafulla, Thanks for reply, I will do the required changes and submit back.. Regards, Ajay Bhargav > > > > /* > > * mv-common.h should be defined after CMD configs since it used > them > > -- > > 1.7.0.4 > > ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet support for GplugD
- "Prafulla Wadaskar" wrote: > > -Original Message- > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > Sent: Thursday, September 08, 2011 10:09 AM > > To: Wolfgang Denk > > Cc: Prafulla Wadaskar; u-boot@lists.denx.de > > Subject: Re: [U-Boot] [PATCH v5 2/3] Armada100: Enable Ethernet > support > > for GplugD > > > > > > - "Wolfgang Denk" wrote: > > > > > Dear Ajay Bhargav, > > > > > > In message > > > <1314940721-1867-2-git-send-email-ajay.bhar...@einfochips.com> > you > > > wrote: > > > > This patch enables ethernet support for Marvell GplugD board. > > > Network > > > > related commands works. > > > ... > > > > > > > +#define CONFIG_BOOTP_SERVERIP > > > > > > Please remove this line. > > > > > > Best regards, > > > > > > Wolfgang Denk > > > > > > -- > > > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev > Zundel > > > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, > Germany > > > Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: > w...@denx.de > > > Roses are red > > > Violets are blue > > > Some poems rhyme > > > > > > > Dear Wolfgang, > > > > I asked Prafulla if he can remove that unwanted line. If it is not > > possible then I can resubmit the patch with that change. > > Hi Ajay, > Ideally you should do it :-) there are also two more suggestions. > Please do the needful, test it and post v6 patch series. > > Hi Wolfgang, > I would like to pull this patch series into u-boot-marvell.git for > Ben. I hope this will be okay with you. > > Regards.. > Prafulla . . > > Hi Prafulla, Sure I will do it. I am looking at your suggestions and will do the necessary changes. Thanks & Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 3/3] Armada100: Enable 88E3015 PHY support for GplugD
This patch adds support for 88E3015 PHY for Marvell GplugD board.
This patch depends on series of patch which adds support for Marvell
GuruPlug-Display.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
Changes for v3:
- code cleanup; removed unwated cast
Changes for v4:
- Not changed
Changes for v5:
- Coding style cleanup
Changes for v6:
- Not changed
board/Marvell/gplugd/gplugd.c | 33 +
include/configs/gplugd.h | 14 ++
2 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index 8560b3f..b4f7f81 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -32,6 +32,8 @@
#include
#include
#include
+#include
+#include
#ifdef CONFIG_ARMADA100_FEC
#include
@@ -83,6 +85,11 @@ int board_init(void)
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
+ /* Assert PHY_RST# */
+ gpio_direction_output(CONFIG_SYS_GPIO_PHY_RST, GPIO_LOW);
+ udelay(10);
+ /* Deassert PHY_RST# */
+ gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
return 0;
}
@@ -97,4 +104,30 @@ int board_eth_init(bd_t *bis)
return armada100_fec_register(ARMD1_FEC_BASE);
}
+
+#ifdef CONFIG_RESET_PHY_R
+/* Configure and initialize PHY chip 88E3015 */
+void reset_phy(void)
+{
+ u16 phy_adr;
+ const char *name = "armd-fec0";
+
+ if (miiphy_set_current_dev(name))
+ return;
+
+ /* command to read PHY dev address */
+ if (miiphy_read(name, 0xff, 0xff, &phy_adr)) {
+ printf("Err..%s could not read PHY dev address\n", __func__);
+ return;
+ }
+
+ /* Set Ethernet LED in TX blink mode */
+ miiphy_write(name, phy_adr, PHY_LED_MAN_REG, 0x00);
+ miiphy_write(name, phy_adr, PHY_LED_PAR_SEL_REG, PHY_LED_VAL);
+
+ /* reset the phy */
+ miiphy_reset(name, phy_adr);
+ debug("88E3015 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
#endif /* CONFIG_ARMADA100_FEC */
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 3ad2de5..5f72163 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -77,6 +77,20 @@
#define CONFIG_BOOTP_DHCP_REQUEST_DELAY5
#endif /* CONFIG_CMD_NET */
+/* GPIO Support */
+#define CONFIG_MARVELL_GPIO
+
+/* PHY configuration */
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_RESET_PHY_R
+/* 88E3015 register definition */
+#define PHY_LED_PAR_SEL_REG22
+#define PHY_LED_MAN_REG25
+#define PHY_LED_VAL0x5b/* LINK LED1, ACT LED2 */
+/* GPIO Configuration for PHY */
+#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6 2/3] Armada100: Enable Ethernet support for GplugD
This patch enables ethernet support for Marvell GplugD board. Network
related commands works.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- armada100_fec_initialize changed to armada100_fec_register
Changes for v3:
- fec base address as argument to armada100_fec_register
Changes for v4:
- Not changed
Changes for v5:
- Coding style cleanup
Changes for v6:
- Removed unwanted defines
arch/arm/include/asm/arch-armada100/armada100.h | 57 +++
arch/arm/include/asm/arch-armada100/mfp.h | 19
board/Marvell/gplugd/gplugd.c | 38 +++
include/configs/gplugd.h| 16 ++-
4 files changed, 128 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 9b9ed16..c449d4e 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -41,6 +41,10 @@
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x)(((x) & 0xf) << 4)
+/* Fast Ethernet Controller Clock register definition */
+#define FE_CLK_RST 0x1
+#define FE_CLK_ENA 0x8
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
@@ -85,6 +89,59 @@ struct armd1mpmu_registers {
};
/*
+ * Application Subsystem Power Management
+ * Refer Datasheet Appendix A.9
+ */
+struct armd1apmu_registers {
+ u32 pcr;/* 0x000 */
+ u32 ccr;/* 0x004 */
+ u32 pad1;
+ u32 ccsr; /* 0x00C */
+ u32 fc_timer; /* 0x010 */
+ u32 pad2;
+ u32 ideal_cfg; /* 0x018 */
+ u8 pad3[0x04C - 0x018 - 4];
+ u32 lcdcrc; /* 0x04C */
+ u32 cciccrc;/* 0x050 */
+ u32 sd1crc; /* 0x054 */
+ u32 sd2crc; /* 0x058 */
+ u32 usbcrc; /* 0x05C */
+ u32 nfccrc; /* 0x060 */
+ u32 dmacrc; /* 0x064 */
+ u32 pad4;
+ u32 buscrc; /* 0x06C */
+ u8 pad5[0x07C - 0x06C - 4];
+ u32 wake_clr; /* 0x07C */
+ u8 pad6[0x090 - 0x07C - 4];
+ u32 core_status;/* 0x090 */
+ u32 rfsc; /* 0x094 */
+ u32 imr;/* 0x098 */
+ u32 irwc; /* 0x09C */
+ u32 isr;/* 0x0A0 */
+ u8 pad7[0x0B0 - 0x0A0 - 4];
+ u32 mhst; /* 0x0B0 */
+ u32 msr;/* 0x0B4 */
+ u8 pad8[0x0C0 - 0x0B4 - 4];
+ u32 msst; /* 0x0C0 */
+ u32 pllss; /* 0x0C4 */
+ u32 smb;/* 0x0C8 */
+ u32 gccrc; /* 0x0CC */
+ u8 pad9[0x0D4 - 0x0CC - 4];
+ u32 smccrc; /* 0x0D4 */
+ u32 pad10;
+ u32 xdcrc; /* 0x0DC */
+ u32 sd3crc; /* 0x0E0 */
+ u32 sd4crc; /* 0x0E4 */
+ u8 pad11[0x0F0 - 0x0E4 - 4];
+ u32 cfcrc; /* 0x0F0 */
+ u32 mspcrc; /* 0x0F4 */
+ u32 cmucrc; /* 0x0F8 */
+ u32 fecrc; /* 0x0FC */
+ u32 pciecrc;/* 0x100 */
+ u32 epdcrc; /* 0x104 */
+};
+
+/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index d6e0494..da76b58 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -64,6 +64,25 @@
#define MFP105_CI2C_SDA(MFP_REG(0x1a4) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL(MFP_REG(0x1a8) | MFP_AF1 |
MFP_DRIVE_MEDIUM)
+/* Fast Ethernet */
+#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP087_ETH_TXEN(MFP_REG(0x15C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP095_ETH_RXER(MFP_REG(0x17C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM
[U-Boot] [PATCH v6 1/3] net: Adds Fast Ethernet Controller driver for Armada100
This patch adds support for Fast Ethernet Controller driver for
Armada100 series.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- removed random MAC generation
- driver init function changed to register as per new naming convention
- code cleanup (Thanks to Wolfgang, Marek & Mike for tips)
Changes for v3:
- code cleanup
Changes for v4:
- Debug and Error messages updated
- base_addr param for armada100_fec_register changed to unsigned long
Changes for v5:
- Coding style cleanup
- removed unwanted function
Changes for v6:
- Coding style cleanup (Thanks Prafulla for tips)
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/net/Makefile|1 +
drivers/net/armada100_fec.c | 736 +++
drivers/net/armada100_fec.h | 232 +++
include/netdev.h|1 +
5 files changed, 971 insertions(+), 0 deletions(-)
create mode 100644 drivers/net/armada100_fec.c
create mode 100644 drivers/net/armada100_fec.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a..9b9ed16 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -43,6 +43,7 @@
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
+#define ARMD1_FEC_BASE 0xC080
#define ARMD1_TIMER_BASE 0xD4014000
#define ARMD1_APBC1_BASE 0xD4015000
#define ARMD1_APBC2_BASE 0xD4015800
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197..34b4322 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libnet.o
COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 000..b526bcb
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,736 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ * Contributor: Mahavir Jain
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "armada100_fec.h"
+
+#define PHY_ADR_REQ 0xFF /* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ unsigned int i = 0;
+
+ printf("\noffset: phy_adr, value: 0x%x\n", readl(®s->phyadr));
+ printf("offset: smi, value: 0x%x\n", readl(®s->smi));
+ for (i = 0x400; i <= 0x4e4; i += 4)
+ printf("offset: 0x%x, value: 0x%x\n",
+ i, readl(ARMD1_FEC_BASE + i));
+ return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
+{
+ u32 timeout = PHY_WAIT_ITERATIONS;
+ u32 reg_val;
+
+ while (--timeout) {
+ reg_val = readl(reg);
+ if (cond && (reg_val & flag))
+ break;
+ else if (!cond && !(reg_val & flag))
+ break;
+ udelay(PHY_WAIT_MICRO_SECONDS);
+ }
+ return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+ u16 *value)
+{
+ struct eth_device *dev = eth_get_dev_by_name(devname);
+ struct armdfec_device *darmdfec = to_darmdfec(dev);
+ struct armdfec_reg *regs = darmdfec->regs;
+ u32 val;
+
+ if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+
Re: [U-Boot] [PATCH v6 3/3] Armada100: Enable 88E3015 PHY support for GplugD
- "Marek Vasut" wrote: > On Tuesday, September 13, 2011 02:54:15 PM Prafulla Wadaskar wrote: > > > -Original Message- > > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > > Sent: Thursday, September 08, 2011 4:13 PM > > > To: Prafulla Wadaskar > > > Cc: u-boot@lists.denx.de; vap...@gentoo.org; > marek.va...@gmail.com; Ajay > > > Bhargav > > > Subject: [PATCH v6 3/3] Armada100: Enable 88E3015 PHY support for > GplugD > > > > > > This patch adds support for 88E3015 PHY for Marvell GplugD board. > > > This patch depends on series of patch which adds support for > Marvell > > > GuruPlug-Display. > > > > > > Signed-off-by: Ajay Bhargav > > > --- > > > > > > Changes for v2: > > > - Not changed > > > > > > Changes for v3: > > > - code cleanup; removed unwated cast > > > > > > Changes for v4: > > > - Not changed > > > > > > Changes for v5: > > > - Coding style cleanup > > > > > > Changes for v6: > > > - Not changed > > > > Applied to u-boot-marvell.git next branch > > I have a good feeling about these drivers, cheers! > Thanks for your support Marek :) Regards, Ajay Bhargav > > > > Regards.. > > Prafulla . . ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] Armada100: Add SPI flash support for Marvell gplugD
This patch enables Atmel AT45 SPI flash support for Marvell gplugD Enables SF commands. Signed-off-by: Ajay Bhargav --- include/configs/gplugd.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 527a0c8..260a1dc 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -96,6 +96,10 @@ #define CONFIG_ENV_SPI_CS 110 #define CONFIG_SYS_SSP_PORT2 +/* Flash Support */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_ATMEL + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/4] SPI: Add SPI driver support for Marvell Armada100
This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/spi.h | 111
drivers/spi/Makefile |1 +
drivers/spi/armada100_spi.c | 205 +
3 files changed, 317 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/spi.h
create mode 100644 drivers/spi/armada100_spi.c
diff --git a/arch/arm/include/asm/arch-armada100/spi.h
b/arch/arm/include/asm/arch-armada100/spi.h
new file mode 100644
index 000..85c2ccf
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/spi.h
@@ -0,0 +1,111 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_SPI_H_
+#define __ARMADA100_SPI_H_
+
+#include
+
+#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
+#define SSP_REG_BASE(x)CAT_BASE_ADDR(x)
+
+/*
+ * SSP Serial Port Registers
+ * refer Appendix A.26
+ */
+struct ssp_reg {
+ u32 sscr0; /* SSP Control Register 0 - 0x000 */
+ u32 sscr1; /* SSP Control Register 1 - 0x004 */
+ u32 sssr; /* SSP Status Register - 0x008 */
+ u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
+ u32 ssdr; /* SSP Data Register - 0x010 */
+ u32 pad1[5];
+ u32 ssto; /* SSP Timeout Register - 0x028 */
+ u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
+ u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
+ u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
+ u32 sstss; /* SSP Timeslot Status Register - 0x038 */
+};
+
+struct armd_spi_slave {
+ struct spi_slave slave;
+ struct ssp_reg *spi_reg;
+ u32 cr0, cr1;
+ u32 int_cr1;
+ u32 clear_sr;
+ const void *tx;
+ void *rx;
+ int gpio_cs_inverted;
+
+ void (*write)(struct armd_spi_slave *pss);
+ void (*read)(struct armd_spi_slave *pss);
+};
+
+#define to_armd_spi_slave(s) container_of(s, struct armd_spi_slave, slave)
+
+#define DEFAULT_WORD_LEN 8
+#define SSP_FLUSH_NUM 0x2000
+#define RX_THRESH_DEF 8
+#define TX_THRESH_DEF 8
+#define TIMEOUT_DEF1000
+
+#define SSCR1_RIE (1 << 0)/* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE (1 << 1)/* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM (1 << 2)/* Loop-Back Mode */
+#define SSCR1_SPO (1 << 3)/* Motorola SPI SSPSCLK polarity
+ setting */
+#define SSCR1_SPH (1 << 4)/* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS (1 << 5)/* Microwire Transmit Data Size */
+#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
+#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
+
+#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
+#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
+#define SSCR1_TINTE(1 << 19) /* Receiver Time-out
+ Interrupt enable */
+
+#define SSCR0_DSS 0x0f/* Data Size Select (mask) */
+#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
+#define SSCR0_FRF 0x30/* FRame Format (mask) */
+#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
+ Peripheral Interface */
+#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
+ Serial Protocol (SSP) */
+#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
+#define SSCR0_ECS (1 << 6)/* External clock select */
+#define SSCR0_SSE (1 << 7)/* Synchronous Serial Port
+
[U-Boot] [PATCH 4/4] Armada100: Add env storage support for Marvell gplugD
This patch adds support for envrionment varaible storage in SPI flash for Marvell gplugD. Signed-off-by: Ajay Bhargav --- include/configs/gplugd.h | 10 -- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 260a1dc..8905df8 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -116,7 +116,13 @@ /* * Environment variables configurations */ -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#define CONFIG_ENV_SIZE0x2 /* 64k */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE 0x4000 +#define CONFIG_ENV_SIZE0x4000 +#define CONFIG_ENV_OFFSET 0x07C000 + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV #endif /* __CONFIG_GPLUGD_H */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/4] Armada100: Add SPI support for Marvell gplugD
This patch add SPI driver support for Marvell gplugD.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h | 19 +++
arch/arm/include/asm/arch-armada100/mfp.h |6 ++
board/Marvell/gplugd/gplugd.c | 12
include/configs/gplugd.h|5 +
4 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index c449d4e..a8181b6 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -45,6 +45,10 @@
#define FE_CLK_RST 0x1
#define FE_CLK_ENA 0x8
+/* SSP2 Clock Control */
+#define SSP2_APBCLK0x01
+#define SSP2_FNCLK 0x02
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
@@ -175,5 +179,20 @@ struct armd1apb1_registers {
u32 ac97; /*0x084*/
};
+/*
+* APB2 Clock Reset/Control Registers
+* Refer Datasheet Appendix A.11
+*/
+struct armd1apb2_registers {
+ u32 pad1[0x01C - 0x000];
+ u32 ssp1_clkrst;/* 0x01C */
+ u32 ssp2_clkrst;/* 0x020 */
+ u32 pad2[0x04C - 0x020 - 4];
+ u32 ssp3_clkrst;/* 0x04C */
+ u32 pad3[0x058 - 0x04C - 4];
+ u32 ssp4_clkrst;/* 0x058 */
+ u32 ssp5_clkrst;/* 0x05C */
+};
+
#endif /* CONFIG_ARMADA100 */
#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index da76b58..d48251a 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -83,6 +83,12 @@
#define MFP101_ETH_MDIO(MFP_REG(0x194) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
#define MFP103_ETH_RXDV(MFP_REG(0x19C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+/* SPI */
+#define MFP107_SSP2_RXD(MFP_REG(0x1AC) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+#define MFP108_SSP2_TXD(MFP_REG(0x1B0) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP111_SSP2_CLK(MFP_REG(0x1BC) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+
/* More macros can be defined here... */
#define MFP_PIN_MAX117
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index b4f7f81..42c8389 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -72,6 +72,12 @@ int board_early_init_f(void)
MFP101_ETH_MDIO,
MFP103_ETH_RXDV,
+ /* SSP2 */
+ MFP107_SSP2_RXD,
+ MFP108_SSP2_TXD,
+ MFP110_SSP2_CS,
+ MFP111_SSP2_CLK,
+
MFP_EOC /*End of configuration*/
};
/* configure MFP's */
@@ -81,6 +87,9 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct armd1apb2_registers *apb2_regs =
+ (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
/* arch number of Board */
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
@@ -90,6 +99,9 @@ int board_init(void)
udelay(10);
/* Deassert PHY_RST# */
gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+ /* Enable SSP2 clock */
+ writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
return 0;
}
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 5f72163..527a0c8 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -91,6 +91,11 @@
/* GPIO Configuration for PHY */
#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+/* SPI Support */
+#define CONFIG_ARMADA100_SPI
+#define CONFIG_ENV_SPI_CS 110
+#define CONFIG_SYS_SSP_PORT2
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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Re: [U-Boot] [PATCH 1/4] SPI: Add SPI driver support for Marvell Armada100
- "Marek Vasut" wrote:
> On Monday, September 19, 2011 12:47:07 PM Ajay Bhargav wrote:
> > This patch provides support for SPI emulated over SSP for Marvell
> > Armada100 SOC.
> >
> > Signed-off-by: Ajay Bhargav
> > ---
> > arch/arm/include/asm/arch-armada100/spi.h | 111
> > drivers/spi/Makefile |1 +
> > drivers/spi/armada100_spi.c | 205
> > + 3 files changed, 317 insertions(+), 0
> > deletions(-)
> > create mode 100644 arch/arm/include/asm/arch-armada100/spi.h
> > create mode 100644 drivers/spi/armada100_spi.c
> >
>
> [...]
>
> > +
> > +#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
> > +#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
>
> ((x) - 1), missing parenthesis, please fix globally.
>
> > +#define SSCR1_TINTE(1 << 19) /* Receiver Time-out
> > + Interrupt enable */
> > +
> > +#define SSCR0_DSS 0x0f/* Data Size Select (mask) */
> > +#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
> > +#define SSCR0_FRF 0x30/* FRame Format (mask) */
> > +#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
> > + Peripheral Interface */
> > +#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
> > + Serial Protocol (SSP) */
> > +#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
> > +#define SSCR0_ECS (1 << 6)/* External clock select */
> > +#define SSCR0_SSE (1 << 7)/* Synchronous Serial Port
> > + Enable */
> > +
> > +#define SSSR_TNF (1 << 2)/* Transmit FIFO Not Full */
> > +#define SSSR_RNE (1 << 3)/* Receive FIFO Not Empty */
> > +#define SSSR_BSY (1 << 4)/* SSP Busy */
> > +#define SSSR_TFS (1 << 5)/* Transmit FIFO Service Request */
> > +#define SSSR_RFS (1 << 6)/* Receive FIFO Service Request */
> > +#define SSSR_ROR (1 << 7)/* Receive FIFO Overrun */
> > +#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
>
> [...]
>
> > +
> > +static void null_writer(struct armd_spi_slave *pss)
> > +{
> > + while (!(readl(&pss->spi_reg->sssr) & SSSR_TNF))
> > + ;
>
> Please avoid endless loops, please fix globally.
>
>
> Cheers
>
Hi Marek,
I will fix that :) any more comments?
Regards,
Ajay Bhargav
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[U-Boot] [PATCH v2 2/4] Armada100: Add SPI support for Marvell gplugD
This patch add SPI driver support for Marvell gplugD.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Not changed
arch/arm/include/asm/arch-armada100/armada100.h | 19 +++
arch/arm/include/asm/arch-armada100/mfp.h |6 ++
board/Marvell/gplugd/gplugd.c | 12
include/configs/gplugd.h|5 +
4 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index c449d4e..a8181b6 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -45,6 +45,10 @@
#define FE_CLK_RST 0x1
#define FE_CLK_ENA 0x8
+/* SSP2 Clock Control */
+#define SSP2_APBCLK0x01
+#define SSP2_FNCLK 0x02
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
@@ -175,5 +179,20 @@ struct armd1apb1_registers {
u32 ac97; /*0x084*/
};
+/*
+* APB2 Clock Reset/Control Registers
+* Refer Datasheet Appendix A.11
+*/
+struct armd1apb2_registers {
+ u32 pad1[0x01C - 0x000];
+ u32 ssp1_clkrst;/* 0x01C */
+ u32 ssp2_clkrst;/* 0x020 */
+ u32 pad2[0x04C - 0x020 - 4];
+ u32 ssp3_clkrst;/* 0x04C */
+ u32 pad3[0x058 - 0x04C - 4];
+ u32 ssp4_clkrst;/* 0x058 */
+ u32 ssp5_clkrst;/* 0x05C */
+};
+
#endif /* CONFIG_ARMADA100 */
#endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/mfp.h
b/arch/arm/include/asm/arch-armada100/mfp.h
index da76b58..d48251a 100644
--- a/arch/arm/include/asm/arch-armada100/mfp.h
+++ b/arch/arm/include/asm/arch-armada100/mfp.h
@@ -83,6 +83,12 @@
#define MFP101_ETH_MDIO(MFP_REG(0x194) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
#define MFP103_ETH_RXDV(MFP_REG(0x19C) | MFP_AF5 |
MFP_DRIVE_MEDIUM)
+/* SPI */
+#define MFP107_SSP2_RXD(MFP_REG(0x1AC) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+#define MFP108_SSP2_TXD(MFP_REG(0x1B0) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP111_SSP2_CLK(MFP_REG(0x1BC) | MFP_AF4 |
MFP_DRIVE_MEDIUM)
+
/* More macros can be defined here... */
#define MFP_PIN_MAX117
diff --git a/board/Marvell/gplugd/gplugd.c b/board/Marvell/gplugd/gplugd.c
index b4f7f81..42c8389 100644
--- a/board/Marvell/gplugd/gplugd.c
+++ b/board/Marvell/gplugd/gplugd.c
@@ -72,6 +72,12 @@ int board_early_init_f(void)
MFP101_ETH_MDIO,
MFP103_ETH_RXDV,
+ /* SSP2 */
+ MFP107_SSP2_RXD,
+ MFP108_SSP2_TXD,
+ MFP110_SSP2_CS,
+ MFP111_SSP2_CLK,
+
MFP_EOC /*End of configuration*/
};
/* configure MFP's */
@@ -81,6 +87,9 @@ int board_early_init_f(void)
int board_init(void)
{
+ struct armd1apb2_registers *apb2_regs =
+ (struct armd1apb2_registers *)ARMD1_APBC2_BASE;
+
/* arch number of Board */
gd->bd->bi_arch_number = MACH_TYPE_SHEEVAD;
/* adress of boot parameters */
@@ -90,6 +99,9 @@ int board_init(void)
udelay(10);
/* Deassert PHY_RST# */
gpio_set_value(CONFIG_SYS_GPIO_PHY_RST, GPIO_HIGH);
+
+ /* Enable SSP2 clock */
+ writel(SSP2_APBCLK | SSP2_FNCLK, &apb2_regs->ssp2_clkrst);
return 0;
}
diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h
index 5f72163..527a0c8 100644
--- a/include/configs/gplugd.h
+++ b/include/configs/gplugd.h
@@ -91,6 +91,11 @@
/* GPIO Configuration for PHY */
#define CONFIG_SYS_GPIO_PHY_RST104 /* GPIO104 */
+/* SPI Support */
+#define CONFIG_ARMADA100_SPI
+#define CONFIG_ENV_SPI_CS 110
+#define CONFIG_SYS_SSP_PORT2
+
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
--
1.7.0.4
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[U-Boot] [PATCH v2 3/4] Armada100: Add SPI flash support for Marvell gplugD
This patch enables Atmel AT45 SPI flash support for Marvell gplugD Enables SF commands. Signed-off-by: Ajay Bhargav --- Changes for v2: - Not changed include/configs/gplugd.h |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 527a0c8..260a1dc 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -96,6 +96,10 @@ #define CONFIG_ENV_SPI_CS 110 #define CONFIG_SYS_SSP_PORT2 +/* Flash Support */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH_ATMEL + /* * mv-common.h should be defined after CMD configs since it used them * to enable certain macros -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] Armada100: Add env storage support for Marvell gplugD
This patch adds support for envrionment varaible storage in SPI flash for Marvell gplugD. Signed-off-by: Ajay Bhargav --- Changes for v2: - Not changed include/configs/gplugd.h | 10 -- 1 files changed, 8 insertions(+), 2 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 260a1dc..8905df8 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -116,7 +116,13 @@ /* * Environment variables configurations */ -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#define CONFIG_ENV_SIZE0x2 /* 64k */ +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SECT_SIZE 0x4000 +#define CONFIG_ENV_SIZE0x4000 +#define CONFIG_ENV_OFFSET 0x07C000 + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_EDITENV +#define CONFIG_CMD_SAVEENV #endif /* __CONFIG_GPLUGD_H */ -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/4] SPI: Add SPI driver support for Marvell Armada100
This patch provides support for SPI emulated over SSP for Marvell
Armada100 SOC.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Code cleanup
arch/arm/include/asm/arch-armada100/spi.h | 95
drivers/spi/Makefile |1 +
drivers/spi/armada100_spi.c | 228 +
3 files changed, 324 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/spi.h
create mode 100644 drivers/spi/armada100_spi.c
diff --git a/arch/arm/include/asm/arch-armada100/spi.h
b/arch/arm/include/asm/arch-armada100/spi.h
new file mode 100644
index 000..58f0d8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/spi.h
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_SPI_H_
+#define __ARMADA100_SPI_H_
+
+#include
+
+#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
+#define SSP_REG_BASE(x)CAT_BASE_ADDR(x)
+
+/*
+ * SSP Serial Port Registers
+ * refer Appendix A.26
+ */
+struct ssp_reg {
+ u32 sscr0; /* SSP Control Register 0 - 0x000 */
+ u32 sscr1; /* SSP Control Register 1 - 0x004 */
+ u32 sssr; /* SSP Status Register - 0x008 */
+ u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
+ u32 ssdr; /* SSP Data Register - 0x010 */
+ u32 pad1[5];
+ u32 ssto; /* SSP Timeout Register - 0x028 */
+ u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
+ u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
+ u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
+ u32 sstss; /* SSP Timeslot Status Register - 0x038 */
+};
+
+#define DEFAULT_WORD_LEN 8
+#define SSP_FLUSH_NUM 0x2000
+#define RX_THRESH_DEF 8
+#define TX_THRESH_DEF 8
+#define TIMEOUT_DEF1000
+
+#define SSCR1_RIE (1 << 0)/* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE (1 << 1)/* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM (1 << 2)/* Loop-Back Mode */
+#define SSCR1_SPO (1 << 3)/* Motorola SPI SSPSCLK polarity
+ setting */
+#define SSCR1_SPH (1 << 4)/* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS (1 << 5)/* Microwire Transmit Data Size */
+#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
+#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
+
+#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
+#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
+#define SSCR1_TINTE(1 << 19) /* Receiver Time-out
+ Interrupt enable */
+
+#define SSCR0_DSS 0x0f/* Data Size Select (mask) */
+#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
+#define SSCR0_FRF 0x30/* FRame Format (mask) */
+#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
+ Peripheral Interface */
+#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
+ Serial Protocol (SSP) */
+#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
+#define SSCR0_ECS (1 << 6)/* External clock select */
+#define SSCR0_SSE (1 << 7)/* Synchronous Serial Port
+ Enable */
+
+#define SSSR_TNF (1 << 2)/* Transmit FIFO Not Full */
+#define SSSR_RNE (1 << 3)/* Receive FIFO Not Empty */
+#define SSSR_BSY (1 << 4)/* SSP Busy */
+#define SSSR_TFS (1 << 5)/* Transmit FIFO Service Request */
+#define SSSR_RFS (1 << 6)/* Receive
Re: [U-Boot] [BREAKAGE] gplugd board / armada100_fec
- "Marek Vasut" wrote: > Dear Ajay Bhargav, > > I compiled the "gplugd" board and I got the following warnings, please > fix. > > Configuring for gplugd board... > armada100_fec.c: In function 'armdfec_init': > armada100_fec.c:483:2: warning: dereferencing type-punned pointer will > break > strict-aliasing rules > armada100_fec.c:484:2: warning: dereferencing type-punned pointer will > break > strict-aliasing rules > armada100_fec.c: In function 'armdfec_recv': > armada100_fec.c:670:2: warning: dereferencing type-punned pointer will > break > strict-aliasing rules > gplugd.c: In function 'board_init': > gplugd.c:95:27: error: 'MACH_TYPE_SHEEVAD' undeclared (first use in > this > function) > gplugd.c:95:27: note: each undeclared identifier is reported only once > for each > function it appears in > > Cheers Hi Marek, May I know what version of gcc are you using? I will fix the MACH_TYPE_SHEEVAD as suggested by Albert. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] gplugD: Fix for error:MACH_TYPE_SHEEVAD undeclared
This patch fix the build failure (error: 'MACH_TYPE_SHEEVAD' undeclared (first use in this function)) for gplugD due to recent sync of mach-types.h with its linux original. Signed-off-by: Ajay Bhargav --- include/configs/gplugd.h | 12 +++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 24bf767..9813309 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -32,6 +32,16 @@ #define __CONFIG_GPLUGD_H /* + * FIXME: fix for error caused due to recent update to mach-types.h + */ +#include +#ifdef MACH_TYPE_SHEEVAD +#error "MACH_TYPE_SHEEVAD has been defined properly, please remove this." +#else +#define MACH_TYPE_SHEEVAD 2625 +#endif + +/* * Version number information */ #define CONFIG_IDENT_STRING"\nMarvell-gplugD" @@ -42,7 +52,7 @@ #define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ #define CONFIG_ARMADA100 1 /* SOC Family Name */ #define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_MACH_SHEEVAD/* Machine type */ +#define CONFIG_MACH_TYPE MACH_TYPE_SHEEVAD /* Machine type */ #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ #defineCONFIG_SYS_TEXT_BASE0x00f0 -- 1.7.0.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] net: Armada100: Fix compilation warnings
This patch fix compilation warnings for Armada100 FEC driver
Ref:
warning: dereferencing type-punned pointer will break
strict-aliasing rules
Signed-off-by: Ajay Bhargav
---
drivers/net/armada100_fec.c | 14 ++
1 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
index fbf9763..1a54362 100644
--- a/drivers/net/armada100_fec.c
+++ b/drivers/net/armada100_fec.c
@@ -440,6 +440,7 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd)
struct armdfec_device *darmdfec = to_darmdfec(dev);
struct armdfec_reg *regs = darmdfec->regs;
int phy_adr;
+ u32 temp;
armdfec_init_rx_desc_ring(darmdfec);
@@ -479,9 +480,12 @@ static int armdfec_init(struct eth_device *dev, bd_t *bd)
update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
/* Update TX and RX queue descriptor register */
- writel((u32)darmdfec->p_txdesc, ®s->txcdp[TXQ]);
- writel((u32)darmdfec->p_rxdesc, ®s->rxfdp[RXQ]);
- writel((u32)darmdfec->p_rxdesc_curr, ®s->rxcdp[RXQ]);
+ temp = (u32)®s->txcdp[TXQ];
+ writel((u32)darmdfec->p_txdesc, temp);
+ temp = (u32)®s->rxfdp[RXQ];
+ writel((u32)darmdfec->p_rxdesc, temp);
+ temp = (u32)®s->rxcdp[RXQ];
+ writel((u32)darmdfec->p_rxdesc_curr, temp);
/* Enable Interrupts */
writel(ALL_INTS, ®s->im);
@@ -614,6 +618,7 @@ static int armdfec_recv(struct eth_device *dev)
struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
u32 cmd_sts;
u32 timeout = 0;
+ u32 temp;
/* wait untill rx packet available or timeout */
do {
@@ -667,7 +672,8 @@ static int armdfec_recv(struct eth_device *dev)
p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
p_rxdesc_curr->byte_cnt = 0;
- writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr);
+ temp = (u32)&darmdfec->p_rxdesc_curr;
+ writel((u32)p_rxdesc_curr->nxtdesc_p, temp);
return 0;
}
--
1.7.0.4
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Re: [U-Boot] [BREAKAGE] gplugd board / armada100_fec
- "Marek Vasut" wrote: > > - "Marek Vasut" wrote: > > > Dear Ajay Bhargav, > > > > > > I compiled the "gplugd" board and I got the following warnings, > please > > > fix. > > > > > > Configuring for gplugd board... > > > armada100_fec.c: In function 'armdfec_init': > > > armada100_fec.c:483:2: warning: dereferencing type-punned pointer > will > > > break > > > strict-aliasing rules > > > armada100_fec.c:484:2: warning: dereferencing type-punned pointer > will > > > break > > > strict-aliasing rules > > > armada100_fec.c: In function 'armdfec_recv': > > > armada100_fec.c:670:2: warning: dereferencing type-punned pointer > will > > > break > > > strict-aliasing rules > > > gplugd.c: In function 'board_init': > > > gplugd.c:95:27: error: 'MACH_TYPE_SHEEVAD' undeclared (first use > in > > > this > > > function) > > > gplugd.c:95:27: note: each undeclared identifier is reported only > once > > > for each > > > function it appears in > > > > > > Cheers > > > > Hi Marek, > > > > May I know what version of gcc are you using? > > ELDK4.2 and ELDK5.0 > > so gcc4.2 and 4.6, but I include you a testcase (edit path to > armada100_fec.h). > > gcc -m32 -Wall -fstrict-aliasing -o test2 test2.c ; ./test2 > > > > > I will fix the MACH_TYPE_SHEEVAD as suggested by Albert. > > > > Regards, > > Ajay Bhargav > Can you please check the patch I have just sent? I have cc it to you too. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] mmc: mv_sdhci: Fix host version read for Armada100
sdhci_readw does not work for host version read in Armada100 series
SoCs. This patch fix this issue by making a sdhci_readl call to get host
version.
Signed-off-by: Ajay Bhargav
---
drivers/mmc/mv_sdhci.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index f92caeb..c7fd287 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -30,6 +30,7 @@ static inline void mv_sdhci_writeb(struct sdhci_host *host,
u8 val, int reg)
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
static char *MVSDH_NAME = "mv_sdh";
+
int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
{
struct sdhci_host *host = NULL;
@@ -48,7 +49,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32
quirks)
mv_ops.write_b = mv_sdhci_writeb;
host->ops = &mv_ops;
#endif
+#ifdef CONFIG_ARMADA100
+ /* SDHCI host version read workaround for Armada100 series */
+ host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
+#else
host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
+#endif
add_sdhci(host, max_clk, min_clk);
return 0;
}
--
1.7.0.4
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Re: [U-Boot] [PATCH] mmc: mv_sdhci: Fix host version read for Armada100
- "Marek Vasut" wrote:
> > sdhci_readw does not work for host version read in Armada100 series
> > SoCs. This patch fix this issue by making a sdhci_readl call to get
> host
> > version.
> >
> > Signed-off-by: Ajay Bhargav
> > ---
> > drivers/mmc/mv_sdhci.c |6 ++
> > 1 files changed, 6 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
> > index f92caeb..c7fd287 100644
> > --- a/drivers/mmc/mv_sdhci.c
> > +++ b/drivers/mmc/mv_sdhci.c
> > @@ -30,6 +30,7 @@ static inline void mv_sdhci_writeb(struct
> sdhci_host
> > *host, u8 val, int reg) #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
> >
> > static char *MVSDH_NAME = "mv_sdh";
> > +
> > int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
> > {
> > struct sdhci_host *host = NULL;
> > @@ -48,7 +49,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32
> min_clk,
> > u32 quirks) mv_ops.write_b = mv_sdhci_writeb;
> > host->ops = &mv_ops;
> > #endif
> > +#ifdef CONFIG_ARMADA100
> > + /* SDHCI host version read workaround for Armada100 series */
> > + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
> > +#else
> > host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
> > +#endif
> > add_sdhci(host, max_clk, min_clk);
> > return 0;
> > }
>
> Basically armada100 can't do 16bit access to that register. Ok, but
> why does it
> work for other registers? Also, can you make this a config option like
>
> CONFIG_SDHCI_REG32_QUIRK (invent some better name ;-) ).
>
> Cheers
>
Hi Marek,
Armada100 SOC has this bug for particularly that register. This is particularly
for that register so Do you think a config is required for this?
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH] mmc: mv_sdhci: Fix host version read for Armada100
- "Lei Wen" wrote:
> Hi Ajay,
>
> On Tue, Nov 1, 2011 at 5:39 PM, Ajay Bhargav
> wrote:
> > sdhci_readw does not work for host version read in Armada100 series
> > SoCs. This patch fix this issue by making a sdhci_readl call to get
> host
> > version.
> >
> > Signed-off-by: Ajay Bhargav
> > ---
> > drivers/mmc/mv_sdhci.c | 6 ++
> > 1 files changed, 6 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
> > index f92caeb..c7fd287 100644
> > --- a/drivers/mmc/mv_sdhci.c
> > +++ b/drivers/mmc/mv_sdhci.c
> > @@ -30,6 +30,7 @@ static inline void mv_sdhci_writeb(struct
> sdhci_host *host, u8 val, int reg)
> > #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
> >
> > static char *MVSDH_NAME = "mv_sdh";
> > +
> > int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
> > {
> > struct sdhci_host *host = NULL;
> > @@ -48,7 +49,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32
> min_clk, u32 quirks)
> > mv_ops.write_b = mv_sdhci_writeb;
> > host->ops = &mv_ops;
> > #endif
> > +#ifdef CONFIG_ARMADA100
>
> You should following my previous fixing sample to add the workaround:
> http://patchwork.ozlabs.org/patch/117575/
>
Patches acked? I didn't know it. Or I should wait for your patches to get
mainlined first.
> Just keep in mind that, it is generic driver and don't put private
> fixing there. :)
>
> Thanks,
> Lei
>
Any good way to put that fix? Or else I can simply follow Marek's solution to
add a quirk for this instead of defining it for a CPU. What you say?
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH] mmc: mv_sdhci: Fix host version read for Armada100
- "Marek Vasut" wrote:
> > - "Marek Vasut" wrote:
> > > > sdhci_readw does not work for host version read in Armada100
> series
> > > > SoCs. This patch fix this issue by making a sdhci_readl call to
> get
> > >
> > > host
> > >
> > > > version.
> > > >
> > > > Signed-off-by: Ajay Bhargav
> > > > ---
> > > >
> > > > drivers/mmc/mv_sdhci.c |6 ++
> > > > 1 files changed, 6 insertions(+), 0 deletions(-)
> > > >
> > > > diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
> > > > index f92caeb..c7fd287 100644
> > > > --- a/drivers/mmc/mv_sdhci.c
> > > > +++ b/drivers/mmc/mv_sdhci.c
> > > > @@ -30,6 +30,7 @@ static inline void mv_sdhci_writeb(struct
> > >
> > > sdhci_host
> > >
> > > > *host, u8 val, int reg) #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS
> */
> > > >
> > > > static char *MVSDH_NAME = "mv_sdh";
> > > >
> > > > +
> > > >
> > > > int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32
> quirks)
> > > > {
> > > >
> > > > struct sdhci_host *host = NULL;
> > > >
> > > > @@ -48,7 +49,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk,
> u32
> > >
> > > min_clk,
> > >
> > > > u32 quirks) mv_ops.write_b = mv_sdhci_writeb;
> > > >
> > > > host->ops = &mv_ops;
> > > >
> > > > #endif
> > > >
> > > > +#ifdef CONFIG_ARMADA100
> > > > + /* SDHCI host version read workaround for Armada100 series */
> > > > + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >>
> 16;
> > > > +#else
> > > >
> > > > host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
> > > >
> > > > +#endif
> > > >
> > > > add_sdhci(host, max_clk, min_clk);
> > > > return 0;
> > > >
> > > > }
> > >
> > > Basically armada100 can't do 16bit access to that register. Ok,
> but
> > > why does it
> > > work for other registers? Also, can you make this a config option
> like
> > >
> > > CONFIG_SDHCI_REG32_QUIRK (invent some better name ;-) ).
> > >
> > > Cheers
> >
> > Hi Marek,
> >
> > Armada100 SOC has this bug for particularly that register. This is
> > particularly for that register so Do you think a config is required
> for
> > this?
>
> Well such crippled hardware might appear somewhere else too, so yes.
> But still,
> it's surprising it's only one register, really. Can you point me to a
>
> datasheet/errata stating it?
>
> Thanks!
>
I agree, adding a quirk for this is best option this way driver will still be
generic for marvell series.
Marek, I am really sorry but I am not allowed to share errata here :) I will
ask my senior if i can atleast send you a screenshot regarding this issue.
Regards,
Ajay Bhargav
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[U-Boot] [Patch V2] mmc: mv_sdhci: Fix host version read for Armada100
sdhci_readw does not work for host version read in Armada100 series SoCs. This patch fix this issue by making a sdhci_readl call to get host version. Signed-off-by: Ajay Bhargav --- Changes for v2: - Added quirk instead of #define (suggested by Marek) drivers/mmc/mv_sdhci.c |5 - include/sdhci.h|1 + 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index f92caeb..c9b7079 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -48,7 +48,10 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks) mv_ops.write_b = mv_sdhci_writeb; host->ops = &mv_ops; #endif - host->version = sdhci_readw(host, SDHCI_HOST_VERSION); + if (quirks & SDHCI_QUIRK_REG32_RW) + host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16; + else + host->version = sdhci_readw(host, SDHCI_HOST_VERSION); add_sdhci(host, max_clk, min_clk); return 0; } diff --git a/include/sdhci.h b/include/sdhci.h index 0690938..800f9d9 100644 --- a/include/sdhci.h +++ b/include/sdhci.h @@ -215,6 +215,7 @@ * quirks */ #define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0) +#define SDHCI_QUIRK_REG32_RW (1 << 1) /* to make gcc happy */ struct sdhci_host; -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] Armada100: gplugD: Add USB command support
This patch adds support for USB commands and USB storage device for Marvell gplugD Signed-off-by: Ajay Bhargav --- include/configs/gplugd.h | 17 + 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 9813309..f8dc74f 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -134,4 +134,21 @@ #define CONFIG_CMD_EDITENV #define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_USB + +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ARMADA100 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE + +#ifndef CONFIG_DOS_PARTITION +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_DOS_PARTITION */ + +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT +#define CONFIG_CMD_EXT2 +#endif /* CONFIG_CMD_USB */ + #endif /* __CONFIG_GPLUGD_H */ -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] USB: Armada100: Add UTMI PHY interface driver
This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h |7 ++
drivers/usb/host/utmi-armada100.c | 87 +++
drivers/usb/host/utmi-armada100.h | 79
3 files changed, 173 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/utmi-armada100.c
create mode 100644 drivers/usb/host/utmi-armada100.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 0ed3a8e..d6984dc 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -43,6 +43,13 @@
#define SSP2_APBCLK0x01
#define SSP2_FNCLK 0x02
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN 0x10
+#define USB_SPH_AXI_RST0x02
+
+/* MPMU Clocks */
+#define MPMU_EN_ALL_CLKS 0x1E
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
diff --git a/drivers/usb/host/utmi-armada100.c
b/drivers/usb/host/utmi-armada100.c
new file mode 100644
index 000..b8225dd
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "utmi-armada100.h"
+
+static void utmi_phy_init(void)
+{
+ struct armd1usb_phy_reg *phy_regs =
+ (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
+
+ setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
+ udelay(1000);
+ setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
+
+ clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
+ setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
+
+ setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
+
+ /* Calibrate pll */
+ while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)
+ ;
+
+ udelay(200);
+ setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
+ udelay(400);
+ clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
+
+ udelay(200);
+ setbits_le32(&phy_regs->utmi_tx, RCAL_START);
+ udelay(400);
+ clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
+
+ while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)
+ ;
+}
+
+/*
+ * Initialize USB host controller's UTMI Physical interface
+ */
+void utmi_init(void)
+{
+ struct armd1mpmu_registers *mpmu_regs =
+ (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
+
+ struct armd1apmu_registers *apmu_regs =
+ (struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+ /* Turn on main PMU clocks */
+ writel(MPMU_EN_ALL_CLKS, &mpmu_regs->acgr);
+
+ /* USB Clock reset */
+ writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
+ writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
+
+ /* Initialize UTMI transceiver */
+ utmi_phy_init();
+}
diff --git a/drivers/usb/host/utmi-armada100.h
b/drivers/usb/host/utmi-armada100.h
new file mode 100644
index 000..dd0ccdb
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied
[U-Boot] [PATCH 2/3] USB: Armada100: ECHI Driver for Armada100 SOCs
This patch adds support for USB EHCI driver for Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/usb/host/Makefile |1 +
drivers/usb/host/ehci-armada100.c | 62 +++
3 files changed, 64 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-armada100.c
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index d6984dc..26f836e 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -67,6 +67,7 @@
#define ARMD1_SSP5_BASE0xD4021000
#define ARMD1_UART3_BASE 0xD4026000
#define ARMD1_MPMU_BASE0xD405
+#define ARMD1_USB_HOST_BASE0xD4209000
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 77e217f..94e72c3 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
+COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
ifdef CONFIG_MPC512X
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
else
diff --git a/drivers/usb/host/ehci-armada100.c
b/drivers/usb/host/ehci-armada100.c
new file mode 100644
index 000..cf05d1a
--- /dev/null
+++ b/drivers/usb/host/ehci-armada100.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * This driver is based on Kirkwood echi driver
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Written-by: Prafulla Wadaskar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include "ehci.h"
+#include "ehci-core.h"
+#include
+#include
+#include "utmi-armada100.h"
+
+/*
+ * EHCI host controller init
+ */
+int ehci_hcd_init(void)
+{
+ utmi_init();
+ hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr
+ + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ printf("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * EHCI host controller stop
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
--
1.7.7.2
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Re: [U-Boot] [PATCH 2/3] USB: Armada100: ECHI Driver for Armada100 SOCs
- "Prafulla Wadaskar" wrote:
[...snip...]
> > +
> > +printf("Kirkwood-ehci: init hccr %x and hcor %x hc_length %d\n",
>
> Wrong printf message, it's not Kirkwood.
>
> Regards..
> Prafulla . . .
>
I don't know how I missed that.. though, I did changed it :/
Any other comments on patches?
Regards,
Ajay Bhargav
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Re: [U-Boot] [PATCH 1/3] USB: Armada100: Add UTMI PHY interface driver
- "Prafulla Wadaskar" wrote: > > + > > +/* MPMU Clocks */ > > +#define MPMU_EN_ALL_CLKS0x1E > > Turning on all clocks is not logical to enable this support, only > relevant clock necessary for this components SHOULD BE enabled. > > Enabling clocks for unused peripherals/components may result in > unnecessarily extra power consumption > > Otherwise ack for rest of the patch > > Regards.. > Prafulla . . . > I followed programming guidlines as per Armada_16x software manual. section: 20.4.3.1 snip of pseudo code from Programming guidlines section: [...snip...] print "**main PMU turn on all clocks\n" set val *(unsigned long *)PMUM_ACGR=0x001E print "**PMUap USBCLK Reset Control\n" set val *(unsigned long *)PMUA_USB_CLK_RES_CTRL=0x1B print "**UTMI ID\n" eval /hex *(unsigned long *)UTMI_REVISION [...snip...] There is nothing mentioned in specific which clock is used/required by USB host controller. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] Armada100: gplugD: Add USB command support
- "Prafulla Wadaskar" wrote: > > -Original Message- > > From: Ajay Bhargav [mailto:ajay.bhar...@einfochips.com] > > Sent: 25 January 2012 17:50 > > To: li...@bohmer.net > > Cc: Prafulla Wadaskar; marek.va...@gmail.com; u-boot@lists.denx.de; > > Ajay Bhargav > > Subject: [PATCH 3/3] Armada100: gplugD: Add USB command support > > > > This patch adds support for USB commands and USB storage device for > > Marvell gplugD [...snip...] > > > > +#ifdef CONFIG_CMD_USB > > +#define CONFIG_USB_EHCI > > +#define CONFIG_USB_EHCI_ARMADA100 > > +#define CONFIG_EHCI_IS_TDI > > +#define CONFIG_USB_STORAGE > > + > > +#ifndef CONFIG_DOS_PARTITION > > Does this undef needed? remove it you can. > > Regards.. > Prafulla . . . > I will review it again and remove it if not needed. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] USB: Armada100: Add UTMI PHY interface driver
- "Wolfgang Denk" wrote: > Dear Ajay Bhargav, > > In message > <1978582266.117750.1327647714615.javamail.r...@ahm.einfochips.com> you > wrote: > > > > > > +#define MPMU_EN_ALL_CLKS0x1E > > > > > > Turning on all clocks is not logical to enable this support, only > > > relevant clock necessary for this components SHOULD BE enabled. > ... > > I followed programming guidlines as per Armada_16x software manual. > > section: 20.4.3.1 > > snip of pseudo code from Programming guidlines section: > > [...snip...] > > print "**main PMU turn on all clocks\n" > > This is a deficiency of this specific document then. Prafulla is > right: please enable only the really needed clocks. I guess there is > better documentation that that pseudo code. > > Best regards, > > Wolfgang Denk > Thanks for feedback... I will look for better documentation then.. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver
This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Fix: enable only required clock in MPMU
arch/arm/include/asm/arch-armada100/armada100.h |8 ++
drivers/usb/host/utmi-armada100.c | 87 +++
drivers/usb/host/utmi-armada100.h | 79
3 files changed, 174 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/utmi-armada100.c
create mode 100644 drivers/usb/host/utmi-armada100.h
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 0ed3a8e..70fba27 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -43,6 +43,14 @@
#define SSP2_APBCLK0x01
#define SSP2_FNCLK 0x02
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN 0x10
+#define USB_SPH_AXI_RST0x02
+
+/* MPMU Clocks */
+#define APB2_26M_EN(1 << 20)
+#define AP_26M (1 << 4)
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
diff --git a/drivers/usb/host/utmi-armada100.c
b/drivers/usb/host/utmi-armada100.c
new file mode 100644
index 000..1a4d3f2
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.c
@@ -0,0 +1,87 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include "utmi-armada100.h"
+
+static void utmi_phy_init(void)
+{
+ struct armd1usb_phy_reg *phy_regs =
+ (struct armd1usb_phy_reg *)UTMI_PHY_BASE;
+
+ setbits_le32(&phy_regs->utmi_ctrl, INPKT_DELAY_SOF | PLL_PWR_UP);
+ udelay(1000);
+ setbits_le32(&phy_regs->utmi_ctrl, PHY_PWR_UP);
+
+ clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK);
+ setbits_le32(&phy_regs->utmi_pll, N_DIVIDER << PLL_FBDIV | M_DIVIDER);
+
+ setbits_le32(&phy_regs->utmi_tx, PHSEL_VAL << CK60_PHSEL);
+
+ /* Calibrate pll */
+ while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)
+ ;
+
+ udelay(200);
+ setbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
+ udelay(400);
+ clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START);
+
+ udelay(200);
+ setbits_le32(&phy_regs->utmi_tx, RCAL_START);
+ udelay(400);
+ clrbits_le32(&phy_regs->utmi_tx, RCAL_START);
+
+ while ((readl(&phy_regs->utmi_pll) & PLL_READY) == 0)
+ ;
+}
+
+/*
+ * Initialize USB host controller's UTMI Physical interface
+ */
+void utmi_init(void)
+{
+ struct armd1mpmu_registers *mpmu_regs =
+ (struct armd1mpmu_registers *)ARMD1_MPMU_BASE;
+
+ struct armd1apmu_registers *apmu_regs =
+ (struct armd1apmu_registers *)ARMD1_APMU_BASE;
+
+ /* Turn on 26Mhz ref clock for UTMI PLL */
+ setbits_le32(&mpmu_regs->acgr, APB2_26M_EN | AP_26M);
+
+ /* USB Clock reset */
+ writel(USB_SPH_AXICLK_EN, &apmu_regs->usbcrc);
+ writel(USB_SPH_AXICLK_EN | USB_SPH_AXI_RST, &apmu_regs->usbcrc);
+
+ /* Initialize UTMI transceiver */
+ utmi_phy_init();
+}
diff --git a/drivers/usb/host/utmi-armada100.h
b/drivers/usb/host/utmi-armada100.h
new file mode 100644
index 000..dd0ccdb
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any
[U-Boot] [v2 3/4] Armada100: gplugD: Add USB command support
This patch adds support for USB commands and USB storage device for Marvell gplugD Signed-off-by: Ajay Bhargav --- Changes for v2: - removed unwanted ifdef - fat and ext2 command support moved to new patch include/configs/gplugd.h | 12 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 9813309..061ebe6 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -72,6 +72,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA +#define CONFIG_CMD_USB /* Disable DCACHE */ #define CONFIG_SYS_DCACHE_OFF @@ -134,4 +135,15 @@ #define CONFIG_CMD_EDITENV #define CONFIG_CMD_SAVEENV +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ARMADA100 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif /* CONFIG_CMD_USB */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT + #endif /* __CONFIG_GPLUGD_H */ -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v2 4/4] Armada100: gplugD: Add FAT & EXT2 command support
This patch adds FAT and ext2 command support for marvell gplugD Signed-off-by: Ajay Bhargav --- Changes for v2: - added this new patch for command support include/configs/gplugd.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 061ebe6..462cc7e 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -73,6 +73,8 @@ #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #define CONFIG_CMD_USB +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* Disable DCACHE */ #define CONFIG_SYS_DCACHE_OFF -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v2 2/4] USB: Armada100: ECHI Driver for Armada100 SOCs
This patch adds support for USB EHCI driver for Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Fix typo for SOC name
- change printf to debug
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/usb/host/Makefile |1 +
drivers/usb/host/ehci-armada100.c | 62 +++
3 files changed, 64 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-armada100.c
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 70fba27..614de55 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -68,6 +68,7 @@
#define ARMD1_SSP5_BASE0xD4021000
#define ARMD1_UART3_BASE 0xD4026000
#define ARMD1_MPMU_BASE0xD405
+#define ARMD1_USB_HOST_BASE0xD4209000
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7c4df53..5fdc97b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
+COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
ifdef CONFIG_MPC512X
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
else
diff --git a/drivers/usb/host/ehci-armada100.c
b/drivers/usb/host/ehci-armada100.c
new file mode 100644
index 000..cfe159d
--- /dev/null
+++ b/drivers/usb/host/ehci-armada100.c
@@ -0,0 +1,62 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * This driver is based on Kirkwood echi driver
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Written-by: Prafulla Wadaskar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include "ehci.h"
+#include "ehci-core.h"
+#include
+#include
+#include "utmi-armada100.h"
+
+/*
+ * EHCI host controller init
+ */
+int ehci_hcd_init(void)
+{
+ utmi_init();
+ hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr
+ + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * EHCI host controller stop
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
--
1.7.7.2
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Re: [U-Boot] [v2 1/4] USB: Armada100: Add UTMI PHY interface driver
On Monday 13 February 2012 02:32 PM, Marek Vasut wrote: + /* Calibrate pll */ + while ((readl(&phy_regs->utmi_pll)& PLL_READY) == 0) + ; No endless loops please. missed it somehow... :) will fix Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v2 2/4] USB: Armada100: ECHI Driver for Armada100 SOCs
On Monday 13 February 2012 02:33 PM, Marek Vasut wrote: This patch adds support for USB EHCI driver for Armada100 SOCs. Fix the subject, you have ECHI written there ;-) what a blunder :) [...snip...] +#include +#include +#include +#include "ehci.h" +#include "ehci-core.h" +#include +#include +#include "utmi-armada100.h" Where does this include come from? Maybe this should be part of the platform includes in asm/arch/... and accessed as such too? M Utmi might not be required outside usb.. so its always a part of USB. Do i really need to keep it out? Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v2 4/4] Armada100: gplugD: Add FAT & EXT2 command support
On Monday 13 February 2012 02:59 PM, Prafulla Wadaskar wrote: -Original Message- From: Marek Vasut [mailto:ma...@denx.de] Sent: 13 February 2012 14:35 To: Ajay Bhargav Cc: li...@bohmer.net; Prafulla Wadaskar; u-boot@lists.denx.de Subject: Re: [v2 4/4] Armada100: gplugD: Add FAT& EXT2 command support This patch adds FAT and ext2 command support for marvell gplugD Signed-off-by: Ajay Bhargav --- Changes for v2: - added this new patch for command support include/configs/gplugd.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 061ebe6..462cc7e 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -73,6 +73,8 @@ #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #define CONFIG_CMD_USB +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* Disable DCACHE */ #define CONFIG_SYS_DCACHE_OFF Just squash it with the previous patch, it's related to it anyway ;- Or you may exclude this patch from this series and post it as a standalone patch (in fact it is). Regards.. Prafulla . . . I better send a new one :) out of this patch series. Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [v3 1/3] USB: Armada100: Add UTMI PHY interface driver
This patch adds USB host controller's UTMI PHY interface driver for
Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Fix: enable only required clock in MPMU
Changes for v3:
- Added timeout on while loops
- moved utmi-armada100.h to arch include folder
arch/arm/include/asm/arch-armada100/armada100.h|8 ++
.../include/asm/arch-armada100/utmi-armada100.h| 79
drivers/usb/host/utmi-armada100.c | 96
3 files changed, 183 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h
create mode 100644 drivers/usb/host/utmi-armada100.c
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 0ed3a8e..70fba27 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -43,6 +43,14 @@
#define SSP2_APBCLK0x01
#define SSP2_FNCLK 0x02
+/* USB Clock/reset control bits */
+#define USB_SPH_AXICLK_EN 0x10
+#define USB_SPH_AXI_RST0x02
+
+/* MPMU Clocks */
+#define APB2_26M_EN(1 << 20)
+#define AP_26M (1 << 4)
+
/* Register Base Addresses */
#define ARMD1_DRAM_BASE0xB000
#define ARMD1_FEC_BASE 0xC080
diff --git a/arch/arm/include/asm/arch-armada100/utmi-armada100.h
b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
new file mode 100644
index 000..dd0ccdb
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/utmi-armada100.h
@@ -0,0 +1,79 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __UTMI_ARMADA100__
+#define __UTMI_ARMADA100__
+
+#define UTMI_PHY_BASE 0xD4206000
+
+/* utmi_ctrl - bits */
+#define INPKT_DELAY_SOF(1 << 28)
+#define PLL_PWR_UP 2
+#define PHY_PWR_UP 1
+
+/* utmi_pll - bits */
+#define PLL_FBDIV_MASK 0x0FF0
+#define PLL_FBDIV 4
+#define PLL_REFDIV_MASK0x000F
+#define PLL_REFDIV 0
+#define PLL_READY 0x80
+#define VCOCAL_START (1 << 21)
+
+#define N_DIVIDER 0xEE
+#define M_DIVIDER 0x0B
+
+/* utmi_tx - bits */
+#define CK60_PHSEL 17
+#define PHSEL_VAL 0x4
+#define RCAL_START (1 << 12)
+
+/*
+ * USB PHY registers
+ * Refer Datasheet Appendix A.21
+ */
+struct armd1usb_phy_reg {
+ u32 utmi_rev; /* USB PHY Revision */
+ u32 utmi_ctrl; /* USB PHY Control register */
+ u32 utmi_pll; /* PLL register */
+ u32 utmi_tx;/* Tx register */
+ u32 utmi_rx;/* Rx register */
+ u32 utmi_ivref; /* IVREF register */
+ u32 utmi_tst_g0;/* Test group 0 register */
+ u32 utmi_tst_g1;/* Test group 1 register */
+ u32 utmi_tst_g2;/* Test group 2 register */
+ u32 utmi_tst_g3;/* Test group 3 register */
+ u32 utmi_tst_g4;/* Test group 4 register */
+ u32 utmi_tst_g5;/* Test group 5 register */
+ u32 utmi_reserve; /* Reserve Register */
+ u32 utmi_usb_int; /* USB interuppt register */
+ u32 utmi_dbg_ctl; /* Debug control register */
+ u32 utmi_otg_addon; /* OTG addon register */
+};
+
+int utmi_init(void);
+
+#endif /* __UTMI_ARMADA100__ */
diff --git a/drivers/usb/host/utmi-armada100.c
b/drivers/usb/host/utmi-armada100.c
new file mode 100644
index 000..124fa8f
--- /dev/null
+++ b/drivers/usb/host/utmi-armada100.c
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either versio
[U-Boot] [v3 2/3] USB: Armada100: EHCI Driver for Armada100 SOCs
This patch adds support for USB EHCI driver for Armada100 SOCs.
Signed-off-by: Ajay Bhargav
---
Changes for v2:
- Fix typo for SOC name
- change printf to debug
Changes for v3:
- Fix type in patch subject
- header file include updated
arch/arm/include/asm/arch-armada100/armada100.h |1 +
drivers/usb/host/Makefile |1 +
drivers/usb/host/ehci-armada100.c | 64 +++
3 files changed, 66 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/host/ehci-armada100.c
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h
b/arch/arm/include/asm/arch-armada100/armada100.h
index 70fba27..614de55 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -68,6 +68,7 @@
#define ARMD1_SSP5_BASE0xD4021000
#define ARMD1_UART3_BASE 0xD4026000
#define ARMD1_MPMU_BASE0xD405
+#define ARMD1_USB_HOST_BASE0xD4209000
#define ARMD1_APMU_BASE0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 7c4df53..5fdc97b 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -35,6 +35,7 @@ COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
+COBJS-$(CONFIG_USB_EHCI_ARMADA100) += ehci-armada100.o utmi-armada100.o
ifdef CONFIG_MPC512X
COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-mpc512x.o
else
diff --git a/drivers/usb/host/ehci-armada100.c
b/drivers/usb/host/ehci-armada100.c
new file mode 100644
index 000..f3d8aef
--- /dev/null
+++ b/drivers/usb/host/ehci-armada100.c
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2012
+ * eInfochips Ltd.
+ * Written-by: Ajay Bhargav
+ *
+ * This driver is based on Kirkwood echi driver
+ * (C) Copyright 2009
+ * Marvell Semiconductor
+ * Written-by: Prafulla Wadaskar
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include
+#include
+#include
+#include "ehci.h"
+#include "ehci-core.h"
+#include
+#include
+#include
+
+/*
+ * EHCI host controller init
+ */
+int ehci_hcd_init(void)
+{
+ if (utmi_init() < 0)
+ return -1;
+
+ hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
+ hcor = (struct ehci_hcor *)((uint32_t) hccr
+ + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n",
+ (uint32_t)hccr, (uint32_t)hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+
+ return 0;
+}
+
+/*
+ * EHCI host controller stop
+ */
+int ehci_hcd_stop(void)
+{
+ return 0;
+}
--
1.7.7.2
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[U-Boot] [v3 3/3] Armada100: gplugD: Add USB command support
This patch adds support for USB commands and USB storage device for Marvell gplugD Signed-off-by: Ajay Bhargav --- Changes for v2: - removed unwanted ifdef - fat and ext2 command support moved to new patch Changes for v3: - Not changed include/configs/gplugd.h | 12 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 9813309..061ebe6 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -72,6 +72,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA +#define CONFIG_CMD_USB /* Disable DCACHE */ #define CONFIG_SYS_DCACHE_OFF @@ -134,4 +135,15 @@ #define CONFIG_CMD_EDITENV #define CONFIG_CMD_SAVEENV +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_ARMADA100 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif /* CONFIG_CMD_USB */ + +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION +#define CONFIG_SUPPORT_VFAT + #endif /* __CONFIG_GPLUGD_H */ -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Armada100: gplugD: Add FAT & EXT2 command support
This patch adds FAT and ext2 command support for marvell gplugD Signed-off-by: Ajay Bhargav --- include/configs/gplugd.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h index 061ebe6..462cc7e 100644 --- a/include/configs/gplugd.h +++ b/include/configs/gplugd.h @@ -73,6 +73,8 @@ #define CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #define CONFIG_CMD_USB +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT /* Disable DCACHE */ #define CONFIG_SYS_DCACHE_OFF -- 1.7.7.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [v3 1/3] USB: Armada100: Add UTMI PHY interface driver
On Monday 13 February 2012 06:57 PM, Ajay Bhargav wrote: This patch adds USB host controller's UTMI PHY interface driver for Armada100 SOCs. Signed-off-by: Ajay Bhargav --- Changes for v2: - Fix: enable only required clock in MPMU Changes for v3: - Added timeout on while loops - moved utmi-armada100.h to arch include folder arch/arm/include/asm/arch-armada100/armada100.h|8 ++ .../include/asm/arch-armada100/utmi-armada100.h| 79 drivers/usb/host/utmi-armada100.c | 96 3 files changed, 183 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/utmi-armada100.h create mode 100644 drivers/usb/host/utmi-armada100.c any comments on these patches? Regards, Ajay Bhargav ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
